[libcpu] auto formatted

libcpu/aarch64/common/armv8.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,47 +14,47 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long long pc;
-	unsigned long long spsr;
-	unsigned long long x30;
-	unsigned long long xz;
-	unsigned long long x28;
-	unsigned long long x29;
-	unsigned long long x26;
-	unsigned long long x27;
-	unsigned long long x24;
-	unsigned long long x25;
-	unsigned long long x22;
-	unsigned long long x23;
-	unsigned long long x20;
-	unsigned long long x21;
-	unsigned long long x18;	
-	unsigned long long x19;
-	unsigned long long x16;
-	unsigned long long x17;
-	unsigned long long x14;
-	unsigned long long x15;
-	unsigned long long x12;
-	unsigned long long x13;
-	unsigned long long x10;
-	unsigned long long x11;
-	unsigned long long x8;
-	unsigned long long x9;
-	unsigned long long x6;
-	unsigned long long x7;
-	unsigned long long x4;
-	unsigned long long x5;
-	unsigned long long x2;
-	unsigned long long x3;
-	unsigned long long x0;
-	unsigned long long x1;
+    unsigned long long pc;
+    unsigned long long spsr;
+    unsigned long long x30;
+    unsigned long long xz;
+    unsigned long long x28;
+    unsigned long long x29;
+    unsigned long long x26;
+    unsigned long long x27;
+    unsigned long long x24;
+    unsigned long long x25;
+    unsigned long long x22;
+    unsigned long long x23;
+    unsigned long long x20;
+    unsigned long long x21;
+    unsigned long long x18;
+    unsigned long long x19;
+    unsigned long long x16;
+    unsigned long long x17;
+    unsigned long long x14;
+    unsigned long long x15;
+    unsigned long long x12;
+    unsigned long long x13;
+    unsigned long long x10;
+    unsigned long long x11;
+    unsigned long long x8;
+    unsigned long long x9;
+    unsigned long long x6;
+    unsigned long long x7;
+    unsigned long long x4;
+    unsigned long long x5;
+    unsigned long long x2;
+    unsigned long long x3;
+    unsigned long long x0;
+    unsigned long long x1;
 };
 
-#define SP_ELx						( ( unsigned long long ) 0x01 )
-#define SP_EL0						( ( unsigned long long ) 0x00 )
-#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
-#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
-#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
+#define SP_ELx                      ( ( unsigned long long ) 0x01 )
+#define SP_EL0                      ( ( unsigned long long ) 0x00 )
+#define PSTATE_EL1                  ( ( unsigned long long ) 0x04 )
+#define PSTATE_EL2                  ( ( unsigned long long ) 0x08 )
+#define PSTATE_EL3                  ( ( unsigned long long ) 0x0c )
 
 rt_ubase_t rt_hw_get_current_el(void);
 void rt_hw_set_elx_env(void);

libcpu/aarch64/common/cp15.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -55,7 +55,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector)
 
 static inline void setup_bootstrap_addr(int cpu, int addr)
 {
-	CORE_MAILBOX3_SET(cpu) = addr;
+    CORE_MAILBOX3_SET(cpu) = addr;
 }
 
 static inline void enable_cpu_ipi_intr(int cpu)
@@ -65,7 +65,7 @@ static inline void enable_cpu_ipi_intr(int cpu)
 
 static inline void enable_cpu_timer_intr(int cpu)
 {
-	CORETIMER_INTCTL(cpu) = 0x8;
+    CORETIMER_INTCTL(cpu) = 0x8;
 }
 
 static inline void enable_cntv(void)

libcpu/aarch64/common/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/common/gic/gic_pl400.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/common/gic/gic_pl400.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/common/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -52,7 +52,7 @@ void mmu_memset(char *dst, char v,  size_t len)
 }
 
 static unsigned long __page_off = 0;
-static unsigned long get_free_page(void) 
+static unsigned long get_free_page(void)
 {
     __page_off += 512;
     return (unsigned long)(main_tbl + __page_off);
@@ -128,7 +128,7 @@ void mmu_enable(void)
 
 }
 
-static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr)
 {
     int level;
     unsigned long* cur_lv_tbl = lv0_tbl;
@@ -136,22 +136,22 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned
     unsigned long off;
     int level_shift = 39;
 
-    if (va & (0x200000UL - 1)) 
+    if (va & (0x200000UL - 1))
     {
         return MMU_MAP_ERROR_VANOTALIGN;
     }
-    if (pa & (0x200000UL - 1)) 
+    if (pa & (0x200000UL - 1))
     {
         return MMU_MAP_ERROR_PANOTALIGN;
     }
-    for (level = 0; level < 2; level++) 
+    for (level = 0; level < 2; level++)
     {
         off = (va >> level_shift);
         off &= MMU_LEVEL_MASK;
-        if ((cur_lv_tbl[off] & 1) == 0) 
+        if ((cur_lv_tbl[off] & 1) == 0)
         {
             page = get_free_page();
-            if (!page) 
+            if (!page)
             {
                 return MMU_MAP_ERROR_NOPAGE;
             }
@@ -159,7 +159,7 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned
             cur_lv_tbl[off] = page | 0x3UL;
         }
         page = cur_lv_tbl[off];
-        if (!(page & 0x2)) 
+        if (!(page & 0x2))
         {
             //is block! error!
             return MMU_MAP_ERROR_CONFLICT;
@@ -239,8 +239,8 @@ static int level2shift(int level)
 static uint64_t *get_level_table(uint64_t *pte)
 {
     uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
-    
-    if (pte_type(pte) != PMD_TYPE_TABLE) 
+
+    if (pte_type(pte) != PMD_TYPE_TABLE)
     {
         table = create_table();
         set_table(pte, table);
@@ -259,10 +259,10 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
     int level = 0;
 
     addr = virt;
-    while (size) 
+    while (size)
     {
         table = &main_tbl[0];
-        for (level = 0; level < 4; level++) 
+        for (level = 0; level < 4; level++)
         {
             block_shift = level2shift(level);
             idx = addr >> block_shift;
@@ -270,7 +270,7 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
             block_size = (uint64_t)(1L << block_shift);
             pte = table + idx;
 
-            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
+            if (size >= block_size && IS_ALIGNED(addr, block_size))
             {
                 attr &= 0xfff0000000000ffcUL;
                 if(level != 3)
@@ -298,7 +298,7 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned
 
 void rt_hw_dcache_enable(void)
 {
-    if (!(get_sctlr() & CR_M)) 
+    if (!(get_sctlr() & CR_M))
     {
         rt_kprintf("please init mmu!\n");
     }
@@ -364,4 +364,4 @@ void rt_hw_icache_invalidate_all(void)
 void rt_hw_icache_disable(void)
 {
     set_sctlr(get_sctlr() & ~CR_I);
-}
+}

libcpu/aarch64/common/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/cortex-a53/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018/5/3       Bernard      first version
  * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues,
  *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
  */
 
@@ -160,15 +160,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
     }
     if(cpu_mask & 0x2)
     {
-    	send_ipi_msg(1, ipi_vector);
+        send_ipi_msg(1, ipi_vector);
     }
     if(cpu_mask & 0x4)
     {
-    	send_ipi_msg(2, ipi_vector);
+        send_ipi_msg(2, ipi_vector);
     }
     if(cpu_mask & 0x8)
     {
-    	send_ipi_msg(3, ipi_vector);
+        send_ipi_msg(3, ipi_vector);
     }
     __DSB();
 }

libcpu/aarch64/cortex-a53/interrupt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/cortex-a53/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,70 +21,70 @@
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry 
+ * @param parameter the parameter of entry
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_ubase_t *stk;
-	rt_ubase_t current_el;
+    rt_ubase_t *stk;
+    rt_ubase_t current_el;
 
-	stk 	 = (rt_ubase_t*)stack_addr;
+    stk      = (rt_ubase_t*)stack_addr;
 
-	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
-	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
-	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
-	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
-	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
-	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
-	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
-	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
-	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
-	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
-	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
-	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
-	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
-	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
-	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
-	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
-	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
-	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
-	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
-	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
-	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
-	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
-	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
-	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
-	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
-	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
-	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
-	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
-	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
-	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X1 */
+    *(--stk) = ( rt_ubase_t ) parameter;    /* X0 */
+    *(--stk) = ( rt_ubase_t ) 33;           /* X3 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X2 */
+    *(--stk) = ( rt_ubase_t ) 55;           /* X5 */
+    *(--stk) = ( rt_ubase_t ) 44;           /* X4 */
+    *(--stk) = ( rt_ubase_t ) 77;           /* X7 */
+    *(--stk) = ( rt_ubase_t ) 66;           /* X6 */
+    *(--stk) = ( rt_ubase_t ) 99;           /* X9 */
+    *(--stk) = ( rt_ubase_t ) 88;           /* X8 */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X11 */
+    *(--stk) = ( rt_ubase_t ) 10;           /* X10 */
+    *(--stk) = ( rt_ubase_t ) 13;           /* X13 */
+    *(--stk) = ( rt_ubase_t ) 12;           /* X12 */
+    *(--stk) = ( rt_ubase_t ) 15;           /* X15 */
+    *(--stk) = ( rt_ubase_t ) 14;           /* X14 */
+    *(--stk) = ( rt_ubase_t ) 17;           /* X17 */
+    *(--stk) = ( rt_ubase_t ) 16;           /* X16 */
+    *(--stk) = ( rt_ubase_t ) 19;           /* X19 */
+    *(--stk) = ( rt_ubase_t ) 18;           /* X18 */
+    *(--stk) = ( rt_ubase_t ) 21;           /* X21 */
+    *(--stk) = ( rt_ubase_t ) 20;           /* X20 */
+    *(--stk) = ( rt_ubase_t ) 23;           /* X23 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X22 */
+    *(--stk) = ( rt_ubase_t ) 25;           /* X25 */
+    *(--stk) = ( rt_ubase_t ) 24;           /* X24 */
+    *(--stk) = ( rt_ubase_t ) 27;           /* X27 */
+    *(--stk) = ( rt_ubase_t ) 26;           /* X26 */
+    *(--stk) = ( rt_ubase_t ) 29;           /* X29 */
+    *(--stk) = ( rt_ubase_t ) 28;           /* X28 */
+    *(--stk) = ( rt_ubase_t ) 0;            /* XZR - has no effect, used so there are an even number of registers. */
+    *(--stk) = ( rt_ubase_t ) texit;        /* X30 - procedure call link register. */
 
-	current_el = rt_hw_get_current_el();
+    current_el = rt_hw_get_current_el();
 
-	if(current_el == 3)
-	{
-		*(--stk) = INITIAL_SPSR_EL3;
-	}
-	else if(current_el == 2)
-	{
-		*(--stk) = INITIAL_SPSR_EL2;
-	}
-	else
-	{
-		*(--stk) = INITIAL_SPSR_EL1;
-	}
+    if(current_el == 3)
+    {
+        *(--stk) = INITIAL_SPSR_EL3;
+    }
+    else if(current_el == 2)
+    {
+        *(--stk) = INITIAL_SPSR_EL2;
+    }
+    else
+    {
+        *(--stk) = INITIAL_SPSR_EL1;
+    }
 
-	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+    *(--stk) = ( rt_ubase_t ) tentry;       /* Exception return address. */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }

libcpu/aarch64/cortex-a53/trap.c

@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
- * 
+ *
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
@@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
     rt_kprintf("Execption:\n");
     rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
     rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+    rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+    rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+    rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
     rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
-	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+    rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+    rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+    rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
 }
 
 /**
@@ -57,7 +57,7 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
 }
 
 #define GIC_ACK_INTID_MASK              (0x000003ff)
-#define CORE0_IRQ_SOURCE	            (0x40000060)
+#define CORE0_IRQ_SOURCE                (0x40000060)
 
 void rt_hw_trap_irq(void)
 {

libcpu/aarch64/cortex-a72/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/cortex-a72/interrupt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/aarch64/cortex-a72/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,70 +21,70 @@
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry 
+ * @param parameter the parameter of entry
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_ubase_t *stk;
-	rt_ubase_t current_el;
+    rt_ubase_t *stk;
+    rt_ubase_t current_el;
 
-	stk 	 = (rt_ubase_t*)stack_addr;
+    stk      = (rt_ubase_t*)stack_addr;
 
-	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
-	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
-	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
-	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
-	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
-	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
-	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
-	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
-	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
-	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
-	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
-	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
-	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
-	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
-	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
-	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
-	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
-	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
-	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
-	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
-	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
-	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
-	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
-	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
-	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
-	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
-	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
-	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
-	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
-	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X1 */
+    *(--stk) = ( rt_ubase_t ) parameter;    /* X0 */
+    *(--stk) = ( rt_ubase_t ) 33;           /* X3 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X2 */
+    *(--stk) = ( rt_ubase_t ) 55;           /* X5 */
+    *(--stk) = ( rt_ubase_t ) 44;           /* X4 */
+    *(--stk) = ( rt_ubase_t ) 77;           /* X7 */
+    *(--stk) = ( rt_ubase_t ) 66;           /* X6 */
+    *(--stk) = ( rt_ubase_t ) 99;           /* X9 */
+    *(--stk) = ( rt_ubase_t ) 88;           /* X8 */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X11 */
+    *(--stk) = ( rt_ubase_t ) 10;           /* X10 */
+    *(--stk) = ( rt_ubase_t ) 13;           /* X13 */
+    *(--stk) = ( rt_ubase_t ) 12;           /* X12 */
+    *(--stk) = ( rt_ubase_t ) 15;           /* X15 */
+    *(--stk) = ( rt_ubase_t ) 14;           /* X14 */
+    *(--stk) = ( rt_ubase_t ) 17;           /* X17 */
+    *(--stk) = ( rt_ubase_t ) 16;           /* X16 */
+    *(--stk) = ( rt_ubase_t ) 19;           /* X19 */
+    *(--stk) = ( rt_ubase_t ) 18;           /* X18 */
+    *(--stk) = ( rt_ubase_t ) 21;           /* X21 */
+    *(--stk) = ( rt_ubase_t ) 20;           /* X20 */
+    *(--stk) = ( rt_ubase_t ) 23;           /* X23 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X22 */
+    *(--stk) = ( rt_ubase_t ) 25;           /* X25 */
+    *(--stk) = ( rt_ubase_t ) 24;           /* X24 */
+    *(--stk) = ( rt_ubase_t ) 27;           /* X27 */
+    *(--stk) = ( rt_ubase_t ) 26;           /* X26 */
+    *(--stk) = ( rt_ubase_t ) 29;           /* X29 */
+    *(--stk) = ( rt_ubase_t ) 28;           /* X28 */
+    *(--stk) = ( rt_ubase_t ) 0;            /* XZR - has no effect, used so there are an even number of registers. */
+    *(--stk) = ( rt_ubase_t ) texit;        /* X30 - procedure call link register. */
 
-	current_el = rt_hw_get_current_el();
+    current_el = rt_hw_get_current_el();
 
-	if(current_el == 3)
-	{
-		*(--stk) = INITIAL_SPSR_EL3;
-	}
-	else if(current_el == 2)
-	{
-		*(--stk) = INITIAL_SPSR_EL2;
-	}
-	else
-	{
-		*(--stk) = INITIAL_SPSR_EL1;
-	}
+    if(current_el == 3)
+    {
+        *(--stk) = INITIAL_SPSR_EL3;
+    }
+    else if(current_el == 2)
+    {
+        *(--stk) = INITIAL_SPSR_EL2;
+    }
+    else
+    {
+        *(--stk) = INITIAL_SPSR_EL1;
+    }
 
-	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+    *(--stk) = ( rt_ubase_t ) tentry;       /* Exception return address. */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }

libcpu/aarch64/cortex-a72/trap.c

@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
- * 
+ *
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
@@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
     rt_kprintf("Execption:\n");
     rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
     rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+    rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+    rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+    rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
     rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
-	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+    rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+    rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+    rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
 }
 
 /**
@@ -64,7 +64,7 @@ void rt_hw_interrupt_ack(int fiq_irq);
 void rt_hw_trap_irq(void)
 {
     void *param;
-    int ir; 
+    int ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 

libcpu/arc/em/cpuport.c

@@ -22,11 +22,11 @@ rt_uint32_t rt_interrupt_to_thread;
 rt_uint32_t exc_nest_count;
 
 struct init_stack_frame {
-	rt_uint32_t pc;
-	rt_uint32_t blink;
-	rt_uint32_t task;
-	rt_uint32_t status32;
-	rt_uint32_t r0;
+    rt_uint32_t pc;
+    rt_uint32_t blink;
+    rt_uint32_t task;
+    rt_uint32_t status32;
+    rt_uint32_t r0;
 };
 
 /**
@@ -55,7 +55,7 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     stack_frame->blink = (rt_uint32_t)texit;
     stack_frame->task = (rt_uint32_t)tentry;
     stack_frame->status32 = ARC_INIT_STATUS;
-	stack_frame->r0 = (rt_uint32_t)parameter;
+    stack_frame->r0 = (rt_uint32_t)parameter;
 
     return stk;
 }
@@ -74,14 +74,14 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context))
 void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to)
 {
     struct rt_thread *rt_thread_to;
-	if (to != NULL) {
+    if (to != NULL) {
         rt_thread_to = rt_container_of(to, struct rt_thread, sp);
 #if ARC_FEATURE_SEC_PRESENT
-		arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr));
-		arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size);
+        arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr));
+        arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size);
 #else
-		arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr));
-		arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size);
+        arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr));
+        arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size);
 #endif
-	}
+    }
 }

libcpu/arm/AT91SAM7S/AT91SAM7S.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,276 +15,276 @@
 extern "C" {
 #endif
 
-#define AT91_REG *(volatile unsigned int *)		/* Hardware register definition */
+#define AT91_REG *(volatile unsigned int *)     /* Hardware register definition */
 
 /* ========== Register definition for TC0 peripheral ==========  */
-#define AT91C_TC0_SR		(AT91_REG(0xFFFA0020)) /* TC0 Status Register */
-#define AT91C_TC0_RC		(AT91_REG(0xFFFA001C)) /* TC0 Register C */
-#define AT91C_TC0_RB		(AT91_REG(0xFFFA0018)) /* TC0 Register B */
-#define AT91C_TC0_CCR		(AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */
-#define AT91C_TC0_CMR		(AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER		(AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */
-#define AT91C_TC0_RA		(AT91_REG(0xFFFA0014)) /* TC0 Register A */
-#define AT91C_TC0_IDR		(AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */
-#define AT91C_TC0_CV		(AT91_REG(0xFFFA0010)) /* TC0 Counter Value */
-#define AT91C_TC0_IMR		(AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */
+#define AT91C_TC0_SR        (AT91_REG(0xFFFA0020)) /* TC0 Status Register */
+#define AT91C_TC0_RC        (AT91_REG(0xFFFA001C)) /* TC0 Register C */
+#define AT91C_TC0_RB        (AT91_REG(0xFFFA0018)) /* TC0 Register B */
+#define AT91C_TC0_CCR       (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */
+#define AT91C_TC0_CMR       (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER       (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */
+#define AT91C_TC0_RA        (AT91_REG(0xFFFA0014)) /* TC0 Register A */
+#define AT91C_TC0_IDR       (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */
+#define AT91C_TC0_CV        (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */
+#define AT91C_TC0_IMR       (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */
 
 /* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB		(AT91_REG(0xFFFA0058)) /* TC1 Register B */
-#define AT91C_TC1_CCR		(AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */
-#define AT91C_TC1_IER		(AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */
-#define AT91C_TC1_IDR		(AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */
-#define AT91C_TC1_SR		(AT91_REG(0xFFFA0060)) /* TC1 Status Register */
-#define AT91C_TC1_CMR		(AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA		(AT91_REG(0xFFFA0054)) /* TC1 Register A */
-#define AT91C_TC1_RC		(AT91_REG(0xFFFA005C)) /* TC1 Register C */
-#define AT91C_TC1_IMR		(AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */
-#define AT91C_TC1_CV		(AT91_REG(0xFFFA0050)) /* TC1 Counter Value */
+#define AT91C_TC1_RB        (AT91_REG(0xFFFA0058)) /* TC1 Register B */
+#define AT91C_TC1_CCR       (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */
+#define AT91C_TC1_IER       (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */
+#define AT91C_TC1_IDR       (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */
+#define AT91C_TC1_SR        (AT91_REG(0xFFFA0060)) /* TC1 Status Register */
+#define AT91C_TC1_CMR       (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA        (AT91_REG(0xFFFA0054)) /* TC1 Register A */
+#define AT91C_TC1_RC        (AT91_REG(0xFFFA005C)) /* TC1 Register C */
+#define AT91C_TC1_IMR       (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */
+#define AT91C_TC1_CV        (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */
 
 /* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR		(AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR		(AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */
-#define AT91C_TC2_CV		(AT91_REG(0xFFFA0090)) /* TC2 Counter Value */
-#define AT91C_TC2_RA		(AT91_REG(0xFFFA0094)) /* TC2 Register A */
-#define AT91C_TC2_RB		(AT91_REG(0xFFFA0098)) /* TC2 Register B */
-#define AT91C_TC2_IDR		(AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */
-#define AT91C_TC2_IMR		(AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */
-#define AT91C_TC2_RC		(AT91_REG(0xFFFA009C)) /* TC2 Register C */
-#define AT91C_TC2_IER		(AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */
-#define AT91C_TC2_SR		(AT91_REG(0xFFFA00A0)) /* TC2 Status Register */
+#define AT91C_TC2_CMR       (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR       (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */
+#define AT91C_TC2_CV        (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */
+#define AT91C_TC2_RA        (AT91_REG(0xFFFA0094)) /* TC2 Register A */
+#define AT91C_TC2_RB        (AT91_REG(0xFFFA0098)) /* TC2 Register B */
+#define AT91C_TC2_IDR       (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */
+#define AT91C_TC2_IMR       (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */
+#define AT91C_TC2_RC        (AT91_REG(0xFFFA009C)) /* TC2 Register C */
+#define AT91C_TC2_IER       (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */
+#define AT91C_TC2_SR        (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */
 
 /* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR		(AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
-#define AT91C_PITC_PISR		(AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
-#define AT91C_PITC_PIIR		(AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
-#define AT91C_PITC_PIMR		(AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
+#define AT91C_PITC_PIVR     (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
+#define AT91C_PITC_PISR     (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
+#define AT91C_PITC_PIIR     (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
+#define AT91C_PITC_PIMR     (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
 
 /* ========== Register definition for UDP peripheral ==========  */
-#define AT91C_UDP_NUM		(AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */
-#define AT91C_UDP_STAT		(AT91_REG(0xFFFB0004)) /* UDP Global State Register */
-#define AT91C_UDP_FADDR		(AT91_REG(0xFFFB0008)) /* UDP Function Address Register */
-#define AT91C_UDP_IER		(AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */
-#define AT91C_UDP_IDR		(AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */
-#define AT91C_UDP_IMR		(AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */
-#define AT91C_UDP_ISR		(AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */
-#define AT91C_UDP_ICR		(AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */
-#define AT91C_UDP_RSTEP		(AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */
-#define AT91C_UDP_CSR0		(AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */
-#define AT91C_UDP_CSR(n)	(*(&AT91C_UDP_CSR0 + n))
-#define AT91C_UDP_FDR0		(AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */
-#define AT91C_UDP_FDR(n)	(*(&AT91C_UDP_FDR0 + n))
-#define AT91C_UDP_TXVC		(AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */
+#define AT91C_UDP_NUM       (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */
+#define AT91C_UDP_STAT      (AT91_REG(0xFFFB0004)) /* UDP Global State Register */
+#define AT91C_UDP_FADDR     (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */
+#define AT91C_UDP_IER       (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */
+#define AT91C_UDP_IDR       (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */
+#define AT91C_UDP_IMR       (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */
+#define AT91C_UDP_ISR       (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */
+#define AT91C_UDP_ICR       (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */
+#define AT91C_UDP_RSTEP     (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */
+#define AT91C_UDP_CSR0      (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */
+#define AT91C_UDP_CSR(n)    (*(&AT91C_UDP_CSR0 + n))
+#define AT91C_UDP_FDR0      (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */
+#define AT91C_UDP_FDR(n)    (*(&AT91C_UDP_FDR0 + n))
+#define AT91C_UDP_TXVC      (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */
 
 /* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_CR		(AT91_REG(0xFFFC0000)) /* US0 Control Register */
-#define AT91C_US0_MR		(AT91_REG(0xFFFC0004)) /* US0 Mode Register */
-#define AT91C_US0_IER		(AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */
-#define AT91C_US0_IDR		(AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */
-#define AT91C_US0_IMR		(AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */
-#define AT91C_US0_CSR		(AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */
-#define AT91C_US0_RHR		(AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */
-#define AT91C_US0_THR		(AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */
-#define AT91C_US0_BRGR		(AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */
-#define AT91C_US0_RTOR		(AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */
-#define AT91C_US0_TTGR		(AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */
-#define AT91C_US0_NER		(AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */
-#define AT91C_US0_FIDI		(AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */
-#define AT91C_US0_IF		(AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */
+#define AT91C_US0_CR        (AT91_REG(0xFFFC0000)) /* US0 Control Register */
+#define AT91C_US0_MR        (AT91_REG(0xFFFC0004)) /* US0 Mode Register */
+#define AT91C_US0_IER       (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */
+#define AT91C_US0_IDR       (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */
+#define AT91C_US0_IMR       (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */
+#define AT91C_US0_CSR       (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */
+#define AT91C_US0_RHR       (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */
+#define AT91C_US0_THR       (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */
+#define AT91C_US0_BRGR      (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */
+#define AT91C_US0_RTOR      (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */
+#define AT91C_US0_TTGR      (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */
+#define AT91C_US0_NER       (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */
+#define AT91C_US0_FIDI      (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */
+#define AT91C_US0_IF        (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */
 
 /* ========== Register definition for AIC peripheral ==========  */
-#define AT91C_AIC_SMR0		(AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */
-#define AT91C_AIC_SMR(n)	(*(&AT91C_AIC_SMR0 + n))
-#define AT91C_AIC_SVR0		(AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */
-#define AT91C_AIC_SVR(n)	(*(&AT91C_AIC_SVR0 + n))
-#define AT91C_AIC_IVR		(AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */
-#define AT91C_AIC_FVR		(AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */
-#define AT91C_AIC_ISR		(AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */
-#define AT91C_AIC_IPR		(AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */
-#define AT91C_AIC_IMR		(AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */
-#define AT91C_AIC_CISR		(AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */
-#define AT91C_AIC_IECR		(AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */
-#define AT91C_AIC_IDCR		(AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */
-#define AT91C_AIC_ICCR		(AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */
-#define AT91C_AIC_ISCR		(AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */
-#define AT91C_AIC_EOICR		(AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */
-#define AT91C_AIC_SPU		(AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */
-#define AT91C_AIC_DCR		(AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */
-#define AT91C_AIC_FFER		(AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */
-#define AT91C_AIC_FFDR		(AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */
-#define AT91C_AIC_FFSR		(AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */
+#define AT91C_AIC_SMR0      (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */
+#define AT91C_AIC_SMR(n)    (*(&AT91C_AIC_SMR0 + n))
+#define AT91C_AIC_SVR0      (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */
+#define AT91C_AIC_SVR(n)    (*(&AT91C_AIC_SVR0 + n))
+#define AT91C_AIC_IVR       (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */
+#define AT91C_AIC_FVR       (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */
+#define AT91C_AIC_ISR       (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */
+#define AT91C_AIC_IPR       (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */
+#define AT91C_AIC_IMR       (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */
+#define AT91C_AIC_CISR      (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */
+#define AT91C_AIC_IECR      (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */
+#define AT91C_AIC_IDCR      (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */
+#define AT91C_AIC_ICCR      (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */
+#define AT91C_AIC_ISCR      (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */
+#define AT91C_AIC_EOICR     (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */
+#define AT91C_AIC_SPU       (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */
+#define AT91C_AIC_DCR       (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */
+#define AT91C_AIC_FFER      (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */
+#define AT91C_AIC_FFDR      (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */
+#define AT91C_AIC_FFSR      (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */
 
 
 /* ========== Register definition for DBGU peripheral ==========  */
-#define AT91C_DBGU_EXID		(AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */
-#define AT91C_DBGU_BRGR		(AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */
-#define AT91C_DBGU_IDR		(AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */
-#define AT91C_DBGU_CSR		(AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */
-#define AT91C_DBGU_CIDR		(AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */
-#define AT91C_DBGU_MR		(AT91_REG(0xFFFFF204)) /* DBGU Mode Register */
-#define AT91C_DBGU_IMR		(AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */
-#define AT91C_DBGU_CR		(AT91_REG(0xFFFFF200)) /* DBGU Control Register */
-#define AT91C_DBGU_FNTR		(AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */
-#define AT91C_DBGU_THR		(AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */
-#define AT91C_DBGU_RHR		(AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */
-#define AT91C_DBGU_IER		(AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */
+#define AT91C_DBGU_EXID     (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */
+#define AT91C_DBGU_BRGR     (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */
+#define AT91C_DBGU_IDR      (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */
+#define AT91C_DBGU_CSR      (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */
+#define AT91C_DBGU_CIDR     (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */
+#define AT91C_DBGU_MR       (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */
+#define AT91C_DBGU_IMR      (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */
+#define AT91C_DBGU_CR       (AT91_REG(0xFFFFF200)) /* DBGU Control Register */
+#define AT91C_DBGU_FNTR     (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */
+#define AT91C_DBGU_THR      (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */
+#define AT91C_DBGU_RHR      (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */
+#define AT91C_DBGU_IER      (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */
 
 /* ========== Register definition for PIO peripheral ========== */
-#define AT91C_PIO_ODR		(AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */
-#define AT91C_PIO_SODR		(AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */
-#define AT91C_PIO_ISR		(AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */
-#define AT91C_PIO_ABSR		(AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */
-#define AT91C_PIO_IER		(AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */
-#define AT91C_PIO_PPUDR		(AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */
-#define AT91C_PIO_IMR		(AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */
-#define AT91C_PIO_PER		(AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */
-#define AT91C_PIO_IFDR		(AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */
-#define AT91C_PIO_OWDR		(AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */
-#define AT91C_PIO_MDSR		(AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */
-#define AT91C_PIO_IDR		(AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */
-#define AT91C_PIO_ODSR		(AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */
-#define AT91C_PIO_PPUSR		(AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */
-#define AT91C_PIO_OWSR		(AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */
-#define AT91C_PIO_BSR		(AT91_REG(0xFFFFF474)) /* PIOA Select B Register */
-#define AT91C_PIO_OWER		(AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */
-#define AT91C_PIO_IFER		(AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */
-#define AT91C_PIO_PDSR		(AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */
-#define AT91C_PIO_PPUER		(AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */
-#define AT91C_PIO_OSR		(AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */
-#define AT91C_PIO_ASR		(AT91_REG(0xFFFFF470)) /* PIOA Select A Register */
-#define AT91C_PIO_MDDR		(AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */
-#define AT91C_PIO_CODR		(AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */
-#define AT91C_PIO_MDER		(AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */
-#define AT91C_PIO_PDR		(AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */
-#define AT91C_PIO_IFSR		(AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */
-#define AT91C_PIO_OER		(AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */
-#define AT91C_PIO_PSR		(AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */
+#define AT91C_PIO_ODR       (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */
+#define AT91C_PIO_SODR      (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */
+#define AT91C_PIO_ISR       (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */
+#define AT91C_PIO_ABSR      (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */
+#define AT91C_PIO_IER       (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */
+#define AT91C_PIO_PPUDR     (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */
+#define AT91C_PIO_IMR       (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */
+#define AT91C_PIO_PER       (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */
+#define AT91C_PIO_IFDR      (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */
+#define AT91C_PIO_OWDR      (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */
+#define AT91C_PIO_MDSR      (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */
+#define AT91C_PIO_IDR       (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */
+#define AT91C_PIO_ODSR      (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */
+#define AT91C_PIO_PPUSR     (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */
+#define AT91C_PIO_OWSR      (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */
+#define AT91C_PIO_BSR       (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */
+#define AT91C_PIO_OWER      (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */
+#define AT91C_PIO_IFER      (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */
+#define AT91C_PIO_PDSR      (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */
+#define AT91C_PIO_PPUER     (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */
+#define AT91C_PIO_OSR       (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */
+#define AT91C_PIO_ASR       (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */
+#define AT91C_PIO_MDDR      (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */
+#define AT91C_PIO_CODR      (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */
+#define AT91C_PIO_MDER      (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */
+#define AT91C_PIO_PDR       (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */
+#define AT91C_PIO_IFSR      (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */
+#define AT91C_PIO_OER       (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */
+#define AT91C_PIO_PSR       (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */
 
 // ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_IMR  	(AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER  	(AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR 	(AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR  	(AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR 	(AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR 	(AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER 	(AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER  	(AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR  	(AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER  	(AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR  	(AT91_REG(0xFFFFF474)) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER 	(AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR 	(AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR  	(AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR  	(AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR 	(AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR 	(AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR  	(AT91_REG(0xFFFFF470)) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR 	(AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_ODSR 	(AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR 	(AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR 	(AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER 	(AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR  	(AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR  	(AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR 	(AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR 	(AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR 	(AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER 	(AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IMR      (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER      (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR     (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR      (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR    (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR     (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER     (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER      (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR      (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER      (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR      (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER    (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR     (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR      (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR      (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR     (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR     (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR      (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR    (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_ODSR     (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR     (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR     (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER     (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR      (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR      (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR     (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR     (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR     (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER     (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register
 // ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWSR 	(AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PPUSR 	(AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_PPUDR 	(AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_MDSR 	(AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_MDER 	(AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_IMR  	(AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_OSR  	(AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register
-#define AT91C_PIOB_OER  	(AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PSR  	(AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register
-#define AT91C_PIOB_PER  	(AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register
-#define AT91C_PIOB_BSR  	(AT91_REG(0xFFFFF674)) // (PIOB) Select B Register
-#define AT91C_PIOB_PPUER 	(AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_IFDR 	(AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_ODR  	(AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_ABSR 	(AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_ASR  	(AT91_REG(0xFFFFF670)) // (PIOB) Select A Register
-#define AT91C_PIOB_IFER 	(AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_IFSR 	(AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_SODR 	(AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ODSR 	(AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_CODR 	(AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_PDSR 	(AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_OWER 	(AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_IER  	(AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_OWDR 	(AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDDR 	(AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_ISR  	(AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_IDR  	(AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_PDR  	(AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_OWSR     (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PPUSR    (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_PPUDR    (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_MDSR     (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_MDER     (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_IMR      (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_OSR      (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register
+#define AT91C_PIOB_OER      (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PSR      (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register
+#define AT91C_PIOB_PER      (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register
+#define AT91C_PIOB_BSR      (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register
+#define AT91C_PIOB_PPUER    (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_IFDR     (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_ODR      (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_ABSR     (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_ASR      (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register
+#define AT91C_PIOB_IFER     (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_IFSR     (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_SODR     (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ODSR     (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_CODR     (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_PDSR     (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_OWER     (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_IER      (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_OWDR     (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDDR     (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_ISR      (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_IDR      (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_PDR      (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register
 
 /* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_SCER		(AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */
-#define AT91C_PMC_SCDR		(AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */
-#define AT91C_PMC_SCSR		(AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */
-#define AT91C_PMC_PCER		(AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */
-#define AT91C_PMC_PCDR		(AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */
-#define AT91C_PMC_PCSR		(AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */
-#define AT91C_PMC_MOR		(AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */
-#define AT91C_PMC_MCFR		(AT91_REG(0xFFFFFC24)) /* PMC Main Clock  Frequency Register */
-#define AT91C_PMC_PLLR		(AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */
-#define AT91C_PMC_MCKR		(AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */
-#define AT91C_PMC_PCKR		(AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */
-#define AT91C_PMC_IER		(AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */
-#define AT91C_PMC_IDR		(AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */
-#define AT91C_PMC_SR		(AT91_REG(0xFFFFFC68)) /* PMC Status Register */
-#define AT91C_PMC_IMR		(AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */
+#define AT91C_PMC_SCER      (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */
+#define AT91C_PMC_SCDR      (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */
+#define AT91C_PMC_SCSR      (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */
+#define AT91C_PMC_PCER      (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */
+#define AT91C_PMC_PCDR      (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */
+#define AT91C_PMC_PCSR      (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */
+#define AT91C_PMC_MOR       (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */
+#define AT91C_PMC_MCFR      (AT91_REG(0xFFFFFC24)) /* PMC Main Clock  Frequency Register */
+#define AT91C_PMC_PLLR      (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */
+#define AT91C_PMC_MCKR      (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */
+#define AT91C_PMC_PCKR      (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */
+#define AT91C_PMC_IER       (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */
+#define AT91C_PMC_IDR       (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */
+#define AT91C_PMC_SR        (AT91_REG(0xFFFFFC68)) /* PMC Status Register */
+#define AT91C_PMC_IMR       (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */
 
 /******************************************************************************/
 /*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64                    */
 /******************************************************************************/
-#define AT91C_ID_FIQ    	0 	/* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS    	1 	/* System Peripheral */
-#define AT91C_ID_PIOA   	2 	/* Parallel IO Controller A */
-#define AT91C_ID_PIOB   	3 	/* Parallel IO Controller B */
-#define AT91C_ID_ADC    	4 	/* Analog-to-Digital Converter */
-#define AT91C_ID_SPI    	5	/* Serial Peripheral Interface */
-#define AT91C_ID_US0    	6	/* USART 0 */
-#define AT91C_ID_US1    	7	/* USART 1 */
-#define AT91C_ID_SSC    	8	/* Serial Synchronous Controller */
-#define AT91C_ID_TWI    	9 	/* Two-Wire Interface */
-#define AT91C_ID_PWMC   	10	/* PWM Controller */
-#define AT91C_ID_UDP    	11 	/* USB Device Port */
-#define AT91C_ID_TC0    	12 	/* Timer Counter 0 */
-#define AT91C_ID_TC1    	13 	/* Timer Counter 1 */
-#define AT91C_ID_TC2    	14 	/* Timer Counter 2 */
-#define AT91C_ID_15			15	/* Reserved */
-#define AT91C_ID_16 		16 	/* Reserved */
-#define AT91C_ID_17 		17 	/* Reserved */
-#define AT91C_ID_18 		18 	/* Reserved */
-#define AT91C_ID_19 		19 	/* Reserved */
-#define AT91C_ID_20 		20 	/* Reserved */
-#define AT91C_ID_21 		21 	/* Reserved */
-#define AT91C_ID_22 		22 	/* Reserved */
-#define AT91C_ID_23 		23 	/* Reserved */
-#define AT91C_ID_24 		24 	/* Reserved */
-#define AT91C_ID_25 		25 	/* Reserved */
-#define AT91C_ID_26 		26 	/* Reserved */
-#define AT91C_ID_27 		27 	/* Reserved */
-#define AT91C_ID_28 		28 	/* Reserved */
-#define AT91C_ID_29 		29 	/* Reserved */
-#define AT91C_ID_IRQ0		30 	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1		31 	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91C_ALL_INT		0xC0007FF7	/* ALL VALID INTERRUPTS */
+#define AT91C_ID_FIQ        0   /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS        1   /* System Peripheral */
+#define AT91C_ID_PIOA       2   /* Parallel IO Controller A */
+#define AT91C_ID_PIOB       3   /* Parallel IO Controller B */
+#define AT91C_ID_ADC        4   /* Analog-to-Digital Converter */
+#define AT91C_ID_SPI        5   /* Serial Peripheral Interface */
+#define AT91C_ID_US0        6   /* USART 0 */
+#define AT91C_ID_US1        7   /* USART 1 */
+#define AT91C_ID_SSC        8   /* Serial Synchronous Controller */
+#define AT91C_ID_TWI        9   /* Two-Wire Interface */
+#define AT91C_ID_PWMC       10  /* PWM Controller */
+#define AT91C_ID_UDP        11  /* USB Device Port */
+#define AT91C_ID_TC0        12  /* Timer Counter 0 */
+#define AT91C_ID_TC1        13  /* Timer Counter 1 */
+#define AT91C_ID_TC2        14  /* Timer Counter 2 */
+#define AT91C_ID_15         15  /* Reserved */
+#define AT91C_ID_16         16  /* Reserved */
+#define AT91C_ID_17         17  /* Reserved */
+#define AT91C_ID_18         18  /* Reserved */
+#define AT91C_ID_19         19  /* Reserved */
+#define AT91C_ID_20         20  /* Reserved */
+#define AT91C_ID_21         21  /* Reserved */
+#define AT91C_ID_22         22  /* Reserved */
+#define AT91C_ID_23         23  /* Reserved */
+#define AT91C_ID_24         24  /* Reserved */
+#define AT91C_ID_25         25  /* Reserved */
+#define AT91C_ID_26         26  /* Reserved */
+#define AT91C_ID_27         27  /* Reserved */
+#define AT91C_ID_28         28  /* Reserved */
+#define AT91C_ID_29         29  /* Reserved */
+#define AT91C_ID_IRQ0       30  /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1       31  /* Advanced Interrupt Controller (IRQ1) */
+#define AT91C_ALL_INT       0xC0007FF7  /* ALL VALID INTERRUPTS */
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE			0x10
-#define FIQMODE				0x11
-#define IRQMODE				0x12
-#define SVCMODE				0x13
-#define ABORTMODE			0x17
-#define UNDEFMODE			0x1b
-#define MODEMASK			0x1f
-#define NOINT				0xc0
+#define USERMODE            0x10
+#define FIQMODE             0x11
+#define IRQMODE             0x12
+#define SVCMODE             0x13
+#define ABORTMODE           0x17
+#define UNDEFMODE           0x1b
+#define MODEMASK            0x1f
+#define NOINT               0xc0
 
 #ifdef __cplusplus
 }

libcpu/arm/AT91SAM7S/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 /*@}*/

libcpu/arm/AT91SAM7S/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,7 +11,7 @@
 #include <rtthread.h>
 #include "AT91SAM7S.h"
 
-#define MAX_HANDLERS	32
+#define MAX_HANDLERS    32
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 void rt_hw_interrupt_handler(int vector)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector)
  */
 void rt_hw_interrupt_init()
 {
-	rt_base_t index;
+    rt_base_t index;
 
-	for (index = 0; index < MAX_HANDLERS; index ++)
-	{
-		AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler;
-	}
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler;
+    }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -53,11 +53,11 @@ void rt_hw_interrupt_init()
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	/* disable interrupt */
-	AT91C_AIC_IDCR = 1 << vector;
+    /* disable interrupt */
+    AT91C_AIC_IDCR = 1 << vector;
 
-	/* clear interrupt */
-	AT91C_AIC_ICCR = 1 << vector;
+    /* clear interrupt */
+    AT91C_AIC_ICCR = 1 << vector;
 }
 
 /**
@@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	AT91C_AIC_IECR = 1 << vector;
+    AT91C_AIC_IECR = 1 << vector;
 }
 
 /**
@@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector)
  */
 void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
 {
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector);
-		if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler;
-	}
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector);
+        if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler;
+    }
 }
 
 /*@}*/

libcpu/arm/AT91SAM7S/serial.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,46 +22,46 @@
 typedef volatile rt_uint32_t REG32;
 struct rt_at91serial_hw
 {
-	REG32	 US_CR; 	// Control Register
-	REG32	 US_MR; 	// Mode Register
-	REG32	 US_IER; 	// Interrupt Enable Register
-	REG32	 US_IDR; 	// Interrupt Disable Register
-	REG32	 US_IMR; 	// Interrupt Mask Register
-	REG32	 US_CSR; 	// Channel Status Register
-	REG32	 US_RHR; 	// Receiver Holding Register
-	REG32	 US_THR; 	// Transmitter Holding Register
-	REG32	 US_BRGR; 	// Baud Rate Generator Register
-	REG32	 US_RTOR; 	// Receiver Time-out Register
-	REG32	 US_TTGR; 	// Transmitter Time-guard Register
-	REG32	 Reserved0[5]; 	//
-	REG32	 US_FIDI; 	// FI_DI_Ratio Register
-	REG32	 US_NER; 	// Nb Errors Register
-	REG32	 Reserved1[1]; 	//
-	REG32	 US_IF; 	// IRDA_FILTER Register
-	REG32	 Reserved2[44]; 	//
-	REG32	 US_RPR; 	// Receive Pointer Register
-	REG32	 US_RCR; 	// Receive Counter Register
-	REG32	 US_TPR; 	// Transmit Pointer Register
-	REG32	 US_TCR; 	// Transmit Counter Register
-	REG32	 US_RNPR; 	// Receive Next Pointer Register
-	REG32	 US_RNCR; 	// Receive Next Counter Register
-	REG32	 US_TNPR; 	// Transmit Next Pointer Register
-	REG32	 US_TNCR; 	// Transmit Next Counter Register
-	REG32	 US_PTCR; 	// PDC Transfer Control Register
-	REG32	 US_PTSR; 	// PDC Transfer Status Register
+    REG32    US_CR;     // Control Register
+    REG32    US_MR;     // Mode Register
+    REG32    US_IER;    // Interrupt Enable Register
+    REG32    US_IDR;    // Interrupt Disable Register
+    REG32    US_IMR;    // Interrupt Mask Register
+    REG32    US_CSR;    // Channel Status Register
+    REG32    US_RHR;    // Receiver Holding Register
+    REG32    US_THR;    // Transmitter Holding Register
+    REG32    US_BRGR;   // Baud Rate Generator Register
+    REG32    US_RTOR;   // Receiver Time-out Register
+    REG32    US_TTGR;   // Transmitter Time-guard Register
+    REG32    Reserved0[5];  //
+    REG32    US_FIDI;   // FI_DI_Ratio Register
+    REG32    US_NER;    // Nb Errors Register
+    REG32    Reserved1[1];  //
+    REG32    US_IF;     // IRDA_FILTER Register
+    REG32    Reserved2[44];     //
+    REG32    US_RPR;    // Receive Pointer Register
+    REG32    US_RCR;    // Receive Counter Register
+    REG32    US_TPR;    // Transmit Pointer Register
+    REG32    US_TCR;    // Transmit Counter Register
+    REG32    US_RNPR;   // Receive Next Pointer Register
+    REG32    US_RNCR;   // Receive Next Counter Register
+    REG32    US_TNPR;   // Transmit Next Pointer Register
+    REG32    US_TNCR;   // Transmit Next Counter Register
+    REG32    US_PTCR;   // PDC Transfer Control Register
+    REG32    US_PTSR;   // PDC Transfer Status Register
 };
 
 struct rt_at91serial
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	struct rt_at91serial_hw* hw_base;
-	rt_uint16_t peripheral_id;
-	rt_uint32_t baudrate;
+    struct rt_at91serial_hw* hw_base;
+    rt_uint16_t peripheral_id;
+    rt_uint32_t baudrate;
 
-	/* reception field */
-	rt_uint16_t save_index, read_index;
-	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* reception field */
+    rt_uint16_t save_index, read_index;
+    rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 #ifdef RT_USING_UART1
 struct rt_at91serial serial1;
@@ -72,312 +72,312 @@ struct rt_at91serial serial2;
 
 static void rt_hw_serial_isr(int irqno)
 {
-	rt_base_t level;
-	struct rt_device* device;
-	struct rt_at91serial* serial = RT_NULL;
+    rt_base_t level;
+    struct rt_device* device;
+    struct rt_at91serial* serial = RT_NULL;
 
-	if (irqno == AT91C_ID_US0)
-	{
+    if (irqno == AT91C_ID_US0)
+    {
 #ifdef RT_USING_UART1
-		/* serial 1 */
-		serial = &serial1;
+        /* serial 1 */
+        serial = &serial1;
 #endif
-	}
-	else if (irqno == AT91C_ID_US1)
-	{
+    }
+    else if (irqno == AT91C_ID_US1)
+    {
 #ifdef RT_USING_UART2
-		/* serial 2 */
-		serial = &serial2;
+        /* serial 2 */
+        serial = &serial2;
 #endif
-	}
-	RT_ASSERT(serial != RT_NULL);
+    }
+    RT_ASSERT(serial != RT_NULL);
 
-	/* get generic device object */
-	device = (rt_device_t)serial;
+    /* get generic device object */
+    device = (rt_device_t)serial;
 
-	/* disable interrupt */
-	level = rt_hw_interrupt_disable();
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
 
-	/* get received character */
-	serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR;
+    /* get received character */
+    serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR;
 
-	/* move to next position */
-	serial->save_index ++;
-	if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
-		serial->save_index = 0;
+    /* move to next position */
+    serial->save_index ++;
+    if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
+        serial->save_index = 0;
 
-	/* if the next position is read index, discard this 'read char' */
-	if (serial->save_index == serial->read_index)
-	{
-		serial->read_index ++;
-		if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-			serial->read_index = 0;
-	}
+    /* if the next position is read index, discard this 'read char' */
+    if (serial->save_index == serial->read_index)
+    {
+        serial->read_index ++;
+        if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+            serial->read_index = 0;
+    }
 
-	/* enable interrupt */
-	rt_hw_interrupt_enable(level);
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
 
-	/* indicate to upper layer application */
-	if (device->rx_indicate != RT_NULL)
-		device->rx_indicate(device, 1);
+    /* indicate to upper layer application */
+    if (device->rx_indicate != RT_NULL)
+        device->rx_indicate(device, 1);
 
-	/* ack interrupt */
-	AT91C_AIC_EOICR = 1;
+    /* ack interrupt */
+    AT91C_AIC_EOICR = 1;
 }
 
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	rt_uint32_t bd;
-	struct rt_at91serial* serial = (struct rt_at91serial*) dev;
-
-	RT_ASSERT(serial != RT_NULL);
-	/* must be US0 or US1 */
-	RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) ||
-		(serial->peripheral_id == AT91C_ID_US1)));
-
-	/* Enable Clock for USART */
-	AT91C_PMC_PCER = 1 << serial->peripheral_id;
-
-	/* Enable RxD0 and TxDO Pin */
-	if (serial->peripheral_id == AT91C_ID_US0)
-	{
-		/* set pinmux */
-		AT91C_PIO_PDR = (1 << 5) | (1 << 6);
-	}
-	else if (serial->peripheral_id == AT91C_ID_US1)
-	{
-		/* set pinmux */
-		AT91C_PIO_PDR = (1 << 21) | (1 << 22);
-	}
-
-	serial->hw_base->US_CR = AT91C_US_RSTRX	| 	/* Reset Receiver      */
-					AT91C_US_RSTTX		|		/* Reset Transmitter   */
-					AT91C_US_RXDIS		|		/* Receiver Disable    */
-					AT91C_US_TXDIS;				/* Transmitter Disable */
-
-	serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL |	/* Normal Mode */
-					AT91C_US_CLKS_CLOCK		|		/* Clock = MCK */
-					AT91C_US_CHRL_8_BITS	|		/* 8-bit Data  */
-					AT91C_US_PAR_NONE		|		/* No Parity   */
-					AT91C_US_NBSTOP_1_BIT;			/* 1 Stop Bit  */
-
-	/* set baud rate divisor */
-	bd =  ((MCK*10)/(serial->baudrate * 16));
-	if ((bd % 10) >= 5) bd = (bd / 10) + 1;
-	else bd /= 10;
-
-	serial->hw_base->US_BRGR = bd;
-	serial->hw_base->US_CR = AT91C_US_RXEN |		/* Receiver Enable     */
-					AT91C_US_TXEN;					/* Transmitter Enable  */
-
-	/* reset rx index */
-	serial->save_index = 0;
-	serial->read_index = 0;
-
-	/* reset rx buffer */
-	rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
-
-	return RT_EOK;
+    rt_uint32_t bd;
+    struct rt_at91serial* serial = (struct rt_at91serial*) dev;
+
+    RT_ASSERT(serial != RT_NULL);
+    /* must be US0 or US1 */
+    RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) ||
+        (serial->peripheral_id == AT91C_ID_US1)));
+
+    /* Enable Clock for USART */
+    AT91C_PMC_PCER = 1 << serial->peripheral_id;
+
+    /* Enable RxD0 and TxDO Pin */
+    if (serial->peripheral_id == AT91C_ID_US0)
+    {
+        /* set pinmux */
+        AT91C_PIO_PDR = (1 << 5) | (1 << 6);
+    }
+    else if (serial->peripheral_id == AT91C_ID_US1)
+    {
+        /* set pinmux */
+        AT91C_PIO_PDR = (1 << 21) | (1 << 22);
+    }
+
+    serial->hw_base->US_CR = AT91C_US_RSTRX |   /* Reset Receiver      */
+                    AT91C_US_RSTTX      |       /* Reset Transmitter   */
+                    AT91C_US_RXDIS      |       /* Receiver Disable    */
+                    AT91C_US_TXDIS;             /* Transmitter Disable */
+
+    serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL |   /* Normal Mode */
+                    AT91C_US_CLKS_CLOCK     |       /* Clock = MCK */
+                    AT91C_US_CHRL_8_BITS    |       /* 8-bit Data  */
+                    AT91C_US_PAR_NONE       |       /* No Parity   */
+                    AT91C_US_NBSTOP_1_BIT;          /* 1 Stop Bit  */
+
+    /* set baud rate divisor */
+    bd =  ((MCK*10)/(serial->baudrate * 16));
+    if ((bd % 10) >= 5) bd = (bd / 10) + 1;
+    else bd /= 10;
+
+    serial->hw_base->US_BRGR = bd;
+    serial->hw_base->US_CR = AT91C_US_RXEN |        /* Receiver Enable     */
+                    AT91C_US_TXEN;                  /* Transmitter Enable  */
+
+    /* reset rx index */
+    serial->save_index = 0;
+    serial->read_index = 0;
+
+    /* reset rx buffer */
+    rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
-
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* enable UART rx interrupt */
-		serial->hw_base->US_IER = 1 << 0; 		/* RxReady interrupt */
-		serial->hw_base->US_IMR |= 1 << 0; 		/* umask RxReady interrupt */
-
-		/* install UART handler */
-		rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL);
-		AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
-		rt_hw_interrupt_umask(serial->peripheral_id);
-	}
-
-	return RT_EOK;
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable UART rx interrupt */
+        serial->hw_base->US_IER = 1 << 0;       /* RxReady interrupt */
+        serial->hw_base->US_IMR |= 1 << 0;      /* umask RxReady interrupt */
+
+        /* install UART handler */
+        rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL);
+        AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
+        rt_hw_interrupt_umask(serial->peripheral_id);
+    }
+
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* disable interrupt */
-		serial->hw_base->US_IDR = 1 << 0; 		/* RxReady interrupt */
-		serial->hw_base->US_IMR &= ~(1 << 0); 	/* mask RxReady interrupt */
-	}
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        serial->hw_base->US_IDR = 1 << 0;       /* RxReady interrupt */
+        serial->hw_base->US_IMR &= ~(1 << 0);   /* mask RxReady interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
-
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
-
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (serial->read_index != serial->save_index)
-			{
-				*ptr = serial->rx_buffer[serial->read_index];
-
-				serial->read_index ++;
-				if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					serial->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
-
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
-
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
-
-			ptr ++; size --;
-		}
-
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
-	{
-		/* not support right now */
-		RT_ASSERT(0);
-	}
-	else
-	{
-		/* poll mode */
-		while (size)
-		{
-			/* Wait for Full Rx Buffer */
-			while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY));
-
-			/* Read Character */
-			*ptr = serial->hw_base->US_RHR;
-			ptr ++;
-			size --;
-		}
-
-		return (rt_size_t)ptr - (rt_size_t)buffer;
-	}
-
-	return 0;
+    rt_uint8_t* ptr;
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
+
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
+
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
+
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (serial->read_index != serial->save_index)
+            {
+                *ptr = serial->rx_buffer[serial->read_index];
+
+                serial->read_index ++;
+                if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    serial->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
+
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
+
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
+
+            ptr ++; size --;
+        }
+
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+    {
+        /* not support right now */
+        RT_ASSERT(0);
+    }
+    else
+    {
+        /* poll mode */
+        while (size)
+        {
+            /* Wait for Full Rx Buffer */
+            while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY));
+
+            /* Read Character */
+            *ptr = serial->hw_base->US_RHR;
+            ptr ++;
+            size --;
+        }
+
+        return (rt_size_t)ptr - (rt_size_t)buffer;
+    }
+
+    return 0;
 }
 
 static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
-
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
-	{
-		if (dev->flag & RT_DEVICE_FLAG_STREAM)
-		{
-			/* it's a stream mode device */
-			while (size)
-			{
-				/* stream mode */
-				if (*ptr == '\n')
-				{
-					while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
-					serial->hw_base->US_THR = '\r';
-				}
-
-				/* Wait for Empty Tx Buffer */
-				while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
-
-				/* Transmit Character */
-				serial->hw_base->US_THR = *ptr;
-				ptr ++; size --;
-			}
-		}
-		else
-		{
-			while (size)
-			{
-				/* Wait for Empty Tx Buffer */
-				while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
-
-				/* Transmit Character */
-				serial->hw_base->US_THR = *ptr;
-				ptr ++; size --;
-			}
-		}
-	}
-
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    rt_uint8_t* ptr;
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
+
+    ptr = (rt_uint8_t*) buffer;
+    if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
+    {
+        if (dev->flag & RT_DEVICE_FLAG_STREAM)
+        {
+            /* it's a stream mode device */
+            while (size)
+            {
+                /* stream mode */
+                if (*ptr == '\n')
+                {
+                    while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
+                    serial->hw_base->US_THR = '\r';
+                }
+
+                /* Wait for Empty Tx Buffer */
+                while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
+
+                /* Transmit Character */
+                serial->hw_base->US_THR = *ptr;
+                ptr ++; size --;
+            }
+        }
+        else
+        {
+            while (size)
+            {
+                /* Wait for Empty Tx Buffer */
+                while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
+
+                /* Transmit Character */
+                serial->hw_base->US_THR = *ptr;
+                ptr ++; size --;
+            }
+        }
+    }
+
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 rt_err_t rt_hw_serial_init()
 {
-	rt_device_t device;
+    rt_device_t device;
 
 #ifdef RT_USING_UART1
-	device = (rt_device_t) &serial1;
-
-	/* init serial device private data */
-	serial1.hw_base 		= (struct rt_at91serial_hw*)AT91C_BASE_US0;
-	serial1.peripheral_id 	= AT91C_ID_US0;
-	serial1.baudrate		= 115200;
-
-	/* set device virtual interface */
-	device->init 	= rt_serial_init;
-	device->open 	= rt_serial_open;
-	device->close 	= rt_serial_close;
-	device->read 	= rt_serial_read;
-	device->write 	= rt_serial_write;
-	device->control = rt_serial_control;
-
-	/* register uart1 on device subsystem */
-	rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    device = (rt_device_t) &serial1;
+
+    /* init serial device private data */
+    serial1.hw_base         = (struct rt_at91serial_hw*)AT91C_BASE_US0;
+    serial1.peripheral_id   = AT91C_ID_US0;
+    serial1.baudrate        = 115200;
+
+    /* set device virtual interface */
+    device->init    = rt_serial_init;
+    device->open    = rt_serial_open;
+    device->close   = rt_serial_close;
+    device->read    = rt_serial_read;
+    device->write   = rt_serial_write;
+    device->control = rt_serial_control;
+
+    /* register uart1 on device subsystem */
+    rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 
 #ifdef RT_USING_UART2
-	device = (rt_device_t) &serial2;
-
-	serial2.hw_base 		= (struct rt_at91serial_hw*)AT91C_BASE_US1;
-	serial2.peripheral_id 	= AT91C_ID_US1;
-	serial2.baudrate		= 115200;
-
-	/* set device virtual interface */
-	device->init 	= rt_serial_init;
-	device->open 	= rt_serial_open;
-	device->close 	= rt_serial_close;
-	device->read 	= rt_serial_read;
-	device->write 	= rt_serial_write;
-	device->control = rt_serial_control;
-
-	/* register uart2 on device subsystem */
-	rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    device = (rt_device_t) &serial2;
+
+    serial2.hw_base         = (struct rt_at91serial_hw*)AT91C_BASE_US1;
+    serial2.peripheral_id   = AT91C_ID_US1;
+    serial2.baudrate        = 115200;
+
+    /* set device virtual interface */
+    device->init    = rt_serial_init;
+    device->open    = rt_serial_open;
+    device->close   = rt_serial_close;
+    device->read    = rt_serial_read;
+    device->write   = rt_serial_write;
+    device->control = rt_serial_control;
+
+    /* register uart2 on device subsystem */
+    rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /*@}*/

libcpu/arm/AT91SAM7S/serial.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,48 +17,48 @@
 #define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
 #endif
 
-#define AT91C_US_RXRDY			((unsigned int) 0x1 <<  0)	/* US RXRDY Interrupt */
-#define AT91C_US_TXRDY			((unsigned int) 0x1 <<  1)	/* US TXRDY Interrupt */
-#define AT91C_US_RSTRX			((unsigned int) 0x1 <<  2)	/* US Reset Receiver */
-#define AT91C_US_RSTTX			((unsigned int) 0x1 <<  3)	/* US Reset Transmitter */
-#define AT91C_US_RXEN			((unsigned int) 0x1 <<  4)	/* US Receiver Enable */
-#define AT91C_US_RXDIS			((unsigned int) 0x1 <<  5)	/* US Receiver Disable */
-#define AT91C_US_TXEN			((unsigned int) 0x1 <<  6)	/* US Transmitter Enable */
-#define AT91C_US_TXDIS			((unsigned int) 0x1 <<  7)	/* US Transmitter Disable */
-#define AT91C_US_RSTSTA			((unsigned int) 0x1 <<  8)	/* US Reset Status Bits */
+#define AT91C_US_RXRDY          ((unsigned int) 0x1 <<  0)  /* US RXRDY Interrupt */
+#define AT91C_US_TXRDY          ((unsigned int) 0x1 <<  1)  /* US TXRDY Interrupt */
+#define AT91C_US_RSTRX          ((unsigned int) 0x1 <<  2)  /* US Reset Receiver */
+#define AT91C_US_RSTTX          ((unsigned int) 0x1 <<  3)  /* US Reset Transmitter */
+#define AT91C_US_RXEN           ((unsigned int) 0x1 <<  4)  /* US Receiver Enable */
+#define AT91C_US_RXDIS          ((unsigned int) 0x1 <<  5)  /* US Receiver Disable */
+#define AT91C_US_TXEN           ((unsigned int) 0x1 <<  6)  /* US Transmitter Enable */
+#define AT91C_US_TXDIS          ((unsigned int) 0x1 <<  7)  /* US Transmitter Disable */
+#define AT91C_US_RSTSTA         ((unsigned int) 0x1 <<  8)  /* US Reset Status Bits */
 
-#define AT91C_US_USMODE_NORMAL	((unsigned int) 0x0)		/* USAR) Normal */
-#define AT91C_US_USMODE_RS485	((unsigned int) 0x1)		/* USAR) RS485 */
-#define AT91C_US_USMODE_HWHSH	((unsigned int) 0x2)		/* USAR) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM	((unsigned int) 0x3)		/* USAR) Modem */
-#define AT91C_US_USMODE_ISO7816_0	((unsigned int) 0x4)	/* USAR) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1	((unsigned int) 0x6)	/* USAR) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA	((unsigned int) 0x8)		/* USAR) IrDA */
-#define AT91C_US_USMODE_SWHSH	((unsigned int) 0xC)		/* USAR) Software Handshaking */
+#define AT91C_US_USMODE_NORMAL  ((unsigned int) 0x0)        /* USAR) Normal */
+#define AT91C_US_USMODE_RS485   ((unsigned int) 0x1)        /* USAR) RS485 */
+#define AT91C_US_USMODE_HWHSH   ((unsigned int) 0x2)        /* USAR) Hardware Handshaking */
+#define AT91C_US_USMODE_MODEM   ((unsigned int) 0x3)        /* USAR) Modem */
+#define AT91C_US_USMODE_ISO7816_0   ((unsigned int) 0x4)    /* USAR) ISO7816 protocol: T = 0 */
+#define AT91C_US_USMODE_ISO7816_1   ((unsigned int) 0x6)    /* USAR) ISO7816 protocol: T = 1 */
+#define AT91C_US_USMODE_IRDA    ((unsigned int) 0x8)        /* USAR) IrDA */
+#define AT91C_US_USMODE_SWHSH   ((unsigned int) 0xC)        /* USAR) Software Handshaking */
 
-#define AT91C_US_CLKS_CLOCK		((unsigned int) 0x0 <<  4)	/* USAR) Clock */
-#define AT91C_US_CLKS_FDIV1		((unsigned int) 0x1 <<  4)	/* USAR) fdiv1 */
-#define AT91C_US_CLKS_SLOW		((unsigned int) 0x2 <<  4)	/* USAR) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT		((unsigned int) 0x3 <<  4)	/* USAR) External (SCK) */
+#define AT91C_US_CLKS_CLOCK     ((unsigned int) 0x0 <<  4)  /* USAR) Clock */
+#define AT91C_US_CLKS_FDIV1     ((unsigned int) 0x1 <<  4)  /* USAR) fdiv1 */
+#define AT91C_US_CLKS_SLOW      ((unsigned int) 0x2 <<  4)  /* USAR) slow_clock (ARM) */
+#define AT91C_US_CLKS_EXT       ((unsigned int) 0x3 <<  4)  /* USAR) External (SCK) */
 
-#define AT91C_US_CHRL_5_BITS	((unsigned int) 0x0 <<  6)	/* USAR) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS	((unsigned int) 0x1 <<  6)	/* USAR) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS	((unsigned int) 0x2 <<  6)	/* USAR) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6)	/* USAR) Character Length: 8 bits */
+#define AT91C_US_CHRL_5_BITS    ((unsigned int) 0x0 <<  6)  /* USAR) Character Length: 5 bits */
+#define AT91C_US_CHRL_6_BITS    ((unsigned int) 0x1 <<  6)  /* USAR) Character Length: 6 bits */
+#define AT91C_US_CHRL_7_BITS    ((unsigned int) 0x2 <<  6)  /* USAR) Character Length: 7 bits */
+#define AT91C_US_CHRL_8_BITS    ((unsigned int) 0x3 <<  6)  /* USAR) Character Length: 8 bits */
 
-#define AT91C_US_PAR_EVEN		((unsigned int) 0x0 <<  9)	/* DBGU Even Parity */
-#define AT91C_US_PAR_ODD		((unsigned int) 0x1 <<  9)	/* DBGU Odd Parity */
-#define AT91C_US_PAR_SPACE		((unsigned int) 0x2 <<  9)	/* DBGU Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK		((unsigned int) 0x3 <<  9)	/* DBGU Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE		((unsigned int) 0x4 <<  9)	/* DBGU No Parity */
-#define AT91C_US_PAR_MULTI_DROP	((unsigned int) 0x6 <<  9)	/* DBGU Multi-drop mode */
+#define AT91C_US_PAR_EVEN       ((unsigned int) 0x0 <<  9)  /* DBGU Even Parity */
+#define AT91C_US_PAR_ODD        ((unsigned int) 0x1 <<  9)  /* DBGU Odd Parity */
+#define AT91C_US_PAR_SPACE      ((unsigned int) 0x2 <<  9)  /* DBGU Parity forced to 0 (Space) */
+#define AT91C_US_PAR_MARK       ((unsigned int) 0x3 <<  9)  /* DBGU Parity forced to 1 (Mark) */
+#define AT91C_US_PAR_NONE       ((unsigned int) 0x4 <<  9)  /* DBGU No Parity */
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 <<  9)  /* DBGU Multi-drop mode */
 
-#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12)	/* USART 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT	((unsigned int) 0x1 << 12)	/* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT	((unsigned int) 0x2 << 12)	/* USART 2 stop bits */
+#define AT91C_US_NBSTOP_1_BIT   ((unsigned int) 0x0 << 12)  /* USART 1 stop bit */
+#define AT91C_US_NBSTOP_15_BIT  ((unsigned int) 0x1 << 12)  /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define AT91C_US_NBSTOP_2_BIT   ((unsigned int) 0x2 << 12)  /* USART 2 stop bits */
 
-#define MCK		48054857
-#define BR    	115200			/* Baud Rate */
-#define BRD  	(MCK/16/BR)		/* Baud Rate Divisor */
+#define MCK     48054857
+#define BR      115200          /* Baud Rate */
+#define BRD     (MCK/16/BR)     /* Baud Rate Divisor */
 
 #endif

libcpu/arm/AT91SAM7S/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/AT91SAM7S/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,12 +20,12 @@
 
 void rt_hw_trap_irq()
 {
-	rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR;
+    rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR;
 
-	hander(AT91C_AIC_ISR);
+    hander(AT91C_AIC_ISR);
 
-	/* end of interrupt */
-	AT91C_AIC_EOICR = 0;
+    /* end of interrupt */
+    AT91C_AIC_EOICR = 0;
 }
 
 void rt_hw_trap_fiq()

libcpu/arm/AT91SAM7X/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 /*@}*/

libcpu/arm/AT91SAM7X/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,10 +13,10 @@
 #include <rthw.h>
 #include "AT91SAM7X256.h"
 
-#define MAX_HANDLERS	32
+#define MAX_HANDLERS    32
 
 /* exception and interrupt handler table */
-struct rt_irq_desc irq_desc[MAX_HANDLERS]; 
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 static void rt_hw_interrupt_handler(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -38,7 +38,7 @@ static void rt_hw_interrupt_handler(int vector, void *param)
  */
 void rt_hw_interrupt_init(void)
 {
-	rt_base_t index;
+    rt_base_t index;
 
     /* init exceptions table */
     for(index=0; index < MAX_HANDLERS; index++)
@@ -47,16 +47,16 @@ void rt_hw_interrupt_init(void)
         irq_desc[index].param = RT_NULL;
     }
 
-	for (index = 0; index < MAX_HANDLERS; index ++)
-	{
-		AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler;
-	}
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler;
+    }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -65,11 +65,11 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	/* disable interrupt */
-	AT91C_BASE_AIC->AIC_IDCR = 1 << vector;
+    /* disable interrupt */
+    AT91C_BASE_AIC->AIC_IDCR = 1 << vector;
 
-	/* clear interrupt */
-	AT91C_BASE_AIC->AIC_ICCR = 1 << vector;
+    /* clear interrupt */
+    AT91C_BASE_AIC->AIC_ICCR = 1 << vector;
 }
 
 /**
@@ -78,7 +78,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	AT91C_BASE_AIC->AIC_IECR = 1 << vector;
+    AT91C_BASE_AIC->AIC_IECR = 1 << vector;
 }
 
 /**
@@ -90,21 +90,21 @@ void rt_hw_interrupt_umask(int vector)
  *
  * @return the old handler
  */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
-									void *param, const char *name)
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                    void *param, const char *name)
 {
-	rt_isr_handler_t old_handler = RT_NULL;
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = (rt_isr_handler_t)handler;
-			irq_desc[vector].param = param;
-		}
-	}
-
-	return old_handler;
+    rt_isr_handler_t old_handler = RT_NULL;
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+        }
+    }
+
+    return old_handler;
 }
 
 /*@}*/

libcpu/arm/AT91SAM7X/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/AT91SAM7X/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,17 +20,17 @@
 
 void rt_hw_trap_irq(void)
 {
-	int irqno;
-	extern struct rt_irq_desc irq_desc[]; 
+    int irqno;
+    extern struct rt_irq_desc irq_desc[];
 
-	/* get interrupt number */
-	irqno = AT91C_BASE_AIC->AIC_ISR;
+    /* get interrupt number */
+    irqno = AT91C_BASE_AIC->AIC_ISR;
 
-	/* invoke isr with parameters */
-	irq_desc[irqno].handler(irqno, irq_desc[irqno].param);
+    /* invoke isr with parameters */
+    irq_desc[irqno].handler(irqno, irq_desc[irqno].param);
 
-	/* end of interrupt */
-	AT91C_BASE_AIC->AIC_EOICR = 0;
+    /* end of interrupt */
+    AT91C_BASE_AIC->AIC_EOICR = 0;
 }
 
 void rt_hw_trap_fiq(void)
@@ -41,9 +41,9 @@ void rt_hw_trap_fiq(void)
 extern struct rt_thread* rt_current_thread;
 void rt_hw_trap_abort(void)
 {
-	rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
-	rt_thread_suspend(rt_current_thread);
-	rt_schedule();
+    rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name);
+    rt_thread_suspend(rt_current_thread);
+    rt_schedule();
 
 }
 /*@}*/

libcpu/arm/am335x/am33xx.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,8 +9,8 @@
 #ifndef __AM33XX_H__
 #define __AM33XX_H__
 
-#define REG32(x) 	(*((volatile unsigned int *)(x)))
-#define REG16(x) 	(*((volatile unsigned short *)(x)))
+#define REG32(x)    (*((volatile unsigned int *)(x)))
+#define REG16(x)    (*((volatile unsigned short *)(x)))
 
 /** Cache Line size in ARM Cortex-A8.                                         */
 #define AM33XX_CACHELINE_SIZE                   (64)
@@ -198,22 +198,22 @@
 #define CM_DPLL_CLKSEL_TIMER2_CLK(base)    REG32(CM_DPLL(base) + 0x8)
 
 /* timer registers */
-#define DMTIMER_TIDR(base)   		REG32(base + 0x0)
-#define DMTIMER_TIOCP_CFG(base)   	REG32(base + 0x10)
-#define DMTIMER_IRQ_EOI(base)   	REG32(base + 0x20)
-#define DMTIMER_IRQSTATUS_RAW(base)	REG32(base + 0x24)
-#define DMTIMER_IRQSTATUS(base)   	REG32(base + 0x28)
-#define DMTIMER_IRQENABLE_SET(base)	REG32(base + 0x2C)
-#define DMTIMER_IRQENABLE_CLR(base)	REG32(base + 0x30)
-#define DMTIMER_IRQWAKEEN(base)   	REG32(base + 0x34)
-#define DMTIMER_TCLR(base)   		REG32(base + 0x38)
-#define DMTIMER_TCRR(base)   		REG32(base + 0x3C)
-#define DMTIMER_TLDR(base)   		REG32(base + 0x40)
-#define DMTIMER_TTGR(base)   		REG32(base + 0x44)
-#define DMTIMER_TWPS(base)   		REG32(base + 0x48)
-#define DMTIMER_TMAR(base)   		REG32(base + 0x4C)
-#define DMTIMER_TCAR(base, n)		REG32(base + 0x50 + (((n) - 1) * 8))
-#define DMTIMER_TSICR(base)   		REG32(base + 0x54)
+#define DMTIMER_TIDR(base)          REG32(base + 0x0)
+#define DMTIMER_TIOCP_CFG(base)     REG32(base + 0x10)
+#define DMTIMER_IRQ_EOI(base)       REG32(base + 0x20)
+#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24)
+#define DMTIMER_IRQSTATUS(base)     REG32(base + 0x28)
+#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C)
+#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30)
+#define DMTIMER_IRQWAKEEN(base)     REG32(base + 0x34)
+#define DMTIMER_TCLR(base)          REG32(base + 0x38)
+#define DMTIMER_TCRR(base)          REG32(base + 0x3C)
+#define DMTIMER_TLDR(base)          REG32(base + 0x40)
+#define DMTIMER_TTGR(base)          REG32(base + 0x44)
+#define DMTIMER_TWPS(base)          REG32(base + 0x48)
+#define DMTIMER_TMAR(base)          REG32(base + 0x4C)
+#define DMTIMER_TCAR(base, n)       REG32(base + 0x50 + (((n) - 1) * 8))
+#define DMTIMER_TSICR(base)         REG32(base + 0x54)
 
 #define EMU_INT               0
 #define COMMTX_INT            1
@@ -317,33 +317,33 @@
 
 struct rt_hw_register
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
-	unsigned long ORIG_r0;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+    unsigned long ORIG_r0;
 };
 
-#define USERMODE	0x10
-#define FIQMODE		0x11
-#define IRQMODE		0x12
-#define SVCMODE		0x13
-#define ABORTMODE	0x17
-#define UNDEFMODE	0x1b
-#define MODEMASK	0x1f
-#define NOINT		0xc0
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define ABORTMODE   0x17
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
 
 #endif

libcpu/arm/am335x/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,74 +17,74 @@
  */
 /*@{*/
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 #if defined(__CC_ARM)
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
-
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
-
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    rt_uint32_t value;
+
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #elif defined(__GNUC__)
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 #endif
 
@@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 #endif
 
@@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
-
-	level = rt_hw_interrupt_disable();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/

libcpu/arm/am335x/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 
 #define AINTC_BASE  AM33XX_AINTC_REGS
 
-#define MAX_HANDLERS	128
+#define MAX_HANDLERS    128
 
 extern volatile rt_uint8_t rt_interrupt_nest;
 
@@ -59,13 +59,13 @@ extern int system_vectors;
 static void rt_hw_vector_init(void)
 {
     unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE;
-    
+
 #ifdef __ICCARM__
     unsigned int *src =  (unsigned int *)&__vector;
 #else
     unsigned int *src =  (unsigned int *)&system_vectors;
 #endif
-    
+
     rt_memcpy(dest, src, 16 * 4);
     rt_cpu_vector_set_base(AM335X_VECTOR_BASE);
 }

libcpu/arm/am335x/interrupt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,28 +14,28 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-#define INTC_REVISION(hw_base) 		    REG32((hw_base) + 0x0)
-#define INTC_SYSCONFIG(hw_base) 		REG32((hw_base) + 0x10)
-#define INTC_SYSSTATUS(hw_base) 		REG32((hw_base) + 0x14)
-#define INTC_SIR_IRQ(hw_base) 		    REG32((hw_base) + 0x40)
-#define INTC_SIR_FIQ(hw_base) 		    REG32((hw_base) + 0x44)
-#define INTC_CONTROL(hw_base) 		    REG32((hw_base) + 0x48)
-#define INTC_PROTECTION(hw_base) 	    REG32((hw_base) + 0x4c)
-#define INTC_IDLE(hw_base)  			REG32((hw_base) + 0x50)
-#define INTC_IRQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x60)
-#define INTC_FIQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x64)
-#define INTC_THRESHOLD(hw_base) 		REG32((hw_base) + 0x68)
-#define INTC_SICR(hw_base)  			REG32((hw_base) + 0x6c)
-#define INTC_SCR(hw_base, n) 		    REG32((hw_base) + 0x70 + ((n) * 0x04))
-#define INTC_ITR(hw_base, n) 		    REG32((hw_base) + 0x80 + ((n) * 0x20))
-#define INTC_MIR(hw_base, n) 		    REG32((hw_base) + 0x84 + ((n) * 0x20))
-#define INTC_MIR_CLEAR(hw_base, n)  	REG32((hw_base) + 0x88 + ((n) * 0x20))
-#define INTC_MIR_SET(hw_base, n) 	    REG32((hw_base) + 0x8c + ((n) * 0x20))
-#define INTC_ISR_SET(hw_base, n) 	    REG32((hw_base) + 0x90 + ((n) * 0x20))
-#define INTC_ISR_CLEAR(hw_base, n) 	    REG32((hw_base) + 0x94 + ((n) * 0x20))
+#define INTC_REVISION(hw_base)          REG32((hw_base) + 0x0)
+#define INTC_SYSCONFIG(hw_base)         REG32((hw_base) + 0x10)
+#define INTC_SYSSTATUS(hw_base)         REG32((hw_base) + 0x14)
+#define INTC_SIR_IRQ(hw_base)           REG32((hw_base) + 0x40)
+#define INTC_SIR_FIQ(hw_base)           REG32((hw_base) + 0x44)
+#define INTC_CONTROL(hw_base)           REG32((hw_base) + 0x48)
+#define INTC_PROTECTION(hw_base)        REG32((hw_base) + 0x4c)
+#define INTC_IDLE(hw_base)              REG32((hw_base) + 0x50)
+#define INTC_IRQ_PRIORITY(hw_base)      REG32((hw_base) + 0x60)
+#define INTC_FIQ_PRIORITY(hw_base)      REG32((hw_base) + 0x64)
+#define INTC_THRESHOLD(hw_base)         REG32((hw_base) + 0x68)
+#define INTC_SICR(hw_base)              REG32((hw_base) + 0x6c)
+#define INTC_SCR(hw_base, n)            REG32((hw_base) + 0x70 + ((n) * 0x04))
+#define INTC_ITR(hw_base, n)            REG32((hw_base) + 0x80 + ((n) * 0x20))
+#define INTC_MIR(hw_base, n)            REG32((hw_base) + 0x84 + ((n) * 0x20))
+#define INTC_MIR_CLEAR(hw_base, n)      REG32((hw_base) + 0x88 + ((n) * 0x20))
+#define INTC_MIR_SET(hw_base, n)        REG32((hw_base) + 0x8c + ((n) * 0x20))
+#define INTC_ISR_SET(hw_base, n)        REG32((hw_base) + 0x90 + ((n) * 0x20))
+#define INTC_ISR_CLEAR(hw_base, n)      REG32((hw_base) + 0x94 + ((n) * 0x20))
 #define INTC_PENDING_IRQ(hw_base, n)    REG32((hw_base) + 0x98 + ((n) * 0x20))
 #define INTC_PENDING_FIQ(hw_base, n)    REG32((hw_base) + 0x9c + ((n) * 0x20))
-#define INTC_ILR(hw_base, n)  		    REG32((hw_base) + 0x100 + ((n) * 0x04))
+#define INTC_ILR(hw_base, n)            REG32((hw_base) + 0x100 + ((n) * 0x04))
 
 void rt_hw_interrupt_control(int vector, int priority, int route);
 int rt_hw_interrupt_get_active(int fiq_irq);

libcpu/arm/am335x/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i);
 
 void mmu_disable_dcache()
 {
-	rt_cpu_dcache_disable();
+    rt_cpu_dcache_disable();
 }
 
 void mmu_enable_dcache()
 {
-	rt_hw_cpu_dcache_enable();
+    rt_hw_cpu_dcache_enable();
 }
 
 void mmu_disable_icache()
 {
-	rt_cpu_icache_disable();
+    rt_cpu_icache_disable();
 }
 
 void mmu_enable_icache()
 {
-	rt_hw_cpu_icache_enable();
+    rt_hw_cpu_icache_enable();
 }
 
 void mmu_disable()
 {
-	rt_cpu_mmu_disable();
+    rt_cpu_mmu_disable();
 }
 
 void mmu_enable()
 {
-	rt_cpu_mmu_enable();
+    rt_cpu_mmu_enable();
 }
 
 void mmu_setttbase(register rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
    /* Invalidates all TLBs.Domain access is selected as
     * client by configuring domain access register,
     * in that case access controlled by permission value
     * set by page table entry
     */
-	value = 0;
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    value = 0;
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	
-	rt_cpu_tlb_set(i);
+    value = 0x55555555;
+    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+
+    rt_cpu_tlb_set(i);
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~0x1f;
+    ptr = buffer & ~0x1f;
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += 32;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += 32;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~0x1f;
+    ptr = buffer & ~0x1f;
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += 32;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += 32;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 /* level1 page table */
@@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS
     nSec=(vaddrEnd>>20)-(vaddrStart>>20);
     for(i=0;i<=nSec;i++)
     {
-		*pTT = attr |(((paddrStart>>20)+i)<<20);
-		pTT++;
+        *pTT = attr |(((paddrStart>>20)+i)<<20);
+        pTT++;
     }
 }
 
@@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void)
     mmu_setmtt(0x00000000, 0xFFFFFFFF,     0x00000000, RW_NCNB);  /* None cached for 4G memory   */
     mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB);    /* 126M cached DDR memory      */
     mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB);  /* 2M none-cached DDR memory   */
-    mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB);    /* 63K OnChip memory 			 */
+    mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB);    /* 63K OnChip memory           */
 }
 
 void rt_hw_mmu_init(void)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
 
     mmu_setmtts();
 
-	/* set MMU table address */
-	mmu_setttbase((rt_uint32_t)_page_table);
+    /* set MMU table address */
+    mmu_setttbase((rt_uint32_t)_page_table);
 
     /* enables MMU */
     mmu_enable();

libcpu/arm/am335x/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,27 +13,27 @@
 
 #include <rtthread.h>
 
-#define DESC_SEC		(0x2)
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
-
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
-
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
-
-#define RW_CB		    (AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		    (AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		    (AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	    (AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define DESC_SEC        (0x2)
+#define CB              (3<<2)  //cache_on, write_back
+#define CNB             (2<<2)  //cache_on, write_through
+#define NCB             (1<<2)  //cache_off,WR_BUF on
+#define NCNB            (0<<2)  //cache_off,WR_BUF off
+#define AP_RW           (3<<10) //supervisor=RW, user=RW
+#define AP_RO           (2<<10) //supervisor=RW, user=RO
+
+#define DOMAIN_FAULT    (0x0)
+#define DOMAIN_CHK      (0x1)
+#define DOMAIN_NOTCHK   (0x3)
+#define DOMAIN0         (0x0<<5)
+#define DOMAIN1         (0x1<<5)
+
+#define DOMAIN0_ATTR    (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR    (DOMAIN_FAULT<<2)
+
+#define RW_CB           (AP_RW|DOMAIN0|CB|DESC_SEC)     /* Read/Write, cache, write back */
+#define RW_CNB          (AP_RW|DOMAIN0|CNB|DESC_SEC)    /* Read/Write, cache, write through */
+#define RW_NCNB         (AP_RW|DOMAIN0|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
+#define RW_FAULT        (AP_RW|DOMAIN1|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
 
 void rt_hw_mmu_init(void);
 

libcpu/arm/am335x/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/am335x/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -36,13 +36,13 @@ extern long list_thread(void);
 
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
         return;
 #endif
 
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
+    rt_kprintf("undefined instruction\n");
+    rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
 
 #ifdef RT_USING_GDB
     if (gdb_mem_fault_handler) {
-        regs->pc = (unsigned long)gdb_mem_fault_handler; 
+        regs->pc = (unsigned long)gdb_mem_fault_handler;
         return;
     }
 #endif
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 void rt_hw_trap_irq()
 {
     void *param;
-	unsigned long ir;
+    unsigned long ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 
-	ir = rt_hw_interrupt_get_active(INT_IRQ);
+    ir = rt_hw_interrupt_get_active(INT_IRQ);
     if (ir == 127)
     {
         /* new IRQ generation */
@@ -169,18 +169,18 @@ void rt_hw_trap_irq()
     if (isr_func != RT_NULL)
         isr_func(ir, param);
 
-	/* new IRQ generation */
+    /* new IRQ generation */
     rt_hw_interrupt_ack(INT_IRQ);
 }
 
 void rt_hw_trap_fiq()
 {
     void *param;
-	unsigned long ir;
+    unsigned long ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 
-	ir = rt_hw_interrupt_get_active(INT_FIQ);
+    ir = rt_hw_interrupt_get_active(INT_FIQ);
 
     /* get interrupt service routine */
     isr_func = isr_table[ir].handler;
@@ -189,7 +189,7 @@ void rt_hw_trap_fiq()
     /* turn to interrupt service routine */
     isr_func(ir, param);
 
-	/* new FIQ generation */
+    /* new FIQ generation */
     rt_hw_interrupt_ack(INT_FIQ);
 }
 

libcpu/arm/arm926/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/arm926/machine.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/arm926/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/arm926/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/arm926/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/arm926/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/armv6/armv6.h

@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef __ARMV6_H__
 #define __ARMV6_H__
 
@@ -26,7 +26,7 @@
 #ifndef __ASSEMBLY__
 struct rt_hw_register
 {
-	rt_uint32_t cpsr;
+    rt_uint32_t cpsr;
     rt_uint32_t r0;
     rt_uint32_t r1;
     rt_uint32_t r2;
@@ -46,24 +46,24 @@ struct rt_hw_register
 };
 #if(0)
 struct rt_hw_register{
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t cpsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t cpsr;
+    rt_uint32_t ORIG_r0;
 };
 #endif
 #endif

libcpu/arm/armv6/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,8 +11,8 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 extern void machine_reset(void);
 extern void machine_shutdown(void);
@@ -20,32 +20,32 @@ extern void machine_shutdown(void);
 #ifdef __GNUC__
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 
@@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit)
 #ifdef __CC_ARM
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #endif
 
@@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 
 /**
@@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 RT_WEAK void rt_hw_cpu_reset()
 {
-	
-	rt_kprintf("Restarting system...\n");
-	machine_reset();
 
-	while(1);	/* loop forever and wait for reset to happen */
+    rt_kprintf("Restarting system...\n");
+    machine_reset();
 
-	/* NEVER REACHED */
+    while(1);   /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
 }
 
 /**
@@ -164,67 +164,67 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	machine_shutdown();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    machine_shutdown();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 #ifdef RT_USING_CPU_FFS
 /**
- * This function finds the first bit set (beginning with the least significant bit) 
+ * This function finds the first bit set (beginning with the least significant bit)
  * in value and return the index of that bit.
  *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of 
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
  * zero from any of these functions means that the argument was zero.
- * 
- * @return return the index of the first bit set. If value is 0, then this function 
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
 #if defined(__CC_ARM)
 int __rt_ffs(int value)
 {
-	register rt_uint32_t x;
+    register rt_uint32_t x;
+
+    if (value == 0)
+        return value;
 
-	if (value == 0)
-		return value;
-	
-	__asm
-	{
-		rsb x, value, #0
-		and x, x, value
-		clz x, x
-		rsb x, x, #32
-	}
+    __asm
+    {
+        rsb x, value, #0
+        and x, x, value
+        clz x, x
+        rsb x, x, #32
+    }
 
-	return x;
+    return x;
 }
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	__ASM("RSB  r4, r0, #0");
-	__ASM("AND  r4, r4, r0");
-	__ASM("CLZ  r4, r4");
-	__ASM("RSB  r0, r4, #32");
+    __ASM("RSB  r4, r0, #0");
+    __ASM("AND  r4, r4, r0");
+    __ASM("CLZ  r4, r4");
+    __ASM("RSB  r0, r4, #32");
 }
 #elif defined(__GNUC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	value &= (-value);
-	asm ("clz %0, %1": "=r"(value) :"r"(value));
+    value &= (-value);
+    asm ("clz %0, %1": "=r"(value) :"r"(value));
 
-	return (32 - value);
+    return (32 - value);
 }
 #endif
 

libcpu/arm/armv6/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,411 +12,411 @@
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	/* Invalidates all TLBs.Domain access is selected as
-	 * client by configuring domain access register,
-	 * in that case access controlled by permission value
-	 * set by page table entry
-	 */
-	value = 0;
-	__asm volatile
-	{
-		mcr p15, 0, value, c8, c7, 0
-	}
+    /* Invalidates all TLBs.Domain access is selected as
+     * client by configuring domain access register,
+     * in that case access controlled by permission value
+     * set by page table entry
+     */
+    value = 0;
+    __asm volatile
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 
-	value = 0x55555555;
-	__asm volatile
-	{
-		mcr p15, 0, value, c3, c0, 0
-			mcr p15, 0, i, c2, c0, 0
-	}
+    value = 0x55555555;
+    __asm volatile
+    {
+        mcr p15, 0, value, c3, c0, 0
+            mcr p15, 0, i, c2, c0, 0
+    }
 }
 
 void mmu_set_domain(rt_uint32_t i)
 {
-	__asm volatile
-	{
-		mcr p15,0, i, c3, c0,  0
-	}
+    __asm volatile
+    {
+        mcr p15,0, i, c3, c0,  0
+    }
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x01
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x01
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x01
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x01
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x1000
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x1000
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x04
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x04
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x1000
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x1000
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x04
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x04
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x02
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x02
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x02
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x02
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	__asm volatile
-	{
-		mcr p15, 0, index, c7, c14, 2
-	}
+    __asm volatile
+    {
+        mcr p15, 0, index, c7, c14, 2
+    }
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while(ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c14, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while(ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c14, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c10, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c10, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c6, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c6, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
-	__asm volatile
-	{
-		mcr p15, 0, value, c8, c7, 0
-	}
+    value = 0;
+    __asm volatile
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 }
 
 void mmu_invalidate_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
+    value = 0;
 
-	__asm volatile
-	{
-		mcr p15, 0, value, c7, c5, 0
-	}
+    __asm volatile
+    {
+        mcr p15, 0, value, c7, c5, 0
+    }
 }
 
 
 void mmu_invalidate_dcache_all()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
+    value = 0;
 
-	__asm volatile
-	{
-		mcr p15, 0, value, c7, c6, 0
-	}
+    __asm volatile
+    {
+        mcr p15, 0, value, c7, c6, 0
+    }
 }
 #elif defined(__GNUC__)
 void mmu_setttbase(register rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	/* Invalidates all TLBs.Domain access is selected as
-	 * client by configuring domain access register,
-	 * in that case access controlled by permission value
-	 * set by page table entry
-	 */
-	value = 0;
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    /* Invalidates all TLBs.Domain access is selected as
+     * client by configuring domain access register,
+     * in that case access controlled by permission value
+     * set by page table entry
+     */
+    value = 0;
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+    value = 0x55555555;
+    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+    asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= 0x1;
-	/* Enables the extended page tables to be configured for
-	   the hardware page translation mechanism, Subpage AP bits disabled */
-	i |= (1 << 23); /* support for ARMv6 MMU features */
-	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
+    i |= 0x1;
+    /* Enables the extended page tables to be configured for
+       the hardware page translation mechanism, Subpage AP bits disabled */
+    i |= (1 << 23); /* support for ARMv6 MMU features */
+    i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~0x1;
+    i &= ~0x1;
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 12);
+    i |= (1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 2);
+    i |= (1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 12);
+    i &= ~(1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 2);
+    i &= ~(1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while(ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while(ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
 }
 #endif
 
@@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024);
  * level2 page table
  * RT_MMU_PTE_SIZE must be 1024*n
  */
-#define RT_MMU_PTE_SIZE		4096
+#define RT_MMU_PTE_SIZE     4096
 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024);
 
 void mmu_create_pgd(struct mem_desc *mdesc)
 {
-	volatile rt_uint32_t *pTT;
-	volatile int i, nSec;
-	pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
-	nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
-	for(i = 0; i <= nSec; i++)
-	{
-		*pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
-		pTT++;
-	}
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
+    nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
+        pTT++;
+    }
 }
 
 void mmu_create_pte(struct mem_desc *mdesc)
 {
-	volatile rt_uint32_t *pTT;
-	volatile rt_uint32_t *p_pteentry;
-	int i;
-	rt_uint32_t vaddr;
-	rt_uint32_t total_page = 0;
-	rt_uint32_t pte_offset = 0;
-	rt_uint32_t sect_attr = 0;
-
-	total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
-	pte_offset = mdesc->sect_attr & 0xfffffc00;
-	sect_attr = mdesc->sect_attr & 0x3ff;
-	vaddr = mdesc->vaddr_start;
-
-	for(i = 0; i < total_page; i++)
-	{
-		pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
-		if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
-		{
-			*pTT = pte_offset | sect_attr;
-			p_pteentry = (rt_uint32_t *)pte_offset +
-				((vaddr & 0x000ff000) >> 12);
-			pte_offset += 1024;
-		}
-		else /* using old Level 1 page table item */
-		{
-			p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
-				((vaddr & 0x000ff000) >> 12);
-		}
-
-
-		*p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
-		vaddr += 0x1000;
-	}
+    volatile rt_uint32_t *pTT;
+    volatile rt_uint32_t *p_pteentry;
+    int i;
+    rt_uint32_t vaddr;
+    rt_uint32_t total_page = 0;
+    rt_uint32_t pte_offset = 0;
+    rt_uint32_t sect_attr = 0;
+
+    total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
+    pte_offset = mdesc->sect_attr & 0xfffffc00;
+    sect_attr = mdesc->sect_attr & 0x3ff;
+    vaddr = mdesc->vaddr_start;
+
+    for(i = 0; i < total_page; i++)
+    {
+        pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
+        if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
+        {
+            *pTT = pte_offset | sect_attr;
+            p_pteentry = (rt_uint32_t *)pte_offset +
+                ((vaddr & 0x000ff000) >> 12);
+            pte_offset += 1024;
+        }
+        else /* using old Level 1 page table item */
+        {
+            p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
+                ((vaddr & 0x000ff000) >> 12);
+        }
+
+
+        *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
+        vaddr += 0x1000;
+    }
 }
 
 static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	rt_uint32_t pte_offset = 0;
-	rt_uint32_t nsec = 0;
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		if (mdesc->mapped_mode == PAGE_MAPPED)
-		{
-			nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
-			mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
-			pte_offset += nsec << 10;
-		}
-		if (pte_offset >= RT_MMU_PTE_SIZE)
-		{
-			rt_kprintf("PTE table size too little\n");
-			RT_ASSERT(0);
-		}
+    rt_uint32_t pte_offset = 0;
+    rt_uint32_t nsec = 0;
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        if (mdesc->mapped_mode == PAGE_MAPPED)
+        {
+            nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
+            mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
+            pte_offset += nsec << 10;
+        }
+        if (pte_offset >= RT_MMU_PTE_SIZE)
+        {
+            rt_kprintf("PTE table size too little\n");
+            RT_ASSERT(0);
+        }
 
-		mdesc++;
-	}
+        mdesc++;
+    }
 }
 
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
-
-	/* clear pgd and pte table */
-	rt_memset((void *)_pgd_table, 0, 16*1024);
-	rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
-	build_pte_mem_desc(mdesc, size);
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		if (mdesc->mapped_mode == SECT_MAPPED)
-		{
-			mmu_create_pgd(mdesc);
-		}
-		else
-		{
-			mmu_create_pte(mdesc);
-		}
-
-		mdesc++;
-	}
-
-	/* set MMU table address */
-	mmu_setttbase((rt_uint32_t)_pgd_table);
-
-	/* enables MMU */
-	mmu_enable();
-
-	/* enable Instruction Cache */
-	mmu_enable_icache();
-
-	/* enable Data Cache */
-	mmu_enable_dcache();
-
-	mmu_invalidate_icache();
-	mmu_invalidate_dcache_all();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
+
+    /* clear pgd and pte table */
+    rt_memset((void *)_pgd_table, 0, 16*1024);
+    rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
+    build_pte_mem_desc(mdesc, size);
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        if (mdesc->mapped_mode == SECT_MAPPED)
+        {
+            mmu_create_pgd(mdesc);
+        }
+        else
+        {
+            mmu_create_pte(mdesc);
+        }
+
+        mdesc++;
+    }
+
+    /* set MMU table address */
+    mmu_setttbase((rt_uint32_t)_pgd_table);
+
+    /* enables MMU */
+    mmu_enable();
+
+    /* enable Instruction Cache */
+    mmu_enable_icache();
+
+    /* enable Data Cache */
+    mmu_enable_dcache();
+
+    mmu_invalidate_icache();
+    mmu_invalidate_dcache_all();
 }
 

libcpu/arm/armv6/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 
 #include <rtthread.h>
 
-#define CACHE_LINE_SIZE	32
+#define CACHE_LINE_SIZE 32
 
 /*
  * Hardware page table definitions.
@@ -30,7 +30,7 @@
 /*
  *   - section
  */
-#define PGD_SECT_BUFFERABLE	(1 << 2)
+#define PGD_SECT_BUFFERABLE (1 << 2)
 #define PGD_SECT_CACHEABLE  (1 << 3)
 #define PGD_SECT_XN         (1 << 4)    /* ARMv6 */
 #define PGD_SECT_AP0        (1 << 10)
@@ -155,35 +155,35 @@
 #define PAGE_RONX_FAULT  (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */
 
 
-#define DESC_SEC		(0x2|(1<<4))
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
+#define DESC_SEC        (0x2|(1<<4))
+#define CB              (3<<2)  //cache_on, write_back
+#define CNB             (2<<2)  //cache_on, write_through
+#define NCB             (1<<2)  //cache_off,WR_BUF on
+#define NCNB            (0<<2)  //cache_off,WR_BUF off
+#define AP_RW           (3<<10) //supervisor=RW, user=RW
+#define AP_RO           (2<<10) //supervisor=RW, user=RO
 
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
+#define DOMAIN_FAULT    (0x0)
+#define DOMAIN_CHK      (0x1)
+#define DOMAIN_NOTCHK   (0x3)
+#define DOMAIN0         (0x0<<5)
+#define DOMAIN1         (0x1<<5)
 
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+#define DOMAIN0_ATTR    (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR    (DOMAIN_FAULT<<2)
 
-#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_CB       (AP_RW|DOMAIN0|CB|DESC_SEC)     /* Read/Write, cache, write back */
+#define RW_CNB      (AP_RW|DOMAIN0|CNB|DESC_SEC)    /* Read/Write, cache, write through */
+#define RW_NCNB     (AP_RW|DOMAIN0|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
+#define RW_FAULT    (AP_RW|DOMAIN1|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
 
 struct mem_desc {
-	rt_uint32_t vaddr_start;
-	rt_uint32_t vaddr_end;
-	rt_uint32_t paddr_start;
-	rt_uint32_t sect_attr;   /* when page mapped */
-	rt_uint32_t page_attr;   /* only sector mapped valid */
-	rt_uint32_t mapped_mode;
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t sect_attr;   /* when page mapped */
+    rt_uint32_t page_attr;   /* only sector mapped valid */
+    rt_uint32_t mapped_mode;
 #define     SECT_MAPPED  0
 #define     PAGE_MAPPED  1
 };

libcpu/arm/armv6/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/armv6/vfp.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/armv6/vfp.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -87,7 +87,7 @@
  })
 
 #define vmsr(vfp, var) \
-    asm("vmsr  "#vfp",  %0"	\
+    asm("vmsr  "#vfp",  %0" \
        : : "r" (var) : "cc")
 
 

libcpu/arm/common/backtrace.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/common/div0.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -8,5 +8,5 @@
  */
 void __div0 (void)
 {
-	while (1) ;
+    while (1) ;
 }

libcpu/arm/common/showmem.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,27 +12,27 @@
 
 void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size)
 {
-	int i = 0, j =0;
+    int i = 0, j =0;
 
-	RT_ASSERT(addr);
+    RT_ASSERT(addr);
 
-	addr = addr & ~0xF;
-	size = 4*((size + 3)/4);
+    addr = addr & ~0xF;
+    size = 4*((size + 3)/4);
 
-	while(i < size)
-	{
-		rt_kprintf("0x%08x: ", addr );
+    while(i < size)
+    {
+        rt_kprintf("0x%08x: ", addr );
 
-		for(j=0; j<4; j++)
-		{
-			rt_kprintf("0x%08x  ", *(rt_uint32_t *)addr);
+        for(j=0; j<4; j++)
+        {
+            rt_kprintf("0x%08x  ", *(rt_uint32_t *)addr);
 
-			addr += 4;
-			i++;
-		}
+            addr += 4;
+            i++;
+        }
 
-		rt_kprintf("\n");
-	}
+        rt_kprintf("\n");
+    }
 
-	return;
+    return;
 }

libcpu/arm/cortex-a/armv7.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,43 +12,43 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
 };
 
 struct rt_hw_stack
 {
-	unsigned long cpsr;
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long lr;
-	unsigned long pc;
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
 };
 
 #define USERMODE    0x10

libcpu/arm/cortex-a/cache.c

@@ -1,11 +1,11 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2019-03-29 	  quanzhao 	   the first version
+ * 2019-03-29     quanzhao     the first version
  */
 #include <rthw.h>
 #include <rtdef.h>

libcpu/arm/cortex-a/cp15.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/gic.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/gic.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/interrupt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/pmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/pmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-a/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-m0/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-m23/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-m3/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-m33/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -457,7 +457,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) 
+#if defined(__CC_ARM)
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00

libcpu/arm/cortex-m33/trustzone.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,7 +31,7 @@ extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2);
 
 rt_ubase_t rt_trustzone_current_context;
 
-#if defined(__CC_ARM) 
+#if defined(__CC_ARM)
 static __inline rt_uint32_t __get_IPSR(void)
 {
   register rt_uint32_t result          __asm("ipsr");
@@ -78,7 +78,7 @@ rt_err_t rt_trustzone_enter(rt_ubase_t module)
     rt_trustzone_init();
     if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0))
     {
-        return RT_EOK; 
+        return RT_EOK;
     }
     return -RT_ERROR;
 }

libcpu/arm/cortex-m4/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -454,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) 
+#if defined(__CC_ARM)
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00

libcpu/arm/cortex-m7/cpu_cache.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,7 +13,7 @@
 #include <rtdef.h>
 #include <board.h>
 
-/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
+/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */
 #define L1CACHE_LINESIZE_BYTE       (32)
 
 void rt_hw_cpu_icache_enable(void)

libcpu/arm/cortex-m7/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-r4/armv7.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -16,23 +16,23 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
 };
 
 #define USERMODE    0x10

libcpu/arm/cortex-r4/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,22 +30,22 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 #ifdef __TI_COMPILER_VERSION__
 #ifdef RT_USING_CPU_FFS
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	__asm("    rsb r1, r0, #0");
-	__asm("    and r1, r1, r0");
-	__asm("    clz r1, r1");
-	__asm("    rsb r0, r1, #32");
+    __asm("    rsb r1, r0, #0");
+    __asm("    and r1, r1, r0");
+    __asm("    clz r1, r1");
+    __asm("    rsb r0, r1, #32");
 }
 #endif
 

libcpu/arm/cortex-r4/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 
 #include "armv7.h"
 
-#define MAX_HANDLERS	96
+#define MAX_HANDLERS    96
 
 /* exception and interrupt handler table */
 struct rt_irq_desc irq_desc[MAX_HANDLERS];
@@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 static void rt_hw_int_not_handle(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 #define vimRAM (0xFFF82000U)
 
 void rt_hw_interrupt_init(void)
 {
-	register int i;
+    register int i;
 
-	rt_uint32_t *vect_addr;
+    rt_uint32_t *vect_addr;
 
     /* the initialization is done in sys_startup.c */
 
@@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void)
     {
         irq_desc[i].handler = rt_hw_int_not_handle;
 
-		vect_addr  = (rt_uint32_t *)(vimRAM + i*4);
-		*vect_addr = (rt_uint32_t)&irq_desc[i];
+        vect_addr  = (rt_uint32_t *)(vimRAM + i*4);
+        *vect_addr = (rt_uint32_t)&irq_desc[i];
     }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 void rt_hw_interrupt_mask(int vector)
@@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector)
  * @return the old handler
  */
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-									void *param, const char *name)
+                                    void *param, const char *name)
 {
-	rt_isr_handler_t old_handler = RT_NULL;
-
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = handler;
-			irq_desc[vector].param = param;
-		}
-	}
-
-	return old_handler;
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = handler;
+            irq_desc[vector].param = param;
+        }
+    }
+
+    return old_handler;
 }
 
 /*@}*/

libcpu/arm/cortex-r4/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/cortex-r4/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,13 +28,13 @@
  */
 void rt_hw_show_register (struct rt_hw_exp_stack *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs)
 {
     rt_kprintf("undefined instruction\n");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
@@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs)
     rt_kprintf("software interrupt\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
     rt_kprintf("prefetch abort\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
     rt_kprintf("Data Abort ");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
     rt_kprintf("Reserved trap\n");
     rt_hw_show_register(regs);
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
     rt_hw_cpu_shutdown();
 }
@@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
 extern rt_isr_handler_t isr_table[];
 void rt_hw_trap_irq(void)
 {
-	int irqno;
-	struct rt_irq_desc* irq;
-	extern struct rt_irq_desc irq_desc[];
+    int irqno;
+    struct rt_irq_desc* irq;
+    extern struct rt_irq_desc irq_desc[];
 
-	irq = (struct rt_irq_desc*) vimREG->IRQVECREG;
-	irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
+    irq = (struct rt_irq_desc*) vimREG->IRQVECREG;
+    irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
 
-	/* invoke isr */
-	irq->handler(irqno, irq->param);
+    /* invoke isr */
+    irq->handler(irqno, irq->param);
 }
 
 void rt_hw_trap_fiq(void)

libcpu/arm/dm36x/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,8 +11,8 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 extern void machine_reset(void);
 extern void machine_shutdown(void);
@@ -20,70 +20,70 @@ extern void machine_shutdown(void);
 #ifdef __GNUC__
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 #endif
 
 #ifdef __CC_ARM
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #endif
 
@@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -102,7 +102,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -111,7 +111,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -120,7 +120,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -129,7 +129,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -138,7 +138,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 
 /**
@@ -147,13 +147,13 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 RT_WEAK void rt_hw_cpu_reset()
 {
-	
-	rt_kprintf("Restarting system...\n");
-	machine_reset();
 
-	while(1);	/* loop forever and wait for reset to happen */
+    rt_kprintf("Restarting system...\n");
+    machine_reset();
 
-	/* NEVER REACHED */
+    while(1);   /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
 }
 
 /**
@@ -162,67 +162,67 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	machine_shutdown();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    machine_shutdown();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 #ifdef RT_USING_CPU_FFS
 /**
- * This function finds the first bit set (beginning with the least significant bit) 
+ * This function finds the first bit set (beginning with the least significant bit)
  * in value and return the index of that bit.
  *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of 
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
  * zero from any of these functions means that the argument was zero.
- * 
- * @return return the index of the first bit set. If value is 0, then this function 
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
 #if defined(__CC_ARM)
 int __rt_ffs(int value)
 {
-	register rt_uint32_t x;
+    register rt_uint32_t x;
+
+    if (value == 0)
+        return value;
 
-	if (value == 0)
-		return value;
-	
-	__asm
-	{
-		rsb x, value, #0
-		and x, x, value
-		clz x, x
-		rsb x, x, #32
-	}
+    __asm
+    {
+        rsb x, value, #0
+        and x, x, value
+        clz x, x
+        rsb x, x, #32
+    }
 
-	return x;
+    return x;
 }
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	__ASM("RSB  r4, r0, #0");
-	__ASM("AND  r4, r4, r0");
-	__ASM("CLZ  r4, r4");
-	__ASM("RSB  r0, r4, #32");
+    __ASM("RSB  r4, r0, #0");
+    __ASM("AND  r4, r4, r0");
+    __ASM("CLZ  r4, r4");
+    __ASM("RSB  r0, r4, #32");
 }
 #elif defined(__GNUC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	value &= (-value);
-	asm ("clz %0, %1": "=r"(value) :"r"(value));
+    value &= (-value);
+    asm ("clz %0, %1": "=r"(value) :"r"(value));
 
-	return (32 - value);
+    return (32 - value);
 }
 #endif
 

libcpu/arm/dm36x/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,22 +12,22 @@
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
    /* Invalidates all TLBs.Domain access is selected as
     * client by configuring domain access register,
     * in that case access controlled by permission value
     * set by page table entry
     */
-	value = 0;
+    value = 0;
     __asm volatile
     {
         mcr p15, 0, value, c8, c7, 0
-	}
+    }
 
-	value = 0x55555555;
-	__asm volatile
-	{
+    value = 0x55555555;
+    __asm volatile
+    {
         mcr p15, 0, value, c3, c0, 0
         mcr p15, 0, i, c2, c0, 0
     }
@@ -153,44 +153,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	__asm volatile
-    	{
-    		MCR p15, 0, ptr, c7, c14, 1
-    	}
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c14, 1
+        }
         ptr += CACHE_LINE_SIZE;
     }
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c10, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c10, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c6, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c6, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
@@ -231,137 +231,137 @@ void mmu_invalidate_dcache_all()
 #elif defined(__GNUC__)
 void mmu_setttbase(register rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
    /* Invalidates all TLBs.Domain access is selected as
     * client by configuring domain access register,
     * in that case access controlled by permission value
     * set by page table entry
     */
-	value = 0;
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    value = 0;
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+    value = 0x55555555;
+    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+    asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= 0x1;
-	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
-	/* S R bit=1 0  for system protection */
-	i |= (1 << 8);
-	i &= ~(1 << 9);
+    i |= 0x1;
+    i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
+    /* S R bit=1 0  for system protection */
+    i |= (1 << 8);
+    i &= ~(1 << 9);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~0x1;
+    i &= ~0x1;
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 12);
+    i |= (1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 2);
+    i |= (1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 12);
+    i &= ~(1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 2);
+    i &= ~(1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
@@ -372,7 +372,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
     while(ptr < buffer + size)
     {
-    	asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
         ptr += CACHE_LINE_SIZE;
     }
 }
@@ -380,38 +380,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
@@ -462,13 +462,13 @@ void mmu_create_pte(struct mem_desc *mdesc)
         if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
         {
             *pTT = pte_offset | sect_attr;
-            p_pteentry = (rt_uint32_t *)pte_offset + 
+            p_pteentry = (rt_uint32_t *)pte_offset +
             ((vaddr & 0x000ff000) >> 12);
             pte_offset += 1024;
         }
         else /* using old Level 1 page table item */
         {
-            p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + 
+            p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
             ((vaddr & 0x000ff000) >> 12);
         }
 
@@ -503,13 +503,13 @@ static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size)
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
 
-	/* clear pgd and pte table */
+    /* clear pgd and pte table */
     rt_memset((void *)_pgd_table, 0, 16*1024);
     rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
     build_pte_mem_desc(mdesc, size);

libcpu/arm/dm36x/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 
 #include <rtthread.h>
 
-#define CACHE_LINE_SIZE	32
+#define CACHE_LINE_SIZE 32
 
 /*
  * Hardware page table definitions.
@@ -30,7 +30,7 @@
 /*
  *   - section
  */
-#define PGD_SECT_BUFFERABLE	(1 << 2)
+#define PGD_SECT_BUFFERABLE (1 << 2)
 #define PGD_SECT_CACHEABLE  (1 << 3)
 #define PGD_SECT_XN         (1 << 4)    /* ARMv6 */
 #define PGD_SECT_AP0        (1 << 10)
@@ -133,14 +133,14 @@
 #define PAGE_RO_FAULT   (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */
 
 struct mem_desc {
-	rt_uint32_t vaddr_start;
-	rt_uint32_t vaddr_end;
-	rt_uint32_t paddr_start;
-	rt_uint32_t sect_attr;   /* when page mapped */
-	rt_uint32_t page_attr;   /* only sector mapped valid */
-	rt_uint32_t mapped_mode;
-	#define     SECT_MAPPED  0
-	#define     PAGE_MAPPED  1
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t sect_attr;   /* when page mapped */
+    rt_uint32_t page_attr;   /* only sector mapped valid */
+    rt_uint32_t mapped_mode;
+    #define     SECT_MAPPED  0
+    #define     PAGE_MAPPED  1
 };
 
 

libcpu/arm/dm36x/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/lpc214x/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,13 +13,13 @@
 #include <rthw.h>
 #include "lpc214x.h"
 
-#define MAX_HANDLERS	32
-#define SVCMODE		    0x13
+#define MAX_HANDLERS    32
+#define SVCMODE         0x13
 
 extern rt_uint32_t rt_interrupt_nest;
 
 /* exception and interrupt handler table */
-struct rt_irq_desc irq_desc[MAX_HANDLERS]; 
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
 
 /**
  * @addtogroup LPC214x
@@ -37,35 +37,35 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS];
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	unsigned long *stk;
-
-	stk 	 = (unsigned long *)stack_addr;
-	*(stk) 	 = (unsigned long)tentry;		/* entry point */
-	*(--stk) = (unsigned long)texit;		/* lr */
-	*(--stk) = 0;							/* r12 */
-	*(--stk) = 0;							/* r11 */
-	*(--stk) = 0;							/* r10 */
-	*(--stk) = 0;							/* r9 */
-	*(--stk) = 0;							/* r8 */
-	*(--stk) = 0;							/* r7 */
-	*(--stk) = 0;							/* r6 */
-	*(--stk) = 0;							/* r5 */
-	*(--stk) = 0;							/* r4 */
-	*(--stk) = 0;							/* r3 */
-	*(--stk) = 0;							/* r2 */
-	*(--stk) = 0;							/* r1 */
-	*(--stk) = (unsigned long)parameter;	/* r0 : argument */
-
-	/* cpsr */
-	if ((rt_uint32_t)tentry & 0x01)
-		*(--stk) = SVCMODE | 0x20;			/* thumb mode */
-	else
-		*(--stk) = SVCMODE;					/* arm mode   */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    unsigned long *stk;
+
+    stk      = (unsigned long *)stack_addr;
+    *(stk)   = (unsigned long)tentry;       /* entry point */
+    *(--stk) = (unsigned long)texit;        /* lr */
+    *(--stk) = 0;                           /* r12 */
+    *(--stk) = 0;                           /* r11 */
+    *(--stk) = 0;                           /* r10 */
+    *(--stk) = 0;                           /* r9 */
+    *(--stk) = 0;                           /* r8 */
+    *(--stk) = 0;                           /* r7 */
+    *(--stk) = 0;                           /* r6 */
+    *(--stk) = 0;                           /* r5 */
+    *(--stk) = 0;                           /* r4 */
+    *(--stk) = 0;                           /* r3 */
+    *(--stk) = 0;                           /* r2 */
+    *(--stk) = 0;                           /* r1 */
+    *(--stk) = (unsigned long)parameter;    /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
 
 /* exception and interrupt handler table */
@@ -74,7 +74,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 void rt_hw_interrupt_handler(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -82,32 +82,32 @@ void rt_hw_interrupt_handler(int vector, void *param)
  */
 void rt_hw_interrupt_init(void)
 {
-	rt_base_t index;
-	rt_uint32_t *vect_addr, *vect_ctl;
+    rt_base_t index;
+    rt_uint32_t *vect_addr, *vect_ctl;
 
-	/* initialize VIC*/
-	VICIntEnClr = 0xffffffff;
-	VICVectAddr = 0;
-	/* set all to IRQ */
-	VICIntSelect = 0;
+    /* initialize VIC*/
+    VICIntEnClr = 0xffffffff;
+    VICVectAddr = 0;
+    /* set all to IRQ */
+    VICIntSelect = 0;
 
     rt_memset(irq_desc, 0x00, sizeof(irq_desc));
-	for (index = 0; index < MAX_HANDLERS; index ++)
-	{
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
         irq_desc[index].handler = rt_hw_interrupt_handler;
 
-		vect_addr 	= (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2));
-		vect_ctl 	= (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2));
+        vect_addr   = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2));
+        vect_ctl    = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2));
 
-		*vect_addr 	= (rt_uint32_t)&irq_desc[index];
-		*vect_ctl 	= 0xF;
-	}
+        *vect_addr  = (rt_uint32_t)&irq_desc[index];
+        *vect_ctl   = 0xF;
+    }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -116,7 +116,7 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	VICIntEnClr = (1 << vector);
+    VICIntEnClr = (1 << vector);
 }
 
 /**
@@ -125,7 +125,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	VICIntEnable = (1 << vector);
+    VICIntEnable = (1 << vector);
 }
 
 /**
@@ -143,17 +143,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 
     if(vector >= 0 && vector < MAX_HANDLERS)
     {
-        rt_uint32_t* vect_ctl 	= (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2));
+        rt_uint32_t* vect_ctl   = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2));
 
         /* assign IRQ slot and enable this slot */
         *vect_ctl = 0x20 | (vector & 0x1F);
 
         old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = handler;
-			irq_desc[vector].param = param;
-		}
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = handler;
+            irq_desc[vector].param = param;
+        }
     }
 
     return old_handler;
@@ -173,22 +173,22 @@ RT_WEAK void rt_hw_cpu_reset(void)
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 void rt_hw_trap_irq(void)
 {
     int irqno;
-	struct rt_irq_desc* irq;
+    struct rt_irq_desc* irq;
     extern struct rt_irq_desc irq_desc[];
 
-	irq = (struct rt_irq_desc*) VICVectAddr;
-	irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
+    irq = (struct rt_irq_desc*) VICVectAddr;
+    irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
 
-	/* invoke isr */
-	irq->handler(irqno, irq->param);
+    /* invoke isr */
+    irq->handler(irqno, irq->param);
 
     /* acknowledge Interrupt */
     // VICVectAddr = 0;

libcpu/arm/lpc214x/lpc214x.h

@@ -361,33 +361,33 @@
 #define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC))
 #define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0))
 
-#define VIC_BASE_ADDR	0xFFFFF000
+#define VIC_BASE_ADDR   0xFFFFF000
 
 enum LPC214x_INT
 {
-	WDT_INT	= 0,
-	SW_INT_reserved,
-	DbgCommRx_INT,
-	DbgCommTx_INT,
-	TIMER0_INT,
-	TIMER1_INT,
-	UART0_INT,
-	UART1_INT,
-	PWM0_INT,
-	I2C0_INT,
-	SP0_INT,
-	SP1_INT,
-	PLL_INT,
-	RTC_INT,
-	EINT0_INT,
-	EINT1_INT,
-	EINT2_INT,
-	EINT3_INT,
-	ADC0_INT,
-	I2C1_INT,
-	BOD_INT,
-	ADC1_INT,
-	USB_INT
+    WDT_INT = 0,
+    SW_INT_reserved,
+    DbgCommRx_INT,
+    DbgCommTx_INT,
+    TIMER0_INT,
+    TIMER1_INT,
+    UART0_INT,
+    UART1_INT,
+    PWM0_INT,
+    I2C0_INT,
+    SP0_INT,
+    SP1_INT,
+    PLL_INT,
+    RTC_INT,
+    EINT0_INT,
+    EINT1_INT,
+    EINT2_INT,
+    EINT3_INT,
+    ADC0_INT,
+    I2C1_INT,
+    BOD_INT,
+    ADC1_INT,
+    USB_INT
 };
 
 #endif  // __LPC214x_H

libcpu/arm/lpc24xx/LPC24xx.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,20 +14,20 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
-	
-#define USERMODE	0x10
-#define FIQMODE		0x11
-#define IRQMODE		0x12
-#define SVCMODE		0x13
-#define ABORTMODE	0x17
-#define UNDEFMODE	0x1b
-#define MODEMASK	0x1f
-#define NOINT		0xc0
-	
-#define MCLK	(72000000)
-	
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define ABORTMODE   0x17
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define MCLK    (72000000)
+
 /* Vectored Interrupt Controller (VIC) */
-#define VIC_BASE_ADDR	0xFFFFF000
+#define VIC_BASE_ADDR   0xFFFFF000
 #define VICIRQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000))
 #define VICFIQStatus   (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004))
 #define VICRawIntr     (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008))
@@ -111,7 +111,7 @@ these registers are known as "VICVectPriority(x)". */
 
 
 /* Pin Connect Block */
-#define PINSEL_BASE_ADDR	0xE002C000
+#define PINSEL_BASE_ADDR    0xE002C000
 #define PINSEL0        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00))
 #define PINSEL1        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04))
 #define PINSEL2        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08))
@@ -137,7 +137,7 @@ these registers are known as "VICVectPriority(x)". */
 #define PINMODE9        (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64))
 
 /* General Purpose Input/Output (GPIO) */
-#define GPIO_BASE_ADDR		0xE0028000
+#define GPIO_BASE_ADDR      0xE0028000
 #define IOPIN0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00))
 #define IOSET0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04))
 #define IODIR0         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08))
@@ -148,13 +148,13 @@ these registers are known as "VICVectPriority(x)". */
 #define IOCLR1         (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C))
 
 /* GPIO Interrupt Registers */
-#define IO0_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) 
+#define IO0_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90))
 #define IO0_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94))
 #define IO0_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84))
 #define IO0_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88))
 #define IO0_INT_CLR     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C))
 
-#define IO2_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) 
+#define IO2_INT_EN_R    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0))
 #define IO2_INT_EN_F    (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4))
 #define IO2_INT_STAT_R  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4))
 #define IO2_INT_STAT_F  (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8))
@@ -162,227 +162,227 @@ these registers are known as "VICVectPriority(x)". */
 
 #define IO_INT_STAT     (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80))
 
-#define PARTCFG_BASE_ADDR		0x3FFF8000
-#define PARTCFG        (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) 
+#define PARTCFG_BASE_ADDR       0x3FFF8000
+#define PARTCFG        (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00))
 
 /* Fast I/O setup */
-#define FIO_BASE_ADDR		0x3FFFC000
-#define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) 
+#define FIO_BASE_ADDR       0x3FFFC000
+#define FIO0DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00))
 #define FIO0MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10))
 #define FIO0PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14))
 #define FIO0SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18))
 #define FIO0CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C))
 
-#define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) 
+#define FIO1DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20))
 #define FIO1MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30))
 #define FIO1PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34))
 #define FIO1SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38))
 #define FIO1CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C))
 
-#define FIO2DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) 
+#define FIO2DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40))
 #define FIO2MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50))
 #define FIO2PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54))
 #define FIO2SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58))
 #define FIO2CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C))
 
-#define FIO3DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) 
+#define FIO3DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60))
 #define FIO3MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70))
 #define FIO3PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74))
 #define FIO3SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78))
 #define FIO3CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C))
 
-#define FIO4DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) 
+#define FIO4DIR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80))
 #define FIO4MASK       (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90))
 #define FIO4PIN        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94))
 #define FIO4SET        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98))
 #define FIO4CLR        (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C))
 
 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
-#define FIO0DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) 
-#define FIO1DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) 
-#define FIO2DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) 
-#define FIO3DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) 
-#define FIO4DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) 
-
-#define FIO0DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) 
-#define FIO1DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) 
-#define FIO2DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) 
-#define FIO3DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) 
-#define FIO4DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) 
-
-#define FIO0DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) 
-#define FIO1DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) 
-#define FIO2DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) 
-#define FIO3DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) 
-#define FIO4DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) 
-
-#define FIO0DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) 
-#define FIO1DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) 
-#define FIO2DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) 
-#define FIO3DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) 
-#define FIO4DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) 
-
-#define FIO0DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) 
-#define FIO1DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) 
-#define FIO2DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) 
-#define FIO3DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) 
-#define FIO4DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) 
-
-#define FIO0DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) 
-#define FIO1DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) 
-#define FIO2DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) 
-#define FIO3DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) 
-#define FIO4DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) 
-
-#define FIO0MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) 
-#define FIO1MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) 
-#define FIO2MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) 
-#define FIO3MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) 
-#define FIO4MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) 
-
-#define FIO0MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) 
-#define FIO1MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) 
-#define FIO2MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) 
-#define FIO3MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) 
-#define FIO4MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) 
-
-#define FIO0MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) 
-#define FIO1MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) 
-#define FIO2MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) 
-#define FIO3MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) 
-#define FIO4MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) 
-
-#define FIO0MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) 
-#define FIO1MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) 
-#define FIO2MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) 
-#define FIO3MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) 
-#define FIO4MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) 
-
-#define FIO0MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) 
-#define FIO1MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) 
-#define FIO2MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) 
-#define FIO3MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) 
-#define FIO4MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) 
-
-#define FIO0MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) 
-#define FIO1MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) 
-#define FIO2MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) 
-#define FIO3MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) 
-#define FIO4MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) 
-
-#define FIO0PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) 
-#define FIO1PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) 
-#define FIO2PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) 
-#define FIO3PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) 
-#define FIO4PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) 
-
-#define FIO0PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) 
-#define FIO1PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) 
-#define FIO2PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) 
-#define FIO3PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) 
-#define FIO4PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) 
-
-#define FIO0PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) 
-#define FIO1PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) 
-#define FIO2PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) 
-#define FIO3PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) 
-#define FIO4PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) 
-
-#define FIO0PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) 
-#define FIO1PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) 
-#define FIO2PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) 
-#define FIO3PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) 
-#define FIO4PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) 
-
-#define FIO0PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) 
-#define FIO1PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) 
-#define FIO2PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) 
-#define FIO3PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) 
-#define FIO4PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) 
-
-#define FIO0PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) 
-#define FIO1PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) 
-#define FIO2PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) 
-#define FIO3PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) 
-#define FIO4PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) 
-
-#define FIO0SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) 
-#define FIO1SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) 
-#define FIO2SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) 
-#define FIO3SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) 
-#define FIO4SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) 
-
-#define FIO0SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) 
-#define FIO1SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) 
-#define FIO2SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) 
-#define FIO3SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) 
-#define FIO4SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) 
-
-#define FIO0SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) 
-#define FIO1SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) 
-#define FIO2SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) 
-#define FIO3SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) 
-#define FIO4SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) 
-
-#define FIO0SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) 
-#define FIO1SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) 
-#define FIO2SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) 
-#define FIO3SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) 
-#define FIO4SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) 
-
-#define FIO0SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) 
-#define FIO1SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) 
-#define FIO2SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) 
-#define FIO3SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) 
-#define FIO4SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) 
-
-#define FIO0SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) 
-#define FIO1SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) 
-#define FIO2SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) 
-#define FIO3SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) 
-#define FIO4SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) 
-
-#define FIO0CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) 
-#define FIO1CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) 
-#define FIO2CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) 
-#define FIO3CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) 
-#define FIO4CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) 
-
-#define FIO0CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) 
-#define FIO1CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) 
-#define FIO2CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) 
-#define FIO3CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) 
-#define FIO4CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) 
-
-#define FIO0CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) 
-#define FIO1CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) 
-#define FIO2CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) 
-#define FIO3CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) 
-#define FIO4CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) 
-
-#define FIO0CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) 
-#define FIO1CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) 
-#define FIO2CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) 
-#define FIO3CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) 
-#define FIO4CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) 
-
-#define FIO0CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) 
-#define FIO1CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) 
-#define FIO2CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) 
-#define FIO3CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) 
-#define FIO4CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) 
-
-#define FIO0CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) 
-#define FIO1CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) 
-#define FIO2CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) 
-#define FIO3CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) 
-#define FIO4CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) 
+#define FIO0DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00))
+#define FIO1DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20))
+#define FIO2DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40))
+#define FIO3DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60))
+#define FIO4DIR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80))
+
+#define FIO0DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01))
+#define FIO1DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
+#define FIO2DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41))
+#define FIO3DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61))
+#define FIO4DIR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81))
+
+#define FIO0DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02))
+#define FIO1DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22))
+#define FIO2DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42))
+#define FIO3DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62))
+#define FIO4DIR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82))
+
+#define FIO0DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03))
+#define FIO1DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23))
+#define FIO2DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43))
+#define FIO3DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63))
+#define FIO4DIR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83))
+
+#define FIO0DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00))
+#define FIO1DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20))
+#define FIO2DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40))
+#define FIO3DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60))
+#define FIO4DIRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80))
+
+#define FIO0DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02))
+#define FIO1DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22))
+#define FIO2DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42))
+#define FIO3DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62))
+#define FIO4DIRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82))
+
+#define FIO0MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10))
+#define FIO1MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30))
+#define FIO2MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50))
+#define FIO3MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70))
+#define FIO4MASK0      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90))
+
+#define FIO0MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11))
+#define FIO1MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21))
+#define FIO2MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51))
+#define FIO3MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71))
+#define FIO4MASK1      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91))
+
+#define FIO0MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12))
+#define FIO1MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32))
+#define FIO2MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52))
+#define FIO3MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72))
+#define FIO4MASK2      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92))
+
+#define FIO0MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13))
+#define FIO1MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33))
+#define FIO2MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53))
+#define FIO3MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73))
+#define FIO4MASK3      (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93))
+
+#define FIO0MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10))
+#define FIO1MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30))
+#define FIO2MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50))
+#define FIO3MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70))
+#define FIO4MASKL      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90))
+
+#define FIO0MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12))
+#define FIO1MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32))
+#define FIO2MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52))
+#define FIO3MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72))
+#define FIO4MASKU      (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92))
+
+#define FIO0PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14))
+#define FIO1PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34))
+#define FIO2PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54))
+#define FIO3PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74))
+#define FIO4PIN0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94))
+
+#define FIO0PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15))
+#define FIO1PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35))
+#define FIO2PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55))
+#define FIO3PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75))
+#define FIO4PIN1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95))
+
+#define FIO0PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16))
+#define FIO1PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36))
+#define FIO2PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56))
+#define FIO3PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76))
+#define FIO4PIN2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96))
+
+#define FIO0PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17))
+#define FIO1PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37))
+#define FIO2PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57))
+#define FIO3PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77))
+#define FIO4PIN3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97))
+
+#define FIO0PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14))
+#define FIO1PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34))
+#define FIO2PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54))
+#define FIO3PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74))
+#define FIO4PINL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94))
+
+#define FIO0PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16))
+#define FIO1PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36))
+#define FIO2PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56))
+#define FIO3PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76))
+#define FIO4PINU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96))
+
+#define FIO0SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18))
+#define FIO1SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38))
+#define FIO2SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58))
+#define FIO3SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78))
+#define FIO4SET0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98))
+
+#define FIO0SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19))
+#define FIO1SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29))
+#define FIO2SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59))
+#define FIO3SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79))
+#define FIO4SET1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99))
+
+#define FIO0SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A))
+#define FIO1SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A))
+#define FIO2SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A))
+#define FIO3SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A))
+#define FIO4SET2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A))
+
+#define FIO0SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B))
+#define FIO1SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B))
+#define FIO2SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B))
+#define FIO3SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B))
+#define FIO4SET3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B))
+
+#define FIO0SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18))
+#define FIO1SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38))
+#define FIO2SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58))
+#define FIO3SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78))
+#define FIO4SETL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98))
+
+#define FIO0SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A))
+#define FIO1SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A))
+#define FIO2SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A))
+#define FIO3SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A))
+#define FIO4SETU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A))
+
+#define FIO0CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C))
+#define FIO1CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C))
+#define FIO2CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C))
+#define FIO3CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C))
+#define FIO4CLR0       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C))
+
+#define FIO0CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D))
+#define FIO1CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D))
+#define FIO2CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D))
+#define FIO3CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D))
+#define FIO4CLR1       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D))
+
+#define FIO0CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E))
+#define FIO1CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E))
+#define FIO2CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E))
+#define FIO3CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E))
+#define FIO4CLR2       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E))
+
+#define FIO0CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F))
+#define FIO1CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F))
+#define FIO2CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F))
+#define FIO3CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F))
+#define FIO4CLR3       (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F))
+
+#define FIO0CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C))
+#define FIO1CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C))
+#define FIO2CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C))
+#define FIO3CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C))
+#define FIO4CLRL       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C))
+
+#define FIO0CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E))
+#define FIO1CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E))
+#define FIO2CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E))
+#define FIO3CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E))
+#define FIO4CLRU       (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E))
 
 
 /* System Control Block(SCB) modules include Memory Accelerator Module,
-Phase Locked Loop, VPB divider, Power Control, External Interrupt, 
+Phase Locked Loop, VPB divider, Power Control, External Interrupt,
 Reset, and Code Security/Debugging */
-#define SCB_BASE_ADDR	0xE01FC000
+#define SCB_BASE_ADDR   0xE01FC000
 
 /* Memory Accelerator Module (MAM) */
 #define MAMCR          (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000))
@@ -405,7 +405,7 @@ Reset, and Code Security/Debugging */
 #define CLKSRCSEL      (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C))
 #define PCLKSEL0       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8))
 #define PCLKSEL1       (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC))
-	
+
 /* External Interrupts */
 #define EXTINT         (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140))
 #define INTWAKE        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144))
@@ -423,22 +423,22 @@ Reset, and Code Security/Debugging */
 #define AHBCFG2        (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C))
 
 /* System Controls and Status */
-#define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))	
+#define SCS            (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0))
 
-/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers 
+/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
 are for LPC24xx only. */
-#define STATIC_MEM0_BASE		0x80000000
-#define STATIC_MEM1_BASE		0x81000000
-#define STATIC_MEM2_BASE		0x82000000
-#define STATIC_MEM3_BASE		0x83000000
+#define STATIC_MEM0_BASE        0x80000000
+#define STATIC_MEM1_BASE        0x81000000
+#define STATIC_MEM2_BASE        0x82000000
+#define STATIC_MEM3_BASE        0x83000000
 
-#define DYNAMIC_MEM0_BASE		0xA0000000
-#define DYNAMIC_MEM1_BASE		0xB0000000
-#define DYNAMIC_MEM2_BASE		0xC0000000
-#define DYNAMIC_MEM3_BASE		0xD0000000
+#define DYNAMIC_MEM0_BASE       0xA0000000
+#define DYNAMIC_MEM1_BASE       0xB0000000
+#define DYNAMIC_MEM2_BASE       0xC0000000
+#define DYNAMIC_MEM3_BASE       0xD0000000
 
 /* External Memory Controller (EMC) */
-#define EMC_BASE_ADDR		0xFFE08000
+#define EMC_BASE_ADDR       0xFFE08000
 #define EMC_CTRL       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000))
 #define EMC_STAT       (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004))
 #define EMC_CONFIG     (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008))
@@ -503,9 +503,9 @@ are for LPC24xx only. */
 
 #define EMC_STA_EXT_WAIT  (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880))
 
-	
+
 /* Timer 0 */
-#define TMR0_BASE_ADDR		0xE0004000
+#define TMR0_BASE_ADDR      0xE0004000
 #define T0IR           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00))
 #define T0TCR          (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04))
 #define T0TC           (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08))
@@ -525,7 +525,7 @@ are for LPC24xx only. */
 #define T0CTCR         (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70))
 
 /* Timer 1 */
-#define TMR1_BASE_ADDR		0xE0008000
+#define TMR1_BASE_ADDR      0xE0008000
 #define T1IR           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00))
 #define T1TCR          (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04))
 #define T1TC           (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08))
@@ -545,7 +545,7 @@ are for LPC24xx only. */
 #define T1CTCR         (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70))
 
 /* Timer 2 */
-#define TMR2_BASE_ADDR		0xE0070000
+#define TMR2_BASE_ADDR      0xE0070000
 #define T2IR           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00))
 #define T2TCR          (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04))
 #define T2TC           (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08))
@@ -565,7 +565,7 @@ are for LPC24xx only. */
 #define T2CTCR         (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70))
 
 /* Timer 3 */
-#define TMR3_BASE_ADDR		0xE0074000
+#define TMR3_BASE_ADDR      0xE0074000
 #define T3IR           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00))
 #define T3TCR          (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04))
 #define T3TC           (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08))
@@ -586,7 +586,7 @@ are for LPC24xx only. */
 
 
 /* Pulse Width Modulator (PWM) */
-#define PWM0_BASE_ADDR		0xE0014000
+#define PWM0_BASE_ADDR      0xE0014000
 #define PWM0IR          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00))
 #define PWM0TCR         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04))
 #define PWM0TC          (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08))
@@ -610,7 +610,7 @@ are for LPC24xx only. */
 #define PWM0LER         (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50))
 #define PWM0CTCR        (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70))
 
-#define PWM1_BASE_ADDR		0xE0018000
+#define PWM1_BASE_ADDR      0xE0018000
 #define PWM1IR          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00))
 #define PWM1TCR         (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04))
 #define PWM1TC          (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08))
@@ -636,7 +636,7 @@ are for LPC24xx only. */
 
 
 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define UART0_BASE_ADDR		0xE000C000
+#define UART0_BASE_ADDR     0xE000C000
 #define U0RBR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
 #define U0THR          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
 #define U0DLL          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00))
@@ -653,7 +653,7 @@ are for LPC24xx only. */
 #define U0TER          (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30))
 
 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define UART1_BASE_ADDR		0xE0010000
+#define UART1_BASE_ADDR     0xE0010000
 #define U1RBR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
 #define U1THR          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
 #define U1DLL          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00))
@@ -671,7 +671,7 @@ are for LPC24xx only. */
 #define U1TER          (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30))
 
 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
-#define UART2_BASE_ADDR		0xE0078000
+#define UART2_BASE_ADDR     0xE0078000
 #define U2RBR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
 #define U2THR          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
 #define U2DLL          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00))
@@ -688,7 +688,7 @@ are for LPC24xx only. */
 #define U2TER          (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30))
 
 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
-#define UART3_BASE_ADDR		0xE007C000
+#define UART3_BASE_ADDR     0xE007C000
 #define U3RBR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
 #define U3THR          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
 #define U3DLL          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00))
@@ -705,7 +705,7 @@ are for LPC24xx only. */
 #define U3TER          (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30))
 
 /* I2C Interface 0 */
-#define I2C0_BASE_ADDR		0xE001C000
+#define I2C0_BASE_ADDR      0xE001C000
 #define I20CONSET      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00))
 #define I20STAT        (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04))
 #define I20DAT         (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08))
@@ -715,7 +715,7 @@ are for LPC24xx only. */
 #define I20CONCLR      (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18))
 
 /* I2C Interface 1 */
-#define I2C1_BASE_ADDR		0xE005C000
+#define I2C1_BASE_ADDR      0xE005C000
 #define I21CONSET      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00))
 #define I21STAT        (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04))
 #define I21DAT         (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08))
@@ -725,7 +725,7 @@ are for LPC24xx only. */
 #define I21CONCLR      (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18))
 
 /* I2C Interface 2 */
-#define I2C2_BASE_ADDR		0xE0080000
+#define I2C2_BASE_ADDR      0xE0080000
 #define I22CONSET      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00))
 #define I22STAT        (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04))
 #define I22DAT         (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08))
@@ -735,7 +735,7 @@ are for LPC24xx only. */
 #define I22CONCLR      (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18))
 
 /* SPI0 (Serial Peripheral Interface 0) */
-#define SPI0_BASE_ADDR		0xE0020000
+#define SPI0_BASE_ADDR      0xE0020000
 #define S0SPCR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00))
 #define S0SPSR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04))
 #define S0SPDR         (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08))
@@ -743,7 +743,7 @@ are for LPC24xx only. */
 #define S0SPINT        (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C))
 
 /* SSP0 Controller */
-#define SSP0_BASE_ADDR		0xE0068000
+#define SSP0_BASE_ADDR      0xE0068000
 #define SSP0CR0        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00))
 #define SSP0CR1        (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04))
 #define SSP0DR         (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08))
@@ -756,7 +756,7 @@ are for LPC24xx only. */
 #define SSP0DMACR      (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24))
 
 /* SSP1 Controller */
-#define SSP1_BASE_ADDR		0xE0030000
+#define SSP1_BASE_ADDR      0xE0030000
 #define SSP1CR0        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00))
 #define SSP1CR1        (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04))
 #define SSP1DR         (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08))
@@ -770,7 +770,7 @@ are for LPC24xx only. */
 
 
 /* Real Time Clock */
-#define RTC_BASE_ADDR		0xE0024000
+#define RTC_BASE_ADDR       0xE0024000
 #define RTC_ILR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00))
 #define RTC_CTC         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04))
 #define RTC_CCR         (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08))
@@ -801,7 +801,7 @@ are for LPC24xx only. */
 
 
 /* A/D Converter 0 (AD0) */
-#define AD0_BASE_ADDR		0xE0034000
+#define AD0_BASE_ADDR       0xE0034000
 #define AD0CR          (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00))
 #define AD0GDR         (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04))
 #define AD0INTEN       (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C))
@@ -817,12 +817,12 @@ are for LPC24xx only. */
 
 
 /* D/A Converter */
-#define DAC_BASE_ADDR		0xE006C000
+#define DAC_BASE_ADDR       0xE006C000
 #define DACR           (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00))
 
 
 /* Watchdog */
-#define WDG_BASE_ADDR		0xE0000000
+#define WDG_BASE_ADDR       0xE0000000
 #define WDMOD          (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00))
 #define WDTC           (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04))
 #define WDFEED         (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08))
@@ -830,78 +830,78 @@ are for LPC24xx only. */
 #define WDCLKSEL       (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10))
 
 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
-#define CAN_ACCEPT_BASE_ADDR		0xE003C000
-#define CAN_AFMR		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))  	
-#define CAN_SFF_SA 		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))  	
-#define CAN_SFF_GRP_SA 	(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
-#define CAN_EFF_SA 		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
-#define CAN_EFF_GRP_SA 	(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))  	
-#define CAN_EOT 		(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
-#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))  	
-#define CAN_LUT_ERR 	(*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
-
-#define CAN_CENTRAL_BASE_ADDR		0xE0040000  	
-#define CAN_TX_SR 	(*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))  	
-#define CAN_RX_SR 	(*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))  	
-#define CAN_MSR 	(*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
-
-#define CAN1_BASE_ADDR		0xE0044000
-#define CAN1MOD 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))  	
-#define CAN1CMR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))  	
-#define CAN1GSR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))  	
-#define CAN1ICR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))  	
-#define CAN1IER 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
-#define CAN1BTR 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))  	
-#define CAN1EWL 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))  	
-#define CAN1SR 		(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))  	
-#define CAN1RFS 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))  	
-#define CAN1RID 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
-#define CAN1RDA 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))  	
-#define CAN1RDB 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
-  	
-#define CAN1TFI1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))  	
-#define CAN1TID1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))  	
-#define CAN1TDA1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
-#define CAN1TDB1 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))  	
-#define CAN1TFI2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))  	
-#define CAN1TID2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))  	
-#define CAN1TDA2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))  	
-#define CAN1TDB2 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
-#define CAN1TFI3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))  	
-#define CAN1TID3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))  	
-#define CAN1TDA3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))  	
-#define CAN1TDB3 	(*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
-
-#define CAN2_BASE_ADDR		0xE0048000
-#define CAN2MOD 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))  	
-#define CAN2CMR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))  	
-#define CAN2GSR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))  	
-#define CAN2ICR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))  	
-#define CAN2IER 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
-#define CAN2BTR 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))  	
-#define CAN2EWL 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))  	
-#define CAN2SR 		(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))  	
-#define CAN2RFS 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))  	
-#define CAN2RID 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
-#define CAN2RDA 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))  	
-#define CAN2RDB 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
-  	
-#define CAN2TFI1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))  	
-#define CAN2TID1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))  	
-#define CAN2TDA1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
-#define CAN2TDB1 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))  	
-#define CAN2TFI2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))  	
-#define CAN2TID2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))  	
-#define CAN2TDA2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))  	
-#define CAN2TDB2 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
-#define CAN2TFI3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))  	
-#define CAN2TID3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))  	
-#define CAN2TDA3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))  	
-#define CAN2TDB3 	(*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
+#define CAN_ACCEPT_BASE_ADDR        0xE003C000
+#define CAN_AFMR        (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00))
+#define CAN_SFF_SA      (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04))
+#define CAN_SFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08))
+#define CAN_EFF_SA      (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
+#define CAN_EFF_GRP_SA  (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10))
+#define CAN_EOT         (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14))
+#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18))
+#define CAN_LUT_ERR     (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
+
+#define CAN_CENTRAL_BASE_ADDR       0xE0040000
+#define CAN_TX_SR   (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00))
+#define CAN_RX_SR   (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04))
+#define CAN_MSR     (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08))
+
+#define CAN1_BASE_ADDR      0xE0044000
+#define CAN1MOD     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00))
+#define CAN1CMR     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04))
+#define CAN1GSR     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08))
+#define CAN1ICR     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C))
+#define CAN1IER     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10))
+#define CAN1BTR     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14))
+#define CAN1EWL     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18))
+#define CAN1SR      (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C))
+#define CAN1RFS     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20))
+#define CAN1RID     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24))
+#define CAN1RDA     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28))
+#define CAN1RDB     (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C))
+
+#define CAN1TFI1    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30))
+#define CAN1TID1    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34))
+#define CAN1TDA1    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38))
+#define CAN1TDB1    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C))
+#define CAN1TFI2    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40))
+#define CAN1TID2    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44))
+#define CAN1TDA2    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48))
+#define CAN1TDB2    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C))
+#define CAN1TFI3    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50))
+#define CAN1TID3    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54))
+#define CAN1TDA3    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58))
+#define CAN1TDB3    (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C))
+
+#define CAN2_BASE_ADDR      0xE0048000
+#define CAN2MOD     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00))
+#define CAN2CMR     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04))
+#define CAN2GSR     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08))
+#define CAN2ICR     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C))
+#define CAN2IER     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10))
+#define CAN2BTR     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14))
+#define CAN2EWL     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18))
+#define CAN2SR      (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C))
+#define CAN2RFS     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20))
+#define CAN2RID     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24))
+#define CAN2RDA     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28))
+#define CAN2RDB     (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C))
+
+#define CAN2TFI1    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30))
+#define CAN2TID1    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34))
+#define CAN2TDA1    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38))
+#define CAN2TDB1    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C))
+#define CAN2TFI2    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40))
+#define CAN2TID2    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44))
+#define CAN2TDA2    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48))
+#define CAN2TDB2    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C))
+#define CAN2TFI3    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50))
+#define CAN2TID3    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54))
+#define CAN2TDA3    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58))
+#define CAN2TDB3    (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C))
 
 
 /* MultiMedia Card Interface(MCI) Controller */
-#define MCI_BASE_ADDR		0xE008C000
+#define MCI_BASE_ADDR       0xE008C000
 #define MCI_POWER      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00))
 #define MCI_CLOCK      (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04))
 #define MCI_ARGUMENT   (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08))
@@ -924,7 +924,7 @@ are for LPC24xx only. */
 
 
 /* I2S Interface Controller (I2S) */
-#define I2S_BASE_ADDR		0xE0088000
+#define I2S_BASE_ADDR       0xE0088000
 #define I2S_DAO        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00))
 #define I2S_DAI        (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04))
 #define I2S_TX_FIFO    (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08))
@@ -938,7 +938,7 @@ are for LPC24xx only. */
 
 
 /* General-purpose DMA Controller */
-#define DMA_BASE_ADDR		0xFFE04000
+#define DMA_BASE_ADDR       0xFFE04000
 #define GPDMA_INT_STAT         (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000))
 #define GPDMA_INT_TCSTAT       (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004))
 #define GPDMA_INT_TCCLR        (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008))
@@ -970,8 +970,8 @@ are for LPC24xx only. */
 
 
 /* USB Controller */
-#define USB_INT_BASE_ADDR	0xE01FC1C0
-#define USB_BASE_ADDR		0xFFE0C200		/* USB Base Address */
+#define USB_INT_BASE_ADDR   0xE01FC1C0
+#define USB_BASE_ADDR       0xFFE0C200      /* USB Base Address */
 
 #define USB_INT_STAT    (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00))
 
@@ -1027,7 +1027,7 @@ are for LPC24xx only. */
 
 /* USB Host and OTG registers are for LPC24xx only */
 /* USB Host Controller */
-#define USBHC_BASE_ADDR		0xFFE0C000
+#define USBHC_BASE_ADDR     0xFFE0C000
 #define HC_REVISION         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00))
 #define HC_CONTROL          (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04))
 #define HC_CMD_STAT         (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08))
@@ -1053,16 +1053,16 @@ are for LPC24xx only. */
 #define HC_RH_PORT_STAT2    (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58))
 
 /* USB OTG Controller */
-#define USBOTG_BASE_ADDR	0xFFE0C100
+#define USBOTG_BASE_ADDR    0xFFE0C100
 #define OTG_INT_STAT        (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00))
 #define OTG_INT_EN          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04))
 #define OTG_INT_SET         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08))
 #define OTG_INT_CLR         (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C))
-/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ 
+/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
 #define OTG_STAT_CTRL       (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
 #define OTG_TIMER           (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14))
 
-#define USBOTG_I2C_BASE_ADDR	0xFFE0C300
+#define USBOTG_I2C_BASE_ADDR    0xFFE0C300
 #define OTG_I2C_RX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
 #define OTG_I2C_TX          (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00))
 #define OTG_I2C_STS         (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04))
@@ -1070,20 +1070,20 @@ are for LPC24xx only. */
 #define OTG_I2C_CLKHI       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C))
 #define OTG_I2C_CLKLO       (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10))
 
-/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are 
+/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
-#define USBOTG_CLK_BASE_ADDR	0xFFE0CFF0
+#define USBOTG_CLK_BASE_ADDR    0xFFE0CFF0
 #define OTG_CLK_CTRL        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
 #define OTG_CLK_STAT        (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
 
 /* Note: below three register name convention is for LPC23xx USB device only, match
-with the spec. update in USB Device Section. */ 
+with the spec. update in USB Device Section. */
 #define USBPortSel          (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10))
 #define USBClkCtrl          (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04))
 #define USBClkSt            (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08))
 
 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
-#define MAC_BASE_ADDR		0xFFE00000 /* AHB Peripheral # 0 */
+#define MAC_BASE_ADDR       0xFFE00000 /* AHB Peripheral # 0 */
 #define MAC_MAC1            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
 #define MAC_MAC2            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
 #define MAC_IPGT            (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
@@ -1139,7 +1139,7 @@ with the spec. update in USB Device Section. */
 #define MAC_MODULEID        (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
 
 /* LCD Controller registers */
-#define LCD_BASE_ADDR		0xFFE10000 /* AHB Peripheral # 4 */
+#define LCD_BASE_ADDR       0xFFE10000 /* AHB Peripheral # 4 */
 #define LCD_CFG             (*(volatile unsigned long *)(0xE01FC1B8))
 #define LCD_TIMH            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000))
 #define LCD_TIMV            (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004))
@@ -1169,24 +1169,24 @@ with the spec. update in USB Device Section. */
 
 struct rt_hw_register
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
-	unsigned long ORIG_r0;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+    unsigned long ORIG_r0;
 };
 
 #ifdef __cplusplus

libcpu/arm/lpc24xx/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset()
  */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 /*@}*/

libcpu/arm/lpc24xx/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,10 +13,10 @@
 #include <rthw.h>
 #include "LPC24xx.h"
 
-#define MAX_HANDLERS	32
+#define MAX_HANDLERS    32
 
 /* exception and interrupt handler table */
-struct rt_irq_desc irq_desc[MAX_HANDLERS]; 
+struct rt_irq_desc irq_desc[MAX_HANDLERS];
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -30,19 +30,19 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 /*@{*/
 void rt_hw_interrupt_handler(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 void rt_hw_interrupt_init(void)
 {
-	register int i;
+    register int i;
 
-	rt_uint32_t *vect_addr, *vect_cntl;
-    
-	/* initialize VIC*/
-	VICIntEnClr = 0xffffffff;
-	VICVectAddr = 0;
-	VICIntSelect = 0;
+    rt_uint32_t *vect_addr, *vect_cntl;
+
+    /* initialize VIC*/
+    VICIntEnClr = 0xffffffff;
+    VICVectAddr = 0;
+    VICIntSelect = 0;
 
     /* init exceptions table */
     rt_memset(irq_desc, 0x00, sizeof(irq_desc));
@@ -50,27 +50,27 @@ void rt_hw_interrupt_init(void)
     {
         irq_desc[i].handler = rt_hw_interrupt_handler;
 
-		vect_addr  = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4);
-		vect_cntl  = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4);
-		*vect_addr = (rt_uint32_t)&irq_desc[i];	
-		*vect_cntl = 0xF;
+        vect_addr  = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4);
+        vect_cntl  = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4);
+        *vect_addr = (rt_uint32_t)&irq_desc[i];
+        *vect_cntl = 0xF;
     }
-	
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 void rt_hw_interrupt_mask(int vector)
 {
-	VICIntEnClr = (1 << vector);
+    VICIntEnClr = (1 << vector);
 }
 
 void rt_hw_interrupt_umask(int vector)
 {
-	VICIntEnable = (1 << vector);
+    VICIntEnable = (1 << vector);
 }
 
 /**
@@ -82,22 +82,22 @@ void rt_hw_interrupt_umask(int vector)
  *
  * @return the old handler
  */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
-									void *param, const char *name)
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+                                    void *param, const char *name)
 {
-	rt_isr_handler_t old_handler = RT_NULL;
-
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = handler;
-			irq_desc[vector].param = param;
-		}
-	}
-
-	return old_handler;
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = handler;
+            irq_desc[vector].param = param;
+        }
+    }
+
+    return old_handler;
 }
 
 /*@}*/

libcpu/arm/lpc24xx/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/lpc24xx/trap.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -27,13 +27,13 @@
  */
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -48,8 +48,8 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
     rt_kprintf("undefined instruction\n");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
@@ -66,8 +66,8 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
     rt_kprintf("software interrupt\n");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
@@ -83,8 +83,8 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
     rt_kprintf("prefetch abort\n");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
@@ -97,11 +97,11 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  * @note never invoke this function in application
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
-{	
+{
     rt_kprintf("Data Abort ");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
@@ -116,27 +116,27 @@ void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
     rt_kprintf("not used\n");
     rt_hw_show_register(regs);
-	if (rt_thread_self() != RT_NULL)
-		rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
+    if (rt_thread_self() != RT_NULL)
+        rt_kprintf("Current Thread: %s\n", rt_thread_self()->name);
     rt_hw_cpu_shutdown();
 }
 
 extern rt_isr_handler_t isr_table[];
 void rt_hw_trap_irq(void)
 {
-	int irqno;
-	struct rt_irq_desc* irq;
-	extern struct rt_irq_desc irq_desc[];
+    int irqno;
+    struct rt_irq_desc* irq;
+    extern struct rt_irq_desc irq_desc[];
 
-	irq = (struct rt_irq_desc*) VICVectAddr;
-	irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
+    irq = (struct rt_irq_desc*) VICVectAddr;
+    irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc);
 
-	/* invoke isr */
-	irq->handler(irqno, irq->param);
+    /* invoke isr */
+    irq->handler(irqno, irq->param);
 }
 
 void rt_hw_trap_fiq(void)
-{	
+{
     rt_kprintf("fast interrupt request\n");
 }
 

libcpu/arm/realview-a8-vmm/armv7.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,43 +12,43 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
 };
 
 struct rt_hw_stack
 {
-	unsigned long cpsr;
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long lr;
-	unsigned long pc;
+    unsigned long cpsr;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long lr;
+    unsigned long pc;
 };
 
 #define USERMODE    0x10

libcpu/arm/realview-a8-vmm/cp15.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/cpu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,14 +20,14 @@
 /** shutdown CPU */
 RT_WEAK void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/

libcpu/arm/realview-a8-vmm/gic.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/gic.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/interrupt.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/interrupt.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,28 +14,28 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-#define INTC_REVISION(hw_base) 		    REG32((hw_base) + 0x0)
-#define INTC_SYSCONFIG(hw_base) 		REG32((hw_base) + 0x10)
-#define INTC_SYSSTATUS(hw_base) 		REG32((hw_base) + 0x14)
-#define INTC_SIR_IRQ(hw_base) 		    REG32((hw_base) + 0x40)
-#define INTC_SIR_FIQ(hw_base) 		    REG32((hw_base) + 0x44)
-#define INTC_CONTROL(hw_base) 		    REG32((hw_base) + 0x48)
-#define INTC_PROTECTION(hw_base) 	    REG32((hw_base) + 0x4c)
-#define INTC_IDLE(hw_base)  			REG32((hw_base) + 0x50)
-#define INTC_IRQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x60)
-#define INTC_FIQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x64)
-#define INTC_THRESHOLD(hw_base) 		REG32((hw_base) + 0x68)
-#define INTC_SICR(hw_base)  			REG32((hw_base) + 0x6c)
-#define INTC_SCR(hw_base, n) 		    REG32((hw_base) + 0x70 + ((n) * 0x04))
-#define INTC_ITR(hw_base, n) 		    REG32((hw_base) + 0x80 + ((n) * 0x20))
-#define INTC_MIR(hw_base, n) 		    REG32((hw_base) + 0x84 + ((n) * 0x20))
-#define INTC_MIR_CLEAR(hw_base, n)  	REG32((hw_base) + 0x88 + ((n) * 0x20))
-#define INTC_MIR_SET(hw_base, n) 	    REG32((hw_base) + 0x8c + ((n) * 0x20))
-#define INTC_ISR_SET(hw_base, n) 	    REG32((hw_base) + 0x90 + ((n) * 0x20))
-#define INTC_ISR_CLEAR(hw_base, n) 	    REG32((hw_base) + 0x94 + ((n) * 0x20))
+#define INTC_REVISION(hw_base)          REG32((hw_base) + 0x0)
+#define INTC_SYSCONFIG(hw_base)         REG32((hw_base) + 0x10)
+#define INTC_SYSSTATUS(hw_base)         REG32((hw_base) + 0x14)
+#define INTC_SIR_IRQ(hw_base)           REG32((hw_base) + 0x40)
+#define INTC_SIR_FIQ(hw_base)           REG32((hw_base) + 0x44)
+#define INTC_CONTROL(hw_base)           REG32((hw_base) + 0x48)
+#define INTC_PROTECTION(hw_base)        REG32((hw_base) + 0x4c)
+#define INTC_IDLE(hw_base)              REG32((hw_base) + 0x50)
+#define INTC_IRQ_PRIORITY(hw_base)      REG32((hw_base) + 0x60)
+#define INTC_FIQ_PRIORITY(hw_base)      REG32((hw_base) + 0x64)
+#define INTC_THRESHOLD(hw_base)         REG32((hw_base) + 0x68)
+#define INTC_SICR(hw_base)              REG32((hw_base) + 0x6c)
+#define INTC_SCR(hw_base, n)            REG32((hw_base) + 0x70 + ((n) * 0x04))
+#define INTC_ITR(hw_base, n)            REG32((hw_base) + 0x80 + ((n) * 0x20))
+#define INTC_MIR(hw_base, n)            REG32((hw_base) + 0x84 + ((n) * 0x20))
+#define INTC_MIR_CLEAR(hw_base, n)      REG32((hw_base) + 0x88 + ((n) * 0x20))
+#define INTC_MIR_SET(hw_base, n)        REG32((hw_base) + 0x8c + ((n) * 0x20))
+#define INTC_ISR_SET(hw_base, n)        REG32((hw_base) + 0x90 + ((n) * 0x20))
+#define INTC_ISR_CLEAR(hw_base, n)      REG32((hw_base) + 0x94 + ((n) * 0x20))
 #define INTC_PENDING_IRQ(hw_base, n)    REG32((hw_base) + 0x98 + ((n) * 0x20))
 #define INTC_PENDING_FIQ(hw_base, n)    REG32((hw_base) + 0x9c + ((n) * 0x20))
-#define INTC_ILR(hw_base, n)  		    REG32((hw_base) + 0x100 + ((n) * 0x04))
+#define INTC_ILR(hw_base, n)            REG32((hw_base) + 0x100 + ((n) * 0x04))
 
 void rt_hw_interrupt_control(int vector, int priority, int route);
 int rt_hw_interrupt_get_active(int fiq_irq);

libcpu/arm/realview-a8-vmm/mmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/pmu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/pmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

libcpu/arm/realview-a8-vmm/stack.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *