[bsp][cvitek] add cache opration functions for cache coherence

By default, the small core enables D-Cache without ensuring cache
coherence. Therefore, when using shared memory, inconsistencies can
occur in the data read by the small core and the big core.

Solution: Migrate cache-related functions from the official
duo-buildroot-sdk library to implement cache-related operations in
rthw.h. This allows you to either disable D-Cache or call the
flush_dcache_range function before reading and after writing for
synchronization.

It is recommended to use the flush_dcache_range function, as disabling
D-Cache can have a significant performance impact.

Signed-off-by: zdtyuiop4444 <ign7798540@gmail.com>

bsp/cvitek/c906_little/Kconfig

@@ -14,6 +14,7 @@ config BSP_USING_C906_LITTLE
     bool
     select ARCH_RISCV64
     select ARCH_RISCV_FPU_D
+    select RT_USING_CACHE
     select RT_USING_COMPONENTS_INIT
     select RT_USING_USER_MAIN
     default y

bsp/cvitek/c906_little/board/cache.c

@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024/11/26     zdtyuiop4444 The first version
+ */
+
+#include "cache.h"
+
+inline void rt_hw_cpu_dcache_enable(void)
+{
+    asm volatile("csrs mhcr, %0;" ::"rI"(0x2));
+}
+
+inline void rt_hw_cpu_dcache_disable(void)
+{
+    asm volatile("csrc mhcr, %0;" ::"rI"(0x2));
+}
+
+inline void inv_dcache_range(uintptr_t start, size_t size) {
+    CACHE_OP_RANGE(DCACHE_IPA_A0, start, size);
+}
+
+inline void flush_dcache_range(uintptr_t start, size_t size) {
+    CACHE_OP_RANGE(DCACHE_CIPA_A0, start, size);
+}
+
+inline void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
+{
+    switch (ops)
+    {
+    case RT_HW_CACHE_FLUSH:
+        flush_dcache_range(addr, size);
+        break;
+    case RT_HW_CACHE_INVALIDATE:
+        inv_dcache_range(addr, size);
+        break;
+    default:
+        break;
+    }
+}
+
+inline void rt_hw_cpu_icache_enable(void)
+{
+    asm volatile("csrs mhcr, %0;" ::"rI"(0x1));
+}
+
+inline void rt_hw_cpu_icache_disable(void)
+{
+    asm volatile("csrc mhcr, %0;" ::"rI"(0x1));
+}
+
+inline void inv_icache_range(uintptr_t start, size_t size) {
+    CACHE_OP_RANGE(ICACHE_IPA_A0, start, size);
+}
+
+inline void rt_hw_cpu_icache_ops(int ops, void* addr, int size)
+{
+    switch (ops)
+    {
+    case RT_HW_CACHE_INVALIDATE:
+        inv_icache_range(addr, size);
+        break;
+    default:
+        break;
+    }
+}

bsp/cvitek/c906_little/board/cache.h

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2006-2024, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2024/11/26     zdtyuiop4444 The first version
+ */
+
+#ifndef __CACHE_H__
+#define __CACHE_H__
+
+#include <rthw.h>
+
+#define L1_CACHE_BYTES 64
+#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1))
+
+/*
+ * dcache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    01010      rs1       000      00000  0001011
+ *
+ * dcache.cpa rs1 (clean)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    01001      rs1       000      00000  0001011
+ *
+ * dcache.cipa rs1 (clean then invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    01011      rs1       000      00000  0001011
+ *
+ * icache.ipa rs1 (invalidate)
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000001    11000      rs1       000      00000  0001011
+ *
+ * sync.s
+ * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
+ *   0000000    11001     00000      000      00000  0001011
+ */
+
+#define DCACHE_IPA_A0 ".long 0x02a5000b"
+#define DCACHE_CPA_A0 ".long 0x0295000b"
+#define DCACHE_CIPA_A0 ".long 0x02b5000b"
+#define ICACHE_IPA_A0 ".long 0x0385000b"
+
+#define SYNC_S ".long 0x0190000b"
+
+#define CACHE_OP_RANGE(OP, start, size)                                        \
+    register unsigned long i asm("a0") = start & ~(L1_CACHE_BYTES - 1);        \
+    for (; i < ALIGN(start + size, L1_CACHE_BYTES); i += L1_CACHE_BYTES)       \
+        __asm__ __volatile__(OP);                                              \
+    __asm__ __volatile__(SYNC_S)
+
+#endif /* __CACHE_H__ */

bsp/cvitek/c906_little/rtconfig.h

@@ -120,6 +120,7 @@
 #define RT_BACKTRACE_LEVEL_MAX_NR 32
 /* end of RT-Thread Kernel */
 #define ARCH_CPU_64BIT
+#define RT_USING_CACHE
 #define ARCH_RISCV
 #define ARCH_RISCV_FPU
 #define ARCH_RISCV_FPU_D