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@@ -12,6 +12,8 @@
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* 2019-03-27 YLZ support double can channels, support stm32F4xx (only Legacy mode).
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* 2019-06-17 YLZ port to new STM32F1xx HAL V1.1.3.
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* 2021-02-02 YuZhe XU fix bug in filter config
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+ * 2021-8-25 SVCHAO The baud rate is configured according to the different APB1 frequencies.
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+ f4-series only.
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*/
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#include "drv_can.h"
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@@ -34,7 +36,22 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
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{CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 150)},
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{CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_3TQ | 300)}
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};
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-#elif defined (SOC_SERIES_STM32F4)/* APB1 45MHz(max) */
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+#elif defined (SOC_SERIES_STM32F4) /* 42MHz or 45MHz */
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+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
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+ defined(STM32F401xC) || defined(STM32F401xE) /* 42MHz(max) */
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+static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
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+{
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+ {CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_4TQ | 3)},
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+ {CAN800kBaud, (CAN_SJW_2TQ | CAN_BS1_8TQ | CAN_BS2_5TQ | 4)},
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+ {CAN500kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 6)},
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+ {CAN250kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 12)},
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+ {CAN125kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 24)},
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+ {CAN100kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 30)},
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+ {CAN50kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 60)},
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+ {CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 150)},
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+ {CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 300)}
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+};
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+#else /* APB1 45MHz(max) */
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static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
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{
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{CAN1MBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 3)},
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@@ -47,6 +64,7 @@ static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
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{CAN20kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 150)},
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{CAN10kBaud, (CAN_SJW_2TQ | CAN_BS1_9TQ | CAN_BS2_5TQ | 300)}
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};
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+#endif
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#elif defined (SOC_SERIES_STM32F7)/* APB1 54MHz(max) */
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static const struct stm32_baud_rate_tab can_baud_rate_tab[] =
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{
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svchao