[bsp]update GPL license to Apache-2.0, and format files

bsp/CME_M7/applications/application.c

@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -32,10 +28,10 @@ int rt_application_init()
 
     tid = rt_thread_create("init",
         rt_init_thread_entry,
-		RT_NULL,
+        RT_NULL,
         2048,
-		RT_THREAD_PRIORITY_MAX/3,
-		20);
+        RT_THREAD_PRIORITY_MAX/3,
+        20);
 
     if (tid != RT_NULL)
         rt_thread_startup(tid);

bsp/CME_M7/drivers/board.c

@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009-2014, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/CME_M7/drivers/board.h

@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2009-2014, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -18,7 +14,7 @@
 #include "cmem7_includes.h"
 //#include "cmem7_retarget.h"
 
-#define SRAM_SIZE         64	// KB
+#define SRAM_SIZE         64    // KB
 #define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
 
 //#define RT_USING_UART0

bsp/allwinner_tina/libcpu/context_gcc.S

@@ -1,21 +1,7 @@
 ;/*
-; * File      : context_iar.S
-; * This file is part of RT-Thread RTOS
-; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; * Copyright (c) 2006-2021, RT-Thread Development Team
 ; *
-; *  This program is free software; you can redistribute it and/or modify
-; *  it under the terms of the GNU General Public License as published by
-; *  the Free Software Foundation; either version 2 of the License, or
-; *  (at your option) any later version.
-; *
-; *  This program is distributed in the hope that it will be useful,
-; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-; *  GNU General Public License for more details.
-; *
-; *  You should have received a copy of the GNU General Public License along
-; *  with this program; if not, write to the Free Software Foundation, Inc.,
-; *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+; * SPDX-License-Identifier: Apache-2.0
 ; *
 ; * Change Logs:
 ; * Date           Author       Notes

bsp/amebaz/libraries/smartconfig/inc/smartconfig.h

@@ -1,21 +1,7 @@
 /*
- * File      : smartconfig.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/applications/application.c

@@ -1,25 +1,11 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		 first version
+ * Date           Author        Notes
+ * 2011-01-13     weety      first version
  * 2015-04-27     ArdaFu     Port bsp from at91sam9260 to asm9260t
  */
 

bsp/asm9260t/drivers/board.c

@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/drivers/board.h

@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/drivers/led.c

@@ -1,21 +1,7 @@
 /*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/drivers/led.h

@@ -1,21 +1,7 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/drivers/usart.c

@@ -1,21 +1,7 @@
 /*
- * File      : usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -72,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial,
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
     uart = (asm_uart_t *)serial->parent.user_data;
-    
+
     Hw_UartDisable(uart->port);
 
     Hw_UartReset(uart->port);
-    
-    Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, 
+
+    Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits,
                   cfg->stop_bits, cfg->parity);
 
     Hw_UartEnable(uart->port);

bsp/asm9260t/platform/gpio.c

@@ -1,27 +1,13 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 #include "asm9260t.h"
 #include "rtthread.h"
 

bsp/asm9260t/platform/gpio.h

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/platform/interrupt.c

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/platform/interrupt.h

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,69 +15,69 @@
 
 
 // IRQ Source
-#define INT_ARM_COMMRX                    0 
-#define INT_ARM_COMMTX                    1 
-#define INT_RTC                           2 
-#define INT_GPIO0                         3 
-#define INT_GPIO1                         4 
-#define INT_GPIO2                         5 
-#define INT_GPIO3                         6 
-#define INT_GPIO4_IIS1                    7 
-#define INT_USB0                          8 
-#define INT_USB1                          9 
-#define INT_USB0_DMA                      10  
-#define INT_USB1_DMA                      11  
-#define INT_MAC                           12  
-#define INT_MAC_PMT                       13  
-#define INT_NAND                          14  
-#define INT_UART0                         15  
-#define INT_UART1                         16  
-#define INT_UART2                         17  
-#define INT_UART3                         18  
-#define INT_UART4                         19  
-#define INT_UART5                         20  
-#define INT_UART6                         21  
-#define INT_UART7                         22  
-#define INT_UART8                         23  
-#define INT_UART9                         24  
-#define INT_I2S0                          25  
-#define INT_I2C0                          26  
-#define INT_I2C1                          27  
-#define INT_CAMIF                         28  
-#define INT_TIMER0                        29  
-#define INT_TIMER1                        30  
-#define INT_TIMER2                        31  
-#define INT_TIMER3                        32  
-#define INT_ADC0                          33  
-#define INT_DAC0                          34  
-#define INT_USB0_RESUME_HOSTDISCONNECT    35    
-#define INT_USB0_VBUSVALID                36    
-#define INT_USB1_RESUME_HOSTDISCONNECT    37    
-#define INT_USB1_VBUSVALID                38    
-#define INT_DMA0_CH0                      39  
-#define INT_DMA0_CH1                      40  
-#define INT_DMA0_CH2                      41  
-#define INT_DMA0_CH3                      42  
-#define INT_DMA0_CH4                      43  
-#define INT_DMA0_CH5                      44  
-#define INT_DMA0_CH6                      45  
-#define INT_DMA0_CH7                      46  
-#define INT_DMA1_CH0                      47  
-#define INT_DMA1_CH1                      48  
-#define INT_DMA1_CH2                      49  
-#define INT_DMA1_CH3                      50  
-#define INT_DMA1_CH4                      51  
-#define INT_DMA1_CH5                      52  
-#define INT_DMA1_CH6                      53  
-#define INT_DMA1_CH7                      54  
-#define INT_WATCHDOG                      55  
-#define INT_CAN0                          56  
-#define INT_CAN1                          57  
-#define INT_QEI                           58  
-#define INT_MCPWM                         59  
-#define INT_SPI0                          60  
-#define INT_SPI1                          61  
-#define INT_QUADSPI0                      62  
+#define INT_ARM_COMMRX                    0
+#define INT_ARM_COMMTX                    1
+#define INT_RTC                           2
+#define INT_GPIO0                         3
+#define INT_GPIO1                         4
+#define INT_GPIO2                         5
+#define INT_GPIO3                         6
+#define INT_GPIO4_IIS1                    7
+#define INT_USB0                          8
+#define INT_USB1                          9
+#define INT_USB0_DMA                      10
+#define INT_USB1_DMA                      11
+#define INT_MAC                           12
+#define INT_MAC_PMT                       13
+#define INT_NAND                          14
+#define INT_UART0                         15
+#define INT_UART1                         16
+#define INT_UART2                         17
+#define INT_UART3                         18
+#define INT_UART4                         19
+#define INT_UART5                         20
+#define INT_UART6                         21
+#define INT_UART7                         22
+#define INT_UART8                         23
+#define INT_UART9                         24
+#define INT_I2S0                          25
+#define INT_I2C0                          26
+#define INT_I2C1                          27
+#define INT_CAMIF                         28
+#define INT_TIMER0                        29
+#define INT_TIMER1                        30
+#define INT_TIMER2                        31
+#define INT_TIMER3                        32
+#define INT_ADC0                          33
+#define INT_DAC0                          34
+#define INT_USB0_RESUME_HOSTDISCONNECT    35
+#define INT_USB0_VBUSVALID                36
+#define INT_USB1_RESUME_HOSTDISCONNECT    37
+#define INT_USB1_VBUSVALID                38
+#define INT_DMA0_CH0                      39
+#define INT_DMA0_CH1                      40
+#define INT_DMA0_CH2                      41
+#define INT_DMA0_CH3                      42
+#define INT_DMA0_CH4                      43
+#define INT_DMA0_CH5                      44
+#define INT_DMA0_CH6                      45
+#define INT_DMA0_CH7                      46
+#define INT_DMA1_CH0                      47
+#define INT_DMA1_CH1                      48
+#define INT_DMA1_CH2                      49
+#define INT_DMA1_CH3                      50
+#define INT_DMA1_CH4                      51
+#define INT_DMA1_CH5                      52
+#define INT_DMA1_CH6                      53
+#define INT_DMA1_CH7                      54
+#define INT_WATCHDOG                      55
+#define INT_CAN0                          56
+#define INT_CAN1                          57
+#define INT_QEI                           58
+#define INT_MCPWM                         59
+#define INT_SPI0                          60
+#define INT_SPI1                          61
+#define INT_QUADSPI0                      62
 #define INT_SSP0                          63
 
 #endif

bsp/asm9260t/platform/reset.c

@@ -1,21 +1,7 @@
 /*
- * File      : reset.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/platform/rt_low_level_init.c

@@ -1,21 +1,7 @@
 /*
- * File      : rt_low_level_init.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/platform/rt_low_level_init.h

@@ -1,21 +1,7 @@
 /*
- * File      : rt_low_level_init.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,7 +9,7 @@
  */
 #ifndef __RT_LOW_LEVEL_INIT_H__
 #define __RT_LOW_LEVEL_INIT_H__
- 
+
 /*-------- Stack size of CPU modes -------------------------------------------*/
 #define UND_STK_SIZE 512
 #define SVC_STK_SIZE 4096

bsp/asm9260t/platform/system_clock.c

@@ -1,21 +1,7 @@
 /*
- * File      : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,269 +14,269 @@
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk clk32k = {
-	"clk32k",
-	AT91_SLOW_CLOCK,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "clk32k",
+    AT91_SLOW_CLOCK,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk main_clk = {
-	"main",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "main",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk plla = {
-	"plla",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "plla",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk mck = {
-	"mck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "mck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk uhpck = {
-	"uhpck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "uhpck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk pllb = {
-	"pllb",
-	0,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "pllb",
+    0,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk udpck = {
-	"udpck",
-	0,
-	&pllb,
-	{RT_NULL, RT_NULL},
+    "udpck",
+    0,
+    &pllb,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk *const standard_pmc_clocks[] = {
-	// four primary clocks 
-	&clk32k,
-	&main_clk,
-	&plla,
+    // four primary clocks
+    &clk32k,
+    &main_clk,
+    &plla,
 
-	// MCK 
-	&mck
+    // MCK
+    &mck
 };
 
 // clocks cannot be de-registered no refcounting necessary
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
-
-	return RT_NULL;
+    struct clk *clk;
+    rt_list_t *list;
+
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	rate;
-
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return rate;
+    rt_uint32_t rate;
+
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return rate;
 }
 
 static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	unsigned mul, div;
+    unsigned mul, div;
 
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
+    div = reg & 0xff;
+    mul = (reg >> 16) & 0x7ff;
+    if (div && mul) {
+        freq /= div;
+        freq *= mul + 1;
+    } else
+        freq = 0;
 
-	return freq;
+    return freq;
 }
 
 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 {
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	//PLL output max 240 MHz (or 180 MHz per errata)
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		//
-		// PLL input between 1MHz and 32MHz per spec, but lower
-		// frequences seem necessary in some cases so allow 100K.
-		// Warning: some newer products need 2MHz min.
-		//
-		input = main_freq / i;
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
+    unsigned i, div = 0, mul = 0, diff = 1 << 30;
+    unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+    //PLL output max 240 MHz (or 180 MHz per errata)
+    if (out_freq > 240000000)
+        goto fail;
+
+    for (i = 1; i < 256; i++) {
+        int diff1;
+        unsigned input, mul1;
+
+        //
+        // PLL input between 1MHz and 32MHz per spec, but lower
+        // frequences seem necessary in some cases so allow 100K.
+        // Warning: some newer products need 2MHz min.
+        //
+        input = main_freq / i;
+        if (input < 100000)
+            continue;
+        if (input > 32000000)
+            continue;
+
+        mul1 = out_freq / input;
+        if (mul1 > 2048)
+            continue;
+        if (mul1 < 2)
+            goto fail;
+
+        diff1 = out_freq - input * mul1;
+        if (diff1 < 0)
+            diff1 = -diff1;
+        if (diff > diff1) {
+            diff = diff1;
+            div = i;
+            mul = mul1;
+            if (diff == 0)
+                break;
+        }
+    }
+    if (i == 256 && diff > (out_freq >> 5))
+        goto fail;
+    return ret | ((mul - 1) << 16) | div;
 fail:
-	return 0;
+    return 0;
 }
 
 static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	if (pll == &pllb && (reg & AT91_PMC_USB96M))
-		return freq / 2;
-	else
-		return freq;
+    if (pll == &pllb && (reg & AT91_PMC_USB96M))
+        return freq / 2;
+    else
+        return freq;
 }
 
 
 // PLLB generated USB full speed clock init
 static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
 {
-	rt_uint32_t at91_pllb_usb_init;
-	//
-	// USB clock init:  choose 48 MHz PLLB value,
-	// disable 48MHz clock during usb peripheral suspend.
-	//
-	// REVISIT:  assumes MCK doesn't derive from PLLB!
-	//
-	uhpck.parent = &pllb;
-
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
-	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-	
-	at91_sys_write(AT91_CKGR_PLLBR, 0);
-
-	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    rt_uint32_t at91_pllb_usb_init;
+    //
+    // USB clock init:  choose 48 MHz PLLB value,
+    // disable 48MHz clock during usb peripheral suspend.
+    //
+    // REVISIT:  assumes MCK doesn't derive from PLLB!
+    //
+    uhpck.parent = &pllb;
+
+    at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+    pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+
+    at91_sys_write(AT91_CKGR_PLLBR, 0);
+
+    udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 }
 
 static struct clk *at91_css_to_clk(unsigned long css)
 {
-	switch (css) {
-		case AT91_PMC_CSS_SLOW:
-			return &clk32k;
-		case AT91_PMC_CSS_MAIN:
-			return &main_clk;
-		case AT91_PMC_CSS_PLLA:
-			return &plla;
-		case AT91_PMC_CSS_PLLB:
-			return &pllb;
-	}
-
-	return RT_NULL;
+    switch (css) {
+        case AT91_PMC_CSS_SLOW:
+            return &clk32k;
+        case AT91_PMC_CSS_MAIN:
+            return &main_clk;
+        case AT91_PMC_CSS_PLLA:
+            return &plla;
+        case AT91_PMC_CSS_PLLB:
+            return &pllb;
+    }
+
+    return RT_NULL;
 }
 
 #define false 0
 #define true  1
 int at91_clock_init(rt_uint32_t main_clock)
 {
-	unsigned tmp, freq, mckr;
-	int i;
-	int pll_overclock = false;
-
-	//
-	// When the bootloader initialized the main oscillator correctly,
-	// there's no problem using the cycle counter.  But if it didn't,
-	// or when using oscillator bypass mode, we must be told the speed
-	 // of the main clock.
-	//
-	if (!main_clock) {
-		do {
-			tmp = at91_sys_read(AT91_CKGR_MCFR);
-		} while (!(tmp & AT91_PMC_MAINRDY));
-		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
-	}
-	main_clk.rate_hz = main_clock;
-
-	// report if PLLA is more than mildly overclocked 
-	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-	if (plla.rate_hz > 209000000)
-		pll_overclock = true;
-	if (pll_overclock)
-		;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
-	at91_pllb_usbfs_clock_init(main_clock);
-
-	//
-	 // MCK and CPU derive from one of those primary clocks.
-	 // For now, assume this parentage won't change.
-	 //
-	mckr = at91_sys_read(AT91_PMC_MCKR);
-	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
-	freq = mck.parent->rate_hz;
-	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				// prescale 
-	
-	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv 
-
-	// Register the PMC's standard clocks 
-	rt_list_init(&clocks);
-	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
-
-	rt_list_insert_after(&clocks, &pllb.node);
-	rt_list_insert_after(&clocks, &uhpck.node);
-	rt_list_insert_after(&clocks, &udpck.node);
-
-	// MCK and CPU clock are "always on" 
-	//clk_enable(&mck);
-
-	//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-	//	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-	//	(unsigned) main_clock / 1000000,
-	//	((unsigned) main_clock % 1000000) / 1000); //cause blocked
-
-	return 0;
+    unsigned tmp, freq, mckr;
+    int i;
+    int pll_overclock = false;
+
+    //
+    // When the bootloader initialized the main oscillator correctly,
+    // there's no problem using the cycle counter.  But if it didn't,
+    // or when using oscillator bypass mode, we must be told the speed
+     // of the main clock.
+    //
+    if (!main_clock) {
+        do {
+            tmp = at91_sys_read(AT91_CKGR_MCFR);
+        } while (!(tmp & AT91_PMC_MAINRDY));
+        main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+    }
+    main_clk.rate_hz = main_clock;
+
+    // report if PLLA is more than mildly overclocked
+    plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+    if (plla.rate_hz > 209000000)
+        pll_overclock = true;
+    if (pll_overclock)
+        ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+
+    at91_pllb_usbfs_clock_init(main_clock);
+
+    //
+     // MCK and CPU derive from one of those primary clocks.
+     // For now, assume this parentage won't change.
+     //
+    mckr = at91_sys_read(AT91_PMC_MCKR);
+    mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+    freq = mck.parent->rate_hz;
+    freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));               // prescale
+
+    mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv
+
+    // Register the PMC's standard clocks
+    rt_list_init(&clocks);
+    for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+        rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+    rt_list_insert_after(&clocks, &pllb.node);
+    rt_list_insert_after(&clocks, &uhpck.node);
+    rt_list_insert_after(&clocks, &udpck.node);
+
+    // MCK and CPU clock are "always on"
+    //clk_enable(&mck);
+
+    //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+    //  freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+    //  (unsigned) main_clock / 1000000,
+    //  ((unsigned) main_clock % 1000000) / 1000); //cause blocked
+
+    return 0;
 }
 */
 
@@ -298,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock)
 
 void rt_hw_clock_init(void)
 {
-	//at91_clock_init(18432000);
+    //at91_clock_init(18432000);
 }
 

bsp/asm9260t/platform/timer0.c

@@ -1,21 +1,7 @@
 /*
- * File      : timer0.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/platform/timer0.h

@@ -1,21 +1,7 @@
 /*
- * File      : timer0.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/asm9260t/platform/uart.c

@@ -1,27 +1,13 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 #include "asm9260t.h"
 #include "rtthread.h"
 #include "uart.h"

bsp/asm9260t/platform/uart.h

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -50,16 +36,16 @@ typedef struct
     volatile rt_uint32_t ISO7816STATUS[4];
 } HW_USART_TypeDef;
 
-#define USART0	((HW_USART_TypeDef *)UART0_BASE)
-#define USART1	((HW_USART_TypeDef *)UART1_BASE)
-#define USART2	((HW_USART_TypeDef *)UART2_BASE)
-#define USART3	((HW_USART_TypeDef *)UART3_BASE)
-#define USART4	((HW_USART_TypeDef *)UART4_BASE)
-#define USART5	((HW_USART_TypeDef *)UART5_BASE)
-#define USART6	((HW_USART_TypeDef *)UART6_BASE)
-#define USART7	((HW_USART_TypeDef *)UART7_BASE)
-#define USART8	((HW_USART_TypeDef *)UART8_BASE)
-#define USART9	((HW_USART_TypeDef *)UART9_BASE)
+#define USART0  ((HW_USART_TypeDef *)UART0_BASE)
+#define USART1  ((HW_USART_TypeDef *)UART1_BASE)
+#define USART2  ((HW_USART_TypeDef *)UART2_BASE)
+#define USART3  ((HW_USART_TypeDef *)UART3_BASE)
+#define USART4  ((HW_USART_TypeDef *)UART4_BASE)
+#define USART5  ((HW_USART_TypeDef *)UART5_BASE)
+#define USART6  ((HW_USART_TypeDef *)UART6_BASE)
+#define USART7  ((HW_USART_TypeDef *)UART7_BASE)
+#define USART8  ((HW_USART_TypeDef *)UART8_BASE)
+#define USART9  ((HW_USART_TypeDef *)UART9_BASE)
 
 
 #define ASM_UART_INTR_RXIS   (1UL << 4)
@@ -105,7 +91,7 @@ typedef struct
 extern void Hw_UartDisable(HW_USART_TypeDef* uartBase);
 extern void Hw_UartEnable(HW_USART_TypeDef* uartBase);
 extern void Hw_UartReset(HW_USART_TypeDef* uartBase);
-extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, 
+extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate,
                           int dataBits, int stopBits, int parity);
 extern void Hw_UartInit(int index);
 #endif

bsp/at91sam9260/applications/application.c

@@ -1,25 +1,11 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 /**
@@ -48,106 +34,106 @@ static int rt_led_app_init(void);
 
 int main(void)
 {
-	int timeout = 0;
+    int timeout = 0;
 
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
+    {
 #if defined(RT_USING_DFS_ROMFS)
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
+        if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+        {
+            rt_kprintf("ROM File System initialized!\n");
+        }
+        else
+            rt_kprintf("ROM File System initialzation failed!\n");
 #endif
 
 #if defined(RT_USING_DFS_UFFS)
-	{
-		/* mount flash device as flash directory */
-		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-	}
+    {
+        /* mount flash device as flash directory */
+        if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+            rt_kprintf("UFFS File System initialized!\n");
+        else
+            rt_kprintf("UFFS File System initialzation failed!\n");
+    }
 #endif
 
 #ifdef RT_USING_SDIO
-	timeout = 0;
-	while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
-	{
-		rt_thread_delay(1);
-	}
-
-	if (timeout < RT_TICK_PER_SECOND*2)
-	{
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
-	}
-	else
-	{
-		rt_kprintf("No SD card found.\n");
-	}
+    timeout = 0;
+    while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
+    {
+        rt_thread_delay(1);
+    }
+
+    if (timeout < RT_TICK_PER_SECOND*2)
+    {
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+        {
+            rt_kprintf("File System initialized!\n");
+        }
+        else
+            rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
+    }
+    else
+    {
+        rt_kprintf("No SD card found.\n");
+    }
 #endif
-	}
+    }
 #endif
-	
+
 #ifdef RT_USING_LED
-	rt_led_app_init();
+    rt_led_app_init();
 #endif
 }
 
 #ifdef RT_USING_LED
 void rt_led_thread_entry(void* parameter)
 {
-	rt_uint8_t cnt = 0;
-	led_init();
-	while(1)
-	{
-		/* light on leds for one second */
-		rt_thread_delay(40);
-		cnt++;
-		if (cnt&0x01)
-			led_on(1);
-		else
-			led_off(1);
-		if (cnt&0x02)
-			led_on(2);
-		else
-			led_off(2);
-		if (cnt&0x04)
-			led_on(3);
-		else
-			led_off(3);
-	}
+    rt_uint8_t cnt = 0;
+    led_init();
+    while(1)
+    {
+        /* light on leds for one second */
+        rt_thread_delay(40);
+        cnt++;
+        if (cnt&0x01)
+            led_on(1);
+        else
+            led_off(1);
+        if (cnt&0x02)
+            led_on(2);
+        else
+            led_off(2);
+        if (cnt&0x04)
+            led_on(3);
+        else
+            led_off(3);
+    }
 }
 #endif
 
 static int rt_led_app_init(void)
 {
 #ifdef RT_USING_LED
-	rt_thread_t led_thread;
+    rt_thread_t led_thread;
 
 #if (RT_THREAD_PRIORITY_MAX == 32)
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 20, 20);						
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 20, 20);
 #else
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 200, 20);					
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 200, 20);
 #endif
 
-	if(led_thread != RT_NULL)
-		rt_thread_startup(led_thread);
+    if(led_thread != RT_NULL)
+        rt_thread_startup(led_thread);
 #endif
 
-	return 0;
+    return 0;
 }
 
 /* NFSv3 Initialization */
@@ -155,14 +141,14 @@ static int rt_led_app_init(void)
 #include <dfs_nfs.h>
 void nfs_start(void)
 {
-	nfs_init();
-
-	if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-	{
-		rt_kprintf("NFSv3 File System initialized!\n");
-	}
-	else
-		rt_kprintf("NFSv3 File System initialzation failed!\n");
+    nfs_init();
+
+    if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
+    {
+        rt_kprintf("NFSv3 File System initialized!\n");
+    }
+    else
+        rt_kprintf("NFSv3 File System initialzation failed!\n");
 }
 
 #include "finsh.h"

bsp/at91sam9260/drivers/at91_i2c_gpio.c

@@ -1,25 +1,11 @@
 /*
- * File      : at91_i2c_gpio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2012-04-25     weety		first version
+ * Date           Author        Notes
+ * 2012-04-25     weety     first version
  */
 
 #include <rtdevice.h>
@@ -29,101 +15,101 @@
 
 static void at91_i2c_gpio_init()
 {
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
-	at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
-	at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
-	at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
-
-	at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
-
-	at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
+    at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
+    at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
+    at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
+
+    at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
+
+    at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
 }
 
 static void at91_set_sda(void *data, rt_int32_t state)
 {
-	if (state)
-	{
-		at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
-	}
-	else
-	{
-		at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
-	}
+    if (state)
+    {
+        at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
+    }
+    else
+    {
+        at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
+    }
 }
 
 static void at91_set_scl(void *data, rt_int32_t state)
 {
-	if (state)
-	{
-		at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
-	}
-	else
-	{
-		at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
-	}
+    if (state)
+    {
+        at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
+    }
+    else
+    {
+        at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
+    }
 }
 
 static rt_int32_t  at91_get_sda(void *data)
 {
-	return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
+    return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
 }
 
 static rt_int32_t  at91_get_scl(void *data)
 {
-	return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
+    return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
 }
 
 static void at91_udelay (rt_uint32_t us)
 {
-	rt_int32_t i;
-	for (; us > 0; us--)
-	{
-		i = 50000;
-		while(i > 0)
-		{
-			i--;
-		}
-	}
+    rt_int32_t i;
+    for (; us > 0; us--)
+    {
+        i = 50000;
+        while(i > 0)
+        {
+            i--;
+        }
+    }
 }
 
 static const struct rt_i2c_bit_ops bit_ops = {
-	RT_NULL,
-	at91_set_sda,
-	at91_set_scl,
-	at91_get_sda,
-	at91_get_scl,
-	
-	at91_udelay,
-
-	5,
-	100
+    RT_NULL,
+    at91_set_sda,
+    at91_set_scl,
+    at91_get_sda,
+    at91_get_scl,
+
+    at91_udelay,
+
+    5,
+    100
 };
 
 int at91_i2c_init(void)
 {
-	struct rt_i2c_bus_device *bus;
+    struct rt_i2c_bus_device *bus;
+
+    bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+    if (bus == RT_NULL)
+    {
+        rt_kprintf("rt_malloc failed\n");
+        return -RT_ENOMEM;
+    }
 
-	bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
-	if (bus == RT_NULL)
-	{
-		rt_kprintf("rt_malloc failed\n");
-		return -RT_ENOMEM;
-	}
-	
-	rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+    rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
 
-	bus->priv = (void *)&bit_ops;
+    bus->priv = (void *)&bit_ops;
 
-	at91_i2c_gpio_init();
+    at91_i2c_gpio_init();
 
-	rt_i2c_bit_add_bus(bus, "i2c0");
+    rt_i2c_bit_add_bus(bus, "i2c0");
 
-	return 0;
+    return 0;
 }
 
 INIT_DEVICE_EXPORT(at91_i2c_init);

bsp/at91sam9260/drivers/at91_mci.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_mci.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,99 +11,99 @@
 #ifndef __AT91_MCI_H__
 #define __AT91_MCI_H__
 
-#define AT91_MCI_CR		0x00		/* Control Register */
-#define		AT91_MCI_MCIEN		(1 <<  0)	/* Multi-Media Interface Enable */
-#define		AT91_MCI_MCIDIS		(1 <<  1)	/* Multi-Media Interface Disable */
-#define		AT91_MCI_PWSEN		(1 <<  2)	/* Power Save Mode Enable */
-#define		AT91_MCI_PWSDIS		(1 <<  3)	/* Power Save Mode Disable */
-#define		AT91_MCI_SWRST		(1 <<  7)	/* Software Reset */
+#define AT91_MCI_CR     0x00        /* Control Register */
+#define     AT91_MCI_MCIEN      (1 <<  0)   /* Multi-Media Interface Enable */
+#define     AT91_MCI_MCIDIS     (1 <<  1)   /* Multi-Media Interface Disable */
+#define     AT91_MCI_PWSEN      (1 <<  2)   /* Power Save Mode Enable */
+#define     AT91_MCI_PWSDIS     (1 <<  3)   /* Power Save Mode Disable */
+#define     AT91_MCI_SWRST      (1 <<  7)   /* Software Reset */
 
-#define AT91_MCI_MR		0x04		/* Mode Register */
-#define		AT91_MCI_CLKDIV		(0xff  <<  0)	/* Clock Divider */
-#define		AT91_MCI_PWSDIV		(7     <<  8)	/* Power Saving Divider */
-#define		AT91_MCI_RDPROOF	(1     << 11)	/* Read Proof Enable [SAM926[03] only] */
-#define		AT91_MCI_WRPROOF	(1     << 12)	/* Write Proof Enable [SAM926[03] only] */
-#define		AT91_MCI_PDCFBYTE	(1     << 13)	/* PDC Force Byte Transfer [SAM926[03] only] */
-#define		AT91_MCI_PDCPADV	(1     << 14)	/* PDC Padding Value */
-#define		AT91_MCI_PDCMODE	(1     << 15)	/* PDC-orientated Mode */
-#define		AT91_MCI_BLKLEN		(0xfff << 18)	/* Data Block Length */
+#define AT91_MCI_MR     0x04        /* Mode Register */
+#define     AT91_MCI_CLKDIV     (0xff  <<  0)   /* Clock Divider */
+#define     AT91_MCI_PWSDIV     (7     <<  8)   /* Power Saving Divider */
+#define     AT91_MCI_RDPROOF    (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define     AT91_MCI_WRPROOF    (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define     AT91_MCI_PDCFBYTE   (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
+#define     AT91_MCI_PDCPADV    (1     << 14)   /* PDC Padding Value */
+#define     AT91_MCI_PDCMODE    (1     << 15)   /* PDC-orientated Mode */
+#define     AT91_MCI_BLKLEN     (0xfff << 18)   /* Data Block Length */
 
-#define AT91_MCI_DTOR		0x08		/* Data Timeout Register */
-#define		AT91_MCI_DTOCYC		(0xf << 0)	/* Data Timeout Cycle Number */
-#define		AT91_MCI_DTOMUL		(7   << 4)	/* Data Timeout Multiplier */
-#define		AT91_MCI_DTOMUL_1		(0 <<  4)
-#define		AT91_MCI_DTOMUL_16		(1 <<  4)
-#define		AT91_MCI_DTOMUL_128		(2 <<  4)
-#define		AT91_MCI_DTOMUL_256		(3 <<  4)
-#define		AT91_MCI_DTOMUL_1K		(4 <<  4)
-#define		AT91_MCI_DTOMUL_4K		(5 <<  4)
-#define		AT91_MCI_DTOMUL_64K		(6 <<  4)
-#define		AT91_MCI_DTOMUL_1M		(7 <<  4)
+#define AT91_MCI_DTOR       0x08        /* Data Timeout Register */
+#define     AT91_MCI_DTOCYC     (0xf << 0)  /* Data Timeout Cycle Number */
+#define     AT91_MCI_DTOMUL     (7   << 4)  /* Data Timeout Multiplier */
+#define     AT91_MCI_DTOMUL_1       (0 <<  4)
+#define     AT91_MCI_DTOMUL_16      (1 <<  4)
+#define     AT91_MCI_DTOMUL_128     (2 <<  4)
+#define     AT91_MCI_DTOMUL_256     (3 <<  4)
+#define     AT91_MCI_DTOMUL_1K      (4 <<  4)
+#define     AT91_MCI_DTOMUL_4K      (5 <<  4)
+#define     AT91_MCI_DTOMUL_64K     (6 <<  4)
+#define     AT91_MCI_DTOMUL_1M      (7 <<  4)
 
-#define AT91_MCI_SDCR		0x0c		/* SD Card Register */
-#define		AT91_MCI_SDCSEL		(3 << 0)	/* SD Card Selector */
-#define		AT91_MCI_SDCBUS		(1 << 7)	/* 1-bit or 4-bit bus */
+#define AT91_MCI_SDCR       0x0c        /* SD Card Register */
+#define     AT91_MCI_SDCSEL     (3 << 0)    /* SD Card Selector */
+#define     AT91_MCI_SDCBUS     (1 << 7)    /* 1-bit or 4-bit bus */
 
-#define AT91_MCI_ARGR		0x10		/* Argument Register */
+#define AT91_MCI_ARGR       0x10        /* Argument Register */
 
-#define AT91_MCI_CMDR		0x14		/* Command Register */
-#define		AT91_MCI_CMDNB		(0x3f << 0)	/* Command Number */
-#define		AT91_MCI_RSPTYP		(3    << 6)	/* Response Type */
-#define			AT91_MCI_RSPTYP_NONE	(0 <<  6)
-#define			AT91_MCI_RSPTYP_48	(1 <<  6)
-#define			AT91_MCI_RSPTYP_136	(2 <<  6)
-#define		AT91_MCI_SPCMD		(7    << 8)	/* Special Command */
-#define			AT91_MCI_SPCMD_NONE	(0 <<  8)
-#define			AT91_MCI_SPCMD_INIT	(1 <<  8)
-#define			AT91_MCI_SPCMD_SYNC	(2 <<  8)
-#define			AT91_MCI_SPCMD_ICMD	(4 <<  8)
-#define			AT91_MCI_SPCMD_IRESP	(5 <<  8)
-#define		AT91_MCI_OPDCMD		(1 << 11)	/* Open Drain Command */
-#define		AT91_MCI_MAXLAT		(1 << 12)	/* Max Latency for Command to Response */
-#define		AT91_MCI_TRCMD		(3 << 16)	/* Transfer Command */
-#define			AT91_MCI_TRCMD_NONE	(0 << 16)
-#define			AT91_MCI_TRCMD_START	(1 << 16)
-#define			AT91_MCI_TRCMD_STOP	(2 << 16)
-#define		AT91_MCI_TRDIR		(1 << 18)	/* Transfer Direction */
-#define		AT91_MCI_TRTYP		(3 << 19)	/* Transfer Type */
-#define			AT91_MCI_TRTYP_BLOCK	(0 << 19)
-#define			AT91_MCI_TRTYP_MULTIPLE	(1 << 19)
-#define			AT91_MCI_TRTYP_STREAM	(2 << 19)
+#define AT91_MCI_CMDR       0x14        /* Command Register */
+#define     AT91_MCI_CMDNB      (0x3f << 0) /* Command Number */
+#define     AT91_MCI_RSPTYP     (3    << 6) /* Response Type */
+#define         AT91_MCI_RSPTYP_NONE    (0 <<  6)
+#define         AT91_MCI_RSPTYP_48  (1 <<  6)
+#define         AT91_MCI_RSPTYP_136 (2 <<  6)
+#define     AT91_MCI_SPCMD      (7    << 8) /* Special Command */
+#define         AT91_MCI_SPCMD_NONE (0 <<  8)
+#define         AT91_MCI_SPCMD_INIT (1 <<  8)
+#define         AT91_MCI_SPCMD_SYNC (2 <<  8)
+#define         AT91_MCI_SPCMD_ICMD (4 <<  8)
+#define         AT91_MCI_SPCMD_IRESP    (5 <<  8)
+#define     AT91_MCI_OPDCMD     (1 << 11)   /* Open Drain Command */
+#define     AT91_MCI_MAXLAT     (1 << 12)   /* Max Latency for Command to Response */
+#define     AT91_MCI_TRCMD      (3 << 16)   /* Transfer Command */
+#define         AT91_MCI_TRCMD_NONE (0 << 16)
+#define         AT91_MCI_TRCMD_START    (1 << 16)
+#define         AT91_MCI_TRCMD_STOP (2 << 16)
+#define     AT91_MCI_TRDIR      (1 << 18)   /* Transfer Direction */
+#define     AT91_MCI_TRTYP      (3 << 19)   /* Transfer Type */
+#define         AT91_MCI_TRTYP_BLOCK    (0 << 19)
+#define         AT91_MCI_TRTYP_MULTIPLE (1 << 19)
+#define         AT91_MCI_TRTYP_STREAM   (2 << 19)
 
-#define AT91_MCI_BLKR		0x18		/* Block Register */
-#define		AT91_MCI_BLKR_BCNT(n)	((0xffff & (n)) << 0)	/* Block count */
-#define		AT91_MCI_BLKR_BLKLEN(n)	((0xffff & (n)) << 16)	/* Block lenght */
+#define AT91_MCI_BLKR       0x18        /* Block Register */
+#define     AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
+#define     AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)  /* Block lenght */
 
-#define AT91_MCI_RSPR(n)	(0x20 + ((n) * 4))	/* Response Registers 0-3 */
-#define AT91_MCR_RDR		0x30		/* Receive Data Register */
-#define AT91_MCR_TDR		0x34		/* Transmit Data Register */
+#define AT91_MCI_RSPR(n)    (0x20 + ((n) * 4))  /* Response Registers 0-3 */
+#define AT91_MCR_RDR        0x30        /* Receive Data Register */
+#define AT91_MCR_TDR        0x34        /* Transmit Data Register */
 
-#define AT91_MCI_SR		0x40		/* Status Register */
-#define		AT91_MCI_CMDRDY		(1U <<  0)	/* Command Ready */
-#define		AT91_MCI_RXRDY		(1U <<  1)	/* Receiver Ready */
-#define		AT91_MCI_TXRDY		(1U <<  2)	/* Transmit Ready */
-#define		AT91_MCI_BLKE		(1U <<  3)	/* Data Block Ended */
-#define		AT91_MCI_DTIP		(1U <<  4)	/* Data Transfer in Progress */
-#define		AT91_MCI_NOTBUSY	(1U <<  5)	/* Data Not Busy */
-#define		AT91_MCI_ENDRX		(1U <<  6)	/* End of RX Buffer */
-#define		AT91_MCI_ENDTX		(1U <<  7)	/* End fo TX Buffer */
-#define		AT91_MCI_SDIOIRQA	(1U <<  8)	/* SDIO Interrupt for Slot A */
-#define		AT91_MCI_SDIOIRQB	(1U <<  9)	/* SDIO Interrupt for Slot B */
-#define		AT91_MCI_RXBUFF		(1U << 14)	/* RX Buffer Full */
-#define		AT91_MCI_TXBUFE		(1U << 15)	/* TX Buffer Empty */
-#define		AT91_MCI_RINDE		(1U << 16)	/* Response Index Error */
-#define		AT91_MCI_RDIRE		(1U << 17)	/* Response Direction Error */
-#define		AT91_MCI_RCRCE		(1U << 18)	/* Response CRC Error */
-#define		AT91_MCI_RENDE		(1U << 19)	/* Response End Bit Error */
-#define		AT91_MCI_RTOE		(1U << 20)	/* Reponse Time-out Error */
-#define		AT91_MCI_DCRCE		(1U << 21)	/* Data CRC Error */
-#define		AT91_MCI_DTOE		(1U << 22)	/* Data Time-out Error */
-#define		AT91_MCI_OVRE		(1U << 30)	/* Overrun */
-#define		AT91_MCI_UNRE		(1U << 31)	/* Underrun */
+#define AT91_MCI_SR     0x40        /* Status Register */
+#define     AT91_MCI_CMDRDY     (1U <<  0)  /* Command Ready */
+#define     AT91_MCI_RXRDY      (1U <<  1)  /* Receiver Ready */
+#define     AT91_MCI_TXRDY      (1U <<  2)  /* Transmit Ready */
+#define     AT91_MCI_BLKE       (1U <<  3)  /* Data Block Ended */
+#define     AT91_MCI_DTIP       (1U <<  4)  /* Data Transfer in Progress */
+#define     AT91_MCI_NOTBUSY    (1U <<  5)  /* Data Not Busy */
+#define     AT91_MCI_ENDRX      (1U <<  6)  /* End of RX Buffer */
+#define     AT91_MCI_ENDTX      (1U <<  7)  /* End fo TX Buffer */
+#define     AT91_MCI_SDIOIRQA   (1U <<  8)  /* SDIO Interrupt for Slot A */
+#define     AT91_MCI_SDIOIRQB   (1U <<  9)  /* SDIO Interrupt for Slot B */
+#define     AT91_MCI_RXBUFF     (1U << 14)  /* RX Buffer Full */
+#define     AT91_MCI_TXBUFE     (1U << 15)  /* TX Buffer Empty */
+#define     AT91_MCI_RINDE      (1U << 16)  /* Response Index Error */
+#define     AT91_MCI_RDIRE      (1U << 17)  /* Response Direction Error */
+#define     AT91_MCI_RCRCE      (1U << 18)  /* Response CRC Error */
+#define     AT91_MCI_RENDE      (1U << 19)  /* Response End Bit Error */
+#define     AT91_MCI_RTOE       (1U << 20)  /* Reponse Time-out Error */
+#define     AT91_MCI_DCRCE      (1U << 21)  /* Data CRC Error */
+#define     AT91_MCI_DTOE       (1U << 22)  /* Data Time-out Error */
+#define     AT91_MCI_OVRE       (1U << 30)  /* Overrun */
+#define     AT91_MCI_UNRE       (1U << 31)  /* Underrun */
 
-#define AT91_MCI_IER		0x44		/* Interrupt Enable Register */
-#define AT91_MCI_IDR		0x48		/* Interrupt Disable Register */
-#define AT91_MCI_IMR		0x4c		/* Interrupt Mask Register */
+#define AT91_MCI_IER        0x44        /* Interrupt Enable Register */
+#define AT91_MCI_IDR        0x48        /* Interrupt Disable Register */
+#define AT91_MCI_IMR        0x4c        /* Interrupt Mask Register */
 
 extern int at91_mci_init(void);
 

bsp/at91sam9260/drivers/board.c

@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -54,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 extern void rt_dbgu_isr(void);
 
 static struct mem_desc at91_mem_desc[] = {
-	{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
-	{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
-	{ 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
-	{ 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB },   /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
-	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }    /* 64M none-cached SDRAM memory */
+    { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
+    { 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
+    { 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
+    { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB },   /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
+    { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }    /* 64M none-cached SDRAM memory */
 };
 
 
-#define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
-#define PIT_PICNT(x)	(((x) & AT91_PIT_PICNT) >> 20)
+#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
+#define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
 
-static rt_uint32_t pit_cycle;		/* write-once */
-static rt_uint32_t pit_cnt;		/* access only w/system irq blocked */
+static rt_uint32_t pit_cycle;       /* write-once */
+static rt_uint32_t pit_cnt;     /* access only w/system irq blocked */
 
 /**
  * This function will handle rtos timer
  */
 void rt_timer_handler(int vector, void *param)
 {
-	#ifdef RT_USING_DBGU
-	if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
-	{
-		rt_dbgu_isr();
-	}
-	#endif
-	if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
-	{
-		unsigned nr_ticks;
-
-		/* Get number of ticks performed before irq, and ack it */
-		nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
-		rt_tick_increase();
-	}
+    #ifdef RT_USING_DBGU
+    if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
+    {
+        rt_dbgu_isr();
+    }
+    #endif
+    if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
+    {
+        unsigned nr_ticks;
+
+        /* Get number of ticks performed before irq, and ack it */
+        nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+        rt_tick_increase();
+    }
 }
 
 static void at91sam926x_pit_reset(void)
 {
-	/* Disable timer and irqs */
-	at91_sys_write(AT91_PIT_MR, 0);
-
-	/* Clear any pending interrupts, wait for PIT to stop counting */
-	while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
-		;
-
-	/* Start PIT but don't enable IRQ */
-	//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
-	pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
-	at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
-			| AT91_PIT_PITIEN);
-	rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
+    /* Disable timer and irqs */
+    at91_sys_write(AT91_PIT_MR, 0);
+
+    /* Clear any pending interrupts, wait for PIT to stop counting */
+    while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+        ;
+
+    /* Start PIT but don't enable IRQ */
+    //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+    pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+    at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+            | AT91_PIT_PITIEN);
+    rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
 }
 
 /*
@@ -111,19 +97,19 @@ static void at91sam926x_pit_reset(void)
  */
 static void at91sam926x_pit_init(void)
 {
-	rt_uint32_t	pit_rate;
-	rt_uint32_t	bits;
+    rt_uint32_t pit_rate;
+    rt_uint32_t bits;
 
-	/*
-	 * Use our actual MCK to figure out how many MCK/16 ticks per
-	 * 1/HZ period (instead of a compile-time constant LATCH).
-	 */
-	pit_rate = clk_get_rate(clk_get("mck")) / 16;
-	rt_kprintf("pit_rate=%dHZ\n", pit_rate);
-	pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
+    /*
+     * Use our actual MCK to figure out how many MCK/16 ticks per
+     * 1/HZ period (instead of a compile-time constant LATCH).
+     */
+    pit_rate = clk_get_rate(clk_get("mck")) / 16;
+    rt_kprintf("pit_rate=%dHZ\n", pit_rate);
+    pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
 
-	/* Initialize and enable the timer */
-	at91sam926x_pit_reset();
+    /* Initialize and enable the timer */
+    at91sam926x_pit_reset();
 
 }
 
@@ -132,69 +118,69 @@ static void at91sam926x_pit_init(void)
  */
  void rt_hw_timer_init()
  {
- 	at91sam926x_pit_init();
+    at91sam926x_pit_init();
 
-	/* install interrupt handler */
-	rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, 
-							RT_NULL, "system");
-	rt_hw_interrupt_umask(AT91_ID_SYS);
+    /* install interrupt handler */
+    rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
+                            RT_NULL, "system");
+    rt_hw_interrupt_umask(AT91_ID_SYS);
 
  }
- 
+
  void at91_tc1_init()
  {
- 	at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
- 	writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
- 	writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
- 	writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
- 	writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
+    at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
+    writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
+    writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
+    writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
+    writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
  }
 
-#define RXRDY			0x01
-#define TXRDY			(1 << 1)
-#define BPS			115200	/* serial baudrate */
+#define RXRDY           0x01
+#define TXRDY           (1 << 1)
+#define BPS         115200  /* serial baudrate */
 
 typedef struct uartport
 {
-	volatile rt_uint32_t CR;
-	volatile rt_uint32_t MR;
-	volatile rt_uint32_t IER;
-	volatile rt_uint32_t IDR;
-	volatile rt_uint32_t IMR;
-	volatile rt_uint32_t CSR;
-	volatile rt_uint32_t RHR;
-	volatile rt_uint32_t THR;
-	volatile rt_uint32_t BRGR;
-	volatile rt_uint32_t RTOR;
-	volatile rt_uint32_t TTGR;
-	volatile rt_uint32_t reserved0[5];
-	volatile rt_uint32_t FIDI;
-	volatile rt_uint32_t NER;
-	volatile rt_uint32_t reserved1;
-	volatile rt_uint32_t IFR;
-	volatile rt_uint32_t reserved2[44];
-	volatile rt_uint32_t RPR;
-	volatile rt_uint32_t RCR;
-	volatile rt_uint32_t TPR;
-	volatile rt_uint32_t TCR;
-	volatile rt_uint32_t RNPR;
-	volatile rt_uint32_t RNCR;
-	volatile rt_uint32_t TNPR;
-	volatile rt_uint32_t TNCR;
-	volatile rt_uint32_t PTCR;
-	volatile rt_uint32_t PTSR;
+    volatile rt_uint32_t CR;
+    volatile rt_uint32_t MR;
+    volatile rt_uint32_t IER;
+    volatile rt_uint32_t IDR;
+    volatile rt_uint32_t IMR;
+    volatile rt_uint32_t CSR;
+    volatile rt_uint32_t RHR;
+    volatile rt_uint32_t THR;
+    volatile rt_uint32_t BRGR;
+    volatile rt_uint32_t RTOR;
+    volatile rt_uint32_t TTGR;
+    volatile rt_uint32_t reserved0[5];
+    volatile rt_uint32_t FIDI;
+    volatile rt_uint32_t NER;
+    volatile rt_uint32_t reserved1;
+    volatile rt_uint32_t IFR;
+    volatile rt_uint32_t reserved2[44];
+    volatile rt_uint32_t RPR;
+    volatile rt_uint32_t RCR;
+    volatile rt_uint32_t TPR;
+    volatile rt_uint32_t TCR;
+    volatile rt_uint32_t RNPR;
+    volatile rt_uint32_t RNCR;
+    volatile rt_uint32_t TNPR;
+    volatile rt_uint32_t TNCR;
+    volatile rt_uint32_t PTCR;
+    volatile rt_uint32_t PTSR;
 }uartport;
 
 #define CIDR FIDI
 #define EXID NER
 #define FNR  reserved1
 
-#define DBGU	((struct uartport *)AT91SAM9260_BASE_DBGU)
+#define DBGU    ((struct uartport *)AT91SAM9260_BASE_DBGU)
 
 static void at91_usart_putc(char c)
 {
     while (!(DBGU->CSR & TXRDY));
-	DBGU->THR = c;
+    DBGU->THR = c;
 }
 
 /**
@@ -205,33 +191,33 @@ static void at91_usart_putc(char c)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
-		if (*str=='\n')
-		{
-			at91_usart_putc('\r');
-		}
-
-		at91_usart_putc(*str++);
-	}
+    while (*str)
+    {
+        if (*str=='\n')
+        {
+            at91_usart_putc('\r');
+        }
+
+        at91_usart_putc(*str++);
+    }
 }
 
 static void rt_hw_console_init(void)
 {
-	int div;
-	int mode = 0;
-
-	DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | 
-	       AT91_US_RXDIS | AT91_US_TXDIS;
-	mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | 
-		AT91_US_CHMODE_NORMAL;
-	mode |= AT91_US_CHRL_8;
-	mode |= AT91_US_NBSTOP_1;
-	mode |= AT91_US_PAR_NONE;
-	DBGU->MR = mode;
-	div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
-	DBGU->BRGR = div;
-	DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
+    int div;
+    int mode = 0;
+
+    DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
+           AT91_US_RXDIS | AT91_US_TXDIS;
+    mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
+        AT91_US_CHMODE_NORMAL;
+    mode |= AT91_US_CHRL_8;
+    mode |= AT91_US_NBSTOP_1;
+    mode |= AT91_US_PAR_NONE;
+    DBGU->MR = mode;
+    div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
+    DBGU->BRGR = div;
+    DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
 }
 
 
@@ -240,31 +226,31 @@ static void rt_hw_console_init(void)
  */
 void rt_hw_board_init()
 {
-	/* initialize the system clock */
-	rt_hw_clock_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
 
-	/* initialize console */
-	rt_hw_console_init();
+    /* initialize console */
+    rt_hw_console_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
+    /* initialize mmu */
+    rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
 
-	/* initialize hardware interrupt */
-	rt_hw_interrupt_init();
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize early device */
+    /* initialize early device */
 #ifdef RT_USING_COMPONENTS_INIT
-	rt_components_board_init();
+    rt_components_board_init();
 #endif
 #ifdef RT_USING_CONSOLE
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-	/* initialize timer0 */
-	rt_hw_timer_init();
+    /* initialize timer0 */
+    rt_hw_timer_init();
 
 /* initialize board */
 #ifdef RT_USING_HEAP
-	rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 
 }

bsp/at91sam9260/drivers/board.h

@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at91sam9260/drivers/led.c

@@ -1,21 +1,7 @@
 /*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,59 +14,59 @@
 
 #if 1
 // GB9260 board
-#define PIO_LED		AT91_PIOB
-#define LED1		(1 << 25)	// LED_SYS
-#define LED2		(0)
-#define LED3		(1 << 23)	// LED_USR
-#define LED_ALL		(LED1 | LED2 | LED3)
+#define PIO_LED     AT91_PIOB
+#define LED1        (1 << 25)   // LED_SYS
+#define LED2        (0)
+#define LED3        (1 << 23)   // LED_USR
+#define LED_ALL     (LED1 | LED2 | LED3)
 #else
-#define PIO_LED		AT91_PIOC
-#define LED1		(1 << 8)
-#define LED2		(1 << 11)
-#define LED3		(1 << 6)
-#define LED_ALL		(LED1 | LED2 | LED3)
+#define PIO_LED     AT91_PIOC
+#define LED1        (1 << 8)
+#define LED2        (1 << 11)
+#define LED3        (1 << 6)
+#define LED_ALL     (LED1 | LED2 | LED3)
 #endif
 
 void led_init(void)
 {
-	at91_sys_write(PIO_LED+0x00, LED_ALL);
-	at91_sys_write(PIO_LED+0x10, LED_ALL);
-	at91_sys_write(PIO_LED+0x64, LED_ALL);
-	at91_sys_write(PIO_LED+0x30, LED_ALL);
+    at91_sys_write(PIO_LED+0x00, LED_ALL);
+    at91_sys_write(PIO_LED+0x10, LED_ALL);
+    at91_sys_write(PIO_LED+0x64, LED_ALL);
+    at91_sys_write(PIO_LED+0x30, LED_ALL);
 }
 
 void led_on(int num)
 {
-	switch(num)
-	{
-		case 1:
-			at91_sys_write(PIO_LED+0x34, LED1);
-			break;
-		case 2:
-			at91_sys_write(PIO_LED+0x34, LED2);
-			break;
-		case 3:
-			at91_sys_write(PIO_LED+0x34, LED3);
-			break;
-		default:
-			break;
-	}
+    switch(num)
+    {
+        case 1:
+            at91_sys_write(PIO_LED+0x34, LED1);
+            break;
+        case 2:
+            at91_sys_write(PIO_LED+0x34, LED2);
+            break;
+        case 3:
+            at91_sys_write(PIO_LED+0x34, LED3);
+            break;
+        default:
+            break;
+    }
 }
 
 void led_off(int num)
 {
-	switch(num)
-	{
-		case 1:
-			at91_sys_write(PIO_LED+0x30, LED1);
-			break;
-		case 2:
-			at91_sys_write(PIO_LED+0x30, LED2);
-			break;
-		case 3:
-			at91_sys_write(PIO_LED+0x30, LED3);
-			break;
-		default:
-			break;
-	}
+    switch(num)
+    {
+        case 1:
+            at91_sys_write(PIO_LED+0x30, LED1);
+            break;
+        case 2:
+            at91_sys_write(PIO_LED+0x30, LED2);
+            break;
+        case 3:
+            at91_sys_write(PIO_LED+0x30, LED3);
+            break;
+        default:
+            break;
+    }
 }

bsp/at91sam9260/drivers/led.h

@@ -1,21 +1,7 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at91sam9260/drivers/macb.h

@@ -1,21 +1,7 @@
 /*
- * File      : macb.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,319 +12,319 @@
 #include <mii.h>
 
 /* MACB register offsets */
-#define MACB_NCR				0x0000
-#define MACB_NCFGR				0x0004
-#define MACB_NSR				0x0008
-#define MACB_TSR				0x0014
-#define MACB_RBQP				0x0018
-#define MACB_TBQP				0x001c
-#define MACB_RSR				0x0020
-#define MACB_ISR				0x0024
-#define MACB_IER				0x0028
-#define MACB_IDR				0x002c
-#define MACB_IMR				0x0030
-#define MACB_MAN				0x0034
-#define MACB_PTR				0x0038
-#define MACB_PFR				0x003c
-#define MACB_FTO				0x0040
-#define MACB_SCF				0x0044
-#define MACB_MCF				0x0048
-#define MACB_FRO				0x004c
-#define MACB_FCSE				0x0050
-#define MACB_ALE				0x0054
-#define MACB_DTF				0x0058
-#define MACB_LCOL				0x005c
-#define MACB_EXCOL				0x0060
-#define MACB_TUND				0x0064
-#define MACB_CSE				0x0068
-#define MACB_RRE				0x006c
-#define MACB_ROVR				0x0070
-#define MACB_RSE				0x0074
-#define MACB_ELE				0x0078
-#define MACB_RJA				0x007c
-#define MACB_USF				0x0080
-#define MACB_STE				0x0084
-#define MACB_RLE				0x0088
-#define MACB_TPF				0x008c
-#define MACB_HRB				0x0090
-#define MACB_HRT				0x0094
-#define MACB_SA1B				0x0098
-#define MACB_SA1T				0x009c
-#define MACB_SA2B				0x00a0
-#define MACB_SA2T				0x00a4
-#define MACB_SA3B				0x00a8
-#define MACB_SA3T				0x00ac
-#define MACB_SA4B				0x00b0
-#define MACB_SA4T				0x00b4
-#define MACB_TID				0x00b8
-#define MACB_TPQ				0x00bc
-#define MACB_USRIO				0x00c0
-#define MACB_WOL				0x00c4
+#define MACB_NCR                0x0000
+#define MACB_NCFGR              0x0004
+#define MACB_NSR                0x0008
+#define MACB_TSR                0x0014
+#define MACB_RBQP               0x0018
+#define MACB_TBQP               0x001c
+#define MACB_RSR                0x0020
+#define MACB_ISR                0x0024
+#define MACB_IER                0x0028
+#define MACB_IDR                0x002c
+#define MACB_IMR                0x0030
+#define MACB_MAN                0x0034
+#define MACB_PTR                0x0038
+#define MACB_PFR                0x003c
+#define MACB_FTO                0x0040
+#define MACB_SCF                0x0044
+#define MACB_MCF                0x0048
+#define MACB_FRO                0x004c
+#define MACB_FCSE               0x0050
+#define MACB_ALE                0x0054
+#define MACB_DTF                0x0058
+#define MACB_LCOL               0x005c
+#define MACB_EXCOL              0x0060
+#define MACB_TUND               0x0064
+#define MACB_CSE                0x0068
+#define MACB_RRE                0x006c
+#define MACB_ROVR               0x0070
+#define MACB_RSE                0x0074
+#define MACB_ELE                0x0078
+#define MACB_RJA                0x007c
+#define MACB_USF                0x0080
+#define MACB_STE                0x0084
+#define MACB_RLE                0x0088
+#define MACB_TPF                0x008c
+#define MACB_HRB                0x0090
+#define MACB_HRT                0x0094
+#define MACB_SA1B               0x0098
+#define MACB_SA1T               0x009c
+#define MACB_SA2B               0x00a0
+#define MACB_SA2T               0x00a4
+#define MACB_SA3B               0x00a8
+#define MACB_SA3T               0x00ac
+#define MACB_SA4B               0x00b0
+#define MACB_SA4T               0x00b4
+#define MACB_TID                0x00b8
+#define MACB_TPQ                0x00bc
+#define MACB_USRIO              0x00c0
+#define MACB_WOL                0x00c4
 
 /* Bitfields in NCR */
-#define MACB_LB_OFFSET				0
-#define MACB_LB_SIZE				1
-#define MACB_LLB_OFFSET				1
-#define MACB_LLB_SIZE				1
-#define MACB_RE_OFFSET				2
-#define MACB_RE_SIZE				1
-#define MACB_TE_OFFSET				3
-#define MACB_TE_SIZE				1
-#define MACB_MPE_OFFSET				4
-#define MACB_MPE_SIZE				1
-#define MACB_CLRSTAT_OFFSET			5
-#define MACB_CLRSTAT_SIZE			1
-#define MACB_INCSTAT_OFFSET			6
-#define MACB_INCSTAT_SIZE			1
-#define MACB_WESTAT_OFFSET			7
-#define MACB_WESTAT_SIZE			1
-#define MACB_BP_OFFSET				8
-#define MACB_BP_SIZE				1
-#define MACB_TSTART_OFFSET			9
-#define MACB_TSTART_SIZE			1
-#define MACB_THALT_OFFSET			10
-#define MACB_THALT_SIZE				1
-#define MACB_NCR_TPF_OFFSET			11
-#define MACB_NCR_TPF_SIZE			1
-#define MACB_TZQ_OFFSET				12
-#define MACB_TZQ_SIZE				1
+#define MACB_LB_OFFSET              0
+#define MACB_LB_SIZE                1
+#define MACB_LLB_OFFSET             1
+#define MACB_LLB_SIZE               1
+#define MACB_RE_OFFSET              2
+#define MACB_RE_SIZE                1
+#define MACB_TE_OFFSET              3
+#define MACB_TE_SIZE                1
+#define MACB_MPE_OFFSET             4
+#define MACB_MPE_SIZE               1
+#define MACB_CLRSTAT_OFFSET         5
+#define MACB_CLRSTAT_SIZE           1
+#define MACB_INCSTAT_OFFSET         6
+#define MACB_INCSTAT_SIZE           1
+#define MACB_WESTAT_OFFSET          7
+#define MACB_WESTAT_SIZE            1
+#define MACB_BP_OFFSET              8
+#define MACB_BP_SIZE                1
+#define MACB_TSTART_OFFSET          9
+#define MACB_TSTART_SIZE            1
+#define MACB_THALT_OFFSET           10
+#define MACB_THALT_SIZE             1
+#define MACB_NCR_TPF_OFFSET         11
+#define MACB_NCR_TPF_SIZE           1
+#define MACB_TZQ_OFFSET             12
+#define MACB_TZQ_SIZE               1
 
 /* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET				0
-#define MACB_SPD_SIZE				1
-#define MACB_FD_OFFSET				1
-#define MACB_FD_SIZE				1
-#define MACB_BIT_RATE_OFFSET			2
-#define MACB_BIT_RATE_SIZE			1
-#define MACB_JFRAME_OFFSET			3
-#define MACB_JFRAME_SIZE			1
-#define MACB_CAF_OFFSET				4
-#define MACB_CAF_SIZE				1
-#define MACB_NBC_OFFSET				5
-#define MACB_NBC_SIZE				1
-#define MACB_NCFGR_MTI_OFFSET			6
-#define MACB_NCFGR_MTI_SIZE			1
-#define MACB_UNI_OFFSET				7
-#define MACB_UNI_SIZE				1
-#define MACB_BIG_OFFSET				8
-#define MACB_BIG_SIZE				1
-#define MACB_EAE_OFFSET				9
-#define MACB_EAE_SIZE				1
-#define MACB_CLK_OFFSET				10
-#define MACB_CLK_SIZE				2
-#define MACB_RTY_OFFSET				12
-#define MACB_RTY_SIZE				1
-#define MACB_PAE_OFFSET				13
-#define MACB_PAE_SIZE				1
-#define MACB_RBOF_OFFSET			14
-#define MACB_RBOF_SIZE				2
-#define MACB_RLCE_OFFSET			16
-#define MACB_RLCE_SIZE				1
-#define MACB_DRFCS_OFFSET			17
-#define MACB_DRFCS_SIZE				1
-#define MACB_EFRHD_OFFSET			18
-#define MACB_EFRHD_SIZE				1
-#define MACB_IRXFCS_OFFSET			19
-#define MACB_IRXFCS_SIZE			1
+#define MACB_SPD_OFFSET             0
+#define MACB_SPD_SIZE               1
+#define MACB_FD_OFFSET              1
+#define MACB_FD_SIZE                1
+#define MACB_BIT_RATE_OFFSET            2
+#define MACB_BIT_RATE_SIZE          1
+#define MACB_JFRAME_OFFSET          3
+#define MACB_JFRAME_SIZE            1
+#define MACB_CAF_OFFSET             4
+#define MACB_CAF_SIZE               1
+#define MACB_NBC_OFFSET             5
+#define MACB_NBC_SIZE               1
+#define MACB_NCFGR_MTI_OFFSET           6
+#define MACB_NCFGR_MTI_SIZE         1
+#define MACB_UNI_OFFSET             7
+#define MACB_UNI_SIZE               1
+#define MACB_BIG_OFFSET             8
+#define MACB_BIG_SIZE               1
+#define MACB_EAE_OFFSET             9
+#define MACB_EAE_SIZE               1
+#define MACB_CLK_OFFSET             10
+#define MACB_CLK_SIZE               2
+#define MACB_RTY_OFFSET             12
+#define MACB_RTY_SIZE               1
+#define MACB_PAE_OFFSET             13
+#define MACB_PAE_SIZE               1
+#define MACB_RBOF_OFFSET            14
+#define MACB_RBOF_SIZE              2
+#define MACB_RLCE_OFFSET            16
+#define MACB_RLCE_SIZE              1
+#define MACB_DRFCS_OFFSET           17
+#define MACB_DRFCS_SIZE             1
+#define MACB_EFRHD_OFFSET           18
+#define MACB_EFRHD_SIZE             1
+#define MACB_IRXFCS_OFFSET          19
+#define MACB_IRXFCS_SIZE            1
 
 /* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET			0
-#define MACB_NSR_LINK_SIZE			1
-#define MACB_MDIO_OFFSET			1
-#define MACB_MDIO_SIZE				1
-#define MACB_IDLE_OFFSET			2
-#define MACB_IDLE_SIZE				1
+#define MACB_NSR_LINK_OFFSET            0
+#define MACB_NSR_LINK_SIZE          1
+#define MACB_MDIO_OFFSET            1
+#define MACB_MDIO_SIZE              1
+#define MACB_IDLE_OFFSET            2
+#define MACB_IDLE_SIZE              1
 
 /* Bitfields in TSR */
-#define MACB_UBR_OFFSET				0
-#define MACB_UBR_SIZE				1
-#define MACB_COL_OFFSET				1
-#define MACB_COL_SIZE				1
-#define MACB_TSR_RLE_OFFSET			2
-#define MACB_TSR_RLE_SIZE			1
-#define MACB_TGO_OFFSET				3
-#define MACB_TGO_SIZE				1
-#define MACB_BEX_OFFSET				4
-#define MACB_BEX_SIZE				1
-#define MACB_COMP_OFFSET			5
-#define MACB_COMP_SIZE				1
-#define MACB_UND_OFFSET				6
-#define MACB_UND_SIZE				1
+#define MACB_UBR_OFFSET             0
+#define MACB_UBR_SIZE               1
+#define MACB_COL_OFFSET             1
+#define MACB_COL_SIZE               1
+#define MACB_TSR_RLE_OFFSET         2
+#define MACB_TSR_RLE_SIZE           1
+#define MACB_TGO_OFFSET             3
+#define MACB_TGO_SIZE               1
+#define MACB_BEX_OFFSET             4
+#define MACB_BEX_SIZE               1
+#define MACB_COMP_OFFSET            5
+#define MACB_COMP_SIZE              1
+#define MACB_UND_OFFSET             6
+#define MACB_UND_SIZE               1
 
 /* Bitfields in RSR */
-#define MACB_BNA_OFFSET				0
-#define MACB_BNA_SIZE				1
-#define MACB_REC_OFFSET				1
-#define MACB_REC_SIZE				1
-#define MACB_OVR_OFFSET				2
-#define MACB_OVR_SIZE				1
+#define MACB_BNA_OFFSET             0
+#define MACB_BNA_SIZE               1
+#define MACB_REC_OFFSET             1
+#define MACB_REC_SIZE               1
+#define MACB_OVR_OFFSET             2
+#define MACB_OVR_SIZE               1
 
 /* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET				0
-#define MACB_MFD_SIZE				1
-#define MACB_RCOMP_OFFSET			1
-#define MACB_RCOMP_SIZE				1
-#define MACB_RXUBR_OFFSET			2
-#define MACB_RXUBR_SIZE				1
-#define MACB_TXUBR_OFFSET			3
-#define MACB_TXUBR_SIZE				1
-#define MACB_ISR_TUND_OFFSET			4
-#define MACB_ISR_TUND_SIZE			1
-#define MACB_ISR_RLE_OFFSET			5
-#define MACB_ISR_RLE_SIZE			1
-#define MACB_TXERR_OFFSET			6
-#define MACB_TXERR_SIZE				1
-#define MACB_TCOMP_OFFSET			7
-#define MACB_TCOMP_SIZE				1
-#define MACB_ISR_LINK_OFFSET			9
-#define MACB_ISR_LINK_SIZE			1
-#define MACB_ISR_ROVR_OFFSET			10
-#define MACB_ISR_ROVR_SIZE			1
-#define MACB_HRESP_OFFSET			11
-#define MACB_HRESP_SIZE				1
-#define MACB_PFR_OFFSET				12
-#define MACB_PFR_SIZE				1
-#define MACB_PTZ_OFFSET				13
-#define MACB_PTZ_SIZE				1
+#define MACB_MFD_OFFSET             0
+#define MACB_MFD_SIZE               1
+#define MACB_RCOMP_OFFSET           1
+#define MACB_RCOMP_SIZE             1
+#define MACB_RXUBR_OFFSET           2
+#define MACB_RXUBR_SIZE             1
+#define MACB_TXUBR_OFFSET           3
+#define MACB_TXUBR_SIZE             1
+#define MACB_ISR_TUND_OFFSET            4
+#define MACB_ISR_TUND_SIZE          1
+#define MACB_ISR_RLE_OFFSET         5
+#define MACB_ISR_RLE_SIZE           1
+#define MACB_TXERR_OFFSET           6
+#define MACB_TXERR_SIZE             1
+#define MACB_TCOMP_OFFSET           7
+#define MACB_TCOMP_SIZE             1
+#define MACB_ISR_LINK_OFFSET            9
+#define MACB_ISR_LINK_SIZE          1
+#define MACB_ISR_ROVR_OFFSET            10
+#define MACB_ISR_ROVR_SIZE          1
+#define MACB_HRESP_OFFSET           11
+#define MACB_HRESP_SIZE             1
+#define MACB_PFR_OFFSET             12
+#define MACB_PFR_SIZE               1
+#define MACB_PTZ_OFFSET             13
+#define MACB_PTZ_SIZE               1
 
 /* Bitfields in MAN */
-#define MACB_DATA_OFFSET			0
-#define MACB_DATA_SIZE				16
-#define MACB_CODE_OFFSET			16
-#define MACB_CODE_SIZE				2
-#define MACB_REGA_OFFSET			18
-#define MACB_REGA_SIZE				5
-#define MACB_PHYA_OFFSET			23
-#define MACB_PHYA_SIZE				5
-#define MACB_RW_OFFSET				28
-#define MACB_RW_SIZE				2
-#define MACB_SOF_OFFSET				30
-#define MACB_SOF_SIZE				2
+#define MACB_DATA_OFFSET            0
+#define MACB_DATA_SIZE              16
+#define MACB_CODE_OFFSET            16
+#define MACB_CODE_SIZE              2
+#define MACB_REGA_OFFSET            18
+#define MACB_REGA_SIZE              5
+#define MACB_PHYA_OFFSET            23
+#define MACB_PHYA_SIZE              5
+#define MACB_RW_OFFSET              28
+#define MACB_RW_SIZE                2
+#define MACB_SOF_OFFSET             30
+#define MACB_SOF_SIZE               2
 
 /* Bitfields in USRIO (AVR32) */
-#define MACB_MII_OFFSET				0
-#define MACB_MII_SIZE				1
-#define MACB_EAM_OFFSET				1
-#define MACB_EAM_SIZE				1
-#define MACB_TX_PAUSE_OFFSET			2
-#define MACB_TX_PAUSE_SIZE			1
-#define MACB_TX_PAUSE_ZERO_OFFSET		3
-#define MACB_TX_PAUSE_ZERO_SIZE			1
+#define MACB_MII_OFFSET             0
+#define MACB_MII_SIZE               1
+#define MACB_EAM_OFFSET             1
+#define MACB_EAM_SIZE               1
+#define MACB_TX_PAUSE_OFFSET            2
+#define MACB_TX_PAUSE_SIZE          1
+#define MACB_TX_PAUSE_ZERO_OFFSET       3
+#define MACB_TX_PAUSE_ZERO_SIZE         1
 
 /* Bitfields in USRIO (AT91) */
-#define MACB_RMII_OFFSET			0
-#define MACB_RMII_SIZE				1
-#define MACB_CLKEN_OFFSET			1
-#define MACB_CLKEN_SIZE				1
+#define MACB_RMII_OFFSET            0
+#define MACB_RMII_SIZE              1
+#define MACB_CLKEN_OFFSET           1
+#define MACB_CLKEN_SIZE             1
 
 /* Bitfields in WOL */
-#define MACB_IP_OFFSET				0
-#define MACB_IP_SIZE				16
-#define MACB_MAG_OFFSET				16
-#define MACB_MAG_SIZE				1
-#define MACB_ARP_OFFSET				17
-#define MACB_ARP_SIZE				1
-#define MACB_SA1_OFFSET				18
-#define MACB_SA1_SIZE				1
-#define MACB_WOL_MTI_OFFSET			19
-#define MACB_WOL_MTI_SIZE			1
+#define MACB_IP_OFFSET              0
+#define MACB_IP_SIZE                16
+#define MACB_MAG_OFFSET             16
+#define MACB_MAG_SIZE               1
+#define MACB_ARP_OFFSET             17
+#define MACB_ARP_SIZE               1
+#define MACB_SA1_OFFSET             18
+#define MACB_SA1_SIZE               1
+#define MACB_WOL_MTI_OFFSET         19
+#define MACB_WOL_MTI_SIZE           1
 
 /* Constants for CLK */
-#define MACB_CLK_DIV8				0
-#define MACB_CLK_DIV16				1
-#define MACB_CLK_DIV32				2
-#define MACB_CLK_DIV64				3
+#define MACB_CLK_DIV8               0
+#define MACB_CLK_DIV16              1
+#define MACB_CLK_DIV32              2
+#define MACB_CLK_DIV64              3
 
 /* Constants for MAN register */
-#define MACB_MAN_SOF				1
-#define MACB_MAN_WRITE				1
-#define MACB_MAN_READ				2
-#define MACB_MAN_CODE				2
+#define MACB_MAN_SOF                1
+#define MACB_MAN_WRITE              1
+#define MACB_MAN_READ               2
+#define MACB_MAN_CODE               2
 
 /* Bit manipulation macros */
-#define MACB_BIT(name)					\
-	(1 << MACB_##name##_OFFSET)
-#define MACB_BF(name,value)				\
-	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
-	 << MACB_##name##_OFFSET)
+#define MACB_BIT(name)                  \
+    (1 << MACB_##name##_OFFSET)
+#define MACB_BF(name,value)             \
+    (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
+     << MACB_##name##_OFFSET)
 #define MACB_BFEXT(name,value)\
-	(((value) >> MACB_##name##_OFFSET)		\
-	 & ((1 << MACB_##name##_SIZE) - 1))
-#define MACB_BFINS(name,value,old)			\
-	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
-		    << MACB_##name##_OFFSET))		\
-	 | MACB_BF(name,value))
+    (((value) >> MACB_##name##_OFFSET)      \
+     & ((1 << MACB_##name##_SIZE) - 1))
+#define MACB_BFINS(name,value,old)          \
+    (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
+            << MACB_##name##_OFFSET))       \
+     | MACB_BF(name,value))
 
 /* Register access macros */
-#define macb_readl(port,reg)				\
-	readl((port)->regs + MACB_##reg)
-#define macb_writel(port,reg,value)			\
-	writel((value), (port)->regs + MACB_##reg)
+#define macb_readl(port,reg)                \
+    readl((port)->regs + MACB_##reg)
+#define macb_writel(port,reg,value)         \
+    writel((value), (port)->regs + MACB_##reg)
 
 struct dma_desc {
-	rt_uint32_t	addr;
-	rt_uint32_t	ctrl;
+    rt_uint32_t addr;
+    rt_uint32_t ctrl;
 };
 
 /* DMA descriptor bitfields */
-#define MACB_RX_USED_OFFSET			0
-#define MACB_RX_USED_SIZE			1
-#define MACB_RX_WRAP_OFFSET			1
-#define MACB_RX_WRAP_SIZE			1
-#define MACB_RX_WADDR_OFFSET			2
-#define MACB_RX_WADDR_SIZE			30
+#define MACB_RX_USED_OFFSET         0
+#define MACB_RX_USED_SIZE           1
+#define MACB_RX_WRAP_OFFSET         1
+#define MACB_RX_WRAP_SIZE           1
+#define MACB_RX_WADDR_OFFSET            2
+#define MACB_RX_WADDR_SIZE          30
 
-#define MACB_RX_FRMLEN_OFFSET			0
-#define MACB_RX_FRMLEN_SIZE			12
-#define MACB_RX_OFFSET_OFFSET			12
-#define MACB_RX_OFFSET_SIZE			2
-#define MACB_RX_SOF_OFFSET			14
-#define MACB_RX_SOF_SIZE			1
-#define MACB_RX_EOF_OFFSET			15
-#define MACB_RX_EOF_SIZE			1
-#define MACB_RX_CFI_OFFSET			16
-#define MACB_RX_CFI_SIZE			1
-#define MACB_RX_VLAN_PRI_OFFSET			17
-#define MACB_RX_VLAN_PRI_SIZE			3
-#define MACB_RX_PRI_TAG_OFFSET			20
-#define MACB_RX_PRI_TAG_SIZE			1
-#define MACB_RX_VLAN_TAG_OFFSET			21
-#define MACB_RX_VLAN_TAG_SIZE			1
-#define MACB_RX_TYPEID_MATCH_OFFSET		22
-#define MACB_RX_TYPEID_MATCH_SIZE		1
-#define MACB_RX_SA4_MATCH_OFFSET		23
-#define MACB_RX_SA4_MATCH_SIZE			1
-#define MACB_RX_SA3_MATCH_OFFSET		24
-#define MACB_RX_SA3_MATCH_SIZE			1
-#define MACB_RX_SA2_MATCH_OFFSET		25
-#define MACB_RX_SA2_MATCH_SIZE			1
-#define MACB_RX_SA1_MATCH_OFFSET		26
-#define MACB_RX_SA1_MATCH_SIZE			1
-#define MACB_RX_EXT_MATCH_OFFSET		28
-#define MACB_RX_EXT_MATCH_SIZE			1
-#define MACB_RX_UHASH_MATCH_OFFSET		29
-#define MACB_RX_UHASH_MATCH_SIZE		1
-#define MACB_RX_MHASH_MATCH_OFFSET		30
-#define MACB_RX_MHASH_MATCH_SIZE		1
-#define MACB_RX_BROADCAST_OFFSET		31
-#define MACB_RX_BROADCAST_SIZE			1
+#define MACB_RX_FRMLEN_OFFSET           0
+#define MACB_RX_FRMLEN_SIZE         12
+#define MACB_RX_OFFSET_OFFSET           12
+#define MACB_RX_OFFSET_SIZE         2
+#define MACB_RX_SOF_OFFSET          14
+#define MACB_RX_SOF_SIZE            1
+#define MACB_RX_EOF_OFFSET          15
+#define MACB_RX_EOF_SIZE            1
+#define MACB_RX_CFI_OFFSET          16
+#define MACB_RX_CFI_SIZE            1
+#define MACB_RX_VLAN_PRI_OFFSET         17
+#define MACB_RX_VLAN_PRI_SIZE           3
+#define MACB_RX_PRI_TAG_OFFSET          20
+#define MACB_RX_PRI_TAG_SIZE            1
+#define MACB_RX_VLAN_TAG_OFFSET         21
+#define MACB_RX_VLAN_TAG_SIZE           1
+#define MACB_RX_TYPEID_MATCH_OFFSET     22
+#define MACB_RX_TYPEID_MATCH_SIZE       1
+#define MACB_RX_SA4_MATCH_OFFSET        23
+#define MACB_RX_SA4_MATCH_SIZE          1
+#define MACB_RX_SA3_MATCH_OFFSET        24
+#define MACB_RX_SA3_MATCH_SIZE          1
+#define MACB_RX_SA2_MATCH_OFFSET        25
+#define MACB_RX_SA2_MATCH_SIZE          1
+#define MACB_RX_SA1_MATCH_OFFSET        26
+#define MACB_RX_SA1_MATCH_SIZE          1
+#define MACB_RX_EXT_MATCH_OFFSET        28
+#define MACB_RX_EXT_MATCH_SIZE          1
+#define MACB_RX_UHASH_MATCH_OFFSET      29
+#define MACB_RX_UHASH_MATCH_SIZE        1
+#define MACB_RX_MHASH_MATCH_OFFSET      30
+#define MACB_RX_MHASH_MATCH_SIZE        1
+#define MACB_RX_BROADCAST_OFFSET        31
+#define MACB_RX_BROADCAST_SIZE          1
 
-#define MACB_TX_FRMLEN_OFFSET			0
-#define MACB_TX_FRMLEN_SIZE			11
-#define MACB_TX_LAST_OFFSET			15
-#define MACB_TX_LAST_SIZE			1
-#define MACB_TX_NOCRC_OFFSET			16
-#define MACB_TX_NOCRC_SIZE			1
-#define MACB_TX_BUF_EXHAUSTED_OFFSET		27
-#define MACB_TX_BUF_EXHAUSTED_SIZE		1
-#define MACB_TX_UNDERRUN_OFFSET			28
-#define MACB_TX_UNDERRUN_SIZE			1
-#define MACB_TX_ERROR_OFFSET			29
-#define MACB_TX_ERROR_SIZE			1
-#define MACB_TX_WRAP_OFFSET			30
-#define MACB_TX_WRAP_SIZE			1
-#define MACB_TX_USED_OFFSET			31
-#define MACB_TX_USED_SIZE			1
+#define MACB_TX_FRMLEN_OFFSET           0
+#define MACB_TX_FRMLEN_SIZE         11
+#define MACB_TX_LAST_OFFSET         15
+#define MACB_TX_LAST_SIZE           1
+#define MACB_TX_NOCRC_OFFSET            16
+#define MACB_TX_NOCRC_SIZE          1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET        27
+#define MACB_TX_BUF_EXHAUSTED_SIZE      1
+#define MACB_TX_UNDERRUN_OFFSET         28
+#define MACB_TX_UNDERRUN_SIZE           1
+#define MACB_TX_ERROR_OFFSET            29
+#define MACB_TX_ERROR_SIZE          1
+#define MACB_TX_WRAP_OFFSET         30
+#define MACB_TX_WRAP_SIZE           1
+#define MACB_TX_USED_OFFSET         31
+#define MACB_TX_USED_SIZE           1
 
 extern int rt_hw_macb_init();
 

bsp/at91sam9260/drivers/mii.h

@@ -1,21 +1,7 @@
 /*
- * File      : mii.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,7 +22,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS     0x0f    /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -51,7 +37,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000      0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -70,7 +56,7 @@
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_ESTATEN        0x0100  /* Extended Status in R15 */
 #define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
 #define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
@@ -99,7 +85,7 @@
 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 
 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
+            ADVERTISE_CSMA)
 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 
@@ -121,8 +107,8 @@
 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 #define LPA_NPAGE               0x8000  /* Next page bit               */
 
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
+#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
 /* Expansion register for auto-negotiation. */
 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
@@ -132,8 +118,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -151,8 +137,8 @@
 #define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
 
 /* Flow control flags */
-#define FLOW_CTRL_TX		0x01
-#define FLOW_CTRL_RX		0x02
+#define FLOW_CTRL_TX        0x01
+#define FLOW_CTRL_RX        0x02
 
 /**
  * mii_nway_result

bsp/at91sam9260/drivers/usart.c

@@ -1,21 +1,7 @@
 /*
- * File      : usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,54 +14,54 @@
 #include <at91sam926x.h>
 #include <rtdevice.h>
 
-#define RXRDY			0x01
-#define TXRDY			(1 << 1)
+#define RXRDY           0x01
+#define TXRDY           (1 << 1)
 
 typedef struct uartport
 {
-	volatile rt_uint32_t CR;
-	volatile rt_uint32_t MR;
-	volatile rt_uint32_t IER;
-	volatile rt_uint32_t IDR;
-	volatile rt_uint32_t IMR;
-	volatile rt_uint32_t CSR;
-	volatile rt_uint32_t RHR;
-	volatile rt_uint32_t THR;
-	volatile rt_uint32_t BRGR;
-	volatile rt_uint32_t RTOR;
-	volatile rt_uint32_t TTGR;
-	volatile rt_uint32_t reserved0[5];
-	volatile rt_uint32_t FIDI;
-	volatile rt_uint32_t NER;
-	volatile rt_uint32_t reserved1;
-	volatile rt_uint32_t IFR;
-	volatile rt_uint32_t reserved2[44];
-	volatile rt_uint32_t RPR;
-	volatile rt_uint32_t RCR;
-	volatile rt_uint32_t TPR;
-	volatile rt_uint32_t TCR;
-	volatile rt_uint32_t RNPR;
-	volatile rt_uint32_t RNCR;
-	volatile rt_uint32_t TNPR;
-	volatile rt_uint32_t TNCR;
-	volatile rt_uint32_t PTCR;
-	volatile rt_uint32_t PTSR;
+    volatile rt_uint32_t CR;
+    volatile rt_uint32_t MR;
+    volatile rt_uint32_t IER;
+    volatile rt_uint32_t IDR;
+    volatile rt_uint32_t IMR;
+    volatile rt_uint32_t CSR;
+    volatile rt_uint32_t RHR;
+    volatile rt_uint32_t THR;
+    volatile rt_uint32_t BRGR;
+    volatile rt_uint32_t RTOR;
+    volatile rt_uint32_t TTGR;
+    volatile rt_uint32_t reserved0[5];
+    volatile rt_uint32_t FIDI;
+    volatile rt_uint32_t NER;
+    volatile rt_uint32_t reserved1;
+    volatile rt_uint32_t IFR;
+    volatile rt_uint32_t reserved2[44];
+    volatile rt_uint32_t RPR;
+    volatile rt_uint32_t RCR;
+    volatile rt_uint32_t TPR;
+    volatile rt_uint32_t TCR;
+    volatile rt_uint32_t RNPR;
+    volatile rt_uint32_t RNCR;
+    volatile rt_uint32_t TNPR;
+    volatile rt_uint32_t TNCR;
+    volatile rt_uint32_t PTCR;
+    volatile rt_uint32_t PTSR;
 }uartport;
 
 #define CIDR FIDI
 #define EXID NER
 #define FNR  reserved1
 
-#define DBGU	((struct uartport *)AT91SAM9260_BASE_DBGU)
+#define DBGU    ((struct uartport *)AT91SAM9260_BASE_DBGU)
 
-#define UART0	((struct uartport *)AT91SAM9260_BASE_US0)
-#define UART1	((struct uartport *)AT91SAM9260_BASE_US1)
-#define UART2	((struct uartport *)AT91SAM9260_BASE_US2)
-#define UART3	((struct uartport *)AT91SAM9260_BASE_US3)
+#define UART0   ((struct uartport *)AT91SAM9260_BASE_US0)
+#define UART1   ((struct uartport *)AT91SAM9260_BASE_US1)
+#define UART2   ((struct uartport *)AT91SAM9260_BASE_US2)
+#define UART3   ((struct uartport *)AT91SAM9260_BASE_US3)
 
 struct at91_uart {
-	uartport *port;
-	int irq;
+    uartport *port;
+    int irq;
 };
 
 
@@ -85,18 +71,18 @@ struct at91_uart {
  */
 void rt_at91_usart_handler(int vector, void *param)
 {
-	int status;
-	struct at91_uart *uart;
-	rt_device_t dev = (rt_device_t)param;
-	uart = (struct at91_uart *)dev->user_data;
-	status = uart->port->CSR;
-	if (!(status & uart->port->IMR))
-	{
-		return;
-	}
-	rt_interrupt_enter();
-	rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
-	rt_interrupt_leave();
+    int status;
+    struct at91_uart *uart;
+    rt_device_t dev = (rt_device_t)param;
+    uart = (struct at91_uart *)dev->user_data;
+    status = uart->port->CSR;
+    if (!(status & uart->port->IMR))
+    {
+        return;
+    }
+    rt_interrupt_enter();
+    rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+    rt_interrupt_leave();
 }
 
 /**
@@ -105,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param)
 static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
                                 struct serial_configure *cfg)
 {
-	int div;
-	int mode = 0;
-	struct at91_uart *uart;
+    int div;
+    int mode = 0;
+    struct at91_uart *uart;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-	uart = (struct at91_uart *)serial->parent.user_data;
-
-	uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | 
-	       AT91_US_RXDIS | AT91_US_TXDIS;
-	mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | 
-		AT91_US_CHMODE_NORMAL;
-	switch (cfg->data_bits)
-	{
-	case DATA_BITS_8:
-		mode |= AT91_US_CHRL_8;
-		break;
-	case DATA_BITS_7:
-		mode |= AT91_US_CHRL_7;
-		break;
-	case DATA_BITS_6:
-		mode |= AT91_US_CHRL_6;
-		break;
-	case DATA_BITS_5:
-		mode |= AT91_US_CHRL_5;
-		break;
-	default:
-		mode |= AT91_US_CHRL_8;
-		break;
-	}
-
-	switch (cfg->stop_bits)
-	{
-	case STOP_BITS_2:
-		mode |= AT91_US_NBSTOP_2;
-		break;
-	case STOP_BITS_1:
-	default:
-		mode |= AT91_US_NBSTOP_1;
-		break;
-	}
-
-	switch (cfg->parity)
-	{
-	case PARITY_ODD:
-		mode |= AT91_US_PAR_ODD;
-		break;
-	case PARITY_EVEN:
-		mode |= AT91_US_PAR_EVEN;
-		break;
-	case PARITY_NONE:
-	default:
-		mode |= AT91_US_PAR_NONE;
-		break;
-	}
-
-	uart->port->MR = mode;
-	div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
-	uart->port->BRGR = div;
-	uart->port->CR = AT91_US_RXEN | AT91_US_TXEN;
-	uart->port->IER = 0x01;
+    uart = (struct at91_uart *)serial->parent.user_data;
+
+    uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX |
+           AT91_US_RXDIS | AT91_US_TXDIS;
+    mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
+        AT91_US_CHMODE_NORMAL;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        mode |= AT91_US_CHRL_8;
+        break;
+    case DATA_BITS_7:
+        mode |= AT91_US_CHRL_7;
+        break;
+    case DATA_BITS_6:
+        mode |= AT91_US_CHRL_6;
+        break;
+    case DATA_BITS_5:
+        mode |= AT91_US_CHRL_5;
+        break;
+    default:
+        mode |= AT91_US_CHRL_8;
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        mode |= AT91_US_NBSTOP_2;
+        break;
+    case STOP_BITS_1:
+    default:
+        mode |= AT91_US_NBSTOP_1;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        mode |= AT91_US_PAR_ODD;
+        break;
+    case PARITY_EVEN:
+        mode |= AT91_US_PAR_EVEN;
+        break;
+    case PARITY_NONE:
+    default:
+        mode |= AT91_US_PAR_NONE;
+        break;
+    }
+
+    uart->port->MR = mode;
+    div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
+    uart->port->BRGR = div;
+    uart->port->CR = AT91_US_RXEN | AT91_US_TXEN;
+    uart->port->IER = 0x01;
 
     return RT_EOK;
 }
@@ -182,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
     {
     case RT_DEVICE_CTRL_CLR_INT:
         /* disable rx irq */
-		rt_hw_interrupt_mask(uart->irq);
+        rt_hw_interrupt_mask(uart->irq);
         break;
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-		rt_hw_interrupt_umask(uart->irq);
+        rt_hw_interrupt_umask(uart->irq);
         break;
     }
 
@@ -196,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
 static int at91_usart_putc(struct rt_serial_device *serial, char c)
 {
     rt_uint32_t level;
-	struct at91_uart *uart = serial->parent.user_data;
+    struct at91_uart *uart = serial->parent.user_data;
 
     while (!(uart->port->CSR & TXRDY));
-	uart->port->THR = c;
+    uart->port->THR = c;
 
     return 1;
 }
@@ -207,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c)
 static int at91_usart_getc(struct rt_serial_device *serial)
 {
     int result;
-	struct at91_uart *uart = serial->parent.user_data;
+    struct at91_uart *uart = serial->parent.user_data;
 
     if (uart->port->CSR & RXRDY)
-	{
-		result = uart->port->RHR & 0xff;
-	}
-	else
-	{
-		result = -1;
-	}
+    {
+        result = uart->port->RHR & 0xff;
+    }
+    else
+    {
+        result = -1;
+    }
 
     return result;
 }
@@ -232,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops =
 #if defined(RT_USING_DBGU)
 static struct rt_serial_device serial_dbgu;
 struct at91_uart dbgu = {
-	DBGU,
-	AT91_ID_SYS
+    DBGU,
+    AT91_ID_SYS
 };
 
 #endif
@@ -241,82 +227,82 @@ struct at91_uart dbgu = {
 #if defined(RT_USING_UART0)
 static struct rt_serial_device serial0;
 struct at91_uart uart0 = {
-	UART0,
-	AT91SAM9260_ID_US0
+    UART0,
+    AT91SAM9260_ID_US0
 };
 #endif
 
 #if defined(RT_USING_UART1)
 static struct rt_serial_device serial1;
 struct at91_uart uart1 = {
-	UART1,
-	AT91SAM9260_ID_US1
+    UART1,
+    AT91SAM9260_ID_US1
 };
 #endif
 
 #if defined(RT_USING_UART2)
 static struct rt_serial_device serial2;
 struct at91_uart uart2 = {
-	UART2,
-	AT91SAM9260_ID_US2
+    UART2,
+    AT91SAM9260_ID_US2
 };
 #endif
 
 #if defined(RT_USING_UART3)
 static struct rt_serial_device serial3;
 struct at91_uart uart3 = {
-	UART3,
-	AT91SAM9260_ID_US3
+    UART3,
+    AT91SAM9260_ID_US3
 };
 #endif
 
 void at91_usart_gpio_init(void)
 {
-	rt_uint32_t val;
+    rt_uint32_t val;
 
 #ifdef RT_USING_DBGU
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
-	//at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
+    //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
 #endif
 
 #ifdef RT_USING_UART0
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5));
 #endif
 
 #ifdef RT_USING_UART1
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
 #endif
 
 #ifdef RT_USING_UART2
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9));
 #endif
 
 #ifdef RT_USING_UART3
-	at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11));
+    at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11));
 #endif
 }
 
@@ -328,17 +314,17 @@ void at91_usart_gpio_init(void)
  */
 int rt_hw_uart_init(void)
 {
-	at91_usart_gpio_init();
+    at91_usart_gpio_init();
 
 #if defined(RT_USING_DBGU)
-	serial_dbgu.ops = &at91_usart_ops;
-	serial_dbgu.config.baud_rate = BAUD_RATE_115200;
+    serial_dbgu.ops = &at91_usart_ops;
+    serial_dbgu.config.baud_rate = BAUD_RATE_115200;
     serial_dbgu.config.bit_order = BIT_ORDER_LSB;
     serial_dbgu.config.data_bits = DATA_BITS_8;
     serial_dbgu.config.parity = PARITY_NONE;
     serial_dbgu.config.stop_bits = STOP_BITS_1;
     serial_dbgu.config.invert = NRZ_NORMAL;
-	serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial_dbgu, "dbgu",
@@ -347,83 +333,83 @@ int rt_hw_uart_init(void)
 #endif
 
 #if defined(RT_USING_UART0)
-	serial0.ops = &at91_usart_ops;
-	serial0.config.baud_rate = BAUD_RATE_115200;
+    serial0.ops = &at91_usart_ops;
+    serial0.config.baud_rate = BAUD_RATE_115200;
     serial0.config.bit_order = BIT_ORDER_LSB;
     serial0.config.data_bits = DATA_BITS_8;
     serial0.config.parity = PARITY_NONE;
     serial0.config.stop_bits = STOP_BITS_1;
     serial0.config.invert = NRZ_NORMAL;
-	serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           &uart0);
-	rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler, 
-							(void *)&(serial0.parent), "UART0");
-	rt_hw_interrupt_umask(uart0.irq);
+    rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
+                            (void *)&(serial0.parent), "UART0");
+    rt_hw_interrupt_umask(uart0.irq);
 #endif
 
 #if defined(RT_USING_UART1)
-	serial1.ops = &at91_usart_ops;
+    serial1.ops = &at91_usart_ops;
     serial1.int_rx = &uart1_int_rx;
-	serial1.config.baud_rate = BAUD_RATE_115200;
+    serial1.config.baud_rate = BAUD_RATE_115200;
     serial1.config.bit_order = BIT_ORDER_LSB;
     serial1.config.data_bits = DATA_BITS_8;
     serial1.config.parity = PARITY_NONE;
     serial1.config.stop_bits = STOP_BITS_1;
     serial1.config.invert = NRZ_NORMAL;
-	serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial1, "uart1",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart1);
-	rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler, 
-							(void *)&(serial1.parent), "UART1");
-	rt_hw_interrupt_umask(uart1.irq);
+    rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
+                            (void *)&(serial1.parent), "UART1");
+    rt_hw_interrupt_umask(uart1.irq);
 #endif
 
 #if defined(RT_USING_UART2)
-	serial2.ops = &at91_usart_ops;
-	serial2.config.baud_rate = BAUD_RATE_115200;
+    serial2.ops = &at91_usart_ops;
+    serial2.config.baud_rate = BAUD_RATE_115200;
     serial2.config.bit_order = BIT_ORDER_LSB;
     serial2.config.data_bits = DATA_BITS_8;
     serial2.config.parity = PARITY_NONE;
     serial2.config.stop_bits = STOP_BITS_1;
     serial2.config.invert = NRZ_NORMAL;
-	serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial2, "uart2",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart2);
-	rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler, 
-							(void *)&(serial2.parent), "UART2");
-	rt_hw_interrupt_umask(uart2.irq);
+    rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
+                            (void *)&(serial2.parent), "UART2");
+    rt_hw_interrupt_umask(uart2.irq);
 #endif
 
 #if defined(RT_USING_UART3)
-	serial3.ops = &at91_usart_ops;
-	serial3.config.baud_rate = BAUD_RATE_115200;
+    serial3.ops = &at91_usart_ops;
+    serial3.config.baud_rate = BAUD_RATE_115200;
     serial3.config.bit_order = BIT_ORDER_LSB;
     serial3.config.data_bits = DATA_BITS_8;
     serial3.config.parity = PARITY_NONE;
     serial3.config.stop_bits = STOP_BITS_1;
     serial3.config.invert = NRZ_NORMAL;
-	serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial3, "uart3",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart3);
-	rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler, 
-							(void *)&(serial3.parent), "UART3");
-	rt_hw_interrupt_umask(uart3.irq);
+    rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
+                            (void *)&(serial3.parent), "UART3");
+    rt_hw_interrupt_umask(uart3.irq);
 #endif
 
-	return 0;
+    return 0;
 }
 
 INIT_BOARD_EXPORT(rt_hw_uart_init);
@@ -431,7 +417,7 @@ INIT_BOARD_EXPORT(rt_hw_uart_init);
 #ifdef RT_USING_DBGU
 void rt_dbgu_isr(void)
 {
-	rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
+    rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
 }
 #endif
 

bsp/at91sam9260/platform/at91_aic.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_aic.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,41 +15,41 @@
 extern "C" {
 #endif
 
-#define AIC_IRQS	32
-
-#define AT91_AIC_SMR(n)		(AT91_AIC + ((n) * 4))	/* Source Mode Registers 0-31 */
-#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */
-#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */
-#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)
-#define			AT91_AIC_SRCTYPE_FALLING	(1 << 5)
-#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)
-#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)
-
-#define AT91_AIC_SVR(n)		(AT91_AIC + 0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR		(AT91_AIC + 0x100)	/* Interrupt Vector Register */
-#define AT91_AIC_FVR		(AT91_AIC + 0x104)	/* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR		(AT91_AIC + 0x108)	/* Interrupt Status Register */
-#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */
-
-#define AT91_AIC_IPR		(AT91_AIC + 0x10c)	/* Interrupt Pending Register */
-#define AT91_AIC_IMR		(AT91_AIC + 0x110)	/* Interrupt Mask Register */
-#define AT91_AIC_CISR		(AT91_AIC + 0x114)	/* Core Interrupt Status Register */
-#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */
-#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */
-
-#define AT91_AIC_IECR		(AT91_AIC + 0x120)	/* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR		(AT91_AIC + 0x124)	/* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR		(AT91_AIC + 0x128)	/* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR		(AT91_AIC + 0x12c)	/* Interrupt Set Command Register */
-#define AT91_AIC_EOICR		(AT91_AIC + 0x130)	/* End of Interrupt Command Register */
-#define AT91_AIC_SPU		(AT91_AIC + 0x134)	/* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR		(AT91_AIC + 0x138)	/* Debug Control Register */
-#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */
-#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */
-
-#define AT91_AIC_FFER		(AT91_AIC + 0x140)	/* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR		(AT91_AIC + 0x144)	/* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR		(AT91_AIC + 0x148)	/* Fast Forcing Status Register [SAM9 only] */
+#define AIC_IRQS    32
+
+#define AT91_AIC_SMR(n)     (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define     AT91_AIC_PRIOR      (7 << 0)        /* Priority Level */
+#define     AT91_AIC_SRCTYPE    (3 << 5)        /* Interrupt Source Type */
+#define         AT91_AIC_SRCTYPE_LOW        (0 << 5)
+#define         AT91_AIC_SRCTYPE_FALLING    (1 << 5)
+#define         AT91_AIC_SRCTYPE_HIGH       (2 << 5)
+#define         AT91_AIC_SRCTYPE_RISING     (3 << 5)
+
+#define AT91_AIC_SVR(n)     (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR        (AT91_AIC + 0x100)  /* Interrupt Vector Register */
+#define AT91_AIC_FVR        (AT91_AIC + 0x104)  /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR        (AT91_AIC + 0x108)  /* Interrupt Status Register */
+#define     AT91_AIC_IRQID      (0x1f << 0)     /* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR        (AT91_AIC + 0x10c)  /* Interrupt Pending Register */
+#define AT91_AIC_IMR        (AT91_AIC + 0x110)  /* Interrupt Mask Register */
+#define AT91_AIC_CISR       (AT91_AIC + 0x114)  /* Core Interrupt Status Register */
+#define     AT91_AIC_NFIQ       (1 << 0)        /* nFIQ Status */
+#define     AT91_AIC_NIRQ       (1 << 1)        /* nIRQ Status */
+
+#define AT91_AIC_IECR       (AT91_AIC + 0x120)  /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR       (AT91_AIC + 0x124)  /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR       (AT91_AIC + 0x128)  /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR       (AT91_AIC + 0x12c)  /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR      (AT91_AIC + 0x130)  /* End of Interrupt Command Register */
+#define AT91_AIC_SPU        (AT91_AIC + 0x134)  /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR        (AT91_AIC + 0x138)  /* Debug Control Register */
+#define     AT91_AIC_DCR_PROT   (1 << 0)        /* Protection Mode */
+#define     AT91_AIC_DCR_GMSK   (1 << 1)        /* General Mask */
+
+#define AT91_AIC_FFER       (AT91_AIC + 0x140)  /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR       (AT91_AIC + 0x144)  /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR       (AT91_AIC + 0x148)  /* Fast Forcing Status Register [SAM9 only] */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_pdc.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_pdc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,21 +11,21 @@
 #ifndef __AT91_PDC_H__
 #define __AT91_PDC_H__
 
-#define AT91_PDC_RPR		0x100	/* Receive Pointer Register */
-#define AT91_PDC_RCR		0x104	/* Receive Counter Register */
-#define AT91_PDC_TPR		0x108	/* Transmit Pointer Register */
-#define AT91_PDC_TCR		0x10c	/* Transmit Counter Register */
-#define AT91_PDC_RNPR		0x110	/* Receive Next Pointer Register */
-#define AT91_PDC_RNCR		0x114	/* Receive Next Counter Register */
-#define AT91_PDC_TNPR		0x118	/* Transmit Next Pointer Register */
-#define AT91_PDC_TNCR		0x11c	/* Transmit Next Counter Register */
+#define AT91_PDC_RPR        0x100   /* Receive Pointer Register */
+#define AT91_PDC_RCR        0x104   /* Receive Counter Register */
+#define AT91_PDC_TPR        0x108   /* Transmit Pointer Register */
+#define AT91_PDC_TCR        0x10c   /* Transmit Counter Register */
+#define AT91_PDC_RNPR       0x110   /* Receive Next Pointer Register */
+#define AT91_PDC_RNCR       0x114   /* Receive Next Counter Register */
+#define AT91_PDC_TNPR       0x118   /* Transmit Next Pointer Register */
+#define AT91_PDC_TNCR       0x11c   /* Transmit Next Counter Register */
 
-#define AT91_PDC_PTCR		0x120	/* Transfer Control Register */
-#define		AT91_PDC_RXTEN		(1 << 0)	/* Receiver Transfer Enable */
-#define		AT91_PDC_RXTDIS	(1 << 1)	/* Receiver Transfer Disable */
-#define		AT91_PDC_TXTEN		(1 << 8)	/* Transmitter Transfer Enable */
-#define		AT91_PDC_TXTDIS	(1 << 9)	/* Transmitter Transfer Disable */
+#define AT91_PDC_PTCR       0x120   /* Transfer Control Register */
+#define     AT91_PDC_RXTEN      (1 << 0)    /* Receiver Transfer Enable */
+#define     AT91_PDC_RXTDIS (1 << 1)    /* Receiver Transfer Disable */
+#define     AT91_PDC_TXTEN      (1 << 8)    /* Transmitter Transfer Enable */
+#define     AT91_PDC_TXTDIS (1 << 9)    /* Transmitter Transfer Disable */
 
-#define AT91_PDC_PTSR		0x124	/* Transfer Status Register */
+#define AT91_PDC_PTSR       0x124   /* Transfer Status Register */
 
 #endif

bsp/at91sam9260/platform/at91_pio.h

@@ -1,22 +1,7 @@
 /*
- * File      : at91_pio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
-
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -30,35 +15,35 @@
 extern "C" {
 #endif
 
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
+#define PIO_PER     0x00    /* Enable Register */
+#define PIO_PDR     0x04    /* Disable Register */
+#define PIO_PSR     0x08    /* Status Register */
+#define PIO_OER     0x10    /* Output Enable Register */
+#define PIO_ODR     0x14    /* Output Disable Register */
+#define PIO_OSR     0x18    /* Output Status Register */
+#define PIO_IFER    0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR    0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR    0x28    /* Glitch Input Filter Status */
+#define PIO_SODR    0x30    /* Set Output Data Register */
+#define PIO_CODR    0x34    /* Clear Output Data Register */
+#define PIO_ODSR    0x38    /* Output Data Status Register */
+#define PIO_PDSR    0x3c    /* Pin Data Status Register */
+#define PIO_IER     0x40    /* Interrupt Enable Register */
+#define PIO_IDR     0x44    /* Interrupt Disable Register */
+#define PIO_IMR     0x48    /* Interrupt Mask Register */
+#define PIO_ISR     0x4c    /* Interrupt Status Register */
+#define PIO_MDER    0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR    0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR    0x58    /* Multi-driver Status Register */
+#define PIO_PUDR    0x60    /* Pull-up Disable Register */
+#define PIO_PUER    0x64    /* Pull-up Enable Register */
+#define PIO_PUSR    0x68    /* Pull-up Status Register */
+#define PIO_ASR     0x70    /* Peripheral A Select Register */
+#define PIO_BSR     0x74    /* Peripheral B Select Register */
+#define PIO_ABSR    0x78    /* AB Status Register */
+#define PIO_OWER    0xa0    /* Output Write Enable Register */
+#define PIO_OWDR    0xa4    /* Output Write Disable Register */
+#define PIO_OWSR    0xa8    /* Output Write Status Register */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_pit.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_pit.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,18 +15,18 @@
 extern "C" {
 #endif
 
-#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
-#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
-#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
-#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
+#define AT91_PIT_MR     (AT91_PIT + 0x00)   /* Mode Register */
+#define     AT91_PIT_PITIEN     (1 << 25)       /* Timer Interrupt Enable */
+#define     AT91_PIT_PITEN      (1 << 24)       /* Timer Enabled */
+#define     AT91_PIT_PIV        (0xfffff)       /* Periodic Interval Value */
 
-#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
-#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
+#define AT91_PIT_SR     (AT91_PIT + 0x04)   /* Status Register */
+#define     AT91_PIT_PITS       (1 << 0)        /* Timer Status */
 
-#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
-#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
-#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
-#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
+#define AT91_PIT_PIVR       (AT91_PIT + 0x08)   /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR       (AT91_PIT + 0x0c)   /* Periodic Interval Image Register */
+#define     AT91_PIT_PICNT      (0xfff << 20)       /* Interval Counter */
+#define     AT91_PIT_CPIV       (0xfffff)       /* Inverval Value */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_pmc.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_pmc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,119 +15,119 @@
 extern "C" {
 #endif
 
-#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
-#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
-
-#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
-#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
-#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
-#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [CAP9 revC & some SAM9 only] */
-#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
-#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
-#define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
-#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
-#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
-#define		AT91_PMC_PCK4		(1 << 12)		/* Programmable Clock 4 [AT572D940HF only] */
-#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
-#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
-#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
-#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
-
-#define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [some SAM9, CAP9] */
-#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
-#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
-#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
-#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI BIAS Start-up Time */
-
-#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
-#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
-#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
-#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-
-#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
-#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
-#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-
-#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
-#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
-#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
-#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
-#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
-#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
-#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
-#define			AT91_PMC_USBDIV_1		(0 << 28)
-#define			AT91_PMC_USBDIV_2		(1 << 28)
-#define			AT91_PMC_USBDIV_4		(2 << 28)
-#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
-
-#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
-#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
-#define			AT91_PMC_CSS_SLOW		(0 << 0)
-#define			AT91_PMC_CSS_MAIN		(1 << 0)
-#define			AT91_PMC_CSS_PLLA		(2 << 0)
-#define			AT91_PMC_CSS_PLLB		(3 << 0)
-#define			AT91_PMC_CSS_UPLL		(3 << 0)	/* [some SAM9 only] */
-#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
-#define			AT91_PMC_PRES_1			(0 << 2)
-#define			AT91_PMC_PRES_2			(1 << 2)
-#define			AT91_PMC_PRES_4			(2 << 2)
-#define			AT91_PMC_PRES_8			(3 << 2)
-#define			AT91_PMC_PRES_16		(4 << 2)
-#define			AT91_PMC_PRES_32		(5 << 2)
-#define			AT91_PMC_PRES_64		(6 << 2)
-#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
-#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
-#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
-#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
-#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
-#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9,CAP9 only] */
-#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
-#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
-#define			AT91SAM9_PMC_MDIV_6		(3 << 8)	/* [some SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
-#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
-#define			AT91_PMC_PDIV_1			(0 << 12)
-#define			AT91_PMC_PDIV_2			(1 << 12)
-#define		AT91_PMC_PLLADIV2	(1 << 12)		/* PLLA divisor by 2 [some SAM9 only] */
-#define			AT91_PMC_PLLADIV2_OFF		(0 << 12)
-#define			AT91_PMC_PLLADIV2_ON		(1 << 12)
-
-#define	AT91_PMC_USB		(AT91_PMC + 0x38)	/* USB Clock Register [some SAM9 only] */
-#define		AT91_PMC_USBS		(0x1 <<  0)		/* USB OHCI Input clock selection */
-#define			AT91_PMC_USBS_PLLA		(0 << 0)
-#define			AT91_PMC_USBS_UPLL		(1 << 0)
-#define		AT91_PMC_OHCIUSBDIV	(0xF <<  8)		/* Divider for USB OHCI Clock */
-
-#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-N Registers */
-#define		AT91_PMC_CSSMCK		(0x1 <<  8)		/* CSS or Master Clock Selection */
-#define			AT91_PMC_CSSMCK_CSS		(0 << 8)
-#define			AT91_PMC_CSSMCK_MCK		(1 << 8)
-
-#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
-#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
-#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
-#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
-#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
-#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
-#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
-#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [some SAM9, AT91CAP9 only] */
-#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Clock Oscillator [AT91CAP9 revC only] */
-#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
-
-#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
-#define		AT91_PMC_PROTKEY	0x504d4301		/* Activation Code */
-
-#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_SCER       (AT91_PMC + 0x00)   /* System Clock Enable Register */
+#define AT91_PMC_SCDR       (AT91_PMC + 0x04)   /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR       (AT91_PMC + 0x08)   /* System Clock Status Register */
+#define     AT91_PMC_PCK        (1 <<  0)       /* Processor Clock */
+#define     AT91RM9200_PMC_UDP  (1 <<  1)       /* USB Devcice Port Clock [AT91RM9200 only] */
+#define     AT91RM9200_PMC_MCKUDP   (1 <<  2)       /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define     AT91CAP9_PMC_DDR    (1 <<  2)       /* DDR Clock [CAP9 revC & some SAM9 only] */
+#define     AT91RM9200_PMC_UHP  (1 <<  4)       /* USB Host Port Clock [AT91RM9200 only] */
+#define     AT91SAM926x_PMC_UHP (1 <<  6)       /* USB Host Port Clock [AT91SAM926x only] */
+#define     AT91CAP9_PMC_UHP    (1 <<  6)       /* USB Host Port Clock [AT91CAP9 only] */
+#define     AT91SAM926x_PMC_UDP (1 <<  7)       /* USB Devcice Port Clock [AT91SAM926x only] */
+#define     AT91_PMC_PCK0       (1 <<  8)       /* Programmable Clock 0 */
+#define     AT91_PMC_PCK1       (1 <<  9)       /* Programmable Clock 1 */
+#define     AT91_PMC_PCK2       (1 << 10)       /* Programmable Clock 2 */
+#define     AT91_PMC_PCK3       (1 << 11)       /* Programmable Clock 3 */
+#define     AT91_PMC_PCK4       (1 << 12)       /* Programmable Clock 4 [AT572D940HF only] */
+#define     AT91_PMC_HCK0       (1 << 16)       /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define     AT91_PMC_HCK1       (1 << 17)       /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_PCER       (AT91_PMC + 0x10)   /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR       (AT91_PMC + 0x14)   /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR       (AT91_PMC + 0x18)   /* Peripheral Clock Status Register */
+
+#define AT91_CKGR_UCKR      (AT91_PMC + 0x1C)   /* UTMI Clock Register [some SAM9, CAP9] */
+#define     AT91_PMC_UPLLEN     (1   << 16)     /* UTMI PLL Enable */
+#define     AT91_PMC_UPLLCOUNT  (0xf << 20)     /* UTMI PLL Start-up Time */
+#define     AT91_PMC_BIASEN     (1   << 24)     /* UTMI BIAS Enable */
+#define     AT91_PMC_BIASCOUNT  (0xf << 28)     /* UTMI BIAS Start-up Time */
+
+#define AT91_CKGR_MOR       (AT91_PMC + 0x20)   /* Main Oscillator Register [not on SAM9RL] */
+#define     AT91_PMC_MOSCEN     (1    << 0)     /* Main Oscillator Enable */
+#define     AT91_PMC_OSCBYPASS  (1    << 1)     /* Oscillator Bypass [SAM9x, CAP9] */
+#define     AT91_PMC_OSCOUNT    (0xff << 8)     /* Main Oscillator Start-up Time */
+
+#define AT91_CKGR_MCFR      (AT91_PMC + 0x24)   /* Main Clock Frequency Register */
+#define     AT91_PMC_MAINF      (0xffff <<  0)      /* Main Clock Frequency */
+#define     AT91_PMC_MAINRDY    (1  << 16)      /* Main Clock Ready */
+
+#define AT91_CKGR_PLLAR     (AT91_PMC + 0x28)   /* PLL A Register */
+#define AT91_CKGR_PLLBR     (AT91_PMC + 0x2c)   /* PLL B Register */
+#define     AT91_PMC_DIV        (0xff  <<  0)       /* Divider */
+#define     AT91_PMC_PLLCOUNT   (0x3f  <<  8)       /* PLL Counter */
+#define     AT91_PMC_OUT        (3     << 14)       /* PLL Clock Frequency Range */
+#define     AT91_PMC_MUL        (0x7ff << 16)       /* PLL Multiplier */
+#define     AT91_PMC_USBDIV     (3     << 28)       /* USB Divisor (PLLB only) */
+#define         AT91_PMC_USBDIV_1       (0 << 28)
+#define         AT91_PMC_USBDIV_2       (1 << 28)
+#define         AT91_PMC_USBDIV_4       (2 << 28)
+#define     AT91_PMC_USB96M     (1     << 28)       /* Divider by 2 Enable (PLLB only) */
+
+#define AT91_PMC_MCKR       (AT91_PMC + 0x30)   /* Master Clock Register */
+#define     AT91_PMC_CSS        (3 <<  0)       /* Master Clock Selection */
+#define         AT91_PMC_CSS_SLOW       (0 << 0)
+#define         AT91_PMC_CSS_MAIN       (1 << 0)
+#define         AT91_PMC_CSS_PLLA       (2 << 0)
+#define         AT91_PMC_CSS_PLLB       (3 << 0)
+#define         AT91_PMC_CSS_UPLL       (3 << 0)    /* [some SAM9 only] */
+#define     AT91_PMC_PRES       (7 <<  2)       /* Master Clock Prescaler */
+#define         AT91_PMC_PRES_1         (0 << 2)
+#define         AT91_PMC_PRES_2         (1 << 2)
+#define         AT91_PMC_PRES_4         (2 << 2)
+#define         AT91_PMC_PRES_8         (3 << 2)
+#define         AT91_PMC_PRES_16        (4 << 2)
+#define         AT91_PMC_PRES_32        (5 << 2)
+#define         AT91_PMC_PRES_64        (6 << 2)
+#define     AT91_PMC_MDIV       (3 <<  8)       /* Master Clock Division */
+#define         AT91RM9200_PMC_MDIV_1       (0 << 8)    /* [AT91RM9200 only] */
+#define         AT91RM9200_PMC_MDIV_2       (1 << 8)
+#define         AT91RM9200_PMC_MDIV_3       (2 << 8)
+#define         AT91RM9200_PMC_MDIV_4       (3 << 8)
+#define         AT91SAM9_PMC_MDIV_1     (0 << 8)    /* [SAM9,CAP9 only] */
+#define         AT91SAM9_PMC_MDIV_2     (1 << 8)
+#define         AT91SAM9_PMC_MDIV_4     (2 << 8)
+#define         AT91SAM9_PMC_MDIV_6     (3 << 8)    /* [some SAM9 only] */
+#define         AT91SAM9_PMC_MDIV_3     (3 << 8)    /* [some SAM9 only] */
+#define     AT91_PMC_PDIV       (1 << 12)       /* Processor Clock Division [some SAM9 only] */
+#define         AT91_PMC_PDIV_1         (0 << 12)
+#define         AT91_PMC_PDIV_2         (1 << 12)
+#define     AT91_PMC_PLLADIV2   (1 << 12)       /* PLLA divisor by 2 [some SAM9 only] */
+#define         AT91_PMC_PLLADIV2_OFF       (0 << 12)
+#define         AT91_PMC_PLLADIV2_ON        (1 << 12)
+
+#define AT91_PMC_USB        (AT91_PMC + 0x38)   /* USB Clock Register [some SAM9 only] */
+#define     AT91_PMC_USBS       (0x1 <<  0)     /* USB OHCI Input clock selection */
+#define         AT91_PMC_USBS_PLLA      (0 << 0)
+#define         AT91_PMC_USBS_UPLL      (1 << 0)
+#define     AT91_PMC_OHCIUSBDIV (0xF <<  8)     /* Divider for USB OHCI Clock */
+
+#define AT91_PMC_PCKR(n)    (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define     AT91_PMC_CSSMCK     (0x1 <<  8)     /* CSS or Master Clock Selection */
+#define         AT91_PMC_CSSMCK_CSS     (0 << 8)
+#define         AT91_PMC_CSSMCK_MCK     (1 << 8)
+
+#define AT91_PMC_IER        (AT91_PMC + 0x60)   /* Interrupt Enable Register */
+#define AT91_PMC_IDR        (AT91_PMC + 0x64)   /* Interrupt Disable Register */
+#define AT91_PMC_SR     (AT91_PMC + 0x68)   /* Status Register */
+#define     AT91_PMC_MOSCS      (1 <<  0)       /* MOSCS Flag */
+#define     AT91_PMC_LOCKA      (1 <<  1)       /* PLLA Lock */
+#define     AT91_PMC_LOCKB      (1 <<  2)       /* PLLB Lock */
+#define     AT91_PMC_MCKRDY     (1 <<  3)       /* Master Clock */
+#define     AT91_PMC_LOCKU      (1 <<  6)       /* UPLL Lock [some SAM9, AT91CAP9 only] */
+#define     AT91_PMC_OSCSEL     (1 <<  7)       /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define     AT91_PMC_PCK0RDY    (1 <<  8)       /* Programmable Clock 0 */
+#define     AT91_PMC_PCK1RDY    (1 <<  9)       /* Programmable Clock 1 */
+#define     AT91_PMC_PCK2RDY    (1 << 10)       /* Programmable Clock 2 */
+#define     AT91_PMC_PCK3RDY    (1 << 11)       /* Programmable Clock 3 */
+#define AT91_PMC_IMR        (AT91_PMC + 0x6c)   /* Interrupt Mask Register */
+
+#define AT91_PMC_PROT       (AT91_PMC + 0xe4)   /* Protect Register [AT91CAP9 revC only] */
+#define     AT91_PMC_PROTKEY    0x504d4301      /* Activation Code */
+
+#define AT91_PMC_VER        (AT91_PMC + 0xfc)   /* PMC Module Version [AT91CAP9 only] */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_rstc.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_rstc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,27 +15,27 @@
 extern "C" {
 #endif
 
-#define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
-#define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
-#define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
-#define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
-#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_RSTC_SR		(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
-#define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
-#define		AT91_RSTC_RSTTYP	(7 << 8)		/* Reset Type */
-#define			AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
-#define			AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
-#define			AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
-#define			AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
-#define			AT91_RSTC_RSTTYP_USER	(4 << 8)
-#define		AT91_RSTC_NRSTL		(1 << 16)		/* NRST Pin Level */
-#define		AT91_RSTC_SRCMP		(1 << 17)		/* Software Reset Command in Progress */
-
-#define AT91_RSTC_MR		(AT91_RSTC + 0x08)	/* Reset Controller Mode Register */
-#define		AT91_RSTC_URSTEN	(1 << 0)		/* User Reset Enable */
-#define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
-#define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
+#define AT91_RSTC_CR        (AT91_RSTC + 0x00)  /* Reset Controller Control Register */
+#define     AT91_RSTC_PROCRST   (1 << 0)        /* Processor Reset */
+#define     AT91_RSTC_PERRST    (1 << 2)        /* Peripheral Reset */
+#define     AT91_RSTC_EXTRST    (1 << 3)        /* External Reset */
+#define     AT91_RSTC_KEY       (0xa5 << 24)        /* KEY Password */
+
+#define AT91_RSTC_SR        (AT91_RSTC + 0x04)  /* Reset Controller Status Register */
+#define     AT91_RSTC_URSTS     (1 << 0)        /* User Reset Status */
+#define     AT91_RSTC_RSTTYP    (7 << 8)        /* Reset Type */
+#define         AT91_RSTC_RSTTYP_GENERAL    (0 << 8)
+#define         AT91_RSTC_RSTTYP_WAKEUP     (1 << 8)
+#define         AT91_RSTC_RSTTYP_WATCHDOG   (2 << 8)
+#define         AT91_RSTC_RSTTYP_SOFTWARE   (3 << 8)
+#define         AT91_RSTC_RSTTYP_USER   (4 << 8)
+#define     AT91_RSTC_NRSTL     (1 << 16)       /* NRST Pin Level */
+#define     AT91_RSTC_SRCMP     (1 << 17)       /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR        (AT91_RSTC + 0x08)  /* Reset Controller Mode Register */
+#define     AT91_RSTC_URSTEN    (1 << 0)        /* User Reset Enable */
+#define     AT91_RSTC_URSTIEN   (1 << 4)        /* User Reset Interrupt Enable */
+#define     AT91_RSTC_ERSTL     (0xf << 8)      /* External Reset Length */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_serial.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,113 +15,113 @@
 extern "C" {
 #endif
 
-#define AT91_US_CR		0x00			/* Control Register */
-#define		AT91_US_RSTRX		(1 <<  2)		/* Reset Receiver */
-#define		AT91_US_RSTTX		(1 <<  3)		/* Reset Transmitter */
-#define		AT91_US_RXEN		(1 <<  4)		/* Receiver Enable */
-#define		AT91_US_RXDIS		(1 <<  5)		/* Receiver Disable */
-#define		AT91_US_TXEN		(1 <<  6)		/* Transmitter Enable */
-#define		AT91_US_TXDIS		(1 <<  7)		/* Transmitter Disable */
-#define		AT91_US_RSTSTA		(1 <<  8)		/* Reset Status Bits */
-#define		AT91_US_STTBRK		(1 <<  9)		/* Start Break */
-#define		AT91_US_STPBRK		(1 << 10)		/* Stop Break */
-#define		AT91_US_STTTO		(1 << 11)		/* Start Time-out */
-#define		AT91_US_SENDA		(1 << 12)		/* Send Address */
-#define		AT91_US_RSTIT		(1 << 13)		/* Reset Iterations */
-#define		AT91_US_RSTNACK	(1 << 14)		/* Reset Non Acknowledge */
-#define		AT91_US_RETTO		(1 << 15)		/* Rearm Time-out */
-#define		AT91_US_DTREN		(1 << 16)		/* Data Terminal Ready Enable [AT91RM9200 only] */
-#define		AT91_US_DTRDIS		(1 << 17)		/* Data Terminal Ready Disable [AT91RM9200 only] */
-#define		AT91_US_RTSEN		(1 << 18)		/* Request To Send Enable */
-#define		AT91_US_RTSDIS		(1 << 19)		/* Request To Send Disable */
+#define AT91_US_CR      0x00            /* Control Register */
+#define     AT91_US_RSTRX       (1 <<  2)       /* Reset Receiver */
+#define     AT91_US_RSTTX       (1 <<  3)       /* Reset Transmitter */
+#define     AT91_US_RXEN        (1 <<  4)       /* Receiver Enable */
+#define     AT91_US_RXDIS       (1 <<  5)       /* Receiver Disable */
+#define     AT91_US_TXEN        (1 <<  6)       /* Transmitter Enable */
+#define     AT91_US_TXDIS       (1 <<  7)       /* Transmitter Disable */
+#define     AT91_US_RSTSTA      (1 <<  8)       /* Reset Status Bits */
+#define     AT91_US_STTBRK      (1 <<  9)       /* Start Break */
+#define     AT91_US_STPBRK      (1 << 10)       /* Stop Break */
+#define     AT91_US_STTTO       (1 << 11)       /* Start Time-out */
+#define     AT91_US_SENDA       (1 << 12)       /* Send Address */
+#define     AT91_US_RSTIT       (1 << 13)       /* Reset Iterations */
+#define     AT91_US_RSTNACK (1 << 14)       /* Reset Non Acknowledge */
+#define     AT91_US_RETTO       (1 << 15)       /* Rearm Time-out */
+#define     AT91_US_DTREN       (1 << 16)       /* Data Terminal Ready Enable [AT91RM9200 only] */
+#define     AT91_US_DTRDIS      (1 << 17)       /* Data Terminal Ready Disable [AT91RM9200 only] */
+#define     AT91_US_RTSEN       (1 << 18)       /* Request To Send Enable */
+#define     AT91_US_RTSDIS      (1 << 19)       /* Request To Send Disable */
 
-#define AT91_US_MR		0x04			/* Mode Register */
-#define		AT91_US_USMODE		(0xf <<  0)		/* Mode of the USART */
-#define			AT91_US_USMODE_NORMAL		0
-#define			AT91_US_USMODE_RS485		1
-#define			AT91_US_USMODE_HWHS		2
-#define			AT91_US_USMODE_MODEM		3
-#define			AT91_US_USMODE_ISO7816_T0	4
-#define			AT91_US_USMODE_ISO7816_T1	6
-#define			AT91_US_USMODE_IRDA		8
-#define		AT91_US_USCLKS		(3   <<  4)		/* Clock Selection */
-#define			AT91_US_USCLKS_MCK		(0 <<  4)
-#define			AT91_US_USCLKS_MCK_DIV8	(1 <<  4)
-#define			AT91_US_USCLKS_SCK		(3 <<  4)
-#define		AT91_US_CHRL		(3   <<  6)		/* Character Length */
-#define			AT91_US_CHRL_5			(0 <<  6)
-#define			AT91_US_CHRL_6			(1 <<  6)
-#define			AT91_US_CHRL_7			(2 <<  6)
-#define			AT91_US_CHRL_8			(3 <<  6)
-#define		AT91_US_SYNC		(1 <<  8)		/* Synchronous Mode Select */
-#define		AT91_US_PAR		(7 <<  9)		/* Parity Type */
-#define			AT91_US_PAR_EVEN		(0 <<  9)
-#define			AT91_US_PAR_ODD		(1 <<  9)
-#define			AT91_US_PAR_SPACE		(2 <<  9)
-#define			AT91_US_PAR_MARK		(3 <<  9)
-#define			AT91_US_PAR_NONE		(4 <<  9)
-#define			AT91_US_PAR_MULTI_DROP		(6 <<  9)
-#define		AT91_US_NBSTOP		(3 << 12)		/* Number of Stop Bits */
-#define			AT91_US_NBSTOP_1		(0 << 12)
-#define			AT91_US_NBSTOP_1_5		(1 << 12)
-#define			AT91_US_NBSTOP_2		(2 << 12)
-#define		AT91_US_CHMODE		(3 << 14)		/* Channel Mode */
-#define			AT91_US_CHMODE_NORMAL		(0 << 14)
-#define			AT91_US_CHMODE_ECHO		(1 << 14)
-#define			AT91_US_CHMODE_LOC_LOOP	(2 << 14)
-#define			AT91_US_CHMODE_REM_LOOP	(3 << 14)
-#define		AT91_US_MSBF		(1 << 16)		/* Bit Order */
-#define		AT91_US_MODE9		(1 << 17)		/* 9-bit Character Length */
-#define		AT91_US_CLKO		(1 << 18)		/* Clock Output Select */
-#define		AT91_US_OVER		(1 << 19)		/* Oversampling Mode */
-#define		AT91_US_INACK		(1 << 20)		/* Inhibit Non Acknowledge */
-#define		AT91_US_DSNACK		(1 << 21)		/* Disable Successive NACK */
-#define		AT91_US_MAX_ITER	(7 << 24)		/* Max Iterations */
-#define		AT91_US_FILTER		(1 << 28)		/* Infrared Receive Line Filter */
+#define AT91_US_MR      0x04            /* Mode Register */
+#define     AT91_US_USMODE      (0xf <<  0)     /* Mode of the USART */
+#define         AT91_US_USMODE_NORMAL       0
+#define         AT91_US_USMODE_RS485        1
+#define         AT91_US_USMODE_HWHS     2
+#define         AT91_US_USMODE_MODEM        3
+#define         AT91_US_USMODE_ISO7816_T0   4
+#define         AT91_US_USMODE_ISO7816_T1   6
+#define         AT91_US_USMODE_IRDA     8
+#define     AT91_US_USCLKS      (3   <<  4)     /* Clock Selection */
+#define         AT91_US_USCLKS_MCK      (0 <<  4)
+#define         AT91_US_USCLKS_MCK_DIV8 (1 <<  4)
+#define         AT91_US_USCLKS_SCK      (3 <<  4)
+#define     AT91_US_CHRL        (3   <<  6)     /* Character Length */
+#define         AT91_US_CHRL_5          (0 <<  6)
+#define         AT91_US_CHRL_6          (1 <<  6)
+#define         AT91_US_CHRL_7          (2 <<  6)
+#define         AT91_US_CHRL_8          (3 <<  6)
+#define     AT91_US_SYNC        (1 <<  8)       /* Synchronous Mode Select */
+#define     AT91_US_PAR     (7 <<  9)       /* Parity Type */
+#define         AT91_US_PAR_EVEN        (0 <<  9)
+#define         AT91_US_PAR_ODD     (1 <<  9)
+#define         AT91_US_PAR_SPACE       (2 <<  9)
+#define         AT91_US_PAR_MARK        (3 <<  9)
+#define         AT91_US_PAR_NONE        (4 <<  9)
+#define         AT91_US_PAR_MULTI_DROP      (6 <<  9)
+#define     AT91_US_NBSTOP      (3 << 12)       /* Number of Stop Bits */
+#define         AT91_US_NBSTOP_1        (0 << 12)
+#define         AT91_US_NBSTOP_1_5      (1 << 12)
+#define         AT91_US_NBSTOP_2        (2 << 12)
+#define     AT91_US_CHMODE      (3 << 14)       /* Channel Mode */
+#define         AT91_US_CHMODE_NORMAL       (0 << 14)
+#define         AT91_US_CHMODE_ECHO     (1 << 14)
+#define         AT91_US_CHMODE_LOC_LOOP (2 << 14)
+#define         AT91_US_CHMODE_REM_LOOP (3 << 14)
+#define     AT91_US_MSBF        (1 << 16)       /* Bit Order */
+#define     AT91_US_MODE9       (1 << 17)       /* 9-bit Character Length */
+#define     AT91_US_CLKO        (1 << 18)       /* Clock Output Select */
+#define     AT91_US_OVER        (1 << 19)       /* Oversampling Mode */
+#define     AT91_US_INACK       (1 << 20)       /* Inhibit Non Acknowledge */
+#define     AT91_US_DSNACK      (1 << 21)       /* Disable Successive NACK */
+#define     AT91_US_MAX_ITER    (7 << 24)       /* Max Iterations */
+#define     AT91_US_FILTER      (1 << 28)       /* Infrared Receive Line Filter */
 
-#define AT91_US_IER		0x08			/* Interrupt Enable Register */
-#define		AT91_US_RXRDY		(1 <<  0)		/* Receiver Ready */
-#define		AT91_US_TXRDY		(1 <<  1)		/* Transmitter Ready */
-#define		AT91_US_RXBRK		(1 <<  2)		/* Break Received / End of Break */
-#define		AT91_US_ENDRX		(1 <<  3)		/* End of Receiver Transfer */
-#define		AT91_US_ENDTX		(1 <<  4)		/* End of Transmitter Transfer */
-#define		AT91_US_OVRE		(1 <<  5)		/* Overrun Error */
-#define		AT91_US_FRAME		(1 <<  6)		/* Framing Error */
-#define		AT91_US_PARE		(1 <<  7)		/* Parity Error */
-#define		AT91_US_TIMEOUT	(1 <<  8)		/* Receiver Time-out */
-#define		AT91_US_TXEMPTY	(1 <<  9)		/* Transmitter Empty */
-#define		AT91_US_ITERATION	(1 << 10)		/* Max number of Repetitions Reached */
-#define		AT91_US_TXBUFE		(1 << 11)		/* Transmission Buffer Empty */
-#define		AT91_US_RXBUFF		(1 << 12)		/* Reception Buffer Full */
-#define		AT91_US_NACK		(1 << 13)		/* Non Acknowledge */
-#define		AT91_US_RIIC		(1 << 16)		/* Ring Indicator Input Change [AT91RM9200 only] */
-#define		AT91_US_DSRIC		(1 << 17)		/* Data Set Ready Input Change [AT91RM9200 only] */
-#define		AT91_US_DCDIC		(1 << 18)		/* Data Carrier Detect Input Change [AT91RM9200 only] */
-#define		AT91_US_CTSIC		(1 << 19)		/* Clear to Send Input Change */
-#define		AT91_US_RI		(1 << 20)		/* RI */
-#define		AT91_US_DSR		(1 << 21)		/* DSR */
-#define		AT91_US_DCD		(1 << 22)		/* DCD */
-#define		AT91_US_CTS		(1 << 23)		/* CTS */
+#define AT91_US_IER     0x08            /* Interrupt Enable Register */
+#define     AT91_US_RXRDY       (1 <<  0)       /* Receiver Ready */
+#define     AT91_US_TXRDY       (1 <<  1)       /* Transmitter Ready */
+#define     AT91_US_RXBRK       (1 <<  2)       /* Break Received / End of Break */
+#define     AT91_US_ENDRX       (1 <<  3)       /* End of Receiver Transfer */
+#define     AT91_US_ENDTX       (1 <<  4)       /* End of Transmitter Transfer */
+#define     AT91_US_OVRE        (1 <<  5)       /* Overrun Error */
+#define     AT91_US_FRAME       (1 <<  6)       /* Framing Error */
+#define     AT91_US_PARE        (1 <<  7)       /* Parity Error */
+#define     AT91_US_TIMEOUT (1 <<  8)       /* Receiver Time-out */
+#define     AT91_US_TXEMPTY (1 <<  9)       /* Transmitter Empty */
+#define     AT91_US_ITERATION   (1 << 10)       /* Max number of Repetitions Reached */
+#define     AT91_US_TXBUFE      (1 << 11)       /* Transmission Buffer Empty */
+#define     AT91_US_RXBUFF      (1 << 12)       /* Reception Buffer Full */
+#define     AT91_US_NACK        (1 << 13)       /* Non Acknowledge */
+#define     AT91_US_RIIC        (1 << 16)       /* Ring Indicator Input Change [AT91RM9200 only] */
+#define     AT91_US_DSRIC       (1 << 17)       /* Data Set Ready Input Change [AT91RM9200 only] */
+#define     AT91_US_DCDIC       (1 << 18)       /* Data Carrier Detect Input Change [AT91RM9200 only] */
+#define     AT91_US_CTSIC       (1 << 19)       /* Clear to Send Input Change */
+#define     AT91_US_RI      (1 << 20)       /* RI */
+#define     AT91_US_DSR     (1 << 21)       /* DSR */
+#define     AT91_US_DCD     (1 << 22)       /* DCD */
+#define     AT91_US_CTS     (1 << 23)       /* CTS */
 
-#define AT91_US_IDR		0x0c			/* Interrupt Disable Register */
-#define AT91_US_IMR		0x10			/* Interrupt Mask Register */
-#define AT91_US_CSR		0x14			/* Channel Status Register */
-#define AT91_US_RHR		0x18			/* Receiver Holding Register */
-#define AT91_US_THR		0x1c			/* Transmitter Holding Register */
-#define		AT91_US_SYNH		(1 << 15)		/* Transmit/Receive Sync [AT91SAM9261 only] */
+#define AT91_US_IDR     0x0c            /* Interrupt Disable Register */
+#define AT91_US_IMR     0x10            /* Interrupt Mask Register */
+#define AT91_US_CSR     0x14            /* Channel Status Register */
+#define AT91_US_RHR     0x18            /* Receiver Holding Register */
+#define AT91_US_THR     0x1c            /* Transmitter Holding Register */
+#define     AT91_US_SYNH        (1 << 15)       /* Transmit/Receive Sync [AT91SAM9261 only] */
 
-#define AT91_US_BRGR		0x20			/* Baud Rate Generator Register */
-#define		AT91_US_CD		(0xffff << 0)		/* Clock Divider */
+#define AT91_US_BRGR        0x20            /* Baud Rate Generator Register */
+#define     AT91_US_CD      (0xffff << 0)       /* Clock Divider */
 
-#define AT91_US_RTOR		0x24			/* Receiver Time-out Register */
-#define		AT91_US_TO		(0xffff << 0)		/* Time-out Value */
+#define AT91_US_RTOR        0x24            /* Receiver Time-out Register */
+#define     AT91_US_TO      (0xffff << 0)       /* Time-out Value */
 
-#define AT91_US_TTGR		0x28			/* Transmitter Timeguard Register */
-#define		AT91_US_TG		(0xff << 0)		/* Timeguard Value */
+#define AT91_US_TTGR        0x28            /* Transmitter Timeguard Register */
+#define     AT91_US_TG      (0xff << 0)     /* Timeguard Value */
 
-#define AT91_US_FIDI		0x40			/* FI DI Ratio Register */
-#define AT91_US_NER		0x44			/* Number of Errors Register */
-#define AT91_US_IF		0x4c			/* IrDA Filter Register */
+#define AT91_US_FIDI        0x40            /* FI DI Ratio Register */
+#define AT91_US_NER     0x44            /* Number of Errors Register */
+#define AT91_US_IF      0x4c            /* IrDA Filter Register */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_shdwc.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_shdwc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,24 +15,24 @@
 extern "C" {
 #endif
 
-#define AT91_SHDW_CR		(AT91_SHDWC + 0x00)	/* Shut Down Control Register */
-#define		AT91_SHDW_SHDW		(1    << 0)		/* Shut Down command */
-#define		AT91_SHDW_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_SHDW_MR		(AT91_SHDWC + 0x04)	/* Shut Down Mode Register */
-#define		AT91_SHDW_WKMODE0	(3 << 0)		/* Wake-up 0 Mode Selection */
-#define			AT91_SHDW_WKMODE0_NONE		0
-#define			AT91_SHDW_WKMODE0_HIGH		1
-#define			AT91_SHDW_WKMODE0_LOW		2
-#define			AT91_SHDW_WKMODE0_ANYLEVEL	3
-#define		AT91_SHDW_CPTWK0	(0xf << 4)		/* Counter On Wake Up 0 */
-#define			AT91_SHDW_CPTWK0_(x)	((x) << 4)
-#define		AT91_SHDW_RTTWKEN	(1   << 16)		/* Real Time Timer Wake-up Enable */
-
-#define AT91_SHDW_SR		(AT91_SHDWC + 0x08)	/* Shut Down Status Register */
-#define		AT91_SHDW_WAKEUP0	(1 <<  0)		/* Wake-up 0 Status */
-#define		AT91_SHDW_RTTWK		(1 << 16)		/* Real-time Timer Wake-up */
-#define		AT91_SHDW_RTCWK		(1 << 17)		/* Real-time Clock Wake-up [SAM9RL] */
+#define AT91_SHDW_CR        (AT91_SHDWC + 0x00) /* Shut Down Control Register */
+#define     AT91_SHDW_SHDW      (1    << 0)     /* Shut Down command */
+#define     AT91_SHDW_KEY       (0xa5 << 24)        /* KEY Password */
+
+#define AT91_SHDW_MR        (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
+#define     AT91_SHDW_WKMODE0   (3 << 0)        /* Wake-up 0 Mode Selection */
+#define         AT91_SHDW_WKMODE0_NONE      0
+#define         AT91_SHDW_WKMODE0_HIGH      1
+#define         AT91_SHDW_WKMODE0_LOW       2
+#define         AT91_SHDW_WKMODE0_ANYLEVEL  3
+#define     AT91_SHDW_CPTWK0    (0xf << 4)      /* Counter On Wake Up 0 */
+#define         AT91_SHDW_CPTWK0_(x)    ((x) << 4)
+#define     AT91_SHDW_RTTWKEN   (1   << 16)     /* Real Time Timer Wake-up Enable */
+
+#define AT91_SHDW_SR        (AT91_SHDWC + 0x08) /* Shut Down Status Register */
+#define     AT91_SHDW_WAKEUP0   (1 <<  0)       /* Wake-up 0 Status */
+#define     AT91_SHDW_RTTWK     (1 << 16)       /* Real-time Timer Wake-up */
+#define     AT91_SHDW_RTCWK     (1 << 17)       /* Real-time Clock Wake-up [SAM9RL] */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_tc.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_tc.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,133 +15,133 @@
 extern "C" {
 #endif
 
-#define AT91_TC_BCR		0xc0		/* TC Block Control Register */
-#define		AT91_TC_SYNC		(1 << 0)	/* Synchro Command */
+#define AT91_TC_BCR     0xc0        /* TC Block Control Register */
+#define     AT91_TC_SYNC        (1 << 0)    /* Synchro Command */
 
-#define AT91_TC_BMR		0xc4		/* TC Block Mode Register */
-#define		AT91_TC_TC0XC0S		(3 << 0)	/* External Clock Signal 0 Selection */
-#define			AT91_TC_TC0XC0S_TCLK0		(0 << 0)
-#define			AT91_TC_TC0XC0S_NONE		(1 << 0)
-#define			AT91_TC_TC0XC0S_TIOA1		(2 << 0)
-#define			AT91_TC_TC0XC0S_TIOA2		(3 << 0)
-#define		AT91_TC_TC1XC1S		(3 << 2)	/* External Clock Signal 1 Selection */
-#define			AT91_TC_TC1XC1S_TCLK1		(0 << 2)
-#define			AT91_TC_TC1XC1S_NONE		(1 << 2)
-#define			AT91_TC_TC1XC1S_TIOA0		(2 << 2)
-#define			AT91_TC_TC1XC1S_TIOA2		(3 << 2)
-#define		AT91_TC_TC2XC2S		(3 << 4)	/* External Clock Signal 2 Selection */
-#define			AT91_TC_TC2XC2S_TCLK2		(0 << 4)
-#define			AT91_TC_TC2XC2S_NONE		(1 << 4)
-#define			AT91_TC_TC2XC2S_TIOA0		(2 << 4)
-#define			AT91_TC_TC2XC2S_TIOA1		(3 << 4)
+#define AT91_TC_BMR     0xc4        /* TC Block Mode Register */
+#define     AT91_TC_TC0XC0S     (3 << 0)    /* External Clock Signal 0 Selection */
+#define         AT91_TC_TC0XC0S_TCLK0       (0 << 0)
+#define         AT91_TC_TC0XC0S_NONE        (1 << 0)
+#define         AT91_TC_TC0XC0S_TIOA1       (2 << 0)
+#define         AT91_TC_TC0XC0S_TIOA2       (3 << 0)
+#define     AT91_TC_TC1XC1S     (3 << 2)    /* External Clock Signal 1 Selection */
+#define         AT91_TC_TC1XC1S_TCLK1       (0 << 2)
+#define         AT91_TC_TC1XC1S_NONE        (1 << 2)
+#define         AT91_TC_TC1XC1S_TIOA0       (2 << 2)
+#define         AT91_TC_TC1XC1S_TIOA2       (3 << 2)
+#define     AT91_TC_TC2XC2S     (3 << 4)    /* External Clock Signal 2 Selection */
+#define         AT91_TC_TC2XC2S_TCLK2       (0 << 4)
+#define         AT91_TC_TC2XC2S_NONE        (1 << 4)
+#define         AT91_TC_TC2XC2S_TIOA0       (2 << 4)
+#define         AT91_TC_TC2XC2S_TIOA1       (3 << 4)
 
 
-#define AT91_TC_CCR		0x00		/* Channel Control Register */
-#define		AT91_TC_CLKEN		(1 << 0)	/* Counter Clock Enable Command */
-#define		AT91_TC_CLKDIS		(1 << 1)	/* Counter CLock Disable Command */
-#define		AT91_TC_SWTRG		(1 << 2)	/* Software Trigger Command */
+#define AT91_TC_CCR     0x00        /* Channel Control Register */
+#define     AT91_TC_CLKEN       (1 << 0)    /* Counter Clock Enable Command */
+#define     AT91_TC_CLKDIS      (1 << 1)    /* Counter CLock Disable Command */
+#define     AT91_TC_SWTRG       (1 << 2)    /* Software Trigger Command */
 
-#define AT91_TC_CMR		0x04		/* Channel Mode Register */
-#define		AT91_TC_TCCLKS		(7 << 0)	/* Capture/Waveform Mode: Clock Selection */
-#define			AT91_TC_TIMER_CLOCK1		(0 << 0)
-#define			AT91_TC_TIMER_CLOCK2		(1 << 0)
-#define			AT91_TC_TIMER_CLOCK3		(2 << 0)
-#define			AT91_TC_TIMER_CLOCK4		(3 << 0)
-#define			AT91_TC_TIMER_CLOCK5		(4 << 0)
-#define			AT91_TC_XC0			(5 << 0)
-#define			AT91_TC_XC1			(6 << 0)
-#define			AT91_TC_XC2			(7 << 0)
-#define		AT91_TC_CLKI		(1 << 3)	/* Capture/Waveform Mode: Clock Invert */
-#define		AT91_TC_BURST		(3 << 4)	/* Capture/Waveform Mode: Burst Signal Selection */
-#define		AT91_TC_LDBSTOP		(1 << 6)	/* Capture Mode: Counter Clock Stopped with TB Loading */
-#define		AT91_TC_LDBDIS		(1 << 7)	/* Capture Mode: Counter Clock Disable with RB Loading */
-#define		AT91_TC_ETRGEDG		(3 << 8)	/* Capture Mode: External Trigger Edge Selection */
-#define		AT91_TC_ABETRG		(1 << 10)	/* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define		AT91_TC_CPCTRG		(1 << 14)	/* Capture Mode: RC Compare Trigger Enable */
-#define		AT91_TC_WAVE		(1 << 15)	/* Capture/Waveform mode */
-#define		AT91_TC_LDRA		(3 << 16)	/* Capture Mode: RA Loading Selection */
-#define		AT91_TC_LDRB		(3 << 18)	/* Capture Mode: RB Loading Selection */
+#define AT91_TC_CMR     0x04        /* Channel Mode Register */
+#define     AT91_TC_TCCLKS      (7 << 0)    /* Capture/Waveform Mode: Clock Selection */
+#define         AT91_TC_TIMER_CLOCK1        (0 << 0)
+#define         AT91_TC_TIMER_CLOCK2        (1 << 0)
+#define         AT91_TC_TIMER_CLOCK3        (2 << 0)
+#define         AT91_TC_TIMER_CLOCK4        (3 << 0)
+#define         AT91_TC_TIMER_CLOCK5        (4 << 0)
+#define         AT91_TC_XC0         (5 << 0)
+#define         AT91_TC_XC1         (6 << 0)
+#define         AT91_TC_XC2         (7 << 0)
+#define     AT91_TC_CLKI        (1 << 3)    /* Capture/Waveform Mode: Clock Invert */
+#define     AT91_TC_BURST       (3 << 4)    /* Capture/Waveform Mode: Burst Signal Selection */
+#define     AT91_TC_LDBSTOP     (1 << 6)    /* Capture Mode: Counter Clock Stopped with TB Loading */
+#define     AT91_TC_LDBDIS      (1 << 7)    /* Capture Mode: Counter Clock Disable with RB Loading */
+#define     AT91_TC_ETRGEDG     (3 << 8)    /* Capture Mode: External Trigger Edge Selection */
+#define     AT91_TC_ABETRG      (1 << 10)   /* Capture Mode: TIOA or TIOB External Trigger Selection */
+#define     AT91_TC_CPCTRG      (1 << 14)   /* Capture Mode: RC Compare Trigger Enable */
+#define     AT91_TC_WAVE        (1 << 15)   /* Capture/Waveform mode */
+#define     AT91_TC_LDRA        (3 << 16)   /* Capture Mode: RA Loading Selection */
+#define     AT91_TC_LDRB        (3 << 18)   /* Capture Mode: RB Loading Selection */
 
-#define		AT91_TC_CPCSTOP		(1 <<  6)	/* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define		AT91_TC_CPCDIS		(1 <<  7)	/* Waveform Mode: Counter Clock Disable with RC Compare */
-#define		AT91_TC_EEVTEDG		(3 <<  8)	/* Waveform Mode: External Event Edge Selection */
-#define			AT91_TC_EEVTEDG_NONE		(0 << 8)
-#define			AT91_TC_EEVTEDG_RISING		(1 << 8)
-#define			AT91_TC_EEVTEDG_FALLING		(2 << 8)
-#define			AT91_TC_EEVTEDG_BOTH		(3 << 8)
-#define		AT91_TC_EEVT		(3 << 10)	/* Waveform Mode: External Event Selection */
-#define			AT91_TC_EEVT_TIOB		(0 << 10)
-#define			AT91_TC_EEVT_XC0		(1 << 10)
-#define			AT91_TC_EEVT_XC1		(2 << 10)
-#define			AT91_TC_EEVT_XC2		(3 << 10)
-#define		AT91_TC_ENETRG		(1 << 12)	/* Waveform Mode: External Event Trigger Enable */
-#define		AT91_TC_WAVESEL		(3 << 13)	/* Waveform Mode: Waveform Selection */
-#define			AT91_TC_WAVESEL_UP		(0 << 13)
-#define			AT91_TC_WAVESEL_UP_AUTO		(2 << 13)
-#define			AT91_TC_WAVESEL_UPDOWN		(1 << 13)
-#define			AT91_TC_WAVESEL_UPDOWN_AUTO	(3 << 13)
-#define		AT91_TC_ACPA		(3 << 16)	/* Waveform Mode: RA Compare Effect on TIOA */
-#define			AT91_TC_ACPA_NONE		(0 << 16)
-#define			AT91_TC_ACPA_SET		(1 << 16)
-#define			AT91_TC_ACPA_CLEAR		(2 << 16)
-#define			AT91_TC_ACPA_TOGGLE		(3 << 16)
-#define		AT91_TC_ACPC		(3 << 18)	/* Waveform Mode: RC Compre Effect on TIOA */
-#define			AT91_TC_ACPC_NONE		(0 << 18)
-#define			AT91_TC_ACPC_SET		(1 << 18)
-#define			AT91_TC_ACPC_CLEAR		(2 << 18)
-#define			AT91_TC_ACPC_TOGGLE		(3 << 18)
-#define		AT91_TC_AEEVT		(3 << 20)	/* Waveform Mode: External Event Effect on TIOA */
-#define			AT91_TC_AEEVT_NONE		(0 << 20)
-#define			AT91_TC_AEEVT_SET		(1 << 20)
-#define			AT91_TC_AEEVT_CLEAR		(2 << 20)
-#define			AT91_TC_AEEVT_TOGGLE		(3 << 20)
-#define		AT91_TC_ASWTRG		(3 << 22)	/* Waveform Mode: Software Trigger Effect on TIOA */
-#define			AT91_TC_ASWTRG_NONE		(0 << 22)
-#define			AT91_TC_ASWTRG_SET		(1 << 22)
-#define			AT91_TC_ASWTRG_CLEAR		(2 << 22)
-#define			AT91_TC_ASWTRG_TOGGLE		(3 << 22)
-#define		AT91_TC_BCPB		(3 << 24)	/* Waveform Mode: RB Compare Effect on TIOB */
-#define			AT91_TC_BCPB_NONE		(0 << 24)
-#define			AT91_TC_BCPB_SET		(1 << 24)
-#define			AT91_TC_BCPB_CLEAR		(2 << 24)
-#define			AT91_TC_BCPB_TOGGLE		(3 << 24)
-#define		AT91_TC_BCPC		(3 << 26)	/* Waveform Mode: RC Compare Effect on TIOB */
-#define			AT91_TC_BCPC_NONE		(0 << 26)
-#define			AT91_TC_BCPC_SET		(1 << 26)
-#define			AT91_TC_BCPC_CLEAR		(2 << 26)
-#define			AT91_TC_BCPC_TOGGLE		(3 << 26)
-#define		AT91_TC_BEEVT		(3 << 28)	/* Waveform Mode: External Event Effect on TIOB */
-#define			AT91_TC_BEEVT_NONE		(0 << 28)
-#define			AT91_TC_BEEVT_SET		(1 << 28)
-#define			AT91_TC_BEEVT_CLEAR		(2 << 28)
-#define			AT91_TC_BEEVT_TOGGLE		(3 << 28)
-#define		AT91_TC_BSWTRG		(3 << 30)	/* Waveform Mode: Software Trigger Effect on TIOB */
-#define			AT91_TC_BSWTRG_NONE		(0 << 30)
-#define			AT91_TC_BSWTRG_SET		(1 << 30)
-#define			AT91_TC_BSWTRG_CLEAR		(2 << 30)
-#define			AT91_TC_BSWTRG_TOGGLE		(3 << 30)
+#define     AT91_TC_CPCSTOP     (1 <<  6)   /* Waveform Mode: Counter Clock Stopped with RC Compare */
+#define     AT91_TC_CPCDIS      (1 <<  7)   /* Waveform Mode: Counter Clock Disable with RC Compare */
+#define     AT91_TC_EEVTEDG     (3 <<  8)   /* Waveform Mode: External Event Edge Selection */
+#define         AT91_TC_EEVTEDG_NONE        (0 << 8)
+#define         AT91_TC_EEVTEDG_RISING      (1 << 8)
+#define         AT91_TC_EEVTEDG_FALLING     (2 << 8)
+#define         AT91_TC_EEVTEDG_BOTH        (3 << 8)
+#define     AT91_TC_EEVT        (3 << 10)   /* Waveform Mode: External Event Selection */
+#define         AT91_TC_EEVT_TIOB       (0 << 10)
+#define         AT91_TC_EEVT_XC0        (1 << 10)
+#define         AT91_TC_EEVT_XC1        (2 << 10)
+#define         AT91_TC_EEVT_XC2        (3 << 10)
+#define     AT91_TC_ENETRG      (1 << 12)   /* Waveform Mode: External Event Trigger Enable */
+#define     AT91_TC_WAVESEL     (3 << 13)   /* Waveform Mode: Waveform Selection */
+#define         AT91_TC_WAVESEL_UP      (0 << 13)
+#define         AT91_TC_WAVESEL_UP_AUTO     (2 << 13)
+#define         AT91_TC_WAVESEL_UPDOWN      (1 << 13)
+#define         AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
+#define     AT91_TC_ACPA        (3 << 16)   /* Waveform Mode: RA Compare Effect on TIOA */
+#define         AT91_TC_ACPA_NONE       (0 << 16)
+#define         AT91_TC_ACPA_SET        (1 << 16)
+#define         AT91_TC_ACPA_CLEAR      (2 << 16)
+#define         AT91_TC_ACPA_TOGGLE     (3 << 16)
+#define     AT91_TC_ACPC        (3 << 18)   /* Waveform Mode: RC Compre Effect on TIOA */
+#define         AT91_TC_ACPC_NONE       (0 << 18)
+#define         AT91_TC_ACPC_SET        (1 << 18)
+#define         AT91_TC_ACPC_CLEAR      (2 << 18)
+#define         AT91_TC_ACPC_TOGGLE     (3 << 18)
+#define     AT91_TC_AEEVT       (3 << 20)   /* Waveform Mode: External Event Effect on TIOA */
+#define         AT91_TC_AEEVT_NONE      (0 << 20)
+#define         AT91_TC_AEEVT_SET       (1 << 20)
+#define         AT91_TC_AEEVT_CLEAR     (2 << 20)
+#define         AT91_TC_AEEVT_TOGGLE        (3 << 20)
+#define     AT91_TC_ASWTRG      (3 << 22)   /* Waveform Mode: Software Trigger Effect on TIOA */
+#define         AT91_TC_ASWTRG_NONE     (0 << 22)
+#define         AT91_TC_ASWTRG_SET      (1 << 22)
+#define         AT91_TC_ASWTRG_CLEAR        (2 << 22)
+#define         AT91_TC_ASWTRG_TOGGLE       (3 << 22)
+#define     AT91_TC_BCPB        (3 << 24)   /* Waveform Mode: RB Compare Effect on TIOB */
+#define         AT91_TC_BCPB_NONE       (0 << 24)
+#define         AT91_TC_BCPB_SET        (1 << 24)
+#define         AT91_TC_BCPB_CLEAR      (2 << 24)
+#define         AT91_TC_BCPB_TOGGLE     (3 << 24)
+#define     AT91_TC_BCPC        (3 << 26)   /* Waveform Mode: RC Compare Effect on TIOB */
+#define         AT91_TC_BCPC_NONE       (0 << 26)
+#define         AT91_TC_BCPC_SET        (1 << 26)
+#define         AT91_TC_BCPC_CLEAR      (2 << 26)
+#define         AT91_TC_BCPC_TOGGLE     (3 << 26)
+#define     AT91_TC_BEEVT       (3 << 28)   /* Waveform Mode: External Event Effect on TIOB */
+#define         AT91_TC_BEEVT_NONE      (0 << 28)
+#define         AT91_TC_BEEVT_SET       (1 << 28)
+#define         AT91_TC_BEEVT_CLEAR     (2 << 28)
+#define         AT91_TC_BEEVT_TOGGLE        (3 << 28)
+#define     AT91_TC_BSWTRG      (3 << 30)   /* Waveform Mode: Software Trigger Effect on TIOB */
+#define         AT91_TC_BSWTRG_NONE     (0 << 30)
+#define         AT91_TC_BSWTRG_SET      (1 << 30)
+#define         AT91_TC_BSWTRG_CLEAR        (2 << 30)
+#define         AT91_TC_BSWTRG_TOGGLE       (3 << 30)
 
-#define AT91_TC_CV		0x10		/* Counter Value */
-#define AT91_TC_RA		0x14		/* Register A */
-#define AT91_TC_RB		0x18		/* Register B */
-#define AT91_TC_RC		0x1c		/* Register C */
+#define AT91_TC_CV      0x10        /* Counter Value */
+#define AT91_TC_RA      0x14        /* Register A */
+#define AT91_TC_RB      0x18        /* Register B */
+#define AT91_TC_RC      0x1c        /* Register C */
 
-#define AT91_TC_SR		0x20		/* Status Register */
-#define		AT91_TC_COVFS		(1 <<  0)	/* Counter Overflow Status */
-#define		AT91_TC_LOVRS		(1 <<  1)	/* Load Overrun Status */
-#define		AT91_TC_CPAS		(1 <<  2)	/* RA Compare Status */
-#define		AT91_TC_CPBS		(1 <<  3)	/* RB Compare Status */
-#define		AT91_TC_CPCS		(1 <<  4)	/* RC Compare Status */
-#define		AT91_TC_LDRAS		(1 <<  5)	/* RA Loading Status */
-#define		AT91_TC_LDRBS		(1 <<  6)	/* RB Loading Status */
-#define		AT91_TC_ETRGS		(1 <<  7)	/* External Trigger Status */
-#define		AT91_TC_CLKSTA		(1 << 16)	/* Clock Enabling Status */
-#define		AT91_TC_MTIOA		(1 << 17)	/* TIOA Mirror */
-#define		AT91_TC_MTIOB		(1 << 18)	/* TIOB Mirror */
+#define AT91_TC_SR      0x20        /* Status Register */
+#define     AT91_TC_COVFS       (1 <<  0)   /* Counter Overflow Status */
+#define     AT91_TC_LOVRS       (1 <<  1)   /* Load Overrun Status */
+#define     AT91_TC_CPAS        (1 <<  2)   /* RA Compare Status */
+#define     AT91_TC_CPBS        (1 <<  3)   /* RB Compare Status */
+#define     AT91_TC_CPCS        (1 <<  4)   /* RC Compare Status */
+#define     AT91_TC_LDRAS       (1 <<  5)   /* RA Loading Status */
+#define     AT91_TC_LDRBS       (1 <<  6)   /* RB Loading Status */
+#define     AT91_TC_ETRGS       (1 <<  7)   /* External Trigger Status */
+#define     AT91_TC_CLKSTA      (1 << 16)   /* Clock Enabling Status */
+#define     AT91_TC_MTIOA       (1 << 17)   /* TIOA Mirror */
+#define     AT91_TC_MTIOB       (1 << 18)   /* TIOB Mirror */
 
-#define AT91_TC_IER		0x24		/* Interrupt Enable Register */
-#define AT91_TC_IDR		0x28		/* Interrupt Disable Register */
-#define AT91_TC_IMR		0x2c		/* Interrupt Mask Register */
+#define AT91_TC_IER     0x24        /* Interrupt Enable Register */
+#define AT91_TC_IDR     0x28        /* Interrupt Disable Register */
+#define AT91_TC_IMR     0x2c        /* Interrupt Mask Register */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91sam9260_matrix.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91sam9260_matrix.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -29,67 +15,67 @@
 extern "C" {
 #endif
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define		AT91_MATRIX_ULBT		(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#define AT91_MATRIX_MCFG0   (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1   (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2   (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3   (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4   (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5   (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define     AT91_MATRIX_ULBT        (7 << 0)    /* Undefined Length Burst Type */
+#define         AT91_MATRIX_ULBT_INFINITE   (0 << 0)
+#define         AT91_MATRIX_ULBT_SINGLE     (1 << 0)
+#define         AT91_MATRIX_ULBT_FOUR       (2 << 0)
+#define         AT91_MATRIX_ULBT_EIGHT      (3 << 0)
+#define         AT91_MATRIX_ULBT_SIXTEEN    (4 << 0)
 
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff <<  0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+#define AT91_MATRIX_SCFG0   (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1   (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2   (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3   (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4   (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define     AT91_MATRIX_SLOT_CYCLE      (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define     AT91_MATRIX_DEFMSTR_TYPE    (3    << 16)    /* Default Master Type */
+#define         AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define         AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define         AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define     AT91_MATRIX_FIXED_DEFMSTR   (7    << 18)    /* Fixed Index of Default Master */
+#define     AT91_MATRIX_ARBT        (3    << 24)    /* Arbitration Type */
+#define         AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define         AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
+#define AT91_MATRIX_PRAS0   (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1   (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2   (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3   (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4   (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define     AT91_MATRIX_M0PR        (3 << 0)    /* Master 0 Priority */
+#define     AT91_MATRIX_M1PR        (3 << 4)    /* Master 1 Priority */
+#define     AT91_MATRIX_M2PR        (3 << 8)    /* Master 2 Priority */
+#define     AT91_MATRIX_M3PR        (3 << 12)   /* Master 3 Priority */
+#define     AT91_MATRIX_M4PR        (3 << 16)   /* Master 4 Priority */
+#define     AT91_MATRIX_M5PR        (3 << 20)   /* Master 5 Priority */
 
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_MRCR    (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define     AT91_MATRIX_RCB0        (1 << 0)    /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define     AT91_MATRIX_RCB1        (1 << 1)    /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x11C)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+#define AT91_MATRIX_EBICSA  (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define     AT91_MATRIX_CS1A        (1 << 1)    /* Chip Select 1 Assignment */
+#define         AT91_MATRIX_CS1A_SMC        (0 << 1)
+#define         AT91_MATRIX_CS1A_SDRAMC     (1 << 1)
+#define     AT91_MATRIX_CS3A        (1 << 3)    /* Chip Select 3 Assignment */
+#define         AT91_MATRIX_CS3A_SMC        (0 << 3)
+#define         AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define     AT91_MATRIX_CS4A        (1 << 4)    /* Chip Select 4 Assignment */
+#define         AT91_MATRIX_CS4A_SMC        (0 << 4)
+#define         AT91_MATRIX_CS4A_SMC_CF1    (1 << 4)
+#define     AT91_MATRIX_CS5A        (1 << 5)    /* Chip Select 5 Assignment */
+#define         AT91_MATRIX_CS5A_SMC        (0 << 5)
+#define         AT91_MATRIX_CS5A_SMC_CF2    (1 << 5)
+#define     AT91_MATRIX_DBPUC       (1 << 8)    /* Data Bus Pull-up Configuration */
+#define     AT91_MATRIX_VDDIOMSEL       (1 << 16)   /* Memory voltage selection */
+#define         AT91_MATRIX_VDDIOMSEL_1_8V  (0 << 16)
+#define         AT91_MATRIX_VDDIOMSEL_3_3V  (1 << 16)
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91sam926x.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91sam926x.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -47,169 +33,169 @@ extern "C" {
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Peripherals */
-#define AT91SAM9260_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC	5	/* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0	6	/* USART 0 */
-#define AT91SAM9260_ID_US1	7	/* USART 1 */
-#define AT91SAM9260_ID_US2	8	/* USART 2 */
-#define AT91SAM9260_ID_MCI	9	/* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP	10	/* USB Device Port */
-#define AT91SAM9260_ID_TWI	11	/* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC	14	/* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0	17	/* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1	18	/* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2	19	/* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP	20	/* USB Host port */
-#define AT91SAM9260_ID_EMAC	21	/* Ethernet */
-#define AT91SAM9260_ID_ISI	22	/* Image Sensor Interface */
-#define AT91SAM9260_ID_US3	23	/* USART 3 */
-#define AT91SAM9260_ID_US4	24	/* USART 4 */
-#define AT91SAM9260_ID_US5	25	/* USART 5 */
-#define AT91SAM9260_ID_TC3	26	/* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4	27	/* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5	28	/* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
+#define AT91_ID_FIQ     0   /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS     1   /* System Peripherals */
+#define AT91SAM9260_ID_PIOA 2   /* Parallel IO Controller A */
+#define AT91SAM9260_ID_PIOB 3   /* Parallel IO Controller B */
+#define AT91SAM9260_ID_PIOC 4   /* Parallel IO Controller C */
+#define AT91SAM9260_ID_ADC  5   /* Analog-to-Digital Converter */
+#define AT91SAM9260_ID_US0  6   /* USART 0 */
+#define AT91SAM9260_ID_US1  7   /* USART 1 */
+#define AT91SAM9260_ID_US2  8   /* USART 2 */
+#define AT91SAM9260_ID_MCI  9   /* Multimedia Card Interface */
+#define AT91SAM9260_ID_UDP  10  /* USB Device Port */
+#define AT91SAM9260_ID_TWI  11  /* Two-Wire Interface */
+#define AT91SAM9260_ID_SPI0 12  /* Serial Peripheral Interface 0 */
+#define AT91SAM9260_ID_SPI1 13  /* Serial Peripheral Interface 1 */
+#define AT91SAM9260_ID_SSC  14  /* Serial Synchronous Controller */
+#define AT91SAM9260_ID_TC0  17  /* Timer Counter 0 */
+#define AT91SAM9260_ID_TC1  18  /* Timer Counter 1 */
+#define AT91SAM9260_ID_TC2  19  /* Timer Counter 2 */
+#define AT91SAM9260_ID_UHP  20  /* USB Host port */
+#define AT91SAM9260_ID_EMAC 21  /* Ethernet */
+#define AT91SAM9260_ID_ISI  22  /* Image Sensor Interface */
+#define AT91SAM9260_ID_US3  23  /* USART 3 */
+#define AT91SAM9260_ID_US4  24  /* USART 4 */
+#define AT91SAM9260_ID_US5  25  /* USART 5 */
+#define AT91SAM9260_ID_TC3  26  /* Timer Counter 3 */
+#define AT91SAM9260_ID_TC4  27  /* Timer Counter 4 */
+#define AT91SAM9260_ID_TC5  28  /* Timer Counter 5 */
+#define AT91SAM9260_ID_IRQ0 29  /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9260_ID_IRQ1 30  /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9260_ID_IRQ2 31  /* Advanced Interrupt Controller (IRQ2) */
 
 
 /*
  * User Peripheral physical base addresses.
  */
-#define AT91SAM9260_BASE_TCB0		0xfffa0000
-#define AT91SAM9260_BASE_TC0		0xfffa0000
-#define AT91SAM9260_BASE_TC1		0xfffa0040
-#define AT91SAM9260_BASE_TC2		0xfffa0080
-#define AT91SAM9260_BASE_UDP		0xfffa4000
-#define AT91SAM9260_BASE_MCI		0xfffa8000
-#define AT91SAM9260_BASE_TWI		0xfffac000
-#define AT91SAM9260_BASE_US0		0xfffb0000
-#define AT91SAM9260_BASE_US1		0xfffb4000
-#define AT91SAM9260_BASE_US2		0xfffb8000
-#define AT91SAM9260_BASE_SSC		0xfffbc000
-#define AT91SAM9260_BASE_ISI		0xfffc0000
-#define AT91SAM9260_BASE_EMAC		0xfffc4000
-#define AT91SAM9260_BASE_SPI0		0xfffc8000
-#define AT91SAM9260_BASE_SPI1		0xfffcc000
-#define AT91SAM9260_BASE_US3		0xfffd0000
-#define AT91SAM9260_BASE_US4		0xfffd4000
-#define AT91SAM9260_BASE_US5		0xfffd8000
-#define AT91SAM9260_BASE_TCB1		0xfffdc000
-#define AT91SAM9260_BASE_TC3		0xfffdc000
-#define AT91SAM9260_BASE_TC4		0xfffdc040
-#define AT91SAM9260_BASE_TC5		0xfffdc080
-#define AT91SAM9260_BASE_ADC		0xfffe0000
-#define AT91_BASE_SYS				0xffffe800
-#define AT91SAM9260_BASE_DBGU		0xfffff200
+#define AT91SAM9260_BASE_TCB0       0xfffa0000
+#define AT91SAM9260_BASE_TC0        0xfffa0000
+#define AT91SAM9260_BASE_TC1        0xfffa0040
+#define AT91SAM9260_BASE_TC2        0xfffa0080
+#define AT91SAM9260_BASE_UDP        0xfffa4000
+#define AT91SAM9260_BASE_MCI        0xfffa8000
+#define AT91SAM9260_BASE_TWI        0xfffac000
+#define AT91SAM9260_BASE_US0        0xfffb0000
+#define AT91SAM9260_BASE_US1        0xfffb4000
+#define AT91SAM9260_BASE_US2        0xfffb8000
+#define AT91SAM9260_BASE_SSC        0xfffbc000
+#define AT91SAM9260_BASE_ISI        0xfffc0000
+#define AT91SAM9260_BASE_EMAC       0xfffc4000
+#define AT91SAM9260_BASE_SPI0       0xfffc8000
+#define AT91SAM9260_BASE_SPI1       0xfffcc000
+#define AT91SAM9260_BASE_US3        0xfffd0000
+#define AT91SAM9260_BASE_US4        0xfffd4000
+#define AT91SAM9260_BASE_US5        0xfffd8000
+#define AT91SAM9260_BASE_TCB1       0xfffdc000
+#define AT91SAM9260_BASE_TC3        0xfffdc000
+#define AT91SAM9260_BASE_TC4        0xfffdc040
+#define AT91SAM9260_BASE_TC5        0xfffdc080
+#define AT91SAM9260_BASE_ADC        0xfffe0000
+#define AT91_BASE_SYS               0xffffe800
+#define AT91SAM9260_BASE_DBGU       0xfffff200
 
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)
+#define AT91_ECC    (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC    (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG   (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC    (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU   (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA   (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB   (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC   (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC    (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC   (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC  (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT    (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT    (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT    (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR   (0xfffffd50 - AT91_BASE_SYS)
 
 
 /*
  * Internal Memory.
  */
-#define AT91SAM9260_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
+#define AT91SAM9260_ROM_BASE    0x00100000  /* Internal ROM base address */
+#define AT91SAM9260_ROM_SIZE    SZ_32K      /* Internal ROM size (32Kb) */
 
-#define AT91SAM9260_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE	SZ_4K		/* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE	SZ_4K		/* Internal SRAM 1 size (4Kb) */
+#define AT91SAM9260_SRAM0_BASE  0x00200000  /* Internal SRAM 0 base address */
+#define AT91SAM9260_SRAM0_SIZE  SZ_4K       /* Internal SRAM 0 size (4Kb) */
+#define AT91SAM9260_SRAM1_BASE  0x00300000  /* Internal SRAM 1 base address */
+#define AT91SAM9260_SRAM1_SIZE  SZ_4K       /* Internal SRAM 1 size (4Kb) */
 
-#define AT91SAM9260_UHP_BASE	0x00500000	/* USB Host controller */
+#define AT91SAM9260_UHP_BASE    0x00500000  /* USB Host controller */
 
-#define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */
+#define AT91SAM9XE_FLASH_BASE   0x00200000  /* Internal FLASH base address */
+#define AT91SAM9XE_SRAM_BASE    0x00300000  /* Internal SRAM base address */
 
-#define AT91SAM9G20_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9G20_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
+#define AT91SAM9G20_ROM_BASE    0x00100000  /* Internal ROM base address */
+#define AT91SAM9G20_ROM_SIZE    SZ_32K      /* Internal ROM size (32Kb) */
 
-#define AT91SAM9G20_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9G20_SRAM0_SIZE	SZ_16K		/* Internal SRAM 0 size (16Kb) */
-#define AT91SAM9G20_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9G20_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */
+#define AT91SAM9G20_SRAM0_BASE  0x00200000  /* Internal SRAM 0 base address */
+#define AT91SAM9G20_SRAM0_SIZE  SZ_16K      /* Internal SRAM 0 size (16Kb) */
+#define AT91SAM9G20_SRAM1_BASE  0x00300000  /* Internal SRAM 1 base address */
+#define AT91SAM9G20_SRAM1_SIZE  SZ_16K      /* Internal SRAM 1 size (16Kb) */
 
-#define AT91SAM9G20_UHP_BASE	0x00500000	/* USB Host controller */
+#define AT91SAM9G20_UHP_BASE    0x00500000  /* USB Host controller */
 
 
 
 /* Serial ports */
-#define ATMEL_MAX_UART		7		/* 6 USART3's and one DBGU port (SAM9260) */
+#define ATMEL_MAX_UART      7       /* 6 USART3's and one DBGU port (SAM9260) */
 
 /* External Memory Map */
-#define AT91_CHIPSELECT_0	0x10000000
-#define AT91_CHIPSELECT_1	0x20000000
-#define AT91_CHIPSELECT_2	0x30000000
-#define AT91_CHIPSELECT_3	0x40000000
-#define AT91_CHIPSELECT_4	0x50000000
-#define AT91_CHIPSELECT_5	0x60000000
-#define AT91_CHIPSELECT_6	0x70000000
-#define AT91_CHIPSELECT_7	0x80000000
+#define AT91_CHIPSELECT_0   0x10000000
+#define AT91_CHIPSELECT_1   0x20000000
+#define AT91_CHIPSELECT_2   0x30000000
+#define AT91_CHIPSELECT_3   0x40000000
+#define AT91_CHIPSELECT_4   0x50000000
+#define AT91_CHIPSELECT_5   0x60000000
+#define AT91_CHIPSELECT_6   0x70000000
+#define AT91_CHIPSELECT_7   0x80000000
 
 /* SDRAM */
-#define AT91_SDRAM_BASE		AT91_CHIPSELECT_1
+#define AT91_SDRAM_BASE     AT91_CHIPSELECT_1
 
 /* Clocks */
-#define AT91_SLOW_CLOCK		32768		/* slow clock */
+#define AT91_SLOW_CLOCK     32768       /* slow clock */
 
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE		0x10
-#define FIQMODE			0x11
-#define IRQMODE			0x12
-#define SVCMODE			0x13
-#define ABORTMODE		0x17
-#define UNDEFMODE		0x1b
-#define MODEMASK		0x1f
-#define NOINT			0xc0
+#define USERMODE        0x10
+#define FIQMODE         0x11
+#define IRQMODE         0x12
+#define SVCMODE         0x13
+#define ABORTMODE       0x17
+#define UNDEFMODE       0x1b
+#define MODEMASK        0x1f
+#define NOINT           0xc0
 
 struct rt_hw_register
 {
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t cpsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t cpsr;
+    rt_uint32_t ORIG_r0;
 };
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))

bsp/at91sam9260/platform/gpio.h

@@ -1,21 +1,7 @@
 /*
- * File      : gpio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,117 +14,117 @@
 #include <rtthread.h>
 #include <at91_aic.h>
 
-#define PIN_BASE		AIC_IRQS
+#define PIN_BASE        AIC_IRQS
 
-#define MAX_GPIO_BANKS		3
+#define MAX_GPIO_BANKS      3
 
-#define PIN_IRQS	(MAX_GPIO_BANKS*32)
+#define PIN_IRQS    (MAX_GPIO_BANKS*32)
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
-#define	AT91_PIN_PA0	(PIN_BASE + 0x00 + 0)
-#define	AT91_PIN_PA1	(PIN_BASE + 0x00 + 1)
-#define	AT91_PIN_PA2	(PIN_BASE + 0x00 + 2)
-#define	AT91_PIN_PA3	(PIN_BASE + 0x00 + 3)
-#define	AT91_PIN_PA4	(PIN_BASE + 0x00 + 4)
-#define	AT91_PIN_PA5	(PIN_BASE + 0x00 + 5)
-#define	AT91_PIN_PA6	(PIN_BASE + 0x00 + 6)
-#define	AT91_PIN_PA7	(PIN_BASE + 0x00 + 7)
-#define	AT91_PIN_PA8	(PIN_BASE + 0x00 + 8)
-#define	AT91_PIN_PA9	(PIN_BASE + 0x00 + 9)
-#define	AT91_PIN_PA10	(PIN_BASE + 0x00 + 10)
-#define	AT91_PIN_PA11	(PIN_BASE + 0x00 + 11)
-#define	AT91_PIN_PA12	(PIN_BASE + 0x00 + 12)
-#define	AT91_PIN_PA13	(PIN_BASE + 0x00 + 13)
-#define	AT91_PIN_PA14	(PIN_BASE + 0x00 + 14)
-#define	AT91_PIN_PA15	(PIN_BASE + 0x00 + 15)
-#define	AT91_PIN_PA16	(PIN_BASE + 0x00 + 16)
-#define	AT91_PIN_PA17	(PIN_BASE + 0x00 + 17)
-#define	AT91_PIN_PA18	(PIN_BASE + 0x00 + 18)
-#define	AT91_PIN_PA19	(PIN_BASE + 0x00 + 19)
-#define	AT91_PIN_PA20	(PIN_BASE + 0x00 + 20)
-#define	AT91_PIN_PA21	(PIN_BASE + 0x00 + 21)
-#define	AT91_PIN_PA22	(PIN_BASE + 0x00 + 22)
-#define	AT91_PIN_PA23	(PIN_BASE + 0x00 + 23)
-#define	AT91_PIN_PA24	(PIN_BASE + 0x00 + 24)
-#define	AT91_PIN_PA25	(PIN_BASE + 0x00 + 25)
-#define	AT91_PIN_PA26	(PIN_BASE + 0x00 + 26)
-#define	AT91_PIN_PA27	(PIN_BASE + 0x00 + 27)
-#define	AT91_PIN_PA28	(PIN_BASE + 0x00 + 28)
-#define	AT91_PIN_PA29	(PIN_BASE + 0x00 + 29)
-#define	AT91_PIN_PA30	(PIN_BASE + 0x00 + 30)
-#define	AT91_PIN_PA31	(PIN_BASE + 0x00 + 31)
+#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
 
-#define	AT91_PIN_PB0	(PIN_BASE + 0x20 + 0)
-#define	AT91_PIN_PB1	(PIN_BASE + 0x20 + 1)
-#define	AT91_PIN_PB2	(PIN_BASE + 0x20 + 2)
-#define	AT91_PIN_PB3	(PIN_BASE + 0x20 + 3)
-#define	AT91_PIN_PB4	(PIN_BASE + 0x20 + 4)
-#define	AT91_PIN_PB5	(PIN_BASE + 0x20 + 5)
-#define	AT91_PIN_PB6	(PIN_BASE + 0x20 + 6)
-#define	AT91_PIN_PB7	(PIN_BASE + 0x20 + 7)
-#define	AT91_PIN_PB8	(PIN_BASE + 0x20 + 8)
-#define	AT91_PIN_PB9	(PIN_BASE + 0x20 + 9)
-#define	AT91_PIN_PB10	(PIN_BASE + 0x20 + 10)
-#define	AT91_PIN_PB11	(PIN_BASE + 0x20 + 11)
-#define	AT91_PIN_PB12	(PIN_BASE + 0x20 + 12)
-#define	AT91_PIN_PB13	(PIN_BASE + 0x20 + 13)
-#define	AT91_PIN_PB14	(PIN_BASE + 0x20 + 14)
-#define	AT91_PIN_PB15	(PIN_BASE + 0x20 + 15)
-#define	AT91_PIN_PB16	(PIN_BASE + 0x20 + 16)
-#define	AT91_PIN_PB17	(PIN_BASE + 0x20 + 17)
-#define	AT91_PIN_PB18	(PIN_BASE + 0x20 + 18)
-#define	AT91_PIN_PB19	(PIN_BASE + 0x20 + 19)
-#define	AT91_PIN_PB20	(PIN_BASE + 0x20 + 20)
-#define	AT91_PIN_PB21	(PIN_BASE + 0x20 + 21)
-#define	AT91_PIN_PB22	(PIN_BASE + 0x20 + 22)
-#define	AT91_PIN_PB23	(PIN_BASE + 0x20 + 23)
-#define	AT91_PIN_PB24	(PIN_BASE + 0x20 + 24)
-#define	AT91_PIN_PB25	(PIN_BASE + 0x20 + 25)
-#define	AT91_PIN_PB26	(PIN_BASE + 0x20 + 26)
-#define	AT91_PIN_PB27	(PIN_BASE + 0x20 + 27)
-#define	AT91_PIN_PB28	(PIN_BASE + 0x20 + 28)
-#define	AT91_PIN_PB29	(PIN_BASE + 0x20 + 29)
-#define	AT91_PIN_PB30	(PIN_BASE + 0x20 + 30)
-#define	AT91_PIN_PB31	(PIN_BASE + 0x20 + 31)
+#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
 
-#define	AT91_PIN_PC0	(PIN_BASE + 0x40 + 0)
-#define	AT91_PIN_PC1	(PIN_BASE + 0x40 + 1)
-#define	AT91_PIN_PC2	(PIN_BASE + 0x40 + 2)
-#define	AT91_PIN_PC3	(PIN_BASE + 0x40 + 3)
-#define	AT91_PIN_PC4	(PIN_BASE + 0x40 + 4)
-#define	AT91_PIN_PC5	(PIN_BASE + 0x40 + 5)
-#define	AT91_PIN_PC6	(PIN_BASE + 0x40 + 6)
-#define	AT91_PIN_PC7	(PIN_BASE + 0x40 + 7)
-#define	AT91_PIN_PC8	(PIN_BASE + 0x40 + 8)
-#define	AT91_PIN_PC9	(PIN_BASE + 0x40 + 9)
-#define	AT91_PIN_PC10	(PIN_BASE + 0x40 + 10)
-#define	AT91_PIN_PC11	(PIN_BASE + 0x40 + 11)
-#define	AT91_PIN_PC12	(PIN_BASE + 0x40 + 12)
-#define	AT91_PIN_PC13	(PIN_BASE + 0x40 + 13)
-#define	AT91_PIN_PC14	(PIN_BASE + 0x40 + 14)
-#define	AT91_PIN_PC15	(PIN_BASE + 0x40 + 15)
-#define	AT91_PIN_PC16	(PIN_BASE + 0x40 + 16)
-#define	AT91_PIN_PC17	(PIN_BASE + 0x40 + 17)
-#define	AT91_PIN_PC18	(PIN_BASE + 0x40 + 18)
-#define	AT91_PIN_PC19	(PIN_BASE + 0x40 + 19)
-#define	AT91_PIN_PC20	(PIN_BASE + 0x40 + 20)
-#define	AT91_PIN_PC21	(PIN_BASE + 0x40 + 21)
-#define	AT91_PIN_PC22	(PIN_BASE + 0x40 + 22)
-#define	AT91_PIN_PC23	(PIN_BASE + 0x40 + 23)
-#define	AT91_PIN_PC24	(PIN_BASE + 0x40 + 24)
-#define	AT91_PIN_PC25	(PIN_BASE + 0x40 + 25)
-#define	AT91_PIN_PC26	(PIN_BASE + 0x40 + 26)
-#define	AT91_PIN_PC27	(PIN_BASE + 0x40 + 27)
-#define	AT91_PIN_PC28	(PIN_BASE + 0x40 + 28)
-#define	AT91_PIN_PC29	(PIN_BASE + 0x40 + 29)
-#define	AT91_PIN_PC30	(PIN_BASE + 0x40 + 30)
-#define	AT91_PIN_PC31	(PIN_BASE + 0x40 + 31)
+#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
 
 
 rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
 {
-	return gpio;
+    return gpio;
 }
 
 #endif

bsp/at91sam9260/platform/interrupt.c

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -189,7 +175,7 @@ static void at91_gpio_irq_init()
         rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
         irq_desc[idx].counter = 0;
 #endif
-		idx++;
+        idx++;
     }
 
     rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
@@ -322,7 +308,7 @@ void rt_hw_interrupt_umask(int irq)
  * @param name the interrupt name
  * @return old handler
  */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
                                     void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
@@ -336,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
             irq_desc[vector].param = param;
 #ifdef RT_USING_INTERRUPT_INFO
             rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
-			irq_desc[vector].counter = 0;
+            irq_desc[vector].counter = 0;
 #endif
         }
     }
@@ -414,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
 #ifdef RT_USING_INTERRUPT_INFO
 void list_irq(void)
 {
-	int irq;
-
-	rt_kprintf("number\tcount\tname\n");
-	for (irq = 0; irq < MAX_HANDLERS; irq++)
-	{
-		if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
-		{
-			rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
-		}
-	}
+    int irq;
+
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
 }
 
 #include <finsh.h>

bsp/at91sam9260/platform/interrupt.h

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at91sam9260/platform/io.h

@@ -1,21 +1,7 @@
 /*
- * File      : io.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,31 +11,31 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define AT91_BASE_SYS			0xffffe800
+#define AT91_BASE_SYS           0xffffe800
 
-#define IO_SPACE_LIMIT		0xFFFFFFFF
+#define IO_SPACE_LIMIT      0xFFFFFFFF
 
-#define readb(a)	(*(volatile unsigned char  *)(a))
-#define readw(a)	(*(volatile unsigned short *)(a))
-#define readl(a)	(*(volatile unsigned int   *)(a))
+#define readb(a)    (*(volatile unsigned char  *)(a))
+#define readw(a)    (*(volatile unsigned short *)(a))
+#define readl(a)    (*(volatile unsigned int   *)(a))
 
-#define writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
-#define writew(v,a)	(*(volatile unsigned short *)(a) = (v))
-#define writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
+#define writeb(v,a) (*(volatile unsigned char  *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int   *)(a) = (v))
 
 
 rt_inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
-	unsigned int  addr = AT91_BASE_SYS;
+    unsigned int  addr = AT91_BASE_SYS;
 
-	return readl(addr + reg_offset);
+    return readl(addr + reg_offset);
 }
 
 rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 {
-	unsigned int addr = AT91_BASE_SYS;
+    unsigned int addr = AT91_BASE_SYS;
 
-	writel(value, addr + reg_offset);
+    writel(value, addr + reg_offset);
 }
 
 

bsp/at91sam9260/platform/irq.h

@@ -1,27 +1,13 @@
 /*
- * File      : irq.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-01-13     weety      first version
  */
- 
+
 #ifndef __IRQ_H__
 #define __IRQ_H__
 
@@ -32,18 +18,18 @@ extern "C" {
 /*
  * IRQ line status.
  *
- * Bits 0-7 are reserved 
+ * Bits 0-7 are reserved
  *
  * IRQ types
  */
-#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
-#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
-#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
+#define IRQ_TYPE_NONE       0x00000000  /* Default, unspecified type */
+#define IRQ_TYPE_EDGE_RISING    0x00000001  /* Edge rising type */
+#define IRQ_TYPE_EDGE_FALLING   0x00000002  /* Edge falling type */
 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
-#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
-#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
-#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */
+#define IRQ_TYPE_LEVEL_HIGH 0x00000004  /* Level high type */
+#define IRQ_TYPE_LEVEL_LOW  0x00000008  /* Level low type */
+#define IRQ_TYPE_SENSE_MASK 0x0000000f  /* Mask of the above */
+#define IRQ_TYPE_PROBE      0x00000010  /* Probing in progress */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/reset.c

@@ -1,21 +1,7 @@
 /*
- * File      : reset.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,12 +19,12 @@
 
 void machine_reset(void)
 {
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+    at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
 void machine_shutdown(void)
 {
-	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+    at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 }
 
 #ifdef RT_USING_FINSH
@@ -49,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
 #ifdef FINSH_USING_MSH
 int cmd_reset(int argc, char** argv)
 {
-	rt_hw_cpu_reset();
-	return 0;
+    rt_hw_cpu_reset();
+    return 0;
 }
 
 int cmd_shutdown(int argc, char** argv)
 {
-	rt_hw_cpu_shutdown();
-	return 0;
+    rt_hw_cpu_shutdown();
+    return 0;
 }
 
 FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);

bsp/at91sam9260/platform/rt_low_level_init.c

@@ -1,29 +1,15 @@
 /*
- * File      : rt_low_level_init.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 /* write register a=address, v=value */
-#define write_reg(a,v)	    (*(volatile unsigned int *)(a) = (v))
+#define write_reg(a,v)      (*(volatile unsigned int *)(a) = (v))
 /* Processor Reset */
 #define AT91_RSTC_PROCRST   (1 << 0)
 #define AT91_RSTC_PERRST    (1 << 2)

bsp/at91sam9260/platform/rt_low_level_init.h

@@ -1,21 +1,7 @@
 /*
- * File      : rt_low_level_init.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,7 +9,7 @@
  */
 #ifndef __RT_LOW_LEVEL_INIT_H__
 #define __RT_LOW_LEVEL_INIT_H__
- 
+
 /*-------- Stack size of CPU modes -------------------------------------------*/
 #define UND_STK_SIZE 512
 #define SVC_STK_SIZE 4096

bsp/at91sam9260/platform/system_clock.c

@@ -1,21 +1,7 @@
 /*
- * File      : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,270 +14,270 @@
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk clk32k = {
-	"clk32k",
-	AT91_SLOW_CLOCK,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "clk32k",
+    AT91_SLOW_CLOCK,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk main_clk = {
-	"main",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "main",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk plla = {
-	"plla",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "plla",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk mck = {
-	"mck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "mck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk uhpck = {
-	"uhpck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "uhpck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk pllb = {
-	"pllb",
-	0,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "pllb",
+    0,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk udpck = {
-	"udpck",
-	0,
-	&pllb,
-	{RT_NULL, RT_NULL},
+    "udpck",
+    0,
+    &pllb,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk *const standard_pmc_clocks[] = {
-	/* four primary clocks */
-	&clk32k,
-	&main_clk,
-	&plla,
+    /* four primary clocks */
+    &clk32k,
+    &main_clk,
+    &plla,
 
-	/* MCK */
-	&mck
+    /* MCK */
+    &mck
 };
 
 /* clocks cannot be de-registered no refcounting necessary */
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
-
-	return RT_NULL;
+    struct clk *clk;
+    rt_list_t *list;
+
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	flags;
-	rt_uint32_t	rate;
-
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return rate;
+    rt_uint32_t flags;
+    rt_uint32_t rate;
+
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return rate;
 }
 
 static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	unsigned mul, div;
+    unsigned mul, div;
 
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
+    div = reg & 0xff;
+    mul = (reg >> 16) & 0x7ff;
+    if (div && mul) {
+        freq /= div;
+        freq *= mul + 1;
+    } else
+        freq = 0;
 
-	return freq;
+    return freq;
 }
 
 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 {
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	/* PLL output max 240 MHz (or 180 MHz per errata) */
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		/*
-		 * PLL input between 1MHz and 32MHz per spec, but lower
-		 * frequences seem necessary in some cases so allow 100K.
-		 * Warning: some newer products need 2MHz min.
-		 */
-		input = main_freq / i;
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
+    unsigned i, div = 0, mul = 0, diff = 1 << 30;
+    unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+    /* PLL output max 240 MHz (or 180 MHz per errata) */
+    if (out_freq > 240000000)
+        goto fail;
+
+    for (i = 1; i < 256; i++) {
+        int diff1;
+        unsigned input, mul1;
+
+        /*
+         * PLL input between 1MHz and 32MHz per spec, but lower
+         * frequences seem necessary in some cases so allow 100K.
+         * Warning: some newer products need 2MHz min.
+         */
+        input = main_freq / i;
+        if (input < 100000)
+            continue;
+        if (input > 32000000)
+            continue;
+
+        mul1 = out_freq / input;
+        if (mul1 > 2048)
+            continue;
+        if (mul1 < 2)
+            goto fail;
+
+        diff1 = out_freq - input * mul1;
+        if (diff1 < 0)
+            diff1 = -diff1;
+        if (diff > diff1) {
+            diff = diff1;
+            div = i;
+            mul = mul1;
+            if (diff == 0)
+                break;
+        }
+    }
+    if (i == 256 && diff > (out_freq >> 5))
+        goto fail;
+    return ret | ((mul - 1) << 16) | div;
 fail:
-	return 0;
+    return 0;
 }
 
 static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	if (pll == &pllb && (reg & AT91_PMC_USB96M))
-		return freq / 2;
-	else
-		return freq;
+    if (pll == &pllb && (reg & AT91_PMC_USB96M))
+        return freq / 2;
+    else
+        return freq;
 }
 
 
 /* PLLB generated USB full speed clock init */
 static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
 {
-	rt_uint32_t at91_pllb_usb_init;
-	/*
-	 * USB clock init:  choose 48 MHz PLLB value,
-	 * disable 48MHz clock during usb peripheral suspend.
-	 *
-	 * REVISIT:  assumes MCK doesn't derive from PLLB!
-	 */
-	uhpck.parent = &pllb;
-
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
-	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-	
-	at91_sys_write(AT91_CKGR_PLLBR, 0);
-
-	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    rt_uint32_t at91_pllb_usb_init;
+    /*
+     * USB clock init:  choose 48 MHz PLLB value,
+     * disable 48MHz clock during usb peripheral suspend.
+     *
+     * REVISIT:  assumes MCK doesn't derive from PLLB!
+     */
+    uhpck.parent = &pllb;
+
+    at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+    pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+
+    at91_sys_write(AT91_CKGR_PLLBR, 0);
+
+    udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 }
 
 static struct clk *at91_css_to_clk(unsigned long css)
 {
-	switch (css) {
-		case AT91_PMC_CSS_SLOW:
-			return &clk32k;
-		case AT91_PMC_CSS_MAIN:
-			return &main_clk;
-		case AT91_PMC_CSS_PLLA:
-			return &plla;
-		case AT91_PMC_CSS_PLLB:
-			return &pllb;
-	}
-
-	return RT_NULL;
+    switch (css) {
+        case AT91_PMC_CSS_SLOW:
+            return &clk32k;
+        case AT91_PMC_CSS_MAIN:
+            return &main_clk;
+        case AT91_PMC_CSS_PLLA:
+            return &plla;
+        case AT91_PMC_CSS_PLLB:
+            return &pllb;
+    }
+
+    return RT_NULL;
 }
 
 #define false 0
 #define true  1
 int at91_clock_init(rt_uint32_t main_clock)
 {
-	unsigned tmp, freq, mckr;
-	int i;
-	int pll_overclock = false;
-
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = at91_sys_read(AT91_CKGR_MCFR);
-		} while (!(tmp & AT91_PMC_MAINRDY));
-		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
-	}
-	main_clk.rate_hz = main_clock;
-
-	/* report if PLLA is more than mildly overclocked */
-	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-	if (plla.rate_hz > 209000000)
-		pll_overclock = true;
-	if (pll_overclock)
-		;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
-	at91_pllb_usbfs_clock_init(main_clock);
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = at91_sys_read(AT91_PMC_MCKR);
-	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
-	freq = mck.parent->rate_hz;
-	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				/* prescale */
-	
-	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
-
-	/* Register the PMC's standard clocks */
-	rt_list_init(&clocks);
-	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
-
-	rt_list_insert_after(&clocks, &pllb.node);
-	rt_list_insert_after(&clocks, &uhpck.node);
-	rt_list_insert_after(&clocks, &udpck.node);
-
-	/* MCK and CPU clock are "always on" */
-	//clk_enable(&mck);
-
-	/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-		(unsigned) main_clock / 1000000,
-		((unsigned) main_clock % 1000000) / 1000);*///cause blocked
-
-	return 0;
+    unsigned tmp, freq, mckr;
+    int i;
+    int pll_overclock = false;
+
+    /*
+     * When the bootloader initialized the main oscillator correctly,
+     * there's no problem using the cycle counter.  But if it didn't,
+     * or when using oscillator bypass mode, we must be told the speed
+     * of the main clock.
+     */
+    if (!main_clock) {
+        do {
+            tmp = at91_sys_read(AT91_CKGR_MCFR);
+        } while (!(tmp & AT91_PMC_MAINRDY));
+        main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+    }
+    main_clk.rate_hz = main_clock;
+
+    /* report if PLLA is more than mildly overclocked */
+    plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+    if (plla.rate_hz > 209000000)
+        pll_overclock = true;
+    if (pll_overclock)
+        ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+
+    at91_pllb_usbfs_clock_init(main_clock);
+
+    /*
+     * MCK and CPU derive from one of those primary clocks.
+     * For now, assume this parentage won't change.
+     */
+    mckr = at91_sys_read(AT91_PMC_MCKR);
+    mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+    freq = mck.parent->rate_hz;
+    freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));               /* prescale */
+
+    mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+
+    /* Register the PMC's standard clocks */
+    rt_list_init(&clocks);
+    for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+        rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+    rt_list_insert_after(&clocks, &pllb.node);
+    rt_list_insert_after(&clocks, &uhpck.node);
+    rt_list_insert_after(&clocks, &udpck.node);
+
+    /* MCK and CPU clock are "always on" */
+    //clk_enable(&mck);
+
+    /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+        freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+        (unsigned) main_clock / 1000000,
+        ((unsigned) main_clock % 1000000) / 1000);*///cause blocked
+
+    return 0;
 }
 
 /**
@@ -299,6 +285,6 @@ int at91_clock_init(rt_uint32_t main_clock)
  */
 void rt_hw_clock_init(void)
 {
-	at91_clock_init(18432000);
+    at91_clock_init(18432000);
 }
 

bsp/at91sam9g45/applications/application.c

@@ -1,25 +1,11 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 /**
@@ -49,106 +35,106 @@ static int rt_led_app_init(void);
 RT_WEAK int main(void)
 {
 #ifdef RT_USING_SDIO
-	int timeout = 0;
+    int timeout = 0;
 #endif
 
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
+    {
 #if defined(RT_USING_DFS_ROMFS)
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
+        if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+        {
+            rt_kprintf("ROM File System initialized!\n");
+        }
+        else
+            rt_kprintf("ROM File System initialzation failed!\n");
 #endif
 
 #if defined(RT_USING_DFS_UFFS)
-	{
-		/* mount flash device as flash directory */
-		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-	}
+    {
+        /* mount flash device as flash directory */
+        if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+            rt_kprintf("UFFS File System initialized!\n");
+        else
+            rt_kprintf("UFFS File System initialzation failed!\n");
+    }
 #endif
 
 #ifdef RT_USING_SDIO
-	timeout = 0;
-	while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
-	{
-		rt_thread_delay(1);
-	}
-
-	if (timeout < RT_TICK_PER_SECOND*2)
-	{
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
-	}
-	else
-	{
-		rt_kprintf("No SD card found.\n");
-	}
+    timeout = 0;
+    while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
+    {
+        rt_thread_delay(1);
+    }
+
+    if (timeout < RT_TICK_PER_SECOND*2)
+    {
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+        {
+            rt_kprintf("File System initialized!\n");
+        }
+        else
+            rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
+    }
+    else
+    {
+        rt_kprintf("No SD card found.\n");
+    }
 #endif
-	}
+    }
 #endif
 
-	rt_led_app_init();
+    rt_led_app_init();
 }
 
 #ifdef RT_USING_LED
 void rt_led_thread_entry(void* parameter)
 {
-	rt_uint8_t cnt = 0;
-	led_init();
-	while(1)
-	{
-		/* light on leds for one second */
-		rt_thread_delay(40);
-		cnt++;
-		if (cnt&0x01)
-			led_on(1);
-		else
-			led_off(1);
-		if (cnt&0x02)
-			led_on(2);
-		else
-			led_off(2);
-		if (cnt&0x04)
-			led_on(3);
-		else
-			led_off(3);
-			
-	}
+    rt_uint8_t cnt = 0;
+    led_init();
+    while(1)
+    {
+        /* light on leds for one second */
+        rt_thread_delay(40);
+        cnt++;
+        if (cnt&0x01)
+            led_on(1);
+        else
+            led_off(1);
+        if (cnt&0x02)
+            led_on(2);
+        else
+            led_off(2);
+        if (cnt&0x04)
+            led_on(3);
+        else
+            led_off(3);
+
+    }
 }
 #endif
 
 static int rt_led_app_init(void)
 {
 #ifdef RT_USING_LED
-	rt_thread_t led_thread;
+    rt_thread_t led_thread;
 
 #if (RT_THREAD_PRIORITY_MAX == 32)
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 20, 20);						
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 20, 20);
 #else
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 200, 20);					
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 200, 20);
 #endif
 
-	if(led_thread != RT_NULL)
-		rt_thread_startup(led_thread);
+    if(led_thread != RT_NULL)
+        rt_thread_startup(led_thread);
 #endif
 
-	return 0;
+    return 0;
 }
 
 /* NFSv3 Initialization */
@@ -156,14 +142,14 @@ static int rt_led_app_init(void)
 #include <dfs_nfs.h>
 void nfs_start(void)
 {
-	nfs_init();
-
-	if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-	{
-		rt_kprintf("NFSv3 File System initialized!\n");
-	}
-	else
-		rt_kprintf("NFSv3 File System initialzation failed!\n");
+    nfs_init();
+
+    if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
+    {
+        rt_kprintf("NFSv3 File System initialized!\n");
+    }
+    else
+        rt_kprintf("NFSv3 File System initialzation failed!\n");
 }
 
 #include "finsh.h"

bsp/at91sam9g45/drivers/at91_i2c_gpio.c

@@ -1,25 +1,11 @@
 /*
- * File      : at91_i2c_gpio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2012-04-25     weety		first version
+ * Date           Author        Notes
+ * 2012-04-25     weety     first version
  */
 
 #include <rtdevice.h>
@@ -29,101 +15,101 @@
 
 static void at91_i2c_gpio_init()
 {
-	AT91C_BASE_PMC->PMC_PCER  = 1 << AT91C_ID_PIOA; //enable PIOA clock
-	AT91C_BASE_PIOA->PIO_PUER = (1 << 23);
-	AT91C_BASE_PIOA->PIO_PER  = (1 << 23);
-	AT91C_BASE_PIOA->PIO_MDER = (1 << 23);
-	AT91C_BASE_PIOA->PIO_PUER = (1 << 24);
-	AT91C_BASE_PIOA->PIO_PER  = (1 << 24);
-	AT91C_BASE_PIOA->PIO_MDER = (1 << 24);
-
-	AT91C_BASE_PIOA->PIO_OER  = (1 << 23);
-	AT91C_BASE_PIOA->PIO_OER  = (1 << 24);
-
-	AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
-	AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
+    AT91C_BASE_PMC->PMC_PCER  = 1 << AT91C_ID_PIOA; //enable PIOA clock
+    AT91C_BASE_PIOA->PIO_PUER = (1 << 23);
+    AT91C_BASE_PIOA->PIO_PER  = (1 << 23);
+    AT91C_BASE_PIOA->PIO_MDER = (1 << 23);
+    AT91C_BASE_PIOA->PIO_PUER = (1 << 24);
+    AT91C_BASE_PIOA->PIO_PER  = (1 << 24);
+    AT91C_BASE_PIOA->PIO_MDER = (1 << 24);
+
+    AT91C_BASE_PIOA->PIO_OER  = (1 << 23);
+    AT91C_BASE_PIOA->PIO_OER  = (1 << 24);
+
+    AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
+    AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
 }
 
 static void at91_set_sda(void *data, rt_int32_t state)
 {
-	if (state)
-	{
-		AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
-	}
-	else
-	{
-		AT91C_BASE_PIOA->PIO_CODR = (1 << 23);
-	}
+    if (state)
+    {
+        AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
+    }
+    else
+    {
+        AT91C_BASE_PIOA->PIO_CODR = (1 << 23);
+    }
 }
 
 static void at91_set_scl(void *data, rt_int32_t state)
 {
-	if (state)
-	{
-		AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
-	}
-	else
-	{
-		AT91C_BASE_PIOA->PIO_CODR = (1 << 24);
-	}
+    if (state)
+    {
+        AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
+    }
+    else
+    {
+        AT91C_BASE_PIOA->PIO_CODR = (1 << 24);
+    }
 }
 
 static rt_int32_t  at91_get_sda(void *data)
 {
-	return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23);
+    return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23);
 }
 
 static rt_int32_t  at91_get_scl(void *data)
 {
-	return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24);
+    return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24);
 }
 
 static void at91_udelay (rt_uint32_t us)
 {
-	rt_int32_t i;
-	for (; us > 0; us--)
-	{
-		i = 50000;
-		while(i > 0)
-		{
-			i--;
-		}
-	}
+    rt_int32_t i;
+    for (; us > 0; us--)
+    {
+        i = 50000;
+        while(i > 0)
+        {
+            i--;
+        }
+    }
 }
 
 static const struct rt_i2c_bit_ops bit_ops = {
-	RT_NULL,
-	at91_set_sda,
-	at91_set_scl,
-	at91_get_sda,
-	at91_get_scl,
-	
-	at91_udelay,
-
-	5,
-	100
+    RT_NULL,
+    at91_set_sda,
+    at91_set_scl,
+    at91_get_sda,
+    at91_get_scl,
+
+    at91_udelay,
+
+    5,
+    100
 };
 
 int at91_i2c_init(void)
 {
-	struct rt_i2c_bus_device *bus;
+    struct rt_i2c_bus_device *bus;
+
+    bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+    if (bus == RT_NULL)
+    {
+        rt_kprintf("rt_malloc failed\n");
+        return -RT_ENOMEM;
+    }
 
-	bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
-	if (bus == RT_NULL)
-	{
-		rt_kprintf("rt_malloc failed\n");
-		return -RT_ENOMEM;
-	}
-	
-	rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+    rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
 
-	bus->priv = (void *)&bit_ops;
+    bus->priv = (void *)&bit_ops;
 
-	at91_i2c_gpio_init();
+    at91_i2c_gpio_init();
 
-	rt_i2c_bit_add_bus(bus, "i2c0");
+    rt_i2c_bit_add_bus(bus, "i2c0");
 
-	return 0;
+    return 0;
 }
 
 INIT_DEVICE_EXPORT(at91_i2c_init);

bsp/at91sam9g45/drivers/at91_mci.h

@@ -1,21 +1,7 @@
 /*
- * File      : at91_mci.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,99 +11,99 @@
 #ifndef __AT91C_MCI_H__
 #define __AT91C_MCI_H__
 
-#define AT91C_MCI_CR		0x00		/* Control Register */
-#define		AT91C_MCI_MCIEN		(1 <<  0)	/* Multi-Media Interface Enable */
-#define		AT91C_MCI_MCIDIS		(1 <<  1)	/* Multi-Media Interface Disable */
-#define		AT91C_MCI_PWSEN		(1 <<  2)	/* Power Save Mode Enable */
-#define		AT91C_MCI_PWSDIS		(1 <<  3)	/* Power Save Mode Disable */
-#define		AT91C_MCI_SWRST		(1 <<  7)	/* Software Reset */
+#define AT91C_MCI_CR        0x00        /* Control Register */
+#define     AT91C_MCI_MCIEN     (1 <<  0)   /* Multi-Media Interface Enable */
+#define     AT91C_MCI_MCIDIS        (1 <<  1)   /* Multi-Media Interface Disable */
+#define     AT91C_MCI_PWSEN     (1 <<  2)   /* Power Save Mode Enable */
+#define     AT91C_MCI_PWSDIS        (1 <<  3)   /* Power Save Mode Disable */
+#define     AT91C_MCI_SWRST     (1 <<  7)   /* Software Reset */
 
-#define AT91C_MCI_MR		0x04		/* Mode Register */
-#define		AT91C_MCI_CLKDIV		(0xff  <<  0)	/* Clock Divider */
-#define		AT91C_MCI_PWSDIV		(7     <<  8)	/* Power Saving Divider */
-#define		AT91C_MCI_RDPROOF	(1     << 11)	/* Read Proof Enable [SAM926[03] only] */
-#define		AT91C_MCI_WRPROOF	(1     << 12)	/* Write Proof Enable [SAM926[03] only] */
-#define		AT91C_MCI_PDCFBYTE	(1     << 13)	/* PDC Force Byte Transfer [SAM926[03] only] */
-#define		AT91C_MCI_PDCPADV	(1     << 14)	/* PDC Padding Value */
-#define		AT91C_MCI_PDCMODE	(1     << 15)	/* PDC-orientated Mode */
-#define		AT91C_MCI_BLKLEN		(0xfff << 18)	/* Data Block Length */
+#define AT91C_MCI_MR        0x04        /* Mode Register */
+#define     AT91C_MCI_CLKDIV        (0xff  <<  0)   /* Clock Divider */
+#define     AT91C_MCI_PWSDIV        (7     <<  8)   /* Power Saving Divider */
+#define     AT91C_MCI_RDPROOF   (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define     AT91C_MCI_WRPROOF   (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define     AT91C_MCI_PDCFBYTE  (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
+#define     AT91C_MCI_PDCPADV   (1     << 14)   /* PDC Padding Value */
+#define     AT91C_MCI_PDCMODE   (1     << 15)   /* PDC-orientated Mode */
+#define     AT91C_MCI_BLKLEN        (0xfff << 18)   /* Data Block Length */
 
-#define AT91C_MCI_DTOR		0x08		/* Data Timeout Register */
-#define		AT91C_MCI_DTOCYC		(0xf << 0)	/* Data Timeout Cycle Number */
-#define		AT91C_MCI_DTOMUL		(7   << 4)	/* Data Timeout Multiplier */
-#define		AT91C_MCI_DTOMUL_1		(0 <<  4)
-#define		AT91C_MCI_DTOMUL_16		(1 <<  4)
-#define		AT91C_MCI_DTOMUL_128		(2 <<  4)
-#define		AT91C_MCI_DTOMUL_256		(3 <<  4)
-#define		AT91C_MCI_DTOMUL_1K		(4 <<  4)
-#define		AT91C_MCI_DTOMUL_4K		(5 <<  4)
-#define		AT91C_MCI_DTOMUL_64K		(6 <<  4)
-#define		AT91C_MCI_DTOMUL_1M		(7 <<  4)
+#define AT91C_MCI_DTOR      0x08        /* Data Timeout Register */
+#define     AT91C_MCI_DTOCYC        (0xf << 0)  /* Data Timeout Cycle Number */
+#define     AT91C_MCI_DTOMUL        (7   << 4)  /* Data Timeout Multiplier */
+#define     AT91C_MCI_DTOMUL_1      (0 <<  4)
+#define     AT91C_MCI_DTOMUL_16     (1 <<  4)
+#define     AT91C_MCI_DTOMUL_128        (2 <<  4)
+#define     AT91C_MCI_DTOMUL_256        (3 <<  4)
+#define     AT91C_MCI_DTOMUL_1K     (4 <<  4)
+#define     AT91C_MCI_DTOMUL_4K     (5 <<  4)
+#define     AT91C_MCI_DTOMUL_64K        (6 <<  4)
+#define     AT91C_MCI_DTOMUL_1M     (7 <<  4)
 
-#define AT91C_MCI_SDCR		0x0c		/* SD Card Register */
-#define		AT91C_MCI_SDCSEL		(3 << 0)	/* SD Card Selector */
-#define		AT91C_MCI_SDCBUS		(1 << 7)	/* 1-bit or 4-bit bus */
+#define AT91C_MCI_SDCR      0x0c        /* SD Card Register */
+#define     AT91C_MCI_SDCSEL        (3 << 0)    /* SD Card Selector */
+#define     AT91C_MCI_SDCBUS        (1 << 7)    /* 1-bit or 4-bit bus */
 
-#define AT91C_MCI_ARGR		0x10		/* Argument Register */
+#define AT91C_MCI_ARGR      0x10        /* Argument Register */
 
-#define AT91C_MCI_CMDR		0x14		/* Command Register */
-#define		AT91C_MCI_CMDNB		(0x3f << 0)	/* Command Number */
-#define		AT91C_MCI_RSPTYP		(3    << 6)	/* Response Type */
-#define			AT91C_MCI_RSPTYP_NONE	(0 <<  6)
-#define			AT91C_MCI_RSPTYP_48	(1 <<  6)
-#define			AT91C_MCI_RSPTYP_136	(2 <<  6)
-#define		AT91C_MCI_SPCMD		(7    << 8)	/* Special Command */
-#define			AT91C_MCI_SPCMD_NONE	(0 <<  8)
-#define			AT91C_MCI_SPCMD_INIT	(1 <<  8)
-#define			AT91C_MCI_SPCMD_SYNC	(2 <<  8)
-#define			AT91C_MCI_SPCMD_ICMD	(4 <<  8)
-#define			AT91C_MCI_SPCMD_IRESP	(5 <<  8)
-#define		AT91C_MCI_OPDCMD		(1 << 11)	/* Open Drain Command */
-#define		AT91C_MCI_MAXLAT		(1 << 12)	/* Max Latency for Command to Response */
-#define		AT91C_MCI_TRCMD		(3 << 16)	/* Transfer Command */
-#define			AT91C_MCI_TRCMD_NONE	(0 << 16)
-#define			AT91C_MCI_TRCMD_START	(1 << 16)
-#define			AT91C_MCI_TRCMD_STOP	(2 << 16)
-#define		AT91C_MCI_TRDIR		(1 << 18)	/* Transfer Direction */
-#define		AT91C_MCI_TRTYP		(3 << 19)	/* Transfer Type */
-#define			AT91C_MCI_TRTYP_BLOCK	(0 << 19)
-#define			AT91C_MCI_TRTYP_MULTIPLE	(1 << 19)
-#define			AT91C_MCI_TRTYP_STREAM	(2 << 19)
+#define AT91C_MCI_CMDR      0x14        /* Command Register */
+#define     AT91C_MCI_CMDNB     (0x3f << 0) /* Command Number */
+#define     AT91C_MCI_RSPTYP        (3    << 6) /* Response Type */
+#define         AT91C_MCI_RSPTYP_NONE   (0 <<  6)
+#define         AT91C_MCI_RSPTYP_48 (1 <<  6)
+#define         AT91C_MCI_RSPTYP_136    (2 <<  6)
+#define     AT91C_MCI_SPCMD     (7    << 8) /* Special Command */
+#define         AT91C_MCI_SPCMD_NONE    (0 <<  8)
+#define         AT91C_MCI_SPCMD_INIT    (1 <<  8)
+#define         AT91C_MCI_SPCMD_SYNC    (2 <<  8)
+#define         AT91C_MCI_SPCMD_ICMD    (4 <<  8)
+#define         AT91C_MCI_SPCMD_IRESP   (5 <<  8)
+#define     AT91C_MCI_OPDCMD        (1 << 11)   /* Open Drain Command */
+#define     AT91C_MCI_MAXLAT        (1 << 12)   /* Max Latency for Command to Response */
+#define     AT91C_MCI_TRCMD     (3 << 16)   /* Transfer Command */
+#define         AT91C_MCI_TRCMD_NONE    (0 << 16)
+#define         AT91C_MCI_TRCMD_START   (1 << 16)
+#define         AT91C_MCI_TRCMD_STOP    (2 << 16)
+#define     AT91C_MCI_TRDIR     (1 << 18)   /* Transfer Direction */
+#define     AT91C_MCI_TRTYP     (3 << 19)   /* Transfer Type */
+#define         AT91C_MCI_TRTYP_BLOCK   (0 << 19)
+#define         AT91C_MCI_TRTYP_MULTIPLE    (1 << 19)
+#define         AT91C_MCI_TRTYP_STREAM  (2 << 19)
 
-#define AT91C_MCI_BLKR		0x18		/* Block Register */
-#define		AT91C_MCI_BLKR_BCNT(n)	((0xffff & (n)) << 0)	/* Block count */
-#define		AT91C_MCI_BLKR_BLKLEN(n)	((0xffff & (n)) << 16)	/* Block lenght */
+#define AT91C_MCI_BLKR      0x18        /* Block Register */
+#define     AT91C_MCI_BLKR_BCNT(n)  ((0xffff & (n)) << 0)   /* Block count */
+#define     AT91C_MCI_BLKR_BLKLEN(n)    ((0xffff & (n)) << 16)  /* Block lenght */
 
-#define AT91C_MCI_RSPR(n)	(0x20 + ((n) * 4))	/* Response Registers 0-3 */
-#define AT91C_MCR_RDR		0x30		/* Receive Data Register */
-#define AT91C_MCR_TDR		0x34		/* Transmit Data Register */
+#define AT91C_MCI_RSPR(n)   (0x20 + ((n) * 4))  /* Response Registers 0-3 */
+#define AT91C_MCR_RDR       0x30        /* Receive Data Register */
+#define AT91C_MCR_TDR       0x34        /* Transmit Data Register */
 
-#define AT91C_MCI_SR		0x40		/* Status Register */
-#define		AT91C_MCI_CMDRDY		(1U <<  0)	/* Command Ready */
-#define		AT91C_MCI_RXRDY		(1U <<  1)	/* Receiver Ready */
-#define		AT91C_MCI_TXRDY		(1U <<  2)	/* Transmit Ready */
-#define		AT91C_MCI_BLKE		(1U <<  3)	/* Data Block Ended */
-#define		AT91C_MCI_DTIP		(1U <<  4)	/* Data Transfer in Progress */
-#define		AT91C_MCI_NOTBUSY	(1U <<  5)	/* Data Not Busy */
-#define		AT91C_MCI_ENDRX		(1U <<  6)	/* End of RX Buffer */
-#define		AT91C_MCI_ENDTX		(1U <<  7)	/* End fo TX Buffer */
-#define		AT91C_MCI_SDIOIRQA	(1U <<  8)	/* SDIO Interrupt for Slot A */
-#define		AT91C_MCI_SDIOIRQB	(1U <<  9)	/* SDIO Interrupt for Slot B */
-#define		AT91C_MCI_RXBUFF		(1U << 14)	/* RX Buffer Full */
-#define		AT91C_MCI_TXBUFE		(1U << 15)	/* TX Buffer Empty */
-#define		AT91C_MCI_RINDE		(1U << 16)	/* Response Index Error */
-#define		AT91C_MCI_RDIRE		(1U << 17)	/* Response Direction Error */
-#define		AT91C_MCI_RCRCE		(1U << 18)	/* Response CRC Error */
-#define		AT91C_MCI_RENDE		(1U << 19)	/* Response End Bit Error */
-#define		AT91C_MCI_RTOE		(1U << 20)	/* Reponse Time-out Error */
-#define		AT91C_MCI_DCRCE		(1U << 21)	/* Data CRC Error */
-#define		AT91C_MCI_DTOE		(1U << 22)	/* Data Time-out Error */
-#define		AT91C_MCI_OVRE		(1U << 30)	/* Overrun */
-#define		AT91C_MCI_UNRE		(1U << 31)	/* Underrun */
+#define AT91C_MCI_SR        0x40        /* Status Register */
+#define     AT91C_MCI_CMDRDY        (1U <<  0)  /* Command Ready */
+#define     AT91C_MCI_RXRDY     (1U <<  1)  /* Receiver Ready */
+#define     AT91C_MCI_TXRDY     (1U <<  2)  /* Transmit Ready */
+#define     AT91C_MCI_BLKE      (1U <<  3)  /* Data Block Ended */
+#define     AT91C_MCI_DTIP      (1U <<  4)  /* Data Transfer in Progress */
+#define     AT91C_MCI_NOTBUSY   (1U <<  5)  /* Data Not Busy */
+#define     AT91C_MCI_ENDRX     (1U <<  6)  /* End of RX Buffer */
+#define     AT91C_MCI_ENDTX     (1U <<  7)  /* End fo TX Buffer */
+#define     AT91C_MCI_SDIOIRQA  (1U <<  8)  /* SDIO Interrupt for Slot A */
+#define     AT91C_MCI_SDIOIRQB  (1U <<  9)  /* SDIO Interrupt for Slot B */
+#define     AT91C_MCI_RXBUFF        (1U << 14)  /* RX Buffer Full */
+#define     AT91C_MCI_TXBUFE        (1U << 15)  /* TX Buffer Empty */
+#define     AT91C_MCI_RINDE     (1U << 16)  /* Response Index Error */
+#define     AT91C_MCI_RDIRE     (1U << 17)  /* Response Direction Error */
+#define     AT91C_MCI_RCRCE     (1U << 18)  /* Response CRC Error */
+#define     AT91C_MCI_RENDE     (1U << 19)  /* Response End Bit Error */
+#define     AT91C_MCI_RTOE      (1U << 20)  /* Reponse Time-out Error */
+#define     AT91C_MCI_DCRCE     (1U << 21)  /* Data CRC Error */
+#define     AT91C_MCI_DTOE      (1U << 22)  /* Data Time-out Error */
+#define     AT91C_MCI_OVRE      (1U << 30)  /* Overrun */
+#define     AT91C_MCI_UNRE      (1U << 31)  /* Underrun */
 
-#define AT91C_MCI_IER		0x44		/* Interrupt Enable Register */
-#define AT91C_MCI_IDR		0x48		/* Interrupt Disable Register */
-#define AT91C_MCI_IMR		0x4c		/* Interrupt Mask Register */
+#define AT91C_MCI_IER       0x44        /* Interrupt Enable Register */
+#define AT91C_MCI_IDR       0x48        /* Interrupt Disable Register */
+#define AT91C_MCI_IMR       0x4c        /* Interrupt Mask Register */
 
 extern int at91_mci_init(void);
 

bsp/at91sam9g45/drivers/board.c

@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -53,36 +39,36 @@ extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
 extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 extern void rt_dbgu_isr(void);
 
-#define SAM9G45_BLOCK_SIZE	0x10000000		// 256M
-#define MMU_SECTION_SIZE	0x100000		// 1M
-#define PERIPHERALS_ADDR			// 1M
-
-#define SECTION_END(sa)		((sa) + MMU_SECTION_SIZE - 1)	// sa: start address
-#define BLOCK_END(ba)		((ba) + SAM9G45_BLOCK_SIZE - 1)	// ba: block address
-
-static struct mem_desc at91_mem_desc[] = {	/* FIXME, hornby, to confirm MMU and memory */
-	  { 0x00000000,             0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
-	//{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB  }, /* TLB for ITCM, ITCM map to address zero, 32KB */
-	//{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB  }, /* TLB for DTCM, 32KB */
-	//{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB  }, /* TLB for internal RAM, 64KB, we use it as global variable area */
-	//{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
-	//{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
-	//{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
-	//{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB   }, /* 1M external SRAM for program code and stack */
-	//{ 0x40000000,   BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
-	//{ 0x60000000,   BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
-	//{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
-	  { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB   }, /* isr */
-	  { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB   }, /* 128M for main DDR-SDRAM for print data */
-	//{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
+#define SAM9G45_BLOCK_SIZE  0x10000000      // 256M
+#define MMU_SECTION_SIZE    0x100000        // 1M
+#define PERIPHERALS_ADDR            // 1M
+
+#define SECTION_END(sa)     ((sa) + MMU_SECTION_SIZE - 1)   // sa: start address
+#define BLOCK_END(ba)       ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address
+
+static struct mem_desc at91_mem_desc[] = {  /* FIXME, hornby, to confirm MMU and memory */
+      { 0x00000000,             0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
+    //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB  }, /* TLB for ITCM, ITCM map to address zero, 32KB */
+    //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB  }, /* TLB for DTCM, 32KB */
+    //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB  }, /* TLB for internal RAM, 64KB, we use it as global variable area */
+    //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
+    //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
+    //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
+    //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB   }, /* 1M external SRAM for program code and stack */
+    //{ 0x40000000,   BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
+    //{ 0x60000000,   BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
+    //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
+      { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB   }, /* isr */
+      { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB   }, /* 128M for main DDR-SDRAM for print data */
+    //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
 };
 
 
-#define PIT_CPIV(x)		((x) & AT91C_PITC_CPIV)
-#define PIT_PICNT(x)	(((x) & AT91C_PITC_PICNT) >> 20)
+#define PIT_CPIV(x)     ((x) & AT91C_PITC_CPIV)
+#define PIT_PICNT(x)    (((x) & AT91C_PITC_PICNT) >> 20)
 
-static rt_uint32_t pit_cycle;	/* write-once */
-static rt_uint32_t pit_cnt;		/* access only w/system irq blocked */
+static rt_uint32_t pit_cycle;   /* write-once */
+static rt_uint32_t pit_cnt;     /* access only w/system irq blocked */
 
 /**
  * This function will handle rtos timer
@@ -90,37 +76,37 @@ static rt_uint32_t pit_cnt;		/* access only w/system irq blocked */
 void rt_timer_handler(int vector, void *param)
 {
 #ifdef RT_USING_DBGU
-	if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
-	{
-		rt_dbgu_isr();
-	}
+    if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
+    {
+        rt_dbgu_isr();
+    }
 #endif
-	if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
-	{
-		unsigned nr_ticks;
+    if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
+    {
+        unsigned nr_ticks;
 
-		/* Get number of ticks performed before irq, and ack it */
-		nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
+        /* Get number of ticks performed before irq, and ack it */
+        nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
         while (nr_ticks--)
-    		rt_tick_increase();
-	}
+            rt_tick_increase();
+    }
 }
 
 static void at91sam9g45_pit_reset(void)
 {
-	/* Disable timer and irqs */
-	AT91C_BASE_PITC->PITC_PIMR = 0;
-
-	/* Clear any pending interrupts, wait for PIT to stop counting */
-	while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
-		;
-
-	/* Start PIT but don't enable IRQ */
-	//AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
-	pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
-	AT91C_BASE_PITC->PITC_PIMR =
-			(pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
-	rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
+    /* Disable timer and irqs */
+    AT91C_BASE_PITC->PITC_PIMR = 0;
+
+    /* Clear any pending interrupts, wait for PIT to stop counting */
+    while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
+        ;
+
+    /* Start PIT but don't enable IRQ */
+    //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
+    pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
+    AT91C_BASE_PITC->PITC_PIMR =
+            (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+    rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
 }
 
 /*
@@ -128,19 +114,19 @@ static void at91sam9g45_pit_reset(void)
  */
 static void at91sam9g45_pit_init(void)
 {
-	rt_uint32_t	pit_rate;
-	//rt_uint32_t	bits;
-
-	/*
-	 * Use our actual MCK to figure out how many MCK/16 ticks per
-	 * 1/HZ period (instead of a compile-time constant LATCH).
-	 */
-	pit_rate = clk_get_rate(clk_get("mck")) / 16;
-	rt_kprintf("pit_rate=%dHZ\n", pit_rate);
-	pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
-
-	/* Initialize and enable the timer */
-	at91sam9g45_pit_reset();
+    rt_uint32_t pit_rate;
+    //rt_uint32_t   bits;
+
+    /*
+     * Use our actual MCK to figure out how many MCK/16 ticks per
+     * 1/HZ period (instead of a compile-time constant LATCH).
+     */
+    pit_rate = clk_get_rate(clk_get("mck")) / 16;
+    rt_kprintf("pit_rate=%dHZ\n", pit_rate);
+    pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
+
+    /* Initialize and enable the timer */
+    at91sam9g45_pit_reset();
 }
 
 /**
@@ -148,30 +134,30 @@ static void at91sam9g45_pit_init(void)
  */
 void rt_hw_timer_init()
 {
-	at91sam9g45_pit_init();
+    at91sam9g45_pit_init();
 
-	/* install interrupt handler */
-	rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
-							RT_NULL, "system");
-	rt_hw_interrupt_umask(AT91C_ID_SYS);
+    /* install interrupt handler */
+    rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
+                            RT_NULL, "system");
+    rt_hw_interrupt_umask(AT91C_ID_SYS);
 }
 
 void at91_tc1_init()
 {
-	AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
-	writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
-	writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
-	writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
-	writel(0xffff, AT91C_TC0_CV);
+    AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
+    writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
+    writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
+    writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
+    writel(0xffff, AT91C_TC0_CV);
 }
 
-#define BPS			115200	/* serial console port baudrate */
+#define BPS         115200  /* serial console port baudrate */
 
 static void at91_usart_putc(char c)
 {
-	while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
-		;
-	AT91C_BASE_DBGU->DBGU_THR = c;
+    while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
+        ;
+    AT91C_BASE_DBGU->DBGU_THR = c;
 }
 
 /**
@@ -182,33 +168,33 @@ static void at91_usart_putc(char c)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
-		if (*str=='\n')
-		{
-			at91_usart_putc('\r');
-		}
-
-		at91_usart_putc(*str++);
-	}
+    while (*str)
+    {
+        if (*str=='\n')
+        {
+            at91_usart_putc('\r');
+        }
+
+        at91_usart_putc(*str++);
+    }
 }
 
 static void rt_hw_console_init(void)
 {
-	int div;
-	int mode = 0;
-
-	AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
-	       AT91C_US_RXDIS | AT91C_US_TXDIS;
-	mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
-	       AT91C_US_CHMODE_NORMAL;
-	mode |= AT91C_US_CHRL_8_BITS;
-	mode |= AT91C_US_NBSTOP_1_BIT;
-	mode |= AT91C_US_PAR_NONE;
-	AT91C_BASE_DBGU->DBGU_MR = mode;
-	div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
-	AT91C_BASE_DBGU->DBGU_BRGR = div;
-	AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+    int div;
+    int mode = 0;
+
+    AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
+           AT91C_US_RXDIS | AT91C_US_TXDIS;
+    mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
+           AT91C_US_CHMODE_NORMAL;
+    mode |= AT91C_US_CHRL_8_BITS;
+    mode |= AT91C_US_NBSTOP_1_BIT;
+    mode |= AT91C_US_PAR_NONE;
+    AT91C_BASE_DBGU->DBGU_MR = mode;
+    div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
+    AT91C_BASE_DBGU->DBGU_BRGR = div;
+    AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
 }
 
 
@@ -217,31 +203,31 @@ static void rt_hw_console_init(void)
  */
 void rt_hw_board_init()
 {
-	/* initialize the system clock */
-	rt_hw_clock_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
 
-	/* initialize console */
-	rt_hw_console_init();
+    /* initialize console */
+    rt_hw_console_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
+    /* initialize mmu */
+    rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
 
-	/* initialize hardware interrupt */
-	rt_hw_interrupt_init();
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize early device */
+    /* initialize early device */
 #ifdef RT_USING_COMPONENTS_INIT
-	rt_components_board_init();
+    rt_components_board_init();
 #endif
 #ifdef RT_USING_CONSOLE
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-	/* initialize timer0 */
-	rt_hw_timer_init();
+    /* initialize timer0 */
+    rt_hw_timer_init();
 
 /* initialize board */
 #ifdef RT_USING_HEAP
-	rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 }
 

bsp/at91sam9g45/drivers/board.h

@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at91sam9g45/drivers/led.c

@@ -1,21 +1,7 @@
 /*
- * File      : led.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -35,10 +21,10 @@
 
 void led_init(void)
 {
-	AT91C_BASE_PIOC->PIO_PER   = LED_ALL;
-	AT91C_BASE_PIOC->PIO_OER   = LED_ALL;
-	AT91C_BASE_PIOC->PIO_PPUER = LED_ALL;
-	AT91C_BASE_PIOC->PIO_SODR  = LED_ALL;
+    AT91C_BASE_PIOC->PIO_PER   = LED_ALL;
+    AT91C_BASE_PIOC->PIO_OER   = LED_ALL;
+    AT91C_BASE_PIOC->PIO_PPUER = LED_ALL;
+    AT91C_BASE_PIOC->PIO_SODR  = LED_ALL;
 }
 
 const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 };

bsp/at91sam9g45/drivers/led.h

@@ -1,21 +1,7 @@
 /*
- * File      : led.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at91sam9g45/drivers/macb.h

@@ -1,21 +1,7 @@
 /*
- * File      : macb.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,319 +12,319 @@
 #include <mii.h>
 
 /* MACB register offsets */
-#define MACB_NCR				0x0000
-#define MACB_NCFGR				0x0004
-#define MACB_NSR				0x0008
-#define MACB_TSR				0x0014
-#define MACB_RBQP				0x0018
-#define MACB_TBQP				0x001c
-#define MACB_RSR				0x0020
-#define MACB_ISR				0x0024
-#define MACB_IER				0x0028
-#define MACB_IDR				0x002c
-#define MACB_IMR				0x0030
-#define MACB_MAN				0x0034
-#define MACB_PTR				0x0038
-#define MACB_PFR				0x003c
-#define MACB_FTO				0x0040
-#define MACB_SCF				0x0044
-#define MACB_MCF				0x0048
-#define MACB_FRO				0x004c
-#define MACB_FCSE				0x0050
-#define MACB_ALE				0x0054
-#define MACB_DTF				0x0058
-#define MACB_LCOL				0x005c
-#define MACB_EXCOL				0x0060
-#define MACB_TUND				0x0064
-#define MACB_CSE				0x0068
-#define MACB_RRE				0x006c
-#define MACB_ROVR				0x0070
-#define MACB_RSE				0x0074
-#define MACB_ELE				0x0078
-#define MACB_RJA				0x007c
-#define MACB_USF				0x0080
-#define MACB_STE				0x0084
-#define MACB_RLE				0x0088
-#define MACB_TPF				0x008c
-#define MACB_HRB				0x0090
-#define MACB_HRT				0x0094
-#define MACB_SA1B				0x0098
-#define MACB_SA1T				0x009c
-#define MACB_SA2B				0x00a0
-#define MACB_SA2T				0x00a4
-#define MACB_SA3B				0x00a8
-#define MACB_SA3T				0x00ac
-#define MACB_SA4B				0x00b0
-#define MACB_SA4T				0x00b4
-#define MACB_TID				0x00b8
-#define MACB_TPQ				0x00bc
-#define MACB_USRIO				0x00c0
-#define MACB_WOL				0x00c4
+#define MACB_NCR                0x0000
+#define MACB_NCFGR              0x0004
+#define MACB_NSR                0x0008
+#define MACB_TSR                0x0014
+#define MACB_RBQP               0x0018
+#define MACB_TBQP               0x001c
+#define MACB_RSR                0x0020
+#define MACB_ISR                0x0024
+#define MACB_IER                0x0028
+#define MACB_IDR                0x002c
+#define MACB_IMR                0x0030
+#define MACB_MAN                0x0034
+#define MACB_PTR                0x0038
+#define MACB_PFR                0x003c
+#define MACB_FTO                0x0040
+#define MACB_SCF                0x0044
+#define MACB_MCF                0x0048
+#define MACB_FRO                0x004c
+#define MACB_FCSE               0x0050
+#define MACB_ALE                0x0054
+#define MACB_DTF                0x0058
+#define MACB_LCOL               0x005c
+#define MACB_EXCOL              0x0060
+#define MACB_TUND               0x0064
+#define MACB_CSE                0x0068
+#define MACB_RRE                0x006c
+#define MACB_ROVR               0x0070
+#define MACB_RSE                0x0074
+#define MACB_ELE                0x0078
+#define MACB_RJA                0x007c
+#define MACB_USF                0x0080
+#define MACB_STE                0x0084
+#define MACB_RLE                0x0088
+#define MACB_TPF                0x008c
+#define MACB_HRB                0x0090
+#define MACB_HRT                0x0094
+#define MACB_SA1B               0x0098
+#define MACB_SA1T               0x009c
+#define MACB_SA2B               0x00a0
+#define MACB_SA2T               0x00a4
+#define MACB_SA3B               0x00a8
+#define MACB_SA3T               0x00ac
+#define MACB_SA4B               0x00b0
+#define MACB_SA4T               0x00b4
+#define MACB_TID                0x00b8
+#define MACB_TPQ                0x00bc
+#define MACB_USRIO              0x00c0
+#define MACB_WOL                0x00c4
 
 /* Bitfields in NCR */
-#define MACB_LB_OFFSET				0
-#define MACB_LB_SIZE				1
-#define MACB_LLB_OFFSET				1
-#define MACB_LLB_SIZE				1
-#define MACB_RE_OFFSET				2
-#define MACB_RE_SIZE				1
-#define MACB_TE_OFFSET				3
-#define MACB_TE_SIZE				1
-#define MACB_MPE_OFFSET				4
-#define MACB_MPE_SIZE				1
-#define MACB_CLRSTAT_OFFSET			5
-#define MACB_CLRSTAT_SIZE			1
-#define MACB_INCSTAT_OFFSET			6
-#define MACB_INCSTAT_SIZE			1
-#define MACB_WESTAT_OFFSET			7
-#define MACB_WESTAT_SIZE			1
-#define MACB_BP_OFFSET				8
-#define MACB_BP_SIZE				1
-#define MACB_TSTART_OFFSET			9
-#define MACB_TSTART_SIZE			1
-#define MACB_THALT_OFFSET			10
-#define MACB_THALT_SIZE				1
-#define MACB_NCR_TPF_OFFSET			11
-#define MACB_NCR_TPF_SIZE			1
-#define MACB_TZQ_OFFSET				12
-#define MACB_TZQ_SIZE				1
+#define MACB_LB_OFFSET              0
+#define MACB_LB_SIZE                1
+#define MACB_LLB_OFFSET             1
+#define MACB_LLB_SIZE               1
+#define MACB_RE_OFFSET              2
+#define MACB_RE_SIZE                1
+#define MACB_TE_OFFSET              3
+#define MACB_TE_SIZE                1
+#define MACB_MPE_OFFSET             4
+#define MACB_MPE_SIZE               1
+#define MACB_CLRSTAT_OFFSET         5
+#define MACB_CLRSTAT_SIZE           1
+#define MACB_INCSTAT_OFFSET         6
+#define MACB_INCSTAT_SIZE           1
+#define MACB_WESTAT_OFFSET          7
+#define MACB_WESTAT_SIZE            1
+#define MACB_BP_OFFSET              8
+#define MACB_BP_SIZE                1
+#define MACB_TSTART_OFFSET          9
+#define MACB_TSTART_SIZE            1
+#define MACB_THALT_OFFSET           10
+#define MACB_THALT_SIZE             1
+#define MACB_NCR_TPF_OFFSET         11
+#define MACB_NCR_TPF_SIZE           1
+#define MACB_TZQ_OFFSET             12
+#define MACB_TZQ_SIZE               1
 
 /* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET				0
-#define MACB_SPD_SIZE				1
-#define MACB_FD_OFFSET				1
-#define MACB_FD_SIZE				1
-#define MACB_BIT_RATE_OFFSET			2
-#define MACB_BIT_RATE_SIZE			1
-#define MACB_JFRAME_OFFSET			3
-#define MACB_JFRAME_SIZE			1
-#define MACB_CAF_OFFSET				4
-#define MACB_CAF_SIZE				1
-#define MACB_NBC_OFFSET				5
-#define MACB_NBC_SIZE				1
-#define MACB_NCFGR_MTI_OFFSET			6
-#define MACB_NCFGR_MTI_SIZE			1
-#define MACB_UNI_OFFSET				7
-#define MACB_UNI_SIZE				1
-#define MACB_BIG_OFFSET				8
-#define MACB_BIG_SIZE				1
-#define MACB_EAE_OFFSET				9
-#define MACB_EAE_SIZE				1
-#define MACB_CLK_OFFSET				10
-#define MACB_CLK_SIZE				2
-#define MACB_RTY_OFFSET				12
-#define MACB_RTY_SIZE				1
-#define MACB_PAE_OFFSET				13
-#define MACB_PAE_SIZE				1
-#define MACB_RBOF_OFFSET			14
-#define MACB_RBOF_SIZE				2
-#define MACB_RLCE_OFFSET			16
-#define MACB_RLCE_SIZE				1
-#define MACB_DRFCS_OFFSET			17
-#define MACB_DRFCS_SIZE				1
-#define MACB_EFRHD_OFFSET			18
-#define MACB_EFRHD_SIZE				1
-#define MACB_IRXFCS_OFFSET			19
-#define MACB_IRXFCS_SIZE			1
+#define MACB_SPD_OFFSET             0
+#define MACB_SPD_SIZE               1
+#define MACB_FD_OFFSET              1
+#define MACB_FD_SIZE                1
+#define MACB_BIT_RATE_OFFSET            2
+#define MACB_BIT_RATE_SIZE          1
+#define MACB_JFRAME_OFFSET          3
+#define MACB_JFRAME_SIZE            1
+#define MACB_CAF_OFFSET             4
+#define MACB_CAF_SIZE               1
+#define MACB_NBC_OFFSET             5
+#define MACB_NBC_SIZE               1
+#define MACB_NCFGR_MTI_OFFSET           6
+#define MACB_NCFGR_MTI_SIZE         1
+#define MACB_UNI_OFFSET             7
+#define MACB_UNI_SIZE               1
+#define MACB_BIG_OFFSET             8
+#define MACB_BIG_SIZE               1
+#define MACB_EAE_OFFSET             9
+#define MACB_EAE_SIZE               1
+#define MACB_CLK_OFFSET             10
+#define MACB_CLK_SIZE               2
+#define MACB_RTY_OFFSET             12
+#define MACB_RTY_SIZE               1
+#define MACB_PAE_OFFSET             13
+#define MACB_PAE_SIZE               1
+#define MACB_RBOF_OFFSET            14
+#define MACB_RBOF_SIZE              2
+#define MACB_RLCE_OFFSET            16
+#define MACB_RLCE_SIZE              1
+#define MACB_DRFCS_OFFSET           17
+#define MACB_DRFCS_SIZE             1
+#define MACB_EFRHD_OFFSET           18
+#define MACB_EFRHD_SIZE             1
+#define MACB_IRXFCS_OFFSET          19
+#define MACB_IRXFCS_SIZE            1
 
 /* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET			0
-#define MACB_NSR_LINK_SIZE			1
-#define MACB_MDIO_OFFSET			1
-#define MACB_MDIO_SIZE				1
-#define MACB_IDLE_OFFSET			2
-#define MACB_IDLE_SIZE				1
+#define MACB_NSR_LINK_OFFSET            0
+#define MACB_NSR_LINK_SIZE          1
+#define MACB_MDIO_OFFSET            1
+#define MACB_MDIO_SIZE              1
+#define MACB_IDLE_OFFSET            2
+#define MACB_IDLE_SIZE              1
 
 /* Bitfields in TSR */
-#define MACB_UBR_OFFSET				0
-#define MACB_UBR_SIZE				1
-#define MACB_COL_OFFSET				1
-#define MACB_COL_SIZE				1
-#define MACB_TSR_RLE_OFFSET			2
-#define MACB_TSR_RLE_SIZE			1
-#define MACB_TGO_OFFSET				3
-#define MACB_TGO_SIZE				1
-#define MACB_BEX_OFFSET				4
-#define MACB_BEX_SIZE				1
-#define MACB_COMP_OFFSET			5
-#define MACB_COMP_SIZE				1
-#define MACB_UND_OFFSET				6
-#define MACB_UND_SIZE				1
+#define MACB_UBR_OFFSET             0
+#define MACB_UBR_SIZE               1
+#define MACB_COL_OFFSET             1
+#define MACB_COL_SIZE               1
+#define MACB_TSR_RLE_OFFSET         2
+#define MACB_TSR_RLE_SIZE           1
+#define MACB_TGO_OFFSET             3
+#define MACB_TGO_SIZE               1
+#define MACB_BEX_OFFSET             4
+#define MACB_BEX_SIZE               1
+#define MACB_COMP_OFFSET            5
+#define MACB_COMP_SIZE              1
+#define MACB_UND_OFFSET             6
+#define MACB_UND_SIZE               1
 
 /* Bitfields in RSR */
-#define MACB_BNA_OFFSET				0
-#define MACB_BNA_SIZE				1
-#define MACB_REC_OFFSET				1
-#define MACB_REC_SIZE				1
-#define MACB_OVR_OFFSET				2
-#define MACB_OVR_SIZE				1
+#define MACB_BNA_OFFSET             0
+#define MACB_BNA_SIZE               1
+#define MACB_REC_OFFSET             1
+#define MACB_REC_SIZE               1
+#define MACB_OVR_OFFSET             2
+#define MACB_OVR_SIZE               1
 
 /* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET				0
-#define MACB_MFD_SIZE				1
-#define MACB_RCOMP_OFFSET			1
-#define MACB_RCOMP_SIZE				1
-#define MACB_RXUBR_OFFSET			2
-#define MACB_RXUBR_SIZE				1
-#define MACB_TXUBR_OFFSET			3
-#define MACB_TXUBR_SIZE				1
-#define MACB_ISR_TUND_OFFSET			4
-#define MACB_ISR_TUND_SIZE			1
-#define MACB_ISR_RLE_OFFSET			5
-#define MACB_ISR_RLE_SIZE			1
-#define MACB_TXERR_OFFSET			6
-#define MACB_TXERR_SIZE				1
-#define MACB_TCOMP_OFFSET			7
-#define MACB_TCOMP_SIZE				1
-#define MACB_ISR_LINK_OFFSET			9
-#define MACB_ISR_LINK_SIZE			1
-#define MACB_ISR_ROVR_OFFSET			10
-#define MACB_ISR_ROVR_SIZE			1
-#define MACB_HRESP_OFFSET			11
-#define MACB_HRESP_SIZE				1
-#define MACB_PFR_OFFSET				12
-#define MACB_PFR_SIZE				1
-#define MACB_PTZ_OFFSET				13
-#define MACB_PTZ_SIZE				1
+#define MACB_MFD_OFFSET             0
+#define MACB_MFD_SIZE               1
+#define MACB_RCOMP_OFFSET           1
+#define MACB_RCOMP_SIZE             1
+#define MACB_RXUBR_OFFSET           2
+#define MACB_RXUBR_SIZE             1
+#define MACB_TXUBR_OFFSET           3
+#define MACB_TXUBR_SIZE             1
+#define MACB_ISR_TUND_OFFSET            4
+#define MACB_ISR_TUND_SIZE          1
+#define MACB_ISR_RLE_OFFSET         5
+#define MACB_ISR_RLE_SIZE           1
+#define MACB_TXERR_OFFSET           6
+#define MACB_TXERR_SIZE             1
+#define MACB_TCOMP_OFFSET           7
+#define MACB_TCOMP_SIZE             1
+#define MACB_ISR_LINK_OFFSET            9
+#define MACB_ISR_LINK_SIZE          1
+#define MACB_ISR_ROVR_OFFSET            10
+#define MACB_ISR_ROVR_SIZE          1
+#define MACB_HRESP_OFFSET           11
+#define MACB_HRESP_SIZE             1
+#define MACB_PFR_OFFSET             12
+#define MACB_PFR_SIZE               1
+#define MACB_PTZ_OFFSET             13
+#define MACB_PTZ_SIZE               1
 
 /* Bitfields in MAN */
-#define MACB_DATA_OFFSET			0
-#define MACB_DATA_SIZE				16
-#define MACB_CODE_OFFSET			16
-#define MACB_CODE_SIZE				2
-#define MACB_REGA_OFFSET			18
-#define MACB_REGA_SIZE				5
-#define MACB_PHYA_OFFSET			23
-#define MACB_PHYA_SIZE				5
-#define MACB_RW_OFFSET				28
-#define MACB_RW_SIZE				2
-#define MACB_SOF_OFFSET				30
-#define MACB_SOF_SIZE				2
+#define MACB_DATA_OFFSET            0
+#define MACB_DATA_SIZE              16
+#define MACB_CODE_OFFSET            16
+#define MACB_CODE_SIZE              2
+#define MACB_REGA_OFFSET            18
+#define MACB_REGA_SIZE              5
+#define MACB_PHYA_OFFSET            23
+#define MACB_PHYA_SIZE              5
+#define MACB_RW_OFFSET              28
+#define MACB_RW_SIZE                2
+#define MACB_SOF_OFFSET             30
+#define MACB_SOF_SIZE               2
 
 /* Bitfields in USRIO (AVR32) */
-#define MACB_MII_OFFSET				0
-#define MACB_MII_SIZE				1
-#define MACB_EAM_OFFSET				1
-#define MACB_EAM_SIZE				1
-#define MACB_TX_PAUSE_OFFSET			2
-#define MACB_TX_PAUSE_SIZE			1
-#define MACB_TX_PAUSE_ZERO_OFFSET		3
-#define MACB_TX_PAUSE_ZERO_SIZE			1
+#define MACB_MII_OFFSET             0
+#define MACB_MII_SIZE               1
+#define MACB_EAM_OFFSET             1
+#define MACB_EAM_SIZE               1
+#define MACB_TX_PAUSE_OFFSET            2
+#define MACB_TX_PAUSE_SIZE          1
+#define MACB_TX_PAUSE_ZERO_OFFSET       3
+#define MACB_TX_PAUSE_ZERO_SIZE         1
 
 /* Bitfields in USRIO (AT91) */
-#define MACB_RMII_OFFSET			0
-#define MACB_RMII_SIZE				1
-#define MACB_CLKEN_OFFSET			1
-#define MACB_CLKEN_SIZE				1
+#define MACB_RMII_OFFSET            0
+#define MACB_RMII_SIZE              1
+#define MACB_CLKEN_OFFSET           1
+#define MACB_CLKEN_SIZE             1
 
 /* Bitfields in WOL */
-#define MACB_IP_OFFSET				0
-#define MACB_IP_SIZE				16
-#define MACB_MAG_OFFSET				16
-#define MACB_MAG_SIZE				1
-#define MACB_ARP_OFFSET				17
-#define MACB_ARP_SIZE				1
-#define MACB_SA1_OFFSET				18
-#define MACB_SA1_SIZE				1
-#define MACB_WOL_MTI_OFFSET			19
-#define MACB_WOL_MTI_SIZE			1
+#define MACB_IP_OFFSET              0
+#define MACB_IP_SIZE                16
+#define MACB_MAG_OFFSET             16
+#define MACB_MAG_SIZE               1
+#define MACB_ARP_OFFSET             17
+#define MACB_ARP_SIZE               1
+#define MACB_SA1_OFFSET             18
+#define MACB_SA1_SIZE               1
+#define MACB_WOL_MTI_OFFSET         19
+#define MACB_WOL_MTI_SIZE           1
 
 /* Constants for CLK */
-#define MACB_CLK_DIV8				0
-#define MACB_CLK_DIV16				1
-#define MACB_CLK_DIV32				2
-#define MACB_CLK_DIV64				3
+#define MACB_CLK_DIV8               0
+#define MACB_CLK_DIV16              1
+#define MACB_CLK_DIV32              2
+#define MACB_CLK_DIV64              3
 
 /* Constants for MAN register */
-#define MACB_MAN_SOF				1
-#define MACB_MAN_WRITE				1
-#define MACB_MAN_READ				2
-#define MACB_MAN_CODE				2
+#define MACB_MAN_SOF                1
+#define MACB_MAN_WRITE              1
+#define MACB_MAN_READ               2
+#define MACB_MAN_CODE               2
 
 /* Bit manipulation macros */
-#define MACB_BIT(name)					\
-	(1 << MACB_##name##_OFFSET)
-#define MACB_BF(name,value)				\
-	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
-	 << MACB_##name##_OFFSET)
+#define MACB_BIT(name)                  \
+    (1 << MACB_##name##_OFFSET)
+#define MACB_BF(name,value)             \
+    (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
+     << MACB_##name##_OFFSET)
 #define MACB_BFEXT(name,value)\
-	(((value) >> MACB_##name##_OFFSET)		\
-	 & ((1 << MACB_##name##_SIZE) - 1))
-#define MACB_BFINS(name,value,old)			\
-	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
-		    << MACB_##name##_OFFSET))		\
-	 | MACB_BF(name,value))
+    (((value) >> MACB_##name##_OFFSET)      \
+     & ((1 << MACB_##name##_SIZE) - 1))
+#define MACB_BFINS(name,value,old)          \
+    (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
+            << MACB_##name##_OFFSET))       \
+     | MACB_BF(name,value))
 
 /* Register access macros */
-#define macb_readl(port,reg)				\
-	readl((port)->regs + MACB_##reg)
-#define macb_writel(port,reg,value)			\
-	writel((value), (port)->regs + MACB_##reg)
+#define macb_readl(port,reg)                \
+    readl((port)->regs + MACB_##reg)
+#define macb_writel(port,reg,value)         \
+    writel((value), (port)->regs + MACB_##reg)
 
 struct dma_desc {
-	rt_uint32_t	addr;
-	rt_uint32_t	ctrl;
+    rt_uint32_t addr;
+    rt_uint32_t ctrl;
 };
 
 /* DMA descriptor bitfields */
-#define MACB_RX_USED_OFFSET			0
-#define MACB_RX_USED_SIZE			1
-#define MACB_RX_WRAP_OFFSET			1
-#define MACB_RX_WRAP_SIZE			1
-#define MACB_RX_WADDR_OFFSET			2
-#define MACB_RX_WADDR_SIZE			30
+#define MACB_RX_USED_OFFSET         0
+#define MACB_RX_USED_SIZE           1
+#define MACB_RX_WRAP_OFFSET         1
+#define MACB_RX_WRAP_SIZE           1
+#define MACB_RX_WADDR_OFFSET            2
+#define MACB_RX_WADDR_SIZE          30
 
-#define MACB_RX_FRMLEN_OFFSET			0
-#define MACB_RX_FRMLEN_SIZE			12
-#define MACB_RX_OFFSET_OFFSET			12
-#define MACB_RX_OFFSET_SIZE			2
-#define MACB_RX_SOF_OFFSET			14
-#define MACB_RX_SOF_SIZE			1
-#define MACB_RX_EOF_OFFSET			15
-#define MACB_RX_EOF_SIZE			1
-#define MACB_RX_CFI_OFFSET			16
-#define MACB_RX_CFI_SIZE			1
-#define MACB_RX_VLAN_PRI_OFFSET			17
-#define MACB_RX_VLAN_PRI_SIZE			3
-#define MACB_RX_PRI_TAG_OFFSET			20
-#define MACB_RX_PRI_TAG_SIZE			1
-#define MACB_RX_VLAN_TAG_OFFSET			21
-#define MACB_RX_VLAN_TAG_SIZE			1
-#define MACB_RX_TYPEID_MATCH_OFFSET		22
-#define MACB_RX_TYPEID_MATCH_SIZE		1
-#define MACB_RX_SA4_MATCH_OFFSET		23
-#define MACB_RX_SA4_MATCH_SIZE			1
-#define MACB_RX_SA3_MATCH_OFFSET		24
-#define MACB_RX_SA3_MATCH_SIZE			1
-#define MACB_RX_SA2_MATCH_OFFSET		25
-#define MACB_RX_SA2_MATCH_SIZE			1
-#define MACB_RX_SA1_MATCH_OFFSET		26
-#define MACB_RX_SA1_MATCH_SIZE			1
-#define MACB_RX_EXT_MATCH_OFFSET		28
-#define MACB_RX_EXT_MATCH_SIZE			1
-#define MACB_RX_UHASH_MATCH_OFFSET		29
-#define MACB_RX_UHASH_MATCH_SIZE		1
-#define MACB_RX_MHASH_MATCH_OFFSET		30
-#define MACB_RX_MHASH_MATCH_SIZE		1
-#define MACB_RX_BROADCAST_OFFSET		31
-#define MACB_RX_BROADCAST_SIZE			1
+#define MACB_RX_FRMLEN_OFFSET           0
+#define MACB_RX_FRMLEN_SIZE         12
+#define MACB_RX_OFFSET_OFFSET           12
+#define MACB_RX_OFFSET_SIZE         2
+#define MACB_RX_SOF_OFFSET          14
+#define MACB_RX_SOF_SIZE            1
+#define MACB_RX_EOF_OFFSET          15
+#define MACB_RX_EOF_SIZE            1
+#define MACB_RX_CFI_OFFSET          16
+#define MACB_RX_CFI_SIZE            1
+#define MACB_RX_VLAN_PRI_OFFSET         17
+#define MACB_RX_VLAN_PRI_SIZE           3
+#define MACB_RX_PRI_TAG_OFFSET          20
+#define MACB_RX_PRI_TAG_SIZE            1
+#define MACB_RX_VLAN_TAG_OFFSET         21
+#define MACB_RX_VLAN_TAG_SIZE           1
+#define MACB_RX_TYPEID_MATCH_OFFSET     22
+#define MACB_RX_TYPEID_MATCH_SIZE       1
+#define MACB_RX_SA4_MATCH_OFFSET        23
+#define MACB_RX_SA4_MATCH_SIZE          1
+#define MACB_RX_SA3_MATCH_OFFSET        24
+#define MACB_RX_SA3_MATCH_SIZE          1
+#define MACB_RX_SA2_MATCH_OFFSET        25
+#define MACB_RX_SA2_MATCH_SIZE          1
+#define MACB_RX_SA1_MATCH_OFFSET        26
+#define MACB_RX_SA1_MATCH_SIZE          1
+#define MACB_RX_EXT_MATCH_OFFSET        28
+#define MACB_RX_EXT_MATCH_SIZE          1
+#define MACB_RX_UHASH_MATCH_OFFSET      29
+#define MACB_RX_UHASH_MATCH_SIZE        1
+#define MACB_RX_MHASH_MATCH_OFFSET      30
+#define MACB_RX_MHASH_MATCH_SIZE        1
+#define MACB_RX_BROADCAST_OFFSET        31
+#define MACB_RX_BROADCAST_SIZE          1
 
-#define MACB_TX_FRMLEN_OFFSET			0
-#define MACB_TX_FRMLEN_SIZE			11
-#define MACB_TX_LAST_OFFSET			15
-#define MACB_TX_LAST_SIZE			1
-#define MACB_TX_NOCRC_OFFSET			16
-#define MACB_TX_NOCRC_SIZE			1
-#define MACB_TX_BUF_EXHAUSTED_OFFSET		27
-#define MACB_TX_BUF_EXHAUSTED_SIZE		1
-#define MACB_TX_UNDERRUN_OFFSET			28
-#define MACB_TX_UNDERRUN_SIZE			1
-#define MACB_TX_ERROR_OFFSET			29
-#define MACB_TX_ERROR_SIZE			1
-#define MACB_TX_WRAP_OFFSET			30
-#define MACB_TX_WRAP_SIZE			1
-#define MACB_TX_USED_OFFSET			31
-#define MACB_TX_USED_SIZE			1
+#define MACB_TX_FRMLEN_OFFSET           0
+#define MACB_TX_FRMLEN_SIZE         11
+#define MACB_TX_LAST_OFFSET         15
+#define MACB_TX_LAST_SIZE           1
+#define MACB_TX_NOCRC_OFFSET            16
+#define MACB_TX_NOCRC_SIZE          1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET        27
+#define MACB_TX_BUF_EXHAUSTED_SIZE      1
+#define MACB_TX_UNDERRUN_OFFSET         28
+#define MACB_TX_UNDERRUN_SIZE           1
+#define MACB_TX_ERROR_OFFSET            29
+#define MACB_TX_ERROR_SIZE          1
+#define MACB_TX_WRAP_OFFSET         30
+#define MACB_TX_WRAP_SIZE           1
+#define MACB_TX_USED_OFFSET         31
+#define MACB_TX_USED_SIZE           1
 
 extern int rt_hw_macb_init();
 

bsp/at91sam9g45/drivers/mii.h

@@ -1,21 +1,7 @@
 /*
- * File      : mii.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -36,7 +22,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS     0x0f    /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -51,7 +37,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000      0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -70,7 +56,7 @@
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_ESTATEN        0x0100  /* Extended Status in R15 */
 #define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
 #define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
@@ -99,7 +85,7 @@
 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 
 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
+            ADVERTISE_CSMA)
 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 
@@ -121,8 +107,8 @@
 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 #define LPA_NPAGE               0x8000  /* Next page bit               */
 
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
+#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
 /* Expansion register for auto-negotiation. */
 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
@@ -132,8 +118,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -151,8 +137,8 @@
 #define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
 
 /* Flow control flags */
-#define FLOW_CTRL_TX		0x01
-#define FLOW_CTRL_RX		0x02
+#define FLOW_CTRL_TX        0x01
+#define FLOW_CTRL_RX        0x02
 
 /**
  * mii_nway_result

bsp/at91sam9g45/drivers/usart.c

@@ -1,21 +1,7 @@
 /*
- * File      : usart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -30,8 +16,8 @@
 
 
 struct at91_uart {
-	AT91S_USART *port;
-	int irq;
+    AT91S_USART *port;
+    int irq;
 };
 
 
@@ -40,18 +26,18 @@ struct at91_uart {
  */
 void rt_at91_usart_handler(int vector, void *param)
 {
-	int status;
-	struct at91_uart *uart;
-	rt_device_t dev = (rt_device_t)param;
-	uart = (struct at91_uart *)dev->user_data;
-	status = uart->port->US_CSR;
-	if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */
-	{
-		return;
-	}
-	rt_interrupt_enter();
-	rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
-	rt_interrupt_leave();
+    int status;
+    struct at91_uart *uart;
+    rt_device_t dev = (rt_device_t)param;
+    uart = (struct at91_uart *)dev->user_data;
+    status = uart->port->US_CSR;
+    if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */
+    {
+        return;
+    }
+    rt_interrupt_enter();
+    rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+    rt_interrupt_leave();
 }
 
 /**
@@ -60,68 +46,68 @@ void rt_at91_usart_handler(int vector, void *param)
 static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
                                 struct serial_configure *cfg)
 {
-	int div;
-	int mode = 0;
-	struct at91_uart *uart;
+    int div;
+    int mode = 0;
+    struct at91_uart *uart;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-	uart = (struct at91_uart *)serial->parent.user_data;
-
-	uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
-	       AT91C_US_RXDIS | AT91C_US_TXDIS;
-	mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
-	       AT91C_US_CHMODE_NORMAL;
-	switch (cfg->data_bits)
-	{
-	case DATA_BITS_8:
-		mode |= AT91C_US_CHRL_8_BITS;
-		break;
-	case DATA_BITS_7:
-		mode |= AT91C_US_CHRL_7_BITS;
-		break;
-	case DATA_BITS_6:
-		mode |= AT91C_US_CHRL_6_BITS;
-		break;
-	case DATA_BITS_5:
-		mode |= AT91C_US_CHRL_5_BITS;
-		break;
-	default:
-		mode |= AT91C_US_CHRL_8_BITS;
-		break;
-	}
-
-	switch (cfg->stop_bits)
-	{
-	case STOP_BITS_2:
-		mode |= AT91C_US_NBSTOP_2_BIT;
-		break;
-	case STOP_BITS_1:
-	default:
-		mode |= AT91C_US_NBSTOP_1_BIT;
-		break;
-	}
-
-	switch (cfg->parity)
-	{
-	case PARITY_ODD:
-		mode |= AT91C_US_PAR_ODD;
-		break;
-	case PARITY_EVEN:
-		mode |= AT91C_US_PAR_EVEN;
-		break;
-	case PARITY_NONE:
-	default:
-		mode |= AT91C_US_PAR_NONE;
-		break;
-	}
-
-	uart->port->US_MR = mode;
+    uart = (struct at91_uart *)serial->parent.user_data;
+
+    uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
+           AT91C_US_RXDIS | AT91C_US_TXDIS;
+    mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
+           AT91C_US_CHMODE_NORMAL;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        mode |= AT91C_US_CHRL_8_BITS;
+        break;
+    case DATA_BITS_7:
+        mode |= AT91C_US_CHRL_7_BITS;
+        break;
+    case DATA_BITS_6:
+        mode |= AT91C_US_CHRL_6_BITS;
+        break;
+    case DATA_BITS_5:
+        mode |= AT91C_US_CHRL_5_BITS;
+        break;
+    default:
+        mode |= AT91C_US_CHRL_8_BITS;
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        mode |= AT91C_US_NBSTOP_2_BIT;
+        break;
+    case STOP_BITS_1:
+    default:
+        mode |= AT91C_US_NBSTOP_1_BIT;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        mode |= AT91C_US_PAR_ODD;
+        break;
+    case PARITY_EVEN:
+        mode |= AT91C_US_PAR_EVEN;
+        break;
+    case PARITY_NONE:
+    default:
+        mode |= AT91C_US_PAR_NONE;
+        break;
+    }
+
+    uart->port->US_MR = mode;
     /* Assume OVER is cleared and fractional baudrate generator is disabled */
-	div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
-	uart->port->US_BRGR = div;
-	uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
-	uart->port->US_IER = AT91C_US_RXRDY;
+    div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
+    uart->port->US_BRGR = div;
+    uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
+    uart->port->US_IER = AT91C_US_RXRDY;
 
     return RT_EOK;
 }
@@ -138,11 +124,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
     {
     case RT_DEVICE_CTRL_CLR_INT:
         /* disable rx irq */
-		rt_hw_interrupt_mask(uart->irq);
+        rt_hw_interrupt_mask(uart->irq);
         break;
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-		rt_hw_interrupt_umask(uart->irq);
+        rt_hw_interrupt_umask(uart->irq);
         break;
     }
 
@@ -152,10 +138,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
 static int at91_usart_putc(struct rt_serial_device *serial, char c)
 {
     //rt_uint32_t level;
-	struct at91_uart *uart = serial->parent.user_data;
+    struct at91_uart *uart = serial->parent.user_data;
 
     while (!(uart->port->US_CSR & AT91C_US_TXRDY));
-	uart->port->US_THR = c;
+    uart->port->US_THR = c;
 
     return 1;
 }
@@ -163,16 +149,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c)
 static int at91_usart_getc(struct rt_serial_device *serial)
 {
     int result;
-	struct at91_uart *uart = serial->parent.user_data;
+    struct at91_uart *uart = serial->parent.user_data;
 
     if (uart->port->US_CSR & AT91C_US_RXRDY)
-	{
-		result = uart->port->US_RHR & 0xff;
-	}
-	else
-	{
-		result = -1;
-	}
+    {
+        result = uart->port->US_RHR & 0xff;
+    }
+    else
+    {
+        result = -1;
+    }
 
     return result;
 }
@@ -188,8 +174,8 @@ static const struct rt_uart_ops at91_usart_ops =
 #if defined(RT_USING_DBGU)
 static struct rt_serial_device serial_dbgu;
 struct at91_uart dbgu = {
-	(AT91PS_USART)AT91C_BASE_DBGU,
-	AT91C_ID_SYS
+    (AT91PS_USART)AT91C_BASE_DBGU,
+    AT91C_ID_SYS
 };
 
 #endif
@@ -197,32 +183,32 @@ struct at91_uart dbgu = {
 #if defined(RT_USING_UART0)
 static struct rt_serial_device serial0;
 struct at91_uart uart0 = {
-	AT91C_BASE_US0,
-	AT91C_ID_US0
+    AT91C_BASE_US0,
+    AT91C_ID_US0
 };
 #endif
 
 #if defined(RT_USING_UART1)
 static struct rt_serial_device serial1;
 struct at91_uart uart1 = {
-	AT91C_BASE_US1,
-	AT91C_ID_US1
+    AT91C_BASE_US1,
+    AT91C_ID_US1
 };
 #endif
 
 #if defined(RT_USING_UART2)
 static struct rt_serial_device serial2;
 struct at91_uart uart2 = {
-	AT91C_BASE_US2,
-	AT91C_ID_US2
+    AT91C_BASE_US2,
+    AT91C_ID_US2
 };
 #endif
 
 #if defined(RT_USING_UART3)
 static struct rt_serial_device serial3;
 struct at91_uart uart3 = {
-	AT91C_BASE_US3,
-	AT91C_ID_US3
+    AT91C_BASE_US3,
+    AT91C_ID_US3
 };
 #endif
 
@@ -230,57 +216,57 @@ struct at91_uart uart3 = {
 void at91_usart_gpio_init(void)
 {
 #ifdef RT_USING_DBGU
-#define DRXD	12		// DBGU  rx as Peripheral A on PB12
-#define DTXD	13		// DBGU  tx as Peripheral A on PB13
-	AT91C_BASE_PIOB->PIO_IDR,   (1<<DRXD)|(1<<DTXD);   // Disables the Input Change Interrupt on the I/O line
-	AT91C_BASE_PIOB->PIO_PPUDR, (1<<DRXD)|(1<<DTXD);   // Disables the pull up resistor on the I/O line
-	AT91C_BASE_PIOB->PIO_ASR,   (1<<DRXD)|(1<<DTXD);   // Assigns the I/O line to the Peripheral A function
-	AT91C_BASE_PIOB->PIO_PDR,   (1<<DRXD)|(1<<DTXD);   // enables peripheral control of the pin
-	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_SYS;
+#define DRXD    12      // DBGU  rx as Peripheral A on PB12
+#define DTXD    13      // DBGU  tx as Peripheral A on PB13
+    AT91C_BASE_PIOB->PIO_IDR,   (1<<DRXD)|(1<<DTXD);   // Disables the Input Change Interrupt on the I/O line
+    AT91C_BASE_PIOB->PIO_PPUDR, (1<<DRXD)|(1<<DTXD);   // Disables the pull up resistor on the I/O line
+    AT91C_BASE_PIOB->PIO_ASR,   (1<<DRXD)|(1<<DTXD);   // Assigns the I/O line to the Peripheral A function
+    AT91C_BASE_PIOB->PIO_PDR,   (1<<DRXD)|(1<<DTXD);   // enables peripheral control of the pin
+    AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_SYS;
 #endif
 
 #ifdef RT_USING_UART0
-#define RXD0    18		// UART0 rx as Peripheral A on PB18
-#define TXD0    19		// UART0 tx as Peripheral A on PB19
-	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US0;
-	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD0)|(1<<TXD0);
-	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD0);
-	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD0);
-	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD0)|(1<<TXD0);
-	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD0)|(1<<TXD0);
+#define RXD0    18      // UART0 rx as Peripheral A on PB18
+#define TXD0    19      // UART0 tx as Peripheral A on PB19
+    AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US0;
+    AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD0)|(1<<TXD0);
+    AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD0);
+    AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD0);
+    AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD0)|(1<<TXD0);
+    AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD0)|(1<<TXD0);
 #endif
 
 #ifdef RT_USING_UART1
-#define TXD1     4		// UART1 tx as Peripheral A on PB4
-#define RXD1     5		// UART1 rx as Peripheral A on PB5
-	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US1;
-	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD1)|(1<<TXD1);
-	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD1);
-	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD1);
-	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD1)|(1<<TXD1);
-	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD1)|(1<<TXD1);
+#define TXD1     4      // UART1 tx as Peripheral A on PB4
+#define RXD1     5      // UART1 rx as Peripheral A on PB5
+    AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US1;
+    AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD1)|(1<<TXD1);
+    AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD1);
+    AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD1);
+    AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD1)|(1<<TXD1);
+    AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD1)|(1<<TXD1);
 #endif
 
 #ifdef RT_USING_UART2
-#define TXD2     6		// UART2 tx as Peripheral A on PB6
-#define RXD2     7		// UART2 rx as Peripheral A on PB7
-	AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US2;
-	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD2)|(1<<TXD2);
-	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD2);
-	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD2);
-	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD2)|(1<<TXD2);
-	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD2)|(1<<TXD2);
+#define TXD2     6      // UART2 tx as Peripheral A on PB6
+#define RXD2     7      // UART2 rx as Peripheral A on PB7
+    AT91C_BASE_PMC->PMC_PCER,    1 << AT91C_ID_US2;
+    AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD2)|(1<<TXD2);
+    AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD2);
+    AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD2);
+    AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD2)|(1<<TXD2);
+    AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD2)|(1<<TXD2);
 #endif
 
 #ifdef RT_USING_UART3
-#define TXD3     8		// UART3 tx as Peripheral A on PB8
-#define RXD3     9		// UART3 rx as Peripheral A on PB9
-	AT91C_BASE_PMC->PMC_PCER,    1<<AT91C_ID_US3;
-	AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD3)|(1<<TXD3);
-	AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD3);
-	AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD3);
-	AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD3)|(1<<TXD3);
-	AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD3)|(1<<TXD3);
+#define TXD3     8      // UART3 tx as Peripheral A on PB8
+#define RXD3     9      // UART3 rx as Peripheral A on PB9
+    AT91C_BASE_PMC->PMC_PCER,    1<<AT91C_ID_US3;
+    AT91C_BASE_PIOB->PIO_IDR,   (1<<RXD3)|(1<<TXD3);
+    AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD3);
+    AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD3);
+    AT91C_BASE_PIOB->PIO_ASR,   (1<<RXD3)|(1<<TXD3);
+    AT91C_BASE_PIOB->PIO_PDR,   (1<<RXD3)|(1<<TXD3);
 #endif
 }
 
@@ -289,17 +275,17 @@ void at91_usart_gpio_init(void)
  */
 int rt_hw_uart_init(void)
 {
-	at91_usart_gpio_init();
+    at91_usart_gpio_init();
 
 #if defined(RT_USING_DBGU)
-	serial_dbgu.ops = &at91_usart_ops;
-	serial_dbgu.config.baud_rate = BAUD_RATE_115200;
+    serial_dbgu.ops = &at91_usart_ops;
+    serial_dbgu.config.baud_rate = BAUD_RATE_115200;
     serial_dbgu.config.bit_order = BIT_ORDER_LSB;
     serial_dbgu.config.data_bits = DATA_BITS_8;
     serial_dbgu.config.parity = PARITY_NONE;
     serial_dbgu.config.stop_bits = STOP_BITS_1;
     serial_dbgu.config.invert = NRZ_NORMAL;
-	serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial_dbgu, "dbgu",
@@ -308,82 +294,82 @@ int rt_hw_uart_init(void)
 #endif
 
 #if defined(RT_USING_UART0)
-	serial0.ops = &at91_usart_ops;
-	serial0.config.baud_rate = BAUD_RATE_115200;
+    serial0.ops = &at91_usart_ops;
+    serial0.config.baud_rate = BAUD_RATE_115200;
     serial0.config.bit_order = BIT_ORDER_LSB;
     serial0.config.data_bits = DATA_BITS_8;
     serial0.config.parity = PARITY_NONE;
     serial0.config.stop_bits = STOP_BITS_1;
     serial0.config.invert = NRZ_NORMAL;
-	serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           &uart0);
-	rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
-							(void *)&(serial0.parent), "UART0");
-	rt_hw_interrupt_umask(uart0.irq);
+    rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
+                            (void *)&(serial0.parent), "UART0");
+    rt_hw_interrupt_umask(uart0.irq);
 #endif
 
 #if defined(RT_USING_UART1)
-	serial1.ops = &at91_usart_ops;
-	serial1.config.baud_rate = BAUD_RATE_115200;
+    serial1.ops = &at91_usart_ops;
+    serial1.config.baud_rate = BAUD_RATE_115200;
     serial1.config.bit_order = BIT_ORDER_LSB;
     serial1.config.data_bits = DATA_BITS_8;
     serial1.config.parity = PARITY_NONE;
     serial1.config.stop_bits = STOP_BITS_1;
     serial1.config.invert = NRZ_NORMAL;
-	serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial1, "uart1",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart1);
-	rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
-							(void *)&(serial1.parent), "UART1");
-	rt_hw_interrupt_umask(uart1.irq);
+    rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
+                            (void *)&(serial1.parent), "UART1");
+    rt_hw_interrupt_umask(uart1.irq);
 #endif
 
 #if defined(RT_USING_UART2)
-	serial2.ops = &at91_usart_ops;
-	serial2.config.baud_rate = BAUD_RATE_115200;
+    serial2.ops = &at91_usart_ops;
+    serial2.config.baud_rate = BAUD_RATE_115200;
     serial2.config.bit_order = BIT_ORDER_LSB;
     serial2.config.data_bits = DATA_BITS_8;
     serial2.config.parity = PARITY_NONE;
     serial2.config.stop_bits = STOP_BITS_1;
     serial2.config.invert = NRZ_NORMAL;
-	serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial2, "uart2",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart2);
-	rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
-							(void *)&(serial2.parent), "UART2");
-	rt_hw_interrupt_umask(uart2.irq);
+    rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
+                            (void *)&(serial2.parent), "UART2");
+    rt_hw_interrupt_umask(uart2.irq);
 #endif
 
 #if defined(RT_USING_UART3)
-	serial3.ops = &at91_usart_ops;
-	serial3.config.baud_rate = BAUD_RATE_115200;
+    serial3.ops = &at91_usart_ops;
+    serial3.config.baud_rate = BAUD_RATE_115200;
     serial3.config.bit_order = BIT_ORDER_LSB;
     serial3.config.data_bits = DATA_BITS_8;
     serial3.config.parity = PARITY_NONE;
     serial3.config.stop_bits = STOP_BITS_1;
     serial3.config.invert = NRZ_NORMAL;
-	serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial3, "uart3",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart3);
-	rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
-							(void *)&(serial3.parent), "UART3");
-	rt_hw_interrupt_umask(uart3.irq);
+    rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
+                            (void *)&(serial3.parent), "UART3");
+    rt_hw_interrupt_umask(uart3.irq);
 #endif
 
-	return 0;
+    return 0;
 }
 
 INIT_BOARD_EXPORT(rt_hw_uart_init);
@@ -391,7 +377,7 @@ INIT_BOARD_EXPORT(rt_hw_uart_init);
 #ifdef RT_USING_DBGU
 void rt_dbgu_isr(void)
 {
-	rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
+    rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
 }
 #endif
 

bsp/at91sam9g45/platform/gpio.h

@@ -1,21 +1,7 @@
 /*
- * File      : gpio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -27,182 +13,182 @@
 
 #include <rtthread.h>
 
-#define PIN_BASE		AIC_IRQS
+#define PIN_BASE        AIC_IRQS
 
-#define MAX_GPIO_BANKS		5
+#define MAX_GPIO_BANKS      5
 
-#define PIN_IRQS	(MAX_GPIO_BANKS*32)
+#define PIN_IRQS    (MAX_GPIO_BANKS*32)
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
-#define	AT91C_PIN_PA0	(PIN_BASE + 0x00 + 0)
-#define	AT91C_PIN_PA1	(PIN_BASE + 0x00 + 1)
-#define	AT91C_PIN_PA2	(PIN_BASE + 0x00 + 2)
-#define	AT91C_PIN_PA3	(PIN_BASE + 0x00 + 3)
-#define	AT91C_PIN_PA4	(PIN_BASE + 0x00 + 4)
-#define	AT91C_PIN_PA5	(PIN_BASE + 0x00 + 5)
-#define	AT91C_PIN_PA6	(PIN_BASE + 0x00 + 6)
-#define	AT91C_PIN_PA7	(PIN_BASE + 0x00 + 7)
-#define	AT91C_PIN_PA8	(PIN_BASE + 0x00 + 8)
-#define	AT91C_PIN_PA9	(PIN_BASE + 0x00 + 9)
-#define	AT91C_PIN_PA10	(PIN_BASE + 0x00 + 10)
-#define	AT91C_PIN_PA11	(PIN_BASE + 0x00 + 11)
-#define	AT91C_PIN_PA12	(PIN_BASE + 0x00 + 12)
-#define	AT91C_PIN_PA13	(PIN_BASE + 0x00 + 13)
-#define	AT91C_PIN_PA14	(PIN_BASE + 0x00 + 14)
-#define	AT91C_PIN_PA15	(PIN_BASE + 0x00 + 15)
-#define	AT91C_PIN_PA16	(PIN_BASE + 0x00 + 16)
-#define	AT91C_PIN_PA17	(PIN_BASE + 0x00 + 17)
-#define	AT91C_PIN_PA18	(PIN_BASE + 0x00 + 18)
-#define	AT91C_PIN_PA19	(PIN_BASE + 0x00 + 19)
-#define	AT91C_PIN_PA20	(PIN_BASE + 0x00 + 20)
-#define	AT91C_PIN_PA21	(PIN_BASE + 0x00 + 21)
-#define	AT91C_PIN_PA22	(PIN_BASE + 0x00 + 22)
-#define	AT91C_PIN_PA23	(PIN_BASE + 0x00 + 23)
-#define	AT91C_PIN_PA24	(PIN_BASE + 0x00 + 24)
-#define	AT91C_PIN_PA25	(PIN_BASE + 0x00 + 25)
-#define	AT91C_PIN_PA26	(PIN_BASE + 0x00 + 26)
-#define	AT91C_PIN_PA27	(PIN_BASE + 0x00 + 27)
-#define	AT91C_PIN_PA28	(PIN_BASE + 0x00 + 28)
-#define	AT91C_PIN_PA29	(PIN_BASE + 0x00 + 29)
-#define	AT91C_PIN_PA30	(PIN_BASE + 0x00 + 30)
-#define	AT91C_PIN_PA31	(PIN_BASE + 0x00 + 31)
+#define AT91C_PIN_PA0   (PIN_BASE + 0x00 + 0)
+#define AT91C_PIN_PA1   (PIN_BASE + 0x00 + 1)
+#define AT91C_PIN_PA2   (PIN_BASE + 0x00 + 2)
+#define AT91C_PIN_PA3   (PIN_BASE + 0x00 + 3)
+#define AT91C_PIN_PA4   (PIN_BASE + 0x00 + 4)
+#define AT91C_PIN_PA5   (PIN_BASE + 0x00 + 5)
+#define AT91C_PIN_PA6   (PIN_BASE + 0x00 + 6)
+#define AT91C_PIN_PA7   (PIN_BASE + 0x00 + 7)
+#define AT91C_PIN_PA8   (PIN_BASE + 0x00 + 8)
+#define AT91C_PIN_PA9   (PIN_BASE + 0x00 + 9)
+#define AT91C_PIN_PA10  (PIN_BASE + 0x00 + 10)
+#define AT91C_PIN_PA11  (PIN_BASE + 0x00 + 11)
+#define AT91C_PIN_PA12  (PIN_BASE + 0x00 + 12)
+#define AT91C_PIN_PA13  (PIN_BASE + 0x00 + 13)
+#define AT91C_PIN_PA14  (PIN_BASE + 0x00 + 14)
+#define AT91C_PIN_PA15  (PIN_BASE + 0x00 + 15)
+#define AT91C_PIN_PA16  (PIN_BASE + 0x00 + 16)
+#define AT91C_PIN_PA17  (PIN_BASE + 0x00 + 17)
+#define AT91C_PIN_PA18  (PIN_BASE + 0x00 + 18)
+#define AT91C_PIN_PA19  (PIN_BASE + 0x00 + 19)
+#define AT91C_PIN_PA20  (PIN_BASE + 0x00 + 20)
+#define AT91C_PIN_PA21  (PIN_BASE + 0x00 + 21)
+#define AT91C_PIN_PA22  (PIN_BASE + 0x00 + 22)
+#define AT91C_PIN_PA23  (PIN_BASE + 0x00 + 23)
+#define AT91C_PIN_PA24  (PIN_BASE + 0x00 + 24)
+#define AT91C_PIN_PA25  (PIN_BASE + 0x00 + 25)
+#define AT91C_PIN_PA26  (PIN_BASE + 0x00 + 26)
+#define AT91C_PIN_PA27  (PIN_BASE + 0x00 + 27)
+#define AT91C_PIN_PA28  (PIN_BASE + 0x00 + 28)
+#define AT91C_PIN_PA29  (PIN_BASE + 0x00 + 29)
+#define AT91C_PIN_PA30  (PIN_BASE + 0x00 + 30)
+#define AT91C_PIN_PA31  (PIN_BASE + 0x00 + 31)
 
-#define	AT91C_PIN_PB0	(PIN_BASE + 0x20 + 0)
-#define	AT91C_PIN_PB1	(PIN_BASE + 0x20 + 1)
-#define	AT91C_PIN_PB2	(PIN_BASE + 0x20 + 2)
-#define	AT91C_PIN_PB3	(PIN_BASE + 0x20 + 3)
-#define	AT91C_PIN_PB4	(PIN_BASE + 0x20 + 4)
-#define	AT91C_PIN_PB5	(PIN_BASE + 0x20 + 5)
-#define	AT91C_PIN_PB6	(PIN_BASE + 0x20 + 6)
-#define	AT91C_PIN_PB7	(PIN_BASE + 0x20 + 7)
-#define	AT91C_PIN_PB8	(PIN_BASE + 0x20 + 8)
-#define	AT91C_PIN_PB9	(PIN_BASE + 0x20 + 9)
-#define	AT91C_PIN_PB10	(PIN_BASE + 0x20 + 10)
-#define	AT91C_PIN_PB11	(PIN_BASE + 0x20 + 11)
-#define	AT91C_PIN_PB12	(PIN_BASE + 0x20 + 12)
-#define	AT91C_PIN_PB13	(PIN_BASE + 0x20 + 13)
-#define	AT91C_PIN_PB14	(PIN_BASE + 0x20 + 14)
-#define	AT91C_PIN_PB15	(PIN_BASE + 0x20 + 15)
-#define	AT91C_PIN_PB16	(PIN_BASE + 0x20 + 16)
-#define	AT91C_PIN_PB17	(PIN_BASE + 0x20 + 17)
-#define	AT91C_PIN_PB18	(PIN_BASE + 0x20 + 18)
-#define	AT91C_PIN_PB19	(PIN_BASE + 0x20 + 19)
-#define	AT91C_PIN_PB20	(PIN_BASE + 0x20 + 20)
-#define	AT91C_PIN_PB21	(PIN_BASE + 0x20 + 21)
-#define	AT91C_PIN_PB22	(PIN_BASE + 0x20 + 22)
-#define	AT91C_PIN_PB23	(PIN_BASE + 0x20 + 23)
-#define	AT91C_PIN_PB24	(PIN_BASE + 0x20 + 24)
-#define	AT91C_PIN_PB25	(PIN_BASE + 0x20 + 25)
-#define	AT91C_PIN_PB26	(PIN_BASE + 0x20 + 26)
-#define	AT91C_PIN_PB27	(PIN_BASE + 0x20 + 27)
-#define	AT91C_PIN_PB28	(PIN_BASE + 0x20 + 28)
-#define	AT91C_PIN_PB29	(PIN_BASE + 0x20 + 29)
-#define	AT91C_PIN_PB30	(PIN_BASE + 0x20 + 30)
-#define	AT91C_PIN_PB31	(PIN_BASE + 0x20 + 31)
+#define AT91C_PIN_PB0   (PIN_BASE + 0x20 + 0)
+#define AT91C_PIN_PB1   (PIN_BASE + 0x20 + 1)
+#define AT91C_PIN_PB2   (PIN_BASE + 0x20 + 2)
+#define AT91C_PIN_PB3   (PIN_BASE + 0x20 + 3)
+#define AT91C_PIN_PB4   (PIN_BASE + 0x20 + 4)
+#define AT91C_PIN_PB5   (PIN_BASE + 0x20 + 5)
+#define AT91C_PIN_PB6   (PIN_BASE + 0x20 + 6)
+#define AT91C_PIN_PB7   (PIN_BASE + 0x20 + 7)
+#define AT91C_PIN_PB8   (PIN_BASE + 0x20 + 8)
+#define AT91C_PIN_PB9   (PIN_BASE + 0x20 + 9)
+#define AT91C_PIN_PB10  (PIN_BASE + 0x20 + 10)
+#define AT91C_PIN_PB11  (PIN_BASE + 0x20 + 11)
+#define AT91C_PIN_PB12  (PIN_BASE + 0x20 + 12)
+#define AT91C_PIN_PB13  (PIN_BASE + 0x20 + 13)
+#define AT91C_PIN_PB14  (PIN_BASE + 0x20 + 14)
+#define AT91C_PIN_PB15  (PIN_BASE + 0x20 + 15)
+#define AT91C_PIN_PB16  (PIN_BASE + 0x20 + 16)
+#define AT91C_PIN_PB17  (PIN_BASE + 0x20 + 17)
+#define AT91C_PIN_PB18  (PIN_BASE + 0x20 + 18)
+#define AT91C_PIN_PB19  (PIN_BASE + 0x20 + 19)
+#define AT91C_PIN_PB20  (PIN_BASE + 0x20 + 20)
+#define AT91C_PIN_PB21  (PIN_BASE + 0x20 + 21)
+#define AT91C_PIN_PB22  (PIN_BASE + 0x20 + 22)
+#define AT91C_PIN_PB23  (PIN_BASE + 0x20 + 23)
+#define AT91C_PIN_PB24  (PIN_BASE + 0x20 + 24)
+#define AT91C_PIN_PB25  (PIN_BASE + 0x20 + 25)
+#define AT91C_PIN_PB26  (PIN_BASE + 0x20 + 26)
+#define AT91C_PIN_PB27  (PIN_BASE + 0x20 + 27)
+#define AT91C_PIN_PB28  (PIN_BASE + 0x20 + 28)
+#define AT91C_PIN_PB29  (PIN_BASE + 0x20 + 29)
+#define AT91C_PIN_PB30  (PIN_BASE + 0x20 + 30)
+#define AT91C_PIN_PB31  (PIN_BASE + 0x20 + 31)
 
-#define	AT91C_PIN_PC0	(PIN_BASE + 0x40 + 0)
-#define	AT91C_PIN_PC1	(PIN_BASE + 0x40 + 1)
-#define	AT91C_PIN_PC2	(PIN_BASE + 0x40 + 2)
-#define	AT91C_PIN_PC3	(PIN_BASE + 0x40 + 3)
-#define	AT91C_PIN_PC4	(PIN_BASE + 0x40 + 4)
-#define	AT91C_PIN_PC5	(PIN_BASE + 0x40 + 5)
-#define	AT91C_PIN_PC6	(PIN_BASE + 0x40 + 6)
-#define	AT91C_PIN_PC7	(PIN_BASE + 0x40 + 7)
-#define	AT91C_PIN_PC8	(PIN_BASE + 0x40 + 8)
-#define	AT91C_PIN_PC9	(PIN_BASE + 0x40 + 9)
-#define	AT91C_PIN_PC10	(PIN_BASE + 0x40 + 10)
-#define	AT91C_PIN_PC11	(PIN_BASE + 0x40 + 11)
-#define	AT91C_PIN_PC12	(PIN_BASE + 0x40 + 12)
-#define	AT91C_PIN_PC13	(PIN_BASE + 0x40 + 13)
-#define	AT91C_PIN_PC14	(PIN_BASE + 0x40 + 14)
-#define	AT91C_PIN_PC15	(PIN_BASE + 0x40 + 15)
-#define	AT91C_PIN_PC16	(PIN_BASE + 0x40 + 16)
-#define	AT91C_PIN_PC17	(PIN_BASE + 0x40 + 17)
-#define	AT91C_PIN_PC18	(PIN_BASE + 0x40 + 18)
-#define	AT91C_PIN_PC19	(PIN_BASE + 0x40 + 19)
-#define	AT91C_PIN_PC20	(PIN_BASE + 0x40 + 20)
-#define	AT91C_PIN_PC21	(PIN_BASE + 0x40 + 21)
-#define	AT91C_PIN_PC22	(PIN_BASE + 0x40 + 22)
-#define	AT91C_PIN_PC23	(PIN_BASE + 0x40 + 23)
-#define	AT91C_PIN_PC24	(PIN_BASE + 0x40 + 24)
-#define	AT91C_PIN_PC25	(PIN_BASE + 0x40 + 25)
-#define	AT91C_PIN_PC26	(PIN_BASE + 0x40 + 26)
-#define	AT91C_PIN_PC27	(PIN_BASE + 0x40 + 27)
-#define	AT91C_PIN_PC28	(PIN_BASE + 0x40 + 28)
-#define	AT91C_PIN_PC29	(PIN_BASE + 0x40 + 29)
-#define	AT91C_PIN_PC30	(PIN_BASE + 0x40 + 30)
-#define	AT91C_PIN_PC31	(PIN_BASE + 0x40 + 31)
+#define AT91C_PIN_PC0   (PIN_BASE + 0x40 + 0)
+#define AT91C_PIN_PC1   (PIN_BASE + 0x40 + 1)
+#define AT91C_PIN_PC2   (PIN_BASE + 0x40 + 2)
+#define AT91C_PIN_PC3   (PIN_BASE + 0x40 + 3)
+#define AT91C_PIN_PC4   (PIN_BASE + 0x40 + 4)
+#define AT91C_PIN_PC5   (PIN_BASE + 0x40 + 5)
+#define AT91C_PIN_PC6   (PIN_BASE + 0x40 + 6)
+#define AT91C_PIN_PC7   (PIN_BASE + 0x40 + 7)
+#define AT91C_PIN_PC8   (PIN_BASE + 0x40 + 8)
+#define AT91C_PIN_PC9   (PIN_BASE + 0x40 + 9)
+#define AT91C_PIN_PC10  (PIN_BASE + 0x40 + 10)
+#define AT91C_PIN_PC11  (PIN_BASE + 0x40 + 11)
+#define AT91C_PIN_PC12  (PIN_BASE + 0x40 + 12)
+#define AT91C_PIN_PC13  (PIN_BASE + 0x40 + 13)
+#define AT91C_PIN_PC14  (PIN_BASE + 0x40 + 14)
+#define AT91C_PIN_PC15  (PIN_BASE + 0x40 + 15)
+#define AT91C_PIN_PC16  (PIN_BASE + 0x40 + 16)
+#define AT91C_PIN_PC17  (PIN_BASE + 0x40 + 17)
+#define AT91C_PIN_PC18  (PIN_BASE + 0x40 + 18)
+#define AT91C_PIN_PC19  (PIN_BASE + 0x40 + 19)
+#define AT91C_PIN_PC20  (PIN_BASE + 0x40 + 20)
+#define AT91C_PIN_PC21  (PIN_BASE + 0x40 + 21)
+#define AT91C_PIN_PC22  (PIN_BASE + 0x40 + 22)
+#define AT91C_PIN_PC23  (PIN_BASE + 0x40 + 23)
+#define AT91C_PIN_PC24  (PIN_BASE + 0x40 + 24)
+#define AT91C_PIN_PC25  (PIN_BASE + 0x40 + 25)
+#define AT91C_PIN_PC26  (PIN_BASE + 0x40 + 26)
+#define AT91C_PIN_PC27  (PIN_BASE + 0x40 + 27)
+#define AT91C_PIN_PC28  (PIN_BASE + 0x40 + 28)
+#define AT91C_PIN_PC29  (PIN_BASE + 0x40 + 29)
+#define AT91C_PIN_PC30  (PIN_BASE + 0x40 + 30)
+#define AT91C_PIN_PC31  (PIN_BASE + 0x40 + 31)
 
-#define	AT91C_PIN_PD0	(PIN_BASE + 0x60 + 0)
-#define	AT91C_PIN_PD1	(PIN_BASE + 0x60 + 1)
-#define	AT91C_PIN_PD2	(PIN_BASE + 0x60 + 2)
-#define	AT91C_PIN_PD3	(PIN_BASE + 0x60 + 3)
-#define	AT91C_PIN_PD4	(PIN_BASE + 0x60 + 4)
-#define	AT91C_PIN_PD5	(PIN_BASE + 0x60 + 5)
-#define	AT91C_PIN_PD6	(PIN_BASE + 0x60 + 6)
-#define	AT91C_PIN_PD7	(PIN_BASE + 0x60 + 7)
-#define	AT91C_PIN_PD8	(PIN_BASE + 0x60 + 8)
-#define	AT91C_PIN_PD9	(PIN_BASE + 0x60 + 9)
-#define	AT91C_PIN_PD10	(PIN_BASE + 0x60 + 10)
-#define	AT91C_PIN_PD11	(PIN_BASE + 0x60 + 11)
-#define	AT91C_PIN_PD12	(PIN_BASE + 0x60 + 12)
-#define	AT91C_PIN_PD13	(PIN_BASE + 0x60 + 13)
-#define	AT91C_PIN_PD14	(PIN_BASE + 0x60 + 14)
-#define	AT91C_PIN_PD15	(PIN_BASE + 0x60 + 15)
-#define	AT91C_PIN_PD16	(PIN_BASE + 0x60 + 16)
-#define	AT91C_PIN_PD17	(PIN_BASE + 0x60 + 17)
-#define	AT91C_PIN_PD18	(PIN_BASE + 0x60 + 18)
-#define	AT91C_PIN_PD19	(PIN_BASE + 0x60 + 19)
-#define	AT91C_PIN_PD20	(PIN_BASE + 0x60 + 20)
-#define	AT91C_PIN_PD21	(PIN_BASE + 0x60 + 21)
-#define	AT91C_PIN_PD22	(PIN_BASE + 0x60 + 22)
-#define	AT91C_PIN_PD23	(PIN_BASE + 0x60 + 23)
-#define	AT91C_PIN_PD24	(PIN_BASE + 0x60 + 24)
-#define	AT91C_PIN_PD25	(PIN_BASE + 0x60 + 25)
-#define	AT91C_PIN_PD26	(PIN_BASE + 0x60 + 26)
-#define	AT91C_PIN_PD27	(PIN_BASE + 0x60 + 27)
-#define	AT91C_PIN_PD28	(PIN_BASE + 0x60 + 28)
-#define	AT91C_PIN_PD29	(PIN_BASE + 0x60 + 29)
-#define	AT91C_PIN_PD30	(PIN_BASE + 0x60 + 30)
-#define	AT91C_PIN_PD31	(PIN_BASE + 0x60 + 31)
+#define AT91C_PIN_PD0   (PIN_BASE + 0x60 + 0)
+#define AT91C_PIN_PD1   (PIN_BASE + 0x60 + 1)
+#define AT91C_PIN_PD2   (PIN_BASE + 0x60 + 2)
+#define AT91C_PIN_PD3   (PIN_BASE + 0x60 + 3)
+#define AT91C_PIN_PD4   (PIN_BASE + 0x60 + 4)
+#define AT91C_PIN_PD5   (PIN_BASE + 0x60 + 5)
+#define AT91C_PIN_PD6   (PIN_BASE + 0x60 + 6)
+#define AT91C_PIN_PD7   (PIN_BASE + 0x60 + 7)
+#define AT91C_PIN_PD8   (PIN_BASE + 0x60 + 8)
+#define AT91C_PIN_PD9   (PIN_BASE + 0x60 + 9)
+#define AT91C_PIN_PD10  (PIN_BASE + 0x60 + 10)
+#define AT91C_PIN_PD11  (PIN_BASE + 0x60 + 11)
+#define AT91C_PIN_PD12  (PIN_BASE + 0x60 + 12)
+#define AT91C_PIN_PD13  (PIN_BASE + 0x60 + 13)
+#define AT91C_PIN_PD14  (PIN_BASE + 0x60 + 14)
+#define AT91C_PIN_PD15  (PIN_BASE + 0x60 + 15)
+#define AT91C_PIN_PD16  (PIN_BASE + 0x60 + 16)
+#define AT91C_PIN_PD17  (PIN_BASE + 0x60 + 17)
+#define AT91C_PIN_PD18  (PIN_BASE + 0x60 + 18)
+#define AT91C_PIN_PD19  (PIN_BASE + 0x60 + 19)
+#define AT91C_PIN_PD20  (PIN_BASE + 0x60 + 20)
+#define AT91C_PIN_PD21  (PIN_BASE + 0x60 + 21)
+#define AT91C_PIN_PD22  (PIN_BASE + 0x60 + 22)
+#define AT91C_PIN_PD23  (PIN_BASE + 0x60 + 23)
+#define AT91C_PIN_PD24  (PIN_BASE + 0x60 + 24)
+#define AT91C_PIN_PD25  (PIN_BASE + 0x60 + 25)
+#define AT91C_PIN_PD26  (PIN_BASE + 0x60 + 26)
+#define AT91C_PIN_PD27  (PIN_BASE + 0x60 + 27)
+#define AT91C_PIN_PD28  (PIN_BASE + 0x60 + 28)
+#define AT91C_PIN_PD29  (PIN_BASE + 0x60 + 29)
+#define AT91C_PIN_PD30  (PIN_BASE + 0x60 + 30)
+#define AT91C_PIN_PD31  (PIN_BASE + 0x60 + 31)
 
-#define	AT91C_PIN_PE0	(PIN_BASE + 0x80 + 0)
-#define	AT91C_PIN_PE1	(PIN_BASE + 0x80 + 1)
-#define	AT91C_PIN_PE2	(PIN_BASE + 0x80 + 2)
-#define	AT91C_PIN_PE3	(PIN_BASE + 0x80 + 3)
-#define	AT91C_PIN_PE4	(PIN_BASE + 0x80 + 4)
-#define	AT91C_PIN_PE5	(PIN_BASE + 0x80 + 5)
-#define	AT91C_PIN_PE6	(PIN_BASE + 0x80 + 6)
-#define	AT91C_PIN_PE7	(PIN_BASE + 0x80 + 7)
-#define	AT91C_PIN_PE8	(PIN_BASE + 0x80 + 8)
-#define	AT91C_PIN_PE9	(PIN_BASE + 0x80 + 9)
-#define	AT91C_PIN_PE10	(PIN_BASE + 0x80 + 10)
-#define	AT91C_PIN_PE11	(PIN_BASE + 0x80 + 11)
-#define	AT91C_PIN_PE12	(PIN_BASE + 0x80 + 12)
-#define	AT91C_PIN_PE13	(PIN_BASE + 0x80 + 13)
-#define	AT91C_PIN_PE14	(PIN_BASE + 0x80 + 14)
-#define	AT91C_PIN_PE15	(PIN_BASE + 0x80 + 15)
-#define	AT91C_PIN_PE16	(PIN_BASE + 0x80 + 16)
-#define	AT91C_PIN_PE17	(PIN_BASE + 0x80 + 17)
-#define	AT91C_PIN_PE18	(PIN_BASE + 0x80 + 18)
-#define	AT91C_PIN_PE19	(PIN_BASE + 0x80 + 19)
-#define	AT91C_PIN_PE20	(PIN_BASE + 0x80 + 20)
-#define	AT91C_PIN_PE21	(PIN_BASE + 0x80 + 21)
-#define	AT91C_PIN_PE22	(PIN_BASE + 0x80 + 22)
-#define	AT91C_PIN_PE23	(PIN_BASE + 0x80 + 23)
-#define	AT91C_PIN_PE24	(PIN_BASE + 0x80 + 24)
-#define	AT91C_PIN_PE25	(PIN_BASE + 0x80 + 25)
-#define	AT91C_PIN_PE26	(PIN_BASE + 0x80 + 26)
-#define	AT91C_PIN_PE27	(PIN_BASE + 0x80 + 27)
-#define	AT91C_PIN_PE28	(PIN_BASE + 0x80 + 28)
-#define	AT91C_PIN_PE29	(PIN_BASE + 0x80 + 29)
-#define	AT91C_PIN_PE30	(PIN_BASE + 0x80 + 30)
-#define	AT91C_PIN_PE31	(PIN_BASE + 0x80 + 31)
+#define AT91C_PIN_PE0   (PIN_BASE + 0x80 + 0)
+#define AT91C_PIN_PE1   (PIN_BASE + 0x80 + 1)
+#define AT91C_PIN_PE2   (PIN_BASE + 0x80 + 2)
+#define AT91C_PIN_PE3   (PIN_BASE + 0x80 + 3)
+#define AT91C_PIN_PE4   (PIN_BASE + 0x80 + 4)
+#define AT91C_PIN_PE5   (PIN_BASE + 0x80 + 5)
+#define AT91C_PIN_PE6   (PIN_BASE + 0x80 + 6)
+#define AT91C_PIN_PE7   (PIN_BASE + 0x80 + 7)
+#define AT91C_PIN_PE8   (PIN_BASE + 0x80 + 8)
+#define AT91C_PIN_PE9   (PIN_BASE + 0x80 + 9)
+#define AT91C_PIN_PE10  (PIN_BASE + 0x80 + 10)
+#define AT91C_PIN_PE11  (PIN_BASE + 0x80 + 11)
+#define AT91C_PIN_PE12  (PIN_BASE + 0x80 + 12)
+#define AT91C_PIN_PE13  (PIN_BASE + 0x80 + 13)
+#define AT91C_PIN_PE14  (PIN_BASE + 0x80 + 14)
+#define AT91C_PIN_PE15  (PIN_BASE + 0x80 + 15)
+#define AT91C_PIN_PE16  (PIN_BASE + 0x80 + 16)
+#define AT91C_PIN_PE17  (PIN_BASE + 0x80 + 17)
+#define AT91C_PIN_PE18  (PIN_BASE + 0x80 + 18)
+#define AT91C_PIN_PE19  (PIN_BASE + 0x80 + 19)
+#define AT91C_PIN_PE20  (PIN_BASE + 0x80 + 20)
+#define AT91C_PIN_PE21  (PIN_BASE + 0x80 + 21)
+#define AT91C_PIN_PE22  (PIN_BASE + 0x80 + 22)
+#define AT91C_PIN_PE23  (PIN_BASE + 0x80 + 23)
+#define AT91C_PIN_PE24  (PIN_BASE + 0x80 + 24)
+#define AT91C_PIN_PE25  (PIN_BASE + 0x80 + 25)
+#define AT91C_PIN_PE26  (PIN_BASE + 0x80 + 26)
+#define AT91C_PIN_PE27  (PIN_BASE + 0x80 + 27)
+#define AT91C_PIN_PE28  (PIN_BASE + 0x80 + 28)
+#define AT91C_PIN_PE29  (PIN_BASE + 0x80 + 29)
+#define AT91C_PIN_PE30  (PIN_BASE + 0x80 + 30)
+#define AT91C_PIN_PE31  (PIN_BASE + 0x80 + 31)
 
 rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
 {
-	return gpio;
+    return gpio;
 }
 
 #endif

bsp/at91sam9g45/platform/interrupt.c

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -26,7 +12,7 @@
 #include "at91sam9g45.h"
 #include "interrupt.h"
 
-#define AIC_IRQS	32
+#define AIC_IRQS    32
 #define MAX_HANDLERS    (AIC_IRQS + PIN_IRQS)
 
 extern rt_uint32_t rt_interrupt_nest;
@@ -101,17 +87,17 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
 rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param)
 {
     rt_uint32_t isr, irq_n;
-	AT91PS_PIO pio;
+    AT91PS_PIO pio;
     void *parameter;
 
     switch (bank)
     {
-	case 0: pio = AT91C_BASE_PIOA; break;
-	case 1: pio = AT91C_BASE_PIOB; break;
-	case 2: pio = AT91C_BASE_PIOC; break;
-	case 3: pio = AT91C_BASE_PIOD; break;
-	case 4: pio = AT91C_BASE_PIOE; break;
-	default: return RT_NULL;
+    case 0: pio = AT91C_BASE_PIOA; break;
+    case 1: pio = AT91C_BASE_PIOB; break;
+    case 2: pio = AT91C_BASE_PIOC; break;
+    case 3: pio = AT91C_BASE_PIOD; break;
+    case 4: pio = AT91C_BASE_PIOE; break;
+    default: return RT_NULL;
     }
     irq_n = AIC_IRQS + 32*bank;
     isr = readl(pio->PIO_ISR);
@@ -133,21 +119,21 @@ rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param)
 unsigned int SpuriousCount = 0;
 static void DefaultSpuriousHandler( void )
 {
-	SpuriousCount++;
-	rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount);
-	return ;
+    SpuriousCount++;
+    rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount);
+    return ;
 }
 
 static void DefaultFiqHandler(void)
 {
-	rt_kprintf("Unhandled FIQ occured!!!\n");
-	while (1);
+    rt_kprintf("Unhandled FIQ occured!!!\n");
+    while (1);
 }
 
 static void DefaultIrqHandler(void)
 {
-	rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR);
-	while (1);
+    rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR);
+    while (1);
 }
 
 /*
@@ -345,7 +331,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
             irq_desc[vector].param = param;
 #ifdef RT_USING_INTERRUPT_INFO
             rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
-			irq_desc[vector].counter = 0;
+            irq_desc[vector].counter = 0;
 #endif
         }
     }
@@ -446,16 +432,16 @@ void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
 #ifdef RT_USING_INTERRUPT_INFO
 void list_irq(void)
 {
-	int irq;
-
-	rt_kprintf("number\tcount\tname\n");
-	for (irq = 0; irq < MAX_HANDLERS; irq++)
-	{
-		if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
-		{
-			rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
-		}
-	}
+    int irq;
+
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
 }
 
 #include <finsh.h>

bsp/at91sam9g45/platform/interrupt.h

@@ -1,21 +1,7 @@
 /*
- * File      : interrupt.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/at91sam9g45/platform/io.h

@@ -1,21 +1,7 @@
 /*
- * File      : io.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,15 +11,15 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT		0xFFFFFFFF
+#define IO_SPACE_LIMIT      0xFFFFFFFF
 
-#define readb(a)	(*(volatile unsigned char  *)(a))
-#define readw(a)	(*(volatile unsigned short *)(a))
-#define readl(a)	(*(volatile unsigned int   *)(a))
+#define readb(a)    (*(volatile unsigned char  *)(a))
+#define readw(a)    (*(volatile unsigned short *)(a))
+#define readl(a)    (*(volatile unsigned int   *)(a))
 
-#define writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
-#define writew(v,a)	(*(volatile unsigned short *)(a) = (v))
-#define writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
+#define writeb(v,a) (*(volatile unsigned char  *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int   *)(a) = (v))
 
 #endif
 

bsp/at91sam9g45/platform/irq.h

@@ -1,27 +1,13 @@
 /*
- * File      : irq.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2011-01-13     weety      first version
  */
- 
+
 #ifndef __IRQ_H__
 #define __IRQ_H__
 
@@ -32,18 +18,18 @@ extern "C" {
 /*
  * IRQ line status.
  *
- * Bits 0-7 are reserved 
+ * Bits 0-7 are reserved
  *
  * IRQ types
  */
-#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
-#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
-#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
+#define IRQ_TYPE_NONE       0x00000000  /* Default, unspecified type */
+#define IRQ_TYPE_EDGE_RISING    0x00000001  /* Edge rising type */
+#define IRQ_TYPE_EDGE_FALLING   0x00000002  /* Edge falling type */
 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
-#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
-#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
-#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */
+#define IRQ_TYPE_LEVEL_HIGH 0x00000004  /* Level high type */
+#define IRQ_TYPE_LEVEL_LOW  0x00000008  /* Level low type */
+#define IRQ_TYPE_SENSE_MASK 0x0000000f  /* Mask of the above */
+#define IRQ_TYPE_PROBE      0x00000010  /* Probing in progress */
 
 #ifdef __cplusplus
 }

bsp/at91sam9g45/platform/reset.c

@@ -1,21 +1,7 @@
 /*
- * File      : reset.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -33,12 +19,12 @@
 
 void machine_reset(void)
 {
-	AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST;
+    AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST;
 }
 
 void machine_shutdown(void)
 {
-	AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW;
+    AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW;
 }
 
 #ifdef RT_USING_FINSH
@@ -49,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
 #ifdef FINSH_USING_MSH
 int cmd_reset(int argc, char** argv)
 {
-	rt_hw_cpu_reset();
-	return 0;
+    rt_hw_cpu_reset();
+    return 0;
 }
 
 int cmd_shutdown(int argc, char** argv)
 {
-	rt_hw_cpu_shutdown();
-	return 0;
+    rt_hw_cpu_shutdown();
+    return 0;
 }
 
 FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);

bsp/at91sam9g45/platform/rt_low_level_init.c

@@ -1,29 +1,15 @@
 /*
- * File      : rt_low_level_init.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 /* write register a=address, v=value */
-#define write_reg(a,v)	    (*(volatile unsigned int *)(a) = (v))
+#define write_reg(a,v)      (*(volatile unsigned int *)(a) = (v))
 /* Processor Reset */
 #define AT91C_RSTC_PROCRST   (1 << 0)
 #define AT91C_RSTC_PERRST    (1 << 2)

bsp/at91sam9g45/platform/rt_low_level_init.h

@@ -1,21 +1,7 @@
 /*
- * File      : rt_low_level_init.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -23,7 +9,7 @@
  */
 #ifndef __RT_LOW_LEVEL_INIT_H__
 #define __RT_LOW_LEVEL_INIT_H__
- 
+
 /*-------- Stack size of CPU modes -------------------------------------------*/
 #define UND_STK_SIZE 512
 #define SVC_STK_SIZE 4096

bsp/at91sam9g45/platform/system_clock.c

@@ -1,21 +1,7 @@
 /*
- * File      : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -28,236 +14,236 @@
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk clk32k = {
-	"clk32k",
-	AT91C_SLOW_CLOCK,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "clk32k",
+    AT91C_SLOW_CLOCK,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk main_clk = {
-	"main",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "main",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk plla = {
-	"plla",
-	0,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "plla",
+    0,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk mck = {
-	"mck",
-	0,
-	NULL,
-	{RT_NULL, RT_NULL},
+    "mck",
+    0,
+    NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk upllck = {
-	"upllck",
-	480*1000*1000,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "upllck",
+    480*1000*1000,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk *const standard_pmc_clocks[] = {
-	/* four primary clocks */
-	&clk32k,
-	&main_clk,
-	&plla,
+    /* four primary clocks */
+    &clk32k,
+    &main_clk,
+    &plla,
 
-	/* MCK */
-	&mck
+    /* MCK */
+    &mck
 };
 
 /* clocks cannot be de-registered no refcounting necessary */
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
-
-	return RT_NULL;
+    struct clk *clk;
+    rt_list_t *list;
+
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	rate;
-
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return rate;
+    rt_uint32_t rate;
+
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return rate;
 }
 
 static void at91_upllck_init(rt_uint32_t main_clock)
 {
-	// EHCI USB use fixed 480MHz clock
+    // EHCI USB use fixed 480MHz clock
 }
 
 static struct clk *at91_css_to_clk(unsigned long css)
 {
-	switch (css) {
-		case AT91C_PMC_CSS_SLOW_CLK:
-			return &clk32k;
-		case AT91C_PMC_CSS_MAIN_CLK:
-			return &main_clk;
-		case AT91C_PMC_CSS_PLLA_CLK:
-			return &plla;
-		case AT91C_PMC_CSS_UPLL_CLK:
-			return &upllck;
-	}
-
-	return RT_NULL;
+    switch (css) {
+        case AT91C_PMC_CSS_SLOW_CLK:
+            return &clk32k;
+        case AT91C_PMC_CSS_MAIN_CLK:
+            return &main_clk;
+        case AT91C_PMC_CSS_PLLA_CLK:
+            return &plla;
+        case AT91C_PMC_CSS_UPLL_CLK:
+            return &upllck;
+    }
+
+    return RT_NULL;
 }
 
 // TODO: how to auto-set register value by OSC and MCK
 /* Settings at 400/133MHz */
 // In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we
 // configure OSC startup timeout to 64*8/32768=15.6ms, should enough
-#define BOARD_OSCOUNT			(AT91C_CKGR_OSCOUNT & (64 << 8))
+#define BOARD_OSCOUNT           (AT91C_CKGR_OSCOUNT & (64 << 8))
 // MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK
-// pls. refer to doc6438G figure 24-6 on pg294.		ICPLLA in reg PMC_PLLICPR
+// pls. refer to doc6438G figure 24-6 on pg294.     ICPLLA in reg PMC_PLLICPR
 // 12MHz / 3 * (199 + 1) = 800MHz
 // OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50
 // PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms
-#define BOARD_CKGR_PLLA			(AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
-#define BOARD_PLLACOUNT			(0x3F << 8)
-#define BOARD_MULA				(AT91C_CKGR_MULA & (199 << 16))
-#define BOARD_DIVA				(AT91C_CKGR_DIVA & 3)
+#define BOARD_CKGR_PLLA         (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0)
+#define BOARD_PLLACOUNT         (0x3F << 8)
+#define BOARD_MULA              (AT91C_CKGR_MULA & (199 << 16))
+#define BOARD_DIVA              (AT91C_CKGR_DIVA & 3)
 // Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK
 //                                                => Processor Clock Divider => PCK
 // Master clock can refer to doc6438G figure 25-2 on pg298
 // PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz),
 // MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock)
-#define BOARD_PRESCALER			(0x00001300) //400/133MHz
+#define BOARD_PRESCALER         (0x00001300) //400/133MHz
 
-#define MHz(n)		((n) * 1000 * 1000)
-#define OSC_FREQ	MHz(12)
-#define PLLA_FREQ	MHz(800)
+#define MHz(n)      ((n) * 1000 * 1000)
+#define OSC_FREQ    MHz(12)
+#define PLLA_FREQ   MHz(800)
 
 static void at91_plla_init(void)
 {
-	rt_uint32_t pllar, mckr;
-
-	// Code refer to doc6438G, 25.10 Programming Sequence
-	/* Initialize main oscillator
-	 ****************************/
-	// enable main OSC and wait OSC startup time timeout.
-	AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
-	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
-
-	/* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */
-	pllar = (MHz(800) - PLLA_FREQ) / MHz(50);		// please refer to Table 46-15 of doc 6438G
-	AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1;	// ICPLLA
-	pllar = (pllar & 3) << 14;	// OUTA
-	pllar |= BOARD_DIVA;		// PLLA input clock as 4MHz
-	pllar |= BOARD_MULA;		// PLLA output clock as 800MHz
-	pllar |= BOARD_PLLACOUNT;
-	pllar |= AT91C_CKGR_SRCA;	// I don't known what means, but seems must set it
-	AT91C_BASE_PMC->PMC_PLLAR = pllar;
-
-	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
-
-	/* Wait for the master clock if it was already initialized */
-	// make sure Master clock in READY status before operate it
-	while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
-
-	/* Switch to fast clock
-	 **********************/
-	/* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */
-	mckr = AT91C_BASE_PMC->PMC_MCKR;
-	if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV))
-	{
-		mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV);
-		AT91C_BASE_PMC->PMC_MCKR = mckr;
-		while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
-	}
-
-	/* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */
-	if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK)
-	{
-		mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK;
-		AT91C_BASE_PMC->PMC_MCKR = mckr;
-		while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
-	}
-
-	plla.rate_hz = PLLA_FREQ;
+    rt_uint32_t pllar, mckr;
+
+    // Code refer to doc6438G, 25.10 Programming Sequence
+    /* Initialize main oscillator
+     ****************************/
+    // enable main OSC and wait OSC startup time timeout.
+    AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+
+    /* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */
+    pllar = (MHz(800) - PLLA_FREQ) / MHz(50);       // please refer to Table 46-15 of doc 6438G
+    AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA
+    pllar = (pllar & 3) << 14;  // OUTA
+    pllar |= BOARD_DIVA;        // PLLA input clock as 4MHz
+    pllar |= BOARD_MULA;        // PLLA output clock as 800MHz
+    pllar |= BOARD_PLLACOUNT;
+    pllar |= AT91C_CKGR_SRCA;   // I don't known what means, but seems must set it
+    AT91C_BASE_PMC->PMC_PLLAR = pllar;
+
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
+
+    /* Wait for the master clock if it was already initialized */
+    // make sure Master clock in READY status before operate it
+    while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+    /* Switch to fast clock
+     **********************/
+    /* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */
+    mckr = AT91C_BASE_PMC->PMC_MCKR;
+    if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV))
+    {
+        mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV);
+        AT91C_BASE_PMC->PMC_MCKR = mckr;
+        while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+    }
+
+    /* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */
+    if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK)
+    {
+        mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK;
+        AT91C_BASE_PMC->PMC_MCKR = mckr;
+        while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+    }
+
+    plla.rate_hz = PLLA_FREQ;
 }
-    
+
 #define false 0
 #define true  1
 int at91_clock_init(rt_uint32_t main_clock)
 {
-	unsigned tmp, freq, mckr, mdiv;
-	int i;
-
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = readl(AT91C_CKGR_MCFR);
-		} while (!(tmp & AT91C_CKGR_MAINRDY));
-		main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16);
-	}
-	main_clk.rate_hz = main_clock;
-
-	at91_plla_init();
-
-	at91_upllck_init(main_clock);
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = readl(AT91C_PMC_MCKR);
-	mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS);
-	freq = mck.parent->rate_hz;
-	freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2));	/* prescale */
-	mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8);
-	if (mdiv == 8) mdiv = 3;
-	freq /= mdiv;			/* mdiv */
-	if (mckr & AT91C_PMC_PLLADIV2) freq /= 2;	/* plla_div2 */
-	mck.rate_hz = freq;	
-
-	/* Register the PMC's standard clocks */
-	rt_list_init(&clocks);
-	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
-
-	rt_list_insert_after(&clocks, &upllck.node);
-
-	/* MCK and CPU clock are "always on" */
-	//clk_enable(&mck);
-
-	/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-		(unsigned) main_clock / 1000000,
-		((unsigned) main_clock % 1000000) / 1000);*///cause blocked
-
-	return 0;
+    unsigned tmp, freq, mckr, mdiv;
+    int i;
+
+    /*
+     * When the bootloader initialized the main oscillator correctly,
+     * there's no problem using the cycle counter.  But if it didn't,
+     * or when using oscillator bypass mode, we must be told the speed
+     * of the main clock.
+     */
+    if (!main_clock) {
+        do {
+            tmp = readl(AT91C_CKGR_MCFR);
+        } while (!(tmp & AT91C_CKGR_MAINRDY));
+        main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16);
+    }
+    main_clk.rate_hz = main_clock;
+
+    at91_plla_init();
+
+    at91_upllck_init(main_clock);
+
+    /*
+     * MCK and CPU derive from one of those primary clocks.
+     * For now, assume this parentage won't change.
+     */
+    mckr = readl(AT91C_PMC_MCKR);
+    mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS);
+    freq = mck.parent->rate_hz;
+    freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2));  /* prescale */
+    mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8);
+    if (mdiv == 8) mdiv = 3;
+    freq /= mdiv;           /* mdiv */
+    if (mckr & AT91C_PMC_PLLADIV2) freq /= 2;   /* plla_div2 */
+    mck.rate_hz = freq;
+
+    /* Register the PMC's standard clocks */
+    rt_list_init(&clocks);
+    for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+        rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+    rt_list_insert_after(&clocks, &upllck.node);
+
+    /* MCK and CPU clock are "always on" */
+    //clk_enable(&mck);
+
+    /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+        freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+        (unsigned) main_clock / 1000000,
+        ((unsigned) main_clock % 1000000) / 1000);*///cause blocked
+
+    return 0;
 }
 
 /**
@@ -265,6 +251,6 @@ int at91_clock_init(rt_uint32_t main_clock)
  */
 void rt_hw_clock_init(void)
 {
-	at91_clock_init(MHz(12));
+    at91_clock_init(MHz(12));
 }
 

bsp/avr32uc3b0/application.c

@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -56,7 +52,7 @@ int rt_application_init()
 {
     /* create led1 thread */
     rt_thread_init(&thread_led1,
-				   "led1",
+                   "led1",
                    rt_thread_entry_led1,
                    RT_NULL,
                    &thread_led1_stack[0],

bsp/avr32uc3b0/board.c

@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -20,11 +16,11 @@
 #include "intc.h"
 #include "serial.h"
 
-#define FOSC0	12000000
-#define FCPU	60000000
-#define FHSB	FCPU
-#define FPBA	FCPU
-#define FPBB	FCPU
+#define FOSC0   12000000
+#define FCPU    60000000
+#define FHSB    FCPU
+#define FPBA    FCPU
+#define FPBB    FCPU
 
 extern void rt_hw_serial_isr(void);
 extern void rt_hw_usart_init(void);
@@ -34,10 +30,10 @@ extern void rt_hw_usart_init(void);
  */
 static void rt_hw_timer_handler(void)
 {
-	// Clears the interrupt request.
-	Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
+    // Clears the interrupt request.
+    Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
 
-	rt_tick_increase();
+    rt_tick_increase();
 }
 
 /**
@@ -45,35 +41,35 @@ static void rt_hw_timer_handler(void)
  */
 static void peripherals_init(void)
 {
-	/*
-	 * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock
-	 */
-	pm_freq_param_t pm_freq_param =
-	{
-		.cpu_f = FCPU,
-		.pba_f = FPBA,
-		.osc0_f = FOSC0,
-		.osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC
-	};
-	pm_configure_clocks(&pm_freq_param);
+    /*
+     * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock
+     */
+    pm_freq_param_t pm_freq_param =
+    {
+        .cpu_f = FCPU,
+        .pba_f = FPBA,
+        .osc0_f = FOSC0,
+        .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC
+    };
+    pm_configure_clocks(&pm_freq_param);
 
-	/*
-	 * USART1 initialization
-	 */
-	gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION);
-	gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION);
-	static const usart_options_t usartOptions = {
-		.baudrate = 115200,
-		.charlength = 8,
-		.paritytype = USART_NO_PARITY,
-		.stopbits = USART_1_STOPBIT,
-		.channelmode = USART_NORMAL_CHMODE
-	};
-	usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU);
+    /*
+     * USART1 initialization
+     */
+    gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION);
+    gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION);
+    static const usart_options_t usartOptions = {
+        .baudrate = 115200,
+        .charlength = 8,
+        .paritytype = USART_NO_PARITY,
+        .stopbits = USART_1_STOPBIT,
+        .channelmode = USART_NORMAL_CHMODE
+    };
+    usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU);
 
-	INTC_init_interrupts();
-	INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0);
-	AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK;
+    INTC_init_interrupts();
+    INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0);
+    AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK;
 }
 
 /**
@@ -81,21 +77,21 @@ static void peripherals_init(void)
  */
 static void cpu_counter_init(void)
 {
-	INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3);
-	Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
-	Set_system_register(AVR32_COUNT, 0);
+    INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3);
+    Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
+    Set_system_register(AVR32_COUNT, 0);
 }
 
 void rt_hw_board_init(void)
 {
-	extern struct rt_device _rt_usart_device;
-	extern struct avr32_serial_device uart;
+    extern struct rt_device _rt_usart_device;
+    extern struct avr32_serial_device uart;
 
-	Disable_global_interrupt();
+    Disable_global_interrupt();
 
-	peripherals_init();
-	cpu_counter_init();
+    peripherals_init();
+    cpu_counter_init();
 
-	rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart);
-	rt_console_set_device("uart1");
+    rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart);
+    rt_console_set_device("uart1");
 }

bsp/avr32uc3b0/rtconfig.h

@@ -1,11 +1,7 @@
 /*
- * File      : rtconfig.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -16,16 +12,16 @@
 #define RTCONFIG_H_
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug*/
@@ -73,7 +69,7 @@
 /* SECTION: Console options */
 /* the buffer size of console*/
 #define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: FinSH shell options */
 /* Using FinSH as Shell*/
@@ -88,21 +84,21 @@
 
 #define RT_USING_DFS_ELMFAT
 #define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_DRIVES			2
+#define RT_DFS_ELM_DRIVES           2
 
 /* SECTION: DFS options */
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					8
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		4
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  8
+/* the max number of cached sector      */
+#define DFS_CACHE_MAX_NUM           4
 
 /* SECTION: RT-Thread/GUI */
 //#define RT_USING_RTGUI
 
 /* name length of RTGUI object */
-#define RTGUI_NAME_MAX		12
+#define RTGUI_NAME_MAX      12
 /* support 16 weight font */
 #define RTGUI_USING_FONT16
 /* support Chinese font */
@@ -116,6 +112,6 @@
 /* use mouse cursor */
 /* #define RTGUI_USING_MOUSE_CURSOR */
 /* default font size in RTGUI */
-#define RTGUI_DEFAULT_FONT_SIZE	16
+#define RTGUI_DEFAULT_FONT_SIZE 16
 
 #endif /* RTCONFIG_H_ */

bsp/avr32uc3b0/startup.c

@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -25,19 +21,19 @@ extern void finsh_set_device(const char* device);
 int main(void)
 {
 #ifdef RT_USING_HEAP
-	extern void __heap_start__;
-	extern void __heap_end__;
+    extern void __heap_start__;
+    extern void __heap_end__;
 #endif
 
-	rt_hw_board_init();
-	rt_system_timer_init();
+    rt_hw_board_init();
+    rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
-	rt_system_heap_init(&__heap_start__, &__heap_end__);
+    rt_system_heap_init(&__heap_start__, &__heap_end__);
 #endif
 
-	rt_system_scheduler_init();
-	rt_application_init();
+    rt_system_scheduler_init();
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
     /* init finsh */
@@ -46,7 +42,7 @@ int main(void)
 #endif
 
     rt_thread_idle_init();
-	rt_system_scheduler_start();
+    rt_system_scheduler_start();
 
-	return 0;
+    return 0;
 }

bsp/beaglebone/applications/board.c

@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -49,7 +45,7 @@ static rt_uint32_t DMTIMER = 0;
 
 static void rt_hw_timer_isr(int vector, void* param)
 {
-	rt_tick_increase();
+    rt_tick_increase();
 
     DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
 }
@@ -71,73 +67,73 @@ static void timer_clk_init(void)
     while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
         ;
 
-	/* Select the clock source for the Timer2 instance.  */
-	CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
-	/* 32k clock source */
-	CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
+    /* Select the clock source for the Timer2 instance.  */
+    CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
+    /* 32k clock source */
+    CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
 
-	while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
-		CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
+    while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
+        CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
 
-	/* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
-	CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
+    /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
+    CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
 
-	/* Waiting for MODULEMODE field to reflect the written value. */
-	while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
-		CM_PER_CLKCTRL_MODULEMODE_ENABLE);
+    /* Waiting for MODULEMODE field to reflect the written value. */
+    while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
+        CM_PER_CLKCTRL_MODULEMODE_ENABLE);
 
-	/*
-	 * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register 
-	 * for the module is fully functional.
-	 */
-	while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
-		CM_PER_CLKCTRL_IDLEST_FUNC);
+    /*
+     * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register
+     * for the module is fully functional.
+     */
+    while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
+        CM_PER_CLKCTRL_IDLEST_FUNC);
 
-	/* Waiting for the L4LS clock */
-	while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
-	/* Waiting for the TIMER7 clock */
-	while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
+    /* Waiting for the L4LS clock */
+    while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
+    /* Waiting for the TIMER7 clock */
+    while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
 }
 
 int rt_hw_timer_init(void)
 {
-	rt_uint32_t counter;
+    rt_uint32_t counter;
 
 #ifdef RT_USING_VMM
     DMTIMER = vmm_find_iomap("TIMER7");
 #endif
 
-	timer_clk_init();
+    timer_clk_init();
 
-	/* soft reset the timer */
-	DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
+    /* soft reset the timer */
+    DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
     while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1)
         ;
 
-	/* calculate count */
-	counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
+    /* calculate count */
+    counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
 
-	/* set initial count */
-	DMTIMER_TCRR(TIMER_HW_BASE) = counter;
-	/* set reload count */
-	DMTIMER_TLDR(TIMER_HW_BASE) = counter;
+    /* set initial count */
+    DMTIMER_TCRR(TIMER_HW_BASE) = counter;
+    /* set reload count */
+    DMTIMER_TLDR(TIMER_HW_BASE) = counter;
 
-	/* set mode: auto reload */
-	DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
+    /* set mode: auto reload */
+    DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
 
-	/* interrupt enable for match */
-	DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
+    /* interrupt enable for match */
+    DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
     DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
 
-	rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
-	rt_hw_interrupt_control(TINT7, 0, 0);
-	rt_hw_interrupt_umask(TINT7);
+    rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_control(TINT7, 0, 0);
+    rt_hw_interrupt_umask(TINT7);
 
     while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
         ;
 
-	/* start timer */
-	DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
+    /* start timer */
+    DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
 
     while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
         ;
@@ -152,7 +148,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init);
 void rt_hw_board_init(void)
 {
     rt_components_board_init();
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 }
 
 void rt_hw_cpu_reset(void)

bsp/beaglebone/applications/board.h

@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/beaglebone/drivers/gpio.c

@@ -1,11 +1,7 @@
 /*
- * File      : gpio.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  */
 

bsp/beaglebone/drivers/gpio.h

@@ -1,11 +1,7 @@
 /*
- * File      : gpio.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2015, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  */
 

bsp/beaglebone/drivers/uart.c

@@ -1,11 +1,7 @@
 /*
- * File      : serial.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/beaglebone/drivers/uart.h

@@ -1,11 +1,7 @@
 /*
- * File      : serial.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/bf533/application.c

@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date         Author      Notes

bsp/bf533/application.h

@@ -1,11 +1,7 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date         Author      Notes

bsp/bf533/board.c

@@ -1,11 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date         Author      Notes
@@ -242,7 +238,7 @@ void rt_hw_isr_install(void)
     *pSIC_IAR1 &= IVG_CLR(IAR1_DMA6_UARTRX_IVG);
     *pSIC_IAR1 |= IVG_SET(IAR1_DMA6_UARTRX_IVG,ik_ivg9);
     register_handler(ik_ivg9,uart_rx_isr);
-    *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/*  ¿ªÖÐ¶Ï      */
+    *pSIC_IMASK |= DMA6_UART_RX_INT_MASK;/*  开中断      */
 }
 
 void rt_hw_board_init(void)

bsp/bf533/board.h

@@ -1,11 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date         Author      Notes
@@ -23,7 +19,7 @@
 #define CLOCKS_PER_SECD CCLKSPEED
 #define SCLOCKS_PER_SEC SCLKSPEED
 
-//SIC_IMASK¼Ä´æÆ÷
+//SIC_IMASK寄存器
 #define PLL_WAKEUP_INT_MASK     0x00000001
 #define DMA_ERROR_INT_MASK      0x00000002
 #define PPI_ERROR_INT_MASK      0x00000004

bsp/bf533/startup.c

@@ -1,11 +1,7 @@
 /*
- * File      : startup.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date         Author      Notes

bsp/ck802/applications/main.c

@@ -1,22 +1,8 @@
 
 /*
- * File      : clock.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/ck802/drivers/board.c

@@ -1,21 +1,7 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/ck802/drivers/board.h

@@ -1,21 +1,7 @@
 /*
- * File      : board.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/ck802/drivers/board_coretimer.c

@@ -1,21 +1,7 @@
 /*
- * File      : board_coretimer.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/ck802/drivers/board_coretimer.h

@@ -1,21 +1,7 @@
 /*
- * File      : board_coretimer.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/ck802/drivers/board_uart.c

@@ -1,21 +1,7 @@
 /*
- * File      : board_uart.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes

bsp/ck802/libraries/startup_gcc.S

@@ -1,21 +1,7 @@
 /*
- * File      : startup.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -24,10 +10,10 @@
 
 
 #undef  VIC_TSPR
-#define VIC_TSPR  					0xE000EC10
+#define VIC_TSPR                    0xE000EC10
 
 #ifndef CONFIG_SEPARATE_IRQ_SP
-#define CONFIG_SEPARATE_IRQ_SP  	1
+#define CONFIG_SEPARATE_IRQ_SP      1
 #endif
 
 #ifndef CONFIG_ARCH_INTERRUPTSTACK
@@ -37,81 +23,81 @@
 .import SysTick_Handler
 .import PendSV_Handler
 
-	.section .vectors
-	.align 10
-	.globl	__Vectors
-	.type	__Vectors, @object
+    .section .vectors
+    .align 10
+    .globl  __Vectors
+    .type   __Vectors, @object
 __Vectors:
-	.long	Reset_Handler         /* 0: Reset Handler */
-    
-	.rept   15
-	.long   Default_Handler       /* 60 0x40 */
-	.endr                         /* 64 0x40 */
-    
-	.long   Default_Handler       /* 64 0x44 */
-    
-	.rept   5
-	.long   Default_Handler       /* 88 0x58 */
-	.endr                         /* 92 0x5C */
-    
-	.long   PendSV_Handler        /* 92 0x5C */
-    
-	.rept	9
-	.long	Default_Handler       /* 128 0x80 */
-	.endr
-
-	/* External interrupts */
-	.long	GPIOA_IRQHandler         /*  32#  0:  GPIOA           */ /*128  0x80 */
-	.long   SysTick_Handler          /*  1:  System Tick     */
-	.long	TIMA0_IRQHandler         /*  2:  TimerA0         */
-	.long	TIMA1_IRQHandler         /*  3:  TimerA1         */
-	.long	Default_Handler
-	.long	WDT_IRQHandler           /*  5:  WDT            */
-	.long	USART0_IRQHandler        /*  6:  UART0          */
-	.long	USART1_IRQHandler        /*  0x27 39 7:  UART1          */
-	.long	USART2_IRQHandler        /*  8:  UART2          */
-	.long	I2C0_IRQHandler          /*  9:  I2C0           */
-	.long	I2C1_IRQHandler          /*  10: I2C1           */
-	.long	SPI1_IRQHandler          /*  11: SPI1           */
-	.long	SPI0_IRQHandler          /*  12: SPI0           */
-	.long	RTC_IRQHandler           /*  13: RTC            */
-	.long	Default_Handler
-	.long	Default_Handler
-	.long	Default_Handler
-	.long	DMAC_IRQHandler          /*  17: DMAC           */
-	.long	Default_Handler
-	.long	PWM_IRQHandler           /*  19: PWM            */
-	.long	Default_Handler
-	.long	USART3_IRQHandler        /*  21: UART3          */
-	.long	Default_Handler
-	.long	TIMB0_IRQHandler         /*  23: TimerB0        */
-	.long	TIMB1_IRQHandler         /*  24: TimerB1        */
-	.long	Default_Handler
-	.long   AES_IRQHandler           /*  26:  AES            */
-	.long	GPIOB_IRQHandler         /*  27:  GPIOB          */
-	.long	Default_Handler
-	.long   SHA_IRQHandler           /*  29:  SHA            */
-
-	.size	__Vectors, . - __Vectors
-
-	.text
-	.align	1
+    .long   Reset_Handler         /* 0: Reset Handler */
+
+    .rept   15
+    .long   Default_Handler       /* 60 0x40 */
+    .endr                         /* 64 0x40 */
+
+    .long   Default_Handler       /* 64 0x44 */
+
+    .rept   5
+    .long   Default_Handler       /* 88 0x58 */
+    .endr                         /* 92 0x5C */
+
+    .long   PendSV_Handler        /* 92 0x5C */
+
+    .rept   9
+    .long   Default_Handler       /* 128 0x80 */
+    .endr
+
+    /* External interrupts */
+    .long   GPIOA_IRQHandler         /*  32#  0:  GPIOA           */ /*128  0x80 */
+    .long   SysTick_Handler          /*  1:  System Tick     */
+    .long   TIMA0_IRQHandler         /*  2:  TimerA0         */
+    .long   TIMA1_IRQHandler         /*  3:  TimerA1         */
+    .long   Default_Handler
+    .long   WDT_IRQHandler           /*  5:  WDT            */
+    .long   USART0_IRQHandler        /*  6:  UART0          */
+    .long   USART1_IRQHandler        /*  0x27 39 7:  UART1          */
+    .long   USART2_IRQHandler        /*  8:  UART2          */
+    .long   I2C0_IRQHandler          /*  9:  I2C0           */
+    .long   I2C1_IRQHandler          /*  10: I2C1           */
+    .long   SPI1_IRQHandler          /*  11: SPI1           */
+    .long   SPI0_IRQHandler          /*  12: SPI0           */
+    .long   RTC_IRQHandler           /*  13: RTC            */
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   Default_Handler
+    .long   DMAC_IRQHandler          /*  17: DMAC           */
+    .long   Default_Handler
+    .long   PWM_IRQHandler           /*  19: PWM            */
+    .long   Default_Handler
+    .long   USART3_IRQHandler        /*  21: UART3          */
+    .long   Default_Handler
+    .long   TIMB0_IRQHandler         /*  23: TimerB0        */
+    .long   TIMB1_IRQHandler         /*  24: TimerB1        */
+    .long   Default_Handler
+    .long   AES_IRQHandler           /*  26:  AES            */
+    .long   GPIOB_IRQHandler         /*  27:  GPIOB          */
+    .long   Default_Handler
+    .long   SHA_IRQHandler           /*  29:  SHA            */
+
+    .size   __Vectors, . - __Vectors
+
+    .text
+    .align  1
 _start:
-	.text
-	.align	1
-	.globl	Reset_Handler
-	.type	Reset_Handler, %function
+    .text
+    .align  1
+    .globl  Reset_Handler
+    .type   Reset_Handler, %function
 Reset_Handler:
     /* under normal circumstances,  it should not be opened */
 
 #ifndef CONFIG_SYSTEM_SECURE
-    lrw   	r0, 0x80000000
-    mtcr  	r0, psr
+    lrw     r0, 0x80000000
+    mtcr    r0, psr
 #endif
 
 /* Initialize the normal stack pointer from the linker definition. */
-    lrw 	a1, __StackTop
-    mov 	sp, a1
+    lrw     a1, __StackTop
+    mov     sp, a1
 
 /*
  *  The ranges of copy from/to are specified by following symbols
@@ -121,22 +107,22 @@ Reset_Handler:
  *
  *  All addresses must be aligned to 4 bytes boundary.
  */
-	lrw		r1, __erodata
-	lrw		r2, __data_start__
-	lrw		r3, __data_end__
+    lrw     r1, __erodata
+    lrw     r2, __data_start__
+    lrw     r3, __data_end__
 
-	subu	r3, r2
-	cmpnei	r3, 0
-	bf		.L_loop0_done
+    subu    r3, r2
+    cmpnei  r3, 0
+    bf      .L_loop0_done
 
 .L_loop0:
-	ldw		r0, (r1, 0)
-	stw		r0, (r2, 0)
-	addi	r1, 4
-	addi	r2, 4
-	subi	r3, 4
-	cmpnei	r3, 0
-	bt		.L_loop0
+    ldw     r0, (r1, 0)
+    stw     r0, (r2, 0)
+    addi    r1, 4
+    addi    r2, 4
+    subi    r3, 4
+    cmpnei  r3, 0
+    bt      .L_loop0
 
 .L_loop0_done:
 
@@ -147,98 +133,98 @@ Reset_Handler:
  *
  *  Both addresses must be aligned to 4 bytes boundary.
  */
-	lrw		r1, __bss_start__
-	lrw		r2, __bss_end__
+    lrw     r1, __bss_start__
+    lrw     r2, __bss_end__
 
-	movi	r0, 0
+    movi    r0, 0
 
-	subu	r2, r1
-	cmpnei	r2, 0
-	bf		.L_loop1_done
+    subu    r2, r1
+    cmpnei  r2, 0
+    bf      .L_loop1_done
 
 .L_loop1:
-	stw		r0, (r1, 0)
-	addi	r1, 4
-	subi	r2, 4
-	cmpnei	r2, 0
-	bt		.L_loop1
+    stw     r0, (r1, 0)
+    addi    r1, 4
+    subi    r2, 4
+    cmpnei  r2, 0
+    bt      .L_loop1
 .L_loop1_done:
 
 #ifdef CONFIG_SEPARATE_IRQ_SP
-    lrw    	r0, g_top_irqstack
-    mtcr   	r0, cr<15, 1>
+    lrw     r0, g_top_irqstack
+    mtcr    r0, cr<15, 1>
 
-    mfcr   	r0, cr<31, 0>
-    bseti  	r0, 14
-    mtcr   	r0, cr<31, 0>
+    mfcr    r0, cr<31, 0>
+    bseti   r0, 14
+    mtcr    r0, cr<31, 0>
 #endif
 
 #ifndef __NO_SYSTEM_INIT
-	bsr		SystemInit
+    bsr     SystemInit
 #endif
 
 //#ifndef __NO_BOARD_INIT
-//	bsr		board_init
+//  bsr     board_init
 //#endif
 
 //VIC init...
-	lrw    r0, VIC_TSPR
-	movi   r1, 0xb00
-	stw    r1, (r0)
+    lrw    r0, VIC_TSPR
+    movi   r1, 0xb00
+    stw    r1, (r0)
 
-	bsr	entry
+    bsr entry
 
 __exit:
-	bkpt
-	.size	Reset_Handler, . - Reset_Handler
+    bkpt
+    .size   Reset_Handler, . - Reset_Handler
 
-	.align	1
-	.weak	Default_Handler
-	.type	Default_Handler, %function
+    .align  1
+    .weak   Default_Handler
+    .type   Default_Handler, %function
 Default_Handler:
-	br		Default_Handler
-	.size	Default_Handler, . - Default_Handler
+    br      Default_Handler
+    .size   Default_Handler, . - Default_Handler
 
 .section .bss
 
-	.align  2
-	.globl  g_intstackalloc
-	.global g_intstackbase
-	.global g_top_irqstack
+    .align  2
+    .globl  g_intstackalloc
+    .global g_intstackbase
+    .global g_top_irqstack
 g_intstackalloc:
 g_intstackbase:
-	.space CONFIG_ARCH_INTERRUPTSTACK
+    .space CONFIG_ARCH_INTERRUPTSTACK
 g_top_irqstack:
 
 /*    Macro to define default handlers. Default handler
  *    will be weak symbol and just dead loops. They can be
  *    overwritten by other handlers */
-	.macro	def_irq_handler	handler_name
-	.weak	\handler_name
-	.set	\handler_name, Default_Handler
-	.endm
-
-	def_irq_handler	CORET_IRQHandler
-	def_irq_handler TIMA0_IRQHandler
-	def_irq_handler TIMA1_IRQHandler
-	def_irq_handler TIMB0_IRQHandler
-	def_irq_handler TIMB1_IRQHandler
-	def_irq_handler	USART0_IRQHandler
-	def_irq_handler	USART1_IRQHandler
-	def_irq_handler	USART2_IRQHandler
-	def_irq_handler	USART3_IRQHandler
-	def_irq_handler	GPIOA_IRQHandler
-	def_irq_handler	GPIOB_IRQHandler
-	def_irq_handler	I2C0_IRQHandler
-	def_irq_handler	I2C1_IRQHandler
-	def_irq_handler	SPI0_IRQHandler
-	def_irq_handler	SPI1_IRQHandler
-	def_irq_handler	RTC_IRQHandler
-	def_irq_handler	WDT_IRQHandler
-	def_irq_handler	PWM_IRQHandler
-	def_irq_handler	DMAC_IRQHandler
-	def_irq_handler AES_IRQHandler
-	def_irq_handler SHA_IRQHandler
-
-	.end
+    .macro  def_irq_handler handler_name
+    .weak   \handler_name
+    .set    \handler_name, Default_Handler
+    .endm
+
+    def_irq_handler CORET_IRQHandler
+    def_irq_handler TIMA0_IRQHandler
+    def_irq_handler TIMA1_IRQHandler
+    def_irq_handler TIMB0_IRQHandler
+    def_irq_handler TIMB1_IRQHandler
+    def_irq_handler USART0_IRQHandler
+    def_irq_handler USART1_IRQHandler
+    def_irq_handler USART2_IRQHandler
+    def_irq_handler USART3_IRQHandler
+    def_irq_handler GPIOA_IRQHandler
+    def_irq_handler GPIOB_IRQHandler
+    def_irq_handler I2C0_IRQHandler
+    def_irq_handler I2C1_IRQHandler
+    def_irq_handler SPI0_IRQHandler
+    def_irq_handler SPI1_IRQHandler
+    def_irq_handler RTC_IRQHandler
+    def_irq_handler WDT_IRQHandler
+    def_irq_handler PWM_IRQHandler
+    def_irq_handler DMAC_IRQHandler
+    def_irq_handler AES_IRQHandler
+    def_irq_handler SHA_IRQHandler
+
+    .end
 

bsp/dm365/applications/application.c

@@ -1,25 +1,11 @@
 /*
- * File      : application.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 
@@ -41,57 +27,57 @@
 
 int main(void)
 {
-	int timeout = 0;
+    int timeout = 0;
 
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
+    {
 
 #if defined(RT_USING_DFS_ROMFS)
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
+        if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+        {
+            rt_kprintf("ROM File System initialized!\n");
+        }
+        else
+            rt_kprintf("ROM File System initialzation failed!\n");
 #endif
 
 #if defined(RT_USING_DFS_UFFS)
-	{
-		/* mount flash device as flash directory */
-		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-	}
+    {
+        /* mount flash device as flash directory */
+        if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+            rt_kprintf("UFFS File System initialized!\n");
+        else
+            rt_kprintf("UFFS File System initialzation failed!\n");
+    }
 #endif
 
 #ifdef RT_USING_SDIO
-	timeout = 0;
-	while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
-	{
-		rt_thread_delay(1);
-	}
-
-	if (timeout < RT_TICK_PER_SECOND*2)
-	{
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
-	}
-	else
-	{
-		rt_kprintf("No SD card found.\n");
-	}
+    timeout = 0;
+    while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
+    {
+        rt_thread_delay(1);
+    }
+
+    if (timeout < RT_TICK_PER_SECOND*2)
+    {
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+        {
+            rt_kprintf("File System initialized!\n");
+        }
+        else
+            rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
+    }
+    else
+    {
+        rt_kprintf("No SD card found.\n");
+    }
 #endif
-	}
+    }
 #endif
 
-	/* put user application code here */
+    /* put user application code here */
 
 }
 
@@ -101,14 +87,14 @@ int main(void)
 #include <dfs_nfs.h>
 void nfs_start(void)
 {
-	nfs_init();
-
-	if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-	{
-		rt_kprintf("NFSv3 File System initialized!\n");
-	}
-	else
-		rt_kprintf("NFSv3 File System initialzation failed!\n");
+    nfs_init();
+
+    if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
+    {
+        rt_kprintf("NFSv3 File System initialized!\n");
+    }
+    else
+        rt_kprintf("NFSv3 File System initialzation failed!\n");
 }
 
 #include "finsh.h"

bsp/dm365/applications/board.c

@@ -1,25 +1,11 @@
 /*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -33,28 +19,28 @@
  */
 /*@{*/
 #if defined(__CC_ARM)
-	extern int Image$$ER_ZI$$ZI$$Base;
-	extern int Image$$ER_ZI$$ZI$$Length;
-	extern int Image$$ER_ZI$$ZI$$Limit;
+    extern int Image$$ER_ZI$$ZI$$Base;
+    extern int Image$$ER_ZI$$ZI$$Length;
+    extern int Image$$ER_ZI$$ZI$$Limit;
 #elif (defined (__GNUC__))
-	rt_uint8_t _irq_stack_start[1024];
-	rt_uint8_t _fiq_stack_start[1024];
-	rt_uint8_t _undefined_stack_start[512];
-	rt_uint8_t _abort_stack_start[512];
-	rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss");
-	extern unsigned char __bss_start;
-	extern unsigned char __bss_end;
+    rt_uint8_t _irq_stack_start[1024];
+    rt_uint8_t _fiq_stack_start[1024];
+    rt_uint8_t _undefined_stack_start[512];
+    rt_uint8_t _abort_stack_start[512];
+    rt_uint8_t _svc_stack_start[1024] RT_SECTION(".nobss");
+    extern unsigned char __bss_start;
+    extern unsigned char __bss_end;
 #endif
 
 extern void rt_hw_clock_init(void);
 extern void rt_hw_uart_init(void);
 
 static struct mem_desc dm365_mem_desc[] = {
-	{ 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED },       /* 128M cached SDRAM memory */
-	{ 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED },     /* 128M No cached SDRAM memory */
-	{ 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */
-	{ 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* CFG BUS peripherals */
-	{ 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* AEMIF */
+    { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED },       /* 128M cached SDRAM memory */
+    { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED },     /* 128M No cached SDRAM memory */
+    { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */
+    { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* CFG BUS peripherals */
+    { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* AEMIF */
 };
 
 
@@ -63,7 +49,7 @@ static struct mem_desc dm365_mem_desc[] = {
  */
 void rt_timer_handler(int vector, void *param)
 {
-	rt_tick_increase();
+    rt_tick_increase();
 }
 
 /**
@@ -71,70 +57,70 @@ void rt_timer_handler(int vector, void *param)
  */
  void rt_hw_timer_init()
  {
-	/* timer0, input clocks 24MHz */
-	volatile timer_regs_t *regs =
-		(volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE;
+    /* timer0, input clocks 24MHz */
+    volatile timer_regs_t *regs =
+        (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE;
+
+    psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3);
+    psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3);
 
-	psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3);
-	psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3);
+    /*disable timer*/
+    regs->tcr &= ~(0x3UL << 6);
 
-	/*disable timer*/
-	regs->tcr &= ~(0x3UL << 6);
+    //TIMMODE 32BIT UNCHAINED MODE
+    regs->tgcr |=(0x1UL << 2);
 
-	//TIMMODE 32BIT UNCHAINED MODE
-	regs->tgcr |=(0x1UL << 2);
+    /*not in reset timer */
+    regs->tgcr |= (0x1UL << 0);
 
-	/*not in reset timer */
-	regs->tgcr |= (0x1UL << 0);
+    //regs->tgcr &= ~(0x1UL << 1);
 
-	//regs->tgcr &= ~(0x1UL << 1);
+    /* set Period Registers */
+    regs->prd12 = 24000000/RT_TICK_PER_SECOND;
+    regs->tim12 = 0;
 
-	/* set Period Registers */
-	regs->prd12 = 24000000/RT_TICK_PER_SECOND;
-	regs->tim12 = 0;
+    /* Set enable mode */
+    regs->tcr |= (0x2UL << 6); //period mode
 
-	/* Set enable mode */
-	regs->tcr |= (0x2UL << 6); //period mode
-	
 
-	/* install interrupt handler */
-	rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler,
-							RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12
-	rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2
+    /* install interrupt handler */
+    rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler,
+                            RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12
+    rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2
 
  }
 
-#define LSR_DR		0x01		/* Data ready */
-#define LSR_THRE	0x20		/* Xmit holding register empty */
-#define BPS			115200	/* serial baudrate */
+#define LSR_DR      0x01        /* Data ready */
+#define LSR_THRE    0x20        /* Xmit holding register empty */
+#define BPS         115200  /* serial baudrate */
 
 typedef struct uartport
 {
-	volatile rt_uint32_t rbr;
-	volatile rt_uint32_t ier;
-	volatile rt_uint32_t fcr;
-	volatile rt_uint32_t lcr;
-	volatile rt_uint32_t mcr;
-	volatile rt_uint32_t lsr;
-	volatile rt_uint32_t msr;
-	volatile rt_uint32_t scr;
-	volatile rt_uint32_t dll;
-	volatile rt_uint32_t dlh;
-	
-	volatile rt_uint32_t res[2];
-	volatile rt_uint32_t pwremu_mgmt;
-	volatile rt_uint32_t mdr;
+    volatile rt_uint32_t rbr;
+    volatile rt_uint32_t ier;
+    volatile rt_uint32_t fcr;
+    volatile rt_uint32_t lcr;
+    volatile rt_uint32_t mcr;
+    volatile rt_uint32_t lsr;
+    volatile rt_uint32_t msr;
+    volatile rt_uint32_t scr;
+    volatile rt_uint32_t dll;
+    volatile rt_uint32_t dlh;
+
+    volatile rt_uint32_t res[2];
+    volatile rt_uint32_t pwremu_mgmt;
+    volatile rt_uint32_t mdr;
 }uartport;
 
 #define thr rbr
 #define iir fcr
 
-#define UART0	((struct uartport *)DAVINCI_UART0_BASE)
+#define UART0   ((struct uartport *)DAVINCI_UART0_BASE)
 
 static void davinci_uart_putc(char c)
 {
     while (!(UART0->lsr & LSR_THRE));
-	UART0->thr = c;
+    UART0->thr = c;
 }
 
 /**
@@ -145,35 +131,35 @@ static void davinci_uart_putc(char c)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
-		if (*str=='\n')
-		{
-			davinci_uart_putc('\r');
-		}
-
-		davinci_uart_putc(*str++);
-	}
+    while (*str)
+    {
+        if (*str=='\n')
+        {
+            davinci_uart_putc('\r');
+        }
+
+        davinci_uart_putc(*str++);
+    }
 }
 
 static void rt_hw_console_init(void)
 {
-	rt_uint32_t divisor;
-	
-	divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS);
-	UART0->ier = 0;
-	UART0->lcr = 0x83; //8N1
-	UART0->dll = 0;
-	UART0->dlh = 0;
-	UART0->lcr = 0x03;
-	UART0->mcr = 0x03; //RTS,CTS
-	UART0->fcr = 0x07; //FIFO
-	UART0->lcr = 0x83;
-	UART0->dll = divisor & 0xff;
-	UART0->dlh = (divisor >> 8) & 0xff;
-	UART0->lcr = 0x03;
-	UART0->mdr = 0; //16x over-sampling
-	UART0->pwremu_mgmt = 0x6000;
+    rt_uint32_t divisor;
+
+    divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS);
+    UART0->ier = 0;
+    UART0->lcr = 0x83; //8N1
+    UART0->dll = 0;
+    UART0->dlh = 0;
+    UART0->lcr = 0x03;
+    UART0->mcr = 0x03; //RTS,CTS
+    UART0->fcr = 0x07; //FIFO
+    UART0->lcr = 0x83;
+    UART0->dll = divisor & 0xff;
+    UART0->dlh = (divisor >> 8) & 0xff;
+    UART0->lcr = 0x03;
+    UART0->mdr = 0; //16x over-sampling
+    UART0->pwremu_mgmt = 0x6000;
 }
 
 /**
@@ -181,35 +167,35 @@ static void rt_hw_console_init(void)
  */
 void rt_hw_board_init()
 {
-	/* initialize console */
-	rt_hw_console_init();
+    /* initialize console */
+    rt_hw_console_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0]));
+    /* initialize mmu */
+    rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0]));
 
-	/* initialize hardware interrupt */
-	rt_hw_interrupt_init();
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize the system clock */
-	rt_hw_clock_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
 
-	/* initialize heap memory system */
+    /* initialize heap memory system */
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000);
+    rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000);
 #else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x88000000);
+    rt_system_heap_init((void*)&__bss_end, (void*)0x88000000);
 #endif
 
-	/* initialize early device */
+    /* initialize early device */
 #ifdef RT_USING_COMPONENTS_INIT
-	rt_components_board_init();
+    rt_components_board_init();
 #endif
 #ifdef RT_USING_CONSOLE
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-	/* initialize timer0 */
-	rt_hw_timer_init();
+    /* initialize timer0 */
+    rt_hw_timer_init();
 
 }