[bsp][stm32]add stm32f103-atk-warshipv3 sram driver

bsp/stm32/libraries/STM32F1xx_HAL/SConscript

@@ -16,7 +16,6 @@ STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_rcc_ex.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_cec.c
-STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c
 STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_gpio.c
 """)
 
@@ -75,6 +74,10 @@ if GetDepend(['RT_USING_MTD_NOR']):
 if GetDepend(['RT_USING_MTD_NAND']):
     src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_nand.c']
 
+if GetDepend(['BSP_USING_SRAM']):
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_fsmc.c']
+    src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_sram.c']
+
 if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
     src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash.c']
     src += ['STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_flash_ex.c']

bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/CubeMX_Config.ioc

@@ -1,27 +1,73 @@
 #MicroXplorer Configuration settings - do not modify
+FSMC.AddressSetupTime1=0
+FSMC.BusTurnAroundDuration1=0
+FSMC.DataSetupTime1=3
+FSMC.IPParameters=AddressSetupTime1,DataSetupTime1,BusTurnAroundDuration1,WriteOperation1
+FSMC.WriteOperation1=FSMC_WRITE_OPERATION_ENABLE
 File.Version=6
 KeepUserPlacement=false
 Mcu.Family=STM32F1
-Mcu.IP0=NVIC
-Mcu.IP1=RCC
-Mcu.IP2=SYS
-Mcu.IP3=TIM3
-Mcu.IP4=USART1
-Mcu.IPNb=5
+Mcu.IP0=FSMC
+Mcu.IP1=NVIC
+Mcu.IP2=RCC
+Mcu.IP3=SYS
+Mcu.IP4=TIM3
+Mcu.IP5=USART1
+Mcu.IPNb=6
 Mcu.Name=STM32F103Z(C-D-E)Tx
 Mcu.Package=LQFP144
 Mcu.Pin0=PC14-OSC32_IN
 Mcu.Pin1=PC15-OSC32_OUT
-Mcu.Pin10=VP_SYS_VS_Systick
-Mcu.Pin2=OSC_IN
-Mcu.Pin3=OSC_OUT
-Mcu.Pin4=PC6
-Mcu.Pin5=PC7
-Mcu.Pin6=PA9
-Mcu.Pin7=PA10
-Mcu.Pin8=PA13
-Mcu.Pin9=PA14
-Mcu.PinsNb=11
+Mcu.Pin10=PF12
+Mcu.Pin11=PF13
+Mcu.Pin12=PF14
+Mcu.Pin13=PF15
+Mcu.Pin14=PG0
+Mcu.Pin15=PG1
+Mcu.Pin16=PE7
+Mcu.Pin17=PE8
+Mcu.Pin18=PE9
+Mcu.Pin19=PE10
+Mcu.Pin2=PF0
+Mcu.Pin20=PE11
+Mcu.Pin21=PE12
+Mcu.Pin22=PE13
+Mcu.Pin23=PE14
+Mcu.Pin24=PE15
+Mcu.Pin25=PD8
+Mcu.Pin26=PD9
+Mcu.Pin27=PD10
+Mcu.Pin28=PD11
+Mcu.Pin29=PD12
+Mcu.Pin3=PF1
+Mcu.Pin30=PD13
+Mcu.Pin31=PD14
+Mcu.Pin32=PD15
+Mcu.Pin33=PG2
+Mcu.Pin34=PG3
+Mcu.Pin35=PG4
+Mcu.Pin36=PG5
+Mcu.Pin37=PC6
+Mcu.Pin38=PC7
+Mcu.Pin39=PA9
+Mcu.Pin4=PF2
+Mcu.Pin40=PA10
+Mcu.Pin41=PA13
+Mcu.Pin42=PA14
+Mcu.Pin43=PD0
+Mcu.Pin44=PD1
+Mcu.Pin45=PD4
+Mcu.Pin46=PD5
+Mcu.Pin47=PG10
+Mcu.Pin48=PE0
+Mcu.Pin49=PE1
+Mcu.Pin5=PF3
+Mcu.Pin50=VP_SYS_VS_Systick
+Mcu.Pin6=PF4
+Mcu.Pin7=PF5
+Mcu.Pin8=OSC_IN
+Mcu.Pin9=OSC_OUT
+Mcu.PinsNb=51
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32F103ZETx
@@ -66,6 +112,49 @@ PCC.Seq0=0
 PCC.Series=STM32F1
 PCC.Temperature=25
 PCC.Vdd=3.3
+PD0.Signal=FSMC_D2_DA2
+PD1.Signal=FSMC_D3_DA3
+PD10.Signal=FSMC_D15_DA15
+PD11.Signal=FSMC_A16_CLE
+PD12.Signal=FSMC_A17_ALE
+PD13.Signal=FSMC_A18
+PD14.Signal=FSMC_D0_DA0
+PD15.Signal=FSMC_D1_DA1
+PD4.Signal=FSMC_NOE
+PD5.Signal=FSMC_NWE
+PD8.Signal=FSMC_D13_DA13
+PD9.Signal=FSMC_D14_DA14
+PE0.Locked=true
+PE0.Signal=FSMC_NBL0
+PE1.Locked=true
+PE1.Signal=FSMC_NBL1
+PE10.Signal=FSMC_D7_DA7
+PE11.Signal=FSMC_D8_DA8
+PE12.Signal=FSMC_D9_DA9
+PE13.Signal=FSMC_D10_DA10
+PE14.Signal=FSMC_D11_DA11
+PE15.Signal=FSMC_D12_DA12
+PE7.Signal=FSMC_D4_DA4
+PE8.Signal=FSMC_D5_DA5
+PE9.Signal=FSMC_D6_DA6
+PF0.Signal=FSMC_A0
+PF1.Signal=FSMC_A1
+PF12.Signal=FSMC_A6
+PF13.Signal=FSMC_A7
+PF14.Signal=FSMC_A8
+PF15.Signal=FSMC_A9
+PF2.Signal=FSMC_A2
+PF3.Signal=FSMC_A3
+PF4.Signal=FSMC_A4
+PF5.Signal=FSMC_A5
+PG0.Signal=FSMC_A10
+PG1.Signal=FSMC_A11
+PG10.Mode=NorPsramChipSelect3_1
+PG10.Signal=FSMC_NE3
+PG2.Signal=FSMC_A12
+PG3.Signal=FSMC_A13
+PG4.Signal=FSMC_A14
+PG5.Signal=FSMC_A15
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@@ -93,7 +182,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=MDK-ARM V5
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_TIM8_Init-TIM8-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-SystemClock_Config-RCC-false-HAL-false,3-MX_USART1_UART_Init-USART1-false-HAL-true,4-MX_FSMC_Init-FSMC-false-HAL-true,5-MX_TIM3_Init-TIM3-false-HAL-true
 RCC.ADCFreqValue=36000000
 RCC.AHBFreq_Value=72000000
 RCC.APB1CLKDivider=RCC_HCLK_DIV2
@@ -120,6 +209,84 @@ RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
 RCC.TimSysFreq_Value=72000000
 RCC.USBFreq_Value=72000000
 RCC.VCOOutput2Freq_Value=8000000
+SH.FSMC_A0.0=FSMC_A0,19b-a1
+SH.FSMC_A0.ConfNb=1
+SH.FSMC_A1.0=FSMC_A1,19b-a1
+SH.FSMC_A1.ConfNb=1
+SH.FSMC_A10.0=FSMC_A10,19b-a1
+SH.FSMC_A10.ConfNb=1
+SH.FSMC_A11.0=FSMC_A11,19b-a1
+SH.FSMC_A11.ConfNb=1
+SH.FSMC_A12.0=FSMC_A12,19b-a1
+SH.FSMC_A12.ConfNb=1
+SH.FSMC_A13.0=FSMC_A13,19b-a1
+SH.FSMC_A13.ConfNb=1
+SH.FSMC_A14.0=FSMC_A14,19b-a1
+SH.FSMC_A14.ConfNb=1
+SH.FSMC_A15.0=FSMC_A15,19b-a1
+SH.FSMC_A15.ConfNb=1
+SH.FSMC_A16_CLE.0=FSMC_A16,19b-a1
+SH.FSMC_A16_CLE.ConfNb=1
+SH.FSMC_A17_ALE.0=FSMC_A17,19b-a1
+SH.FSMC_A17_ALE.ConfNb=1
+SH.FSMC_A18.0=FSMC_A18,19b-a1
+SH.FSMC_A18.ConfNb=1
+SH.FSMC_A2.0=FSMC_A2,19b-a1
+SH.FSMC_A2.ConfNb=1
+SH.FSMC_A3.0=FSMC_A3,19b-a1
+SH.FSMC_A3.ConfNb=1
+SH.FSMC_A4.0=FSMC_A4,19b-a1
+SH.FSMC_A4.ConfNb=1
+SH.FSMC_A5.0=FSMC_A5,19b-a1
+SH.FSMC_A5.ConfNb=1
+SH.FSMC_A6.0=FSMC_A6,19b-a1
+SH.FSMC_A6.ConfNb=1
+SH.FSMC_A7.0=FSMC_A7,19b-a1
+SH.FSMC_A7.ConfNb=1
+SH.FSMC_A8.0=FSMC_A8,19b-a1
+SH.FSMC_A8.ConfNb=1
+SH.FSMC_A9.0=FSMC_A9,19b-a1
+SH.FSMC_A9.ConfNb=1
+SH.FSMC_D0_DA0.0=FSMC_D0,16b-d1
+SH.FSMC_D0_DA0.ConfNb=1
+SH.FSMC_D10_DA10.0=FSMC_D10,16b-d1
+SH.FSMC_D10_DA10.ConfNb=1
+SH.FSMC_D11_DA11.0=FSMC_D11,16b-d1
+SH.FSMC_D11_DA11.ConfNb=1
+SH.FSMC_D12_DA12.0=FSMC_D12,16b-d1
+SH.FSMC_D12_DA12.ConfNb=1
+SH.FSMC_D13_DA13.0=FSMC_D13,16b-d1
+SH.FSMC_D13_DA13.ConfNb=1
+SH.FSMC_D14_DA14.0=FSMC_D14,16b-d1
+SH.FSMC_D14_DA14.ConfNb=1
+SH.FSMC_D15_DA15.0=FSMC_D15,16b-d1
+SH.FSMC_D15_DA15.ConfNb=1
+SH.FSMC_D1_DA1.0=FSMC_D1,16b-d1
+SH.FSMC_D1_DA1.ConfNb=1
+SH.FSMC_D2_DA2.0=FSMC_D2,16b-d1
+SH.FSMC_D2_DA2.ConfNb=1
+SH.FSMC_D3_DA3.0=FSMC_D3,16b-d1
+SH.FSMC_D3_DA3.ConfNb=1
+SH.FSMC_D4_DA4.0=FSMC_D4,16b-d1
+SH.FSMC_D4_DA4.ConfNb=1
+SH.FSMC_D5_DA5.0=FSMC_D5,16b-d1
+SH.FSMC_D5_DA5.ConfNb=1
+SH.FSMC_D6_DA6.0=FSMC_D6,16b-d1
+SH.FSMC_D6_DA6.ConfNb=1
+SH.FSMC_D7_DA7.0=FSMC_D7,16b-d1
+SH.FSMC_D7_DA7.ConfNb=1
+SH.FSMC_D8_DA8.0=FSMC_D8,16b-d1
+SH.FSMC_D8_DA8.ConfNb=1
+SH.FSMC_D9_DA9.0=FSMC_D9,16b-d1
+SH.FSMC_D9_DA9.ConfNb=1
+SH.FSMC_NBL0.0=FSMC_NBL0
+SH.FSMC_NBL0.ConfNb=1
+SH.FSMC_NBL1.0=FSMC_NBL1
+SH.FSMC_NBL1.ConfNb=1
+SH.FSMC_NOE.0=FSMC_NOE,Sram1
+SH.FSMC_NOE.ConfNb=1
+SH.FSMC_NWE.0=FSMC_NWE,Sram1
+SH.FSMC_NWE.ConfNb=1
 SH.S_TIM3_CH1.0=TIM3_CH1,Encoder_Interface
 SH.S_TIM3_CH1.ConfNb=1
 SH.S_TIM3_CH2.0=TIM3_CH2,Encoder_Interface

bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Inc/stm32f1xx_hal_conf.h

@@ -62,7 +62,7 @@
 /*#define HAL_SDRAM_MODULE_ENABLED   */
 /*#define HAL_SMARTCARD_MODULE_ENABLED   */
 /*#define HAL_SPI_MODULE_ENABLED   */
-/*#define HAL_SRAM_MODULE_ENABLED   */
+#define HAL_SRAM_MODULE_ENABLED
 #define HAL_TIM_MODULE_ENABLED
 #define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */

bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/main.c

@@ -46,6 +46,8 @@ TIM_HandleTypeDef htim3;
 
 UART_HandleTypeDef huart1;
 
+SRAM_HandleTypeDef hsram1;
+
 /* USER CODE BEGIN PV */
 
 /* USER CODE END PV */
@@ -54,6 +56,7 @@ UART_HandleTypeDef huart1;
 void SystemClock_Config(void);
 static void MX_GPIO_Init(void);
 static void MX_USART1_UART_Init(void);
+static void MX_FSMC_Init(void);
 static void MX_TIM3_Init(void);
 /* USER CODE BEGIN PFP */
 
@@ -94,6 +97,7 @@ int main(void)
   /* Initialize all configured peripherals */
   MX_GPIO_Init();
   MX_USART1_UART_Init();
+  MX_FSMC_Init();
   MX_TIM3_Init();
   /* USER CODE BEGIN 2 */
 
@@ -239,10 +243,71 @@ static void MX_GPIO_Init(void)
 
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOC_CLK_ENABLE();
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOG_CLK_ENABLE();
+  __HAL_RCC_GPIOE_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
 }
 
+/* FSMC initialization function */
+static void MX_FSMC_Init(void)
+{
+
+  /* USER CODE BEGIN FSMC_Init 0 */
+
+  /* USER CODE END FSMC_Init 0 */
+
+  FSMC_NORSRAM_TimingTypeDef Timing = {0};
+
+  /* USER CODE BEGIN FSMC_Init 1 */
+
+  /* USER CODE END FSMC_Init 1 */
+
+  /** Perform the SRAM1 memory initialization sequence
+  */
+  hsram1.Instance = FSMC_NORSRAM_DEVICE;
+  hsram1.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
+  /* hsram1.Init */
+  hsram1.Init.NSBank = FSMC_NORSRAM_BANK3;
+  hsram1.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
+  hsram1.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
+  hsram1.Init.MemoryDataWidth = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
+  hsram1.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
+  hsram1.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
+  hsram1.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
+  hsram1.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
+  hsram1.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
+  hsram1.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
+  hsram1.Init.ExtendedMode = FSMC_EXTENDED_MODE_DISABLE;
+  hsram1.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
+  hsram1.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
+  /* Timing */
+  Timing.AddressSetupTime = 0;
+  Timing.AddressHoldTime = 15;
+  Timing.DataSetupTime = 3;
+  Timing.BusTurnAroundDuration = 0;
+  Timing.CLKDivision = 16;
+  Timing.DataLatency = 17;
+  Timing.AccessMode = FSMC_ACCESS_MODE_A;
+  /* ExtTiming */
+
+  if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
+  {
+    Error_Handler( );
+  }
+
+  /** Disconnect NADV
+  */
+
+  __HAL_AFIO_FSMCNADV_DISCONNECTED();
+
+  /* USER CODE BEGIN FSMC_Init 2 */
+
+  /* USER CODE END FSMC_Init 2 */
+}
+
 /* USER CODE BEGIN 4 */
 
 /* USER CODE END 4 */

bsp/stm32/stm32f103-atk-warshipv3/board/CubeMX_Config/Src/stm32f1xx_hal_msp.c

@@ -214,6 +214,190 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
 
 }
 
+static uint32_t FSMC_Initialized = 0;
+
+static void HAL_FSMC_MspInit(void){
+  /* USER CODE BEGIN FSMC_MspInit 0 */
+
+  /* USER CODE END FSMC_MspInit 0 */
+  GPIO_InitTypeDef GPIO_InitStruct ={0};
+  if (FSMC_Initialized) {
+    return;
+  }
+  FSMC_Initialized = 1;
+
+  /* Peripheral clock enable */
+  __HAL_RCC_FSMC_CLK_ENABLE();
+  
+  /** FSMC GPIO Configuration  
+  PF0   ------> FSMC_A0
+  PF1   ------> FSMC_A1
+  PF2   ------> FSMC_A2
+  PF3   ------> FSMC_A3
+  PF4   ------> FSMC_A4
+  PF5   ------> FSMC_A5
+  PF12   ------> FSMC_A6
+  PF13   ------> FSMC_A7
+  PF14   ------> FSMC_A8
+  PF15   ------> FSMC_A9
+  PG0   ------> FSMC_A10
+  PG1   ------> FSMC_A11
+  PE7   ------> FSMC_D4
+  PE8   ------> FSMC_D5
+  PE9   ------> FSMC_D6
+  PE10   ------> FSMC_D7
+  PE11   ------> FSMC_D8
+  PE12   ------> FSMC_D9
+  PE13   ------> FSMC_D10
+  PE14   ------> FSMC_D11
+  PE15   ------> FSMC_D12
+  PD8   ------> FSMC_D13
+  PD9   ------> FSMC_D14
+  PD10   ------> FSMC_D15
+  PD11   ------> FSMC_A16
+  PD12   ------> FSMC_A17
+  PD13   ------> FSMC_A18
+  PD14   ------> FSMC_D0
+  PD15   ------> FSMC_D1
+  PG2   ------> FSMC_A12
+  PG3   ------> FSMC_A13
+  PG4   ------> FSMC_A14
+  PG5   ------> FSMC_A15
+  PD0   ------> FSMC_D2
+  PD1   ------> FSMC_D3
+  PD4   ------> FSMC_NOE
+  PD5   ------> FSMC_NWE
+  PG10   ------> FSMC_NE3
+  PE0   ------> FSMC_NBL0
+  PE1   ------> FSMC_NBL1
+  */
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 
+                          |GPIO_PIN_14|GPIO_PIN_15;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOF, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 
+                          |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+  GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 
+                          |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 
+                          |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN FSMC_MspInit 1 */
+
+  /* USER CODE END FSMC_MspInit 1 */
+}
+
+void HAL_SRAM_MspInit(SRAM_HandleTypeDef* hsram){
+  /* USER CODE BEGIN SRAM_MspInit 0 */
+
+  /* USER CODE END SRAM_MspInit 0 */
+  HAL_FSMC_MspInit();
+  /* USER CODE BEGIN SRAM_MspInit 1 */
+
+  /* USER CODE END SRAM_MspInit 1 */
+}
+
+static uint32_t FSMC_DeInitialized = 0;
+
+static void HAL_FSMC_MspDeInit(void){
+  /* USER CODE BEGIN FSMC_MspDeInit 0 */
+
+  /* USER CODE END FSMC_MspDeInit 0 */
+  if (FSMC_DeInitialized) {
+    return;
+  }
+  FSMC_DeInitialized = 1;
+  /* Peripheral clock enable */
+  __HAL_RCC_FSMC_CLK_DISABLE();
+  
+  /** FSMC GPIO Configuration  
+  PF0   ------> FSMC_A0
+  PF1   ------> FSMC_A1
+  PF2   ------> FSMC_A2
+  PF3   ------> FSMC_A3
+  PF4   ------> FSMC_A4
+  PF5   ------> FSMC_A5
+  PF12   ------> FSMC_A6
+  PF13   ------> FSMC_A7
+  PF14   ------> FSMC_A8
+  PF15   ------> FSMC_A9
+  PG0   ------> FSMC_A10
+  PG1   ------> FSMC_A11
+  PE7   ------> FSMC_D4
+  PE8   ------> FSMC_D5
+  PE9   ------> FSMC_D6
+  PE10   ------> FSMC_D7
+  PE11   ------> FSMC_D8
+  PE12   ------> FSMC_D9
+  PE13   ------> FSMC_D10
+  PE14   ------> FSMC_D11
+  PE15   ------> FSMC_D12
+  PD8   ------> FSMC_D13
+  PD9   ------> FSMC_D14
+  PD10   ------> FSMC_D15
+  PD11   ------> FSMC_A16
+  PD12   ------> FSMC_A17
+  PD13   ------> FSMC_A18
+  PD14   ------> FSMC_D0
+  PD15   ------> FSMC_D1
+  PG2   ------> FSMC_A12
+  PG3   ------> FSMC_A13
+  PG4   ------> FSMC_A14
+  PG5   ------> FSMC_A15
+  PD0   ------> FSMC_D2
+  PD1   ------> FSMC_D3
+  PD4   ------> FSMC_NOE
+  PD5   ------> FSMC_NWE
+  PG10   ------> FSMC_NE3
+  PE0   ------> FSMC_NBL0
+  PE1   ------> FSMC_NBL1
+  */
+  HAL_GPIO_DeInit(GPIOF, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_12|GPIO_PIN_13 
+                          |GPIO_PIN_14|GPIO_PIN_15);
+
+  HAL_GPIO_DeInit(GPIOG, GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_3 
+                          |GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_10);
+
+  HAL_GPIO_DeInit(GPIOE, GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10 
+                          |GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14 
+                          |GPIO_PIN_15|GPIO_PIN_0|GPIO_PIN_1);
+
+  HAL_GPIO_DeInit(GPIOD, GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11 
+                          |GPIO_PIN_12|GPIO_PIN_13|GPIO_PIN_14|GPIO_PIN_15 
+                          |GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5);
+
+  /* USER CODE BEGIN FSMC_MspDeInit 1 */
+
+  /* USER CODE END FSMC_MspDeInit 1 */
+}
+
+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef* hsram){
+  /* USER CODE BEGIN SRAM_MspDeInit 0 */
+
+  /* USER CODE END SRAM_MspDeInit 0 */
+  HAL_FSMC_MspDeInit();
+  /* USER CODE BEGIN SRAM_MspDeInit 1 */
+
+  /* USER CODE END SRAM_MspDeInit 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */

bsp/stm32/stm32f103-atk-warshipv3/board/Kconfig

@@ -34,6 +34,10 @@ menu "Onboard Peripheral Drivers"
         select BSP_USING_ADC1
         default n 
 
+    config BSP_USING_SRAM
+        bool "Enable SRAM"
+        default n
+
 endmenu
 
 menu "On-chip Peripheral Drivers"

bsp/stm32/stm32f103-atk-warshipv3/board/SConscript

@@ -12,8 +12,12 @@ board.c
 CubeMX_Config/Src/stm32f1xx_hal_msp.c
 ''')
 
+if GetDepend(['BSP_USING_SRAM']):
+    src += Glob('ports/drv_sram.c')
+
 path =  [cwd]
 path += [cwd + '/CubeMX_Config/Inc']
+path += [cwd + '/ports/include']
 
 startup_path_prefix = SDK_LIB
 

bsp/stm32/stm32f103-atk-warshipv3/board/ports/drv_sram.c

@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-01-05     linyiyang    first version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef BSP_USING_SRAM
+#include <sram_port.h>
+
+#define DRV_DEBUG
+#define LOG_TAG             "drv.sram"
+#include <drv_log.h>
+
+static SRAM_HandleTypeDef hsram1;
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+static struct rt_memheap system_heap;
+#endif
+
+static int sram_init(void)
+{
+    int result = RT_EOK;
+
+    FSMC_NORSRAM_TimingTypeDef Timing = {0};
+
+    /** Perform the SRAM1 memory initialization sequence
+    */
+    hsram1.Instance                 = FSMC_NORSRAM_DEVICE;
+    hsram1.Extended                 = FSMC_NORSRAM_EXTENDED_DEVICE;
+
+    /* hsram1.Init */
+    hsram1.Init.NSBank              = FSMC_NORSRAM_BANK3;
+    hsram1.Init.DataAddressMux      = FSMC_DATA_ADDRESS_MUX_DISABLE;
+    hsram1.Init.MemoryType          = FSMC_MEMORY_TYPE_SRAM;
+#if SRAM_DATA_WIDTH == 8
+    hsram1.Init.MemoryDataWidth     = FSMC_NORSRAM_MEM_BUS_WIDTH_8;
+#elif SRAM_DATA_WIDTH == 16
+    hsram1.Init.MemoryDataWidth     = FSMC_NORSRAM_MEM_BUS_WIDTH_16;
+#else
+    hsram1.Init.MemoryDataWidth     = FSMC_NORSRAM_MEM_BUS_WIDTH_32;
+#endif
+    hsram1.Init.BurstAccessMode     = FSMC_BURST_ACCESS_MODE_DISABLE;
+    hsram1.Init.WaitSignalPolarity  = FSMC_WAIT_SIGNAL_POLARITY_LOW;
+    hsram1.Init.WrapMode            = FSMC_WRAP_MODE_DISABLE;
+    hsram1.Init.WaitSignalActive    = FSMC_WAIT_TIMING_BEFORE_WS;
+    hsram1.Init.WriteOperation      = FSMC_WRITE_OPERATION_ENABLE;
+    hsram1.Init.WaitSignal          = FSMC_WAIT_SIGNAL_DISABLE;
+    hsram1.Init.ExtendedMode        = FSMC_EXTENDED_MODE_DISABLE;
+    hsram1.Init.AsynchronousWait    = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
+    hsram1.Init.WriteBurst          = FSMC_WRITE_BURST_DISABLE;
+
+    /* Timing */
+    Timing.AddressSetupTime         = 0;
+    Timing.AddressHoldTime          = 15;
+    Timing.DataSetupTime            = 3;
+    Timing.BusTurnAroundDuration    = 0;
+    Timing.CLKDivision              = 16;
+    Timing.DataLatency              = 17;
+    Timing.AccessMode               = FSMC_ACCESS_MODE_A;
+    /* ExtTiming */
+
+    /* Initialize the SRAM controller */
+    if (HAL_SRAM_Init(&hsram1, &Timing, NULL) != HAL_OK)
+    {
+        LOG_E("SRAM init failed!");
+        result = -RT_ERROR;
+    }
+    else
+    {
+        LOG_D("sram init success, mapped at 0x%X, size is %d bytes, data width is %d", SRAM_BANK_ADDR, SRAM_SIZE, SRAM_DATA_WIDTH);
+#ifdef RT_USING_MEMHEAP_AS_HEAP
+        /* If RT_USING_MEMHEAP_AS_HEAP is enabled, SRAM is initialized to the heap */
+        rt_memheap_init(&system_heap, "sram", (void *)SRAM_BANK_ADDR, SRAM_SIZE);
+#endif
+    }
+
+    /** Disconnect NADV
+    */
+
+    __HAL_AFIO_FSMCNADV_DISCONNECTED();
+
+    return result;
+}
+INIT_BOARD_EXPORT(sram_init);
+
+#ifdef DRV_DEBUG
+#ifdef FINSH_USING_MSH
+int sram_test(void)
+{
+    int i = 0;
+    uint32_t start_time = 0, time_cast = 0;
+#if SRAM_DATA_WIDTH == 8
+    char data_width = 1;
+    uint8_t data = 0;
+    uint8_t *ptr = (uint8_t *)SRAM_BANK_ADDR;
+#elif SRAM_DATA_WIDTH == 16
+    char data_width = 2;
+    uint16_t data = 0;
+    uint16_t *ptr = (uint16_t *)SRAM_BANK_ADDR;
+#else
+    char data_width = 4;
+    uint32_t data = 0;
+    uint32_t *ptr = (uint32_t *)SRAM_BANK_ADDR;
+#endif
+
+    /* write data */
+    LOG_D("Writing the %ld bytes data, waiting....", SRAM_SIZE);
+    start_time = rt_tick_get();
+    for (i = 0; i < SRAM_SIZE / data_width; i++)
+    {
+#if SRAM_DATA_WIDTH == 8
+        ((__IO uint8_t *)ptr)[i] = (uint8_t)0x55;
+#elif SRAM_DATA_WIDTH == 16
+        ((__IO uint16_t *)ptr)[i] = (uint16_t)0x5555;
+#else
+        ((__IO uint32_t *)ptr)[i] = (uint32_t)0x55555555;
+#endif
+    }
+    time_cast = rt_tick_get() - start_time;
+    LOG_D("Write data success, total time: %d.%03dS.", time_cast / RT_TICK_PER_SECOND,
+          time_cast % RT_TICK_PER_SECOND / ((RT_TICK_PER_SECOND * 1 + 999) / 1000));
+
+    /* read data */
+    LOG_D("start Reading and verifying data, waiting....");
+    for (i = 0; i < SRAM_SIZE / data_width; i++)
+    {
+#if SRAM_DATA_WIDTH == 8
+        data = ((__IO uint8_t *)ptr)[i];
+        if (data != 0x55)
+        {
+            LOG_E("SRAM test failed!");
+            break;
+        }
+#elif SRAM_DATA_WIDTH == 16
+        data = ((__IO uint16_t *)ptr)[i];
+        if (data != 0x5555)
+        {
+            LOG_E("SRAM test failed!");
+            break;
+        }
+#else
+        data = ((__IO uint32_t *)ptr)[i];
+        if (data != 0x55555555)
+        {
+            LOG_E("SRAM test failed!");
+            break;
+        }
+#endif
+    }
+
+    if (i >= SRAM_SIZE / data_width)
+    {
+        LOG_D("SRAM test success!");
+    }
+
+    return RT_EOK;
+}
+MSH_CMD_EXPORT(sram_test, sram test);
+#endif /* FINSH_USING_MSH */
+#endif /* DRV_DEBUG */
+#endif /* BSP_USING_SRAM */

bsp/stm32/stm32f103-atk-warshipv3/board/ports/include/sram_port.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-01-05     linyiyang    first version
+ */
+
+#ifndef __SDRAM_PORT_H__
+#define __SDRAM_PORT_H__
+
+/* parameters for sdram peripheral */
+/* stm32f1 Bank1:0x68000000 */
+#define SRAM_BANK_ADDR                  ((uint32_t)0x68000000)
+/* data width: 8, 16, 32 */
+#define SRAM_DATA_WIDTH                 16
+/* sram size */
+#define SRAM_SIZE                       ((uint32_t)0x100000)
+
+#endif