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@@ -8,9 +8,14 @@
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* 2013-07-05 Bernard the first version
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* 2018-11-22 Jesven in the interrupt context, use rt_scheduler_do_irq_switch checks
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* and switches to a new thread
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+ * 2024-01-16 huanghe restructure this code section following the aarch64 architectural style
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*/
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#include "rtconfig.h"
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+
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+#define ARM_CPU_STACK_SIZE_OFFSET 12
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+#define ARM_CPU_STACK_SIZE (1<<ARM_CPU_STACK_SIZE_OFFSET)
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+
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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@@ -22,17 +27,73 @@
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.equ I_Bit, 0x80 /* when I bit is set, IRQ is disabled */
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.equ F_Bit, 0x40 /* when F bit is set, FIQ is disabled */
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-#ifdef RT_USING_SMART
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-.data
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-.align 14
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-init_mtbl:
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- .space 16*1024
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-#endif
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+/*Load the physical address of a symbol into a register.
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+ Through pv_off calculates the offset of the physical address */
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+.macro get_phy, reg, symbol, _pvoff
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+ ldr \reg, =\symbol
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+ add \reg, \_pvoff
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+.endm
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+/*Calculate the offset between the physical address and the virtual address of the "_reset".*/
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+.macro get_pvoff, tmp, out
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+ ldr \tmp, =_reset
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+ adr \out, _reset
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+ sub \out, \out, \tmp
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+.endm
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+
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+pv_off .req r11 /* Used to store the offset between physical address and the virtual address */
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+cpu_id .req r10 /* Used to store the cpu id */
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-.text
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/* reset entry */
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-.globl _reset
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+ .globl _reset
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_reset:
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+ /* Calculate the offset between the physical address and the virtual address */
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+ get_pvoff r0, pv_off
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+
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+ /* exit hyp mode */
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+ bl init_cpu_mode
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+ /* clear bss section */
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+ bl init_kernel_bss
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+ /* Initializes the assembly environment stack */
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+ bl init_cpu_stack_early
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+
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+ /* init mmu */
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+ b init_mmu_early
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+
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+init_cpu_stack_early:
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+
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+ cps #Mode_SVC
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+
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+ get_phy r0, svc_stack_top, pv_off
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+ mov sp, r0
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+
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+#ifdef RT_USING_FPU
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+ mov r4, #0xfffffff
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+ mcr p15, 0, r4, c1, c0, 2
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+#endif
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+
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+ mov pc, lr
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+
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+init_kernel_bss:
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+
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+ /* enable I cache + branch prediction */
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+ mrc p15, 0, r0, c1, c0, 0
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+ orr r0, r0, #(1<<12)
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+ orr r0, r0, #(1<<11)
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+ mcr p15, 0, r0, c1, c0, 0
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+
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+ mov r0,#0 /* get a zero */
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+ get_phy r1, __bss_start, pv_off
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+ get_phy r2, __bss_end, pv_off
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+
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+bss_loop:
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+ cmp r1,r2 /* check if data to clear */
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+ strlo r0,[r1],#4 /* clear 4 bytes */
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+ blo bss_loop /* loop until done */
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+
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+ mov pc, lr
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+
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+init_cpu_mode:
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+
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#ifdef ARCH_ARMV8
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/* Check for HYP mode */
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mrs r0, cpsr_all
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@@ -40,20 +101,26 @@ _reset:
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mov r8, #0x1A
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cmp r0, r8
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beq overHyped
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- b continue
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+ b continue_exit
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overHyped: /* Get out of HYP mode */
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- adr r1, continue
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+ mov r9, lr
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+ /* HYP mode has a dedicated register, called ELR_hyp,
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+ to store the exception return address.
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+ The lr register needs to be temporarily saved,
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+ otherwise "mov pc lr" cannot be used after switching modes. */
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+ adr r1, continue_exit
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msr ELR_hyp, r1
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mrs r1, cpsr_all
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- and r1, r1, #0x1f /* CPSR_MODE_MASK */
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- orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */
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+ and r1, r1, #0xFFFFFFE0 /* CPSR_MODE_MASK */
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+ orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */
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msr SPSR_hyp, r1
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eret
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-continue:
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+continue_exit:
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+ mov lr ,r9
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+
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#endif
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-
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#ifdef SOC_BCM283x
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/* Suspend the other cpu cores */
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mrc p15, 0, r0, c0, c0, 5
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@@ -69,23 +136,30 @@ continue:
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mov r8, #0x1A
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cmp r0, r8
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beq overHyped
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- b continue
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+ b continue_exit
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overHyped: /* Get out of HYP mode */
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- adr r1, continue
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+ mov r9, lr
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+ /* HYP mode has a dedicated register, called ELR_hyp,
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+ to store the exception return address.
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+ The lr register needs to be temporarily saved,
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+ otherwise "mov pc lr" cannot be used after switching modes. */
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+ adr r1, continue_exit
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msr ELR_hyp, r1
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mrs r1, cpsr_all
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- and r1, r1, #0x1f /* CPSR_MODE_MASK */
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- orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */
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+ and r1, r1, #0xFFFFFFE0 /* CPSR_MODE_MASK */
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+ orr r1, r1, #0x13 /* CPSR_MODE_SUPERVISOR */
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msr SPSR_hyp, r1
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eret
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-continue:
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+continue_exit:
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+ mov lr ,r9
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/* set the cpu to SVC32 mode and disable interrupt */
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mrs r0, cpsr
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bic r0, r0, #0x1f
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orr r0, r0, #0x13
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msr cpsr_c, r0
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+
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#endif
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/* invalid tlb before enable mmu */
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@@ -94,6 +168,7 @@ continue:
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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+
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0
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mcr p15, 0, r0, c7, c5, 0 /* iciallu */
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@@ -101,78 +176,31 @@ continue:
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dsb
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isb
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-#ifdef RT_USING_SMART
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- /* load r5 with PV_OFFSET */
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- ldr r7, =_reset
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- adr r5, _reset
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- sub r5, r5, r7
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-
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- mov r7, #0x100000
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- sub r7, #1
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- mvn r8, r7
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-
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-
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- ldr r9, =KERNEL_VADDR_START
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-
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- ldr r6, =__bss_end
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- add r6, r7
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- and r6, r8 /* r6 end vaddr align up to 1M */
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- sub r6, r9 /* r6 is size */
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-
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- ldr sp, =svc_stack_n_limit
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- add sp, r5 /* use paddr */
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-
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- ldr r0, =init_mtbl
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- add r0, r5
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- mov r1, r6
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- mov r2, r5
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- bl init_mm_setup
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-
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- ldr lr, =after_enable_mmu
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- ldr r0, =init_mtbl
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- add r0, r5
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- b enable_mmu
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-
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-after_enable_mmu:
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-#endif
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-#ifndef SOC_BCM283x
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- /* set the cpu to SVC32 mode and disable interrupt */
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- cps #Mode_SVC
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-#endif
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+ mov pc, lr
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-#ifdef RT_USING_FPU
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- mov r4, #0xfffffff
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- mcr p15, 0, r4, c1, c0, 2
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-#endif
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+init_mmu_early:
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+ get_phy r0, init_mtbl, pv_off
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+ mov r1, pv_off
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+ bl rt_hw_mem_setup_early
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- /* disable the data alignment check */
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- mrc p15, 0, r1, c1, c0, 0
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- bic r1, #(1<<1) /* Disable Alignment fault checking */
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-#ifndef RT_USING_SMART
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- bic r1, #(1<<0) /* Disable MMU */
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- bic r1, #(1<<2) /* Disable data cache */
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- bic r1, #(1<<11) /* Disable program flow prediction */
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- bic r1, #(1<<12) /* Disable instruction cache */
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- bic r1, #(3<<19) /* bit[20:19] must be zero */
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-#endif /* RT_USING_SMART */
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- mcr p15, 0, r1, c1, c0, 0
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-
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-#ifndef RT_USING_SMART
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-#ifdef RT_USING_SMP
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- /* Use spin-table to start secondary cores */
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- @ get cpu id, and subtract the offset from the stacks base address
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+ /* get cpu id */
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bl rt_hw_cpu_id
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- mov r5, r0
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+ mov cpu_id ,r0
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+ /* enable_mmu_early is changed to master_core_startup */
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+ ldr lr, =master_core_startup
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+
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+ cmp cpu_id, #0
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+ beq enable_mmu_early
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- cmp r5, #0 @ cpu id == 0
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- beq normal_setup
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- @ cpu id > 0, stop or wait
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+#ifdef RT_USING_SMP
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#ifdef RT_SMP_AUTO_BOOT
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+ /* if cpu id > 0, stop or wait */
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ldr r0, =secondary_cpu_entry
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mov r1, #0
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str r1, [r0] /* clean secondary_cpu_entry */
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-#endif /* RT_SMP_AUTO_BOOT */
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+#endif
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+#endif
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secondary_loop:
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@ cpu core 1 goes into sleep until core 0 wakeup it
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@@ -184,115 +212,46 @@ secondary_loop:
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blxne r0 /* if(secondary_cpu_entry) secondary_cpu_entry(); */
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#endif /* RT_SMP_AUTO_BOOT */
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b secondary_loop
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+
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+enable_mmu_early:
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+ /* init TTBR0 */
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+ get_phy r0, init_mtbl, pv_off
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+ mcr p15, #0, r0, c2, c0, #0
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+ dmb
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+
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+ ldr r0,=#0x55555555
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+ mcr p15, #0, r0, c3, c0, #0
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+
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+ /* disable ttbr1 */
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+ mov r0, #(1 << 5) /* PD1=1 */
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+ mcr p15, 0, r0, c2, c0, 2 /* ttbcr */
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-normal_setup:
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-#endif /* RT_USING_SMP */
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-#endif /* RT_USING_SMART */
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-
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- /* enable I cache + branch prediction */
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- mrc p15, 0, r0, c1, c0, 0
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- orr r0, r0, #(1<<12)
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- orr r0, r0, #(1<<11)
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- mcr p15, 0, r0, c1, c0, 0
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-
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- /* setup stack */
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- bl stack_setup
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-
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- /* clear .bss */
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- mov r0,#0 /* get a zero */
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- ldr r1,=__bss_start /* bss start */
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- ldr r2,=__bss_end /* bss end */
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-
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-bss_loop:
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- cmp r1,r2 /* check if data to clear */
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- strlo r0,[r1],#4 /* clear 4 bytes */
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- blo bss_loop /* loop until done */
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-
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- mov r0, r5
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- bl rt_kmem_pvoff_set
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-
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-#ifdef RT_USING_SMP
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- mrc p15, 0, r1, c1, c0, 1
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- mov r0, #(1<<6)
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- orr r1, r0
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- mcr p15, 0, r1, c1, c0, 1 /* enable smp */
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-#endif
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-
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- /**
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- * void rt_hw_init_mmu_table(struct mem_desc *mdesc, rt_uint32_t size)
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- * initialize the mmu table and enable mmu
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- */
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- ldr r0, =platform_mem_desc
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- ldr r1, =platform_mem_desc_size
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- ldr r1, [r1]
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- bl rt_hw_init_mmu_table
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-
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-#ifdef RT_USING_SMART
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- ldr r0, =MMUTable /* vaddr */
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- add r0, r5 /* to paddr */
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- bl rt_hw_mmu_switch
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-#else
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- bl rt_hw_mmu_init
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-#endif
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-
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- /* start RT-Thread Kernel */
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- ldr pc, _rtthread_startup
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-_rtthread_startup:
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- .word rtthread_startup
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-
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-.weak rt_asm_cpu_id
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-rt_asm_cpu_id:
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- mrc p15, 0, r0, c0, c0, 5
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- and r0, r0, #0xf
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- mov pc, lr
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-
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-stack_setup:
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-
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-#ifdef RT_USING_SMP
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- /* cpu id */
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- mov r10, lr
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- bl rt_asm_cpu_id
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- mov lr, r10
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- add r0, r0, #1
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-
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-#else
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- mov r0, #1
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-#endif
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-
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+
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+ /* init stack for cpu mod */
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cps #Mode_UND
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- ldr r1, =und_stack_n
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- add sp, r1, r0, asl #12
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+ ldr r1,=und_stack_top
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+ sub sp, r1, cpu_id, asl #ARM_CPU_STACK_SIZE_OFFSET
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+
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cps #Mode_IRQ
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- ldr r1, =irq_stack_n
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- add sp, r1, r0, asl #12
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+ ldr r1, =irq_stack_top
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+ sub sp, r1, cpu_id, asl #ARM_CPU_STACK_SIZE_OFFSET
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+
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cps #Mode_FIQ
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- ldr r1, =irq_stack_n
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- add sp, r1, r0, asl #12
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+ ldr r1, =irq_stack_top
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+ sub sp, r1, cpu_id, asl #ARM_CPU_STACK_SIZE_OFFSET
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- cps #Mode_ABT
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- ldr r1, =abt_stack_n
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- add sp, r1, r0, asl #12
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- cps #Mode_SVC
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- ldr r1, =svc_stack_n
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- add sp, r1, r0, asl #12
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-
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- bx lr
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+ cps #Mode_ABT
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+ ldr r1, =abt_stack_top
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+ sub sp, r1, cpu_id, asl #ARM_CPU_STACK_SIZE_OFFSET
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-#ifdef RT_USING_SMART
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-.align 2
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-.global enable_mmu
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-enable_mmu:
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- orr r0, #0x18
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- mcr p15, 0, r0, c2, c0, 0 /* ttbr0 */
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- mov r0, #(1 << 5) /* PD1=1 */
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- mcr p15, 0, r0, c2, c0, 2 /* ttbcr */
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+ cps #Mode_SVC
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+ ldr r1, =svc_stack_top
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+ sub sp, r1, cpu_id, asl #ARM_CPU_STACK_SIZE_OFFSET
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- mov r0, #1
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- mcr p15, 0, r0, c3, c0, 0 /* dacr */
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/* invalid tlb before enable mmu */
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mov r0, #0
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@@ -306,28 +265,14 @@ enable_mmu:
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mcr p15, 0, r0, c1, c0, 0
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dsb
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isb
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- mov pc, lr
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-.global rt_hw_set_process_id
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-rt_hw_set_process_id:
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- LSL r0, r0, #8
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- MCR p15, 0, r0, c13, c0, 1
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mov pc, lr
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-#endif
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-.global rt_hw_mmu_switch
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-rt_hw_mmu_switch:
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- orr r0, #0x18
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- mcr p15, 0, r0, c2, c0, 0 // ttbr0
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-
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- //invalid tlb
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- mov r0, #0
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- mcr p15, 0, r0, c8, c7, 0
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- mcr p15, 0, r0, c7, c5, 0 //iciallu
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- mcr p15, 0, r0, c7, c5, 6 //bpiall
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+master_core_startup :
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+ mov r0 ,pv_off
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+ bl rt_kmem_pvoff_set
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- dsb
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- isb
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+ ldr lr, =rtthread_startup
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mov pc, lr
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.global rt_hw_mmu_tbl_get
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@@ -336,53 +281,29 @@ rt_hw_mmu_tbl_get:
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bic r0, #0x18
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mov pc, lr
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-_halt:
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- wfe
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- b _halt
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+.weak rt_hw_cpu_id
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+rt_hw_cpu_id:
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+ mrc p15, 0, r0, c0, c0, 5
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+ and r0, r0, #0xf
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+ mov pc, lr
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#ifdef RT_USING_SMP
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-
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.global rt_secondary_cpu_entry
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rt_secondary_cpu_entry:
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-#ifdef RT_USING_SMART
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- ldr r0, =_reset
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- adr r5, _reset
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- sub r5, r5, r0
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-
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- ldr lr, =after_enable_mmu_n
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- ldr r0, =init_mtbl
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- add r0, r5
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- b enable_mmu
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-
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-after_enable_mmu_n:
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- ldr r0, =MMUTable
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- add r0, r5
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- bl rt_hw_mmu_switch
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-#endif
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-
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-#ifdef RT_USING_FPU
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- mov r4, #0xfffffff
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- mcr p15, 0, r4, c1, c0, 2
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-#endif
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-
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- mrc p15, 0, r1, c1, c0, 1
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- mov r0, #(1<<6)
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- orr r1, r0
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- mcr p15, 0, r1, c1, c0, 1 /* enable smp */
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+ ldr r0, =_reset
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+ adr pv_off, _reset
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+ sub pv_off, pv_off, r0
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- mrc p15, 0, r0, c1, c0, 0
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- bic r0, #(1<<13)
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- mcr p15, 0, r0, c1, c0, 0
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+ bl init_cpu_stack_early
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- bl stack_setup
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+ /* init mmu */
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+ bl rt_hw_cpu_id
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+ mov cpu_id ,r0
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- /* initialize the mmu table and enable mmu */
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-#ifndef RT_USING_SMART
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- bl rt_hw_mmu_init
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+ ldr lr ,= rt_hw_secondary_cpu_bsp_start
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+ b enable_mmu_early
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#endif
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- b rt_hw_secondary_cpu_bsp_start
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-#endif
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/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */
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.section .text.isr, "ax"
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@@ -698,9 +619,6 @@ rt_hw_clz:
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clz r0, r0
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bx lr
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-#ifndef RT_CPUS_NR
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-#define RT_CPUS_NR 1
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-#endif
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#include "asm-generic.h"
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@@ -711,17 +629,66 @@ START_POINT(_thread_start)
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b . /* never here */
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START_POINT_END(_thread_start)
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+.data
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+.align 14
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+init_mtbl:
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+ .space (4*4096) /* The L1 translation table therefore contains 4096 32-bit (word-sized) entries. */
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+
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+.global rt_hw_mmu_switch
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+rt_hw_mmu_switch:
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+ orr r0, #0x18
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+ mcr p15, 0, r0, c2, c0, 0 // ttbr0
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+ //invalid tlb
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+ mov r0, #0
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+ mcr p15, 0, r0, c8, c7, 0
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+ mcr p15, 0, r0, c7, c5, 0 //iciallu
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+ mcr p15, 0, r0, c7, c5, 6 //bpiall
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+
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+ dsb
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+ isb
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+ mov pc, lr
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+
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+
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+.global rt_hw_set_process_id
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+rt_hw_set_process_id:
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+ LSL r0, r0, #8
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+ MCR p15, 0, r0, c13, c0, 1
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+ mov pc, lr
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+
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+
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.bss
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.align 3 /* align to 2~3=8 */
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+
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+.cpus_stack:
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svc_stack_n:
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- .space (RT_CPUS_NR << 12)
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-svc_stack_n_limit:
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+#if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
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+ .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
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+#endif
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+ .space (ARM_CPU_STACK_SIZE)
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+svc_stack_top:
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irq_stack_n:
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- .space (RT_CPUS_NR << 12)
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+#if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
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+ .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
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+#endif
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+ .space (ARM_CPU_STACK_SIZE)
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+irq_stack_top:
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+
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und_stack_n:
|
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- .space (RT_CPUS_NR << 12)
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+#if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
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+ .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
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+#endif
|
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+ .space (ARM_CPU_STACK_SIZE)
|
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|
+und_stack_top:
|
|
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|
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abt_stack_n:
|
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|
- .space (RT_CPUS_NR << 12)
|
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+#if defined(RT_USING_SMP) && (RT_CPUS_NR > 1)
|
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+ .space ((RT_CPUS_NR - 1) * ARM_CPU_STACK_SIZE)
|
|
|
+#endif
|
|
|
+ .space (ARM_CPU_STACK_SIZE)
|
|
|
+abt_stack_top:
|
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+
|
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+
|
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+
|
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+
|