Microchip SAM MCU新增ethernet支持和驱动更新 (#5821)

* Microchip SAM MCU BSP update and add ethernet driver

1. Update Microchip SAM MCU BSP, add I2C, GMAC, ADC driver support. 2. Add ethernet driver support of SAM MCU for RT-Thread.

* Add GMAC and I2C driver support

1. Update MCU BSP to support I2C/ADC/GMAC peripherals. 2. Add I2C and ethernet driver and LWIP support. 3. Update serial driver.

* Add I2C driver and move some files to the common folder

1. Add I2C driver. 2. Move the same drivers and demo code to same folder to reduce duplicated code.

bsp/microchip/README.md

@@ -183,6 +183,9 @@ About RT-Thread env tools, click [Here](https://github.com/RT-Thread/rt-thread/b
 
 ![](doc/3-1-8-atmel-start-Studio7-start-debugging3.png)
 
+		* Debugging message output.
+
+![](doc/3-1-9-atmel-start-rt-thread-run.png)
 
 # 4. Reconfigure MCU BSP
 

bsp/microchip/common/applications/SConscript

@@ -0,0 +1,23 @@
+import rtconfig
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+if GetDepend('SAM_CAN_EXAMPLE') == False:
+    SrcRemove(src, ['can_demo.c'])
+
+if GetDepend('SAM_I2C_EXAMPLE') == False:
+    SrcRemove(src, ['i2c_demo.c'])
+
+if GetDepend('SAM_ADC_EXAMPLE') == False:
+    SrcRemove(src, ['adc_demo.c'])
+
+if GetDepend('SAM_LWIP_EXAMPLE') == False:
+    SrcRemove(src, ['lwip_demo.c'])
+ 
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/microchip/common/applications/adc_demo.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#include <atmel_start.h>
+
+#include "adc_demo.h"
+
+#ifdef SAM_ADC_EXAMPLE
+
+#if defined(SOC_SAMC21)
+#define ADC_RESOLUTION_12BIT    ADC_CTRLC_RESSEL_12BIT_Val
+#define ADC_RESOLUTION_16BIT    ADC_CTRLC_RESSEL_16BIT_Val
+#elif defined(SOC_SAME54)
+#define ADC_RESOLUTION_12BIT    ADC_CTRLB_RESSEL_12BIT_Val
+#define ADC_RESOLUTION_16BIT    ADC_CTRLB_RESSEL_16BIT_Val
+#elif defined(SOC_SAME70)
+#define ADC_RESOLUTION_12BIT    AFEC_EMR_RES_NO_AVERAGE_Val
+#define ADC_RESOLUTION_16BIT    AFEC_EMR_RES_OSR256_Val
+#else
+#error "ADC undefined SOC Platform"
+#endif
+
+/**
+ * @brief    Call this function will run ADC test code.
+ *
+ * @note     Test code will try to read ADC conversion result.
+ *
+ * @param    None.
+ *
+ * @return   RT_OK or -RT_ERROR.
+ */
+
+rt_err_t adc_demo_run(void)
+{
+    rt_uint8_t buffer[2];
+
+    /* enable ADC driver module */
+    adc_sync_enable_channel(&ADC_0, 0);
+
+    adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+#ifndef RT_USING_FINSH
+    rt_kprintf("buf[0]=0x%02X buf[1]=0x%02X\r\n", buffer[0], buffer[1]);
+#endif
+
+    /* ADC 16-bit resolution */
+    adc_sync_disable_channel(&ADC_0, 0);
+    adc_sync_set_resolution(&ADC_0,  ADC_RESOLUTION_16BIT);
+    adc_sync_enable_channel(&ADC_0,  0);
+#ifndef RT_USING_FINSH
+    rt_kprintf("buf[0]=0x%02X buf[1]=0x%02X\r\n", buffer[0], buffer[1]);
+#endif
+
+    /* ADC 12-bit resolution */
+    adc_sync_disable_channel(&ADC_0, 0);
+    adc_sync_set_resolution(&ADC_0,  ADC_RESOLUTION_12BIT);
+    adc_sync_enable_channel(&ADC_0,  0);
+#ifndef RT_USING_FINSH
+    rt_kprintf("buf[0]=0x%02X buf[1]=0x%02X\r\n", buffer[0], buffer[1]);
+#endif
+
+    return RT_EOK;
+}
+#endif
+
+/*@}*/

bsp/microchip/same54/board/serial.h → bsp/microchip/common/applications/adc_demo.h

@@ -5,11 +5,11 @@
  *
  * Change Logs:
  * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ * 2022-04-11  Kevin.Liu kevin.liu.mchp@gmail.com First Release
  */
 
-#ifndef __BOARD_SERIAL_H_
-#define __BOARD_SERIAL_H_
+#ifndef __APPLICATION_ADC_H_
+#define __APPLICATION_ADC_H_
 
 #include <rtthread.h>
 
@@ -17,6 +17,6 @@
  * @brief External function definitions
  *
  */
-int rt_hw_uart_init(void);
+rt_err_t adc_demo_run(void);
 
-#endif // __BOARD_SERIAL_H_
+#endif // __APPLICATION_I2C_H_

bsp/microchip/same54/applications/can_demo.c → bsp/microchip/common/applications/can_demo.c

@@ -5,16 +5,11 @@
  *
  * Change Logs:
  * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ * 2022-04-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
  */
 
 #include <rtthread.h>
 
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-#include <shell.h>
-#endif
-
 #include "atmel_start.h"
 #include "driver_init.h"
 #include "utils.h"
@@ -23,6 +18,14 @@
 
 #ifdef SAM_CAN_EXAMPLE
 
+#if defined(SOC_SAMC21) || defined(SOC_SAME54)
+#define CAN_HARDWARE            (void *)CAN1
+#elif defined(SOC_SAME70)
+#define CAN_HARDWARE            (void *)MCAN1
+#else
+#error "CAN undefined SOC Platform"
+#endif
+
 static volatile enum can_async_interrupt_type can_errors;
 static rt_sem_t   can_txdone;
 static rt_sem_t   can_rxdone;
@@ -251,7 +254,7 @@ static void can_thread_entry(void* parameter)
         /* CAN task got CAN error message, handler CAN Error Status */
         if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
         {
-            can_async_init(&CAN_0, CAN1);
+            can_async_init(&CAN_0, CAN_HARDWARE);
         }
     }
 }

bsp/microchip/common/applications/i2c_demo.c

@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+
+#include <atmel_start.h>
+
+#include "i2c_demo.h"
+
+#ifdef SAM_I2C_EXAMPLE
+
+#define I2C_AT24MAC_PGMAXSZ  (16+1)
+#define CONF_AT24MAC_ADDRESS  0x57
+
+/**
+ * @brief    Call this function will run I2C test code.
+ *
+ * @note     Test code will try to read/write external EEPROM.
+ *
+ * @param    None.
+ *
+ * @return   RT_OK or -RT_ERROR.
+ */
+
+rt_err_t i2c_demo_run(void)
+{
+    rt_uint8_t addr = 0x20;
+    rt_int32_t len;
+    rt_uint8_t i2ctx[I2C_AT24MAC_PGMAXSZ];
+    rt_uint8_t i2crx[I2C_AT24MAC_PGMAXSZ];
+
+    for (len = 1; len < I2C_AT24MAC_PGMAXSZ; len++)
+    {
+        i2ctx[len] = (rt_uint8_t)(len + 0x20);
+    }
+
+    /* enable I2C master and set slave address before use I2C driver module */
+    i2c_m_sync_enable(&I2C_0);
+    i2c_m_sync_set_slaveaddr(&I2C_0, CONF_AT24MAC_ADDRESS, I2C_M_SEVEN);
+
+    /* write 16bytes data to address 0x20 - I2C slave address + random address + write data[0]...[n] */
+    i2ctx[0] = addr; /* Refer to AT24MAC data sheet, first byte is page address. */
+    io_write(&(I2C_0.io), i2ctx, I2C_AT24MAC_PGMAXSZ);
+
+    /* Refer to data sheet, for random read, should send read address first. */
+    io_write(&(I2C_0.io), &addr, 1);
+
+    /* Then start I2C read after send I2C slave address first */
+    io_read(&(I2C_0.io), &i2crx[1], 16);
+#ifndef RT_USING_FINSH
+    rt_kprintf("i2crx[0]=0x%02X i2crx[15]=0x%02X\r\n", i2crx[0], i2crx[15]);
+#endif
+
+    return RT_EOK;
+}
+#endif
+
+/*@}*/

bsp/microchip/common/applications/i2c_demo.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-11  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __APPLICATION_I2C_H_
+#define __APPLICATION_I2C_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+rt_err_t i2c_demo_run(void);
+
+#endif // __APPLICATION_I2C_H_

bsp/microchip/common/applications/lwip_demo.c

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-01-24     ChungHsuan   improve code comments
+ */
+
+#include <rtthread.h>
+#include <string.h>
+
+#if !defined(SAL_USING_POSIX)
+#error "Please enable SAL_USING_POSIX!"
+#else
+#include <sys/time.h>
+#include <sys/select.h>
+#endif
+#include <sys/socket.h> /* socket.h header file is needed when using BSD socket */ /* 使用BSD socket，需要包含socket.h头文件 */
+#include "netdb.h"
+
+#define DEBUG_TCP_CLIENT
+
+#define DBG_TAG               "TCP"
+#ifdef DEBUG_TCP_CLIENT
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO /* DBG_ERROR */
+#endif
+#include <rtdbg.h>
+
+#include "lwip_demo.h"
+
+#ifdef SAM_LWIP_EXAMPLE
+
+#define BUFSZ   1024
+
+static int started = 0;
+static int is_running = 0;
+static char url[256] = "www.baidu.com";
+static int port = 8080;
+static const char send_data[] = "This is TCP Client from RT-Thread."; /* The message be sent */ /* 发送用到的数据 */
+
+/**
+* @brief  This function is for creating a tcp client on RT-Thread
+*/
+static void tcpclient(void *arg)
+{
+    int ret;
+    char *recv_data;
+    int bytes_received;
+    int sock = -1;
+    struct hostent *host = RT_NULL;
+    struct sockaddr_in server_addr;
+
+    struct timeval timeout;
+    fd_set readset;
+    /* Get host address by parameter url(Domain name resolution if input domain) */
+    /* 通过函数入口参数url获得host地址（如果是域名，会做域名解析） */
+    host = gethostbyname(url);
+    if (host == RT_NULL)
+    {
+        LOG_E("Get host by name failed!");
+        return;
+    }
+    /* Allocate space for recv_data */
+    /* 分配用于存放接收数据的缓冲 */
+    recv_data = rt_malloc(BUFSZ);
+    if (recv_data == RT_NULL)
+    {
+        LOG_E("No memory");
+        return;
+    }
+    /* Create a socket and set it to SOCK_STREAM(TCP) */
+    /* 创建一个socket，类型是SOCKET_STREAM，TCP类型 */
+    if ((sock = socket(AF_INET, SOCK_STREAM, 0)) == -1)
+    {
+        /* Failed on creatinf socket */
+        /* 创建socket失败 */
+        LOG_E("Create socket error");
+        goto __exit;
+    }
+    /* Initialize server side address */
+    /* 初始化预连接的服务端地址 */
+    server_addr.sin_family = AF_INET;
+    server_addr.sin_port = htons(port);
+    server_addr.sin_addr = *((struct in_addr *)host->h_addr);
+    rt_memset(&(server_addr.sin_zero), 0, sizeof(server_addr.sin_zero));
+    /* Connect to server */
+    /* 连接到服务端 */
+    if (connect(sock, (struct sockaddr *)&server_addr, sizeof(struct sockaddr)) == -1)
+    {
+        /*Failed on connecting to server*/
+        /* 连接失败 */
+        LOG_E("Connect fail!");
+        goto __exit;
+    }
+
+    started = 1;
+    is_running = 1;
+
+    timeout.tv_sec = 3;
+    timeout.tv_usec = 0;
+
+    while (is_running)
+    {
+        FD_ZERO(&readset);
+        FD_SET(sock, &readset);
+
+        /* Wait for read */
+        if (select(sock + 1, &readset, RT_NULL, RT_NULL, &timeout) == 0)
+            continue;
+        /* Receive the maximum size 1024 bytes from socket */
+        /* 从sock连接中接收最大BUFSZ - 1字节数据 */
+        bytes_received = recv(sock, recv_data, BUFSZ - 1, 0);
+        if (bytes_received < 0)
+        {
+            /* Receive failed and close the connection */
+            /* 接收失败，关闭这个连接 */
+            LOG_E("Received error, close the socket.");
+            goto __exit;
+        }
+        else if (bytes_received == 0)
+        {
+            /* Print warning message when recv function return 0 */
+            /* 打印recv函数返回值为0的警告信息 */
+            LOG_W("Received warning, recv function return 0.");
+            continue;
+        }
+        else
+        {
+            /* Receive data sucessfully and append '\0' at the end of message */
+            /* 有接收到数据，把末端清零 */
+            recv_data[bytes_received] = '\0';
+
+            if (rt_strcmp(recv_data, "q") == 0 || rt_strcmp(recv_data, "Q") == 0)
+            {
+                /* If the first letter is 'q' or 'Q', close the connection */
+                /* 如果是首字母是q或Q，关闭这个连接 */
+                LOG_I("Got a 'q' or 'Q', close the socket.");
+                goto __exit;
+            }
+            else
+            {
+                /* Show the message in terminal */
+                /* 在控制终端显示收到的数据 */
+                LOG_D("Received data = %s", recv_data);
+            }
+        }
+        /* Send message to connected socket */
+        /* 发送数据到sock连接 */
+        ret = send(sock, send_data, rt_strlen(send_data), 0);
+        if (ret < 0)
+        {
+            /* Send failed, close the connection */
+            /* 发送失败，关闭这个连接 */
+            LOG_I("send error, close the socket.");
+            goto __exit;
+        }
+        else if (ret == 0)
+        {
+            /* Print warning message when send function return 0 */
+            /* 打印send函数返回值为0的警告信息 */
+            LOG_W("Send warning, send function return 0.");
+        }
+    }
+
+__exit:
+    if (recv_data)
+    {
+        rt_free(recv_data);
+        recv_data = RT_NULL;
+    }
+    if (sock >= 0)
+    {
+        closesocket(sock);
+        sock = -1;
+    }
+    started = 0;
+    is_running = 0;
+    return;
+}
+
+/**
+ * @brief    Call this function will run LWIP example code.
+ *
+ * @note     .
+ *
+ * @param    None.
+ *
+ * @return   RT_OK or -RT_ERROR.
+ */
+
+rt_err_t lwip_demo_run(void)
+{
+    rt_thread_t tid;
+
+    tid = rt_thread_create("tcp_client",
+                           tcpclient, RT_NULL,
+                           2048, RT_THREAD_PRIORITY_MAX/3, 20);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+
+    return RT_EOK;
+}
+#endif
+
+/*@}*/

bsp/microchip/common/applications/lwip_demo.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-11  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __APPLICATION_LWIP_H_
+#define __APPLICATION_LWIP_H_
+
+#include <rtthread.h>
+
+/**
+ * @brief External function definitions
+ *
+ */
+rt_err_t lwip_demo_run(void);
+
+#endif // __APPLICATION_LWIP_H_

bsp/microchip/common/board/SConscript

@@ -0,0 +1,21 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+if GetDepend('SAM_I2C_EXAMPLE') == False:
+    SrcRemove(src, ['sam_i2c.c'])
+
+if GetDepend('SAM_LWIP_EXAMPLE') == False:
+    SrcRemove(src, ['sam_gmac.c'])
+
+# You can select chips from the list above
+CPPDEFINES = []
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
+
+Return('group')

bsp/microchip/common/board/sam_gmac.c

@@ -0,0 +1,428 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-06  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <rtdbg.h>
+
+#include <netif/ethernetif.h>
+#include <lwipopts.h>
+
+#include <atmel_start.h>
+#include <peripheral_clk_config.h>
+#include <ieee8023_mii_standard_config.h>
+
+#include "board.h"
+#include "sam_gmac.h"
+
+#ifdef RT_USING_LWIP
+
+struct rt_sam_eth
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+
+    struct mac_async_descriptor    *macif;
+    struct ethernet_phy_descriptor *phyif;
+
+#ifdef RT_USING_TIMER_SOFT
+    rt_timer_t  phy_monitor_timer;
+#else
+    rt_thread_t phy_monitor_tid;
+#endif
+
+    /* ethernet MAC address */
+    rt_uint8_t  mac_addr[NETIF_MAX_HWADDR_LEN];
+
+    /* GMAC Link Speed */
+    gmac_speed_type  link_speed;
+    /* GMAC Link Mode */
+    gmac_duplex_type link_mode;
+};
+
+static struct rt_sam_eth sam_eth_device;
+
+/**
+ * @brief Called by GMAC RX interrupt, will notify RX task
+ *
+ * @note  Will call eth_device_ready to notify RX task.
+ *
+ * @param
+ *
+ * @return
+ */
+static void rt_sam_gmac_rxcb(void)
+{
+    rt_err_t result;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    result = eth_device_ready(&sam_eth_device.parent);
+    if (result != RT_EOK)
+        LOG_E("rt_sam_gmac_rxcb error");
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * @brief Initialize the MAC hardware
+ *
+ * @note  Will set MAC filter by using input MAC address.
+ *
+ * @param gmac_dev GMAC device description.
+ *
+ * @return
+ */
+static inline void rt_sam_gmac_init(struct rt_sam_eth *gmac_dev)
+{
+    struct mac_async_filter filter;
+
+    /* set MAC hardware address */
+    rt_memcpy(filter.mac, sam_eth_device.mac_addr, NETIF_MAX_HWADDR_LEN);
+    filter.tid_enable = false;
+    mac_async_set_filter(gmac_dev->macif, 0, &filter);
+    mac_async_register_callback(gmac_dev->macif, MAC_ASYNC_RECEIVE_CB, (FUNC_PTR)rt_sam_gmac_rxcb);
+}
+
+static rt_err_t rt_sam_eth_init(rt_device_t dev)
+{
+    LOG_D("gmac init");
+    return RT_EOK;
+}
+
+static rt_err_t rt_sam_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    LOG_D("gmac open");
+    return RT_EOK;
+}
+
+static rt_err_t rt_sam_eth_close(rt_device_t dev)
+{
+    LOG_D("gmac close");
+    return RT_EOK;
+}
+
+static rt_size_t rt_sam_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    LOG_D("gmac read");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t rt_sam_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    LOG_D("gmac write");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t rt_sam_eth_control(rt_device_t dev, int cmd, void *args)
+{
+    rt_err_t ret = RT_EOK;
+
+    switch (cmd)
+    {
+        case NIOCTL_GADDR:
+            /* get mac address */
+            if (args)
+                rt_memcpy(args, sam_eth_device.mac_addr, 6);
+            break;
+
+        default :
+            break;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief Transmission packet though the MAC hardware
+ *
+ * @note  Send package to MAC.
+ *
+ * @param dev the RT net device input.
+ *
+ * @param p stored message will be sent to MAC.
+ *
+ * @return RT_EOK.
+ */
+rt_err_t rt_sam_eth_tx(rt_device_t dev, struct pbuf *p)
+{
+    struct rt_sam_eth *gmac_dev = (struct rt_sam_eth *)dev->user_data;
+    struct pbuf *      q;
+    void *             tbuf;
+    uint8_t *          pos;
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+    if (p->tot_len == p->len)
+    {
+        mac_async_write(gmac_dev->macif, p->payload, p->tot_len);
+    }
+    else
+    {
+        tbuf = mem_malloc(LWIP_MEM_ALIGN_SIZE(p->tot_len));
+        pos  = tbuf;
+        if (tbuf == NULL)
+        {
+            return ERR_MEM;
+        }
+        for (q = p; q != NULL; q = q->next)
+        {
+            rt_memcpy(pos, q->payload, q->len);
+            pos += q->len;
+        }
+        mac_async_write(gmac_dev->macif, tbuf, p->tot_len);
+        mem_free(tbuf);
+    }
+
+#if ETH_PAD_SIZE
+    pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+    LINK_STATS_INC(link.xmit);
+
+    return ERR_OK;
+}
+
+/**
+ * @brief Receive packet from the MAC hardware
+ *
+ * @note  Returned pbuf filled with the received packet (including MAC header)
+ *
+ * @param dev the RT net device input.
+ *
+ * @return NULL on memory error
+ */
+struct pbuf *rt_sam_eth_rx(rt_device_t dev)
+{
+    struct rt_sam_eth *gmac_dev = (struct rt_sam_eth *)dev->user_data;
+    struct pbuf *      p;
+    u16_t              len;
+
+    len = mac_async_read_len(gmac_dev->macif); /* Obtain the size of the packet */
+    if (len == 0)
+    {
+        return NULL;
+    }
+
+#if ETH_PAD_SIZE
+    len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
+#endif
+
+    /* Allocate a pbuf as one large chunk, This include protocol header */
+    p = pbuf_alloc(PBUF_RAW, len, PBUF_RAM);
+
+    if (p != NULL)
+    {
+#if ETH_PAD_SIZE
+        pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
+#endif
+
+        /* Read the entire packet into the pbuf. */
+        mac_async_read(gmac_dev->macif, p->payload, p->len);
+
+#if ETH_PAD_SIZE
+        pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
+#endif
+
+        LINK_STATS_INC(link.recv);
+    }
+    else
+    {
+        mac_async_read(gmac_dev->macif, NULL, 0);
+        LINK_STATS_INC(link.memerr);
+        LINK_STATS_INC(link.drop);
+    }
+
+    return p;
+}
+
+/**
+ * @brief  PHY link status monitor task - timer task or thread
+ *
+ * @note   Will check link status, link mode and link speed
+ *
+ * @param parameter input parameter passing to the function.
+ *
+ * @return
+ */
+static void rt_sam_eth_monitor(void *parameter)
+{
+    struct rt_sam_eth *sam_eth = (struct rt_sam_eth *)parameter;
+    bool link_up;
+    int32_t  ret;
+    uint16_t val;
+    static rt_uint8_t link_count = 0;
+
+#ifndef RT_USING_TIMER_SOFT
+    while (1)
+    {
+#endif
+        ret = ethernet_phy_get_link_status(sam_eth->phyif, &link_up);
+        if (ERR_NONE == ret)
+        {
+            if (link_up)
+            {
+                /* send link up. */
+                eth_device_linkchange(&sam_eth->parent, RT_TRUE);
+            }
+            else
+            {
+                /* send link down. */
+                eth_device_linkchange(&sam_eth->parent, RT_FALSE);;
+            }
+        }
+
+        ret = ethernet_phy_read_reg(sam_eth->phyif, MDIO_REG1_BMSR, &val);
+        if (ERR_NONE == ret)
+        {
+            if (val & (MDIO_REG1_BIT_100BASE_TX_FD | MDIO_REG1_BIT_100BASE_TX_HD))
+            {
+                LOG_D("100Mbps");
+                sam_eth_device.link_speed = GMAC_SPEED_100MBPS;
+            }
+            else
+            {
+                LOG_D("10Mbps");
+                sam_eth_device.link_speed = GMAC_SPEED_10MBPS;
+            }
+
+            if (val & (MDIO_REG1_BIT_100BASE_TX_FD | MDIO_REG1_BIT_10BASE_T_FD))
+            {
+                LOG_D("100Mbps");
+                sam_eth_device.link_mode = GMAC_FULL_DUPLEX;
+            }
+            else
+            {
+                LOG_D("10Mbps");
+                sam_eth_device.link_mode = GMAC_HALF_DUPLEX;
+            }
+        }
+
+        if (link_count >= 10)
+        {
+            link_count = 0;
+
+            /* Restart an auto-negotiation */
+            ethernet_phy_restart_autoneg(sam_eth->phyif);
+        }
+
+#ifndef RT_USING_TIMER_SOFT
+        rt_thread_mdelay(1000);
+    }
+#endif
+}
+
+/**
+ * @brief    Register the GMAC Ethernet device.
+ *
+ * @note
+ *
+ * @param
+ *
+ * @return   RT_OK or RT_ERROR.
+ */
+
+static int rt_hw_sam_eth_init(void)
+{
+    rt_err_t   state = RT_EOK;
+#if CONF_AT24MAC_ADDRESS != 0
+    rt_uint8_t addr  = 0x9A;
+#endif
+
+    sam_eth_device.macif = &MACIF;
+    sam_eth_device.phyif = &MACIF_PHY_desc;
+
+    sam_eth_device.link_speed = GMAC_SPEED_100MBPS;
+    sam_eth_device.link_mode  = GMAC_FULL_DUPLEX;
+
+#if CONF_AT24MAC_ADDRESS != 0
+    i2c_m_sync_enable(&I2C_0);
+    i2c_m_sync_set_slaveaddr(&I2C_0, CONF_AT24MAC_ADDRESS, I2C_M_SEVEN);
+    io_write(&(I2C_0.io), &addr, 1);
+    io_read(&(I2C_0.io),  sam_eth_device.mac_addr, 6);
+#else
+    /* set mac to 0x11 if no EEPROM mounted */
+    memset(sam_eth_device.mac_addr, 0x11, 6);
+#endif
+
+    sam_eth_device.parent.parent.init      = rt_sam_eth_init;
+    sam_eth_device.parent.parent.open      = rt_sam_eth_open;
+    sam_eth_device.parent.parent.close     = rt_sam_eth_close;
+    sam_eth_device.parent.parent.read      = rt_sam_eth_read;
+    sam_eth_device.parent.parent.write     = rt_sam_eth_write;
+    sam_eth_device.parent.parent.control   = rt_sam_eth_control;
+    sam_eth_device.parent.parent.user_data = (void *)&sam_eth_device;
+
+    sam_eth_device.parent.eth_rx = rt_sam_eth_rx;
+    sam_eth_device.parent.eth_tx = rt_sam_eth_tx;
+
+    rt_sam_gmac_init(&sam_eth_device);
+
+    /* register eth device */
+    state = eth_device_init(&(sam_eth_device.parent), "e0");
+
+    if (RT_EOK == state)
+    {
+        LOG_D("gmac device init success");
+    }
+    else
+    {
+        LOG_E("gmac device init faild: %d", state);
+        state = -RT_ERROR;
+        goto outs;
+    }
+
+    /* start SAM PHY monitor */
+#ifdef RT_USING_TIMER_SOFT
+    sam_eth_device.phy_monitor_timer = rt_timer_create("phylnk",
+                                                       rt_sam_eth_monitor,
+                                                       (void *)&sam_eth_device,
+                                                       10*RT_TICK_PER_SECOND,
+                                                       RT_TIMER_FLAG_PERIODIC);
+
+    if (RT_NULL != sam_eth_device.phy_monitor_timer)
+    {
+        rt_timer_start(sam_eth_device.phy_monitor_timer);
+    }
+    else
+    {
+        state = -RT_ERROR;
+        LOG_E("gmac rt_timer_create faild: %d", state);
+    }
+#else
+    sam_eth_device.phy_monitor_tid = rt_thread_create("phy",
+                                                      rt_sam_eth_monitor,
+                                                      (void *)&sam_eth_device,
+                                                      1024,
+                                                      RT_THREAD_PRIORITY_MAX - 2,
+                                                      2);
+    if (sam_eth_device.phy_monitor_tid != RT_NULL)
+    {
+        rt_thread_startup(sam_eth_device.phy_monitor_tid);
+    }
+    else
+    {
+        state = -RT_ERROR;
+        LOG_E("gmac rt_thread_create faild: %d", state);
+    }
+#endif
+
+outs:
+    return state;
+}
+INIT_DEVICE_EXPORT(rt_hw_sam_eth_init);
+
+#endif /* BSP_USING_ETH_ARTPI */

bsp/microchip/common/board/sam_gmac.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-11  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#ifndef __BOARD_SAM_GMAC_H_
+#define __BOARD_SAM_GMAC_H_
+
+#include <rtthread.h>
+
+/**
+  * @brief  GMAC duplex type
+  */
+typedef enum
+{
+  GMAC_HALF_DUPLEX                       = 0x00, /*!< half duplex */
+  GMAC_FULL_DUPLEX                       = 0x01  /*!< full duplex */
+} gmac_duplex_type;
+
+/**
+  * @brief  GMAC speed type
+  */
+typedef enum
+{
+  GMAC_SPEED_10MBPS                      = 0x00, /*!< 10 mbps */
+  GMAC_SPEED_100MBPS                     = 0x01  /*!< 100 mbps */
+} gmac_speed_type;
+
+#define CONF_AT24MAC_ADDRESS               0x57
+
+#endif // __BOARD_SAM_GMAC_H_

bsp/microchip/common/board/sam_i2c.c

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date        Author    Email                    Notes
+ * 2022-04-11  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#include <atmel_start.h>
+
+#ifdef SAM_I2C_EXAMPLE
+
+struct sam_i2c_bus
+{
+    struct rt_i2c_bus_device parent;
+    struct i2c_m_sync_desc  *i2c_desc;
+    char                    *device_name;
+};
+
+#define I2CBUS_NAME          "i2c0"
+
+static struct sam_i2c_bus sam_i2c0 =
+{
+    .i2c_desc    = &I2C_0,
+    .device_name = I2CBUS_NAME,
+};
+
+static rt_size_t sam_i2c_master_xfer(struct rt_i2c_bus_device *bus,
+                                     struct rt_i2c_msg msgs[],
+                                     rt_uint32_t num);
+static rt_size_t sam_i2c_slave_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num);
+static rt_err_t sam_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                    rt_uint32_t, rt_uint32_t);
+
+static const struct rt_i2c_bus_device_ops sam_i2c_ops =
+{
+    .master_xfer     = sam_i2c_master_xfer,
+    .slave_xfer      = sam_i2c_slave_xfer,
+    .i2c_bus_control = sam_i2c_bus_control,
+};
+
+static inline void sam_i2c_update_control(struct rt_i2c_msg *src,
+                                          struct _i2c_m_msg *dest)
+{
+    dest->len    = (int32_t)src->len;
+    dest->addr   = src->addr;
+    dest->buffer = src->buf;
+
+    /* Get I2C message R/W attribute first */
+    dest->flags = dest->flags & 0x0001;
+
+    if (dest->flags & RT_I2C_ADDR_10BIT)
+        dest->flags |= I2C_M_TEN;
+    else
+        dest->flags |= I2C_M_SEVEN;
+}
+
+static rt_size_t sam_i2c_master_xfer(struct rt_i2c_bus_device *bus,
+                                     struct rt_i2c_msg msgs[],
+                                     rt_uint32_t num)
+{
+    struct sam_i2c_bus *sam_i2c = (struct sam_i2c_bus *)bus;
+    struct _i2c_m_msg   i2c_msg;
+    rt_size_t i;
+
+    RT_ASSERT(bus != RT_NULL);
+
+    for (i = 0; i < num; i++)
+    {
+        sam_i2c_update_control(&msgs[i], &i2c_msg);
+        if (i2c_m_sync_transfer(sam_i2c->i2c_desc, &i2c_msg) != 0)
+            break;
+    }
+
+    return i;
+}
+
+static rt_size_t sam_i2c_slave_xfer(struct rt_i2c_bus_device *bus,
+                                    struct rt_i2c_msg msgs[],
+                                    rt_uint32_t num)
+{
+    return 0;
+}
+
+static rt_err_t sam_i2c_bus_control(struct rt_i2c_bus_device *bus,
+                                    rt_uint32_t cmd,
+                                    rt_uint32_t arg)
+{
+    return RT_ERROR;
+    struct sam_i2c_bus *sam_i2c = (struct sam_i2c_bus *)bus;
+
+    RT_ASSERT(bus != RT_NULL);
+
+    switch (cmd)
+    {
+    case RT_I2C_DEV_CTRL_CLK:
+        i2c_m_sync_set_baudrate(sam_i2c->i2c_desc, 0, arg);
+        break;
+    default:
+        return -RT_EIO;
+    }
+
+    return RT_EOK;
+}
+
+int rt_hw_i2c_init(void)
+{
+    rt_i2c_bus_device_register(&sam_i2c0.parent, sam_i2c0.device_name);
+    return 0;
+}
+#ifdef RT_USING_COMPONENTS_INIT
+INIT_BOARD_EXPORT(rt_hw_i2c_init);
+#endif
+#endif
+/*@}*/

bsp/microchip/same70/board/serial.h → bsp/microchip/common/board/sam_i2c.h

@@ -5,11 +5,11 @@
  *
  * Change Logs:
  * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ * 2022-04-11  Kevin.Liu kevin.liu.mchp@gmail.com First Release
  */
 
-#ifndef __BOARD_SERIAL_H_
-#define __BOARD_SERIAL_H_
+#ifndef __BOARD_SAM_I2C_H_
+#define __BOARD_SAM_I2C_H_
 
 #include <rtthread.h>
 
@@ -17,6 +17,6 @@
  * @brief External function definitions
  *
  */
-int rt_hw_uart_init(void);
+int rt_hw_i2c_init(void);
 
-#endif // __BOARD_SERIAL_H_
+#endif // __BOARD_SAM_I2C_H_

bsp/microchip/same54/board/serial.c → bsp/microchip/common/board/serial.c

@@ -16,6 +16,34 @@
 /* SAM MCU serial device */
 static struct rt_serial_device sam_serial;
 
+static void serial_rxcallback(const struct usart_async_descriptor *const io_descr)
+{
+    (void)io_descr;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Notify Serial driver to process RX data */
+    rt_hw_serial_isr(&sam_serial, RT_SERIAL_EVENT_RX_IND);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+static void serial_txcallback(const struct usart_async_descriptor *const io_descr)
+{
+    (void)io_descr;
+
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    /* Notify Serial driver to process TX done event */
+    rt_hw_serial_isr(&sam_serial, RT_SERIAL_EVENT_TX_DONE);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
 /**
  * @brief Configure serial port
  *
@@ -25,61 +53,61 @@ static struct rt_serial_device sam_serial;
  */
 static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
-    struct usart_sync_descriptor* desc;
+    struct usart_async_descriptor* desc;
 
     RT_ASSERT(serial != RT_NULL);
 
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+    desc = (struct usart_async_descriptor *)serial->parent.user_data;
 
     RT_ASSERT(desc != RT_NULL);
     RT_ASSERT(cfg  != RT_NULL);
 
-    usart_sync_disable(desc);
+    usart_async_disable(desc);
 
     /* Set baudrate */
-    usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
+    usart_async_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
 
     /* Set stop bit */
     if (cfg->stop_bits == STOP_BITS_1)
-        usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
+        usart_async_set_stopbits(desc, USART_STOP_BITS_ONE);
     else if (cfg->stop_bits == STOP_BITS_2)
-        usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
+        usart_async_set_stopbits(desc, USART_STOP_BITS_TWO);
 
     if (cfg->bit_order == BIT_ORDER_LSB)
-        usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
+        usart_async_set_data_order(desc, USART_DATA_ORDER_LSB);
     else if (cfg->bit_order == BIT_ORDER_MSB)
-        usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
+        usart_async_set_data_order(desc, USART_DATA_ORDER_MSB);
 
     /* Set character size */
     switch (cfg->data_bits)
     {
         case DATA_BITS_5:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
+            usart_async_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
             break;
         case DATA_BITS_6:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
+            usart_async_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
             break;
         case DATA_BITS_7:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
+            usart_async_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
             break;
         case DATA_BITS_8:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
+            usart_async_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
             break;
         case DATA_BITS_9:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
+            usart_async_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
             break;
         default:
             break;
     }
 
     if (cfg->parity == PARITY_NONE)
-        usart_sync_set_parity(desc, USART_PARITY_NONE);
+        usart_async_set_parity(desc, USART_PARITY_NONE);
     else if (cfg->parity == PARITY_ODD)
-        usart_sync_set_parity(desc, USART_PARITY_ODD);
+        usart_async_set_parity(desc, USART_PARITY_ODD);
     else if (cfg->parity == PARITY_EVEN)
-        usart_sync_set_parity(desc, USART_PARITY_EVEN);
+        usart_async_set_parity(desc, USART_PARITY_EVEN);
 
-    usart_sync_enable(desc);
+    usart_async_enable(desc);
 
     return RT_EOK;
 }
@@ -93,10 +121,10 @@ static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_
  */
 static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
 {
-    struct usart_sync_descriptor* desc;
+    struct usart_async_descriptor* desc;
 
     RT_ASSERT(serial != RT_NULL);
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+    desc = (struct usart_async_descriptor *)serial->parent.user_data;
 
     RT_ASSERT(desc != RT_NULL);
 
@@ -104,11 +132,11 @@ static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *a
     {
         /* disable interrupt */
         case RT_DEVICE_CTRL_CLR_INT:
-            usart_sync_disable(desc);
+            usart_async_disable(desc);
             break;
         /* enable interrupt */
         case RT_DEVICE_CTRL_SET_INT:
-            usart_sync_enable(desc);
+            usart_async_enable(desc);
             break;
         /* UART config */
         case RT_DEVICE_CTRL_CONFIG :
@@ -127,14 +155,15 @@ static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *a
  */
 static int serial_putc(struct rt_serial_device *serial, char c)
 {
-    struct usart_sync_descriptor* desc;
+    struct usart_async_descriptor* desc;
 
     RT_ASSERT(serial != RT_NULL);
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+    desc = (struct usart_async_descriptor *)serial->parent.user_data;
 
     RT_ASSERT(desc != RT_NULL);
 
-    io_write(&desc->io, (const uint8_t *)&c, 1);
+    while (usart_async_is_tx_empty(desc) == 0);
+    _usart_async_write_byte(&TARGET_IO.device, (uint8_t)c);
 
     return 1;
 }
@@ -150,17 +179,17 @@ static int serial_getc(struct rt_serial_device *serial)
 {
     char c;
     int ch;
-    struct usart_sync_descriptor* desc;
+    struct usart_async_descriptor* desc;
 
     RT_ASSERT(serial != RT_NULL);
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
+    desc = (struct usart_async_descriptor *)serial->parent.user_data;
 
     RT_ASSERT(desc != RT_NULL);
 
     ch = -1;
-    if (usart_sync_is_rx_not_empty(desc))
+    if (usart_async_is_rx_not_empty(desc))
     {
-        io_read(&desc->io, (uint8_t *)&c, 1);;
+        io_read(&desc->io, (uint8_t *)&c, 1);
         ch = c & 0xff;
     }
 
@@ -190,8 +219,12 @@ int rt_hw_uart_init(void)
     sam_serial.config    = config;
     sam_serial.serial_rx = RT_NULL;
     sam_serial.serial_rx = RT_NULL;
-    rt_hw_serial_register(&sam_serial, "uart0",
-                          RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
+    rt_hw_serial_register(&sam_serial, RT_CONSOLE_DEVICE_NAME,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX, (void *)&TARGET_IO);
+
+    usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, serial_txcallback);
+    usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, serial_rxcallback);
 
     return 0;
 }

bsp/microchip/samc21/.config

@@ -93,8 +93,32 @@ CONFIG_RT_USING_USER_MAIN=y
 CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # CONFIG_RT_USING_LEGACY is not set
-# CONFIG_RT_USING_MSH is not set
-# CONFIG_RT_USING_DFS is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
 # CONFIG_RT_USING_FAL is not set
 # CONFIG_RT_USING_LWP is not set
 
@@ -102,7 +126,9 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
@@ -111,7 +137,9 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+# CONFIG_RT_USING_I2C_BITOPS is not set
 # CONFIG_RT_USING_PHY is not set
 # CONFIG_RT_USING_PIN is not set
 # CONFIG_RT_USING_ADC is not set
@@ -639,10 +667,12 @@ CONFIG_SOC_SAMC21J18=y
 #
 CONFIG_SAMC21_CAN0=y
 CONFIG_SAMC21_ADC0=y
+CONFIG_SAMC21_I2C0=y
 
 #
 # Application Demo Config
 #
 CONFIG_SAM_CAN_EXAMPLE=y
 CONFIG_SAM_ADC_EXAMPLE=y
+CONFIG_SAM_I2C_EXAMPLE=y
 CONFIG_SOC_SAMC21=y

bsp/microchip/samc21/SConstruct

@@ -34,8 +34,27 @@ if rtconfig.PLATFORM == 'iar':
 Export('RTT_ROOT')
 Export('rtconfig')
 
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/common'):
+    common_path_prefix = SDK_ROOT + '/common'
+else:
+    common_path_prefix = os.path.dirname(SDK_ROOT) + '/common'
+
+SDK_LIB = common_path_prefix
+Export('SDK_LIB')
+
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
+sam_board = 'board'
+rtconfig.BSP_LIBRARY_TYPE = sam_board
+
+# include libraries
+objs.extend(SConscript(os.path.join(common_path_prefix, sam_board, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(common_path_prefix, 'applications', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)

bsp/microchip/samc21/applications/can_demo.c

@@ -1,333 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
- */
-
-#include <rtthread.h>
-
-#ifdef RT_USING_FINSH
-#include <finsh.h>
-#include <shell.h>
-#endif
-
-#include "atmel_start.h"
-#include "driver_init.h"
-#include "utils.h"
-
-#include "can_demo.h"
-
-#ifdef SAM_CAN_EXAMPLE
-
-static volatile enum can_async_interrupt_type can_errors;
-static rt_sem_t   can_txdone;
-static rt_sem_t   can_rxdone;
-static rt_uint8_t can_stack[ 512 ];
-static struct rt_thread can_thread;
-
-/**
- * @brief    Callback function and should be invoked after call can_async_write.
- *
- * @note
- *
- * @param    descr is CAN device description.
- *
- * @return   None.
- */
-
-static void can_tx_callback(struct can_async_descriptor *const descr)
-{
-    rt_err_t result;
-
-    rt_interrupt_enter();
-    result = rt_sem_release(can_txdone);
-    if (RT_EOK != result)
-    {
-#ifndef RT_USING_FINSH
-        rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
-#endif
-    }
-    rt_interrupt_leave();
-}
-
-/**
- * @brief    Callback function and should be invoked after remote device send.
- *
- * @note     This callback function will be called in CAN interrupt function
- *
- * @param    descr is CAN device description.
- *
- * @return   None.
- */
-
-static void can_rx_callback(struct can_async_descriptor *const descr)
-{
-    rt_err_t result;
-
-    rt_interrupt_enter();
-    result = rt_sem_release(can_rxdone);
-    if (RT_EOK != result)
-    {
-#ifndef RT_USING_FINSH
-        rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
-#endif
-    }
-    rt_interrupt_leave();
-}
-
-/**
- * @brief    Callback function and should be invoked after CAN device IRQ handler detects errors happened.
- *
- * @note     This callback function will be called in CAN interrupt function
- *
- * @param    descr is CAN device description.
- *
- * @return   None.
- */
-
-static void can_err_callback(struct can_async_descriptor *const descr,
-                             enum can_async_interrupt_type type)
-{
-    rt_err_t result;
-
-    if (type == CAN_IRQ_EW)
-    {
-      /* Error warning, Error counter has reached the error warning limit of 96,
-       * An error count value greater than about 96 indicates a heavily disturbed
-       * bus. It may be of advantage to provide means to test for this condition.
-       */
-    }
-    else if (type == CAN_IRQ_EA)
-    {
-        /* Error Active State, The CAN node normally take part in bus communication
-         * and sends an ACTIVE ERROR FLAG when an error has been detected.
-         */
-    }
-    else if (type == CAN_IRQ_EP)
-    {
-        /* Error Passive State, The Can node goes into error passive state if at least
-         * one of its error counters is greater than 127. It still takes part in bus
-         * activities, but it sends a passive error frame only, on errors.
-         */
-    }
-    else if (type == CAN_IRQ_BO)
-    {
-        /* Bus Off State, The CAN node is 'bus off' when the TRANSMIT ERROR COUNT is
-         * greater than or equal to 256.
-         */
-
-        /* Suspend CAN task and re-initialize CAN module. */
-        can_errors = type;
-        rt_interrupt_enter();
-        result = rt_sem_release(can_rxdone);
-        if (RT_EOK != result)
-        {
-#ifndef RT_USING_FINSH
-            rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
-#endif
-        }
-        rt_interrupt_leave();
-    }
-    else if (type == CAN_IRQ_DO)
-    {
-        /* Data Overrun in receive queue. A message was lost because the messages in
-         * the queue was not reading and releasing fast enough. There is not enough
-         * space for a new message in receive queue.
-         */
-
-        /* Suggest to delete CAN task and re-initialize it. */
-        can_errors = type;
-        rt_interrupt_enter();
-        result = rt_sem_release(can_rxdone);
-        if (RT_EOK != result)
-        {
-#ifndef RT_USING_FINSH
-            rt_kprintf("rt_sem_release failed in %s %d\r\n",__FUNCTION__, __LINE__);
-#endif
-        }
-        rt_interrupt_leave();
-    }
-};
-
-/**
- * @brief    Initialize CAN module before task run.
- *
- * @note     This function will set CAN Tx/Rx callback function and filters.
- *
- * @param    None.
- *
- * @return   None.
- */
-
-static inline void can_demo_init(void)
-{
-    struct can_filter  filter;
-
-    /**
-     * CAN_Node0_tx_callback callback should be invoked after call
-     * can_async_write, and remote device should receive message with ID=0x45A
-     */
-    can_async_register_callback(&CAN_0, CAN_ASYNC_TX_CB, (FUNC_PTR)can_tx_callback);
-
-    /**
-     * CAN_0_rx_callback callback should be invoked after call
-     * can_async_set_filter and remote device send CAN Message with the same
-     * content as the filter.
-     */
-    can_async_register_callback(&CAN_0, CAN_ASYNC_RX_CB, (FUNC_PTR)can_rx_callback);
-
-
-    /* Should set at least one CAN standard & message filter before enable it. */
-
-    filter.id   = 0x469;
-    filter.mask = 0;
-    can_async_set_filter(&CAN_0, 0, CAN_FMT_STDID, &filter);
-
-    /* If set second standard message filter, should increase filter index
-     * and filter algorithm
-     * For example: index should set to 1, otherwise it will replace filter 0.
-     * can_async_set_filter(&CAN_0, 1, CAN_FMT_STDID, &filter); */
-
-    filter.id   = 0x10000096;
-    filter.mask = 0;
-    can_async_set_filter(&CAN_0, 0, CAN_FMT_EXTID, &filter);
-
-    can_async_enable(&CAN_0);
-}
-
-/**
- * @brief    CAN task.
- *
- * @note     This task will waiting for CAN RX semaphore and then process input.
- *
- * @param    parameter - task input parameter.
- *
- * @return   None.
- */
-
-static void can_thread_entry(void* parameter)
-{
-    int32_t  ret;
-    rt_err_t result;
-    uint8_t  data[64];
-    uint32_t count=0;
-    struct can_message msg;
-
-    while (1)
-    {
-#ifndef RT_USING_FINSH
-        rt_kprintf("can task run count : %d\r\n",count);
-#endif
-        count++;
-
-        result = rt_sem_take(can_rxdone, RT_WAITING_FOREVER);
-        if (RT_EOK != result)
-            continue;
-
-        do
-        {
-            /* Process the incoming packet. */
-            ret = can_async_read(&CAN_0, &msg);
-            if (ret == ERR_NONE)
-            {
-#ifndef RT_USING_FINSH
-                rt_kprintf("CAN RX Message is % frame\r\n",
-                           msg.type == CAN_TYPE_DATA ? "data" : "remote");
-                rt_kprintf("CAN RX Message is % frame\r\n",
-                           msg.type == CAN_FMT_STDID ? "Standard" : "Extended");
-                rt_kprintf("can RX Message ID: 0x%X length: %d\r\n", msg.id, msg.len);
-                rt_kprintf("CAN RX Message content: ");
-                for (uint8_t i = 0; i < msg.len; i++)
-                    rt_kprintf("0x%02X ", data[i]);
-                rt_kprintf("\r\n");
-#endif
-            }
-        } while (ret == ERR_NONE); /* Get all data stored in CAN RX FIFO */
-
-        /* CAN task got CAN error message, handler CAN Error Status */
-        if ((can_errors == CAN_IRQ_BO) || (can_errors == CAN_IRQ_DO))
-        {
-            can_async_init(&CAN_0, CAN1);
-        }
-    }
-}
-
-/**
- * @brief    Call this function will to send a CAN message.
- *
- * @note
- *
- * @param    msg - message to be sent, timeouts - wait timeouts for Tx completion.
- *
- * @return   RT_OK or RT_ERROR.
- */
-
-rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts)
-{
-    rt_err_t result;
-
-    if (RT_NULL == msg)
-    {
-        rt_kprintf("can_send_message input message error\r\n");
-        return RT_ERROR;
-    }
-
-    can_async_write(&CAN_0, msg);
-    result = rt_sem_take(can_rxdone, timeouts);
-
-    return result;
-}
-
-/**
- * @brief    Call this function will create a CAN task.
- *
- * @note     Should create Tx/Rx semaphore before run task.
- *
- * @param    None.
- *
- * @return   RT_OK or -RT_ERROR.
- */
-
-rt_err_t can_demo_run(void)
-{
-    rt_err_t result;
-
-    can_rxdone = rt_sem_create("can_rx", 0, RT_IPC_FLAG_FIFO);
-    if (RT_NULL == can_rxdone)
-    {
-        rt_kprintf("can_rx semaphore create failed\r\n");
-        return (-RT_ERROR);
-    }
-
-    can_txdone = rt_sem_create("can_tx", 0, RT_IPC_FLAG_FIFO);
-    if (RT_NULL == can_txdone)
-    {
-        rt_kprintf("can_tx semaphore create failed\r\n");
-        return (-RT_ERROR);
-    }
-
-    can_demo_init();
-
-    /* initialize CAN thread */
-    result = rt_thread_init(&can_thread,
-                            "can",
-                            can_thread_entry,
-                            RT_NULL,
-                            (rt_uint8_t*)&can_stack[0],
-                            sizeof(can_stack),
-                            RT_THREAD_PRIORITY_MAX/3,
-                            5);
-    if (result == RT_EOK)
-    {
-        rt_thread_startup(&can_thread);
-    }
-
-    return result;
-}
-#endif
-
-/*@}*/

bsp/microchip/samc21/applications/main.c

@@ -5,7 +5,7 @@
  *
  * Change Logs:
  * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ * 2022-04-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
  */
 
 #include <rtthread.h>
@@ -22,6 +22,14 @@
 #include "can_demo.h"
 #endif
 
+#ifdef SAM_I2C_EXAMPLE
+#include "i2c_demo.h"
+#endif
+
+#ifdef SAM_ADC_EXAMPLE
+#include "adc_demo.h"
+#endif
+
 static rt_uint8_t led_stack[ 512 ];
 static struct rt_thread led_thread;
 
@@ -63,6 +71,14 @@ int main(void)
     can_demo_run();
 #endif
 
+#ifdef SAM_I2C_EXAMPLE
+    i2c_demo_run();
+#endif
+
+#ifdef SAM_ADC_EXAMPLE
+    adc_demo_run();
+#endif
+
     return 0;
 }
 

bsp/microchip/samc21/board/Kconfig

@@ -32,6 +32,11 @@ menu "Onboard Peripheral Drivers"
     config SAMC21_ADC0
         bool "Enable ADC0"
         default false
+
+    config SAMC21_I2C0
+        bool "Enable I2C0"
+        default false
+
 endmenu
 
 menu "Application Demo Config"
@@ -49,4 +54,10 @@ menu "Application Demo Config"
         help
             Add ADC example task to project
 
+    config SAM_I2C_EXAMPLE
+        bool "Enable SAM I2C Example"
+        depends on SAMC21_I2C0
+        default true
+        help
+            Add I2C example task to project
 endmenu

bsp/microchip/samc21/board/board.c

@@ -25,13 +25,14 @@ static struct io_descriptor* g_stdio;
 void rt_hw_console_output(const char *str)
 {
     io_write(g_stdio, (uint8_t *)str, strlen(str));
+    while (TARGET_IO.stat != 0);
 }
 RTM_EXPORT(rt_hw_console_output);
 
 static inline void hw_board_init_usart(void)
 {
-    usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
-    usart_sync_enable(&TARGET_IO);
+    usart_async_get_io_descriptor(&TARGET_IO, &g_stdio);
+    usart_async_enable(&TARGET_IO);
 }
 
 /**

bsp/microchip/samc21/board/serial.c

@@ -1,199 +0,0 @@
-/*
- * Copyright (c)
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
- */
-
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#include <atmel_start.h>
-
-/* SAM MCU serial device */
-static struct rt_serial_device sam_serial;
-
-/**
- * @brief Configure serial port
- *
- * This function will configure UART baudrate, parity and so on.
- *
- * @return RT_EOK.
- */
-static rt_err_t serial_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    struct usart_sync_descriptor* desc;
-
-    RT_ASSERT(serial != RT_NULL);
-
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
-
-    RT_ASSERT(desc != RT_NULL);
-    RT_ASSERT(cfg  != RT_NULL);
-
-    usart_sync_disable(desc);
-
-    /* Set baudrate */
-    usart_sync_set_baud_rate(desc, (const uint32_t)cfg->baud_rate);
-
-    /* Set stop bit */
-    if (cfg->stop_bits == STOP_BITS_1)
-        usart_sync_set_stopbits(desc, USART_STOP_BITS_ONE);
-    else if (cfg->stop_bits == STOP_BITS_2)
-        usart_sync_set_stopbits(desc, USART_STOP_BITS_TWO);
-
-    if (cfg->bit_order == BIT_ORDER_LSB)
-        usart_sync_set_data_order(desc, USART_DATA_ORDER_LSB);
-    else if (cfg->bit_order == BIT_ORDER_MSB)
-        usart_sync_set_data_order(desc, USART_DATA_ORDER_MSB);
-
-    /* Set character size */
-    switch (cfg->data_bits)
-    {
-        case DATA_BITS_5:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_5BITS);
-            break;
-        case DATA_BITS_6:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_6BITS);
-            break;
-        case DATA_BITS_7:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_7BITS);
-            break;
-        case DATA_BITS_8:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_8BITS);
-            break;
-        case DATA_BITS_9:
-            usart_sync_set_character_size(desc, USART_CHARACTER_SIZE_9BITS);
-            break;
-        default:
-            break;
-    }
-
-    if (cfg->parity == PARITY_NONE)
-        usart_sync_set_parity(desc, USART_PARITY_NONE);
-    else if (cfg->parity == PARITY_ODD)
-        usart_sync_set_parity(desc, USART_PARITY_ODD);
-    else if (cfg->parity == PARITY_EVEN)
-        usart_sync_set_parity(desc, USART_PARITY_EVEN);
-
-    usart_sync_enable(desc);
-
-    return RT_EOK;
-}
-
-/**
- * @brief Control serial port
- *
- * This function provide UART enable/disable control.
- *
- * @return RT_EOK.
- */
-static rt_err_t serial_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct usart_sync_descriptor* desc;
-
-    RT_ASSERT(serial != RT_NULL);
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
-
-    RT_ASSERT(desc != RT_NULL);
-
-    switch (cmd)
-    {
-        /* disable interrupt */
-        case RT_DEVICE_CTRL_CLR_INT:
-            usart_sync_disable(desc);
-            break;
-        /* enable interrupt */
-        case RT_DEVICE_CTRL_SET_INT:
-            usart_sync_enable(desc);
-            break;
-        /* UART config */
-        case RT_DEVICE_CTRL_CONFIG :
-            break;
-    }
-
-    return RT_EOK;
-}
-
-/**
- * @brief Serial sends a char
- *
- * This function will send a char to the UART
- *
- * @return 1.
- */
-static int serial_putc(struct rt_serial_device *serial, char c)
-{
-    struct usart_sync_descriptor* desc;
-
-    RT_ASSERT(serial != RT_NULL);
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
-
-    RT_ASSERT(desc != RT_NULL);
-
-    io_write(&desc->io, (const uint8_t *)&c, 1);
-
-    return 1;
-}
-
-/**
- * @brief Serial gets a char
- *
- * This function will get a char from the UART
- *
- * @return received char character or -1 if no char received.
- */
-static int serial_getc(struct rt_serial_device *serial)
-{
-    char c;
-    int ch;
-    struct usart_sync_descriptor* desc;
-
-    RT_ASSERT(serial != RT_NULL);
-    desc = (struct usart_sync_descriptor *)serial->parent.user_data;
-
-    RT_ASSERT(desc != RT_NULL);
-
-    ch = -1;
-    if (usart_sync_is_rx_not_empty(desc))
-    {
-        io_read(&desc->io, (uint8_t *)&c, 1);;
-        ch = c & 0xff;
-    }
-
-    return ch;
-}
-
-static const struct rt_uart_ops sam_serial_ops =
-{
-    serial_configure,
-    serial_control,
-    serial_putc,
-    serial_getc,
-};
-
-/**
- * @brief Initialize the UART
- *
- * This function initialize the UART
- *
- * @return None.
- */
-int rt_hw_uart_init(void)
-{
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
-
-    sam_serial.ops       = &sam_serial_ops;
-    sam_serial.config    = config;
-    sam_serial.serial_rx = RT_NULL;
-    sam_serial.serial_rx = RT_NULL;
-    rt_hw_serial_register(&sam_serial, "uart0",
-                          RT_DEVICE_FLAG_RDWR, (void *)&TARGET_IO);
-
-    return 0;
-}
-
-/*@}*/

bsp/microchip/samc21/bsp/AtmelStart.gpdsc

@@ -42,17 +42,21 @@
       <description>Atmel Start Framework</description>
       <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
       <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/flash.rst"/>
-        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_flash.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
@@ -78,6 +82,7 @@
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_flash.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
@@ -90,9 +95,11 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
         <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/divas/hpl_divas.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_c21.h"/>
@@ -138,7 +145,10 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="config/hpl_divas_config.h"/>
-        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
@@ -148,8 +158,11 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
-        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_async.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can_base.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m0plus_base.c"/>
@@ -168,6 +181,7 @@
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_can_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
@@ -183,6 +197,7 @@
         <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/can"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/divas"/>

bsp/microchip/samc21/bsp/SConscript

@@ -11,8 +11,10 @@ CPPDEFINES = []
 CPPDEFINES += [rtconfig.DEVICE_TYPE]
 
 # The set of source files associated with this SConscript file.
+
 src  = Glob('hal/src/*.c')
 src += Glob('hal/utils/src/*.c')
+src += Glob('hpl/adc/*.c')
 src += Glob('hpl/can/*.c')
 src += Glob('hpl/core/*.c')
 src += Glob('hpl/divas/*.c')
@@ -45,12 +47,15 @@ path = [
     cwd + '/config',
     cwd + '/hal/include',
     cwd + '/hal/utils/include',
+    cwd + '/hpl/adc',
     cwd + '/hpl/can',
     cwd + '/hpl/core',
     cwd + '/hpl/gclk',
     cwd + '/hpl/pm',
     cwd + '/hpl/port',
     cwd + '/hri',
+    cwd + '/../board',
+    cwd + '/../../common/applications',
     cwd + '/samc21/include']
 
 group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)

bsp/microchip/samc21/bsp/armcc/Makefile

@@ -1,218 +0,0 @@
-
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-ifdef SystemRoot
-	SHELL = cmd.exe
-	MK_DIR = mkdir
-else
-	ifeq ($(shell uname), Linux)
-		MK_DIR = mkdir -p
-	endif
-
-	ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
-		MK_DIR = mkdir -p
-	endif
-
-	ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
-		MK_DIR = mkdir -p
-	endif
-
-	ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
-		MK_DIR = mkdir -p
-	endif
-endif
-
-# List the subdirectories for creating object files
-SUB_DIRS +=  \
- \
-hpl/pm \
-hpl/osc32kctrl \
-hpl/can \
-hpl/dmac \
-samc21/armcc/Device/SAMC21/Source/ARM \
-hal/src \
-hpl/mclk \
-hal/utils/src \
-hpl/sercom \
-examples \
-hpl/gclk \
-hpl/oscctrl \
-samc21/armcc/Device/SAMC21/Source \
-hpl/nvmctrl \
-hpl/core \
-hpl/divas
-
-# List the object files
-OBJS +=  \
-hal/src/hal_io.o \
-hal/src/hal_can_async.o \
-hpl/can/hpl_can.o \
-hpl/nvmctrl/hpl_nvmctrl.o \
-samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.o \
-hal/src/hal_delay.o \
-hpl/oscctrl/hpl_oscctrl.o \
-hpl/core/hpl_init.o \
-hal/utils/src/utils_list.o \
-hpl/core/hpl_core_m0plus_base.o \
-hal/utils/src/utils_assert.o \
-hpl/dmac/hpl_dmac.o \
-hpl/pm/hpl_pm.o \
-hal/src/hal_usart_sync.o \
-hpl/mclk/hpl_mclk.o \
-hpl/gclk/hpl_gclk.o \
-hal/src/hal_flash.o \
-hal/src/hal_init.o \
-main.o \
-hpl/osc32kctrl/hpl_osc32kctrl.o \
-examples/driver_examples.o \
-driver_init.o \
-samc21/armcc/Device/SAMC21/Source/system_samc21.o \
-hpl/sercom/hpl_sercom.o \
-hal/src/hal_gpio.o \
-hpl/divas/hpl_divas.o \
-hal/utils/src/utils_event.o \
-hal/src/hal_sleep.o \
-atmel_start.o \
-hal/src/hal_atomic.o
-
-OBJS_AS_ARGS +=  \
-"hal/src/hal_io.o" \
-"hal/src/hal_can_async.o" \
-"hpl/can/hpl_can.o" \
-"hpl/nvmctrl/hpl_nvmctrl.o" \
-"samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.o" \
-"hal/src/hal_delay.o" \
-"hpl/oscctrl/hpl_oscctrl.o" \
-"hpl/core/hpl_init.o" \
-"hal/utils/src/utils_list.o" \
-"hpl/core/hpl_core_m0plus_base.o" \
-"hal/utils/src/utils_assert.o" \
-"hpl/dmac/hpl_dmac.o" \
-"hpl/pm/hpl_pm.o" \
-"hal/src/hal_usart_sync.o" \
-"hpl/mclk/hpl_mclk.o" \
-"hpl/gclk/hpl_gclk.o" \
-"hal/src/hal_flash.o" \
-"hal/src/hal_init.o" \
-"main.o" \
-"hpl/osc32kctrl/hpl_osc32kctrl.o" \
-"examples/driver_examples.o" \
-"driver_init.o" \
-"samc21/armcc/Device/SAMC21/Source/system_samc21.o" \
-"hpl/sercom/hpl_sercom.o" \
-"hal/src/hal_gpio.o" \
-"hpl/divas/hpl_divas.o" \
-"hal/utils/src/utils_event.o" \
-"hal/src/hal_sleep.o" \
-"atmel_start.o" \
-"hal/src/hal_atomic.o"
-
-# List the dependency files
-DEPS := $(OBJS:%.o=%.d)
-
-DEPS_AS_ARGS +=  \
-"hal/utils/src/utils_event.d" \
-"hal/src/hal_io.d" \
-"hal/src/hal_can_async.d" \
-"hpl/can/hpl_can.d" \
-"samc21/armcc/Device/SAMC21/Source/ARM/startup_SAMC21.d" \
-"hpl/nvmctrl/hpl_nvmctrl.d" \
-"hpl/core/hpl_core_m0plus_base.d" \
-"hal/utils/src/utils_list.d" \
-"hpl/dmac/hpl_dmac.d" \
-"hal/utils/src/utils_assert.d" \
-"hal/src/hal_delay.d" \
-"hpl/core/hpl_init.d" \
-"hpl/pm/hpl_pm.d" \
-"hal/src/hal_flash.d" \
-"hpl/gclk/hpl_gclk.d" \
-"hal/src/hal_init.d" \
-"hal/src/hal_usart_sync.d" \
-"hpl/mclk/hpl_mclk.d" \
-"driver_init.d" \
-"samc21/armcc/Device/SAMC21/Source/system_samc21.d" \
-"hpl/osc32kctrl/hpl_osc32kctrl.d" \
-"main.d" \
-"examples/driver_examples.d" \
-"hpl/divas/hpl_divas.d" \
-"hal/src/hal_sleep.d" \
-"hpl/sercom/hpl_sercom.d" \
-"hal/src/hal_gpio.d" \
-"hal/src/hal_atomic.d" \
-"hpl/oscctrl/hpl_oscctrl.d" \
-"atmel_start.d"
-
-OUTPUT_FILE_NAME :=AtmelStart
-QUOTE := "
-OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
-OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
-
-vpath %.c ../
-vpath %.s ../
-vpath %.S ../
-
-# All Target
-all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
-
-# Linker target
-
-$(OUTPUT_FILE_PATH): $(OBJS)
-	@echo Building target: $@
-	@echo Invoking: ARMCC Linker
-	$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
---strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
---info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
--o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M0+ \
-$(OBJS_AS_ARGS)
-
-	@echo Finished building target: $@
-
-# Compiler target(s)
-
-
-
-
-%.o: %.c
-	@echo Building file: $<
-	@echo ARMCC Compiler
-	$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMC21J18A__ \
--I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/can" -I"../hpl/core" -I"../hpl/divas" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../samc21/include"  \
---depend "$@"  -o "$@" "$<"
-
-	@echo Finished building: $<
-
-%.o: %.s
-	@echo Building file: $<
-	@echo ARMCC Assembler
-	$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M0+ --pd "D__SAMC21J18A__ SETA 1" \
--I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/can" -I"../hpl/core" -I"../hpl/divas" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../samc21/include"  \
---depend "$(@:%.o=%.d)" -o "$@" "$<"
-
-	@echo Finished building: $<
-
-%.o: %.S
-	@echo Building file: $<
-	@echo ARMCC Preprocessing Assembler
-	$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M0+ -D__SAMC21J18A__ \
--I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/can" -I"../hpl/core" -I"../hpl/divas" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/nvmctrl" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../samc21/include"  \
---depend "$@"  -o "$@" "$<"
-
-	@echo Finished building: $<
-
-# Detect changes in the dependent files and recompile the respective object files.
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(DEPS)),)
--include $(DEPS)
-endif
-endif
-
-$(SUB_DIRS):
-	$(MK_DIR) "$@"
-
-clean:
-	rm -f $(OBJS_AS_ARGS)
-	rm -f $(OUTPUT_FILE_PATH)
-	rm -f $(DEPS_AS_ARGS)
-	rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf

bsp/microchip/samc21/bsp/atmel_start_config.atstart

@@ -22,6 +22,64 @@ application:
   configuration: null
 middlewares: {}
 drivers:
+  ADC_0:
+    user_label: ADC_0
+    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+    functionality: ADC
+    api: HAL:Driver:ADC_Sync
+    configuration:
+      adc_advanced_settings: true
+      adc_arch_adjres: 0
+      adc_arch_corren: false
+      adc_arch_dbgrun: false
+      adc_arch_dualsel: BOTH
+      adc_arch_event_settings: false
+      adc_arch_flushei: false
+      adc_arch_flushinv: false
+      adc_arch_gaincorr: 0
+      adc_arch_leftadj: false
+      adc_arch_offcomp: false
+      adc_arch_offsetcorr: 0
+      adc_arch_ondemand: false
+      adc_arch_r2r: false
+      adc_arch_refcomp: false
+      adc_arch_resrdyeo: false
+      adc_arch_runstdby: false
+      adc_arch_samplen: 0
+      adc_arch_samplenum: 1 sample
+      adc_arch_seqen: 0
+      adc_arch_slaveen: false
+      adc_arch_startei: false
+      adc_arch_startinv: false
+      adc_arch_winlt: 0
+      adc_arch_winmode: No window mode
+      adc_arch_winmoneo: false
+      adc_arch_winut: 0
+      adc_differential_mode: false
+      adc_freerunning_mode: false
+      adc_pinmux_negative: I/O ground
+      adc_pinmux_positive: ADC AIN0 pin
+      adc_prescaler: Peripheral clock divided by 2
+      adc_reference: Internal bandgap reference
+      adc_resolution: 16-bit (averaging must be enabled)
+    optional_signals:
+    - identifier: ADC_0:AIN/10
+      pad: PA10
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::optional_signal_definition::ADC0.AIN.10
+      name: ADC0/AIN/10
+      label: AIN/10
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: ADC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          adc_gclk_selection: Generic clock generator 0
   DMAC:
     user_label: DMAC
     definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC
@@ -589,13 +647,53 @@ drivers:
     variant: null
     clocks:
       domain_group: null
+  I2C_0:
+    user_label: I2C_0
+    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM0::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
+    functionality: I2C
+    api: HAL:Driver:I2C_Master_Sync
+    configuration:
+      i2c_master_advanced: true
+      i2c_master_arch_dbgstop: Keep running
+      i2c_master_arch_inactout: 20-21 SCL cycle time-out(200-210us)
+      i2c_master_arch_lowtout: true
+      i2c_master_arch_mexttoen: true
+      i2c_master_arch_runstdby: false
+      i2c_master_arch_sdahold: 300-600ns hold time
+      i2c_master_arch_sexttoen: false
+      i2c_master_arch_trise: 215
+      i2c_master_baud_rate: 100000
+    optional_signals: []
+    variant:
+      specification: SDA=0, SCL=1
+      required_signals:
+      - name: SERCOM0/PAD/0
+        pad: PA08
+        label: SDA
+      - name: SERCOM0/PAD/1
+        pad: PA09
+        label: SCL
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 1
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 0
+          slow_gclk_selection: Generic clock generator 1
   TARGET_IO:
     user_label: TARGET_IO
-    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Sync
+    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::SERCOM4::driver_config_definition::UART::HAL:Driver:USART.Async
     functionality: USART
-    api: HAL:Driver:USART_Sync
+    api: HAL:Driver:USART_Async
     configuration:
-      usart_advanced: false
+      usart_advanced: true
       usart_arch_clock_mode: USART with internal clock
       usart_arch_cloden: false
       usart_arch_dbgstop: Keep running
@@ -703,6 +801,24 @@ drivers:
         configuration:
           can_gclk_selection: Generic clock generator 0
 pads:
+  PA08:
+    name: PA08
+    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA08
+    mode: I2C
+    user_label: PA08
+    configuration: null
+  PA09:
+    name: PA09
+    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA09
+    mode: I2C
+    user_label: PA09
+    configuration: null
+  PA10:
+    name: PA10
+    definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PA10
+    mode: Analog
+    user_label: PA10
+    configuration: null
   PB10:
     name: PB10
     definition: Atmel:SAMC21_Drivers:0.0.1::SAMC21J18A-AN::pad::PB10

bsp/microchip/samc21/bsp/atmel_start_pins.h

@@ -22,6 +22,9 @@
 #define GPIO_PIN_FUNCTION_H 7
 #define GPIO_PIN_FUNCTION_I 8
 
+#define PA08 GPIO(GPIO_PORTA, 8)
+#define PA09 GPIO(GPIO_PORTA, 9)
+#define PA10 GPIO(GPIO_PORTA, 10)
 #define LED0 GPIO(GPIO_PORTA, 15)
 #define PA24 GPIO(GPIO_PORTA, 24)
 #define PA25 GPIO(GPIO_PORTA, 25)

bsp/microchip/samc21/bsp/config/hpl_adc_config.h

@@ -0,0 +1,317 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x1
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x1=>1/1.6 VDDANA
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>External reference A
+// <0x4=>DAC internal output
+// <0x5=>VDDANA
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x0
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x19=>Bandgap voltage
+// <0x1A=>1/4 scaled core supply
+// <0x1B=>1/4 scaled I/O supply
+// <0x1C=>DAC output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x18=>Internal ground
+// <0x19=>I/O ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x19
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 1
+#endif
+
+// <q> Slave enable
+// <i> Will enable master/slave operation and only available in slave instance
+// <id> adc_arch_slaveen
+#ifndef CONF_ADC_0_SLAVEEN
+#define CONF_ADC_0_SLAVEEN 0
+#endif
+
+// <o> Dual mode trigger selection
+// <0x0=>BOTH
+// <0x1=>INTERLEAVE
+// <i> These bits define the trigger mode. (DUALSEL)
+// <id> adc_arch_dualsel
+#ifndef CONF_ADC_0_DUALSEL
+#define CONF_ADC_0_DUALSEL 0x0
+#endif
+
+// <q> Rail-to-Rail operation
+// <i> This bit enable R2R operation (R2R)
+// <id> adc_arch_r2r
+#ifndef CONF_ADC_0_R2R
+#define CONF_ADC_0_R2R 0
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x0
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 0
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H

bsp/microchip/samc21/bsp/config/hpl_sercom_config.h

@@ -6,6 +6,141 @@
 
 #include <peripheral_clk_config.h>
 
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_0_I2CM_ENABLE
+#define CONF_SERCOM_0_I2CM_ENABLE 1
+#endif
+
+// <h> Basic
+
+// <o> I2C Bus clock speed (Hz) <1-400000>
+// <i> I2C Bus clock (SCL) speed measured in Hz
+// <id> i2c_master_baud_rate
+#ifndef CONF_SERCOM_0_I2CM_BAUD
+#define CONF_SERCOM_0_I2CM_BAUD 100000
+#endif
+
+// </h>
+
+// <e> Advanced
+// <id> i2c_master_advanced
+#ifndef CONF_SERCOM_0_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_0_I2CM_ADVANCED_CONFIG 1
+#endif
+
+// <o> TRise (ns) <0-300>
+// <i> Determined by the bus impedance, check electric characteristics in the datasheet
+// <i> Standard Fast Mode: typical 215ns, max 300ns
+// <i> Fast Mode +: typical 60ns, max 100ns
+// <i> High Speed Mode: typical 20ns, max 40ns
+// <id> i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215
+#endif
+
+// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
+// <i> This enables the master SCL low extend time-out
+// <id> i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_0_I2CM_MEXTTOEN
+#define CONF_SERCOM_0_I2CM_MEXTTOEN 1
+#endif
+
+// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
+// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// <id> i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_0_I2CM_SEXTTOEN
+#define CONF_SERCOM_0_I2CM_SEXTTOEN 0
+#endif
+
+// <q> SCL Low Time-Out (LOWTOUT)
+// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// <id> i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_0_I2CM_LOWTOUT
+#define CONF_SERCOM_0_I2CM_LOWTOUT 1
+#endif
+
+// <o> Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
+// <id> i2c_master_arch_inactout
+#ifndef CONF_SERCOM_0_I2CM_INACTOUT
+#define CONF_SERCOM_0_I2CM_INACTOUT 0x3
+#endif
+
+// <o> SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// <i> Defines the SDA hold time with respect to the negative edge of SCL
+// <id> i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_0_I2CM_SDAHOLD
+#define CONF_SERCOM_0_I2CM_SDAHOLD 0x2
+#endif
+
+// <q> Run in stand-by
+// <i> Determine if the module shall run in standby sleep mode
+// <id> i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_0_I2CM_RUNSTDBY
+#define CONF_SERCOM_0_I2CM_RUNSTDBY 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_0_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_0_I2CM_SPEED
+#define CONF_SERCOM_0_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_0_I2CM_TRISE < 215 || CONF_SERCOM_0_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_0_I2CM_TRISE
+#define CONF_SERCOM_0_I2CM_TRISE 215U
+#endif
+
+//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+//                  i2c_scl_freq
+// BAUD:    register value low  [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_0_I2CM_BAUD_BAUDLOW                                                                                \
+	(((CONF_GCLK_SERCOM0_CORE_FREQUENCY - (CONF_SERCOM_0_I2CM_BAUD * 10U)                                              \
+	   - (CONF_SERCOM_0_I2CM_TRISE * (CONF_SERCOM_0_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM0_CORE_FREQUENCY / 10000U)    \
+	      / 1000U))                                                                                                    \
+	      * 10U                                                                                                        \
+	  + 5U)                                                                                                            \
+	 / (CONF_SERCOM_0_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_0_I2CM_BAUD_RATE
+#if CONF_SERCOM_0_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_0_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_0_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_0_I2CM_BAUD_RATE                                                                                   \
+	((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
+	     ? (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
+	     : (CONF_SERCOM_0_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
+#include <peripheral_clk_config.h>
+
 #ifndef CONF_SERCOM_4_USART_ENABLE
 #define CONF_SERCOM_4_USART_ENABLE 1
 #endif
@@ -69,7 +204,7 @@
 // <e> Advanced configuration
 // <id> usart_advanced
 #ifndef CONF_SERCOM_4_USART_ADVANCED_CONFIG
-#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 0
+#define CONF_SERCOM_4_USART_ADVANCED_CONFIG 1
 #endif
 
 // <q> Run in stand-by

bsp/microchip/samc21/bsp/config/peripheral_clk_config.h

@@ -4,6 +4,38 @@
 
 // <<< Use Configuration Wizard in Context Menu >>>
 
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC0_SRC
+#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC0_FREQUENCY
+ * \brief ADC0's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC0_FREQUENCY
+#define CONF_GCLK_ADC0_FREQUENCY 40001536
+#endif
+
 /**
  * \def CONF_CPU_FREQUENCY
  * \brief CPU's Clock frequency
@@ -31,6 +63,70 @@
 
 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
 
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM0_CORE_SRC
+#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM0_SLOW_SRC
+#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY
+ * \brief SERCOM0's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 40001536
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+ * \brief SERCOM0's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 4000000
+#endif
+
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
 // <i> Select the clock source for CORE.
 #ifndef CONF_GCLK_SERCOM4_CORE_SRC
 #define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val

bsp/microchip/samc21/bsp/driver_init.c

@@ -11,11 +11,43 @@
 #include <utils.h>
 #include <hal_init.h>
 
-struct can_async_descriptor CAN_0;
+#include <hpl_adc_base.h>
+
+/*! The buffer size for USART */
+#define TARGET_IO_BUFFER_SIZE 16
+
+struct usart_async_descriptor TARGET_IO;
+struct can_async_descriptor   CAN_0;
+
+static uint8_t TARGET_IO_buffer[TARGET_IO_BUFFER_SIZE];
+
+struct adc_sync_descriptor ADC_0;
 
 struct flash_descriptor FLASH_0;
 
-struct usart_sync_descriptor TARGET_IO;
+struct i2c_m_sync_desc I2C_0;
+
+void ADC_0_PORT_init(void)
+{
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(PA10, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(PA10, PINMUX_PA10B_ADC0_AIN10);
+}
+
+void ADC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBCMASK_ADC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_0_init(void)
+{
+	ADC_0_CLOCK_init();
+	ADC_0_PORT_init();
+	adc_sync_init(&ADC_0, ADC0, _adc_get_adc_sync());
+}
 
 void FLASH_0_CLOCK_init(void)
 {
@@ -29,25 +61,79 @@ void FLASH_0_init(void)
 	flash_init(&FLASH_0, NVMCTRL);
 }
 
-void TARGET_IO_PORT_init(void)
+void I2C_0_PORT_init(void)
 {
 
-	gpio_set_pin_function(PB10, PINMUX_PB10D_SERCOM4_PAD2);
+	gpio_set_pin_pull_mode(PA08,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PA08, PINMUX_PA08C_SERCOM0_PAD0);
+
+	gpio_set_pin_pull_mode(PA09,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PA09, PINMUX_PA09C_SERCOM0_PAD1);
+}
 
-	gpio_set_pin_function(PB11, PINMUX_PB11D_SERCOM4_PAD3);
+void I2C_0_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_mclk_set_APBCMASK_SERCOM0_bit(MCLK);
+}
+
+void I2C_0_init(void)
+{
+	I2C_0_CLOCK_init();
+	i2c_m_sync_init(&I2C_0, SERCOM0);
+	I2C_0_PORT_init();
 }
 
-void TARGET_IO_CLOCK_init(void)
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void TARGET_IO_CLOCK_init()
 {
+
 	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 	hri_mclk_set_APBCMASK_SERCOM4_bit(MCLK);
 }
 
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void TARGET_IO_PORT_init()
+{
+
+	gpio_set_pin_function(PB10, PINMUX_PB10D_SERCOM4_PAD2);
+
+	gpio_set_pin_function(PB11, PINMUX_PB11D_SERCOM4_PAD3);
+}
+
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
 void TARGET_IO_init(void)
 {
 	TARGET_IO_CLOCK_init();
-	usart_sync_init(&TARGET_IO, SERCOM4, (void *)NULL);
+	usart_async_init(&TARGET_IO, SERCOM4, TARGET_IO_buffer, TARGET_IO_BUFFER_SIZE, (void *)NULL);
 	TARGET_IO_PORT_init();
 }
 
@@ -89,8 +175,11 @@ void system_init(void)
 
 	gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF);
 
+	ADC_0_init();
+
 	FLASH_0_init();
 
+	I2C_0_init();
 	TARGET_IO_init();
 	CAN_0_init();
 }

bsp/microchip/samc21/bsp/driver_init.h

@@ -21,19 +21,33 @@ extern "C" {
 #include <hal_io.h>
 #include <hal_sleep.h>
 
+#include <hal_adc_sync.h>
+
 #include <hal_flash.h>
 
-#include <hal_usart_sync.h>
+#include <hal_i2c_m_sync.h>
+#include <hal_usart_async.h>
 #include <hal_can_async.h>
 
+extern struct adc_sync_descriptor ADC_0;
+
 extern struct flash_descriptor FLASH_0;
 
-extern struct usart_sync_descriptor TARGET_IO;
-extern struct can_async_descriptor  CAN_0;
+extern struct i2c_m_sync_desc        I2C_0;
+extern struct usart_async_descriptor TARGET_IO;
+extern struct can_async_descriptor   CAN_0;
+
+void ADC_0_PORT_init(void);
+void ADC_0_CLOCK_init(void);
+void ADC_0_init(void);
 
 void FLASH_0_init(void);
 void FLASH_0_CLOCK_init(void);
 
+void I2C_0_CLOCK_init(void);
+void I2C_0_init(void);
+void I2C_0_PORT_init(void);
+
 void TARGET_IO_PORT_init(void);
 void TARGET_IO_CLOCK_init(void);
 void TARGET_IO_init(void);

bsp/microchip/samc21/bsp/examples/driver_examples.c

@@ -10,6 +10,20 @@
 #include "driver_init.h"
 #include "utils.h"
 
+/**
+ * Example of using ADC_0 to generate waveform.
+ */
+void ADC_0_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_0, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+	}
+}
+
 static uint8_t src_data[128];
 static uint8_t chk_data[128];
 /**
@@ -70,16 +84,43 @@ void RWW_FLASH_0_example(void)
 	}
 }
 
+void I2C_0_example(void)
+{
+	struct io_descriptor *I2C_0_io;
+
+	i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
+	i2c_m_sync_enable(&I2C_0);
+	i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
+	io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
+}
+
 /**
  * Example of using TARGET_IO to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
  */
+
+static uint8_t example_TARGET_IO[12] = "Hello World!";
+
+static void tx_cb_TARGET_IO(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
 void TARGET_IO_example(void)
 {
 	struct io_descriptor *io;
-	usart_sync_get_io_descriptor(&TARGET_IO, &io);
-	usart_sync_enable(&TARGET_IO);
 
-	io_write(io, (uint8_t *)"Hello World!", 12);
+	usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, tx_cb_TARGET_IO);
+	/*usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&TARGET_IO, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&TARGET_IO, &io);
+	usart_async_enable(&TARGET_IO);
+
+	io_write(io, example_TARGET_IO, 12);
 }
 
 void CAN_0_tx_callback(struct can_async_descriptor *const descr)

bsp/microchip/samc21/bsp/examples/driver_examples.h

@@ -12,9 +12,13 @@
 extern "C" {
 #endif
 
+void ADC_0_example(void);
+
 void FLASH_0_example(void);
 void RWW_FLASH_0_example(void);
 
+void I2C_0_example(void);
+
 void TARGET_IO_example(void);
 
 void CAN_0_example(void);

bsp/microchip/samc21/bsp/hal/documentation/adc_sync.rst

@@ -0,0 +1,74 @@
+======================
+ADC Synchronous driver
+======================
+
+An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
+A reference signal with a known voltage level is quantified into equally
+sized chunks, each representing a digital value from 0 to the highest number
+possible with the bit resolution supported by the ADC. The input voltage
+measured by the ADC is compared against these chunks and the chunk with the
+closest voltage level defines the digital value that can be used to represent
+the analog input voltage level.
+
+Usually an ADC can operate in either differential or single-ended mode.
+In differential mode two signals (V+ and V-) are compared against each other
+and the resulting digital value represents the relative voltage level between
+V+ and V-. This means that if the input voltage level on V+ is lower than on
+V- the digital value is negative, which also means that in differential
+mode one bit is lost to the sign. In single-ended mode only V+ is compared
+against the reference voltage, and the resulting digital value can only be
+positive, but the full bit-range of the ADC can be used.
+
+Usually multiple resolutions are supported by the ADC, lower resolution can
+reduce the conversion time, but lose accuracy.
+
+Some ADCs has a gain stage on the input lines which can be used to increase the
+dynamic range. The default gain value is usually x1, which means that the
+conversion range is from 0V to the reference voltage.
+Applications can change the gain stage, to increase or reduce the conversion
+range.
+
+The window mode allows the conversion result to be compared to a set of
+predefined threshold values. Applications can use callback function to monitor
+if the conversion result exceeds predefined threshold value.
+
+Usually multiple reference voltages are supported by the ADC, both internal and
+external with difference voltage levels. The reference voltage have an impact
+on the accuracy, and should be selected to cover the full range of the analog
+input signal and never less than the expected maximum input voltage.
+
+There are two conversion modes supported by ADC, single shot and free running.
+In single shot mode the ADC only make one conversion when triggered by the
+application, in free running mode it continues to make conversion from it
+is triggered until it is stopped by the application. When window monitoring,
+the ADC should be set to free running mode.
+
+Features
+--------
+* Initialization and de-initialization
+* Support multiple Conversion Mode, Single or Free run
+* Start ADC Conversion
+* Read Conversion Result
+
+Applications
+------------
+* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
+* Measurement of external sensor. E.g., Temperature, humidity sensor value.
+* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
+
+Dependencies
+------------
+* ADC hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+

bsp/microchip/samc21/bsp/hal/documentation/i2c_master_sync.rst

@@ -0,0 +1,87 @@
+=============================
+I2C Master synchronous driver
+=============================
+
+I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
+for on-board low-speed bi-directional communication between controllers and
+peripherals. The master device is responsible for initiating and controlling
+all transfers on the I2C bus. Only one master device can be active on the I2C
+bus at the time, but the master role can be transferred between devices on the
+same I2C bus. I2C uses only two bidirectional open-drain lines, usually
+designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
+resistors.
+
+The stop condition is automatically controlled by the driver if the I/O write and
+read functions are used, but can be manually controlled by using the
+i2c_m_sync_transfer function.
+
+Often a master accesses different information in the slave by accessing
+different registers in the slave. This is done by first sending a message to
+the target slave containing the register address, followed by a repeated start
+condition (no stop condition between) ending with transferring register data.
+This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
+function, but limited to 8-bit register addresses.
+
+I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
+Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
+stick within the SCL clock frequency range supported by the selected mode.
+The requested SCL clock frequency is not validated by the
+i2c_m_sync_set_baudrate function against the selected I2C mode.
+
+Features
+--------
+
+	* I2C Master support
+	* Initialization and de-initialization
+	* Enabling and disabling
+	* Run-time bus speed configuration
+	* Write and read I2C messages
+	* Slave register access functions (limited to 8-bit address)
+	* Manual or automatic stop condition generation
+	* 10- and 7- bit addressing
+	* I2C Modes supported
+	       +----------------------+-------------------+
+	       |* Standard/Fast mode  | (SCL: 1 - 400kHz) |
+	       +----------------------+-------------------+
+	       |* Fastmode+           | (SCL: 1 - 1000kHz)|
+	       +----------------------+-------------------+
+	       |* Highspeed mode      | (SCL: 1 - 3400kHz)|
+	       +----------------------+-------------------+
+
+Applications
+------------
+
+* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
+* Data communication between micro controllers
+* Controlling displays
+
+Dependencies
+------------
+
+* I2C Master capable hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+General
+^^^^^^^
+
+	* System Managmenet Bus (SMBus) not supported.
+	* Power Management Bus (PMBus) not supported.
+
+Clock considerations
+^^^^^^^^^^^^^^^^^^^^
+
+The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
+

bsp/microchip/samc21/bsp/hal/documentation/usart_sync.rst → bsp/microchip/samc21/bsp/hal/documentation/usart_async.rst

@@ -1,9 +1,20 @@
-The USART Synchronous Driver
-============================
+The USART Asynchronous Driver
+=============================
 
 The universal synchronous and asynchronous receiver and transmitter
 (USART) is usually used to transfer data from one device to the other.
 
+The USART driver use a ring buffer to store received data. When the USART
+raise the data received interrupt, this data will be stored in the ring buffer
+at the next free location. When the ring buffer is full, the next reception
+will overwrite the oldest data stored in the ring buffer. There is one
+USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
+is called SERCOM0_USART_BUFFER_SIZE.
+
+On the other hand, when sending data over USART, the data is not copied to an
+internal buffer, but the data buffer supplied by the user is used. The callback
+will only be generated at the end of the buffer and not for each byte.
+
 User can set action for flow control pins by function usart_set_flow_control,
 if the flow control is enabled. All the available states are defined in union
 usart_flow_control_state.
@@ -24,6 +35,8 @@ Features
   * Data order
   * Flow control
 * Data transfer: transmission, reception
+* Notifications about transfer done or error case via callbacks
+* Status information with busy state and transfer count
 
 Applications
 ------------
@@ -34,7 +47,8 @@ between devices.
 Dependencies
 ------------
 
-USART capable hardware.
+USART capable hardware, with interrupt on each character is sent or
+received.
 
 Concurrency
 -----------

bsp/microchip/samc21/bsp/hal/include/hal_adc_sync.h

@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ADC_SYNC_H_INCLUDED
+#define _HAL_ADC_SYNC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_adc_sync
+ *
+ * @{
+ */
+
+/**
+ * \brief ADC descriptor
+ *
+ * The ADC descriptor forward declaration.
+ */
+struct adc_sync_descriptor;
+
+/**
+ * \brief ADC descriptor
+ */
+struct adc_sync_descriptor {
+	/** ADC device */
+	struct _adc_sync_device device;
+};
+
+/**
+ * \brief Initialize ADC
+ *
+ * This function initializes the given ADC descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr An ADC descriptor to initialize
+ * \param[in] hw     The pointer to hardware instance
+ * \param[in] func   The pointer to a set of functions pointers
+ *
+ * \return Initialization status.
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * This function deinitializes the given ADC descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] descr An ADC descriptor to deinitialize
+ *
+ * \return De-initialization status.
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
+
+/**
+ * \brief Enable ADC
+ *
+ * Use this function to set the ADC peripheral to enabled state.
+ *
+ * \param[in] descr    Pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * Use this function to set the ADC peripheral to disabled state.
+ *
+ * \param[in] descr   Pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Read data from ADC
+ *
+ * \param[in] descr    The pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ * \param[in] buf      A buffer to read data to
+ * \param[in] length   The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length);
+
+/**
+ * \brief Set ADC reference source
+ *
+ * This function sets ADC reference source.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] reference A reference source to set
+ *
+ * \return Status of the ADC reference source setting.
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
+
+/**
+ * \brief Set ADC resolution
+ *
+ * This function sets ADC resolution.
+ *
+ * \param[in] descr      The pointer to the ADC descriptor
+ * \param[in] resolution A resolution to set
+ *
+ * \return Status of the ADC resolution setting.
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * This function sets ADC positive and negative input sources.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ *
+ * \return Status of the ADC channels setting.
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set ADC conversion mode
+ *
+ * This function sets ADC conversion mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A conversion mode to set
+ *
+ * \return Status of the ADC conversion mode setting.
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set ADC differential mode
+ *
+ * This function sets ADC differential mode.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ *
+ * \return Status of the ADC differential mode setting.
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode);
+
+/**
+ * \brief Set ADC channel gain
+ *
+ * This function sets ADC channel gain.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ *
+ * \return Status of the ADC gain setting.
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                  const adc_gain_t gain);
+
+/**
+ * \brief Set ADC window mode
+ *
+ * This function sets ADC window mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A window mode to set
+ *
+ * \return Status of the ADC window mode setting.
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
+
+/**
+ * \brief Set ADC thresholds
+ *
+ * This function sets ADC positive and negative thresholds.
+ *
+ * \param[in] descr         The pointer to the ADC descriptor
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ *
+ * \return Status of the ADC thresholds setting.
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * This function retrieves ADC threshold state.
+ *
+ * \param[in] descr  The pointer to the ADC descriptor
+ * \param[out] state The threshold state
+ *
+ * \return The state of ADC thresholds state retrieving.
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
+                                     adc_threshold_status_t *const           state);
+
+/**
+ * \brief Check if conversion is complete
+ *
+ * This function checks if the ADC has finished the conversion.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return The status of ADC conversion completion checking.
+ * \retval 1 The conversion is complete
+ * \retval 0 The conversion is not complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t adc_sync_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <hpl_missing_features.h>
+
+#endif /* _HAL_ADC_SYNC_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/include/hal_i2c_m_sync.h

@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
+#define _HAL_I2C_M_SYNC_H_INCLUDED
+
+#include <hpl_i2c_m_sync.h>
+#include <hal_io.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_i2c_master_sync
+ *
+ * @{
+ */
+
+#define I2C_M_MAX_RETRY 1
+
+/**
+ * \brief I2C descriptor structure, embed i2c_device & i2c_interface
+ */
+struct i2c_m_sync_desc {
+	struct _i2c_m_sync_device device;
+	struct io_descriptor      io;
+	uint16_t                  slave_addr;
+};
+
+/**
+ * \brief Initialize synchronous I2C interface
+ *
+ * This function initializes the given I/O descriptor to be used as a
+ * synchronous I2C interface descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
+
+/**
+ * \brief Deinitialize I2C interface
+ *
+ * This function deinitializes the given I/O descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Uninitialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Set the slave device address
+ *
+ * This function sets the next transfer target slave I2C device address.
+ * It takes no effect to any already started access.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] addr The slave address to access
+ * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
+ *
+ * \return Masked slave address. The mask is a maximum 10-bit address, and 10th
+ *         bit is set if a 10-bit address is used
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
+
+/**
+ * \brief Set baudrate
+ *
+ * This function sets the I2C device to the specified baudrate.
+ * It only takes effect when the hardware is disabled.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] clkrate Unused parameter. Should always be 0
+ * \param[in] baudrate The baudrate value set to master
+ *
+ * \return Whether successfully set the baudrate
+ * \retval -1 The passed parameters were invalid or the device is already enabled
+ * \retval 0 The baudrate set is completed successfully
+ */
+int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Sync version of enable hardware
+ *
+ * This function enables the I2C device, and then waits for this enabling operation to be done
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Whether successfully enable the device
+ * \retval -1 The passed parameters were invalid or the device enable failed
+ * \retval 0 The hardware enabling is completed successfully
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Sync version of disable hardware
+ *
+ * This function disables the I2C device and then waits for this disabling operation to be done
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Whether successfully disable the device
+ * \retval -1 The passed parameters were invalid or the device disable failed
+ * \retval 0 The hardware disabling is completed successfully
+ */
+int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Sync version of write command to I2C slave
+ *
+ * This function will write the value to a specified register in the I2C slave device and
+ * then wait for this operation to be done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] buffer The buffer holding data to write to the I2C slave device
+ * \param[in] length The length (in bytes) to write to the I2C slave device
+ *
+ * \return Whether successfully write to the device
+ * \retval <0 The passed parameters were invalid or write fail
+ * \retval 0 Writing to register is completed successfully
+ */
+int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
+
+/**
+ * \brief Sync version of read register value from I2C slave
+ *
+ * This function will read a byte value from a specified register in the I2C slave device and
+ * then wait for this operation to be done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] buffer The buffer to hold the read data from the I2C slave device
+ * \param[in] length The length (in bytes) to read from the I2C slave device
+ *
+ * \return Whether successfully read from the device
+ * \retval <0 The passed parameters were invalid or read fail
+ * \retval 0 Reading from register is completed successfully
+ */
+int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
+
+/**
+ * \brief Sync version of transfer message to/from the I2C slave
+ *
+ * This function will transfer a message between the I2C slave and the master. This function will wait for the operation
+ * to be done.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] msg  An i2c_m_msg struct
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Sync version of send stop condition on the i2c bus
+ *
+ * This function will create a stop condition on the i2c bus to release the bus
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
+
+/**
+ * \brief Return I/O descriptor for this I2C instance
+ *
+ * This function will return a I/O instance for this I2C driver instance
+ *
+ * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
+ * \param[in] io_descriptor A pointer to an I/O descriptor pointer type
+ *
+ * \return Error code
+ * \retval 0 No error detected
+ * \retval <0 Error code
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t i2c_m_sync_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/microchip/samc21/bsp/hal/include/hal_usart_async.h

@@ -0,0 +1,339 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_USART_ASYNC_H_INCLUDED
+#define _HAL_USART_ASYNC_H_INCLUDED
+
+#include "hal_io.h"
+#include <hpl_usart_async.h>
+#include <utils_ringbuffer.h>
+
+/**
+ * \addtogroup doc_driver_hal_usart_async
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART descriptor
+ *
+ * The USART descriptor forward declaration.
+ */
+struct usart_async_descriptor;
+
+/**
+ * \brief USART callback type
+ */
+typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr);
+
+/**
+ * \brief USART callback types
+ */
+enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB };
+
+/**
+ * \brief USART callbacks
+ */
+struct usart_async_callbacks {
+	usart_cb_t tx_done;
+	usart_cb_t rx_done;
+	usart_cb_t error;
+};
+
+/** \brief USART status
+ *  Status descriptor holds the current status of transfer.
+ */
+struct usart_async_status {
+	/** Status flags */
+	uint32_t flags;
+	/** Number of characters transmitted */
+	uint16_t txcnt;
+	/** Number of characters receviced */
+	uint16_t rxcnt;
+};
+
+/**
+ * \brief Asynchronous USART descriptor structure
+ */
+struct usart_async_descriptor {
+	struct io_descriptor         io;
+	struct _usart_async_device   device;
+	struct usart_async_callbacks usart_cb;
+	uint32_t                     stat;
+
+	struct ringbuffer rx;
+	uint16_t          tx_por;
+	uint8_t *         tx_buffer;
+	uint16_t          tx_buffer_length;
+};
+
+/** USART write busy */
+#define USART_ASYNC_STATUS_BUSY 0x0001
+
+/**
+ * \brief Initialize USART interface
+ *
+ * This function initializes the given I/O descriptor to be used as USART
+ * interface descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr A USART descriptor which is used to communicate via the USART
+ * \param[in] hw The pointer to the hardware instance
+ * \param[in] rx_buffer An RX buffer
+ * \param[in] rx_buffer_length The length of the buffer above
+ * \param[in] func The pointer to a set of function pointers
+ *
+ * \return Initialization status.
+ * \retval -1 Passed parameters were invalid or the interface is already
+ * initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer,
+                         const uint16_t rx_buffer_length, void *const func);
+
+/**
+ * \brief Deinitialize USART interface
+ *
+ * This function deinitializes the given I/O descriptor.
+ * It checks if the given hardware is initialized and if the given hardware
+ * is permitted to be deinitialized.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return De-initialization status.
+ */
+int32_t usart_async_deinit(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Enable USART interface
+ *
+ * Enables the USART interface
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return Enabling status.
+ */
+int32_t usart_async_enable(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Disable USART interface
+ *
+ * Disables the USART interface
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return Disabling status.
+ */
+int32_t usart_async_disable(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Retrieve I/O descriptor
+ *
+ * This function retrieves the I/O descriptor of the given USART descriptor.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[out] io An I/O descriptor to retrieve
+ *
+ * \return The status of I/O descriptor retrieving.
+ */
+int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io);
+
+/**
+ * \brief Register USART callback
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] type Callback type
+ * \param[in] cb A callback function
+ *
+ * \return The status of callback assignment.
+ * \retval -1 Passed parameters were invalid or the interface is not initialized
+ * \retval 0 A callback is registered successfully
+ */
+int32_t usart_async_register_callback(struct usart_async_descriptor *const descr,
+                                      const enum usart_async_callback_type type, usart_cb_t cb);
+
+/**
+ * \brief Specify action for flow control pins
+ *
+ * This function sets action (or state) for flow control pins if
+ * the flow control is enabled.
+ * It sets state of flow control pins only if automatic support of
+ * the flow control is not supported by the hardware.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] state A state to set the flow control pins
+ *
+ * \return The status of flow control action setup.
+ */
+int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr,
+                                     const union usart_flow_control_state state);
+
+/**
+ * \brief Set USART baud rate
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] baud_rate A baud rate to set
+ *
+ * \return The status of baud rate setting.
+ */
+int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate);
+
+/**
+ * \brief Set USART data order
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] data_order A data order to set
+ *
+ * \return The status of data order setting.
+ */
+int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order);
+
+/**
+ * \brief Set USART mode
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] mode A mode to set
+ *
+ * \return The status of mode setting.
+ */
+int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode);
+
+/**
+ * \brief Set USART parity
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] parity A parity to set
+ *
+ * \return The status of parity setting.
+ */
+int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity);
+
+/**
+ * \brief Set USART stop bits
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] stop_bits Stop bits to set
+ *
+ * \return The status of stop bits setting.
+ */
+int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits);
+
+/**
+ * \brief Set USART character size
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] size A character size to set
+ *
+ * \return The status of character size setting.
+ */
+int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr,
+                                       const enum usart_character_size      size);
+
+/**
+ * \brief Retrieve the state of flow control pins
+ *
+ * This function retrieves the flow control pins
+ * if the flow control is enabled.
+ *
+ * The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
+ * if the flow control is done by the hardware
+ * and the pins state cannot be read out.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[out] state The state of flow control pins
+ *
+ * \return The status of flow control state reading.
+ */
+int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr,
+                                        union usart_flow_control_state *const      state);
+
+/**
+ * \brief Check if the USART transmitter is empty
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return The status of USART TX empty checking.
+ * \retval 0 The USART transmitter is not empty
+ * \retval 1 The USART transmitter is empty
+ */
+int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Check if the USART receiver is not empty
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return The status of the USART RX empty checking.
+ * \retval 1 The USART receiver is not empty
+ * \retval 0 The USART receiver is empty
+ */
+int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Retrieve the current interface status
+ *
+ * \param[in]  descr A USART descriptor which is used to communicate via USART
+ * \param[out] status The state of USART
+ *
+ * \return The status of USART status retrieving.
+ */
+int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status);
+
+/**
+ * \brief flush USART ringbuf
+ *
+ * This function flush USART RX ringbuf.
+ *
+ * \param[in] descr The pointer to USART descriptor
+ *
+ * \return ERR_NONE
+ */
+int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t usart_async_get_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HAL_USART_ASYNC_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/include/hal_usart_sync.h

@@ -1,247 +0,0 @@
-/**
- * \file
- *
- * \brief USART related functionality declaration.
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _HAL_SYNC_USART_H_INCLUDED
-#define _HAL_SYNC_USART_H_INCLUDED
-
-#include "hal_io.h"
-#include <hpl_usart_sync.h>
-
-/**
- * \addtogroup doc_driver_hal_usart_sync
- *
- * @{
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief Synchronous USART descriptor
- */
-struct usart_sync_descriptor {
-	struct io_descriptor      io;
-	struct _usart_sync_device device;
-};
-
-/**
- * \brief Initialize USART interface
- *
- * This function initializes the given I/O descriptor to be used
- * as USART interface descriptor.
- * It checks if the given hardware is not initialized and
- * if the given hardware is permitted to be initialized.
- *
- * \param[out] descr A USART descriptor which is used to communicate via USART
- * \param[in] hw The pointer to hardware instance
- * \param[in] func The pointer to as set of functions pointers
- *
- * \return Initialization status.
- */
-int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
-
-/**
- * \brief Deinitialize USART interface
- *
- * This function deinitializes the given I/O descriptor.
- * It checks if the given hardware is initialized and
- * if the given hardware is permitted to be deinitialized.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return De-initialization status.
- */
-int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Enable USART interface
- *
- * Enables the USART interface
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return Enabling status.
- */
-int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Disable USART interface
- *
- * Disables the USART interface
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return Disabling status.
- */
-int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Retrieve I/O descriptor
- *
- * This function retrieves the I/O descriptor of the given USART descriptor.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[out] io An I/O descriptor to retrieve
- *
- * \return The status of the I/O descriptor retrieving.
- */
-int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
-
-/**
- * \brief Specify action for flow control pins
- *
- * This function sets the action (or state) for the flow control pins
- * if the flow control is enabled.
- * It sets the state of flow control pins only if the automatic support of
- * the flow control is not supported by the hardware.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] state A state to set the flow control pins
- *
- * \return The status of flow control action setup.
- */
-int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const  descr,
-                                    const union usart_flow_control_state state);
-
-/**
- * \brief Set USART baud rate
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] baud_rate A baud rate to set
- *
- * \return The status of baud rate setting.
- */
-int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
-
-/**
- * \brief Set USART data order
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] data_order A data order to set
- *
- * \return The status of data order setting.
- */
-int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
-
-/**
- * \brief Set USART mode
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] mode A mode to set
- *
- * \return The status of mode setting.
- */
-int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
-
-/**
- * \brief Set USART parity
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] parity A parity to set
- *
- * \return The status of parity setting.
- */
-int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
-
-/**
- * \brief Set USART stop bits
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] stop_bits Stop bits to set
- *
- * \return The status of stop bits setting.
- */
-int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
-
-/**
- * \brief Set USART character size
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] size A character size to set
- *
- * \return The status of character size setting.
- */
-int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
-
-/**
- * \brief Retrieve the state of flow control pins
- *
- * This function retrieves the of flow control pins
- * if the flow control is enabled.
- * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
- * if the flow control is done by the hardware
- * and the pins state cannot be read out.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[out] state The state of flow control pins
- *
- * \return The status of flow control state reading.
- */
-int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
-                                       union usart_flow_control_state *const     state);
-
-/**
- * \brief Check if the USART transmitter is empty
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return The status of USART TX empty checking.
- * \retval 0 The USART transmitter is not empty
- * \retval 1 The USART transmitter is empty
- */
-int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Check if the USART receiver is not empty
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return The status of USART RX empty checking.
- * \retval 1 The USART receiver is not empty
- * \retval 0 The USART receiver is empty
- */
-int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Retrieve the current driver version
- *
- * \return Current driver version.
- */
-uint32_t usart_sync_get_version(void);
-
-#ifdef __cplusplus
-}
-#endif
-/**@}*/
-#endif /* _HAL_SYNC_USART_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/include/hpl_adc_async.h

@@ -0,0 +1,264 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_ASYNC_H_INCLUDED
+#define _HPL_ADC_ASYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_async_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "hpl_adc_sync.h"
+#include "hpl_irq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC device structure
+ *
+ * The ADC device structure forward declaration.
+ */
+struct _adc_async_device;
+
+/**
+ * \brief ADC callback types
+ */
+enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
+
+/**
+ * \brief ADC interrupt callbacks
+ */
+struct _adc_async_callbacks {
+	void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
+	void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
+};
+
+/**
+ * \brief ADC channel interrupt callbacks
+ */
+struct _adc_async_ch_callbacks {
+	void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
+};
+
+/**
+ * \brief ADC descriptor device structure
+ */
+struct _adc_async_device {
+	struct _adc_async_callbacks    adc_async_cb;
+	struct _adc_async_ch_callbacks adc_async_ch_cb;
+	struct _irq_descriptor         irq;
+	void *                         hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw     The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_async_deinit(struct _adc_async_device *const device);
+
+/**
+ * \brief Enable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_async_convert(struct _adc_async_device *const device);
+
+/**
+ * \brief Retrieve the conversion result
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ *
+ * The result value
+ */
+uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
+                           const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
+                                              const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] gain     A gain to set
+ */
+void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode   A mode to set
+ */
+void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set lower threshold
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold  A lower threshold to set
+ * \param[in] up_threshold   An upper thresholds to set
+ */
+void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
+                               const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
+
+/**
+ * \brief Enable/disable ADC channel interrupt
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] type     The type of interrupt to disable/enable if applicable
+ * \param[in] state    Enable or disable
+ */
+void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
+                              const enum _adc_async_callback_type type, const bool state);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_ASYNC_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/include/hpl_adc_dma.h

@@ -0,0 +1,243 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_DMA_H_INCLUDED
+#define _HPL_ADC_DMA_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_dma_adc_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include <hpl_adc_sync.h>
+#include <hpl_irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC device structure
+ *
+ * The ADC device structure forward declaration.
+ */
+struct _adc_dma_device;
+
+/**
+ * \brief ADC callback types
+ */
+enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
+
+/**
+ * \brief ADC interrupt callbacks
+ */
+struct _adc_dma_callbacks {
+	void (*complete)(struct _adc_dma_device *device, const uint16_t data);
+	void (*error)(struct _adc_dma_device *device);
+};
+
+/**
+ * \brief ADC descriptor device structure
+ */
+struct _adc_dma_device {
+	struct _adc_dma_callbacks adc_dma_cb;
+	struct _irq_descriptor    irq;
+	void *                    hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_dma_deinit(struct _adc_dma_device *const device);
+
+/**
+ * \brief Enable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC peripheral
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
+
+/**
+ * \brief Return address of ADC DMA source
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return ADC DMA source address
+ */
+uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device   The pointer to ADC device instance
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_dma_convert(struct _adc_dma_device *const device);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
+                         const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
+                                            const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ */
+void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A mode to set
+ */
+void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set thresholds
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ */
+void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
+                             const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
+
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_DMA_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/include/hpl_adc_sync.h

@@ -0,0 +1,271 @@
+/**
+ * \file
+ *
+ * \brief ADC related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HPL_ADC_SYNC_H_INCLUDED
+#define _HPL_ADC_SYNC_H_INCLUDED
+
+/**
+ * \addtogroup HPL ADC
+ *
+ * \section hpl_adc_sync_rev Revision History
+ * - v1.0.0 Initial Release
+ *
+ *@{
+ */
+
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief ADC reference source
+ */
+typedef uint8_t adc_reference_t;
+
+/**
+ * \brief ADC resolution
+ */
+typedef uint8_t adc_resolution_t;
+
+/**
+ * \brief ADC positive input for channel
+ */
+typedef uint8_t adc_pos_input_t;
+
+/**
+ * \brief ADC negative input for channel
+ */
+typedef uint8_t adc_neg_input_t;
+
+/**
+ * \brief ADC threshold
+ */
+typedef uint16_t adc_threshold_t;
+
+/**
+ * \brief ADC gain
+ */
+typedef uint8_t adc_gain_t;
+
+/**
+ * \brief ADC conversion mode
+ */
+enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
+
+/**
+ * \brief ADC differential mode
+ */
+enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
+
+/**
+ * \brief ADC window mode
+ */
+typedef uint8_t adc_window_mode_t;
+
+/**
+ * \brief ADC threshold status
+ */
+typedef bool adc_threshold_status_t;
+
+/**
+ * \brief ADC sync descriptor device structure
+ */
+struct _adc_sync_device {
+	void *hw;
+};
+
+/**
+ * \name HPL functions
+ */
+//@{
+/**
+ * \brief Initialize synchronous ADC
+ *
+ * This function does low level ADC configuration.
+ *
+ * param[in] device The pointer to ADC device instance
+ * param[in] hw     The pointer to hardware instance
+ *
+ * \return Initialization status
+ */
+int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_sync_deinit(struct _adc_sync_device *const device);
+
+/**
+ * \brief Enable ADC
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ */
+void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Retrieve ADC conversion data size
+ *
+ * \param[in] device The pointer to ADC device instance
+ *
+ * \return The data size in bytes
+ */
+uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
+
+/**
+ * \brief Check if conversion is done
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ *
+ * \return The status of conversion
+ * \retval true The conversion is done
+ * \retval false The conversion is not done
+ */
+bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Make conversion
+ *
+ * \param[in] device The pointer to ADC device instance
+ */
+void _adc_sync_convert(struct _adc_sync_device *const device);
+
+/**
+ * \brief Retrieve the conversion result
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ *
+ * \return The result value of channel
+ */
+uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
+
+/**
+ * \brief Set reference source
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] reference A reference source to set
+ */
+void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
+
+/**
+ * \brief Set resolution
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] resolution A resolution to set
+ */
+void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * \param[in] device    The pointer to ADC device instance
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ */
+void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
+                          const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set conversion mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode A conversion mode to set
+ */
+void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set differential mode
+ *
+ * \param[in] device  The pointer to ADC device instance
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ */
+void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
+                                             const enum adc_differential_mode mode);
+
+/**
+ * \brief Set gain
+ *
+ * \param[in] device   The pointer to ADC device instance
+ * \param[in] channel  Channel number
+ * \param[in] gain     A gain to set
+ */
+void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
+
+/**
+ * \brief Set window mode
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[in] mode   A mode to set
+ */
+void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
+
+/**
+ * \brief Set threshold
+ *
+ * \param[in] device        The pointer to ADC device instance
+ * \param[in] low_threshold  A lower threshold to set
+ * \param[in] up_threshold   An upper thresholds to set
+ */
+void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
+                              const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * \param[in] device The pointer to ADC device instance
+ * \param[out] state The threshold state
+ */
+void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
+//@}
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HPL_ADC_SYNC_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/src/hal_adc_sync.c

@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+/**
+ * \brief Indicates HAL being compiled. Must be defined before including.
+ */
+#define _COMPILING_HAL
+
+#include "hal_adc_sync.h"
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Maximum amount of ADC interface instances
+ */
+#define MAX_ADC_AMOUNT ADC_INST_NUM
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
+{
+	ASSERT(descr && hw);
+
+	return _adc_sync_init(&descr->device, hw);
+}
+
+/**
+ * \brief Deinitialize ADC
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
+{
+	ASSERT(descr);
+	_adc_sync_deinit(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable ADC
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_enable_channel(&descr->device, channel);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable ADC
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_disable_channel(&descr->device, channel);
+	return ERR_NONE;
+}
+
+/*
+ * \brief Read data from ADC
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length)
+{
+	uint8_t  data_size;
+	uint16_t offset = 0;
+
+	ASSERT(descr && buffer && length);
+	data_size = _adc_sync_get_data_size(&descr->device);
+	ASSERT(!(length % data_size));
+
+	do {
+		uint16_t result;
+		_adc_sync_convert(&descr->device);
+
+		while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
+			;
+
+		result         = _adc_sync_read_channel_data(&descr->device, channel);
+		buffer[offset] = result;
+		if (1 < data_size) {
+			buffer[offset + 1] = result >> 8;
+		}
+		offset += data_size;
+	} while (offset < length);
+
+	return offset;
+}
+
+/**
+ * \brief Set ADC reference source
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
+{
+	ASSERT(descr);
+	_adc_sync_set_reference_source(&descr->device, reference);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC resolution
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
+{
+	ASSERT(descr);
+	_adc_sync_set_resolution(&descr->device, resolution);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC input source of a channel
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	ASSERT(descr);
+	_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC thresholds
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold)
+{
+	ASSERT(descr);
+	_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC gain
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
+{
+	ASSERT(descr);
+	_adc_sync_set_channel_gain(&descr->device, channel, gain);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC conversion mode
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_conversion_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC differential mode
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set ADC window mode
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
+{
+	ASSERT(descr);
+	_adc_sync_set_window_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
+{
+	ASSERT(descr && state);
+	_adc_sync_get_threshold_state(&descr->device, state);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check if conversion is complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
+{
+	ASSERT(descr);
+	return _adc_sync_is_channel_conversion_done(&descr->device, channel);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t adc_sync_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+//@}

bsp/microchip/samc21/bsp/hal/src/hal_i2c_m_sync.c

@@ -0,0 +1,258 @@
+/**
+ * \file
+ *
+ * \brief I/O I2C related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include <hal_i2c_m_sync.h>
+#include <utils.h>
+#include <utils_assert.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+/**
+ * \brief Sync version of I2C I/O read
+ */
+static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n)
+{
+	struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
+	struct _i2c_m_msg       msg;
+	int32_t                 ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = n;
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+	msg.buffer = buf;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret) {
+		return ret;
+	}
+
+	return n;
+}
+
+/**
+ * \brief Sync version of I2C I/O write
+ */
+static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n)
+{
+	struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
+	struct _i2c_m_msg       msg;
+	int32_t                 ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = n;
+	msg.flags  = I2C_M_STOP;
+	msg.buffer = (uint8_t *)buf;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret) {
+		return ret;
+	}
+
+	return n;
+}
+
+/**
+ * \brief Sync version of i2c initialize
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw)
+{
+	int32_t init_status;
+	ASSERT(i2c);
+
+	init_status = _i2c_m_sync_init(&i2c->device, hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	/* Init I/O */
+	i2c->io.read  = i2c_m_sync_read;
+	i2c->io.write = i2c_m_sync_write;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief deinitialize
+ */
+int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c)
+{
+	int32_t status;
+	ASSERT(i2c);
+
+	status = _i2c_m_sync_deinit(&i2c->device);
+	if (status) {
+		return status;
+	}
+
+	i2c->io.read  = NULL;
+	i2c->io.write = NULL;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Sync version of i2c enable
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c)
+{
+	return _i2c_m_sync_enable(&i2c->device);
+}
+
+/**
+ * \brief Sync version of i2c disable
+ */
+int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c)
+{
+	return _i2c_m_sync_disable(&i2c->device);
+}
+
+/**
+ * \brief Sync version of i2c set slave address
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len)
+{
+	return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
+}
+
+/**
+ * \brief Sync version of i2c set baudrate
+ */
+int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate)
+{
+	return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate);
+}
+
+/**
+ * \brief Sync version of i2c write command
+ */
+int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
+{
+	struct _i2c_m_msg msg;
+	int32_t           ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = 1;
+	msg.flags  = 0;
+	msg.buffer = &reg;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	msg.flags  = I2C_M_STOP;
+	msg.buffer = buffer;
+	msg.len    = length;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Sync version of i2c read command
+ */
+int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
+{
+	struct _i2c_m_msg msg;
+	int32_t           ret;
+
+	msg.addr   = i2c->slave_addr;
+	msg.len    = 1;
+	msg.flags  = 0;
+	msg.buffer = &reg;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	msg.flags  = I2C_M_STOP | I2C_M_RD;
+	msg.buffer = buffer;
+	msg.len    = length;
+
+	ret = _i2c_m_sync_transfer(&i2c->device, &msg);
+
+	if (ret != 0) {
+		/* error occurred */
+		return ret;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Sync version of i2c transfer command
+ */
+int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg)
+{
+	return _i2c_m_sync_transfer(&i2c->device, msg);
+}
+
+/**
+ * \brief Sync version of i2c send stop condition command
+ */
+int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c)
+{
+	return _i2c_m_sync_send_stop(&i2c->device);
+}
+
+/**
+ * \brief Retrieve I/O descriptor
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io)
+{
+	*io = &i2c->io;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t i2c_m_sync_get_version(void)
+{
+	return DRIVER_VERSION;
+}

bsp/microchip/samc21/bsp/hal/src/hal_usart_async.c

@@ -0,0 +1,420 @@
+/**
+ * \file
+ *
+ * \brief I/O USART related functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include "hal_usart_async.h"
+#include <utils_assert.h>
+#include <hal_atomic.h>
+#include <utils.h>
+
+/**
+ * \brief Driver version
+ */
+#define DRIVER_VERSION 0x00000001u
+
+static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
+static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
+static void    usart_process_byte_sent(struct _usart_async_device *device);
+static void    usart_transmission_complete(struct _usart_async_device *device);
+static void    usart_error(struct _usart_async_device *device);
+static void    usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data);
+
+/**
+ * \brief Initialize usart interface
+ */
+int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *rx_buffer,
+                         uint16_t rx_buffer_length, void *const func)
+{
+	int32_t init_status;
+	ASSERT(descr && hw && rx_buffer && rx_buffer_length);
+
+	if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) {
+		return ERR_INVALID_ARG;
+	}
+	init_status = _usart_async_init(&descr->device, hw);
+	if (init_status) {
+		return init_status;
+	}
+
+	descr->io.read  = usart_async_read;
+	descr->io.write = usart_async_write;
+
+	descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent;
+	descr->device.usart_cb.rx_done_cb   = usart_fill_rx_buffer;
+	descr->device.usart_cb.tx_done_cb   = usart_transmission_complete;
+	descr->device.usart_cb.error_cb     = usart_error;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Deinitialize usart interface
+ */
+int32_t usart_async_deinit(struct usart_async_descriptor *const descr)
+{
+	ASSERT(descr);
+	_usart_async_deinit(&descr->device);
+	descr->io.read  = NULL;
+	descr->io.write = NULL;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Enable usart interface
+ */
+int32_t usart_async_enable(struct usart_async_descriptor *const descr)
+{
+	ASSERT(descr);
+	_usart_async_enable(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Disable usart interface
+ */
+int32_t usart_async_disable(struct usart_async_descriptor *const descr)
+{
+	ASSERT(descr);
+	_usart_async_disable(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve I/O descriptor
+ */
+int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io)
+{
+	ASSERT(descr && io);
+
+	*io = &descr->io;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Register usart callback
+ */
+int32_t usart_async_register_callback(struct usart_async_descriptor *const descr,
+                                      const enum usart_async_callback_type type, usart_cb_t cb)
+{
+	ASSERT(descr);
+
+	switch (type) {
+	case USART_ASYNC_RXC_CB:
+		descr->usart_cb.rx_done = cb;
+		_usart_async_set_irq_state(&descr->device, USART_ASYNC_RX_DONE, NULL != cb);
+		break;
+	case USART_ASYNC_TXC_CB:
+		descr->usart_cb.tx_done = cb;
+		_usart_async_set_irq_state(&descr->device, USART_ASYNC_TX_DONE, NULL != cb);
+		break;
+	case USART_ASYNC_ERROR_CB:
+		descr->usart_cb.error = cb;
+		_usart_async_set_irq_state(&descr->device, USART_ASYNC_ERROR, NULL != cb);
+		break;
+	default:
+		return ERR_INVALID_ARG;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Specify action for flow control pins
+ */
+int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr,
+                                     const union usart_flow_control_state state)
+{
+	ASSERT(descr);
+	_usart_async_set_flow_control_state(&descr->device, state);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set usart baud rate
+ */
+int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate)
+{
+	ASSERT(descr);
+	_usart_async_set_baud_rate(&descr->device, baud_rate);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set usart data order
+ */
+int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order)
+{
+	ASSERT(descr);
+	_usart_async_set_data_order(&descr->device, data_order);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set usart mode
+ */
+int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode)
+{
+	ASSERT(descr);
+	_usart_async_set_mode(&descr->device, mode);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set usart parity
+ */
+int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity)
+{
+	ASSERT(descr);
+	_usart_async_set_parity(&descr->device, parity);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set usart stop bits
+ */
+int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits)
+{
+	ASSERT(descr);
+	_usart_async_set_stop_bits(&descr->device, stop_bits);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set usart character size
+ */
+int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, const enum usart_character_size size)
+{
+	ASSERT(descr);
+	_usart_async_set_character_size(&descr->device, size);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Retrieve the state of flow control pins
+ */
+int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr,
+                                        union usart_flow_control_state *const      state)
+{
+	ASSERT(descr && state);
+	*state = _usart_async_get_flow_control_state(&descr->device);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Check if the usart transmitter is empty
+ */
+int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr)
+{
+	ASSERT(descr);
+	return _usart_async_is_byte_sent(&descr->device);
+}
+
+/**
+ * \brief Check if the usart receiver is not empty
+ */
+int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr)
+{
+	ASSERT(descr);
+
+	return ringbuffer_num(&descr->rx) > 0;
+}
+
+/**
+ * \brief Retrieve the current interface status
+ */
+int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status)
+{
+	ASSERT(descr);
+
+	volatile uint32_t *tmp_stat  = &(descr->stat);
+	volatile uint16_t *tmp_txcnt = &(descr->tx_por);
+
+	if (status) {
+		status->flags = *tmp_stat;
+		status->txcnt = *tmp_txcnt;
+		status->rxcnt = ringbuffer_num(&descr->rx);
+	}
+	if (*tmp_stat & USART_ASYNC_STATUS_BUSY) {
+		return ERR_BUSY;
+	}
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief flush usart rx ringbuf
+ */
+int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr)
+{
+	ASSERT(descr);
+
+	return ringbuffer_flush(&descr->rx);
+}
+
+/**
+ * \brief Retrieve the current driver version
+ */
+uint32_t usart_async_get_version(void)
+{
+	return DRIVER_VERSION;
+}
+
+/*
+ * \internal Write the given data to usart interface
+ *
+ * \param[in] descr The pointer to an io descriptor
+ * \param[in] buf Data to write to usart
+ * \param[in] length The number of bytes to write
+ *
+ * \return The number of bytes written.
+ */
+static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
+{
+	struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io);
+
+	ASSERT(descr && buf && length);
+
+	if (descr->tx_por != descr->tx_buffer_length) {
+		return ERR_NO_RESOURCE;
+	}
+	descr->tx_buffer        = (uint8_t *)buf;
+	descr->tx_buffer_length = length;
+	descr->tx_por           = 0;
+	descr->stat             = USART_ASYNC_STATUS_BUSY;
+	_usart_async_enable_byte_sent_irq(&descr->device);
+
+	return (int32_t)length;
+}
+
+/*
+ * \internal Read data from usart interface
+ *
+ * \param[in] descr The pointer to an io descriptor
+ * \param[in] buf A buffer to read data to
+ * \param[in] length The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
+{
+	uint16_t                       was_read = 0;
+	uint32_t                       num;
+	struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io);
+
+	ASSERT(descr && buf && length);
+
+	CRITICAL_SECTION_ENTER()
+	num = ringbuffer_num(&descr->rx);
+	CRITICAL_SECTION_LEAVE()
+
+	while ((was_read < num) && (was_read < length)) {
+		ringbuffer_get(&descr->rx, &buf[was_read++]);
+	}
+
+	return (int32_t)was_read;
+}
+
+/**
+ * \brief Process "byte is sent" interrupt
+ *
+ * \param[in] device The pointer to device structure
+ */
+static void usart_process_byte_sent(struct _usart_async_device *device)
+{
+	struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device);
+	if (descr->tx_por != descr->tx_buffer_length) {
+		_usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]);
+		_usart_async_enable_byte_sent_irq(&descr->device);
+	} else {
+		_usart_async_enable_tx_done_irq(&descr->device);
+	}
+}
+
+/**
+ * \brief Process completion of data sending
+ *
+ * \param[in] device The pointer to device structure
+ */
+static void usart_transmission_complete(struct _usart_async_device *device)
+{
+	struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device);
+
+	descr->stat = 0;
+	if (descr->usart_cb.tx_done) {
+		descr->usart_cb.tx_done(descr);
+	}
+}
+
+/**
+ * \brief Process byte reception
+ *
+ * \param[in] device The pointer to device structure
+ * \param[in] data Data read
+ */
+static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data)
+{
+	struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device);
+
+	ringbuffer_put(&descr->rx, data);
+
+	if (descr->usart_cb.rx_done) {
+		descr->usart_cb.rx_done(descr);
+	}
+}
+
+/**
+ * \brief Process error interrupt
+ *
+ * \param[in] device The pointer to device structure
+ */
+static void usart_error(struct _usart_async_device *device)
+{
+	struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device);
+
+	descr->stat = 0;
+	if (descr->usart_cb.error) {
+		descr->usart_cb.error(descr);
+	}
+}
+
+//@}

bsp/microchip/samc21/bsp/hal/src/hal_usart_sync.c

@@ -1,276 +0,0 @@
-/**
- * \file
- *
- * \brief I/O USART related functionality implementation.
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#include "hal_usart_sync.h"
-#include <utils_assert.h>
-#include <utils.h>
-
-/**
- * \brief Driver version
- */
-#define DRIVER_VERSION 0x00000001u
-
-static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
-static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
-
-/**
- * \brief Initialize usart interface
- */
-int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func)
-{
-	int32_t init_status;
-	ASSERT(descr && hw);
-	init_status = _usart_sync_init(&descr->device, hw);
-	if (init_status) {
-		return init_status;
-	}
-
-	descr->io.read  = usart_sync_read;
-	descr->io.write = usart_sync_write;
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Uninitialize usart interface
- */
-int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr)
-{
-	ASSERT(descr);
-	_usart_sync_deinit(&descr->device);
-
-	descr->io.read  = NULL;
-	descr->io.write = NULL;
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Enable usart interface
- */
-int32_t usart_sync_enable(struct usart_sync_descriptor *const descr)
-{
-	ASSERT(descr);
-	_usart_sync_enable(&descr->device);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Disable usart interface
- */
-int32_t usart_sync_disable(struct usart_sync_descriptor *const descr)
-{
-	ASSERT(descr);
-	_usart_sync_disable(&descr->device);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Retrieve I/O descriptor
- */
-int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io)
-{
-	ASSERT(descr && io);
-
-	*io = &descr->io;
-	return ERR_NONE;
-}
-
-/**
- * \brief Specify action for flow control pins
- */
-int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const  descr,
-                                    const union usart_flow_control_state state)
-{
-	ASSERT(descr);
-	_usart_sync_set_flow_control_state(&descr->device, state);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Set usart baud rate
- */
-int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate)
-{
-	ASSERT(descr);
-	_usart_sync_set_baud_rate(&descr->device, baud_rate);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Set usart data order
- */
-int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order)
-{
-	ASSERT(descr);
-	_usart_sync_set_data_order(&descr->device, data_order);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Set usart mode
- */
-int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode)
-{
-	ASSERT(descr);
-	_usart_sync_set_mode(&descr->device, mode);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Set usart parity
- */
-int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity)
-{
-	ASSERT(descr);
-	_usart_sync_set_parity(&descr->device, parity);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Set usart stop bits
- */
-int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits)
-{
-	ASSERT(descr);
-	_usart_sync_set_stop_bits(&descr->device, stop_bits);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Set usart character size
- */
-int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size)
-{
-	ASSERT(descr);
-	_usart_sync_set_character_size(&descr->device, size);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Retrieve the state of flow control pins
- */
-int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
-                                       union usart_flow_control_state *const     state)
-{
-	ASSERT(descr && state);
-	*state = _usart_sync_get_flow_control_state(&descr->device);
-
-	return ERR_NONE;
-}
-
-/**
- * \brief Check if the usart transmitter is empty
- */
-int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr)
-{
-	ASSERT(descr);
-	return _usart_sync_is_ready_to_send(&descr->device);
-}
-
-/**
- * \brief Check if the usart receiver is not empty
- */
-int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr)
-{
-	ASSERT(descr);
-	return _usart_sync_is_byte_received(&descr->device);
-}
-
-/**
- * \brief Retrieve the current driver version
- */
-uint32_t usart_sync_get_version(void)
-{
-	return DRIVER_VERSION;
-}
-
-/*
- * \internal Write the given data to usart interface
- *
- * \param[in] descr The pointer to an io descriptor
- * \param[in] buf Data to write to usart
- * \param[in] length The number of bytes to write
- *
- * \return The number of bytes written.
- */
-static int32_t usart_sync_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
-{
-	uint32_t                      offset = 0;
-	struct usart_sync_descriptor *descr  = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
-
-	ASSERT(io_descr && buf && length);
-	while (!_usart_sync_is_ready_to_send(&descr->device))
-		;
-	do {
-		_usart_sync_write_byte(&descr->device, buf[offset]);
-		while (!_usart_sync_is_ready_to_send(&descr->device))
-			;
-	} while (++offset < length);
-	while (!_usart_sync_is_transmit_done(&descr->device))
-		;
-	return (int32_t)offset;
-}
-
-/*
- * \internal Read data from usart interface
- *
- * \param[in] descr The pointer to an io descriptor
- * \param[in] buf A buffer to read data to
- * \param[in] length The size of a buffer
- *
- * \return The number of bytes read.
- */
-static int32_t usart_sync_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
-{
-	uint32_t                      offset = 0;
-	struct usart_sync_descriptor *descr  = CONTAINER_OF(io_descr, struct usart_sync_descriptor, io);
-
-	ASSERT(io_descr && buf && length);
-	do {
-		while (!_usart_sync_is_byte_received(&descr->device))
-			;
-		buf[offset] = _usart_sync_read_byte(&descr->device);
-	} while (++offset < length);
-
-	return (int32_t)offset;
-}

bsp/microchip/samc21/bsp/hal/utils/include/utils_ringbuffer.h

@@ -0,0 +1,116 @@
+/**
+ * \file
+ *
+ * \brief Ringbuffer declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#ifndef _UTILS_RINGBUFFER_H_INCLUDED
+#define _UTILS_RINGBUFFER_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_utils_ringbuffer
+ *
+ * @{
+ */
+
+#include "compiler.h"
+#include "utils_assert.h"
+
+/**
+ * \brief Ring buffer element type
+ */
+struct ringbuffer {
+	uint8_t *buf;         /** Buffer base address */
+	uint32_t size;        /** Buffer size */
+	uint32_t read_index;  /** Buffer read index */
+	uint32_t write_index; /** Buffer write index */
+};
+
+/**
+ * \brief Ring buffer init
+ *
+ * \param[in] rb The pointer to a ring buffer structure instance
+ * \param[in] buf Space to store the data
+ * \param[in] size The buffer length, must be aligned with power of 2
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size);
+
+/**
+ * \brief Get one byte from ring buffer, the user needs to handle the concurrent
+ * access on buffer via put/get/flush
+ *
+ * \param[in] rb The pointer to a ring buffer structure instance
+ * \param[in] data One byte space to store the read data
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data);
+
+/**
+ * \brief Put one byte to ring buffer, the user needs to handle the concurrent access
+ * on buffer via put/get/flush
+ *
+ * \param[in] rb The pointer to a ring buffer structure instance
+ * \param[in] data One byte data to be put into ring buffer
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data);
+
+/**
+ * \brief Return the element number of ring buffer
+ *
+ * \param[in] rb The pointer to a ring buffer structure instance
+ *
+ * \return The number of elements in ring buffer [0, rb->size]
+ */
+uint32_t ringbuffer_num(const struct ringbuffer *const rb);
+
+/**
+ * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer
+ * via put/get/flush
+ *
+ * \param[in] rb The pointer to a ring buffer structure instance
+ *
+ * \return ERR_NONE on success, or an error code on failure.
+ */
+uint32_t ringbuffer_flush(struct ringbuffer *const rb);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* _UTILS_RINGBUFFER_H_INCLUDED */

bsp/microchip/samc21/bsp/hal/utils/src/utils_ringbuffer.c

@@ -0,0 +1,118 @@
+/**
+ * \file
+ *
+ * \brief Ringbuffer functionality implementation.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+#include "utils_ringbuffer.h"
+
+/**
+ * \brief Ringbuffer init
+ */
+int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size)
+{
+	ASSERT(rb && buf && size);
+
+	/*
+	 * buf size must be aligned to power of 2
+	 */
+	if ((size & (size - 1)) != 0) {
+		return ERR_INVALID_ARG;
+	}
+
+	/* size - 1 is faster in calculation */
+	rb->size        = size - 1;
+	rb->read_index  = 0;
+	rb->write_index = rb->read_index;
+	rb->buf         = (uint8_t *)buf;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Get one byte from ringbuffer
+ *
+ */
+int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data)
+{
+	ASSERT(rb && data);
+
+	if (rb->write_index != rb->read_index) {
+		*data = rb->buf[rb->read_index & rb->size];
+		rb->read_index++;
+		return ERR_NONE;
+	}
+
+	return ERR_NOT_FOUND;
+}
+
+/**
+ * \brief Put one byte to ringbuffer
+ *
+ */
+int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data)
+{
+	ASSERT(rb);
+
+	rb->buf[rb->write_index & rb->size] = data;
+
+	/*
+	 * buffer full strategy: new data will overwrite the oldest data in
+	 * the buffer
+	 */
+	if ((rb->write_index - rb->read_index) > rb->size) {
+		rb->read_index = rb->write_index - rb->size;
+	}
+
+	rb->write_index++;
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Return the element number of ringbuffer
+ */
+uint32_t ringbuffer_num(const struct ringbuffer *const rb)
+{
+	ASSERT(rb);
+
+	return rb->write_index - rb->read_index;
+}
+
+/**
+ * \brief Flush ringbuffer
+ */
+uint32_t ringbuffer_flush(struct ringbuffer *const rb)
+{
+	ASSERT(rb);
+
+	rb->read_index = rb->write_index;
+
+	return ERR_NONE;
+}

bsp/microchip/samc21/bsp/hpl/adc/hpl_adc.c

@@ -0,0 +1,771 @@
+
+/**
+ * \file
+ *
+ * \brief SAM Analog Digital Converter
+ *
+ * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <hpl_adc_async.h>
+#include <hpl_adc_dma.h>
+#include <hpl_adc_sync.h>
+#include <utils_assert.h>
+#include <utils_repeat_macro.h>
+#include <hpl_adc_config.h>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 0
+#endif
+#ifndef CONF_ADC_1_ENABLE
+#define CONF_ADC_1_ENABLE 0
+#endif
+
+/**
+ * \brief Macro is used to fill ADC configuration structure based on its number
+ *
+ * \param[in] n The number of structures
+ */
+
+#define ADC_CONFIGURATION(n)                                                                                           \
+	{                                                                                                                  \
+		(n),                                                                                                           \
+		    (CONF_ADC_##n##_RUNSTDBY << ADC_CTRLA_RUNSTDBY_Pos) | (CONF_ADC_##n##_ONDEMAND << ADC_CTRLA_ONDEMAND_Pos)  \
+		        | (CONF_ADC_##n##_SLAVEEN << ADC_CTRLA_SLAVEEN_Pos),                                                   \
+		    ADC_CTRLB_PRESCALER(CONF_ADC_##n##_PRESCALER),                                                             \
+		    (CONF_ADC_##n##_REFCOMP << ADC_REFCTRL_REFCOMP_Pos) | ADC_REFCTRL_REFSEL(CONF_ADC_##n##_REFSEL),           \
+		    (CONF_ADC_##n##_WINMONEO << ADC_EVCTRL_WINMONEO_Pos)                                                       \
+		        | (CONF_ADC_##n##_RESRDYEO << ADC_EVCTRL_RESRDYEO_Pos)                                                 \
+		        | (CONF_ADC_##n##_STARTINV << ADC_EVCTRL_STARTINV_Pos)                                                 \
+		        | (CONF_ADC_##n##_FLUSHINV << ADC_EVCTRL_FLUSHINV_Pos)                                                 \
+		        | (CONF_ADC_##n##_STARTEI << ADC_EVCTRL_STARTEI_Pos)                                                   \
+		        | (CONF_ADC_##n##_FLUSHEI << ADC_EVCTRL_FLUSHEI_Pos),                                                  \
+		    ADC_INPUTCTRL_MUXNEG(CONF_ADC_##n##_MUXNEG) | ADC_INPUTCTRL_MUXPOS(CONF_ADC_##n##_MUXPOS),                 \
+		    ADC_CTRLC_DUALSEL(CONF_ADC_##n##_DUALSEL) | ADC_CTRLC_WINMODE(CONF_ADC_##n##_WINMODE)                      \
+		        | (CONF_ADC_##n##_R2R << ADC_CTRLC_R2R_Pos) | ADC_CTRLC_RESSEL(CONF_ADC_##n##_RESSEL)                  \
+		        | (CONF_ADC_##n##_CORREN << ADC_CTRLC_CORREN_Pos) | (CONF_ADC_##n##_FREERUN << ADC_CTRLC_FREERUN_Pos)  \
+		        | (CONF_ADC_##n##_LEFTADJ << ADC_CTRLC_LEFTADJ_Pos)                                                    \
+		        | (CONF_ADC_##n##_DIFFMODE << ADC_CTRLC_DIFFMODE_Pos),                                                 \
+		    ADC_AVGCTRL_ADJRES(CONF_ADC_##n##_ADJRES) | ADC_AVGCTRL_SAMPLENUM(CONF_ADC_##n##_SAMPLENUM),               \
+		    (CONF_ADC_##n##_OFFCOMP << ADC_SAMPCTRL_OFFCOMP_Pos) | ADC_SAMPCTRL_SAMPLEN(CONF_ADC_##n##_SAMPLEN),       \
+		    ADC_WINLT_WINLT(CONF_ADC_##n##_WINLT), ADC_WINUT_WINUT(CONF_ADC_##n##_WINUT),                              \
+		    ADC_GAINCORR_GAINCORR(CONF_ADC_##n##_GAINCORR), ADC_OFFSETCORR_OFFSETCORR(CONF_ADC_##n##_OFFSETCORR),      \
+		    CONF_ADC_##n##_DBGRUN << ADC_DBGCTRL_DBGRUN_Pos, ADC_SEQCTRL_SEQEN(CONF_ADC_##n##_SEQEN),                  \
+	}
+
+/**
+ * \brief ADC configuration
+ */
+struct adc_configuration {
+	uint8_t                  number;
+	hri_adc_ctrla_reg_t      ctrl_a;
+	hri_adc_ctrlb_reg_t      ctrl_b;
+	hri_adc_refctrl_reg_t    ref_ctrl;
+	hri_adc_evctrl_reg_t     ev_ctrl;
+	hri_adc_inputctrl_reg_t  input_ctrl;
+	hri_adc_ctrlc_reg_t      ctrl_c;
+	hri_adc_avgctrl_reg_t    avg_ctrl;
+	hri_adc_sampctrl_reg_t   samp_ctrl;
+	hri_adc_winlt_reg_t      win_lt;
+	hri_adc_winut_reg_t      win_ut;
+	hri_adc_gaincorr_reg_t   gain_corr;
+	hri_adc_offsetcorr_reg_t offset_corr;
+	hri_adc_dbgctrl_reg_t    dbg_ctrl;
+	hri_adc_seqctrl_reg_t    seq_ctrl;
+};
+
+#define ADC_AMOUNT (CONF_ADC_0_ENABLE + CONF_ADC_1_ENABLE)
+
+/**
+ * \brief Array of ADC configurations
+ */
+static const struct adc_configuration _adcs[] = {
+#if CONF_ADC_0_ENABLE == 1
+    ADC_CONFIGURATION(0),
+#endif
+#if CONF_ADC_1_ENABLE == 1
+    ADC_CONFIGURATION(1),
+#endif
+};
+
+static void _adc_set_reference_source(void *const hw, const adc_reference_t reference);
+
+/**
+ * \brief Retrieve ordinal number of the given adc hardware instance
+ */
+static uint8_t _adc_get_hardware_index(const void *const hw)
+{
+	return ((uint32_t)hw - (uint32_t)ADC0) >> 10;
+}
+
+/** \brief Return the pointer to register settings of specific ADC
+ *  \param[in] hw_addr The hardware register base address.
+ *  \return Pointer to register settings of specific ADC.
+ */
+static uint8_t _adc_get_regs(const uint32_t hw_addr)
+{
+	uint8_t n = _adc_get_hardware_index((const void *)hw_addr);
+	uint8_t i;
+
+	for (i = 0; i < sizeof(_adcs) / sizeof(struct adc_configuration); i++) {
+		if (_adcs[i].number == n) {
+			return i;
+		}
+	}
+
+	ASSERT(false);
+	return 0;
+}
+
+/**
+ * \brief Retrieve IRQ number for the given hardware instance
+ */
+static uint8_t _adc_get_irq_num(const struct _adc_async_device *const device)
+{
+	return ADC0_IRQn + _adc_get_hardware_index(device->hw);
+}
+
+/**
+ * \brief Init irq param with the given afec hardware instance
+ */
+static void _adc_init_irq_param(const void *const hw, struct _adc_async_device *dev)
+{
+}
+
+/**
+ * \brief Initialize ADC
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] i The number of hardware instance
+ */
+static int32_t _adc_init(void *const hw, const uint8_t i)
+{
+	uint16_t calib_reg = 0;
+	if (hw == ADC0) {
+		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC0_FUSES_BIASREFBUF_ADDR >> ADC0_FUSES_BIASREFBUF_Pos))
+		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC0_FUSES_BIASCOMP_ADDR >> ADC0_FUSES_BIASCOMP_Pos));
+	} else if (hw == ADC1) {
+		calib_reg = ADC_CALIB_BIASREFBUF((*(uint32_t *)ADC1_FUSES_BIASREFBUF_ADDR >> ADC1_FUSES_BIASREFBUF_Pos))
+		            | ADC_CALIB_BIASCOMP((*(uint32_t *)ADC1_FUSES_BIASCOMP_ADDR >> ADC1_FUSES_BIASCOMP_Pos));
+	}
+
+	if (!hri_adc_is_syncing(hw, ADC_SYNCBUSY_SWRST)) {
+		if (hri_adc_get_CTRLA_reg(hw, ADC_CTRLA_ENABLE)) {
+			hri_adc_clear_CTRLA_ENABLE_bit(hw);
+			hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_ENABLE);
+		}
+		hri_adc_write_CTRLA_reg(hw, ADC_CTRLA_SWRST);
+	}
+	hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST);
+
+	hri_adc_write_CALIB_reg(hw, calib_reg);
+	hri_adc_write_CTRLB_reg(hw, _adcs[i].ctrl_b);
+	hri_adc_write_REFCTRL_reg(hw, _adcs[i].ref_ctrl);
+	hri_adc_write_EVCTRL_reg(hw, _adcs[i].ev_ctrl);
+	hri_adc_write_INPUTCTRL_reg(hw, _adcs[i].input_ctrl);
+	hri_adc_write_CTRLC_reg(hw, _adcs[i].ctrl_c);
+	hri_adc_write_AVGCTRL_reg(hw, _adcs[i].avg_ctrl);
+	hri_adc_write_SAMPCTRL_reg(hw, _adcs[i].samp_ctrl);
+	hri_adc_write_WINLT_reg(hw, _adcs[i].win_lt);
+	hri_adc_write_WINUT_reg(hw, _adcs[i].win_ut);
+	hri_adc_write_GAINCORR_reg(hw, _adcs[i].gain_corr);
+	hri_adc_write_OFFSETCORR_reg(hw, _adcs[i].offset_corr);
+	hri_adc_write_DBGCTRL_reg(hw, _adcs[i].dbg_ctrl);
+	hri_adc_write_SEQCTRL_reg(hw, _adcs[i].seq_ctrl);
+	hri_adc_write_CTRLA_reg(hw, _adcs[i].ctrl_a);
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief De-initialize ADC
+ *
+ * \param[in] hw The pointer to hardware instance
+ */
+static inline void _adc_deinit(void *hw)
+{
+	hri_adc_clear_CTRLA_ENABLE_bit(hw);
+	hri_adc_set_CTRLA_SWRST_bit(hw);
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _adc_init(hw, _adc_get_regs((uint32_t)hw));
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw)
+{
+	int32_t init_status;
+
+	ASSERT(device);
+
+	init_status = _adc_init(hw, _adc_get_regs((uint32_t)hw));
+	if (init_status) {
+		return init_status;
+	}
+	device->hw = hw;
+	_adc_init_irq_param(hw, device);
+	NVIC_DisableIRQ(_adc_get_irq_num(device));
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
+	NVIC_EnableIRQ(_adc_get_irq_num(device));
+
+	return ERR_NONE;
+}
+
+/**
+ * \brief Initialize ADC
+ */
+int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw)
+{
+	ASSERT(device);
+
+	device->hw = hw;
+
+	return _adc_init(hw, _adc_get_regs((uint32_t)hw));
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_sync_deinit(struct _adc_sync_device *const device)
+{
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_async_deinit(struct _adc_async_device *const device)
+{
+	NVIC_DisableIRQ(_adc_get_irq_num(device));
+	NVIC_ClearPendingIRQ(_adc_get_irq_num(device));
+
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief De-initialize ADC
+ */
+void _adc_dma_deinit(struct _adc_dma_device *const device)
+{
+	_adc_deinit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Enable ADC
+ */
+void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_set_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Disable ADC
+ */
+void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_clear_CTRLA_ENABLE_bit(device->hw);
+}
+
+/**
+ * \brief Return address of ADC DMA source
+ */
+uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device)
+{
+	return (uint32_t) & (((Adc *)(device->hw))->RESULT.reg);
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device)
+{
+	return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device)
+{
+	return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Retrieve ADC conversion data size
+ */
+uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device)
+{
+	return hri_adc_read_CTRLC_RESSEL_bf(device->hw) == ADC_CTRLC_RESSEL_8BIT_Val ? 1 : 2;
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Check if conversion is done
+ */
+bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device)
+{
+	return hri_adc_get_interrupt_RESRDY_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_sync_convert(struct _adc_sync_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_async_convert(struct _adc_async_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Make conversion
+ */
+void _adc_dma_convert(struct _adc_dma_device *const device)
+{
+	hri_adc_set_SWTRIG_START_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve the conversion result
+ */
+uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_read_RESULT_reg(device->hw);
+}
+
+/**
+ * \brief Retrieve the conversion result
+ */
+uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel)
+{
+	(void)channel;
+
+	return hri_adc_read_RESULT_reg(device->hw);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set reference source
+ */
+void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference)
+{
+	_adc_set_reference_source(device->hw, reference);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set resolution
+ */
+void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution)
+{
+	hri_adc_write_CTRLC_RESSEL_bf(device->hw, resolution);
+}
+
+/**
+ * \brief Set channels input sources
+ */
+void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
+                          const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set channels input sources
+ */
+void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
+                           const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set channels input source
+ */
+void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
+                         const adc_neg_input_t neg_input, const uint8_t channel)
+{
+	(void)channel;
+
+	hri_adc_write_INPUTCTRL_MUXPOS_bf(device->hw, pos_input);
+	hri_adc_write_INPUTCTRL_MUXNEG_bf(device->hw, neg_input);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
+                              const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
+                               const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set thresholds
+ */
+void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
+                             const adc_threshold_t up_threshold)
+{
+	hri_adc_write_WINLT_reg(device->hw, low_threshold);
+	hri_adc_write_WINUT_reg(device->hw, up_threshold);
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set gain
+ */
+void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain)
+{
+	(void)device, (void)channel, (void)gain;
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLC_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLC_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set conversion mode
+ */
+void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode)
+{
+	if (ADC_CONVERSION_MODE_FREERUN == mode) {
+		hri_adc_set_CTRLC_FREERUN_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_FREERUN_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
+                                             const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
+                                              const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set differential mode
+ */
+void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
+                                            const enum adc_differential_mode mode)
+{
+	(void)channel;
+
+	if (ADC_DIFFERENTIAL_MODE_DIFFERENTIAL == mode) {
+		hri_adc_set_CTRLC_DIFFMODE_bit(device->hw);
+	} else {
+		hri_adc_clear_CTRLC_DIFFMODE_bit(device->hw);
+	}
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Set window mode
+ */
+void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode)
+{
+	hri_adc_write_CTRLC_WINMODE_bf(device->hw, mode);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Retrieve threshold state
+ */
+void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state)
+{
+	*state = hri_adc_get_interrupt_WINMON_bit(device->hw);
+}
+
+/**
+ * \brief Enable/disable ADC channel interrupt
+ */
+void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
+                              const enum _adc_async_callback_type type, const bool state)
+{
+	(void)channel;
+
+	void *const hw = device->hw;
+
+	if (ADC_ASYNC_DEVICE_MONITOR_CB == type) {
+		hri_adc_write_INTEN_WINMON_bit(hw, state);
+	} else if (ADC_ASYNC_DEVICE_ERROR_CB == type) {
+		hri_adc_write_INTEN_OVERRUN_bit(hw, state);
+	} else if (ADC_ASYNC_DEVICE_CONVERT_CB == type) {
+		hri_adc_write_INTEN_RESRDY_bit(hw, state);
+	}
+}
+
+/**
+ * \brief Retrieve ADC sync helper functions
+ */
+void *_adc_get_adc_sync(void)
+{
+	return (void *)NULL;
+}
+
+/**
+ * \brief Retrieve ADC async helper functions
+ */
+void *_adc_get_adc_async(void)
+{
+	return (void *)NULL;
+}
+
+/**
+ * \brief Set ADC reference source
+ *
+ * \param[in] hw The pointer to hardware instance
+ * \param[in] reference The reference to set
+ */
+static void _adc_set_reference_source(void *const hw, const adc_reference_t reference)
+{
+	bool enabled = hri_adc_get_CTRLA_ENABLE_bit(hw);
+
+	hri_adc_clear_CTRLA_ENABLE_bit(hw);
+	hri_adc_write_REFCTRL_REFSEL_bf(hw, reference);
+
+	if (enabled) {
+		hri_adc_set_CTRLA_ENABLE_bit(hw);
+	}
+}

bsp/microchip/same70/bsp/hal/include/hpl_time_measure.h → bsp/microchip/samc21/bsp/hpl/adc/hpl_adc_base.h

@@ -1,9 +1,9 @@
 /**
  * \file
  *
- * \brief Time measure related functionality declaration.
+ * \brief ADC related functionality declaration.
  *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
  *
  * \asf_license_start
  *
@@ -31,64 +31,42 @@
  *
  */
 
-#ifndef _HPL_TIME_MEASURE_H_INCLUDED
-#define _HPL_TIME_MEASURE_H_INCLUDED
+#ifndef _HPL_ADC_ADC_H_INCLUDED
+#define _HPL_ADC_ADC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+#include <hpl_adc_async.h>
 
 /**
- * \addtogroup HPL Time measure
+ * \addtogroup HPL ADC
  *
- * \section hpl_time_measure_rev Revision History
+ * \section hpl_adc_rev Revision History
  * - v1.0.0 Initial Release
  *
  *@{
  */
 
-#include <compiler.h>
-
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/**
- * \brief System time type
- */
-typedef uint32_t system_time_t;
-
 /**
  * \name HPL functions
  */
 //@{
-/**
- * \brief Initialize system time module
- *
- * \param[in] hw The pointer to hardware instance to initialize
- */
-void _system_time_init(void *const hw);
 
 /**
- * \brief Deinitialize system time module
+ * \brief Retrieve ADC helper functions
  *
- * \param[in] hw The pointer to hardware instance to initialize
+ * \return A pointer to set of ADC helper functions
  */
-void _system_time_deinit(void *const hw);
+void *_adc_get_adc_sync(void);
+void *_adc_get_adc_async(void);
 
-/**
- * \brief Get system time
- *
- * \param[in] hw The pointer to hardware instance to initialize
- */
-system_time_t _system_time_get(const void *const hw);
-
-/**
- * \brief Get maximum possible system time
- *
- * \param[in] hw The pointer to hardware instance to initialize
- */
-system_time_t _system_time_get_max_time_value(const void *const hw);
 //@}
 
 #ifdef __cplusplus
 }
 #endif
 /**@}*/
-#endif /* _HPL_TIME_MEASURE_H_INCLUDED */
+#endif /* _HPL_USART_UART_H_INCLUDED */

bsp/microchip/samc21/bsp/hpl/sercom/hpl_sercom.c

@@ -156,6 +156,8 @@ static struct usart_configuration _usarts[] = {
 };
 #endif
 
+static struct _usart_async_device *_sercom4_dev = NULL;
+
 static uint8_t _get_sercom_index(const void *const hw);
 static uint8_t _sercom_get_irq_num(const void *const hw);
 static void    _sercom_init_irq_param(const void *const hw, void *dev);
@@ -549,6 +551,40 @@ void _usart_async_set_irq_state(struct _usart_async_device *const device, const
 	}
 }
 
+/**
+ * \internal Sercom interrupt handler
+ *
+ * \param[in] p The pointer to interrupt parameter
+ */
+static void _sercom_usart_interrupt_handler(struct _usart_async_device *device)
+{
+	void *hw = device->hw;
+
+	if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) {
+		hri_sercomusart_clear_INTEN_DRE_bit(hw);
+		device->usart_cb.tx_byte_sent(device);
+	} else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) {
+		hri_sercomusart_clear_INTEN_TXC_bit(hw);
+		device->usart_cb.tx_done_cb(device);
+	} else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) {
+		if (hri_sercomusart_read_STATUS_reg(hw)
+		    & (SERCOM_USART_STATUS_PERR | SERCOM_USART_STATUS_FERR | SERCOM_USART_STATUS_BUFOVF
+		       | SERCOM_USART_STATUS_ISF | SERCOM_USART_STATUS_COLL)) {
+			hri_sercomusart_clear_STATUS_reg(hw, SERCOM_USART_STATUS_MASK);
+			return;
+		}
+
+		device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw));
+	} else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) {
+		uint32_t status;
+
+		hri_sercomusart_clear_interrupt_ERROR_bit(hw);
+		device->usart_cb.error_cb(device);
+		status = hri_sercomusart_read_STATUS_reg(hw);
+		hri_sercomusart_clear_STATUS_reg(hw, status);
+	}
+}
+
 /**
  * \internal Retrieve ordinal number of the given sercom hardware instance
  *
@@ -576,6 +612,10 @@ static uint8_t _get_sercom_index(const void *const hw)
  */
 static void _sercom_init_irq_param(const void *const hw, void *dev)
 {
+
+	if (hw == SERCOM4) {
+		_sercom4_dev = (struct _usart_async_device *)dev;
+	}
 }
 
 /**
@@ -2407,6 +2447,11 @@ static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_a
 	return NULL;
 }
 
+void SERCOM4_Handler(void)
+{
+	_sercom_usart_interrupt_handler(_sercom4_dev);
+}
+
 int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw)
 {
 	const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw);

bsp/microchip/samc21/bsp/iar-project-connection.ipcf

@@ -10,6 +10,7 @@
         <path>$PROJ_DIR$\examples</path>
         <path>$PROJ_DIR$\hal\include</path>
         <path>$PROJ_DIR$\hal\utils\include</path>
+        <path>$PROJ_DIR$\hpl\adc</path>
         <path>$PROJ_DIR$\hpl\can</path>
         <path>$PROJ_DIR$\hpl\core</path>
         <path>$PROJ_DIR$\hpl\divas</path>
@@ -34,6 +35,7 @@
         <path>$PROJ_DIR$\examples</path>
         <path>$PROJ_DIR$\hal\include</path>
         <path>$PROJ_DIR$\hal\utils\include</path>
+        <path>$PROJ_DIR$\hpl\adc</path>
         <path>$PROJ_DIR$\hpl\can</path>
         <path>$PROJ_DIR$\hpl\core</path>
         <path>$PROJ_DIR$\hpl\divas</path>
@@ -101,6 +103,7 @@
         </group>
 
         <group name="config">
+            <path>config/hpl_adc_config.h</path>
             <path>config/hpl_can_config.h</path>
             <path>config/hpl_divas_config.h</path>
             <path>config/hpl_dmac_config.h</path>
@@ -120,15 +123,20 @@
         </group>
 
         <group name="hal/include">
+            <path>hal/include/hal_adc_sync.h</path>
             <path>hal/include/hal_atomic.h</path>
             <path>hal/include/hal_can_async.h</path>
             <path>hal/include/hal_delay.h</path>
             <path>hal/include/hal_flash.h</path>
             <path>hal/include/hal_gpio.h</path>
+            <path>hal/include/hal_i2c_m_sync.h</path>
             <path>hal/include/hal_init.h</path>
             <path>hal/include/hal_io.h</path>
             <path>hal/include/hal_sleep.h</path>
-            <path>hal/include/hal_usart_sync.h</path>
+            <path>hal/include/hal_usart_async.h</path>
+            <path>hal/include/hpl_adc_async.h</path>
+            <path>hal/include/hpl_adc_dma.h</path>
+            <path>hal/include/hpl_adc_sync.h</path>
             <path>hal/include/hpl_can.h</path>
             <path>hal/include/hpl_can_async.h</path>
             <path>hal/include/hpl_core.h</path>
@@ -161,15 +169,17 @@
         </group>
 
         <group name="hal/src">
+            <path>hal/src/hal_adc_sync.c</path>
             <path>hal/src/hal_atomic.c</path>
             <path>hal/src/hal_can_async.c</path>
             <path>hal/src/hal_delay.c</path>
             <path>hal/src/hal_flash.c</path>
             <path>hal/src/hal_gpio.c</path>
+            <path>hal/src/hal_i2c_m_sync.c</path>
             <path>hal/src/hal_init.c</path>
             <path>hal/src/hal_io.c</path>
             <path>hal/src/hal_sleep.c</path>
-            <path>hal/src/hal_usart_sync.c</path>
+            <path>hal/src/hal_usart_async.c</path>
         </group>
 
         <group name="hal/utils/include">
@@ -183,12 +193,19 @@
             <path>hal/utils/include/utils_increment_macro.h</path>
             <path>hal/utils/include/utils_list.h</path>
             <path>hal/utils/include/utils_repeat_macro.h</path>
+            <path>hal/utils/include/utils_ringbuffer.h</path>
         </group>
 
         <group name="hal/utils/src">
             <path>hal/utils/src/utils_assert.c</path>
             <path>hal/utils/src/utils_event.c</path>
             <path>hal/utils/src/utils_list.c</path>
+            <path>hal/utils/src/utils_ringbuffer.c</path>
+        </group>
+
+        <group name="hpl/adc">
+            <path>hpl/adc/hpl_adc.c</path>
+            <path>hpl/adc/hpl_adc_base.h</path>
         </group>
 
         <group name="hpl/can">

bsp/microchip/samc21/bsp/samc21/gcc/gcc/samc21j18a_flash.ld

@@ -58,6 +58,31 @@ SECTIONS
         *(.rodata .rodata* .gnu.linkonce.r.*)
         *(.ARM.extab* .gnu.linkonce.armextab.*)
 
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+
         /* Support C constructors, and C destructors in both user code
            and the C library. This also provides support for C++ code. */
         . = ALIGN(4);

bsp/microchip/samc21/rtconfig.h

@@ -54,14 +54,38 @@
 #define RT_USING_USER_MAIN
 #define RT_MAIN_THREAD_STACK_SIZE 2048
 #define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+#define RT_USING_DFS
+#define DFS_USING_POSIX
+#define DFS_USING_WORKDIR
+#define DFS_FILESYSTEMS_MAX 4
+#define DFS_FILESYSTEM_TYPES_MAX 4
+#define DFS_FD_MAX 16
+#define RT_USING_DFS_DEVFS
 
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
+#define RT_USING_SYSTEM_WORKQUEUE
+#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048
+#define RT_SYSTEM_WORKQUEUE_PRIORITY 23
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_USING_DMA
 #define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_I2C
 
 /* Using USB */
 
@@ -170,11 +194,13 @@
 
 #define SAMC21_CAN0
 #define SAMC21_ADC0
+#define SAMC21_I2C0
 
 /* Application Demo Config */
 
 #define SAM_CAN_EXAMPLE
 #define SAM_ADC_EXAMPLE
+#define SAM_I2C_EXAMPLE
 #define SOC_SAMC21
 
 #endif

bsp/microchip/same54/.config

@@ -21,7 +21,9 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
 CONFIG_IDLE_THREAD_STACK_SIZE=256
-# CONFIG_RT_USING_TIMER_SOFT is not set
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
 
 #
 # kservice optimization
@@ -93,8 +95,33 @@ CONFIG_RT_USING_USER_MAIN=y
 CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
 CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # CONFIG_RT_USING_LEGACY is not set
-# CONFIG_RT_USING_MSH is not set
-# CONFIG_RT_USING_DFS is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+CONFIG_RT_USING_DFS=y
+CONFIG_DFS_USING_POSIX=y
+CONFIG_DFS_USING_WORKDIR=y
+CONFIG_DFS_FILESYSTEMS_MAX=4
+CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
+CONFIG_DFS_FD_MAX=16
+# CONFIG_RT_USING_DFS_MNTTABLE is not set
+# CONFIG_RT_USING_DFS_ELMFAT is not set
+CONFIG_RT_USING_DFS_DEVFS=y
+# CONFIG_RT_USING_DFS_ROMFS is not set
+# CONFIG_RT_USING_DFS_RAMFS is not set
+# CONFIG_RT_USING_DFS_NFS is not set
 # CONFIG_RT_USING_FAL is not set
 # CONFIG_RT_USING_LWP is not set
 
@@ -102,7 +129,9 @@ CONFIG_RT_MAIN_THREAD_PRIORITY=10
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
-# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SYSTEM_WORKQUEUE=y
+CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048
+CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
 # CONFIG_RT_USING_SERIAL_V2 is not set
@@ -111,9 +140,11 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+# CONFIG_RT_USING_I2C_BITOPS is not set
 # CONFIG_RT_USING_PHY is not set
-CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PIN is not set
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
 # CONFIG_RT_USING_PWM is not set
@@ -147,11 +178,20 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # POSIX (Portable Operating System Interface) layer
 #
-# CONFIG_RT_USING_POSIX_FS is not set
-# CONFIG_RT_USING_POSIX_DELAY is not set
-# CONFIG_RT_USING_POSIX_CLOCK is not set
-# CONFIG_RT_USING_POSIX_TIMER is not set
-# CONFIG_RT_USING_PTHREADS is not set
+CONFIG_RT_USING_POSIX_FS=y
+CONFIG_RT_USING_POSIX_DEVIO=y
+# CONFIG_RT_USING_POSIX_STDIO is not set
+CONFIG_RT_USING_POSIX_POLL=y
+CONFIG_RT_USING_POSIX_SELECT=y
+CONFIG_RT_USING_POSIX_SOCKET=y
+# CONFIG_RT_USING_POSIX_TERMIOS is not set
+CONFIG_RT_USING_POSIX_AIO=y
+# CONFIG_RT_USING_POSIX_MMAN is not set
+CONFIG_RT_USING_POSIX_DELAY=y
+CONFIG_RT_USING_POSIX_CLOCK=y
+CONFIG_RT_USING_POSIX_TIMER=y
+CONFIG_RT_USING_PTHREADS=y
+CONFIG_PTHREAD_NUM_MAX=8
 # CONFIG_RT_USING_MODULE is not set
 
 #
@@ -169,9 +209,80 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 #
 # Network
 #
-# CONFIG_RT_USING_SAL is not set
-# CONFIG_RT_USING_NETDEV is not set
-# CONFIG_RT_USING_LWIP is not set
+CONFIG_RT_USING_SAL=y
+CONFIG_SAL_INTERNET_CHECK=y
+
+#
+# protocol stack implement
+#
+CONFIG_SAL_USING_LWIP=y
+CONFIG_SAL_USING_POSIX=y
+CONFIG_RT_USING_NETDEV=y
+CONFIG_NETDEV_USING_IFCONFIG=y
+CONFIG_NETDEV_USING_PING=y
+CONFIG_NETDEV_USING_NETSTAT=y
+CONFIG_NETDEV_USING_AUTO_DEFAULT=y
+# CONFIG_NETDEV_USING_IPV6 is not set
+CONFIG_NETDEV_IPV4=1
+CONFIG_NETDEV_IPV6=0
+# CONFIG_NETDEV_IPV6_SCOPES is not set
+CONFIG_RT_USING_LWIP=y
+CONFIG_RT_USING_LWIP_LOCAL_VERSION=y
+# CONFIG_RT_USING_LWIP141 is not set
+# CONFIG_RT_USING_LWIP203 is not set
+CONFIG_RT_USING_LWIP212=y
+CONFIG_RT_USING_LWIP_VER_NUM=0x20102
+# CONFIG_RT_USING_LWIP_IPV6 is not set
+CONFIG_RT_LWIP_MEM_ALIGNMENT=4
+CONFIG_RT_LWIP_IGMP=y
+CONFIG_RT_LWIP_ICMP=y
+# CONFIG_RT_LWIP_SNMP is not set
+CONFIG_RT_LWIP_DNS=y
+CONFIG_RT_LWIP_DHCP=y
+CONFIG_IP_SOF_BROADCAST=1
+CONFIG_IP_SOF_BROADCAST_RECV=1
+
+#
+# Static IPv4 Address
+#
+CONFIG_RT_LWIP_IPADDR="192.168.1.30"
+CONFIG_RT_LWIP_GWADDR="192.168.1.1"
+CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
+CONFIG_RT_LWIP_UDP=y
+CONFIG_RT_LWIP_TCP=y
+CONFIG_RT_LWIP_RAW=y
+# CONFIG_RT_LWIP_PPP is not set
+CONFIG_RT_MEMP_NUM_NETCONN=8
+CONFIG_RT_LWIP_PBUF_NUM=16
+CONFIG_RT_LWIP_RAW_PCB_NUM=4
+CONFIG_RT_LWIP_UDP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_PCB_NUM=4
+CONFIG_RT_LWIP_TCP_SEG_NUM=40
+CONFIG_RT_LWIP_TCP_SND_BUF=8196
+CONFIG_RT_LWIP_TCP_WND=8196
+CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
+CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
+CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
+CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
+CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
+CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
+# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
+CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
+CONFIG_LWIP_NETIF_LINK_CALLBACK=1
+CONFIG_SO_REUSE=1
+CONFIG_LWIP_SO_RCVTIMEO=1
+CONFIG_LWIP_SO_SNDTIMEO=1
+CONFIG_LWIP_SO_RCVBUF=1
+CONFIG_LWIP_SO_LINGER=0
+# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
+CONFIG_LWIP_NETIF_LOOPBACK=0
+# CONFIG_RT_LWIP_STATS is not set
+# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
+CONFIG_RT_LWIP_USING_PING=y
+# CONFIG_LWIP_USING_DHCPD is not set
+# CONFIG_RT_LWIP_DEBUG is not set
 # CONFIG_RT_USING_AT is not set
 
 #
@@ -640,10 +751,14 @@ CONFIG_SOC_SAME54P20=y
 #
 CONFIG_SAME5X_CAN0=y
 CONFIG_SAME5X_ADC0=y
+CONFIG_SAME5X_I2C0=y
+CONFIG_SAME5X_GMAC=y
 
 #
 # Application Demo Config
 #
 CONFIG_SAM_CAN_EXAMPLE=y
 CONFIG_SAM_ADC_EXAMPLE=y
+CONFIG_SAM_I2C_EXAMPLE=y
+CONFIG_SAM_LWIP_EXAMPLE=y
 CONFIG_SOC_SAME54=y

bsp/microchip/same54/SConstruct

@@ -34,8 +34,27 @@ if rtconfig.PLATFORM == 'iar':
 Export('RTT_ROOT')
 Export('rtconfig')
 
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/common'):
+    common_path_prefix = SDK_ROOT + '/common'
+else:
+    common_path_prefix = os.path.dirname(SDK_ROOT) + '/common'
+
+SDK_LIB = common_path_prefix
+Export('SDK_LIB')
+
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
 
+sam_board = 'board'
+rtconfig.BSP_LIBRARY_TYPE = sam_board
+
+# include libraries
+objs.extend(SConscript(os.path.join(common_path_prefix, sam_board, 'SConscript')))
+
+# include drivers
+objs.extend(SConscript(os.path.join(common_path_prefix, 'applications', 'SConscript')))
+
 # make a building
 DoBuilding(TARGET, objs)

bsp/microchip/same54/applications/can_demo.h

@@ -1,24 +0,0 @@
-/*
- * Copyright (c)
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
- */
-
-#ifndef __APPLICATION_CAN_H_
-#define __APPLICATION_CAN_H_
-
-#include <rtthread.h>
-
-/**
- * @brief External function definitions
- *
- */
-rt_err_t can_demo_run(void);
-
-rt_err_t can_send_message(struct can_message *msg, rt_uint32_t timeouts);
-
-#endif // __APPLICATION_CAN_H_

bsp/microchip/same54/applications/main.c

@@ -5,7 +5,7 @@
  *
  * Change Logs:
  * Date        Author    Email                    Notes
- * 2019-07-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
+ * 2022-04-16  Kevin.Liu kevin.liu.mchp@gmail.com First Release
  */
 
 #include <rtthread.h>
@@ -22,6 +22,18 @@
 #include "can_demo.h"
 #endif
 
+#ifdef SAM_I2C_EXAMPLE
+#include "i2c_demo.h"
+#endif
+
+#ifdef SAM_ADC_EXAMPLE
+#include "adc_demo.h"
+#endif
+
+#ifdef SAM_LWIP_EXAMPLE
+#include "lwip_demo.h"
+#endif
+
 static rt_uint8_t led_stack[ 512 ];
 static struct rt_thread led_thread;
 
@@ -63,6 +75,18 @@ int main(void)
     can_demo_run();
 #endif
 
+#ifdef SAM_I2C_EXAMPLE
+    i2c_demo_run();
+#endif
+
+#ifdef SAM_ADC_EXAMPLE
+    adc_demo_run();
+#endif
+
+#ifdef SAM_LWIP_EXAMPLE
+    lwip_demo_run();
+#endif
+
     return 0;
 }
 

bsp/microchip/same54/board/Kconfig

@@ -32,6 +32,14 @@ menu "Onboard Peripheral Drivers"
     config SAME5X_ADC0
         bool "Enable ADC0"
         default false
+
+    config SAME5X_I2C0
+        bool "Enable I2C0"
+        default false
+
+    config SAME5X_GMAC
+        bool "Enable GMAC"
+        default false
 endmenu
 
 menu "Application Demo Config"
@@ -49,4 +57,18 @@ menu "Application Demo Config"
         help
             Add ADC example task to project
 
+    config SAM_I2C_EXAMPLE
+        bool "Enable SAM I2C Example"
+        depends on SAME5X_I2C0
+        default true
+        help
+            Add I2C example task to project
+
+    config SAM_LWIP_EXAMPLE
+        bool "Enable SAM LWIP Example"
+        depends on SAME5X_GMAC
+        default false
+        help
+            Add GMAC LWIP example task to project
+
 endmenu

bsp/microchip/same54/board/board.c

@@ -21,17 +21,20 @@ extern int rt_hw_uart_init(void);
 #endif
 
 static struct io_descriptor* g_stdio;
+static uint8_t board_info[16] = "Microchip SAME54";
 
 void rt_hw_console_output(const char *str)
 {
     io_write(g_stdio, (uint8_t *)str, strlen(str));
+    while (TARGET_IO.stat != 0);
 }
 RTM_EXPORT(rt_hw_console_output);
 
 static inline void hw_board_init_usart(void)
 {
-    usart_sync_get_io_descriptor(&TARGET_IO, &g_stdio);
-    usart_sync_enable(&TARGET_IO);
+    usart_async_get_io_descriptor(&TARGET_IO, &g_stdio);
+    usart_async_enable(&TARGET_IO);
+    io_write(g_stdio, board_info, 16);
 }
 
 /**

bsp/microchip/same54/bsp/AtmelStart.gpdsc

@@ -42,18 +42,24 @@
       <description>Atmel Start Framework</description>
       <RTE_Components_h>#define ATMEL_START</RTE_Components_h>
       <files>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/aes_sync.rst"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/can_async.rst"/>
-        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/mac_async.rst"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/usart_async.rst"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_aes_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_cache.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_can_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_mac_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_aes.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_aes_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_can.h"/>
@@ -69,6 +75,7 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_mac_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ramecc.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
@@ -81,8 +88,10 @@
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_can_async.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_mac_async.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
@@ -93,9 +102,11 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_ringbuffer.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_ringbuffer.c"/>
         <file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_e54.h"/>
@@ -136,6 +147,10 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_e54.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_e54.h"/>
+        <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/ethernet_phy.rst"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="ethernet_phy/ethernet_phy.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy/ethernet_phy.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy/ieee8023_mii_standard_register.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
         <file category="doc" condition="ARMCC, GCC, IAR" name="documentation/aes_demo.rst"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
@@ -143,7 +158,10 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
-        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_usart_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
@@ -153,8 +171,11 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
-        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_usart_async.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/aes/hpl_aes.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/can/hpl_can_base.h"/>
@@ -165,6 +186,7 @@
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="hpl/gmac/hpl_gmac.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
@@ -173,24 +195,30 @@
         <file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/ramecc/hpl_ramecc.c"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
+        <file category="source" condition="ARMCC, GCC, IAR" name="ethernet_phy_main.c"/>
+        <file category="header" condition="ARMCC, GCC, IAR" name="ethernet_phy_main.h"/>
         <file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
         <file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_aes_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_can_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_cmcc_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gmac_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
         <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
+        <file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/ieee8023_mii_standard_config.h"/>
         <file category="include" condition="ARMCC, GCC, IAR" name=""/>
         <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/aes"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/can"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/cmcc"/>
@@ -206,6 +234,9 @@
         <file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
         <file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
         <file category="include" condition="ARMCC, GCC, IAR" name=""/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="config"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name="ethernet_phy"/>
+        <file category="include" condition="ARMCC, GCC, IAR" name=""/>
       </files>
     </component>
   </components>

bsp/microchip/same54/bsp/SConscript

@@ -11,14 +11,17 @@ CPPDEFINES = []
 CPPDEFINES += [rtconfig.DEVICE_TYPE]
 
 # The set of source files associated with this SConscript file.
+
 src  = Glob('hal/src/*.c')
 src += Glob('hal/utils/src/*.c')
+src += Glob('hpl/adc/*.c')
 src += Glob('hpl/aes/*.c')
 src += Glob('hpl/can/*.c')
 src += Glob('hpl/cmcc/*.c')
 src += Glob('hpl/core/*.c')
 src += Glob('hpl/dmac/*.c')
 src += Glob('hpl/gclk/*.c')
+src += Glob('hpl/gmac/*.c')
 src += Glob('hpl/mclk/*.c')
 src += Glob('hpl/osc32kctrl/*.c')
 src += Glob('hpl/oscctrl/*.c')
@@ -26,8 +29,10 @@ src += Glob('hpl/pm/*.c')
 src += Glob('hpl/port/*.c')
 src += Glob('hpl/ramecc/*.c')
 src += Glob('hpl/sercom/*.c')
+src += Glob('ethernet_phy/*.c')
 src += [cwd + '/atmel_start.c']
 src += [cwd + '/driver_init.c']
+src += [cwd + '/ethernet_phy_main.c']
 
 #add for startup script
 if rtconfig.CROSS_TOOL == 'gcc':
@@ -44,15 +49,19 @@ path = [
     cwd,
     cwd + '/CMSIS/Core/Include',
     cwd + '/config',
+    cwd + '/ethernet_phy',
     cwd + '/hal/include',
     cwd + '/hal/utils/include',
+    cwd + '/hpl/adc',
     cwd + '/hpl/can',
     cwd + '/hpl/core',
     cwd + '/hpl/gclk',
     cwd + '/hpl/pm',
     cwd + '/hpl/port',
     cwd + '/hri',
-    cwd + '/include',]
+    cwd + '/include',
+    cwd + '/../board',
+    cwd + '/../../common/applications']
 
 group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
 

bsp/microchip/same54/bsp/armcc/Makefile

@@ -1,225 +0,0 @@
-
-################################################################################
-# Automatically-generated file. Do not edit!
-################################################################################
-
-ifdef SystemRoot
-	SHELL = cmd.exe
-	MK_DIR = mkdir
-else
-	ifeq ($(shell uname), Linux)
-		MK_DIR = mkdir -p
-	endif
-
-	ifeq ($(shell uname | cut -d _ -f 1), CYGWIN)
-		MK_DIR = mkdir -p
-	endif
-
-	ifeq ($(shell uname | cut -d _ -f 1), MINGW32)
-		MK_DIR = mkdir -p
-	endif
-
-	ifeq ($(shell uname | cut -d _ -f 1), MINGW64)
-		MK_DIR = mkdir -p
-	endif
-endif
-
-# List the subdirectories for creating object files
-SUB_DIRS +=  \
- \
-hpl/pm \
-hpl/osc32kctrl \
-hpl/can \
-hpl/ramecc \
-hpl/dmac \
-hal/src \
-hpl/mclk \
-hpl/aes \
-hpl/sercom \
-examples \
-hpl/gclk \
-hpl/oscctrl \
-hal/utils/src \
-armcc/arm_addon/armcc/arm \
-armcc/arm_addon/armcc \
-hpl/core \
-hpl/cmcc
-
-# List the object files
-OBJS +=  \
-hal/src/hal_io.o \
-hal/src/hal_can_async.o \
-armcc/arm_addon/armcc/system_same54.o \
-hpl/can/hpl_can.o \
-hpl/core/hpl_core_m4.o \
-hal/src/hal_cache.o \
-hpl/aes/hpl_aes.o \
-hal/src/hal_delay.o \
-hpl/pm/hpl_pm.o \
-hpl/core/hpl_init.o \
-hpl/gclk/hpl_gclk.o \
-hal/utils/src/utils_list.o \
-hal/utils/src/utils_assert.o \
-hpl/dmac/hpl_dmac.o \
-hpl/oscctrl/hpl_oscctrl.o \
-hal/src/hal_usart_sync.o \
-hpl/mclk/hpl_mclk.o \
-hpl/ramecc/hpl_ramecc.o \
-hal/src/hal_init.o \
-main.o \
-hpl/osc32kctrl/hpl_osc32kctrl.o \
-examples/driver_examples.o \
-driver_init.o \
-hpl/sercom/hpl_sercom.o \
-hal/src/hal_gpio.o \
-hal/utils/src/utils_event.o \
-hal/src/hal_sleep.o \
-hal/src/hal_aes_sync.o \
-hpl/cmcc/hpl_cmcc.o \
-atmel_start.o \
-hal/src/hal_atomic.o \
-armcc/arm_addon/armcc/arm/startup_same54.o
-
-OBJS_AS_ARGS +=  \
-"hal/src/hal_io.o" \
-"hal/src/hal_can_async.o" \
-"armcc/arm_addon/armcc/system_same54.o" \
-"hpl/can/hpl_can.o" \
-"hpl/core/hpl_core_m4.o" \
-"hal/src/hal_cache.o" \
-"hpl/aes/hpl_aes.o" \
-"hal/src/hal_delay.o" \
-"hpl/pm/hpl_pm.o" \
-"hpl/core/hpl_init.o" \
-"hpl/gclk/hpl_gclk.o" \
-"hal/utils/src/utils_list.o" \
-"hal/utils/src/utils_assert.o" \
-"hpl/dmac/hpl_dmac.o" \
-"hpl/oscctrl/hpl_oscctrl.o" \
-"hal/src/hal_usart_sync.o" \
-"hpl/mclk/hpl_mclk.o" \
-"hpl/ramecc/hpl_ramecc.o" \
-"hal/src/hal_init.o" \
-"main.o" \
-"hpl/osc32kctrl/hpl_osc32kctrl.o" \
-"examples/driver_examples.o" \
-"driver_init.o" \
-"hpl/sercom/hpl_sercom.o" \
-"hal/src/hal_gpio.o" \
-"hal/utils/src/utils_event.o" \
-"hal/src/hal_sleep.o" \
-"hal/src/hal_aes_sync.o" \
-"hpl/cmcc/hpl_cmcc.o" \
-"atmel_start.o" \
-"hal/src/hal_atomic.o" \
-"armcc/arm_addon/armcc/arm/startup_same54.o"
-
-# List the dependency files
-DEPS := $(OBJS:%.o=%.d)
-
-DEPS_AS_ARGS +=  \
-"hal/utils/src/utils_event.d" \
-"hal/src/hal_io.d" \
-"armcc/arm_addon/armcc/system_same54.d" \
-"hal/src/hal_can_async.d" \
-"hpl/core/hpl_core_m4.d" \
-"hpl/can/hpl_can.d" \
-"hpl/aes/hpl_aes.d" \
-"hal/utils/src/utils_list.d" \
-"hpl/cmcc/hpl_cmcc.d" \
-"hpl/dmac/hpl_dmac.d" \
-"hal/utils/src/utils_assert.d" \
-"hal/src/hal_delay.d" \
-"hpl/core/hpl_init.d" \
-"hpl/pm/hpl_pm.d" \
-"hpl/ramecc/hpl_ramecc.d" \
-"hpl/gclk/hpl_gclk.d" \
-"hal/src/hal_init.d" \
-"hal/src/hal_usart_sync.d" \
-"hpl/mclk/hpl_mclk.d" \
-"driver_init.d" \
-"hpl/osc32kctrl/hpl_osc32kctrl.d" \
-"hal/src/hal_cache.d" \
-"main.d" \
-"examples/driver_examples.d" \
-"hal/src/hal_aes_sync.d" \
-"hal/src/hal_sleep.d" \
-"hpl/sercom/hpl_sercom.d" \
-"hal/src/hal_gpio.d" \
-"hal/src/hal_atomic.d" \
-"hpl/oscctrl/hpl_oscctrl.d" \
-"armcc/arm_addon/armcc/arm/startup_same54.d" \
-"atmel_start.d"
-
-OUTPUT_FILE_NAME :=AtmelStart
-QUOTE := "
-OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf
-OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf
-
-vpath %.c ../
-vpath %.s ../
-vpath %.S ../
-
-# All Target
-all: $(SUB_DIRS) $(OUTPUT_FILE_PATH)
-
-# Linker target
-
-$(OUTPUT_FILE_PATH): $(OBJS)
-	@echo Building target: $@
-	@echo Invoking: ARMCC Linker
-	$(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \
---strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \
---info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \
--o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \
-$(OBJS_AS_ARGS)
-
-	@echo Finished building target: $@
-
-# Compiler target(s)
-
-
-
-
-%.o: %.c
-	@echo Building file: $<
-	@echo ARMCC Compiler
-	$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
--I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include"  \
---depend "$@"  -o "$@" "$<"
-
-	@echo Finished building: $<
-
-%.o: %.s
-	@echo Building file: $<
-	@echo ARMCC Assembler
-	$(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54P20A__ SETA 1" \
--I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include"  \
---depend "$(@:%.o=%.d)" -o "$@" "$<"
-
-	@echo Finished building: $<
-
-%.o: %.S
-	@echo Building file: $<
-	@echo ARMCC Preprocessing Assembler
-	$(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54P20A__ \
--I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/aes" -I"../hpl/can" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include"  \
---depend "$@"  -o "$@" "$<"
-
-	@echo Finished building: $<
-
-# Detect changes in the dependent files and recompile the respective object files.
-ifneq ($(MAKECMDGOALS),clean)
-ifneq ($(strip $(DEPS)),)
--include $(DEPS)
-endif
-endif
-
-$(SUB_DIRS):
-	$(MK_DIR) "$@"
-
-clean:
-	rm -f $(OBJS_AS_ARGS)
-	rm -f $(OUTPUT_FILE_PATH)
-	rm -f $(DEPS_AS_ARGS)
-	rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf

bsp/microchip/same54/bsp/atmel_start.c

@@ -6,4 +6,5 @@
 void atmel_start_init(void)
 {
 	system_init();
+	ethernet_phys_init();
 }

bsp/microchip/same54/bsp/atmel_start.h

@@ -6,6 +6,7 @@ extern "C" {
 #endif
 
 #include "driver_init.h"
+#include "ethernet_phy_main.h"
 
 /**
  * Initializes MCU, drivers and middleware in the project

bsp/microchip/same54/bsp/atmel_start_config.atstart

@@ -20,8 +20,79 @@ details: null
 application:
   definition: 'Atmel:Application_Examples:0.0.1::Application:AES_Demo:'
   configuration: null
-middlewares: {}
+middlewares:
+  MACIF_PHY:
+    user_label: MACIF_PHY
+    configuration:
+      ieee8023_mii_control_autoneg_en: true
+      ieee8023_mii_control_duplex_mode: full duplex
+      ieee8023_mii_control_isolate_en: false
+      ieee8023_mii_control_loopback_en: false
+      ieee8023_mii_control_powerdown_en: false
+      ieee8023_mii_control_reg0_setting: true
+      ieee8023_mii_control_speed_lsb: 100 Mb/s
+      ieee8023_mii_phy_address: 0
+    definition: Atmel:Ethernet_PHY:0.0.1::Generic_Ethernet_PHY_Driver
+    functionality: Ethernet_PHY
+    api: Ethernet:GenericPHY:Driver
+    dependencies:
+      Communication IO: MACIF
 drivers:
+  ADC_0:
+    user_label: ADC_0
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::ADC0::driver_config_definition::ADC::HAL:Driver:ADC.Sync
+    functionality: ADC
+    api: HAL:Driver:ADC_Sync
+    configuration:
+      adc_advanced_settings: true
+      adc_arch_adjres: 0
+      adc_arch_corren: false
+      adc_arch_dbgrun: false
+      adc_arch_event_settings: false
+      adc_arch_flushei: false
+      adc_arch_flushinv: false
+      adc_arch_gaincorr: 0
+      adc_arch_leftadj: false
+      adc_arch_offcomp: false
+      adc_arch_offsetcorr: 0
+      adc_arch_ondemand: false
+      adc_arch_refcomp: false
+      adc_arch_resrdyeo: false
+      adc_arch_runstdby: false
+      adc_arch_samplen: 2
+      adc_arch_samplenum: 4 samples
+      adc_arch_seqen: 0
+      adc_arch_startei: false
+      adc_arch_startinv: false
+      adc_arch_winlt: 0
+      adc_arch_winmode: No window mode
+      adc_arch_winmoneo: false
+      adc_arch_winut: 0
+      adc_differential_mode: false
+      adc_freerunning_mode: false
+      adc_pinmux_negative: Internal ground
+      adc_pinmux_positive: ADC AIN0 pin
+      adc_prescaler: Peripheral clock divided by 2
+      adc_reference: VDDANA
+      adc_resolution: 16-bit (averaging must be enabled)
+    optional_signals:
+    - identifier: ADC_0:AIN/0
+      pad: PA02
+      mode: Enabled
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::ADC0.AIN.0
+      name: ADC0/AIN/0
+      label: AIN/0
+    variant: null
+    clocks:
+      domain_group:
+        nodes:
+        - name: ADC
+          input: Generic clock generator 0
+          external: false
+          external_frequency: 0
+        configuration:
+          adc_gclk_selection: Generic clock generator 0
   CRYPTOGRAPHY_0:
     user_label: CRYPTOGRAPHY_0
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::AES::driver_config_definition::AES::HAL:Driver:AES.Sync
@@ -591,10 +662,10 @@ drivers:
     functionality: System
     api: HAL:HPL:GCLK
     configuration:
-      $input: 120000000
-      $input_id: Digital Phase Locked Loop (DPLL0)
-      RESERVED_InputFreq: 120000000
-      RESERVED_InputFreq_id: Digital Phase Locked Loop (DPLL0)
+      $input: 12000000
+      $input_id: External Crystal Oscillator 8-48MHz (XOSC1)
+      RESERVED_InputFreq: 12000000
+      RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1)
       _$freq_output_Generic clock generator 0: 120000000
       _$freq_output_Generic clock generator 1: 3000000
       _$freq_output_Generic clock generator 10: 12000000
@@ -798,10 +869,10 @@ drivers:
     functionality: System
     api: HAL:HPL:OSCCTRL
     configuration:
-      $input: 40000000
-      $input_id: Generic clock generator 3
-      RESERVED_InputFreq: 40000000
-      RESERVED_InputFreq_id: Generic clock generator 3
+      $input: 32768
+      $input_id: 32kHz External Crystal Oscillator (XOSC32K)
+      RESERVED_InputFreq: 32768
+      RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K)
       _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000
       _$freq_output_Digital Phase Locked Loop (DPLL0): 120000000
       _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664
@@ -956,11 +1027,11 @@ drivers:
       domain_group: null
   TARGET_IO:
     user_label: TARGET_IO
-    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Sync
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM2::driver_config_definition::UART::HAL:Driver:USART.Async
     functionality: USART
-    api: HAL:Driver:USART_Sync
+    api: HAL:Driver:USART_Async
     configuration:
-      usart_advanced: false
+      usart_advanced: true
       usart_arch_clock_mode: USART with internal clock
       usart_arch_cloden: false
       usart_arch_dbgstop: Keep running
@@ -1003,6 +1074,46 @@ drivers:
         configuration:
           core_gclk_selection: Generic clock generator 0
           slow_gclk_selection: Generic clock generator 1
+  I2C_0:
+    user_label: I2C_0
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::SERCOM7::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync
+    functionality: I2C
+    api: HAL:Driver:I2C_Master_Sync
+    configuration:
+      i2c_master_advanced: true
+      i2c_master_arch_dbgstop: Keep running
+      i2c_master_arch_inactout: 20-21 SCL cycle time-out(200-210us)
+      i2c_master_arch_lowtout: true
+      i2c_master_arch_mexttoen: true
+      i2c_master_arch_runstdby: false
+      i2c_master_arch_sdahold: 300-600ns hold time
+      i2c_master_arch_sexttoen: false
+      i2c_master_arch_trise: 215
+      i2c_master_baud_rate: 100000
+    optional_signals: []
+    variant:
+      specification: SDA=0, SCL=1
+      required_signals:
+      - name: SERCOM7/PAD/0
+        pad: PD08
+        label: SDA
+      - name: SERCOM7/PAD/1
+        pad: PD09
+        label: SCL
+    clocks:
+      domain_group:
+        nodes:
+        - name: Core
+          input: Generic clock generator 3
+          external: false
+          external_frequency: 0
+        - name: Slow
+          input: Generic clock generator 1
+          external: false
+          external_frequency: 0
+        configuration:
+          core_gclk_selection: Generic clock generator 3
+          slow_gclk_selection: Generic clock generator 1
   CAN_0:
     user_label: CAN_0
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::CAN1::driver_config_definition::CAN::HAL:Driver:CAN.Async
@@ -1067,7 +1178,145 @@ drivers:
           external_frequency: 0
         configuration:
           can_gclk_selection: Generic clock generator 3
+  MACIF:
+    user_label: MACIF
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::GMAC::driver_config_definition::GMAC::HAL:Driver:GMAC.Async
+    functionality: Ethernet_MAC
+    api: HAL:Driver:GMAC_Async
+    configuration:
+      gmac_arch_adv_cfg: true
+      gmac_arch_cltto: Clause 22 Operation
+      gmac_arch_dcfgr_ddrp: false
+      gmac_arch_dcfgr_drbs: 2
+      gmac_arch_dcfgr_esma: false
+      gmac_arch_dcfgr_espa: false
+      gmac_arch_dcfgr_fbldo: Always use INCR4 AHB bursts
+      gmac_arch_dcfgr_rxbms: 4 Kbytes
+      gmac_arch_dcfgr_txcoen: false
+      gmac_arch_dcfgr_txpbms: 4 Kbytes
+      gmac_arch_dma_cfg: true
+      gmac_arch_ipgs_fl_div: 1
+      gmac_arch_ipgs_fl_mul: 1
+      gmac_arch_mii_cfg: true
+      gmac_arch_ncfgr_caf: false
+      gmac_arch_ncfgr_clk: '64'
+      gmac_arch_ncfgr_dcpf: false
+      gmac_arch_ncfgr_df: true
+      gmac_arch_ncfgr_dnvlan: false
+      gmac_arch_ncfgr_efrhd: false
+      gmac_arch_ncfgr_ipgsen: false
+      gmac_arch_ncfgr_irxer: false
+      gmac_arch_ncfgr_irxfcs: false
+      gmac_arch_ncfgr_jframe: false
+      gmac_arch_ncfgr_lferd: false
+      gmac_arch_ncfgr_maxfs: true
+      gmac_arch_ncfgr_mtihen: false
+      gmac_arch_ncfgr_nbc: false
+      gmac_arch_ncfgr_pen: false
+      gmac_arch_ncfgr_rfcs: false
+      gmac_arch_ncfgr_rty: false
+      gmac_arch_ncfgr_rxbp: false
+      gmac_arch_ncfgr_rxbufo: 0
+      gmac_arch_ncfgr_rxcoen: false
+      gmac_arch_ncfgr_spd: true
+      gmac_arch_ncfgr_unihen: false
+      gmac_arch_ncr_bp: false
+      gmac_arch_ncr_enpbpr: false
+      gmac_arch_ncr_lbl: false
+      gmac_arch_ncr_mpe: true
+      gmac_arch_ncr_txpbpf: false
+      gmac_arch_ncr_westat: false
+      gmac_arch_rpsf_en: false
+      gmac_arch_rpsf_wm: 100
+      gmac_arch_rxdescr_num: 16
+      gmac_arch_svlan_enable: false
+      gmac_arch_svlan_type: 33024
+      gmac_arch_tpsf_en: false
+      gmac_arch_tpsf_wm: 100
+      gmac_arch_txbuf_size: 1500
+      gmac_arch_txdescr_num: 2
+      gmac_arch_ur_mii: RMII
+    optional_signals:
+    - identifier: MACIF:GMDC
+      pad: PC11
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GMDC
+      name: GMAC/GMDC
+      label: GMDC
+    - identifier: MACIF:GMDIO
+      pad: PC12
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GMDIO
+      name: GMAC/GMDIO
+      label: GMDIO
+    - identifier: MACIF:GRX/0
+      pad: PA13
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GRX.0
+      name: GMAC/GRX/0
+      label: GRX/0
+    - identifier: MACIF:GRX/1
+      pad: PA12
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GRX.1
+      name: GMAC/GRX/1
+      label: GRX/1
+    - identifier: MACIF:GRXDV
+      pad: PC20
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GRXDV
+      name: GMAC/GRXDV
+      label: GRXDV
+    - identifier: MACIF:GRXER
+      pad: PA15
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GRXER
+      name: GMAC/GRXER
+      label: GRXER
+    - identifier: MACIF:GTX/0
+      pad: PA18
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GTX.0
+      name: GMAC/GTX/0
+      label: GTX/0
+    - identifier: MACIF:GTX/1
+      pad: PA19
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GTX.1
+      name: GMAC/GTX/1
+      label: GTX/1
+    - identifier: MACIF:GTXCK
+      pad: PA14
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GTXCK
+      name: GMAC/GTXCK
+      label: GTXCK
+    - identifier: MACIF:GTXEN
+      pad: PA17
+      mode: Enable
+      configuration: null
+      definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::optional_signal_definition::GMAC.GTXEN
+      name: GMAC/GTXEN
+      label: GTXEN
+    variant: null
+    clocks:
+      domain_group: null
 pads:
+  PA02:
+    name: PA02
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA02
+    mode: Analog
+    user_label: PA02
+    configuration: null
   PB12:
     name: PB12
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB12
@@ -1080,12 +1329,84 @@ pads:
     mode: Peripheral IO
     user_label: PB13
     configuration: null
+  PD08:
+    name: PD08
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PD08
+    mode: I2C
+    user_label: PD08
+    configuration: null
+  PD09:
+    name: PD09
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PD09
+    mode: I2C
+    user_label: PD09
+    configuration: null
+  PC11:
+    name: PC11
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC11
+    mode: Peripheral IO
+    user_label: PC11
+    configuration: null
+  PC12:
+    name: PC12
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC12
+    mode: Peripheral IO
+    user_label: PC12
+    configuration: null
+  PA12:
+    name: PA12
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA12
+    mode: Peripheral IO
+    user_label: PA12
+    configuration: null
+  PA13:
+    name: PA13
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA13
+    mode: Peripheral IO
+    user_label: PA13
+    configuration: null
+  PA14:
+    name: PA14
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA14
+    mode: Peripheral IO
+    user_label: PA14
+    configuration: null
+  PA15:
+    name: PA15
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA15
+    mode: Peripheral IO
+    user_label: PA15
+    configuration: null
+  PA17:
+    name: PA17
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA17
+    mode: Peripheral IO
+    user_label: PA17
+    configuration: null
+  PA18:
+    name: PA18
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA18
+    mode: Peripheral IO
+    user_label: PA18
+    configuration: null
+  PA19:
+    name: PA19
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PA19
+    mode: Peripheral IO
+    user_label: PA19
+    configuration: null
   LED0:
     name: PC18
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC18
     mode: Digital output
     user_label: LED0
     configuration: null
+  PC20:
+    name: PC20
+    definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PC20
+    mode: Peripheral IO
+    user_label: PC20
+    configuration: null
   PB24:
     name: PB24
     definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AU::pad::PB24

bsp/microchip/same54/bsp/atmel_start_pins.h

@@ -27,10 +27,23 @@
 #define GPIO_PIN_FUNCTION_M 12
 #define GPIO_PIN_FUNCTION_N 13
 
+#define PA02 GPIO(GPIO_PORTA, 2)
+#define PA12 GPIO(GPIO_PORTA, 12)
+#define PA13 GPIO(GPIO_PORTA, 13)
+#define PA14 GPIO(GPIO_PORTA, 14)
+#define PA15 GPIO(GPIO_PORTA, 15)
+#define PA17 GPIO(GPIO_PORTA, 17)
+#define PA18 GPIO(GPIO_PORTA, 18)
+#define PA19 GPIO(GPIO_PORTA, 19)
 #define PB12 GPIO(GPIO_PORTB, 12)
 #define PB13 GPIO(GPIO_PORTB, 13)
 #define PB24 GPIO(GPIO_PORTB, 24)
 #define PB25 GPIO(GPIO_PORTB, 25)
+#define PC11 GPIO(GPIO_PORTC, 11)
+#define PC12 GPIO(GPIO_PORTC, 12)
 #define LED0 GPIO(GPIO_PORTC, 18)
+#define PC20 GPIO(GPIO_PORTC, 20)
+#define PD08 GPIO(GPIO_PORTD, 8)
+#define PD09 GPIO(GPIO_PORTD, 9)
 
 #endif // ATMEL_START_PINS_H_INCLUDED

bsp/microchip/same54/bsp/config/hpl_adc_config.h

@@ -0,0 +1,302 @@
+/* Auto-generated config file hpl_adc_config.h */
+#ifndef HPL_ADC_CONFIG_H
+#define HPL_ADC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#ifndef CONF_ADC_0_ENABLE
+#define CONF_ADC_0_ENABLE 1
+#endif
+
+// <h> Basic Configuration
+
+// <o> Conversion Result Resolution
+// <0x0=>12-bit
+// <0x1=>16-bit (averaging must be enabled)
+// <0x2=>10-bit
+// <0x3=>8-bit
+// <i>  Defines the bit resolution for the ADC sample values (RESSEL)
+// <id> adc_resolution
+#ifndef CONF_ADC_0_RESSEL
+#define CONF_ADC_0_RESSEL 0x1
+#endif
+
+// <o> Reference Selection
+// <0x0=>Internal bandgap reference
+// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
+// <0x3=>VDDANA
+// <0x4=>External reference A
+// <0x5=>External reference B
+// <0x6=>External reference C
+// <i> Select the reference for the ADC (REFSEL)
+// <id> adc_reference
+#ifndef CONF_ADC_0_REFSEL
+#define CONF_ADC_0_REFSEL 0x3
+#endif
+
+// <o> Prescaler configuration
+// <0x0=>Peripheral clock divided by 2
+// <0x1=>Peripheral clock divided by 4
+// <0x2=>Peripheral clock divided by 8
+// <0x3=>Peripheral clock divided by 16
+// <0x4=>Peripheral clock divided by 32
+// <0x5=>Peripheral clock divided by 64
+// <0x6=>Peripheral clock divided by 128
+// <0x7=>Peripheral clock divided by 256
+// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
+// <id> adc_prescaler
+#ifndef CONF_ADC_0_PRESCALER
+#define CONF_ADC_0_PRESCALER 0x0
+#endif
+
+// <q> Free Running Mode
+// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
+// <id> adc_freerunning_mode
+#ifndef CONF_ADC_0_FREERUN
+#define CONF_ADC_0_FREERUN 0
+#endif
+
+// <q> Differential Mode
+// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
+// <id> adc_differential_mode
+#ifndef CONF_ADC_0_DIFFMODE
+#define CONF_ADC_0_DIFFMODE 0
+#endif
+
+// <o> Positive Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x08=>ADC AIN8 pin
+// <0x09=>ADC AIN9 pin
+// <0x0A=>ADC AIN10 pin
+// <0x0B=>ADC AIN11 pin
+// <0x0C=>ADC AIN12 pin
+// <0x0D=>ADC AIN13 pin
+// <0x0E=>ADC AIN14 pin
+// <0x0F=>ADC AIN15 pin
+// <0x18=>1/4 scaled core supply
+// <0x19=>1/4 Scaled VBAT Supply
+// <0x1A=>1/4 scaled I/O supply
+// <0x1B=>Bandgap voltage
+// <0x1C=>Temperature reference (PTAT)
+// <0x1D=>Temperature reference (CTAT)
+// <0x1E=>DAC Output
+// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
+// <id> adc_pinmux_positive
+#ifndef CONF_ADC_0_MUXPOS
+#define CONF_ADC_0_MUXPOS 0x0
+#endif
+
+// <o> Negative Mux Input Selection
+// <0x00=>ADC AIN0 pin
+// <0x01=>ADC AIN1 pin
+// <0x02=>ADC AIN2 pin
+// <0x03=>ADC AIN3 pin
+// <0x04=>ADC AIN4 pin
+// <0x05=>ADC AIN5 pin
+// <0x06=>ADC AIN6 pin
+// <0x07=>ADC AIN7 pin
+// <0x18=>Internal ground
+// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
+// <id> adc_pinmux_negative
+#ifndef CONF_ADC_0_MUXNEG
+#define CONF_ADC_0_MUXNEG 0x18
+#endif
+
+// </h>
+
+// <e> Advanced Configuration
+// <id> adc_advanced_settings
+#ifndef CONF_ADC_0_ADVANCED
+#define CONF_ADC_0_ADVANCED 1
+#endif
+
+// <q> Run in standby
+// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
+// <id> adc_arch_runstdby
+#ifndef CONF_ADC_0_RUNSTDBY
+#define CONF_ADC_0_RUNSTDBY 0
+#endif
+
+// <q>Debug Run
+// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
+// <id> adc_arch_dbgrun
+#ifndef CONF_ADC_0_DBGRUN
+#define CONF_ADC_0_DBGRUN 0
+#endif
+
+// <q> On Demand Control
+// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
+// <id> adc_arch_ondemand
+#ifndef CONF_ADC_0_ONDEMAND
+#define CONF_ADC_0_ONDEMAND 0
+#endif
+
+// <q> Left-Adjusted Result
+// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
+// <id> adc_arch_leftadj
+#ifndef CONF_ADC_0_LEFTADJ
+#define CONF_ADC_0_LEFTADJ 0
+#endif
+
+// <q> Reference Buffer Offset Compensation Enable
+// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
+// <id> adc_arch_refcomp
+#ifndef CONF_ADC_0_REFCOMP
+#define CONF_ADC_0_REFCOMP 0
+#endif
+
+// <q>Comparator Offset Compensation Enable
+// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
+// <id> adc_arch_offcomp
+#ifndef CONF_ADC_0_OFFCOMP
+#define CONF_ADC_0_OFFCOMP 0
+#endif
+
+// <q> Digital Correction Logic Enabled
+// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
+// <id> adc_arch_corren
+#ifndef CONF_ADC_0_CORREN
+#define CONF_ADC_0_CORREN 0
+#endif
+
+// <o> Offset Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
+// <id> adc_arch_offsetcorr
+#ifndef CONF_ADC_0_OFFSETCORR
+#define CONF_ADC_0_OFFSETCORR 0
+#endif
+
+// <o> Gain Correction Value <0-4095>
+// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
+// <id> adc_arch_gaincorr
+#ifndef CONF_ADC_0_GAINCORR
+#define CONF_ADC_0_GAINCORR 0
+#endif
+
+// <o> Adjusting Result / Division Coefficient <0-7>
+// <i> These bits define the division coefficient in 2n steps. (ADJRES)
+// <id> adc_arch_adjres
+#ifndef CONF_ADC_0_ADJRES
+#define CONF_ADC_0_ADJRES 0x0
+#endif
+
+// <o.0..10> Number of Samples to be Collected
+// <0x0=>1 sample
+// <0x1=>2 samples
+// <0x2=>4 samples
+// <0x3=>8 samples
+// <0x4=>16 samples
+// <0x5=>32 samples
+// <0x6=>64 samples
+// <0x7=>128 samples
+// <0x8=>256 samples
+// <0x9=>512 samples
+// <0xA=>1024 samples
+// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
+// <id> adc_arch_samplenum
+#ifndef CONF_ADC_0_SAMPLENUM
+#define CONF_ADC_0_SAMPLENUM 0x2
+#endif
+
+// <o> Sampling Time Length <0-63>
+// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
+// <id> adc_arch_samplen
+#ifndef CONF_ADC_0_SAMPLEN
+#define CONF_ADC_0_SAMPLEN 2
+#endif
+
+// <o> Window Monitor Mode
+// <0x0=>No window mode
+// <0x1=>Mode 1: RESULT above lower threshold
+// <0x2=>Mode 2: RESULT beneath upper threshold
+// <0x3=>Mode 3: RESULT inside lower and upper threshold
+// <0x4=>Mode 4: RESULT outside lower and upper threshold
+// <i> These bits enable and define the window monitor mode. (WINMODE)
+// <id> adc_arch_winmode
+#ifndef CONF_ADC_0_WINMODE
+#define CONF_ADC_0_WINMODE 0x0
+#endif
+
+// <o> Window Monitor Lower Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
+// <id> adc_arch_winlt
+#ifndef CONF_ADC_0_WINLT
+#define CONF_ADC_0_WINLT 0
+#endif
+
+// <o> Window Monitor Upper Threshold <0-65535>
+// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
+// <id> adc_arch_winut
+#ifndef CONF_ADC_0_WINUT
+#define CONF_ADC_0_WINUT 0
+#endif
+
+// <o> Bitmask for positive input sequence <0-4294967295>
+// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
+// <id> adc_arch_seqen
+#ifndef CONF_ADC_0_SEQEN
+#define CONF_ADC_0_SEQEN 0x0
+#endif
+
+// </e>
+
+// <e> Event Control
+// <id> adc_arch_event_settings
+#ifndef CONF_ADC_0_EVENT_CONTROL
+#define CONF_ADC_0_EVENT_CONTROL 0
+#endif
+
+// <q> Window Monitor Event Out
+// <i> Enables event output on window event (WINMONEO)
+// <id> adc_arch_winmoneo
+#ifndef CONF_ADC_0_WINMONEO
+#define CONF_ADC_0_WINMONEO 0
+#endif
+
+// <q> Result Ready Event Out
+// <i> Enables event output on result ready event (RESRDEO)
+// <id> adc_arch_resrdyeo
+#ifndef CONF_ADC_0_RESRDYEO
+#define CONF_ADC_0_RESRDYEO 0
+#endif
+
+// <q> Invert flush Event Signal
+// <i> Invert the flush event input signal (FLUSHINV)
+// <id> adc_arch_flushinv
+#ifndef CONF_ADC_0_FLUSHINV
+#define CONF_ADC_0_FLUSHINV 0
+#endif
+
+// <q> Trigger Flush On Event
+// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
+// <id> adc_arch_flushei
+#ifndef CONF_ADC_0_FLUSHEI
+#define CONF_ADC_0_FLUSHEI 0
+#endif
+
+// <q> Invert Start Conversion Event Signal
+// <i> Invert the start conversion event input signal (STARTINV)
+// <id> adc_arch_startinv
+#ifndef CONF_ADC_0_STARTINV
+#define CONF_ADC_0_STARTINV 0
+#endif
+
+// <q> Trigger Conversion On Event
+// <i> Trigger a conversion on event. (STARTEI)
+// <id> adc_arch_startei
+#ifndef CONF_ADC_0_STARTEI
+#define CONF_ADC_0_STARTEI 0
+#endif
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_ADC_CONFIG_H

bsp/microchip/same54/bsp/config/hpl_gmac_config.h

@@ -0,0 +1,483 @@
+/* Auto-generated config file hpl_gmac_config.h */
+#ifndef HPL_GMAC_CONFIG_H
+#define HPL_GMAC_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+#include <peripheral_clk_config.h>
+
+// <h> Network Control configuration
+
+// <q> Enable LoopBack Local
+// <i> Connects GTX to GRX, GTXEN to GRXDV and forces full duplex mode.
+// <id> gmac_arch_ncr_lbl
+#ifndef CONF_GMAC_NCR_LBL
+#define CONF_GMAC_NCR_LBL 0
+#endif
+
+// <q> Management Port Enable
+// <i> Enable the Management port
+// <id> gmac_arch_ncr_mpe
+#ifndef CONF_GMAC_NCR_MPE
+#define CONF_GMAC_NCR_MPE 1
+#endif
+
+// <q> Enable write for Static Register
+// <i> Make the statistics registers writable for functional test proposes.
+// <id> gmac_arch_ncr_westat
+#ifndef CONF_GMAC_NCR_WESTAT
+#define CONF_GMAC_NCR_WESTAT 0
+#endif
+
+// <q> Enable Back pressure
+// <i> If set in 10M or 100M half duplex mode, forces collisions on all received frames.
+// <id> gmac_arch_ncr_bp
+#ifndef CONF_GMAC_NCR_BP
+#define CONF_GMAC_NCR_BP 0
+#endif
+
+// <q> Enable PFC Priority-based Pause Reception
+// <i> Enables PFC negotiation and recognition of priority-based pause frames.
+// <id> gmac_arch_ncr_enpbpr
+#ifndef CONF_GMAC_NCR_ENPBPR
+#define CONF_GMAC_NCR_ENPBPR 0
+#endif
+
+// <q> Enable PFC Priority-based Pause Frame
+// <i> Takes the values stored in the Transmit PFC Pause Register.
+// <id> gmac_arch_ncr_txpbpf
+#ifndef CONF_GMAC_NCR_TXPBPF
+#define CONF_GMAC_NCR_TXPBPF 0
+#endif
+
+// </h>
+
+// <h> Network Configuration
+
+// <q> 100Mbps Speed
+// <i> Set to one to indicate 100 Mbps operation, zero for 10 Mbps.
+// <id> gmac_arch_ncfgr_spd
+#ifndef CONF_GMAC_NCFGR_SPD
+#define CONF_GMAC_NCFGR_SPD 1
+#endif
+
+// <q> Enable Full Duplex
+// <i> Enable Full duplex
+// <id> gmac_arch_ncfgr_df
+#ifndef CONF_GMAC_NCFGR_FD
+#define CONF_GMAC_NCFGR_FD 1
+#endif
+
+// <q> Discard Non-VLAN Frames
+// <i> Discard Non-VLAN Frames
+// <id> gmac_arch_ncfgr_dnvlan
+#ifndef CONF_GMAC_NCFGR_DNVLAN
+#define CONF_GMAC_NCFGR_DNVLAN 0
+#endif
+
+// <q> Enable Jumbo Frame
+// <i> Enable jumbo frames up to 10240 bytes to be accepted.
+// <id> gmac_arch_ncfgr_jframe
+#ifndef CONF_GMAC_NCFGR_JFRAME
+#define CONF_GMAC_NCFGR_JFRAME 0
+#endif
+
+// <q> Copy All Frames
+// <i> All valid frames will be accepted
+// <id> gmac_arch_ncfgr_caf
+#ifndef CONF_GMAC_NCFGR_CAF
+#define CONF_GMAC_NCFGR_CAF 0
+#endif
+
+// <q> No broadcast
+// <i> Frames addressed to the broadcast address of all ones will not be accepted.
+// <id> gmac_arch_ncfgr_nbc
+#ifndef CONF_GMAC_NCFGR_NBC
+#define CONF_GMAC_NCFGR_NBC 0
+#endif
+
+// <q> Multicast Hash Enable
+// <i> Multicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register.
+// <id> gmac_arch_ncfgr_mtihen
+#ifndef CONF_GMAC_NCFGR_MTIHEN
+#define CONF_GMAC_NCFGR_MTIHEN 0
+#endif
+
+// <q> Unicast Hash Enable
+// <i> Unicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register.
+// <id> gmac_arch_ncfgr_unihen
+#ifndef CONF_GMAC_NCFGR_UNIHEN
+#define CONF_GMAC_NCFGR_UNIHEN 0
+#endif
+
+// <q> 1536 Maximum Frame Size
+// <i> Accept frames up to 1536 bytes in length.
+// <id> gmac_arch_ncfgr_maxfs
+#ifndef CONF_GMAC_NCFGR_MAXFS
+#define CONF_GMAC_NCFGR_MAXFS 1
+#endif
+
+// <q> Retry Test
+// <i> Must be set to zero for normal operation. If set to one the backoff
+// <i> between collisions will always be one slot time. Setting this bit to
+// <i> one helps test the too many retries condition. Also used in the pause
+// <i> frame tests to reduce the pause counter's decrement time from 512 bit
+// <i> times, to every GRXCK cycle.
+// <id> gmac_arch_ncfgr_rty
+#ifndef CONF_GMAC_NCFGR_RTY
+#define CONF_GMAC_NCFGR_RTY 0
+#endif
+
+// <q> Pause Enable
+// <i> When set, transmission will pause if a non-zero 802.3 classic pause
+// <i> frame is received and PFC has not been negotiated
+// <id> gmac_arch_ncfgr_pen
+#ifndef CONF_GMAC_NCFGR_PEN
+#define CONF_GMAC_NCFGR_PEN 0
+#endif
+
+// <o> Receive Buffer Offset <0-3>
+// <i> Indicates the number of bytes by which the received data is offset from
+// <i> the start of the receive buffer.
+// <id> gmac_arch_ncfgr_rxbufo
+#ifndef CONF_GMAC_NCFGR_RXBUFO
+#define CONF_GMAC_NCFGR_RXBUFO 0
+#endif
+
+// <q> Length Field Error Frame Discard
+// <i> Setting this bit causes frames with a measured length shorter than the
+// <i> extracted length field (as indicated by bytes 13 and 14 in a non-VLAN
+// <i> tagged frame) to be discarded. This only applies to frames with a length
+// <i> field less than 0x0600.
+// <id> gmac_arch_ncfgr_lferd
+#ifndef CONF_GMAC_NCFGR_LFERD
+#define CONF_GMAC_NCFGR_LFERD 0
+#endif
+
+// <q> Remove FCS
+// <i> Setting this bit will cause received frames to be written to memory
+// <i> without their frame check sequence (last 4 bytes). The frame length
+// <i> indicated will be reduced by four bytes in this mode.
+// <id> gmac_arch_ncfgr_rfcs
+#ifndef CONF_GMAC_NCFGR_RFCS
+#define CONF_GMAC_NCFGR_RFCS 0
+#endif
+
+// <o> MDC Clock Division
+// <i> Set according to MCK speed. These three bits determine the number MCK
+// <i> will be divided by to generate Management Data Clock (MDC). For
+// <i> conformance with the 802.3 specification, MDC must not exceed 2.5 MHz
+// <i> (MDC is only active during MDIO read and write operations).
+// <0=> 8
+// <1=> 16
+// <2=> 32
+// <3=> 48
+// <4=> 64
+// <5=> 96
+// <id> gmac_arch_ncfgr_clk
+#ifndef CONF_GMAC_NCFGR_CLK
+#define CONF_GMAC_NCFGR_CLK 4
+#endif
+
+/**
+ * For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz
+ **/
+#ifndef CONF_GMAC_MCK_FREQUENCY
+#if CONF_GMAC_NCFGR_CLK == 0
+#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 8)
+#elif CONF_GMAC_NCFGR_CLK == 1
+#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 16)
+#elif CONF_GMAC_NCFGR_CLK == 2
+#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 32)
+#elif CONF_GMAC_NCFGR_CLK == 3
+#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 48)
+#elif CONF_GMAC_NCFGR_CLK == 4
+#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 64)
+#elif CONF_GMAC_NCFGR_CLK == 5
+#define CONF_GMAC_MCK_FREQUENCY (CONF_GMAC_FREQUENCY / 96)
+#endif
+#endif
+
+#if CONF_GMAC_MCK_FREQUENCY > 2500000
+#warning For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz
+#endif
+// <q> Disable Copy of Pause Frames
+// <i> Set to one to prevent valid pause frames being copied to memory. When
+// <i> set, pause frames are not copied to memory regardless of the state of
+// <i> the Copy All Frames bit, whether a hash match is found or whether a
+// <i> type ID match is identified. If a destination address match is found,
+// <i> the pause frame will be copied to memory. Note that valid pause frames
+// <i> received will still increment pause statistics and pause the
+// <i> transmission of frames as required.
+// <id> gmac_arch_ncfgr_dcpf
+#ifndef CONF_GMAC_NCFGR_DCPF
+#define CONF_GMAC_NCFGR_DCPF 0
+#endif
+
+// <q> Receive Checksum Offload Enable
+// <i> When set, the receive checksum engine is enabled. Frames with bad IP,
+// <i> TCP or UDP checksums are discarded.
+// <id> gmac_arch_ncfgr_rxcoen
+#ifndef CONF_GMAC_NCFGR_RXCOEN
+#define CONF_GMAC_NCFGR_RXCOEN 0
+#endif
+
+// <q> Enable Frames Received in Half Duplex
+// <i> Enable frames to be received in half-duplex mode while transmittinga.
+// <id> gmac_arch_ncfgr_efrhd
+#ifndef CONF_GMAC_NCFGR_EFRHD
+#define CONF_GMAC_NCFGR_EFRHD 0
+#endif
+
+// <q> Ignore RX FCS
+// <i> When set, frames with FCS/CRC errors will not be rejected. FCS error
+// <i> statistics will still be collected for frames with bad FCS and FCS
+// <i> status will be recorded in frame's DMA descriptor. For normal operation
+// <i> this bit must be set to zero.
+// <id> gmac_arch_ncfgr_irxfcs
+#ifndef CONF_GMAC_NCFGR_IRXFCS
+#define CONF_GMAC_NCFGR_IRXFCS 0
+#endif
+
+// <q> IP Stretch Enable
+// <i> When set, the transmit IPG can be increased above 96 bit times depending
+// <i> on the previous frame length using the IPG Stretch Register.
+// <id> gmac_arch_ncfgr_ipgsen
+#ifndef CONF_GMAC_NCFGR_IPGSEN
+#define CONF_GMAC_NCFGR_IPGSEN 0
+#endif
+
+// <q> Receive Bad Preamble
+// <i> When set, frames with non-standard preamble are not rejected.
+// <id> gmac_arch_ncfgr_rxbp
+#ifndef CONF_GMAC_NCFGR_RXBP
+#define CONF_GMAC_NCFGR_RXBP 0
+#endif
+
+// <q> Ignore IPG GRXER
+// <i> When set, GRXER has no effect on the GMAC's operation when GRXDV is low.
+// <id> gmac_arch_ncfgr_irxer
+#ifndef CONF_GMAC_NCFGR_IRXER
+#define CONF_GMAC_NCFGR_IRXER 0
+#endif
+
+// </h>
+
+// <e> MII Configuration
+// <id> gmac_arch_mii_cfg
+
+// <o> MII Mode
+// <i> Select MII or RMII mode
+// <0=> RMII
+// <1=> MII
+// <id> gmac_arch_ur_mii
+#ifndef CONF_GMAC_ur_mii
+#define CONF_GMAC_UR_MII 0
+#endif
+
+// <o> PHY Clause Operation
+// <i> Chose which Clause operation will be used
+// <0=>Clause 45 Operation
+// <1=>Clause 22 Operation
+// <id> gmac_arch_cltto
+#ifndef CONF_GMAC_CLTTO
+#define CONF_GMAC_CLTTO 1
+#endif
+
+// </e>
+
+// <e> Stacked VLAN Processing
+// <i> When enabled, the first VLAN tag in a received frame will only be
+// <i> accepted if the VLAN type field is equal to the User defined VLAN Type,
+// <i> OR equal to the standard VLAN type (0x8100). Note that the second VLAN
+// <i> tag of a Stacked VLAN packet will only be matched correctly if its
+// <i> VLAN_TYPE field equals 0x8100.
+// <id> gmac_arch_svlan_enable
+#ifndef CONF_GMAC_SVLAN_ENABLE
+#define CONF_GMAC_SVLAN_ENABLE 0
+#endif
+
+// <o> User Defined VLAN Type <0x0-0xFFFF>
+// <i> User defined VLAN TYPE
+// <id> gmac_arch_svlan_type
+#ifndef CONF_GMAC_SVLAN_TYPE
+#define CONF_GMAC_SVLAN_TYPE 0x8100
+#endif
+// </e>
+
+// <e> DMA Configuration
+// <i> The GMAC DMA controller is connected to the MAC FIFO interface and
+// <i> provides a scatter-gather type capability for packet data storage.
+// <i> The DMA implements packet buffering where dual-port memories are used
+// <i> to buffer multiple frames.
+// <id> gmac_arch_dma_cfg
+#ifndef CONF_GMAC_DMA_CFG
+#define CONF_GMAC_DMACFG 1
+#endif
+
+// <o> Fixed Burst Length for DMA Data Operations
+// <i> Selects the burst length to attempt to use on the AHB when transferring
+// <i> frame data. Not used for DMA management operations and only used where
+// <i> space and data size allow. Otherwise SINGLE type AHB transfers are used.
+// <1=> Always use SINGLE AHB bursts
+// <4=> Always use INCR4 AHB bursts
+// <8=> Always use INCR8 AHB bursts
+// <16=> Always use INCR16 AHB bursts
+// <id> gmac_arch_dcfgr_fbldo
+#ifndef CONF_GMAC_DCFGR_FBLDO
+#define CONF_GMAC_DCFGR_FBLDO 4
+#endif
+
+// <q> Endian Swap Mode Enable for Management Descriptor Accesses
+// <i> When set, selects swapped endianism for AHB transfers. When clear,
+// <i> selects little endian mode.
+// <id> gmac_arch_dcfgr_esma
+#ifndef CONF_GMAC_DCFGR_ESMA
+#define CONF_GMAC_DCFGR_ESMA 0
+#endif
+
+// <q> Endian Swap Mode Enable for Packet Data Accesses
+// <i> When set, selects swapped endianism for AHB transfers. When clear,
+// <i> selects little endian mode.
+// <id> gmac_arch_dcfgr_espa
+#ifndef CONF_GMAC_DCFGR_ESPA
+#define CONF_GMAC_DCFGR_ESPA 0
+#endif
+
+// <o> Receiver Packet Buffer Memory Size Select
+// <i> Select the receive packet buffer size
+// <0=> 0.5 Kbytes
+// <1=> 1 Kbytes
+// <2=> 2 Kbytes
+// <3=> 4 Kbytes
+// <id> gmac_arch_dcfgr_rxbms
+#ifndef CONF_GMAC_DCFGR_RXBMS
+#define CONF_GMAC_DCFGR_RXBMS 3
+#endif
+
+// <o> Transmitter Packet Buffer Memory Size Select
+// <i> Select the Transmitter packet buffer size
+// <0=> 2 Kbytes
+// <1=> 4 Kbytes
+// <id> gmac_arch_dcfgr_txpbms
+#ifndef CONF_GMAC_DCFGR_TXPBMS
+#define CONF_GMAC_DCFGR_TXPBMS 1
+#endif
+
+// <q> Transmitter Checksum Generation Offload Enable
+// <i> Transmitter IP, TCP and UDP checksum generation offload enable. When
+// <i> set, the transmitter checksum generation engine is enabled to calculate
+// <i> and substitute checksums for transmit frames. When clear, frame data is
+// <i> unaffected
+// <id> gmac_arch_dcfgr_txcoen
+#ifndef CONF_GMAC_DCFGR_TXCOEN
+#define CONF_GMAC_DCFGR_TXCOEN 0
+#endif
+
+// <o> DMA Receive Buffer Size <1-255>
+// <i> DMA receive buffer size in AHB system memory. The value defined by these
+// <i> bits determines the size of buffer to use in main AHB system memory when
+// <i> writing received data. The value is defined in multiples of 64 bytes,
+// <i> thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02
+// <i> corresponds to 128 bytes etc.
+// <id> gmac_arch_dcfgr_drbs
+#ifndef CONF_GMAC_DCFGR_DRBS
+#define CONF_GMAC_DCFGR_DRBS 2
+#endif
+
+// <q> DMA Discard Received Packets
+// <i> When set, the GMAC DMA will automatically discard receive packets from
+// <i> the receiver packet buffer memory when no AHB resource is available.
+// <i> When low, the received packets will remain to be stored in the SRAM
+// <i> based packet buffer until AHB buffer resource next becomes available.
+// <i> Note: packet buffer full store and forward mode should be enabled.
+// <id> gmac_arch_dcfgr_ddrp
+#ifndef CONF_GMAC_DCFGR_DDRP
+#define CONF_GMAC_DCFGR_DDRP 0
+#endif
+// </e>
+
+// <e> Advanced configuration
+// <id> gmac_arch_adv_cfg
+#ifndef CONF_GMAC_ADV_CFG
+#define CONF_GMAC_ADV_CFG 1
+#endif
+
+// <o> Number of Transmit Buffer Descriptor <1-255>
+// <i> Number of Transmit Buffer Descriptor
+// <id> gmac_arch_txdescr_num
+#ifndef CONF_GMAC_TXDESCR_NUM
+#define CONF_GMAC_TXDESCR_NUM 2
+#endif
+
+// <o> Number of Receive Buffer Descriptor <1-255>
+// <i> Number of Receive Buffer Descriptor
+// <id> gmac_arch_rxdescr_num
+#ifndef CONF_GMAC_RXDESCR_NUM
+#define CONF_GMAC_RXDESCR_NUM 16
+#endif
+
+// <o> Byte size of Transmit Buffer <64-10240>
+// <i> Byte size of buffer for each transmit buffer descriptor.
+// <id> gmac_arch_txbuf_size
+#ifndef CONF_GMAC_TXBUF_SIZE
+#define CONF_GMAC_TXBUF_SIZE 1500
+#endif
+
+#ifndef CONF_GMAC_RXBUF_SIZE
+#define CONF_GMAC_RXBUF_SIZE (CONF_GMAC_DCFGR_DRBS * 64)
+#endif
+
+// <e> Enable Transmit Partial Store and Forward
+// <i> This allows for a reduced latency but there are performance implications.
+// <id> gmac_arch_tpsf_en
+#ifndef CONF_GMAC_TPSF_EN
+#define CONF_GMAC_TPSF_EN 0
+#endif
+
+// <o> Watermark <20-4095>
+// <i> Byte size of buffer for each transmit buffer descriptor.
+// <id> gmac_arch_tpsf_wm
+#ifndef CONF_GMAC_TPSF_WM
+#define CONF_GMAC_TPSF_WM 100
+#endif
+// </e>
+
+// <e> Enable Receive Partial Store and Forward
+// <i> This allows for a reduced latency but there are performance implications.
+// <id> gmac_arch_rpsf_en
+#ifndef CONF_GMAC_RPSF_EN
+#define CONF_GMAC_RPSF_EN 0
+#endif
+
+// <o> Watermark <20-4095>
+// <i> Byte size of buffer for each transmite buffer descriptor.
+// <id> gmac_arch_rpsf_wm
+#ifndef CONF_GMAC_RPSF_WM
+#define CONF_GMAC_RPSF_WM 100
+#endif
+
+// <o> IPG Stretch Multiple <0-15>
+// <i> This value will multiplied with the previously transmitted frame length
+// <i> (including preamble)
+// <id> gmac_arch_ipgs_fl_mul
+#ifndef CONF_GMAC_IPGS_FL_MUL
+#define CONF_GMAC_IPGS_FL_MUL 1
+#endif
+
+// <o> IPG Stretch Divide <1-16>
+// <i> Divide the frame length. If the resulting number is greater than 96 and
+// <i> IP Stretch Enabled then the resulting number is used for the transmit
+// <i> inter-packet-gap
+// <id> gmac_arch_ipgs_fl_div
+#ifndef CONF_GMAC_IPGS_FL_DIV
+#define CONF_GMAC_IPGS_FL_DIV 1
+#endif
+
+// </e>
+
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // HPL_GMAC_CONFIG_H

bsp/microchip/same54/bsp/config/hpl_sercom_config.h

@@ -69,7 +69,7 @@
 // <e> Advanced configuration
 // <id> usart_advanced
 #ifndef CONF_SERCOM_2_USART_ADVANCED_CONFIG
-#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 0
+#define CONF_SERCOM_2_USART_ADVANCED_CONFIG 1
 #endif
 
 // <q> Run in stand-by
@@ -273,6 +273,141 @@
 #endif
 #endif
 
+#include <peripheral_clk_config.h>
+
+#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
+#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
+#endif
+
+#ifndef CONF_SERCOM_7_I2CM_ENABLE
+#define CONF_SERCOM_7_I2CM_ENABLE 1
+#endif
+
+// <h> Basic
+
+// <o> I2C Bus clock speed (Hz) <1-400000>
+// <i> I2C Bus clock (SCL) speed measured in Hz
+// <id> i2c_master_baud_rate
+#ifndef CONF_SERCOM_7_I2CM_BAUD
+#define CONF_SERCOM_7_I2CM_BAUD 100000
+#endif
+
+// </h>
+
+// <e> Advanced
+// <id> i2c_master_advanced
+#ifndef CONF_SERCOM_7_I2CM_ADVANCED_CONFIG
+#define CONF_SERCOM_7_I2CM_ADVANCED_CONFIG 1
+#endif
+
+// <o> TRise (ns) <0-300>
+// <i> Determined by the bus impedance, check electric characteristics in the datasheet
+// <i> Standard Fast Mode: typical 215ns, max 300ns
+// <i> Fast Mode +: typical 60ns, max 100ns
+// <i> High Speed Mode: typical 20ns, max 40ns
+// <id> i2c_master_arch_trise
+
+#ifndef CONF_SERCOM_7_I2CM_TRISE
+#define CONF_SERCOM_7_I2CM_TRISE 215
+#endif
+
+// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
+// <i> This enables the master SCL low extend time-out
+// <id> i2c_master_arch_mexttoen
+#ifndef CONF_SERCOM_7_I2CM_MEXTTOEN
+#define CONF_SERCOM_7_I2CM_MEXTTOEN 1
+#endif
+
+// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
+// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
+// <id> i2c_master_arch_sexttoen
+#ifndef CONF_SERCOM_7_I2CM_SEXTTOEN
+#define CONF_SERCOM_7_I2CM_SEXTTOEN 0
+#endif
+
+// <q> SCL Low Time-Out (LOWTOUT)
+// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
+// <id> i2c_master_arch_lowtout
+#ifndef CONF_SERCOM_7_I2CM_LOWTOUT
+#define CONF_SERCOM_7_I2CM_LOWTOUT 1
+#endif
+
+// <o> Inactive Time-Out (INACTOUT)
+// <0x0=>Disabled
+// <0x1=>5-6 SCL cycle time-out(50-60us)
+// <0x2=>10-11 SCL cycle time-out(100-110us)
+// <0x3=>20-21 SCL cycle time-out(200-210us)
+// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
+// <id> i2c_master_arch_inactout
+#ifndef CONF_SERCOM_7_I2CM_INACTOUT
+#define CONF_SERCOM_7_I2CM_INACTOUT 0x3
+#endif
+
+// <o> SDA Hold Time (SDAHOLD)
+// <0=>Disabled
+// <1=>50-100ns hold time
+// <2=>300-600ns hold time
+// <3=>400-800ns hold time
+// <i> Defines the SDA hold time with respect to the negative edge of SCL
+// <id> i2c_master_arch_sdahold
+#ifndef CONF_SERCOM_7_I2CM_SDAHOLD
+#define CONF_SERCOM_7_I2CM_SDAHOLD 0x2
+#endif
+
+// <q> Run in stand-by
+// <i> Determine if the module shall run in standby sleep mode
+// <id> i2c_master_arch_runstdby
+#ifndef CONF_SERCOM_7_I2CM_RUNSTDBY
+#define CONF_SERCOM_7_I2CM_RUNSTDBY 0
+#endif
+
+// <o> Debug Stop Mode
+// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
+// <0=>Keep running
+// <1=>Halt
+// <id> i2c_master_arch_dbgstop
+#ifndef CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE
+#define CONF_SERCOM_7_I2CM_DEBUG_STOP_MODE 0
+#endif
+
+// </e>
+
+#ifndef CONF_SERCOM_7_I2CM_SPEED
+#define CONF_SERCOM_7_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
+#endif
+#if CONF_SERCOM_7_I2CM_TRISE < 215 || CONF_SERCOM_7_I2CM_TRISE > 300
+#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
+#undef CONF_SERCOM_7_I2CM_TRISE
+#define CONF_SERCOM_7_I2CM_TRISE 215U
+#endif
+
+//                  gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
+// BAUD + BAUDLOW = --------------------------------------------------------------------
+//                  i2c_scl_freq
+// BAUD:    register value low  [7:0]
+// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
+#define CONF_SERCOM_7_I2CM_BAUD_BAUDLOW                                                                                \
+	(((CONF_GCLK_SERCOM7_CORE_FREQUENCY - (CONF_SERCOM_7_I2CM_BAUD * 10U)                                              \
+	   - (CONF_SERCOM_7_I2CM_TRISE * (CONF_SERCOM_7_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM7_CORE_FREQUENCY / 10000U)    \
+	      / 1000U))                                                                                                    \
+	      * 10U                                                                                                        \
+	  + 5U)                                                                                                            \
+	 / (CONF_SERCOM_7_I2CM_BAUD * 10U))
+#ifndef CONF_SERCOM_7_I2CM_BAUD_RATE
+#if CONF_SERCOM_7_I2CM_BAUD_BAUDLOW > (0xFF * 2)
+#warning Requested I2C baudrate too low, please check
+#define CONF_SERCOM_7_I2CM_BAUD_RATE 0xFF
+#elif CONF_SERCOM_7_I2CM_BAUD_BAUDLOW <= 1
+#warning Requested I2C baudrate too high, please check
+#define CONF_SERCOM_7_I2CM_BAUD_RATE 1
+#else
+#define CONF_SERCOM_7_I2CM_BAUD_RATE                                                                                   \
+	((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW & 0x1)                                                                           \
+	     ? (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2 + 1) << 8)                    \
+	     : (CONF_SERCOM_7_I2CM_BAUD_BAUDLOW / 2))
+#endif
+#endif
+
 // <<< end of configuration section >>>
 
 #endif // HPL_SERCOM_CONFIG_H

bsp/microchip/same54/bsp/config/ieee8023_mii_standard_config.h

@@ -0,0 +1,106 @@
+/* Auto-generated config file ieee8023_mii_standard_config.h */
+#ifndef IEEE8023_MII_STANDARD_CONFIG_H
+#define IEEE8023_MII_STANDARD_CONFIG_H
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Basic configuration
+
+// <o> PHY Address <0-31>
+// <i> The PHY Address is five bits, allowing 32 unique PHY addresses. A PHY
+// <i> that is connected to the station management entity via the mechanical
+// <i> interface defined in IEEE 802.3 22.6 shall always respond to
+// <i> transactions addressed to PHY Address zero b00000. A station management
+// <i> entity that is attached to multiple PHYs must have prior knowledge of
+// <i> the appropriate PHY Address for each PHY.
+// <id> ieee8023_mii_phy_address
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS
+#define CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS 0
+#endif
+
+// </h>
+
+// <e> Control Register (Register 0) Settings
+// <i> The MII Management Interface Control Register (Register 0) Setting.
+// <i> Full details about the can be found in Clause 22.2.4 of the IEEE 802.3
+// <i> Specification.
+// <id> ieee8023_mii_control_reg0_setting
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING 1
+#endif
+
+// <q> Loopback Enable
+// <i> Set PHY be placed in a loopback mode of operation.
+// <id> ieee8023_mii_control_loopback_en
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN 0
+#endif
+
+// <o> Speed Selection
+// <i> These bits select the PHY speed.
+// <0x0=> 10 Mb/s
+// <0x1=> 100 Mb/s
+// <0x2=> 1000 Mb/s
+// <id> ieee8023_mii_control_speed_lsb
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED 1
+#endif
+
+// <q> Auto-Negotiation Enable
+// <i> Indicates whether the Auto-Negotiation enable or not
+// <id> ieee8023_mii_control_autoneg_en
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN 1
+#endif
+
+// <q> Power Down Enable
+// <i> Set PHY in a low-power consumption state, The specific behavior of a
+// <i> PHY in the power-down state is implementation specific. While in the
+// <i> power-down state, the PHY shall respond to management transactions.
+// <i> During the transition to the power-down state and while in the
+// <i> power-down state, the PHY shall not generate spurious signals on the
+// <i> MII or GMII.
+// <id> ieee8023_mii_control_powerdown_en
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN 0
+#endif
+
+// <q> Isolate Enable
+// <i> Set PHY forced to electrically isolate its data paths from the MII or
+// <i> GMII. When the PHY is isolated from the MII or GMII it shall not
+// <i> respond to the TXD data bundle, TX_EN, TX_ER and GTX_CLK inputs, and it
+// <i> shall present a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD
+// <i> data bundle, COL, and CRS outputs. When the PHY is isolated from the
+// <i> MII or GMII it shall respond to management transactions.
+// <id> ieee8023_mii_control_isolate_en
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN 0
+#endif
+
+// <o> Duplex Mode Selection
+// <i> The duplex mode can be selected via either the Auto-Negotiation enable,
+// <i> or manual duplex selection. Manual duplex selection is allowed when
+// <i> Auto-Negotiation is disabled. When Auto-Negotiation is enabled, this
+// <i> setting has no effect on the link configuration.
+// <0x0=> half duplex
+// <0x1=> full duplex
+// <id> ieee8023_mii_control_duplex_mode
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE 1
+#endif
+
+#ifndef CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0
+#define CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0                                                                       \
+	(CONF_MACIF_PHY_IEEE8023_MII_CONTROL_LOOPBACK_EN ? MDIO_REG0_BIT_RESET : 0)                                        \
+	    | ((CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED & 0x1) ? MDIO_REG0_BIT_SPEED_SELECT_LSB : 0)                     \
+	    | ((CONF_MACIF_PHY_IEEE8023_MII_CONTROL_SPEED & 0x2) ? MDIO_REG0_BIT_SPEED_SELECT_MSB : 0)                     \
+	    | (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_AUTONEG_EN ? MDIO_REG0_BIT_AUTONEG : 0)                                 \
+	    | (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_POWER_DOWN_EN ? MDIO_REG0_BIT_POWER_DOWN : 0)                           \
+	    | (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_ISOLATE_EN ? MDIO_REG0_BIT_ISOLATE : 0)                                 \
+	    | (CONF_MACIF_PHY_IEEE8023_MII_CONTROL_DUPLEX_MODE ? MDIO_REG0_BIT_DUPLEX_MODE : 0)
+#endif
+// </e>
+
+// <<< end of configuration section >>>
+
+#endif // IEEE8023_MII_STANDARD_CONFIG_H

bsp/microchip/same54/bsp/config/peripheral_clk_config.h

@@ -4,6 +4,46 @@
 
 // <<< Use Configuration Wizard in Context Menu >>>
 
+// <y> ADC Clock Source
+// <id> adc_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for ADC.
+#ifndef CONF_GCLK_ADC0_SRC
+#define CONF_GCLK_ADC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
+#endif
+
+/**
+ * \def CONF_GCLK_ADC0_FREQUENCY
+ * \brief ADC0's Clock frequency
+ */
+#ifndef CONF_GCLK_ADC0_FREQUENCY
+#define CONF_GCLK_ADC0_FREQUENCY 120000000
+#endif
+
 /**
  * \def CONF_CPU_FREQUENCY
  * \brief CPU's Clock frequency
@@ -92,6 +132,86 @@
 #define CONF_GCLK_SERCOM2_SLOW_FREQUENCY 3000000
 #endif
 
+// <y> Core Clock Source
+// <id> core_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the clock source for CORE.
+#ifndef CONF_GCLK_SERCOM7_CORE_SRC
+#define CONF_GCLK_SERCOM7_CORE_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
+#endif
+
+// <y> Slow Clock Source
+// <id> slow_gclk_selection
+
+// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
+
+// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
+
+// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
+
+// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
+
+// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
+
+// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
+
+// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
+
+// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
+
+// <GCLK_PCHCTRL_GEN_GCLK8_Val"> Generic clock generator 8
+
+// <GCLK_PCHCTRL_GEN_GCLK9_Val"> Generic clock generator 9
+
+// <GCLK_PCHCTRL_GEN_GCLK10_Val"> Generic clock generator 10
+
+// <GCLK_PCHCTRL_GEN_GCLK11_Val"> Generic clock generator 11
+
+// <i> Select the slow clock source.
+#ifndef CONF_GCLK_SERCOM7_SLOW_SRC
+#define CONF_GCLK_SERCOM7_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK1_Val
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM7_CORE_FREQUENCY
+ * \brief SERCOM7's Core Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM7_CORE_FREQUENCY
+#define CONF_GCLK_SERCOM7_CORE_FREQUENCY 40000000
+#endif
+
+/**
+ * \def CONF_GCLK_SERCOM7_SLOW_FREQUENCY
+ * \brief SERCOM7's Slow Clock frequency
+ */
+#ifndef CONF_GCLK_SERCOM7_SLOW_FREQUENCY
+#define CONF_GCLK_SERCOM7_SLOW_FREQUENCY 3000000
+#endif
+
 // <y> CAN1 Clock Source
 // <id> can_gclk_selection
 

bsp/microchip/same54/bsp/documentation/ethernet_phy.rst

@@ -0,0 +1,56 @@
+======================================
+Generic IEEE 802.3 Ethernet PHY Driver
+======================================
+
+This software component supply a generic IEEE802.3 Ethernet PHY driver.
+The PHY chip should be compliant IEEE 802.3 Ethernet Standard that
+supports MDC/MDIO management interface for PHY register configuration.
+
+The management interface specified here provides a simple, two-wire, serial
+interface to connect a management entity and a managed PHY for the purposes of
+controlling the PHY and gathering status from the PHY. This interface is
+referred to as the MII Management Interface.
+
+The management interface consists of a pair of signals that physically
+transport the management information across the MII or GMII, a frame format
+and a protocol specification for exchanging management frames, and a register
+set that can be read and written using these frames. The register definition 
+specifies a basic register set with an extension mechanism. The MII uses two
+basic registers. The GMII also uses the same two basic registers and adds a
+third basic register.
+
+The MII basic register set consists of two registers referred to as the Control
+register (Register 0) and the Status register (Register 1). All PHYs that
+provide an MII shall incorporate the basic register set. All PHYs that provide
+a GMII shall incorporate an extended basic register set consisting of the
+Control register (Register 0), Status register (Register 1), and Extended
+Status register (Register 15). The status and control functions defined here
+are considered basic and fundamental to 100 Mb/s and 1000 Mb/s PHYs.
+Registers 2 through 14 are part of the extended register set. The format of
+Registers 4 through 10 are defined for the specific Auto-Negotiation protocol
+used (Clause 28 or Clause 37). The format of these registers is selected by
+the bit settings of Registers 1 and 15.
+More information please refer to IEEE Std 802.3 Chapter 22.2.4
+
+Features
+--------
+
+* Initialization the Ethernet PHY driver with Ethernet MAC communication
+* Setting PHY address
+* Reading/Writing register from PHY device
+* Setting/Clearing register bit from PHY device
+* Enabling/Disabling Power Down
+* Restart Auto Negotiation
+* Enabling/Disabling Loop Back
+* Getting Link Status
+* Reset PHY device
+
+Dependencies
+------------
+
+* An instance of the Ethernet MAC driver is used by this driver.
+
+Limitations
+-----------
+
+N/A

bsp/microchip/same54/bsp/driver_init.c

@@ -11,10 +11,44 @@
 #include <utils.h>
 #include <hal_init.h>
 
-struct aes_sync_descriptor  CRYPTOGRAPHY_0;
-struct can_async_descriptor CAN_0;
+#include <hpl_adc_base.h>
 
-struct usart_sync_descriptor TARGET_IO;
+/*! The buffer size for USART */
+#define TARGET_IO_BUFFER_SIZE 16
+
+struct aes_sync_descriptor    CRYPTOGRAPHY_0;
+struct usart_async_descriptor TARGET_IO;
+struct can_async_descriptor   CAN_0;
+
+static uint8_t TARGET_IO_buffer[TARGET_IO_BUFFER_SIZE];
+
+struct adc_sync_descriptor ADC_0;
+
+struct i2c_m_sync_desc I2C_0;
+
+struct mac_async_descriptor MACIF;
+
+void ADC_0_PORT_init(void)
+{
+
+	// Disable digital pin circuitry
+	gpio_set_pin_direction(PA02, GPIO_DIRECTION_OFF);
+
+	gpio_set_pin_function(PA02, PINMUX_PA02B_ADC0_AIN0);
+}
+
+void ADC_0_CLOCK_init(void)
+{
+	hri_mclk_set_APBDMASK_ADC0_bit(MCLK);
+	hri_gclk_write_PCHCTRL_reg(GCLK, ADC0_GCLK_ID, CONF_GCLK_ADC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+}
+
+void ADC_0_init(void)
+{
+	ADC_0_CLOCK_init();
+	ADC_0_PORT_init();
+	adc_sync_init(&ADC_0, ADC0, (void *)NULL);
+}
 
 /**
  * \brief AES initialization function
@@ -27,29 +61,84 @@ void CRYPTOGRAPHY_0_init(void)
 	aes_sync_init(&CRYPTOGRAPHY_0, AES);
 }
 
-void TARGET_IO_PORT_init(void)
+/**
+ * \brief USART Clock initialization function
+ *
+ * Enables register interface and peripheral clock
+ */
+void TARGET_IO_CLOCK_init()
 {
 
-	gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 
-	gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
+	hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
 }
 
-void TARGET_IO_CLOCK_init(void)
+/**
+ * \brief USART pinmux initialization function
+ *
+ * Set each required pin to USART functionality
+ */
+void TARGET_IO_PORT_init()
 {
-	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
-	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
 
-	hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK);
+	gpio_set_pin_function(PB25, PINMUX_PB25D_SERCOM2_PAD0);
+
+	gpio_set_pin_function(PB24, PINMUX_PB24D_SERCOM2_PAD1);
 }
 
+/**
+ * \brief USART initialization function
+ *
+ * Enables USART peripheral, clocks and initializes USART driver
+ */
 void TARGET_IO_init(void)
 {
 	TARGET_IO_CLOCK_init();
-	usart_sync_init(&TARGET_IO, SERCOM2, (void *)NULL);
+	usart_async_init(&TARGET_IO, SERCOM2, TARGET_IO_buffer, TARGET_IO_BUFFER_SIZE, (void *)NULL);
 	TARGET_IO_PORT_init();
 }
 
+void I2C_0_PORT_init(void)
+{
+
+	gpio_set_pin_pull_mode(PD08,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PD08, PINMUX_PD08C_SERCOM7_PAD0);
+
+	gpio_set_pin_pull_mode(PD09,
+	                       // <y> Pull configuration
+	                       // <id> pad_pull_config
+	                       // <GPIO_PULL_OFF"> Off
+	                       // <GPIO_PULL_UP"> Pull-up
+	                       // <GPIO_PULL_DOWN"> Pull-down
+	                       GPIO_PULL_OFF);
+
+	gpio_set_pin_function(PD09, PINMUX_PD09C_SERCOM7_PAD1);
+}
+
+void I2C_0_CLOCK_init(void)
+{
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM7_GCLK_ID_CORE, CONF_GCLK_SERCOM7_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+	hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM7_GCLK_ID_SLOW, CONF_GCLK_SERCOM7_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
+
+	hri_mclk_set_APBDMASK_SERCOM7_bit(MCLK);
+}
+
+void I2C_0_init(void)
+{
+	I2C_0_CLOCK_init();
+	i2c_m_sync_init(&I2C_0, SERCOM7);
+	I2C_0_PORT_init();
+}
+
 void CAN_0_PORT_init(void)
 {
 
@@ -70,6 +159,49 @@ void CAN_0_init(void)
 	CAN_0_PORT_init();
 }
 
+void MACIF_PORT_init(void)
+{
+
+	gpio_set_pin_function(PC11, PINMUX_PC11L_GMAC_GMDC);
+
+	gpio_set_pin_function(PC12, PINMUX_PC12L_GMAC_GMDIO);
+
+	gpio_set_pin_function(PA13, PINMUX_PA13L_GMAC_GRX0);
+
+	gpio_set_pin_function(PA12, PINMUX_PA12L_GMAC_GRX1);
+
+	gpio_set_pin_function(PC20, PINMUX_PC20L_GMAC_GRXDV);
+
+	gpio_set_pin_function(PA15, PINMUX_PA15L_GMAC_GRXER);
+
+	gpio_set_pin_function(PA18, PINMUX_PA18L_GMAC_GTX0);
+
+	gpio_set_pin_function(PA19, PINMUX_PA19L_GMAC_GTX1);
+
+	gpio_set_pin_function(PA14, PINMUX_PA14L_GMAC_GTXCK);
+
+	gpio_set_pin_function(PA17, PINMUX_PA17L_GMAC_GTXEN);
+}
+
+void MACIF_CLOCK_init(void)
+{
+	hri_mclk_set_AHBMASK_GMAC_bit(MCLK);
+	hri_mclk_set_APBCMASK_GMAC_bit(MCLK);
+}
+
+void MACIF_init(void)
+{
+	MACIF_CLOCK_init();
+	mac_async_init(&MACIF, GMAC);
+	MACIF_PORT_init();
+}
+
+void MACIF_example(void)
+{
+	mac_async_enable(&MACIF);
+	mac_async_write(&MACIF, (uint8_t *)"Hello World!", 12);
+}
+
 void system_init(void)
 {
 	init_mcu();
@@ -88,8 +220,13 @@ void system_init(void)
 
 	gpio_set_pin_function(LED0, GPIO_PIN_FUNCTION_OFF);
 
+	ADC_0_init();
 	CRYPTOGRAPHY_0_init();
 
 	TARGET_IO_init();
+
+	I2C_0_init();
 	CAN_0_init();
+
+	MACIF_init();
 }

bsp/microchip/same54/bsp/driver_init.h

@@ -21,20 +21,42 @@ extern "C" {
 #include <hal_io.h>
 #include <hal_sleep.h>
 
+#include <hal_adc_sync.h>
 #include <hal_aes_sync.h>
 
-#include <hal_usart_sync.h>
+#include <hal_usart_async.h>
+
+#include <hal_i2c_m_sync.h>
 #include <hal_can_async.h>
 
-extern struct aes_sync_descriptor CRYPTOGRAPHY_0;
+#include <hal_mac_async.h>
+
+extern struct adc_sync_descriptor    ADC_0;
+extern struct aes_sync_descriptor    CRYPTOGRAPHY_0;
+extern struct usart_async_descriptor TARGET_IO;
+
+extern struct i2c_m_sync_desc      I2C_0;
+extern struct can_async_descriptor CAN_0;
 
-extern struct usart_sync_descriptor TARGET_IO;
-extern struct can_async_descriptor  CAN_0;
+extern struct mac_async_descriptor MACIF;
+
+void ADC_0_PORT_init(void);
+void ADC_0_CLOCK_init(void);
+void ADC_0_init(void);
 
 void TARGET_IO_PORT_init(void);
 void TARGET_IO_CLOCK_init(void);
 void TARGET_IO_init(void);
 
+void I2C_0_CLOCK_init(void);
+void I2C_0_init(void);
+void I2C_0_PORT_init(void);
+
+void MACIF_CLOCK_init(void);
+void MACIF_init(void);
+void MACIF_PORT_init(void);
+void MACIF_example(void);
+
 /**
  * \brief Perform system initialization, initialize pins and clocks for
  * peripherals

bsp/microchip/same54/bsp/ethernet_phy/ethernet_phy.c

@@ -0,0 +1,184 @@
+/**
+ * \file
+ *
+ * \brief Ethernet PHY functionality implementation.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#include <ethernet_phy.h>
+#include <utils_assert.h>
+/**
+ * \brief Perform a HW initialization to the PHY
+ */
+int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
+                          uint16_t addr)
+{
+	ASSERT(descr && mac && (addr <= 0x1F));
+
+	descr->mac  = mac;
+	descr->addr = addr;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Set PHY address
+ */
+int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr)
+{
+	ASSERT(descr && (addr <= 0x1F));
+
+	descr->addr = addr;
+	return ERR_NONE;
+}
+
+/**
+ * \brief Read PHY Register value.
+ */
+int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val)
+{
+	ASSERT(descr && descr->mac && (reg <= 0x1F) && val);
+
+	return mac_async_read_phy_reg(descr->mac, descr->addr, reg, val);
+}
+
+/**
+ * \brief Write PHY Register value.
+ */
+int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val)
+{
+	ASSERT(descr && descr->mac && (reg <= 0x1F));
+	return mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
+}
+
+/**
+ * \brief Setting bit for a PHY Register
+ */
+int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
+{
+	int32_t  rst;
+	uint16_t val;
+
+	ASSERT(descr && descr->mac && (reg <= 0x1F));
+
+	rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
+	if (rst == ERR_NONE) {
+		val |= ofst;
+		rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
+	}
+	return rst;
+}
+/**
+ * \brief Clear bit for a PHY Register
+ */
+int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst)
+{
+	int32_t  rst;
+	uint16_t val;
+
+	ASSERT(descr && (reg <= 0x1F));
+
+	rst = mac_async_read_phy_reg(descr->mac, descr->addr, reg, &val);
+	if (rst == ERR_NONE) {
+		val &= ~ofst;
+		rst = mac_async_write_phy_reg(descr->mac, descr->addr, reg, val);
+	}
+	return rst;
+}
+/**
+ * \brief Set PHY low-power consumption state.
+ */
+int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state)
+{
+	ASSERT(descr);
+	if (state) {
+		return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
+	} else {
+		return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_POWER_DOWN);
+	}
+}
+
+/**
+ * \brief Set PHY electrically isolate state.
+ */
+int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state)
+{
+	ASSERT(descr);
+	if (state) {
+		return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
+	} else {
+		return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_ISOLATE);
+	}
+}
+
+/**
+ * \brief Restart an auto negotiation of the PHY.
+ */
+int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr)
+{
+	ASSERT(descr);
+	return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESTART_AUTONEG);
+}
+
+/**
+ * \brief Set PHY placed in a loopback mode of operation.
+ */
+int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state)
+{
+	ASSERT(descr);
+	if (state) {
+		return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
+	} else {
+		return ethernet_phy_clear_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_LOOPBACK);
+	}
+}
+
+/**
+ * \brief Get PHY link status
+ */
+int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status)
+{
+	int32_t  rst;
+	uint16_t val;
+
+	ASSERT(descr && descr->mac && status);
+	rst = mac_async_read_phy_reg(descr->mac, descr->addr, MDIO_REG1_BMSR, &val);
+	if (rst == ERR_NONE) {
+		*status = (val & MDIO_REG1_BIT_LINK_STATUS) ? true : false;
+	}
+	return rst;
+}
+
+/**
+ * \brief Reset PHY.
+ */
+int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr)
+{
+	ASSERT(descr);
+	return ethernet_phy_set_reg_bit(descr, MDIO_REG0_BMCR, MDIO_REG0_BIT_RESET);
+}

bsp/microchip/same54/bsp/ethernet_phy/ethernet_phy.h

@@ -0,0 +1,230 @@
+/**
+ * \file
+ *
+ * \brief Ethernet PHY functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ETHERNET_PHY_H_INCLUDED
+#define ETHERNET_PHY_H_INCLUDED
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "compiler.h"
+#include "hal_mac_async.h"
+#include "ieee8023_mii_standard_register.h"
+
+struct ethernet_phy_descriptor {
+	struct mac_async_descriptor *mac;  /* MAC descriptor handler */
+	uint16_t                     addr; /* PHY address, defined by IEEE802.3
+	                                      section 22.2.4.5.5 */
+};
+
+/**
+ * \brief Perform a HW initialization to the PHY
+ *
+ * This should be called only once to initialize the PHY pre-settings.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] mac   MAC descriptor, the descriptor should be initialized.
+ * \param[in] addr  Ethernet PHY 5 bits address.
+ *
+ * \return Operation result
+ * \retval ERR_NONE initializing successful.
+ */
+int32_t ethernet_phy_init(struct ethernet_phy_descriptor *const descr, struct mac_async_descriptor *const mac,
+                          uint16_t addr);
+
+/**
+ * \brief Set PHY address
+ *
+ * Set PHY management PHY address which defined by IEEE802.3 section 22.2.4.5.5
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] addr  PHY address
+ *
+ * \return Operation result
+ * \retval ERR_NONE Set address successful.
+ */
+int32_t ethernet_phy_set_address(struct ethernet_phy_descriptor *const descr, uint16_t addr);
+
+/**
+ * \brief Read PHY Register value.
+ *
+ * Read PHY Register value from PHY.
+ *
+ * \note For conformance with the 802.3 specification, MDC must not exceed
+ *       2.5 MHz (MDC is only active during MDIO read and write operations).
+ *       The function execution time depend on MDC frequency.
+ *
+ * \param[in]  descr Ethernet PHY descriptor.
+ * \param[in]  reg   Register address
+ * \param[out] val   Register value
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Read register successful.
+ */
+int32_t ethernet_phy_read_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t *val);
+
+/**
+ * \brief Write PHY Register value.
+ *
+ * Read PHY Register value from PHY.
+ *
+ * \note For conformance with the 802.3 specification, MDC must not exceed
+ *       2.5 MHz (MDC is only active during MDIO read and write operations).
+ *       The function execution time depend on MDC frequency.
+ *
+ * \param[in]  descr Ethernet PHY descriptor.
+ * \param[in]  reg   Register address
+ * \param[out] val   Register value
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Write register successful.
+ */
+int32_t ethernet_phy_write_reg(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t val);
+
+/**
+ * \brief Setting bit for a PHY Register
+ *
+ * Bit setting for a PHY Register.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] reg   Register address.
+ * \param[in] ofst  Register bit mask.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Set register bit successful.
+ */
+int32_t ethernet_phy_set_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst);
+
+/**
+ * \brief Clear bit for a PHY Register
+ *
+ * Clear bit for a PHY Register.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] reg   Register address.
+ * \param[in] ofst  Register bit mask.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Clear register bit successful.
+ */
+int32_t ethernet_phy_clear_reg_bit(struct ethernet_phy_descriptor *const descr, uint16_t reg, uint16_t ofst);
+
+/**
+ * \brief Set PHY low-power consumption state.
+ *
+ * The specific behavior of a PHY in the power-down state is implementation
+ * specific. While in the power-down state, the PHY shall respond to management
+ * transactions. During the transition to the power-down state and while in the
+ * power-down state, the PHY shall not generate spurious signals on the MII or
+ * GMII.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] state The state of the power-down mode.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Power-Down has been config successful.
+ */
+int32_t ethernet_phy_set_powerdown(struct ethernet_phy_descriptor *const descr, bool state);
+
+/**
+ * \brief Set PHY electrically isolate state.
+ *
+ * When the PHY is isolated from the MII or RMII it shall not respond to the
+ * data bundle.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] state The state of the isolate mode.
+ *
+ * \return Operation result.
+ * \retval ERR_NONE Isolate has been config successful.
+ */
+int32_t ethernet_phy_set_isolate(struct ethernet_phy_descriptor *const descr, bool state);
+
+/**
+ * \brief Restart an auto negotiation of the PHY.
+ *
+ * Restart Auto_Negotantion process
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ *
+ * \return Operation result
+ * \retval ERR_NONE Auto-Negotiation has been initiated.
+ */
+int32_t ethernet_phy_restart_autoneg(struct ethernet_phy_descriptor *const descr);
+
+/**
+ * \brief Set PHY placed in a loopback mode of operation.
+ *
+ * When in loopback mode, the PHY shall accept data from the MII/RMII transmit
+ * data path and return it to the MII/RMII receive data path.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ * \param[in] state State of the loopback mode.
+ *
+ * \return Operation result
+ * \retval ERR_NONE Loopback has been set successful.
+ */
+int32_t ethernet_phy_set_loopback(struct ethernet_phy_descriptor *const descr, bool state);
+
+/**
+ * \brief Get PHY link status
+ *
+ * Get PHY link status
+ *
+ * \param[in]  descr  Ethernet PHY descriptor.
+ * \param[out] status Pointer to the Link Status.
+ *
+ * \return ERR_NONE if successfully
+ */
+int32_t ethernet_phy_get_link_status(struct ethernet_phy_descriptor *const descr, bool *status);
+
+/**
+ * \brief Reset PHY.
+ *
+ * Resetting PHY, this action set all the status and control register to their
+ * default states. As a consequence this action may change the internal state
+ * of the PHY and the state of the physical link associated with the PHY. The
+ * reset process shall be completed within 0.5 second.
+ *
+ * \param[in] descr Ethernet PHY descriptor.
+ *
+ * \return ERR_NONE if successfully
+ */
+int32_t ethernet_phy_reset(struct ethernet_phy_descriptor *const descr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef ETHERNET_PHY_H_INCLUDED */

bsp/microchip/same54/bsp/ethernet_phy/ieee8023_mii_standard_register.h

@@ -0,0 +1,137 @@
+/**
+ * \file
+ *
+ * \brief IEEE802.3 MII Management Standard Register Set
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef ETHERNET_MII_REGISTER_H_INCLUDED
+#define ETHERNET_MII_REGISTER_H_INCLUDED
+
+/* IEEE 802.3 Clause22.2.4 defined Standard Registers.
+ * The MII basic register set consists of two registers referred to as the
+ * Control register (Register 0) and the Status register (Register 1). All
+ * PHYs that provide an MII shall incorporate the basic register set. All PHYs
+ * that provide a GMII shall incorporate an extended basic register set
+ * consisting of the Control register (Register 0), Status register
+ * (Register 1), and Extended Status register (Register 15). The status and
+ * control functions defined here are considered basic and fundamental to
+ * 100 Mb/s and 1000 Mb/s PHYs. Registers 2 through 14 are part of the
+ * extended register set. The format of Registers 4 through 10 are defined for
+ * the specific Auto-Negotiation protocol used (Clause 28 or Clause 37). The
+ * format of these registers is selected by the bit settings of Registers 1
+ * and 15.
+ **/
+#define MDIO_REG0_BMCR 0x00    /*  Basic Control */
+#define MDIO_REG1_BMSR 0x01    /*  Basic Status */
+#define MDIO_REG2_PHYID1 0x02  /*  PHY Idendifier 1 */
+#define MDIO_REG3_PHYID2 0x03  /*  PHY Idendifier 2 */
+#define MDIO_REG4_ANA 0x04     /*  Auto_Negotiation Advertisement */
+#define MDIO_REG5_ANLPA 0x05   /*  Auto_negotiation Link Partner Base Page Ability */
+#define MDIO_REG6_ANE 0x06     /*  Auto-negotiation Expansion */
+#define MDIO_REG7_ANNPT 0x07   /*  Auto-negotiation Next Page Transmit */
+#define MDIO_REG8_ANLPRNP 0x08 /*  Auto-Negotiation Link Partner Received Next Page */
+#define MDIO_REG9_MSC 0x09     /*  MASTER-SLAVE Control Register */
+#define MDIO_REG10_MSS 0x0A    /*  MASTER-SLAVE Status Register */
+#define MDIO_REG11_PSEC 0x0B   /*  PSE Control Register */
+#define MDIO_REG12_PSES 0x0C   /*  PSE Status Register */
+#define MDIO_REG13_MMDAC 0x0D  /*  MMD Access Control Register */
+#define MDIO_REG14_MMDAAD 0x0E /*  MMD Access Address Data Register */
+#define MDIO_REG15_EXTS 0x0F   /*  Extended Status */
+/* Register 16 to 31 are Reserved for Vendor Specific */
+
+/* Bit definitions: MDIO_REG0_BMCR 0x00 Basic Control */
+#define MDIO_REG0_BIT_RESET (1 << 15)            /*  1 = Software Reset; 0 = Normal Operation */
+#define MDIO_REG0_BIT_LOOPBACK (1 << 14)         /*  1 = loopback Enabled; 0 = Normal Operation */
+#define MDIO_REG0_BIT_SPEED_SELECT_LSB (1 << 13) /*  1 = 100Mbps; 0=10Mbps */
+#define MDIO_REG0_BIT_AUTONEG (1 << 12)          /*  1 = Auto-negotiation Enable */
+#define MDIO_REG0_BIT_POWER_DOWN (1 << 11)       /*  1 = Power down 0=Normal operation */
+#define MDIO_REG0_BIT_ISOLATE (1 << 10)          /*  1 = Isolates 0 = Normal operation */
+#define MDIO_REG0_BIT_RESTART_AUTONEG (1 << 9)   /*  1 = Restart auto-negotiation 0 = Normal operation */
+#define MDIO_REG0_BIT_DUPLEX_MODE (1 << 8)       /*  1 = Full duplex operation 0 = Normal operation */
+#define MDIO_REG0_BIT_COLLISION_TEST (1 << 7)    /*  1 = Enable COL test; 0 = Disable COL test */
+#define MDIO_REG0_BIT_SPEED_SELECT_MSB (1 << 6)  /*  1 with LSB0 = 1000Mbps */
+#define MDIO_REG0_BIT_UNIDIR_ENABLE (1 << 5)     /*  Unidirectional Enable */
+/* Reserved                     4 to 0       Read as 0, ignore on write */
+
+/* Bit definitions: MDIO_BMSR 0x01 Basic Status */
+#define MDIO_REG1_BIT_100BASE_T4 (1 << 15)     /*  100BASE-T4 Capable */
+#define MDIO_REG1_BIT_100BASE_TX_FD (1 << 14)  /*  100BASE-TX Full Duplex Capable */
+#define MDIO_REG1_BIT_100BASE_TX_HD (1 << 13)  /*  100BASE-TX Half Duplex Capable */
+#define MDIO_REG1_BIT_10BASE_T_FD (1 << 12)    /*  10BASE-T Full Duplex Capable */
+#define MDIO_REG1_BIT_10BASE_T_HD (1 << 11)    /*  10BASE-T Half Duplex Capable */
+#define MDIO_REG1_BIT_100BASE_T2_FD (1 << 10)  /*  1000BASE-T2 Full Duplex Capable */
+#define MDIO_REG1_BIT_100BASE_T2_HD (1 << 9)   /*  1000BASE-T2 Half Duplex Capable */
+#define MDIO_REG1_BIT_EXTEND_STATUS (1 << 8)   /*  1 = Extend Status Information In Reg 15 */
+#define MDIO_REG1_BIT_UNIDIR_ABILITY (1 << 7)  /*  Unidirectional ability */
+#define MDIO_REG1_BIT_MF_PREAMB_SUPPR (1 << 6) /*  MII Frame Preamble Suppression */
+#define MDIO_REG1_BIT_AUTONEG_COMP (1 << 5)    /*  Auto-negotiation Complete */
+#define MDIO_REG1_BIT_REMOTE_FAULT (1 << 4)    /*  Remote Fault */
+#define MDIO_REG1_BIT_AUTONEG_ABILITY (1 << 3) /*  Auto Configuration Ability */
+#define MDIO_REG1_BIT_LINK_STATUS (1 << 2)     /*  Link Status */
+#define MDIO_REG1_BIT_JABBER_DETECT (1 << 1)   /*  Jabber Detect */
+#define MDIO_REG1_BIT_EXTEND_CAPAB (1 << 0)    /*  Extended Capability */
+
+/*  Bit definitions: MDIO_PHYID1 0x02 PHY Idendifier 1 */
+/*  Bit definitions: MDIO_PHYID2 0x03 PHY Idendifier 2 */
+#define MDIO_LSB_MASK 0x3F
+#define MDIO_OUI_MSB 0x0022
+#define MDIO_OUI_LSB 0x1572
+
+/* Bit definitions: MDIO_REG4_ANA 0x04 Auto-Negotiation advertisement */
+#define MDIO_REG4_BIT_NEXTPAGE (15 << 0)     /* Next Page */
+#define MDIO_REG4_BIT_REMOTE_FAULT (13 << 0) /* Remote Fault */
+#define MDIO_REG4_BIT_EXT_NEXTPAGE (12 << 0) /* Extended Next Page */
+
+/*  Bit definitions: MDIO_ANAR   0x04 Auto_Negotiation Advertisement */
+/*  Bit definitions: MDIO_ANLPAR 0x05 Auto_negotiation Link Partner Ability */
+#define MDIO_NP (1 << 15)         /*  Next page Indication */
+#define MDIO_RF (1 << 13)         /*  Remote Fault */
+#define MDIO_PAUSE_MASK (3 << 10) /*  0,0 = No Pause 1,0 = Asymmetric Pause(link partner) */
+                                  /*  0,1 = Symmetric Pause 1,1 = Symmetric&Asymmetric Pause(local device) */
+#define MDIO_100T4 (1 << 9)       /*  100BASE-T4 Support */
+#define MDIO_100TX_FDX (1 << 8)   /*  100BASE-TX Full Duplex Support */
+#define MDIO_100TX_HDX (1 << 7)   /*  100BASE-TX Half Duplex Support */
+#define MDIO_10_FDX (1 << 6)      /*  10BASE-T Full Duplex Support */
+#define MDIO_10_HDX (1 << 5)      /*  10BASE-T Half Duplex Support */
+#define MDIO_AN_IEEE_802_3 0x0001 /*  [00001] = IEEE 802.3 */
+
+/* Bit definitions: MDIO_ANER 0x06 Auto-negotiation Expansion */
+#define MDIO_PDF (1 << 4)        /*  Local Device Parallel Detection Fault */
+#define MDIO_LP_NP_ABLE (1 << 3) /*  Link Partner Next Page Able */
+#define MDIO_NP_ABLE (1 << 2)    /*  Local Device Next Page Able */
+#define MDIO_PAGE_RX (1 << 1)    /*  New Page Received */
+#define MDIO_LP_AN_ABLE (1 << 0) /*  Link Partner Auto-negotiation Able */
+
+/* Bit definitions: MDIO_PCR1 0x1E PHY Control 1 */
+#define MDIO_OMI_10BASE_T_HD 0x0001
+#define MDIO_OMI_100BASE_TX_HD 0x0002
+#define MDIO_OMI_10BASE_T_FD 0x0005
+
+#endif /* #ifndef ETHERNET_MII_REGISTER_H_INCLUDED */

bsp/microchip/same54/bsp/ethernet_phy_main.c

@@ -0,0 +1,43 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+
+#include <atmel_start.h>
+#include <ieee8023_mii_standard_config.h>
+#include <ethernet_phy_main.h>
+
+struct ethernet_phy_descriptor MACIF_PHY_desc;
+
+void MACIF_PHY_init(void)
+{
+	mac_async_enable(&MACIF);
+	ethernet_phy_init(&MACIF_PHY_desc, &MACIF, CONF_MACIF_PHY_IEEE8023_MII_PHY_ADDRESS);
+#if CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING == 1
+	ethernet_phy_write_reg(&MACIF_PHY_desc, MDIO_REG0_BMCR, CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0);
+#endif /* CONF_MACIF_PHY_IEEE8023_MII_CONTROL_REG0_SETTING */
+}
+
+void MACIF_PHY_example(void)
+{
+	bool    link_state;
+	int32_t rst;
+	/* Restart an auto-negotiation */
+	rst = ethernet_phy_restart_autoneg(&MACIF_PHY_desc);
+	while (rst != ERR_NONE) {
+	}
+
+	/* Wait for PHY link up */
+	do {
+		rst = ethernet_phy_get_link_status(&MACIF_PHY_desc, &link_state);
+	} while (rst == ERR_NONE && link_state == true);
+}
+
+void ethernet_phys_init(void)
+{
+
+	MACIF_PHY_init();
+}

bsp/microchip/same54/bsp/ethernet_phy_main.h

@@ -0,0 +1,30 @@
+/*
+ * Code generated from Atmel Start.
+ *
+ * This file will be overwritten when reconfiguring your Atmel Start project.
+ * Please copy examples or other code you want to keep to a separate file or main.c
+ * to avoid loosing it when reconfiguring.
+ */
+#ifndef ETHERNET_PHY_MAIN_H
+#define ETHERNET_PHY_MAIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <ethernet_phy.h>
+
+extern struct ethernet_phy_descriptor MACIF_PHY_desc;
+
+void ethernet_phys_init(void);
+void MACIF_PHY_example(void);
+
+/**
+ * \brief Ethernet PHY devices
+ */
+void ethernet_phys_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ETHERNET_PHY_MAIN_H */

bsp/microchip/same54/bsp/examples/driver_examples.c

@@ -10,6 +10,20 @@
 #include "driver_init.h"
 #include "utils.h"
 
+/**
+ * Example of using ADC_0 to generate waveform.
+ */
+void ADC_0_example(void)
+{
+	uint8_t buffer[2];
+
+	adc_sync_enable_channel(&ADC_0, 0);
+
+	while (1) {
+		adc_sync_read_channel(&ADC_0, 0, buffer, 2);
+	}
+}
+
 static uint8_t aes_plain_text[16]
     = {0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a};
 static uint8_t aes_key[16]
@@ -34,14 +48,41 @@ void CRYPTOGRAPHY_0_example(void)
 
 /**
  * Example of using TARGET_IO to write "Hello World" using the IO abstraction.
+ *
+ * Since the driver is asynchronous we need to use statically allocated memory for string
+ * because driver initiates transfer and then returns before the transmission is completed.
+ *
+ * Once transfer has been completed the tx_cb function will be called.
  */
+
+static uint8_t example_TARGET_IO[12] = "Hello World!";
+
+static void tx_cb_TARGET_IO(const struct usart_async_descriptor *const io_descr)
+{
+	/* Transfer completed */
+}
+
 void TARGET_IO_example(void)
 {
 	struct io_descriptor *io;
-	usart_sync_get_io_descriptor(&TARGET_IO, &io);
-	usart_sync_enable(&TARGET_IO);
 
-	io_write(io, (uint8_t *)"Hello World!", 12);
+	usart_async_register_callback(&TARGET_IO, USART_ASYNC_TXC_CB, tx_cb_TARGET_IO);
+	/*usart_async_register_callback(&TARGET_IO, USART_ASYNC_RXC_CB, rx_cb);
+	usart_async_register_callback(&TARGET_IO, USART_ASYNC_ERROR_CB, err_cb);*/
+	usart_async_get_io_descriptor(&TARGET_IO, &io);
+	usart_async_enable(&TARGET_IO);
+
+	io_write(io, example_TARGET_IO, 12);
+}
+
+void I2C_0_example(void)
+{
+	struct io_descriptor *I2C_0_io;
+
+	i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
+	i2c_m_sync_enable(&I2C_0);
+	i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
+	io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
 }
 
 void CAN_0_tx_callback(struct can_async_descriptor *const descr)

bsp/microchip/same54/bsp/examples/driver_examples.h

@@ -12,10 +12,14 @@
 extern "C" {
 #endif
 
+void ADC_0_example(void);
+
 void CRYPTOGRAPHY_0_example(void);
 
 void TARGET_IO_example(void);
 
+void I2C_0_example(void);
+
 void CAN_0_example(void);
 
 #ifdef __cplusplus

bsp/microchip/same54/bsp/gcc/gcc/same54p20a_flash.ld

@@ -60,6 +60,31 @@ SECTIONS
         *(.rodata .rodata* .gnu.linkonce.r.*)
         *(.ARM.extab* .gnu.linkonce.armextab.*)
 
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        /* section information for utest */
+        . = ALIGN(4);
+        __rt_utest_tc_tab_start = .;
+        KEEP(*(UtestTcTab))
+        __rt_utest_tc_tab_end = .;
+
+
         /* Support C constructors, and C destructors in both user code
            and the C library. This also provides support for C++ code. */
         . = ALIGN(4);

bsp/microchip/same54/bsp/hal/documentation/adc_sync.rst

@@ -0,0 +1,74 @@
+======================
+ADC Synchronous driver
+======================
+
+An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
+A reference signal with a known voltage level is quantified into equally
+sized chunks, each representing a digital value from 0 to the highest number
+possible with the bit resolution supported by the ADC. The input voltage
+measured by the ADC is compared against these chunks and the chunk with the
+closest voltage level defines the digital value that can be used to represent
+the analog input voltage level.
+
+Usually an ADC can operate in either differential or single-ended mode.
+In differential mode two signals (V+ and V-) are compared against each other
+and the resulting digital value represents the relative voltage level between
+V+ and V-. This means that if the input voltage level on V+ is lower than on
+V- the digital value is negative, which also means that in differential
+mode one bit is lost to the sign. In single-ended mode only V+ is compared
+against the reference voltage, and the resulting digital value can only be
+positive, but the full bit-range of the ADC can be used.
+
+Usually multiple resolutions are supported by the ADC, lower resolution can
+reduce the conversion time, but lose accuracy.
+
+Some ADCs has a gain stage on the input lines which can be used to increase the
+dynamic range. The default gain value is usually x1, which means that the
+conversion range is from 0V to the reference voltage.
+Applications can change the gain stage, to increase or reduce the conversion
+range.
+
+The window mode allows the conversion result to be compared to a set of
+predefined threshold values. Applications can use callback function to monitor
+if the conversion result exceeds predefined threshold value.
+
+Usually multiple reference voltages are supported by the ADC, both internal and
+external with difference voltage levels. The reference voltage have an impact
+on the accuracy, and should be selected to cover the full range of the analog
+input signal and never less than the expected maximum input voltage.
+
+There are two conversion modes supported by ADC, single shot and free running.
+In single shot mode the ADC only make one conversion when triggered by the
+application, in free running mode it continues to make conversion from it
+is triggered until it is stopped by the application. When window monitoring,
+the ADC should be set to free running mode.
+
+Features
+--------
+* Initialization and de-initialization
+* Support multiple Conversion Mode, Single or Free run
+* Start ADC Conversion
+* Read Conversion Result
+
+Applications
+------------
+* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
+* Measurement of external sensor. E.g., Temperature, humidity sensor value.
+* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
+
+Dependencies
+------------
+* ADC hardware
+
+Concurrency
+-----------
+N/A
+
+Limitations
+-----------
+N/A
+
+Knows issues and workarounds
+----------------------------
+N/A
+

bsp/microchip/same54/bsp/hal/documentation/i2c_master_sync.rst

@@ -0,0 +1,87 @@
+=============================
+I2C Master synchronous driver
+=============================
+
+I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
+for on-board low-speed bi-directional communication between controllers and
+peripherals. The master device is responsible for initiating and controlling
+all transfers on the I2C bus. Only one master device can be active on the I2C
+bus at the time, but the master role can be transferred between devices on the
+same I2C bus. I2C uses only two bidirectional open-drain lines, usually
+designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
+resistors.
+
+The stop condition is automatically controlled by the driver if the I/O write and
+read functions are used, but can be manually controlled by using the
+i2c_m_sync_transfer function.
+
+Often a master accesses different information in the slave by accessing
+different registers in the slave. This is done by first sending a message to
+the target slave containing the register address, followed by a repeated start
+condition (no stop condition between) ending with transferring register data.
+This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
+function, but limited to 8-bit register addresses.
+
+I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
+Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
+stick within the SCL clock frequency range supported by the selected mode.
+The requested SCL clock frequency is not validated by the
+i2c_m_sync_set_baudrate function against the selected I2C mode.
+
+Features
+--------
+
+	* I2C Master support
+	* Initialization and de-initialization
+	* Enabling and disabling
+	* Run-time bus speed configuration
+	* Write and read I2C messages
+	* Slave register access functions (limited to 8-bit address)
+	* Manual or automatic stop condition generation
+	* 10- and 7- bit addressing
+	* I2C Modes supported
+	       +----------------------+-------------------+
+	       |* Standard/Fast mode  | (SCL: 1 - 400kHz) |
+	       +----------------------+-------------------+
+	       |* Fastmode+           | (SCL: 1 - 1000kHz)|
+	       +----------------------+-------------------+
+	       |* Highspeed mode      | (SCL: 1 - 3400kHz)|
+	       +----------------------+-------------------+
+
+Applications
+------------
+
+* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
+* Data communication between micro controllers
+* Controlling displays
+
+Dependencies
+------------
+
+* I2C Master capable hardware
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+General
+^^^^^^^
+
+	* System Managmenet Bus (SMBus) not supported.
+	* Power Management Bus (PMBus) not supported.
+
+Clock considerations
+^^^^^^^^^^^^^^^^^^^^
+
+The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
+
+Known issues and workarounds
+----------------------------
+
+N/A
+
+

bsp/microchip/same54/bsp/hal/documentation/mac_async.rst

@@ -0,0 +1,43 @@
+================================
+Ethernet MAC Asynchronous Driver
+================================
+
+The Ethernet MAC driver implements a 10/100 Mbps Ethernet MAC compatible with
+the IEEE 802.3 standard.
+
+Features
+--------
+
+* Initialization/de-initialization
+* Enabling/disabling
+* Data transfer: transmission, reception
+* Enabling/disabling Interrupt
+* Notifications about transfer completion and frame received via callbacks
+* Address Filter for Specific 48-bit Addresses and Type ID
+* Address Filter for Unicast and Multicase Addresses
+* Reading/writing PHY registers
+
+Applications
+------------
+
+Co-works with thirdpart TCP/IP stacks. E.g., Lwip, Cyclone IP stack.
+
+Dependencies
+------------
+
+MAC capable hardware compatible with the IEEE 802.3 standard.
+
+Concurrency
+-----------
+
+N/A
+
+Limitations
+-----------
+
+N/A
+
+Known issues and workarounds
+----------------------------
+
+N/A

bsp/microchip/same70/bsp/hal/documentation/usart_sync.rst → bsp/microchip/same54/bsp/hal/documentation/usart_async.rst

@@ -1,9 +1,20 @@
-The USART Synchronous Driver
-============================
+The USART Asynchronous Driver
+=============================
 
 The universal synchronous and asynchronous receiver and transmitter
 (USART) is usually used to transfer data from one device to the other.
 
+The USART driver use a ring buffer to store received data. When the USART
+raise the data received interrupt, this data will be stored in the ring buffer
+at the next free location. When the ring buffer is full, the next reception
+will overwrite the oldest data stored in the ring buffer. There is one
+USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro
+is called SERCOM0_USART_BUFFER_SIZE.
+
+On the other hand, when sending data over USART, the data is not copied to an
+internal buffer, but the data buffer supplied by the user is used. The callback
+will only be generated at the end of the buffer and not for each byte.
+
 User can set action for flow control pins by function usart_set_flow_control,
 if the flow control is enabled. All the available states are defined in union
 usart_flow_control_state.
@@ -24,6 +35,8 @@ Features
   * Data order
   * Flow control
 * Data transfer: transmission, reception
+* Notifications about transfer done or error case via callbacks
+* Status information with busy state and transfer count
 
 Applications
 ------------
@@ -34,7 +47,8 @@ between devices.
 Dependencies
 ------------
 
-USART capable hardware.
+USART capable hardware, with interrupt on each character is sent or
+received.
 
 Concurrency
 -----------

bsp/microchip/same54/bsp/hal/include/hal_adc_sync.h

@@ -0,0 +1,277 @@
+/**
+ * \file
+ *
+ * \brief ADC functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_ADC_SYNC_H_INCLUDED
+#define _HAL_ADC_SYNC_H_INCLUDED
+
+#include <hpl_adc_sync.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_adc_sync
+ *
+ * @{
+ */
+
+/**
+ * \brief ADC descriptor
+ *
+ * The ADC descriptor forward declaration.
+ */
+struct adc_sync_descriptor;
+
+/**
+ * \brief ADC descriptor
+ */
+struct adc_sync_descriptor {
+	/** ADC device */
+	struct _adc_sync_device device;
+};
+
+/**
+ * \brief Initialize ADC
+ *
+ * This function initializes the given ADC descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr An ADC descriptor to initialize
+ * \param[in] hw     The pointer to hardware instance
+ * \param[in] func   The pointer to a set of functions pointers
+ *
+ * \return Initialization status.
+ */
+int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
+
+/**
+ * \brief Deinitialize ADC
+ *
+ * This function deinitializes the given ADC descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is
+ * permitted to be deinitialized.
+ *
+ * \param[in] descr An ADC descriptor to deinitialize
+ *
+ * \return De-initialization status.
+ */
+int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
+
+/**
+ * \brief Enable ADC
+ *
+ * Use this function to set the ADC peripheral to enabled state.
+ *
+ * \param[in] descr    Pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Disable ADC
+ *
+ * Use this function to set the ADC peripheral to disabled state.
+ *
+ * \param[in] descr   Pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return Operation status
+ *
+ */
+int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Read data from ADC
+ *
+ * \param[in] descr    The pointer to the ADC descriptor
+ * \param[in] channel  Channel number
+ * \param[in] buf      A buffer to read data to
+ * \param[in] length   The size of a buffer
+ *
+ * \return The number of bytes read.
+ */
+int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
+                              const uint16_t length);
+
+/**
+ * \brief Set ADC reference source
+ *
+ * This function sets ADC reference source.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] reference A reference source to set
+ *
+ * \return Status of the ADC reference source setting.
+ */
+int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
+
+/**
+ * \brief Set ADC resolution
+ *
+ * This function sets ADC resolution.
+ *
+ * \param[in] descr      The pointer to the ADC descriptor
+ * \param[in] resolution A resolution to set
+ *
+ * \return Status of the ADC resolution setting.
+ */
+int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
+
+/**
+ * \brief Set ADC input source of a channel
+ *
+ * This function sets ADC positive and negative input sources.
+ *
+ * \param[in] descr     The pointer to the ADC descriptor
+ * \param[in] pos_input A positive input source to set
+ * \param[in] neg_input A negative input source to set
+ * \param[in] channel   Channel number
+ *
+ * \return Status of the ADC channels setting.
+ */
+int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
+                            const adc_neg_input_t neg_input, const uint8_t channel);
+
+/**
+ * \brief Set ADC conversion mode
+ *
+ * This function sets ADC conversion mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A conversion mode to set
+ *
+ * \return Status of the ADC conversion mode setting.
+ */
+int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
+
+/**
+ * \brief Set ADC differential mode
+ *
+ * This function sets ADC differential mode.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] mode    A differential mode to set
+ *
+ * \return Status of the ADC differential mode setting.
+ */
+int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                               const enum adc_differential_mode mode);
+
+/**
+ * \brief Set ADC channel gain
+ *
+ * This function sets ADC channel gain.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ * \param[in] gain    A gain to set
+ *
+ * \return Status of the ADC gain setting.
+ */
+int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
+                                  const adc_gain_t gain);
+
+/**
+ * \brief Set ADC window mode
+ *
+ * This function sets ADC window mode.
+ *
+ * \param[in] descr The pointer to the ADC descriptor
+ * \param[in] mode  A window mode to set
+ *
+ * \return Status of the ADC window mode setting.
+ */
+int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
+
+/**
+ * \brief Set ADC thresholds
+ *
+ * This function sets ADC positive and negative thresholds.
+ *
+ * \param[in] descr         The pointer to the ADC descriptor
+ * \param[in] low_threshold A lower thresholds to set
+ * \param[in] up_threshold  An upper thresholds to set
+ *
+ * \return Status of the ADC thresholds setting.
+ */
+int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
+                                const adc_threshold_t up_threshold);
+
+/**
+ * \brief Retrieve threshold state
+ *
+ * This function retrieves ADC threshold state.
+ *
+ * \param[in] descr  The pointer to the ADC descriptor
+ * \param[out] state The threshold state
+ *
+ * \return The state of ADC thresholds state retrieving.
+ */
+int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
+                                     adc_threshold_status_t *const           state);
+
+/**
+ * \brief Check if conversion is complete
+ *
+ * This function checks if the ADC has finished the conversion.
+ *
+ * \param[in] descr   The pointer to the ADC descriptor
+ * \param[in] channel Channel number
+ *
+ * \return The status of ADC conversion completion checking.
+ * \retval 1 The conversion is complete
+ * \retval 0 The conversion is not complete
+ */
+int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t adc_sync_get_version(void);
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#include <hpl_missing_features.h>
+
+#endif /* _HAL_ADC_SYNC_H_INCLUDED */

bsp/microchip/same54/bsp/hal/include/hal_i2c_m_sync.h

@@ -0,0 +1,244 @@
+/**
+ * \file
+ *
+ * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
+#define _HAL_I2C_M_SYNC_H_INCLUDED
+
+#include <hpl_i2c_m_sync.h>
+#include <hal_io.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_i2c_master_sync
+ *
+ * @{
+ */
+
+#define I2C_M_MAX_RETRY 1
+
+/**
+ * \brief I2C descriptor structure, embed i2c_device & i2c_interface
+ */
+struct i2c_m_sync_desc {
+	struct _i2c_m_sync_device device;
+	struct io_descriptor      io;
+	uint16_t                  slave_addr;
+};
+
+/**
+ * \brief Initialize synchronous I2C interface
+ *
+ * This function initializes the given I/O descriptor to be used as a
+ * synchronous I2C interface descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] hw The pointer to hardware instance
+ *
+ * \return Initialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
+
+/**
+ * \brief Deinitialize I2C interface
+ *
+ * This function deinitializes the given I/O descriptor.
+ * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Uninitialization status.
+ * \retval -1 The passed parameters were invalid or the interface is already deinitialized
+ * \retval 0 The de-initialization is completed successfully
+ */
+int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Set the slave device address
+ *
+ * This function sets the next transfer target slave I2C device address.
+ * It takes no effect to any already started access.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] addr The slave address to access
+ * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
+ *
+ * \return Masked slave address. The mask is a maximum 10-bit address, and 10th
+ *         bit is set if a 10-bit address is used
+ */
+int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
+
+/**
+ * \brief Set baudrate
+ *
+ * This function sets the I2C device to the specified baudrate.
+ * It only takes effect when the hardware is disabled.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] clkrate Unused parameter. Should always be 0
+ * \param[in] baudrate The baudrate value set to master
+ *
+ * \return Whether successfully set the baudrate
+ * \retval -1 The passed parameters were invalid or the device is already enabled
+ * \retval 0 The baudrate set is completed successfully
+ */
+int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
+
+/**
+ * \brief Sync version of enable hardware
+ *
+ * This function enables the I2C device, and then waits for this enabling operation to be done
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Whether successfully enable the device
+ * \retval -1 The passed parameters were invalid or the device enable failed
+ * \retval 0 The hardware enabling is completed successfully
+ */
+int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Sync version of disable hardware
+ *
+ * This function disables the I2C device and then waits for this disabling operation to be done
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return Whether successfully disable the device
+ * \retval -1 The passed parameters were invalid or the device disable failed
+ * \retval 0 The hardware disabling is completed successfully
+ */
+int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
+
+/**
+ * \brief Sync version of write command to I2C slave
+ *
+ * This function will write the value to a specified register in the I2C slave device and
+ * then wait for this operation to be done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] buffer The buffer holding data to write to the I2C slave device
+ * \param[in] length The length (in bytes) to write to the I2C slave device
+ *
+ * \return Whether successfully write to the device
+ * \retval <0 The passed parameters were invalid or write fail
+ * \retval 0 Writing to register is completed successfully
+ */
+int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
+
+/**
+ * \brief Sync version of read register value from I2C slave
+ *
+ * This function will read a byte value from a specified register in the I2C slave device and
+ * then wait for this operation to be done.
+ *
+ * The sequence of this routine is
+ * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] reg The internal address/register of the I2C slave device
+ * \param[in] buffer The buffer to hold the read data from the I2C slave device
+ * \param[in] length The length (in bytes) to read from the I2C slave device
+ *
+ * \return Whether successfully read from the device
+ * \retval <0 The passed parameters were invalid or read fail
+ * \retval 0 Reading from register is completed successfully
+ */
+int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
+
+/**
+ * \brief Sync version of transfer message to/from the I2C slave
+ *
+ * This function will transfer a message between the I2C slave and the master. This function will wait for the operation
+ * to be done.
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ * \param[in] msg  An i2c_m_msg struct
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
+
+/**
+ * \brief Sync version of send stop condition on the i2c bus
+ *
+ * This function will create a stop condition on the i2c bus to release the bus
+ *
+ * \param[in] i2c An I2C descriptor, which is used to communicate through I2C
+ *
+ * \return The status of the operation
+ * \retval 0 Operation completed successfully
+ * \retval <0 Operation failed
+ */
+int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
+
+/**
+ * \brief Return I/O descriptor for this I2C instance
+ *
+ * This function will return a I/O instance for this I2C driver instance
+ *
+ * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
+ * \param[in] io_descriptor A pointer to an I/O descriptor pointer type
+ *
+ * \return Error code
+ * \retval 0 No error detected
+ * \retval <0 Error code
+ */
+int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t i2c_m_sync_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

bsp/microchip/same54/bsp/hal/include/hal_mac_async.h

@@ -0,0 +1,260 @@
+/**
+ * \file
+ *
+ * \brief MAC functionality declaration.
+ *
+ * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef HAL_MAC_ASYNC_H_INCLUDED
+#define HAL_MAC_ASYNC_H_INCLUDED
+
+#include <hpl_mac_async.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \addtogroup doc_driver_hal_mac_async
+ *
+ *@{
+ */
+
+/**
+ * \brief MAC descriptor
+ *
+ * The MAC descriptor forward declaration.
+ */
+struct mac_async_descriptor;
+
+/**
+ * \brief MAC callback type
+ *
+ * \param[in] descr A MAC descriptor
+ */
+typedef void (*mac_async_cb_t)(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief MAC callbacks
+ */
+struct mac_async_callbacks {
+	mac_async_cb_t receive;
+	mac_async_cb_t transmit;
+};
+
+/**
+ * \brief MAC descriptor
+ */
+struct mac_async_descriptor {
+	struct _mac_async_device   dev; /*!< MAC HPL device descriptor */
+	struct mac_async_callbacks cb;  /*!< MAC Callback handlers */
+};
+
+/**
+ * Callback for MAC interrupt
+ */
+typedef void (*mac_cb)(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief Initialize the MAC driver
+ *
+ * \param[in] descr A MAC descriptor to init.
+ * \param[in] hw    Hardware instance pointer.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+
+ */
+int32_t mac_async_init(struct mac_async_descriptor *const descr, void *const dev);
+
+/**
+ * \brief Deinitialize the MAC driver
+ *
+ * \param[in] descr A MAC descriptor to deinitialize.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_deinit(struct mac_async_descriptor *const descr);
+
+/** \brief Enable the MAC
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_enable(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief Disable the MAC
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_disable(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief Write raw data to MAC
+ *
+ * Write the raw data to the MAC that will be transmitted
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor.
+ * \param[in] buf   Pointer to the data buffer.
+ * \param[in] len   Length of the data buffer.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_write(struct mac_async_descriptor *const descr, uint8_t *buf, uint32_t len);
+
+/**
+ * \brief Read raw data from MAC
+ *
+ * Read received raw data from MAC
+ *
+ * \param[in] descr  Pointer to the HAL MAC descriptor.
+ * \param[in] buffer Pointer to the data buffer. If the pointer is NULL, then the
+ *                   frame will be discarded.
+ * \param[in] length The max. length of the data buffer to be read. If the length is zero,
+ *                   then the frame will be discard
+ *
+ * \return Number of bytes that received
+ */
+uint32_t mac_async_read(struct mac_async_descriptor *const descr, uint8_t *buf, uint32_t len);
+
+/**
+ * \brief Get next valid package length
+ *
+ * Get next valid package length from the MAC. The application can use this function
+ * to fetch the length of the next package, malloc a buffer with this
+ * length, and then invoke mac_async_read to read out the package data.
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor.
+ *
+ * \return The number of bytes in the next package that can be read.
+ */
+uint32_t mac_async_read_len(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief Enable the MAC IRQ
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor
+ */
+void mac_async_enable_irq(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief Disable the MAC IRQ
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor
+ */
+void mac_async_disable_irq(struct mac_async_descriptor *const descr);
+
+/**
+ * \brief Register the MAC callback function
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor.
+ * \param[in] type  Callback function type.
+ * \param[in] func  A callback function. Passing NULL will de-register any
+ *                  registered callback.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_register_callback(struct mac_async_descriptor *const descr, const enum mac_async_cb_type type,
+                                    const FUNC_PTR func);
+
+/**
+ * \brief Set MAC filter
+ *
+ * Set MAC filter. Ethernet frames matching the filter, will be received.
+ *
+ * \param[in] descr  Pointer to the HAL MAC descriptor.
+ * \param[in] index  MAC filter index. Start from 0. The maximum value depends on
+ *            the hardware specifications.
+ * \param[in] filter Pointer to the filter descriptor.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_set_filter(struct mac_async_descriptor *const descr, uint8_t index, struct mac_async_filter *filter);
+
+/**
+ * \brief Set MAC filter (expanded).
+ *
+ * Set MAC filter. The Ethernet frames matching the filter, will be received.
+ *
+ * \param[in] descr  Pointer to the HAL MAC descriptor
+ * \param[in] mac    MAC address
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_set_filter_ex(struct mac_async_descriptor *const descr, uint8_t mac[6]);
+
+/**
+ * \brief Write PHY register
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor.
+ * \param[in] addr  PHY address.
+ * \param[in] reg   Register address.
+ * \param[in] val   Register value.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_write_phy_reg(struct mac_async_descriptor *const descr, uint16_t addr, uint16_t reg, uint16_t val);
+
+/**
+ * \brief Read PHY register
+ *
+ * \param[in] descr Pointer to the HAL MAC descriptor.
+ * \param[in] addr  PHY address.
+ * \param[in] reg   Register address.
+ * \param[in] val   Register value.
+ *
+ * \return Operation status.
+ * \retval ERR_NONE Success.
+ */
+int32_t mac_async_read_phy_reg(struct mac_async_descriptor *const descr, uint16_t addr, uint16_t reg, uint16_t *val);
+
+/**
+ * \brief Get the MAC driver version
+ */
+uint32_t mac_async_get_version(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_MAC_ASYNC_H_INCLUDED */

bsp/microchip/same54/bsp/hal/include/hal_usart_async.h

@@ -0,0 +1,339 @@
+/**
+ * \file
+ *
+ * \brief USART related functionality declaration.
+ *
+ * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
+ *
+ * \asf_license_start
+ *
+ * \page License
+ *
+ * Subject to your compliance with these terms, you may use Microchip
+ * software and any derivatives exclusively with Microchip products.
+ * It is your responsibility to comply with third party license terms applicable
+ * to your use of third party software (including open source software) that
+ * may accompany Microchip software.
+ *
+ * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
+ * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
+ * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
+ * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
+ * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
+ * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
+ * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
+ * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
+ * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
+ * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
+ * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
+ *
+ * \asf_license_stop
+ *
+ */
+
+#ifndef _HAL_USART_ASYNC_H_INCLUDED
+#define _HAL_USART_ASYNC_H_INCLUDED
+
+#include "hal_io.h"
+#include <hpl_usart_async.h>
+#include <utils_ringbuffer.h>
+
+/**
+ * \addtogroup doc_driver_hal_usart_async
+ *
+ * @{
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \brief USART descriptor
+ *
+ * The USART descriptor forward declaration.
+ */
+struct usart_async_descriptor;
+
+/**
+ * \brief USART callback type
+ */
+typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr);
+
+/**
+ * \brief USART callback types
+ */
+enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB };
+
+/**
+ * \brief USART callbacks
+ */
+struct usart_async_callbacks {
+	usart_cb_t tx_done;
+	usart_cb_t rx_done;
+	usart_cb_t error;
+};
+
+/** \brief USART status
+ *  Status descriptor holds the current status of transfer.
+ */
+struct usart_async_status {
+	/** Status flags */
+	uint32_t flags;
+	/** Number of characters transmitted */
+	uint16_t txcnt;
+	/** Number of characters receviced */
+	uint16_t rxcnt;
+};
+
+/**
+ * \brief Asynchronous USART descriptor structure
+ */
+struct usart_async_descriptor {
+	struct io_descriptor         io;
+	struct _usart_async_device   device;
+	struct usart_async_callbacks usart_cb;
+	uint32_t                     stat;
+
+	struct ringbuffer rx;
+	uint16_t          tx_por;
+	uint8_t *         tx_buffer;
+	uint16_t          tx_buffer_length;
+};
+
+/** USART write busy */
+#define USART_ASYNC_STATUS_BUSY 0x0001
+
+/**
+ * \brief Initialize USART interface
+ *
+ * This function initializes the given I/O descriptor to be used as USART
+ * interface descriptor.
+ * It checks if the given hardware is not initialized and if the given hardware
+ * is permitted to be initialized.
+ *
+ * \param[out] descr A USART descriptor which is used to communicate via the USART
+ * \param[in] hw The pointer to the hardware instance
+ * \param[in] rx_buffer An RX buffer
+ * \param[in] rx_buffer_length The length of the buffer above
+ * \param[in] func The pointer to a set of function pointers
+ *
+ * \return Initialization status.
+ * \retval -1 Passed parameters were invalid or the interface is already
+ * initialized
+ * \retval 0 The initialization is completed successfully
+ */
+int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer,
+                         const uint16_t rx_buffer_length, void *const func);
+
+/**
+ * \brief Deinitialize USART interface
+ *
+ * This function deinitializes the given I/O descriptor.
+ * It checks if the given hardware is initialized and if the given hardware
+ * is permitted to be deinitialized.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return De-initialization status.
+ */
+int32_t usart_async_deinit(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Enable USART interface
+ *
+ * Enables the USART interface
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return Enabling status.
+ */
+int32_t usart_async_enable(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Disable USART interface
+ *
+ * Disables the USART interface
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return Disabling status.
+ */
+int32_t usart_async_disable(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Retrieve I/O descriptor
+ *
+ * This function retrieves the I/O descriptor of the given USART descriptor.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[out] io An I/O descriptor to retrieve
+ *
+ * \return The status of I/O descriptor retrieving.
+ */
+int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io);
+
+/**
+ * \brief Register USART callback
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] type Callback type
+ * \param[in] cb A callback function
+ *
+ * \return The status of callback assignment.
+ * \retval -1 Passed parameters were invalid or the interface is not initialized
+ * \retval 0 A callback is registered successfully
+ */
+int32_t usart_async_register_callback(struct usart_async_descriptor *const descr,
+                                      const enum usart_async_callback_type type, usart_cb_t cb);
+
+/**
+ * \brief Specify action for flow control pins
+ *
+ * This function sets action (or state) for flow control pins if
+ * the flow control is enabled.
+ * It sets state of flow control pins only if automatic support of
+ * the flow control is not supported by the hardware.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] state A state to set the flow control pins
+ *
+ * \return The status of flow control action setup.
+ */
+int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr,
+                                     const union usart_flow_control_state state);
+
+/**
+ * \brief Set USART baud rate
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] baud_rate A baud rate to set
+ *
+ * \return The status of baud rate setting.
+ */
+int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate);
+
+/**
+ * \brief Set USART data order
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] data_order A data order to set
+ *
+ * \return The status of data order setting.
+ */
+int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order);
+
+/**
+ * \brief Set USART mode
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] mode A mode to set
+ *
+ * \return The status of mode setting.
+ */
+int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode);
+
+/**
+ * \brief Set USART parity
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] parity A parity to set
+ *
+ * \return The status of parity setting.
+ */
+int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity);
+
+/**
+ * \brief Set USART stop bits
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] stop_bits Stop bits to set
+ *
+ * \return The status of stop bits setting.
+ */
+int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits);
+
+/**
+ * \brief Set USART character size
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[in] size A character size to set
+ *
+ * \return The status of character size setting.
+ */
+int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr,
+                                       const enum usart_character_size      size);
+
+/**
+ * \brief Retrieve the state of flow control pins
+ *
+ * This function retrieves the flow control pins
+ * if the flow control is enabled.
+ *
+ * The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
+ * if the flow control is done by the hardware
+ * and the pins state cannot be read out.
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ * \param[out] state The state of flow control pins
+ *
+ * \return The status of flow control state reading.
+ */
+int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr,
+                                        union usart_flow_control_state *const      state);
+
+/**
+ * \brief Check if the USART transmitter is empty
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return The status of USART TX empty checking.
+ * \retval 0 The USART transmitter is not empty
+ * \retval 1 The USART transmitter is empty
+ */
+int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Check if the USART receiver is not empty
+ *
+ * \param[in] descr A USART descriptor which is used to communicate via USART
+ *
+ * \return The status of the USART RX empty checking.
+ * \retval 1 The USART receiver is not empty
+ * \retval 0 The USART receiver is empty
+ */
+int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Retrieve the current interface status
+ *
+ * \param[in]  descr A USART descriptor which is used to communicate via USART
+ * \param[out] status The state of USART
+ *
+ * \return The status of USART status retrieving.
+ */
+int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status);
+
+/**
+ * \brief flush USART ringbuf
+ *
+ * This function flush USART RX ringbuf.
+ *
+ * \param[in] descr The pointer to USART descriptor
+ *
+ * \return ERR_NONE
+ */
+int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr);
+
+/**
+ * \brief Retrieve the current driver version
+ *
+ * \return Current driver version.
+ */
+uint32_t usart_async_get_version(void);
+
+#ifdef __cplusplus
+}
+#endif
+/**@}*/
+#endif /* _HAL_USART_ASYNC_H_INCLUDED */

bsp/microchip/same54/bsp/hal/include/hal_usart_sync.h

@@ -1,247 +0,0 @@
-/**
- * \file
- *
- * \brief USART related functionality declaration.
- *
- * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Subject to your compliance with these terms, you may use Microchip
- * software and any derivatives exclusively with Microchip products.
- * It is your responsibility to comply with third party license terms applicable
- * to your use of third party software (including open source software) that
- * may accompany Microchip software.
- *
- * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
- * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
- * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
- * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
- * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
- * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
- * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
- * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE.  TO THE FULLEST EXTENT
- * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
- * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
- * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
- *
- * \asf_license_stop
- *
- */
-
-#ifndef _HAL_SYNC_USART_H_INCLUDED
-#define _HAL_SYNC_USART_H_INCLUDED
-
-#include "hal_io.h"
-#include <hpl_usart_sync.h>
-
-/**
- * \addtogroup doc_driver_hal_usart_sync
- *
- * @{
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \brief Synchronous USART descriptor
- */
-struct usart_sync_descriptor {
-	struct io_descriptor      io;
-	struct _usart_sync_device device;
-};
-
-/**
- * \brief Initialize USART interface
- *
- * This function initializes the given I/O descriptor to be used
- * as USART interface descriptor.
- * It checks if the given hardware is not initialized and
- * if the given hardware is permitted to be initialized.
- *
- * \param[out] descr A USART descriptor which is used to communicate via USART
- * \param[in] hw The pointer to hardware instance
- * \param[in] func The pointer to as set of functions pointers
- *
- * \return Initialization status.
- */
-int32_t usart_sync_init(struct usart_sync_descriptor *const descr, void *const hw, void *const func);
-
-/**
- * \brief Deinitialize USART interface
- *
- * This function deinitializes the given I/O descriptor.
- * It checks if the given hardware is initialized and
- * if the given hardware is permitted to be deinitialized.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return De-initialization status.
- */
-int32_t usart_sync_deinit(struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Enable USART interface
- *
- * Enables the USART interface
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return Enabling status.
- */
-int32_t usart_sync_enable(struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Disable USART interface
- *
- * Disables the USART interface
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return Disabling status.
- */
-int32_t usart_sync_disable(struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Retrieve I/O descriptor
- *
- * This function retrieves the I/O descriptor of the given USART descriptor.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[out] io An I/O descriptor to retrieve
- *
- * \return The status of the I/O descriptor retrieving.
- */
-int32_t usart_sync_get_io_descriptor(struct usart_sync_descriptor *const descr, struct io_descriptor **io);
-
-/**
- * \brief Specify action for flow control pins
- *
- * This function sets the action (or state) for the flow control pins
- * if the flow control is enabled.
- * It sets the state of flow control pins only if the automatic support of
- * the flow control is not supported by the hardware.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] state A state to set the flow control pins
- *
- * \return The status of flow control action setup.
- */
-int32_t usart_sync_set_flow_control(struct usart_sync_descriptor *const  descr,
-                                    const union usart_flow_control_state state);
-
-/**
- * \brief Set USART baud rate
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] baud_rate A baud rate to set
- *
- * \return The status of baud rate setting.
- */
-int32_t usart_sync_set_baud_rate(struct usart_sync_descriptor *const descr, const uint32_t baud_rate);
-
-/**
- * \brief Set USART data order
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] data_order A data order to set
- *
- * \return The status of data order setting.
- */
-int32_t usart_sync_set_data_order(struct usart_sync_descriptor *const descr, const enum usart_data_order data_order);
-
-/**
- * \brief Set USART mode
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] mode A mode to set
- *
- * \return The status of mode setting.
- */
-int32_t usart_sync_set_mode(struct usart_sync_descriptor *const descr, const enum usart_mode mode);
-
-/**
- * \brief Set USART parity
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] parity A parity to set
- *
- * \return The status of parity setting.
- */
-int32_t usart_sync_set_parity(struct usart_sync_descriptor *const descr, const enum usart_parity parity);
-
-/**
- * \brief Set USART stop bits
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] stop_bits Stop bits to set
- *
- * \return The status of stop bits setting.
- */
-int32_t usart_sync_set_stopbits(struct usart_sync_descriptor *const descr, const enum usart_stop_bits stop_bits);
-
-/**
- * \brief Set USART character size
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[in] size A character size to set
- *
- * \return The status of character size setting.
- */
-int32_t usart_sync_set_character_size(struct usart_sync_descriptor *const descr, const enum usart_character_size size);
-
-/**
- * \brief Retrieve the state of flow control pins
- *
- * This function retrieves the of flow control pins
- * if the flow control is enabled.
- * Function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case
- * if the flow control is done by the hardware
- * and the pins state cannot be read out.
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- * \param[out] state The state of flow control pins
- *
- * \return The status of flow control state reading.
- */
-int32_t usart_sync_flow_control_status(const struct usart_sync_descriptor *const descr,
-                                       union usart_flow_control_state *const     state);
-
-/**
- * \brief Check if the USART transmitter is empty
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return The status of USART TX empty checking.
- * \retval 0 The USART transmitter is not empty
- * \retval 1 The USART transmitter is empty
- */
-int32_t usart_sync_is_tx_empty(const struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Check if the USART receiver is not empty
- *
- * \param[in] descr A USART descriptor which is used to communicate via USART
- *
- * \return The status of USART RX empty checking.
- * \retval 1 The USART receiver is not empty
- * \retval 0 The USART receiver is empty
- */
-int32_t usart_sync_is_rx_not_empty(const struct usart_sync_descriptor *const descr);
-
-/**
- * \brief Retrieve the current driver version
- *
- * \return Current driver version.
- */
-uint32_t usart_sync_get_version(void);
-
-#ifdef __cplusplus
-}
-#endif
-/**@}*/
-#endif /* _HAL_SYNC_USART_H_INCLUDED */