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@@ -6,6 +6,7 @@
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* Change Logs:
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* Date Author Notes
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* 2024-02-06 Dyyt587 first version
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+ * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG
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*/
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#ifndef __I2C_HARD_CONFIG_H__
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#define __I2C_HARD_CONFIG_H__
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@@ -32,6 +33,15 @@ extern "C" {
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#ifdef BSP_I2C1_TX_USING_DMA
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#ifndef I2C1_TX_DMA_CONFIG
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+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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+#define I2C1_TX_DMA_CONFIG \
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+ { \
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+ .dma_rcc = I2C1_TX_DMA_RCC, \
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+ .Instance = I2C1_TX_DMA_INSTANCE, \
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+ .dma_irq = I2C1_TX_DMA_IRQ, \
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+ .channel = I2C1_TX_DMA_CHANNEL \
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+ }
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
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#define I2C1_TX_DMA_CONFIG \
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{ \
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.dma_rcc = I2C1_TX_DMA_RCC, \
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@@ -39,11 +49,21 @@ extern "C" {
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.dma_irq = I2C1_TX_DMA_IRQ, \
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.request = DMA_REQUEST_I2C1_TX \
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}
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+#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
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#endif /* I2C1_TX_DMA_CONFIG */
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#endif /* BSP_I2C1_TX_USING_DMA */
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#ifdef BSP_I2C1_RX_USING_DMA
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#ifndef I2C1_RX_DMA_CONFIG
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+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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+#define I2C1_RX_DMA_CONFIG \
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+ { \
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+ .dma_rcc = I2C1_RX_DMA_RCC, \
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+ .Instance = I2C1_RX_DMA_INSTANCE, \
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+ .dma_irq = I2C1_RX_DMA_IRQ, \
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+ .channel = I2C1_RX_DMA_CHANNEL, \
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+ }
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
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#define I2C1_RX_DMA_CONFIG \
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{ \
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.dma_rcc = I2C1_RX_DMA_RCC, \
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@@ -51,6 +71,7 @@ extern "C" {
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.dma_irq = I2C1_RX_DMA_IRQ, \
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.request = DMA_REQUEST_I2C1_RX \
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}
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+#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
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#endif /* I2C1_RX_DMA_CONFIG */
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#endif /* BSP_I2C1_RX_USING_DMA */
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@@ -70,6 +91,15 @@ extern "C" {
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#ifdef BSP_I2C2_TX_USING_DMA
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#ifndef I2C2_TX_DMA_CONFIG
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+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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+#define I2C2_TX_DMA_CONFIG \
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+ { \
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+ .dma_rcc = I2C2_TX_DMA_RCC, \
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+ .Instance = I2C2_TX_DMA_INSTANCE, \
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+ .dma_irq = I2C2_TX_DMA_IRQ, \
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+ .channel = I2C2_TX_DMA_CHANNEL, \
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+ }
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
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#define I2C2_TX_DMA_CONFIG \
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{ \
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.dma_rcc = I2C2_TX_DMA_RCC, \
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@@ -77,11 +107,21 @@ extern "C" {
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.dma_irq = I2C2_TX_DMA_IRQ, \
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.request = DMA_REQUEST_I2C2_TX \
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}
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+#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
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#endif /* I2C2_TX_DMA_CONFIG */
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#endif /* BSP_I2C2_TX_USING_DMA */
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#ifdef BSP_I2C2_RX_USING_DMA
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#ifndef I2C2_RX_DMA_CONFIG
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+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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+#define I2C2_RX_DMA_CONFIG \
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+ { \
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+ .dma_rcc = I2C2_RX_DMA_RCC, \
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+ .Instance = I2C2_RX_DMA_INSTANCE, \
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+ .dma_irq = I2C2_RX_DMA_IRQ, \
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+ .channel = I2C2_RX_DMA_CHANNEL, \
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+ }
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
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#define I2C2_RX_DMA_CONFIG \
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{ \
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.dma_rcc = I2C2_RX_DMA_RCC, \
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@@ -89,6 +129,7 @@ extern "C" {
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.dma_irq = I2C2_RX_DMA_IRQ, \
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.request = DMA_REQUEST_I2C2_RX \
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}
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+#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
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#endif /* I2C2_RX_DMA_CONFIG */
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#endif /* BSP_I2C2_RX_USING_DMA */
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@@ -108,6 +149,15 @@ extern "C" {
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#ifdef BSP_I2C3_TX_USING_DMA
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#ifndef I2C3_TX_DMA_CONFIG
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+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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+#define I2C3_TX_DMA_CONFIG \
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+ { \
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+ .dma_rcc = I2C3_TX_DMA_RCC, \
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+ .Instance = I2C3_TX_DMA_INSTANCE, \
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+ .dma_irq = I2C3_TX_DMA_IRQ, \
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+ .channel = I2C3_TX_DMA_CHANNEL, \
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+ }
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
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#define I2C3_TX_DMA_CONFIG \
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{ \
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.dma_rcc = I2C3_TX_DMA_RCC, \
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@@ -115,11 +165,21 @@ extern "C" {
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.dma_irq = I2C3_TX_DMA_IRQ, \
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.request = DMA_REQUEST_I2C3_TX \
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}
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+#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
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#endif /* I2C3_TX_DMA_CONFIG */
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#endif /* BSP_I2C3_TX_USING_DMA */
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#ifdef BSP_I2C3_RX_USING_DMA
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#ifndef I2C3_RX_DMA_CONFIG
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+#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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+#define I2C3_RX_DMA_CONFIG \
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+ { \
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+ .dma_rcc = I2C3_RX_DMA_RCC, \
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+ .Instance = I2C3_RX_DMA_INSTANCE, \
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+ .dma_irq = I2C3_RX_DMA_IRQ, \
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+ .channel = I2C3_RX_DMA_CHANNEL, \
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+ }
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
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#define I2C3_RX_DMA_CONFIG \
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{ \
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.dma_rcc = I2C3_RX_DMA_RCC, \
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@@ -127,6 +187,7 @@ extern "C" {
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.dma_irq = I2C3_RX_DMA_IRQ, \
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.request = DMA_REQUEST_I2C3_RX \
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}
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+#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */
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#endif /* I2C3_RX_DMA_CONFIG */
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#endif /* BSP_I2C3_RX_USING_DMA */
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