Merge pull request #1632 from Guozhanxin/imx1052

[BSP][RT1052] Merge network drive.

bsp/imxrt1052-evk/drivers/SConscript

@@ -63,8 +63,11 @@ if GetDepend('BOARD_RT1050_EVK') or GetDepend('BOARD_RT1050_SeeedStudio'):
         CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']
         
 if GetDepend('BOARD_RT1050_FIRE') and GetDepend('RT_USING_LWIP'):
-    src += ['drv_eth_fire.c', 'fsl_phy_fire.c']
+    src += ['drv_eth.c', 'fsl_phy.c']
 
+if GetDepend('BOARD_RT1050_ATK') and GetDepend('RT_USING_LWIP'):
+    src += ['drv_eth.c', 'fsl_phy.c', 'drv_pcf8574.c']
+    
 if GetDepend('RT_USING_AUDIO'):
     src += ['drv_codec.c', 'fsl_wm8960.c']
 

bsp/imxrt1052-evk/drivers/drv_eth.c

@@ -30,13 +30,22 @@
 #include <netif/ethernetif.h>
 #include "lwipopts.h"
 
+#ifdef BOARD_RT1050_ATK
+    #include "drv_pcf8574.h"
+#endif
+
 #define ENET_RXBD_NUM (4)
 #define ENET_TXBD_NUM (4)
 #define ENET_RXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
 #define ENET_TXBUFF_SIZE (ENET_FRAME_MAX_FRAMELEN)
 
-#define PHY_ADDRESS     0x02u
+#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK)
+    #define PHY_ADDRESS     0x00u
+#endif
 
+#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio)
+    #define PHY_ADDRESS     0x02u
+#endif
 /* debug option */
 //#define ETH_RX_DUMP
 //#define ETH_TX_DUMP
@@ -128,8 +137,8 @@ void _enet_callback(ENET_Type *base, enet_handle_t *handle, enet_event_t event,
         break;
     }
 }
-
-static void _enet_io_init(void)
+#if defined(BOARD_RT1050_SeeedStudio) || defined(BOARD_RT1050_EVK)
+static void evk_enet_io_init(void)
 {
     CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
 
@@ -316,7 +325,285 @@ static void _enet_io_init(void)
                                                  Pull Up / Down Config. Field: 100K Ohm Pull Up
                                                  Hyst. Enable Field: Hysteresis Disabled */
 }
+#endif
+
+#ifdef BOARD_RT1050_ATK
+static void atk_enet_io_init(void)
+{
+    CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
+
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 is configured as ENET_RX_EN */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 is configured as ENET_TX_EN */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 is configured as ENET_REF_CLK */
+        1U);                                    /* Software Input On Field: Force input path of pad GPIO_B1_10 */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_14_ENET_MDC,            /* GPIO_EMC_40 is configured as ENET_MDC */
+        0);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_15_ENET_MDIO,           /* GPIO_EMC_41 is configured as ENET_MDIO */
+        0);                                    /* Software Input On Field: Input Path is determined by functionality */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 PAD functional properties : */
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 PAD functional properties : */
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 PAD functional properties : */
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 PAD functional properties : */
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 PAD functional properties : */
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 PAD functional properties : */
+        0x110F9);
 
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 PAD functional properties : */
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_14_ENET_MDC,
+        0x110F9);
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_15_ENET_MDIO,
+        0x110F9);
+
+    IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true); 
+    IOMUXC_GPR->GPR1 |= 1 << 23;  
+
+}
+#endif
+
+#ifdef BOARD_RT1050_FIRE
+static void fire_enet_io_init(void)
+{
+    CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
+
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 is configured as ENET_RX_ER */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 is configured as ENET_RX_EN */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 is configured as ENET_TX_EN */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 is configured as ENET_REF_CLK */
+        1U);                                    /* Software Input On Field: Force input path of pad GPIO_B1_10 */
+
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_AD_B1_04_ENET_MDC,            /* GPIO_EMC_40 is configured as ENET_MDC */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+    IOMUXC_SetPinMux(
+        IOMUXC_GPIO_B1_15_ENET_MDIO,           /* GPIO_EMC_41 is configured as ENET_MDIO */
+        0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_09_GPIO1_IO09,        /* GPIO_AD_B0_09 PAD functional properties : */
+        0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
+                                                 Drive Strength Field: R0/5
+                                                 Speed Field: medium(100MHz)
+                                                 Open Drain Enable Field: Open Drain Disabled
+                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                 Pull / Keep Select Field: Pull
+                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                 Hyst. Enable Field: Hysteresis Disabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_10_GPIO1_IO10,        /* GPIO_AD_B0_10 PAD functional properties : */
+        0xB0A9u);                               /* Slew Rate Field: Fast Slew Rate
+                                                 Drive Strength Field: R0/5
+                                                 Speed Field: medium(100MHz)
+                                                 Open Drain Enable Field: Open Drain Disabled
+                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                 Pull / Keep Select Field: Pull
+                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                 Hyst. Enable Field: Hysteresis Disabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 PAD functional properties : */
+        0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+                                                 Drive Strength Field: R0/6
+                                                 Speed Field: medium(100MHz)
+                                                 Open Drain Enable Field: Open Drain Disabled
+                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                 Pull / Keep Select Field: Keeper
+                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                 Hyst. Enable Field: Hysteresis Disabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 PAD functional properties : */
+        0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+                                                 Drive Strength Field: R0/6
+                                                 Speed Field: medium(100MHz)
+                                                 Open Drain Enable Field: Open Drain Disabled
+                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                 Pull / Keep Select Field: Keeper
+                                                 Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                 Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_04_ENET_RX_DATA00,       /* GPIO_B1_04 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+                                                 Drive Strength Field: R0/5
+                                                 Speed Field: max(200MHz)
+                                                 Open Drain Enable Field: Open Drain Disabled
+                                                 Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                 Pull / Keep Select Field: Pull
+                                                 Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                 Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_05_ENET_RX_DATA01,       /* GPIO_B1_05 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+                                                   Drive Strength Field: R0/5
+                                                   Speed Field: max(200MHz)
+                                                   Open Drain Enable Field: Open Drain Disabled
+                                                   Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                   Pull / Keep Select Field: Pull
+                                                   Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                   Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_06_ENET_RX_EN,           /* GPIO_B1_06 PAD functional properties : */
+        0xB0E9u);
+                                                /* Slew Rate Field: Fast Slew Rate
+                                                   Drive Strength Field: R0/5
+                                                   Speed Field: max(200MHz)
+                                                   Open Drain Enable Field: Open Drain Disabled
+                                                   Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                   Pull / Keep Select Field: Pull
+                                                   Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                   Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_07_ENET_TX_DATA00,       /* GPIO_B1_07 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0/5
+                                                    Speed Field: max(200MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 100K Ohm Pull Up
+
+                                                 Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_08_ENET_TX_DATA01,       /* GPIO_B1_08 PAD functional properties : */
+        0xB0E9u);                              /* Slew Rate Field: Fast Slew Rate
+                                                   Drive Strength Field: R0/5
+                                                   Speed Field: max(200MHz)
+                                                   Open Drain Enable Field: Open Drain Disabled
+                                                   Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                   Pull / Keep Select Field: Pull
+                                                   Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                   Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_09_ENET_TX_EN,           /* GPIO_B1_09 PAD functional properties : */
+        0xB0E9u);                              /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0/5
+                                                    Speed Field: max(200MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_10_ENET_REF_CLK,         /* GPIO_B1_10 PAD functional properties : */
+        0x31u);                                /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0/6
+                                                    Speed Field: low(50MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Disabled
+                                                    Pull / Keep Select Field: Keeper
+                                                    Pull Up / Down Config. Field: 100K Ohm Pull Down
+                                                    Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_11_ENET_RX_ER,           /* GPIO_B1_11 PAD functional properties : */
+        0xB0E9u);                               /* Slew Rate Field: Fast Slew Rate
+                                                    Drive Strength Field: R0/5
+                                                    Speed Field: max(200MHz)
+                                                    Open Drain Enable Field: Open Drain Disabled
+                                                    Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                    Pull / Keep Select Field: Pull
+                                                    Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                    Hyst. Enable Field: Hysteresis Disabled */
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_AD_B1_04_ENET_MDC,
+        0xB0E9u);                              /* Slew Rate Field: Fast Slew Rate
+                                                   Drive Strength Field: R0/5
+                                                   Speed Field: max(200MHz)
+                                                   Open Drain Enable Field: Open Drain Disabled
+                                                   Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                   Pull / Keep Select Field: Pull
+                                                   Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                   Hyst. Enable Field: Hysteresis Disabled */
+
+    IOMUXC_SetPinConfig(
+        IOMUXC_GPIO_B1_15_ENET_MDIO,
+        0xB829u);                              /* Slew Rate Field: Fast Slew Rate
+                                                   Drive Strength Field: R0/5
+                                                   Speed Field: low(50MHz)
+                                                   Open Drain Enable Field: Open Drain Enabled
+                                                   Pull / Keep Enable Field: Pull/Keeper Enabled
+                                                   Pull / Keep Select Field: Pull
+                                                   Pull Up / Down Config. Field: 100K Ohm Pull Up
+                                                   Hyst. Enable Field: Hysteresis Disabled */
+} 
+#endif
 static void _enet_clk_init(void)
 {
     const clock_enet_pll_config_t config = {true, false, 1};
@@ -337,13 +624,22 @@ static void _enet_phy_reset_by_gpio(void)
 {
     gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
 
+#ifndef BOARD_RT1050_ATK
     GPIO_PinInit(GPIO1, 9, &gpio_config);
+#endif
     GPIO_PinInit(GPIO1, 10, &gpio_config);
     /* pull up the ENET_INT before RESET. */
     GPIO_WritePinOutput(GPIO1, 10, 1);
+
+#ifdef BOARD_RT1050_ATK
+    pcf8574_write_bit(7, 1);
+    _delay();
+    pcf8574_write_bit(7, 0);
+#else
     GPIO_WritePinOutput(GPIO1, 9, 0);
     _delay();
     GPIO_WritePinOutput(GPIO1, 9, 1);
+#endif
 }
 
 static void _enet_config(void)
@@ -656,7 +952,8 @@ static status_t _ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const ui
             /* Get the current buffer descriptor address. */
             curBuffDescrip = handle->txBdCurrent[0];
 
-        } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
+        }
+        while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
 
         return kStatus_ENET_TxFrameBusy;
     }
@@ -821,18 +1118,27 @@ static void phy_monitor_thread_entry(void *parameter)
 static int rt_hw_imxrt_eth_init(void)
 {
     rt_err_t state;
+    
+#ifdef BOARD_RT1050_ATK
+    atk_enet_io_init();
+#endif
 
-    _enet_io_init();
-    _enet_clk_init();
+#ifdef BOARD_RT1050_FIRE
+    fire_enet_io_init();
+#endif
 
+#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio)
+    evk_enet_io_init();
+#endif
+    _enet_clk_init();
     /* OUI 00-80-E1 STMICROELECTRONICS. */
     imxrt_eth_device.dev_addr[0] = 0x00;
     imxrt_eth_device.dev_addr[1] = 0x04;
     imxrt_eth_device.dev_addr[2] = 0x9F;
     /* generate MAC addr from 96bit unique ID (only for test). */
     imxrt_eth_device.dev_addr[3] = 0x08;
-    imxrt_eth_device.dev_addr[4] = 0x44;
-    imxrt_eth_device.dev_addr[5] = 0xE5;
+    imxrt_eth_device.dev_addr[4] = 0x43;
+    imxrt_eth_device.dev_addr[5] = 0x75;
 
     imxrt_eth_device.speed = kENET_MiiSpeed100M;
     imxrt_eth_device.duplex = kENET_MiiFullDuplex;
@@ -883,7 +1189,11 @@ static int rt_hw_imxrt_eth_init(void)
 
     return state;
 }
-INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
+#ifdef BOARD_RT1050_ATK
+    INIT_ENV_EXPORT(rt_hw_imxrt_eth_init);
+#else
+    INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
+#endif
 #endif
 
 #ifdef RT_USING_FINSH

bsp/imxrt1052-evk/drivers/drv_pcf8574.c

@@ -0,0 +1,69 @@
+/*
+ * File      : drv_pcf8574.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-06-12     zylx     the first version.
+ */
+#include "drv_pcf8574.h"
+
+#define PCF8574_I2CBUS_NAME  "i2c1"
+static struct rt_i2c_bus_device *pcf8574_i2c_bus;
+
+int pcf8574_Init(void)
+{
+    rt_uint8_t value = 0x01;
+
+    pcf8574_i2c_bus = rt_i2c_bus_device_find(PCF8574_I2CBUS_NAME);
+
+    if (pcf8574_i2c_bus == RT_NULL)
+    {
+        rt_kprintf("can't find i2c device\r\n");
+        return -RT_ERROR;
+    }
+
+    if (!rt_i2c_master_send(pcf8574_i2c_bus, PCF8574_ADDR, 0, &value, 1))
+    {
+        rt_kprintf("can't find pcf8574\r\n");
+        return -RT_ERROR;
+    }
+
+    return 0;
+}
+INIT_COMPONENT_EXPORT(pcf8574_Init);
+
+rt_uint8_t pcf8574_read_byte(void)
+{
+    rt_uint8_t temp = 0;
+    rt_i2c_master_recv(pcf8574_i2c_bus, PCF8574_ADDR, 0, &temp, 1);
+    return temp;
+}
+
+void pcf8574_write_byte(rt_uint8_t data)
+{
+    rt_i2c_master_send(pcf8574_i2c_bus, PCF8574_ADDR, 0, &data, 1);
+}
+
+void pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t sta)
+{
+    rt_uint8_t data;
+    data = pcf8574_read_byte();
+    if (sta == 0)data &= ~(1 << bit);
+    else data |= 1 << bit;
+    pcf8574_write_byte(data);
+}
+
+rt_uint8_t pcf8574_read_bit(rt_uint8_t bit)
+{
+    rt_uint8_t data;
+    data = pcf8574_read_byte();
+    if (data & (1 << bit))return 1;
+    else return 0;
+}
+

bsp/imxrt1052-evk/drivers/drv_pcf8574.h

@@ -0,0 +1,28 @@
+/*
+ * File      : drv_pcf8574.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-06-12     zylx     the first version.
+ */
+#ifndef __PCF8574_H
+#define __PCF8574_H
+
+#include <rtthread.h>
+#include "rtdevice.h"
+
+#define PCF8574_ADDR 0X20	
+
+rt_uint8_t pcf8574_read_byte(void);
+void pcf8574_write_byte(rt_uint8_t data);
+void pcf8574_write_bit(rt_uint8_t bit, rt_uint8_t sta);
+rt_uint8_t pcf8574_read_bit(rt_uint8_t bit);
+
+#endif
+

bsp/imxrt1052-evk/drivers/fsl_phy.c

@@ -69,8 +69,6 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     uint32_t idReg = 0;
     status_t result = kStatus_Success;
     uint32_t instance = ENET_GetInstance(base);
-    uint32_t timeDelay;
-    uint32_t ctlReg = 0;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Set SMI first. */
@@ -95,7 +93,19 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
     result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
     if (result == kStatus_Success)
     {
-
+#if defined(BOARD_RT1050_FIRE)
+        for (uint32_t i = 0x10000; i > 0; i--)
+        {
+            result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg);
+            if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK))
+            {
+                break;
+            }
+        }
+#endif
+#if defined(BOARD_RT1050_ATK)
+      rt_thread_delay(RT_TICK_PER_SECOND);  
+#endif
 #if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
         uint32_t data = 0;
         result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
@@ -126,16 +136,22 @@ status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
                     result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
                     if ( result == kStatus_Success)
                     {
+#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK)
+                        if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0))
+#else
+                        uint32_t ctlReg = 0;
                         PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
                         if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
+#endif
                         {
-                            /* Wait a moment for Phy status stable. */
-                            for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
-                            {
-                                __ASM("nop");
-                            }
+                            rt_kprintf("auto negotiation complete success\n");
                             break;
                         }
+                        else
+                        {
+                         /* Wait a moment for Phy status stable. */
+                                __ASM("nop");
+                        }
                     }
                     
                     rt_kprintf("[PHY] wait autonegotiation complete...\n");
@@ -309,7 +325,12 @@ status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *
     uint32_t data, ctlReg;
 
     /* Read the control two register. */
+#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK)
+    result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg);
+#endif
+#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio)
     result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
+#endif
     if (result == kStatus_Success)
     {
         data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;

bsp/imxrt1052-evk/drivers/fsl_phy.h

@@ -29,7 +29,7 @@
  */
 #ifndef _FSL_PHY_H_
 #define _FSL_PHY_H_
-
+#include "rtconfig.h"
 #include "fsl_enet.h"
 
 /*!
@@ -53,8 +53,12 @@
 #define PHY_CONTROL1_REG 0x1EU          /*!< The PHY control one register. */
 #define PHY_CONTROL2_REG 0x1FU          /*!< The PHY control two register. */
 
+#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK)
+#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
+#endif
+#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio)
 #define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
-
+#endif
 /*! @brief Defines the mask flag in basic control register. */
 #define PHY_BCTL_DUPLEX_MASK 0x0100U          /*!< The PHY duplex bit mask. */
 #define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
@@ -63,8 +67,23 @@
 #define PHY_BCTL_LOOP_MASK 0x4000U            /*!< The PHY loop bit mask. */
 #define PHY_BCTL_RESET_MASK 0x8000U           /*!< The PHY reset bit mask. */
 #define PHY_BCTL_SPEED_100M_MASK  0x2000U     /*!< The PHY 100M speed mask. */
+#define PHY_BCTL_POWER_DOWN_MASK  0x800U      /*!< The PHY Power Down mask. */
+
 
 /*!@brief Defines the mask flag of operation mode in control two register*/
+#if defined(BOARD_RT1050_FIRE) || defined(BOARD_RT1050_ATK)
+#define PHY_CTL2_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
+#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 
+#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U  /*!< The PHY 10M half duplex mask. */
+#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */
+#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U  /*!< The PHY 10M full duplex mask. */
+#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */
+#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU     /*!< The PHY speed and duplex mask. */
+#define PHY_CTL1_ENERGYDETECT_MASK 0x10U    /*!< The PHY signal present on rx differential pair. */
+#define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */        
+#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
+#endif
+#if defined(BOARD_RT1050_EVK) || defined(BOARD_RT1050_SeeedStudio)
 #define PHY_CTL2_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
 #define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 
 #define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U  /*!< The PHY 10M half duplex mask. */
@@ -75,7 +94,7 @@
 #define PHY_CTL1_ENERGYDETECT_MASK 0x10U    /*!< The PHY signal present on rx differential pair. */
 #define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */        
 #define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
-   
+#endif   
 /*! @brief Defines the mask flag in basic status register. */
 #define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U  /*!< The PHY link status mask. */
 #define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */

bsp/imxrt1052-evk/drivers/fsl_phy_fire.c

@@ -1,319 +0,0 @@
-/*
- * File      : fsl_phy_fire.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-05-21     zylx         first version
- */
-
-#include "fsl_phy_fire.h"
-#include <rtthread.h>
-
-#define DBG_ENABLE
-#define DBG_SECTION_NAME    "PHY"
-#define DBG_COLOR
-#define DBG_LEVEL           DBG_LOG
-#include <rtdbg.h>
-
-#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
-
-extern uint32_t ENET_GetInstance(ENET_Type *base);
-
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to enet clocks for each instance. */
-extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*******************************************************************************
- * Code
- ******************************************************************************/
-
-status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
-{
-    uint32_t bssReg;
-    uint32_t i;
-    uint32_t counter = PHY_TIMEOUT_COUNT;
-    uint32_t idReg = 0;
-    status_t result = kStatus_Success;
-    uint32_t instance = ENET_GetInstance(base);
-    uint32_t timeDelay;
-
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-    /* Set SMI first. */
-    CLOCK_EnableClock(s_enetClock[instance]);
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-    ENET_SetSMI(base, srcClock_Hz, false);
-
-    /* Initialization after PHY stars to work. */
-    while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
-    {
-        PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
-        counter --;
-    }
-
-    if (!counter)
-    {
-        return kStatus_Fail;
-    }
-
-    /* Reset PHY. */
-    counter = PHY_TIMEOUT_COUNT;
-    result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
-    if (result == kStatus_Success)
-    {
-        for (i = 0x10000; i > 0; i--)
-        {
-            result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &bssReg);
-            if (!(bssReg & PHY_BCTL_POWER_DOWN_MASK))
-            {
-                break;
-            }
-        }
-
-        if (i != 0)
-        {
-            /* Set the negotiation. */
-            result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
-                               (PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
-                                PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
-            if (result == kStatus_Success)
-            {
-                result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
-                                   (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
-                if (result == kStatus_Success)
-                {
-                    /* Check auto negotiation complete. */
-                    while (counter --)
-                    {
-                        result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
-                        if (result == kStatus_Success)
-                        {
-                            if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0))
-                            {
-                                rt_thread_delay(1);
-                            }
-                            else
-                            {
-                                dbg_log(DBG_LOG, "auto negotiation complete success\n");
-                                break;
-                            }
-                        }
-                    }
-
-                    if (!counter)
-                    {
-                        dbg_log(DBG_LOG, "auto negotiation complete falied\n");
-                        return kStatus_PHY_AutoNegotiateFail;
-                    }
-
-                }
-            }
-        }
-    }
-
-    return result;
-}
-
-status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
-{
-    uint32_t counter;
-
-    /* Clear the SMI interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-    /* Starts a SMI write command. */
-    ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
-
-    /* Wait for SMI complete. */
-    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
-    {
-        if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
-        {
-            break;
-        }
-    }
-
-    /* Check for timeout. */
-    if (!counter)
-    {
-        return kStatus_PHY_SMIVisitTimeout;
-    }
-
-    /* Clear MII interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-    return kStatus_Success;
-}
-
-status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
-{
-    assert(dataPtr);
-
-    uint32_t counter;
-
-    /* Clear the MII interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-    /* Starts a SMI read command operation. */
-    ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
-
-    /* Wait for MII complete. */
-    for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
-    {
-        if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
-        {
-            break;
-        }
-    }
-
-    /* Check for timeout. */
-    if (!counter)
-    {
-        return kStatus_PHY_SMIVisitTimeout;
-    }
-
-    /* Get data from MII register. */
-    *dataPtr = ENET_ReadSMIData(base);
-
-    /* Clear MII interrupt event. */
-    ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
-
-    return kStatus_Success;
-}
-
-status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
-{
-    status_t result;
-    uint32_t data = 0;
-
-    /* Set the loop mode. */
-    if (enable)
-    {
-        if (mode == kPHY_LocalLoop)
-        {
-            if (speed == kPHY_Speed100M)
-            {
-                data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
-            }
-            else
-            {
-                data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
-            }
-            return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
-        }
-        else
-        {
-            /* First read the current status in control register. */
-            result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
-            if (result == kStatus_Success)
-            {
-                return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
-            }
-        }
-    }
-    else
-    {
-        /* Disable the loop mode. */
-        if (mode == kPHY_LocalLoop)
-        {
-            /* First read the current status in control register. */
-            result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
-            if (result == kStatus_Success)
-            {
-                data &= ~PHY_BCTL_LOOP_MASK;
-                return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
-            }
-        }
-        else
-        {
-            /* First read the current status in control one register. */
-            result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
-            if (result == kStatus_Success)
-            {
-                return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
-            }
-        }
-    }
-    return result;
-}
-
-status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
-{
-    assert(status);
-
-    status_t result = kStatus_Success;
-    uint32_t data;
-
-    /* Read the basic status register. */
-    result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
-    if (result == kStatus_Success)
-    {
-        if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
-        {
-            /* link down. */
-            *status = false;
-        }
-        else
-        {
-            /* link up. */
-            *status = true;
-        }
-    }
-    return result;
-}
-
-status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
-{
-    assert(duplex);
-
-    status_t result = kStatus_Success;
-    uint32_t data, ctlReg;
-
-    /* Read the control two register. */
-    result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &ctlReg);
-    if (result == kStatus_Success)
-    {
-        data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
-        if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
-        {
-            /* Full duplex. */
-            *duplex = kPHY_FullDuplex;
-        }
-        else
-        {
-            /* Half duplex. */
-            *duplex = kPHY_HalfDuplex;
-        }
-
-        data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
-        if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
-        {
-            /* 100M speed. */
-            *speed = kPHY_Speed100M;
-        }
-        else
-        {
-            /* 10M speed. */
-            *speed = kPHY_Speed10M;
-        }
-    }
-
-    return result;
-}

bsp/imxrt1052-evk/drivers/fsl_phy_fire.h

@@ -1,223 +0,0 @@
-/*
- * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef _FSL_PHY_FIRE_H_
-#define _FSL_PHY_FIRE_H_
-
-#include "fsl_enet.h"
-
-/*!
- * @addtogroup phy_driver
- * @{
- */
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
-
-/*! @brief PHY driver version */
-#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
-
-/*! @brief Defines the PHY registers. */
-#define PHY_BASICCONTROL_REG 0x00U      /*!< The PHY basic control register. */
-#define PHY_BASICSTATUS_REG 0x01U       /*!< The PHY basic status register. */
-#define PHY_ID1_REG 0x02U               /*!< The PHY ID one register. */
-#define PHY_ID2_REG 0x03U               /*!< The PHY ID two register. */
-#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
-#define PHY_CONTROL1_REG 0x1EU          /*!< The PHY control one register. */
-#define PHY_CONTROL2_REG 0x1FU          /*!< The PHY control two register. */
-
-#define PHY_CONTROL_ID1 0x07U /*!< The PHY ID1*/
-
-/*! @brief Defines the mask flag in basic control register. */
-#define PHY_BCTL_DUPLEX_MASK 0x0100U          /*!< The PHY duplex bit mask. */
-#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
-#define PHY_BCTL_AUTONEG_MASK 0x1000U         /*!< The PHY auto negotiation bit mask. */
-#define PHY_BCTL_SPEED_MASK 0x2000U           /*!< The PHY speed bit mask. */
-#define PHY_BCTL_LOOP_MASK 0x4000U            /*!< The PHY loop bit mask. */
-#define PHY_BCTL_RESET_MASK 0x8000U           /*!< The PHY reset bit mask. */
-#define PHY_BCTL_SPEED_100M_MASK  0x2000U     /*!< The PHY 100M speed mask. */
-#define PHY_BCTL_POWER_DOWN_MASK  0x800U      /*!< The PHY Power Down mask. */
-
-/*!@brief Defines the mask flag of operation mode in control two register*/
-#define PHY_CTL2_REMOTELOOP_MASK 0x0004U    /*!< The PHY remote loopback mask. */
-#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */ 
-#define PHY_CTL1_10HALFDUPLEX_MASK 0x0004U  /*!< The PHY 10M half duplex mask. */
-#define PHY_CTL1_100HALFDUPLEX_MASK 0x0008U /*!< The PHY 100M half duplex mask. */
-#define PHY_CTL1_10FULLDUPLEX_MASK 0x0014U  /*!< The PHY 10M full duplex mask. */
-#define PHY_CTL1_100FULLDUPLEX_MASK 0x0018U /*!< The PHY 100M full duplex mask. */
-#define PHY_CTL1_SPEEDUPLX_MASK 0x001CU     /*!< The PHY speed and duplex mask. */
-#define PHY_CTL1_ENERGYDETECT_MASK 0x10U    /*!< The PHY signal present on rx differential pair. */
-#define PHY_CTL1_LINKUP_MASK 0x100U         /*!< The PHY link up. */        
-#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
-   
-/*! @brief Defines the mask flag in basic status register. */
-#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U  /*!< The PHY link status mask. */
-#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
-#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
-
-/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
-#define PHY_100BaseT4_ABILITY_MASK 0x200U    /*!< The PHY have the T4 ability. */
-#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
-#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
-#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U  /*!< The PHY has the 10M full duplex ability.*/
-#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U  /*!< The PHY has the 10M full duplex ability.*/
-
-/*! @brief Defines the PHY status. */
-enum _phy_status
-{
-    kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1),  /*!< ENET PHY SMI visit timeout. */
-    kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
-};
-
-/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
-typedef enum _phy_speed
-{
-    kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
-    kPHY_Speed100M      /*!< ENET PHY 100M speed. */
-} phy_speed_t;
-
-/*! @brief Defines the PHY link duplex. */
-typedef enum _phy_duplex
-{
-    kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
-    kPHY_FullDuplex       /*!< ENET PHY full duplex. */
-} phy_duplex_t;
-
-/*! @brief Defines the PHY loopback mode. */
-typedef enum _phy_loop
-{
-    kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
-    kPHY_RemoteLoop      /*!< ENET PHY remote loopback. */
-} phy_loop_t;
-
-/*******************************************************************************
- * API
- ******************************************************************************/
-
-#if defined(__cplusplus)
-extern "C" {
-#endif
-
-/*!
-  * @name PHY Driver
-  * @{
-  */
-
-/*!
- * @brief Initializes PHY.
- *
- *  This function initialize the SMI interface and initialize PHY.
- *  The SMI is the MII management interface between PHY and MAC, which should be
- *  firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. 
- *
- * @param base       ENET peripheral base address.
- * @param phyAddr    The PHY address.
- * @param srcClock_Hz  The module clock frequency - system clock for MII management interface - SMI.
- * @retval kStatus_Success  PHY initialize success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- * @retval kStatus_PHY_AutoNegotiateFail  PHY auto negotiate fail
- */
-status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
-
-/*!
- * @brief PHY Write function. This function write data over the SMI to
- * the specified PHY register. This function is called by all PHY interfaces.
- *
- * @param base    ENET peripheral base address.
- * @param phyAddr The PHY address.
- * @param phyReg  The PHY register.
- * @param data    The data written to the PHY register.
- * @retval kStatus_Success     PHY write success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
-
-/*!
- * @brief PHY Read function. This interface read data over the SMI from the
- * specified PHY register. This function is called by all PHY interfaces.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param phyReg   The PHY register.
- * @param dataPtr  The address to store the data read from the PHY register.
- * @retval kStatus_Success  PHY read success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
-
-/*!
- * @brief Enables/disables PHY loopback.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param mode     The loopback mode to be enabled, please see "phy_loop_t".
- * the two loopback mode should not be both set. when one loopback mode is set
- * the other one should be disabled.
- * @param speed    PHY speed for loopback mode.
- * @param enable   True to enable, false to disable.
- * @retval kStatus_Success  PHY loopback success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
-
-/*!
- * @brief Gets the PHY link status.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param status   The link up or down status of the PHY.
- *         - true the link is up.
- *         - false the link is down.
- * @retval kStatus_Success   PHY get link status success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
-
-/*!
- * @brief Gets the PHY link speed and duplex.
- *
- * @param base     ENET peripheral base address.
- * @param phyAddr  The PHY address.
- * @param speed    The address of PHY link speed.
- * @param duplex   The link duplex of PHY.
- * @retval kStatus_Success   PHY get link speed and duplex success
- * @retval kStatus_PHY_SMIVisitTimeout  PHY SMI visit time out
- */
-status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
-
-/* @} */
-
-#if defined(__cplusplus)
-}
-#endif
-
-/*! @}*/
-
-#endif /* _FSL_PHY_H_ */