[bsp][nxp][mcxa153] driver code formatted

bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pwm.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2024 RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,20 +18,20 @@ typedef struct
 {
     struct rt_device_pwm pwm_device;
     CTIMER_Type *ct_instance;
-	uint32_t timerClock;
-	const ctimer_match_t pwmPeriodChannel;
+    uint32_t timerClock;
+    const ctimer_match_t pwmPeriodChannel;
     ctimer_match_t matchChannel;
-	char *name;
+    char *name;
 } mcx_pwm_obj_t;
 
-static mcx_pwm_obj_t mcx_pwm_list[]= 
+static mcx_pwm_obj_t mcx_pwm_list[]=
 {
 #ifdef BSP_USING_PWM0
     {
         .ct_instance = CTIMER1,
         .timerClock = 0,
-		.pwmPeriodChannel = kCTIMER_Match_3,
-		.matchChannel = kCTIMER_Match_2,
+        .pwmPeriodChannel = kCTIMER_Match_3,
+        .matchChannel = kCTIMER_Match_2,
         .name = "pwm0",
     }
 #endif
@@ -54,9 +54,9 @@ status_t CTIMER_GetPwmPeriodValue(uint32_t pwmFreqHz, uint8_t dutyCyclePercent,
 static rt_err_t mcx_drv_pwm_set(mcx_pwm_obj_t *pwm, struct rt_pwm_configuration *configuration)
 {
     CTIMER_Type *ct = pwm->ct_instance;
-	uint32_t pwmFreqHz = 1000000000 / configuration->period;
-	uint8_t dutyCyclePercent = configuration->pulse * 100 / configuration->period; 
-	CTIMER_GetPwmPeriodValue(pwmFreqHz, dutyCyclePercent, pwm->timerClock);
+    uint32_t pwmFreqHz = 1000000000 / configuration->period;
+    uint8_t dutyCyclePercent = configuration->pulse * 100 / configuration->period;
+    CTIMER_GetPwmPeriodValue(pwmFreqHz, dutyCyclePercent, pwm->timerClock);
     CTIMER_SetupPwmPeriod(ct, kCTIMER_Match_3, kCTIMER_Match_2, g_pwmPeriod, g_pulsePeriod, false);
     return 0;
 }
@@ -108,13 +108,13 @@ int mcx_pwm_init(void)
 {
     rt_err_t ret;
     char name_buf[8];
-	
-	ctimer_config_t config;
-	CTIMER_GetDefaultConfig(&config);
+
+    ctimer_config_t config;
+    CTIMER_GetDefaultConfig(&config);
     for (uint8_t i = 0; i < ARRAY_SIZE(mcx_pwm_list); i++)
     {
         mcx_pwm_list[i].timerClock = CLOCK_GetCTimerClkFreq(1U) / (config.prescale + 1);
-		CTIMER_Init(mcx_pwm_list[i].ct_instance, &config);
+        CTIMER_Init(mcx_pwm_list[i].ct_instance, &config);
         ret = rt_device_pwm_register(&mcx_pwm_list[i].pwm_device, mcx_pwm_list[i].name, &mcx_pwm_ops, &mcx_pwm_list[i]);
         if (ret != RT_EOK)
         {

bsp/nxp/mcx/mcxa/Libraries/drivers/drv_pwm.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2024 RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/nxp/mcx/mcxa/Libraries/drivers/drv_spi.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2024 RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -119,7 +119,7 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m
     transfer.rxData   = (uint8_t *)(message->recv_buf);
     transfer.txData   = (uint8_t *)(message->send_buf);
 
-    //  if(message->length < MAX_DMA_TRANSFER_SIZE)
+    /*  if(message->length < MAX_DMA_TRANSFER_SIZE)*/
     if (0)
     {
         LPSPI_MasterTransferBlocking(spi->LPSPIx, &transfer);

bsp/nxp/mcx/mcxa/Libraries/drivers/drv_spi.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2024 RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/nxp/mcx/mcxa/frdm-mcxa153/board/MCUX_Config/board/pin_mux.c

@@ -44,17 +44,17 @@ void BOARD_InitPins(void)
     CLOCK_EnableClock(kCLOCK_GateGPIO1);
     CLOCK_EnableClock(kCLOCK_GateGPIO2);
     CLOCK_EnableClock(kCLOCK_GateGPIO3);
-	
-	CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u);
+
+    CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u);
     CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
 
     RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
     RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
     RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
-	
-	RESET_ReleasePeripheralReset(kCTIMER1_RST_SHIFT_RSTn);
-	RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn);
-	
+
+    RESET_ReleasePeripheralReset(kCTIMER1_RST_SHIFT_RSTn);
+    RESET_ReleasePeripheralReset(kLPSPI0_RST_SHIFT_RSTn);
+
     RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
     RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
     RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
@@ -114,10 +114,10 @@ void BOARD_InitPins(void)
                                                     kPORT_UnlockRegister};
     /* PORT0_3 (pin 52) is configured as LPUART0_TXD */
     PORT_SetPinConfig(PORT0, 3U, &port0_3_pin52_config);
-	
+
 #ifdef BSP_USING_PWM0
-	ctimer_config_t config;
-	CTIMER_Init(CTIMER1, &config);
+    ctimer_config_t config;
+    CTIMER_Init(CTIMER1, &config);
     const port_pin_config_t port1_4_pin62_config = {/* Internal pull-up/down resistor is disabled */
                                                     kPORT_PullDisable,
                                                     /* Low internal pull resistor value is selected. */

bsp/nxp/mcx/mcxa/frdm-mcxa153/board/board.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2024, RT-Thread Development Team
+ * Copyright (c) 2006-2024 RT-Thread Development Team
  * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -37,8 +37,8 @@ void SysTick_Handler(void)
 void rt_hw_board_init()
 {
     BOARD_InitBootPins();
-	
-	edma_config_t userConfig = {0};
+
+    edma_config_t userConfig = {0};
     EDMA_GetDefaultConfig(&userConfig);
     EDMA_Init(DMA0, &userConfig);