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@@ -0,0 +1,220 @@
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+/*
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+ * Copyright (c) 2006-2021, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2021-10-25 KevinXu first version
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+ */
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+
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+#include "drv_pwm.h"
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+
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+#ifdef RT_USING_PWM
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+
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+/* Declare the control function first */
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+static rt_err_t drv_pwm_control(struct rt_device_pwm *, int, void *);
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+static struct rt_pwm_ops drv_ops =
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+{
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+ drv_pwm_control
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+};
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+
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+static struct ra_pwm ra6m4_pwm_obj[BSP_PWMS_NUM] =
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+{
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+#ifdef BSP_USING_PWM0
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+ [BSP_PWM0_INDEX] = PWM_DRV_INITIALIZER(0),
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+#endif
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+#ifdef BSP_USING_PWM1
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+ [BSP_PWM1_INDEX] = PWM_DRV_INITIALIZER(1),
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+#endif
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+#ifdef BSP_USING_PWM2
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+ [BSP_PWM2_INDEX] = PWM_DRV_INITIALIZER(2),
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+#endif
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+#ifdef BSP_USING_PWM3
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+ [BSP_PWM3_INDEX] = PWM_DRV_INITIALIZER(3),
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+#endif
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+#ifdef BSP_USING_PWM4
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+ [BSP_PWM4_INDEX] = PWM_DRV_INITIALIZER(4),
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+#endif
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+#ifdef BSP_USING_PWM5
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+ [BSP_PWM5_INDEX] = PWM_DRV_INITIALIZER(5),
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+#endif
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+#ifdef BSP_USING_PWM6
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+ [BSP_PWM6_INDEX] = PWM_DRV_INITIALIZER(6),
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+#endif
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+#ifdef BSP_USING_PWM7
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+ [BSP_PWM7_INDEX] = PWM_DRV_INITIALIZER(7),
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+#endif
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+#ifdef BSP_USING_PWM8
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+ [BSP_PWM8_INDEX] = PWM_DRV_INITIALIZER(8),
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+#endif
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+#ifdef BSP_USING_PWM9
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+ [BSP_PWM9_INDEX] = PWM_DRV_INITIALIZER(9),
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+#endif
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+};
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+
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+
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+/* Convert the raw PWM period counts into ns */
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+static rt_uint32_t _convert_counts_ns(uint32_t source_div, uint32_t raw)
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+{
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+ uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
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+ uint32_t ns = (uint32_t)(((uint64_t)raw * 1000000000ULL) / pclkd_freq_hz);
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+ return ns;
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+}
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+
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+/* Convert ns into raw PWM period counts */
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+static rt_uint32_t _convert_ns_counts(uint32_t source_div, uint32_t raw)
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+{
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+ uint32_t pclkd_freq_hz = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_PCLKD) >> source_div;
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+ uint32_t counts = (uint32_t)(((uint64_t)raw * (uint64_t)pclkd_freq_hz) / 1000000000ULL);
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+ return counts;
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+}
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+
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+
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+/* PWM_CMD_ENABLE or PWM_CMD_DISABLE */
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+static rt_err_t drv_pwm_enable(struct ra_pwm *device,
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+ struct rt_pwm_configuration *configuration,
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+ rt_bool_t enable)
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+{
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+ fsp_err_t err = FSP_SUCCESS;
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+
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+ if (enable)
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+ {
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+ err = R_GPT_Start(device->g_ctrl);
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+ }
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+ else
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+ {
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+ err = R_GPT_Stop(device->g_ctrl);
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+ }
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+
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+ return (err == FSP_SUCCESS) ? RT_EOK : -RT_ERROR;
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+}
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+
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+/* PWM_CMD_GET */
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+static rt_err_t drv_pwm_get(struct ra_pwm *device,
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+ struct rt_pwm_configuration *configuration)
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+{
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+ timer_info_t info;
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+ if (R_GPT_InfoGet(device->g_ctrl, &info) != FSP_SUCCESS)
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+ return -RT_ERROR;
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+
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+ configuration->pulse =
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+ _convert_counts_ns(device->g_cfg->source_div, device->g_cfg->duty_cycle_counts);
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+ configuration->period =
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+ _convert_counts_ns(device->g_cfg->source_div, info.period_counts);
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+ configuration->channel = device->g_cfg->channel;
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+
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+ return RT_EOK;
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+}
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+
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+/* PWM_CMD_SET */
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+static rt_err_t drv_pwm_set(struct ra_pwm *device,
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+ struct rt_pwm_configuration *conf)
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+{
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+ uint32_t counts;
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+ fsp_err_t fsp_erra;
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+ fsp_err_t fsp_errb;
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+ rt_err_t rt_err;
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+ uint32_t pulse;
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+ uint32_t period;
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+ struct rt_pwm_configuration orig_conf;
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+
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+ rt_err = drv_pwm_get(device, &orig_conf);
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+ if (rt_err != RT_EOK)
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+ {
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+ return rt_err;
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+ }
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+
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+ /* Pulse cannot last longer than period. */
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+ period = conf->period;
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+ pulse = (period >= conf->pulse) ? conf->pulse : period;
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+
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+ /* Not to set period again if it's not changed. */
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+ if (period != orig_conf.period)
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+ {
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+ counts = _convert_ns_counts(device->g_cfg->source_div, period);
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+ fsp_erra = R_GPT_PeriodSet(device->g_ctrl, counts);
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+ if (fsp_erra != FSP_SUCCESS)
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+ {
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+ return -RT_ERROR;
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+ }
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+ }
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+
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+ /* Two pins of a channel will not be separated. */
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+ counts = _convert_ns_counts(device->g_cfg->source_div, pulse);
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+ fsp_erra = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCA);
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+ fsp_errb = R_GPT_DutyCycleSet(device->g_ctrl, counts, GPT_IO_PIN_GTIOCB);
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+ if (fsp_erra != FSP_SUCCESS || fsp_errb != FSP_SUCCESS)
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+ {
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+ return -RT_ERROR;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+/**
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+ * Implement of control method in struct rt_pwm_ops.
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+ */
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+static rt_err_t drv_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
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+{
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+ struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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+ struct ra_pwm *pwm_device = (struct ra_pwm *)device->parent.user_data;
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+
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+ /**
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+ * There's actually only one GPT timer with 10 channels. In this case, the
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+ * timer is separated into 10 PWM devices, so each device has only one
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+ * channel.
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+ */
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+ if (configuration->channel != 0)
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+ {
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+ return -RT_EINVAL;
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+ }
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+
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+ switch (cmd)
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+ {
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+ case PWM_CMD_ENABLE:
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+ return drv_pwm_enable(pwm_device, configuration, RT_TRUE);
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+ case PWM_CMD_DISABLE:
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+ return drv_pwm_enable(pwm_device, configuration, RT_FALSE);
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+ case PWM_CMD_GET:
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+ return drv_pwm_get(pwm_device, configuration);
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+ case PWM_CMD_SET:
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+ return drv_pwm_set(pwm_device, configuration);
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+ default:
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+ return -RT_EINVAL;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+/**
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+ * This is to register the PWM device
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+ *
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+ * Note that the PWM driver only supports one fixed pin.
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+ */
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+int rt_hw_pwm_init(void)
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+{
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+ rt_err_t ret = RT_EOK;
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+ rt_err_t rt_err = RT_EOK;
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+ fsp_err_t fsp_err = FSP_SUCCESS;
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+
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+ for (int i = 0; i < BSP_PWMS_NUM; i++)
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+ {
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+ fsp_err = R_GPT_Open(ra6m4_pwm_obj[i].g_ctrl,
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+ ra6m4_pwm_obj[i].g_cfg);
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+
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+ rt_err = rt_device_pwm_register(&ra6m4_pwm_obj[i].pwm_device,
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+ ra6m4_pwm_obj[i].name,
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+ &drv_ops,
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+ &ra6m4_pwm_obj[i]);
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+
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+ if (fsp_err != FSP_SUCCESS || rt_err != RT_EOK)
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+ {
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+ ret = -RT_ERROR;
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+ }
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+ }
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+
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+ return ret;
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+}
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+INIT_BOARD_EXPORT(rt_hw_pwm_init);
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+#endif /* RT_USING_PWM */
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Sherman
