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@@ -8,7 +8,7 @@
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* 2020-12-27 iysheng first version
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* 2020-12-27 iysheng first version
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* 2021-01-01 iysheng support exti interrupt
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* 2021-01-01 iysheng support exti interrupt
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* 2021-09-07 FuC Suit for Vango V85xx
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* 2021-09-07 FuC Suit for Vango V85xx
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- * 2021-09-09 ZhuXW Fixing GPIO interrupt ...
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+ * 2021-09-09 ZhuXW Add GPIO interrupt
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*/
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*/
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#include <board.h>
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#include <board.h>
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@@ -33,7 +33,32 @@
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#error Unsupported V85XX GPIO peripheral.
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#error Unsupported V85XX GPIO peripheral.
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#endif
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#endif
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-#define PIN_GDPORT_MAX __V85XX_PORT_MAX
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+#define PIN_V85XXPORT_MAX __V85XX_PORT_MAX
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+#define PIN_V85XXPORT_A 0u
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+
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+static const struct pin_irq_map pin_irq_map[] =
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+{
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+#if defined(SOC_SERIES_V85XX)
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+ {GPIO_Pin_0, PMU_IRQn},
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+ {GPIO_Pin_1, PMU_IRQn},
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+ {GPIO_Pin_2, PMU_IRQn},
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+ {GPIO_Pin_3, PMU_IRQn},
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+ {GPIO_Pin_4, PMU_IRQn},
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+ {GPIO_Pin_5, PMU_IRQn},
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+ {GPIO_Pin_6, PMU_IRQn},
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+ {GPIO_Pin_7, PMU_IRQn},
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+ {GPIO_Pin_8, PMU_IRQn},
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+ {GPIO_Pin_9, PMU_IRQn},
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+ {GPIO_Pin_10, PMU_IRQn},
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+ {GPIO_Pin_11, PMU_IRQn},
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+ {GPIO_Pin_12, PMU_IRQn},
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+ {GPIO_Pin_13, PMU_IRQn},
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+ {GPIO_Pin_14, PMU_IRQn},
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+ {GPIO_Pin_15, PMU_IRQn},
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+#else
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+#error "Unsupported soc series"
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+#endif
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+};
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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{
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@@ -100,12 +125,18 @@ static void v85xx_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
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GPIO_TypeDef *gpio_port;
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GPIO_TypeDef *gpio_port;
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uint16_t gpio_pin;
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uint16_t gpio_pin;
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- if (PIN_PORT(pin) < PIN_GDPORT_MAX)
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+ if (PIN_PORT(pin) == PIN_V85XXPORT_A)
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{
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{
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- gpio_port = PIN_GDPORT(pin);
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- gpio_pin = PIN_GDPIN(pin);
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+ gpio_pin = PIN_V85XXPIN(pin);
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- GPIOBToF_WriteBit(gpio_port, gpio_pin, (BitState)value);//GPIOA ignored
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+ GPIOA_WriteBit(GPIOA, gpio_pin, (BitState)value);
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+ }
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+ else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX)
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+ {
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+ gpio_port = PIN_V85XXPORT(pin);
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+ gpio_pin = PIN_V85XXPIN(pin);
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+
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+ GPIOBToF_WriteBit(gpio_port, gpio_pin, (BitState)value);
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}
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}
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}
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}
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@@ -115,11 +146,16 @@ static int v85xx_pin_read(rt_device_t dev, rt_base_t pin)
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uint16_t gpio_pin;
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uint16_t gpio_pin;
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int value = PIN_LOW;
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int value = PIN_LOW;
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- if (PIN_PORT(pin) < PIN_GDPORT_MAX)
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+ if (PIN_PORT(pin) == PIN_V85XXPORT_A)
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{
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{
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- gpio_port = PIN_GDPORT(pin);
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- gpio_pin = PIN_GDPIN(pin);
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- value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin);//GPIOA ignored
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+ gpio_pin = PIN_V85XXPIN(pin);
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+ value = GPIOA_ReadInputDataBit(GPIOA, gpio_pin);
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+ }
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+ else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX)
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+ {
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+ gpio_port = PIN_V85XXPORT(pin);
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+ gpio_pin = PIN_V85XXPIN(pin);
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+ value = GPIOBToF_ReadInputDataBit(gpio_port, gpio_pin);
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}
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}
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return value;
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return value;
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@@ -129,13 +165,13 @@ static void v85xx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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{
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{
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GPIO_InitType GPIO_InitStruct = {0};
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GPIO_InitType GPIO_InitStruct = {0};
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- if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
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+ if (PIN_PORT(pin) >= PIN_V85XXPORT_MAX)
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{
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{
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return;
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return;
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}
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}
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/* Configure GPIO_InitStructure */
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/* Configure GPIO_InitStructure */
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- GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
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+ GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin);
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
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switch (mode)
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switch (mode)
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@@ -159,7 +195,14 @@ static void v85xx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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break;
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break;
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}
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}
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- GPIOBToF_Init(PIN_GDPORT(pin), &GPIO_InitStruct);//ignore GPIOA
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+ if (PIN_PORT(pin) == PIN_V85XXPORT_A)
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+ {
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+ GPIOA_Init(GPIOA, &GPIO_InitStruct);
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+ }
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+ else if (PIN_PORT(pin) < PIN_V85XXPORT_MAX)
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+ {
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+ GPIOBToF_Init(PIN_V85XXPORT(pin), &GPIO_InitStruct);
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+ }
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}
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}
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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@@ -182,12 +225,16 @@ static rt_err_t v85xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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rt_base_t level;
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rt_base_t level;
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rt_int32_t irqindex = -1;
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rt_int32_t irqindex = -1;
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- if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
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+ if (PIN_PORT(pin) > PIN_V85XXPORT_A)
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{
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{
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return -RT_ENOSYS;
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return -RT_ENOSYS;
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}
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}
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- irqindex = bit2bitno(PIN_GDPIN(pin));
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+ irqindex = bit2bitno(PIN_V85XXPIN(pin));
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+ if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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+ {
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+ return RT_ENOSYS;
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+ }
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level = rt_hw_interrupt_disable();
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level = rt_hw_interrupt_disable();
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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if (pin_irq_hdr_tab[irqindex].pin == pin &&
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@@ -213,12 +260,112 @@ static rt_err_t v85xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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}
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}
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static rt_err_t v85xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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static rt_err_t v85xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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{
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{
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+ rt_base_t level;
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+ rt_int32_t irqindex = -1;
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+
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+ if (PIN_PORT(pin) > PIN_V85XXPORT_A)
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+ {
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+ return -RT_ENOSYS;
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+ }
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+
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+ irqindex = bit2bitno(PIN_V85XXPIN(pin));
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+ if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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+ {
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+ return RT_ENOSYS;
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+ }
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+
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+ level = rt_hw_interrupt_disable();
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+ if (pin_irq_hdr_tab[irqindex].pin == -1)
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+ {
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+ rt_hw_interrupt_enable(level);
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+ return RT_EOK;
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+ }
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+ pin_irq_hdr_tab[irqindex].pin = -1;
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+ pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
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+ pin_irq_hdr_tab[irqindex].mode = 0;
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+ pin_irq_hdr_tab[irqindex].args = RT_NULL;
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+ rt_hw_interrupt_enable(level);
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return RT_EOK;
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return RT_EOK;
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}
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}
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static rt_err_t v85xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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static rt_err_t v85xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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{
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{
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+ const struct pin_irq_map *irqmap;
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+ rt_base_t level;
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+ rt_int32_t irqindex = -1;
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+ GPIO_InitType GPIO_InitStruct = {0};
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+
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+ if (PIN_PORT(pin) > PIN_V85XXPORT_A)
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+ {
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+ return -RT_ENOSYS;
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+ }
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+
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+ GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin);
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+ if (enabled == PIN_IRQ_ENABLE)
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+ {
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+ irqindex = bit2bitno(PIN_V85XXPIN(pin));
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+ if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
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+ {
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+ return RT_ENOSYS;
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+ }
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+
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+ level = rt_hw_interrupt_disable();
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+ if (pin_irq_hdr_tab[irqindex].pin == -1)
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+ {
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+ rt_hw_interrupt_enable(level);
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+ return RT_ENOSYS;
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+ }
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+
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+ GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
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+ GPIO_InitStruct.GPIO_Pin = PIN_V85XXPIN(pin);
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+ GPIOA_Init(GPIOA, &GPIO_InitStruct);
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+
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+ irqmap = &pin_irq_map[irqindex];
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+
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+ switch (pin_irq_hdr_tab[irqindex].mode)
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+ {
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+ case PIN_IRQ_MODE_RISING:
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+ PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_RISING);
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+ break;
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+ case PIN_IRQ_MODE_FALLING:
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+ PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_FALLING);
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+ break;
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+ case PIN_IRQ_MODE_RISING_FALLING:
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+ PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_EDGEBOTH);
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+ break;
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+ case PIN_IRQ_MODE_HIGH_LEVEL:
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+ PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_HIGH);
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+ break;
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+ case PIN_IRQ_MODE_LOW_LEVEL:
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+ PMU_WakeUpPinConfig(PIN_V85XXPIN(pin), IOA_LOW);
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+ break;
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+ default:
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+ break;
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+ }
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+ PMU_INTConfig(PMU_INT_IOAEN, ENABLE);
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+
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+ NVIC_SetPriority(irqmap->irqno, 0);
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+ NVIC_EnableIRQ(irqmap->irqno);
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+ pin_irq_enable_mask |= irqmap->pinbit;
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+
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+ rt_hw_interrupt_enable(level);
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+ }
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+ else if (enabled == PIN_IRQ_DISABLE)
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+ {
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+
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+ level = rt_hw_interrupt_disable();
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+
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+ PMU_INTConfig(PMU_INT_IOAEN, DISABLE);
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+
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+ NVIC_DisableIRQ(irqmap->irqno);
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+
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+ rt_hw_interrupt_enable(level);
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+ }
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+ else
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+ {
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+ return -RT_ENOSYS;
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+ }
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return RT_EOK;
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return RT_EOK;
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}
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}
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@@ -243,6 +390,32 @@ rt_inline void pin_irq_hdr(int irqno)
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}
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}
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}
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}
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+
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+void v85xx_pin_exti_irqhandler()
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+{
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+ rt_base_t intsts=0;
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+ int i=0;
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+
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+ intsts = PMU_GetIOAAllINTStatus();
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+ for(i=0; i<16; i++)
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+ {
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+ if((1<<i) & intsts)
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+ {
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+ PMU_ClearIOAINTStatus(1<<i);
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+ pin_irq_hdr(bit2bitno(1<<i));
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+ return;
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+ }
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+ }
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+}
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+
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+void PMU_IRQHandler()
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+{
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+ rt_interrupt_enter();
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+ v85xx_pin_exti_irqhandler();
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+ rt_interrupt_leave();
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+}
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+
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+
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int rt_hw_pin_init(void)
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int rt_hw_pin_init(void)
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{
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{
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GPIO_InitType GPIO_InitStruct;
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GPIO_InitType GPIO_InitStruct;
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@@ -272,4 +445,3 @@ int rt_hw_pin_init(void)
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}
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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#endif /* RT_USING_PIN */
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#endif /* RT_USING_PIN */
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-
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