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@@ -16,10 +16,6 @@
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#include "gicv3.h"
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#include "ioremap.h"
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-
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-/* exception and interrupt handler table */
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-struct rt_irq_desc isr_table[MAX_HANDLERS];
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-
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#ifndef RT_USING_SMP
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/* Those variables will be accessed in ISR, so we need to share them. */
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rt_ubase_t rt_interrupt_from_thread = 0;
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@@ -27,6 +23,11 @@ rt_ubase_t rt_interrupt_to_thread = 0;
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rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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#endif
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+#ifndef RT_USING_PIC
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+
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+/* exception and interrupt handler table */
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+struct rt_irq_desc isr_table[MAX_HANDLERS];
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+
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#ifndef RT_CPUS_NR
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#define RT_CPUS_NR 1
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#endif
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@@ -138,17 +139,17 @@ void rt_hw_interrupt_mask(int vector)
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#ifdef SOC_BCM283x
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if (vector < 32)
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{
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- IRQ_DISABLE1 = (1 << vector);
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+ IRQ_DISABLE1 = (1UL << vector);
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}
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else if (vector < 64)
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{
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vector = vector % 32;
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- IRQ_DISABLE2 = (1 << vector);
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+ IRQ_DISABLE2 = (1UL << vector);
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}
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else
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{
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vector = vector - 64;
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- IRQ_DISABLE_BASIC = (1 << vector);
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+ IRQ_DISABLE_BASIC = (1UL << vector);
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}
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#else
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arm_gic_mask(0, vector);
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@@ -164,17 +165,17 @@ void rt_hw_interrupt_umask(int vector)
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#ifdef SOC_BCM283x
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if (vector < 32)
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{
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- IRQ_ENABLE1 = (1 << vector);
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+ IRQ_ENABLE1 = (1UL << vector);
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}
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else if (vector < 64)
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{
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vector = vector % 32;
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- IRQ_ENABLE2 = (1 << vector);
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+ IRQ_ENABLE2 = (1UL << vector);
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}
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else
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{
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vector = vector - 64;
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- IRQ_ENABLE_BASIC = (1 << vector);
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+ IRQ_ENABLE_BASIC = (1UL << vector);
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}
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#else
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arm_gic_umask(0, vector);
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@@ -416,6 +417,8 @@ void rt_hw_ipi_handler_install(int ipi_vector, rt_isr_handler_t ipi_isr_handler)
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}
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#endif
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+#endif /* RT_USING_PIC */
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+
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#if defined(FINSH_USING_MSH) && defined(RT_USING_INTERRUPT_INFO)
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int list_isr()
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{
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