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@@ -8,6 +8,7 @@
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* 2018/10/28 Bernard The unify RISC-V porting implementation
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* 2018/12/27 Jesven Add SMP support
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* 2020/11/20 BalanceTWK Add FPU support
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+ * 2022/12/28 WangShun Add macro to distinguish whether FPU is supported
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*/
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#define __ASSEMBLY__
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@@ -212,8 +213,11 @@ rt_hw_context_switch_exit:
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csrw mepc, a0
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LOAD x1, 1 * REGBYTES(sp)
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-
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+ #ifdef ARCH_RISCV_FPU
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li t0, 0x00007800
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+ #else
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+ li t0, 0x00001800
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+ #endif
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csrw mstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
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csrs mstatus, a0
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