修改汇编rt_hw_context_switch_to处关于时间槽的使用；修改格式

libcpu/ti-dsp/c6x/context.asm

@@ -136,15 +136,14 @@ rt_hw_context_switch_to:
 ;
 ; this maybe do better
 ;
-	MVC	.S2	B11,RILC					; Restore RILC
-	MVC	.S2	B10,ILC						; Restore ILC
-	MV	B13,B3							; Restore PC
-	MVC	.S2	B12,CSR						; Restore CSR
-
 	LDDW	.D2T2	*++SP[1],B11:B10
+ || MVC	.S2	B11,RILC					; Restore RILC
   	LDDW	.D2T2	*++SP[1],B13:B12
+ ||	MVC	.S2	B10,ILC						; Restore ILC
 	LDDW	.D2T1	*++SP[1],A11:A10
+ ||	MV	B13,B3							; Restore PC
 	LDDW	.D2T1	*++SP[1],A13:A12
+ ||	MVC	.S2	B12,CSR						; Restore CSR
 	LDDW	.D2T1	*++SP[1],A15:A14
 	B	B3                              ; Return to caller
 	ADDAW	.D2	SP,2,SP
@@ -236,7 +235,6 @@ _reswitch:
 	.global	rt_interrupt_context_restore
 rt_interrupt_context_restore:
 ;{
-; if rt_switch_interrupt_flag set, jump to rt_hw_context_switch_interrupt and don't return
 	MVKL	rt_thread_switch_interrupt_flag,A3
 	MVKH	rt_thread_switch_interrupt_flag,A3
 	LDW		*A3,A1

libcpu/ti-dsp/c6x/contextinc.asm

@@ -19,7 +19,7 @@ SAVE_ALL	.macro  __rp, __tsr
 
 	NOP	3
 	STW	.D2T2	B1,*+SP[1]				; save original B1
-	XOR	.D2	SP,B1,B0					; (SP ^ KSP, check current stack types)
+	XOR	.D2	SP,B1,B0					; check current stack types
 	LDW	.D2T2	*+SP[1],B1				; restore B0/B1
 	LDW	.D2T2	*++SP[2],B0
 	SHR	.S2	B0,12,B0					; 0 if already using system stack
@@ -75,7 +75,7 @@ SAVE_ALL	.macro  __rp, __tsr
 
 	STDW	.D2T2	B13:B12,*SP--[1]	; save PC and CSR
 	STDW	.D2T2	B11:B10,*SP--[1]	; save RILC and ILC
-	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and orig A4
+	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and  orig A4(stack type)
 			.endm
 
 RESTORE_ALL	.macro  __rp, __tsr
@@ -183,5 +183,5 @@ THREAD_SAVE_ALL	.macro  __rp, __tsr
 
 	STDW	.D2T2	B13:B12,*SP--[1]	; save PC and CSR
 	STDW	.D2T2	B11:B10,*SP--[1]	; save RILC and ILC
-	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and orig A4
+	STDW	.D2T1	A5:A4,*SP--[1]		; save TSR and orig A4(stack type)
 				.endm

libcpu/ti-dsp/c6x/intexc.asm

@@ -9,7 +9,7 @@
 ;
 
 ;-----------------------------------------------------------
-; 		interrupt and execption handler for C000 DSP
+; 		interrupt and execption handler for C6000 DSP
 ;-----------------------------------------------------------
 
 ;-----------------------------------------------------------
@@ -94,7 +94,7 @@ RT_EXECPTION_ENTRY	.macro
 
 RT_EXECPTION_EXIT	.macro
 	RESTORE_ALL NRP,NTSR
-	B	.S2	NRP				; return from interruption
+	B	.S2	NRP				; return from execption
 	NOP	5
 					.endm
 
@@ -137,7 +137,7 @@ ret_from_trap:
  [!B0]	MVKH	.S2	ret_from_exception,B3
  [!B0]	BNOP	.S2	B3,5
 ;
-; return from trap£¬restore exception context
+; return from trap restore exception context
 ;
 ret_from_exception:
 	RT_EXECPTION_EXIT

libcpu/ti-dsp/c6x/stack.asm

@@ -35,73 +35,73 @@ ADDRESS_MSK .set    0xFFFFFFF0
 ;{
     .global rt_hw_stack_init
 rt_hw_stack_init:
-	SUB		A6,1,B1			;
-	MVKL	ADDRESS_MSK,A1	;
-	MVKH	ADDRESS_MSK,A1	; Build address mask
-	MVC		CSR,B0			;
-	AND		-2,B0,B0		; Clear GIE bit
-	OR		2,B0,B0			; Set PGIE bit for interrupt return
-	AND		A1,B1,B1		; Ensure alignment
+	SUB		A6,1,B1					;
+    MVKL	.S1	ADDRESS_MSK,A1		;
+    MVKH	.S1	ADDRESS_MSK,A1		; Build address mask
+	MVC	.S2	CSR,B0					;
+	AND		-2,B0,B0				; Clear GIE bit
+	OR		2,B0,B0					; Set PGIE bit for interrupt return
+	AND		A1,B1,B1				; Ensure alignment
 ;
 ; Actually build the stack frame.
 ;
-	MV	B1,A3
-	MV	B14,A2
-	STDW	A3:A2,*--B1[1]	; Initial B15:B14
+	MV	.S1	B1,A3
+	MV	.S1	B14,A2
+	STDW	.D2T1	A3:A2,*--B1[1]	; Initial B15:B14
 	SUBAW	.D2	B1,2,B1
 	ZERO	A2
-	ZERO	A3              ; Clear value
-	STDW	A3:A2,*B1--[1]	; Initial A15:A14
-	STDW	A3:A2,*B1--[1]	; Initial A13:A12
-	STDW	A3:A2,*B1--[1]	; Initial A11:A10
-	STDW	A3:A2,*B1--[1]	; Initial A9:A8
-	STDW	A3:A2,*B1--[1]	; Initial A7:A6
-	MV	B4,A2
-	STDW	A3:A2,*B1--[1]	; Initial A5:A4
+	ZERO	A3              		; Clear value
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A15:A14
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A13:A12
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A11:A10
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A9:A8
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A7:A6
+	MV	.S1	B4,A2
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A5:A4
 	ZERO	A2
-	STDW	A3:A2,*B1--[1]	; Initial A3:A2
-	STDW	A3:A2,*B1--[1]	; Initial A1:A0
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A3:A2
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A1:A0
 
-	STDW	A3:A2,*B1--[1]	; Initial A31:A30
-	STDW	A3:A2,*B1--[1]	; Initial A29:A28
-	STDW	A3:A2,*B1--[1]	; Initial A27:A26
-	STDW	A3:A2,*B1--[1]	; Initial A25:A24
-	STDW	A3:A2,*B1--[1]	; Initial A23:A22
-	STDW	A3:A2,*B1--[1]	; Initial A21:A20
-	STDW	A3:A2,*B1--[1]	; Initial A19:A18
-	STDW	A3:A2,*B1--[1]	; Initial A17:A16
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A31:A30
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A29:A28
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A27:A26
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A25:A24
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A23:A22
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A21:A20
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A19:A18
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial A17:A16
 
-	STDW	A3:A2,*B1--[1]	; Initial B13:B12
-	STDW	A3:A2,*B1--[1]	; Initial B11:B10
-	STDW	A3:A2,*B1--[1]	; Initial B9:B8
-	STDW	A3:A2,*B1--[1]	; Initial B7:B6
-	STDW	A3:A2,*B1--[1]	; Initial B5:B4
-	MV	B6,A3
-	STDW	A3:A2,*B1--[1]	; Initial B3:B2
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B13:B12
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B11:B10
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B9:B8
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B7:B6
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B5:B4
+	MV	.S1	B6,A3
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B3:B2
 	ZERO	A3
-	STDW	A3:A2,*B1--[1]	; Initial B1:B0
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B1:B0
 
-	STDW	A3:A2,*B1--[1]	; Initial B31:B30
-	STDW	A3:A2,*B1--[1]	; Initial B29:B28
-	STDW	A3:A2,*B1--[1]	; Initial B27:B26
-	STDW	A3:A2,*B1--[1]	; Initial B25:B24
-	STDW	A3:A2,*B1--[1]	; Initial B23:B22
-	STDW	A3:A2,*B1--[1]	; Initial B21:B20
-	STDW	A3:A2,*B1--[1]	; Initial B19:B18
-	STDW	A3:A2,*B1--[1]	; Initial B17:B16
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B31:B30
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B29:B28
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B27:B26
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B25:B24
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B23:B22
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B21:B20
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B19:B18
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial B17:B16
 
-	MV	A4,A3
-	MV	B0,A2
-	STDW	A3:A2,*B1--[1]	; Initial PC:CSR
+	MV	.S1	A4,A3
+	MV	.S1	B0,A2
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial PC:CSR
 
 	ZERO	A2
 	ZERO	A3
-	STDW	A3:A2,*B1--[1]	; Initial ILC:RILC
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial ILC:RILC
 	B	B3
-	MVKL	0x3,B0
-	MV	B0,A3
-	MVKL	1,A2
-	STDW	A3:A2,*B1--[1]	; Initial TSR:stack type
-	MV	B1,A4				; Save to TCB
+	MVKL	.S2	0x3,B0
+	MV	.S1	B0,A3
+	MVKL	.S1	1,A2
+	STDW	.D2T1	A3:A2,*B1--[1]	; Initial TSR:stack type
+	MV	.S1	B1,A4					; Save to TCB
 ;}
 	.end