Merge pull request #4737 from mysterywolf/3,1,xformat

[lts 3.1.x] format codes

bsp/CME_M7/applications/application.c

@@ -28,10 +28,10 @@ int rt_application_init()
 
     tid = rt_thread_create("init",
         rt_init_thread_entry,
-		RT_NULL,
+        RT_NULL,
         2048,
-		RT_THREAD_PRIORITY_MAX/3,
-		20);
+        RT_THREAD_PRIORITY_MAX/3,
+        20);
 
     if (tid != RT_NULL)
         rt_thread_startup(tid);

bsp/CME_M7/applications/startup.c

@@ -1,7 +1,7 @@
 /*
  * File      : startup.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at

bsp/CME_M7/drivers/board.h

@@ -14,7 +14,7 @@
 #include "cmem7_includes.h"
 //#include "cmem7_retarget.h"
 
-#define SRAM_SIZE         64	// KB
+#define SRAM_SIZE         64    // KB
 #define SRAM_END          (0x20000000 + SRAM_SIZE * 1024)
 
 //#define RT_USING_UART0

bsp/CME_M7/drivers/emac.c

@@ -1,7 +1,7 @@
 /*
  * File      : emac.c
  * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006-2014, RT-Thread Develop Team
+ * COPYRIGHT (C) 2006-2021, RT-Thread Develop Team
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -38,7 +38,7 @@ struct rt_cme_eth
     struct eth_device parent;
 
     /* interface address info. */
-    rt_uint8_t  dev_addr[MAX_ADDR_LEN];			/* hw address	*/
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];         /* hw address   */
 
     uint32_t    ETH_Speed;
     uint32_t    ETH_Mode;
@@ -95,8 +95,8 @@ uint32_t txTotalMemory = 0x2000;
 BOOL isRxNoBuf = FALSE;
 
 #define ETH_MAX_PACKET_SIZE    1520    /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */
-#define ETH_RXBUFNB        	4
-#define ETH_TXBUFNB        	2
+#define ETH_RXBUFNB         4
+#define ETH_TXBUFNB         2
 
 struct eth_rx_buffer
 {

bsp/CME_M7/rtconfig.h

@@ -3,16 +3,16 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX		8
+#define RT_NAME_MAX     8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -61,8 +61,8 @@
 /* SECTION: Console options */
 #define RT_USING_CONSOLE
 /* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE	128
-#define RT_CONSOLE_DEVICE_NAME	        "uart2"
+#define RT_CONSOLEBUF_SIZE  128
+#define RT_CONSOLE_DEVICE_NAME          "uart2"
 
 /* SECTION: finsh, a C-Express shell */
 #define RT_USING_FINSH
@@ -79,15 +79,15 @@
 #define RT_USING_DFS_ELMFAT
 #define RT_DFS_ELM_REENTRANT
 #define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_DRIVES			1
-#define RT_DFS_ELM_USE_LFN			2
-#define RT_DFS_ELM_MAX_LFN			255
+#define RT_DFS_ELM_DRIVES           1
+#define RT_DFS_ELM_USE_LFN          2
+#define RT_DFS_ELM_MAX_LFN          255
 #define RT_DFS_ELM_MAX_SECTOR_SIZE  512
 
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					4
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  4
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 #define RT_USING_LWIP
@@ -121,13 +121,13 @@
 #define RT_LWIP_MSKADDR  "255.255.255.0"
 
 /* tcp thread options */
-#define RT_LWIP_TCPTHREAD_PRIORITY		12
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
-#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+#define RT_LWIP_TCPTHREAD_PRIORITY      12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE     4
+#define RT_LWIP_TCPTHREAD_STACKSIZE     1024
 
-#define RT_LWIP_ETHTHREAD_PRIORITY		15
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
-#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+#define RT_LWIP_ETHTHREAD_PRIORITY      15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE     4
+#define RT_LWIP_ETHTHREAD_STACKSIZE     512
 
 // <bool name="RT_USING_CMSIS_OS" description="Using CMSIS OS API" default="true" />
 // #define RT_USING_CMSIS_OS

bsp/allwinner_tina/drivers/drv_clock.c

@@ -527,7 +527,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
         *mmc_clk &= ~(0x1 << 31);
         return RT_EOK;
     }
-    
+
     if (hz <= 24000000)
     {
         pll = (0x0 << 24);
@@ -579,7 +579,7 @@ rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz)
         oclk_dly = 1;
         sclk_dly = 4;
     }
-    
+
     *mmc_clk = (0x1 << 31) | pll | (sclk_dly << 20) | \
            (n << 16) | (oclk_dly << 8) | (div - 1);
 

bsp/allwinner_tina/drivers/drv_clock.h

@@ -238,4 +238,4 @@ rt_err_t dram_gate_clk_enable(enum dram_gate dram_gate);
 rt_err_t dram_gate_clk_disable(enum dram_gate dram_gate);
 
 rt_err_t mmc_set_clk(enum mmc_clk_id clk_id, int hz);
-#endif
+#endif

bsp/allwinner_tina/drivers/drv_gpio.h

@@ -227,4 +227,4 @@ void gpio_set_debounce(enum gpio_port port, rt_uint8_t prescaler);
 void gpio_set_irq_callback(enum gpio_port port, enum gpio_pin pin, void (*irq_cb)(void *), void *irq_arg);
 int rt_hw_gpio_init(void);
 
-#endif /* __DRV_GPIO_H__ */
+#endif /* __DRV_GPIO_H__ */

bsp/allwinner_tina/drivers/drv_sdio.c

@@ -20,10 +20,10 @@
 
 
 #define DBG_TAG  "MMC"
-// #define DBG_LVL DBG_LOG    
-// #define DBG_LVL DBG_INFO   
+// #define DBG_LVL DBG_LOG
+// #define DBG_LVL DBG_INFO
 #define DBG_LVL DBG_WARNING
-// #define DBG_LVL DBG_ERROR  
+// #define DBG_LVL DBG_ERROR
 #include <rtdbg.h>
 
 #ifdef RT_USING_SDIO
@@ -33,12 +33,12 @@
 struct mmc_xfe_des
 {
     rt_uint32_t size;    /* block size  */
-	rt_uint32_t num;     /* block num   */
-	rt_uint8_t *buff;    /* buff addr   */
-	rt_uint32_t flag;    /* write or read or stream */
-#define MMC_DATA_WRITE	(1 << 0)
-#define MMC_DATA_READ	(1 << 1)
-#define MMC_DATA_STREAM	(1 << 2)
+    rt_uint32_t num;     /* block num   */
+    rt_uint8_t *buff;    /* buff addr   */
+    rt_uint32_t flag;    /* write or read or stream */
+#define MMC_DATA_WRITE  (1 << 0)
+#define MMC_DATA_READ   (1 << 1)
+#define MMC_DATA_STREAM (1 << 2)
 };
 
 struct mmc_flag
@@ -57,7 +57,7 @@ struct sdio_drv
     tina_mmc_t mmc_des;
     rt_uint8_t *mmc_buf;
     rt_uint8_t usedma;
-    
+
 };
 
 #ifdef CONFIG_MMC_USE_DMA
@@ -122,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc)
     mmc->risr_reg = mmc->risr_reg;
     return RT_EOK;
 }
-    
+
 static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
 {
     ALIGN(32) static struct mmc_des_v4p1 pdes[128];  // mast ALIGN(32)
@@ -131,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     unsigned length = xfe->size * xfe->num;
     unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT;
     unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1);
-    
+
     if (remain)
     {
         buff_frag_num ++;
@@ -142,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     }
     memset(pdes, 0, sizeof(pdes));
     mmu_clean_dcache((rt_uint32_t)(xfe->buff), length);
-    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++) 
+    for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++)
     {
         // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
         pdes[des_idx].des_chain = 1;
@@ -168,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
             pdes[des_idx].last_des = 1;
             pdes[des_idx].end_of_ring = 1;
             pdes[des_idx].buf_addr_ptr2 = 0;
-        } 
-        else 
+        }
+        else
         {
             pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1];
         }
@@ -203,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     mmc->dmac_reg = (1 << 1) | (1 << 7);        /* idma on              */
     rval = mmc->idie_reg & (~3);
     if (xfe->flag == MMC_DATA_WRITE)
-        rval |= (1 << 0);        
+        rval |= (1 << 0);
     else
         rval |= (1 << 1);
     mmc->idie_reg = rval;
@@ -222,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
 
     if (xfe->flag == MMC_DATA_WRITE)
     {
-        for (i = 0; i < (byte_cnt >> 2); i++) 
+        for (i = 0; i < (byte_cnt >> 2); i++)
         {
             while(--timeout && (mmc->star_reg & (1 << 3)));
 
@@ -237,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
     }
     else
     {
-        for (i = 0; i < (byte_cnt >> 2); i++) 
+        for (i = 0; i < (byte_cnt >> 2); i++)
         {
             while(--timeout && (mmc->star_reg & (1 << 2)));
 
@@ -276,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
     {
         mmc_set_clk(SDMMC1, clk);
     }
-    
+
     /* Re-enable card clock */
     rval = mmc->ckcr_reg;
     rval |=  (0x1 << 16); //(3 << 16);
@@ -369,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
         cmdval |= (1 << 7);
     if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4))
         cmdval |= (1 << 8);
-    
+
     if (data)
     {
         cmdval |= (1 << 9) | (1 << 13);
@@ -592,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
 
     memset(&sdio->flag, 0, sizeof(struct mmc_flag));
     mmc_send_cmd(host, req->cmd);
-    
+
     return;
 }
 

bsp/allwinner_tina/drivers/drv_sdio.h

@@ -119,8 +119,8 @@ REG[31]  : Load cmd
 #define SDXC_UPDATE_CLOCK_CMD    BIT(21)
 #define SDXC_LOAD_CMD            BIT(31)
 
-/* 
-    SD status reg 
+/*
+    SD status reg
 REG[0]   : FIFO_RX_LEVEL
 REG[1]   : FIFO_TX_LEVEL
 REG[2]   : FIFO_EMPTY
@@ -129,7 +129,7 @@ REG[4-7] : FSM_STA
 REG[8]   : CARD_PRESENT
 REG[9]   : CARD_BUSY
 REG[10]  : FSM_BUSY
-REG[11-16]: RESP_IDX 
+REG[11-16]: RESP_IDX
 REG[17-21]: FIFO_LEVEL
 REG[31]   : DMA_REQ
 */

bsp/allwinner_tina/drivers/drv_uart.c

@@ -310,4 +310,4 @@ void uart_irq_handler(int irqno, void *param)
 
 }
 
-#endif
+#endif

bsp/allwinner_tina/drivers/spi/drv_spi_flash.c

@@ -51,4 +51,4 @@ INIT_PREV_EXPORT(rt_hw_spi_flash_with_sfud_init);
 
 #endif
 
-#endif
+#endif

bsp/amebaz/drivers/board.c

@@ -40,7 +40,7 @@ void __wrap_rtl_printf(const char *fmt, ...)
      * length. */
     length = rt_vsnprintf(rt_log_buf, sizeof(rt_log_buf) - 1, fmt, args);
     if (length > RT_CONSOLEBUF_SIZE - 1)
-        length = RT_CONSOLEBUF_SIZE - 1;    
+        length = RT_CONSOLEBUF_SIZE - 1;
     rt_kprintf("%s", rt_log_buf);
     va_end(args);
 }
@@ -85,11 +85,11 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_HEAP
         rt_system_heap_init((void*)HEAP_BEGIN, (void*)HEAP_END);
 #endif
-    
+
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-    
+
 #ifdef RT_USING_CONSOLE
     rt_hw_uart_init();
     rt_console_set_device(RT_CONSOLE_DEVICE_NAME);

bsp/amebaz/drivers/drv_uart.c

@@ -111,7 +111,7 @@ static int ameba_uart_getc (struct rt_serial_device *serial)
 {
     struct device_uart* uart = serial->parent.user_data;
 
-	if(!serial_readable(&uart->serial))
+    if(!serial_readable(&uart->serial))
         return -1;
 
     /* Receive Data Available */
@@ -126,13 +126,13 @@ static rt_size_t ameba_uart_dma_transmit (struct rt_serial_device *serial, rt_ui
 static void ameba_uart_irq(uint32_t id, SerialIrq event)
 {
     struct rt_serial_device *serial = (struct rt_serial_device *)id;
-	if(event == RxIrq)
+    if(event == RxIrq)
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
-	}
-	else if(event == TxIrq)
+    }
+    else if(event == TxIrq)
     {
-	}
+    }
 }
 
 static rt_err_t dbg_configure(struct rt_serial_device *serial, struct serial_configure *cfg);
@@ -141,7 +141,7 @@ static int dbg_putc(struct rt_serial_device *serial, char c);
 static int dbg_getc(struct rt_serial_device *serial);
 
 static struct rt_serial_device ameba_dbg_serial;
-const struct rt_uart_ops _ambed_dbg_ops = 
+const struct rt_uart_ops _ambed_dbg_ops =
 {
     dbg_configure,
     dbg_control,
@@ -163,7 +163,7 @@ void dbg_uart_irq_handler(void * data)
     DiagSetIsrEnReg(0);
 
     rt_hw_serial_isr(&ameba_dbg_serial, RT_SERIAL_EVENT_RX_IND);
-    
+
     DiagSetIsrEnReg(IrqEn);
 }
 
@@ -178,9 +178,9 @@ static rt_err_t dbg_control(struct rt_serial_device *serial, int cmd, void *arg)
 
     case RT_DEVICE_CTRL_SET_INT:
         /* install interrupt */
-    	DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
+        DIAG_UartReInit((IRQ_FUN) dbg_uart_irq_handler);
         /* Enable the UART Interrupt */
-    	NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
+        NVIC_SetPriority(UART_LOG_IRQ, 10); /* this is rom_code_patch */
         break;
     }
 
@@ -200,12 +200,12 @@ static int dbg_getc(struct rt_serial_device *serial)
 
     if(!UART_Readable(UART2_DEV))
         return -1;
-    
+
     c = DiagGetChar(_FALSE);
 
     return c;
 }
- 
+
 /*
  * UART Initiation
  */
@@ -217,7 +217,7 @@ int rt_hw_uart_init(void)
 #ifdef BSP_USING_UART0
     {
         struct device_uart      *uart;
-        
+
         serial  = &serial0;
         uart    = &uart0;
 
@@ -242,7 +242,7 @@ int rt_hw_uart_init(void)
 
         serial->ops = &_ambed_dbg_ops;
         serial->config = config;
-        
+
         rt_hw_serial_register(serial,
                               RT_CONSOLE_DEVICE_NAME,
                               RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,

bsp/amebaz/drivers/wlan/drv_wifi.c

@@ -101,7 +101,7 @@ void netif_pre_sleep_processing(void)
 }
 
 unsigned char *rltk_wlan_get_ip(int idx)
-{   
+{
     struct ameba_wifi *wifi;
 
     wifi = rthw_wifi_get_dev(idx);
@@ -116,7 +116,7 @@ unsigned char *rltk_wlan_get_ip(int idx)
 
 int netif_is_valid_IP(int idx, unsigned char *ip_dest)
 {
-    LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__, 
+    LOG_D("F:%s L:%d is run ip: %d:%d:%d:%d", __FUNCTION__, __LINE__,
         ip_dest[0], ip_dest[1], ip_dest[2], ip_dest[3]);
     return 1;
 }
@@ -362,9 +362,9 @@ static rt_err_t rthw_wlan_join                 (struct rt_wlan_device *wlan, str
             ssid = &sta_info->ssid.val[0];
         if (sta_info->key.len > 0)
             key = &sta_info->key.val[0];
-            LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d", 
+            LOG_D("bssid connect bssid: %02x:%02x:%02x:%02x:%02x:%02x ssid:%s ssid_len:%d key:%s key_len%d",
             sta_info->bssid[0],sta_info->bssid[1],sta_info->bssid[2],sta_info->bssid[3],sta_info->bssid[4],sta_info->bssid[5],
-            ssid, 
+            ssid,
             sta_info->ssid.len,
             key,
             sta_info->key.len
@@ -594,7 +594,7 @@ exit:
     return RT_EOK;
 }
 
-static const struct rt_wlan_dev_ops ops = 
+static const struct rt_wlan_dev_ops ops =
 {
     .wlan_init             =     rthw_wlan_init           ,
     .wlan_mode             =     rthw_wlan_mode           ,

bsp/amebaz/drivers/wlan/drv_wifi.h

@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-5-30      Bernard      the first version
  */
- 
+
 #ifndef __DRV_WIFI_H__
 #define __DRV_WIFI_H__
 

bsp/amebaz/drivers/wlan/drv_wlan.c

@@ -137,20 +137,20 @@ int rthw_wifi_ap_start(char *ssid, char *password, int channel)
         return -1;
     }
 
-    while(1) 
+    while(1)
     {
         char essid[33];
         if(wext_get_ssid(name, (unsigned char *) essid) > 0)
         {
-            if(strcmp((const char *) essid, (const char *)ssid) == 0) 
+            if(strcmp((const char *) essid, (const char *)ssid) == 0)
             {
                 rt_kprintf("%s started\n", ssid);
                 break;
             }
         }
-        if(timeout == 0) 
+        if(timeout == 0)
         {
-            rt_kprintf("Start AP timeout\n");   
+            rt_kprintf("Start AP timeout\n");
             return -1;
         }
         rt_thread_delay(1 * RT_TICK_PER_SECOND);
@@ -169,7 +169,7 @@ static int rthw_wifi_disconnect(char *name)
     if (name == RT_NULL)
         return -1;
 
-    if (wext_get_ssid(name, (unsigned char *) essid) < 0) 
+    if (wext_get_ssid(name, (unsigned char *) essid) < 0)
     {
         rt_kprintf("\nWIFI disconnected!\n");
         return -1;
@@ -189,7 +189,7 @@ static int rthw_wifi_disconnect(char *name)
             break;
         }
 
-        if(timeout == 0) 
+        if(timeout == 0)
         {
             rt_kprintf("ERROR: Deassoc timeout!\n");
             return -1;
@@ -245,7 +245,7 @@ int rthw_wifi_ap_disconnect(void)
 
 int rthw_wifi_rssi_get(void)
 {
-    int rssi = 0;   
+    int rssi = 0;
     wifi_get_rssi(&rssi);
     return rssi;
 }

bsp/amebaz/drivers/wlan/drv_wlan.h

@@ -11,14 +11,14 @@
 #ifndef __DRV_WLAN_H__
 #define __DRV_WLAN_H__
 
-typedef enum 
+typedef enum
 {
-	RTHW_MODE_NONE = 0,
-	RTHW_MODE_STA,
-	RTHW_MODE_AP,
-	RTHW_MODE_STA_AP,
-	RTHW_MODE_PROMISC,
-	RTHW_MODE_P2P
+    RTHW_MODE_NONE = 0,
+    RTHW_MODE_STA,
+    RTHW_MODE_AP,
+    RTHW_MODE_STA_AP,
+    RTHW_MODE_PROMISC,
+    RTHW_MODE_P2P
 }rthw_mode_t;
 
 #define SHARED_ENABLED  0x00008000
@@ -52,7 +52,7 @@ typedef enum {
 typedef enum {
     RTHW_WIFI_EVENT_CONNECT = 0,
     RTHW_WIFI_EVENT_DISCONNECT = 1,
-    RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,	
+    RTHW_WIFI_EVENT_FOURWAY_HANDSHAKE_DONE = 2,
     RTHW_WIFI_EVENT_SCAN_RESULT_REPORT = 3,
     RTHW_WIFI_EVENT_SCAN_DONE = 4,
     RTHW_WIFI_EVENT_RECONNECTION_FAIL = 5,

bsp/apollo2/board/adc.c

@@ -18,7 +18,7 @@
 struct rt_messagequeue adcbat_mq;
 
 #define BATTERY_GPIO            35                        /* Battery */
-#define BATTERY_ADC_PIN         AM_HAL_PIN_35_ADCSE7 
+#define BATTERY_ADC_PIN         AM_HAL_PIN_35_ADCSE7
 #define BATTERY_ADC_CHANNEL     AM_HAL_ADC_SLOT_CHSEL_SE7 /* BATTERY ADC采集通道 */
 #define BATTERY_ADC_CHANNELNUM  7                         /* BATTERY ADC采集通道号 */
 
@@ -38,7 +38,7 @@ rt_uint8_t am_adc_data_get(rt_uint8_t channel, rt_int16_t *buff, rt_uint16_t siz
 
     if (channel == BATTERY_ADC_CHANNELNUM)
     {
-        /* wait adc message forever */	
+        /* wait adc message forever */
         rt_mq_recv(&adcbat_mq, adc_bufftemp, 32, RT_WAITING_FOREVER);
     }
 

bsp/apollo2/board/gpio.c

@@ -56,7 +56,7 @@ void am_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     else if (value == PIN_HIGH)
     {
         am_hal_gpio_out_bit_set(pin);
-    }    
+    }
 }
 
 int am_pin_read(rt_device_t dev, rt_base_t pin)

bsp/apollo2/board/gpio.h

@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-09-16     Haley        the first version
  */
- 
+
 #ifndef __GPIO_H
 #define __GPIO_H
 

bsp/apollo2/board/i2c.c

@@ -119,7 +119,7 @@ static const struct rt_i2c_bus_device_ops am_i2c_ops =
 };
 
 #ifdef RT_USING_I2C0
-static struct am_i2c_bus am_i2c_bus_0 = 
+static struct am_i2c_bus am_i2c_bus_0 =
 {
     {0},
     AM_I2C0_IOM_INST
@@ -127,7 +127,7 @@ static struct am_i2c_bus am_i2c_bus_0 =
 #endif
 
 #ifdef RT_USING_I2C1
-static struct am_i2c_bus am_i2c_bus_1 = 
+static struct am_i2c_bus am_i2c_bus_1 =
 {
     {1},
     AM_I2C1_IOM_INST
@@ -135,7 +135,7 @@ static struct am_i2c_bus am_i2c_bus_1 =
 #endif
 
 #ifdef RT_USING_I2C2
-static struct am_i2c_bus am_i2c_bus_2 = 
+static struct am_i2c_bus am_i2c_bus_2 =
 {
     {2},
     AM_I2C2_IOM_INST
@@ -143,7 +143,7 @@ static struct am_i2c_bus am_i2c_bus_2 =
 #endif
 
 #ifdef RT_USING_I2C3
-static struct am_i2c_bus am_i2c_bus_3 = 
+static struct am_i2c_bus am_i2c_bus_3 =
 {
     {3},
     AM_I2C3_IOM_INST
@@ -151,7 +151,7 @@ static struct am_i2c_bus am_i2c_bus_3 =
 #endif
 
 #ifdef RT_USING_I2C4
-static struct am_i2c_bus am_i2c_bus_4 = 
+static struct am_i2c_bus am_i2c_bus_4 =
 {
     {4},
     AM_I2C4_IOM_INST

bsp/apollo2/board/pdm.c

@@ -52,7 +52,7 @@ rt_uint8_t am_pdm_data_get(rt_uint8_t *buff, rt_uint16_t size)
 {
     rt_uint8_t pdm_rbufftemp[340];
 
-    /* wait pdm message forever */	
+    /* wait pdm message forever */
     rt_mq_recv(&pdm_mq, pdm_rbufftemp, 340, RT_WAITING_FOREVER);
 
     /* copy the data */

bsp/apollo2/board/rtc.c

@@ -101,7 +101,7 @@ int rt_hw_rtc_init(void)
     /* Select LFRC for RTC clock source */
     am_hal_rtc_osc_select(AM_HAL_RTC_OSC_LFRC);
 #endif
-  
+
 #if RTC_CLK_SRC == XT
     /* Enable the XT for the RTC */
     am_hal_clkgen_osc_start(AM_HAL_CLKGEN_OSC_XT);
@@ -114,12 +114,12 @@ int rt_hw_rtc_init(void)
     am_hal_rtc_osc_enable();
 
     /* register rtc device */
-    rtc.type	= RT_Device_Class_RTC;
-    rtc.init 	= RT_NULL;
-    rtc.open 	= rt_rtc_open;
-    rtc.close	= RT_NULL;
-    rtc.read 	= rt_rtc_read;
-    rtc.write	= RT_NULL;
+    rtc.type    = RT_Device_Class_RTC;
+    rtc.init    = RT_NULL;
+    rtc.open    = rt_rtc_open;
+    rtc.close   = RT_NULL;
+    rtc.read    = rt_rtc_read;
+    rtc.write   = RT_NULL;
     rtc.control = rt_rtc_control;
 
     /* no private */

bsp/apollo2/board/rtc.h

@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2017-09-14     Haley        the first version
  */
- 
+
 #ifndef __RTC_H
 #define __RTC_H
 

bsp/apollo2/board/smbus.c

@@ -28,8 +28,8 @@
 #define mSDA_OUT()        am_hal_gpio_pin_config(SMBUS_GPIO_SDA, AM_HAL_GPIO_OUTPUT)                      /* Set SDA as Output */
 #define mSCL_OUT()        am_hal_gpio_pin_config(SMBUS_GPIO_SCL, AM_HAL_GPIO_OUTPUT)                      /* Set SCL as Output */
 
-#define ACK	      0
-#define	NACK      1
+#define ACK       0
+#define NACK      1
 
 /* SCL keep time */
 static void keep_delay(void)
@@ -46,7 +46,7 @@ static void few_delay(void)
 }
 
 static rt_uint8_t am_smbus_send_bit(rt_uint8_t send_bit)
-{       
+{
     mSDA_OUT();
     few_delay();
 
@@ -114,7 +114,7 @@ static void am_smbus_stop_bit(void)
 
 static rt_uint8_t am_smbus_tx_byte(rt_uint8_t tx_byte)
 {
-    int	i;
+    int i;
     rt_uint8_t ack_bit;
     rt_uint8_t bit_out;
 
@@ -162,7 +162,7 @@ rt_uint8_t am_smbus_tx_then_tx(rt_uint8_t SlaveAddress, rt_uint8_t command, rt_u
     int i;
 
     am_smbus_start_bit();                      /* Start condition */
-		
+
     if(am_smbus_tx_byte(SlaveAddress))         /* Send SlaveAddress and write */
         return 1;
 

bsp/apollo2/board/spi.c

@@ -211,7 +211,7 @@ static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message* mes
                 u32TransferSize = 64;
                 am_hal_iom_spi_write(am_spi_bus->u32Module, am_spi_cs->chip_select,
                                     (uint32_t *)send_ptr, u32TransferSize, AM_HAL_IOM_RAW);
-        
+
             }
             else
             {
@@ -243,7 +243,7 @@ static const struct rt_spi_ops am_spi_ops =
 };
 
 #ifdef RT_USING_SPI0
-static struct am_spi_bus am_spi_bus_0 = 
+static struct am_spi_bus am_spi_bus_0 =
 {
     {0},
     AM_SPI0_IOM_INST

bsp/apollo2/board/uart.c

@@ -150,11 +150,11 @@ static rt_err_t am_configure(struct rt_serial_device *serial, struct serial_conf
     else if (cfg->stop_bits == STOP_BITS_2)
         uart_cfg.bTwoStopBits = true;
 
-    if (cfg->parity == PARITY_NONE)    
+    if (cfg->parity == PARITY_NONE)
         uart_cfg.ui32Parity = AM_HAL_UART_PARITY_NONE;
-    else if (cfg->parity == PARITY_ODD)    
+    else if (cfg->parity == PARITY_ODD)
         uart_cfg.ui32Parity = AM_HAL_UART_PARITY_ODD;
-    else if (cfg->parity == PARITY_EVEN)    
+    else if (cfg->parity == PARITY_EVEN)
         uart_cfg.ui32Parity = AM_HAL_UART_PARITY_EVEN;
 
     uart_cfg.ui32FlowCtrl = AM_HAL_UART_FLOW_CTRL_NONE;

bsp/asm9260t/applications/application.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		 first version
+ * Date           Author        Notes
+ * 2011-01-13     weety      first version
  * 2015-04-27     ArdaFu     Port bsp from at91sam9260 to asm9260t
  */
 

bsp/asm9260t/drivers/usart.c

@@ -58,12 +58,12 @@ static rt_err_t asm_usart_configure(struct rt_serial_device *serial,
     RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
     uart = (asm_uart_t *)serial->parent.user_data;
-    
+
     Hw_UartDisable(uart->port);
 
     Hw_UartReset(uart->port);
-    
-    Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits, 
+
+    Hw_UartConfig(uart->port, cfg->baud_rate, cfg->data_bits,
                   cfg->stop_bits, cfg->parity);
 
     Hw_UartEnable(uart->port);

bsp/asm9260t/platform/gpio.c

@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 #include "asm9260t.h"
 #include "rtthread.h"
 

bsp/asm9260t/platform/interrupt.h

@@ -15,69 +15,69 @@
 
 
 // IRQ Source
-#define INT_ARM_COMMRX                    0 
-#define INT_ARM_COMMTX                    1 
-#define INT_RTC                           2 
-#define INT_GPIO0                         3 
-#define INT_GPIO1                         4 
-#define INT_GPIO2                         5 
-#define INT_GPIO3                         6 
-#define INT_GPIO4_IIS1                    7 
-#define INT_USB0                          8 
-#define INT_USB1                          9 
-#define INT_USB0_DMA                      10  
-#define INT_USB1_DMA                      11  
-#define INT_MAC                           12  
-#define INT_MAC_PMT                       13  
-#define INT_NAND                          14  
-#define INT_UART0                         15  
-#define INT_UART1                         16  
-#define INT_UART2                         17  
-#define INT_UART3                         18  
-#define INT_UART4                         19  
-#define INT_UART5                         20  
-#define INT_UART6                         21  
-#define INT_UART7                         22  
-#define INT_UART8                         23  
-#define INT_UART9                         24  
-#define INT_I2S0                          25  
-#define INT_I2C0                          26  
-#define INT_I2C1                          27  
-#define INT_CAMIF                         28  
-#define INT_TIMER0                        29  
-#define INT_TIMER1                        30  
-#define INT_TIMER2                        31  
-#define INT_TIMER3                        32  
-#define INT_ADC0                          33  
-#define INT_DAC0                          34  
-#define INT_USB0_RESUME_HOSTDISCONNECT    35    
-#define INT_USB0_VBUSVALID                36    
-#define INT_USB1_RESUME_HOSTDISCONNECT    37    
-#define INT_USB1_VBUSVALID                38    
-#define INT_DMA0_CH0                      39  
-#define INT_DMA0_CH1                      40  
-#define INT_DMA0_CH2                      41  
-#define INT_DMA0_CH3                      42  
-#define INT_DMA0_CH4                      43  
-#define INT_DMA0_CH5                      44  
-#define INT_DMA0_CH6                      45  
-#define INT_DMA0_CH7                      46  
-#define INT_DMA1_CH0                      47  
-#define INT_DMA1_CH1                      48  
-#define INT_DMA1_CH2                      49  
-#define INT_DMA1_CH3                      50  
-#define INT_DMA1_CH4                      51  
-#define INT_DMA1_CH5                      52  
-#define INT_DMA1_CH6                      53  
-#define INT_DMA1_CH7                      54  
-#define INT_WATCHDOG                      55  
-#define INT_CAN0                          56  
-#define INT_CAN1                          57  
-#define INT_QEI                           58  
-#define INT_MCPWM                         59  
-#define INT_SPI0                          60  
-#define INT_SPI1                          61  
-#define INT_QUADSPI0                      62  
+#define INT_ARM_COMMRX                    0
+#define INT_ARM_COMMTX                    1
+#define INT_RTC                           2
+#define INT_GPIO0                         3
+#define INT_GPIO1                         4
+#define INT_GPIO2                         5
+#define INT_GPIO3                         6
+#define INT_GPIO4_IIS1                    7
+#define INT_USB0                          8
+#define INT_USB1                          9
+#define INT_USB0_DMA                      10
+#define INT_USB1_DMA                      11
+#define INT_MAC                           12
+#define INT_MAC_PMT                       13
+#define INT_NAND                          14
+#define INT_UART0                         15
+#define INT_UART1                         16
+#define INT_UART2                         17
+#define INT_UART3                         18
+#define INT_UART4                         19
+#define INT_UART5                         20
+#define INT_UART6                         21
+#define INT_UART7                         22
+#define INT_UART8                         23
+#define INT_UART9                         24
+#define INT_I2S0                          25
+#define INT_I2C0                          26
+#define INT_I2C1                          27
+#define INT_CAMIF                         28
+#define INT_TIMER0                        29
+#define INT_TIMER1                        30
+#define INT_TIMER2                        31
+#define INT_TIMER3                        32
+#define INT_ADC0                          33
+#define INT_DAC0                          34
+#define INT_USB0_RESUME_HOSTDISCONNECT    35
+#define INT_USB0_VBUSVALID                36
+#define INT_USB1_RESUME_HOSTDISCONNECT    37
+#define INT_USB1_VBUSVALID                38
+#define INT_DMA0_CH0                      39
+#define INT_DMA0_CH1                      40
+#define INT_DMA0_CH2                      41
+#define INT_DMA0_CH3                      42
+#define INT_DMA0_CH4                      43
+#define INT_DMA0_CH5                      44
+#define INT_DMA0_CH6                      45
+#define INT_DMA0_CH7                      46
+#define INT_DMA1_CH0                      47
+#define INT_DMA1_CH1                      48
+#define INT_DMA1_CH2                      49
+#define INT_DMA1_CH3                      50
+#define INT_DMA1_CH4                      51
+#define INT_DMA1_CH5                      52
+#define INT_DMA1_CH6                      53
+#define INT_DMA1_CH7                      54
+#define INT_WATCHDOG                      55
+#define INT_CAN0                          56
+#define INT_CAN1                          57
+#define INT_QEI                           58
+#define INT_MCPWM                         59
+#define INT_SPI0                          60
+#define INT_SPI1                          61
+#define INT_QUADSPI0                      62
 #define INT_SSP0                          63
 
 #endif

bsp/asm9260t/platform/rt_low_level_init.h

@@ -9,7 +9,7 @@
  */
 #ifndef __RT_LOW_LEVEL_INIT_H__
 #define __RT_LOW_LEVEL_INIT_H__
- 
+
 /*-------- Stack size of CPU modes -------------------------------------------*/
 #define UND_STK_SIZE 512
 #define SVC_STK_SIZE 4096

bsp/asm9260t/platform/system_clock.c

@@ -14,269 +14,269 @@
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk clk32k = {
-	"clk32k",
-	AT91_SLOW_CLOCK,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "clk32k",
+    AT91_SLOW_CLOCK,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk main_clk = {
-	"main",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "main",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk plla = {
-	"plla",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "plla",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk mck = {
-	"mck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "mck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk uhpck = {
-	"uhpck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "uhpck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk pllb = {
-	"pllb",
-	0,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "pllb",
+    0,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk udpck = {
-	"udpck",
-	0,
-	&pllb,
-	{RT_NULL, RT_NULL},
+    "udpck",
+    0,
+    &pllb,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk *const standard_pmc_clocks[] = {
-	// four primary clocks 
-	&clk32k,
-	&main_clk,
-	&plla,
+    // four primary clocks
+    &clk32k,
+    &main_clk,
+    &plla,
 
-	// MCK 
-	&mck
+    // MCK
+    &mck
 };
 
 // clocks cannot be de-registered no refcounting necessary
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
-
-	return RT_NULL;
+    struct clk *clk;
+    rt_list_t *list;
+
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	rate;
-
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return rate;
+    rt_uint32_t rate;
+
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return rate;
 }
 
 static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	unsigned mul, div;
+    unsigned mul, div;
 
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
+    div = reg & 0xff;
+    mul = (reg >> 16) & 0x7ff;
+    if (div && mul) {
+        freq /= div;
+        freq *= mul + 1;
+    } else
+        freq = 0;
 
-	return freq;
+    return freq;
 }
 
 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 {
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	//PLL output max 240 MHz (or 180 MHz per errata)
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		//
-		// PLL input between 1MHz and 32MHz per spec, but lower
-		// frequences seem necessary in some cases so allow 100K.
-		// Warning: some newer products need 2MHz min.
-		//
-		input = main_freq / i;
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
+    unsigned i, div = 0, mul = 0, diff = 1 << 30;
+    unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+    //PLL output max 240 MHz (or 180 MHz per errata)
+    if (out_freq > 240000000)
+        goto fail;
+
+    for (i = 1; i < 256; i++) {
+        int diff1;
+        unsigned input, mul1;
+
+        //
+        // PLL input between 1MHz and 32MHz per spec, but lower
+        // frequences seem necessary in some cases so allow 100K.
+        // Warning: some newer products need 2MHz min.
+        //
+        input = main_freq / i;
+        if (input < 100000)
+            continue;
+        if (input > 32000000)
+            continue;
+
+        mul1 = out_freq / input;
+        if (mul1 > 2048)
+            continue;
+        if (mul1 < 2)
+            goto fail;
+
+        diff1 = out_freq - input * mul1;
+        if (diff1 < 0)
+            diff1 = -diff1;
+        if (diff > diff1) {
+            diff = diff1;
+            div = i;
+            mul = mul1;
+            if (diff == 0)
+                break;
+        }
+    }
+    if (i == 256 && diff > (out_freq >> 5))
+        goto fail;
+    return ret | ((mul - 1) << 16) | div;
 fail:
-	return 0;
+    return 0;
 }
 
 static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	if (pll == &pllb && (reg & AT91_PMC_USB96M))
-		return freq / 2;
-	else
-		return freq;
+    if (pll == &pllb && (reg & AT91_PMC_USB96M))
+        return freq / 2;
+    else
+        return freq;
 }
 
 
 // PLLB generated USB full speed clock init
 static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
 {
-	rt_uint32_t at91_pllb_usb_init;
-	//
-	// USB clock init:  choose 48 MHz PLLB value,
-	// disable 48MHz clock during usb peripheral suspend.
-	//
-	// REVISIT:  assumes MCK doesn't derive from PLLB!
-	//
-	uhpck.parent = &pllb;
-
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
-	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-	
-	at91_sys_write(AT91_CKGR_PLLBR, 0);
-
-	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    rt_uint32_t at91_pllb_usb_init;
+    //
+    // USB clock init:  choose 48 MHz PLLB value,
+    // disable 48MHz clock during usb peripheral suspend.
+    //
+    // REVISIT:  assumes MCK doesn't derive from PLLB!
+    //
+    uhpck.parent = &pllb;
+
+    at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+    pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+
+    at91_sys_write(AT91_CKGR_PLLBR, 0);
+
+    udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 }
 
 static struct clk *at91_css_to_clk(unsigned long css)
 {
-	switch (css) {
-		case AT91_PMC_CSS_SLOW:
-			return &clk32k;
-		case AT91_PMC_CSS_MAIN:
-			return &main_clk;
-		case AT91_PMC_CSS_PLLA:
-			return &plla;
-		case AT91_PMC_CSS_PLLB:
-			return &pllb;
-	}
-
-	return RT_NULL;
+    switch (css) {
+        case AT91_PMC_CSS_SLOW:
+            return &clk32k;
+        case AT91_PMC_CSS_MAIN:
+            return &main_clk;
+        case AT91_PMC_CSS_PLLA:
+            return &plla;
+        case AT91_PMC_CSS_PLLB:
+            return &pllb;
+    }
+
+    return RT_NULL;
 }
 
 #define false 0
 #define true  1
 int at91_clock_init(rt_uint32_t main_clock)
 {
-	unsigned tmp, freq, mckr;
-	int i;
-	int pll_overclock = false;
-
-	//
-	// When the bootloader initialized the main oscillator correctly,
-	// there's no problem using the cycle counter.  But if it didn't,
-	// or when using oscillator bypass mode, we must be told the speed
-	 // of the main clock.
-	//
-	if (!main_clock) {
-		do {
-			tmp = at91_sys_read(AT91_CKGR_MCFR);
-		} while (!(tmp & AT91_PMC_MAINRDY));
-		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
-	}
-	main_clk.rate_hz = main_clock;
-
-	// report if PLLA is more than mildly overclocked 
-	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-	if (plla.rate_hz > 209000000)
-		pll_overclock = true;
-	if (pll_overclock)
-		;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
-	at91_pllb_usbfs_clock_init(main_clock);
-
-	//
-	 // MCK and CPU derive from one of those primary clocks.
-	 // For now, assume this parentage won't change.
-	 //
-	mckr = at91_sys_read(AT91_PMC_MCKR);
-	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
-	freq = mck.parent->rate_hz;
-	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				// prescale 
-	
-	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv 
-
-	// Register the PMC's standard clocks 
-	rt_list_init(&clocks);
-	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
-
-	rt_list_insert_after(&clocks, &pllb.node);
-	rt_list_insert_after(&clocks, &uhpck.node);
-	rt_list_insert_after(&clocks, &udpck.node);
-
-	// MCK and CPU clock are "always on" 
-	//clk_enable(&mck);
-
-	//rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-	//	freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-	//	(unsigned) main_clock / 1000000,
-	//	((unsigned) main_clock % 1000000) / 1000); //cause blocked
-
-	return 0;
+    unsigned tmp, freq, mckr;
+    int i;
+    int pll_overclock = false;
+
+    //
+    // When the bootloader initialized the main oscillator correctly,
+    // there's no problem using the cycle counter.  But if it didn't,
+    // or when using oscillator bypass mode, we must be told the speed
+     // of the main clock.
+    //
+    if (!main_clock) {
+        do {
+            tmp = at91_sys_read(AT91_CKGR_MCFR);
+        } while (!(tmp & AT91_PMC_MAINRDY));
+        main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+    }
+    main_clk.rate_hz = main_clock;
+
+    // report if PLLA is more than mildly overclocked
+    plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+    if (plla.rate_hz > 209000000)
+        pll_overclock = true;
+    if (pll_overclock)
+        ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+
+    at91_pllb_usbfs_clock_init(main_clock);
+
+    //
+     // MCK and CPU derive from one of those primary clocks.
+     // For now, assume this parentage won't change.
+     //
+    mckr = at91_sys_read(AT91_PMC_MCKR);
+    mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+    freq = mck.parent->rate_hz;
+    freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));               // prescale
+
+    mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      // mdiv
+
+    // Register the PMC's standard clocks
+    rt_list_init(&clocks);
+    for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+        rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+    rt_list_insert_after(&clocks, &pllb.node);
+    rt_list_insert_after(&clocks, &uhpck.node);
+    rt_list_insert_after(&clocks, &udpck.node);
+
+    // MCK and CPU clock are "always on"
+    //clk_enable(&mck);
+
+    //rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+    //  freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+    //  (unsigned) main_clock / 1000000,
+    //  ((unsigned) main_clock % 1000000) / 1000); //cause blocked
+
+    return 0;
 }
 */
 
@@ -284,6 +284,6 @@ int at91_clock_init(rt_uint32_t main_clock)
 
 void rt_hw_clock_init(void)
 {
-	//at91_clock_init(18432000);
+    //at91_clock_init(18432000);
 }
 

bsp/asm9260t/platform/uart.c

@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 #include "asm9260t.h"
 #include "rtthread.h"
 #include "uart.h"

bsp/asm9260t/platform/uart.h

@@ -36,16 +36,16 @@ typedef struct
     volatile rt_uint32_t ISO7816STATUS[4];
 } HW_USART_TypeDef;
 
-#define USART0	((HW_USART_TypeDef *)UART0_BASE)
-#define USART1	((HW_USART_TypeDef *)UART1_BASE)
-#define USART2	((HW_USART_TypeDef *)UART2_BASE)
-#define USART3	((HW_USART_TypeDef *)UART3_BASE)
-#define USART4	((HW_USART_TypeDef *)UART4_BASE)
-#define USART5	((HW_USART_TypeDef *)UART5_BASE)
-#define USART6	((HW_USART_TypeDef *)UART6_BASE)
-#define USART7	((HW_USART_TypeDef *)UART7_BASE)
-#define USART8	((HW_USART_TypeDef *)UART8_BASE)
-#define USART9	((HW_USART_TypeDef *)UART9_BASE)
+#define USART0  ((HW_USART_TypeDef *)UART0_BASE)
+#define USART1  ((HW_USART_TypeDef *)UART1_BASE)
+#define USART2  ((HW_USART_TypeDef *)UART2_BASE)
+#define USART3  ((HW_USART_TypeDef *)UART3_BASE)
+#define USART4  ((HW_USART_TypeDef *)UART4_BASE)
+#define USART5  ((HW_USART_TypeDef *)UART5_BASE)
+#define USART6  ((HW_USART_TypeDef *)UART6_BASE)
+#define USART7  ((HW_USART_TypeDef *)UART7_BASE)
+#define USART8  ((HW_USART_TypeDef *)UART8_BASE)
+#define USART9  ((HW_USART_TypeDef *)UART9_BASE)
 
 
 #define ASM_UART_INTR_RXIS   (1UL << 4)
@@ -91,7 +91,7 @@ typedef struct
 extern void Hw_UartDisable(HW_USART_TypeDef* uartBase);
 extern void Hw_UartEnable(HW_USART_TypeDef* uartBase);
 extern void Hw_UartReset(HW_USART_TypeDef* uartBase);
-extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate, 
+extern void Hw_UartConfig(HW_USART_TypeDef* uartBase, int baudRate,
                           int dataBits, int stopBits, int parity);
 extern void Hw_UartInit(int index);
 #endif

bsp/at91sam9260/applications/application.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 /**
@@ -34,106 +34,106 @@ static int rt_led_app_init(void);
 
 int main(void)
 {
-	int timeout = 0;
+    int timeout = 0;
 
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
+    {
 #if defined(RT_USING_DFS_ROMFS)
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
+        if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+        {
+            rt_kprintf("ROM File System initialized!\n");
+        }
+        else
+            rt_kprintf("ROM File System initialzation failed!\n");
 #endif
 
 #if defined(RT_USING_DFS_UFFS)
-	{
-		/* mount flash device as flash directory */
-		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-	}
+    {
+        /* mount flash device as flash directory */
+        if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+            rt_kprintf("UFFS File System initialized!\n");
+        else
+            rt_kprintf("UFFS File System initialzation failed!\n");
+    }
 #endif
 
 #ifdef RT_USING_SDIO
-	timeout = 0;
-	while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
-	{
-		rt_thread_delay(1);
-	}
-
-	if (timeout < RT_TICK_PER_SECOND*2)
-	{
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
-	}
-	else
-	{
-		rt_kprintf("No SD card found.\n");
-	}
+    timeout = 0;
+    while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
+    {
+        rt_thread_delay(1);
+    }
+
+    if (timeout < RT_TICK_PER_SECOND*2)
+    {
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+        {
+            rt_kprintf("File System initialized!\n");
+        }
+        else
+            rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
+    }
+    else
+    {
+        rt_kprintf("No SD card found.\n");
+    }
 #endif
-	}
+    }
 #endif
-	
+
 #ifdef RT_USING_LED
-	rt_led_app_init();
+    rt_led_app_init();
 #endif
 }
 
 #ifdef RT_USING_LED
 void rt_led_thread_entry(void* parameter)
 {
-	rt_uint8_t cnt = 0;
-	led_init();
-	while(1)
-	{
-		/* light on leds for one second */
-		rt_thread_delay(40);
-		cnt++;
-		if (cnt&0x01)
-			led_on(1);
-		else
-			led_off(1);
-		if (cnt&0x02)
-			led_on(2);
-		else
-			led_off(2);
-		if (cnt&0x04)
-			led_on(3);
-		else
-			led_off(3);
-	}
+    rt_uint8_t cnt = 0;
+    led_init();
+    while(1)
+    {
+        /* light on leds for one second */
+        rt_thread_delay(40);
+        cnt++;
+        if (cnt&0x01)
+            led_on(1);
+        else
+            led_off(1);
+        if (cnt&0x02)
+            led_on(2);
+        else
+            led_off(2);
+        if (cnt&0x04)
+            led_on(3);
+        else
+            led_off(3);
+    }
 }
 #endif
 
 static int rt_led_app_init(void)
 {
 #ifdef RT_USING_LED
-	rt_thread_t led_thread;
+    rt_thread_t led_thread;
 
 #if (RT_THREAD_PRIORITY_MAX == 32)
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 20, 20);						
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 20, 20);
 #else
-	led_thread = rt_thread_create("led",
-								rt_led_thread_entry, RT_NULL,
-								512, 200, 20);					
+    led_thread = rt_thread_create("led",
+                                rt_led_thread_entry, RT_NULL,
+                                512, 200, 20);
 #endif
 
-	if(led_thread != RT_NULL)
-		rt_thread_startup(led_thread);
+    if(led_thread != RT_NULL)
+        rt_thread_startup(led_thread);
 #endif
 
-	return 0;
+    return 0;
 }
 
 /* NFSv3 Initialization */
@@ -141,14 +141,14 @@ static int rt_led_app_init(void)
 #include <dfs_nfs.h>
 void nfs_start(void)
 {
-	nfs_init();
-
-	if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-	{
-		rt_kprintf("NFSv3 File System initialized!\n");
-	}
-	else
-		rt_kprintf("NFSv3 File System initialzation failed!\n");
+    nfs_init();
+
+    if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
+    {
+        rt_kprintf("NFSv3 File System initialized!\n");
+    }
+    else
+        rt_kprintf("NFSv3 File System initialzation failed!\n");
 }
 
 #include "finsh.h"

bsp/at91sam9260/drivers/at91_i2c_gpio.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2012-04-25     weety		first version
+ * Date           Author        Notes
+ * 2012-04-25     weety     first version
  */
 
 #include <rtdevice.h>
@@ -15,101 +15,101 @@
 
 static void at91_i2c_gpio_init()
 {
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
-	at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
-	at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
-	at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
-
-	at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
-
-	at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
-	at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOA); //enable PIOA clock
+    at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_PER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_PUER, (1 << 24));
+    at91_sys_write(AT91_PIOA + PIO_PER, (1 << 24));
+    at91_sys_write(AT91_PIOA + PIO_MDER, (1 << 24));
+
+    at91_sys_write(AT91_PIOA + PIO_OER, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_OER, (1 << 24));
+
+    at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
+    at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
 }
 
 static void at91_set_sda(void *data, rt_int32_t state)
 {
-	if (state)
-	{
-		at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
-	}
-	else
-	{
-		at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
-	}
+    if (state)
+    {
+        at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 23));
+    }
+    else
+    {
+        at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 23));
+    }
 }
 
 static void at91_set_scl(void *data, rt_int32_t state)
 {
-	if (state)
-	{
-		at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
-	}
-	else
-	{
-		at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
-	}
+    if (state)
+    {
+        at91_sys_write(AT91_PIOA + PIO_SODR, (1 << 24));
+    }
+    else
+    {
+        at91_sys_write(AT91_PIOA + PIO_CODR, (1 << 24));
+    }
 }
 
 static rt_int32_t  at91_get_sda(void *data)
 {
-	return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
+    return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 23);
 }
 
 static rt_int32_t  at91_get_scl(void *data)
 {
-	return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
+    return at91_sys_read(AT91_PIOA + PIO_PDSR) & (1 << 24);
 }
 
 static void at91_udelay (rt_uint32_t us)
 {
-	rt_int32_t i;
-	for (; us > 0; us--)
-	{
-		i = 50000;
-		while(i > 0)
-		{
-			i--;
-		}
-	}
+    rt_int32_t i;
+    for (; us > 0; us--)
+    {
+        i = 50000;
+        while(i > 0)
+        {
+            i--;
+        }
+    }
 }
 
 static const struct rt_i2c_bit_ops bit_ops = {
-	RT_NULL,
-	at91_set_sda,
-	at91_set_scl,
-	at91_get_sda,
-	at91_get_scl,
-	
-	at91_udelay,
-
-	5,
-	100
+    RT_NULL,
+    at91_set_sda,
+    at91_set_scl,
+    at91_get_sda,
+    at91_get_scl,
+
+    at91_udelay,
+
+    5,
+    100
 };
 
 int at91_i2c_init(void)
 {
-	struct rt_i2c_bus_device *bus;
+    struct rt_i2c_bus_device *bus;
+
+    bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+    if (bus == RT_NULL)
+    {
+        rt_kprintf("rt_malloc failed\n");
+        return -RT_ENOMEM;
+    }
 
-	bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
-	if (bus == RT_NULL)
-	{
-		rt_kprintf("rt_malloc failed\n");
-		return -RT_ENOMEM;
-	}
-	
-	rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+    rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
 
-	bus->priv = (void *)&bit_ops;
+    bus->priv = (void *)&bit_ops;
 
-	at91_i2c_gpio_init();
+    at91_i2c_gpio_init();
 
-	rt_i2c_bit_add_bus(bus, "i2c0");
+    rt_i2c_bit_add_bus(bus, "i2c0");
 
-	return 0;
+    return 0;
 }
 
 INIT_DEVICE_EXPORT(at91_i2c_init);

bsp/at91sam9260/drivers/at91_mci.h

@@ -11,99 +11,99 @@
 #ifndef __AT91_MCI_H__
 #define __AT91_MCI_H__
 
-#define AT91_MCI_CR		0x00		/* Control Register */
-#define		AT91_MCI_MCIEN		(1 <<  0)	/* Multi-Media Interface Enable */
-#define		AT91_MCI_MCIDIS		(1 <<  1)	/* Multi-Media Interface Disable */
-#define		AT91_MCI_PWSEN		(1 <<  2)	/* Power Save Mode Enable */
-#define		AT91_MCI_PWSDIS		(1 <<  3)	/* Power Save Mode Disable */
-#define		AT91_MCI_SWRST		(1 <<  7)	/* Software Reset */
+#define AT91_MCI_CR     0x00        /* Control Register */
+#define     AT91_MCI_MCIEN      (1 <<  0)   /* Multi-Media Interface Enable */
+#define     AT91_MCI_MCIDIS     (1 <<  1)   /* Multi-Media Interface Disable */
+#define     AT91_MCI_PWSEN      (1 <<  2)   /* Power Save Mode Enable */
+#define     AT91_MCI_PWSDIS     (1 <<  3)   /* Power Save Mode Disable */
+#define     AT91_MCI_SWRST      (1 <<  7)   /* Software Reset */
 
-#define AT91_MCI_MR		0x04		/* Mode Register */
-#define		AT91_MCI_CLKDIV		(0xff  <<  0)	/* Clock Divider */
-#define		AT91_MCI_PWSDIV		(7     <<  8)	/* Power Saving Divider */
-#define		AT91_MCI_RDPROOF	(1     << 11)	/* Read Proof Enable [SAM926[03] only] */
-#define		AT91_MCI_WRPROOF	(1     << 12)	/* Write Proof Enable [SAM926[03] only] */
-#define		AT91_MCI_PDCFBYTE	(1     << 13)	/* PDC Force Byte Transfer [SAM926[03] only] */
-#define		AT91_MCI_PDCPADV	(1     << 14)	/* PDC Padding Value */
-#define		AT91_MCI_PDCMODE	(1     << 15)	/* PDC-orientated Mode */
-#define		AT91_MCI_BLKLEN		(0xfff << 18)	/* Data Block Length */
+#define AT91_MCI_MR     0x04        /* Mode Register */
+#define     AT91_MCI_CLKDIV     (0xff  <<  0)   /* Clock Divider */
+#define     AT91_MCI_PWSDIV     (7     <<  8)   /* Power Saving Divider */
+#define     AT91_MCI_RDPROOF    (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define     AT91_MCI_WRPROOF    (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define     AT91_MCI_PDCFBYTE   (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
+#define     AT91_MCI_PDCPADV    (1     << 14)   /* PDC Padding Value */
+#define     AT91_MCI_PDCMODE    (1     << 15)   /* PDC-orientated Mode */
+#define     AT91_MCI_BLKLEN     (0xfff << 18)   /* Data Block Length */
 
-#define AT91_MCI_DTOR		0x08		/* Data Timeout Register */
-#define		AT91_MCI_DTOCYC		(0xf << 0)	/* Data Timeout Cycle Number */
-#define		AT91_MCI_DTOMUL		(7   << 4)	/* Data Timeout Multiplier */
-#define		AT91_MCI_DTOMUL_1		(0 <<  4)
-#define		AT91_MCI_DTOMUL_16		(1 <<  4)
-#define		AT91_MCI_DTOMUL_128		(2 <<  4)
-#define		AT91_MCI_DTOMUL_256		(3 <<  4)
-#define		AT91_MCI_DTOMUL_1K		(4 <<  4)
-#define		AT91_MCI_DTOMUL_4K		(5 <<  4)
-#define		AT91_MCI_DTOMUL_64K		(6 <<  4)
-#define		AT91_MCI_DTOMUL_1M		(7 <<  4)
+#define AT91_MCI_DTOR       0x08        /* Data Timeout Register */
+#define     AT91_MCI_DTOCYC     (0xf << 0)  /* Data Timeout Cycle Number */
+#define     AT91_MCI_DTOMUL     (7   << 4)  /* Data Timeout Multiplier */
+#define     AT91_MCI_DTOMUL_1       (0 <<  4)
+#define     AT91_MCI_DTOMUL_16      (1 <<  4)
+#define     AT91_MCI_DTOMUL_128     (2 <<  4)
+#define     AT91_MCI_DTOMUL_256     (3 <<  4)
+#define     AT91_MCI_DTOMUL_1K      (4 <<  4)
+#define     AT91_MCI_DTOMUL_4K      (5 <<  4)
+#define     AT91_MCI_DTOMUL_64K     (6 <<  4)
+#define     AT91_MCI_DTOMUL_1M      (7 <<  4)
 
-#define AT91_MCI_SDCR		0x0c		/* SD Card Register */
-#define		AT91_MCI_SDCSEL		(3 << 0)	/* SD Card Selector */
-#define		AT91_MCI_SDCBUS		(1 << 7)	/* 1-bit or 4-bit bus */
+#define AT91_MCI_SDCR       0x0c        /* SD Card Register */
+#define     AT91_MCI_SDCSEL     (3 << 0)    /* SD Card Selector */
+#define     AT91_MCI_SDCBUS     (1 << 7)    /* 1-bit or 4-bit bus */
 
-#define AT91_MCI_ARGR		0x10		/* Argument Register */
+#define AT91_MCI_ARGR       0x10        /* Argument Register */
 
-#define AT91_MCI_CMDR		0x14		/* Command Register */
-#define		AT91_MCI_CMDNB		(0x3f << 0)	/* Command Number */
-#define		AT91_MCI_RSPTYP		(3    << 6)	/* Response Type */
-#define			AT91_MCI_RSPTYP_NONE	(0 <<  6)
-#define			AT91_MCI_RSPTYP_48	(1 <<  6)
-#define			AT91_MCI_RSPTYP_136	(2 <<  6)
-#define		AT91_MCI_SPCMD		(7    << 8)	/* Special Command */
-#define			AT91_MCI_SPCMD_NONE	(0 <<  8)
-#define			AT91_MCI_SPCMD_INIT	(1 <<  8)
-#define			AT91_MCI_SPCMD_SYNC	(2 <<  8)
-#define			AT91_MCI_SPCMD_ICMD	(4 <<  8)
-#define			AT91_MCI_SPCMD_IRESP	(5 <<  8)
-#define		AT91_MCI_OPDCMD		(1 << 11)	/* Open Drain Command */
-#define		AT91_MCI_MAXLAT		(1 << 12)	/* Max Latency for Command to Response */
-#define		AT91_MCI_TRCMD		(3 << 16)	/* Transfer Command */
-#define			AT91_MCI_TRCMD_NONE	(0 << 16)
-#define			AT91_MCI_TRCMD_START	(1 << 16)
-#define			AT91_MCI_TRCMD_STOP	(2 << 16)
-#define		AT91_MCI_TRDIR		(1 << 18)	/* Transfer Direction */
-#define		AT91_MCI_TRTYP		(3 << 19)	/* Transfer Type */
-#define			AT91_MCI_TRTYP_BLOCK	(0 << 19)
-#define			AT91_MCI_TRTYP_MULTIPLE	(1 << 19)
-#define			AT91_MCI_TRTYP_STREAM	(2 << 19)
+#define AT91_MCI_CMDR       0x14        /* Command Register */
+#define     AT91_MCI_CMDNB      (0x3f << 0) /* Command Number */
+#define     AT91_MCI_RSPTYP     (3    << 6) /* Response Type */
+#define         AT91_MCI_RSPTYP_NONE    (0 <<  6)
+#define         AT91_MCI_RSPTYP_48  (1 <<  6)
+#define         AT91_MCI_RSPTYP_136 (2 <<  6)
+#define     AT91_MCI_SPCMD      (7    << 8) /* Special Command */
+#define         AT91_MCI_SPCMD_NONE (0 <<  8)
+#define         AT91_MCI_SPCMD_INIT (1 <<  8)
+#define         AT91_MCI_SPCMD_SYNC (2 <<  8)
+#define         AT91_MCI_SPCMD_ICMD (4 <<  8)
+#define         AT91_MCI_SPCMD_IRESP    (5 <<  8)
+#define     AT91_MCI_OPDCMD     (1 << 11)   /* Open Drain Command */
+#define     AT91_MCI_MAXLAT     (1 << 12)   /* Max Latency for Command to Response */
+#define     AT91_MCI_TRCMD      (3 << 16)   /* Transfer Command */
+#define         AT91_MCI_TRCMD_NONE (0 << 16)
+#define         AT91_MCI_TRCMD_START    (1 << 16)
+#define         AT91_MCI_TRCMD_STOP (2 << 16)
+#define     AT91_MCI_TRDIR      (1 << 18)   /* Transfer Direction */
+#define     AT91_MCI_TRTYP      (3 << 19)   /* Transfer Type */
+#define         AT91_MCI_TRTYP_BLOCK    (0 << 19)
+#define         AT91_MCI_TRTYP_MULTIPLE (1 << 19)
+#define         AT91_MCI_TRTYP_STREAM   (2 << 19)
 
-#define AT91_MCI_BLKR		0x18		/* Block Register */
-#define		AT91_MCI_BLKR_BCNT(n)	((0xffff & (n)) << 0)	/* Block count */
-#define		AT91_MCI_BLKR_BLKLEN(n)	((0xffff & (n)) << 16)	/* Block lenght */
+#define AT91_MCI_BLKR       0x18        /* Block Register */
+#define     AT91_MCI_BLKR_BCNT(n)   ((0xffff & (n)) << 0)   /* Block count */
+#define     AT91_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16)  /* Block lenght */
 
-#define AT91_MCI_RSPR(n)	(0x20 + ((n) * 4))	/* Response Registers 0-3 */
-#define AT91_MCR_RDR		0x30		/* Receive Data Register */
-#define AT91_MCR_TDR		0x34		/* Transmit Data Register */
+#define AT91_MCI_RSPR(n)    (0x20 + ((n) * 4))  /* Response Registers 0-3 */
+#define AT91_MCR_RDR        0x30        /* Receive Data Register */
+#define AT91_MCR_TDR        0x34        /* Transmit Data Register */
 
-#define AT91_MCI_SR		0x40		/* Status Register */
-#define		AT91_MCI_CMDRDY		(1U <<  0)	/* Command Ready */
-#define		AT91_MCI_RXRDY		(1U <<  1)	/* Receiver Ready */
-#define		AT91_MCI_TXRDY		(1U <<  2)	/* Transmit Ready */
-#define		AT91_MCI_BLKE		(1U <<  3)	/* Data Block Ended */
-#define		AT91_MCI_DTIP		(1U <<  4)	/* Data Transfer in Progress */
-#define		AT91_MCI_NOTBUSY	(1U <<  5)	/* Data Not Busy */
-#define		AT91_MCI_ENDRX		(1U <<  6)	/* End of RX Buffer */
-#define		AT91_MCI_ENDTX		(1U <<  7)	/* End fo TX Buffer */
-#define		AT91_MCI_SDIOIRQA	(1U <<  8)	/* SDIO Interrupt for Slot A */
-#define		AT91_MCI_SDIOIRQB	(1U <<  9)	/* SDIO Interrupt for Slot B */
-#define		AT91_MCI_RXBUFF		(1U << 14)	/* RX Buffer Full */
-#define		AT91_MCI_TXBUFE		(1U << 15)	/* TX Buffer Empty */
-#define		AT91_MCI_RINDE		(1U << 16)	/* Response Index Error */
-#define		AT91_MCI_RDIRE		(1U << 17)	/* Response Direction Error */
-#define		AT91_MCI_RCRCE		(1U << 18)	/* Response CRC Error */
-#define		AT91_MCI_RENDE		(1U << 19)	/* Response End Bit Error */
-#define		AT91_MCI_RTOE		(1U << 20)	/* Reponse Time-out Error */
-#define		AT91_MCI_DCRCE		(1U << 21)	/* Data CRC Error */
-#define		AT91_MCI_DTOE		(1U << 22)	/* Data Time-out Error */
-#define		AT91_MCI_OVRE		(1U << 30)	/* Overrun */
-#define		AT91_MCI_UNRE		(1U << 31)	/* Underrun */
+#define AT91_MCI_SR     0x40        /* Status Register */
+#define     AT91_MCI_CMDRDY     (1U <<  0)  /* Command Ready */
+#define     AT91_MCI_RXRDY      (1U <<  1)  /* Receiver Ready */
+#define     AT91_MCI_TXRDY      (1U <<  2)  /* Transmit Ready */
+#define     AT91_MCI_BLKE       (1U <<  3)  /* Data Block Ended */
+#define     AT91_MCI_DTIP       (1U <<  4)  /* Data Transfer in Progress */
+#define     AT91_MCI_NOTBUSY    (1U <<  5)  /* Data Not Busy */
+#define     AT91_MCI_ENDRX      (1U <<  6)  /* End of RX Buffer */
+#define     AT91_MCI_ENDTX      (1U <<  7)  /* End fo TX Buffer */
+#define     AT91_MCI_SDIOIRQA   (1U <<  8)  /* SDIO Interrupt for Slot A */
+#define     AT91_MCI_SDIOIRQB   (1U <<  9)  /* SDIO Interrupt for Slot B */
+#define     AT91_MCI_RXBUFF     (1U << 14)  /* RX Buffer Full */
+#define     AT91_MCI_TXBUFE     (1U << 15)  /* TX Buffer Empty */
+#define     AT91_MCI_RINDE      (1U << 16)  /* Response Index Error */
+#define     AT91_MCI_RDIRE      (1U << 17)  /* Response Direction Error */
+#define     AT91_MCI_RCRCE      (1U << 18)  /* Response CRC Error */
+#define     AT91_MCI_RENDE      (1U << 19)  /* Response End Bit Error */
+#define     AT91_MCI_RTOE       (1U << 20)  /* Reponse Time-out Error */
+#define     AT91_MCI_DCRCE      (1U << 21)  /* Data CRC Error */
+#define     AT91_MCI_DTOE       (1U << 22)  /* Data Time-out Error */
+#define     AT91_MCI_OVRE       (1U << 30)  /* Overrun */
+#define     AT91_MCI_UNRE       (1U << 31)  /* Underrun */
 
-#define AT91_MCI_IER		0x44		/* Interrupt Enable Register */
-#define AT91_MCI_IDR		0x48		/* Interrupt Disable Register */
-#define AT91_MCI_IMR		0x4c		/* Interrupt Mask Register */
+#define AT91_MCI_IER        0x44        /* Interrupt Enable Register */
+#define AT91_MCI_IDR        0x48        /* Interrupt Disable Register */
+#define AT91_MCI_IMR        0x4c        /* Interrupt Mask Register */
 
 extern int at91_mci_init(void);
 

bsp/at91sam9260/drivers/board.c

@@ -40,56 +40,56 @@ extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
 extern void rt_dbgu_isr(void);
 
 static struct mem_desc at91_mem_desc[] = {
-	{ 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
-	{ 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
-	{ 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
-	{ 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB },   /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
-	{ 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }    /* 64M none-cached SDRAM memory */
+    { 0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB },     /* None cached for 4G memory */
+    { 0x20000000, 0x24000000-1, 0x20000000, RW_CB },     /* 64M cached SDRAM memory */
+    { 0x00000000, 0x100000, 0x20000000, RW_CB },         /* isr vector table */
+    { 0x90000000, 0x90400000-1, 0x00200000, RW_NCNB },   /* 4K SRAM0@2M + 4k SRAM1@3M + 16k UHP@5M */
+    { 0xA0000000, 0xA4000000-1, 0x20000000, RW_NCNB }    /* 64M none-cached SDRAM memory */
 };
 
 
-#define PIT_CPIV(x)	((x) & AT91_PIT_CPIV)
-#define PIT_PICNT(x)	(((x) & AT91_PIT_PICNT) >> 20)
+#define PIT_CPIV(x) ((x) & AT91_PIT_CPIV)
+#define PIT_PICNT(x)    (((x) & AT91_PIT_PICNT) >> 20)
 
-static rt_uint32_t pit_cycle;		/* write-once */
-static rt_uint32_t pit_cnt;		/* access only w/system irq blocked */
+static rt_uint32_t pit_cycle;       /* write-once */
+static rt_uint32_t pit_cnt;     /* access only w/system irq blocked */
 
 /**
  * This function will handle rtos timer
  */
 void rt_timer_handler(int vector, void *param)
 {
-	#ifdef RT_USING_DBGU
-	if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
-	{
-		rt_dbgu_isr();
-	}
-	#endif
-	if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
-	{
-		unsigned nr_ticks;
-
-		/* Get number of ticks performed before irq, and ack it */
-		nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
-		rt_tick_increase();
-	}
+    #ifdef RT_USING_DBGU
+    if (at91_sys_read(AT91_DBGU + AT91_US_CSR) & 0x1)
+    {
+        rt_dbgu_isr();
+    }
+    #endif
+    if (at91_sys_read(AT91_PIT_SR) & AT91_PIT_PITS)
+    {
+        unsigned nr_ticks;
+
+        /* Get number of ticks performed before irq, and ack it */
+        nr_ticks = PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+        rt_tick_increase();
+    }
 }
 
 static void at91sam926x_pit_reset(void)
 {
-	/* Disable timer and irqs */
-	at91_sys_write(AT91_PIT_MR, 0);
-
-	/* Clear any pending interrupts, wait for PIT to stop counting */
-	while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
-		;
-
-	/* Start PIT but don't enable IRQ */
-	//at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
-	pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
-	at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
-			| AT91_PIT_PITIEN);
-	rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
+    /* Disable timer and irqs */
+    at91_sys_write(AT91_PIT_MR, 0);
+
+    /* Clear any pending interrupts, wait for PIT to stop counting */
+    while (PIT_CPIV(at91_sys_read(AT91_PIT_PIVR)) != 0)
+        ;
+
+    /* Start PIT but don't enable IRQ */
+    //at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN);
+    pit_cnt += pit_cycle * PIT_PICNT(at91_sys_read(AT91_PIT_PIVR));
+    at91_sys_write(AT91_PIT_MR, (pit_cycle - 1) | AT91_PIT_PITEN
+            | AT91_PIT_PITIEN);
+    rt_kprintf("PIT_MR=0x%08x\n", at91_sys_read(AT91_PIT_MR));
 }
 
 /*
@@ -97,19 +97,19 @@ static void at91sam926x_pit_reset(void)
  */
 static void at91sam926x_pit_init(void)
 {
-	rt_uint32_t	pit_rate;
-	rt_uint32_t	bits;
+    rt_uint32_t pit_rate;
+    rt_uint32_t bits;
 
-	/*
-	 * Use our actual MCK to figure out how many MCK/16 ticks per
-	 * 1/HZ period (instead of a compile-time constant LATCH).
-	 */
-	pit_rate = clk_get_rate(clk_get("mck")) / 16;
-	rt_kprintf("pit_rate=%dHZ\n", pit_rate);
-	pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
+    /*
+     * Use our actual MCK to figure out how many MCK/16 ticks per
+     * 1/HZ period (instead of a compile-time constant LATCH).
+     */
+    pit_rate = clk_get_rate(clk_get("mck")) / 16;
+    rt_kprintf("pit_rate=%dHZ\n", pit_rate);
+    pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
 
-	/* Initialize and enable the timer */
-	at91sam926x_pit_reset();
+    /* Initialize and enable the timer */
+    at91sam926x_pit_reset();
 
 }
 
@@ -118,69 +118,69 @@ static void at91sam926x_pit_init(void)
  */
  void rt_hw_timer_init()
  {
- 	at91sam926x_pit_init();
+    at91sam926x_pit_init();
 
-	/* install interrupt handler */
-	rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler, 
-							RT_NULL, "system");
-	rt_hw_interrupt_umask(AT91_ID_SYS);
+    /* install interrupt handler */
+    rt_hw_interrupt_install(AT91_ID_SYS, rt_timer_handler,
+                            RT_NULL, "system");
+    rt_hw_interrupt_umask(AT91_ID_SYS);
 
  }
- 
+
  void at91_tc1_init()
  {
- 	at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
- 	writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
- 	writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
- 	writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
- 	writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
+    at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_TC0);
+    writel(AT91_TC_TC0XC0S_NONE | AT91_TC_TC1XC1S_NONE | AT91_TC_TC2XC2S_NONE, AT91SAM9260_BASE_TCB0 + AT91_TC_BMR);
+    writel(AT91_TC_CLKDIS, AT91SAM9260_BASE_TC0 + AT91_TC_CCR);
+    writel(AT91_TC_TIMER_CLOCK4, AT91SAM9260_BASE_TC0 + AT91_TC_CMR);
+    writel(0xffff, AT91SAM9260_BASE_TC0 + AT91_TC_CV);
  }
 
-#define RXRDY			0x01
-#define TXRDY			(1 << 1)
-#define BPS			115200	/* serial baudrate */
+#define RXRDY           0x01
+#define TXRDY           (1 << 1)
+#define BPS         115200  /* serial baudrate */
 
 typedef struct uartport
 {
-	volatile rt_uint32_t CR;
-	volatile rt_uint32_t MR;
-	volatile rt_uint32_t IER;
-	volatile rt_uint32_t IDR;
-	volatile rt_uint32_t IMR;
-	volatile rt_uint32_t CSR;
-	volatile rt_uint32_t RHR;
-	volatile rt_uint32_t THR;
-	volatile rt_uint32_t BRGR;
-	volatile rt_uint32_t RTOR;
-	volatile rt_uint32_t TTGR;
-	volatile rt_uint32_t reserved0[5];
-	volatile rt_uint32_t FIDI;
-	volatile rt_uint32_t NER;
-	volatile rt_uint32_t reserved1;
-	volatile rt_uint32_t IFR;
-	volatile rt_uint32_t reserved2[44];
-	volatile rt_uint32_t RPR;
-	volatile rt_uint32_t RCR;
-	volatile rt_uint32_t TPR;
-	volatile rt_uint32_t TCR;
-	volatile rt_uint32_t RNPR;
-	volatile rt_uint32_t RNCR;
-	volatile rt_uint32_t TNPR;
-	volatile rt_uint32_t TNCR;
-	volatile rt_uint32_t PTCR;
-	volatile rt_uint32_t PTSR;
+    volatile rt_uint32_t CR;
+    volatile rt_uint32_t MR;
+    volatile rt_uint32_t IER;
+    volatile rt_uint32_t IDR;
+    volatile rt_uint32_t IMR;
+    volatile rt_uint32_t CSR;
+    volatile rt_uint32_t RHR;
+    volatile rt_uint32_t THR;
+    volatile rt_uint32_t BRGR;
+    volatile rt_uint32_t RTOR;
+    volatile rt_uint32_t TTGR;
+    volatile rt_uint32_t reserved0[5];
+    volatile rt_uint32_t FIDI;
+    volatile rt_uint32_t NER;
+    volatile rt_uint32_t reserved1;
+    volatile rt_uint32_t IFR;
+    volatile rt_uint32_t reserved2[44];
+    volatile rt_uint32_t RPR;
+    volatile rt_uint32_t RCR;
+    volatile rt_uint32_t TPR;
+    volatile rt_uint32_t TCR;
+    volatile rt_uint32_t RNPR;
+    volatile rt_uint32_t RNCR;
+    volatile rt_uint32_t TNPR;
+    volatile rt_uint32_t TNCR;
+    volatile rt_uint32_t PTCR;
+    volatile rt_uint32_t PTSR;
 }uartport;
 
 #define CIDR FIDI
 #define EXID NER
 #define FNR  reserved1
 
-#define DBGU	((struct uartport *)AT91SAM9260_BASE_DBGU)
+#define DBGU    ((struct uartport *)AT91SAM9260_BASE_DBGU)
 
 static void at91_usart_putc(char c)
 {
     while (!(DBGU->CSR & TXRDY));
-	DBGU->THR = c;
+    DBGU->THR = c;
 }
 
 /**
@@ -191,33 +191,33 @@ static void at91_usart_putc(char c)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
-		if (*str=='\n')
-		{
-			at91_usart_putc('\r');
-		}
-
-		at91_usart_putc(*str++);
-	}
+    while (*str)
+    {
+        if (*str=='\n')
+        {
+            at91_usart_putc('\r');
+        }
+
+        at91_usart_putc(*str++);
+    }
 }
 
 static void rt_hw_console_init(void)
 {
-	int div;
-	int mode = 0;
-
-	DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX | 
-	       AT91_US_RXDIS | AT91_US_TXDIS;
-	mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | 
-		AT91_US_CHMODE_NORMAL;
-	mode |= AT91_US_CHRL_8;
-	mode |= AT91_US_NBSTOP_1;
-	mode |= AT91_US_PAR_NONE;
-	DBGU->MR = mode;
-	div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
-	DBGU->BRGR = div;
-	DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
+    int div;
+    int mode = 0;
+
+    DBGU->CR = AT91_US_RSTTX | AT91_US_RSTRX |
+           AT91_US_RXDIS | AT91_US_TXDIS;
+    mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
+        AT91_US_CHMODE_NORMAL;
+    mode |= AT91_US_CHRL_8;
+    mode |= AT91_US_NBSTOP_1;
+    mode |= AT91_US_PAR_NONE;
+    DBGU->MR = mode;
+    div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
+    DBGU->BRGR = div;
+    DBGU->CR = AT91_US_RXEN | AT91_US_TXEN;
 }
 
 
@@ -226,31 +226,31 @@ static void rt_hw_console_init(void)
  */
 void rt_hw_board_init()
 {
-	/* initialize the system clock */
-	rt_hw_clock_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
 
-	/* initialize console */
-	rt_hw_console_init();
+    /* initialize console */
+    rt_hw_console_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
+    /* initialize mmu */
+    rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
 
-	/* initialize hardware interrupt */
-	rt_hw_interrupt_init();
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize early device */
+    /* initialize early device */
 #ifdef RT_USING_COMPONENTS_INIT
-	rt_components_board_init();
+    rt_components_board_init();
 #endif
 #ifdef RT_USING_CONSOLE
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
-	/* initialize timer0 */
-	rt_hw_timer_init();
+    /* initialize timer0 */
+    rt_hw_timer_init();
 
 /* initialize board */
 #ifdef RT_USING_HEAP
-	rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
+    rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
 #endif
 
 }

bsp/at91sam9260/drivers/led.c

@@ -14,59 +14,59 @@
 
 #if 1
 // GB9260 board
-#define PIO_LED		AT91_PIOB
-#define LED1		(1 << 25)	// LED_SYS
-#define LED2		(0)
-#define LED3		(1 << 23)	// LED_USR
-#define LED_ALL		(LED1 | LED2 | LED3)
+#define PIO_LED     AT91_PIOB
+#define LED1        (1 << 25)   // LED_SYS
+#define LED2        (0)
+#define LED3        (1 << 23)   // LED_USR
+#define LED_ALL     (LED1 | LED2 | LED3)
 #else
-#define PIO_LED		AT91_PIOC
-#define LED1		(1 << 8)
-#define LED2		(1 << 11)
-#define LED3		(1 << 6)
-#define LED_ALL		(LED1 | LED2 | LED3)
+#define PIO_LED     AT91_PIOC
+#define LED1        (1 << 8)
+#define LED2        (1 << 11)
+#define LED3        (1 << 6)
+#define LED_ALL     (LED1 | LED2 | LED3)
 #endif
 
 void led_init(void)
 {
-	at91_sys_write(PIO_LED+0x00, LED_ALL);
-	at91_sys_write(PIO_LED+0x10, LED_ALL);
-	at91_sys_write(PIO_LED+0x64, LED_ALL);
-	at91_sys_write(PIO_LED+0x30, LED_ALL);
+    at91_sys_write(PIO_LED+0x00, LED_ALL);
+    at91_sys_write(PIO_LED+0x10, LED_ALL);
+    at91_sys_write(PIO_LED+0x64, LED_ALL);
+    at91_sys_write(PIO_LED+0x30, LED_ALL);
 }
 
 void led_on(int num)
 {
-	switch(num)
-	{
-		case 1:
-			at91_sys_write(PIO_LED+0x34, LED1);
-			break;
-		case 2:
-			at91_sys_write(PIO_LED+0x34, LED2);
-			break;
-		case 3:
-			at91_sys_write(PIO_LED+0x34, LED3);
-			break;
-		default:
-			break;
-	}
+    switch(num)
+    {
+        case 1:
+            at91_sys_write(PIO_LED+0x34, LED1);
+            break;
+        case 2:
+            at91_sys_write(PIO_LED+0x34, LED2);
+            break;
+        case 3:
+            at91_sys_write(PIO_LED+0x34, LED3);
+            break;
+        default:
+            break;
+    }
 }
 
 void led_off(int num)
 {
-	switch(num)
-	{
-		case 1:
-			at91_sys_write(PIO_LED+0x30, LED1);
-			break;
-		case 2:
-			at91_sys_write(PIO_LED+0x30, LED2);
-			break;
-		case 3:
-			at91_sys_write(PIO_LED+0x30, LED3);
-			break;
-		default:
-			break;
-	}
+    switch(num)
+    {
+        case 1:
+            at91_sys_write(PIO_LED+0x30, LED1);
+            break;
+        case 2:
+            at91_sys_write(PIO_LED+0x30, LED2);
+            break;
+        case 3:
+            at91_sys_write(PIO_LED+0x30, LED3);
+            break;
+        default:
+            break;
+    }
 }

bsp/at91sam9260/drivers/macb.h

@@ -12,319 +12,319 @@
 #include <mii.h>
 
 /* MACB register offsets */
-#define MACB_NCR				0x0000
-#define MACB_NCFGR				0x0004
-#define MACB_NSR				0x0008
-#define MACB_TSR				0x0014
-#define MACB_RBQP				0x0018
-#define MACB_TBQP				0x001c
-#define MACB_RSR				0x0020
-#define MACB_ISR				0x0024
-#define MACB_IER				0x0028
-#define MACB_IDR				0x002c
-#define MACB_IMR				0x0030
-#define MACB_MAN				0x0034
-#define MACB_PTR				0x0038
-#define MACB_PFR				0x003c
-#define MACB_FTO				0x0040
-#define MACB_SCF				0x0044
-#define MACB_MCF				0x0048
-#define MACB_FRO				0x004c
-#define MACB_FCSE				0x0050
-#define MACB_ALE				0x0054
-#define MACB_DTF				0x0058
-#define MACB_LCOL				0x005c
-#define MACB_EXCOL				0x0060
-#define MACB_TUND				0x0064
-#define MACB_CSE				0x0068
-#define MACB_RRE				0x006c
-#define MACB_ROVR				0x0070
-#define MACB_RSE				0x0074
-#define MACB_ELE				0x0078
-#define MACB_RJA				0x007c
-#define MACB_USF				0x0080
-#define MACB_STE				0x0084
-#define MACB_RLE				0x0088
-#define MACB_TPF				0x008c
-#define MACB_HRB				0x0090
-#define MACB_HRT				0x0094
-#define MACB_SA1B				0x0098
-#define MACB_SA1T				0x009c
-#define MACB_SA2B				0x00a0
-#define MACB_SA2T				0x00a4
-#define MACB_SA3B				0x00a8
-#define MACB_SA3T				0x00ac
-#define MACB_SA4B				0x00b0
-#define MACB_SA4T				0x00b4
-#define MACB_TID				0x00b8
-#define MACB_TPQ				0x00bc
-#define MACB_USRIO				0x00c0
-#define MACB_WOL				0x00c4
+#define MACB_NCR                0x0000
+#define MACB_NCFGR              0x0004
+#define MACB_NSR                0x0008
+#define MACB_TSR                0x0014
+#define MACB_RBQP               0x0018
+#define MACB_TBQP               0x001c
+#define MACB_RSR                0x0020
+#define MACB_ISR                0x0024
+#define MACB_IER                0x0028
+#define MACB_IDR                0x002c
+#define MACB_IMR                0x0030
+#define MACB_MAN                0x0034
+#define MACB_PTR                0x0038
+#define MACB_PFR                0x003c
+#define MACB_FTO                0x0040
+#define MACB_SCF                0x0044
+#define MACB_MCF                0x0048
+#define MACB_FRO                0x004c
+#define MACB_FCSE               0x0050
+#define MACB_ALE                0x0054
+#define MACB_DTF                0x0058
+#define MACB_LCOL               0x005c
+#define MACB_EXCOL              0x0060
+#define MACB_TUND               0x0064
+#define MACB_CSE                0x0068
+#define MACB_RRE                0x006c
+#define MACB_ROVR               0x0070
+#define MACB_RSE                0x0074
+#define MACB_ELE                0x0078
+#define MACB_RJA                0x007c
+#define MACB_USF                0x0080
+#define MACB_STE                0x0084
+#define MACB_RLE                0x0088
+#define MACB_TPF                0x008c
+#define MACB_HRB                0x0090
+#define MACB_HRT                0x0094
+#define MACB_SA1B               0x0098
+#define MACB_SA1T               0x009c
+#define MACB_SA2B               0x00a0
+#define MACB_SA2T               0x00a4
+#define MACB_SA3B               0x00a8
+#define MACB_SA3T               0x00ac
+#define MACB_SA4B               0x00b0
+#define MACB_SA4T               0x00b4
+#define MACB_TID                0x00b8
+#define MACB_TPQ                0x00bc
+#define MACB_USRIO              0x00c0
+#define MACB_WOL                0x00c4
 
 /* Bitfields in NCR */
-#define MACB_LB_OFFSET				0
-#define MACB_LB_SIZE				1
-#define MACB_LLB_OFFSET				1
-#define MACB_LLB_SIZE				1
-#define MACB_RE_OFFSET				2
-#define MACB_RE_SIZE				1
-#define MACB_TE_OFFSET				3
-#define MACB_TE_SIZE				1
-#define MACB_MPE_OFFSET				4
-#define MACB_MPE_SIZE				1
-#define MACB_CLRSTAT_OFFSET			5
-#define MACB_CLRSTAT_SIZE			1
-#define MACB_INCSTAT_OFFSET			6
-#define MACB_INCSTAT_SIZE			1
-#define MACB_WESTAT_OFFSET			7
-#define MACB_WESTAT_SIZE			1
-#define MACB_BP_OFFSET				8
-#define MACB_BP_SIZE				1
-#define MACB_TSTART_OFFSET			9
-#define MACB_TSTART_SIZE			1
-#define MACB_THALT_OFFSET			10
-#define MACB_THALT_SIZE				1
-#define MACB_NCR_TPF_OFFSET			11
-#define MACB_NCR_TPF_SIZE			1
-#define MACB_TZQ_OFFSET				12
-#define MACB_TZQ_SIZE				1
+#define MACB_LB_OFFSET              0
+#define MACB_LB_SIZE                1
+#define MACB_LLB_OFFSET             1
+#define MACB_LLB_SIZE               1
+#define MACB_RE_OFFSET              2
+#define MACB_RE_SIZE                1
+#define MACB_TE_OFFSET              3
+#define MACB_TE_SIZE                1
+#define MACB_MPE_OFFSET             4
+#define MACB_MPE_SIZE               1
+#define MACB_CLRSTAT_OFFSET         5
+#define MACB_CLRSTAT_SIZE           1
+#define MACB_INCSTAT_OFFSET         6
+#define MACB_INCSTAT_SIZE           1
+#define MACB_WESTAT_OFFSET          7
+#define MACB_WESTAT_SIZE            1
+#define MACB_BP_OFFSET              8
+#define MACB_BP_SIZE                1
+#define MACB_TSTART_OFFSET          9
+#define MACB_TSTART_SIZE            1
+#define MACB_THALT_OFFSET           10
+#define MACB_THALT_SIZE             1
+#define MACB_NCR_TPF_OFFSET         11
+#define MACB_NCR_TPF_SIZE           1
+#define MACB_TZQ_OFFSET             12
+#define MACB_TZQ_SIZE               1
 
 /* Bitfields in NCFGR */
-#define MACB_SPD_OFFSET				0
-#define MACB_SPD_SIZE				1
-#define MACB_FD_OFFSET				1
-#define MACB_FD_SIZE				1
-#define MACB_BIT_RATE_OFFSET			2
-#define MACB_BIT_RATE_SIZE			1
-#define MACB_JFRAME_OFFSET			3
-#define MACB_JFRAME_SIZE			1
-#define MACB_CAF_OFFSET				4
-#define MACB_CAF_SIZE				1
-#define MACB_NBC_OFFSET				5
-#define MACB_NBC_SIZE				1
-#define MACB_NCFGR_MTI_OFFSET			6
-#define MACB_NCFGR_MTI_SIZE			1
-#define MACB_UNI_OFFSET				7
-#define MACB_UNI_SIZE				1
-#define MACB_BIG_OFFSET				8
-#define MACB_BIG_SIZE				1
-#define MACB_EAE_OFFSET				9
-#define MACB_EAE_SIZE				1
-#define MACB_CLK_OFFSET				10
-#define MACB_CLK_SIZE				2
-#define MACB_RTY_OFFSET				12
-#define MACB_RTY_SIZE				1
-#define MACB_PAE_OFFSET				13
-#define MACB_PAE_SIZE				1
-#define MACB_RBOF_OFFSET			14
-#define MACB_RBOF_SIZE				2
-#define MACB_RLCE_OFFSET			16
-#define MACB_RLCE_SIZE				1
-#define MACB_DRFCS_OFFSET			17
-#define MACB_DRFCS_SIZE				1
-#define MACB_EFRHD_OFFSET			18
-#define MACB_EFRHD_SIZE				1
-#define MACB_IRXFCS_OFFSET			19
-#define MACB_IRXFCS_SIZE			1
+#define MACB_SPD_OFFSET             0
+#define MACB_SPD_SIZE               1
+#define MACB_FD_OFFSET              1
+#define MACB_FD_SIZE                1
+#define MACB_BIT_RATE_OFFSET            2
+#define MACB_BIT_RATE_SIZE          1
+#define MACB_JFRAME_OFFSET          3
+#define MACB_JFRAME_SIZE            1
+#define MACB_CAF_OFFSET             4
+#define MACB_CAF_SIZE               1
+#define MACB_NBC_OFFSET             5
+#define MACB_NBC_SIZE               1
+#define MACB_NCFGR_MTI_OFFSET           6
+#define MACB_NCFGR_MTI_SIZE         1
+#define MACB_UNI_OFFSET             7
+#define MACB_UNI_SIZE               1
+#define MACB_BIG_OFFSET             8
+#define MACB_BIG_SIZE               1
+#define MACB_EAE_OFFSET             9
+#define MACB_EAE_SIZE               1
+#define MACB_CLK_OFFSET             10
+#define MACB_CLK_SIZE               2
+#define MACB_RTY_OFFSET             12
+#define MACB_RTY_SIZE               1
+#define MACB_PAE_OFFSET             13
+#define MACB_PAE_SIZE               1
+#define MACB_RBOF_OFFSET            14
+#define MACB_RBOF_SIZE              2
+#define MACB_RLCE_OFFSET            16
+#define MACB_RLCE_SIZE              1
+#define MACB_DRFCS_OFFSET           17
+#define MACB_DRFCS_SIZE             1
+#define MACB_EFRHD_OFFSET           18
+#define MACB_EFRHD_SIZE             1
+#define MACB_IRXFCS_OFFSET          19
+#define MACB_IRXFCS_SIZE            1
 
 /* Bitfields in NSR */
-#define MACB_NSR_LINK_OFFSET			0
-#define MACB_NSR_LINK_SIZE			1
-#define MACB_MDIO_OFFSET			1
-#define MACB_MDIO_SIZE				1
-#define MACB_IDLE_OFFSET			2
-#define MACB_IDLE_SIZE				1
+#define MACB_NSR_LINK_OFFSET            0
+#define MACB_NSR_LINK_SIZE          1
+#define MACB_MDIO_OFFSET            1
+#define MACB_MDIO_SIZE              1
+#define MACB_IDLE_OFFSET            2
+#define MACB_IDLE_SIZE              1
 
 /* Bitfields in TSR */
-#define MACB_UBR_OFFSET				0
-#define MACB_UBR_SIZE				1
-#define MACB_COL_OFFSET				1
-#define MACB_COL_SIZE				1
-#define MACB_TSR_RLE_OFFSET			2
-#define MACB_TSR_RLE_SIZE			1
-#define MACB_TGO_OFFSET				3
-#define MACB_TGO_SIZE				1
-#define MACB_BEX_OFFSET				4
-#define MACB_BEX_SIZE				1
-#define MACB_COMP_OFFSET			5
-#define MACB_COMP_SIZE				1
-#define MACB_UND_OFFSET				6
-#define MACB_UND_SIZE				1
+#define MACB_UBR_OFFSET             0
+#define MACB_UBR_SIZE               1
+#define MACB_COL_OFFSET             1
+#define MACB_COL_SIZE               1
+#define MACB_TSR_RLE_OFFSET         2
+#define MACB_TSR_RLE_SIZE           1
+#define MACB_TGO_OFFSET             3
+#define MACB_TGO_SIZE               1
+#define MACB_BEX_OFFSET             4
+#define MACB_BEX_SIZE               1
+#define MACB_COMP_OFFSET            5
+#define MACB_COMP_SIZE              1
+#define MACB_UND_OFFSET             6
+#define MACB_UND_SIZE               1
 
 /* Bitfields in RSR */
-#define MACB_BNA_OFFSET				0
-#define MACB_BNA_SIZE				1
-#define MACB_REC_OFFSET				1
-#define MACB_REC_SIZE				1
-#define MACB_OVR_OFFSET				2
-#define MACB_OVR_SIZE				1
+#define MACB_BNA_OFFSET             0
+#define MACB_BNA_SIZE               1
+#define MACB_REC_OFFSET             1
+#define MACB_REC_SIZE               1
+#define MACB_OVR_OFFSET             2
+#define MACB_OVR_SIZE               1
 
 /* Bitfields in ISR/IER/IDR/IMR */
-#define MACB_MFD_OFFSET				0
-#define MACB_MFD_SIZE				1
-#define MACB_RCOMP_OFFSET			1
-#define MACB_RCOMP_SIZE				1
-#define MACB_RXUBR_OFFSET			2
-#define MACB_RXUBR_SIZE				1
-#define MACB_TXUBR_OFFSET			3
-#define MACB_TXUBR_SIZE				1
-#define MACB_ISR_TUND_OFFSET			4
-#define MACB_ISR_TUND_SIZE			1
-#define MACB_ISR_RLE_OFFSET			5
-#define MACB_ISR_RLE_SIZE			1
-#define MACB_TXERR_OFFSET			6
-#define MACB_TXERR_SIZE				1
-#define MACB_TCOMP_OFFSET			7
-#define MACB_TCOMP_SIZE				1
-#define MACB_ISR_LINK_OFFSET			9
-#define MACB_ISR_LINK_SIZE			1
-#define MACB_ISR_ROVR_OFFSET			10
-#define MACB_ISR_ROVR_SIZE			1
-#define MACB_HRESP_OFFSET			11
-#define MACB_HRESP_SIZE				1
-#define MACB_PFR_OFFSET				12
-#define MACB_PFR_SIZE				1
-#define MACB_PTZ_OFFSET				13
-#define MACB_PTZ_SIZE				1
+#define MACB_MFD_OFFSET             0
+#define MACB_MFD_SIZE               1
+#define MACB_RCOMP_OFFSET           1
+#define MACB_RCOMP_SIZE             1
+#define MACB_RXUBR_OFFSET           2
+#define MACB_RXUBR_SIZE             1
+#define MACB_TXUBR_OFFSET           3
+#define MACB_TXUBR_SIZE             1
+#define MACB_ISR_TUND_OFFSET            4
+#define MACB_ISR_TUND_SIZE          1
+#define MACB_ISR_RLE_OFFSET         5
+#define MACB_ISR_RLE_SIZE           1
+#define MACB_TXERR_OFFSET           6
+#define MACB_TXERR_SIZE             1
+#define MACB_TCOMP_OFFSET           7
+#define MACB_TCOMP_SIZE             1
+#define MACB_ISR_LINK_OFFSET            9
+#define MACB_ISR_LINK_SIZE          1
+#define MACB_ISR_ROVR_OFFSET            10
+#define MACB_ISR_ROVR_SIZE          1
+#define MACB_HRESP_OFFSET           11
+#define MACB_HRESP_SIZE             1
+#define MACB_PFR_OFFSET             12
+#define MACB_PFR_SIZE               1
+#define MACB_PTZ_OFFSET             13
+#define MACB_PTZ_SIZE               1
 
 /* Bitfields in MAN */
-#define MACB_DATA_OFFSET			0
-#define MACB_DATA_SIZE				16
-#define MACB_CODE_OFFSET			16
-#define MACB_CODE_SIZE				2
-#define MACB_REGA_OFFSET			18
-#define MACB_REGA_SIZE				5
-#define MACB_PHYA_OFFSET			23
-#define MACB_PHYA_SIZE				5
-#define MACB_RW_OFFSET				28
-#define MACB_RW_SIZE				2
-#define MACB_SOF_OFFSET				30
-#define MACB_SOF_SIZE				2
+#define MACB_DATA_OFFSET            0
+#define MACB_DATA_SIZE              16
+#define MACB_CODE_OFFSET            16
+#define MACB_CODE_SIZE              2
+#define MACB_REGA_OFFSET            18
+#define MACB_REGA_SIZE              5
+#define MACB_PHYA_OFFSET            23
+#define MACB_PHYA_SIZE              5
+#define MACB_RW_OFFSET              28
+#define MACB_RW_SIZE                2
+#define MACB_SOF_OFFSET             30
+#define MACB_SOF_SIZE               2
 
 /* Bitfields in USRIO (AVR32) */
-#define MACB_MII_OFFSET				0
-#define MACB_MII_SIZE				1
-#define MACB_EAM_OFFSET				1
-#define MACB_EAM_SIZE				1
-#define MACB_TX_PAUSE_OFFSET			2
-#define MACB_TX_PAUSE_SIZE			1
-#define MACB_TX_PAUSE_ZERO_OFFSET		3
-#define MACB_TX_PAUSE_ZERO_SIZE			1
+#define MACB_MII_OFFSET             0
+#define MACB_MII_SIZE               1
+#define MACB_EAM_OFFSET             1
+#define MACB_EAM_SIZE               1
+#define MACB_TX_PAUSE_OFFSET            2
+#define MACB_TX_PAUSE_SIZE          1
+#define MACB_TX_PAUSE_ZERO_OFFSET       3
+#define MACB_TX_PAUSE_ZERO_SIZE         1
 
 /* Bitfields in USRIO (AT91) */
-#define MACB_RMII_OFFSET			0
-#define MACB_RMII_SIZE				1
-#define MACB_CLKEN_OFFSET			1
-#define MACB_CLKEN_SIZE				1
+#define MACB_RMII_OFFSET            0
+#define MACB_RMII_SIZE              1
+#define MACB_CLKEN_OFFSET           1
+#define MACB_CLKEN_SIZE             1
 
 /* Bitfields in WOL */
-#define MACB_IP_OFFSET				0
-#define MACB_IP_SIZE				16
-#define MACB_MAG_OFFSET				16
-#define MACB_MAG_SIZE				1
-#define MACB_ARP_OFFSET				17
-#define MACB_ARP_SIZE				1
-#define MACB_SA1_OFFSET				18
-#define MACB_SA1_SIZE				1
-#define MACB_WOL_MTI_OFFSET			19
-#define MACB_WOL_MTI_SIZE			1
+#define MACB_IP_OFFSET              0
+#define MACB_IP_SIZE                16
+#define MACB_MAG_OFFSET             16
+#define MACB_MAG_SIZE               1
+#define MACB_ARP_OFFSET             17
+#define MACB_ARP_SIZE               1
+#define MACB_SA1_OFFSET             18
+#define MACB_SA1_SIZE               1
+#define MACB_WOL_MTI_OFFSET         19
+#define MACB_WOL_MTI_SIZE           1
 
 /* Constants for CLK */
-#define MACB_CLK_DIV8				0
-#define MACB_CLK_DIV16				1
-#define MACB_CLK_DIV32				2
-#define MACB_CLK_DIV64				3
+#define MACB_CLK_DIV8               0
+#define MACB_CLK_DIV16              1
+#define MACB_CLK_DIV32              2
+#define MACB_CLK_DIV64              3
 
 /* Constants for MAN register */
-#define MACB_MAN_SOF				1
-#define MACB_MAN_WRITE				1
-#define MACB_MAN_READ				2
-#define MACB_MAN_CODE				2
+#define MACB_MAN_SOF                1
+#define MACB_MAN_WRITE              1
+#define MACB_MAN_READ               2
+#define MACB_MAN_CODE               2
 
 /* Bit manipulation macros */
-#define MACB_BIT(name)					\
-	(1 << MACB_##name##_OFFSET)
-#define MACB_BF(name,value)				\
-	(((value) & ((1 << MACB_##name##_SIZE) - 1))	\
-	 << MACB_##name##_OFFSET)
+#define MACB_BIT(name)                  \
+    (1 << MACB_##name##_OFFSET)
+#define MACB_BF(name,value)             \
+    (((value) & ((1 << MACB_##name##_SIZE) - 1))    \
+     << MACB_##name##_OFFSET)
 #define MACB_BFEXT(name,value)\
-	(((value) >> MACB_##name##_OFFSET)		\
-	 & ((1 << MACB_##name##_SIZE) - 1))
-#define MACB_BFINS(name,value,old)			\
-	(((old) & ~(((1 << MACB_##name##_SIZE) - 1)	\
-		    << MACB_##name##_OFFSET))		\
-	 | MACB_BF(name,value))
+    (((value) >> MACB_##name##_OFFSET)      \
+     & ((1 << MACB_##name##_SIZE) - 1))
+#define MACB_BFINS(name,value,old)          \
+    (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
+            << MACB_##name##_OFFSET))       \
+     | MACB_BF(name,value))
 
 /* Register access macros */
-#define macb_readl(port,reg)				\
-	readl((port)->regs + MACB_##reg)
-#define macb_writel(port,reg,value)			\
-	writel((value), (port)->regs + MACB_##reg)
+#define macb_readl(port,reg)                \
+    readl((port)->regs + MACB_##reg)
+#define macb_writel(port,reg,value)         \
+    writel((value), (port)->regs + MACB_##reg)
 
 struct dma_desc {
-	rt_uint32_t	addr;
-	rt_uint32_t	ctrl;
+    rt_uint32_t addr;
+    rt_uint32_t ctrl;
 };
 
 /* DMA descriptor bitfields */
-#define MACB_RX_USED_OFFSET			0
-#define MACB_RX_USED_SIZE			1
-#define MACB_RX_WRAP_OFFSET			1
-#define MACB_RX_WRAP_SIZE			1
-#define MACB_RX_WADDR_OFFSET			2
-#define MACB_RX_WADDR_SIZE			30
+#define MACB_RX_USED_OFFSET         0
+#define MACB_RX_USED_SIZE           1
+#define MACB_RX_WRAP_OFFSET         1
+#define MACB_RX_WRAP_SIZE           1
+#define MACB_RX_WADDR_OFFSET            2
+#define MACB_RX_WADDR_SIZE          30
 
-#define MACB_RX_FRMLEN_OFFSET			0
-#define MACB_RX_FRMLEN_SIZE			12
-#define MACB_RX_OFFSET_OFFSET			12
-#define MACB_RX_OFFSET_SIZE			2
-#define MACB_RX_SOF_OFFSET			14
-#define MACB_RX_SOF_SIZE			1
-#define MACB_RX_EOF_OFFSET			15
-#define MACB_RX_EOF_SIZE			1
-#define MACB_RX_CFI_OFFSET			16
-#define MACB_RX_CFI_SIZE			1
-#define MACB_RX_VLAN_PRI_OFFSET			17
-#define MACB_RX_VLAN_PRI_SIZE			3
-#define MACB_RX_PRI_TAG_OFFSET			20
-#define MACB_RX_PRI_TAG_SIZE			1
-#define MACB_RX_VLAN_TAG_OFFSET			21
-#define MACB_RX_VLAN_TAG_SIZE			1
-#define MACB_RX_TYPEID_MATCH_OFFSET		22
-#define MACB_RX_TYPEID_MATCH_SIZE		1
-#define MACB_RX_SA4_MATCH_OFFSET		23
-#define MACB_RX_SA4_MATCH_SIZE			1
-#define MACB_RX_SA3_MATCH_OFFSET		24
-#define MACB_RX_SA3_MATCH_SIZE			1
-#define MACB_RX_SA2_MATCH_OFFSET		25
-#define MACB_RX_SA2_MATCH_SIZE			1
-#define MACB_RX_SA1_MATCH_OFFSET		26
-#define MACB_RX_SA1_MATCH_SIZE			1
-#define MACB_RX_EXT_MATCH_OFFSET		28
-#define MACB_RX_EXT_MATCH_SIZE			1
-#define MACB_RX_UHASH_MATCH_OFFSET		29
-#define MACB_RX_UHASH_MATCH_SIZE		1
-#define MACB_RX_MHASH_MATCH_OFFSET		30
-#define MACB_RX_MHASH_MATCH_SIZE		1
-#define MACB_RX_BROADCAST_OFFSET		31
-#define MACB_RX_BROADCAST_SIZE			1
+#define MACB_RX_FRMLEN_OFFSET           0
+#define MACB_RX_FRMLEN_SIZE         12
+#define MACB_RX_OFFSET_OFFSET           12
+#define MACB_RX_OFFSET_SIZE         2
+#define MACB_RX_SOF_OFFSET          14
+#define MACB_RX_SOF_SIZE            1
+#define MACB_RX_EOF_OFFSET          15
+#define MACB_RX_EOF_SIZE            1
+#define MACB_RX_CFI_OFFSET          16
+#define MACB_RX_CFI_SIZE            1
+#define MACB_RX_VLAN_PRI_OFFSET         17
+#define MACB_RX_VLAN_PRI_SIZE           3
+#define MACB_RX_PRI_TAG_OFFSET          20
+#define MACB_RX_PRI_TAG_SIZE            1
+#define MACB_RX_VLAN_TAG_OFFSET         21
+#define MACB_RX_VLAN_TAG_SIZE           1
+#define MACB_RX_TYPEID_MATCH_OFFSET     22
+#define MACB_RX_TYPEID_MATCH_SIZE       1
+#define MACB_RX_SA4_MATCH_OFFSET        23
+#define MACB_RX_SA4_MATCH_SIZE          1
+#define MACB_RX_SA3_MATCH_OFFSET        24
+#define MACB_RX_SA3_MATCH_SIZE          1
+#define MACB_RX_SA2_MATCH_OFFSET        25
+#define MACB_RX_SA2_MATCH_SIZE          1
+#define MACB_RX_SA1_MATCH_OFFSET        26
+#define MACB_RX_SA1_MATCH_SIZE          1
+#define MACB_RX_EXT_MATCH_OFFSET        28
+#define MACB_RX_EXT_MATCH_SIZE          1
+#define MACB_RX_UHASH_MATCH_OFFSET      29
+#define MACB_RX_UHASH_MATCH_SIZE        1
+#define MACB_RX_MHASH_MATCH_OFFSET      30
+#define MACB_RX_MHASH_MATCH_SIZE        1
+#define MACB_RX_BROADCAST_OFFSET        31
+#define MACB_RX_BROADCAST_SIZE          1
 
-#define MACB_TX_FRMLEN_OFFSET			0
-#define MACB_TX_FRMLEN_SIZE			11
-#define MACB_TX_LAST_OFFSET			15
-#define MACB_TX_LAST_SIZE			1
-#define MACB_TX_NOCRC_OFFSET			16
-#define MACB_TX_NOCRC_SIZE			1
-#define MACB_TX_BUF_EXHAUSTED_OFFSET		27
-#define MACB_TX_BUF_EXHAUSTED_SIZE		1
-#define MACB_TX_UNDERRUN_OFFSET			28
-#define MACB_TX_UNDERRUN_SIZE			1
-#define MACB_TX_ERROR_OFFSET			29
-#define MACB_TX_ERROR_SIZE			1
-#define MACB_TX_WRAP_OFFSET			30
-#define MACB_TX_WRAP_SIZE			1
-#define MACB_TX_USED_OFFSET			31
-#define MACB_TX_USED_SIZE			1
+#define MACB_TX_FRMLEN_OFFSET           0
+#define MACB_TX_FRMLEN_SIZE         11
+#define MACB_TX_LAST_OFFSET         15
+#define MACB_TX_LAST_SIZE           1
+#define MACB_TX_NOCRC_OFFSET            16
+#define MACB_TX_NOCRC_SIZE          1
+#define MACB_TX_BUF_EXHAUSTED_OFFSET        27
+#define MACB_TX_BUF_EXHAUSTED_SIZE      1
+#define MACB_TX_UNDERRUN_OFFSET         28
+#define MACB_TX_UNDERRUN_SIZE           1
+#define MACB_TX_ERROR_OFFSET            29
+#define MACB_TX_ERROR_SIZE          1
+#define MACB_TX_WRAP_OFFSET         30
+#define MACB_TX_WRAP_SIZE           1
+#define MACB_TX_USED_OFFSET         31
+#define MACB_TX_USED_SIZE           1
 
 extern int rt_hw_macb_init();
 

bsp/at91sam9260/drivers/mii.h

@@ -22,7 +22,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS     0x0f    /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -37,7 +37,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000      0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -56,7 +56,7 @@
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_ESTATEN        0x0100  /* Extended Status in R15 */
 #define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
 #define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
@@ -85,7 +85,7 @@
 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 
 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
+            ADVERTISE_CSMA)
 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 
@@ -107,8 +107,8 @@
 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 #define LPA_NPAGE               0x8000  /* Next page bit               */
 
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
+#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
 /* Expansion register for auto-negotiation. */
 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
@@ -118,8 +118,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -137,8 +137,8 @@
 #define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
 
 /* Flow control flags */
-#define FLOW_CTRL_TX		0x01
-#define FLOW_CTRL_RX		0x02
+#define FLOW_CTRL_TX        0x01
+#define FLOW_CTRL_RX        0x02
 
 /**
  * mii_nway_result

bsp/at91sam9260/drivers/usart.c

@@ -14,54 +14,54 @@
 #include <at91sam926x.h>
 #include <rtdevice.h>
 
-#define RXRDY			0x01
-#define TXRDY			(1 << 1)
+#define RXRDY           0x01
+#define TXRDY           (1 << 1)
 
 typedef struct uartport
 {
-	volatile rt_uint32_t CR;
-	volatile rt_uint32_t MR;
-	volatile rt_uint32_t IER;
-	volatile rt_uint32_t IDR;
-	volatile rt_uint32_t IMR;
-	volatile rt_uint32_t CSR;
-	volatile rt_uint32_t RHR;
-	volatile rt_uint32_t THR;
-	volatile rt_uint32_t BRGR;
-	volatile rt_uint32_t RTOR;
-	volatile rt_uint32_t TTGR;
-	volatile rt_uint32_t reserved0[5];
-	volatile rt_uint32_t FIDI;
-	volatile rt_uint32_t NER;
-	volatile rt_uint32_t reserved1;
-	volatile rt_uint32_t IFR;
-	volatile rt_uint32_t reserved2[44];
-	volatile rt_uint32_t RPR;
-	volatile rt_uint32_t RCR;
-	volatile rt_uint32_t TPR;
-	volatile rt_uint32_t TCR;
-	volatile rt_uint32_t RNPR;
-	volatile rt_uint32_t RNCR;
-	volatile rt_uint32_t TNPR;
-	volatile rt_uint32_t TNCR;
-	volatile rt_uint32_t PTCR;
-	volatile rt_uint32_t PTSR;
+    volatile rt_uint32_t CR;
+    volatile rt_uint32_t MR;
+    volatile rt_uint32_t IER;
+    volatile rt_uint32_t IDR;
+    volatile rt_uint32_t IMR;
+    volatile rt_uint32_t CSR;
+    volatile rt_uint32_t RHR;
+    volatile rt_uint32_t THR;
+    volatile rt_uint32_t BRGR;
+    volatile rt_uint32_t RTOR;
+    volatile rt_uint32_t TTGR;
+    volatile rt_uint32_t reserved0[5];
+    volatile rt_uint32_t FIDI;
+    volatile rt_uint32_t NER;
+    volatile rt_uint32_t reserved1;
+    volatile rt_uint32_t IFR;
+    volatile rt_uint32_t reserved2[44];
+    volatile rt_uint32_t RPR;
+    volatile rt_uint32_t RCR;
+    volatile rt_uint32_t TPR;
+    volatile rt_uint32_t TCR;
+    volatile rt_uint32_t RNPR;
+    volatile rt_uint32_t RNCR;
+    volatile rt_uint32_t TNPR;
+    volatile rt_uint32_t TNCR;
+    volatile rt_uint32_t PTCR;
+    volatile rt_uint32_t PTSR;
 }uartport;
 
 #define CIDR FIDI
 #define EXID NER
 #define FNR  reserved1
 
-#define DBGU	((struct uartport *)AT91SAM9260_BASE_DBGU)
+#define DBGU    ((struct uartport *)AT91SAM9260_BASE_DBGU)
 
-#define UART0	((struct uartport *)AT91SAM9260_BASE_US0)
-#define UART1	((struct uartport *)AT91SAM9260_BASE_US1)
-#define UART2	((struct uartport *)AT91SAM9260_BASE_US2)
-#define UART3	((struct uartport *)AT91SAM9260_BASE_US3)
+#define UART0   ((struct uartport *)AT91SAM9260_BASE_US0)
+#define UART1   ((struct uartport *)AT91SAM9260_BASE_US1)
+#define UART2   ((struct uartport *)AT91SAM9260_BASE_US2)
+#define UART3   ((struct uartport *)AT91SAM9260_BASE_US3)
 
 struct at91_uart {
-	uartport *port;
-	int irq;
+    uartport *port;
+    int irq;
 };
 
 
@@ -71,18 +71,18 @@ struct at91_uart {
  */
 void rt_at91_usart_handler(int vector, void *param)
 {
-	int status;
-	struct at91_uart *uart;
-	rt_device_t dev = (rt_device_t)param;
-	uart = (struct at91_uart *)dev->user_data;
-	status = uart->port->CSR;
-	if (!(status & uart->port->IMR))
-	{
-		return;
-	}
-	rt_interrupt_enter();
-	rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
-	rt_interrupt_leave();
+    int status;
+    struct at91_uart *uart;
+    rt_device_t dev = (rt_device_t)param;
+    uart = (struct at91_uart *)dev->user_data;
+    status = uart->port->CSR;
+    if (!(status & uart->port->IMR))
+    {
+        return;
+    }
+    rt_interrupt_enter();
+    rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
+    rt_interrupt_leave();
 }
 
 /**
@@ -91,67 +91,67 @@ void rt_at91_usart_handler(int vector, void *param)
 static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
                                 struct serial_configure *cfg)
 {
-	int div;
-	int mode = 0;
-	struct at91_uart *uart;
+    int div;
+    int mode = 0;
+    struct at91_uart *uart;
 
-	RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial != RT_NULL);
     RT_ASSERT(cfg != RT_NULL);
-	uart = (struct at91_uart *)serial->parent.user_data;
-
-	uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX | 
-	       AT91_US_RXDIS | AT91_US_TXDIS;
-	mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK | 
-		AT91_US_CHMODE_NORMAL;
-	switch (cfg->data_bits)
-	{
-	case DATA_BITS_8:
-		mode |= AT91_US_CHRL_8;
-		break;
-	case DATA_BITS_7:
-		mode |= AT91_US_CHRL_7;
-		break;
-	case DATA_BITS_6:
-		mode |= AT91_US_CHRL_6;
-		break;
-	case DATA_BITS_5:
-		mode |= AT91_US_CHRL_5;
-		break;
-	default:
-		mode |= AT91_US_CHRL_8;
-		break;
-	}
-
-	switch (cfg->stop_bits)
-	{
-	case STOP_BITS_2:
-		mode |= AT91_US_NBSTOP_2;
-		break;
-	case STOP_BITS_1:
-	default:
-		mode |= AT91_US_NBSTOP_1;
-		break;
-	}
-
-	switch (cfg->parity)
-	{
-	case PARITY_ODD:
-		mode |= AT91_US_PAR_ODD;
-		break;
-	case PARITY_EVEN:
-		mode |= AT91_US_PAR_EVEN;
-		break;
-	case PARITY_NONE:
-	default:
-		mode |= AT91_US_PAR_NONE;
-		break;
-	}
-
-	uart->port->MR = mode;
-	div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
-	uart->port->BRGR = div;
-	uart->port->CR = AT91_US_RXEN | AT91_US_TXEN;
-	uart->port->IER = 0x01;
+    uart = (struct at91_uart *)serial->parent.user_data;
+
+    uart->port->CR = AT91_US_RSTTX | AT91_US_RSTRX |
+           AT91_US_RXDIS | AT91_US_TXDIS;
+    mode |= AT91_US_USMODE_NORMAL | AT91_US_USCLKS_MCK |
+        AT91_US_CHMODE_NORMAL;
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        mode |= AT91_US_CHRL_8;
+        break;
+    case DATA_BITS_7:
+        mode |= AT91_US_CHRL_7;
+        break;
+    case DATA_BITS_6:
+        mode |= AT91_US_CHRL_6;
+        break;
+    case DATA_BITS_5:
+        mode |= AT91_US_CHRL_5;
+        break;
+    default:
+        mode |= AT91_US_CHRL_8;
+        break;
+    }
+
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_2:
+        mode |= AT91_US_NBSTOP_2;
+        break;
+    case STOP_BITS_1:
+    default:
+        mode |= AT91_US_NBSTOP_1;
+        break;
+    }
+
+    switch (cfg->parity)
+    {
+    case PARITY_ODD:
+        mode |= AT91_US_PAR_ODD;
+        break;
+    case PARITY_EVEN:
+        mode |= AT91_US_PAR_EVEN;
+        break;
+    case PARITY_NONE:
+    default:
+        mode |= AT91_US_PAR_NONE;
+        break;
+    }
+
+    uart->port->MR = mode;
+    div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
+    uart->port->BRGR = div;
+    uart->port->CR = AT91_US_RXEN | AT91_US_TXEN;
+    uart->port->IER = 0x01;
 
     return RT_EOK;
 }
@@ -168,11 +168,11 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
     {
     case RT_DEVICE_CTRL_CLR_INT:
         /* disable rx irq */
-		rt_hw_interrupt_mask(uart->irq);
+        rt_hw_interrupt_mask(uart->irq);
         break;
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-		rt_hw_interrupt_umask(uart->irq);
+        rt_hw_interrupt_umask(uart->irq);
         break;
     }
 
@@ -182,10 +182,10 @@ static rt_err_t at91_usart_control(struct rt_serial_device *serial,
 static int at91_usart_putc(struct rt_serial_device *serial, char c)
 {
     rt_uint32_t level;
-	struct at91_uart *uart = serial->parent.user_data;
+    struct at91_uart *uart = serial->parent.user_data;
 
     while (!(uart->port->CSR & TXRDY));
-	uart->port->THR = c;
+    uart->port->THR = c;
 
     return 1;
 }
@@ -193,16 +193,16 @@ static int at91_usart_putc(struct rt_serial_device *serial, char c)
 static int at91_usart_getc(struct rt_serial_device *serial)
 {
     int result;
-	struct at91_uart *uart = serial->parent.user_data;
+    struct at91_uart *uart = serial->parent.user_data;
 
     if (uart->port->CSR & RXRDY)
-	{
-		result = uart->port->RHR & 0xff;
-	}
-	else
-	{
-		result = -1;
-	}
+    {
+        result = uart->port->RHR & 0xff;
+    }
+    else
+    {
+        result = -1;
+    }
 
     return result;
 }
@@ -218,8 +218,8 @@ static const struct rt_uart_ops at91_usart_ops =
 #if defined(RT_USING_DBGU)
 static struct rt_serial_device serial_dbgu;
 struct at91_uart dbgu = {
-	DBGU,
-	AT91_ID_SYS
+    DBGU,
+    AT91_ID_SYS
 };
 
 #endif
@@ -227,82 +227,82 @@ struct at91_uart dbgu = {
 #if defined(RT_USING_UART0)
 static struct rt_serial_device serial0;
 struct at91_uart uart0 = {
-	UART0,
-	AT91SAM9260_ID_US0
+    UART0,
+    AT91SAM9260_ID_US0
 };
 #endif
 
 #if defined(RT_USING_UART1)
 static struct rt_serial_device serial1;
 struct at91_uart uart1 = {
-	UART1,
-	AT91SAM9260_ID_US1
+    UART1,
+    AT91SAM9260_ID_US1
 };
 #endif
 
 #if defined(RT_USING_UART2)
 static struct rt_serial_device serial2;
 struct at91_uart uart2 = {
-	UART2,
-	AT91SAM9260_ID_US2
+    UART2,
+    AT91SAM9260_ID_US2
 };
 #endif
 
 #if defined(RT_USING_UART3)
 static struct rt_serial_device serial3;
 struct at91_uart uart3 = {
-	UART3,
-	AT91SAM9260_ID_US3
+    UART3,
+    AT91SAM9260_ID_US3
 };
 #endif
 
 void at91_usart_gpio_init(void)
 {
-	rt_uint32_t val;
+    rt_uint32_t val;
 
 #ifdef RT_USING_DBGU
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
-	//at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<14)|(1<<15));
+    //at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<14)|(1<<15));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<14)|(1<<15));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<14)|(1<<15));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
 #endif
 
 #ifdef RT_USING_UART0
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<4)|(1<<5));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<4));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<5));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<4)|(1<<5));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<4)|(1<<5));
 #endif
 
 #ifdef RT_USING_UART1
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<6)|(1<<7));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<6));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<7));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<6)|(1<<7));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<6)|(1<<7));
 #endif
 
 #ifdef RT_USING_UART2
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9));
+    at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<8)|(1<<9));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<8));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<9));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<8)|(1<<9));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<8)|(1<<9));
 #endif
 
 #ifdef RT_USING_UART3
-	at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
-	at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11));
-	at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10));
-	at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11));
-	at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11));
-	at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11));
+    at91_sys_write(AT91_PMC_PCER, 1<<AT91SAM9260_ID_US3);
+    at91_sys_write(AT91_PIOB + PIO_IDR, (1<<10)|(1<<11));
+    at91_sys_write(AT91_PIOB + PIO_PUER, (1<<10));
+    at91_sys_write(AT91_PIOB + PIO_PUDR, (1<<11));
+    at91_sys_write(AT91_PIOB + PIO_ASR, (1<<10)|(1<<11));
+    at91_sys_write(AT91_PIOB + PIO_PDR, (1<<10)|(1<<11));
 #endif
 }
 
@@ -314,17 +314,17 @@ void at91_usart_gpio_init(void)
  */
 int rt_hw_uart_init(void)
 {
-	at91_usart_gpio_init();
+    at91_usart_gpio_init();
 
 #if defined(RT_USING_DBGU)
-	serial_dbgu.ops = &at91_usart_ops;
-	serial_dbgu.config.baud_rate = BAUD_RATE_115200;
+    serial_dbgu.ops = &at91_usart_ops;
+    serial_dbgu.config.baud_rate = BAUD_RATE_115200;
     serial_dbgu.config.bit_order = BIT_ORDER_LSB;
     serial_dbgu.config.data_bits = DATA_BITS_8;
     serial_dbgu.config.parity = PARITY_NONE;
     serial_dbgu.config.stop_bits = STOP_BITS_1;
     serial_dbgu.config.invert = NRZ_NORMAL;
-	serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial_dbgu, "dbgu",
@@ -333,83 +333,83 @@ int rt_hw_uart_init(void)
 #endif
 
 #if defined(RT_USING_UART0)
-	serial0.ops = &at91_usart_ops;
-	serial0.config.baud_rate = BAUD_RATE_115200;
+    serial0.ops = &at91_usart_ops;
+    serial0.config.baud_rate = BAUD_RATE_115200;
     serial0.config.bit_order = BIT_ORDER_LSB;
     serial0.config.data_bits = DATA_BITS_8;
     serial0.config.parity = PARITY_NONE;
     serial0.config.stop_bits = STOP_BITS_1;
     serial0.config.invert = NRZ_NORMAL;
-	serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           &uart0);
-	rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler, 
-							(void *)&(serial0.parent), "UART0");
-	rt_hw_interrupt_umask(uart0.irq);
+    rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
+                            (void *)&(serial0.parent), "UART0");
+    rt_hw_interrupt_umask(uart0.irq);
 #endif
 
 #if defined(RT_USING_UART1)
-	serial1.ops = &at91_usart_ops;
+    serial1.ops = &at91_usart_ops;
     serial1.int_rx = &uart1_int_rx;
-	serial1.config.baud_rate = BAUD_RATE_115200;
+    serial1.config.baud_rate = BAUD_RATE_115200;
     serial1.config.bit_order = BIT_ORDER_LSB;
     serial1.config.data_bits = DATA_BITS_8;
     serial1.config.parity = PARITY_NONE;
     serial1.config.stop_bits = STOP_BITS_1;
     serial1.config.invert = NRZ_NORMAL;
-	serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial1, "uart1",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart1);
-	rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler, 
-							(void *)&(serial1.parent), "UART1");
-	rt_hw_interrupt_umask(uart1.irq);
+    rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
+                            (void *)&(serial1.parent), "UART1");
+    rt_hw_interrupt_umask(uart1.irq);
 #endif
 
 #if defined(RT_USING_UART2)
-	serial2.ops = &at91_usart_ops;
-	serial2.config.baud_rate = BAUD_RATE_115200;
+    serial2.ops = &at91_usart_ops;
+    serial2.config.baud_rate = BAUD_RATE_115200;
     serial2.config.bit_order = BIT_ORDER_LSB;
     serial2.config.data_bits = DATA_BITS_8;
     serial2.config.parity = PARITY_NONE;
     serial2.config.stop_bits = STOP_BITS_1;
     serial2.config.invert = NRZ_NORMAL;
-	serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial2, "uart2",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart2);
-	rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler, 
-							(void *)&(serial2.parent), "UART2");
-	rt_hw_interrupt_umask(uart2.irq);
+    rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
+                            (void *)&(serial2.parent), "UART2");
+    rt_hw_interrupt_umask(uart2.irq);
 #endif
 
 #if defined(RT_USING_UART3)
-	serial3.ops = &at91_usart_ops;
-	serial3.config.baud_rate = BAUD_RATE_115200;
+    serial3.ops = &at91_usart_ops;
+    serial3.config.baud_rate = BAUD_RATE_115200;
     serial3.config.bit_order = BIT_ORDER_LSB;
     serial3.config.data_bits = DATA_BITS_8;
     serial3.config.parity = PARITY_NONE;
     serial3.config.stop_bits = STOP_BITS_1;
     serial3.config.invert = NRZ_NORMAL;
-	serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&serial3, "uart3",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           &uart3);
-	rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler, 
-							(void *)&(serial3.parent), "UART3");
-	rt_hw_interrupt_umask(uart3.irq);
+    rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
+                            (void *)&(serial3.parent), "UART3");
+    rt_hw_interrupt_umask(uart3.irq);
 #endif
 
-	return 0;
+    return 0;
 }
 
 INIT_BOARD_EXPORT(rt_hw_uart_init);
@@ -417,7 +417,7 @@ INIT_BOARD_EXPORT(rt_hw_uart_init);
 #ifdef RT_USING_DBGU
 void rt_dbgu_isr(void)
 {
-	rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
+    rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
 }
 #endif
 

bsp/at91sam9260/platform/at91_aic.h

@@ -15,41 +15,41 @@
 extern "C" {
 #endif
 
-#define AIC_IRQS	32
-
-#define AT91_AIC_SMR(n)		(AT91_AIC + ((n) * 4))	/* Source Mode Registers 0-31 */
-#define		AT91_AIC_PRIOR		(7 << 0)		/* Priority Level */
-#define		AT91_AIC_SRCTYPE	(3 << 5)		/* Interrupt Source Type */
-#define			AT91_AIC_SRCTYPE_LOW		(0 << 5)
-#define			AT91_AIC_SRCTYPE_FALLING	(1 << 5)
-#define			AT91_AIC_SRCTYPE_HIGH		(2 << 5)
-#define			AT91_AIC_SRCTYPE_RISING		(3 << 5)
-
-#define AT91_AIC_SVR(n)		(AT91_AIC + 0x80 + ((n) * 4))	/* Source Vector Registers 0-31 */
-#define AT91_AIC_IVR		(AT91_AIC + 0x100)	/* Interrupt Vector Register */
-#define AT91_AIC_FVR		(AT91_AIC + 0x104)	/* Fast Interrupt Vector Register */
-#define AT91_AIC_ISR		(AT91_AIC + 0x108)	/* Interrupt Status Register */
-#define		AT91_AIC_IRQID		(0x1f << 0)		/* Current Interrupt Identifier */
-
-#define AT91_AIC_IPR		(AT91_AIC + 0x10c)	/* Interrupt Pending Register */
-#define AT91_AIC_IMR		(AT91_AIC + 0x110)	/* Interrupt Mask Register */
-#define AT91_AIC_CISR		(AT91_AIC + 0x114)	/* Core Interrupt Status Register */
-#define		AT91_AIC_NFIQ		(1 << 0)		/* nFIQ Status */
-#define		AT91_AIC_NIRQ		(1 << 1)		/* nIRQ Status */
-
-#define AT91_AIC_IECR		(AT91_AIC + 0x120)	/* Interrupt Enable Command Register */
-#define AT91_AIC_IDCR		(AT91_AIC + 0x124)	/* Interrupt Disable Command Register */
-#define AT91_AIC_ICCR		(AT91_AIC + 0x128)	/* Interrupt Clear Command Register */
-#define AT91_AIC_ISCR		(AT91_AIC + 0x12c)	/* Interrupt Set Command Register */
-#define AT91_AIC_EOICR		(AT91_AIC + 0x130)	/* End of Interrupt Command Register */
-#define AT91_AIC_SPU		(AT91_AIC + 0x134)	/* Spurious Interrupt Vector Register */
-#define AT91_AIC_DCR		(AT91_AIC + 0x138)	/* Debug Control Register */
-#define		AT91_AIC_DCR_PROT	(1 << 0)		/* Protection Mode */
-#define		AT91_AIC_DCR_GMSK	(1 << 1)		/* General Mask */
-
-#define AT91_AIC_FFER		(AT91_AIC + 0x140)	/* Fast Forcing Enable Register [SAM9 only] */
-#define AT91_AIC_FFDR		(AT91_AIC + 0x144)	/* Fast Forcing Disable Register [SAM9 only] */
-#define AT91_AIC_FFSR		(AT91_AIC + 0x148)	/* Fast Forcing Status Register [SAM9 only] */
+#define AIC_IRQS    32
+
+#define AT91_AIC_SMR(n)     (AT91_AIC + ((n) * 4))  /* Source Mode Registers 0-31 */
+#define     AT91_AIC_PRIOR      (7 << 0)        /* Priority Level */
+#define     AT91_AIC_SRCTYPE    (3 << 5)        /* Interrupt Source Type */
+#define         AT91_AIC_SRCTYPE_LOW        (0 << 5)
+#define         AT91_AIC_SRCTYPE_FALLING    (1 << 5)
+#define         AT91_AIC_SRCTYPE_HIGH       (2 << 5)
+#define         AT91_AIC_SRCTYPE_RISING     (3 << 5)
+
+#define AT91_AIC_SVR(n)     (AT91_AIC + 0x80 + ((n) * 4))   /* Source Vector Registers 0-31 */
+#define AT91_AIC_IVR        (AT91_AIC + 0x100)  /* Interrupt Vector Register */
+#define AT91_AIC_FVR        (AT91_AIC + 0x104)  /* Fast Interrupt Vector Register */
+#define AT91_AIC_ISR        (AT91_AIC + 0x108)  /* Interrupt Status Register */
+#define     AT91_AIC_IRQID      (0x1f << 0)     /* Current Interrupt Identifier */
+
+#define AT91_AIC_IPR        (AT91_AIC + 0x10c)  /* Interrupt Pending Register */
+#define AT91_AIC_IMR        (AT91_AIC + 0x110)  /* Interrupt Mask Register */
+#define AT91_AIC_CISR       (AT91_AIC + 0x114)  /* Core Interrupt Status Register */
+#define     AT91_AIC_NFIQ       (1 << 0)        /* nFIQ Status */
+#define     AT91_AIC_NIRQ       (1 << 1)        /* nIRQ Status */
+
+#define AT91_AIC_IECR       (AT91_AIC + 0x120)  /* Interrupt Enable Command Register */
+#define AT91_AIC_IDCR       (AT91_AIC + 0x124)  /* Interrupt Disable Command Register */
+#define AT91_AIC_ICCR       (AT91_AIC + 0x128)  /* Interrupt Clear Command Register */
+#define AT91_AIC_ISCR       (AT91_AIC + 0x12c)  /* Interrupt Set Command Register */
+#define AT91_AIC_EOICR      (AT91_AIC + 0x130)  /* End of Interrupt Command Register */
+#define AT91_AIC_SPU        (AT91_AIC + 0x134)  /* Spurious Interrupt Vector Register */
+#define AT91_AIC_DCR        (AT91_AIC + 0x138)  /* Debug Control Register */
+#define     AT91_AIC_DCR_PROT   (1 << 0)        /* Protection Mode */
+#define     AT91_AIC_DCR_GMSK   (1 << 1)        /* General Mask */
+
+#define AT91_AIC_FFER       (AT91_AIC + 0x140)  /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC_FFDR       (AT91_AIC + 0x144)  /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC_FFSR       (AT91_AIC + 0x148)  /* Fast Forcing Status Register [SAM9 only] */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_pdc.h

@@ -11,21 +11,21 @@
 #ifndef __AT91_PDC_H__
 #define __AT91_PDC_H__
 
-#define AT91_PDC_RPR		0x100	/* Receive Pointer Register */
-#define AT91_PDC_RCR		0x104	/* Receive Counter Register */
-#define AT91_PDC_TPR		0x108	/* Transmit Pointer Register */
-#define AT91_PDC_TCR		0x10c	/* Transmit Counter Register */
-#define AT91_PDC_RNPR		0x110	/* Receive Next Pointer Register */
-#define AT91_PDC_RNCR		0x114	/* Receive Next Counter Register */
-#define AT91_PDC_TNPR		0x118	/* Transmit Next Pointer Register */
-#define AT91_PDC_TNCR		0x11c	/* Transmit Next Counter Register */
+#define AT91_PDC_RPR        0x100   /* Receive Pointer Register */
+#define AT91_PDC_RCR        0x104   /* Receive Counter Register */
+#define AT91_PDC_TPR        0x108   /* Transmit Pointer Register */
+#define AT91_PDC_TCR        0x10c   /* Transmit Counter Register */
+#define AT91_PDC_RNPR       0x110   /* Receive Next Pointer Register */
+#define AT91_PDC_RNCR       0x114   /* Receive Next Counter Register */
+#define AT91_PDC_TNPR       0x118   /* Transmit Next Pointer Register */
+#define AT91_PDC_TNCR       0x11c   /* Transmit Next Counter Register */
 
-#define AT91_PDC_PTCR		0x120	/* Transfer Control Register */
-#define		AT91_PDC_RXTEN		(1 << 0)	/* Receiver Transfer Enable */
-#define		AT91_PDC_RXTDIS	(1 << 1)	/* Receiver Transfer Disable */
-#define		AT91_PDC_TXTEN		(1 << 8)	/* Transmitter Transfer Enable */
-#define		AT91_PDC_TXTDIS	(1 << 9)	/* Transmitter Transfer Disable */
+#define AT91_PDC_PTCR       0x120   /* Transfer Control Register */
+#define     AT91_PDC_RXTEN      (1 << 0)    /* Receiver Transfer Enable */
+#define     AT91_PDC_RXTDIS (1 << 1)    /* Receiver Transfer Disable */
+#define     AT91_PDC_TXTEN      (1 << 8)    /* Transmitter Transfer Enable */
+#define     AT91_PDC_TXTDIS (1 << 9)    /* Transmitter Transfer Disable */
 
-#define AT91_PDC_PTSR		0x124	/* Transfer Status Register */
+#define AT91_PDC_PTSR       0x124   /* Transfer Status Register */
 
 #endif

bsp/at91sam9260/platform/at91_pio.h

@@ -16,35 +16,35 @@
 extern "C" {
 #endif
 
-#define PIO_PER		0x00	/* Enable Register */
-#define PIO_PDR		0x04	/* Disable Register */
-#define PIO_PSR		0x08	/* Status Register */
-#define PIO_OER		0x10	/* Output Enable Register */
-#define PIO_ODR		0x14	/* Output Disable Register */
-#define PIO_OSR		0x18	/* Output Status Register */
-#define PIO_IFER	0x20	/* Glitch Input Filter Enable */
-#define PIO_IFDR	0x24	/* Glitch Input Filter Disable */
-#define PIO_IFSR	0x28	/* Glitch Input Filter Status */
-#define PIO_SODR	0x30	/* Set Output Data Register */
-#define PIO_CODR	0x34	/* Clear Output Data Register */
-#define PIO_ODSR	0x38	/* Output Data Status Register */
-#define PIO_PDSR	0x3c	/* Pin Data Status Register */
-#define PIO_IER		0x40	/* Interrupt Enable Register */
-#define PIO_IDR		0x44	/* Interrupt Disable Register */
-#define PIO_IMR		0x48	/* Interrupt Mask Register */
-#define PIO_ISR		0x4c	/* Interrupt Status Register */
-#define PIO_MDER	0x50	/* Multi-driver Enable Register */
-#define PIO_MDDR	0x54	/* Multi-driver Disable Register */
-#define PIO_MDSR	0x58	/* Multi-driver Status Register */
-#define PIO_PUDR	0x60	/* Pull-up Disable Register */
-#define PIO_PUER	0x64	/* Pull-up Enable Register */
-#define PIO_PUSR	0x68	/* Pull-up Status Register */
-#define PIO_ASR		0x70	/* Peripheral A Select Register */
-#define PIO_BSR		0x74	/* Peripheral B Select Register */
-#define PIO_ABSR	0x78	/* AB Status Register */
-#define PIO_OWER	0xa0	/* Output Write Enable Register */
-#define PIO_OWDR	0xa4	/* Output Write Disable Register */
-#define PIO_OWSR	0xa8	/* Output Write Status Register */
+#define PIO_PER     0x00    /* Enable Register */
+#define PIO_PDR     0x04    /* Disable Register */
+#define PIO_PSR     0x08    /* Status Register */
+#define PIO_OER     0x10    /* Output Enable Register */
+#define PIO_ODR     0x14    /* Output Disable Register */
+#define PIO_OSR     0x18    /* Output Status Register */
+#define PIO_IFER    0x20    /* Glitch Input Filter Enable */
+#define PIO_IFDR    0x24    /* Glitch Input Filter Disable */
+#define PIO_IFSR    0x28    /* Glitch Input Filter Status */
+#define PIO_SODR    0x30    /* Set Output Data Register */
+#define PIO_CODR    0x34    /* Clear Output Data Register */
+#define PIO_ODSR    0x38    /* Output Data Status Register */
+#define PIO_PDSR    0x3c    /* Pin Data Status Register */
+#define PIO_IER     0x40    /* Interrupt Enable Register */
+#define PIO_IDR     0x44    /* Interrupt Disable Register */
+#define PIO_IMR     0x48    /* Interrupt Mask Register */
+#define PIO_ISR     0x4c    /* Interrupt Status Register */
+#define PIO_MDER    0x50    /* Multi-driver Enable Register */
+#define PIO_MDDR    0x54    /* Multi-driver Disable Register */
+#define PIO_MDSR    0x58    /* Multi-driver Status Register */
+#define PIO_PUDR    0x60    /* Pull-up Disable Register */
+#define PIO_PUER    0x64    /* Pull-up Enable Register */
+#define PIO_PUSR    0x68    /* Pull-up Status Register */
+#define PIO_ASR     0x70    /* Peripheral A Select Register */
+#define PIO_BSR     0x74    /* Peripheral B Select Register */
+#define PIO_ABSR    0x78    /* AB Status Register */
+#define PIO_OWER    0xa0    /* Output Write Enable Register */
+#define PIO_OWDR    0xa4    /* Output Write Disable Register */
+#define PIO_OWSR    0xa8    /* Output Write Status Register */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_pit.h

@@ -15,18 +15,18 @@
 extern "C" {
 #endif
 
-#define AT91_PIT_MR		(AT91_PIT + 0x00)	/* Mode Register */
-#define		AT91_PIT_PITIEN		(1 << 25)		/* Timer Interrupt Enable */
-#define		AT91_PIT_PITEN		(1 << 24)		/* Timer Enabled */
-#define		AT91_PIT_PIV		(0xfffff)		/* Periodic Interval Value */
-
-#define AT91_PIT_SR		(AT91_PIT + 0x04)	/* Status Register */
-#define		AT91_PIT_PITS		(1 << 0)		/* Timer Status */
-
-#define AT91_PIT_PIVR		(AT91_PIT + 0x08)	/* Periodic Interval Value Register */
-#define AT91_PIT_PIIR		(AT91_PIT + 0x0c)	/* Periodic Interval Image Register */
-#define		AT91_PIT_PICNT		(0xfff << 20)		/* Interval Counter */
-#define		AT91_PIT_CPIV		(0xfffff)		/* Inverval Value */
+#define AT91_PIT_MR     (AT91_PIT + 0x00)   /* Mode Register */
+#define     AT91_PIT_PITIEN     (1 << 25)       /* Timer Interrupt Enable */
+#define     AT91_PIT_PITEN      (1 << 24)       /* Timer Enabled */
+#define     AT91_PIT_PIV        (0xfffff)       /* Periodic Interval Value */
+
+#define AT91_PIT_SR     (AT91_PIT + 0x04)   /* Status Register */
+#define     AT91_PIT_PITS       (1 << 0)        /* Timer Status */
+
+#define AT91_PIT_PIVR       (AT91_PIT + 0x08)   /* Periodic Interval Value Register */
+#define AT91_PIT_PIIR       (AT91_PIT + 0x0c)   /* Periodic Interval Image Register */
+#define     AT91_PIT_PICNT      (0xfff << 20)       /* Interval Counter */
+#define     AT91_PIT_CPIV       (0xfffff)       /* Inverval Value */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_pmc.h

@@ -15,119 +15,119 @@
 extern "C" {
 #endif
 
-#define	AT91_PMC_SCER		(AT91_PMC + 0x00)	/* System Clock Enable Register */
-#define	AT91_PMC_SCDR		(AT91_PMC + 0x04)	/* System Clock Disable Register */
-
-#define	AT91_PMC_SCSR		(AT91_PMC + 0x08)	/* System Clock Status Register */
-#define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
-#define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
-#define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
-#define		AT91CAP9_PMC_DDR	(1 <<  2)		/* DDR Clock [CAP9 revC & some SAM9 only] */
-#define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
-#define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
-#define		AT91CAP9_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91CAP9 only] */
-#define		AT91SAM926x_PMC_UDP	(1 <<  7)		/* USB Devcice Port Clock [AT91SAM926x only] */
-#define		AT91_PMC_PCK0		(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1		(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2		(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3		(1 << 11)		/* Programmable Clock 3 */
-#define		AT91_PMC_PCK4		(1 << 12)		/* Programmable Clock 4 [AT572D940HF only] */
-#define		AT91_PMC_HCK0		(1 << 16)		/* AHB Clock (USB host) [AT91SAM9261 only] */
-#define		AT91_PMC_HCK1		(1 << 17)		/* AHB Clock (LCD) [AT91SAM9261 only] */
-
-#define	AT91_PMC_PCER		(AT91_PMC + 0x10)	/* Peripheral Clock Enable Register */
-#define	AT91_PMC_PCDR		(AT91_PMC + 0x14)	/* Peripheral Clock Disable Register */
-#define	AT91_PMC_PCSR		(AT91_PMC + 0x18)	/* Peripheral Clock Status Register */
-
-#define	AT91_CKGR_UCKR		(AT91_PMC + 0x1C)	/* UTMI Clock Register [some SAM9, CAP9] */
-#define		AT91_PMC_UPLLEN		(1   << 16)		/* UTMI PLL Enable */
-#define		AT91_PMC_UPLLCOUNT	(0xf << 20)		/* UTMI PLL Start-up Time */
-#define		AT91_PMC_BIASEN		(1   << 24)		/* UTMI BIAS Enable */
-#define		AT91_PMC_BIASCOUNT	(0xf << 28)		/* UTMI BIAS Start-up Time */
-
-#define	AT91_CKGR_MOR		(AT91_PMC + 0x20)	/* Main Oscillator Register [not on SAM9RL] */
-#define		AT91_PMC_MOSCEN		(1    << 0)		/* Main Oscillator Enable */
-#define		AT91_PMC_OSCBYPASS	(1    << 1)		/* Oscillator Bypass [SAM9x, CAP9] */
-#define		AT91_PMC_OSCOUNT	(0xff << 8)		/* Main Oscillator Start-up Time */
-
-#define	AT91_CKGR_MCFR		(AT91_PMC + 0x24)	/* Main Clock Frequency Register */
-#define		AT91_PMC_MAINF		(0xffff <<  0)		/* Main Clock Frequency */
-#define		AT91_PMC_MAINRDY	(1	<< 16)		/* Main Clock Ready */
-
-#define	AT91_CKGR_PLLAR		(AT91_PMC + 0x28)	/* PLL A Register */
-#define	AT91_CKGR_PLLBR		(AT91_PMC + 0x2c)	/* PLL B Register */
-#define		AT91_PMC_DIV		(0xff  <<  0)		/* Divider */
-#define		AT91_PMC_PLLCOUNT	(0x3f  <<  8)		/* PLL Counter */
-#define		AT91_PMC_OUT		(3     << 14)		/* PLL Clock Frequency Range */
-#define		AT91_PMC_MUL		(0x7ff << 16)		/* PLL Multiplier */
-#define		AT91_PMC_USBDIV		(3     << 28)		/* USB Divisor (PLLB only) */
-#define			AT91_PMC_USBDIV_1		(0 << 28)
-#define			AT91_PMC_USBDIV_2		(1 << 28)
-#define			AT91_PMC_USBDIV_4		(2 << 28)
-#define		AT91_PMC_USB96M		(1     << 28)		/* Divider by 2 Enable (PLLB only) */
-
-#define	AT91_PMC_MCKR		(AT91_PMC + 0x30)	/* Master Clock Register */
-#define		AT91_PMC_CSS		(3 <<  0)		/* Master Clock Selection */
-#define			AT91_PMC_CSS_SLOW		(0 << 0)
-#define			AT91_PMC_CSS_MAIN		(1 << 0)
-#define			AT91_PMC_CSS_PLLA		(2 << 0)
-#define			AT91_PMC_CSS_PLLB		(3 << 0)
-#define			AT91_PMC_CSS_UPLL		(3 << 0)	/* [some SAM9 only] */
-#define		AT91_PMC_PRES		(7 <<  2)		/* Master Clock Prescaler */
-#define			AT91_PMC_PRES_1			(0 << 2)
-#define			AT91_PMC_PRES_2			(1 << 2)
-#define			AT91_PMC_PRES_4			(2 << 2)
-#define			AT91_PMC_PRES_8			(3 << 2)
-#define			AT91_PMC_PRES_16		(4 << 2)
-#define			AT91_PMC_PRES_32		(5 << 2)
-#define			AT91_PMC_PRES_64		(6 << 2)
-#define		AT91_PMC_MDIV		(3 <<  8)		/* Master Clock Division */
-#define			AT91RM9200_PMC_MDIV_1		(0 << 8)	/* [AT91RM9200 only] */
-#define			AT91RM9200_PMC_MDIV_2		(1 << 8)
-#define			AT91RM9200_PMC_MDIV_3		(2 << 8)
-#define			AT91RM9200_PMC_MDIV_4		(3 << 8)
-#define			AT91SAM9_PMC_MDIV_1		(0 << 8)	/* [SAM9,CAP9 only] */
-#define			AT91SAM9_PMC_MDIV_2		(1 << 8)
-#define			AT91SAM9_PMC_MDIV_4		(2 << 8)
-#define			AT91SAM9_PMC_MDIV_6		(3 << 8)	/* [some SAM9 only] */
-#define			AT91SAM9_PMC_MDIV_3		(3 << 8)	/* [some SAM9 only] */
-#define		AT91_PMC_PDIV		(1 << 12)		/* Processor Clock Division [some SAM9 only] */
-#define			AT91_PMC_PDIV_1			(0 << 12)
-#define			AT91_PMC_PDIV_2			(1 << 12)
-#define		AT91_PMC_PLLADIV2	(1 << 12)		/* PLLA divisor by 2 [some SAM9 only] */
-#define			AT91_PMC_PLLADIV2_OFF		(0 << 12)
-#define			AT91_PMC_PLLADIV2_ON		(1 << 12)
-
-#define	AT91_PMC_USB		(AT91_PMC + 0x38)	/* USB Clock Register [some SAM9 only] */
-#define		AT91_PMC_USBS		(0x1 <<  0)		/* USB OHCI Input clock selection */
-#define			AT91_PMC_USBS_PLLA		(0 << 0)
-#define			AT91_PMC_USBS_UPLL		(1 << 0)
-#define		AT91_PMC_OHCIUSBDIV	(0xF <<  8)		/* Divider for USB OHCI Clock */
-
-#define	AT91_PMC_PCKR(n)	(AT91_PMC + 0x40 + ((n) * 4))	/* Programmable Clock 0-N Registers */
-#define		AT91_PMC_CSSMCK		(0x1 <<  8)		/* CSS or Master Clock Selection */
-#define			AT91_PMC_CSSMCK_CSS		(0 << 8)
-#define			AT91_PMC_CSSMCK_MCK		(1 << 8)
-
-#define	AT91_PMC_IER		(AT91_PMC + 0x60)	/* Interrupt Enable Register */
-#define	AT91_PMC_IDR		(AT91_PMC + 0x64)	/* Interrupt Disable Register */
-#define	AT91_PMC_SR		(AT91_PMC + 0x68)	/* Status Register */
-#define		AT91_PMC_MOSCS		(1 <<  0)		/* MOSCS Flag */
-#define		AT91_PMC_LOCKA		(1 <<  1)		/* PLLA Lock */
-#define		AT91_PMC_LOCKB		(1 <<  2)		/* PLLB Lock */
-#define		AT91_PMC_MCKRDY		(1 <<  3)		/* Master Clock */
-#define		AT91_PMC_LOCKU		(1 <<  6)		/* UPLL Lock [some SAM9, AT91CAP9 only] */
-#define		AT91_PMC_OSCSEL		(1 <<  7)		/* Slow Clock Oscillator [AT91CAP9 revC only] */
-#define		AT91_PMC_PCK0RDY	(1 <<  8)		/* Programmable Clock 0 */
-#define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
-#define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
-#define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
-#define	AT91_PMC_IMR		(AT91_PMC + 0x6c)	/* Interrupt Mask Register */
-
-#define AT91_PMC_PROT		(AT91_PMC + 0xe4)	/* Protect Register [AT91CAP9 revC only] */
-#define		AT91_PMC_PROTKEY	0x504d4301		/* Activation Code */
-
-#define AT91_PMC_VER		(AT91_PMC + 0xfc)	/* PMC Module Version [AT91CAP9 only] */
+#define AT91_PMC_SCER       (AT91_PMC + 0x00)   /* System Clock Enable Register */
+#define AT91_PMC_SCDR       (AT91_PMC + 0x04)   /* System Clock Disable Register */
+
+#define AT91_PMC_SCSR       (AT91_PMC + 0x08)   /* System Clock Status Register */
+#define     AT91_PMC_PCK        (1 <<  0)       /* Processor Clock */
+#define     AT91RM9200_PMC_UDP  (1 <<  1)       /* USB Devcice Port Clock [AT91RM9200 only] */
+#define     AT91RM9200_PMC_MCKUDP   (1 <<  2)       /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
+#define     AT91CAP9_PMC_DDR    (1 <<  2)       /* DDR Clock [CAP9 revC & some SAM9 only] */
+#define     AT91RM9200_PMC_UHP  (1 <<  4)       /* USB Host Port Clock [AT91RM9200 only] */
+#define     AT91SAM926x_PMC_UHP (1 <<  6)       /* USB Host Port Clock [AT91SAM926x only] */
+#define     AT91CAP9_PMC_UHP    (1 <<  6)       /* USB Host Port Clock [AT91CAP9 only] */
+#define     AT91SAM926x_PMC_UDP (1 <<  7)       /* USB Devcice Port Clock [AT91SAM926x only] */
+#define     AT91_PMC_PCK0       (1 <<  8)       /* Programmable Clock 0 */
+#define     AT91_PMC_PCK1       (1 <<  9)       /* Programmable Clock 1 */
+#define     AT91_PMC_PCK2       (1 << 10)       /* Programmable Clock 2 */
+#define     AT91_PMC_PCK3       (1 << 11)       /* Programmable Clock 3 */
+#define     AT91_PMC_PCK4       (1 << 12)       /* Programmable Clock 4 [AT572D940HF only] */
+#define     AT91_PMC_HCK0       (1 << 16)       /* AHB Clock (USB host) [AT91SAM9261 only] */
+#define     AT91_PMC_HCK1       (1 << 17)       /* AHB Clock (LCD) [AT91SAM9261 only] */
+
+#define AT91_PMC_PCER       (AT91_PMC + 0x10)   /* Peripheral Clock Enable Register */
+#define AT91_PMC_PCDR       (AT91_PMC + 0x14)   /* Peripheral Clock Disable Register */
+#define AT91_PMC_PCSR       (AT91_PMC + 0x18)   /* Peripheral Clock Status Register */
+
+#define AT91_CKGR_UCKR      (AT91_PMC + 0x1C)   /* UTMI Clock Register [some SAM9, CAP9] */
+#define     AT91_PMC_UPLLEN     (1   << 16)     /* UTMI PLL Enable */
+#define     AT91_PMC_UPLLCOUNT  (0xf << 20)     /* UTMI PLL Start-up Time */
+#define     AT91_PMC_BIASEN     (1   << 24)     /* UTMI BIAS Enable */
+#define     AT91_PMC_BIASCOUNT  (0xf << 28)     /* UTMI BIAS Start-up Time */
+
+#define AT91_CKGR_MOR       (AT91_PMC + 0x20)   /* Main Oscillator Register [not on SAM9RL] */
+#define     AT91_PMC_MOSCEN     (1    << 0)     /* Main Oscillator Enable */
+#define     AT91_PMC_OSCBYPASS  (1    << 1)     /* Oscillator Bypass [SAM9x, CAP9] */
+#define     AT91_PMC_OSCOUNT    (0xff << 8)     /* Main Oscillator Start-up Time */
+
+#define AT91_CKGR_MCFR      (AT91_PMC + 0x24)   /* Main Clock Frequency Register */
+#define     AT91_PMC_MAINF      (0xffff <<  0)      /* Main Clock Frequency */
+#define     AT91_PMC_MAINRDY    (1  << 16)      /* Main Clock Ready */
+
+#define AT91_CKGR_PLLAR     (AT91_PMC + 0x28)   /* PLL A Register */
+#define AT91_CKGR_PLLBR     (AT91_PMC + 0x2c)   /* PLL B Register */
+#define     AT91_PMC_DIV        (0xff  <<  0)       /* Divider */
+#define     AT91_PMC_PLLCOUNT   (0x3f  <<  8)       /* PLL Counter */
+#define     AT91_PMC_OUT        (3     << 14)       /* PLL Clock Frequency Range */
+#define     AT91_PMC_MUL        (0x7ff << 16)       /* PLL Multiplier */
+#define     AT91_PMC_USBDIV     (3     << 28)       /* USB Divisor (PLLB only) */
+#define         AT91_PMC_USBDIV_1       (0 << 28)
+#define         AT91_PMC_USBDIV_2       (1 << 28)
+#define         AT91_PMC_USBDIV_4       (2 << 28)
+#define     AT91_PMC_USB96M     (1     << 28)       /* Divider by 2 Enable (PLLB only) */
+
+#define AT91_PMC_MCKR       (AT91_PMC + 0x30)   /* Master Clock Register */
+#define     AT91_PMC_CSS        (3 <<  0)       /* Master Clock Selection */
+#define         AT91_PMC_CSS_SLOW       (0 << 0)
+#define         AT91_PMC_CSS_MAIN       (1 << 0)
+#define         AT91_PMC_CSS_PLLA       (2 << 0)
+#define         AT91_PMC_CSS_PLLB       (3 << 0)
+#define         AT91_PMC_CSS_UPLL       (3 << 0)    /* [some SAM9 only] */
+#define     AT91_PMC_PRES       (7 <<  2)       /* Master Clock Prescaler */
+#define         AT91_PMC_PRES_1         (0 << 2)
+#define         AT91_PMC_PRES_2         (1 << 2)
+#define         AT91_PMC_PRES_4         (2 << 2)
+#define         AT91_PMC_PRES_8         (3 << 2)
+#define         AT91_PMC_PRES_16        (4 << 2)
+#define         AT91_PMC_PRES_32        (5 << 2)
+#define         AT91_PMC_PRES_64        (6 << 2)
+#define     AT91_PMC_MDIV       (3 <<  8)       /* Master Clock Division */
+#define         AT91RM9200_PMC_MDIV_1       (0 << 8)    /* [AT91RM9200 only] */
+#define         AT91RM9200_PMC_MDIV_2       (1 << 8)
+#define         AT91RM9200_PMC_MDIV_3       (2 << 8)
+#define         AT91RM9200_PMC_MDIV_4       (3 << 8)
+#define         AT91SAM9_PMC_MDIV_1     (0 << 8)    /* [SAM9,CAP9 only] */
+#define         AT91SAM9_PMC_MDIV_2     (1 << 8)
+#define         AT91SAM9_PMC_MDIV_4     (2 << 8)
+#define         AT91SAM9_PMC_MDIV_6     (3 << 8)    /* [some SAM9 only] */
+#define         AT91SAM9_PMC_MDIV_3     (3 << 8)    /* [some SAM9 only] */
+#define     AT91_PMC_PDIV       (1 << 12)       /* Processor Clock Division [some SAM9 only] */
+#define         AT91_PMC_PDIV_1         (0 << 12)
+#define         AT91_PMC_PDIV_2         (1 << 12)
+#define     AT91_PMC_PLLADIV2   (1 << 12)       /* PLLA divisor by 2 [some SAM9 only] */
+#define         AT91_PMC_PLLADIV2_OFF       (0 << 12)
+#define         AT91_PMC_PLLADIV2_ON        (1 << 12)
+
+#define AT91_PMC_USB        (AT91_PMC + 0x38)   /* USB Clock Register [some SAM9 only] */
+#define     AT91_PMC_USBS       (0x1 <<  0)     /* USB OHCI Input clock selection */
+#define         AT91_PMC_USBS_PLLA      (0 << 0)
+#define         AT91_PMC_USBS_UPLL      (1 << 0)
+#define     AT91_PMC_OHCIUSBDIV (0xF <<  8)     /* Divider for USB OHCI Clock */
+
+#define AT91_PMC_PCKR(n)    (AT91_PMC + 0x40 + ((n) * 4))   /* Programmable Clock 0-N Registers */
+#define     AT91_PMC_CSSMCK     (0x1 <<  8)     /* CSS or Master Clock Selection */
+#define         AT91_PMC_CSSMCK_CSS     (0 << 8)
+#define         AT91_PMC_CSSMCK_MCK     (1 << 8)
+
+#define AT91_PMC_IER        (AT91_PMC + 0x60)   /* Interrupt Enable Register */
+#define AT91_PMC_IDR        (AT91_PMC + 0x64)   /* Interrupt Disable Register */
+#define AT91_PMC_SR     (AT91_PMC + 0x68)   /* Status Register */
+#define     AT91_PMC_MOSCS      (1 <<  0)       /* MOSCS Flag */
+#define     AT91_PMC_LOCKA      (1 <<  1)       /* PLLA Lock */
+#define     AT91_PMC_LOCKB      (1 <<  2)       /* PLLB Lock */
+#define     AT91_PMC_MCKRDY     (1 <<  3)       /* Master Clock */
+#define     AT91_PMC_LOCKU      (1 <<  6)       /* UPLL Lock [some SAM9, AT91CAP9 only] */
+#define     AT91_PMC_OSCSEL     (1 <<  7)       /* Slow Clock Oscillator [AT91CAP9 revC only] */
+#define     AT91_PMC_PCK0RDY    (1 <<  8)       /* Programmable Clock 0 */
+#define     AT91_PMC_PCK1RDY    (1 <<  9)       /* Programmable Clock 1 */
+#define     AT91_PMC_PCK2RDY    (1 << 10)       /* Programmable Clock 2 */
+#define     AT91_PMC_PCK3RDY    (1 << 11)       /* Programmable Clock 3 */
+#define AT91_PMC_IMR        (AT91_PMC + 0x6c)   /* Interrupt Mask Register */
+
+#define AT91_PMC_PROT       (AT91_PMC + 0xe4)   /* Protect Register [AT91CAP9 revC only] */
+#define     AT91_PMC_PROTKEY    0x504d4301      /* Activation Code */
+
+#define AT91_PMC_VER        (AT91_PMC + 0xfc)   /* PMC Module Version [AT91CAP9 only] */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_rstc.h

@@ -15,27 +15,27 @@
 extern "C" {
 #endif
 
-#define AT91_RSTC_CR		(AT91_RSTC + 0x00)	/* Reset Controller Control Register */
-#define		AT91_RSTC_PROCRST	(1 << 0)		/* Processor Reset */
-#define		AT91_RSTC_PERRST	(1 << 2)		/* Peripheral Reset */
-#define		AT91_RSTC_EXTRST	(1 << 3)		/* External Reset */
-#define		AT91_RSTC_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_RSTC_SR		(AT91_RSTC + 0x04)	/* Reset Controller Status Register */
-#define		AT91_RSTC_URSTS		(1 << 0)		/* User Reset Status */
-#define		AT91_RSTC_RSTTYP	(7 << 8)		/* Reset Type */
-#define			AT91_RSTC_RSTTYP_GENERAL	(0 << 8)
-#define			AT91_RSTC_RSTTYP_WAKEUP		(1 << 8)
-#define			AT91_RSTC_RSTTYP_WATCHDOG	(2 << 8)
-#define			AT91_RSTC_RSTTYP_SOFTWARE	(3 << 8)
-#define			AT91_RSTC_RSTTYP_USER	(4 << 8)
-#define		AT91_RSTC_NRSTL		(1 << 16)		/* NRST Pin Level */
-#define		AT91_RSTC_SRCMP		(1 << 17)		/* Software Reset Command in Progress */
-
-#define AT91_RSTC_MR		(AT91_RSTC + 0x08)	/* Reset Controller Mode Register */
-#define		AT91_RSTC_URSTEN	(1 << 0)		/* User Reset Enable */
-#define		AT91_RSTC_URSTIEN	(1 << 4)		/* User Reset Interrupt Enable */
-#define		AT91_RSTC_ERSTL		(0xf << 8)		/* External Reset Length */
+#define AT91_RSTC_CR        (AT91_RSTC + 0x00)  /* Reset Controller Control Register */
+#define     AT91_RSTC_PROCRST   (1 << 0)        /* Processor Reset */
+#define     AT91_RSTC_PERRST    (1 << 2)        /* Peripheral Reset */
+#define     AT91_RSTC_EXTRST    (1 << 3)        /* External Reset */
+#define     AT91_RSTC_KEY       (0xa5 << 24)        /* KEY Password */
+
+#define AT91_RSTC_SR        (AT91_RSTC + 0x04)  /* Reset Controller Status Register */
+#define     AT91_RSTC_URSTS     (1 << 0)        /* User Reset Status */
+#define     AT91_RSTC_RSTTYP    (7 << 8)        /* Reset Type */
+#define         AT91_RSTC_RSTTYP_GENERAL    (0 << 8)
+#define         AT91_RSTC_RSTTYP_WAKEUP     (1 << 8)
+#define         AT91_RSTC_RSTTYP_WATCHDOG   (2 << 8)
+#define         AT91_RSTC_RSTTYP_SOFTWARE   (3 << 8)
+#define         AT91_RSTC_RSTTYP_USER   (4 << 8)
+#define     AT91_RSTC_NRSTL     (1 << 16)       /* NRST Pin Level */
+#define     AT91_RSTC_SRCMP     (1 << 17)       /* Software Reset Command in Progress */
+
+#define AT91_RSTC_MR        (AT91_RSTC + 0x08)  /* Reset Controller Mode Register */
+#define     AT91_RSTC_URSTEN    (1 << 0)        /* User Reset Enable */
+#define     AT91_RSTC_URSTIEN   (1 << 4)        /* User Reset Interrupt Enable */
+#define     AT91_RSTC_ERSTL     (0xf << 8)      /* External Reset Length */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_serial.h

@@ -15,113 +15,113 @@
 extern "C" {
 #endif
 
-#define AT91_US_CR		0x00			/* Control Register */
-#define		AT91_US_RSTRX		(1 <<  2)		/* Reset Receiver */
-#define		AT91_US_RSTTX		(1 <<  3)		/* Reset Transmitter */
-#define		AT91_US_RXEN		(1 <<  4)		/* Receiver Enable */
-#define		AT91_US_RXDIS		(1 <<  5)		/* Receiver Disable */
-#define		AT91_US_TXEN		(1 <<  6)		/* Transmitter Enable */
-#define		AT91_US_TXDIS		(1 <<  7)		/* Transmitter Disable */
-#define		AT91_US_RSTSTA		(1 <<  8)		/* Reset Status Bits */
-#define		AT91_US_STTBRK		(1 <<  9)		/* Start Break */
-#define		AT91_US_STPBRK		(1 << 10)		/* Stop Break */
-#define		AT91_US_STTTO		(1 << 11)		/* Start Time-out */
-#define		AT91_US_SENDA		(1 << 12)		/* Send Address */
-#define		AT91_US_RSTIT		(1 << 13)		/* Reset Iterations */
-#define		AT91_US_RSTNACK	(1 << 14)		/* Reset Non Acknowledge */
-#define		AT91_US_RETTO		(1 << 15)		/* Rearm Time-out */
-#define		AT91_US_DTREN		(1 << 16)		/* Data Terminal Ready Enable [AT91RM9200 only] */
-#define		AT91_US_DTRDIS		(1 << 17)		/* Data Terminal Ready Disable [AT91RM9200 only] */
-#define		AT91_US_RTSEN		(1 << 18)		/* Request To Send Enable */
-#define		AT91_US_RTSDIS		(1 << 19)		/* Request To Send Disable */
+#define AT91_US_CR      0x00            /* Control Register */
+#define     AT91_US_RSTRX       (1 <<  2)       /* Reset Receiver */
+#define     AT91_US_RSTTX       (1 <<  3)       /* Reset Transmitter */
+#define     AT91_US_RXEN        (1 <<  4)       /* Receiver Enable */
+#define     AT91_US_RXDIS       (1 <<  5)       /* Receiver Disable */
+#define     AT91_US_TXEN        (1 <<  6)       /* Transmitter Enable */
+#define     AT91_US_TXDIS       (1 <<  7)       /* Transmitter Disable */
+#define     AT91_US_RSTSTA      (1 <<  8)       /* Reset Status Bits */
+#define     AT91_US_STTBRK      (1 <<  9)       /* Start Break */
+#define     AT91_US_STPBRK      (1 << 10)       /* Stop Break */
+#define     AT91_US_STTTO       (1 << 11)       /* Start Time-out */
+#define     AT91_US_SENDA       (1 << 12)       /* Send Address */
+#define     AT91_US_RSTIT       (1 << 13)       /* Reset Iterations */
+#define     AT91_US_RSTNACK (1 << 14)       /* Reset Non Acknowledge */
+#define     AT91_US_RETTO       (1 << 15)       /* Rearm Time-out */
+#define     AT91_US_DTREN       (1 << 16)       /* Data Terminal Ready Enable [AT91RM9200 only] */
+#define     AT91_US_DTRDIS      (1 << 17)       /* Data Terminal Ready Disable [AT91RM9200 only] */
+#define     AT91_US_RTSEN       (1 << 18)       /* Request To Send Enable */
+#define     AT91_US_RTSDIS      (1 << 19)       /* Request To Send Disable */
 
-#define AT91_US_MR		0x04			/* Mode Register */
-#define		AT91_US_USMODE		(0xf <<  0)		/* Mode of the USART */
-#define			AT91_US_USMODE_NORMAL		0
-#define			AT91_US_USMODE_RS485		1
-#define			AT91_US_USMODE_HWHS		2
-#define			AT91_US_USMODE_MODEM		3
-#define			AT91_US_USMODE_ISO7816_T0	4
-#define			AT91_US_USMODE_ISO7816_T1	6
-#define			AT91_US_USMODE_IRDA		8
-#define		AT91_US_USCLKS		(3   <<  4)		/* Clock Selection */
-#define			AT91_US_USCLKS_MCK		(0 <<  4)
-#define			AT91_US_USCLKS_MCK_DIV8	(1 <<  4)
-#define			AT91_US_USCLKS_SCK		(3 <<  4)
-#define		AT91_US_CHRL		(3   <<  6)		/* Character Length */
-#define			AT91_US_CHRL_5			(0 <<  6)
-#define			AT91_US_CHRL_6			(1 <<  6)
-#define			AT91_US_CHRL_7			(2 <<  6)
-#define			AT91_US_CHRL_8			(3 <<  6)
-#define		AT91_US_SYNC		(1 <<  8)		/* Synchronous Mode Select */
-#define		AT91_US_PAR		(7 <<  9)		/* Parity Type */
-#define			AT91_US_PAR_EVEN		(0 <<  9)
-#define			AT91_US_PAR_ODD		(1 <<  9)
-#define			AT91_US_PAR_SPACE		(2 <<  9)
-#define			AT91_US_PAR_MARK		(3 <<  9)
-#define			AT91_US_PAR_NONE		(4 <<  9)
-#define			AT91_US_PAR_MULTI_DROP		(6 <<  9)
-#define		AT91_US_NBSTOP		(3 << 12)		/* Number of Stop Bits */
-#define			AT91_US_NBSTOP_1		(0 << 12)
-#define			AT91_US_NBSTOP_1_5		(1 << 12)
-#define			AT91_US_NBSTOP_2		(2 << 12)
-#define		AT91_US_CHMODE		(3 << 14)		/* Channel Mode */
-#define			AT91_US_CHMODE_NORMAL		(0 << 14)
-#define			AT91_US_CHMODE_ECHO		(1 << 14)
-#define			AT91_US_CHMODE_LOC_LOOP	(2 << 14)
-#define			AT91_US_CHMODE_REM_LOOP	(3 << 14)
-#define		AT91_US_MSBF		(1 << 16)		/* Bit Order */
-#define		AT91_US_MODE9		(1 << 17)		/* 9-bit Character Length */
-#define		AT91_US_CLKO		(1 << 18)		/* Clock Output Select */
-#define		AT91_US_OVER		(1 << 19)		/* Oversampling Mode */
-#define		AT91_US_INACK		(1 << 20)		/* Inhibit Non Acknowledge */
-#define		AT91_US_DSNACK		(1 << 21)		/* Disable Successive NACK */
-#define		AT91_US_MAX_ITER	(7 << 24)		/* Max Iterations */
-#define		AT91_US_FILTER		(1 << 28)		/* Infrared Receive Line Filter */
+#define AT91_US_MR      0x04            /* Mode Register */
+#define     AT91_US_USMODE      (0xf <<  0)     /* Mode of the USART */
+#define         AT91_US_USMODE_NORMAL       0
+#define         AT91_US_USMODE_RS485        1
+#define         AT91_US_USMODE_HWHS     2
+#define         AT91_US_USMODE_MODEM        3
+#define         AT91_US_USMODE_ISO7816_T0   4
+#define         AT91_US_USMODE_ISO7816_T1   6
+#define         AT91_US_USMODE_IRDA     8
+#define     AT91_US_USCLKS      (3   <<  4)     /* Clock Selection */
+#define         AT91_US_USCLKS_MCK      (0 <<  4)
+#define         AT91_US_USCLKS_MCK_DIV8 (1 <<  4)
+#define         AT91_US_USCLKS_SCK      (3 <<  4)
+#define     AT91_US_CHRL        (3   <<  6)     /* Character Length */
+#define         AT91_US_CHRL_5          (0 <<  6)
+#define         AT91_US_CHRL_6          (1 <<  6)
+#define         AT91_US_CHRL_7          (2 <<  6)
+#define         AT91_US_CHRL_8          (3 <<  6)
+#define     AT91_US_SYNC        (1 <<  8)       /* Synchronous Mode Select */
+#define     AT91_US_PAR     (7 <<  9)       /* Parity Type */
+#define         AT91_US_PAR_EVEN        (0 <<  9)
+#define         AT91_US_PAR_ODD     (1 <<  9)
+#define         AT91_US_PAR_SPACE       (2 <<  9)
+#define         AT91_US_PAR_MARK        (3 <<  9)
+#define         AT91_US_PAR_NONE        (4 <<  9)
+#define         AT91_US_PAR_MULTI_DROP      (6 <<  9)
+#define     AT91_US_NBSTOP      (3 << 12)       /* Number of Stop Bits */
+#define         AT91_US_NBSTOP_1        (0 << 12)
+#define         AT91_US_NBSTOP_1_5      (1 << 12)
+#define         AT91_US_NBSTOP_2        (2 << 12)
+#define     AT91_US_CHMODE      (3 << 14)       /* Channel Mode */
+#define         AT91_US_CHMODE_NORMAL       (0 << 14)
+#define         AT91_US_CHMODE_ECHO     (1 << 14)
+#define         AT91_US_CHMODE_LOC_LOOP (2 << 14)
+#define         AT91_US_CHMODE_REM_LOOP (3 << 14)
+#define     AT91_US_MSBF        (1 << 16)       /* Bit Order */
+#define     AT91_US_MODE9       (1 << 17)       /* 9-bit Character Length */
+#define     AT91_US_CLKO        (1 << 18)       /* Clock Output Select */
+#define     AT91_US_OVER        (1 << 19)       /* Oversampling Mode */
+#define     AT91_US_INACK       (1 << 20)       /* Inhibit Non Acknowledge */
+#define     AT91_US_DSNACK      (1 << 21)       /* Disable Successive NACK */
+#define     AT91_US_MAX_ITER    (7 << 24)       /* Max Iterations */
+#define     AT91_US_FILTER      (1 << 28)       /* Infrared Receive Line Filter */
 
-#define AT91_US_IER		0x08			/* Interrupt Enable Register */
-#define		AT91_US_RXRDY		(1 <<  0)		/* Receiver Ready */
-#define		AT91_US_TXRDY		(1 <<  1)		/* Transmitter Ready */
-#define		AT91_US_RXBRK		(1 <<  2)		/* Break Received / End of Break */
-#define		AT91_US_ENDRX		(1 <<  3)		/* End of Receiver Transfer */
-#define		AT91_US_ENDTX		(1 <<  4)		/* End of Transmitter Transfer */
-#define		AT91_US_OVRE		(1 <<  5)		/* Overrun Error */
-#define		AT91_US_FRAME		(1 <<  6)		/* Framing Error */
-#define		AT91_US_PARE		(1 <<  7)		/* Parity Error */
-#define		AT91_US_TIMEOUT	(1 <<  8)		/* Receiver Time-out */
-#define		AT91_US_TXEMPTY	(1 <<  9)		/* Transmitter Empty */
-#define		AT91_US_ITERATION	(1 << 10)		/* Max number of Repetitions Reached */
-#define		AT91_US_TXBUFE		(1 << 11)		/* Transmission Buffer Empty */
-#define		AT91_US_RXBUFF		(1 << 12)		/* Reception Buffer Full */
-#define		AT91_US_NACK		(1 << 13)		/* Non Acknowledge */
-#define		AT91_US_RIIC		(1 << 16)		/* Ring Indicator Input Change [AT91RM9200 only] */
-#define		AT91_US_DSRIC		(1 << 17)		/* Data Set Ready Input Change [AT91RM9200 only] */
-#define		AT91_US_DCDIC		(1 << 18)		/* Data Carrier Detect Input Change [AT91RM9200 only] */
-#define		AT91_US_CTSIC		(1 << 19)		/* Clear to Send Input Change */
-#define		AT91_US_RI		(1 << 20)		/* RI */
-#define		AT91_US_DSR		(1 << 21)		/* DSR */
-#define		AT91_US_DCD		(1 << 22)		/* DCD */
-#define		AT91_US_CTS		(1 << 23)		/* CTS */
+#define AT91_US_IER     0x08            /* Interrupt Enable Register */
+#define     AT91_US_RXRDY       (1 <<  0)       /* Receiver Ready */
+#define     AT91_US_TXRDY       (1 <<  1)       /* Transmitter Ready */
+#define     AT91_US_RXBRK       (1 <<  2)       /* Break Received / End of Break */
+#define     AT91_US_ENDRX       (1 <<  3)       /* End of Receiver Transfer */
+#define     AT91_US_ENDTX       (1 <<  4)       /* End of Transmitter Transfer */
+#define     AT91_US_OVRE        (1 <<  5)       /* Overrun Error */
+#define     AT91_US_FRAME       (1 <<  6)       /* Framing Error */
+#define     AT91_US_PARE        (1 <<  7)       /* Parity Error */
+#define     AT91_US_TIMEOUT (1 <<  8)       /* Receiver Time-out */
+#define     AT91_US_TXEMPTY (1 <<  9)       /* Transmitter Empty */
+#define     AT91_US_ITERATION   (1 << 10)       /* Max number of Repetitions Reached */
+#define     AT91_US_TXBUFE      (1 << 11)       /* Transmission Buffer Empty */
+#define     AT91_US_RXBUFF      (1 << 12)       /* Reception Buffer Full */
+#define     AT91_US_NACK        (1 << 13)       /* Non Acknowledge */
+#define     AT91_US_RIIC        (1 << 16)       /* Ring Indicator Input Change [AT91RM9200 only] */
+#define     AT91_US_DSRIC       (1 << 17)       /* Data Set Ready Input Change [AT91RM9200 only] */
+#define     AT91_US_DCDIC       (1 << 18)       /* Data Carrier Detect Input Change [AT91RM9200 only] */
+#define     AT91_US_CTSIC       (1 << 19)       /* Clear to Send Input Change */
+#define     AT91_US_RI      (1 << 20)       /* RI */
+#define     AT91_US_DSR     (1 << 21)       /* DSR */
+#define     AT91_US_DCD     (1 << 22)       /* DCD */
+#define     AT91_US_CTS     (1 << 23)       /* CTS */
 
-#define AT91_US_IDR		0x0c			/* Interrupt Disable Register */
-#define AT91_US_IMR		0x10			/* Interrupt Mask Register */
-#define AT91_US_CSR		0x14			/* Channel Status Register */
-#define AT91_US_RHR		0x18			/* Receiver Holding Register */
-#define AT91_US_THR		0x1c			/* Transmitter Holding Register */
-#define		AT91_US_SYNH		(1 << 15)		/* Transmit/Receive Sync [AT91SAM9261 only] */
+#define AT91_US_IDR     0x0c            /* Interrupt Disable Register */
+#define AT91_US_IMR     0x10            /* Interrupt Mask Register */
+#define AT91_US_CSR     0x14            /* Channel Status Register */
+#define AT91_US_RHR     0x18            /* Receiver Holding Register */
+#define AT91_US_THR     0x1c            /* Transmitter Holding Register */
+#define     AT91_US_SYNH        (1 << 15)       /* Transmit/Receive Sync [AT91SAM9261 only] */
 
-#define AT91_US_BRGR		0x20			/* Baud Rate Generator Register */
-#define		AT91_US_CD		(0xffff << 0)		/* Clock Divider */
+#define AT91_US_BRGR        0x20            /* Baud Rate Generator Register */
+#define     AT91_US_CD      (0xffff << 0)       /* Clock Divider */
 
-#define AT91_US_RTOR		0x24			/* Receiver Time-out Register */
-#define		AT91_US_TO		(0xffff << 0)		/* Time-out Value */
+#define AT91_US_RTOR        0x24            /* Receiver Time-out Register */
+#define     AT91_US_TO      (0xffff << 0)       /* Time-out Value */
 
-#define AT91_US_TTGR		0x28			/* Transmitter Timeguard Register */
-#define		AT91_US_TG		(0xff << 0)		/* Timeguard Value */
+#define AT91_US_TTGR        0x28            /* Transmitter Timeguard Register */
+#define     AT91_US_TG      (0xff << 0)     /* Timeguard Value */
 
-#define AT91_US_FIDI		0x40			/* FI DI Ratio Register */
-#define AT91_US_NER		0x44			/* Number of Errors Register */
-#define AT91_US_IF		0x4c			/* IrDA Filter Register */
+#define AT91_US_FIDI        0x40            /* FI DI Ratio Register */
+#define AT91_US_NER     0x44            /* Number of Errors Register */
+#define AT91_US_IF      0x4c            /* IrDA Filter Register */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_shdwc.h

@@ -15,24 +15,24 @@
 extern "C" {
 #endif
 
-#define AT91_SHDW_CR		(AT91_SHDWC + 0x00)	/* Shut Down Control Register */
-#define		AT91_SHDW_SHDW		(1    << 0)		/* Shut Down command */
-#define		AT91_SHDW_KEY		(0xa5 << 24)		/* KEY Password */
-
-#define AT91_SHDW_MR		(AT91_SHDWC + 0x04)	/* Shut Down Mode Register */
-#define		AT91_SHDW_WKMODE0	(3 << 0)		/* Wake-up 0 Mode Selection */
-#define			AT91_SHDW_WKMODE0_NONE		0
-#define			AT91_SHDW_WKMODE0_HIGH		1
-#define			AT91_SHDW_WKMODE0_LOW		2
-#define			AT91_SHDW_WKMODE0_ANYLEVEL	3
-#define		AT91_SHDW_CPTWK0	(0xf << 4)		/* Counter On Wake Up 0 */
-#define			AT91_SHDW_CPTWK0_(x)	((x) << 4)
-#define		AT91_SHDW_RTTWKEN	(1   << 16)		/* Real Time Timer Wake-up Enable */
-
-#define AT91_SHDW_SR		(AT91_SHDWC + 0x08)	/* Shut Down Status Register */
-#define		AT91_SHDW_WAKEUP0	(1 <<  0)		/* Wake-up 0 Status */
-#define		AT91_SHDW_RTTWK		(1 << 16)		/* Real-time Timer Wake-up */
-#define		AT91_SHDW_RTCWK		(1 << 17)		/* Real-time Clock Wake-up [SAM9RL] */
+#define AT91_SHDW_CR        (AT91_SHDWC + 0x00) /* Shut Down Control Register */
+#define     AT91_SHDW_SHDW      (1    << 0)     /* Shut Down command */
+#define     AT91_SHDW_KEY       (0xa5 << 24)        /* KEY Password */
+
+#define AT91_SHDW_MR        (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
+#define     AT91_SHDW_WKMODE0   (3 << 0)        /* Wake-up 0 Mode Selection */
+#define         AT91_SHDW_WKMODE0_NONE      0
+#define         AT91_SHDW_WKMODE0_HIGH      1
+#define         AT91_SHDW_WKMODE0_LOW       2
+#define         AT91_SHDW_WKMODE0_ANYLEVEL  3
+#define     AT91_SHDW_CPTWK0    (0xf << 4)      /* Counter On Wake Up 0 */
+#define         AT91_SHDW_CPTWK0_(x)    ((x) << 4)
+#define     AT91_SHDW_RTTWKEN   (1   << 16)     /* Real Time Timer Wake-up Enable */
+
+#define AT91_SHDW_SR        (AT91_SHDWC + 0x08) /* Shut Down Status Register */
+#define     AT91_SHDW_WAKEUP0   (1 <<  0)       /* Wake-up 0 Status */
+#define     AT91_SHDW_RTTWK     (1 << 16)       /* Real-time Timer Wake-up */
+#define     AT91_SHDW_RTCWK     (1 << 17)       /* Real-time Clock Wake-up [SAM9RL] */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91_tc.h

@@ -15,133 +15,133 @@
 extern "C" {
 #endif
 
-#define AT91_TC_BCR		0xc0		/* TC Block Control Register */
-#define		AT91_TC_SYNC		(1 << 0)	/* Synchro Command */
+#define AT91_TC_BCR     0xc0        /* TC Block Control Register */
+#define     AT91_TC_SYNC        (1 << 0)    /* Synchro Command */
 
-#define AT91_TC_BMR		0xc4		/* TC Block Mode Register */
-#define		AT91_TC_TC0XC0S		(3 << 0)	/* External Clock Signal 0 Selection */
-#define			AT91_TC_TC0XC0S_TCLK0		(0 << 0)
-#define			AT91_TC_TC0XC0S_NONE		(1 << 0)
-#define			AT91_TC_TC0XC0S_TIOA1		(2 << 0)
-#define			AT91_TC_TC0XC0S_TIOA2		(3 << 0)
-#define		AT91_TC_TC1XC1S		(3 << 2)	/* External Clock Signal 1 Selection */
-#define			AT91_TC_TC1XC1S_TCLK1		(0 << 2)
-#define			AT91_TC_TC1XC1S_NONE		(1 << 2)
-#define			AT91_TC_TC1XC1S_TIOA0		(2 << 2)
-#define			AT91_TC_TC1XC1S_TIOA2		(3 << 2)
-#define		AT91_TC_TC2XC2S		(3 << 4)	/* External Clock Signal 2 Selection */
-#define			AT91_TC_TC2XC2S_TCLK2		(0 << 4)
-#define			AT91_TC_TC2XC2S_NONE		(1 << 4)
-#define			AT91_TC_TC2XC2S_TIOA0		(2 << 4)
-#define			AT91_TC_TC2XC2S_TIOA1		(3 << 4)
+#define AT91_TC_BMR     0xc4        /* TC Block Mode Register */
+#define     AT91_TC_TC0XC0S     (3 << 0)    /* External Clock Signal 0 Selection */
+#define         AT91_TC_TC0XC0S_TCLK0       (0 << 0)
+#define         AT91_TC_TC0XC0S_NONE        (1 << 0)
+#define         AT91_TC_TC0XC0S_TIOA1       (2 << 0)
+#define         AT91_TC_TC0XC0S_TIOA2       (3 << 0)
+#define     AT91_TC_TC1XC1S     (3 << 2)    /* External Clock Signal 1 Selection */
+#define         AT91_TC_TC1XC1S_TCLK1       (0 << 2)
+#define         AT91_TC_TC1XC1S_NONE        (1 << 2)
+#define         AT91_TC_TC1XC1S_TIOA0       (2 << 2)
+#define         AT91_TC_TC1XC1S_TIOA2       (3 << 2)
+#define     AT91_TC_TC2XC2S     (3 << 4)    /* External Clock Signal 2 Selection */
+#define         AT91_TC_TC2XC2S_TCLK2       (0 << 4)
+#define         AT91_TC_TC2XC2S_NONE        (1 << 4)
+#define         AT91_TC_TC2XC2S_TIOA0       (2 << 4)
+#define         AT91_TC_TC2XC2S_TIOA1       (3 << 4)
 
 
-#define AT91_TC_CCR		0x00		/* Channel Control Register */
-#define		AT91_TC_CLKEN		(1 << 0)	/* Counter Clock Enable Command */
-#define		AT91_TC_CLKDIS		(1 << 1)	/* Counter CLock Disable Command */
-#define		AT91_TC_SWTRG		(1 << 2)	/* Software Trigger Command */
+#define AT91_TC_CCR     0x00        /* Channel Control Register */
+#define     AT91_TC_CLKEN       (1 << 0)    /* Counter Clock Enable Command */
+#define     AT91_TC_CLKDIS      (1 << 1)    /* Counter CLock Disable Command */
+#define     AT91_TC_SWTRG       (1 << 2)    /* Software Trigger Command */
 
-#define AT91_TC_CMR		0x04		/* Channel Mode Register */
-#define		AT91_TC_TCCLKS		(7 << 0)	/* Capture/Waveform Mode: Clock Selection */
-#define			AT91_TC_TIMER_CLOCK1		(0 << 0)
-#define			AT91_TC_TIMER_CLOCK2		(1 << 0)
-#define			AT91_TC_TIMER_CLOCK3		(2 << 0)
-#define			AT91_TC_TIMER_CLOCK4		(3 << 0)
-#define			AT91_TC_TIMER_CLOCK5		(4 << 0)
-#define			AT91_TC_XC0			(5 << 0)
-#define			AT91_TC_XC1			(6 << 0)
-#define			AT91_TC_XC2			(7 << 0)
-#define		AT91_TC_CLKI		(1 << 3)	/* Capture/Waveform Mode: Clock Invert */
-#define		AT91_TC_BURST		(3 << 4)	/* Capture/Waveform Mode: Burst Signal Selection */
-#define		AT91_TC_LDBSTOP		(1 << 6)	/* Capture Mode: Counter Clock Stopped with TB Loading */
-#define		AT91_TC_LDBDIS		(1 << 7)	/* Capture Mode: Counter Clock Disable with RB Loading */
-#define		AT91_TC_ETRGEDG		(3 << 8)	/* Capture Mode: External Trigger Edge Selection */
-#define		AT91_TC_ABETRG		(1 << 10)	/* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define		AT91_TC_CPCTRG		(1 << 14)	/* Capture Mode: RC Compare Trigger Enable */
-#define		AT91_TC_WAVE		(1 << 15)	/* Capture/Waveform mode */
-#define		AT91_TC_LDRA		(3 << 16)	/* Capture Mode: RA Loading Selection */
-#define		AT91_TC_LDRB		(3 << 18)	/* Capture Mode: RB Loading Selection */
+#define AT91_TC_CMR     0x04        /* Channel Mode Register */
+#define     AT91_TC_TCCLKS      (7 << 0)    /* Capture/Waveform Mode: Clock Selection */
+#define         AT91_TC_TIMER_CLOCK1        (0 << 0)
+#define         AT91_TC_TIMER_CLOCK2        (1 << 0)
+#define         AT91_TC_TIMER_CLOCK3        (2 << 0)
+#define         AT91_TC_TIMER_CLOCK4        (3 << 0)
+#define         AT91_TC_TIMER_CLOCK5        (4 << 0)
+#define         AT91_TC_XC0         (5 << 0)
+#define         AT91_TC_XC1         (6 << 0)
+#define         AT91_TC_XC2         (7 << 0)
+#define     AT91_TC_CLKI        (1 << 3)    /* Capture/Waveform Mode: Clock Invert */
+#define     AT91_TC_BURST       (3 << 4)    /* Capture/Waveform Mode: Burst Signal Selection */
+#define     AT91_TC_LDBSTOP     (1 << 6)    /* Capture Mode: Counter Clock Stopped with TB Loading */
+#define     AT91_TC_LDBDIS      (1 << 7)    /* Capture Mode: Counter Clock Disable with RB Loading */
+#define     AT91_TC_ETRGEDG     (3 << 8)    /* Capture Mode: External Trigger Edge Selection */
+#define     AT91_TC_ABETRG      (1 << 10)   /* Capture Mode: TIOA or TIOB External Trigger Selection */
+#define     AT91_TC_CPCTRG      (1 << 14)   /* Capture Mode: RC Compare Trigger Enable */
+#define     AT91_TC_WAVE        (1 << 15)   /* Capture/Waveform mode */
+#define     AT91_TC_LDRA        (3 << 16)   /* Capture Mode: RA Loading Selection */
+#define     AT91_TC_LDRB        (3 << 18)   /* Capture Mode: RB Loading Selection */
 
-#define		AT91_TC_CPCSTOP		(1 <<  6)	/* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define		AT91_TC_CPCDIS		(1 <<  7)	/* Waveform Mode: Counter Clock Disable with RC Compare */
-#define		AT91_TC_EEVTEDG		(3 <<  8)	/* Waveform Mode: External Event Edge Selection */
-#define			AT91_TC_EEVTEDG_NONE		(0 << 8)
-#define			AT91_TC_EEVTEDG_RISING		(1 << 8)
-#define			AT91_TC_EEVTEDG_FALLING		(2 << 8)
-#define			AT91_TC_EEVTEDG_BOTH		(3 << 8)
-#define		AT91_TC_EEVT		(3 << 10)	/* Waveform Mode: External Event Selection */
-#define			AT91_TC_EEVT_TIOB		(0 << 10)
-#define			AT91_TC_EEVT_XC0		(1 << 10)
-#define			AT91_TC_EEVT_XC1		(2 << 10)
-#define			AT91_TC_EEVT_XC2		(3 << 10)
-#define		AT91_TC_ENETRG		(1 << 12)	/* Waveform Mode: External Event Trigger Enable */
-#define		AT91_TC_WAVESEL		(3 << 13)	/* Waveform Mode: Waveform Selection */
-#define			AT91_TC_WAVESEL_UP		(0 << 13)
-#define			AT91_TC_WAVESEL_UP_AUTO		(2 << 13)
-#define			AT91_TC_WAVESEL_UPDOWN		(1 << 13)
-#define			AT91_TC_WAVESEL_UPDOWN_AUTO	(3 << 13)
-#define		AT91_TC_ACPA		(3 << 16)	/* Waveform Mode: RA Compare Effect on TIOA */
-#define			AT91_TC_ACPA_NONE		(0 << 16)
-#define			AT91_TC_ACPA_SET		(1 << 16)
-#define			AT91_TC_ACPA_CLEAR		(2 << 16)
-#define			AT91_TC_ACPA_TOGGLE		(3 << 16)
-#define		AT91_TC_ACPC		(3 << 18)	/* Waveform Mode: RC Compre Effect on TIOA */
-#define			AT91_TC_ACPC_NONE		(0 << 18)
-#define			AT91_TC_ACPC_SET		(1 << 18)
-#define			AT91_TC_ACPC_CLEAR		(2 << 18)
-#define			AT91_TC_ACPC_TOGGLE		(3 << 18)
-#define		AT91_TC_AEEVT		(3 << 20)	/* Waveform Mode: External Event Effect on TIOA */
-#define			AT91_TC_AEEVT_NONE		(0 << 20)
-#define			AT91_TC_AEEVT_SET		(1 << 20)
-#define			AT91_TC_AEEVT_CLEAR		(2 << 20)
-#define			AT91_TC_AEEVT_TOGGLE		(3 << 20)
-#define		AT91_TC_ASWTRG		(3 << 22)	/* Waveform Mode: Software Trigger Effect on TIOA */
-#define			AT91_TC_ASWTRG_NONE		(0 << 22)
-#define			AT91_TC_ASWTRG_SET		(1 << 22)
-#define			AT91_TC_ASWTRG_CLEAR		(2 << 22)
-#define			AT91_TC_ASWTRG_TOGGLE		(3 << 22)
-#define		AT91_TC_BCPB		(3 << 24)	/* Waveform Mode: RB Compare Effect on TIOB */
-#define			AT91_TC_BCPB_NONE		(0 << 24)
-#define			AT91_TC_BCPB_SET		(1 << 24)
-#define			AT91_TC_BCPB_CLEAR		(2 << 24)
-#define			AT91_TC_BCPB_TOGGLE		(3 << 24)
-#define		AT91_TC_BCPC		(3 << 26)	/* Waveform Mode: RC Compare Effect on TIOB */
-#define			AT91_TC_BCPC_NONE		(0 << 26)
-#define			AT91_TC_BCPC_SET		(1 << 26)
-#define			AT91_TC_BCPC_CLEAR		(2 << 26)
-#define			AT91_TC_BCPC_TOGGLE		(3 << 26)
-#define		AT91_TC_BEEVT		(3 << 28)	/* Waveform Mode: External Event Effect on TIOB */
-#define			AT91_TC_BEEVT_NONE		(0 << 28)
-#define			AT91_TC_BEEVT_SET		(1 << 28)
-#define			AT91_TC_BEEVT_CLEAR		(2 << 28)
-#define			AT91_TC_BEEVT_TOGGLE		(3 << 28)
-#define		AT91_TC_BSWTRG		(3 << 30)	/* Waveform Mode: Software Trigger Effect on TIOB */
-#define			AT91_TC_BSWTRG_NONE		(0 << 30)
-#define			AT91_TC_BSWTRG_SET		(1 << 30)
-#define			AT91_TC_BSWTRG_CLEAR		(2 << 30)
-#define			AT91_TC_BSWTRG_TOGGLE		(3 << 30)
+#define     AT91_TC_CPCSTOP     (1 <<  6)   /* Waveform Mode: Counter Clock Stopped with RC Compare */
+#define     AT91_TC_CPCDIS      (1 <<  7)   /* Waveform Mode: Counter Clock Disable with RC Compare */
+#define     AT91_TC_EEVTEDG     (3 <<  8)   /* Waveform Mode: External Event Edge Selection */
+#define         AT91_TC_EEVTEDG_NONE        (0 << 8)
+#define         AT91_TC_EEVTEDG_RISING      (1 << 8)
+#define         AT91_TC_EEVTEDG_FALLING     (2 << 8)
+#define         AT91_TC_EEVTEDG_BOTH        (3 << 8)
+#define     AT91_TC_EEVT        (3 << 10)   /* Waveform Mode: External Event Selection */
+#define         AT91_TC_EEVT_TIOB       (0 << 10)
+#define         AT91_TC_EEVT_XC0        (1 << 10)
+#define         AT91_TC_EEVT_XC1        (2 << 10)
+#define         AT91_TC_EEVT_XC2        (3 << 10)
+#define     AT91_TC_ENETRG      (1 << 12)   /* Waveform Mode: External Event Trigger Enable */
+#define     AT91_TC_WAVESEL     (3 << 13)   /* Waveform Mode: Waveform Selection */
+#define         AT91_TC_WAVESEL_UP      (0 << 13)
+#define         AT91_TC_WAVESEL_UP_AUTO     (2 << 13)
+#define         AT91_TC_WAVESEL_UPDOWN      (1 << 13)
+#define         AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
+#define     AT91_TC_ACPA        (3 << 16)   /* Waveform Mode: RA Compare Effect on TIOA */
+#define         AT91_TC_ACPA_NONE       (0 << 16)
+#define         AT91_TC_ACPA_SET        (1 << 16)
+#define         AT91_TC_ACPA_CLEAR      (2 << 16)
+#define         AT91_TC_ACPA_TOGGLE     (3 << 16)
+#define     AT91_TC_ACPC        (3 << 18)   /* Waveform Mode: RC Compre Effect on TIOA */
+#define         AT91_TC_ACPC_NONE       (0 << 18)
+#define         AT91_TC_ACPC_SET        (1 << 18)
+#define         AT91_TC_ACPC_CLEAR      (2 << 18)
+#define         AT91_TC_ACPC_TOGGLE     (3 << 18)
+#define     AT91_TC_AEEVT       (3 << 20)   /* Waveform Mode: External Event Effect on TIOA */
+#define         AT91_TC_AEEVT_NONE      (0 << 20)
+#define         AT91_TC_AEEVT_SET       (1 << 20)
+#define         AT91_TC_AEEVT_CLEAR     (2 << 20)
+#define         AT91_TC_AEEVT_TOGGLE        (3 << 20)
+#define     AT91_TC_ASWTRG      (3 << 22)   /* Waveform Mode: Software Trigger Effect on TIOA */
+#define         AT91_TC_ASWTRG_NONE     (0 << 22)
+#define         AT91_TC_ASWTRG_SET      (1 << 22)
+#define         AT91_TC_ASWTRG_CLEAR        (2 << 22)
+#define         AT91_TC_ASWTRG_TOGGLE       (3 << 22)
+#define     AT91_TC_BCPB        (3 << 24)   /* Waveform Mode: RB Compare Effect on TIOB */
+#define         AT91_TC_BCPB_NONE       (0 << 24)
+#define         AT91_TC_BCPB_SET        (1 << 24)
+#define         AT91_TC_BCPB_CLEAR      (2 << 24)
+#define         AT91_TC_BCPB_TOGGLE     (3 << 24)
+#define     AT91_TC_BCPC        (3 << 26)   /* Waveform Mode: RC Compare Effect on TIOB */
+#define         AT91_TC_BCPC_NONE       (0 << 26)
+#define         AT91_TC_BCPC_SET        (1 << 26)
+#define         AT91_TC_BCPC_CLEAR      (2 << 26)
+#define         AT91_TC_BCPC_TOGGLE     (3 << 26)
+#define     AT91_TC_BEEVT       (3 << 28)   /* Waveform Mode: External Event Effect on TIOB */
+#define         AT91_TC_BEEVT_NONE      (0 << 28)
+#define         AT91_TC_BEEVT_SET       (1 << 28)
+#define         AT91_TC_BEEVT_CLEAR     (2 << 28)
+#define         AT91_TC_BEEVT_TOGGLE        (3 << 28)
+#define     AT91_TC_BSWTRG      (3 << 30)   /* Waveform Mode: Software Trigger Effect on TIOB */
+#define         AT91_TC_BSWTRG_NONE     (0 << 30)
+#define         AT91_TC_BSWTRG_SET      (1 << 30)
+#define         AT91_TC_BSWTRG_CLEAR        (2 << 30)
+#define         AT91_TC_BSWTRG_TOGGLE       (3 << 30)
 
-#define AT91_TC_CV		0x10		/* Counter Value */
-#define AT91_TC_RA		0x14		/* Register A */
-#define AT91_TC_RB		0x18		/* Register B */
-#define AT91_TC_RC		0x1c		/* Register C */
+#define AT91_TC_CV      0x10        /* Counter Value */
+#define AT91_TC_RA      0x14        /* Register A */
+#define AT91_TC_RB      0x18        /* Register B */
+#define AT91_TC_RC      0x1c        /* Register C */
 
-#define AT91_TC_SR		0x20		/* Status Register */
-#define		AT91_TC_COVFS		(1 <<  0)	/* Counter Overflow Status */
-#define		AT91_TC_LOVRS		(1 <<  1)	/* Load Overrun Status */
-#define		AT91_TC_CPAS		(1 <<  2)	/* RA Compare Status */
-#define		AT91_TC_CPBS		(1 <<  3)	/* RB Compare Status */
-#define		AT91_TC_CPCS		(1 <<  4)	/* RC Compare Status */
-#define		AT91_TC_LDRAS		(1 <<  5)	/* RA Loading Status */
-#define		AT91_TC_LDRBS		(1 <<  6)	/* RB Loading Status */
-#define		AT91_TC_ETRGS		(1 <<  7)	/* External Trigger Status */
-#define		AT91_TC_CLKSTA		(1 << 16)	/* Clock Enabling Status */
-#define		AT91_TC_MTIOA		(1 << 17)	/* TIOA Mirror */
-#define		AT91_TC_MTIOB		(1 << 18)	/* TIOB Mirror */
+#define AT91_TC_SR      0x20        /* Status Register */
+#define     AT91_TC_COVFS       (1 <<  0)   /* Counter Overflow Status */
+#define     AT91_TC_LOVRS       (1 <<  1)   /* Load Overrun Status */
+#define     AT91_TC_CPAS        (1 <<  2)   /* RA Compare Status */
+#define     AT91_TC_CPBS        (1 <<  3)   /* RB Compare Status */
+#define     AT91_TC_CPCS        (1 <<  4)   /* RC Compare Status */
+#define     AT91_TC_LDRAS       (1 <<  5)   /* RA Loading Status */
+#define     AT91_TC_LDRBS       (1 <<  6)   /* RB Loading Status */
+#define     AT91_TC_ETRGS       (1 <<  7)   /* External Trigger Status */
+#define     AT91_TC_CLKSTA      (1 << 16)   /* Clock Enabling Status */
+#define     AT91_TC_MTIOA       (1 << 17)   /* TIOA Mirror */
+#define     AT91_TC_MTIOB       (1 << 18)   /* TIOB Mirror */
 
-#define AT91_TC_IER		0x24		/* Interrupt Enable Register */
-#define AT91_TC_IDR		0x28		/* Interrupt Disable Register */
-#define AT91_TC_IMR		0x2c		/* Interrupt Mask Register */
+#define AT91_TC_IER     0x24        /* Interrupt Enable Register */
+#define AT91_TC_IDR     0x28        /* Interrupt Disable Register */
+#define AT91_TC_IMR     0x2c        /* Interrupt Mask Register */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91sam9260_matrix.h

@@ -15,67 +15,67 @@
 extern "C" {
 #endif
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define		AT91_MATRIX_ULBT		(7 << 0)	/* Undefined Length Burst Type */
-#define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
-#define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
-#define			AT91_MATRIX_ULBT_FOUR		(2 << 0)
-#define			AT91_MATRIX_ULBT_EIGHT		(3 << 0)
-#define			AT91_MATRIX_ULBT_SIXTEEN	(4 << 0)
+#define AT91_MATRIX_MCFG0   (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1   (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2   (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3   (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4   (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5   (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define     AT91_MATRIX_ULBT        (7 << 0)    /* Undefined Length Burst Type */
+#define         AT91_MATRIX_ULBT_INFINITE   (0 << 0)
+#define         AT91_MATRIX_ULBT_SINGLE     (1 << 0)
+#define         AT91_MATRIX_ULBT_FOUR       (2 << 0)
+#define         AT91_MATRIX_ULBT_EIGHT      (3 << 0)
+#define         AT91_MATRIX_ULBT_SIXTEEN    (4 << 0)
 
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define		AT91_MATRIX_SLOT_CYCLE		(0xff <<  0)	/* Maximum Number of Allowed Cycles for a Burst */
-#define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
-#define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_LAST	(1 << 16)
-#define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
-#define		AT91_MATRIX_FIXED_DEFMSTR	(7    << 18)	/* Fixed Index of Default Master */
-#define		AT91_MATRIX_ARBT		(3    << 24)	/* Arbitration Type */
-#define			AT91_MATRIX_ARBT_ROUND_ROBIN	(0 << 24)
-#define			AT91_MATRIX_ARBT_FIXED_PRIORITY	(1 << 24)
+#define AT91_MATRIX_SCFG0   (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1   (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2   (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3   (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4   (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define     AT91_MATRIX_SLOT_CYCLE      (0xff <<  0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define     AT91_MATRIX_DEFMSTR_TYPE    (3    << 16)    /* Default Master Type */
+#define         AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define         AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define         AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define     AT91_MATRIX_FIXED_DEFMSTR   (7    << 18)    /* Fixed Index of Default Master */
+#define     AT91_MATRIX_ARBT        (3    << 24)    /* Arbitration Type */
+#define         AT91_MATRIX_ARBT_ROUND_ROBIN    (0 << 24)
+#define         AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
 
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
-#define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
-#define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
-#define		AT91_MATRIX_M3PR		(3 << 12)	/* Master 3 Priority */
-#define		AT91_MATRIX_M4PR		(3 << 16)	/* Master 4 Priority */
-#define		AT91_MATRIX_M5PR		(3 << 20)	/* Master 5 Priority */
+#define AT91_MATRIX_PRAS0   (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRAS1   (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRAS2   (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRAS3   (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRAS4   (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define     AT91_MATRIX_M0PR        (3 << 0)    /* Master 0 Priority */
+#define     AT91_MATRIX_M1PR        (3 << 4)    /* Master 1 Priority */
+#define     AT91_MATRIX_M2PR        (3 << 8)    /* Master 2 Priority */
+#define     AT91_MATRIX_M3PR        (3 << 12)   /* Master 3 Priority */
+#define     AT91_MATRIX_M4PR        (3 << 16)   /* Master 4 Priority */
+#define     AT91_MATRIX_M5PR        (3 << 20)   /* Master 5 Priority */
 
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
-#define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91_MATRIX_MRCR    (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define     AT91_MATRIX_RCB0        (1 << 0)    /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define     AT91_MATRIX_RCB1        (1 << 1)    /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x11C)	/* EBI Chip Select Assignment Register */
-#define		AT91_MATRIX_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
-#define			AT91_MATRIX_CS1A_SMC		(0 << 1)
-#define			AT91_MATRIX_CS1A_SDRAMC		(1 << 1)
-#define		AT91_MATRIX_CS3A		(1 << 3)	/* Chip Select 3 Assignment */
-#define			AT91_MATRIX_CS3A_SMC		(0 << 3)
-#define			AT91_MATRIX_CS3A_SMC_SMARTMEDIA	(1 << 3)
-#define		AT91_MATRIX_CS4A		(1 << 4)	/* Chip Select 4 Assignment */
-#define			AT91_MATRIX_CS4A_SMC		(0 << 4)
-#define			AT91_MATRIX_CS4A_SMC_CF1	(1 << 4)
-#define		AT91_MATRIX_CS5A		(1 << 5)	/* Chip Select 5 Assignment */
-#define			AT91_MATRIX_CS5A_SMC		(0 << 5)
-#define			AT91_MATRIX_CS5A_SMC_CF2	(1 << 5)
-#define		AT91_MATRIX_DBPUC		(1 << 8)	/* Data Bus Pull-up Configuration */
-#define		AT91_MATRIX_VDDIOMSEL		(1 << 16)	/* Memory voltage selection */
-#define			AT91_MATRIX_VDDIOMSEL_1_8V	(0 << 16)
-#define			AT91_MATRIX_VDDIOMSEL_3_3V	(1 << 16)
+#define AT91_MATRIX_EBICSA  (AT91_MATRIX + 0x11C)   /* EBI Chip Select Assignment Register */
+#define     AT91_MATRIX_CS1A        (1 << 1)    /* Chip Select 1 Assignment */
+#define         AT91_MATRIX_CS1A_SMC        (0 << 1)
+#define         AT91_MATRIX_CS1A_SDRAMC     (1 << 1)
+#define     AT91_MATRIX_CS3A        (1 << 3)    /* Chip Select 3 Assignment */
+#define         AT91_MATRIX_CS3A_SMC        (0 << 3)
+#define         AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define     AT91_MATRIX_CS4A        (1 << 4)    /* Chip Select 4 Assignment */
+#define         AT91_MATRIX_CS4A_SMC        (0 << 4)
+#define         AT91_MATRIX_CS4A_SMC_CF1    (1 << 4)
+#define     AT91_MATRIX_CS5A        (1 << 5)    /* Chip Select 5 Assignment */
+#define         AT91_MATRIX_CS5A_SMC        (0 << 5)
+#define         AT91_MATRIX_CS5A_SMC_CF2    (1 << 5)
+#define     AT91_MATRIX_DBPUC       (1 << 8)    /* Data Bus Pull-up Configuration */
+#define     AT91_MATRIX_VDDIOMSEL       (1 << 16)   /* Memory voltage selection */
+#define         AT91_MATRIX_VDDIOMSEL_1_8V  (0 << 16)
+#define         AT91_MATRIX_VDDIOMSEL_3_3V  (1 << 16)
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/at91sam926x.h

@@ -33,169 +33,169 @@ extern "C" {
 /*
  * Peripheral identifiers/interrupts.
  */
-#define AT91_ID_FIQ		0	/* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS		1	/* System Peripherals */
-#define AT91SAM9260_ID_PIOA	2	/* Parallel IO Controller A */
-#define AT91SAM9260_ID_PIOB	3	/* Parallel IO Controller B */
-#define AT91SAM9260_ID_PIOC	4	/* Parallel IO Controller C */
-#define AT91SAM9260_ID_ADC	5	/* Analog-to-Digital Converter */
-#define AT91SAM9260_ID_US0	6	/* USART 0 */
-#define AT91SAM9260_ID_US1	7	/* USART 1 */
-#define AT91SAM9260_ID_US2	8	/* USART 2 */
-#define AT91SAM9260_ID_MCI	9	/* Multimedia Card Interface */
-#define AT91SAM9260_ID_UDP	10	/* USB Device Port */
-#define AT91SAM9260_ID_TWI	11	/* Two-Wire Interface */
-#define AT91SAM9260_ID_SPI0	12	/* Serial Peripheral Interface 0 */
-#define AT91SAM9260_ID_SPI1	13	/* Serial Peripheral Interface 1 */
-#define AT91SAM9260_ID_SSC	14	/* Serial Synchronous Controller */
-#define AT91SAM9260_ID_TC0	17	/* Timer Counter 0 */
-#define AT91SAM9260_ID_TC1	18	/* Timer Counter 1 */
-#define AT91SAM9260_ID_TC2	19	/* Timer Counter 2 */
-#define AT91SAM9260_ID_UHP	20	/* USB Host port */
-#define AT91SAM9260_ID_EMAC	21	/* Ethernet */
-#define AT91SAM9260_ID_ISI	22	/* Image Sensor Interface */
-#define AT91SAM9260_ID_US3	23	/* USART 3 */
-#define AT91SAM9260_ID_US4	24	/* USART 4 */
-#define AT91SAM9260_ID_US5	25	/* USART 5 */
-#define AT91SAM9260_ID_TC3	26	/* Timer Counter 3 */
-#define AT91SAM9260_ID_TC4	27	/* Timer Counter 4 */
-#define AT91SAM9260_ID_TC5	28	/* Timer Counter 5 */
-#define AT91SAM9260_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */
+#define AT91_ID_FIQ     0   /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS     1   /* System Peripherals */
+#define AT91SAM9260_ID_PIOA 2   /* Parallel IO Controller A */
+#define AT91SAM9260_ID_PIOB 3   /* Parallel IO Controller B */
+#define AT91SAM9260_ID_PIOC 4   /* Parallel IO Controller C */
+#define AT91SAM9260_ID_ADC  5   /* Analog-to-Digital Converter */
+#define AT91SAM9260_ID_US0  6   /* USART 0 */
+#define AT91SAM9260_ID_US1  7   /* USART 1 */
+#define AT91SAM9260_ID_US2  8   /* USART 2 */
+#define AT91SAM9260_ID_MCI  9   /* Multimedia Card Interface */
+#define AT91SAM9260_ID_UDP  10  /* USB Device Port */
+#define AT91SAM9260_ID_TWI  11  /* Two-Wire Interface */
+#define AT91SAM9260_ID_SPI0 12  /* Serial Peripheral Interface 0 */
+#define AT91SAM9260_ID_SPI1 13  /* Serial Peripheral Interface 1 */
+#define AT91SAM9260_ID_SSC  14  /* Serial Synchronous Controller */
+#define AT91SAM9260_ID_TC0  17  /* Timer Counter 0 */
+#define AT91SAM9260_ID_TC1  18  /* Timer Counter 1 */
+#define AT91SAM9260_ID_TC2  19  /* Timer Counter 2 */
+#define AT91SAM9260_ID_UHP  20  /* USB Host port */
+#define AT91SAM9260_ID_EMAC 21  /* Ethernet */
+#define AT91SAM9260_ID_ISI  22  /* Image Sensor Interface */
+#define AT91SAM9260_ID_US3  23  /* USART 3 */
+#define AT91SAM9260_ID_US4  24  /* USART 4 */
+#define AT91SAM9260_ID_US5  25  /* USART 5 */
+#define AT91SAM9260_ID_TC3  26  /* Timer Counter 3 */
+#define AT91SAM9260_ID_TC4  27  /* Timer Counter 4 */
+#define AT91SAM9260_ID_TC5  28  /* Timer Counter 5 */
+#define AT91SAM9260_ID_IRQ0 29  /* Advanced Interrupt Controller (IRQ0) */
+#define AT91SAM9260_ID_IRQ1 30  /* Advanced Interrupt Controller (IRQ1) */
+#define AT91SAM9260_ID_IRQ2 31  /* Advanced Interrupt Controller (IRQ2) */
 
 
 /*
  * User Peripheral physical base addresses.
  */
-#define AT91SAM9260_BASE_TCB0		0xfffa0000
-#define AT91SAM9260_BASE_TC0		0xfffa0000
-#define AT91SAM9260_BASE_TC1		0xfffa0040
-#define AT91SAM9260_BASE_TC2		0xfffa0080
-#define AT91SAM9260_BASE_UDP		0xfffa4000
-#define AT91SAM9260_BASE_MCI		0xfffa8000
-#define AT91SAM9260_BASE_TWI		0xfffac000
-#define AT91SAM9260_BASE_US0		0xfffb0000
-#define AT91SAM9260_BASE_US1		0xfffb4000
-#define AT91SAM9260_BASE_US2		0xfffb8000
-#define AT91SAM9260_BASE_SSC		0xfffbc000
-#define AT91SAM9260_BASE_ISI		0xfffc0000
-#define AT91SAM9260_BASE_EMAC		0xfffc4000
-#define AT91SAM9260_BASE_SPI0		0xfffc8000
-#define AT91SAM9260_BASE_SPI1		0xfffcc000
-#define AT91SAM9260_BASE_US3		0xfffd0000
-#define AT91SAM9260_BASE_US4		0xfffd4000
-#define AT91SAM9260_BASE_US5		0xfffd8000
-#define AT91SAM9260_BASE_TCB1		0xfffdc000
-#define AT91SAM9260_BASE_TC3		0xfffdc000
-#define AT91SAM9260_BASE_TC4		0xfffdc040
-#define AT91SAM9260_BASE_TC5		0xfffdc080
-#define AT91SAM9260_BASE_ADC		0xfffe0000
-#define AT91_BASE_SYS				0xffffe800
-#define AT91SAM9260_BASE_DBGU		0xfffff200
+#define AT91SAM9260_BASE_TCB0       0xfffa0000
+#define AT91SAM9260_BASE_TC0        0xfffa0000
+#define AT91SAM9260_BASE_TC1        0xfffa0040
+#define AT91SAM9260_BASE_TC2        0xfffa0080
+#define AT91SAM9260_BASE_UDP        0xfffa4000
+#define AT91SAM9260_BASE_MCI        0xfffa8000
+#define AT91SAM9260_BASE_TWI        0xfffac000
+#define AT91SAM9260_BASE_US0        0xfffb0000
+#define AT91SAM9260_BASE_US1        0xfffb4000
+#define AT91SAM9260_BASE_US2        0xfffb8000
+#define AT91SAM9260_BASE_SSC        0xfffbc000
+#define AT91SAM9260_BASE_ISI        0xfffc0000
+#define AT91SAM9260_BASE_EMAC       0xfffc4000
+#define AT91SAM9260_BASE_SPI0       0xfffc8000
+#define AT91SAM9260_BASE_SPI1       0xfffcc000
+#define AT91SAM9260_BASE_US3        0xfffd0000
+#define AT91SAM9260_BASE_US4        0xfffd4000
+#define AT91SAM9260_BASE_US5        0xfffd8000
+#define AT91SAM9260_BASE_TCB1       0xfffdc000
+#define AT91SAM9260_BASE_TC3        0xfffdc000
+#define AT91SAM9260_BASE_TC4        0xfffdc040
+#define AT91SAM9260_BASE_TC5        0xfffdc080
+#define AT91SAM9260_BASE_ADC        0xfffe0000
+#define AT91_BASE_SYS               0xffffe800
+#define AT91SAM9260_BASE_DBGU       0xfffff200
 
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_ECC	(0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC	(0xffffea00 - AT91_BASE_SYS)
-#define AT91_SMC	(0xffffec00 - AT91_BASE_SYS)
-#define AT91_MATRIX	(0xffffee00 - AT91_BASE_SYS)
-#define AT91_CCFG	(0xffffef10 - AT91_BASE_SYS)
-#define AT91_AIC	(0xfffff000 - AT91_BASE_SYS)
-#define AT91_DBGU	(0xfffff200 - AT91_BASE_SYS)
-#define AT91_PIOA	(0xfffff400 - AT91_BASE_SYS)
-#define AT91_PIOB	(0xfffff600 - AT91_BASE_SYS)
-#define AT91_PIOC	(0xfffff800 - AT91_BASE_SYS)
-#define AT91_PMC	(0xfffffc00 - AT91_BASE_SYS)
-#define AT91_RSTC	(0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC	(0xfffffd10 - AT91_BASE_SYS)
-#define AT91_RTT	(0xfffffd20 - AT91_BASE_SYS)
-#define AT91_PIT	(0xfffffd30 - AT91_BASE_SYS)
-#define AT91_WDT	(0xfffffd40 - AT91_BASE_SYS)
-#define AT91_GPBR	(0xfffffd50 - AT91_BASE_SYS)
+#define AT91_ECC    (0xffffe800 - AT91_BASE_SYS)
+#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SMC    (0xffffec00 - AT91_BASE_SYS)
+#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
+#define AT91_CCFG   (0xffffef10 - AT91_BASE_SYS)
+#define AT91_AIC    (0xfffff000 - AT91_BASE_SYS)
+#define AT91_DBGU   (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOA   (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOB   (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOC   (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PMC    (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC   (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC  (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT    (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT    (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT    (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR   (0xfffffd50 - AT91_BASE_SYS)
 
 
 /*
  * Internal Memory.
  */
-#define AT91SAM9260_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9260_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
+#define AT91SAM9260_ROM_BASE    0x00100000  /* Internal ROM base address */
+#define AT91SAM9260_ROM_SIZE    SZ_32K      /* Internal ROM size (32Kb) */
 
-#define AT91SAM9260_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9260_SRAM0_SIZE	SZ_4K		/* Internal SRAM 0 size (4Kb) */
-#define AT91SAM9260_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9260_SRAM1_SIZE	SZ_4K		/* Internal SRAM 1 size (4Kb) */
+#define AT91SAM9260_SRAM0_BASE  0x00200000  /* Internal SRAM 0 base address */
+#define AT91SAM9260_SRAM0_SIZE  SZ_4K       /* Internal SRAM 0 size (4Kb) */
+#define AT91SAM9260_SRAM1_BASE  0x00300000  /* Internal SRAM 1 base address */
+#define AT91SAM9260_SRAM1_SIZE  SZ_4K       /* Internal SRAM 1 size (4Kb) */
 
-#define AT91SAM9260_UHP_BASE	0x00500000	/* USB Host controller */
+#define AT91SAM9260_UHP_BASE    0x00500000  /* USB Host controller */
 
-#define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */
-#define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */
+#define AT91SAM9XE_FLASH_BASE   0x00200000  /* Internal FLASH base address */
+#define AT91SAM9XE_SRAM_BASE    0x00300000  /* Internal SRAM base address */
 
-#define AT91SAM9G20_ROM_BASE	0x00100000	/* Internal ROM base address */
-#define AT91SAM9G20_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */
+#define AT91SAM9G20_ROM_BASE    0x00100000  /* Internal ROM base address */
+#define AT91SAM9G20_ROM_SIZE    SZ_32K      /* Internal ROM size (32Kb) */
 
-#define AT91SAM9G20_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */
-#define AT91SAM9G20_SRAM0_SIZE	SZ_16K		/* Internal SRAM 0 size (16Kb) */
-#define AT91SAM9G20_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */
-#define AT91SAM9G20_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */
+#define AT91SAM9G20_SRAM0_BASE  0x00200000  /* Internal SRAM 0 base address */
+#define AT91SAM9G20_SRAM0_SIZE  SZ_16K      /* Internal SRAM 0 size (16Kb) */
+#define AT91SAM9G20_SRAM1_BASE  0x00300000  /* Internal SRAM 1 base address */
+#define AT91SAM9G20_SRAM1_SIZE  SZ_16K      /* Internal SRAM 1 size (16Kb) */
 
-#define AT91SAM9G20_UHP_BASE	0x00500000	/* USB Host controller */
+#define AT91SAM9G20_UHP_BASE    0x00500000  /* USB Host controller */
 
 
 
 /* Serial ports */
-#define ATMEL_MAX_UART		7		/* 6 USART3's and one DBGU port (SAM9260) */
+#define ATMEL_MAX_UART      7       /* 6 USART3's and one DBGU port (SAM9260) */
 
 /* External Memory Map */
-#define AT91_CHIPSELECT_0	0x10000000
-#define AT91_CHIPSELECT_1	0x20000000
-#define AT91_CHIPSELECT_2	0x30000000
-#define AT91_CHIPSELECT_3	0x40000000
-#define AT91_CHIPSELECT_4	0x50000000
-#define AT91_CHIPSELECT_5	0x60000000
-#define AT91_CHIPSELECT_6	0x70000000
-#define AT91_CHIPSELECT_7	0x80000000
+#define AT91_CHIPSELECT_0   0x10000000
+#define AT91_CHIPSELECT_1   0x20000000
+#define AT91_CHIPSELECT_2   0x30000000
+#define AT91_CHIPSELECT_3   0x40000000
+#define AT91_CHIPSELECT_4   0x50000000
+#define AT91_CHIPSELECT_5   0x60000000
+#define AT91_CHIPSELECT_6   0x70000000
+#define AT91_CHIPSELECT_7   0x80000000
 
 /* SDRAM */
-#define AT91_SDRAM_BASE		AT91_CHIPSELECT_1
+#define AT91_SDRAM_BASE     AT91_CHIPSELECT_1
 
 /* Clocks */
-#define AT91_SLOW_CLOCK		32768		/* slow clock */
+#define AT91_SLOW_CLOCK     32768       /* slow clock */
 
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE		0x10
-#define FIQMODE			0x11
-#define IRQMODE			0x12
-#define SVCMODE			0x13
-#define ABORTMODE		0x17
-#define UNDEFMODE		0x1b
-#define MODEMASK		0x1f
-#define NOINT			0xc0
+#define USERMODE        0x10
+#define FIQMODE         0x11
+#define IRQMODE         0x12
+#define SVCMODE         0x13
+#define ABORTMODE       0x17
+#define UNDEFMODE       0x1b
+#define MODEMASK        0x1f
+#define NOINT           0xc0
 
 struct rt_hw_register
 {
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t cpsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t cpsr;
+    rt_uint32_t ORIG_r0;
 };
 
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))

bsp/at91sam9260/platform/gpio.h

@@ -14,117 +14,117 @@
 #include <rtthread.h>
 #include <at91_aic.h>
 
-#define PIN_BASE		AIC_IRQS
+#define PIN_BASE        AIC_IRQS
 
-#define MAX_GPIO_BANKS		3
+#define MAX_GPIO_BANKS      3
 
-#define PIN_IRQS	(MAX_GPIO_BANKS*32)
+#define PIN_IRQS    (MAX_GPIO_BANKS*32)
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
-#define	AT91_PIN_PA0	(PIN_BASE + 0x00 + 0)
-#define	AT91_PIN_PA1	(PIN_BASE + 0x00 + 1)
-#define	AT91_PIN_PA2	(PIN_BASE + 0x00 + 2)
-#define	AT91_PIN_PA3	(PIN_BASE + 0x00 + 3)
-#define	AT91_PIN_PA4	(PIN_BASE + 0x00 + 4)
-#define	AT91_PIN_PA5	(PIN_BASE + 0x00 + 5)
-#define	AT91_PIN_PA6	(PIN_BASE + 0x00 + 6)
-#define	AT91_PIN_PA7	(PIN_BASE + 0x00 + 7)
-#define	AT91_PIN_PA8	(PIN_BASE + 0x00 + 8)
-#define	AT91_PIN_PA9	(PIN_BASE + 0x00 + 9)
-#define	AT91_PIN_PA10	(PIN_BASE + 0x00 + 10)
-#define	AT91_PIN_PA11	(PIN_BASE + 0x00 + 11)
-#define	AT91_PIN_PA12	(PIN_BASE + 0x00 + 12)
-#define	AT91_PIN_PA13	(PIN_BASE + 0x00 + 13)
-#define	AT91_PIN_PA14	(PIN_BASE + 0x00 + 14)
-#define	AT91_PIN_PA15	(PIN_BASE + 0x00 + 15)
-#define	AT91_PIN_PA16	(PIN_BASE + 0x00 + 16)
-#define	AT91_PIN_PA17	(PIN_BASE + 0x00 + 17)
-#define	AT91_PIN_PA18	(PIN_BASE + 0x00 + 18)
-#define	AT91_PIN_PA19	(PIN_BASE + 0x00 + 19)
-#define	AT91_PIN_PA20	(PIN_BASE + 0x00 + 20)
-#define	AT91_PIN_PA21	(PIN_BASE + 0x00 + 21)
-#define	AT91_PIN_PA22	(PIN_BASE + 0x00 + 22)
-#define	AT91_PIN_PA23	(PIN_BASE + 0x00 + 23)
-#define	AT91_PIN_PA24	(PIN_BASE + 0x00 + 24)
-#define	AT91_PIN_PA25	(PIN_BASE + 0x00 + 25)
-#define	AT91_PIN_PA26	(PIN_BASE + 0x00 + 26)
-#define	AT91_PIN_PA27	(PIN_BASE + 0x00 + 27)
-#define	AT91_PIN_PA28	(PIN_BASE + 0x00 + 28)
-#define	AT91_PIN_PA29	(PIN_BASE + 0x00 + 29)
-#define	AT91_PIN_PA30	(PIN_BASE + 0x00 + 30)
-#define	AT91_PIN_PA31	(PIN_BASE + 0x00 + 31)
+#define AT91_PIN_PA0    (PIN_BASE + 0x00 + 0)
+#define AT91_PIN_PA1    (PIN_BASE + 0x00 + 1)
+#define AT91_PIN_PA2    (PIN_BASE + 0x00 + 2)
+#define AT91_PIN_PA3    (PIN_BASE + 0x00 + 3)
+#define AT91_PIN_PA4    (PIN_BASE + 0x00 + 4)
+#define AT91_PIN_PA5    (PIN_BASE + 0x00 + 5)
+#define AT91_PIN_PA6    (PIN_BASE + 0x00 + 6)
+#define AT91_PIN_PA7    (PIN_BASE + 0x00 + 7)
+#define AT91_PIN_PA8    (PIN_BASE + 0x00 + 8)
+#define AT91_PIN_PA9    (PIN_BASE + 0x00 + 9)
+#define AT91_PIN_PA10   (PIN_BASE + 0x00 + 10)
+#define AT91_PIN_PA11   (PIN_BASE + 0x00 + 11)
+#define AT91_PIN_PA12   (PIN_BASE + 0x00 + 12)
+#define AT91_PIN_PA13   (PIN_BASE + 0x00 + 13)
+#define AT91_PIN_PA14   (PIN_BASE + 0x00 + 14)
+#define AT91_PIN_PA15   (PIN_BASE + 0x00 + 15)
+#define AT91_PIN_PA16   (PIN_BASE + 0x00 + 16)
+#define AT91_PIN_PA17   (PIN_BASE + 0x00 + 17)
+#define AT91_PIN_PA18   (PIN_BASE + 0x00 + 18)
+#define AT91_PIN_PA19   (PIN_BASE + 0x00 + 19)
+#define AT91_PIN_PA20   (PIN_BASE + 0x00 + 20)
+#define AT91_PIN_PA21   (PIN_BASE + 0x00 + 21)
+#define AT91_PIN_PA22   (PIN_BASE + 0x00 + 22)
+#define AT91_PIN_PA23   (PIN_BASE + 0x00 + 23)
+#define AT91_PIN_PA24   (PIN_BASE + 0x00 + 24)
+#define AT91_PIN_PA25   (PIN_BASE + 0x00 + 25)
+#define AT91_PIN_PA26   (PIN_BASE + 0x00 + 26)
+#define AT91_PIN_PA27   (PIN_BASE + 0x00 + 27)
+#define AT91_PIN_PA28   (PIN_BASE + 0x00 + 28)
+#define AT91_PIN_PA29   (PIN_BASE + 0x00 + 29)
+#define AT91_PIN_PA30   (PIN_BASE + 0x00 + 30)
+#define AT91_PIN_PA31   (PIN_BASE + 0x00 + 31)
 
-#define	AT91_PIN_PB0	(PIN_BASE + 0x20 + 0)
-#define	AT91_PIN_PB1	(PIN_BASE + 0x20 + 1)
-#define	AT91_PIN_PB2	(PIN_BASE + 0x20 + 2)
-#define	AT91_PIN_PB3	(PIN_BASE + 0x20 + 3)
-#define	AT91_PIN_PB4	(PIN_BASE + 0x20 + 4)
-#define	AT91_PIN_PB5	(PIN_BASE + 0x20 + 5)
-#define	AT91_PIN_PB6	(PIN_BASE + 0x20 + 6)
-#define	AT91_PIN_PB7	(PIN_BASE + 0x20 + 7)
-#define	AT91_PIN_PB8	(PIN_BASE + 0x20 + 8)
-#define	AT91_PIN_PB9	(PIN_BASE + 0x20 + 9)
-#define	AT91_PIN_PB10	(PIN_BASE + 0x20 + 10)
-#define	AT91_PIN_PB11	(PIN_BASE + 0x20 + 11)
-#define	AT91_PIN_PB12	(PIN_BASE + 0x20 + 12)
-#define	AT91_PIN_PB13	(PIN_BASE + 0x20 + 13)
-#define	AT91_PIN_PB14	(PIN_BASE + 0x20 + 14)
-#define	AT91_PIN_PB15	(PIN_BASE + 0x20 + 15)
-#define	AT91_PIN_PB16	(PIN_BASE + 0x20 + 16)
-#define	AT91_PIN_PB17	(PIN_BASE + 0x20 + 17)
-#define	AT91_PIN_PB18	(PIN_BASE + 0x20 + 18)
-#define	AT91_PIN_PB19	(PIN_BASE + 0x20 + 19)
-#define	AT91_PIN_PB20	(PIN_BASE + 0x20 + 20)
-#define	AT91_PIN_PB21	(PIN_BASE + 0x20 + 21)
-#define	AT91_PIN_PB22	(PIN_BASE + 0x20 + 22)
-#define	AT91_PIN_PB23	(PIN_BASE + 0x20 + 23)
-#define	AT91_PIN_PB24	(PIN_BASE + 0x20 + 24)
-#define	AT91_PIN_PB25	(PIN_BASE + 0x20 + 25)
-#define	AT91_PIN_PB26	(PIN_BASE + 0x20 + 26)
-#define	AT91_PIN_PB27	(PIN_BASE + 0x20 + 27)
-#define	AT91_PIN_PB28	(PIN_BASE + 0x20 + 28)
-#define	AT91_PIN_PB29	(PIN_BASE + 0x20 + 29)
-#define	AT91_PIN_PB30	(PIN_BASE + 0x20 + 30)
-#define	AT91_PIN_PB31	(PIN_BASE + 0x20 + 31)
+#define AT91_PIN_PB0    (PIN_BASE + 0x20 + 0)
+#define AT91_PIN_PB1    (PIN_BASE + 0x20 + 1)
+#define AT91_PIN_PB2    (PIN_BASE + 0x20 + 2)
+#define AT91_PIN_PB3    (PIN_BASE + 0x20 + 3)
+#define AT91_PIN_PB4    (PIN_BASE + 0x20 + 4)
+#define AT91_PIN_PB5    (PIN_BASE + 0x20 + 5)
+#define AT91_PIN_PB6    (PIN_BASE + 0x20 + 6)
+#define AT91_PIN_PB7    (PIN_BASE + 0x20 + 7)
+#define AT91_PIN_PB8    (PIN_BASE + 0x20 + 8)
+#define AT91_PIN_PB9    (PIN_BASE + 0x20 + 9)
+#define AT91_PIN_PB10   (PIN_BASE + 0x20 + 10)
+#define AT91_PIN_PB11   (PIN_BASE + 0x20 + 11)
+#define AT91_PIN_PB12   (PIN_BASE + 0x20 + 12)
+#define AT91_PIN_PB13   (PIN_BASE + 0x20 + 13)
+#define AT91_PIN_PB14   (PIN_BASE + 0x20 + 14)
+#define AT91_PIN_PB15   (PIN_BASE + 0x20 + 15)
+#define AT91_PIN_PB16   (PIN_BASE + 0x20 + 16)
+#define AT91_PIN_PB17   (PIN_BASE + 0x20 + 17)
+#define AT91_PIN_PB18   (PIN_BASE + 0x20 + 18)
+#define AT91_PIN_PB19   (PIN_BASE + 0x20 + 19)
+#define AT91_PIN_PB20   (PIN_BASE + 0x20 + 20)
+#define AT91_PIN_PB21   (PIN_BASE + 0x20 + 21)
+#define AT91_PIN_PB22   (PIN_BASE + 0x20 + 22)
+#define AT91_PIN_PB23   (PIN_BASE + 0x20 + 23)
+#define AT91_PIN_PB24   (PIN_BASE + 0x20 + 24)
+#define AT91_PIN_PB25   (PIN_BASE + 0x20 + 25)
+#define AT91_PIN_PB26   (PIN_BASE + 0x20 + 26)
+#define AT91_PIN_PB27   (PIN_BASE + 0x20 + 27)
+#define AT91_PIN_PB28   (PIN_BASE + 0x20 + 28)
+#define AT91_PIN_PB29   (PIN_BASE + 0x20 + 29)
+#define AT91_PIN_PB30   (PIN_BASE + 0x20 + 30)
+#define AT91_PIN_PB31   (PIN_BASE + 0x20 + 31)
 
-#define	AT91_PIN_PC0	(PIN_BASE + 0x40 + 0)
-#define	AT91_PIN_PC1	(PIN_BASE + 0x40 + 1)
-#define	AT91_PIN_PC2	(PIN_BASE + 0x40 + 2)
-#define	AT91_PIN_PC3	(PIN_BASE + 0x40 + 3)
-#define	AT91_PIN_PC4	(PIN_BASE + 0x40 + 4)
-#define	AT91_PIN_PC5	(PIN_BASE + 0x40 + 5)
-#define	AT91_PIN_PC6	(PIN_BASE + 0x40 + 6)
-#define	AT91_PIN_PC7	(PIN_BASE + 0x40 + 7)
-#define	AT91_PIN_PC8	(PIN_BASE + 0x40 + 8)
-#define	AT91_PIN_PC9	(PIN_BASE + 0x40 + 9)
-#define	AT91_PIN_PC10	(PIN_BASE + 0x40 + 10)
-#define	AT91_PIN_PC11	(PIN_BASE + 0x40 + 11)
-#define	AT91_PIN_PC12	(PIN_BASE + 0x40 + 12)
-#define	AT91_PIN_PC13	(PIN_BASE + 0x40 + 13)
-#define	AT91_PIN_PC14	(PIN_BASE + 0x40 + 14)
-#define	AT91_PIN_PC15	(PIN_BASE + 0x40 + 15)
-#define	AT91_PIN_PC16	(PIN_BASE + 0x40 + 16)
-#define	AT91_PIN_PC17	(PIN_BASE + 0x40 + 17)
-#define	AT91_PIN_PC18	(PIN_BASE + 0x40 + 18)
-#define	AT91_PIN_PC19	(PIN_BASE + 0x40 + 19)
-#define	AT91_PIN_PC20	(PIN_BASE + 0x40 + 20)
-#define	AT91_PIN_PC21	(PIN_BASE + 0x40 + 21)
-#define	AT91_PIN_PC22	(PIN_BASE + 0x40 + 22)
-#define	AT91_PIN_PC23	(PIN_BASE + 0x40 + 23)
-#define	AT91_PIN_PC24	(PIN_BASE + 0x40 + 24)
-#define	AT91_PIN_PC25	(PIN_BASE + 0x40 + 25)
-#define	AT91_PIN_PC26	(PIN_BASE + 0x40 + 26)
-#define	AT91_PIN_PC27	(PIN_BASE + 0x40 + 27)
-#define	AT91_PIN_PC28	(PIN_BASE + 0x40 + 28)
-#define	AT91_PIN_PC29	(PIN_BASE + 0x40 + 29)
-#define	AT91_PIN_PC30	(PIN_BASE + 0x40 + 30)
-#define	AT91_PIN_PC31	(PIN_BASE + 0x40 + 31)
+#define AT91_PIN_PC0    (PIN_BASE + 0x40 + 0)
+#define AT91_PIN_PC1    (PIN_BASE + 0x40 + 1)
+#define AT91_PIN_PC2    (PIN_BASE + 0x40 + 2)
+#define AT91_PIN_PC3    (PIN_BASE + 0x40 + 3)
+#define AT91_PIN_PC4    (PIN_BASE + 0x40 + 4)
+#define AT91_PIN_PC5    (PIN_BASE + 0x40 + 5)
+#define AT91_PIN_PC6    (PIN_BASE + 0x40 + 6)
+#define AT91_PIN_PC7    (PIN_BASE + 0x40 + 7)
+#define AT91_PIN_PC8    (PIN_BASE + 0x40 + 8)
+#define AT91_PIN_PC9    (PIN_BASE + 0x40 + 9)
+#define AT91_PIN_PC10   (PIN_BASE + 0x40 + 10)
+#define AT91_PIN_PC11   (PIN_BASE + 0x40 + 11)
+#define AT91_PIN_PC12   (PIN_BASE + 0x40 + 12)
+#define AT91_PIN_PC13   (PIN_BASE + 0x40 + 13)
+#define AT91_PIN_PC14   (PIN_BASE + 0x40 + 14)
+#define AT91_PIN_PC15   (PIN_BASE + 0x40 + 15)
+#define AT91_PIN_PC16   (PIN_BASE + 0x40 + 16)
+#define AT91_PIN_PC17   (PIN_BASE + 0x40 + 17)
+#define AT91_PIN_PC18   (PIN_BASE + 0x40 + 18)
+#define AT91_PIN_PC19   (PIN_BASE + 0x40 + 19)
+#define AT91_PIN_PC20   (PIN_BASE + 0x40 + 20)
+#define AT91_PIN_PC21   (PIN_BASE + 0x40 + 21)
+#define AT91_PIN_PC22   (PIN_BASE + 0x40 + 22)
+#define AT91_PIN_PC23   (PIN_BASE + 0x40 + 23)
+#define AT91_PIN_PC24   (PIN_BASE + 0x40 + 24)
+#define AT91_PIN_PC25   (PIN_BASE + 0x40 + 25)
+#define AT91_PIN_PC26   (PIN_BASE + 0x40 + 26)
+#define AT91_PIN_PC27   (PIN_BASE + 0x40 + 27)
+#define AT91_PIN_PC28   (PIN_BASE + 0x40 + 28)
+#define AT91_PIN_PC29   (PIN_BASE + 0x40 + 29)
+#define AT91_PIN_PC30   (PIN_BASE + 0x40 + 30)
+#define AT91_PIN_PC31   (PIN_BASE + 0x40 + 31)
 
 
 rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
 {
-	return gpio;
+    return gpio;
 }
 
 #endif

bsp/at91sam9260/platform/interrupt.c

@@ -175,7 +175,7 @@ static void at91_gpio_irq_init()
         rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
         irq_desc[idx].counter = 0;
 #endif
-		idx++;
+        idx++;
     }
 
     rt_hw_interrupt_umask(AT91SAM9260_ID_PIOA);
@@ -308,7 +308,7 @@ void rt_hw_interrupt_umask(int irq)
  * @param name the interrupt name
  * @return old handler
  */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, 
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
                                     void *param, const char *name)
 {
     rt_isr_handler_t old_handler = RT_NULL;
@@ -322,7 +322,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
             irq_desc[vector].param = param;
 #ifdef RT_USING_INTERRUPT_INFO
             rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
-			irq_desc[vector].counter = 0;
+            irq_desc[vector].counter = 0;
 #endif
         }
     }
@@ -400,16 +400,16 @@ void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
 #ifdef RT_USING_INTERRUPT_INFO
 void list_irq(void)
 {
-	int irq;
-
-	rt_kprintf("number\tcount\tname\n");
-	for (irq = 0; irq < MAX_HANDLERS; irq++)
-	{
-		if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
-		{
-			rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
-		}
-	}
+    int irq;
+
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
 }
 
 #include <finsh.h>

bsp/at91sam9260/platform/io.h

@@ -11,31 +11,31 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define AT91_BASE_SYS			0xffffe800
+#define AT91_BASE_SYS           0xffffe800
 
-#define IO_SPACE_LIMIT		0xFFFFFFFF
+#define IO_SPACE_LIMIT      0xFFFFFFFF
 
-#define readb(a)	(*(volatile unsigned char  *)(a))
-#define readw(a)	(*(volatile unsigned short *)(a))
-#define readl(a)	(*(volatile unsigned int   *)(a))
+#define readb(a)    (*(volatile unsigned char  *)(a))
+#define readw(a)    (*(volatile unsigned short *)(a))
+#define readl(a)    (*(volatile unsigned int   *)(a))
 
-#define writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
-#define writew(v,a)	(*(volatile unsigned short *)(a) = (v))
-#define writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
+#define writeb(v,a) (*(volatile unsigned char  *)(a) = (v))
+#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define writel(v,a) (*(volatile unsigned int   *)(a) = (v))
 
 
 rt_inline unsigned int at91_sys_read(unsigned int reg_offset)
 {
-	unsigned int  addr = AT91_BASE_SYS;
+    unsigned int  addr = AT91_BASE_SYS;
 
-	return readl(addr + reg_offset);
+    return readl(addr + reg_offset);
 }
 
 rt_inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
 {
-	unsigned int addr = AT91_BASE_SYS;
+    unsigned int addr = AT91_BASE_SYS;
 
-	writel(value, addr + reg_offset);
+    writel(value, addr + reg_offset);
 }
 
 

bsp/at91sam9260/platform/irq.h

@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2011-01-13     weety      first version
  */
- 
+
 #ifndef __IRQ_H__
 #define __IRQ_H__
 
@@ -18,18 +18,18 @@ extern "C" {
 /*
  * IRQ line status.
  *
- * Bits 0-7 are reserved 
+ * Bits 0-7 are reserved
  *
  * IRQ types
  */
-#define IRQ_TYPE_NONE		0x00000000	/* Default, unspecified type */
-#define IRQ_TYPE_EDGE_RISING	0x00000001	/* Edge rising type */
-#define IRQ_TYPE_EDGE_FALLING	0x00000002	/* Edge falling type */
+#define IRQ_TYPE_NONE       0x00000000  /* Default, unspecified type */
+#define IRQ_TYPE_EDGE_RISING    0x00000001  /* Edge rising type */
+#define IRQ_TYPE_EDGE_FALLING   0x00000002  /* Edge falling type */
 #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
-#define IRQ_TYPE_LEVEL_HIGH	0x00000004	/* Level high type */
-#define IRQ_TYPE_LEVEL_LOW	0x00000008	/* Level low type */
-#define IRQ_TYPE_SENSE_MASK	0x0000000f	/* Mask of the above */
-#define IRQ_TYPE_PROBE		0x00000010	/* Probing in progress */
+#define IRQ_TYPE_LEVEL_HIGH 0x00000004  /* Level high type */
+#define IRQ_TYPE_LEVEL_LOW  0x00000008  /* Level low type */
+#define IRQ_TYPE_SENSE_MASK 0x0000000f  /* Mask of the above */
+#define IRQ_TYPE_PROBE      0x00000010  /* Probing in progress */
 
 #ifdef __cplusplus
 }

bsp/at91sam9260/platform/reset.c

@@ -19,12 +19,12 @@
 
 void machine_reset(void)
 {
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+    at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
 }
 
 void machine_shutdown(void)
 {
-	at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+    at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
 }
 
 #ifdef RT_USING_FINSH
@@ -35,14 +35,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
 #ifdef FINSH_USING_MSH
 int cmd_reset(int argc, char** argv)
 {
-	rt_hw_cpu_reset();
-	return 0;
+    rt_hw_cpu_reset();
+    return 0;
 }
 
 int cmd_shutdown(int argc, char** argv)
 {
-	rt_hw_cpu_shutdown();
-	return 0;
+    rt_hw_cpu_shutdown();
+    return 0;
 }
 
 FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);

bsp/at91sam9260/platform/rt_low_level_init.c

@@ -7,9 +7,9 @@
  * Date           Author       Notes
  * 2015-04-14     ArdaFu      first version
  */
- 
+
 /* write register a=address, v=value */
-#define write_reg(a,v)	    (*(volatile unsigned int *)(a) = (v))
+#define write_reg(a,v)      (*(volatile unsigned int *)(a) = (v))
 /* Processor Reset */
 #define AT91_RSTC_PROCRST   (1 << 0)
 #define AT91_RSTC_PERRST    (1 << 2)

bsp/at91sam9260/platform/rt_low_level_init.h

@@ -9,7 +9,7 @@
  */
 #ifndef __RT_LOW_LEVEL_INIT_H__
 #define __RT_LOW_LEVEL_INIT_H__
- 
+
 /*-------- Stack size of CPU modes -------------------------------------------*/
 #define UND_STK_SIZE 512
 #define SVC_STK_SIZE 4096

bsp/at91sam9260/platform/system_clock.c

@@ -14,270 +14,270 @@
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk clk32k = {
-	"clk32k",
-	AT91_SLOW_CLOCK,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "clk32k",
+    AT91_SLOW_CLOCK,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk main_clk = {
-	"main",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "main",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk plla = {
-	"plla",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "plla",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk mck = {
-	"mck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "mck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk uhpck = {
-	"uhpck",
-	0,
-	RT_NULL,
-	{RT_NULL, RT_NULL},
+    "uhpck",
+    0,
+    RT_NULL,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk pllb = {
-	"pllb",
-	0,
-	&main_clk,
-	{RT_NULL, RT_NULL},
+    "pllb",
+    0,
+    &main_clk,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk udpck = {
-	"udpck",
-	0,
-	&pllb,
-	{RT_NULL, RT_NULL},
+    "udpck",
+    0,
+    &pllb,
+    {RT_NULL, RT_NULL},
 };
 
 static struct clk *const standard_pmc_clocks[] = {
-	/* four primary clocks */
-	&clk32k,
-	&main_clk,
-	&plla,
+    /* four primary clocks */
+    &clk32k,
+    &main_clk,
+    &plla,
 
-	/* MCK */
-	&mck
+    /* MCK */
+    &mck
 };
 
 /* clocks cannot be de-registered no refcounting necessary */
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
-
-	return RT_NULL;
+    struct clk *clk;
+    rt_list_t *list;
+
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	flags;
-	rt_uint32_t	rate;
-
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return rate;
+    rt_uint32_t flags;
+    rt_uint32_t rate;
+
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return rate;
 }
 
 static rt_uint32_t at91_pll_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	unsigned mul, div;
+    unsigned mul, div;
 
-	div = reg & 0xff;
-	mul = (reg >> 16) & 0x7ff;
-	if (div && mul) {
-		freq /= div;
-		freq *= mul + 1;
-	} else
-		freq = 0;
+    div = reg & 0xff;
+    mul = (reg >> 16) & 0x7ff;
+    if (div && mul) {
+        freq /= div;
+        freq *= mul + 1;
+    } else
+        freq = 0;
 
-	return freq;
+    return freq;
 }
 
 static unsigned at91_pll_calc(unsigned main_freq, unsigned out_freq)
 {
-	unsigned i, div = 0, mul = 0, diff = 1 << 30;
-	unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
-
-	/* PLL output max 240 MHz (or 180 MHz per errata) */
-	if (out_freq > 240000000)
-		goto fail;
-
-	for (i = 1; i < 256; i++) {
-		int diff1;
-		unsigned input, mul1;
-
-		/*
-		 * PLL input between 1MHz and 32MHz per spec, but lower
-		 * frequences seem necessary in some cases so allow 100K.
-		 * Warning: some newer products need 2MHz min.
-		 */
-		input = main_freq / i;
-		if (input < 100000)
-			continue;
-		if (input > 32000000)
-			continue;
-
-		mul1 = out_freq / input;
-		if (mul1 > 2048)
-			continue;
-		if (mul1 < 2)
-			goto fail;
-
-		diff1 = out_freq - input * mul1;
-		if (diff1 < 0)
-			diff1 = -diff1;
-		if (diff > diff1) {
-			diff = diff1;
-			div = i;
-			mul = mul1;
-			if (diff == 0)
-				break;
-		}
-	}
-	if (i == 256 && diff > (out_freq >> 5))
-		goto fail;
-	return ret | ((mul - 1) << 16) | div;
+    unsigned i, div = 0, mul = 0, diff = 1 << 30;
+    unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
+
+    /* PLL output max 240 MHz (or 180 MHz per errata) */
+    if (out_freq > 240000000)
+        goto fail;
+
+    for (i = 1; i < 256; i++) {
+        int diff1;
+        unsigned input, mul1;
+
+        /*
+         * PLL input between 1MHz and 32MHz per spec, but lower
+         * frequences seem necessary in some cases so allow 100K.
+         * Warning: some newer products need 2MHz min.
+         */
+        input = main_freq / i;
+        if (input < 100000)
+            continue;
+        if (input > 32000000)
+            continue;
+
+        mul1 = out_freq / input;
+        if (mul1 > 2048)
+            continue;
+        if (mul1 < 2)
+            goto fail;
+
+        diff1 = out_freq - input * mul1;
+        if (diff1 < 0)
+            diff1 = -diff1;
+        if (diff > diff1) {
+            diff = diff1;
+            div = i;
+            mul = mul1;
+            if (diff == 0)
+                break;
+        }
+    }
+    if (i == 256 && diff > (out_freq >> 5))
+        goto fail;
+    return ret | ((mul - 1) << 16) | div;
 fail:
-	return 0;
+    return 0;
 }
 
 static rt_uint32_t at91_usb_rate(struct clk *pll, rt_uint32_t freq, rt_uint32_t reg)
 {
-	if (pll == &pllb && (reg & AT91_PMC_USB96M))
-		return freq / 2;
-	else
-		return freq;
+    if (pll == &pllb && (reg & AT91_PMC_USB96M))
+        return freq / 2;
+    else
+        return freq;
 }
 
 
 /* PLLB generated USB full speed clock init */
 static void at91_pllb_usbfs_clock_init(rt_uint32_t main_clock)
 {
-	rt_uint32_t at91_pllb_usb_init;
-	/*
-	 * USB clock init:  choose 48 MHz PLLB value,
-	 * disable 48MHz clock during usb peripheral suspend.
-	 *
-	 * REVISIT:  assumes MCK doesn't derive from PLLB!
-	 */
-	uhpck.parent = &pllb;
-
-	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
-	pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
-	
-	at91_sys_write(AT91_CKGR_PLLBR, 0);
-
-	udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
-	uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    rt_uint32_t at91_pllb_usb_init;
+    /*
+     * USB clock init:  choose 48 MHz PLLB value,
+     * disable 48MHz clock during usb peripheral suspend.
+     *
+     * REVISIT:  assumes MCK doesn't derive from PLLB!
+     */
+    uhpck.parent = &pllb;
+
+    at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
+    pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
+
+    at91_sys_write(AT91_CKGR_PLLBR, 0);
+
+    udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
+    uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 }
 
 static struct clk *at91_css_to_clk(unsigned long css)
 {
-	switch (css) {
-		case AT91_PMC_CSS_SLOW:
-			return &clk32k;
-		case AT91_PMC_CSS_MAIN:
-			return &main_clk;
-		case AT91_PMC_CSS_PLLA:
-			return &plla;
-		case AT91_PMC_CSS_PLLB:
-			return &pllb;
-	}
-
-	return RT_NULL;
+    switch (css) {
+        case AT91_PMC_CSS_SLOW:
+            return &clk32k;
+        case AT91_PMC_CSS_MAIN:
+            return &main_clk;
+        case AT91_PMC_CSS_PLLA:
+            return &plla;
+        case AT91_PMC_CSS_PLLB:
+            return &pllb;
+    }
+
+    return RT_NULL;
 }
 
 #define false 0
 #define true  1
 int at91_clock_init(rt_uint32_t main_clock)
 {
-	unsigned tmp, freq, mckr;
-	int i;
-	int pll_overclock = false;
-
-	/*
-	 * When the bootloader initialized the main oscillator correctly,
-	 * there's no problem using the cycle counter.  But if it didn't,
-	 * or when using oscillator bypass mode, we must be told the speed
-	 * of the main clock.
-	 */
-	if (!main_clock) {
-		do {
-			tmp = at91_sys_read(AT91_CKGR_MCFR);
-		} while (!(tmp & AT91_PMC_MAINRDY));
-		main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
-	}
-	main_clk.rate_hz = main_clock;
-
-	/* report if PLLA is more than mildly overclocked */
-	plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-	if (plla.rate_hz > 209000000)
-		pll_overclock = true;
-	if (pll_overclock)
-		;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
-
-	at91_pllb_usbfs_clock_init(main_clock);
-
-	/*
-	 * MCK and CPU derive from one of those primary clocks.
-	 * For now, assume this parentage won't change.
-	 */
-	mckr = at91_sys_read(AT91_PMC_MCKR);
-	mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
-	freq = mck.parent->rate_hz;
-	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));				/* prescale */
-	
-	mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
-
-	/* Register the PMC's standard clocks */
-	rt_list_init(&clocks);
-	for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
-		rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
-
-	rt_list_insert_after(&clocks, &pllb.node);
-	rt_list_insert_after(&clocks, &uhpck.node);
-	rt_list_insert_after(&clocks, &udpck.node);
-
-	/* MCK and CPU clock are "always on" */
-	//clk_enable(&mck);
-
-	/*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
-		freq / 1000000, (unsigned) mck.rate_hz / 1000000,
-		(unsigned) main_clock / 1000000,
-		((unsigned) main_clock % 1000000) / 1000);*///cause blocked
-
-	return 0;
+    unsigned tmp, freq, mckr;
+    int i;
+    int pll_overclock = false;
+
+    /*
+     * When the bootloader initialized the main oscillator correctly,
+     * there's no problem using the cycle counter.  But if it didn't,
+     * or when using oscillator bypass mode, we must be told the speed
+     * of the main clock.
+     */
+    if (!main_clock) {
+        do {
+            tmp = at91_sys_read(AT91_CKGR_MCFR);
+        } while (!(tmp & AT91_PMC_MAINRDY));
+        main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
+    }
+    main_clk.rate_hz = main_clock;
+
+    /* report if PLLA is more than mildly overclocked */
+    plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
+    if (plla.rate_hz > 209000000)
+        pll_overclock = true;
+    if (pll_overclock)
+        ;//rt_kprintf("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+
+    at91_pllb_usbfs_clock_init(main_clock);
+
+    /*
+     * MCK and CPU derive from one of those primary clocks.
+     * For now, assume this parentage won't change.
+     */
+    mckr = at91_sys_read(AT91_PMC_MCKR);
+    mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
+    freq = mck.parent->rate_hz;
+    freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));               /* prescale */
+
+    mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
+
+    /* Register the PMC's standard clocks */
+    rt_list_init(&clocks);
+    for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
+        rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node);
+
+    rt_list_insert_after(&clocks, &pllb.node);
+    rt_list_insert_after(&clocks, &uhpck.node);
+    rt_list_insert_after(&clocks, &udpck.node);
+
+    /* MCK and CPU clock are "always on" */
+    //clk_enable(&mck);
+
+    /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
+        freq / 1000000, (unsigned) mck.rate_hz / 1000000,
+        (unsigned) main_clock / 1000000,
+        ((unsigned) main_clock % 1000000) / 1000);*///cause blocked
+
+    return 0;
 }
 
 /**
@@ -285,6 +285,6 @@ int at91_clock_init(rt_uint32_t main_clock)
  */
 void rt_hw_clock_init(void)
 {
-	at91_clock_init(18432000);
+    at91_clock_init(18432000);
 }
 

bsp/avr32uc3b0/application.c

@@ -52,7 +52,7 @@ int rt_application_init()
 {
     /* create led1 thread */
     rt_thread_init(&thread_led1,
-				   "led1",
+                   "led1",
                    rt_thread_entry_led1,
                    RT_NULL,
                    &thread_led1_stack[0],

bsp/avr32uc3b0/board.c

@@ -16,11 +16,11 @@
 #include "intc.h"
 #include "serial.h"
 
-#define FOSC0	12000000
-#define FCPU	60000000
-#define FHSB	FCPU
-#define FPBA	FCPU
-#define FPBB	FCPU
+#define FOSC0   12000000
+#define FCPU    60000000
+#define FHSB    FCPU
+#define FPBA    FCPU
+#define FPBB    FCPU
 
 extern void rt_hw_serial_isr(void);
 extern void rt_hw_usart_init(void);
@@ -30,10 +30,10 @@ extern void rt_hw_usart_init(void);
  */
 static void rt_hw_timer_handler(void)
 {
-	// Clears the interrupt request.
-	Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
+    // Clears the interrupt request.
+    Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
 
-	rt_tick_increase();
+    rt_tick_increase();
 }
 
 /**
@@ -41,35 +41,35 @@ static void rt_hw_timer_handler(void)
  */
 static void peripherals_init(void)
 {
-	/*
-	 * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock
-	 */
-	pm_freq_param_t pm_freq_param =
-	{
-		.cpu_f = FCPU,
-		.pba_f = FPBA,
-		.osc0_f = FOSC0,
-		.osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC
-	};
-	pm_configure_clocks(&pm_freq_param);
+    /*
+     * PM initialization: OSC0 = 12MHz XTAL, PLL0 = 60MHz System Clock
+     */
+    pm_freq_param_t pm_freq_param =
+    {
+        .cpu_f = FCPU,
+        .pba_f = FPBA,
+        .osc0_f = FOSC0,
+        .osc0_startup = AVR32_PM_OSCCTRL0_STARTUP_2048_RCOSC
+    };
+    pm_configure_clocks(&pm_freq_param);
 
-	/*
-	 * USART1 initialization
-	 */
-	gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION);
-	gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION);
-	static const usart_options_t usartOptions = {
-		.baudrate = 115200,
-		.charlength = 8,
-		.paritytype = USART_NO_PARITY,
-		.stopbits = USART_1_STOPBIT,
-		.channelmode = USART_NORMAL_CHMODE
-	};
-	usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU);
+    /*
+     * USART1 initialization
+     */
+    gpio_enable_module_pin(AVR32_USART1_TXD_0_1_PIN, AVR32_USART1_TXD_0_1_FUNCTION);
+    gpio_enable_module_pin(AVR32_USART1_RXD_0_1_PIN, AVR32_USART1_RXD_0_1_FUNCTION);
+    static const usart_options_t usartOptions = {
+        .baudrate = 115200,
+        .charlength = 8,
+        .paritytype = USART_NO_PARITY,
+        .stopbits = USART_1_STOPBIT,
+        .channelmode = USART_NORMAL_CHMODE
+    };
+    usart_init_rs232(&AVR32_USART1, &usartOptions, FCPU);
 
-	INTC_init_interrupts();
-	INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0);
-	AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK;
+    INTC_init_interrupts();
+    INTC_register_interrupt(&rt_hw_serial_isr, AVR32_USART1_IRQ, AVR32_INTC_INT0);
+    AVR32_USART1.ier = AVR32_USART_IER_RXRDY_MASK;
 }
 
 /**
@@ -77,21 +77,21 @@ static void peripherals_init(void)
  */
 static void cpu_counter_init(void)
 {
-	INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3);
-	Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
-	Set_system_register(AVR32_COUNT, 0);
+    INTC_register_interrupt(&rt_hw_timer_handler, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT3);
+    Set_system_register(AVR32_COMPARE, FCPU / RT_TICK_PER_SECOND);
+    Set_system_register(AVR32_COUNT, 0);
 }
 
 void rt_hw_board_init(void)
 {
-	extern struct rt_device _rt_usart_device;
-	extern struct avr32_serial_device uart;
+    extern struct rt_device _rt_usart_device;
+    extern struct avr32_serial_device uart;
 
-	Disable_global_interrupt();
+    Disable_global_interrupt();
 
-	peripherals_init();
-	cpu_counter_init();
+    peripherals_init();
+    cpu_counter_init();
 
-	rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart);
-	rt_console_set_device("uart1");
+    rt_hw_serial_register(&_rt_usart_device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM, &uart);
+    rt_console_set_device("uart1");
 }

bsp/avr32uc3b0/rtconfig.h

@@ -12,16 +12,16 @@
 #define RTCONFIG_H_
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX 8
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX  32
 
 /* Tick per Second*/
-#define RT_TICK_PER_SECOND	100
+#define RT_TICK_PER_SECOND  100
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug*/
@@ -69,7 +69,7 @@
 /* SECTION: Console options */
 /* the buffer size of console*/
 #define RT_USING_CONSOLE
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: FinSH shell options */
 /* Using FinSH as Shell*/
@@ -84,21 +84,21 @@
 
 #define RT_USING_DFS_ELMFAT
 #define RT_DFS_ELM_WORD_ACCESS
-#define RT_DFS_ELM_DRIVES			2
+#define RT_DFS_ELM_DRIVES           2
 
 /* SECTION: DFS options */
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX			2
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					8
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		4
+#define DFS_FILESYSTEMS_MAX         2
+/* the max number of opened files       */
+#define DFS_FD_MAX                  8
+/* the max number of cached sector      */
+#define DFS_CACHE_MAX_NUM           4
 
 /* SECTION: RT-Thread/GUI */
 //#define RT_USING_RTGUI
 
 /* name length of RTGUI object */
-#define RTGUI_NAME_MAX		12
+#define RTGUI_NAME_MAX      12
 /* support 16 weight font */
 #define RTGUI_USING_FONT16
 /* support Chinese font */
@@ -112,6 +112,6 @@
 /* use mouse cursor */
 /* #define RTGUI_USING_MOUSE_CURSOR */
 /* default font size in RTGUI */
-#define RTGUI_DEFAULT_FONT_SIZE	16
+#define RTGUI_DEFAULT_FONT_SIZE 16
 
 #endif /* RTCONFIG_H_ */

bsp/avr32uc3b0/startup.c

@@ -21,21 +21,21 @@ extern void finsh_set_device(const char* device);
 int main(void)
 {
 #ifdef RT_USING_HEAP
-	extern void __heap_start__;
-	extern void __heap_end__;
+    extern void __heap_start__;
+    extern void __heap_end__;
 #endif
 
-	rt_hw_board_init();
-	rt_system_tick_init();
-	rt_system_object_init();
-	rt_system_timer_init();
+    rt_hw_board_init();
+    rt_system_tick_init();
+    rt_system_object_init();
+    rt_system_timer_init();
 
 #ifdef RT_USING_HEAP
-	rt_system_heap_init(&__heap_start__, &__heap_end__);
+    rt_system_heap_init(&__heap_start__, &__heap_end__);
 #endif
 
-	rt_system_scheduler_init();
-	rt_application_init();
+    rt_system_scheduler_init();
+    rt_application_init();
 
 #ifdef RT_USING_FINSH
     /* init finsh */
@@ -44,7 +44,7 @@ int main(void)
 #endif
 
     rt_thread_idle_init();
-	rt_system_scheduler_start();
+    rt_system_scheduler_start();
 
-	return 0;
+    return 0;
 }

bsp/beaglebone/applications/board.c

@@ -45,7 +45,7 @@ static rt_uint32_t DMTIMER = 0;
 
 static void rt_hw_timer_isr(int vector, void* param)
 {
-	rt_tick_increase();
+    rt_tick_increase();
 
     DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
 }
@@ -67,73 +67,73 @@ static void timer_clk_init(void)
     while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & (1<<8)))
         ;
 
-	/* Select the clock source for the Timer2 instance.  */
-	CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
-	/* 32k clock source */
-	CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
+    /* Select the clock source for the Timer2 instance.  */
+    CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) &= ~(CM_DPLL_CLKSEL_CLK_CLKSEL);
+    /* 32k clock source */
+    CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) |= CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3;
 
-	while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
-		CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
+    while ((CM_DPLL_CLKSEL_TIMER7_CLK(prcm_base) & CM_DPLL_CLKSEL_CLK_CLKSEL) !=
+        CM_DPLL_CLKSEL_CLK_CLKSEL_SEL3);
 
-	/* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
-	CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
+    /* Writing to MODULEMODE field of CM_PER_TIMER7_CLKCTRL register. */
+    CM_PER_TIMER7_CLKCTRL(prcm_base) |= CM_PER_CLKCTRL_MODULEMODE_ENABLE;
 
-	/* Waiting for MODULEMODE field to reflect the written value. */
-	while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
-		CM_PER_CLKCTRL_MODULEMODE_ENABLE);
+    /* Waiting for MODULEMODE field to reflect the written value. */
+    while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_MODULEMODE) !=
+        CM_PER_CLKCTRL_MODULEMODE_ENABLE);
 
-	/*
-	 * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register 
-	 * for the module is fully functional.
-	 */
-	while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
-		CM_PER_CLKCTRL_IDLEST_FUNC);
+    /*
+     * Waiting for IDLEST field in CM_PER_TIMER7_CLKCTRL register
+     * for the module is fully functional.
+     */
+    while ((CM_PER_TIMER7_CLKCTRL(prcm_base) & CM_PER_CLKCTRL_IDLEST) !=
+        CM_PER_CLKCTRL_IDLEST_FUNC);
 
-	/* Waiting for the L4LS clock */
-	while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
-	/* Waiting for the TIMER7 clock */
-	while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
+    /* Waiting for the L4LS clock */
+    while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK));
+    /* Waiting for the TIMER7 clock */
+    while (!(CM_PER_L4LS_CLKSTCTRL_REG(prcm_base) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_TIMER7_GCLK));
 }
 
 int rt_hw_timer_init(void)
 {
-	rt_uint32_t counter;
+    rt_uint32_t counter;
 
 #ifdef RT_USING_VMM
     DMTIMER = vmm_find_iomap("TIMER7");
 #endif
 
-	timer_clk_init();
+    timer_clk_init();
 
-	/* soft reset the timer */
-	DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
+    /* soft reset the timer */
+    DMTIMER_TIOCP_CFG(TIMER_HW_BASE) |= 1;
     while ((DMTIMER_TIOCP_CFG(TIMER_HW_BASE) & 0x1) == 1)
         ;
 
-	/* calculate count */
-	counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
+    /* calculate count */
+    counter = 0xffffffff - (32768UL/RT_TICK_PER_SECOND);
 
-	/* set initial count */
-	DMTIMER_TCRR(TIMER_HW_BASE) = counter;
-	/* set reload count */
-	DMTIMER_TLDR(TIMER_HW_BASE) = counter;
+    /* set initial count */
+    DMTIMER_TCRR(TIMER_HW_BASE) = counter;
+    /* set reload count */
+    DMTIMER_TLDR(TIMER_HW_BASE) = counter;
 
-	/* set mode: auto reload */
-	DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
+    /* set mode: auto reload */
+    DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_AR;
 
-	/* interrupt enable for match */
-	DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
+    /* interrupt enable for match */
+    DMTIMER_IRQENABLE_SET(TIMER_HW_BASE) = DMTIMER_IRQENABLE_SET_OVF_EN_FLAG;
     DMTIMER_IRQSTATUS(TIMER_HW_BASE) = DMTIMER_IRQSTATUS_RAW_OVF_IT_FLAG;
 
-	rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
-	rt_hw_interrupt_control(TINT7, 0, 0);
-	rt_hw_interrupt_umask(TINT7);
+    rt_hw_interrupt_install(TINT7, rt_hw_timer_isr, RT_NULL, "tick");
+    rt_hw_interrupt_control(TINT7, 0, 0);
+    rt_hw_interrupt_umask(TINT7);
 
     while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
         ;
 
-	/* start timer */
-	DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
+    /* start timer */
+    DMTIMER_TCLR(TIMER_HW_BASE) |= DMTIMER_TCLR_ST;
 
     while (DMTIMER_TWPS(TIMER_HW_BASE) != 0)
         ;
@@ -148,7 +148,7 @@ INIT_BOARD_EXPORT(rt_hw_timer_init);
 void rt_hw_board_init(void)
 {
     rt_components_board_init();
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 }
 
 void rt_hw_cpu_reset(void)

bsp/bf533/rtconfig.h

@@ -6,16 +6,16 @@
 #define IDLE_THREAD_STACK_SIZE 512
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	32
+#define RT_NAME_MAX 32
 
 /* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE	4
+#define RT_ALIGN_SIZE   4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	256
+#define RT_THREAD_PRIORITY_MAX  256
 
 /* Tick per Second */
-#define RT_TICK_PER_SECOND	1000
+#define RT_TICK_PER_SECOND  1000
 
 /* SECTION: RT_DEBUG */
 /* Thread Debug */
@@ -29,9 +29,9 @@
 
 /* Using Software Timer */
 //#define RT_USING_TIMER_SOFT
-#define RT_TIMER_THREAD_PRIO		8
-#define RT_TIMER_THREAD_STACK_SIZE	512
-#define RT_TIMER_TICK_PER_SECOND	1000
+#define RT_TIMER_THREAD_PRIO        8
+#define RT_TIMER_THREAD_STACK_SIZE  512
+#define RT_TIMER_TICK_PER_SECOND    1000
 
 /* SECTION: IPC */
 /* Using Semaphore */
@@ -73,7 +73,7 @@
 #define RT_USING_CONSOLE
 
 /* the buffer size of console */
-#define RT_CONSOLEBUF_SIZE	128
+#define RT_CONSOLEBUF_SIZE  128
 
 /* SECTION: finsh, a C-Express shell */
 /* Using FinSH as Shell*/
@@ -96,25 +96,25 @@
 /* using DFS support */
 //#define RT_USING_DFS
 #define RT_USING_DFS_ELMFAT
-/* use long file name feature 			*/
-#define RT_DFS_ELM_USE_LFN			1
-/* the max number of file length 		*/
-#define RT_DFS_ELM_MAX_LFN		128
+/* use long file name feature           */
+#define RT_DFS_ELM_USE_LFN          1
+/* the max number of file length        */
+#define RT_DFS_ELM_MAX_LFN      128
 /* #define RT_USING_DFS_YAFFS2 */
 /* #define RT_USING_DFS_UFFS */
 #define RT_USING_DFS_DEVFS
 
 /* #define RT_USING_DFS_NFS */
-#define RT_NFS_HOST_EXPORT		"192.168.1.5:/"
+#define RT_NFS_HOST_EXPORT      "192.168.1.5:/"
 
 #define DFS_USING_WORKDIR
 
 /* the max number of mounted filesystem */
-#define DFS_FILESYSTEMS_MAX		4
-/* the max number of opened files 		*/
-#define DFS_FD_MAX					16
-/* the max number of cached sector 		*/
-#define DFS_CACHE_MAX_NUM   		4
+#define DFS_FILESYSTEMS_MAX     4
+/* the max number of opened files       */
+#define DFS_FD_MAX                  16
+/* the max number of cached sector      */
+#define DFS_CACHE_MAX_NUM           4
 
 /* Enable freemodbus protocal stack*/
 /* #define RT_USING_MODBUS */
@@ -140,13 +140,13 @@
 #define RT_LWIP_TCP
 
 /* the number of simulatenously active TCP connections*/
-#define RT_LWIP_TCP_PCB_NUM	5
+#define RT_LWIP_TCP_PCB_NUM 5
 
 /* TCP sender buffer space */
-#define RT_LWIP_TCP_SND_BUF	1024*8
+#define RT_LWIP_TCP_SND_BUF 1024*8
 
 /* TCP receive window. */
-#define RT_LWIP_TCP_WND	1024*8
+#define RT_LWIP_TCP_WND 1024*8
 
 /* Enable SNMP protocol */
 /* #define RT_LWIP_SNMP */
@@ -155,53 +155,53 @@
 /* #define RT_LWIP_DHCP */
 
 /* ip address of target */
-#define RT_LWIP_IPADDR0	192
-#define RT_LWIP_IPADDR1	168
-#define RT_LWIP_IPADDR2	1
-#define RT_LWIP_IPADDR3	30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 1
+#define RT_LWIP_IPADDR3 30
 
 /* gateway address of target */
-#define RT_LWIP_GWADDR0	192
-#define RT_LWIP_GWADDR1	168
-#define RT_LWIP_GWADDR2	1
-#define RT_LWIP_GWADDR3	1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 1
+#define RT_LWIP_GWADDR3 1
 
 /* mask address of target */
-#define RT_LWIP_MSKADDR0	255
-#define RT_LWIP_MSKADDR1	255
-#define RT_LWIP_MSKADDR2	255
-#define RT_LWIP_MSKADDR3	0
+#define RT_LWIP_MSKADDR0    255
+#define RT_LWIP_MSKADDR1    255
+#define RT_LWIP_MSKADDR2    255
+#define RT_LWIP_MSKADDR3    0
 
 /* the number of blocks for pbuf */
-#define RT_LWIP_PBUF_NUM	16
+#define RT_LWIP_PBUF_NUM    16
 
 /* the number of simultaneously queued TCP */
 #define RT_LWIP_TCP_SEG_NUM    40
 
 /* thread priority of tcpip thread */
-#define RT_LWIP_TCPTHREAD_PRIORITY	128
+#define RT_LWIP_TCPTHREAD_PRIORITY  128
 
 /* mail box size of tcpip thread to wait for */
-#define RT_LWIP_TCPTHREAD_MBOX_SIZE	32
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE 32
 
 /* thread stack size of tcpip thread */
-#define RT_LWIP_TCPTHREAD_STACKSIZE	4096
+#define RT_LWIP_TCPTHREAD_STACKSIZE 4096
 
 /* thread priority of ethnetif thread */
-#define RT_LWIP_ETHTHREAD_PRIORITY	144
+#define RT_LWIP_ETHTHREAD_PRIORITY  144
 
 /* mail box size of ethnetif thread to wait for */
-#define RT_LWIP_ETHTHREAD_MBOX_SIZE	32
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE 32
 
 /* thread stack size of ethnetif thread */
-#define RT_LWIP_ETHTHREAD_STACKSIZE	1024
+#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
 
 /* SECTION: RTGUI support */
 /* using RTGUI support */
 #define RT_USING_RTGUI
 
 /* name length of RTGUI object */
-#define RTGUI_NAME_MAX		16
+#define RTGUI_NAME_MAX      16
 /* support 16 weight font */
 #define RTGUI_USING_FONT16
 /* support 16 weight font */
@@ -236,7 +236,7 @@
  * #define DFS_USING_WORKDIR
  *
  * And the maximal length must great than 64
- * #define RT_DFS_ELM_MAX_LFN	128
+ * #define RT_DFS_ELM_MAX_LFN   128
  */
 
 #endif

bsp/dm365/applications/application.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 
@@ -27,57 +27,57 @@
 
 int main(void)
 {
-	int timeout = 0;
+    int timeout = 0;
 
 /* Filesystem Initialization */
 #ifdef RT_USING_DFS
-	{
+    {
 
 #if defined(RT_USING_DFS_ROMFS)
-		if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
-		{
-			rt_kprintf("ROM File System initialized!\n");
-		}
-		else
-			rt_kprintf("ROM File System initialzation failed!\n");
+        if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
+        {
+            rt_kprintf("ROM File System initialized!\n");
+        }
+        else
+            rt_kprintf("ROM File System initialzation failed!\n");
 #endif
 
 #if defined(RT_USING_DFS_UFFS)
-	{
-		/* mount flash device as flash directory */
-		if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
-			rt_kprintf("UFFS File System initialized!\n");
-		else
-			rt_kprintf("UFFS File System initialzation failed!\n");
-	}
+    {
+        /* mount flash device as flash directory */
+        if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
+            rt_kprintf("UFFS File System initialized!\n");
+        else
+            rt_kprintf("UFFS File System initialzation failed!\n");
+    }
 #endif
 
 #ifdef RT_USING_SDIO
-	timeout = 0;
-	while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
-	{
-		rt_thread_delay(1);
-	}
-
-	if (timeout < RT_TICK_PER_SECOND*2)
-	{
-		/* mount sd card fat partition 1 as root directory */
-		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
-		{
-			rt_kprintf("File System initialized!\n");
-		}
-		else
-			rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
-	}
-	else
-	{
-		rt_kprintf("No SD card found.\n");
-	}
+    timeout = 0;
+    while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
+    {
+        rt_thread_delay(1);
+    }
+
+    if (timeout < RT_TICK_PER_SECOND*2)
+    {
+        /* mount sd card fat partition 1 as root directory */
+        if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+        {
+            rt_kprintf("File System initialized!\n");
+        }
+        else
+            rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
+    }
+    else
+    {
+        rt_kprintf("No SD card found.\n");
+    }
 #endif
-	}
+    }
 #endif
 
-	/* put user application code here */
+    /* put user application code here */
 
 }
 
@@ -87,14 +87,14 @@ int main(void)
 #include <dfs_nfs.h>
 void nfs_start(void)
 {
-	nfs_init();
-
-	if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
-	{
-		rt_kprintf("NFSv3 File System initialized!\n");
-	}
-	else
-		rt_kprintf("NFSv3 File System initialzation failed!\n");
+    nfs_init();
+
+    if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
+    {
+        rt_kprintf("NFSv3 File System initialized!\n");
+    }
+    else
+        rt_kprintf("NFSv3 File System initialzation failed!\n");
 }
 
 #include "finsh.h"

bsp/dm365/applications/board.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -19,28 +19,28 @@
  */
 /*@{*/
 #if defined(__CC_ARM)
-	extern int Image$$ER_ZI$$ZI$$Base;
-	extern int Image$$ER_ZI$$ZI$$Length;
-	extern int Image$$ER_ZI$$ZI$$Limit;
+    extern int Image$$ER_ZI$$ZI$$Base;
+    extern int Image$$ER_ZI$$ZI$$Length;
+    extern int Image$$ER_ZI$$ZI$$Limit;
 #elif (defined (__GNUC__))
-	rt_uint8_t _irq_stack_start[1024];
-	rt_uint8_t _fiq_stack_start[1024];
-	rt_uint8_t _undefined_stack_start[512];
-	rt_uint8_t _abort_stack_start[512];
-	rt_uint8_t _svc_stack_start[1024] SECTION(".nobss");
-	extern unsigned char __bss_start;
-	extern unsigned char __bss_end;
+    rt_uint8_t _irq_stack_start[1024];
+    rt_uint8_t _fiq_stack_start[1024];
+    rt_uint8_t _undefined_stack_start[512];
+    rt_uint8_t _abort_stack_start[512];
+    rt_uint8_t _svc_stack_start[1024] SECTION(".nobss");
+    extern unsigned char __bss_start;
+    extern unsigned char __bss_end;
 #endif
 
 extern void rt_hw_clock_init(void);
 extern void rt_hw_uart_init(void);
 
 static struct mem_desc dm365_mem_desc[] = {
-	{ 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED },       /* 128M cached SDRAM memory */
-	{ 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED },     /* 128M No cached SDRAM memory */
-	{ 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */
-	{ 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* CFG BUS peripherals */
-	{ 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* AEMIF */
+    { 0x80000000, 0x88000000-1, 0x80000000, SECT_RW_CB, 0, SECT_MAPPED },       /* 128M cached SDRAM memory */
+    { 0xA0000000, 0xA8000000-1, 0x80000000, SECT_RW_NCNB, 0, SECT_MAPPED },     /* 128M No cached SDRAM memory */
+    { 0xFFFF0000, 0xFFFF1000-1, 0x80000000, SECT_TO_PAGE, PAGE_RO_CB, PAGE_MAPPED }, /* isr vector table */
+    { 0x01C00000, 0x02000000-1, 0x01C00000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* CFG BUS peripherals */
+    { 0x02000000, 0x0A000000-1, 0x02000000, SECT_RW_NCNB, 0, SECT_MAPPED },       /* AEMIF */
 };
 
 
@@ -49,7 +49,7 @@ static struct mem_desc dm365_mem_desc[] = {
  */
 void rt_timer_handler(int vector, void *param)
 {
-	rt_tick_increase();
+    rt_tick_increase();
 }
 
 /**
@@ -57,70 +57,70 @@ void rt_timer_handler(int vector, void *param)
  */
  void rt_hw_timer_init()
  {
-	/* timer0, input clocks 24MHz */
-	volatile timer_regs_t *regs =
-		(volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE;
+    /* timer0, input clocks 24MHz */
+    volatile timer_regs_t *regs =
+        (volatile timer_regs_t*)DAVINCI_TIMER1_BASE;//DAVINCI_TIMER0_BASE;
 
-	psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3);
-	psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3);
+    psc_change_state(DAVINCI_DM365_LPSC_TIMER0, 3);
+    psc_change_state(DAVINCI_DM365_LPSC_TIMER1, 3);
 
-	/*disable timer*/
-	regs->tcr &= ~(0x3UL << 6);
+    /*disable timer*/
+    regs->tcr &= ~(0x3UL << 6);
 
-	//TIMMODE 32BIT UNCHAINED MODE
-	regs->tgcr |=(0x1UL << 2);
+    //TIMMODE 32BIT UNCHAINED MODE
+    regs->tgcr |=(0x1UL << 2);
 
-	/*not in reset timer */
-	regs->tgcr |= (0x1UL << 0);
+    /*not in reset timer */
+    regs->tgcr |= (0x1UL << 0);
 
-	//regs->tgcr &= ~(0x1UL << 1);
+    //regs->tgcr &= ~(0x1UL << 1);
 
-	/* set Period Registers */
-	regs->prd12 = 24000000/RT_TICK_PER_SECOND;
-	regs->tim12 = 0;
+    /* set Period Registers */
+    regs->prd12 = 24000000/RT_TICK_PER_SECOND;
+    regs->tim12 = 0;
 
-	/* Set enable mode */
-	regs->tcr |= (0x2UL << 6); //period mode
-	
+    /* Set enable mode */
+    regs->tcr |= (0x2UL << 6); //period mode
 
-	/* install interrupt handler */
-	rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler,
-							RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12
-	rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2
+
+    /* install interrupt handler */
+    rt_hw_interrupt_install(IRQ_DM365_TINT2, rt_timer_handler,
+                            RT_NULL, "timer1_12");//IRQ_DM365_TINT0_TINT12
+    rt_hw_interrupt_umask(IRQ_DM365_TINT2);//IRQ_DM365_TINT2
 
  }
 
-#define LSR_DR		0x01		/* Data ready */
-#define LSR_THRE	0x20		/* Xmit holding register empty */
-#define BPS			115200	/* serial baudrate */
+#define LSR_DR      0x01        /* Data ready */
+#define LSR_THRE    0x20        /* Xmit holding register empty */
+#define BPS         115200  /* serial baudrate */
 
 typedef struct uartport
 {
-	volatile rt_uint32_t rbr;
-	volatile rt_uint32_t ier;
-	volatile rt_uint32_t fcr;
-	volatile rt_uint32_t lcr;
-	volatile rt_uint32_t mcr;
-	volatile rt_uint32_t lsr;
-	volatile rt_uint32_t msr;
-	volatile rt_uint32_t scr;
-	volatile rt_uint32_t dll;
-	volatile rt_uint32_t dlh;
-	
-	volatile rt_uint32_t res[2];
-	volatile rt_uint32_t pwremu_mgmt;
-	volatile rt_uint32_t mdr;
+    volatile rt_uint32_t rbr;
+    volatile rt_uint32_t ier;
+    volatile rt_uint32_t fcr;
+    volatile rt_uint32_t lcr;
+    volatile rt_uint32_t mcr;
+    volatile rt_uint32_t lsr;
+    volatile rt_uint32_t msr;
+    volatile rt_uint32_t scr;
+    volatile rt_uint32_t dll;
+    volatile rt_uint32_t dlh;
+
+    volatile rt_uint32_t res[2];
+    volatile rt_uint32_t pwremu_mgmt;
+    volatile rt_uint32_t mdr;
 }uartport;
 
 #define thr rbr
 #define iir fcr
 
-#define UART0	((struct uartport *)DAVINCI_UART0_BASE)
+#define UART0   ((struct uartport *)DAVINCI_UART0_BASE)
 
 static void davinci_uart_putc(char c)
 {
     while (!(UART0->lsr & LSR_THRE));
-	UART0->thr = c;
+    UART0->thr = c;
 }
 
 /**
@@ -131,35 +131,35 @@ static void davinci_uart_putc(char c)
  */
 void rt_hw_console_output(const char* str)
 {
-	while (*str)
-	{
-		if (*str=='\n')
-		{
-			davinci_uart_putc('\r');
-		}
-
-		davinci_uart_putc(*str++);
-	}
+    while (*str)
+    {
+        if (*str=='\n')
+        {
+            davinci_uart_putc('\r');
+        }
+
+        davinci_uart_putc(*str++);
+    }
 }
 
 static void rt_hw_console_init(void)
 {
-	rt_uint32_t divisor;
-	
-	divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS);
-	UART0->ier = 0;
-	UART0->lcr = 0x83; //8N1
-	UART0->dll = 0;
-	UART0->dlh = 0;
-	UART0->lcr = 0x03;
-	UART0->mcr = 0x03; //RTS,CTS
-	UART0->fcr = 0x07; //FIFO
-	UART0->lcr = 0x83;
-	UART0->dll = divisor & 0xff;
-	UART0->dlh = (divisor >> 8) & 0xff;
-	UART0->lcr = 0x03;
-	UART0->mdr = 0; //16x over-sampling
-	UART0->pwremu_mgmt = 0x6000;
+    rt_uint32_t divisor;
+
+    divisor = (24000000 + (BPS * (16 / 2))) / (16 * BPS);
+    UART0->ier = 0;
+    UART0->lcr = 0x83; //8N1
+    UART0->dll = 0;
+    UART0->dlh = 0;
+    UART0->lcr = 0x03;
+    UART0->mcr = 0x03; //RTS,CTS
+    UART0->fcr = 0x07; //FIFO
+    UART0->lcr = 0x83;
+    UART0->dll = divisor & 0xff;
+    UART0->dlh = (divisor >> 8) & 0xff;
+    UART0->lcr = 0x03;
+    UART0->mdr = 0; //16x over-sampling
+    UART0->pwremu_mgmt = 0x6000;
 }
 
 /**
@@ -167,35 +167,35 @@ static void rt_hw_console_init(void)
  */
 void rt_hw_board_init()
 {
-	/* initialize console */
-	rt_hw_console_init();
+    /* initialize console */
+    rt_hw_console_init();
 
-	/* initialize mmu */
-	rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0]));
+    /* initialize mmu */
+    rt_hw_mmu_init(dm365_mem_desc, sizeof(dm365_mem_desc)/sizeof(dm365_mem_desc[0]));
 
-	/* initialize hardware interrupt */
-	rt_hw_interrupt_init();
+    /* initialize hardware interrupt */
+    rt_hw_interrupt_init();
 
-	/* initialize the system clock */
-	rt_hw_clock_init();
+    /* initialize the system clock */
+    rt_hw_clock_init();
 
-	/* initialize heap memory system */
+    /* initialize heap memory system */
 #ifdef __CC_ARM
-	rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000);
+    rt_system_heap_init((void*)&Image$$ER_ZI$$ZI$$Limit, (void*)0x88000000);
 #else
-	rt_system_heap_init((void*)&__bss_end, (void*)0x88000000);
+    rt_system_heap_init((void*)&__bss_end, (void*)0x88000000);
 #endif
 
-	/* initialize early device */
+    /* initialize early device */
 #ifdef RT_USING_COMPONENTS_INIT
-	rt_components_board_init();
+    rt_components_board_init();
 #endif
 #ifdef RT_USING_CONSOLE
-	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
 
-	/* initialize timer0 */
-	rt_hw_timer_init();
+    /* initialize timer0 */
+    rt_hw_timer_init();
 
 }
 

bsp/dm365/applications/board.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 

bsp/dm365/drivers/davinci_emac.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2013-01-30     weety		first version
+ * Date           Author        Notes
+ * 2013-01-30     weety     first version
  */
 
 #ifndef _DAVINCI_EMAC_H
@@ -17,249 +17,249 @@
 #endif
 
 enum {
-	EMAC_VERSION_1,	/* DM644x */
-	EMAC_VERSION_2,	/* DM646x */
+    EMAC_VERSION_1, /* DM644x */
+    EMAC_VERSION_2, /* DM646x */
 };
 
 
 #define __iomem
 
-#define BIT(nr)			(1UL << (nr))
+#define BIT(nr)         (1UL << (nr))
 
 
 /* Configuration items */
-#define EMAC_DEF_PASS_CRC		(0) /* Do not pass CRC upto frames */
-#define EMAC_DEF_QOS_EN			(0) /* EMAC proprietary QoS disabled */
-#define EMAC_DEF_NO_BUFF_CHAIN		(0) /* No buffer chain */
-#define EMAC_DEF_MACCTRL_FRAME_EN	(0) /* Discard Maccontrol frames */
-#define EMAC_DEF_SHORT_FRAME_EN		(0) /* Discard short frames */
-#define EMAC_DEF_ERROR_FRAME_EN		(0) /* Discard error frames */
-#define EMAC_DEF_PROM_EN		(0) /* Promiscous disabled */
-#define EMAC_DEF_PROM_CH		(0) /* Promiscous channel is 0 */
-#define EMAC_DEF_BCAST_EN		(1) /* Broadcast enabled */
-#define EMAC_DEF_BCAST_CH		(0) /* Broadcast channel is 0 */
-#define EMAC_DEF_MCAST_EN		(1) /* Multicast enabled */
-#define EMAC_DEF_MCAST_CH		(0) /* Multicast channel is 0 */
-
-#define EMAC_DEF_TXPRIO_FIXED		(1) /* TX Priority is fixed */
-#define EMAC_DEF_TXPACING_EN		(0) /* TX pacing NOT supported*/
-
-#define EMAC_DEF_BUFFER_OFFSET		(0) /* Buffer offset to DMA (future) */
-#define EMAC_DEF_MIN_ETHPKTSIZE		(60) /* Minimum ethernet pkt size */
-#define EMAC_DEF_MAX_FRAME_SIZE		(1500 + 14 + 4 + 4)
-#define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
-#define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
-#define EMAC_DEF_MDIO_TICK_MS		(10) /* typically 1 tick=1 ms) */
-#define EMAC_DEF_MAX_TX_CH		(1) /* Max TX channels configured */
-#define EMAC_DEF_MAX_RX_CH		(1) /* Max RX channels configured */
-#define EMAC_POLL_WEIGHT		(64) /* Default NAPI poll weight */
+#define EMAC_DEF_PASS_CRC       (0) /* Do not pass CRC upto frames */
+#define EMAC_DEF_QOS_EN         (0) /* EMAC proprietary QoS disabled */
+#define EMAC_DEF_NO_BUFF_CHAIN      (0) /* No buffer chain */
+#define EMAC_DEF_MACCTRL_FRAME_EN   (0) /* Discard Maccontrol frames */
+#define EMAC_DEF_SHORT_FRAME_EN     (0) /* Discard short frames */
+#define EMAC_DEF_ERROR_FRAME_EN     (0) /* Discard error frames */
+#define EMAC_DEF_PROM_EN        (0) /* Promiscous disabled */
+#define EMAC_DEF_PROM_CH        (0) /* Promiscous channel is 0 */
+#define EMAC_DEF_BCAST_EN       (1) /* Broadcast enabled */
+#define EMAC_DEF_BCAST_CH       (0) /* Broadcast channel is 0 */
+#define EMAC_DEF_MCAST_EN       (1) /* Multicast enabled */
+#define EMAC_DEF_MCAST_CH       (0) /* Multicast channel is 0 */
+
+#define EMAC_DEF_TXPRIO_FIXED       (1) /* TX Priority is fixed */
+#define EMAC_DEF_TXPACING_EN        (0) /* TX pacing NOT supported*/
+
+#define EMAC_DEF_BUFFER_OFFSET      (0) /* Buffer offset to DMA (future) */
+#define EMAC_DEF_MIN_ETHPKTSIZE     (60) /* Minimum ethernet pkt size */
+#define EMAC_DEF_MAX_FRAME_SIZE     (1500 + 14 + 4 + 4)
+#define EMAC_DEF_TX_CH          (0) /* Default 0th channel */
+#define EMAC_DEF_RX_CH          (0) /* Default 0th channel */
+#define EMAC_DEF_MDIO_TICK_MS       (10) /* typically 1 tick=1 ms) */
+#define EMAC_DEF_MAX_TX_CH      (1) /* Max TX channels configured */
+#define EMAC_DEF_MAX_RX_CH      (1) /* Max RX channels configured */
+#define EMAC_POLL_WEIGHT        (64) /* Default NAPI poll weight */
 
 /* Buffer descriptor parameters */
-#define EMAC_DEF_TX_MAX_SERVICE		(32) /* TX max service BD's */
-#define EMAC_DEF_RX_MAX_SERVICE		(64) /* should = netdev->weight */
+#define EMAC_DEF_TX_MAX_SERVICE     (32) /* TX max service BD's */
+#define EMAC_DEF_RX_MAX_SERVICE     (64) /* should = netdev->weight */
 
 /* EMAC register related defines */
-#define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
-#define EMAC_NUM_MULTICAST_BITS		(64)
-#define EMAC_TEARDOWN_VALUE		(0xFFFFFFFC)
-#define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
-#define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
-#define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
-#define EMAC_RX_UNICAST_CLEAR_ALL	(0xFF)
-#define EMAC_INT_MASK_CLEAR		(0xFF)
+#define EMAC_ALL_MULTI_REG_VALUE    (0xFFFFFFFF)
+#define EMAC_NUM_MULTICAST_BITS     (64)
+#define EMAC_TEARDOWN_VALUE     (0xFFFFFFFC)
+#define EMAC_TX_CONTROL_TX_ENABLE_VAL   (0x1)
+#define EMAC_RX_CONTROL_RX_ENABLE_VAL   (0x1)
+#define EMAC_MAC_HOST_ERR_INTMASK_VAL   (0x2)
+#define EMAC_RX_UNICAST_CLEAR_ALL   (0xFF)
+#define EMAC_INT_MASK_CLEAR     (0xFF)
 
 /* RX MBP register bit positions */
-#define EMAC_RXMBP_PASSCRC_MASK		BIT(30)
-#define EMAC_RXMBP_QOSEN_MASK		BIT(29)
-#define EMAC_RXMBP_NOCHAIN_MASK		BIT(28)
-#define EMAC_RXMBP_CMFEN_MASK		BIT(24)
-#define EMAC_RXMBP_CSFEN_MASK		BIT(23)
-#define EMAC_RXMBP_CEFEN_MASK		BIT(22)
-#define EMAC_RXMBP_CAFEN_MASK		BIT(21)
-#define EMAC_RXMBP_PROMCH_SHIFT		(16)
-#define EMAC_RXMBP_PROMCH_MASK		(0x7 << 16)
-#define EMAC_RXMBP_BROADEN_MASK		BIT(13)
-#define EMAC_RXMBP_BROADCH_SHIFT	(8)
-#define EMAC_RXMBP_BROADCH_MASK		(0x7 << 8)
-#define EMAC_RXMBP_MULTIEN_MASK		BIT(5)
-#define EMAC_RXMBP_MULTICH_SHIFT	(0)
-#define EMAC_RXMBP_MULTICH_MASK		(0x7)
-#define EMAC_RXMBP_CHMASK		(0x7)
+#define EMAC_RXMBP_PASSCRC_MASK     BIT(30)
+#define EMAC_RXMBP_QOSEN_MASK       BIT(29)
+#define EMAC_RXMBP_NOCHAIN_MASK     BIT(28)
+#define EMAC_RXMBP_CMFEN_MASK       BIT(24)
+#define EMAC_RXMBP_CSFEN_MASK       BIT(23)
+#define EMAC_RXMBP_CEFEN_MASK       BIT(22)
+#define EMAC_RXMBP_CAFEN_MASK       BIT(21)
+#define EMAC_RXMBP_PROMCH_SHIFT     (16)
+#define EMAC_RXMBP_PROMCH_MASK      (0x7 << 16)
+#define EMAC_RXMBP_BROADEN_MASK     BIT(13)
+#define EMAC_RXMBP_BROADCH_SHIFT    (8)
+#define EMAC_RXMBP_BROADCH_MASK     (0x7 << 8)
+#define EMAC_RXMBP_MULTIEN_MASK     BIT(5)
+#define EMAC_RXMBP_MULTICH_SHIFT    (0)
+#define EMAC_RXMBP_MULTICH_MASK     (0x7)
+#define EMAC_RXMBP_CHMASK       (0x7)
 
 /* EMAC register definitions/bit maps used */
-# define EMAC_MBP_RXPROMISC		(0x00200000)
-# define EMAC_MBP_PROMISCCH(ch)		(((ch) & 0x7) << 16)
-# define EMAC_MBP_RXBCAST		(0x00002000)
-# define EMAC_MBP_BCASTCHAN(ch)		(((ch) & 0x7) << 8)
-# define EMAC_MBP_RXMCAST		(0x00000020)
-# define EMAC_MBP_MCASTCHAN(ch)		((ch) & 0x7)
+# define EMAC_MBP_RXPROMISC     (0x00200000)
+# define EMAC_MBP_PROMISCCH(ch)     (((ch) & 0x7) << 16)
+# define EMAC_MBP_RXBCAST       (0x00002000)
+# define EMAC_MBP_BCASTCHAN(ch)     (((ch) & 0x7) << 8)
+# define EMAC_MBP_RXMCAST       (0x00000020)
+# define EMAC_MBP_MCASTCHAN(ch)     ((ch) & 0x7)
 
 /* EMAC mac_control register */
-#define EMAC_MACCONTROL_TXPTYPE		BIT(9)
-#define EMAC_MACCONTROL_TXPACEEN	BIT(6)
-#define EMAC_MACCONTROL_GMIIEN		BIT(5)
-#define EMAC_MACCONTROL_GIGABITEN	BIT(7)
-#define EMAC_MACCONTROL_FULLDUPLEXEN	BIT(0)
-#define EMAC_MACCONTROL_RMIISPEED_MASK	BIT(15)
+#define EMAC_MACCONTROL_TXPTYPE     BIT(9)
+#define EMAC_MACCONTROL_TXPACEEN    BIT(6)
+#define EMAC_MACCONTROL_GMIIEN      BIT(5)
+#define EMAC_MACCONTROL_GIGABITEN   BIT(7)
+#define EMAC_MACCONTROL_FULLDUPLEXEN    BIT(0)
+#define EMAC_MACCONTROL_RMIISPEED_MASK  BIT(15)
 
 /* GIGABIT MODE related bits */
-#define EMAC_DM646X_MACCONTORL_GIG	BIT(7)
-#define EMAC_DM646X_MACCONTORL_GIGFORCE	BIT(17)
+#define EMAC_DM646X_MACCONTORL_GIG  BIT(7)
+#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
 
 /* EMAC mac_status register */
-#define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)
-#define EMAC_MACSTATUS_TXERRCODE_SHIFT	(20)
-#define EMAC_MACSTATUS_TXERRCH_MASK	(0x7)
-#define EMAC_MACSTATUS_TXERRCH_SHIFT	(16)
-#define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)
-#define EMAC_MACSTATUS_RXERRCODE_SHIFT	(12)
-#define EMAC_MACSTATUS_RXERRCH_MASK	(0x7)
-#define EMAC_MACSTATUS_RXERRCH_SHIFT	(8)
+#define EMAC_MACSTATUS_TXERRCODE_MASK   (0xF00000)
+#define EMAC_MACSTATUS_TXERRCODE_SHIFT  (20)
+#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
+#define EMAC_MACSTATUS_TXERRCH_SHIFT    (16)
+#define EMAC_MACSTATUS_RXERRCODE_MASK   (0xF000)
+#define EMAC_MACSTATUS_RXERRCODE_SHIFT  (12)
+#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
+#define EMAC_MACSTATUS_RXERRCH_SHIFT    (8)
 
 /* EMAC RX register masks */
-#define EMAC_RX_MAX_LEN_MASK		(0xFFFF)
-#define EMAC_RX_BUFFER_OFFSET_MASK	(0xFFFF)
+#define EMAC_RX_MAX_LEN_MASK        (0xFFFF)
+#define EMAC_RX_BUFFER_OFFSET_MASK  (0xFFFF)
 
 /* MAC_IN_VECTOR (0x180) register bit fields */
-#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT	BIT(17)
-#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT	BIT(16)
-#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC	BIT(8)
-#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC	BIT(0)
+#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT  BIT(17)
+#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT  BIT(16)
+#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC    BIT(8)
+#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC    BIT(0)
 
 /** NOTE:: For DM646x the IN_VECTOR has changed */
-#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC	BIT(EMAC_DEF_RX_CH)
-#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC	BIT(16 + EMAC_DEF_TX_CH)
-#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT	BIT(26)
-#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT	BIT(27)
+#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC    BIT(EMAC_DEF_RX_CH)
+#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC    BIT(16 + EMAC_DEF_TX_CH)
+#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT  BIT(26)
+#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT  BIT(27)
 
 /* CPPI bit positions */
-#define EMAC_CPPI_SOP_BIT		BIT(31)
-#define EMAC_CPPI_EOP_BIT		BIT(30)
-#define EMAC_CPPI_OWNERSHIP_BIT		BIT(29)
-#define EMAC_CPPI_EOQ_BIT		BIT(28)
+#define EMAC_CPPI_SOP_BIT       BIT(31)
+#define EMAC_CPPI_EOP_BIT       BIT(30)
+#define EMAC_CPPI_OWNERSHIP_BIT     BIT(29)
+#define EMAC_CPPI_EOQ_BIT       BIT(28)
 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
-#define EMAC_CPPI_PASS_CRC_BIT		BIT(26)
-#define EMAC_RX_BD_BUF_SIZE		(0xFFFF)
-#define EMAC_BD_LENGTH_FOR_CACHE	(16) /* only CPPI bytes */
-#define EMAC_RX_BD_PKT_LENGTH_MASK	(0xFFFF)
+#define EMAC_CPPI_PASS_CRC_BIT      BIT(26)
+#define EMAC_RX_BD_BUF_SIZE     (0xFFFF)
+#define EMAC_BD_LENGTH_FOR_CACHE    (16) /* only CPPI bytes */
+#define EMAC_RX_BD_PKT_LENGTH_MASK  (0xFFFF)
 
 /* Max hardware defines */
-#define EMAC_MAX_TXRX_CHANNELS		 (8)  /* Max hardware channels */
+#define EMAC_MAX_TXRX_CHANNELS       (8)  /* Max hardware channels */
 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
 
 /* EMAC Peripheral Device Register Memory Layout structure */
-#define EMAC_TXIDVER		0x0
-#define EMAC_TXCONTROL		0x4
-#define EMAC_TXTEARDOWN		0x8
-#define EMAC_RXIDVER		0x10
-#define EMAC_RXCONTROL		0x14
-#define EMAC_RXTEARDOWN		0x18
-#define EMAC_TXINTSTATRAW	0x80
-#define EMAC_TXINTSTATMASKED	0x84
-#define EMAC_TXINTMASKSET	0x88
-#define EMAC_TXINTMASKCLEAR	0x8C
-#define EMAC_MACINVECTOR	0x90
-
-#define EMAC_DM646X_MACEOIVECTOR	0x94
-
-#define EMAC_RXINTSTATRAW	0xA0
-#define EMAC_RXINTSTATMASKED	0xA4
-#define EMAC_RXINTMASKSET	0xA8
-#define EMAC_RXINTMASKCLEAR	0xAC
-#define EMAC_MACINTSTATRAW	0xB0
-#define EMAC_MACINTSTATMASKED	0xB4
-#define EMAC_MACINTMASKSET	0xB8
-#define EMAC_MACINTMASKCLEAR	0xBC
-
-#define EMAC_RXMBPENABLE	0x100
-#define EMAC_RXUNICASTSET	0x104
-#define EMAC_RXUNICASTCLEAR	0x108
-#define EMAC_RXMAXLEN		0x10C
-#define EMAC_RXBUFFEROFFSET	0x110
-#define EMAC_RXFILTERLOWTHRESH	0x114
-
-#define EMAC_MACCONTROL		0x160
-#define EMAC_MACSTATUS		0x164
-#define EMAC_EMCONTROL		0x168
-#define EMAC_FIFOCONTROL	0x16C
-#define EMAC_MACCONFIG		0x170
-#define EMAC_SOFTRESET		0x174
-#define EMAC_MACSRCADDRLO	0x1D0
-#define EMAC_MACSRCADDRHI	0x1D4
-#define EMAC_MACHASH1		0x1D8
-#define EMAC_MACHASH2		0x1DC
-#define EMAC_MACADDRLO		0x500
-#define EMAC_MACADDRHI		0x504
-#define EMAC_MACINDEX		0x508
+#define EMAC_TXIDVER        0x0
+#define EMAC_TXCONTROL      0x4
+#define EMAC_TXTEARDOWN     0x8
+#define EMAC_RXIDVER        0x10
+#define EMAC_RXCONTROL      0x14
+#define EMAC_RXTEARDOWN     0x18
+#define EMAC_TXINTSTATRAW   0x80
+#define EMAC_TXINTSTATMASKED    0x84
+#define EMAC_TXINTMASKSET   0x88
+#define EMAC_TXINTMASKCLEAR 0x8C
+#define EMAC_MACINVECTOR    0x90
+
+#define EMAC_DM646X_MACEOIVECTOR    0x94
+
+#define EMAC_RXINTSTATRAW   0xA0
+#define EMAC_RXINTSTATMASKED    0xA4
+#define EMAC_RXINTMASKSET   0xA8
+#define EMAC_RXINTMASKCLEAR 0xAC
+#define EMAC_MACINTSTATRAW  0xB0
+#define EMAC_MACINTSTATMASKED   0xB4
+#define EMAC_MACINTMASKSET  0xB8
+#define EMAC_MACINTMASKCLEAR    0xBC
+
+#define EMAC_RXMBPENABLE    0x100
+#define EMAC_RXUNICASTSET   0x104
+#define EMAC_RXUNICASTCLEAR 0x108
+#define EMAC_RXMAXLEN       0x10C
+#define EMAC_RXBUFFEROFFSET 0x110
+#define EMAC_RXFILTERLOWTHRESH  0x114
+
+#define EMAC_MACCONTROL     0x160
+#define EMAC_MACSTATUS      0x164
+#define EMAC_EMCONTROL      0x168
+#define EMAC_FIFOCONTROL    0x16C
+#define EMAC_MACCONFIG      0x170
+#define EMAC_SOFTRESET      0x174
+#define EMAC_MACSRCADDRLO   0x1D0
+#define EMAC_MACSRCADDRHI   0x1D4
+#define EMAC_MACHASH1       0x1D8
+#define EMAC_MACHASH2       0x1DC
+#define EMAC_MACADDRLO      0x500
+#define EMAC_MACADDRHI      0x504
+#define EMAC_MACINDEX       0x508
 
 /* EMAC HDP and Completion registors */
-#define EMAC_TXHDP(ch)		(0x600 + (ch * 4))
-#define EMAC_RXHDP(ch)		(0x620 + (ch * 4))
-#define EMAC_TXCP(ch)		(0x640 + (ch * 4))
-#define EMAC_RXCP(ch)		(0x660 + (ch * 4))
+#define EMAC_TXHDP(ch)      (0x600 + (ch * 4))
+#define EMAC_RXHDP(ch)      (0x620 + (ch * 4))
+#define EMAC_TXCP(ch)       (0x640 + (ch * 4))
+#define EMAC_RXCP(ch)       (0x660 + (ch * 4))
 
 /* EMAC statistics registers */
-#define EMAC_RXGOODFRAMES	0x200
-#define EMAC_RXBCASTFRAMES	0x204
-#define EMAC_RXMCASTFRAMES	0x208
-#define EMAC_RXPAUSEFRAMES	0x20C
-#define EMAC_RXCRCERRORS	0x210
-#define EMAC_RXALIGNCODEERRORS	0x214
-#define EMAC_RXOVERSIZED	0x218
-#define EMAC_RXJABBER		0x21C
-#define EMAC_RXUNDERSIZED	0x220
-#define EMAC_RXFRAGMENTS	0x224
-#define EMAC_RXFILTERED		0x228
-#define EMAC_RXQOSFILTERED	0x22C
-#define EMAC_RXOCTETS		0x230
-#define EMAC_TXGOODFRAMES	0x234
-#define EMAC_TXBCASTFRAMES	0x238
-#define EMAC_TXMCASTFRAMES	0x23C
-#define EMAC_TXPAUSEFRAMES	0x240
-#define EMAC_TXDEFERRED		0x244
-#define EMAC_TXCOLLISION	0x248
-#define EMAC_TXSINGLECOLL	0x24C
-#define EMAC_TXMULTICOLL	0x250
-#define EMAC_TXEXCESSIVECOLL	0x254
-#define EMAC_TXLATECOLL		0x258
-#define EMAC_TXUNDERRUN		0x25C
-#define EMAC_TXCARRIERSENSE	0x260
-#define EMAC_TXOCTETS		0x264
-#define EMAC_NETOCTETS		0x280
-#define EMAC_RXSOFOVERRUNS	0x284
-#define EMAC_RXMOFOVERRUNS	0x288
-#define EMAC_RXDMAOVERRUNS	0x28C
+#define EMAC_RXGOODFRAMES   0x200
+#define EMAC_RXBCASTFRAMES  0x204
+#define EMAC_RXMCASTFRAMES  0x208
+#define EMAC_RXPAUSEFRAMES  0x20C
+#define EMAC_RXCRCERRORS    0x210
+#define EMAC_RXALIGNCODEERRORS  0x214
+#define EMAC_RXOVERSIZED    0x218
+#define EMAC_RXJABBER       0x21C
+#define EMAC_RXUNDERSIZED   0x220
+#define EMAC_RXFRAGMENTS    0x224
+#define EMAC_RXFILTERED     0x228
+#define EMAC_RXQOSFILTERED  0x22C
+#define EMAC_RXOCTETS       0x230
+#define EMAC_TXGOODFRAMES   0x234
+#define EMAC_TXBCASTFRAMES  0x238
+#define EMAC_TXMCASTFRAMES  0x23C
+#define EMAC_TXPAUSEFRAMES  0x240
+#define EMAC_TXDEFERRED     0x244
+#define EMAC_TXCOLLISION    0x248
+#define EMAC_TXSINGLECOLL   0x24C
+#define EMAC_TXMULTICOLL    0x250
+#define EMAC_TXEXCESSIVECOLL    0x254
+#define EMAC_TXLATECOLL     0x258
+#define EMAC_TXUNDERRUN     0x25C
+#define EMAC_TXCARRIERSENSE 0x260
+#define EMAC_TXOCTETS       0x264
+#define EMAC_NETOCTETS      0x280
+#define EMAC_RXSOFOVERRUNS  0x284
+#define EMAC_RXMOFOVERRUNS  0x288
+#define EMAC_RXDMAOVERRUNS  0x28C
 
 /* EMAC DM644x control registers */
-#define EMAC_CTRL_EWCTL		(0x4)
-#define EMAC_CTRL_EWINTTCNT	(0x8)
+#define EMAC_CTRL_EWCTL     (0x4)
+#define EMAC_CTRL_EWINTTCNT (0x8)
 
 /* EMAC MDIO related */
 /* Mask & Control defines */
-#define MDIO_CONTROL_CLKDIV	(0xFF)
-#define MDIO_CONTROL_ENABLE	BIT(30)
-#define MDIO_USERACCESS_GO	BIT(31)
-#define MDIO_USERACCESS_WRITE	BIT(30)
-#define MDIO_USERACCESS_READ	(0)
-#define MDIO_USERACCESS_REGADR	(0x1F << 21)
-#define MDIO_USERACCESS_PHYADR	(0x1F << 16)
-#define MDIO_USERACCESS_DATA	(0xFFFF)
-#define MDIO_USERPHYSEL_LINKSEL	BIT(7)
-#define MDIO_VER_MODID		(0xFFFF << 16)
-#define MDIO_VER_REVMAJ		(0xFF   << 8)
-#define MDIO_VER_REVMIN		(0xFF)
-
-#define MDIO_USERACCESS(inst)	(0x80 + (inst * 8))
-#define MDIO_USERPHYSEL(inst)	(0x84 + (inst * 8))
-#define MDIO_CONTROL		(0x04)
+#define MDIO_CONTROL_CLKDIV (0xFF)
+#define MDIO_CONTROL_ENABLE BIT(30)
+#define MDIO_USERACCESS_GO  BIT(31)
+#define MDIO_USERACCESS_WRITE   BIT(30)
+#define MDIO_USERACCESS_READ    (0)
+#define MDIO_USERACCESS_REGADR  (0x1F << 21)
+#define MDIO_USERACCESS_PHYADR  (0x1F << 16)
+#define MDIO_USERACCESS_DATA    (0xFFFF)
+#define MDIO_USERPHYSEL_LINKSEL BIT(7)
+#define MDIO_VER_MODID      (0xFFFF << 16)
+#define MDIO_VER_REVMAJ     (0xFF   << 8)
+#define MDIO_VER_REVMIN     (0xFF)
+
+#define MDIO_USERACCESS(inst)   (0x80 + (inst * 8))
+#define MDIO_USERPHYSEL(inst)   (0x84 + (inst * 8))
+#define MDIO_CONTROL        (0x04)
 
 /* EMAC DM646X control module registers */
-#define EMAC_DM646X_CMRXINTEN	(0x14)
-#define EMAC_DM646X_CMTXINTEN	(0x18)
+#define EMAC_DM646X_CMRXINTEN   (0x14)
+#define EMAC_DM646X_CMTXINTEN   (0x18)
 
 /* EMAC EOI codes for C0 */
-#define EMAC_DM646X_MAC_EOI_C0_RXEN	(0x01)
-#define EMAC_DM646X_MAC_EOI_C0_TXEN	(0x02)
+#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
+#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
 
 /* EMAC Stats Clear Mask */
 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
@@ -269,9 +269,9 @@ enum {
  * EMAC network buffer data structure
  */
 struct emac_netbufobj {
-	void *buf_token;
-	char *data_ptr;
-	int length;
+    void *buf_token;
+    char *data_ptr;
+    int length;
 };
 
 /** net_pkt_obj: EMAC network packet data structure
@@ -279,10 +279,10 @@ struct emac_netbufobj {
  * EMAC network packet data structure - supports buffer list (for future)
  */
 struct emac_netpktobj {
-	void *pkt_token; /* data token may hold tx/rx chan id */
-	struct emac_netbufobj *buf_list; /* array of network buffer objects */
-	int num_bufs;
-	int pkt_length;
+    void *pkt_token; /* data token may hold tx/rx chan id */
+    struct emac_netbufobj *buf_list; /* array of network buffer objects */
+    int num_bufs;
+    int pkt_length;
 };
 
 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
@@ -290,12 +290,12 @@ struct emac_netpktobj {
  * EMAC TX Buffer descriptor data structure
  */
 struct emac_tx_bd {
-	int h_next;
-	int buff_ptr;
-	int off_b_len;
-	int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
-	struct emac_tx_bd __iomem *next;
-	void *buf_token;
+    int h_next;
+    int buff_ptr;
+    int off_b_len;
+    int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
+    struct emac_tx_bd __iomem *next;
+    void *buf_token;
 };
 
 /** emac_txch: EMAC TX Channel data structure
@@ -303,29 +303,29 @@ struct emac_tx_bd {
  * EMAC TX Channel data structure
  */
 struct emac_txch {
-	/* Config related */
-	rt_uint32_t num_bd;
-	rt_uint32_t service_max;
-
-	/* CPPI specific */
-	rt_uint32_t alloc_size;
-	void __iomem *bd_mem;
-	struct emac_tx_bd __iomem *bd_pool_head;
-	struct emac_tx_bd __iomem *active_queue_head;
-	struct emac_tx_bd __iomem *active_queue_tail;
-	struct emac_tx_bd __iomem *last_hw_bdprocessed;
-	rt_uint32_t queue_active;
-	rt_uint32_t teardown_pending;
-	rt_uint32_t *tx_complete;
-
-	/** statistics */
-	rt_uint32_t proc_count;     /* TX: # of times emac_tx_bdproc is called */
-	rt_uint32_t mis_queued_packets;
-	rt_uint32_t queue_reinit;
-	rt_uint32_t end_of_queue_add;
-	rt_uint32_t out_of_tx_bd;
-	rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */
-	rt_uint32_t active_queue_count;
+    /* Config related */
+    rt_uint32_t num_bd;
+    rt_uint32_t service_max;
+
+    /* CPPI specific */
+    rt_uint32_t alloc_size;
+    void __iomem *bd_mem;
+    struct emac_tx_bd __iomem *bd_pool_head;
+    struct emac_tx_bd __iomem *active_queue_head;
+    struct emac_tx_bd __iomem *active_queue_tail;
+    struct emac_tx_bd __iomem *last_hw_bdprocessed;
+    rt_uint32_t queue_active;
+    rt_uint32_t teardown_pending;
+    rt_uint32_t *tx_complete;
+
+    /** statistics */
+    rt_uint32_t proc_count;     /* TX: # of times emac_tx_bdproc is called */
+    rt_uint32_t mis_queued_packets;
+    rt_uint32_t queue_reinit;
+    rt_uint32_t end_of_queue_add;
+    rt_uint32_t out_of_tx_bd;
+    rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */
+    rt_uint32_t active_queue_count;
 };
 
 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
@@ -333,13 +333,13 @@ struct emac_txch {
  * EMAC RX Buffer descriptor data structure
  */
 struct emac_rx_bd {
-	int h_next;
-	int buff_ptr;
-	int off_b_len;
-	int mode;
-	struct emac_rx_bd __iomem *next;
-	void *data_ptr;
-	void *buf_token;
+    int h_next;
+    int buff_ptr;
+    int off_b_len;
+    int mode;
+    struct emac_rx_bd __iomem *next;
+    void *data_ptr;
+    void *buf_token;
 };
 
 /** emac_rxch: EMAC RX Channel data structure
@@ -347,68 +347,68 @@ struct emac_rx_bd {
  * EMAC RX Channel data structure
  */
 struct emac_rxch {
-	/* configuration info */
-	rt_uint32_t num_bd;
-	rt_uint32_t service_max;
-	rt_uint32_t buf_size;
-	char mac_addr[6];
-
-	/** CPPI specific */
-	rt_uint32_t alloc_size;
-	void __iomem *bd_mem;
-	struct emac_rx_bd __iomem *bd_pool_head;
-	struct emac_rx_bd __iomem *active_queue_head;
-	struct emac_rx_bd __iomem *active_queue_tail;
-	rt_uint32_t queue_active;
-	rt_uint32_t teardown_pending;
-
-	/* packet and buffer objects */
-	struct emac_netpktobj pkt_queue;
-	struct emac_netbufobj buf_queue;
-
-	/** statistics */
-	rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */
-	rt_uint32_t processed_bd;
-	rt_uint32_t recycled_bd;
-	rt_uint32_t out_of_rx_bd;
-	rt_uint32_t out_of_rx_buffers;
-	rt_uint32_t queue_reinit;
-	rt_uint32_t end_of_queue_add;
-	rt_uint32_t end_of_queue;
-	rt_uint32_t mis_queued_packets;
+    /* configuration info */
+    rt_uint32_t num_bd;
+    rt_uint32_t service_max;
+    rt_uint32_t buf_size;
+    char mac_addr[6];
+
+    /** CPPI specific */
+    rt_uint32_t alloc_size;
+    void __iomem *bd_mem;
+    struct emac_rx_bd __iomem *bd_pool_head;
+    struct emac_rx_bd __iomem *active_queue_head;
+    struct emac_rx_bd __iomem *active_queue_tail;
+    rt_uint32_t queue_active;
+    rt_uint32_t teardown_pending;
+
+    /* packet and buffer objects */
+    struct emac_netpktobj pkt_queue;
+    struct emac_netbufobj buf_queue;
+
+    /** statistics */
+    rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */
+    rt_uint32_t processed_bd;
+    rt_uint32_t recycled_bd;
+    rt_uint32_t out_of_rx_bd;
+    rt_uint32_t out_of_rx_buffers;
+    rt_uint32_t queue_reinit;
+    rt_uint32_t end_of_queue_add;
+    rt_uint32_t end_of_queue;
+    rt_uint32_t mis_queued_packets;
 };
 
 struct net_device_stats
 {
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received 	*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
-
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
-
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-	
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
+    unsigned long   rx_packets;     /* total packets received   */
+    unsigned long   tx_packets;     /* total packets transmitted    */
+    unsigned long   rx_bytes;       /* total bytes received     */
+    unsigned long   tx_bytes;       /* total bytes transmitted  */
+    unsigned long   rx_errors;      /* bad packets received     */
+    unsigned long   tx_errors;      /* packet transmit problems */
+    unsigned long   rx_dropped;     /* no space in linux buffers    */
+    unsigned long   tx_dropped;     /* no space available in linux  */
+    unsigned long   multicast;      /* multicast packets received   */
+    unsigned long   collisions;
+
+    /* detailed rx_errors: */
+    unsigned long   rx_length_errors;
+    unsigned long   rx_over_errors;     /* receiver ring buff overflow  */
+    unsigned long   rx_crc_errors;      /* recved pkt with crc error    */
+    unsigned long   rx_frame_errors;    /* recv'd frame alignment error */
+    unsigned long   rx_fifo_errors;     /* recv'r fifo overrun      */
+    unsigned long   rx_missed_errors;   /* receiver missed packet   */
+
+    /* detailed tx_errors */
+    unsigned long   tx_aborted_errors;
+    unsigned long   tx_carrier_errors;
+    unsigned long   tx_fifo_errors;
+    unsigned long   tx_heartbeat_errors;
+    unsigned long   tx_window_errors;
+
+    /* for cslip etc */
+    unsigned long   rx_compressed;
+    unsigned long   tx_compressed;
 };
 
 
@@ -419,44 +419,44 @@ struct net_device_stats
 #define MAX_ADDR_LEN 6
 
 struct emac_priv {
-	/* inherit from ethernet device */
-	struct eth_device parent;
-
-	/* interface address info. */
-	rt_uint8_t  mac_addr[MAX_ADDR_LEN];		/* hw address	*/
-	unsigned short		phy_addr;
-	
-	struct rt_semaphore tx_lock;
-	struct rt_semaphore rx_lock;
-	void __iomem *remap_addr;
-	rt_uint32_t emac_base_phys;
-	void __iomem *emac_base;
-	void __iomem *ctrl_base;
-	void __iomem *emac_ctrl_ram;
-	void __iomem *mdio_base;
-	rt_uint32_t ctrl_ram_size;
-	rt_uint32_t hw_ram_addr;
-	struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
-	struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
-	rt_uint32_t link; /* 1=link on, 0=link off */
-	rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
-	rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */
-	rt_uint32_t rx_buf_size;
-	rt_uint32_t isr_count;
-	rt_uint8_t rmii_en;
-	rt_uint8_t version;
-	struct net_device_stats net_dev_stats;
-	rt_uint32_t mac_hash1;
-	rt_uint32_t mac_hash2;
-	rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
-	rt_uint32_t rx_addr_type;
-	/* periodic timer required for MDIO polling */
-	struct rt_timer  timer;
-	rt_uint32_t periodic_ticks;
-	rt_uint32_t timer_active;
-	rt_uint32_t phy_mask;
-	/* mii_bus,phy members */
-	struct rt_semaphore lock;
+    /* inherit from ethernet device */
+    struct eth_device parent;
+
+    /* interface address info. */
+    rt_uint8_t  mac_addr[MAX_ADDR_LEN];     /* hw address   */
+    unsigned short      phy_addr;
+
+    struct rt_semaphore tx_lock;
+    struct rt_semaphore rx_lock;
+    void __iomem *remap_addr;
+    rt_uint32_t emac_base_phys;
+    void __iomem *emac_base;
+    void __iomem *ctrl_base;
+    void __iomem *emac_ctrl_ram;
+    void __iomem *mdio_base;
+    rt_uint32_t ctrl_ram_size;
+    rt_uint32_t hw_ram_addr;
+    struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
+    struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
+    rt_uint32_t link; /* 1=link on, 0=link off */
+    rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
+    rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */
+    rt_uint32_t rx_buf_size;
+    rt_uint32_t isr_count;
+    rt_uint8_t rmii_en;
+    rt_uint8_t version;
+    struct net_device_stats net_dev_stats;
+    rt_uint32_t mac_hash1;
+    rt_uint32_t mac_hash2;
+    rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
+    rt_uint32_t rx_addr_type;
+    /* periodic timer required for MDIO polling */
+    struct rt_timer  timer;
+    rt_uint32_t periodic_ticks;
+    rt_uint32_t timer_active;
+    rt_uint32_t phy_mask;
+    /* mii_bus,phy members */
+    struct rt_semaphore lock;
 };
 
 

bsp/dm365/drivers/davinci_serial.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
@@ -18,35 +18,35 @@ static struct rt_serial_device davinci_serial_dev0;
 static struct rt_serial_device davinci_serial_dev1;
 
 
-#define LSR_DR		0x01		/* Data ready */
-#define LSR_THRE	0x20		/* Xmit holding register empty */
-//#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
+#define LSR_DR      0x01        /* Data ready */
+#define LSR_THRE    0x20        /* Xmit holding register empty */
+//#define   USTAT_TXB_EMPTY     0x02    /* tx buffer empty */
+#define BPS                 115200  /* serial baudrate */
 
 typedef struct uartport
 {
-	volatile rt_uint32_t rbr;
-	volatile rt_uint32_t ier;
-	volatile rt_uint32_t fcr;
-	volatile rt_uint32_t lcr;
-	volatile rt_uint32_t mcr;
-	volatile rt_uint32_t lsr;
-	volatile rt_uint32_t msr;
-	volatile rt_uint32_t scr;
-	volatile rt_uint32_t dll;
-	volatile rt_uint32_t dlh;
-	
-	volatile rt_uint32_t res[2];
-	volatile rt_uint32_t pwremu_mgmt;
-	volatile rt_uint32_t mdr;
+    volatile rt_uint32_t rbr;
+    volatile rt_uint32_t ier;
+    volatile rt_uint32_t fcr;
+    volatile rt_uint32_t lcr;
+    volatile rt_uint32_t mcr;
+    volatile rt_uint32_t lsr;
+    volatile rt_uint32_t msr;
+    volatile rt_uint32_t scr;
+    volatile rt_uint32_t dll;
+    volatile rt_uint32_t dlh;
+
+    volatile rt_uint32_t res[2];
+    volatile rt_uint32_t pwremu_mgmt;
+    volatile rt_uint32_t mdr;
 }uartport;
 
 #define thr rbr
 #define iir fcr
 
-#define UART0	((struct uartport *)DAVINCI_UART0_BASE)
+#define UART0   ((struct uartport *)DAVINCI_UART0_BASE)
 
-#define UART1	((struct uartport *)DM365_UART1_BASE)
+#define UART1   ((struct uartport *)DM365_UART1_BASE)
 
 
 /**
@@ -54,8 +54,8 @@ typedef struct uartport
  */
 void rt_davinci_serial_handler(int vector, void *param)
 {
-	struct rt_serial_device *dev = (struct rt_serial_device *)param;
-	rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND);
+    struct rt_serial_device *dev = (struct rt_serial_device *)param;
+    rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND);
 }
 
 /**
@@ -70,23 +70,23 @@ static rt_err_t davinci_uart_configure(struct rt_serial_device *serial,
 static rt_err_t davinci_uart_control(struct rt_serial_device *serial,
                               int cmd, void *arg)
 {
-	uartport *uart = serial->parent.user_data;
+    uartport *uart = serial->parent.user_data;
 
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
         /* disable rx irq */
-		if (uart == UART0)
-			rt_hw_interrupt_mask(IRQ_UARTINT0);
-		else if (uart == UART1)
-			rt_hw_interrupt_mask(IRQ_UARTINT1);
+        if (uart == UART0)
+            rt_hw_interrupt_mask(IRQ_UARTINT0);
+        else if (uart == UART1)
+            rt_hw_interrupt_mask(IRQ_UARTINT1);
         break;
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-		if (uart == UART0)
-			rt_hw_interrupt_umask(IRQ_UARTINT0);
-		else if (uart == UART1)
-			rt_hw_interrupt_umask(IRQ_UARTINT1);
+        if (uart == UART0)
+            rt_hw_interrupt_umask(IRQ_UARTINT0);
+        else if (uart == UART1)
+            rt_hw_interrupt_umask(IRQ_UARTINT1);
         break;
     }
 
@@ -96,10 +96,10 @@ static rt_err_t davinci_uart_control(struct rt_serial_device *serial,
 static int davinci_uart_putc(struct rt_serial_device *serial, char c)
 {
     rt_uint32_t level;
-	uartport *uart = serial->parent.user_data;
+    uartport *uart = serial->parent.user_data;
 
     while (!(uart->lsr & LSR_THRE));
-	uart->thr = c;
+    uart->thr = c;
 
     return 1;
 }
@@ -107,16 +107,16 @@ static int davinci_uart_putc(struct rt_serial_device *serial, char c)
 static int davinci_uart_getc(struct rt_serial_device *serial)
 {
     int result;
-	uartport *uart = serial->parent.user_data;
+    uartport *uart = serial->parent.user_data;
 
     if (uart->lsr & LSR_DR)
-	{
-		result = uart->rbr & 0xff;
-	}
-	else
-	{
-		result = -1;
-	}
+    {
+        result = uart->rbr & 0xff;
+    }
+    else
+    {
+        result = -1;
+    }
 
     return result;
 }
@@ -131,78 +131,78 @@ static const struct rt_uart_ops davinci_uart_ops =
 
 void davinci_uart0_init(void)
 {
-	rt_uint32_t divisor;
-
-	divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200);
-	UART0->ier = 0;
-	UART0->lcr = 0x83; //8N1
-	UART0->dll = 0;
-	UART0->dlh = 0;
-	UART0->lcr = 0x03;
-	UART0->mcr = 0x03; //RTS,CTS
-	UART0->fcr = 0x07; //FIFO
-	UART0->lcr = 0x83;
-	UART0->dll = divisor & 0xff;
-	UART0->dlh = (divisor >> 8) & 0xff;
-	UART0->lcr = 0x03;
-	UART0->mdr = 0; //16x over-sampling
-	UART0->pwremu_mgmt = 0x6000;
-	rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, 
-							(void *)&davinci_serial_dev0, "UART0");
-	rt_hw_interrupt_mask(IRQ_UARTINT0);
-	UART0->ier = 0x05;
+    rt_uint32_t divisor;
+
+    divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200);
+    UART0->ier = 0;
+    UART0->lcr = 0x83; //8N1
+    UART0->dll = 0;
+    UART0->dlh = 0;
+    UART0->lcr = 0x03;
+    UART0->mcr = 0x03; //RTS,CTS
+    UART0->fcr = 0x07; //FIFO
+    UART0->lcr = 0x83;
+    UART0->dll = divisor & 0xff;
+    UART0->dlh = (divisor >> 8) & 0xff;
+    UART0->lcr = 0x03;
+    UART0->mdr = 0; //16x over-sampling
+    UART0->pwremu_mgmt = 0x6000;
+    rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler,
+                            (void *)&davinci_serial_dev0, "UART0");
+    rt_hw_interrupt_mask(IRQ_UARTINT0);
+    UART0->ier = 0x05;
 }
 
 void davinci_uart_gpio_init()
 {
-	rt_uint32_t val;
-
-	val = davinci_readl(PINMUX3);
-	val &= 0xf3ffffff; /* gio23 RS485_CTRL */
-	val |= 0x60000000; /*UART1_TXD (gio25)*/
-	davinci_writel(val, PINMUX3);
-	val = davinci_readl(PINMUX4);
-	val |= 0x0000c000; /* UART1_RXD (gio34) */
-	davinci_writel(val, PINMUX4);
-
-	val = davinci_readl(DAVINCI_GPIO_BASE + 0x10);
-	val &= ~(1 << 23);
-	davinci_writel(val, DAVINCI_GPIO_BASE + 0x10);
-	davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C);
+    rt_uint32_t val;
+
+    val = davinci_readl(PINMUX3);
+    val &= 0xf3ffffff; /* gio23 RS485_CTRL */
+    val |= 0x60000000; /*UART1_TXD (gio25)*/
+    davinci_writel(val, PINMUX3);
+    val = davinci_readl(PINMUX4);
+    val |= 0x0000c000; /* UART1_RXD (gio34) */
+    davinci_writel(val, PINMUX4);
+
+    val = davinci_readl(DAVINCI_GPIO_BASE + 0x10);
+    val &= ~(1 << 23);
+    davinci_writel(val, DAVINCI_GPIO_BASE + 0x10);
+    davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C);
 }
 
 void davinci_uart1_init(void)
 {
-	rt_uint32_t divisor;
-	rt_uint32_t freq;
-	rt_uint32_t baudrate;
-	struct clk *clk;
-
-	davinci_uart_gpio_init();
-	psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE);
-	clk = clk_get("UART1");
-	freq = clk_get_rate(clk);
-
-	baudrate = 9600;
-	divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate);
-	UART1->ier = 0;
-	UART1->lcr = 0x87; //8N2, 0x83 8N1
-	UART1->dll = 0;
-	UART1->dlh = 0;
-	UART1->lcr = 0x07;
-	UART1->mcr = 0x03; //RTS,CTS
-	UART1->fcr = 0x07; //FIFO
-	UART1->lcr = 0x87;
-	UART1->dll = divisor & 0xff;
-	UART1->dlh = (divisor >> 8) & 0xff;
-	UART1->lcr = 0x07;
-	UART1->mdr = 0; //16x over-sampling
-	UART1->pwremu_mgmt = 0x6000;
-	
-	rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, 
-							(void *)&davinci_serial_dev1, "UART1");
-	rt_hw_interrupt_mask(IRQ_UARTINT1);
-	UART1->ier = 0x05;
+    rt_uint32_t divisor;
+    rt_uint32_t freq;
+    rt_uint32_t baudrate;
+    struct clk *clk;
+
+    davinci_uart_gpio_init();
+    psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE);
+    clk = clk_get("UART1");
+    freq = clk_get_rate(clk);
+
+    baudrate = 9600;
+    divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate);
+    UART1->ier = 0;
+    UART1->lcr = 0x87; //8N2, 0x83 8N1
+    UART1->dll = 0;
+    UART1->dlh = 0;
+    UART1->lcr = 0x07;
+    UART1->mcr = 0x03; //RTS,CTS
+    UART1->fcr = 0x07; //FIFO
+    UART1->lcr = 0x87;
+    UART1->dll = divisor & 0xff;
+    UART1->dlh = (divisor >> 8) & 0xff;
+    UART1->lcr = 0x07;
+    UART1->mdr = 0; //16x over-sampling
+    UART1->pwremu_mgmt = 0x6000;
+
+    rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler,
+                            (void *)&davinci_serial_dev1, "UART1");
+    rt_hw_interrupt_mask(IRQ_UARTINT1);
+    UART1->ier = 0x05;
 }
 
 
@@ -211,39 +211,39 @@ void davinci_uart1_init(void)
  */
 int rt_hw_uart_init(void)
 {
-	davinci_serial_dev0.ops = &davinci_uart_ops;
+    davinci_serial_dev0.ops = &davinci_uart_ops;
     //davinci_serial_dev0.config = RT_SERIAL_CONFIG_DEFAULT;
-	davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200;
+    davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200;
     davinci_serial_dev0.config.bit_order = BIT_ORDER_LSB;
     davinci_serial_dev0.config.data_bits = DATA_BITS_8;
     davinci_serial_dev0.config.parity = PARITY_NONE;
     davinci_serial_dev0.config.stop_bits = STOP_BITS_1;
     davinci_serial_dev0.config.invert = NRZ_NORMAL;
-	davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&davinci_serial_dev0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           UART0);
-	davinci_uart0_init();
+    davinci_uart0_init();
 
-	davinci_serial_dev1.ops = &davinci_uart_ops;
+    davinci_serial_dev1.ops = &davinci_uart_ops;
     //davinci_serial_dev1.config = RT_SERIAL_CONFIG_DEFAULT;
-	davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200;
+    davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200;
     davinci_serial_dev1.config.bit_order = BIT_ORDER_LSB;
     davinci_serial_dev1.config.data_bits = DATA_BITS_8;
     davinci_serial_dev1.config.parity = PARITY_NONE;
     davinci_serial_dev1.config.stop_bits = STOP_BITS_1;
     davinci_serial_dev1.config.invert = NRZ_NORMAL;
-	davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&davinci_serial_dev1, "uart1",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           UART1);
-	davinci_uart1_init();
+    davinci_uart1_init();
 
-	return 0;
+    return 0;
 }
 
 INIT_BOARD_EXPORT(rt_hw_uart_init);

bsp/dm365/drivers/gpio.c

@@ -4,159 +4,159 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
 #include "gpio.h"
 
-#define GPIO0_BASE			(DAVINCI_GPIO_BASE + 0x10)
-#define GPIO1_BASE			(DAVINCI_GPIO_BASE + 0x38)
-#define GPIO2_BASE			(DAVINCI_GPIO_BASE + 0x60)
-#define GPIO3_BASE			(DAVINCI_GPIO_BASE + 0x88)
+#define GPIO0_BASE          (DAVINCI_GPIO_BASE + 0x10)
+#define GPIO1_BASE          (DAVINCI_GPIO_BASE + 0x38)
+#define GPIO2_BASE          (DAVINCI_GPIO_BASE + 0x60)
+#define GPIO3_BASE          (DAVINCI_GPIO_BASE + 0x88)
 
 
 static unsigned int dm365_gpio_base = (unsigned int)GPIO0_BASE;
 
-#define GPIO_OE			(dm365_gpio_base + 0x00)
-#define GPIO_DATAIN		(dm365_gpio_base + 0x10)
-#define GPIO_DATAOUT		(dm365_gpio_base + 0x04)
-#define GPIO_CLROUT		(dm365_gpio_base + 0x0C)
-#define GPIO_SETOUT		(dm365_gpio_base + 0x08)
+#define GPIO_OE         (dm365_gpio_base + 0x00)
+#define GPIO_DATAIN     (dm365_gpio_base + 0x10)
+#define GPIO_DATAOUT        (dm365_gpio_base + 0x04)
+#define GPIO_CLROUT     (dm365_gpio_base + 0x0C)
+#define GPIO_SETOUT     (dm365_gpio_base + 0x08)
 
-#define gpio_dirin(n)		*(volatile unsigned int *)((GPIO_OE)) |= 1<<(n)
-#define gpio_dirout(n)	*(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n))
-#define gpio_set(n)		*(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n)
-#define gpio_clr(n)		*(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n)
-#define gpio_get(n)		( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 )
+#define gpio_dirin(n)       *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n)
+#define gpio_dirout(n)  *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n))
+#define gpio_set(n)     *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n)
+#define gpio_clr(n)     *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n)
+#define gpio_get(n)     ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 )
 
  #define GPIO_GRP_MASK (5)
- 
+
 static int gpio_to_base(unsigned int gpio)
 {
-	unsigned int grp_idx;
-	int ret;
-
-	grp_idx = gpio >> GPIO_GRP_MASK;  
-
-	switch (grp_idx) {
-		case 0:
-			dm365_gpio_base = (unsigned int)GPIO0_BASE;
-			ret = 0;
-			break;
-		case 1:
-			dm365_gpio_base = (unsigned int)GPIO1_BASE;
-			ret = 0;
-			break;
-		case 2:
-			dm365_gpio_base = (unsigned int)GPIO2_BASE;
-			ret = 0;
-			break;    
-		case 3:
-			dm365_gpio_base = (unsigned int)GPIO3_BASE;
-			ret = 0;
-			break;   
-		default:
-			ret =-RT_EIO;
-			break;      
-	}
-	return ret;
+    unsigned int grp_idx;
+    int ret;
+
+    grp_idx = gpio >> GPIO_GRP_MASK;
+
+    switch (grp_idx) {
+        case 0:
+            dm365_gpio_base = (unsigned int)GPIO0_BASE;
+            ret = 0;
+            break;
+        case 1:
+            dm365_gpio_base = (unsigned int)GPIO1_BASE;
+            ret = 0;
+            break;
+        case 2:
+            dm365_gpio_base = (unsigned int)GPIO2_BASE;
+            ret = 0;
+            break;
+        case 3:
+            dm365_gpio_base = (unsigned int)GPIO3_BASE;
+            ret = 0;
+            break;
+        default:
+            ret =-RT_EIO;
+            break;
+    }
+    return ret;
 }
 
 
 int gpio_direction_input(unsigned int gpio)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
 
-	gpio_dirin(offset);
+    gpio_dirin(offset);
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 int gpio_direction_output(unsigned int gpio, int value)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
 
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
 
-	if (value) {
-		gpio_set(offset);
-	}
-	else {
-		gpio_clr(offset);
-	}
+    if (value) {
+        gpio_set(offset);
+    }
+    else {
+        gpio_clr(offset);
+    }
 
-	gpio_dirout(offset);
+    gpio_dirout(offset);
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 int  gpio_set_value(unsigned int gpio, int value)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
 
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
 
-	if (value) {
-		gpio_set(offset);
-	}
-	else {
-		gpio_clr(offset);
-	}
+    if (value) {
+        gpio_set(offset);
+    }
+    else {
+        gpio_clr(offset);
+    }
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 int gpio_get_value(unsigned int gpio)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
 
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
-	ret = gpio_get(offset);
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    ret = gpio_get(offset);
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 

bsp/dm365/drivers/gpio.h

@@ -4,34 +4,34 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
-#ifndef	__DM365_GPIO_H
-#define	__DM365_GPIO_H
+#ifndef __DM365_GPIO_H
+#define __DM365_GPIO_H
 #include <dm36x.h>
 
-#define	GPIO(X)		(X)		
+#define GPIO(X)     (X)
 
 
-#define get_io(r)			*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r)))
-#define set_io(r,v)		*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v)
-#define and_io(r,v)		*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v)
-#define or_io(r,v)			*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v)
+#define get_io(r)           *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r)))
+#define set_io(r,v)     *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v)
+#define and_io(r,v)     *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v)
+#define or_io(r,v)          *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v)
 
-#define v_get_io(r)			*((volatile u_int *)(r))
-#define v_set_io(r,v)		*((volatile u_int *)(r)) = (v)
-#define v_and_io(r,v)		*((volatile u_int *)(r)) &= (v)
-#define v_or_io(r,v)			*((volatile u_int *)(r)) |= (v)
+#define v_get_io(r)         *((volatile u_int *)(r))
+#define v_set_io(r,v)       *((volatile u_int *)(r)) = (v)
+#define v_and_io(r,v)       *((volatile u_int *)(r)) &= (v)
+#define v_or_io(r,v)            *((volatile u_int *)(r)) |= (v)
 
 enum gpio_intr_mode
 {
     LEVELDETECT_LOW = 0,
     LEVELDETECT_HIGH,
-    RISINGDETECT,  
+    RISINGDETECT,
     FALLINGDETECT,
-    EDGEDETECT	//both rising-edge and falling-edge detect
+    EDGEDETECT  //both rising-edge and falling-edge detect
 };
 
 enum gpio_intr_req
@@ -42,10 +42,10 @@ enum gpio_intr_req
 
 enum gpio_intr_num
 {
-	GPIOINT0A = 96,
-	GPIOINT0B,
-	GPIOINT1A,
-	GPIOINT1B, 
+    GPIOINT0A = 96,
+    GPIOINT0B,
+    GPIOINT1A,
+    GPIOINT1B,
 };
 
 enum pin_func_mod
@@ -56,4 +56,4 @@ enum pin_func_mod
     IIC_MOD=0x20
 };
 
-#endif				/* __TI814X_GPIO_H */
+#endif              /* __TI814X_GPIO_H */

bsp/dm365/drivers/i2c-davinci.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
@@ -13,61 +13,61 @@
 #include <dm36x.h>
 
 /* ----- global defines ----------------------------------------------- */
-#define BIT(nr)			(1UL << (nr))
+#define BIT(nr)         (1UL << (nr))
 
-#define DAVINCI_I2C_TIMEOUT	(1*RT_TICK_PER_SECOND)
-#define DAVINCI_I2C_MAX_TRIES	2
+#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND)
+#define DAVINCI_I2C_MAX_TRIES   2
 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
-				 DAVINCI_I2C_IMR_SCD | \
-				 DAVINCI_I2C_IMR_ARDY | \
-				 DAVINCI_I2C_IMR_NACK | \
-				 DAVINCI_I2C_IMR_AL)
-
-#define DAVINCI_I2C_OAR_REG	0x00
-#define DAVINCI_I2C_IMR_REG	0x04
-#define DAVINCI_I2C_STR_REG	0x08
-#define DAVINCI_I2C_CLKL_REG	0x0c
-#define DAVINCI_I2C_CLKH_REG	0x10
-#define DAVINCI_I2C_CNT_REG	0x14
-#define DAVINCI_I2C_DRR_REG	0x18
-#define DAVINCI_I2C_SAR_REG	0x1c
-#define DAVINCI_I2C_DXR_REG	0x20
-#define DAVINCI_I2C_MDR_REG	0x24
-#define DAVINCI_I2C_IVR_REG	0x28
-#define DAVINCI_I2C_EMDR_REG	0x2c
-#define DAVINCI_I2C_PSC_REG	0x30
-
-#define DAVINCI_I2C_IVR_AAS	0x07
-#define DAVINCI_I2C_IVR_SCD	0x06
-#define DAVINCI_I2C_IVR_XRDY	0x05
-#define DAVINCI_I2C_IVR_RDR	0x04
-#define DAVINCI_I2C_IVR_ARDY	0x03
-#define DAVINCI_I2C_IVR_NACK	0x02
-#define DAVINCI_I2C_IVR_AL	0x01
-
-#define DAVINCI_I2C_STR_BB	BIT(12)
-#define DAVINCI_I2C_STR_RSFULL	BIT(11)
-#define DAVINCI_I2C_STR_SCD	BIT(5)
-#define DAVINCI_I2C_STR_ARDY	BIT(2)
-#define DAVINCI_I2C_STR_NACK	BIT(1)
-#define DAVINCI_I2C_STR_AL	BIT(0)
-
-#define DAVINCI_I2C_MDR_NACK	BIT(15)
-#define DAVINCI_I2C_MDR_STT	BIT(13)
-#define DAVINCI_I2C_MDR_STP	BIT(11)
-#define DAVINCI_I2C_MDR_MST	BIT(10)
-#define DAVINCI_I2C_MDR_TRX	BIT(9)
-#define DAVINCI_I2C_MDR_XA	BIT(8)
-#define DAVINCI_I2C_MDR_RM	BIT(7)
-#define DAVINCI_I2C_MDR_IRS	BIT(5)
-
-#define DAVINCI_I2C_IMR_AAS	BIT(6)
-#define DAVINCI_I2C_IMR_SCD	BIT(5)
-#define DAVINCI_I2C_IMR_XRDY	BIT(4)
-#define DAVINCI_I2C_IMR_RRDY	BIT(3)
-#define DAVINCI_I2C_IMR_ARDY	BIT(2)
-#define DAVINCI_I2C_IMR_NACK	BIT(1)
-#define DAVINCI_I2C_IMR_AL	BIT(0)
+                 DAVINCI_I2C_IMR_SCD | \
+                 DAVINCI_I2C_IMR_ARDY | \
+                 DAVINCI_I2C_IMR_NACK | \
+                 DAVINCI_I2C_IMR_AL)
+
+#define DAVINCI_I2C_OAR_REG 0x00
+#define DAVINCI_I2C_IMR_REG 0x04
+#define DAVINCI_I2C_STR_REG 0x08
+#define DAVINCI_I2C_CLKL_REG    0x0c
+#define DAVINCI_I2C_CLKH_REG    0x10
+#define DAVINCI_I2C_CNT_REG 0x14
+#define DAVINCI_I2C_DRR_REG 0x18
+#define DAVINCI_I2C_SAR_REG 0x1c
+#define DAVINCI_I2C_DXR_REG 0x20
+#define DAVINCI_I2C_MDR_REG 0x24
+#define DAVINCI_I2C_IVR_REG 0x28
+#define DAVINCI_I2C_EMDR_REG    0x2c
+#define DAVINCI_I2C_PSC_REG 0x30
+
+#define DAVINCI_I2C_IVR_AAS 0x07
+#define DAVINCI_I2C_IVR_SCD 0x06
+#define DAVINCI_I2C_IVR_XRDY    0x05
+#define DAVINCI_I2C_IVR_RDR 0x04
+#define DAVINCI_I2C_IVR_ARDY    0x03
+#define DAVINCI_I2C_IVR_NACK    0x02
+#define DAVINCI_I2C_IVR_AL  0x01
+
+#define DAVINCI_I2C_STR_BB  BIT(12)
+#define DAVINCI_I2C_STR_RSFULL  BIT(11)
+#define DAVINCI_I2C_STR_SCD BIT(5)
+#define DAVINCI_I2C_STR_ARDY    BIT(2)
+#define DAVINCI_I2C_STR_NACK    BIT(1)
+#define DAVINCI_I2C_STR_AL  BIT(0)
+
+#define DAVINCI_I2C_MDR_NACK    BIT(15)
+#define DAVINCI_I2C_MDR_STT BIT(13)
+#define DAVINCI_I2C_MDR_STP BIT(11)
+#define DAVINCI_I2C_MDR_MST BIT(10)
+#define DAVINCI_I2C_MDR_TRX BIT(9)
+#define DAVINCI_I2C_MDR_XA  BIT(8)
+#define DAVINCI_I2C_MDR_RM  BIT(7)
+#define DAVINCI_I2C_MDR_IRS BIT(5)
+
+#define DAVINCI_I2C_IMR_AAS BIT(6)
+#define DAVINCI_I2C_IMR_SCD BIT(5)
+#define DAVINCI_I2C_IMR_XRDY    BIT(4)
+#define DAVINCI_I2C_IMR_RRDY    BIT(3)
+#define DAVINCI_I2C_IMR_ARDY    BIT(2)
+#define DAVINCI_I2C_IMR_NACK    BIT(1)
+#define DAVINCI_I2C_IMR_AL  BIT(0)
 
 #ifdef RT_EDMA_DEBUG
 #define i2c_dbg(fmt, ...)  rt_kprintf(fmt, ##__VA_ARGS__)
@@ -77,42 +77,42 @@
 
 
 struct davinci_i2c_dev {
-	void		*base;
-	struct rt_semaphore  completion;
-	struct clk  *clk;
-	int         cmd_err;
-	rt_uint8_t  *buf;
-	rt_uint32_t      buf_len;
-	int         irq;
-	int         stop;
-	rt_uint8_t  terminate;
-	rt_uint32_t bus_freq;
-	rt_uint32_t bus_delay;
-	struct rt_i2c_bus_device *bus;
+    void        *base;
+    struct rt_semaphore  completion;
+    struct clk  *clk;
+    int         cmd_err;
+    rt_uint8_t  *buf;
+    rt_uint32_t      buf_len;
+    int         irq;
+    int         stop;
+    rt_uint8_t  terminate;
+    rt_uint32_t bus_freq;
+    rt_uint32_t bus_delay;
+    struct rt_i2c_bus_device *bus;
 };
 
 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
-					 int reg, rt_uint16_t val)
+                     int reg, rt_uint16_t val)
 {
-	davinci_writew(val, i2c_dev->base + reg);
+    davinci_writew(val, i2c_dev->base + reg);
 }
 
 static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 {
-	return davinci_readw(i2c_dev->base + reg);
+    return davinci_readw(i2c_dev->base + reg);
 }
 
 static void udelay (rt_uint32_t us)
 {
-	rt_int32_t i;
-	for (; us > 0; us--)
-	{
-		i = 50000;
-		while(i > 0)
-		{
-			i--;
-		}
-	}
+    rt_int32_t i;
+    for (; us > 0; us--)
+    {
+        i = 50000;
+        while(i > 0)
+        {
+            i--;
+        }
+    }
 }
 
 
@@ -120,17 +120,17 @@ static void udelay (rt_uint32_t us)
 /* Generate a pulse on the i2c clock pin. */
 static void generic_i2c_clock_pulse(unsigned int scl_pin)
 {
-	rt_uint16_t i;
-
-	if (scl_pin) {
-		/* Send high and low on the SCL line */
-		for (i = 0; i < 9; i++) {
-			gpio_set_value(scl_pin, 0);
-			udelay(20);
-			gpio_set_value(scl_pin, 1);
-			udelay(20);
-		}
-	}
+    rt_uint16_t i;
+
+    if (scl_pin) {
+        /* Send high and low on the SCL line */
+        for (i = 0; i < 9; i++) {
+            gpio_set_value(scl_pin, 0);
+            udelay(20);
+            gpio_set_value(scl_pin, 1);
+            udelay(20);
+        }
+    }
 }
 #endif
 
@@ -139,78 +139,78 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin)
  */
 static void i2c_recover_bus(struct davinci_i2c_dev *dev)
 {
-	rt_uint32_t flag = 0;
-
-	i2c_dbg("initiating i2c bus recovery\n");
-	/* Send NACK to the slave */
-	flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	flag |=  DAVINCI_I2C_MDR_NACK;
-	/* write the data into mode register */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+    rt_uint32_t flag = 0;
+
+    i2c_dbg("initiating i2c bus recovery\n");
+    /* Send NACK to the slave */
+    flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    flag |=  DAVINCI_I2C_MDR_NACK;
+    /* write the data into mode register */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 #if 0
-	if (pdata)
-		generic_i2c_clock_pulse(pdata->scl_pin);
+    if (pdata)
+        generic_i2c_clock_pulse(pdata->scl_pin);
 #endif
-	/* Send STOP */
-	flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	flag |= DAVINCI_I2C_MDR_STP;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+    /* Send STOP */
+    flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    flag |= DAVINCI_I2C_MDR_STP;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 }
 
 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
-								int val)
+                                int val)
 {
-	rt_uint16_t w;
+    rt_uint16_t w;
 
-	w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
-	if (!val)	/* put I2C into reset */
-		w &= ~DAVINCI_I2C_MDR_IRS;
-	else		/* take I2C out of reset */
-		w |= DAVINCI_I2C_MDR_IRS;
+    w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
+    if (!val)   /* put I2C into reset */
+        w &= ~DAVINCI_I2C_MDR_IRS;
+    else        /* take I2C out of reset */
+        w |= DAVINCI_I2C_MDR_IRS;
 
-	davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
+    davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 }
 
 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 {
-	rt_uint16_t psc;
-	rt_uint32_t clk;
-	rt_uint32_t d;
-	rt_uint32_t clkh;
-	rt_uint32_t clkl;
-	rt_uint32_t input_clock = clk_get_rate(dev->clk);
-
-	/* NOTE: I2C Clock divider programming info
-	 * As per I2C specs the following formulas provide prescaler
-	 * and low/high divider values
-	 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
-	 *                       module clk
-	 *
-	 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
-	 *
-	 * Thus,
-	 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
-	 *
-	 * where if PSC == 0, d = 7,
-	 *       if PSC == 1, d = 6
-	 *       if PSC > 1 , d = 5
-	 */
-
-	/* get minimum of 7 MHz clock, but max of 12 MHz */
-	psc = (input_clock / 7000000) - 1;
-	if ((input_clock / (psc + 1)) > 12000000)
-		psc++;	/* better to run under spec than over */
-	d = (psc >= 2) ? 5 : 7 - psc;
-
-	clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1);
-	clkh = clk >> 1;
-	clkl = clk - clkh;
-
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
-
-	i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk);
+    rt_uint16_t psc;
+    rt_uint32_t clk;
+    rt_uint32_t d;
+    rt_uint32_t clkh;
+    rt_uint32_t clkl;
+    rt_uint32_t input_clock = clk_get_rate(dev->clk);
+
+    /* NOTE: I2C Clock divider programming info
+     * As per I2C specs the following formulas provide prescaler
+     * and low/high divider values
+     * input clk --> PSC Div -----------> ICCL/H Div --> output clock
+     *                       module clk
+     *
+     * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
+     *
+     * Thus,
+     * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
+     *
+     * where if PSC == 0, d = 7,
+     *       if PSC == 1, d = 6
+     *       if PSC > 1 , d = 5
+     */
+
+    /* get minimum of 7 MHz clock, but max of 12 MHz */
+    psc = (input_clock / 7000000) - 1;
+    if ((input_clock / (psc + 1)) > 12000000)
+        psc++;  /* better to run under spec than over */
+    d = (psc >= 2) ? 5 : 7 - psc;
+
+    clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1);
+    clkh = clk >> 1;
+    clkl = clk - clkh;
+
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
+
+    i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk);
 }
 
 /*
@@ -220,65 +220,65 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
  */
 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 {
-	/* put I2C into reset */
-	davinci_i2c_reset_ctrl(dev, 0);
+    /* put I2C into reset */
+    davinci_i2c_reset_ctrl(dev, 0);
 
-	/* compute clock dividers */
-	i2c_davinci_calc_clk_dividers(dev);
+    /* compute clock dividers */
+    i2c_davinci_calc_clk_dividers(dev);
 
-	/* Respond at reserved "SMBus Host" slave address" (and zero);
-	 * we seem to have no option to not respond...
-	 */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
+    /* Respond at reserved "SMBus Host" slave address" (and zero);
+     * we seem to have no option to not respond...
+     */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 
-	i2c_dbg("PSC  = %d\n",
-		davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
-	i2c_dbg("CLKL = %d\n",
-		davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
-	i2c_dbg("CLKH = %d\n",
-		davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
-	i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n",
-		dev->bus_freq, dev->bus_delay);
+    i2c_dbg("PSC  = %d\n",
+        davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
+    i2c_dbg("CLKL = %d\n",
+        davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
+    i2c_dbg("CLKH = %d\n",
+        davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
+    i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n",
+        dev->bus_freq, dev->bus_delay);
 
-	/* Take the I2C module out of reset: */
-	davinci_i2c_reset_ctrl(dev, 1);
+    /* Take the I2C module out of reset: */
+    davinci_i2c_reset_ctrl(dev, 1);
 
-	/* Enable interrupts */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
+    /* Enable interrupts */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 
-	return 0;
+    return 0;
 }
 
 /*
  * Waiting for bus not busy
  */
 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
-					 char allow_sleep)
+                     char allow_sleep)
 {
-	unsigned long timeout;
-	static rt_uint16_t to_cnt;
-	RT_ASSERT(dev != RT_NULL);
-	RT_ASSERT(dev->bus != RT_NULL);
-
-	timeout = rt_tick_get() + dev->bus->timeout;
-	while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
-	       & DAVINCI_I2C_STR_BB) {
-		if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
-			if (rt_tick_get() >= timeout) {
-				rt_kprintf("timeout waiting for bus ready\n");
-				to_cnt++;
-				return -RT_ETIMEOUT;
-			} else {
-				to_cnt = 0;
-				i2c_recover_bus(dev);
-				i2c_davinci_init(dev);
-			}
-		}
-		if (allow_sleep)
-			rt_thread_delay(2);
-	}
-
-	return 0;
+    unsigned long timeout;
+    static rt_uint16_t to_cnt;
+    RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev->bus != RT_NULL);
+
+    timeout = rt_tick_get() + dev->bus->timeout;
+    while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
+           & DAVINCI_I2C_STR_BB) {
+        if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
+            if (rt_tick_get() >= timeout) {
+                rt_kprintf("timeout waiting for bus ready\n");
+                to_cnt++;
+                return -RT_ETIMEOUT;
+            } else {
+                to_cnt = 0;
+                i2c_recover_bus(dev);
+                i2c_davinci_init(dev);
+            }
+        }
+        if (allow_sleep)
+            rt_thread_delay(2);
+    }
+
+    return 0;
 }
 
 /*
@@ -288,125 +288,125 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 static int
 i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop)
 {
-	struct davinci_i2c_dev *dev = bus->priv;
-	rt_uint32_t flag;
-	rt_uint16_t w;
-	int r;
-
-	/* Introduce a delay, required for some boards (e.g Davinci EVM) */
-	if (dev->bus_delay)
-		udelay(dev->bus_delay);
-
-	/* set the slave address */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
-
-	dev->buf = msg->buf;
-	dev->buf_len = msg->len;
-	dev->stop = stop;
-
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
-
-	//INIT_COMPLETION(dev->cmd_complete);
-	dev->cmd_err = 0;
-
-	/* Take I2C out of reset and configure it as master */
-	flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
-
-	/* if the slave address is ten bit address, enable XA bit */
-	if (msg->flags & RT_I2C_ADDR_10BIT)
-		flag |= DAVINCI_I2C_MDR_XA;
-	if (!(msg->flags & RT_I2C_RD))
-		flag |= DAVINCI_I2C_MDR_TRX;
-	if (msg->len == 0)
-		flag |= DAVINCI_I2C_MDR_RM;
-
-	/* Enable receive or transmit interrupts */
-	w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
-	if (msg->flags & RT_I2C_RD)
-		w |= DAVINCI_I2C_IMR_RRDY;
-	else
-		w |= DAVINCI_I2C_IMR_XRDY;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
-
-	dev->terminate = 0;
-
-	/*
-	 * Write mode register first as needed for correct behaviour
-	 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
-	 * occurring before we have loaded DXR
-	 */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
-
-	/*
-	 * First byte should be set here, not after interrupt,
-	 * because transmit-data-ready interrupt can come before
-	 * NACK-interrupt during sending of previous message and
-	 * ICDXR may have wrong data
-	 * It also saves us one interrupt, slightly faster
-	 */
-	if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len)
-	{
-		davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
-		dev->buf_len--;
-	}
-
-	/* Set STT to begin transmit now DXR is loaded */
-	flag |= DAVINCI_I2C_MDR_STT;
-	if (stop && msg->len != 0)
-		flag |= DAVINCI_I2C_MDR_STP;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
-
-	r = rt_sem_take(&dev->completion, dev->bus->timeout);
-	if (r == -RT_ETIMEOUT)
-	{
-		rt_kprintf("controller timed out\n");
-		i2c_recover_bus(dev);
-		i2c_davinci_init(dev);
-		dev->buf_len = 0;
-		return -RT_ETIMEOUT;
-	}
-	if (dev->buf_len)
-	{
-		/* This should be 0 if all bytes were transferred
-		 * or dev->cmd_err denotes an error.
-		 * A signal may have aborted the transfer.
-		 */
-		if (r == RT_EOK)
-		{
-			rt_kprintf("abnormal termination buf_len=%i\n",
-				dev->buf_len);
-			r = -RT_EIO;
-		}
-		dev->terminate = 1;
-		dev->buf_len = 0;
-	}
-	if (r < 0)
-		return r;
-
-	/* no error */
-	if (!dev->cmd_err)
-		return msg->len;
-
-	/* We have an error */
-	if (dev->cmd_err & DAVINCI_I2C_STR_AL)
-	{
-		i2c_davinci_init(dev);
-		return -RT_EIO;
-	}
-
-	if (dev->cmd_err & DAVINCI_I2C_STR_NACK)
-	{
-		if (msg->flags & RT_I2C_IGNORE_NACK)
-			return msg->len;
-		if (stop)
-		{
-			w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-			w |= DAVINCI_I2C_MDR_STP;
-			davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
-		}
-		return -RT_EIO;
-	}
-	return -RT_EIO;
+    struct davinci_i2c_dev *dev = bus->priv;
+    rt_uint32_t flag;
+    rt_uint16_t w;
+    int r;
+
+    /* Introduce a delay, required for some boards (e.g Davinci EVM) */
+    if (dev->bus_delay)
+        udelay(dev->bus_delay);
+
+    /* set the slave address */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
+
+    dev->buf = msg->buf;
+    dev->buf_len = msg->len;
+    dev->stop = stop;
+
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
+
+    //INIT_COMPLETION(dev->cmd_complete);
+    dev->cmd_err = 0;
+
+    /* Take I2C out of reset and configure it as master */
+    flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
+
+    /* if the slave address is ten bit address, enable XA bit */
+    if (msg->flags & RT_I2C_ADDR_10BIT)
+        flag |= DAVINCI_I2C_MDR_XA;
+    if (!(msg->flags & RT_I2C_RD))
+        flag |= DAVINCI_I2C_MDR_TRX;
+    if (msg->len == 0)
+        flag |= DAVINCI_I2C_MDR_RM;
+
+    /* Enable receive or transmit interrupts */
+    w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
+    if (msg->flags & RT_I2C_RD)
+        w |= DAVINCI_I2C_IMR_RRDY;
+    else
+        w |= DAVINCI_I2C_IMR_XRDY;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
+
+    dev->terminate = 0;
+
+    /*
+     * Write mode register first as needed for correct behaviour
+     * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
+     * occurring before we have loaded DXR
+     */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+
+    /*
+     * First byte should be set here, not after interrupt,
+     * because transmit-data-ready interrupt can come before
+     * NACK-interrupt during sending of previous message and
+     * ICDXR may have wrong data
+     * It also saves us one interrupt, slightly faster
+     */
+    if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len)
+    {
+        davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
+        dev->buf_len--;
+    }
+
+    /* Set STT to begin transmit now DXR is loaded */
+    flag |= DAVINCI_I2C_MDR_STT;
+    if (stop && msg->len != 0)
+        flag |= DAVINCI_I2C_MDR_STP;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+
+    r = rt_sem_take(&dev->completion, dev->bus->timeout);
+    if (r == -RT_ETIMEOUT)
+    {
+        rt_kprintf("controller timed out\n");
+        i2c_recover_bus(dev);
+        i2c_davinci_init(dev);
+        dev->buf_len = 0;
+        return -RT_ETIMEOUT;
+    }
+    if (dev->buf_len)
+    {
+        /* This should be 0 if all bytes were transferred
+         * or dev->cmd_err denotes an error.
+         * A signal may have aborted the transfer.
+         */
+        if (r == RT_EOK)
+        {
+            rt_kprintf("abnormal termination buf_len=%i\n",
+                dev->buf_len);
+            r = -RT_EIO;
+        }
+        dev->terminate = 1;
+        dev->buf_len = 0;
+    }
+    if (r < 0)
+        return r;
+
+    /* no error */
+    if (!dev->cmd_err)
+        return msg->len;
+
+    /* We have an error */
+    if (dev->cmd_err & DAVINCI_I2C_STR_AL)
+    {
+        i2c_davinci_init(dev);
+        return -RT_EIO;
+    }
+
+    if (dev->cmd_err & DAVINCI_I2C_STR_NACK)
+    {
+        if (msg->flags & RT_I2C_IGNORE_NACK)
+            return msg->len;
+        if (stop)
+        {
+            w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+            w |= DAVINCI_I2C_MDR_STP;
+            davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
+        }
+        return -RT_EIO;
+    }
+    return -RT_EIO;
 }
 
 /*
@@ -415,52 +415,52 @@ i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int
 static int
 i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num)
 {
-	struct davinci_i2c_dev *dev = bus->priv;
-	int i;
-	int ret;
-
-	i2c_dbg("%s: msgs: %d\n", __func__, num);
-
-	ret = i2c_davinci_wait_bus_not_busy(dev, 1);
-	if (ret < 0)
-	{
-		i2c_dbg("timeout waiting for bus ready\n");
-		return ret;
-	}
-
-	for (i = 0; i < num; i++)
-	{
-		ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1)));
-		i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num,
-			ret);
-		if (ret < 0)
-			return ret;
-	}
-
-
-	return num;
+    struct davinci_i2c_dev *dev = bus->priv;
+    int i;
+    int ret;
+
+    i2c_dbg("%s: msgs: %d\n", __func__, num);
+
+    ret = i2c_davinci_wait_bus_not_busy(dev, 1);
+    if (ret < 0)
+    {
+        i2c_dbg("timeout waiting for bus ready\n");
+        return ret;
+    }
+
+    for (i = 0; i < num; i++)
+    {
+        ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1)));
+        i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num,
+            ret);
+        if (ret < 0)
+            return ret;
+    }
+
+
+    return num;
 }
 
 
 static void terminate_read(struct davinci_i2c_dev *dev)
 {
-	rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	w |= DAVINCI_I2C_MDR_NACK;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
-
-	/* Throw away data */
-	davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
-	if (!dev->terminate)
-		rt_kprintf("RDR IRQ while no data requested\n");
+    rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    w |= DAVINCI_I2C_MDR_NACK;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
+
+    /* Throw away data */
+    davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
+    if (!dev->terminate)
+        rt_kprintf("RDR IRQ while no data requested\n");
 }
 static void terminate_write(struct davinci_i2c_dev *dev)
 {
-	rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
+    rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 
-	if (!dev->terminate)
-		i2c_dbg("TDR IRQ while no data to send\n");
+    if (!dev->terminate)
+        i2c_dbg("TDR IRQ while no data to send\n");
 }
 
 /*
@@ -469,173 +469,173 @@ static void terminate_write(struct davinci_i2c_dev *dev)
  */
 static void i2c_davinci_isr(int irq, void *param)
 {
-	struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param;
-	rt_uint32_t stat;
-	int count = 0;
-	rt_uint16_t w;
-
-	while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
-		i2c_dbg("%s: stat=0x%x\n", __func__, stat);
-		if (count++ == 100) {
-			rt_kprintf("Too much work in one IRQ\n");
-			break;
-		}
-
-		switch (stat) {
-		case DAVINCI_I2C_IVR_AL:
-			/* Arbitration lost, must retry */
-			dev->cmd_err |= DAVINCI_I2C_STR_AL;
-			dev->buf_len = 0;
-			rt_sem_release(&dev->completion);
-			break;
-
-		case DAVINCI_I2C_IVR_NACK:
-			dev->cmd_err |= DAVINCI_I2C_STR_NACK;
-			dev->buf_len = 0;
-			rt_sem_release(&dev->completion);
-			break;
-
-		case DAVINCI_I2C_IVR_ARDY:
-			davinci_i2c_write_reg(dev,
-				DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
-			if (((dev->buf_len == 0) && (dev->stop != 0)) ||
-			    (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
-				w = davinci_i2c_read_reg(dev,
-							 DAVINCI_I2C_MDR_REG);
-				w |= DAVINCI_I2C_MDR_STP;
-				davinci_i2c_write_reg(dev,
-						      DAVINCI_I2C_MDR_REG, w);
-			}
-			rt_sem_release(&dev->completion);
-			break;
-
-		case DAVINCI_I2C_IVR_RDR:
-			if (dev->buf_len) {
-				*dev->buf++ =
-				    davinci_i2c_read_reg(dev,
-							 DAVINCI_I2C_DRR_REG);
-				dev->buf_len--;
-				if (dev->buf_len)
-					continue;
-
-				davinci_i2c_write_reg(dev,
-					DAVINCI_I2C_STR_REG,
-					DAVINCI_I2C_IMR_RRDY);
-			} else {
-				/* signal can terminate transfer */
-				terminate_read(dev);
-			}
-			break;
-
-		case DAVINCI_I2C_IVR_XRDY:
-			if (dev->buf_len) {
-				davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
-						      *dev->buf++);
-				dev->buf_len--;
-				if (dev->buf_len)
-					continue;
-
-				w = davinci_i2c_read_reg(dev,
-							 DAVINCI_I2C_IMR_REG);
-				w &= ~DAVINCI_I2C_IMR_XRDY;
-				davinci_i2c_write_reg(dev,
-						      DAVINCI_I2C_IMR_REG,
-						      w);
-			} else {
-				/* signal can terminate transfer */
-				terminate_write(dev);
-			}
-			break;
-
-		case DAVINCI_I2C_IVR_SCD:
-			davinci_i2c_write_reg(dev,
-				DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
-			rt_sem_release(&dev->completion);
-			break;
-
-		case DAVINCI_I2C_IVR_AAS:
-			i2c_dbg("Address as slave interrupt\n");
-			break;
-
-		default:
-			i2c_dbg("Unrecognized irq stat %d\n", stat);
-			break;
-		}
-	}
+    struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param;
+    rt_uint32_t stat;
+    int count = 0;
+    rt_uint16_t w;
+
+    while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
+        i2c_dbg("%s: stat=0x%x\n", __func__, stat);
+        if (count++ == 100) {
+            rt_kprintf("Too much work in one IRQ\n");
+            break;
+        }
+
+        switch (stat) {
+        case DAVINCI_I2C_IVR_AL:
+            /* Arbitration lost, must retry */
+            dev->cmd_err |= DAVINCI_I2C_STR_AL;
+            dev->buf_len = 0;
+            rt_sem_release(&dev->completion);
+            break;
+
+        case DAVINCI_I2C_IVR_NACK:
+            dev->cmd_err |= DAVINCI_I2C_STR_NACK;
+            dev->buf_len = 0;
+            rt_sem_release(&dev->completion);
+            break;
+
+        case DAVINCI_I2C_IVR_ARDY:
+            davinci_i2c_write_reg(dev,
+                DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
+            if (((dev->buf_len == 0) && (dev->stop != 0)) ||
+                (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
+                w = davinci_i2c_read_reg(dev,
+                             DAVINCI_I2C_MDR_REG);
+                w |= DAVINCI_I2C_MDR_STP;
+                davinci_i2c_write_reg(dev,
+                              DAVINCI_I2C_MDR_REG, w);
+            }
+            rt_sem_release(&dev->completion);
+            break;
+
+        case DAVINCI_I2C_IVR_RDR:
+            if (dev->buf_len) {
+                *dev->buf++ =
+                    davinci_i2c_read_reg(dev,
+                             DAVINCI_I2C_DRR_REG);
+                dev->buf_len--;
+                if (dev->buf_len)
+                    continue;
+
+                davinci_i2c_write_reg(dev,
+                    DAVINCI_I2C_STR_REG,
+                    DAVINCI_I2C_IMR_RRDY);
+            } else {
+                /* signal can terminate transfer */
+                terminate_read(dev);
+            }
+            break;
+
+        case DAVINCI_I2C_IVR_XRDY:
+            if (dev->buf_len) {
+                davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
+                              *dev->buf++);
+                dev->buf_len--;
+                if (dev->buf_len)
+                    continue;
+
+                w = davinci_i2c_read_reg(dev,
+                             DAVINCI_I2C_IMR_REG);
+                w &= ~DAVINCI_I2C_IMR_XRDY;
+                davinci_i2c_write_reg(dev,
+                              DAVINCI_I2C_IMR_REG,
+                              w);
+            } else {
+                /* signal can terminate transfer */
+                terminate_write(dev);
+            }
+            break;
+
+        case DAVINCI_I2C_IVR_SCD:
+            davinci_i2c_write_reg(dev,
+                DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
+            rt_sem_release(&dev->completion);
+            break;
+
+        case DAVINCI_I2C_IVR_AAS:
+            i2c_dbg("Address as slave interrupt\n");
+            break;
+
+        default:
+            i2c_dbg("Unrecognized irq stat %d\n", stat);
+            break;
+        }
+    }
 
 }
 
 
 
 static struct rt_i2c_bus_device_ops bus_ops = {
-	.master_xfer	= i2c_davinci_xfer,
+    .master_xfer    = i2c_davinci_xfer,
 };
 
 int davinci_i2c_init(char *bus_name)
 {
-	struct rt_i2c_bus_device *bus;
-	struct davinci_i2c_dev *dev;
-	int r;
+    struct rt_i2c_bus_device *bus;
+    struct davinci_i2c_dev *dev;
+    int r;
 
-	bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
-	if (bus == RT_NULL)
-	{
-		rt_kprintf("rt_malloc failed\n");
-		return -RT_ENOMEM;
-	}
-	
-	rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+    bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+    if (bus == RT_NULL)
+    {
+        rt_kprintf("rt_malloc failed\n");
+        return -RT_ENOMEM;
+    }
 
-	bus->ops = &bus_ops;
-	bus->timeout = DAVINCI_I2C_TIMEOUT;
+    rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
 
-	dev = rt_malloc(sizeof(struct davinci_i2c_dev));
-	if (!dev) 
-	{
-		r = -RT_ENOMEM;
-		goto err;
-	}
+    bus->ops = &bus_ops;
+    bus->timeout = DAVINCI_I2C_TIMEOUT;
 
-	rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev));
+    dev = rt_malloc(sizeof(struct davinci_i2c_dev));
+    if (!dev)
+    {
+        r = -RT_ENOMEM;
+        goto err;
+    }
 
-	rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO);
+    rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev));
 
-	dev->irq = IRQ_I2C;
+    rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO);
 
-	dev->clk = clk_get("I2CCLK");
-	if (dev->clk == RT_NULL) {
-		r = -RT_ERROR;
-		goto err1;
-	}
+    dev->irq = IRQ_I2C;
 
-	psc_change_state(DAVINCI_DM365_LPSC_I2C, 3);
+    dev->clk = clk_get("I2CCLK");
+    if (dev->clk == RT_NULL) {
+        r = -RT_ERROR;
+        goto err1;
+    }
 
-	dev->base = DAVINCI_I2C_BASE;
-	dev->bus_freq = 100;
-	dev->bus_delay = 0;
-	dev->bus = bus;
+    psc_change_state(DAVINCI_DM365_LPSC_I2C, 3);
 
-	bus->priv = dev;
+    dev->base = DAVINCI_I2C_BASE;
+    dev->bus_freq = 100;
+    dev->bus_delay = 0;
+    dev->bus = bus;
 
-	i2c_davinci_init(dev);
+    bus->priv = dev;
 
-	rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C");
-	rt_hw_interrupt_umask(dev->irq);
+    i2c_davinci_init(dev);
 
-	return rt_i2c_bus_device_register(bus, bus_name);
+    rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C");
+    rt_hw_interrupt_umask(dev->irq);
+
+    return rt_i2c_bus_device_register(bus, bus_name);
 
 err1:
-	rt_free(dev);
+    rt_free(dev);
 
 err:
-	rt_free(bus);
+    rt_free(bus);
 
-	return r;
+    return r;
 }
 
 int rt_hw_iic_init(void)
 {
-	davinci_i2c_init("I2C1");
+    davinci_i2c_init("I2C1");
 }
 
 INIT_DEVICE_EXPORT(rt_hw_iic_init);

bsp/dm365/drivers/mii.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-03-18     weety		first version
+ * Date           Author        Notes
+ * 2011-03-18     weety     first version
  */
 
 
@@ -23,7 +23,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS     0x0f    /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -38,7 +38,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000      0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -57,7 +57,7 @@
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_ESTATEN        0x0100  /* Extended Status in R15 */
 #define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
 #define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
@@ -86,7 +86,7 @@
 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 
 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
+            ADVERTISE_CSMA)
 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 
@@ -108,8 +108,8 @@
 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 #define LPA_NPAGE               0x8000  /* Next page bit               */
 
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
+#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
 /* Expansion register for auto-negotiation. */
 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
@@ -119,8 +119,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -138,8 +138,8 @@
 #define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
 
 /* Flow control flags */
-#define FLOW_CTRL_TX		0x01
-#define FLOW_CTRL_RX		0x02
+#define FLOW_CTRL_TX        0x01
+#define FLOW_CTRL_RX        0x02
 
 /**
  * mii_nway_result
@@ -174,11 +174,11 @@ rt_inline unsigned int mii_nway_result (unsigned int negotiated)
 }
 
 /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
-#define SPEED_10		10
-#define SPEED_100		100
-#define SPEED_1000		1000
-#define SPEED_2500		2500
-#define SPEED_10000		10000
+#define SPEED_10        10
+#define SPEED_100       100
+#define SPEED_1000      1000
+#define SPEED_2500      2500
+#define SPEED_10000     10000
 
 
 #endif /* __MII_H__ */

bsp/dm365/drivers/mmcsd.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #ifndef __DAVINCI_MMC_H__
@@ -30,18 +30,18 @@
 #define MMCCLK_CLKRT_MASK     (0xFF << 0)
 
 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
-#define MMCST0_DATDNE         (1 << 0)	/* data done */
-#define MMCST0_BSYDNE         (1 << 1)	/* busy done */
-#define MMCST0_RSPDNE         (1 << 2)	/* command done */
-#define MMCST0_TOUTRD         (1 << 3)	/* data read timeout */
-#define MMCST0_TOUTRS         (1 << 4)	/* command response timeout */
-#define MMCST0_CRCWR          (1 << 5)	/* data write CRC error */
-#define MMCST0_CRCRD          (1 << 6)	/* data read CRC error */
-#define MMCST0_CRCRS          (1 << 7)	/* command response CRC error */
-#define MMCST0_DXRDY          (1 << 9)	/* data transmit ready (fifo empty) */
-#define MMCST0_DRRDY          (1 << 10)	/* data receive ready (data in fifo)*/
-#define MMCST0_DATED          (1 << 11)	/* DAT3 edge detect */
-#define MMCST0_TRNDNE         (1 << 12)	/* transfer done */
+#define MMCST0_DATDNE         (1 << 0)  /* data done */
+#define MMCST0_BSYDNE         (1 << 1)  /* busy done */
+#define MMCST0_RSPDNE         (1 << 2)  /* command done */
+#define MMCST0_TOUTRD         (1 << 3)  /* data read timeout */
+#define MMCST0_TOUTRS         (1 << 4)  /* command response timeout */
+#define MMCST0_CRCWR          (1 << 5)  /* data write CRC error */
+#define MMCST0_CRCRD          (1 << 6)  /* data read CRC error */
+#define MMCST0_CRCRS          (1 << 7)  /* command response CRC error */
+#define MMCST0_DXRDY          (1 << 9)  /* data transmit ready (fifo empty) */
+#define MMCST0_DRRDY          (1 << 10) /* data receive ready (data in fifo)*/
+#define MMCST0_DATED          (1 << 11) /* DAT3 edge detect */
+#define MMCST0_TRNDNE         (1 << 12) /* transfer done */
 
 /* DAVINCI_MMCST1 definitions */
 #define MMCST1_BUSY           (1 << 0)
@@ -86,44 +86,44 @@
 #define SDIOIST_RWS           (1 << 1)
 
 /* MMCSD Init clock in Hz in opendrain mode */
-#define MMCSD_INIT_CLOCK		200000
+#define MMCSD_INIT_CLOCK        200000
 
-#define MAX_CCNT	((1 << 16) - 1)
+#define MAX_CCNT    ((1 << 16) - 1)
 
-#define MAX_NR_SG	16
+#define MAX_NR_SG   16
 
-#define MMC_DATA_WRITE	(1 << 8)
-#define MMC_DATA_READ	(1 << 9)
-#define MMC_DATA_STREAM	(1 << 10)
+#define MMC_DATA_WRITE  (1 << 8)
+#define MMC_DATA_READ   (1 << 9)
+#define MMC_DATA_STREAM (1 << 10)
 
 typedef struct {
-	volatile rt_uint32_t MMCCTL;
-	volatile rt_uint32_t MMCCLK;
-	volatile rt_uint32_t MMCST0;
-	volatile rt_uint32_t MMCST1;
-	volatile rt_uint32_t MMCIM;
-	volatile rt_uint32_t MMCTOR;
-	volatile rt_uint32_t MMCTOD;
-	volatile rt_uint32_t MMCBLEN;
-	volatile rt_uint32_t MMCNBLK;
-	volatile rt_uint32_t MMCNBLC;
-	volatile rt_uint32_t MMCDRR;
-	volatile rt_uint32_t MMCDXR;
-	volatile rt_uint32_t MMCCMD;
-	volatile rt_uint32_t MMCARGHL;
-	volatile rt_uint32_t MMCRSP01;
-	volatile rt_uint32_t MMCRSP23;
-	volatile rt_uint32_t MMCRSP45;
-	volatile rt_uint32_t MMCRSP67;
-	volatile rt_uint32_t MMCDRSP;
-	volatile rt_uint32_t reserved0;
-	volatile rt_uint32_t MMCCIDX;
-	volatile rt_uint32_t reserved1[4];
-	volatile rt_uint32_t SDIOCTL;
-	volatile rt_uint32_t SDIOST0;
-	volatile rt_uint32_t SDIOIEN;
-	volatile rt_uint32_t SDIOIST;
-	volatile rt_uint32_t MMCFIFOCTL;
+    volatile rt_uint32_t MMCCTL;
+    volatile rt_uint32_t MMCCLK;
+    volatile rt_uint32_t MMCST0;
+    volatile rt_uint32_t MMCST1;
+    volatile rt_uint32_t MMCIM;
+    volatile rt_uint32_t MMCTOR;
+    volatile rt_uint32_t MMCTOD;
+    volatile rt_uint32_t MMCBLEN;
+    volatile rt_uint32_t MMCNBLK;
+    volatile rt_uint32_t MMCNBLC;
+    volatile rt_uint32_t MMCDRR;
+    volatile rt_uint32_t MMCDXR;
+    volatile rt_uint32_t MMCCMD;
+    volatile rt_uint32_t MMCARGHL;
+    volatile rt_uint32_t MMCRSP01;
+    volatile rt_uint32_t MMCRSP23;
+    volatile rt_uint32_t MMCRSP45;
+    volatile rt_uint32_t MMCRSP67;
+    volatile rt_uint32_t MMCDRSP;
+    volatile rt_uint32_t reserved0;
+    volatile rt_uint32_t MMCCIDX;
+    volatile rt_uint32_t reserved1[4];
+    volatile rt_uint32_t SDIOCTL;
+    volatile rt_uint32_t SDIOST0;
+    volatile rt_uint32_t SDIOIEN;
+    volatile rt_uint32_t SDIOIST;
+    volatile rt_uint32_t MMCFIFOCTL;
 }mmcsd_regs_t;
 
 extern int rt_hw_mmcsd_init(void);

bsp/dm365/drivers/spi-davinci.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #ifndef __DAVINCI_SPI_H
@@ -16,46 +16,46 @@ typedef unsigned short u16;
 typedef unsigned char  u8;
 typedef unsigned int   bool;
 
-#define SPI_INTERN_CS	0xFF
+#define SPI_INTERN_CS   0xFF
 
 enum {
-	SPI_VERSION_1, /* For DM355/DM365/DM6467 */
-	SPI_VERSION_2, /* For DA8xx */
+    SPI_VERSION_1, /* For DM355/DM365/DM6467 */
+    SPI_VERSION_2, /* For DA8xx */
 };
 
 /**
  * davinci_spi_config - Per-chip-select configuration for SPI slave devices
  *
- * @wdelay:	amount of delay between transmissions. Measured in number of
- *		SPI module clocks.
- * @odd_parity:	polarity of parity flag at the end of transmit data stream.
- *		0 - odd parity, 1 - even parity.
+ * @wdelay: amount of delay between transmissions. Measured in number of
+ *      SPI module clocks.
+ * @odd_parity: polarity of parity flag at the end of transmit data stream.
+ *      0 - odd parity, 1 - even parity.
  * @parity_enable: enable transmission of parity at end of each transmit
- *		data stream.
- * @io_type:	type of IO transfer. Choose between polled, interrupt and DMA.
+ *      data stream.
+ * @io_type:    type of IO transfer. Choose between polled, interrupt and DMA.
  * @timer_disable: disable chip-select timers (setup and hold)
- * @c2tdelay:	chip-select setup time. Measured in number of SPI module clocks.
- * @t2cdelay:	chip-select hold time. Measured in number of SPI module clocks.
- * @t2edelay:	transmit data finished to SPI ENAn pin inactive time. Measured
- *		in number of SPI clocks.
- * @c2edelay:	chip-select active to SPI ENAn signal active time. Measured in
- *		number of SPI clocks.
+ * @c2tdelay:   chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay:   chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay:   transmit data finished to SPI ENAn pin inactive time. Measured
+ *      in number of SPI clocks.
+ * @c2edelay:   chip-select active to SPI ENAn signal active time. Measured in
+ *      number of SPI clocks.
  */
 struct davinci_spi_config {
-	u8	wdelay;
-	u8	odd_parity;
-	u8	parity_enable;
-#define SPI_IO_TYPE_INTR	0
-#define SPI_IO_TYPE_POLL	1
-#define SPI_IO_TYPE_DMA		2
-	u8	io_type;
-	u8	timer_disable;
-	u8	c2tdelay;
-	u8	t2cdelay;
-	u8	t2edelay;
-	u8	c2edelay;
+    u8  wdelay;
+    u8  odd_parity;
+    u8  parity_enable;
+#define SPI_IO_TYPE_INTR    0
+#define SPI_IO_TYPE_POLL    1
+#define SPI_IO_TYPE_DMA     2
+    u8  io_type;
+    u8  timer_disable;
+    u8  c2tdelay;
+    u8  t2cdelay;
+    u8  t2edelay;
+    u8  c2edelay;
 };
 
 extern int rt_hw_spi_init(void);
 
-#endif	/* __DAVINCI_SPI_H */
+#endif  /* __DAVINCI_SPI_H */

bsp/dm365/platform/dm365.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #include <edma.h>
@@ -26,285 +26,285 @@ static rt_uint32_t vpssrate, vencrate_sd, vencrate_hd;
 /* Four Transfer Controllers on DM365 */
 static const rt_int8_t
 dm365_queue_tc_mapping[][2] = {
-	/* {event queue no, TC no} */
-	{0, 0},
-	{1, 1},
-	{2, 2},
-	{3, 3},
-	{-1, -1},
+    /* {event queue no, TC no} */
+    {0, 0},
+    {1, 1},
+    {2, 2},
+    {3, 3},
+    {-1, -1},
 };
 
 static const rt_int8_t
 dm365_queue_priority_mapping[][2] = {
-	/* {event queue no, Priority} */
-	{0, 7},
-	{1, 7},
-	{2, 7},
-	{3, 0},
-	{-1, -1},
+    /* {event queue no, Priority} */
+    {0, 7},
+    {1, 7},
+    {2, 7},
+    {3, 0},
+    {-1, -1},
 };
 
 static struct edma_soc_info edma_cc0_info = {
-	.n_channel		= 64,
-	.n_region		= 4,
-	.n_slot			= 256,
-	.n_tc			= 4,
-	.n_cc			= 1,
-	.queue_tc_mapping	= dm365_queue_tc_mapping,
-	.queue_priority_mapping	= dm365_queue_priority_mapping,
-	.default_queue		= EVENTQ_3,
+    .n_channel      = 64,
+    .n_region       = 4,
+    .n_slot         = 256,
+    .n_tc           = 4,
+    .n_cc           = 1,
+    .queue_tc_mapping   = dm365_queue_tc_mapping,
+    .queue_priority_mapping = dm365_queue_priority_mapping,
+    .default_queue      = EVENTQ_3,
 };
 
 static struct edma_soc_info *dm365_edma_info[EDMA_MAX_CC] = {
-	&edma_cc0_info,
+    &edma_cc0_info,
 };
 
 static rt_list_t clocks;
 
 struct clk {
-	char name[32];
-	rt_uint32_t *rate_hz;
-	struct clk *parent;
-	rt_list_t  node;
+    char name[32];
+    rt_uint32_t *rate_hz;
+    struct clk *parent;
+    rt_list_t  node;
 };
 
 static struct clk davinci_dm365_clks[] = {
-	{
-		.name = "ARMCLK",
-		.rate_hz = &armrate,
-	},
-	{
-		.name = "UART0",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "UART1",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "HPI",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "EMACCLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "I2CCLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "McBSPCLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "MMCSDCLK0",
-		.rate_hz = &mmcsdrate,
-	},
-	{
-		.name = "MMCSDCLK1",
-		.rate_hz = &mmcsdrate,
-	},
-	{
-		.name = "SPICLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "gpio",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "AEMIFCLK",
-		.rate_hz = &commonrate,
-	},
-	{
-		.name = "PWM0_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "PWM1_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "PWM2_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "PWM3_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "USBCLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "VOICECODEC_CLK",
-		.rate_hz = &voicerate,
-	},
-	{
-		.name = "RTC_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "KEYSCAN_CLK",
-		.rate_hz = &fixedrate,
-	},
-	{
-		.name = "ADCIF_CLK",
-		.rate_hz = &fixedrate,
-	},
+    {
+        .name = "ARMCLK",
+        .rate_hz = &armrate,
+    },
+    {
+        .name = "UART0",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "UART1",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "HPI",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "EMACCLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "I2CCLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "McBSPCLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "MMCSDCLK0",
+        .rate_hz = &mmcsdrate,
+    },
+    {
+        .name = "MMCSDCLK1",
+        .rate_hz = &mmcsdrate,
+    },
+    {
+        .name = "SPICLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "gpio",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "AEMIFCLK",
+        .rate_hz = &commonrate,
+    },
+    {
+        .name = "PWM0_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "PWM1_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "PWM2_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "PWM3_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "USBCLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "VOICECODEC_CLK",
+        .rate_hz = &voicerate,
+    },
+    {
+        .name = "RTC_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "KEYSCAN_CLK",
+        .rate_hz = &fixedrate,
+    },
+    {
+        .name = "ADCIF_CLK",
+        .rate_hz = &fixedrate,
+    },
 };
 
 /* clocks cannot be de-registered no refcounting necessary */
 struct clk *clk_get(const char *id)
 {
-	struct clk *clk;
-	rt_list_t *list;
-	
-	for (list = (&clocks)->next; list != &clocks; list = list->next)
-	{
-		clk = (struct clk *)rt_list_entry(list, struct clk, node);
-		if (rt_strcmp(id, clk->name) == 0)
-			return clk;
-	}
-
-	return RT_NULL;
+    struct clk *clk;
+    rt_list_t *list;
+
+    for (list = (&clocks)->next; list != &clocks; list = list->next)
+    {
+        clk = (struct clk *)rt_list_entry(list, struct clk, node);
+        if (rt_strcmp(id, clk->name) == 0)
+            return clk;
+    }
+
+    return RT_NULL;
 }
 
 rt_uint32_t clk_get_rate(struct clk *clk)
 {
-	rt_uint32_t	flags;
-	rt_uint32_t	*rate;
-
-	for (;;) {
-		rate = clk->rate_hz;
-		if (rate || !clk->parent)
-			break;
-		clk = clk->parent;
-	}
-	return *rate;
+    rt_uint32_t flags;
+    rt_uint32_t *rate;
+
+    for (;;) {
+        rate = clk->rate_hz;
+        if (rate || !clk->parent)
+            break;
+        clk = clk->parent;
+    }
+    return *rate;
 }
 
 void clk_register(struct clk *clk)
 {
-	rt_list_insert_after(&clocks, &clk->node);
+    rt_list_insert_after(&clocks, &clk->node);
 }
 
 int davinci_register_clks(struct clk *clk_list, int num_clks)
 {
-	struct clk *clkp;
-	int i;
+    struct clk *clkp;
+    int i;
 
-	for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++)
-	{
-		//rt_kprintf("1:%s\n", clkp->name);
-		clk_register(clkp);
-		//rt_kprintf("2:%s\n", clkp->name);
-	}
+    for (i = 0, clkp = clk_list; i < num_clks; i++, clkp++)
+    {
+        //rt_kprintf("1:%s\n", clkp->name);
+        clk_register(clkp);
+        //rt_kprintf("2:%s\n", clkp->name);
+    }
 
-	return 0;
+    return 0;
 }
 
 /* PLL/Reset register offsets */
-#define PLLM		0x110
-#define PREDIV		0x114
-#define PLLDIV2		0x11C
-#define POSTDIV		0x128
-#define PLLDIV4		0x160
-#define PLLDIV5		0x164
-#define PLLDIV6		0x168
-#define PLLDIV7		0x16C
-#define PLLDIV8		0x170
+#define PLLM        0x110
+#define PREDIV      0x114
+#define PLLDIV2     0x11C
+#define POSTDIV     0x128
+#define PLLDIV4     0x160
+#define PLLDIV5     0x164
+#define PLLDIV6     0x168
+#define PLLDIV7     0x16C
+#define PLLDIV8     0x170
 
 
 int davinci_clk_init(void)
 {
-	struct clk *clk_list;
-	int num_clks;
-	rt_uint32_t pll0_mult, pll1_mult;
-
-	unsigned long prediv, postdiv;
-	unsigned long pll_rate;
-	unsigned long pll_div2, pll_div4, pll_div5,
-		pll_div6, pll_div7, pll_div8;
-
-	rt_list_init(&clocks);
-
-	//davinci_psc_register(davinci_psc_base, 1);
-
-	pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
-	pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM);
-
-	commonrate = ((pll0_mult + 1) * 27000000) / 6;
-	armrate = ((pll0_mult + 1) * 27000000) / 2;
-
-	fixedrate = 24000000;
-
-	/* Read PLL0 configuration */
-	prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) &
-			0x1f) + 1;
-	postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) &
-			0x1f) + 1;
-
-	/* PLL0 dividers */
-	pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) &
-			0x1f) + 1; /* EDMA, EMAC, config, common */
-	pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) &
-			0x1f) + 1; /* VPSS */
-	pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) &
-			0x1f) + 1; /* VENC */
-	pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) &
-			0x1f) + 1; /* DDR */
-	pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) &
-			0x1f) + 1; /* MMC/SD */
-
-	pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv;
-
-	commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */
-	vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */
-	vencrate_sd = pll_rate / pll_div6; /* 486/18 =  27MHz */
-	ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */
-	mmcsdrate = pll_rate / pll_div8; /* 486/4 =  121.5MHz */
-
-	rt_kprintf(
-		"PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n",
-		fixedrate, commonrate, vpssrate);
-	rt_kprintf(
-		"PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n",
-		vencrate_sd, (ddrrate/2), mmcsdrate);
-
-	/* Read PLL1 configuration */
-	prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) &
-			0x1f) + 1;
-	postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) &
-			0x1f) + 1;
-	pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv;
-
-	/* PLL1 dividers */
-	pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) &
-			0x1f) + 1; /* ARM */
-	pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) &
-			0x1f) + 1; /* VOICE */
-	pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) &
-			0x1f) + 1; /* VENC */
-
-	armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */
-	voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */
-	vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */
-
-	rt_kprintf(
-		"PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n",
-		armrate, voicerate, vencrate_hd);
-
-	clk_list = davinci_dm365_clks;
-	num_clks = ARRAY_SIZE(davinci_dm365_clks); 
-
-	return davinci_register_clks(clk_list, num_clks);
+    struct clk *clk_list;
+    int num_clks;
+    rt_uint32_t pll0_mult, pll1_mult;
+
+    unsigned long prediv, postdiv;
+    unsigned long pll_rate;
+    unsigned long pll_div2, pll_div4, pll_div5,
+        pll_div6, pll_div7, pll_div8;
+
+    rt_list_init(&clocks);
+
+    //davinci_psc_register(davinci_psc_base, 1);
+
+    pll0_mult = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLM);
+    pll1_mult = davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLM);
+
+    commonrate = ((pll0_mult + 1) * 27000000) / 6;
+    armrate = ((pll0_mult + 1) * 27000000) / 2;
+
+    fixedrate = 24000000;
+
+    /* Read PLL0 configuration */
+    prediv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PREDIV) &
+            0x1f) + 1;
+    postdiv = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + POSTDIV) &
+            0x1f) + 1;
+
+    /* PLL0 dividers */
+    pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV4) &
+            0x1f) + 1; /* EDMA, EMAC, config, common */
+    pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV5) &
+            0x1f) + 1; /* VPSS */
+    pll_div6 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV6) &
+            0x1f) + 1; /* VENC */
+    pll_div7 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV7) &
+            0x1f) + 1; /* DDR */
+    pll_div8 = (davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLDIV8) &
+            0x1f) + 1; /* MMC/SD */
+
+    pll_rate = ((fixedrate / prediv) * (2 * pll0_mult)) / postdiv;
+
+    commonrate = pll_rate / pll_div4; /* 486/4 = 121.5MHz */
+    vpssrate = pll_rate / pll_div5; /* 486/2 = 243MHz */
+    vencrate_sd = pll_rate / pll_div6; /* 486/18 =  27MHz */
+    ddrrate = pll_rate / pll_div7; /* 486/2 = 243MHz */
+    mmcsdrate = pll_rate / pll_div8; /* 486/4 =  121.5MHz */
+
+    rt_kprintf(
+        "PLL0: fixedrate: %d, commonrate: %d, vpssrate: %d\n",
+        fixedrate, commonrate, vpssrate);
+    rt_kprintf(
+        "PLL0: vencrate_sd: %d, ddrrate: %d mmcsdrate: %d\n",
+        vencrate_sd, (ddrrate/2), mmcsdrate);
+
+    /* Read PLL1 configuration */
+    prediv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PREDIV) &
+            0x1f) + 1;
+    postdiv = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + POSTDIV) &
+            0x1f) + 1;
+    pll_rate = ((fixedrate / prediv) * (2 * pll1_mult)) / postdiv;
+
+    /* PLL1 dividers */
+    pll_div2 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV2) &
+            0x1f) + 1; /* ARM */
+    pll_div4 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV4) &
+            0x1f) + 1; /* VOICE */
+    pll_div5 = (davinci_readl(DAVINCI_PLL_CNTRL1_BASE + PLLDIV5) &
+            0x1f) + 1; /* VENC */
+
+    armrate = pll_rate / pll_div2; /* 594/2 = 297MHz */
+    voicerate = pll_rate / pll_div4; /* 594/6 = 99MHz */
+    vencrate_hd = pll_rate / pll_div5; /* 594/8 = 74.25MHz */
+
+    rt_kprintf(
+        "PLL1: armrate: %d, voicerate: %d, vencrate_hd: %d\n",
+        armrate, voicerate, vencrate_hd);
+
+    clk_list = davinci_dm365_clks;
+    num_clks = ARRAY_SIZE(davinci_dm365_clks);
+
+    return davinci_register_clks(clk_list, num_clks);
 }
 
 int platform_init(void)
 {
-	edma_init(dm365_edma_info);
+    edma_init(dm365_edma_info);
 }
 
 INIT_BOARD_EXPORT(platform_init);
@@ -312,44 +312,44 @@ INIT_BOARD_EXPORT(platform_init);
 /* Reset board using the watchdog timer */
 void reset_system(void)
 {
-	rt_uint32_t tgcr, wdtcr;
-	rt_uint32_t base = DAVINCI_WDOG_BASE;
-
-	/* Disable, internal clock source */
-	davinci_writel(0, base + TCR);
-
-	/* Reset timer, set mode to 64-bit watchdog, and unreset */
-	davinci_writel(0, base + TGCR);
-	tgcr =	(TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) |
-		(TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
-		(TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
-	davinci_writel(tgcr, base + TGCR);
-
-	/* Clear counter and period regs */
-	davinci_writel(0, base + TIM12);
-	davinci_writel(0, base + TIM34);
-	davinci_writel(0, base + PRD12);
-	davinci_writel(0, base + PRD34);
-
-	/* Enable periodic mode */
-	davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR);
-
-	/* Put watchdog in pre-active state */
-	wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
-		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-	davinci_writel(wdtcr, base + WDTCR);
-
-	/* Put watchdog in active state */
-	wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
-		(WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
-	davinci_writel(wdtcr, base + WDTCR);
-
-	/*
-	 * Write an invalid value to the WDKEY field to trigger
-	 * a watchdog reset.
-	 */
-	wdtcr = 0xDEADBEEF;
-	davinci_writel(wdtcr, base + WDTCR);
+    rt_uint32_t tgcr, wdtcr;
+    rt_uint32_t base = DAVINCI_WDOG_BASE;
+
+    /* Disable, internal clock source */
+    davinci_writel(0, base + TCR);
+
+    /* Reset timer, set mode to 64-bit watchdog, and unreset */
+    davinci_writel(0, base + TGCR);
+    tgcr =  (TGCR_TIMMODE_64BIT_WDOG << TGCR_TIMMODE_SHIFT) |
+        (TGCR_UNRESET << TGCR_TIM12RS_SHIFT) |
+        (TGCR_UNRESET << TGCR_TIM34RS_SHIFT);
+    davinci_writel(tgcr, base + TGCR);
+
+    /* Clear counter and period regs */
+    davinci_writel(0, base + TIM12);
+    davinci_writel(0, base + TIM34);
+    davinci_writel(0, base + PRD12);
+    davinci_writel(0, base + PRD34);
+
+    /* Enable periodic mode */
+    davinci_writel(TCR_ENAMODE_PERIODIC << ENAMODE12_SHIFT, base + TCR);
+
+    /* Put watchdog in pre-active state */
+    wdtcr = (WDTCR_WDKEY_SEQ0 << WDTCR_WDKEY_SHIFT) |
+        (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+    davinci_writel(wdtcr, base + WDTCR);
+
+    /* Put watchdog in active state */
+    wdtcr = (WDTCR_WDKEY_SEQ1 << WDTCR_WDKEY_SHIFT) |
+        (WDTCR_WDEN_ENABLE << WDTCR_WDEN_SHIFT);
+    davinci_writel(wdtcr, base + WDTCR);
+
+    /*
+     * Write an invalid value to the WDKEY field to trigger
+     * a watchdog reset.
+     */
+    wdtcr = 0xDEADBEEF;
+    davinci_writel(wdtcr, base + WDTCR);
 }
 
 

bsp/dm365/platform/dm365_timer.h

@@ -4,57 +4,57 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __ASM_ARCH_TIME_H
 #define __ASM_ARCH_TIME_H
 
 /* Timer register offsets */
-#define PID12				0x0
-#define TIM12				0x10
-#define TIM34				0x14
-#define PRD12				0x18
-#define PRD34				0x1c
-#define TCR				0x20
-#define TGCR				0x24
-#define WDTCR				0x28
-#define CMP12(n)			(0x60 + ((n) << 2))
+#define PID12               0x0
+#define TIM12               0x10
+#define TIM34               0x14
+#define PRD12               0x18
+#define PRD34               0x1c
+#define TCR             0x20
+#define TGCR                0x24
+#define WDTCR               0x28
+#define CMP12(n)            (0x60 + ((n) << 2))
 
 /* Timer register bitfields */
-#define ENAMODE12_SHIFT 		6
-#define ENAMODE34_SHIFT 		22
-#define TCR_ENAMODE_DISABLE		0x0
-#define TCR_ENAMODE_ONESHOT		0x1
-#define TCR_ENAMODE_PERIODIC		0x2
-#define TCR_ENAMODE_MASK		0x3
-
-#define TGCR_TIMMODE_SHIFT		2
-#define TGCR_TIMMODE_64BIT_GP		0x0
-#define TGCR_TIMMODE_32BIT_UNCHAINED	0x1
-#define TGCR_TIMMODE_64BIT_WDOG 	0x2
-#define TGCR_TIMMODE_32BIT_CHAINED	0x3
-
-#define TGCR_TIM12RS_SHIFT		0
-#define TGCR_TIM34RS_SHIFT		1
-#define TGCR_RESET			0x0
-#define TGCR_UNRESET			0x1
-#define TGCR_RESET_MASK 		0x3
-
-#define WDTCR_WDEN_SHIFT		14
-#define WDTCR_WDEN_DISABLE		0x0
-#define WDTCR_WDEN_ENABLE		0x1
-#define WDTCR_WDKEY_SHIFT		16
-#define WDTCR_WDKEY_SEQ0		0xA5C6
-#define WDTCR_WDKEY_SEQ1		0xDA7E
+#define ENAMODE12_SHIFT         6
+#define ENAMODE34_SHIFT         22
+#define TCR_ENAMODE_DISABLE     0x0
+#define TCR_ENAMODE_ONESHOT     0x1
+#define TCR_ENAMODE_PERIODIC        0x2
+#define TCR_ENAMODE_MASK        0x3
+
+#define TGCR_TIMMODE_SHIFT      2
+#define TGCR_TIMMODE_64BIT_GP       0x0
+#define TGCR_TIMMODE_32BIT_UNCHAINED    0x1
+#define TGCR_TIMMODE_64BIT_WDOG     0x2
+#define TGCR_TIMMODE_32BIT_CHAINED  0x3
+
+#define TGCR_TIM12RS_SHIFT      0
+#define TGCR_TIM34RS_SHIFT      1
+#define TGCR_RESET          0x0
+#define TGCR_UNRESET            0x1
+#define TGCR_RESET_MASK         0x3
+
+#define WDTCR_WDEN_SHIFT        14
+#define WDTCR_WDEN_DISABLE      0x0
+#define WDTCR_WDEN_ENABLE       0x1
+#define WDTCR_WDKEY_SHIFT       16
+#define WDTCR_WDKEY_SEQ0        0xA5C6
+#define WDTCR_WDKEY_SEQ1        0xDA7E
 
 enum {
-	T0_BOT,
-	T0_TOP,
-	T1_BOT,
-	T1_TOP,
-	NUM_TIMERS
+    T0_BOT,
+    T0_TOP,
+    T1_BOT,
+    T1_TOP,
+    NUM_TIMERS
 };
 
 #endif /* __ASM_ARCH_TIME_H__ */

bsp/dm365/platform/dm36x.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __DM36X_H__
@@ -29,43 +29,43 @@ extern "C" {
 /*
  * Base register addresses
  */
-#define DAVINCI_DMA_3PCC_BASE			(0x01C00000)
-#define DAVINCI_DMA_3PTC0_BASE			(0x01C10000)
-#define DAVINCI_DMA_3PTC1_BASE			(0x01C10400)
-#define DAVINCI_I2C_BASE			(0x01C21000)
-#define DAVINCI_TIMER0_BASE			(0x01C21400)
-#define DAVINCI_TIMER1_BASE			(0x01C21800)
-#define DAVINCI_WDOG_BASE			(0x01C21C00)
-#define DAVINCI_PWM0_BASE			(0x01C22000)
-#define DAVINCI_PWM1_BASE			(0x01C22400)
-#define DAVINCI_PWM2_BASE			(0x01C22800)
-#define DAVINCI_SYSTEM_MODULE_BASE		(0x01C40000)
-#define DAVINCI_PLL_CNTRL0_BASE			(0x01C40800)
-#define DAVINCI_PLL_CNTRL1_BASE			(0x01C40C00)
-#define DAVINCI_PWR_SLEEP_CNTRL_BASE		(0x01C41000)
-#define DAVINCI_SYSTEM_DFT_BASE			(0x01C42000)
-#define DAVINCI_IEEE1394_BASE			(0x01C60000)
-#define DAVINCI_USB_OTG_BASE			(0x01C64000)
-#define DAVINCI_CFC_ATA_BASE			(0x01C66000)
-#define DAVINCI_SPI_BASE			(0x01C66800)
-#define DAVINCI_GPIO_BASE			(0x01C67000)
-#define DAVINCI_UHPI_BASE			(0x01C67800)
-#define DAVINCI_VPSS_REGS_BASE			(0x01C70000)
-#define DAVINCI_EMAC_CNTRL_REGS_BASE		(0x01C80000)
-#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE	(0x01C81000)
-#define DAVINCI_EMAC_WRAPPER_RAM_BASE		(0x01C82000)
-#define DAVINCI_MDIO_CNTRL_REGS_BASE		(0x01C84000)
-#define DAVINCI_IMCOP_BASE			(0x01CC0000)
-#define DAVINCI_ASYNC_EMIF_CNTRL_BASE		(0x01E00000)
-#define DAVINCI_VLYNQ_BASE			(0x01E01000)
-#define DAVINCI_MCBSP_BASE			(0x01E02000)
-#define DAVINCI_MMC_SD_BASE			(0x01E10000)
-#define DAVINCI_MS_BASE				(0x01E20000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE	(0x02000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE	(0x04000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE	(0x06000000)
-#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE	(0x08000000)
-#define DAVINCI_VLYNQ_REMOTE_BASE		(0x0C000000)
+#define DAVINCI_DMA_3PCC_BASE           (0x01C00000)
+#define DAVINCI_DMA_3PTC0_BASE          (0x01C10000)
+#define DAVINCI_DMA_3PTC1_BASE          (0x01C10400)
+#define DAVINCI_I2C_BASE            (0x01C21000)
+#define DAVINCI_TIMER0_BASE         (0x01C21400)
+#define DAVINCI_TIMER1_BASE         (0x01C21800)
+#define DAVINCI_WDOG_BASE           (0x01C21C00)
+#define DAVINCI_PWM0_BASE           (0x01C22000)
+#define DAVINCI_PWM1_BASE           (0x01C22400)
+#define DAVINCI_PWM2_BASE           (0x01C22800)
+#define DAVINCI_SYSTEM_MODULE_BASE      (0x01C40000)
+#define DAVINCI_PLL_CNTRL0_BASE         (0x01C40800)
+#define DAVINCI_PLL_CNTRL1_BASE         (0x01C40C00)
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE        (0x01C41000)
+#define DAVINCI_SYSTEM_DFT_BASE         (0x01C42000)
+#define DAVINCI_IEEE1394_BASE           (0x01C60000)
+#define DAVINCI_USB_OTG_BASE            (0x01C64000)
+#define DAVINCI_CFC_ATA_BASE            (0x01C66000)
+#define DAVINCI_SPI_BASE            (0x01C66800)
+#define DAVINCI_GPIO_BASE           (0x01C67000)
+#define DAVINCI_UHPI_BASE           (0x01C67800)
+#define DAVINCI_VPSS_REGS_BASE          (0x01C70000)
+#define DAVINCI_EMAC_CNTRL_REGS_BASE        (0x01C80000)
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE    (0x01C81000)
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE       (0x01C82000)
+#define DAVINCI_MDIO_CNTRL_REGS_BASE        (0x01C84000)
+#define DAVINCI_IMCOP_BASE          (0x01CC0000)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE       (0x01E00000)
+#define DAVINCI_VLYNQ_BASE          (0x01E01000)
+#define DAVINCI_MCBSP_BASE          (0x01E02000)
+#define DAVINCI_MMC_SD_BASE         (0x01E10000)
+#define DAVINCI_MS_BASE             (0x01E20000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE    (0x02000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE    (0x04000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE    (0x06000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE    (0x08000000)
+#define DAVINCI_VLYNQ_REMOTE_BASE       (0x0C000000)
 
 
 /*
@@ -77,14 +77,14 @@ extern "C" {
  * In case of only one VLYNQ IP, define only the
  * 'LOW_VLYNQ_CONTROL_BASE'.
  */
-#define LOW_VLYNQ_CONTROL_BASE			DAVINCI_VLYNQ_BASE
+#define LOW_VLYNQ_CONTROL_BASE          DAVINCI_VLYNQ_BASE
 
-#define DM365_EMAC_BASE			(0x01D07000)
-#define DM365_EMAC_CNTRL_OFFSET		(0x0000)
-#define DM365_EMAC_CNTRL_MOD_OFFSET	(0x3000)
-#define DM365_EMAC_CNTRL_RAM_OFFSET	(0x1000)
-#define DM365_EMAC_MDIO_OFFSET		(0x4000)
-#define DM365_EMAC_CNTRL_RAM_SIZE	(0x2000)
+#define DM365_EMAC_BASE         (0x01D07000)
+#define DM365_EMAC_CNTRL_OFFSET     (0x0000)
+#define DM365_EMAC_CNTRL_MOD_OFFSET (0x3000)
+#define DM365_EMAC_CNTRL_RAM_OFFSET (0x1000)
+#define DM365_EMAC_MDIO_OFFSET      (0x4000)
+#define DM365_EMAC_CNTRL_RAM_SIZE   (0x2000)
 
 
 /*
@@ -96,117 +96,117 @@ extern "C" {
 /*
  * System module registers
  */
-#define PINMUX0		(DAVINCI_SYSTEM_MODULE_BASE + 0x00)
-#define PINMUX1		(DAVINCI_SYSTEM_MODULE_BASE + 0x04)
-#define PINMUX2		(DAVINCI_SYSTEM_MODULE_BASE + 0x08)
-#define PINMUX3		(DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
-#define PINMUX4		(DAVINCI_SYSTEM_MODULE_BASE + 0x10)
+#define PINMUX0     (DAVINCI_SYSTEM_MODULE_BASE + 0x00)
+#define PINMUX1     (DAVINCI_SYSTEM_MODULE_BASE + 0x04)
+#define PINMUX2     (DAVINCI_SYSTEM_MODULE_BASE + 0x08)
+#define PINMUX3     (DAVINCI_SYSTEM_MODULE_BASE + 0x0c)
+#define PINMUX4     (DAVINCI_SYSTEM_MODULE_BASE + 0x10)
 
-#define DM365_ARM_INTMUX	(DAVINCI_SYSTEM_MODULE_BASE + 0x18)
-#define DM365_EDMA_EVTMUX	(DAVINCI_SYSTEM_MODULE_BASE + 0x1C)
-#define DAVINCI_PUPDCTL1	(DAVINCI_SYSTEM_MODULE_BASE + 0x7C)
+#define DM365_ARM_INTMUX    (DAVINCI_SYSTEM_MODULE_BASE + 0x18)
+#define DM365_EDMA_EVTMUX   (DAVINCI_SYSTEM_MODULE_BASE + 0x1C)
+#define DAVINCI_PUPDCTL1    (DAVINCI_SYSTEM_MODULE_BASE + 0x7C)
 
 
 
-#define ASYNC_EMIF_REVID	0x00
-#define ASYNC_EMIF_AWCCR	0x04
-#define ASYNC_EMIF_A1CR 	0x10
-#define ASYNC_EMIF_A2CR 	0x14
-#define ASYNC_EMIF_A3CR 	0x18
+#define ASYNC_EMIF_REVID    0x00
+#define ASYNC_EMIF_AWCCR    0x04
+#define ASYNC_EMIF_A1CR     0x10
+#define ASYNC_EMIF_A2CR     0x14
+#define ASYNC_EMIF_A3CR     0x18
 
 /*
  * Base register addresses common across DM355 and DM365
  */
-#define DM3XX_TIMER2_BASE		(0x01C20800)
-#define DM3XX_REALTIME_BASE		(0x01C20C00)
-#define DM3XX_PWM3_BASE			(0x01C22C00)
-#define DM3XX_SPI_BASE			(0x01C66000)
-#define DM3XX_SPI0_BASE			DM3XX_SPI_BASE
-#define DM3XX_SPI1_BASE			(0x01C66800)
-#define DM3XX_SPI2_BASE			(0x01C67800)
+#define DM3XX_TIMER2_BASE       (0x01C20800)
+#define DM3XX_REALTIME_BASE     (0x01C20C00)
+#define DM3XX_PWM3_BASE         (0x01C22C00)
+#define DM3XX_SPI_BASE          (0x01C66000)
+#define DM3XX_SPI0_BASE         DM3XX_SPI_BASE
+#define DM3XX_SPI1_BASE         (0x01C66800)
+#define DM3XX_SPI2_BASE         (0x01C67800)
 
 
 
 /*
  * DM365 base register address
  */
-#define DM365_DMA_3PTC2_BASE		(0x01C10800)
-#define DM365_DMA_3PTC3_BASE		(0x01C10C00)
-#define DM365_TIMER3_BASE		(0x01C23800)
-#define DM365_ADCIF_BASE		(0x01C23C00)
-#define DM365_SPI3_BASE			(0x01C68000)
-#define DM365_SPI4_BASE			(0x01C23000)
-#define DM365_RTC_BASE			(0x01C69000)
-#define DM365_KEYSCAN_BASE		(0x01C69400)
-#define DM365_UHPI_BASE			(0x01C69800)
-#define DM365_IMCOP_BASE		(0x01CA0000)
-#define DM365_MMC_SD1_BASE		(0x01D00000)
-#define DM365_MCBSP_BASE		(0x01D02000)
-#define DM365_UART1_BASE		(0x01D06000)
-#define DM365_EMAC_CNTRL_BASE		(0x01D07000)
-#define DM365_EMAC_WRAP_RAM_BASE	(0x01D08000)
-#define DM365_EMAC_WRAP_CNTRL_BASE	(0x01D0A000)
-#define DM365_EMAC_MDIO_BASE		(0x01D0B000)
-#define DM365_VOICE_CODEC_BASE		(0x01D0C000)
-#define DM365_ASYNC_EMIF_CNTRL_BASE	(0x01D10000)
-#define DM365_MMC_SD0_BASE		(0x01D11000)
-#define DM365_MS_BASE			(0x01D20000)
-#define DM365_KALEIDO_BASE		(0x01E00000)
-
-#define DAVINCI_UART0_BASE		(0x01C20000)
-
-#define PSC_MDCTL_BASE			(0x01c41a00)
-#define PSC_MDSTAT_BASE			(0x01c41800)
-#define PSC_PTCMD			(0x01c41120)
-#define PSC_PTSTAT			(0x01c41128)
-
-#define DM365_EINT_ENABLE0		0x01c48018
-#define DM365_EINT_ENABLE1		0x01c4801c
-
-#define davinci_readb(a)	(*(volatile unsigned char  *)(a))
-#define davinci_readw(a)	(*(volatile unsigned short *)(a))
-#define davinci_readl(a)	(*(volatile unsigned int   *)(a))
-
-#define davinci_writeb(v,a)	(*(volatile unsigned char  *)(a) = (v))
-#define davinci_writew(v,a)	(*(volatile unsigned short *)(a) = (v))
-#define davinci_writel(v,a)	(*(volatile unsigned int   *)(a) = (v))
-
-#define readb(a)	davinci_readb(a)
-#define readw(a)	davinci_readw(a)
-#define readl(a)	davinci_readl(a)
-
-#define write(v,a)	davinci_writeb(v,a)
-#define writew(v,a)	davinci_writew(v,a)
-#define writel(v,a)	davinci_writel(v,a)
+#define DM365_DMA_3PTC2_BASE        (0x01C10800)
+#define DM365_DMA_3PTC3_BASE        (0x01C10C00)
+#define DM365_TIMER3_BASE       (0x01C23800)
+#define DM365_ADCIF_BASE        (0x01C23C00)
+#define DM365_SPI3_BASE         (0x01C68000)
+#define DM365_SPI4_BASE         (0x01C23000)
+#define DM365_RTC_BASE          (0x01C69000)
+#define DM365_KEYSCAN_BASE      (0x01C69400)
+#define DM365_UHPI_BASE         (0x01C69800)
+#define DM365_IMCOP_BASE        (0x01CA0000)
+#define DM365_MMC_SD1_BASE      (0x01D00000)
+#define DM365_MCBSP_BASE        (0x01D02000)
+#define DM365_UART1_BASE        (0x01D06000)
+#define DM365_EMAC_CNTRL_BASE       (0x01D07000)
+#define DM365_EMAC_WRAP_RAM_BASE    (0x01D08000)
+#define DM365_EMAC_WRAP_CNTRL_BASE  (0x01D0A000)
+#define DM365_EMAC_MDIO_BASE        (0x01D0B000)
+#define DM365_VOICE_CODEC_BASE      (0x01D0C000)
+#define DM365_ASYNC_EMIF_CNTRL_BASE (0x01D10000)
+#define DM365_MMC_SD0_BASE      (0x01D11000)
+#define DM365_MS_BASE           (0x01D20000)
+#define DM365_KALEIDO_BASE      (0x01E00000)
+
+#define DAVINCI_UART0_BASE      (0x01C20000)
+
+#define PSC_MDCTL_BASE          (0x01c41a00)
+#define PSC_MDSTAT_BASE         (0x01c41800)
+#define PSC_PTCMD           (0x01c41120)
+#define PSC_PTSTAT          (0x01c41128)
+
+#define DM365_EINT_ENABLE0      0x01c48018
+#define DM365_EINT_ENABLE1      0x01c4801c
+
+#define davinci_readb(a)    (*(volatile unsigned char  *)(a))
+#define davinci_readw(a)    (*(volatile unsigned short *)(a))
+#define davinci_readl(a)    (*(volatile unsigned int   *)(a))
+
+#define davinci_writeb(v,a) (*(volatile unsigned char  *)(a) = (v))
+#define davinci_writew(v,a) (*(volatile unsigned short *)(a) = (v))
+#define davinci_writel(v,a) (*(volatile unsigned int   *)(a) = (v))
+
+#define readb(a)    davinci_readb(a)
+#define readw(a)    davinci_readw(a)
+#define readl(a)    davinci_readl(a)
+
+#define write(v,a)  davinci_writeb(v,a)
+#define writew(v,a) davinci_writew(v,a)
+#define writel(v,a) davinci_writel(v,a)
 
 /* define timer register struct*/
 typedef struct timer_regs_s {
-	rt_uint32_t pid12;            /* 0x0 */
-	rt_uint32_t emumgt_clksped;   /* 0x4 */
-	rt_uint32_t gpint_en;         /* 0x8 */
-	rt_uint32_t gpdir_dat;        /* 0xC */
-	rt_uint32_t tim12;            /* 0x10 */
-	rt_uint32_t tim34;            /* 0x14 */
-	rt_uint32_t prd12;            /* 0x18 */
-	rt_uint32_t prd34;            /* 0x1C */
-	rt_uint32_t tcr;              /* 0x20 */
-	rt_uint32_t tgcr;             /* 0x24 */
-	rt_uint32_t wdtcr;            /* 0x28 */
-	rt_uint32_t tlgc;             /* 0x2C */
-	rt_uint32_t tlmr;             /* 0x30 */
+    rt_uint32_t pid12;            /* 0x0 */
+    rt_uint32_t emumgt_clksped;   /* 0x4 */
+    rt_uint32_t gpint_en;         /* 0x8 */
+    rt_uint32_t gpdir_dat;        /* 0xC */
+    rt_uint32_t tim12;            /* 0x10 */
+    rt_uint32_t tim34;            /* 0x14 */
+    rt_uint32_t prd12;            /* 0x18 */
+    rt_uint32_t prd34;            /* 0x1C */
+    rt_uint32_t tcr;              /* 0x20 */
+    rt_uint32_t tgcr;             /* 0x24 */
+    rt_uint32_t wdtcr;            /* 0x28 */
+    rt_uint32_t tlgc;             /* 0x2C */
+    rt_uint32_t tlmr;             /* 0x30 */
 } timer_regs_t;
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE		0x10
-#define FIQMODE			0x11
-#define IRQMODE			0x12
-#define SVCMODE			0x13
-#define ABORTMODE		0x17
-#define UNDEFMODE		0x1b
-#define MODEMASK		0x1f
-#define NOINT			0xc0
+#define USERMODE        0x10
+#define FIQMODE         0x11
+#define IRQMODE         0x12
+#define SVCMODE         0x13
+#define ABORTMODE       0x17
+#define UNDEFMODE       0x1b
+#define MODEMASK        0x1f
+#define NOINT           0xc0
 
 struct rt_hw_register
 {

bsp/dm365/platform/edma.h

@@ -4,22 +4,22 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 /*
  * This EDMA3 programming framework exposes two basic kinds of resource:
  *
- *  Channel	Triggers transfers, usually from a hardware event but
- *		also manually or by "chaining" from DMA completions.
- *		Each channel is coupled to a Parameter RAM (PaRAM) slot.
+ *  Channel Triggers transfers, usually from a hardware event but
+ *      also manually or by "chaining" from DMA completions.
+ *      Each channel is coupled to a Parameter RAM (PaRAM) slot.
  *
- *  Slot	Each PaRAM slot holds a DMA transfer descriptor (PaRAM
- *		"set"), source and destination addresses, a link to a
- *		next PaRAM slot (if any), options for the transfer, and
- *		instructions for updating those addresses.  There are
- *		more than twice as many slots as event channels.
+ *  Slot    Each PaRAM slot holds a DMA transfer descriptor (PaRAM
+ *      "set"), source and destination addresses, a link to a
+ *      next PaRAM slot (if any), options for the transfer, and
+ *      instructions for updating those addresses.  There are
+ *      more than twice as many slots as event channels.
  *
  * Each PaRAM set describes a sequence of transfers, either for one large
  * buffer or for several discontiguous smaller buffers.  An EDMA transfer
@@ -52,14 +52,14 @@
 
 /* PaRAM slots are laid out like this */
 struct edmacc_param {
-	unsigned int opt;
-	unsigned int src;
-	unsigned int a_b_cnt;
-	unsigned int dst;
-	unsigned int src_dst_bidx;
-	unsigned int link_bcntrld;
-	unsigned int src_dst_cidx;
-	unsigned int ccnt;
+    unsigned int opt;
+    unsigned int src;
+    unsigned int a_b_cnt;
+    unsigned int dst;
+    unsigned int src_dst_bidx;
+    unsigned int link_bcntrld;
+    unsigned int src_dst_cidx;
+    unsigned int ccnt;
 };
 
 #define CCINT0_INTERRUPT     16
@@ -68,110 +68,110 @@ struct edmacc_param {
 #define TCERRINT1_INTERRUPT   19
 
 /* fields in edmacc_param.opt */
-#define SAM		BIT(0)
-#define DAM		BIT(1)
-#define SYNCDIM		BIT(2)
-#define STATIC		BIT(3)
-#define EDMA_FWID	(0x07 << 8)
-#define TCCMODE		BIT(11)
-#define EDMA_TCC(t)	((t) << 12)
-#define TCINTEN		BIT(20)
-#define ITCINTEN	BIT(21)
-#define TCCHEN		BIT(22)
-#define ITCCHEN		BIT(23)
+#define SAM     BIT(0)
+#define DAM     BIT(1)
+#define SYNCDIM     BIT(2)
+#define STATIC      BIT(3)
+#define EDMA_FWID   (0x07 << 8)
+#define TCCMODE     BIT(11)
+#define EDMA_TCC(t) ((t) << 12)
+#define TCINTEN     BIT(20)
+#define ITCINTEN    BIT(21)
+#define TCCHEN      BIT(22)
+#define ITCCHEN     BIT(23)
 
 #define TRWORD (0x7<<2)
 #define PAENTRY (0x1ff<<5)
 
 /* DM365 specific EDMA3 Events Information */
 enum dm365_edma_ch {
-	DM365_DMA_TIMER3_TINT6,
-	DM365_DMA_TIMER3_TINT7,
-	DM365_DMA_MCBSP_TX = 2,
-	DM365_DMA_VCIF_TX = 2,
-	DM365_DMA_MCBSP_RX = 3,
-	DM365_DMA_VCIF_RX = 3,
-	DM365_DMA_VPSS_EVT1,
-	DM365_DMA_VPSS_EVT2,
-	DM365_DMA_VPSS_EVT3,
-	DM365_DMA_VPSS_EVT4,
-	DM365_DMA_TIMER2_TINT4,
-	DM365_DMA_TIMER2_TINT5,
-	DM365_DMA_SPI2XEVT,
-	DM365_DMA_SPI2REVT,
-	DM365_DMA_IMCOP_IMX0INT = 12,
-	DM365_DMA_KALEIDO_ARMINT = 12,
-	DM365_DMA_IMCOP_SEQINT,
-	DM365_DMA_SPI1XEVT,
-	DM365_DMA_SPI1REVT,
-	DM365_DMA_SPI0XEVT,
-	DM365_DMA_SPI0REVT,
-	DM365_DMA_URXEVT0 = 18,
-	DM365_DMA_SPI3XEVT = 18,
-	DM365_DMA_UTXEVT0 = 19,
-	DM365_DMA_SPI3REVT = 19,
-	DM365_DMA_URXEVT1,
-	DM365_DMA_UTXEVT1,
-	DM365_DMA_TIMER4_TINT8,
-	DM365_DMA_TIMER4_TINT9,
-	DM365_DMA_RTOINT,
-	DM365_DMA_GPIONT9,
-	DM365_DMA_MMC0RXEVT = 26,
-	DM365_DMA_MEMSTK_MSEVT = 26,
-	DM365_DMA_MMC0TXEVT,
-	DM365_DMA_I2C_ICREVT,
-	DM365_DMA_I2C_ICXEVT,
-	DM365_DMA_MMC1RXEVT,
-	DM365_DMA_MMC1TXEVT,
-	DM365_DMA_GPIOINT0,
-	DM365_DMA_GPIOINT1,
-	DM365_DMA_GPIOINT2,
-	DM365_DMA_GPIOINT3,
-	DM365_DMA_GPIOINT4,
-	DM365_DMA_GPIOINT5,
-	DM365_DMA_GPIOINT6,
-	DM365_DMA_GPIOINT7,
-	DM365_DMA_GPIOINT10 = 40,
-	DM365_DMA_EMAC_RXTHREESH = 40,
-	DM365_DMA_GPIOINT11 = 41,
-	DM365_DMA_EMAC_RXPULSE = 41,
-	DM365_DMA_GPIOINT12 = 42,
-	DM365_DMA_EMAC_TXPULSE = 42,
-	DM365_DMA_GPIOINT13 = 43,
-	DM365_DMA_EMAC_MISCPULSE = 43,
-	DM365_DMA_GPIOINT14 = 44,
-	DM365_DMA_SPI4XEVT = 44,
-	DM365_DMA_GPIOINT15 = 45,
-	DM365_DMA_SPI4REVT = 45,
-	DM365_DMA_ADC_ADINT,
-	DM365_DMA_GPIOINT8,
-	DM365_DMA_TIMER0_TINT0,
-	DM365_DMA_TIMER0_TINT1,
-	DM365_DMA_TIMER1_TINT2,
-	DM365_DMA_TIMER1_TINT3,
-	DM365_DMA_PWM0,
-	DM365_DMA_PWM1 = 53,
-	DM365_DMA_IMCOP_IMX1INT = 53,
-	DM365_DMA_PWM2 = 54,
-	DM365_DMA_IMCOP_NSFINT = 54,
-	DM365_DMA_PWM3 = 55,
-	DM365_DMA_KALEIDO6_CP_UNDEF = 55,
-	DM365_DMA_IMCOP_VLCDINT = 56,
-	DM365_DMA_KALEIDO5_CP_ECDCMP = 56,
-	DM365_DMA_IMCOP_BIMINT = 57,
-	DM365_DMA_KALEIDO8_CP_ME = 57,
-	DM365_DMA_IMCOP_DCTINT = 58,
-	DM365_DMA_KALEIDO1_CP_CALC = 58,
-	DM365_DMA_IMCOP_QIQINT = 59,
-	DM365_DMA_KALEIDO7_CP_IPE = 59,
-	DM365_DMA_IMCOP_BPSINT = 60,
-	DM365_DMA_KALEIDO2_CP_BS = 60,
-	DM365_DMA_IMCOP_VLCDERRINT = 61,
-	DM365_DMA_KALEIDO0_CP_LPF = 61,
-	DM365_DMA_IMCOP_RCNTINT = 62,
-	DM365_DMA_KALEIDO3_CP_MC = 62,
-	DM365_DMA_IMCOP_COPCINT = 63,
-	DM365_DMA_KALEIDO4_CP_ECDEND = 63,
+    DM365_DMA_TIMER3_TINT6,
+    DM365_DMA_TIMER3_TINT7,
+    DM365_DMA_MCBSP_TX = 2,
+    DM365_DMA_VCIF_TX = 2,
+    DM365_DMA_MCBSP_RX = 3,
+    DM365_DMA_VCIF_RX = 3,
+    DM365_DMA_VPSS_EVT1,
+    DM365_DMA_VPSS_EVT2,
+    DM365_DMA_VPSS_EVT3,
+    DM365_DMA_VPSS_EVT4,
+    DM365_DMA_TIMER2_TINT4,
+    DM365_DMA_TIMER2_TINT5,
+    DM365_DMA_SPI2XEVT,
+    DM365_DMA_SPI2REVT,
+    DM365_DMA_IMCOP_IMX0INT = 12,
+    DM365_DMA_KALEIDO_ARMINT = 12,
+    DM365_DMA_IMCOP_SEQINT,
+    DM365_DMA_SPI1XEVT,
+    DM365_DMA_SPI1REVT,
+    DM365_DMA_SPI0XEVT,
+    DM365_DMA_SPI0REVT,
+    DM365_DMA_URXEVT0 = 18,
+    DM365_DMA_SPI3XEVT = 18,
+    DM365_DMA_UTXEVT0 = 19,
+    DM365_DMA_SPI3REVT = 19,
+    DM365_DMA_URXEVT1,
+    DM365_DMA_UTXEVT1,
+    DM365_DMA_TIMER4_TINT8,
+    DM365_DMA_TIMER4_TINT9,
+    DM365_DMA_RTOINT,
+    DM365_DMA_GPIONT9,
+    DM365_DMA_MMC0RXEVT = 26,
+    DM365_DMA_MEMSTK_MSEVT = 26,
+    DM365_DMA_MMC0TXEVT,
+    DM365_DMA_I2C_ICREVT,
+    DM365_DMA_I2C_ICXEVT,
+    DM365_DMA_MMC1RXEVT,
+    DM365_DMA_MMC1TXEVT,
+    DM365_DMA_GPIOINT0,
+    DM365_DMA_GPIOINT1,
+    DM365_DMA_GPIOINT2,
+    DM365_DMA_GPIOINT3,
+    DM365_DMA_GPIOINT4,
+    DM365_DMA_GPIOINT5,
+    DM365_DMA_GPIOINT6,
+    DM365_DMA_GPIOINT7,
+    DM365_DMA_GPIOINT10 = 40,
+    DM365_DMA_EMAC_RXTHREESH = 40,
+    DM365_DMA_GPIOINT11 = 41,
+    DM365_DMA_EMAC_RXPULSE = 41,
+    DM365_DMA_GPIOINT12 = 42,
+    DM365_DMA_EMAC_TXPULSE = 42,
+    DM365_DMA_GPIOINT13 = 43,
+    DM365_DMA_EMAC_MISCPULSE = 43,
+    DM365_DMA_GPIOINT14 = 44,
+    DM365_DMA_SPI4XEVT = 44,
+    DM365_DMA_GPIOINT15 = 45,
+    DM365_DMA_SPI4REVT = 45,
+    DM365_DMA_ADC_ADINT,
+    DM365_DMA_GPIOINT8,
+    DM365_DMA_TIMER0_TINT0,
+    DM365_DMA_TIMER0_TINT1,
+    DM365_DMA_TIMER1_TINT2,
+    DM365_DMA_TIMER1_TINT3,
+    DM365_DMA_PWM0,
+    DM365_DMA_PWM1 = 53,
+    DM365_DMA_IMCOP_IMX1INT = 53,
+    DM365_DMA_PWM2 = 54,
+    DM365_DMA_IMCOP_NSFINT = 54,
+    DM365_DMA_PWM3 = 55,
+    DM365_DMA_KALEIDO6_CP_UNDEF = 55,
+    DM365_DMA_IMCOP_VLCDINT = 56,
+    DM365_DMA_KALEIDO5_CP_ECDCMP = 56,
+    DM365_DMA_IMCOP_BIMINT = 57,
+    DM365_DMA_KALEIDO8_CP_ME = 57,
+    DM365_DMA_IMCOP_DCTINT = 58,
+    DM365_DMA_KALEIDO1_CP_CALC = 58,
+    DM365_DMA_IMCOP_QIQINT = 59,
+    DM365_DMA_KALEIDO7_CP_IPE = 59,
+    DM365_DMA_IMCOP_BPSINT = 60,
+    DM365_DMA_KALEIDO2_CP_BS = 60,
+    DM365_DMA_IMCOP_VLCDERRINT = 61,
+    DM365_DMA_KALEIDO0_CP_LPF = 61,
+    DM365_DMA_IMCOP_RCNTINT = 62,
+    DM365_DMA_KALEIDO3_CP_MC = 62,
+    DM365_DMA_IMCOP_COPCINT = 63,
+    DM365_DMA_KALEIDO4_CP_ECDEND = 63,
 };
 /* end DM365 specific info */
 
@@ -183,48 +183,48 @@ enum dm365_edma_ch {
 #define DMA_TC2_ERROR 4
 
 enum address_mode {
-	INCR = 0,
-	FIFO = 1
+    INCR = 0,
+    FIFO = 1
 };
 
 enum fifo_width {
-	W8BIT = 0,
-	W16BIT = 1,
-	W32BIT = 2,
-	W64BIT = 3,
-	W128BIT = 4,
-	W256BIT = 5
+    W8BIT = 0,
+    W16BIT = 1,
+    W32BIT = 2,
+    W64BIT = 3,
+    W128BIT = 4,
+    W256BIT = 5
 };
 
 enum dma_event_q {
-	EVENTQ_0 = 0,
-	EVENTQ_1 = 1,
-	EVENTQ_2 = 2,
-	EVENTQ_3 = 3,
-	EVENTQ_DEFAULT = -1
+    EVENTQ_0 = 0,
+    EVENTQ_1 = 1,
+    EVENTQ_2 = 2,
+    EVENTQ_3 = 3,
+    EVENTQ_DEFAULT = -1
 };
 
 enum sync_dimension {
-	ASYNC = 0,
-	ABSYNC = 1
+    ASYNC = 0,
+    ABSYNC = 1
 };
 
-#define EDMA_CTLR_CHAN(ctlr, chan)	(((ctlr) << 16) | (chan))
-#define EDMA_CTLR(i)			((i) >> 16)
-#define EDMA_CHAN_SLOT(i)		((i) & 0xffff)
+#define EDMA_CTLR_CHAN(ctlr, chan)  (((ctlr) << 16) | (chan))
+#define EDMA_CTLR(i)            ((i) >> 16)
+#define EDMA_CHAN_SLOT(i)       ((i) & 0xffff)
 
-#define EDMA_CHANNEL_ANY		-1	/* for edma_alloc_channel() */
-#define EDMA_SLOT_ANY			-1	/* for edma_alloc_slot() */
-#define EDMA_CONT_PARAMS_ANY		 1001
-#define EDMA_CONT_PARAMS_FIXED_EXACT	 1002
+#define EDMA_CHANNEL_ANY        -1  /* for edma_alloc_channel() */
+#define EDMA_SLOT_ANY           -1  /* for edma_alloc_slot() */
+#define EDMA_CONT_PARAMS_ANY         1001
+#define EDMA_CONT_PARAMS_FIXED_EXACT     1002
 #define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
 
 #define EDMA_MAX_CC               2
 
 /* alloc/free DMA channels and their dedicated parameter RAM slots */
 int edma_alloc_channel(int channel,
-	void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
-	void *data, enum dma_event_q);
+    void (*callback)(unsigned channel, rt_uint16_t ch_status, void *data),
+    void *data, enum dma_event_q);
 void edma_free_channel(unsigned channel);
 
 /* alloc/free parameter RAM slots */
@@ -237,14 +237,14 @@ int edma_free_cont_slots(unsigned slot, int count);
 
 /* calls that operate on part of a parameter RAM slot */
 void edma_set_src(unsigned slot, rt_uint32_t src_port,
-				enum address_mode mode, enum fifo_width);
+                enum address_mode mode, enum fifo_width);
 void edma_set_dest(unsigned slot, rt_uint32_t dest_port,
-				 enum address_mode mode, enum fifo_width);
+                 enum address_mode mode, enum fifo_width);
 void edma_get_position(unsigned slot, rt_uint32_t *src, rt_uint32_t *dst);
 void edma_set_src_index(unsigned slot, rt_int16_t src_bidx, rt_int16_t src_cidx);
 void edma_set_dest_index(unsigned slot, rt_int16_t dest_bidx, rt_int16_t dest_cidx);
 void edma_set_transfer_params(unsigned slot, rt_uint16_t acnt, rt_uint16_t bcnt, rt_uint16_t ccnt,
-		rt_uint16_t bcnt_rld, enum sync_dimension sync_mode);
+        rt_uint16_t bcnt_rld, enum sync_dimension sync_mode);
 void edma_link(unsigned from, unsigned to);
 void edma_unlink(unsigned from);
 
@@ -263,26 +263,26 @@ void edma_resume(unsigned channel);
 
 struct edma_rsv_info {
 
-	const rt_int16_t	(*rsv_chans)[2];
-	const rt_int16_t	(*rsv_slots)[2];
+    const rt_int16_t    (*rsv_chans)[2];
+    const rt_int16_t    (*rsv_slots)[2];
 };
 
 /* platform_data for EDMA driver */
 struct edma_soc_info {
 
-	/* how many dma resources of each type */
-	unsigned	n_channel;
-	unsigned	n_region;
-	unsigned	n_slot;
-	unsigned	n_tc;
-	unsigned	n_cc;
-	enum dma_event_q	default_queue;
+    /* how many dma resources of each type */
+    unsigned    n_channel;
+    unsigned    n_region;
+    unsigned    n_slot;
+    unsigned    n_tc;
+    unsigned    n_cc;
+    enum dma_event_q    default_queue;
 
-	/* Resource reservation for other cores */
-	struct edma_rsv_info	*rsv;
+    /* Resource reservation for other cores */
+    struct edma_rsv_info    *rsv;
 
-	const rt_int8_t	(*queue_tc_mapping)[2];
-	const rt_int8_t	(*queue_priority_mapping)[2];
+    const rt_int8_t (*queue_tc_mapping)[2];
+    const rt_int8_t (*queue_priority_mapping)[2];
 };
 
 int edma_init(struct edma_soc_info **info);

bsp/dm365/platform/interrupt.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -13,7 +13,7 @@
 #include <rthw.h>
 #include "dm36x.h"
 
-#define MAX_HANDLERS	64
+#define MAX_HANDLERS    64
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -23,95 +23,95 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS];
 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
 rt_uint32_t rt_thread_switch_interrupt_flag;
 
-#define IRQ_BIT(irq)		((irq) & 0x1f)
+#define IRQ_BIT(irq)        ((irq) & 0x1f)
 
-#define FIQ_REG0_OFFSET		0x0000
-#define FIQ_REG1_OFFSET		0x0004
-#define IRQ_REG0_OFFSET		0x0008
-#define IRQ_REG1_OFFSET		0x000C
-#define IRQ_ENT_REG0_OFFSET	0x0018
-#define IRQ_ENT_REG1_OFFSET	0x001C
-#define IRQ_INCTL_REG_OFFSET	0x0020
-#define IRQ_EABASE_REG_OFFSET	0x0024
-#define IRQ_INTPRI0_REG_OFFSET	0x0030
-#define IRQ_INTPRI7_REG_OFFSET	0x004C
+#define FIQ_REG0_OFFSET     0x0000
+#define FIQ_REG1_OFFSET     0x0004
+#define IRQ_REG0_OFFSET     0x0008
+#define IRQ_REG1_OFFSET     0x000C
+#define IRQ_ENT_REG0_OFFSET 0x0018
+#define IRQ_ENT_REG1_OFFSET 0x001C
+#define IRQ_INCTL_REG_OFFSET    0x0020
+#define IRQ_EABASE_REG_OFFSET   0x0024
+#define IRQ_INTPRI0_REG_OFFSET  0x0030
+#define IRQ_INTPRI7_REG_OFFSET  0x004C
 
 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 static const rt_uint8_t dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
-	[IRQ_DM3XX_VPSSINT0]	= 2,
-	[IRQ_DM3XX_VPSSINT1]	= 6,
-	[IRQ_DM3XX_VPSSINT2]	= 6,
-	[IRQ_DM3XX_VPSSINT3]	= 6,
-	[IRQ_DM3XX_VPSSINT4]	= 6,
-	[IRQ_DM3XX_VPSSINT5]	= 6,
-	[IRQ_DM3XX_VPSSINT6]	= 6,
-	[IRQ_DM3XX_VPSSINT7]	= 7,
-	[IRQ_DM3XX_VPSSINT8]	= 6,
-	[IRQ_ASQINT]		= 6,
-	[IRQ_DM365_IMXINT0]	= 6,
-	[IRQ_DM3XX_IMCOPINT]	= 6,
-	[IRQ_USBINT]		= 4,
-	[IRQ_DM3XX_RTOINT]	= 4,
-	[IRQ_DM3XX_TINT5]	= 7,
-	[IRQ_DM3XX_TINT6]	= 7,
-	[IRQ_CCINT0]		= 5,	/* dma */
-	[IRQ_DM3XX_SPINT1_0]	= 5,	/* dma */
-	[IRQ_DM3XX_SPINT1_1]	= 5,	/* dma */
-	[IRQ_DM3XX_SPINT2_0]	= 5,	/* dma */
-	[IRQ_DM365_PSCINT]	= 7,
-	[IRQ_DM3XX_SPINT2_1]	= 7,
-	[IRQ_DM3XX_TINT7]	= 4,
-	[IRQ_DM3XX_SDIOINT0]	= 7,
-	[IRQ_DM365_MBXINT]	= 7,
-	[IRQ_DM365_MBRINT]	= 7,
-	[IRQ_DM3XX_MMCINT0]	= 7,
-	[IRQ_DM3XX_MMCINT1]	= 7,
-	[IRQ_DM3XX_PWMINT3]	= 7,
-	[IRQ_DM365_DDRINT]	= 7,
-	[IRQ_DM365_AEMIFINT]	= 7,
-	[IRQ_DM3XX_SDIOINT1]	= 4,
-	[IRQ_DM365_TINT0]	= 2,	/* clockevent */
-	[IRQ_DM365_TINT1]	= 2,	/* clocksource */
-	[IRQ_DM365_TINT2]	= 7,	/* DSP timer */
-	[IRQ_DM365_TINT3]	= 7,	/* system tick */
-	[IRQ_PWMINT0]		= 7,
-	[IRQ_PWMINT1]		= 7,
-	[IRQ_DM365_PWMINT2]	= 7,
-	[IRQ_DM365_IICINT]	= 3,
-	[IRQ_UARTINT0]		= 3,
-	[IRQ_UARTINT1]		= 3,
-	[IRQ_DM3XX_SPINT0_0]	= 3,
-	[IRQ_DM3XX_SPINT0_1]	= 3,
-	[IRQ_DM3XX_GPIO0]	= 3,
-	[IRQ_DM3XX_GPIO1]	= 7,
-	[IRQ_DM3XX_GPIO2]	= 4,
-	[IRQ_DM3XX_GPIO3]	= 4,
-	[IRQ_DM3XX_GPIO4]	= 7,
-	[IRQ_DM3XX_GPIO5]	= 7,
-	[IRQ_DM3XX_GPIO6]	= 7,
-	[IRQ_DM3XX_GPIO7]	= 7,
-	[IRQ_DM3XX_GPIO8]	= 7,
-	[IRQ_DM3XX_GPIO9]	= 7,
-	[IRQ_DM365_GPIO10]	= 7,
-	[IRQ_DM365_GPIO11]	= 7,
-	[IRQ_DM365_GPIO12]	= 7,
-	[IRQ_DM365_GPIO13]	= 7,
-	[IRQ_DM365_GPIO14]	= 7,
-	[IRQ_DM365_GPIO15]	= 7,
-	[IRQ_DM365_KEYINT]	= 7,
-	[IRQ_DM365_COMMTX]	= 7,
-	[IRQ_DM365_COMMRX]	= 7,
-	[IRQ_EMUINT]		= 7,
+    [IRQ_DM3XX_VPSSINT0]    = 2,
+    [IRQ_DM3XX_VPSSINT1]    = 6,
+    [IRQ_DM3XX_VPSSINT2]    = 6,
+    [IRQ_DM3XX_VPSSINT3]    = 6,
+    [IRQ_DM3XX_VPSSINT4]    = 6,
+    [IRQ_DM3XX_VPSSINT5]    = 6,
+    [IRQ_DM3XX_VPSSINT6]    = 6,
+    [IRQ_DM3XX_VPSSINT7]    = 7,
+    [IRQ_DM3XX_VPSSINT8]    = 6,
+    [IRQ_ASQINT]        = 6,
+    [IRQ_DM365_IMXINT0] = 6,
+    [IRQ_DM3XX_IMCOPINT]    = 6,
+    [IRQ_USBINT]        = 4,
+    [IRQ_DM3XX_RTOINT]  = 4,
+    [IRQ_DM3XX_TINT5]   = 7,
+    [IRQ_DM3XX_TINT6]   = 7,
+    [IRQ_CCINT0]        = 5,    /* dma */
+    [IRQ_DM3XX_SPINT1_0]    = 5,    /* dma */
+    [IRQ_DM3XX_SPINT1_1]    = 5,    /* dma */
+    [IRQ_DM3XX_SPINT2_0]    = 5,    /* dma */
+    [IRQ_DM365_PSCINT]  = 7,
+    [IRQ_DM3XX_SPINT2_1]    = 7,
+    [IRQ_DM3XX_TINT7]   = 4,
+    [IRQ_DM3XX_SDIOINT0]    = 7,
+    [IRQ_DM365_MBXINT]  = 7,
+    [IRQ_DM365_MBRINT]  = 7,
+    [IRQ_DM3XX_MMCINT0] = 7,
+    [IRQ_DM3XX_MMCINT1] = 7,
+    [IRQ_DM3XX_PWMINT3] = 7,
+    [IRQ_DM365_DDRINT]  = 7,
+    [IRQ_DM365_AEMIFINT]    = 7,
+    [IRQ_DM3XX_SDIOINT1]    = 4,
+    [IRQ_DM365_TINT0]   = 2,    /* clockevent */
+    [IRQ_DM365_TINT1]   = 2,    /* clocksource */
+    [IRQ_DM365_TINT2]   = 7,    /* DSP timer */
+    [IRQ_DM365_TINT3]   = 7,    /* system tick */
+    [IRQ_PWMINT0]       = 7,
+    [IRQ_PWMINT1]       = 7,
+    [IRQ_DM365_PWMINT2] = 7,
+    [IRQ_DM365_IICINT]  = 3,
+    [IRQ_UARTINT0]      = 3,
+    [IRQ_UARTINT1]      = 3,
+    [IRQ_DM3XX_SPINT0_0]    = 3,
+    [IRQ_DM3XX_SPINT0_1]    = 3,
+    [IRQ_DM3XX_GPIO0]   = 3,
+    [IRQ_DM3XX_GPIO1]   = 7,
+    [IRQ_DM3XX_GPIO2]   = 4,
+    [IRQ_DM3XX_GPIO3]   = 4,
+    [IRQ_DM3XX_GPIO4]   = 7,
+    [IRQ_DM3XX_GPIO5]   = 7,
+    [IRQ_DM3XX_GPIO6]   = 7,
+    [IRQ_DM3XX_GPIO7]   = 7,
+    [IRQ_DM3XX_GPIO8]   = 7,
+    [IRQ_DM3XX_GPIO9]   = 7,
+    [IRQ_DM365_GPIO10]  = 7,
+    [IRQ_DM365_GPIO11]  = 7,
+    [IRQ_DM365_GPIO12]  = 7,
+    [IRQ_DM365_GPIO13]  = 7,
+    [IRQ_DM365_GPIO14]  = 7,
+    [IRQ_DM365_GPIO15]  = 7,
+    [IRQ_DM365_KEYINT]  = 7,
+    [IRQ_DM365_COMMTX]  = 7,
+    [IRQ_DM365_COMMRX]  = 7,
+    [IRQ_EMUINT]        = 7,
 };
 
 static inline unsigned int davinci_irq_readl(int offset)
 {
-	return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
+    return davinci_readl(DAVINCI_ARM_INTC_BASE + offset);
 }
 
 static inline void davinci_irq_writel(unsigned long value, int offset)
 {
-	davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
+    davinci_writel(value, DAVINCI_ARM_INTC_BASE + offset);
 }
 
 /**
@@ -121,8 +121,8 @@ static inline void davinci_irq_writel(unsigned long value, int offset)
 
 rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-	return RT_NULL;
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    return RT_NULL;
 }
 
 /**
@@ -130,59 +130,59 @@ rt_isr_handler_t rt_hw_interrupt_handle(int vector, void *param)
  */
 void rt_hw_interrupt_init(void)
 {
-	int i;
-	register rt_uint32_t idx;
-	const rt_uint8_t *priority;
-	priority = dm365_default_priorities;
-
-	/* Clear all interrupt requests */
-	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
-
-	/* Disable all interrupts */
-	davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
-	davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
-
-	/* Interrupts disabled immediately, IRQ entry reflects all */
-	davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
-
-	/* we don't use the hardware vector table, just its entry addresses */
-	davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
-
-	/* Clear all interrupt requests */
-	davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
-	davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
-
-	for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
-		unsigned	j;
-		rt_uint32_t	pri;
-
-		for (j = 0, pri = 0; j < 32; j += 4, priority++)
-			pri |= (*priority & 0x07) << j;
-		davinci_irq_writel(pri, i);
-	}
-
-	/* init exceptions table */
-	for(idx=0; idx < MAX_HANDLERS; idx++)
-	{
-		
-		irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
-		irq_desc[idx].param = RT_NULL;
-	#ifdef RT_USING_INTERRUPT_INFO
-		rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
-		irq_desc[idx].counter = 0;
-	#endif
-	}
-
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    int i;
+    register rt_uint32_t idx;
+    const rt_uint8_t *priority;
+    priority = dm365_default_priorities;
+
+    /* Clear all interrupt requests */
+    davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
+
+    /* Disable all interrupts */
+    davinci_irq_writel(0x0, IRQ_ENT_REG0_OFFSET);
+    davinci_irq_writel(0x0, IRQ_ENT_REG1_OFFSET);
+
+    /* Interrupts disabled immediately, IRQ entry reflects all */
+    davinci_irq_writel(0x0, IRQ_INCTL_REG_OFFSET);
+
+    /* we don't use the hardware vector table, just its entry addresses */
+    davinci_irq_writel(0, IRQ_EABASE_REG_OFFSET);
+
+    /* Clear all interrupt requests */
+    davinci_irq_writel(~0x0, FIQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, FIQ_REG1_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG0_OFFSET);
+    davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
+
+    for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
+        unsigned    j;
+        rt_uint32_t pri;
+
+        for (j = 0, pri = 0; j < 32; j += 4, priority++)
+            pri |= (*priority & 0x07) << j;
+        davinci_irq_writel(pri, i);
+    }
+
+    /* init exceptions table */
+    for(idx=0; idx < MAX_HANDLERS; idx++)
+    {
+
+        irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
+        irq_desc[idx].param = RT_NULL;
+    #ifdef RT_USING_INTERRUPT_INFO
+        rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
+        irq_desc[idx].counter = 0;
+    #endif
+    }
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -191,20 +191,20 @@ void rt_hw_interrupt_init(void)
  */
 void rt_hw_interrupt_mask(int irq)
 {
-	unsigned int mask;
-	rt_uint32_t l;
-
-	mask = 1 << IRQ_BIT(irq);
-
-	if (irq > 31) {
-		l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-		l &= ~mask;
-		davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-	} else {
-		l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-		l &= ~mask;
-		davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-	}
+    unsigned int mask;
+    rt_uint32_t l;
+
+    mask = 1 << IRQ_BIT(irq);
+
+    if (irq > 31) {
+        l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
+        l &= ~mask;
+        davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
+    } else {
+        l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
+        l &= ~mask;
+        davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
+    }
 }
 
 /**
@@ -213,20 +213,20 @@ void rt_hw_interrupt_mask(int irq)
  */
 void rt_hw_interrupt_umask(int irq)
 {
-	unsigned int mask;
-	rt_uint32_t l;
-
-	mask = 1 << IRQ_BIT(irq);
-
-	if (irq > 31) {
-		l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
-		l |= mask;
-		davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
-	} else {
-		l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
-		l |= mask;
-		davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
-	}
+    unsigned int mask;
+    rt_uint32_t l;
+
+    mask = 1 << IRQ_BIT(irq);
+
+    if (irq > 31) {
+        l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
+        l |= mask;
+        davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
+    } else {
+        l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
+        l |= mask;
+        davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
+    }
 }
 
 /**
@@ -239,25 +239,25 @@ void rt_hw_interrupt_umask(int irq)
  */
 
 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-									void *param, const char *name)
+                                    void *param, const char *name)
 {
-	rt_isr_handler_t old_handler = RT_NULL;
-
-	if(vector < MAX_HANDLERS)
-	{
-		old_handler = irq_desc[vector].handler;
-		if (handler != RT_NULL)
-		{
-			irq_desc[vector].handler = (rt_isr_handler_t)handler;
-			irq_desc[vector].param = param;
-		#ifdef RT_USING_INTERRUPT_INFO
-			rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
-			irq_desc[vector].counter = 0;
-		#endif
-		}
-	}
-
-	return old_handler;
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if(vector < MAX_HANDLERS)
+    {
+        old_handler = irq_desc[vector].handler;
+        if (handler != RT_NULL)
+        {
+            irq_desc[vector].handler = (rt_isr_handler_t)handler;
+            irq_desc[vector].param = param;
+        #ifdef RT_USING_INTERRUPT_INFO
+            rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
+            irq_desc[vector].counter = 0;
+        #endif
+        }
+    }
+
+    return old_handler;
 
 }
 
@@ -265,16 +265,16 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
 #ifdef RT_USING_INTERRUPT_INFO
 void list_irq(void)
 {
-	int irq;
-	
-	rt_kprintf("number\tcount\tname\n");
-	for (irq = 0; irq < MAX_HANDLERS; irq++)
-	{
-		if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
-		{
-			rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
-		}
-	}
+    int irq;
+
+    rt_kprintf("number\tcount\tname\n");
+    for (irq = 0; irq < MAX_HANDLERS; irq++)
+    {
+        if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
+        {
+            rt_kprintf("%02ld: %10ld  %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
+        }
+    }
 }
 
 #include <finsh.h>

bsp/dm365/platform/irqs.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __DM36X_IRQS_H__
@@ -18,7 +18,7 @@ extern "C" {
 /* Base address */
 #define DAVINCI_ARM_INTC_BASE 0x01C48000
 
-#define DAVINCI_N_AINTC_IRQ	64
+#define DAVINCI_N_AINTC_IRQ 64
 
 /* Interrupt lines */
 #define IRQ_VDINT0       0
@@ -88,100 +88,100 @@ extern "C" {
 /*
  * Base Interrupts common across DM355 and DM365
  */
-#define IRQ_DM3XX_VPSSINT0	0
-#define IRQ_DM3XX_VPSSINT1	1
-#define IRQ_DM3XX_VPSSINT2	2
-#define IRQ_DM3XX_VPSSINT3	3
-#define IRQ_DM3XX_VPSSINT4	4
-#define IRQ_DM3XX_VPSSINT5	5
-#define IRQ_DM3XX_VPSSINT6	6
-#define IRQ_DM3XX_VPSSINT7	7
-#define IRQ_DM3XX_VPSSINT8	8
-#define IRQ_DM3XX_IMCOPINT	11
-#define IRQ_DM3XX_RTOINT	13
-#define IRQ_DM3XX_TINT4		13
-#define IRQ_DM3XX_TINT2_TINT12	13
-#define IRQ_DM3XX_TINT5		14
-#define IRQ_DM3XX_TINT2_TINT34	14
-#define IRQ_DM3XX_TINT6		15
-#define IRQ_DM3XX_TINT3_TINT12	15
-#define IRQ_DM3XX_SPINT1_0	17
-#define IRQ_DM3XX_SPINT1_1	18
-#define IRQ_DM3XX_SPINT2_0	19
-#define IRQ_DM3XX_SPINT2_1	21
-#define IRQ_DM3XX_TINT7		22
-#define IRQ_DM3XX_TINT3_TINT34	22
-#define IRQ_DM3XX_SDIOINT0	23
-#define IRQ_DM3XX_MMCINT0	26
-#define IRQ_DM3XX_MSINT		26
-#define IRQ_DM3XX_MMCINT1	27
-#define IRQ_DM3XX_PWMINT3	28
-#define IRQ_DM3XX_SDIOINT1	31
-#define IRQ_DM3XX_SPINT0_0	42
-#define IRQ_DM3XX_SPINT0_1	43
-#define IRQ_DM3XX_GPIO0		44
-#define IRQ_DM3XX_GPIO1		45
-#define IRQ_DM3XX_GPIO2		46
-#define IRQ_DM3XX_GPIO3		47
-#define IRQ_DM3XX_GPIO4		48
-#define IRQ_DM3XX_GPIO5		49
-#define IRQ_DM3XX_GPIO6		50
-#define IRQ_DM3XX_GPIO7		51
-#define IRQ_DM3XX_GPIO8		52
-#define IRQ_DM3XX_GPIO9		53
+#define IRQ_DM3XX_VPSSINT0  0
+#define IRQ_DM3XX_VPSSINT1  1
+#define IRQ_DM3XX_VPSSINT2  2
+#define IRQ_DM3XX_VPSSINT3  3
+#define IRQ_DM3XX_VPSSINT4  4
+#define IRQ_DM3XX_VPSSINT5  5
+#define IRQ_DM3XX_VPSSINT6  6
+#define IRQ_DM3XX_VPSSINT7  7
+#define IRQ_DM3XX_VPSSINT8  8
+#define IRQ_DM3XX_IMCOPINT  11
+#define IRQ_DM3XX_RTOINT    13
+#define IRQ_DM3XX_TINT4     13
+#define IRQ_DM3XX_TINT2_TINT12  13
+#define IRQ_DM3XX_TINT5     14
+#define IRQ_DM3XX_TINT2_TINT34  14
+#define IRQ_DM3XX_TINT6     15
+#define IRQ_DM3XX_TINT3_TINT12  15
+#define IRQ_DM3XX_SPINT1_0  17
+#define IRQ_DM3XX_SPINT1_1  18
+#define IRQ_DM3XX_SPINT2_0  19
+#define IRQ_DM3XX_SPINT2_1  21
+#define IRQ_DM3XX_TINT7     22
+#define IRQ_DM3XX_TINT3_TINT34  22
+#define IRQ_DM3XX_SDIOINT0  23
+#define IRQ_DM3XX_MMCINT0   26
+#define IRQ_DM3XX_MSINT     26
+#define IRQ_DM3XX_MMCINT1   27
+#define IRQ_DM3XX_PWMINT3   28
+#define IRQ_DM3XX_SDIOINT1  31
+#define IRQ_DM3XX_SPINT0_0  42
+#define IRQ_DM3XX_SPINT0_1  43
+#define IRQ_DM3XX_GPIO0     44
+#define IRQ_DM3XX_GPIO1     45
+#define IRQ_DM3XX_GPIO2     46
+#define IRQ_DM3XX_GPIO3     47
+#define IRQ_DM3XX_GPIO4     48
+#define IRQ_DM3XX_GPIO5     49
+#define IRQ_DM3XX_GPIO6     50
+#define IRQ_DM3XX_GPIO7     51
+#define IRQ_DM3XX_GPIO8     52
+#define IRQ_DM3XX_GPIO9     53
 
 /* DaVinci DM365-specific Interrupts */
-#define IRQ_DM365_INSFINT	7
-#define IRQ_DM365_IMXINT1	8
-#define IRQ_DM365_IMXINT0	10
-#define IRQ_DM365_KLD_ARMINT	10
-#define IRQ_DM365_CCERRINT	17
-#define IRQ_DM365_TCERRINT0	18
-#define IRQ_DM365_SPINT2_0	19
-#define IRQ_DM365_PSCINT	20
-#define IRQ_DM365_TVINT		20
-#define IRQ_DM365_SPINT4_0	21
-#define IRQ_DM365_MBXINT	24
-#define IRQ_DM365_VCINT		24
-#define IRQ_DM365_MBRINT	25
-#define IRQ_DM365_TINT9		28
-#define IRQ_DM365_TINT4_TINT34	28
-#define IRQ_DM365_DDRINT	29
-#define IRQ_DM365_RTCINT	29
-#define IRQ_DM365_AEMIFINT	30
-#define IRQ_DM365_HPIINT	30
-#define IRQ_DM365_TINT0		32
-#define IRQ_DM365_TINT0_TINT12	32
-#define IRQ_DM365_TINT1		33
-#define IRQ_DM365_TINT0_TINT34	33
-#define IRQ_DM365_TINT2		34
-#define IRQ_DM365_TINT1_TINT12	34
-#define IRQ_DM365_TINT3		35
-#define IRQ_DM365_TINT1_TINT34	35
-#define IRQ_DM365_PWMINT2	38
-#define IRQ_DM365_TINT8		38
-#define IRQ_DM365_TINT4_TINT12	38
-#define IRQ_DM365_IICINT	39
-#define IRQ_DM365_SPINT3_0	43
-#define IRQ_DM365_EMAC_RXTHRESH	52
-#define IRQ_DM365_EMAC_RXPULSE	53
-#define IRQ_DM365_GPIO10	54
-#define IRQ_DM365_EMAC_TXPULSE	54
-#define IRQ_DM365_GPIO11	55
+#define IRQ_DM365_INSFINT   7
+#define IRQ_DM365_IMXINT1   8
+#define IRQ_DM365_IMXINT0   10
+#define IRQ_DM365_KLD_ARMINT    10
+#define IRQ_DM365_CCERRINT  17
+#define IRQ_DM365_TCERRINT0 18
+#define IRQ_DM365_SPINT2_0  19
+#define IRQ_DM365_PSCINT    20
+#define IRQ_DM365_TVINT     20
+#define IRQ_DM365_SPINT4_0  21
+#define IRQ_DM365_MBXINT    24
+#define IRQ_DM365_VCINT     24
+#define IRQ_DM365_MBRINT    25
+#define IRQ_DM365_TINT9     28
+#define IRQ_DM365_TINT4_TINT34  28
+#define IRQ_DM365_DDRINT    29
+#define IRQ_DM365_RTCINT    29
+#define IRQ_DM365_AEMIFINT  30
+#define IRQ_DM365_HPIINT    30
+#define IRQ_DM365_TINT0     32
+#define IRQ_DM365_TINT0_TINT12  32
+#define IRQ_DM365_TINT1     33
+#define IRQ_DM365_TINT0_TINT34  33
+#define IRQ_DM365_TINT2     34
+#define IRQ_DM365_TINT1_TINT12  34
+#define IRQ_DM365_TINT3     35
+#define IRQ_DM365_TINT1_TINT34  35
+#define IRQ_DM365_PWMINT2   38
+#define IRQ_DM365_TINT8     38
+#define IRQ_DM365_TINT4_TINT12  38
+#define IRQ_DM365_IICINT    39
+#define IRQ_DM365_SPINT3_0  43
+#define IRQ_DM365_EMAC_RXTHRESH 52
+#define IRQ_DM365_EMAC_RXPULSE  53
+#define IRQ_DM365_GPIO10    54
+#define IRQ_DM365_EMAC_TXPULSE  54
+#define IRQ_DM365_GPIO11    55
 #define IRQ_DM365_EMAC_MISCPULSE 55
-#define IRQ_DM365_GPIO12	56
-#define IRQ_DM365_PWRGIO0	56
-#define IRQ_DM365_GPIO13	57
-#define IRQ_DM365_PWRGIO1	57
-#define IRQ_DM365_GPIO14	58
-#define IRQ_DM365_PWRGIO2	58
-#define IRQ_DM365_GPIO15	59
-#define IRQ_DM365_ADCINT	59
-#define IRQ_DM365_KEYINT	60
-#define IRQ_DM365_COMMTX	61
-#define IRQ_DM365_TCERRINT2	61
-#define IRQ_DM365_COMMRX	62
-#define IRQ_DM365_TCERRINT3	62
+#define IRQ_DM365_GPIO12    56
+#define IRQ_DM365_PWRGIO0   56
+#define IRQ_DM365_GPIO13    57
+#define IRQ_DM365_PWRGIO1   57
+#define IRQ_DM365_GPIO14    58
+#define IRQ_DM365_PWRGIO2   58
+#define IRQ_DM365_GPIO15    59
+#define IRQ_DM365_ADCINT    59
+#define IRQ_DM365_KEYINT    60
+#define IRQ_DM365_COMMTX    61
+#define IRQ_DM365_TCERRINT2 61
+#define IRQ_DM365_COMMRX    62
+#define IRQ_DM365_TCERRINT3 62
 
 
 #ifdef __cplusplus

bsp/dm365/platform/psc.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #include "dm36x.h"
@@ -19,13 +19,13 @@
  * ------------------------------------------------------------------------ */
 void psc_change_state(int id, int state)
 {
-	rt_uint32_t mdstat, mdctl;
+    rt_uint32_t mdstat, mdctl;
 
-	if (id > DAVINCI_DM365_LPSC_KALEIDO)
-		return;
+    if (id > DAVINCI_DM365_LPSC_KALEIDO)
+        return;
 
-	mdstat = PSC_MDSTAT_BASE + (id * 4);
-	mdctl = PSC_MDCTL_BASE + (id * 4);
+    mdstat = PSC_MDSTAT_BASE + (id * 4);
+    mdctl = PSC_MDCTL_BASE + (id * 4);
 
     /*
      *  Step 0 - Ignore request if the state is already set as is

bsp/dm365/platform/psc.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 #ifndef __DM36X_PSC_H
@@ -17,69 +17,69 @@ extern "C" {
 
 
 /* PSC register offsets */
-#define EPCPR		0x070
-#define PTCMD		0x120
-#define PTSTAT		0x128
-#define PDSTAT		0x200
-#define PDCTL1		0x304
-#define MDSTAT(n)	(0x800 + (n) * 4)
-#define MDCTL(n)	(0xA00 + (n) * 4)
+#define EPCPR       0x070
+#define PTCMD       0x120
+#define PTSTAT      0x128
+#define PDSTAT      0x200
+#define PDCTL1      0x304
+#define MDSTAT(n)   (0x800 + (n) * 4)
+#define MDCTL(n)    (0xA00 + (n) * 4)
 
 /* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN		0
-#define DAVINCI_GPSC_DSPDOMAIN		1
+#define DAVINCI_GPSC_ARMDOMAIN      0
+#define DAVINCI_GPSC_DSPDOMAIN      1
 
 
-#define DAVINCI_DM365_LPSC_TPCC		0
-#define DAVINCI_DM365_LPSC_TPTC0	1
-#define DAVINCI_DM365_LPSC_TPTC1	2
-#define DAVINCI_DM365_LPSC_TPTC2	3
-#define DAVINCI_DM365_LPSC_TPTC3	4
-#define DAVINCI_DM365_LPSC_TIMER3	5
-#define DAVINCI_DM365_LPSC_SPI1		6
-#define DAVINCI_DM365_LPSC_MMC_SD1	7
-#define DAVINCI_DM365_LPSC_McBSP	8
-#define DAVINCI_DM365_LPSC_USB		9
-#define DAVINCI_DM365_LPSC_PWM3		10
-#define DAVINCI_DM365_LPSC_SPI2		11
-#define DAVINCI_DM365_LPSC_RTO		12
-#define DAVINCI_DM365_LPSC_DDR_EMIF	13
-#define DAVINCI_DM365_LPSC_AEMIF	14
-#define DAVINCI_DM365_LPSC_MMC_SD	15
-#define DAVINCI_DM365_LPSC_MMC_SD0	15
-#define DAVINCI_DM365_LPSC_MEMSTICK	16
-#define DAVINCI_DM365_LPSC_TIMER4	17
-#define DAVINCI_DM365_LPSC_I2C		18
-#define DAVINCI_DM365_LPSC_UART0	19
-#define DAVINCI_DM365_LPSC_UART1	20
-#define DAVINCI_DM365_LPSC_UHPI		21
-#define DAVINCI_DM365_LPSC_SPI0		22
-#define DAVINCI_DM365_LPSC_PWM0		23
-#define DAVINCI_DM365_LPSC_PWM1		24
-#define DAVINCI_DM365_LPSC_PWM2		25
-#define DAVINCI_DM365_LPSC_GPIO		26
-#define DAVINCI_DM365_LPSC_TIMER0	27
-#define DAVINCI_DM365_LPSC_TIMER1	28
-#define DAVINCI_DM365_LPSC_TIMER2	29
+#define DAVINCI_DM365_LPSC_TPCC     0
+#define DAVINCI_DM365_LPSC_TPTC0    1
+#define DAVINCI_DM365_LPSC_TPTC1    2
+#define DAVINCI_DM365_LPSC_TPTC2    3
+#define DAVINCI_DM365_LPSC_TPTC3    4
+#define DAVINCI_DM365_LPSC_TIMER3   5
+#define DAVINCI_DM365_LPSC_SPI1     6
+#define DAVINCI_DM365_LPSC_MMC_SD1  7
+#define DAVINCI_DM365_LPSC_McBSP    8
+#define DAVINCI_DM365_LPSC_USB      9
+#define DAVINCI_DM365_LPSC_PWM3     10
+#define DAVINCI_DM365_LPSC_SPI2     11
+#define DAVINCI_DM365_LPSC_RTO      12
+#define DAVINCI_DM365_LPSC_DDR_EMIF 13
+#define DAVINCI_DM365_LPSC_AEMIF    14
+#define DAVINCI_DM365_LPSC_MMC_SD   15
+#define DAVINCI_DM365_LPSC_MMC_SD0  15
+#define DAVINCI_DM365_LPSC_MEMSTICK 16
+#define DAVINCI_DM365_LPSC_TIMER4   17
+#define DAVINCI_DM365_LPSC_I2C      18
+#define DAVINCI_DM365_LPSC_UART0    19
+#define DAVINCI_DM365_LPSC_UART1    20
+#define DAVINCI_DM365_LPSC_UHPI     21
+#define DAVINCI_DM365_LPSC_SPI0     22
+#define DAVINCI_DM365_LPSC_PWM0     23
+#define DAVINCI_DM365_LPSC_PWM1     24
+#define DAVINCI_DM365_LPSC_PWM2     25
+#define DAVINCI_DM365_LPSC_GPIO     26
+#define DAVINCI_DM365_LPSC_TIMER0   27
+#define DAVINCI_DM365_LPSC_TIMER1   28
+#define DAVINCI_DM365_LPSC_TIMER2   29
 #define DAVINCI_DM365_LPSC_SYSTEM_SUBSYS 30
-#define DAVINCI_DM365_LPSC_ARM		31
-#define DAVINCI_DM365_LPSC_SCR0		33
-#define DAVINCI_DM365_LPSC_SCR1		34
-#define DAVINCI_DM365_LPSC_EMU		35
-#define DAVINCI_DM365_LPSC_CHIPDFT	36
-#define DAVINCI_DM365_LPSC_PBIST	37
-#define DAVINCI_DM365_LPSC_SPI3		38
-#define DAVINCI_DM365_LPSC_SPI4		39
-#define DAVINCI_DM365_LPSC_CPGMAC	40
-#define DAVINCI_DM365_LPSC_RTC		41
-#define DAVINCI_DM365_LPSC_KEYSCAN	42
-#define DAVINCI_DM365_LPSC_ADCIF	43
-#define DAVINCI_DM365_LPSC_VOICE_CODEC	44
-#define DAVINCI_DM365_LPSC_DAC_CLKRES	45
-#define DAVINCI_DM365_LPSC_DAC_CLK	46
-#define DAVINCI_DM365_LPSC_VPSSMSTR	47
-#define DAVINCI_DM365_LPSC_IMCOP	50
-#define DAVINCI_DM365_LPSC_KALEIDO	51
+#define DAVINCI_DM365_LPSC_ARM      31
+#define DAVINCI_DM365_LPSC_SCR0     33
+#define DAVINCI_DM365_LPSC_SCR1     34
+#define DAVINCI_DM365_LPSC_EMU      35
+#define DAVINCI_DM365_LPSC_CHIPDFT  36
+#define DAVINCI_DM365_LPSC_PBIST    37
+#define DAVINCI_DM365_LPSC_SPI3     38
+#define DAVINCI_DM365_LPSC_SPI4     39
+#define DAVINCI_DM365_LPSC_CPGMAC   40
+#define DAVINCI_DM365_LPSC_RTC      41
+#define DAVINCI_DM365_LPSC_KEYSCAN  42
+#define DAVINCI_DM365_LPSC_ADCIF    43
+#define DAVINCI_DM365_LPSC_VOICE_CODEC  44
+#define DAVINCI_DM365_LPSC_DAC_CLKRES   45
+#define DAVINCI_DM365_LPSC_DAC_CLK  46
+#define DAVINCI_DM365_LPSC_VPSSMSTR 47
+#define DAVINCI_DM365_LPSC_IMCOP    50
+#define DAVINCI_DM365_LPSC_KALEIDO  51
 
 #define PSC_ENABLE     3
 #define PSC_DISABLE    2

bsp/dm365/platform/reset.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -24,7 +24,7 @@
  */
 void machine_reset()
 {
-	reset_system();
+    reset_system();
 }
 
 /**
@@ -44,14 +44,14 @@ FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system);
 #ifdef FINSH_USING_MSH
 int cmd_reset(int argc, char** argv)
 {
-	rt_hw_cpu_reset();
-	return 0;
+    rt_hw_cpu_reset();
+    return 0;
 }
 
 int cmd_shutdown(int argc, char** argv)
 {
-	rt_hw_cpu_shutdown();
-	return 0;
+    rt_hw_cpu_shutdown();
+    return 0;
 }
 
 FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.);

bsp/dm365/platform/system_clock.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -19,6 +19,6 @@ extern int davinci_clk_init(void);
  */
 void rt_hw_clock_init(void)
 {
-	davinci_clk_init();
+    davinci_clk_init();
 }
 

bsp/dm365/platform/trap.c

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2010-11-13     weety		first version
+ * Date           Author        Notes
+ * 2010-11-13     weety     first version
  */
 
 
@@ -32,13 +32,13 @@ extern long list_thread(void);
 
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -51,15 +51,15 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("undefined instruction\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -73,10 +73,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -89,15 +89,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -110,30 +110,30 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
-	rt_uint32_t fault_addr;
-	rt_uint32_t fault_status;
-	asm  volatile ("mrc p15, 0, %0, c6, c0, 0"
-			:
-			:"r"(fault_addr)
-			:"cc");
-	rt_kprintf("unhandler access to 0x%08x\n", fault_addr);
-
-	/* read DFSR */
-	asm volatile ("MRC p15, 0, %0, c5, c0, 0"
-			:
-			:"r"(fault_status)
-			:"cc");
-	rt_kprintf("fault status 0x%08x\n", fault_status);
-
-	rt_hw_show_register(regs);
-
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
+    rt_uint32_t fault_addr;
+    rt_uint32_t fault_status;
+    asm  volatile ("mrc p15, 0, %0, c6, c0, 0"
+            :
+            :"r"(fault_addr)
+            :"cc");
+    rt_kprintf("unhandler access to 0x%08x\n", fault_addr);
+
+    /* read DFSR */
+    asm volatile ("MRC p15, 0, %0, c5, c0, 0"
+            :
+            :"r"(fault_status)
+            :"cc");
+    rt_kprintf("fault status 0x%08x\n", fault_status);
+
+    rt_hw_show_register(regs);
+
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread - %s stack:\n", rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -145,9 +145,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_resv(struct rt_hw_register *regs)
 {
-	rt_kprintf("not used\n");
-	rt_hw_show_register(regs);
-	rt_hw_cpu_shutdown();
+    rt_kprintf("not used\n");
+    rt_hw_show_register(regs);
+    rt_hw_cpu_shutdown();
 }
 
 extern struct rt_irq_desc irq_desc[];
@@ -155,32 +155,32 @@ extern struct rt_irq_desc irq_desc[];
 
 void rt_hw_trap_irq()
 {
-	rt_isr_handler_t isr_func;
-	rt_uint32_t val, irq, mask;
-	void *param;
-
-	/* get irq number */
-	val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24);
-	irq = (val >> 2) - 1;
-	/* clear pending register */
-	mask = 1 << (irq & 0x1f);
-	if (irq > 31)
-		writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1
-	else
-		writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0
-	
-	/* get interrupt service routine */
-	isr_func = irq_desc[irq].handler;
-	param = irq_desc[irq].param;
-
-	/* turn to interrupt service routine */
-	isr_func(irq, param);
-	irq_desc[irq].counter++;
+    rt_isr_handler_t isr_func;
+    rt_uint32_t val, irq, mask;
+    void *param;
+
+    /* get irq number */
+    val = readl(DAVINCI_ARM_INTC_BASE+0x14) - readl(DAVINCI_ARM_INTC_BASE+0x24);
+    irq = (val >> 2) - 1;
+    /* clear pending register */
+    mask = 1 << (irq & 0x1f);
+    if (irq > 31)
+        writel(mask, DAVINCI_ARM_INTC_BASE+0x0c); //IRQ1
+    else
+        writel(mask, DAVINCI_ARM_INTC_BASE+0x08); //IRQ0
+
+    /* get interrupt service routine */
+    isr_func = irq_desc[irq].handler;
+    param = irq_desc[irq].param;
+
+    /* turn to interrupt service routine */
+    isr_func(irq, param);
+    irq_desc[irq].counter++;
 }
 
 void rt_hw_trap_fiq()
 {
-	rt_kprintf("fast interrupt request\n");
+    rt_kprintf("fast interrupt request\n");
 }
 
 /*@}*/

bsp/efm32/application.c

@@ -77,8 +77,8 @@ struct photo_event
 {
     struct rtgui_event_win win;
     rt_uint32_t cmd;
-	rt_uint8_t* path;
-	rt_uint8_t* format;
+    rt_uint8_t* path;
+    rt_uint8_t* format;
 };
 
 /* Private defines -----------------------------------------------------------*/
@@ -95,10 +95,10 @@ volatile rt_uint32_t    rt_system_status = 0;
 #if defined(RT_USING_RTGUI)
 static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *event)
 {
-	rt_bool_t result;
+    rt_bool_t result;
     rt_bool_t load = RT_FALSE;
 
-	result = rtgui_container_event_handler(object, event);
+    result = rtgui_container_event_handler(object, event);
 
     switch(event->type)
     {
@@ -108,27 +108,27 @@ static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *e
 
     case RTGUI_EVENT_MOUSE_BUTTON:
         {
-			struct rtgui_event_mouse *mouse = (struct rtgui_event_mouse *)event;
+            struct rtgui_event_mouse *mouse = (struct rtgui_event_mouse *)event;
 
-			if (mouse->button == RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP)
-			{
+            if (mouse->button == RTGUI_MOUSE_BUTTON_LEFT | RTGUI_MOUSE_BUTTON_UP)
+            {
                 rt_kprintf("APP: left click (%x)\n", mouse->button);
-			}
+            }
         }
         break;
     }
 
     if (load)
-	{
-		struct rtgui_dc* dc;
-		rtgui_rect_t rect;
+    {
+        struct rtgui_dc* dc;
+        rtgui_rect_t rect;
         rtgui_image_t* image;
 
         image = rtgui_image_create_from_file("jpg", "/test9.jpg", RT_FALSE);
 //        image = rtgui_image_create_from_file("bmp", "/test_565.bmp", RT_FALSE);
 
-		dc = rtgui_dc_begin_drawing(RTGUI_WIDGET(object));
-		if (dc == RT_NULL)
+        dc = rtgui_dc_begin_drawing(RTGUI_WIDGET(object));
+        if (dc == RT_NULL)
         {
             return result;
         }
@@ -138,9 +138,9 @@ static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *e
         rect.x1 +=10;
         rect.y1 +=10;
 
-		if (image != RT_NULL)
+        if (image != RT_NULL)
         {
-			rtgui_image_blit(image, dc, &rect);
+            rtgui_image_blit(image, dc, &rect);
             rtgui_image_destroy(image);
         }
         else
@@ -148,10 +148,10 @@ static rt_bool_t pic_view_event_handler(rtgui_object_t *object, rtgui_event_t *e
             rt_kprintf("APP err: no image found!\n");
         }
 
-		rtgui_dc_end_drawing(dc, RT_TRUE);
-	}
+        rtgui_dc_end_drawing(dc, RT_TRUE);
+    }
 
-	return result;
+    return result;
 }
 
 static void app_main(void *parameter)
@@ -169,21 +169,21 @@ static void app_main(void *parameter)
     lcd->control(lcd, RTGRAPHIC_CTRL_GET_INFO, (void *)&lcd_info);
     rt_kprintf("LCD size: %dX%d\n", lcd_info.width, lcd_info.height);
 
-	/* create application */
-	struct rtgui_app *app;
-	app = rtgui_app_create("gui_app");
-	if (app == RT_NULL)
+    /* create application */
+    struct rtgui_app *app;
+    app = rtgui_app_create("gui_app");
+    if (app == RT_NULL)
     {
         rt_kprintf("Create application \"gui_app\" failed!\n");
         return;
     }
 
-	struct rtgui_rect rect1, rect2, rect3;
+    struct rtgui_rect rect1, rect2, rect3;
     struct rtgui_win *win_info, *win_main, *win_hello;
-	struct rtgui_container *container;
+    struct rtgui_container *container;
     struct rtgui_label* label;
 
-	rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1);
+    rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1);
     rect2.x1 = rect1.x1;
     rect2.y1 = 25;
     rect2.x2 = rect1.x2;
@@ -191,106 +191,106 @@ static void app_main(void *parameter)
     rect1.y2 = 25;
 
     /* create info window */
-	win_info = rtgui_win_create(RT_NULL, "info",
+    win_info = rtgui_win_create(RT_NULL, "info",
                     &rect1,
                     RTGUI_WIN_STYLE_NO_BORDER | RTGUI_WIN_STYLE_NO_TITLE);
-	if (win_info == RT_NULL)
-	{
+    if (win_info == RT_NULL)
+    {
         rt_kprintf("Create window \"info\" failed!\n");
-		rtgui_app_destroy(app);
+        rtgui_app_destroy(app);
         return;
-	}
+    }
 
     /* create container in info window */
-	container = rtgui_container_create();
-	if (container == RT_NULL)
-	{
+    container = rtgui_container_create();
+    if (container == RT_NULL)
+    {
         rt_kprintf("Create container failed!\n");
-		return;
-	}
-	rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1);
+        return;
+    }
+    rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1);
     rtgui_container_add_child(RTGUI_CONTAINER(win_info), RTGUI_WIDGET(container));
 
     /* create lable in info window */
-	label = rtgui_label_create("RT-Thread & RTGUI");
+    label = rtgui_label_create("RT-Thread & RTGUI");
     if (label == RT_NULL)
     {
         rt_kprintf("Create lable failed!\n");
         return;
     }
 
-	RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT;
-	RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = red;
+    RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT;
+    RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = red;
     RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = white;
 
-	rect3.x1 = rect1.x1 + 5;
-	rect3.y1 = rect1.y1 + 5;
-	rect3.x2 = rect1.x2 - 5;
-	rect3.y2 = rect1.y2 - 5;
-	rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3);
-	rtgui_container_add_child(container, RTGUI_WIDGET(label));
+    rect3.x1 = rect1.x1 + 5;
+    rect3.y1 = rect1.y1 + 5;
+    rect3.x2 = rect1.x2 - 5;
+    rect3.y2 = rect1.y2 - 5;
+    rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3);
+    rtgui_container_add_child(container, RTGUI_WIDGET(label));
 
 
     /* create main window */
-	win_main = rtgui_win_create(RT_NULL, "main",
+    win_main = rtgui_win_create(RT_NULL, "main",
                     &rect2,
                     RTGUI_WIN_STYLE_NO_BORDER | RTGUI_WIN_STYLE_NO_TITLE);
-	if (win_main == RT_NULL)
-	{
+    if (win_main == RT_NULL)
+    {
         rt_kprintf("Create window \"main\" failed!\n");
-		rtgui_app_destroy(app);
+        rtgui_app_destroy(app);
         return;
-	}
+    }
 
     /* create container in main window */
-	container = rtgui_container_create();
-	if (container == RT_NULL)
-	{
+    container = rtgui_container_create();
+    if (container == RT_NULL)
+    {
         rt_kprintf("Create container failed!\n");
-		return;
-	}
+        return;
+    }
 
-	rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect2);
+    rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect2);
     rtgui_object_set_event_handler(RTGUI_OBJECT(container), pic_view_event_handler);
     rtgui_container_add_child(RTGUI_CONTAINER(win_main), RTGUI_WIDGET(container));
 
     /* create lable in main window */
-	label = rtgui_label_create("EFM32GG_DK3750 Kit");
+    label = rtgui_label_create("EFM32GG_DK3750 Kit");
     if (label == RT_NULL)
     {
         rt_kprintf("Create lable failed!\n");
         return;
     }
-	RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT;
-	RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white;
+    RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT;
+    RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white;
     RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = blue;
 
-	rect3.x1 = rect2.x1 + 5;
-	rect3.y1 = rect2.y1 + 5;
-	rect3.x2 = rect2.x2 - 5;
-	rect3.y2 = rect2.y1 + 20;
-	rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3);
-	rtgui_container_add_child(container, RTGUI_WIDGET(label));
+    rect3.x1 = rect2.x1 + 5;
+    rect3.y1 = rect2.y1 + 5;
+    rect3.x2 = rect2.x2 - 5;
+    rect3.y2 = rect2.y1 + 20;
+    rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect3);
+    rtgui_container_add_child(container, RTGUI_WIDGET(label));
 
 
     /* create hello window */
-	rect3.x1 = 80;
-	rect3.y1 = 50;
-	rect3.x2 = 320 - 80;
-	rect3.y2 = 240 - 50;
-	win_hello = rtgui_win_create(RT_NULL, "hello",
+    rect3.x1 = 80;
+    rect3.y1 = 50;
+    rect3.x2 = 320 - 80;
+    rect3.y2 = 240 - 50;
+    win_hello = rtgui_win_create(RT_NULL, "hello",
                     &rect3,
                     RTGUI_WIN_STYLE_DEFAULT);
-	if (win_hello == RT_NULL)
-	{
+    if (win_hello == RT_NULL)
+    {
         rt_kprintf("Create window \"hello\" failed!\n");
-		rtgui_app_destroy(app);
+        rtgui_app_destroy(app);
         return;
-	}
+    }
 
     /* create a box */
     rtgui_box_t *box = rtgui_box_create(RTGUI_VERTICAL, RT_NULL);
-	if(box == RT_NULL)
+    if(box == RT_NULL)
     {
         rt_kprintf("Create box failed!\n");
         return;
@@ -298,12 +298,12 @@ static void app_main(void *parameter)
 //    rtgui_win_set_box(win_hello, box);
 
     label = rtgui_label_create("哈罗,盹胖!");
-	if(label == RT_NULL)
+    if(label == RT_NULL)
     {
         rt_kprintf("Create lable failed!\n");
         return;
     }
-	RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white;
+    RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white;
     RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = black;
     RTGUI_WIDGET(label)->align = RTGUI_ALIGN_CENTER_HORIZONTAL | RTGUI_ALIGN_CENTER_VERTICAL;
     rtgui_widget_set_miniwidth(RTGUI_WIDGET(label),130);
@@ -322,18 +322,18 @@ static void app_main(void *parameter)
 
 static rt_bool_t photo_view_event_handler(rtgui_object_t *object, rtgui_event_t *event)
 {
-	rt_bool_t result = RT_FALSE;
+    rt_bool_t result = RT_FALSE;
     struct photo_event *photo_event = (struct photo_event *)event;
 
-	result = rtgui_container_event_handler(object, event);
+    result = rtgui_container_event_handler(object, event);
     rt_kprintf("container event %x\n", event->type);
 
-	struct rtgui_event_win* wevent = (struct rtgui_event_win*)event;
+    struct rtgui_event_win* wevent = (struct rtgui_event_win*)event;
     rt_kprintf("wevent->wid %x\n", wevent->wid);
 
     if ((event->type == RTGUI_EVENT_COMMAND) && \
         (photo_event->cmd == APP_CMD_PHOTO_FRAME))
-	{
+    {
         rtgui_rect_t rect;
         rtgui_image_t* image;
         struct rtgui_dc* dc;
@@ -361,25 +361,25 @@ static rt_bool_t photo_view_event_handler(rtgui_object_t *object, rtgui_event_t
         return RT_TRUE;
     }
 
-	return result;
+    return result;
 }
 
 static rt_bool_t photo_lable_event_handler(rtgui_object_t *object, rtgui_event_t *event)
 {
-	rt_bool_t result = RT_FALSE;
+    rt_bool_t result = RT_FALSE;
 
-	result = rtgui_label_event_handler(object, event);
+    result = rtgui_label_event_handler(object, event);
     rt_kprintf("lable event %x\n", event->type);
 
     if (event->type == RTGUI_EVENT_COMMAND)
-	{
+    {
         struct photo_event *photo = (struct photo_event *)event;
 
         rtgui_label_set_text((rtgui_label_t *)object, photo->path);
         rt_kprintf("path %s\n", photo->path);
     }
 
-	return result;
+    return result;
 }
 
 static void app_photo(void *parameter)
@@ -399,64 +399,64 @@ static void app_photo(void *parameter)
     lcd->control(lcd, RTGRAPHIC_CTRL_GET_INFO, (void *)&lcd_info);
     rt_kprintf("LCD size: %dX%d\n", lcd_info.width, lcd_info.height);
 
-	/* create application */
-	struct rtgui_app *app;
-	app = rtgui_app_create("pho_app");
-	if (app == RT_NULL)
+    /* create application */
+    struct rtgui_app *app;
+    app = rtgui_app_create("pho_app");
+    if (app == RT_NULL)
     {
         rt_kprintf("Create application \"pho_app\" failed!\n");
         return;
     }
 
-	struct rtgui_rect rect1, rect2;
+    struct rtgui_rect rect1, rect2;
     struct rtgui_win *window;
-	struct rtgui_container *container;
+    struct rtgui_container *container;
     struct rtgui_label* label;
 
-	rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1);
+    rtgui_graphic_driver_get_rect(rtgui_graphic_driver_get_default(), &rect1);
 
     /* create window */
-	window = rtgui_win_create(RT_NULL, "photo",
+    window = rtgui_win_create(RT_NULL, "photo",
                     &rect1,
                     RTGUI_WIN_STYLE_NO_BORDER | RTGUI_WIN_STYLE_NO_TITLE);
-	if (window == RT_NULL)
-	{
+    if (window == RT_NULL)
+    {
         rt_kprintf("Create window \"photo\" failed!\n");
-		rtgui_app_destroy(app);
+        rtgui_app_destroy(app);
         return;
-	}
+    }
     event->win.wid = window;
 
     /* create container */
-	container = rtgui_container_create();
-	if (container == RT_NULL)
-	{
+    container = rtgui_container_create();
+    if (container == RT_NULL)
+    {
         rt_kprintf("Create container failed!\n");
-		return;
-	}
-	rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1);
+        return;
+    }
+    rtgui_widget_set_rect(RTGUI_WIDGET(container), &rect1);
     rtgui_object_set_event_handler(RTGUI_OBJECT(container), photo_view_event_handler);
     rtgui_container_add_child(RTGUI_CONTAINER(window), RTGUI_WIDGET(container));
 
     /* create lable in info window */
-	label = rtgui_label_create("Photo Frame Demo");
+    label = rtgui_label_create("Photo Frame Demo");
     if (label == RT_NULL)
     {
         rt_kprintf("Create lable failed!\n");
         return;
     }
 
-	RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT;
-	RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white;
+    RTGUI_WIDGET_TEXTALIGN(RTGUI_WIDGET(label)) = RTGUI_ALIGN_LEFT;
+    RTGUI_WIDGET_BACKGROUND(RTGUI_WIDGET(label)) = white;
     RTGUI_WIDGET_FOREGROUND(RTGUI_WIDGET(label)) = blue;
 
     rect2.x1 = rect1.x1;
     rect2.y1 = rect1.y1;
     rect2.x2 = rect1.x2;
     rect2.y2 = 15;
-	rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect2);
+    rtgui_widget_set_rect(RTGUI_WIDGET(label), &rect2);
     rtgui_object_set_event_handler(RTGUI_OBJECT(label), photo_lable_event_handler);
-	rtgui_container_add_child(container, RTGUI_WIDGET(label));
+    rtgui_container_add_child(container, RTGUI_WIDGET(label));
 
     rtgui_win_show(window, RT_FALSE);
 

bsp/efm32/board.c

@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	board.c
- * @brief 	Board support of RT-Thread RTOS for EFM32
+ * @file    board.c
+ * @brief   Board support of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,12 +10,12 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2010-12-21	onelife		Initial creation for EFM32
- * 2011-05-06	onelife		Add EFM32 development kit and SPI Flash support
- * 2011-07-12	onelife		Add SWO output enable function
- * 2011-12-08	onelife		Add giant gecko development kit support
- * 2011-12-09	onelife		Add giant gecko support
+ * Date         Author      Notes
+ * 2010-12-21   onelife     Initial creation for EFM32
+ * 2011-05-06   onelife     Add EFM32 development kit and SPI Flash support
+ * 2011-07-12   onelife     Add SWO output enable function
+ * 2011-12-08   onelife     Add giant gecko development kit support
+ * 2011-12-09   onelife     Add giant gecko support
  * 2011-12-09   onelife     Add LEUART module support
  * 2011-12-14   onelife     Add LFXO enabling routine in driver initialization
  *  function
@@ -37,19 +37,19 @@
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-#define IS_NVIC_VECTTAB(VECTTAB) 		(((VECTTAB) == RAM_MEM_BASE) || \
-										((VECTTAB) == FLASH_MEM_BASE))
-#define IS_NVIC_OFFSET(OFFSET) 			((OFFSET) < 0x000FFFFF)
+#define IS_NVIC_VECTTAB(VECTTAB)        (((VECTTAB) == RAM_MEM_BASE) || \
+                                        ((VECTTAB) == FLASH_MEM_BASE))
+#define IS_NVIC_OFFSET(OFFSET)          ((OFFSET) < 0x000FFFFF)
 
 /***************************************************************************//**
  * @addtogroup SysTick_clock_source
  * @{
  ******************************************************************************/
 #define SysTick_CLKSource_MASK          ((rt_uint32_t)0x00000004)
-#define SysTick_CLKSource_RTC		    ((rt_uint32_t)0x00000000)
-#define SysTick_CLKSource_HFCORECLK		((rt_uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE)	(((SOURCE) == SysTick_CLKSource_RTC) || \
-										((SOURCE) == SysTick_CLKSource_HFCORECLK))
+#define SysTick_CLKSource_RTC           ((rt_uint32_t)0x00000000)
+#define SysTick_CLKSource_HFCORECLK     ((rt_uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE)   (((SOURCE) == SysTick_CLKSource_RTC) || \
+                                        ((SOURCE) == SysTick_CLKSource_HFCORECLK))
 /***************************************************************************//**
  * @}
  ******************************************************************************/
@@ -67,20 +67,20 @@
  * @note
  *
  * @param[in] NVIC_VectTab
- *	 Indicate the vector table is allocated in RAM or ROM
+ *   Indicate the vector table is allocated in RAM or ROM
  *
  * @param[in] Offset
  *   The vector table offset
  ******************************************************************************/
 static void NVIC_SetVectorTable(
-	rt_uint32_t NVIC_VectTab,
-	rt_uint32_t Offset)
+    rt_uint32_t NVIC_VectTab,
+    rt_uint32_t Offset)
 {
-	/* Check the parameters */
-	RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
-	RT_ASSERT(IS_NVIC_OFFSET(Offset));
+    /* Check the parameters */
+    RT_ASSERT(IS_NVIC_VECTTAB(NVIC_VectTab));
+    RT_ASSERT(IS_NVIC_OFFSET(Offset));
 
-	SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
+    SCB->VTOR = NVIC_VectTab | (Offset & (rt_uint32_t)0x1FFFFF80);
 }
 
 /***************************************************************************//**
@@ -95,19 +95,19 @@ static void NVIC_SetVectorTable(
 static void NVIC_Configuration(void)
 {
 #ifdef  VECT_TAB_RAM
-	/* Set the vector table allocated at 0x20000000 */
-	NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
+    /* Set the vector table allocated at 0x20000000 */
+    NVIC_SetVectorTable(RAM_MEM_BASE, 0x0);
 #else  /* VECT_TAB_FLASH  */
-	/* Set the vector table allocated at 0x00000000 */
-	NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
+    /* Set the vector table allocated at 0x00000000 */
+    NVIC_SetVectorTable(FLASH_MEM_BASE, 0x0);
 #endif
 
-	/* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
-	   subpriority */
-	NVIC_SetPriorityGrouping(0x7UL);
+    /* Set NVIC Preemption Priority Bits: 0 bit for pre-emption, 4 bits for
+       subpriority */
+    NVIC_SetPriorityGrouping(0x7UL);
 
-	/* Set Base Priority Mask Register */
-	__set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
+    /* Set Base Priority Mask Register */
+    __set_BASEPRI(EFM32_BASE_PRI_DEFAULT);
 }
 
 /***************************************************************************//**
@@ -119,13 +119,13 @@ static void NVIC_Configuration(void)
  * @note
  *
  * @param[in] SysTick_CLKSource
- *	 Specifies the SysTick clock source.
+ *   Specifies the SysTick clock source.
  *
  * @arg SysTick_CLKSource_HCLK_Div8
- * 	 AHB clock divided by 8 selected as SysTick clock source.
+ *   AHB clock divided by 8 selected as SysTick clock source.
  *
  * @arg SysTick_CLKSource_HCLK
- *	 AHB clock selected as SysTick clock source.
+ *   AHB clock selected as SysTick clock source.
  ******************************************************************************/
 static void SysTick_CLKSourceConfig(rt_uint32_t SysTick_CLKSource)
 {
@@ -184,14 +184,14 @@ static void  SysTick_Configuration(void)
     /* Start LETIMER0 */
     LETIMER_Init(LETIMER0, &letimerInit);
 #else
-	rt_uint32_t 	coreClk;
-	rt_uint32_t 	cnts;
+    rt_uint32_t     coreClk;
+    rt_uint32_t     cnts;
 
-	coreClk = SystemCoreClockGet();
-	cnts = coreClk / RT_TICK_PER_SECOND;
+    coreClk = SystemCoreClockGet();
+    cnts = coreClk / RT_TICK_PER_SECOND;
 
-	SysTick_Config(cnts);
-	SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HFCORECLK);
 #endif
 }
 
@@ -206,9 +206,9 @@ static void  SysTick_Configuration(void)
  ******************************************************************************/
 void Swo_Configuration(void)
 {
-	rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
-	rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
-	rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
+    rt_uint32_t *dwt_ctrl = (rt_uint32_t *) 0xE0001000;
+    rt_uint32_t *tpiu_prescaler = (rt_uint32_t *) 0xE0040010;
+    rt_uint32_t *tpiu_protocol = (rt_uint32_t *) 0xE00400F0;
 
     CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO;
     /* Enable Serial wire output pin */
@@ -258,12 +258,12 @@ void Swo_Configuration(void)
  ******************************************************************************/
 void rt_hw_board_init(void)
 {
-	/* Chip errata */
-	CHIP_Init();
+    /* Chip errata */
+    CHIP_Init();
 
     /* Initialize DVK board register access */
 #if defined(EFM32_GXXX_DK)
-	DVK_init();
+    DVK_init();
 #elif defined(EFM32GG_DK3750)
     DVK_init(DVK_Init_EBI);
 
@@ -272,12 +272,12 @@ void rt_hw_board_init(void)
     DVK_clearInterruptFlags(BC_INTFLAG_MASK);
 #endif
 
-	/* config NVIC Configuration */
-	NVIC_Configuration();
+    /* config NVIC Configuration */
+    NVIC_Configuration();
 
 #if defined(EFM32_USING_HFXO)
-	/* Configure external oscillator */
-	SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
+    /* Configure external oscillator */
+    SystemHFXOClockSet(EFM32_HFXO_FREQUENCY);
 
     /* Switching the CPU clock source to HFXO */
     CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO);
@@ -293,15 +293,15 @@ void rt_hw_board_init(void)
 
 #if defined(EFM32_SWO_ENABLE)
     /* Enable SWO */
-	Swo_Configuration();
+    Swo_Configuration();
 #endif
 
-	/* Enable high frequency peripheral clock */
-	CMU_ClockEnable(cmuClock_HFPER, true);
-	/* Enabling clock to the interface of the low energy modules */
-	CMU_ClockEnable(cmuClock_CORELE, true);
+    /* Enable high frequency peripheral clock */
+    CMU_ClockEnable(cmuClock_HFPER, true);
+    /* Enabling clock to the interface of the low energy modules */
+    CMU_ClockEnable(cmuClock_CORELE, true);
     /* Enable GPIO clock */
-	CMU_ClockEnable(cmuClock_GPIO, true);
+    CMU_ClockEnable(cmuClock_GPIO, true);
 
     /* Configure the SysTick */
     SysTick_Configuration();
@@ -318,8 +318,8 @@ void rt_hw_board_init(void)
  ******************************************************************************/
 void rt_hw_driver_init(void)
 {
-	/* Initialize DMA */
-	rt_hw_dma_init();
+    /* Initialize DMA */
+    rt_hw_dma_init();
 
     /* Select LFXO for specified module (and wait for it to stabilize) */
 #if (!defined(EFM32_USING_LFXO) && defined(RT_USING_RTC))
@@ -331,11 +331,11 @@ void rt_hw_driver_init(void)
 #error "Low frequency clock source is needed for using LEUART"
 #endif
 
-	/* Initialize USART */
+    /* Initialize USART */
 #if (defined(RT_USING_USART0) || defined(RT_USING_USART1) || \
     defined(RT_USING_USART2) || defined(RT_USING_UART0) || \
     defined(RT_USING_UART1))
-	rt_hw_usart_init();
+    rt_hw_usart_init();
 #endif
 
     /* Initialize LEUART */
@@ -343,7 +343,7 @@ void rt_hw_driver_init(void)
     rt_hw_leuart_init();
 #endif
 
-	/* Setup Console */
+    /* Setup Console */
 #if defined(EFM32_GXXX_DK)
     DVK_enablePeripheral(DVK_RS232A);
     DVK_enablePeripheral(DVK_SPI);
@@ -354,31 +354,31 @@ void rt_hw_driver_init(void)
     DVK_enablePeripheral(DVK_RS232_LEUART);
  #endif
 #endif
-	rt_console_set_device(CONSOLE_DEVICE);
+    rt_console_set_device(CONSOLE_DEVICE);
 
-	/* Initialize Timer */
+    /* Initialize Timer */
 #if (defined(RT_USING_TIMER0) || defined(RT_USING_TIMER1) || defined(RT_USING_TIMER2))
-	rt_hw_timer_init();
+    rt_hw_timer_init();
 #endif
 
-	/* Initialize ADC */
+    /* Initialize ADC */
 #if defined(RT_USING_ADC0)
-	rt_hw_adc_init();
+    rt_hw_adc_init();
 #endif
 
-	/* Initialize ACMP */
+    /* Initialize ACMP */
 #if (defined(RT_USING_ACMP0) || defined(RT_USING_ACMP1))
-	rt_hw_acmp_init();
+    rt_hw_acmp_init();
 #endif
 
-	/* Initialize IIC */
+    /* Initialize IIC */
 #if (defined(RT_USING_IIC0) || defined(RT_USING_IIC1))
-	rt_hw_iic_init();
+    rt_hw_iic_init();
 #endif
 
-	/* Initialize RTC */
+    /* Initialize RTC */
 #if defined(RT_USING_RTC)
-	rt_hw_rtc_init();
+    rt_hw_rtc_init();
 #endif
 
     /* Enable SPI access to MicroSD card */

bsp/efm32/board.h

@@ -1,8 +1,8 @@
 /***************************************************************************//**
- * @file 	board.h
- * @brief 	Board support of RT-Thread RTOS for EFM32
+ * @file    board.h
+ * @brief   Board support of RT-Thread RTOS for EFM32
  *  COPYRIGHT (C) 2012, RT-Thread Development Team
- * @author 	onelife
+ * @author  onelife
  * @version 1.0
  *******************************************************************************
  * @section License
@@ -10,18 +10,18 @@
  * LICENSE in this distribution or at http://www.rt-thread.org/license/LICENSE
  *******************************************************************************
  * @section Change Logs
- * Date			Author		Notes
- * 2010-12-21	onelife		Initial creation for EFM32
- * 2011-05-06	onelife		Add EFM32 development kit and SPI Flash support
- * 2011-07-12	onelife		Add prototype for SWO output enable and interrupt
+ * Date         Author      Notes
+ * 2010-12-21   onelife     Initial creation for EFM32
+ * 2011-05-06   onelife     Add EFM32 development kit and SPI Flash support
+ * 2011-07-12   onelife     Add prototype for SWO output enable and interrupt
  *  context check functions
- * 2011-12-08	onelife		Add giant gecko development kit support
- * 2011-12-09	onelife		Add giant gecko support
+ * 2011-12-08   onelife     Add giant gecko development kit support
+ * 2011-12-09   onelife     Add giant gecko support
  * 2011-12-09   onelife     Add LEUART module support
  * 2011-12-14   onelife     Add LFXO enabling routine in driver initialization
  *  function
  * 2011-12-20   onelife     Move SPI Auto-CS setting to "rtconfig.h"
- * 2012-05-15	onelife		Modified to compatible with CMSIS v3
+ * 2012-05-15   onelife     Modified to compatible with CMSIS v3
  ******************************************************************************/
 #ifndef __BOARD_H__
 #define __BOARD_H__
@@ -72,15 +72,15 @@ extern volatile rt_uint32_t rt_system_status;
 #define EFM32_SWO_ENABLE
 #endif
 
-#define EFM32_NO_DATA				(0)
-#define EFM32_NO_POINTER			(RT_NULL)
-#define EFM32_NO_OFFSET				(-1)
-#define EFM32_NO_DMA				(-1)
+#define EFM32_NO_DATA               (0)
+#define EFM32_NO_POINTER            (RT_NULL)
+#define EFM32_NO_OFFSET             (-1)
+#define EFM32_NO_DMA                (-1)
 
 /* SECTION: SPI Flash */
 #if defined(EFM32_USING_SFLASH)
-#define SFLASH_CS_PORT 				(gpioPortC)
-#define SFLASH_CS_PIN 				(8)
+#define SFLASH_CS_PORT              (gpioPortC)
+#define SFLASH_CS_PIN               (8)
 #endif
 
 /* SECTION: Micro SD */
@@ -114,9 +114,9 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SECTION: SYSTEM */
-#define EFM32_SRAM_END 				(SRAM_BASE + SRAM_SIZE)
-#define EFM32_BASE_PRI_DEFAULT 		(0x0UL << 5)
-#define EFM32_IRQ_PRI_DEFAULT 		(0x4UL << 5)
+#define EFM32_SRAM_END              (SRAM_BASE + SRAM_SIZE)
+#define EFM32_BASE_PRI_DEFAULT      (0x0UL << 5)
+#define EFM32_IRQ_PRI_DEFAULT       (0x4UL << 5)
 
 /* SECTION: CLOCK */
 #define EFM32_USING_HFXO
@@ -125,9 +125,9 @@ extern volatile rt_uint32_t rt_system_status;
  #if (defined(EFM32_G8XX_STK) || defined(EFM32_GXXX_DK))
  #define EFM32_HFXO_FREQUENCY       (32000000)
  #elif defined(EFM32GG_DK3750)
- #define EFM32_HFXO_FREQUENCY 		(48000000)
+ #define EFM32_HFXO_FREQUENCY       (48000000)
  #else
- #define EFM32_HFXO_FREQUENCY		(00000000)
+ #define EFM32_HFXO_FREQUENCY       (00000000)
  #endif
 #endif
 #if defined(EFM32_USING_LFXO)
@@ -141,8 +141,8 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SECTION: USART */
-#define USART_RX_BUFFER_SIZE		(64)
-#define LEUART_RX_BUFFER_SIZE		(64)
+#define USART_RX_BUFFER_SIZE        (64)
+#define LEUART_RX_BUFFER_SIZE       (64)
 /* Location count (start from 0) */
 #if defined(_EFM32_GECKO_FAMILY)
 #define EFM32_USART_LOCATION_COUNT  (3)
@@ -155,14 +155,14 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SUBSECTION: UART */
-#define UART_BAUDRATE				(115200)
+#define UART_BAUDRATE               (115200)
 
 /* SUBSECTION: SPI */
 /* Max SPI clock: HFPERCLK/2 for master, HFPERCLK/8 for slave */
-#define SPI_BAUDRATE				(4000000)
+#define SPI_BAUDRATE                (4000000)
 
 /* SECTION: I2C */
-#define IIC_RX_BUFFER_SIZE			(32)
+#define IIC_RX_BUFFER_SIZE          (32)
 #if defined(_EFM32_GECKO_FAMILY)
 #define EFM32_IIC_LOCATION_COUNT    (4)
 #elif defined(_EFM32_GIANT_FAMILY)
@@ -170,61 +170,61 @@ extern volatile rt_uint32_t rt_system_status;
 #endif
 
 /* SECTION: ADC */
-#define ADC_CALI_REF				(adcRef2V5)
-#define ADC_CALI_CH 				(adcSingleInpCh5)
-#define ADC_CONVERT_FREQUENCY 		(7000000)
+#define ADC_CALI_REF                (adcRef2V5)
+#define ADC_CALI_CH                 (adcSingleInpCh5)
+#define ADC_CONVERT_FREQUENCY       (7000000)
 
 #if (RT_CONSOLE_DEVICE == EFM_USART0)
-#define CONSOLE_DEVICE 				RT_USART0_NAME
+#define CONSOLE_DEVICE              RT_USART0_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_USART1)
-#define CONSOLE_DEVICE 				RT_USART1_NAME
+#define CONSOLE_DEVICE              RT_USART1_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_USART2)
-#define CONSOLE_DEVICE 				RT_USART2_NAME
+#define CONSOLE_DEVICE              RT_USART2_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_UART0)
-#define CONSOLE_DEVICE 				RT_UART0_NAME
+#define CONSOLE_DEVICE              RT_UART0_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_UART1)
-#define CONSOLE_DEVICE 				RT_UART1_NAME
+#define CONSOLE_DEVICE              RT_UART1_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_LEUART0)
-#define CONSOLE_DEVICE 				RT_LEUART0_NAME
+#define CONSOLE_DEVICE              RT_LEUART0_NAME
 #elif (RT_CONSOLE_DEVICE == EFM_LEUART1)
-#define CONSOLE_DEVICE 				RT_LEUART1_NAME
+#define CONSOLE_DEVICE              RT_LEUART1_NAME
 #else
-#define CONSOLE_DEVICE 				"NONE"
+#define CONSOLE_DEVICE              "NONE"
 #endif
 
 
 /* The following defines should be consistent with those in diskio.h */
-#define CTRL_SYNC						0
-#define GET_SECTOR_COUNT				1
-#define GET_SECTOR_SIZE					2
-#define GET_BLOCK_SIZE					3
-#define MMC_GET_TYPE					10
-#define MMC_GET_CSD						11
-#define MMC_GET_CID						12
-#define MMC_GET_OCR						13
-#define MMC_GET_SDSTAT					14
+#define CTRL_SYNC                       0
+#define GET_SECTOR_COUNT                1
+#define GET_SECTOR_SIZE                 2
+#define GET_BLOCK_SIZE                  3
+#define MMC_GET_TYPE                    10
+#define MMC_GET_CSD                     11
+#define MMC_GET_CID                     12
+#define MMC_GET_OCR                     13
+#define MMC_GET_SDSTAT                  14
 /* The above defines should be consistent with those in diskio.h */
 
 /* I/O control options */
-#define RT_DEVICE_CTRL_SD_SYNC 			CTRL_SYNC
-#define RT_DEVICE_CTRL_SD_GET_SCOUNT 	GET_SECTOR_COUNT
-#define RT_DEVICE_CTRL_SD_GET_SSIZE		GET_SECTOR_SIZE
-#define RT_DEVICE_CTRL_SD_GET_BSIZE 	GET_BLOCK_SIZE
-#define RT_DEVICE_CTRL_SD_GET_TYPE 		MMC_GET_TYPE
-#define RT_DEVICE_CTRL_SD_GET_CSD		MMC_GET_CSD
-#define RT_DEVICE_CTRL_SD_GET_CID 		MMC_GET_CID
-#define RT_DEVICE_CTRL_SD_GET_OCR 		MMC_GET_OCR
-#define RT_DEVICE_CTRL_SD_GET_SDSTAT	MMC_GET_SDSTAT
+#define RT_DEVICE_CTRL_SD_SYNC          CTRL_SYNC
+#define RT_DEVICE_CTRL_SD_GET_SCOUNT    GET_SECTOR_COUNT
+#define RT_DEVICE_CTRL_SD_GET_SSIZE     GET_SECTOR_SIZE
+#define RT_DEVICE_CTRL_SD_GET_BSIZE     GET_BLOCK_SIZE
+#define RT_DEVICE_CTRL_SD_GET_TYPE      MMC_GET_TYPE
+#define RT_DEVICE_CTRL_SD_GET_CSD       MMC_GET_CSD
+#define RT_DEVICE_CTRL_SD_GET_CID       MMC_GET_CID
+#define RT_DEVICE_CTRL_SD_GET_OCR       MMC_GET_OCR
+#define RT_DEVICE_CTRL_SD_GET_SDSTAT    MMC_GET_SDSTAT
 
 /*! fixme: move the following define to Rtdef.h */
-#define RT_DEVICE_CTRL_USART_RBUFFER	(0xF1)		/*!< set USART/UART rx buffer */
-#define RT_DEVICE_CTRL_LEUART_RBUFFER	(0xF2)		/*!< set LEUART rx buffer */
-#define RT_DEVICE_CTRL_IIC_SETTING		(0xF3)		/*!< change IIC setting */
-#define RT_DEVICE_CTRL_TIMER_PERIOD		(0xF4)		/*!< set Timer timeout period */
-#define RT_DEVICE_CTRL_ADC_MODE			(0xF5)		/*!< change ADC mode */
-#define RT_DEVICE_CTRL_ADC_RESULT		(0xF6)		/*!< get ADC result */
-#define RT_DEVICE_CTRL_ACMP_INIT		(0xF7)		/*!< Initialize ACMP */
-#define RT_DEVICE_CTRL_ACMP_OUTPUT		(0xF8)		/*!< get ACMP output */
+#define RT_DEVICE_CTRL_USART_RBUFFER    (0xF1)      /*!< set USART/UART rx buffer */
+#define RT_DEVICE_CTRL_LEUART_RBUFFER   (0xF2)      /*!< set LEUART rx buffer */
+#define RT_DEVICE_CTRL_IIC_SETTING      (0xF3)      /*!< change IIC setting */
+#define RT_DEVICE_CTRL_TIMER_PERIOD     (0xF4)      /*!< set Timer timeout period */
+#define RT_DEVICE_CTRL_ADC_MODE         (0xF5)      /*!< change ADC mode */
+#define RT_DEVICE_CTRL_ADC_RESULT       (0xF6)      /*!< get ADC result */
+#define RT_DEVICE_CTRL_ACMP_INIT        (0xF7)      /*!< Initialize ACMP */
+#define RT_DEVICE_CTRL_ACMP_OUTPUT      (0xF8)      /*!< get ACMP output */
 
 /* Exported functions ------------------------------------------------------- */
 void rt_hw_board_init(void);