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@@ -84,7 +84,11 @@
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#define CM_PER(base) ((base) + 0)
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#define CM_PER_L4LS_CLKSTCTRL(base) (CM_PER(base) + 0)
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-#define CM_PER_UART1_CLKCTRL(base) (CM_PER(base) + 0x06C)
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+#define CM_PER_UART1_CLKCTRL(base) (CM_PER(base) + 0x6C)
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+#define CM_PER_UART2_CLKCTRL(base) (CM_PER(base) + 0x70)
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+#define CM_PER_UART3_CLKCTRL(base) (CM_PER(base) + 0x74)
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+#define CM_PER_UART4_CLKCTRL(base) (CM_PER(base) + 0x78)
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+#define CM_PER_UART5_CLKCTRL(base) (CM_PER(base) + 0x38)
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#define CM_WKUP(base) ((base) + 0x400)
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#define CM_DPLL(base) ((base) + 0x500)
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#define CM_MPU(base) ((base) + 0x600)
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@@ -171,6 +175,10 @@
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/* PRCM registers */
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#define CM_PER_L4LS_CLKSTCTRL_REG(base) REG32((base) + 0x0)
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#define CM_PER_UART1_CLKCTRL_REG(base) REG32(CM_PER_UART1_CLKCTRL(base))
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+#define CM_PER_UART2_CLKCTRL_REG(base) REG32(CM_PER_UART2_CLKCTRL(base))
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+#define CM_PER_UART3_CLKCTRL_REG(base) REG32(CM_PER_UART3_CLKCTRL(base))
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+#define CM_PER_UART4_CLKCTRL_REG(base) REG32(CM_PER_UART4_CLKCTRL(base))
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+#define CM_PER_UART5_CLKCTRL_REG(base) REG32(CM_PER_UART5_CLKCTRL(base))
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#define CM_PER_TIMER7_CLKCTRL(base) REG32((base) + 0x7C)
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#define CM_PER_TIMER2_CLKCTRL(base) REG32((base) + 0x80)
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RTsien