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@@ -19,6 +19,7 @@
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#include "raspi4.h"
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#include "drv_eth.h"
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+
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#define DBG_LEVEL DBG_LOG
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#include <rtdbg.h>
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#define LOG_TAG "drv.eth"
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@@ -26,12 +27,14 @@
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static int link_speed = 0;
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static int link_flag = 0;
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-#define RECV_CACHE_BUF (2048)
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-#define SEND_CACHE_BUF (2048)
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-#define DMA_DISC_ADDR_SIZE (2 * 1024 *1024)
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+#define RECV_CACHE_BUF (1024)
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+#define SEND_CACHE_BUF (1024)
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+#define SEND_DATA_NO_CACHE (0x08200000)
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+#define RECV_DATA_NO_CACHE (0x08400000)
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+#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024)
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-#define RX_DESC_BASE (mac_reg_base_addr + GENET_RX_OFF)
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-#define TX_DESC_BASE (mac_reg_base_addr + GENET_TX_OFF)
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+#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF)
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+#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF)
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#define MAX_ADDR_LEN (6)
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@@ -45,11 +48,11 @@ static rt_thread_t link_thread_tid = RT_NULL;
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#define LINK_THREAD_PRIORITY (20)
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#define LINK_THREAD_TIMESLICE (10)
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-
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static rt_uint32_t tx_index = 0;
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static rt_uint32_t rx_index = 0;
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static rt_uint32_t index_flag = 0;
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+static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF];
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struct rt_eth_dev
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{
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@@ -60,12 +63,11 @@ struct rt_eth_dev
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int state;
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int index;
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struct rt_timer link_timer;
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+ struct rt_timer rx_poll_timer;
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void *priv;
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};
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static struct rt_eth_dev eth_dev;
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-
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-static struct rt_semaphore send_finsh_sem_lock;
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-
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+static struct rt_semaphore sem_lock;
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static struct rt_semaphore link_ack;
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static inline rt_uint32_t read32(void *addr)
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@@ -78,18 +80,12 @@ static inline void write32(void *addr, rt_uint32_t value)
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(*((volatile unsigned int*)(addr))) = value;
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}
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-
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-
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-
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static void eth_rx_irq(int irq, void *param)
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{
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rt_uint32_t val = 0;
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-
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- val = read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT);
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- val &= ~read32(mac_reg_base_addr + GENET_INTRL2_CPU_STAT_MASK);
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-
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- write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR, val);
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-
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+ val = read32(MAC_REG + GENET_INTRL2_CPU_STAT);
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+ val &= ~read32(MAC_REG + GENET_INTRL2_CPU_STAT_MASK);
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+ write32(MAC_REG + GENET_INTRL2_CPU_CLEAR, val);
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if (val & GENET_IRQ_RXDMA_DONE)
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{
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eth_device_ready(ð_dev.parent);
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@@ -97,7 +93,7 @@ static void eth_rx_irq(int irq, void *param)
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if (val & GENET_IRQ_TXDMA_DONE)
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{
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- rt_sem_release(&send_finsh_sem_lock);
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+ rt_sem_release(&sem_lock);
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}
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}
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@@ -109,11 +105,10 @@ static int bcmgenet_interface_set(void)
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{
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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- write32(mac_reg_base_addr + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
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+ write32(MAC_REG + SYS_PORT_CTRL, PORT_MODE_EXT_GPHY);
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break;
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-
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default:
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- rt_kprintf("unknown phy mode: %d\n", mac_reg_base_addr);
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+ rt_kprintf("unknown phy mode: %d\n", MAC_REG);
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return -1;
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}
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return 0;
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@@ -122,48 +117,44 @@ static int bcmgenet_interface_set(void)
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static void bcmgenet_umac_reset(void)
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{
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rt_uint32_t reg;
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- reg = read32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL);
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+ reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL);
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reg |= BIT(1);
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- write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg);
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+ write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
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reg &= ~BIT(1);
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- write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), reg);
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+ write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
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DELAY_MICROS(10);
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-
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- write32((mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL), 0);
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+ write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), 0);
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DELAY_MICROS(10);
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-
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- write32(mac_reg_base_addr + UMAC_CMD, 0);
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- write32(mac_reg_base_addr + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
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+ write32(MAC_REG + UMAC_CMD, 0);
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+ write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
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DELAY_MICROS(2);
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-
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- write32(mac_reg_base_addr + UMAC_CMD, 0);
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+ write32(MAC_REG + UMAC_CMD, 0);
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/* clear tx/rx counter */
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- write32(mac_reg_base_addr + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
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- write32(mac_reg_base_addr + UMAC_MIB_CTRL, 0);
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- write32(mac_reg_base_addr + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
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-
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+ write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
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+ write32(MAC_REG + UMAC_MIB_CTRL, 0);
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+ write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
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/* init rx registers, enable ip header optimization */
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- reg = read32(mac_reg_base_addr + RBUF_CTRL);
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+ reg = read32(MAC_REG + RBUF_CTRL);
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reg |= RBUF_ALIGN_2B;
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- write32(mac_reg_base_addr + RBUF_CTRL, reg);
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- write32(mac_reg_base_addr + RBUF_TBUF_SIZE_CTRL, 1);
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+ write32(MAC_REG + RBUF_CTRL, reg);
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+ write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1);
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}
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static void bcmgenet_disable_dma(void)
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{
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rt_uint32_t tdma_reg = 0, rdma_reg = 0;
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- tdma_reg = read32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL);
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+ tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL);
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tdma_reg &= ~(1UL << DMA_EN);
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- write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
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- rdma_reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL);
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+ write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
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+ rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
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rdma_reg &= ~(1UL << DMA_EN);
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- write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
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- write32(mac_reg_base_addr + UMAC_TX_FLUSH, 1);
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+ write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
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+ write32(MAC_REG + UMAC_TX_FLUSH, 1);
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DELAY_MICROS(100);
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- write32(mac_reg_base_addr + UMAC_TX_FLUSH, 0);
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+ write32(MAC_REG + UMAC_TX_FLUSH, 0);
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}
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static void bcmgenet_enable_dma(void)
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@@ -172,10 +163,10 @@ static void bcmgenet_enable_dma(void)
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rt_uint32_t dma_ctrl = 0;
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dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
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- write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
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+ write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
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- reg = read32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL);
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- write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
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+ reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
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+ write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
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}
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static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value)
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@@ -183,16 +174,16 @@ static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t va
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int count = 10000;
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rt_uint32_t val;
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val = MDIO_WR | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT) | (0xffff & value);
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- write32(mac_reg_base_addr + MDIO_CMD, val);
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+ write32(MAC_REG + MDIO_CMD, val);
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- rt_uint32_t reg_val = read32(mac_reg_base_addr + MDIO_CMD);
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+ rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD);
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reg_val = reg_val | MDIO_START_BUSY;
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- write32(mac_reg_base_addr + MDIO_CMD, reg_val);
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+ write32(MAC_REG + MDIO_CMD, reg_val);
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- while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count))
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+ while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
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DELAY_MICROS(1);
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- reg_val = read32(mac_reg_base_addr + MDIO_CMD);
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+ reg_val = read32(MAC_REG + MDIO_CMD);
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return reg_val & 0xffff;
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}
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@@ -204,31 +195,32 @@ static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
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rt_uint32_t reg_val = 0;
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val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
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- write32(mac_reg_base_addr + MDIO_CMD, val);
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+ write32(MAC_REG + MDIO_CMD, val);
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- reg_val = read32(mac_reg_base_addr + MDIO_CMD);
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+ reg_val = read32(MAC_REG + MDIO_CMD);
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reg_val = reg_val | MDIO_START_BUSY;
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- write32(mac_reg_base_addr + MDIO_CMD, reg_val);
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+ write32(MAC_REG + MDIO_CMD, reg_val);
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- while ((read32(mac_reg_base_addr + MDIO_CMD) & MDIO_START_BUSY) && (--count))
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+ while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
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DELAY_MICROS(1);
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- reg_val = read32(mac_reg_base_addr + MDIO_CMD);
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+ reg_val = read32(MAC_REG + MDIO_CMD);
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return reg_val & 0xffff;
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}
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static int bcmgenet_gmac_write_hwaddr(void)
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{
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+ //{0xdc,0xa6,0x32,0x28,0x22,0x50};
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rt_uint8_t addr[6];
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rt_uint32_t reg;
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bcm271x_mbox_hardware_get_mac_address(&addr[0]);
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reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
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- write32(mac_reg_base_addr + UMAC_MAC0, reg);
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+ write32(MAC_REG + UMAC_MAC0, reg);
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reg = addr[4] << 8 | addr[5];
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- write32(mac_reg_base_addr + UMAC_MAC1, reg);
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+ write32(MAC_REG + UMAC_MAC1, reg);
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return 0;
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}
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@@ -254,8 +246,10 @@ static void bcmgenet_mdio_init(void)
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rt_uint32_t ret = 0;
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/*get ethernet uid*/
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ret = get_ethernet_uid();
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- if (ret == 0) return;
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-
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+ if (ret == 0)
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+ {
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+ return;
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+ }
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/* reset phy */
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bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET);
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/* read control reg */
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@@ -282,34 +276,34 @@ static void bcmgenet_mdio_init(void)
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static void rx_ring_init(void)
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{
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- write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
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- write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
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- write32(mac_reg_base_addr + RDMA_READ_PTR, 0x0);
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- write32(mac_reg_base_addr + RDMA_WRITE_PTR, 0x0);
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- write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
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-
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- write32(mac_reg_base_addr + RDMA_PROD_INDEX, 0x0);
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- write32(mac_reg_base_addr + RDMA_CONS_INDEX, 0x0);
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- write32(mac_reg_base_addr + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
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- write32(mac_reg_base_addr + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
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- write32(mac_reg_base_addr + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
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+ write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
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+ write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
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+ write32(MAC_REG + RDMA_READ_PTR, 0x0);
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+ write32(MAC_REG + RDMA_WRITE_PTR, 0x0);
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+ write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
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+
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+ write32(MAC_REG + RDMA_PROD_INDEX, 0x0);
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+ write32(MAC_REG + RDMA_CONS_INDEX, 0x0);
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+ write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
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+ write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
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+ write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
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}
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static void tx_ring_init(void)
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{
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- write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
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- write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
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- write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
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- write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
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- write32(mac_reg_base_addr + TDMA_READ_PTR, 0x0);
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- write32(mac_reg_base_addr + TDMA_WRITE_PTR, 0x0);
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- write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1);
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- write32(mac_reg_base_addr + TDMA_PROD_INDEX, 0x0);
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- write32(mac_reg_base_addr + TDMA_CONS_INDEX, 0x0);
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- write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1);
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- write32(mac_reg_base_addr + TDMA_FLOW_PERIOD, 0x0);
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- write32(mac_reg_base_addr + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
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- write32(mac_reg_base_addr + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
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+ write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
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+ write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
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+ write32(MAC_REG + TDMA_READ_PTR, 0x0);
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+ write32(MAC_REG + TDMA_READ_PTR, 0x0);
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+ write32(MAC_REG + TDMA_READ_PTR, 0x0);
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+ write32(MAC_REG + TDMA_WRITE_PTR, 0x0);
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+ write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR, TX_DESCS * DMA_DESC_SIZE / 4 - 1);
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+ write32(MAC_REG + TDMA_PROD_INDEX, 0x0);
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+ write32(MAC_REG + TDMA_CONS_INDEX, 0x0);
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+ write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH, 0x1);
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+ write32(MAC_REG + TDMA_FLOW_PERIOD, 0x0);
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+ write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
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+ write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG, 1 << DEFAULT_Q);
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}
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static void rx_descs_init(void)
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@@ -348,14 +342,14 @@ static int bcmgenet_adjust_link(void)
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return -1;
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}
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- rt_uint32_t reg1 = read32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL);
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+ rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL);
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//reg1 &= ~(1UL << OOB_DISABLE);
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//rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE);
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reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
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- write32(mac_reg_base_addr + EXT_RGMII_OOB_CTRL, reg1);
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+ write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1);
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DELAY_MICROS(1000);
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- write32(mac_reg_base_addr + UMAC_CMD, speed << CMD_SPEED_SHIFT);
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+ write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT);
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return 0;
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}
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@@ -393,28 +387,28 @@ static int bcmgenet_gmac_eth_start(void)
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}
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/* wait tx index clear */
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- while ((read32(mac_reg_base_addr + TDMA_CONS_INDEX) != 0) && (--count))
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+ while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count))
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DELAY_MICROS(1);
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- tx_index = read32(mac_reg_base_addr + TDMA_CONS_INDEX);
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- write32(mac_reg_base_addr + TDMA_PROD_INDEX, tx_index);
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+ tx_index = read32(MAC_REG + TDMA_CONS_INDEX);
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+ write32(MAC_REG + TDMA_PROD_INDEX, tx_index);
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- index_flag = read32(mac_reg_base_addr + RDMA_PROD_INDEX);
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+ index_flag = read32(MAC_REG + RDMA_PROD_INDEX);
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rx_index = index_flag % RX_DESCS;
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- write32(mac_reg_base_addr + RDMA_CONS_INDEX, index_flag);
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- write32(mac_reg_base_addr + RDMA_PROD_INDEX, index_flag);
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+ write32(MAC_REG + RDMA_CONS_INDEX, index_flag);
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+ write32(MAC_REG + RDMA_PROD_INDEX, index_flag);
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/* Enable Rx/Tx */
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rt_uint32_t rx_tx_en;
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- rx_tx_en = read32(mac_reg_base_addr + UMAC_CMD);
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- rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
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+ rx_tx_en = read32(MAC_REG + UMAC_CMD);
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- write32(mac_reg_base_addr + UMAC_CMD, rx_tx_en);
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+ rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
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- // eanble IRQ for TxDMA done and RxDMA done
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- write32(mac_reg_base_addr + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
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+ write32(MAC_REG + UMAC_CMD, rx_tx_en);
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+ //IRQ
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+ write32(MAC_REG + GENET_INTRL2_CPU_CLEAR_MASK, GENET_IRQ_TXDMA_DONE | GENET_IRQ_RXDMA_DONE);
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return 0;
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}
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@@ -424,16 +418,17 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
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{
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void* desc_base;
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rt_uint32_t length = 0, addr = 0;
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- rt_uint32_t prod_index = read32(mac_reg_base_addr + RDMA_PROD_INDEX);
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- if(prod_index == index_flag) //no buff
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+ rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX);
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+ if(prod_index == index_flag)
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{
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cur_recv_cnt = index_flag;
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index_flag = 0x7fffffff;
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+ /* no buff */
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return 0;
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}
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else
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{
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- if(prev_recv_cnt == (prod_index & 0xffff)) //no new buff
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+ if(prev_recv_cnt == prod_index & 0xffff)
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{
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return 0;
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}
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@@ -446,11 +441,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
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* This would actually not be needed if we don't program
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* RBUF_ALIGN_2B
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*/
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-
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- //Convert to memory address
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- addr = addr + eth_recv_no_cache - RECV_DATA_NO_CACHE;
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- rt_hw_cpu_dcache_invalidate(addr,length);
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-
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+ rt_hw_cpu_dcache_invalidate(addr,length);
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*packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET);
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rx_index = rx_index + 1;
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@@ -458,8 +449,7 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
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{
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rx_index = 0;
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}
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-
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- write32(mac_reg_base_addr + RDMA_CONS_INDEX, cur_recv_cnt);
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+ write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt);
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cur_recv_cnt = cur_recv_cnt + 1;
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@@ -469,43 +459,45 @@ static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
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}
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prev_recv_cnt = cur_recv_cnt;
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- return length - RX_BUF_OFFSET;
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+ return length;
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}
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}
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-
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-static int bcmgenet_gmac_eth_send(rt_uint32_t packet, int length,struct pbuf *p)
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+static int bcmgenet_gmac_eth_send(void *packet, int length)
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{
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- rt_ubase_t level;
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void *desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
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- pbuf_copy_partial(p, (void*)(packet + tx_index * SEND_CACHE_BUF), p->tot_len, 0);
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rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
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- len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
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- len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
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- rt_hw_cpu_dcache_clean((void*)(packet + tx_index * SEND_CACHE_BUF),length);
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- rt_uint32_t prod_index;
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+ rt_uint32_t prod_index, cons;
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+ rt_uint32_t tries = 100;
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- prod_index = read32(mac_reg_base_addr + TDMA_PROD_INDEX);
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+ prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
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- write32((desc_base + DMA_DESC_ADDRESS_LO), SEND_DATA_NO_CACHE + tx_index * SEND_CACHE_BUF);
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+ len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
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+ len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
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+
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+ rt_hw_cpu_dcache_clean((void*)packet, length);
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+ write32((desc_base + DMA_DESC_ADDRESS_LO), packet);
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write32((desc_base + DMA_DESC_ADDRESS_HI), 0);
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write32((desc_base + DMA_DESC_LENGTH_STATUS), len_stat);
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- tx_index ++;
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- if(tx_index >= TX_DESCS)
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- {
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- tx_index = 0;
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- }
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+ tx_index = tx_index + 1;
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prod_index = prod_index + 1;
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- if (prod_index > 0xffff)
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+ if (prod_index == 0xe000)
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{
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+ write32(MAC_REG + TDMA_PROD_INDEX, 0);
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prod_index = 0;
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}
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+ if (tx_index >= TX_DESCS)
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+ {
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+ tx_index = 0;
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+ }
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+
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/* Start Transmisson */
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- write32(mac_reg_base_addr + TDMA_PROD_INDEX, prod_index);
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+ write32(MAC_REG + TDMA_PROD_INDEX, prod_index);
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+ rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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return 0;
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}
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@@ -514,10 +506,8 @@ static void link_task_entry(void *param)
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struct eth_device *eth_device = (struct eth_device *)param;
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RT_ASSERT(eth_device != RT_NULL);
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struct rt_eth_dev *dev = ð_dev;
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-
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//start mdio
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bcmgenet_mdio_init();
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-
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//start timer link
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rt_timer_init(&dev->link_timer, "link_timer",
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link_irq,
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@@ -532,7 +522,7 @@ static void link_task_entry(void *param)
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rt_timer_stop(&dev->link_timer);
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//set mac
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- // bcmgenet_gmac_write_hwaddr();
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+ bcmgenet_gmac_write_hwaddr();
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bcmgenet_gmac_write_hwaddr();
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//check link speed
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@@ -552,13 +542,9 @@ static void link_task_entry(void *param)
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rt_kprintf("Support link mode Speed 10M\n");
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}
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-
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- //Convert to memory address
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bcmgenet_gmac_eth_start();
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-
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rt_hw_interrupt_install(ETH_IRQ, eth_rx_irq, NULL, "eth_irq");
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rt_hw_interrupt_umask(ETH_IRQ);
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-
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link_flag = 1;
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}
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@@ -569,7 +555,7 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
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/* Read GENET HW version */
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rt_uint8_t major = 0;
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- hw_reg = read32(mac_reg_base_addr + SYS_REV_CTRL);
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+ hw_reg = read32(MAC_REG + SYS_REV_CTRL);
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major = (hw_reg >> 24) & 0x0f;
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if (major != 6)
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{
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@@ -589,12 +575,12 @@ static rt_err_t bcmgenet_eth_init(rt_device_t device)
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}
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/* rbuf clear */
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- write32(mac_reg_base_addr + SYS_RBUF_FLUSH_CTRL, 0);
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+ write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0);
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/* disable MAC while updating its registers */
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- write32(mac_reg_base_addr + UMAC_CMD, 0);
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+ write32(MAC_REG + UMAC_CMD, 0);
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/* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
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- write32(mac_reg_base_addr + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
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+ write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
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link_thread_tid = rt_thread_create("link", link_task_entry, (void *)device,
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LINK_THREAD_STACK_SIZE,
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@@ -623,28 +609,32 @@ static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
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rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
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{
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+ rt_uint32_t sendbuf = (rt_uint32_t)SEND_DATA_NO_CACHE + (rt_uint32_t)(tx_index * SEND_CACHE_BUF);
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+ /* lock eth device */
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if (link_flag == 1)
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{
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- bcmgenet_gmac_eth_send((rt_uint32_t)eth_send_no_cache, p->tot_len,p);
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- rt_sem_take(&send_finsh_sem_lock,RT_WAITING_FOREVER);
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+ pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
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+ rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
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+ bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
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}
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-
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return RT_EOK;
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}
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struct pbuf *rt_eth_rx(rt_device_t device)
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{
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int recv_len = 0;
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- rt_uint8_t* addr_point = RT_NULL;
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+ rt_uint8_t *addr_point = RT_NULL;
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struct pbuf *pbuf = RT_NULL;
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if (link_flag == 1)
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{
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- recv_len = bcmgenet_gmac_eth_recv(&addr_point);
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+ recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point);
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if (recv_len > 0)
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{
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pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
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- if(pbuf)
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- rt_memcpy(pbuf->payload, addr_point, recv_len);
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+ if(pbuf)
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+ {
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+ rt_memcpy(pbuf->payload, addr_point, recv_len);
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+ }
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}
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}
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return pbuf;
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@@ -653,14 +643,15 @@ struct pbuf *rt_eth_rx(rt_device_t device)
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int rt_hw_eth_init(void)
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{
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rt_uint8_t mac_addr[6];
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- rt_sem_init(&send_finsh_sem_lock,"send_finsh_sem_lock",TX_DESCS,RT_IPC_FLAG_FIFO);
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+ rt_sem_init(&sem_lock, "eth_send_lock", TX_DESCS, RT_IPC_FLAG_FIFO);
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rt_sem_init(&link_ack, "link_ack", 0, RT_IPC_FLAG_FIFO);
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+
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memset(ð_dev, 0, sizeof(eth_dev));
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- memset((void *)eth_send_no_cache, 0, DMA_DISC_ADDR_SIZE);
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- memset((void *)eth_recv_no_cache, 0, DMA_DISC_ADDR_SIZE);
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+ memset((void *)SEND_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE);
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+ memset((void *)RECV_DATA_NO_CACHE, 0, DMA_DISC_ADDR_SIZE);
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bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
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- eth_dev.iobase = mac_reg_base_addr;
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+ eth_dev.iobase = MAC_REG;
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eth_dev.name = "e0";
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eth_dev.dev_addr[0] = mac_addr[0];
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eth_dev.dev_addr[1] = mac_addr[1];
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YJ98