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+/* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ * 1. Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * 2. Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the distribution.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+/*
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+ * Copyright (c) 2006-2025, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ */
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+
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+#include <rtthread.h>
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+#include <rtdevice.h>
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+#include <riscv_io.h>
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+#include "board.h"
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+#include "ioremap.h"
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+#include "sysctl_clk.h"
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+#include "drv_wdt.h"
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+#include <rtdbg.h>
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+#include <sys/ioctl.h>
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+
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+struct k230_wdt_dev
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+{
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+ struct rt_watchdog_device device;
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+ const char *name;
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+ rt_ubase_t base;
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+ size_t size;
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+ sysctl_clk_node_e clk; /* clock source */
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+};
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+
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+/* There are sixteen TOPs (timeout periods) that can be set in the watchdog. */
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+
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+static const rt_uint32_t *tops;
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+
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+static const rt_uint32_t k230_wdt_fix_tops[KD_WDT_NUM_TOPS] = {
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+ KD_WDT_FIX_TOP(0), KD_WDT_FIX_TOP(1), KD_WDT_FIX_TOP(2),
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+ KD_WDT_FIX_TOP(3), KD_WDT_FIX_TOP(4), KD_WDT_FIX_TOP(5),
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+ KD_WDT_FIX_TOP(6), KD_WDT_FIX_TOP(7), KD_WDT_FIX_TOP(8),
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+ KD_WDT_FIX_TOP(9), KD_WDT_FIX_TOP(10), KD_WDT_FIX_TOP(11),
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+ KD_WDT_FIX_TOP(12), KD_WDT_FIX_TOP(13), KD_WDT_FIX_TOP(14),
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+ KD_WDT_FIX_TOP(15)
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+};
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+
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+static struct k230_wdt_timeout timeouts[KD_WDT_NUM_TOPS];
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+static char rmod; /* wdt reset mode, */
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+
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+static void k230_wdt_timeouts_init(struct k230_wdt_dev *dev)
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+{
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+ rt_uint32_t wdt_clk;
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+ rt_uint32_t time_value;
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+ rt_uint32_t i, t;
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+ rt_uint64_t msec;
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+ struct k230_wdt_timeout tout, *dst;
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+ /* caculate timeout value */
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+ wdt_clk = sysctl_clk_get_leaf_freq(dev->clk);
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+
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+ for (i = 0; i < KD_WDT_NUM_TOPS; ++i)
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+ {
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+ tout.top_val = i;
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+ tout.sec = tops[i] / wdt_clk;
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+ msec = (rt_uint64_t)tops[i] * (rt_uint64_t)1000L;
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+ msec = msec / wdt_clk;
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+ tout.msec = msec - (rt_uint64_t)tout.sec * (rt_uint64_t)1000L;
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+
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+ for (t = 0; t < i; ++t)
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+ {
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+ dst = &timeouts[t];
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+ if (tout.sec > dst->sec || (tout.sec == dst->sec &&
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+ tout.msec >= dst->msec))
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+ continue;
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+ else
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+ swap(*dst, tout);
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+ }
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+
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+ timeouts[i] = tout;
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+ }
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+ rt_kprintf("watchdog timeout table init OK!\n");
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+}
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+
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+static rt_err_t k230_wdt_feed(struct k230_wdt_dev *dev)
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+{
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+ k230_wdt_t *reg = (k230_wdt_t *)dev->base;
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+ reg->crr = 0x76;
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t k230_wdt_enable(struct k230_wdt_dev *dev)
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+{
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+ k230_wdt_t *reg = (k230_wdt_t *)dev->base;
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+ reg->crr = 0x76;
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+ reg->cr |= 0x1;
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t k230_wdt_disable(struct k230_wdt_dev *dev)
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+{
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+ k230_wdt_t *reg = (k230_wdt_t *)dev->base;
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+ reg->crr = 0x76;
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+ reg->cr &= ~0x1;
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t k230_wdt_set_timeout(struct k230_wdt_dev *dev, rt_uint64_t timeout)
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+{
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+ k230_wdt_t *reg = (k230_wdt_t *)dev->base;
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+ rt_uint32_t top_val;
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+ rt_uint32_t i;
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+ rt_uint32_t time = (timeout + rmod -1) / rmod;
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+
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+ for (i = 0; i < KD_WDT_NUM_TOPS; ++i)
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+ {
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+ if (timeouts[i].sec >= time)
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+ break;
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+ }
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+
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+ if (i == KD_WDT_NUM_TOPS)
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+ --i;
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+
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+ top_val = timeouts[i].top_val;
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+
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+ reg->torr = (top_val << 4) | (top_val << 0);
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t k230_wdt_get_timeout(struct k230_wdt_dev *dev, void *timeout)
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+{
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+ rt_uint64_t top_val;
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+ rt_uint32_t i;
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+ k230_wdt_t *reg = (k230_wdt_t *)dev->base;
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+ top_val = ((reg->torr) & 0xf);
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+
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+ for (i = 0; i < KD_WDT_NUM_TOPS; ++i)
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+ {
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+ if (timeouts[i].top_val == top_val)
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+ break;
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+ }
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+
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+ *((rt_uint64_t *)timeout) = timeouts[i].sec * rmod;
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t k230_wdt_init(rt_watchdog_t *wdt)
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+{
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+ RT_ASSERT(wdt != NULL);
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+
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+ struct k230_wdt_dev *dev = rt_container_of(wdt, struct k230_wdt_dev, device);
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+ k230_wdt_t *reg = (k230_wdt_t *)dev->base;
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+
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+ reg->cr &= ~(0x01 << 1);
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+ reg->cr |= (0x0 << 1); /* default set wdt reset mode */
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+ rmod = KD_WDT_RMOD_RESET;
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+
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+ if (reg->comp_param_1 & (1 << 6))
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+ {
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+ tops = k230_wdt_fix_tops;
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+ }
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+
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+ k230_wdt_timeouts_init(dev);
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+
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+ if (!timeouts[KD_WDT_NUM_TOPS - 1].sec)
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+ {
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+ rt_kprintf("No any valid Timeout period detected\n");
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+ return -RT_EINVAL;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t k230_wdt_control(rt_watchdog_t *wdt, int cmd, void *args)
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+{
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+ RT_ASSERT(wdt != NULL);
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+
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+ struct k230_wdt_dev *dev = rt_container_of(wdt, struct k230_wdt_dev, device);
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+
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+ switch(cmd)
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+ {
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+ case KD_DEVICE_CTRL_WDT_GET_TIMEOUT:
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+ k230_wdt_get_timeout(dev, args);
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+ break;
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+ case KD_DEVICE_CTRL_WDT_SET_TIMEOUT:
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+ k230_wdt_set_timeout(dev, *((rt_uint32_t*)args));
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+ break;
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+ case KD_DEVICE_CTRL_WDT_KEEPALIVE:
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+ k230_wdt_feed(dev);
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+ break;
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+ case KD_DEVICE_CTRL_WDT_START:
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+ k230_wdt_enable(dev);
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+ break;
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+ case RT_DEVICE_CTRL_WDT_STOP:
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+ case KD_DEVICE_CTRL_WDT_STOP:
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+ k230_wdt_disable(dev);
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+ break;
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+ default:
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+ return -RT_EINVAL;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static struct rt_watchdog_ops k230_wdt_ops =
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+{
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+ .init = k230_wdt_init,
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+ .control = k230_wdt_control,
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+};
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+
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+static struct k230_wdt_dev wdt_devices[] =
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+{
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+#ifdef BSP_USING_WDT0
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+ {
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+ .name = "wdt0",
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+ .base = WDT0_BASE_ADDR,
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+ .size = WDT0_IO_SIZE,
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+ .clk = SYSCTL_CLK_WDT0,
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+ },
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+#endif /* BSP_USING_WDT0 */
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+
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+#ifdef BSP_USING_WDT1
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+ {
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+ .name = "wdt1",
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+ .base = WDT1_BASE_ADDR,
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+ .size = WDT1_IO_SIZE,
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+ .clk = SYSCTL_CLK_WDT1,
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+ },
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+#endif /* BSP_USING_WDT1 */
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+
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+#if !defined(BSP_USING_WDT0) && !defined(BSP_USING_WDT1)
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+#error "No watchdog device defined!"
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+#endif
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+};
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+
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+int rt_hw_wdt_init(void)
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+{
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+ rt_uint8_t i;
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+ for (i = 0; i < sizeof(wdt_devices) / sizeof(struct k230_wdt_dev); i++)
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+ {
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+ wdt_devices[i].device.ops = &k230_wdt_ops;
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+ wdt_devices[i].base = (rt_ubase_t)rt_ioremap((void *)wdt_devices[i].base, wdt_devices[i].size);
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+
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+ if (rt_hw_watchdog_register(&wdt_devices[i].device, wdt_devices[i].name, RT_DEVICE_FLAG_RDWR, RT_NULL) != RT_EOK)
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+ {
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+ LOG_E("%s register failed!", wdt_devices[i].name);
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+ return -RT_ERROR;
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+ }
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+ LOG_D("%s register OK!", wdt_devices[i].name);
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+ }
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+
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+ return RT_EOK;
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+}
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+INIT_DEVICE_EXPORT(rt_hw_wdt_init);
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