remove "csrrc a5, mstatus, MSTATUS_MIE" in rt_hw_interrupt_enable();

	it will lead to interrupt again in interrupt

bsp/risc-v/Makefile

@@ -104,19 +104,22 @@ DEBUG_INTERFACE = jlink
 #DEBUG_INTERFACE = stlink-v2
 #DEBUG_INTERFACE = ftdi/openjtag
 
+GDB_CMD = -ex "tar ext 127.0.0.1:3333" 
+GDB_CMD += -ex "monitor reset halt" 
+#GDB_CMD += -ex "monitor step 0x20400000" 
+GDB_CMD += --command=.gdbinit
 
 run:
 	setsid ${OPENOCD}   > /dev/null 2>&1 &
 #	(sleep 1 && echo -e "halt" && sleep 1) | telnet 127.0.0.1 4444
-	${GDB} ${TARGET}.axf -ex "tar ext 127.0.0.1:3333" -ex "monitor reset halt" \
-		 -ex "monitor step 0x20400000"
+	${GDB} ${TARGET}.axf  ${GDB_CMD}
 #	arm-none-eabi-gdb ${TARGET} -ex "tar ext 127.0.0.1:3333" -ex "b main" -ex "lay n" -ex "lay n" -ex "lay n"
-	pid=`ps -C openocd -o pid --noheader` && kill -9 $$pid
+	killall -9 openocd
 
 programe:
 	setsid ${OPENOCD}   > /dev/null 2>&1 &
-	${GDB} ${TARGET}.axf -ex "tar ext 127.0.0.1:3333" -ex "load ${TARGET}.axf"  
-	pid=`ps -C openocd -o pid --noheader` && kill -9 $$pid
+	${GDB} ${TARGET}.axf -ex "tar ext 127.0.0.1:3333" -ex "load ${TARGET}.axf"
+	killall -9 openocd
 
 clean:
 	-cd "${BUILD_DIR}" && rm *

bsp/risc-v/applications/startup.c

@@ -29,16 +29,17 @@ static void rtthread_startup(void)
 	/* initialize idle thread */
 	rt_thread_idle_init();
 
+	while(1);
 	/* start scheduler */
 	rt_system_scheduler_start();
 
 	/* never reach here */
 	return;
 }
-
+#include "encoding.h"
+#include <platform.h>
 int main(void)
 {
-
 	rtthread_startup();
 	return 0;
 }

bsp/risc-v/drivers/board.c

@@ -1,5 +1,6 @@
 #include <interrupt.h>
 #include <rthw.h>
+#include <platform.h>
 #if 0
 static struct mem_desc hw_mem_desc[] =
 {
@@ -18,8 +19,23 @@ static void rt_systick_handler(int vector, void *param)
         rt_tick_increase();
 	return;
 }
+#include <encoding.h>
 static void rt_hw_timer_init(void)
 {
+	GPIO_REG(GPIO_INPUT_EN)    &= ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;
+	GPIO_REG(GPIO_OUTPUT_EN)   |=  ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET) | (0x1 << BLUE_LED_OFFSET)) ;
+	GPIO_REG(GPIO_OUTPUT_VAL)  |=   (0x1 << BLUE_LED_OFFSET) ;
+	GPIO_REG(GPIO_OUTPUT_VAL)  &=  ~((0x1<< RED_LED_OFFSET) | (0x1<< GREEN_LED_OFFSET)) ;
+	rt_hw_interrupt_enable(1);
+/*	enable timer intrrupt*/
+	set_csr(mie, MIP_MTIP);
+
+	CLINT_REG(CLINT_MTIME) = 0x0;
+	//CLINT_REG(CLINT_MTIMECMP) = 0x10000;
+	set_csr(mie, MIP_MTIP);
+/*	set_csr(mstatus, MSTATUS_MIE);*/
+	volatile uint64_t * mtimecmp    = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP);
+	*mtimecmp = 0x20000;
 	return;
 }
 void rt_hw_board_init(void)
@@ -31,7 +47,7 @@ void rt_hw_board_init(void)
 
 	/* initialize the system clock */
 	//rt_hw_clock_init(); //set each pll etc.
-
+	
 	/* initialize uart */
 	rt_hw_uart_init();
 	rt_console_set_device(RT_CONSOLE_DEVICE_NAME);

bsp/risc-v/platform/interrupt.c

@@ -1,4 +1,5 @@
 #include <rthw.h>
+#include "platform.h"
 
 #define MAX_HANDLERS    (128)
 extern rt_uint32_t rt_interrupt_nest;
@@ -35,7 +36,10 @@ void rt_hw_interrupt_init(void)
 {
 	int idx;
 /*	config interrupt vector*/
-
+	asm volatile(
+		"la t0, trap_entry\n"
+		"csrw mtvec, t0"
+	);
 /*	enable interrupt*/
 
 	/* init exceptions table */

bsp/risc-v/rtconfig.py

@@ -44,7 +44,7 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY = PREFIX + 'objcopy'
 
-    DEVICE = ' -march=rv32imac -mabi=ilp32 -mcmodel=medany -msmall-data-limit=8  -g -L.  -nostartfiles  -lc '
+    DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -mcmodel=medany -msmall-data-limit=8  -g -L.  -nostartfiles  -lc '
 #    DEVICE += '-Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit'
     CFLAGS = DEVICE
 #    CFLAGS += ' -I ./mx28_registers/'

libcpu/risc-v/e310/context_gcc.S

@@ -30,14 +30,26 @@
  */
     .globl rt_hw_interrupt_disable
 rt_hw_interrupt_disable:
-	ret
+  addi sp, sp, -12
+  sw a5, (sp)
+  csrrc a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP
+/*  csrrc a5, mstatus, MSTATUS_MIE*/
+  lw a5, (sp)
+  addi sp, sp, 12
+  ret
 
 /*
  * void rt_hw_interrupt_enable(rt_base_t level);
  */
     .globl rt_hw_interrupt_enable
 rt_hw_interrupt_enable:
-	ret
+  addi sp, sp, -12
+  sw a5, (sp)
+  csrrs a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP
+/*  csrrsi a5, mstatus, MSTATUS_MIE*/
+  lw a5, (sp)
+  addi sp, sp, 12
+  ret
 
 /*
  * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
@@ -178,5 +190,22 @@ rt_hw_context_switch_to:
     .globl rt_interrupt_to_thread
     .globl rt_hw_context_switch_interrupt
 rt_hw_context_switch_interrupt:
+  addi sp, sp, -16
+  sw s0, 12(sp)
+  sw a0, 8(sp)
+  sw a5, 4(sp)
+  la a0, rt_thread_switch_interrupt_flag
+  beqz a5, _reswitch
+  li a5, 1
+  sw a5, (a0)
+  la a5, rt_interrupt_from_thread
+  lw a0, 8(sp)
+  sw a0, (a5)
 _reswitch:
-	ret
+  la a5, rt_interrupt_to_thread
+  sw a1, (a5)
+  lw a5, 4(sp)
+  lw a0, 8(sp)
+  lw s0, 12(sp)
+  addi sp, sp, 16
+  ret

libcpu/risc-v/e310/entry_gcc.S

@@ -1,97 +0,0 @@
-// See LICENSE for license details
-
-#ifndef ENTRY_S
-#define ENTRY_S
-
-#include "encoding.h"
-#include "sifive/bits.h"
-
-  .section      .text.entry	
-  .align 2
-  .global trap_entry
-trap_entry:
-  addi sp, sp, -32*REGBYTES
-
-  STORE x1, 1*REGBYTES(sp)
-  STORE x2, 2*REGBYTES(sp)
-  STORE x3, 3*REGBYTES(sp)
-  STORE x4, 4*REGBYTES(sp)
-  STORE x5, 5*REGBYTES(sp)
-  STORE x6, 6*REGBYTES(sp)
-  STORE x7, 7*REGBYTES(sp)
-  STORE x8, 8*REGBYTES(sp)
-  STORE x9, 9*REGBYTES(sp)
-  STORE x10, 10*REGBYTES(sp)
-  STORE x11, 11*REGBYTES(sp)
-  STORE x12, 12*REGBYTES(sp)
-  STORE x13, 13*REGBYTES(sp)
-  STORE x14, 14*REGBYTES(sp)
-  STORE x15, 15*REGBYTES(sp)
-  STORE x16, 16*REGBYTES(sp)
-  STORE x17, 17*REGBYTES(sp)
-  STORE x18, 18*REGBYTES(sp)
-  STORE x19, 19*REGBYTES(sp)
-  STORE x20, 20*REGBYTES(sp)
-  STORE x21, 21*REGBYTES(sp)
-  STORE x22, 22*REGBYTES(sp)
-  STORE x23, 23*REGBYTES(sp)
-  STORE x24, 24*REGBYTES(sp)
-  STORE x25, 25*REGBYTES(sp)
-  STORE x26, 26*REGBYTES(sp)
-  STORE x27, 27*REGBYTES(sp)
-  STORE x28, 28*REGBYTES(sp)
-  STORE x29, 29*REGBYTES(sp)
-  STORE x30, 30*REGBYTES(sp)
-  STORE x31, 31*REGBYTES(sp)
-
-  csrr a0, mcause
-  csrr a1, mepc
-  mv a2, sp
-  call handle_trap
-  csrw mepc, a0
-
-  # Remain in M-mode after mret
-  li t0, MSTATUS_MPP
-  csrs mstatus, t0
-
-  LOAD x1, 1*REGBYTES(sp)
-  LOAD x2, 2*REGBYTES(sp)
-  LOAD x3, 3*REGBYTES(sp)
-  LOAD x4, 4*REGBYTES(sp)
-  LOAD x5, 5*REGBYTES(sp)
-  LOAD x6, 6*REGBYTES(sp)
-  LOAD x7, 7*REGBYTES(sp)
-  LOAD x8, 8*REGBYTES(sp)
-  LOAD x9, 9*REGBYTES(sp)
-  LOAD x10, 10*REGBYTES(sp)
-  LOAD x11, 11*REGBYTES(sp)
-  LOAD x12, 12*REGBYTES(sp)
-  LOAD x13, 13*REGBYTES(sp)
-  LOAD x14, 14*REGBYTES(sp)
-  LOAD x15, 15*REGBYTES(sp)
-  LOAD x16, 16*REGBYTES(sp)
-  LOAD x17, 17*REGBYTES(sp)
-  LOAD x18, 18*REGBYTES(sp)
-  LOAD x19, 19*REGBYTES(sp)
-  LOAD x20, 20*REGBYTES(sp)
-  LOAD x21, 21*REGBYTES(sp)
-  LOAD x22, 22*REGBYTES(sp)
-  LOAD x23, 23*REGBYTES(sp)
-  LOAD x24, 24*REGBYTES(sp)
-  LOAD x25, 25*REGBYTES(sp)
-  LOAD x26, 26*REGBYTES(sp)
-  LOAD x27, 27*REGBYTES(sp)
-  LOAD x28, 28*REGBYTES(sp)
-  LOAD x29, 29*REGBYTES(sp)
-  LOAD x30, 30*REGBYTES(sp)
-  LOAD x31, 31*REGBYTES(sp)
-
-  addi sp, sp, 32*REGBYTES
-  mret
-
-.weak handle_trap
-handle_trap:
-1:
-  j 1b
-	
-#endif

libcpu/risc-v/e310/start_gcc.S

@@ -17,6 +17,8 @@ _start:
 	la gp, __global_pointer$
 .option pop
 	la sp, _sp
+/*disable all interrupt*/
+	csrw mie, 0
 
 #if defined(ENABLE_SMP)
 	smp_pause(t0, t1)
@@ -49,6 +51,7 @@ _start:
 	la a0, __libc_fini_array
 	call atexit
 	call __libc_init_array
+        call _init
 
 #ifndef __riscv_float_abi_soft
 	/* Enable FPU */
@@ -109,3 +112,139 @@ _start:
 	j 1b
 #endif
 	.cfi_endproc
+
+#include "encoding.h"
+#include "sifive/bits.h"
+
+  .section      .text.entry	
+  .align 2
+  .global trap_entry
+trap_entry:
+  addi sp, sp, -32*REGBYTES
+
+  STORE x30, 1*REGBYTES(sp)
+  STORE x31, 2*REGBYTES(sp)
+  STORE x3, 3*REGBYTES(sp)
+  STORE x4, 4*REGBYTES(sp)
+  STORE x5, 5*REGBYTES(sp)
+  STORE x6, 6*REGBYTES(sp)
+  STORE x7, 7*REGBYTES(sp)
+  STORE x8, 8*REGBYTES(sp)
+  STORE x9, 9*REGBYTES(sp)
+  STORE x10, 10*REGBYTES(sp)
+  STORE x11, 11*REGBYTES(sp)
+  STORE x12, 12*REGBYTES(sp)
+  STORE x13, 13*REGBYTES(sp)
+  STORE x14, 14*REGBYTES(sp)
+  STORE x15, 15*REGBYTES(sp)
+  STORE x16, 16*REGBYTES(sp)
+  STORE x17, 17*REGBYTES(sp)
+  STORE x18, 18*REGBYTES(sp)
+  STORE x19, 19*REGBYTES(sp)
+  STORE x20, 20*REGBYTES(sp)
+  STORE x21, 21*REGBYTES(sp)
+  STORE x22, 22*REGBYTES(sp)
+  STORE x23, 23*REGBYTES(sp)
+  STORE x24, 24*REGBYTES(sp)
+  STORE x25, 25*REGBYTES(sp)
+  STORE x26, 26*REGBYTES(sp)
+  STORE x27, 27*REGBYTES(sp)
+  STORE x28, 28*REGBYTES(sp)
+  STORE x1, 31*REGBYTES(sp)
+  STORE x10, 29*REGBYTES(sp)
+  STORE x1, 30*REGBYTES(sp)
+
+  csrr a0, mcause
+  csrr a1, mepc
+  csrw mepc, a0
+
+  call rt_interrupt_enter
+  call rt_hw_trap_irq
+  call handle_m_time_interrupt
+  call rt_interrupt_leave
+
+  la a0, rt_thread_switch_interrupt_flag
+  lw a1, (a0)
+  beqz a1, rt_hw_context_switch_interrupt_do
+
+  csrw mepc, a0
+  # Remain in M-mode after mret
+  li t0, MSTATUS_MPP
+  csrs mstatus, t0
+
+  LOAD x30, 1*REGBYTES(sp)
+  LOAD x31, 2*REGBYTES(sp)
+  LOAD x3,  3*REGBYTES(sp)
+  LOAD x4,  4*REGBYTES(sp)
+  LOAD x5,  5*REGBYTES(sp)
+  LOAD x6,  6*REGBYTES(sp)
+  LOAD x7,  7*REGBYTES(sp)
+  LOAD x8,  8*REGBYTES(sp)
+  LOAD x9,  9*REGBYTES(sp)
+  LOAD x29, 10*REGBYTES(sp)
+  LOAD x11, 11*REGBYTES(sp)
+  LOAD x12, 12*REGBYTES(sp)
+  LOAD x13, 13*REGBYTES(sp)
+  LOAD x14, 14*REGBYTES(sp)
+  LOAD x15, 15*REGBYTES(sp)
+  LOAD x16, 16*REGBYTES(sp)
+  LOAD x17, 17*REGBYTES(sp)
+  LOAD x18, 18*REGBYTES(sp)
+  LOAD x19, 19*REGBYTES(sp)
+  LOAD x20, 20*REGBYTES(sp)
+  LOAD x21, 21*REGBYTES(sp)
+  LOAD x22, 22*REGBYTES(sp)
+  LOAD x23, 23*REGBYTES(sp)
+  LOAD x24, 24*REGBYTES(sp)
+  LOAD x25, 25*REGBYTES(sp)
+  LOAD x26, 26*REGBYTES(sp)
+  LOAD x27, 27*REGBYTES(sp)
+  LOAD x28, 28*REGBYTES(sp)
+  LOAD x10, 31*REGBYTES(sp)
+  csrw mepc, a0
+  LOAD x10, 29*REGBYTES(sp)
+  LOAD x1,  30*REGBYTES(sp)
+  
+
+  addi sp, sp, 32*REGBYTES
+  mret
+
+rt_hw_context_switch_interrupt_do:
+  LOAD a0, rt_interrupt_to_thread
+  LOAD sp, (a0)
+  LOAD x30, 1*REGBYTES(sp)
+  LOAD x31, 2*REGBYTES(sp)
+  LOAD x3,  3*REGBYTES(sp)
+  LOAD x4,  4*REGBYTES(sp)
+  LOAD x5,  5*REGBYTES(sp)
+  LOAD x6,  6*REGBYTES(sp)
+  LOAD x7,  7*REGBYTES(sp)
+  LOAD x8,  8*REGBYTES(sp)
+  LOAD x9,  9*REGBYTES(sp)
+  LOAD x29, 10*REGBYTES(sp)
+  LOAD x11, 11*REGBYTES(sp)
+  LOAD x12, 12*REGBYTES(sp)
+  LOAD x13, 13*REGBYTES(sp)
+  LOAD x14, 14*REGBYTES(sp)
+  LOAD x15, 15*REGBYTES(sp)
+  LOAD x16, 16*REGBYTES(sp)
+  LOAD x17, 17*REGBYTES(sp)
+  LOAD x18, 18*REGBYTES(sp)
+  LOAD x19, 19*REGBYTES(sp)
+  LOAD x20, 20*REGBYTES(sp)
+  LOAD x21, 21*REGBYTES(sp)
+  LOAD x22, 22*REGBYTES(sp)
+  LOAD x23, 23*REGBYTES(sp)
+  LOAD x24, 24*REGBYTES(sp)
+  LOAD x25, 25*REGBYTES(sp)
+  LOAD x26, 26*REGBYTES(sp)
+  LOAD x27, 27*REGBYTES(sp)
+  LOAD x28, 28*REGBYTES(sp)
+  LOAD x10, 31*REGBYTES(sp)
+  csrw mepc, a0
+  LOAD x10, 29*REGBYTES(sp)
+  LOAD x1,  30*REGBYTES(sp)
+  
+
+  addi sp, sp, 32*REGBYTES
+  mret