[bsp/ch32v103r-evt] add ch32v103r-evt bsp

feat: move MRS demo source to bsp and libraries folder

feat: update Sconscript

feat: modify SConstruct in the bsp

feat: use the rtconfig.py of gd32vf103v-eval bsp to modify

feat: use the MRS's rtconfig.h temoporarily

feat: update Kconfig files

feat: use the MRS's .ld and rename as link.lds

feat: add ch32v1 porting folder

perf: remove board/system_ch32v10x.c

fix: define SOC_ARM_SERIES_CH32V103 in rtconfig.h

fix: add some neccessary macros in rtconfig.h

perf: use the menuconfig to generate rtconfig.h

feat: add readme.md

fix: correct the bad encode in main.c

fix: include board.h in main.c

perf: check and update README.md

perf: remove ch32f10x_port_cn.md

feat: ignore the standard libraries's CI checking

feat: add sdk_dist.py

fix: correct some style errors again

perf: simply the board/kconfig

fix: format ch32v103r-evt

fix: format drvs and libcpu

bsp/wch/risc-v/.ignore_format.yml

@@ -0,0 +1,6 @@
+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- Libraries/CH32V10x_StdPeriph_Driver

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/ch32v10x.h

@@ -0,0 +1,3215 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer Header File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_H
+#define __CH32V10x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __MPU_PRESENT             0  /* Other CH32 devices does not provide an MPU */
+#define __Vendor_SysTickConfig    0  /* Set to 1 if different SysTick Config is used */
+
+#define HSE_VALUE                 ((uint32_t)8000000) /* Value of the External oscillator in Hz */
+
+/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
+#define HSE_STARTUP_TIMEOUT       ((uint16_t)0x500) /* Time out for HSE start up */
+
+#define HSI_VALUE                 ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+
+/* Interrupt Number Definition, according to the selected device */
+typedef enum IRQn
+{
+    /******  RISC-V Processor Exceptions Numbers *******************************************************/
+    NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt                             */
+    EXC_IRQn = 3,            /* 4 Exception Interrupt                                */
+    SysTicK_IRQn = 12,       /* 12 System timer Interrupt                            */
+    Software_IRQn = 14,      /* 14 software Interrupt                                */
+
+    /******  RISC-V specific Interrupt Numbers *********************************************************/
+    WWDG_IRQn = 16,          /* Window WatchDog Interrupt                            */
+    PVD_IRQn = 17,           /* PVD through EXTI Line detection Interrupt            */
+    TAMPER_IRQn = 18,        /* Tamper Interrupt                                     */
+    RTC_IRQn = 19,           /* RTC global Interrupt                                 */
+    FLASH_IRQn = 20,         /* FLASH global Interrupt                               */
+    RCC_IRQn = 21,           /* RCC global Interrupt                                 */
+    EXTI0_IRQn = 22,         /* EXTI Line0 Interrupt                                 */
+    EXTI1_IRQn = 23,         /* EXTI Line1 Interrupt                                 */
+    EXTI2_IRQn = 24,         /* EXTI Line2 Interrupt                                 */
+    EXTI3_IRQn = 25,         /* EXTI Line3 Interrupt                                 */
+    EXTI4_IRQn = 26,         /* EXTI Line4 Interrupt                                 */
+    DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt                      */
+    DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt                      */
+    DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt                      */
+    DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt                      */
+    DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt                      */
+    DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt                      */
+    DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt                      */
+    ADC_IRQn = 34,           /* ADC1 global Interrupt                                */
+    EXTI9_5_IRQn = 39,       /* External Line[9:5] Interrupts                        */
+    TIM1_BRK_IRQn = 40,      /* TIM1 Break Interrupt                                 */
+    TIM1_UP_IRQn = 41,       /* TIM1 Update Interrupt                                */
+    TIM1_TRG_COM_IRQn = 42,  /* TIM1 Trigger and Commutation Interrupt               */
+    TIM1_CC_IRQn = 43,       /* TIM1 Capture Compare Interrupt                       */
+    TIM2_IRQn = 44,          /* TIM2 global Interrupt                                */
+    TIM3_IRQn = 45,          /* TIM3 global Interrupt                                */
+    TIM4_IRQn = 46,          /* TIM4 global Interrupt                                */
+    I2C1_EV_IRQn = 47,       /* I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn = 48,       /* I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn = 49,       /* I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn = 50,       /* I2C2 Error Interrupt                                 */
+    SPI1_IRQn = 51,          /* SPI1 global Interrupt                                */
+    SPI2_IRQn = 52,          /* SPI2 global Interrupt                                */
+    USART1_IRQn = 53,        /* USART1 global Interrupt                              */
+    USART2_IRQn = 54,        /* USART2 global Interrupt                              */
+    USART3_IRQn = 55,        /* USART3 global Interrupt                              */
+    EXTI15_10_IRQn = 56,     /* External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn = 57,      /* RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn = 58,     /* USB WakeUp from suspend through EXTI Line Interrupt  */
+    USBHD_IRQn = 59,         /* USBHD Interrupt                                      */
+
+} IRQn_Type;
+
+#define HardFault_IRQn    EXC_IRQn
+#define ADC1_2_IRQn       ADC_IRQn
+
+#include <stdint.h>
+#include "core_riscv.h"
+#include "system_ch32v10x.h"
+
+/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSI_Value             HSI_VALUE
+#define HSE_Value             HSE_VALUE
+#define HSEStartUp_TimeOut    HSE_STARTUP_TIMEOUT
+
+/* Analog to Digital Converter */
+typedef struct
+{
+    __IO uint32_t STATR;
+    __IO uint32_t CTLR1;
+    __IO uint32_t CTLR2;
+    __IO uint32_t SAMPTR1;
+    __IO uint32_t SAMPTR2;
+    __IO uint32_t IOFR1;
+    __IO uint32_t IOFR2;
+    __IO uint32_t IOFR3;
+    __IO uint32_t IOFR4;
+    __IO uint32_t WDHTR;
+    __IO uint32_t WDLTR;
+    __IO uint32_t RSQR1;
+    __IO uint32_t RSQR2;
+    __IO uint32_t RSQR3;
+    __IO uint32_t ISQR;
+    __IO uint32_t IDATAR1;
+    __IO uint32_t IDATAR2;
+    __IO uint32_t IDATAR3;
+    __IO uint32_t IDATAR4;
+    __IO uint32_t RDATAR;
+} ADC_TypeDef;
+
+/* Backup Registers */
+typedef struct
+{
+    uint32_t      RESERVED0;
+    __IO uint16_t DATAR1;
+    uint16_t      RESERVED1;
+    __IO uint16_t DATAR2;
+    uint16_t      RESERVED2;
+    __IO uint16_t DATAR3;
+    uint16_t      RESERVED3;
+    __IO uint16_t DATAR4;
+    uint16_t      RESERVED4;
+    __IO uint16_t DATAR5;
+    uint16_t      RESERVED5;
+    __IO uint16_t DATAR6;
+    uint16_t      RESERVED6;
+    __IO uint16_t DATAR7;
+    uint16_t      RESERVED7;
+    __IO uint16_t DATAR8;
+    uint16_t      RESERVED8;
+    __IO uint16_t DATAR9;
+    uint16_t      RESERVED9;
+    __IO uint16_t DATAR10;
+    uint16_t      RESERVED10;
+    __IO uint16_t OCTLR;
+    uint16_t      RESERVED11;
+    __IO uint16_t TPCTLR;
+    uint16_t      RESERVED12;
+    __IO uint16_t TPCSR;
+    uint16_t      RESERVED13[5];
+    __IO uint16_t DATAR11;
+    uint16_t      RESERVED14;
+    __IO uint16_t DATAR12;
+    uint16_t      RESERVED15;
+    __IO uint16_t DATAR13;
+    uint16_t      RESERVED16;
+    __IO uint16_t DATAR14;
+    uint16_t      RESERVED17;
+    __IO uint16_t DATAR15;
+    uint16_t      RESERVED18;
+    __IO uint16_t DATAR16;
+    uint16_t      RESERVED19;
+    __IO uint16_t DATAR17;
+    uint16_t      RESERVED20;
+    __IO uint16_t DATAR18;
+    uint16_t      RESERVED21;
+    __IO uint16_t DATAR19;
+    uint16_t      RESERVED22;
+    __IO uint16_t DATAR20;
+    uint16_t      RESERVED23;
+    __IO uint16_t DATAR21;
+    uint16_t      RESERVED24;
+    __IO uint16_t DATAR22;
+    uint16_t      RESERVED25;
+    __IO uint16_t DATAR23;
+    uint16_t      RESERVED26;
+    __IO uint16_t DATAR24;
+    uint16_t      RESERVED27;
+    __IO uint16_t DATAR25;
+    uint16_t      RESERVED28;
+    __IO uint16_t DATAR26;
+    uint16_t      RESERVED29;
+    __IO uint16_t DATAR27;
+    uint16_t      RESERVED30;
+    __IO uint16_t DATAR28;
+    uint16_t      RESERVED31;
+    __IO uint16_t DATAR29;
+    uint16_t      RESERVED32;
+    __IO uint16_t DATAR30;
+    uint16_t      RESERVED33;
+    __IO uint16_t DATAR31;
+    uint16_t      RESERVED34;
+    __IO uint16_t DATAR32;
+    uint16_t      RESERVED35;
+    __IO uint16_t DATAR33;
+    uint16_t      RESERVED36;
+    __IO uint16_t DATAR34;
+    uint16_t      RESERVED37;
+    __IO uint16_t DATAR35;
+    uint16_t      RESERVED38;
+    __IO uint16_t DATAR36;
+    uint16_t      RESERVED39;
+    __IO uint16_t DATAR37;
+    uint16_t      RESERVED40;
+    __IO uint16_t DATAR38;
+    uint16_t      RESERVED41;
+    __IO uint16_t DATAR39;
+    uint16_t      RESERVED42;
+    __IO uint16_t DATAR40;
+    uint16_t      RESERVED43;
+    __IO uint16_t DATAR41;
+    uint16_t      RESERVED44;
+    __IO uint16_t DATAR42;
+    uint16_t      RESERVED45;
+} BKP_TypeDef;
+
+/* CRC Calculation Unit */
+typedef struct
+{
+    __IO uint32_t DATAR;
+    __IO uint8_t  IDATAR;
+    uint8_t       RESERVED0;
+    uint16_t      RESERVED1;
+    __IO uint32_t CTLR;
+} CRC_TypeDef;
+
+/* Digital to Analog Converter */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t SWTR;
+    __IO uint32_t R12BDHR1;
+    __IO uint32_t L12BDHR1;
+    __IO uint32_t R8BDHR1;
+    __IO uint32_t R12BDHR2;
+    __IO uint32_t L12BDHR2;
+    __IO uint32_t R8BDHR2;
+    __IO uint32_t RD12BDHR;
+    __IO uint32_t LD12BDHR;
+    __IO uint32_t RD8BDHR;
+    __IO uint32_t DOR1;
+    __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/* Debug MCU */
+typedef struct
+{
+    __IO uint32_t CFGR0;
+    __IO uint32_t CFGR1;
+} DBGMCU_TypeDef;
+
+/* DMA Controller */
+typedef struct
+{
+    __IO uint32_t CFGR;
+    __IO uint32_t CNTR;
+    __IO uint32_t PADDR;
+    __IO uint32_t MADDR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t INTFR;
+    __IO uint32_t INTFCR;
+} DMA_TypeDef;
+
+/* External Interrupt/Event Controller */
+typedef struct
+{
+    __IO uint32_t INTENR;
+    __IO uint32_t EVENR;
+    __IO uint32_t RTENR;
+    __IO uint32_t FTENR;
+    __IO uint32_t SWIEVR;
+    __IO uint32_t INTFR;
+} EXTI_TypeDef;
+
+/* FLASH Registers */
+typedef struct
+{
+    __IO uint32_t ACTLR;
+    __IO uint32_t KEYR;
+    __IO uint32_t OBKEYR;
+    __IO uint32_t STATR;
+    __IO uint32_t CTLR;
+    __IO uint32_t ADDR;
+    __IO uint32_t RESERVED;
+    __IO uint32_t OBR;
+    __IO uint32_t WPR;
+    __IO uint32_t MODEKEYR;
+} FLASH_TypeDef;
+
+/* Option Bytes Registers */
+typedef struct
+{
+    __IO uint16_t RDPR;
+    __IO uint16_t USER;
+    __IO uint16_t Data0;
+    __IO uint16_t Data1;
+    __IO uint16_t WRPR0;
+    __IO uint16_t WRPR1;
+    __IO uint16_t WRPR2;
+    __IO uint16_t WRPR3;
+} OB_TypeDef;
+
+/* General Purpose I/O */
+typedef struct
+{
+    __IO uint32_t CFGLR;
+    __IO uint32_t CFGHR;
+    __IO uint32_t INDR;
+    __IO uint32_t OUTDR;
+    __IO uint32_t BSHR;
+    __IO uint32_t BCR;
+    __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/* Alternate Function I/O */
+typedef struct
+{
+    __IO uint32_t ECR;
+    __IO uint32_t PCFR1;
+    __IO uint32_t EXTICR[4];
+    uint32_t      RESERVED0;
+    __IO uint32_t PCFR2;
+} AFIO_TypeDef;
+
+/* Inter Integrated Circuit Interface */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t OADDR1;
+    uint16_t      RESERVED2;
+    __IO uint16_t OADDR2;
+    uint16_t      RESERVED3;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED4;
+    __IO uint16_t STAR1;
+    uint16_t      RESERVED5;
+    __IO uint16_t STAR2;
+    uint16_t      RESERVED6;
+    __IO uint16_t CKCFGR;
+    uint16_t      RESERVED7;
+    __IO uint16_t RTR;
+    uint16_t      RESERVED8;
+} I2C_TypeDef;
+
+/* Independent WatchDog */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t PSCR;
+    __IO uint32_t RLDR;
+    __IO uint32_t STATR;
+} IWDG_TypeDef;
+
+/* Power Control */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/* Reset and Clock Control */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CFGR0;
+    __IO uint32_t INTR;
+    __IO uint32_t APB2PRSTR;
+    __IO uint32_t APB1PRSTR;
+    __IO uint32_t AHBPCENR;
+    __IO uint32_t APB2PCENR;
+    __IO uint32_t APB1PCENR;
+    __IO uint32_t BDCTLR;
+    __IO uint32_t RSTSCKR;
+} RCC_TypeDef;
+
+/* Real-Time Clock */
+typedef struct
+{
+    __IO uint16_t CTLRH;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLRL;
+    uint16_t      RESERVED1;
+    __IO uint16_t PSCRH;
+    uint16_t      RESERVED2;
+    __IO uint16_t PSCRL;
+    uint16_t      RESERVED3;
+    __IO uint16_t DIVH;
+    uint16_t      RESERVED4;
+    __IO uint16_t DIVL;
+    uint16_t      RESERVED5;
+    __IO uint16_t CNTH;
+    uint16_t      RESERVED6;
+    __IO uint16_t CNTL;
+    uint16_t      RESERVED7;
+    __IO uint16_t ALRMH;
+    uint16_t      RESERVED8;
+    __IO uint16_t ALRML;
+    uint16_t      RESERVED9;
+} RTC_TypeDef;
+
+/* Serial Peripheral Interface */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t STATR;
+    uint16_t      RESERVED2;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED3;
+    __IO uint16_t CRCR;
+    uint16_t      RESERVED4;
+    __IO uint16_t RCRCR;
+    uint16_t      RESERVED5;
+    __IO uint16_t TCRCR;
+    uint16_t      RESERVED6;
+    __IO uint16_t I2SCFGR;
+    uint16_t      RESERVED7;
+    __IO uint16_t I2SPR;
+    uint16_t      RESERVED8;
+} SPI_TypeDef;
+
+/* TIM */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t SMCFGR;
+    uint16_t      RESERVED2;
+    __IO uint16_t DMAINTENR;
+    uint16_t      RESERVED3;
+    __IO uint16_t INTFR;
+    uint16_t      RESERVED4;
+    __IO uint16_t SWEVGR;
+    uint16_t      RESERVED5;
+    __IO uint16_t CHCTLR1;
+    uint16_t      RESERVED6;
+    __IO uint16_t CHCTLR2;
+    uint16_t      RESERVED7;
+    __IO uint16_t CCER;
+    uint16_t      RESERVED8;
+    __IO uint16_t CNT;
+    uint16_t      RESERVED9;
+    __IO uint16_t PSC;
+    uint16_t      RESERVED10;
+    __IO uint16_t ATRLR;
+    uint16_t      RESERVED11;
+    __IO uint16_t RPTCR;
+    uint16_t      RESERVED12;
+    __IO uint16_t CH1CVR;
+    uint16_t      RESERVED13;
+    __IO uint16_t CH2CVR;
+    uint16_t      RESERVED14;
+    __IO uint16_t CH3CVR;
+    uint16_t      RESERVED15;
+    __IO uint16_t CH4CVR;
+    uint16_t      RESERVED16;
+    __IO uint16_t BDTR;
+    uint16_t      RESERVED17;
+    __IO uint16_t DMACFGR;
+    uint16_t      RESERVED18;
+    __IO uint16_t DMAADR;
+    uint16_t      RESERVED19;
+} TIM_TypeDef;
+
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+typedef struct
+{
+    __IO uint16_t STATR;
+    uint16_t      RESERVED0;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED1;
+    __IO uint16_t BRR;
+    uint16_t      RESERVED2;
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED3;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED4;
+    __IO uint16_t CTLR3;
+    uint16_t      RESERVED5;
+    __IO uint16_t GPR;
+    uint16_t      RESERVED6;
+} USART_TypeDef;
+
+/* Window WatchDog */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CFGR;
+    __IO uint32_t STATR;
+} WWDG_TypeDef;
+
+/* Enhanced Registers */
+typedef struct
+{
+    __IO uint32_t EXTEN_CTR;
+} EXTEN_TypeDef;
+
+/* Peripheral memory map */
+#define FLASH_BASE                              ((uint32_t)0x08000000) /* FLASH base address in the alias region */
+#define SRAM_BASE                               ((uint32_t)0x20000000) /* SRAM base address in the alias region */
+#define PERIPH_BASE                             ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
+
+#define APB1PERIPH_BASE                         (PERIPH_BASE)
+#define APB2PERIPH_BASE                         (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE                          (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE                               (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE                               (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE                               (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE                               (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE                               (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE                               (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE                              (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE                              (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE                              (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE                                (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE                               (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE                               (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE                               (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE                               (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE                             (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE                             (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE                              (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE                              (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE                               (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE                               (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE                                (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE                                (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE                                (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE                               (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE                               (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE                              (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE                              (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE                              (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE                              (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE                              (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE                              (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE                              (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE                               (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE                               (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE                               (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE                               (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE                               (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE                             (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE                               (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE                              (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE                              (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE                              (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE                               (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE                              (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE                              (APB2PERIPH_BASE + 0x5400)
+
+#define DMA1_BASE                               (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE                      (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE                      (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE                      (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE                      (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE                      (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE                      (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE                      (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE                               (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE                      (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE                      (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE                      (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE                      (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE                      (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE                                (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE                                (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE                            (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
+#define OB_BASE                                 ((uint32_t)0x1FFFF800)    /* Flash Option Bytes base address */
+#define DBGMCU_BASE                             ((uint32_t)0xE000D000)
+#define EXTEN_BASE                              ((uint32_t)0x40023800)
+
+/* Peripheral declaration */
+#define TIM2                                    ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3                                    ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4                                    ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5                                    ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6                                    ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7                                    ((TIM_TypeDef *)TIM7_BASE)
+#define TIM12                                   ((TIM_TypeDef *)TIM12_BASE)
+#define TIM13                                   ((TIM_TypeDef *)TIM13_BASE)
+#define TIM14                                   ((TIM_TypeDef *)TIM14_BASE)
+#define RTC                                     ((RTC_TypeDef *)RTC_BASE)
+#define WWDG                                    ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG                                    ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2                                    ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3                                    ((SPI_TypeDef *)SPI3_BASE)
+#define USART2                                  ((USART_TypeDef *)USART2_BASE)
+#define USART3                                  ((USART_TypeDef *)USART3_BASE)
+#define UART4                                   ((USART_TypeDef *)UART4_BASE)
+#define UART5                                   ((USART_TypeDef *)UART5_BASE)
+#define I2C1                                    ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2                                    ((I2C_TypeDef *)I2C2_BASE)
+#define BKP                                     ((BKP_TypeDef *)BKP_BASE)
+#define PWR                                     ((PWR_TypeDef *)PWR_BASE)
+#define DAC                                     ((DAC_TypeDef *)DAC_BASE)
+#define AFIO                                    ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI                                    ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA                                   ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB                                   ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC                                   ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD                                   ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE                                   ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF                                   ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG                                   ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1                                    ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2                                    ((ADC_TypeDef *)ADC2_BASE)
+#define TIM1                                    ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1                                    ((SPI_TypeDef *)SPI1_BASE)
+#define TIM8                                    ((TIM_TypeDef *)TIM8_BASE)
+#define USART1                                  ((USART_TypeDef *)USART1_BASE)
+#define ADC3                                    ((ADC_TypeDef *)ADC3_BASE)
+#define TIM15                                   ((TIM_TypeDef *)TIM15_BASE)
+#define TIM16                                   ((TIM_TypeDef *)TIM16_BASE)
+#define TIM17                                   ((TIM_TypeDef *)TIM17_BASE)
+#define TIM9                                    ((TIM_TypeDef *)TIM9_BASE)
+#define TIM10                                   ((TIM_TypeDef *)TIM10_BASE)
+#define TIM11                                   ((TIM_TypeDef *)TIM11_BASE)
+#define DMA1                                    ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2                                    ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1                           ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2                           ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3                           ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4                           ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5                           ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6                           ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7                           ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1                           ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2                           ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3                           ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4                           ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5                           ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC                                     ((RCC_TypeDef *)RCC_BASE)
+#define CRC                                     ((CRC_TypeDef *)CRC_BASE)
+#define FLASH                                   ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB                                      ((OB_TypeDef *)OB_BASE)
+#define DBGMCU                                  ((DBGMCU_TypeDef *)DBGMCU_BASE)
+#define EXTEN                                   ((EXTEN_TypeDef *)EXTEN_BASE)
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                        Analog to Digital Converter                         */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STATR register  ********************/
+#define ADC_AWD                                 ((uint8_t)0x01) /* Analog watchdog flag */
+#define ADC_EOC                                 ((uint8_t)0x02) /* End of conversion */
+#define ADC_JEOC                                ((uint8_t)0x04) /* Injected channel end of conversion */
+#define ADC_JSTRT                               ((uint8_t)0x08) /* Injected channel Start flag */
+#define ADC_STRT                                ((uint8_t)0x10) /* Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CTLR1 register  ********************/
+#define ADC_AWDCH                               ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_AWDCH_0                             ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_AWDCH_1                             ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_AWDCH_2                             ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_AWDCH_3                             ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_AWDCH_4                             ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_EOCIE                               ((uint32_t)0x00000020) /* Interrupt enable for EOC */
+#define ADC_AWDIE                               ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */
+#define ADC_JEOCIE                              ((uint32_t)0x00000080) /* Interrupt enable for injected channels */
+#define ADC_SCAN                                ((uint32_t)0x00000100) /* Scan mode */
+#define ADC_AWDSGL                              ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */
+#define ADC_JAUTO                               ((uint32_t)0x00000400) /* Automatic injected group conversion */
+#define ADC_DISCEN                              ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */
+#define ADC_JDISCEN                             ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */
+
+#define ADC_DISCNUM                             ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_DISCNUM_0                           ((uint32_t)0x00002000) /* Bit 0 */
+#define ADC_DISCNUM_1                           ((uint32_t)0x00004000) /* Bit 1 */
+#define ADC_DISCNUM_2                           ((uint32_t)0x00008000) /* Bit 2 */
+
+#define ADC_DUALMOD                             ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_DUALMOD_0                           ((uint32_t)0x00010000) /* Bit 0 */
+#define ADC_DUALMOD_1                           ((uint32_t)0x00020000) /* Bit 1 */
+#define ADC_DUALMOD_2                           ((uint32_t)0x00040000) /* Bit 2 */
+#define ADC_DUALMOD_3                           ((uint32_t)0x00080000) /* Bit 3 */
+
+#define ADC_JAWDEN                              ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */
+#define ADC_AWDEN                               ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CTLR2 register  ********************/
+#define ADC_ADON                                ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
+#define ADC_CONT                                ((uint32_t)0x00000002) /* Continuous Conversion */
+#define ADC_CAL                                 ((uint32_t)0x00000004) /* A/D Calibration */
+#define ADC_RSTCAL                              ((uint32_t)0x00000008) /* Reset Calibration */
+#define ADC_DMA                                 ((uint32_t)0x00000100) /* Direct Memory access mode */
+#define ADC_ALIGN                               ((uint32_t)0x00000800) /* Data Alignment */
+
+#define ADC_JEXTSEL                             ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_JEXTSEL_0                           ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_JEXTSEL_1                           ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_JEXTSEL_2                           ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_JEXTTRIG                            ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */
+
+#define ADC_EXTSEL                              ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_EXTSEL_0                            ((uint32_t)0x00020000) /* Bit 0 */
+#define ADC_EXTSEL_1                            ((uint32_t)0x00040000) /* Bit 1 */
+#define ADC_EXTSEL_2                            ((uint32_t)0x00080000) /* Bit 2 */
+
+#define ADC_EXTTRIG                             ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */
+#define ADC_JSWSTART                            ((uint32_t)0x00200000) /* Start Conversion of injected channels */
+#define ADC_SWSTART                             ((uint32_t)0x00400000) /* Start Conversion of regular channels */
+#define ADC_TSVREFE                             ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SAMPTR1 register  *******************/
+#define ADC_SMP10                               ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMP10_0                             ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SMP10_1                             ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SMP10_2                             ((uint32_t)0x00000004) /* Bit 2 */
+
+#define ADC_SMP11                               ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMP11_0                             ((uint32_t)0x00000008) /* Bit 0 */
+#define ADC_SMP11_1                             ((uint32_t)0x00000010) /* Bit 1 */
+#define ADC_SMP11_2                             ((uint32_t)0x00000020) /* Bit 2 */
+
+#define ADC_SMP12                               ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMP12_0                             ((uint32_t)0x00000040) /* Bit 0 */
+#define ADC_SMP12_1                             ((uint32_t)0x00000080) /* Bit 1 */
+#define ADC_SMP12_2                             ((uint32_t)0x00000100) /* Bit 2 */
+
+#define ADC_SMP13                               ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMP13_0                             ((uint32_t)0x00000200) /* Bit 0 */
+#define ADC_SMP13_1                             ((uint32_t)0x00000400) /* Bit 1 */
+#define ADC_SMP13_2                             ((uint32_t)0x00000800) /* Bit 2 */
+
+#define ADC_SMP14                               ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMP14_0                             ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_SMP14_1                             ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_SMP14_2                             ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_SMP15                               ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMP15_0                             ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SMP15_1                             ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SMP15_2                             ((uint32_t)0x00020000) /* Bit 2 */
+
+#define ADC_SMP16                               ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMP16_0                             ((uint32_t)0x00040000) /* Bit 0 */
+#define ADC_SMP16_1                             ((uint32_t)0x00080000) /* Bit 1 */
+#define ADC_SMP16_2                             ((uint32_t)0x00100000) /* Bit 2 */
+
+#define ADC_SMP17                               ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMP17_0                             ((uint32_t)0x00200000) /* Bit 0 */
+#define ADC_SMP17_1                             ((uint32_t)0x00400000) /* Bit 1 */
+#define ADC_SMP17_2                             ((uint32_t)0x00800000) /* Bit 2 */
+
+/******************  Bit definition for ADC_SAMPTR2 register  *******************/
+#define ADC_SMP0                                ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMP0_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SMP0_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SMP0_2                              ((uint32_t)0x00000004) /* Bit 2 */
+
+#define ADC_SMP1                                ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMP1_0                              ((uint32_t)0x00000008) /* Bit 0 */
+#define ADC_SMP1_1                              ((uint32_t)0x00000010) /* Bit 1 */
+#define ADC_SMP1_2                              ((uint32_t)0x00000020) /* Bit 2 */
+
+#define ADC_SMP2                                ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMP2_0                              ((uint32_t)0x00000040) /* Bit 0 */
+#define ADC_SMP2_1                              ((uint32_t)0x00000080) /* Bit 1 */
+#define ADC_SMP2_2                              ((uint32_t)0x00000100) /* Bit 2 */
+
+#define ADC_SMP3                                ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMP3_0                              ((uint32_t)0x00000200) /* Bit 0 */
+#define ADC_SMP3_1                              ((uint32_t)0x00000400) /* Bit 1 */
+#define ADC_SMP3_2                              ((uint32_t)0x00000800) /* Bit 2 */
+
+#define ADC_SMP4                                ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMP4_0                              ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_SMP4_1                              ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_SMP4_2                              ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_SMP5                                ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMP5_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SMP5_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SMP5_2                              ((uint32_t)0x00020000) /* Bit 2 */
+
+#define ADC_SMP6                                ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMP6_0                              ((uint32_t)0x00040000) /* Bit 0 */
+#define ADC_SMP6_1                              ((uint32_t)0x00080000) /* Bit 1 */
+#define ADC_SMP6_2                              ((uint32_t)0x00100000) /* Bit 2 */
+
+#define ADC_SMP7                                ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMP7_0                              ((uint32_t)0x00200000) /* Bit 0 */
+#define ADC_SMP7_1                              ((uint32_t)0x00400000) /* Bit 1 */
+#define ADC_SMP7_2                              ((uint32_t)0x00800000) /* Bit 2 */
+
+#define ADC_SMP8                                ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMP8_0                              ((uint32_t)0x01000000) /* Bit 0 */
+#define ADC_SMP8_1                              ((uint32_t)0x02000000) /* Bit 1 */
+#define ADC_SMP8_2                              ((uint32_t)0x04000000) /* Bit 2 */
+
+#define ADC_SMP9                                ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMP9_0                              ((uint32_t)0x08000000) /* Bit 0 */
+#define ADC_SMP9_1                              ((uint32_t)0x10000000) /* Bit 1 */
+#define ADC_SMP9_2                              ((uint32_t)0x20000000) /* Bit 2 */
+
+/******************  Bit definition for ADC_IOFR1 register  *******************/
+#define ADC_JOFFSET1                            ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_IOFR2 register  *******************/
+#define ADC_JOFFSET2                            ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_IOFR3 register  *******************/
+#define ADC_JOFFSET3                            ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_IOFR4 register  *******************/
+#define ADC_JOFFSET4                            ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WDHTR register  ********************/
+#define ADC_HT                                  ((uint16_t)0x0FFF) /* Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WDLTR register  ********************/
+#define ADC_LT                                  ((uint16_t)0x0FFF) /* Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSQR1 register  *******************/
+#define ADC_SQ13                                ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQ13_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ13_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ13_2                              ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ13_3                              ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ13_4                              ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ14                                ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQ14_0                              ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ14_1                              ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ14_2                              ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ14_3                              ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ14_4                              ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ15                                ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQ15_0                              ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ15_1                              ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ15_2                              ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ15_3                              ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ15_4                              ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ16                                ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQ16_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ16_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ16_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ16_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ16_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_L                                   ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
+#define ADC_L_0                                 ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_L_1                                 ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_L_2                                 ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_L_3                                 ((uint32_t)0x00800000) /* Bit 3 */
+
+/*******************  Bit definition for ADC_RSQR2 register  *******************/
+#define ADC_SQ7                                 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQ7_0                               ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ7_1                               ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ7_2                               ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ7_3                               ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ7_4                               ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ8                                 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQ8_0                               ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ8_1                               ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ8_2                               ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ8_3                               ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ8_4                               ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ9                                 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQ9_0                               ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ9_1                               ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ9_2                               ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ9_3                               ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ9_4                               ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ10                                ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQ10_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ10_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ10_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ10_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ10_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_SQ11                                ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQ11_0                              ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_SQ11_1                              ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_SQ11_2                              ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_SQ11_3                              ((uint32_t)0x00800000) /* Bit 3 */
+#define ADC_SQ11_4                              ((uint32_t)0x01000000) /* Bit 4 */
+
+#define ADC_SQ12                                ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQ12_0                              ((uint32_t)0x02000000) /* Bit 0 */
+#define ADC_SQ12_1                              ((uint32_t)0x04000000) /* Bit 1 */
+#define ADC_SQ12_2                              ((uint32_t)0x08000000) /* Bit 2 */
+#define ADC_SQ12_3                              ((uint32_t)0x10000000) /* Bit 3 */
+#define ADC_SQ12_4                              ((uint32_t)0x20000000) /* Bit 4 */
+
+/*******************  Bit definition for ADC_RSQR3 register  *******************/
+#define ADC_SQ1                                 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQ1_0                               ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ1_1                               ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ1_2                               ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ1_3                               ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ1_4                               ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ2                                 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQ2_0                               ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ2_1                               ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ2_2                               ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ2_3                               ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ2_4                               ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ3                                 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQ3_0                               ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ3_1                               ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ3_2                               ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ3_3                               ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ3_4                               ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ4                                 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQ4_0                               ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ4_1                               ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ4_2                               ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ4_3                               ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ4_4                               ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_SQ5                                 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQ5_0                               ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_SQ5_1                               ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_SQ5_2                               ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_SQ5_3                               ((uint32_t)0x00800000) /* Bit 3 */
+#define ADC_SQ5_4                               ((uint32_t)0x01000000) /* Bit 4 */
+
+#define ADC_SQ6                                 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQ6_0                               ((uint32_t)0x02000000) /* Bit 0 */
+#define ADC_SQ6_1                               ((uint32_t)0x04000000) /* Bit 1 */
+#define ADC_SQ6_2                               ((uint32_t)0x08000000) /* Bit 2 */
+#define ADC_SQ6_3                               ((uint32_t)0x10000000) /* Bit 3 */
+#define ADC_SQ6_4                               ((uint32_t)0x20000000) /* Bit 4 */
+
+/*******************  Bit definition for ADC_ISQR register  *******************/
+#define ADC_JSQ1                                ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQ1_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_JSQ1_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_JSQ1_2                              ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_JSQ1_3                              ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_JSQ1_4                              ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_JSQ2                                ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQ2_0                              ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_JSQ2_1                              ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_JSQ2_2                              ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_JSQ2_3                              ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_JSQ2_4                              ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_JSQ3                                ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQ3_0                              ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_JSQ3_1                              ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_JSQ3_2                              ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_JSQ3_3                              ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_JSQ3_4                              ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_JSQ4                                ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQ4_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_JSQ4_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_JSQ4_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_JSQ4_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_JSQ4_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_JL                                  ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
+#define ADC_JL_0                                ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_JL_1                                ((uint32_t)0x00200000) /* Bit 1 */
+
+/*******************  Bit definition for ADC_IDATAR1 register  *******************/
+#define ADC_IDATAR1_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR2 register  *******************/
+#define ADC_IDATAR2_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR3 register  *******************/
+#define ADC_IDATAR3_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR4 register  *******************/
+#define ADC_IDATAR4_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/********************  Bit definition for ADC_RDATAR register  ********************/
+#define ADC_RDATAR_DATA                         ((uint32_t)0x0000FFFF) /* Regular data */
+#define ADC_RDATAR_ADC2DATA                     ((uint32_t)0xFFFF0000) /* ADC2 data */
+
+/******************************************************************************/
+/*                            Backup registers                                */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DATAR1 register  ********************/
+#define BKP_DATAR1_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR2 register  ********************/
+#define BKP_DATAR2_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR3 register  ********************/
+#define BKP_DATAR3_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR4 register  ********************/
+#define BKP_DATAR4_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR5 register  ********************/
+#define BKP_DATAR5_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR6 register  ********************/
+#define BKP_DATAR6_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR7 register  ********************/
+#define BKP_DATAR7_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR8 register  ********************/
+#define BKP_DATAR8_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR9 register  ********************/
+#define BKP_DATAR9_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR10 register  *******************/
+#define BKP_DATAR10_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR11 register  *******************/
+#define BKP_DATAR11_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR12 register  *******************/
+#define BKP_DATAR12_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR13 register  *******************/
+#define BKP_DATAR13_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR14 register  *******************/
+#define BKP_DATAR14_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR15 register  *******************/
+#define BKP_DATAR15_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR16 register  *******************/
+#define BKP_DATAR16_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR17 register  *******************/
+#define BKP_DATAR17_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/******************  Bit definition for BKP_DATAR18 register  ********************/
+#define BKP_DATAR18_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR19 register  *******************/
+#define BKP_DATAR19_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR20 register  *******************/
+#define BKP_DATAR20_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR21 register  *******************/
+#define BKP_DATAR21_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR22 register  *******************/
+#define BKP_DATAR22_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR23 register  *******************/
+#define BKP_DATAR23_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR24 register  *******************/
+#define BKP_DATAR24_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR25 register  *******************/
+#define BKP_DATAR25_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR26 register  *******************/
+#define BKP_DATAR26_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR27 register  *******************/
+#define BKP_DATAR27_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR28 register  *******************/
+#define BKP_DATAR28_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR29 register  *******************/
+#define BKP_DATAR29_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR30 register  *******************/
+#define BKP_DATAR30_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR31 register  *******************/
+#define BKP_DATAR31_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR32 register  *******************/
+#define BKP_DATAR32_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR33 register  *******************/
+#define BKP_DATAR33_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR34 register  *******************/
+#define BKP_DATAR34_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR35 register  *******************/
+#define BKP_DATAR35_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR36 register  *******************/
+#define BKP_DATAR36_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR37 register  *******************/
+#define BKP_DATAR37_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR38 register  *******************/
+#define BKP_DATAR38_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR39 register  *******************/
+#define BKP_DATAR39_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR40 register  *******************/
+#define BKP_DATAR40_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR41 register  *******************/
+#define BKP_DATAR41_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR42 register  *******************/
+#define BKP_DATAR42_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/******************  Bit definition for BKP_OCTLR register  *******************/
+#define BKP_CAL                                 ((uint16_t)0x007F) /* Calibration value */
+#define BKP_CCO                                 ((uint16_t)0x0080) /* Calibration Clock Output */
+#define BKP_ASOE                                ((uint16_t)0x0100) /* Alarm or Second Output Enable */
+#define BKP_ASOS                                ((uint16_t)0x0200) /* Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_TPCTLR register  ********************/
+#define BKP_TPE                                 ((uint8_t)0x01) /* TAMPER pin enable */
+#define BKP_TPAL                                ((uint8_t)0x02) /* TAMPER pin active level */
+
+/*******************  Bit definition for BKP_TPCSR register  ********************/
+#define BKP_CTE                                 ((uint16_t)0x0001) /* Clear Tamper event */
+#define BKP_CTI                                 ((uint16_t)0x0002) /* Clear Tamper Interrupt */
+#define BKP_TPIE                                ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */
+#define BKP_TEF                                 ((uint16_t)0x0100) /* Tamper Event Flag */
+#define BKP_TIF                                 ((uint16_t)0x0200) /* Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                          CRC Calculation Unit                              */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DATAR register  *********************/
+#define CRC_DATAR_DR                            ((uint32_t)0xFFFFFFFF) /* Data register bits */
+
+/*******************  Bit definition for CRC_IDATAR register  ********************/
+#define CRC_IDR_IDATAR                          ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CTLR register  ********************/
+#define CRC_CTLR_RESET                          ((uint8_t)0x01) /* RESET bit */
+
+/******************************************************************************/
+/*                      Digital to Analog Converter                           */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CTLR register  ********************/
+#define DAC_EN1                                 ((uint32_t)0x00000001) /* DAC channel1 enable */
+#define DAC_BOFF1                               ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */
+#define DAC_TEN1                                ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */
+
+#define DAC_TSEL1                               ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_TSEL1_0                             ((uint32_t)0x00000008) /* Bit 0 */
+#define DAC_TSEL1_1                             ((uint32_t)0x00000010) /* Bit 1 */
+#define DAC_TSEL1_2                             ((uint32_t)0x00000020) /* Bit 2 */
+
+#define DAC_WAVE1                               ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_WAVE1_0                             ((uint32_t)0x00000040) /* Bit 0 */
+#define DAC_WAVE1_1                             ((uint32_t)0x00000080) /* Bit 1 */
+
+#define DAC_MAMP1                               ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_MAMP1_0                             ((uint32_t)0x00000100) /* Bit 0 */
+#define DAC_MAMP1_1                             ((uint32_t)0x00000200) /* Bit 1 */
+#define DAC_MAMP1_2                             ((uint32_t)0x00000400) /* Bit 2 */
+#define DAC_MAMP1_3                             ((uint32_t)0x00000800) /* Bit 3 */
+
+#define DAC_DMAEN1                              ((uint32_t)0x00001000) /* DAC channel1 DMA enable */
+#define DAC_EN2                                 ((uint32_t)0x00010000) /* DAC channel2 enable */
+#define DAC_BOFF2                               ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */
+#define DAC_TEN2                                ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */
+
+#define DAC_TSEL2                               ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_TSEL2_0                             ((uint32_t)0x00080000) /* Bit 0 */
+#define DAC_TSEL2_1                             ((uint32_t)0x00100000) /* Bit 1 */
+#define DAC_TSEL2_2                             ((uint32_t)0x00200000) /* Bit 2 */
+
+#define DAC_WAVE2                               ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_WAVE2_0                             ((uint32_t)0x00400000) /* Bit 0 */
+#define DAC_WAVE2_1                             ((uint32_t)0x00800000) /* Bit 1 */
+
+#define DAC_MAMP2                               ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_MAMP2_0                             ((uint32_t)0x01000000) /* Bit 0 */
+#define DAC_MAMP2_1                             ((uint32_t)0x02000000) /* Bit 1 */
+#define DAC_MAMP2_2                             ((uint32_t)0x04000000) /* Bit 2 */
+#define DAC_MAMP2_3                             ((uint32_t)0x08000000) /* Bit 3 */
+
+#define DAC_DMAEN2                              ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTR register  ******************/
+#define DAC_SWTRIG1                             ((uint8_t)0x01) /* DAC channel1 software trigger */
+#define DAC_SWTRIG2                             ((uint8_t)0x02) /* DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_R12BDHR1 register  ******************/
+#define DAC_DHR12R1                             ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR1 register  ******************/
+#define DAC_DHR12L1                             ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR1 register  ******************/
+#define DAC_DHR8R1                              ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_R12BDHR2 register  ******************/
+#define DAC_DHR12R2                             ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR2 register  ******************/
+#define DAC_DHR12L2                             ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR2 register  ******************/
+#define DAC_DHR8R2                              ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_RD12BDHR register  ******************/
+#define DAC_RD12BDHR_DACC1DHR                   ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */
+#define DAC_RD12BDHR_DACC2DHR                   ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_LD12BDHR register  ******************/
+#define DAC_LD12BDHR_DACC1DHR                   ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */
+#define DAC_LD12BDHR_DACC2DHR                   ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_RD8BDHR register  ******************/
+#define DAC_RD8BDHR_DACC1DHR                    ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */
+#define DAC_RD8BDHR_DACC2DHR                    ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DACC1DOR                            ((uint16_t)0x0FFF) /* DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DACC2DOR                            ((uint16_t)0x0FFF) /* DAC channel2 data output */
+
+/******************************************************************************/
+/*                             DMA Controller                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_INTFR register  ********************/
+#define DMA_GIF1                                ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */
+#define DMA_TCIF1                               ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */
+#define DMA_HTIF1                               ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */
+#define DMA_TEIF1                               ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */
+#define DMA_GIF2                                ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */
+#define DMA_TCIF2                               ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */
+#define DMA_HTIF2                               ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */
+#define DMA_TEIF2                               ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */
+#define DMA_GIF3                                ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */
+#define DMA_TCIF3                               ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */
+#define DMA_HTIF3                               ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */
+#define DMA_TEIF3                               ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */
+#define DMA_GIF4                                ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */
+#define DMA_TCIF4                               ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */
+#define DMA_HTIF4                               ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */
+#define DMA_TEIF4                               ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */
+#define DMA_GIF5                                ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */
+#define DMA_TCIF5                               ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */
+#define DMA_HTIF5                               ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */
+#define DMA_TEIF5                               ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */
+#define DMA_GIF6                                ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */
+#define DMA_TCIF6                               ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */
+#define DMA_HTIF6                               ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */
+#define DMA_TEIF6                               ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */
+#define DMA_GIF7                                ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */
+#define DMA_TCIF7                               ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */
+#define DMA_HTIF7                               ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
+#define DMA_TEIF7                               ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_INTFCR register  *******************/
+#define DMA_CGIF1                               ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
+#define DMA_CTCIF1                              ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
+#define DMA_CHTIF1                              ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */
+#define DMA_CTEIF1                              ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */
+#define DMA_CGIF2                               ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */
+#define DMA_CTCIF2                              ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */
+#define DMA_CHTIF2                              ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */
+#define DMA_CTEIF2                              ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */
+#define DMA_CGIF3                               ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */
+#define DMA_CTCIF3                              ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */
+#define DMA_CHTIF3                              ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */
+#define DMA_CTEIF3                              ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */
+#define DMA_CGIF4                               ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */
+#define DMA_CTCIF4                              ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */
+#define DMA_CHTIF4                              ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */
+#define DMA_CTEIF4                              ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */
+#define DMA_CGIF5                               ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */
+#define DMA_CTCIF5                              ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */
+#define DMA_CHTIF5                              ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */
+#define DMA_CTEIF5                              ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */
+#define DMA_CGIF6                               ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */
+#define DMA_CTCIF6                              ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */
+#define DMA_CHTIF6                              ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */
+#define DMA_CTEIF6                              ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */
+#define DMA_CGIF7                               ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */
+#define DMA_CTCIF7                              ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */
+#define DMA_CHTIF7                              ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */
+#define DMA_CTEIF7                              ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CFGR1 register  *******************/
+#define DMA_CFGR1_EN                            ((uint16_t)0x0001) /* Channel enable*/
+#define DMA_CFGR1_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR1_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR1_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR1_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR1_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR1_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR1_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR1_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR1_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR1_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR1_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR1_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR1_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR1_PL                            ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */
+#define DMA_CFGR1_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR1_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR1_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR2 register  *******************/
+#define DMA_CFGR2_EN                            ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFGR2_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR2_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR2_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR2_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR2_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR2_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR2_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR2_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR2_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR2_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR2_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR2_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR2_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR2_PL                            ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFGR2_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR2_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR2_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR3 register  *******************/
+#define DMA_CFGR3_EN                            ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFGR3_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR3_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR3_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR3_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR3_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR3_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR3_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR3_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR3_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR3_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR3_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR3_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR3_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR3_PL                            ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFGR3_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR3_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR3_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG4 register  *******************/
+#define DMA_CFG4_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG4_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG4_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG4_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG4_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG4_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG4_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG4_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG4_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG4_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG4_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG4_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG4_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG4_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG4_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG4_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG4_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG4_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode */
+
+/******************  Bit definition for DMA_CFG5 register  *******************/
+#define DMA_CFG5_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG5_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG5_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG5_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG5_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG5_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG5_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG5_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG5_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG5_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG5_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG5_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG5_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG5_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG5_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG5_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG5_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG5_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CFG6 register  *******************/
+#define DMA_CFG6_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG6_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG6_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG6_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG6_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG6_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG6_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG6_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG6_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG6_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG6_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG6_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG6_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG6_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG6_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG6_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG6_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG6_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG7 register  *******************/
+#define DMA_CFG7_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG7_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG7_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG7_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG7_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG7_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG7_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG7_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG7_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG7_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG7_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG7_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG7_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG7_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG7_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG7_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG7_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG7_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNTR1 register  ******************/
+#define DMA_CNTR1_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR2 register  ******************/
+#define DMA_CNTR2_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR3 register  ******************/
+#define DMA_CNTR3_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR4 register  ******************/
+#define DMA_CNTR4_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR5 register  ******************/
+#define DMA_CNTR5_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR6 register  ******************/
+#define DMA_CNTR6_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR7 register  ******************/
+#define DMA_CNTR7_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_PADDR1 register  *******************/
+#define DMA_PADDR1_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR2 register  *******************/
+#define DMA_PADDR2_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR3 register  *******************/
+#define DMA_PADDR3_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR4 register  *******************/
+#define DMA_PADDR4_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR5 register  *******************/
+#define DMA_PADDR5_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR6 register  *******************/
+#define DMA_PADDR6_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR7 register  *******************/
+#define DMA_PADDR7_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_MADDR1 register  *******************/
+#define DMA_MADDR1_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR2 register  *******************/
+#define DMA_MADDR2_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR3 register  *******************/
+#define DMA_MADDR3_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR4 register  *******************/
+#define DMA_MADDR4_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR5 register  *******************/
+#define DMA_MADDR5_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR6 register  *******************/
+#define DMA_MADDR6_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR7 register  *******************/
+#define DMA_MADDR7_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************************************************************************/
+/*                    External Interrupt/Event Controller                     */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_INTENR register  *******************/
+#define EXTI_INTENR_MR0                         ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */
+#define EXTI_INTENR_MR1                         ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */
+#define EXTI_INTENR_MR2                         ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */
+#define EXTI_INTENR_MR3                         ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */
+#define EXTI_INTENR_MR4                         ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */
+#define EXTI_INTENR_MR5                         ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */
+#define EXTI_INTENR_MR6                         ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */
+#define EXTI_INTENR_MR7                         ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */
+#define EXTI_INTENR_MR8                         ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */
+#define EXTI_INTENR_MR9                         ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */
+#define EXTI_INTENR_MR10                        ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */
+#define EXTI_INTENR_MR11                        ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */
+#define EXTI_INTENR_MR12                        ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */
+#define EXTI_INTENR_MR13                        ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */
+#define EXTI_INTENR_MR14                        ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */
+#define EXTI_INTENR_MR15                        ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */
+#define EXTI_INTENR_MR16                        ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */
+#define EXTI_INTENR_MR17                        ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */
+#define EXTI_INTENR_MR18                        ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */
+#define EXTI_INTENR_MR19                        ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EVENR register  *******************/
+#define EXTI_EVENR_MR0                          ((uint32_t)0x00000001) /* Event Mask on line 0 */
+#define EXTI_EVENR_MR1                          ((uint32_t)0x00000002) /* Event Mask on line 1 */
+#define EXTI_EVENR_MR2                          ((uint32_t)0x00000004) /* Event Mask on line 2 */
+#define EXTI_EVENR_MR3                          ((uint32_t)0x00000008) /* Event Mask on line 3 */
+#define EXTI_EVENR_MR4                          ((uint32_t)0x00000010) /* Event Mask on line 4 */
+#define EXTI_EVENR_MR5                          ((uint32_t)0x00000020) /* Event Mask on line 5 */
+#define EXTI_EVENR_MR6                          ((uint32_t)0x00000040) /* Event Mask on line 6 */
+#define EXTI_EVENR_MR7                          ((uint32_t)0x00000080) /* Event Mask on line 7 */
+#define EXTI_EVENR_MR8                          ((uint32_t)0x00000100) /* Event Mask on line 8 */
+#define EXTI_EVENR_MR9                          ((uint32_t)0x00000200) /* Event Mask on line 9 */
+#define EXTI_EVENR_MR10                         ((uint32_t)0x00000400) /* Event Mask on line 10 */
+#define EXTI_EVENR_MR11                         ((uint32_t)0x00000800) /* Event Mask on line 11 */
+#define EXTI_EVENR_MR12                         ((uint32_t)0x00001000) /* Event Mask on line 12 */
+#define EXTI_EVENR_MR13                         ((uint32_t)0x00002000) /* Event Mask on line 13 */
+#define EXTI_EVENR_MR14                         ((uint32_t)0x00004000) /* Event Mask on line 14 */
+#define EXTI_EVENR_MR15                         ((uint32_t)0x00008000) /* Event Mask on line 15 */
+#define EXTI_EVENR_MR16                         ((uint32_t)0x00010000) /* Event Mask on line 16 */
+#define EXTI_EVENR_MR17                         ((uint32_t)0x00020000) /* Event Mask on line 17 */
+#define EXTI_EVENR_MR18                         ((uint32_t)0x00040000) /* Event Mask on line 18 */
+#define EXTI_EVENR_MR19                         ((uint32_t)0x00080000) /* Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTENR register  *******************/
+#define EXTI_RTENR_TR0                          ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */
+#define EXTI_RTENR_TR1                          ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */
+#define EXTI_RTENR_TR2                          ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */
+#define EXTI_RTENR_TR3                          ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */
+#define EXTI_RTENR_TR4                          ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */
+#define EXTI_RTENR_TR5                          ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */
+#define EXTI_RTENR_TR6                          ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */
+#define EXTI_RTENR_TR7                          ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */
+#define EXTI_RTENR_TR8                          ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */
+#define EXTI_RTENR_TR9                          ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */
+#define EXTI_RTENR_TR10                         ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */
+#define EXTI_RTENR_TR11                         ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */
+#define EXTI_RTENR_TR12                         ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */
+#define EXTI_RTENR_TR13                         ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */
+#define EXTI_RTENR_TR14                         ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */
+#define EXTI_RTENR_TR15                         ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */
+#define EXTI_RTENR_TR16                         ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */
+#define EXTI_RTENR_TR17                         ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */
+#define EXTI_RTENR_TR18                         ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */
+#define EXTI_RTENR_TR19                         ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTENR register  *******************/
+#define EXTI_FTENR_TR0                          ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */
+#define EXTI_FTENR_TR1                          ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */
+#define EXTI_FTENR_TR2                          ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */
+#define EXTI_FTENR_TR3                          ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */
+#define EXTI_FTENR_TR4                          ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */
+#define EXTI_FTENR_TR5                          ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */
+#define EXTI_FTENR_TR6                          ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */
+#define EXTI_FTENR_TR7                          ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */
+#define EXTI_FTENR_TR8                          ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */
+#define EXTI_FTENR_TR9                          ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */
+#define EXTI_FTENR_TR10                         ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */
+#define EXTI_FTENR_TR11                         ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */
+#define EXTI_FTENR_TR12                         ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */
+#define EXTI_FTENR_TR13                         ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */
+#define EXTI_FTENR_TR14                         ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */
+#define EXTI_FTENR_TR15                         ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */
+#define EXTI_FTENR_TR16                         ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */
+#define EXTI_FTENR_TR17                         ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */
+#define EXTI_FTENR_TR18                         ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */
+#define EXTI_FTENR_TR19                         ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIEVR register  ******************/
+#define EXTI_SWIEVR_SWIEVR0                     ((uint32_t)0x00000001) /* Software Interrupt on line 0 */
+#define EXTI_SWIEVR_SWIEVR1                     ((uint32_t)0x00000002) /* Software Interrupt on line 1 */
+#define EXTI_SWIEVR_SWIEVR2                     ((uint32_t)0x00000004) /* Software Interrupt on line 2 */
+#define EXTI_SWIEVR_SWIEVR3                     ((uint32_t)0x00000008) /* Software Interrupt on line 3 */
+#define EXTI_SWIEVR_SWIEVR4                     ((uint32_t)0x00000010) /* Software Interrupt on line 4 */
+#define EXTI_SWIEVR_SWIEVR5                     ((uint32_t)0x00000020) /* Software Interrupt on line 5 */
+#define EXTI_SWIEVR_SWIEVR6                     ((uint32_t)0x00000040) /* Software Interrupt on line 6 */
+#define EXTI_SWIEVR_SWIEVR7                     ((uint32_t)0x00000080) /* Software Interrupt on line 7 */
+#define EXTI_SWIEVR_SWIEVR8                     ((uint32_t)0x00000100) /* Software Interrupt on line 8 */
+#define EXTI_SWIEVR_SWIEVR9                     ((uint32_t)0x00000200) /* Software Interrupt on line 9 */
+#define EXTI_SWIEVR_SWIEVR10                    ((uint32_t)0x00000400) /* Software Interrupt on line 10 */
+#define EXTI_SWIEVR_SWIEVR11                    ((uint32_t)0x00000800) /* Software Interrupt on line 11 */
+#define EXTI_SWIEVR_SWIEVR12                    ((uint32_t)0x00001000) /* Software Interrupt on line 12 */
+#define EXTI_SWIEVR_SWIEVR13                    ((uint32_t)0x00002000) /* Software Interrupt on line 13 */
+#define EXTI_SWIEVR_SWIEVR14                    ((uint32_t)0x00004000) /* Software Interrupt on line 14 */
+#define EXTI_SWIEVR_SWIEVR15                    ((uint32_t)0x00008000) /* Software Interrupt on line 15 */
+#define EXTI_SWIEVR_SWIEVR16                    ((uint32_t)0x00010000) /* Software Interrupt on line 16 */
+#define EXTI_SWIEVR_SWIEVR17                    ((uint32_t)0x00020000) /* Software Interrupt on line 17 */
+#define EXTI_SWIEVR_SWIEVR18                    ((uint32_t)0x00040000) /* Software Interrupt on line 18 */
+#define EXTI_SWIEVR_SWIEVR19                    ((uint32_t)0x00080000) /* Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_INTFR register  ********************/
+#define EXTI_INTF_INTF0                         ((uint32_t)0x00000001) /* Pending bit for line 0 */
+#define EXTI_INTF_INTF1                         ((uint32_t)0x00000002) /* Pending bit for line 1 */
+#define EXTI_INTF_INTF2                         ((uint32_t)0x00000004) /* Pending bit for line 2 */
+#define EXTI_INTF_INTF3                         ((uint32_t)0x00000008) /* Pending bit for line 3 */
+#define EXTI_INTF_INTF4                         ((uint32_t)0x00000010) /* Pending bit for line 4 */
+#define EXTI_INTF_INTF5                         ((uint32_t)0x00000020) /* Pending bit for line 5 */
+#define EXTI_INTF_INTF6                         ((uint32_t)0x00000040) /* Pending bit for line 6 */
+#define EXTI_INTF_INTF7                         ((uint32_t)0x00000080) /* Pending bit for line 7 */
+#define EXTI_INTF_INTF8                         ((uint32_t)0x00000100) /* Pending bit for line 8 */
+#define EXTI_INTF_INTF9                         ((uint32_t)0x00000200) /* Pending bit for line 9 */
+#define EXTI_INTF_INTF10                        ((uint32_t)0x00000400) /* Pending bit for line 10 */
+#define EXTI_INTF_INTF11                        ((uint32_t)0x00000800) /* Pending bit for line 11 */
+#define EXTI_INTF_INTF12                        ((uint32_t)0x00001000) /* Pending bit for line 12 */
+#define EXTI_INTF_INTF13                        ((uint32_t)0x00002000) /* Pending bit for line 13 */
+#define EXTI_INTF_INTF14                        ((uint32_t)0x00004000) /* Pending bit for line 14 */
+#define EXTI_INTF_INTF15                        ((uint32_t)0x00008000) /* Pending bit for line 15 */
+#define EXTI_INTF_INTF16                        ((uint32_t)0x00010000) /* Pending bit for line 16 */
+#define EXTI_INTF_INTF17                        ((uint32_t)0x00020000) /* Pending bit for line 17 */
+#define EXTI_INTF_INTF18                        ((uint32_t)0x00040000) /* Pending bit for line 18 */
+#define EXTI_INTF_INTF19                        ((uint32_t)0x00080000) /* Pending bit for line 19 */
+
+/******************************************************************************/
+/*                      FLASH and Option Bytes Registers                      */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACTLR register  ******************/
+#define FLASH_ACTLR_LATENCY                     ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */
+#define FLASH_ACTLR_LATENCY_0                   ((uint8_t)0x00) /* Bit 0 */
+#define FLASH_ACTLR_LATENCY_1                   ((uint8_t)0x01) /* Bit 0 */
+#define FLASH_ACTLR_LATENCY_2                   ((uint8_t)0x02) /* Bit 1 */
+
+#define FLASH_ACTLR_HLFCYA                      ((uint8_t)0x08) /* Flash Half Cycle Access Enable */
+#define FLASH_ACTLR_PRFTBE                      ((uint8_t)0x10) /* Prefetch Buffer Enable */
+#define FLASH_ACTLR_PRFTBS                      ((uint8_t)0x20) /* Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define FLASH_KEYR_FKEYR                        ((uint32_t)0xFFFFFFFF) /* FPEC Key */
+
+/*****************  Bit definition for FLASH_OBKEYR register  ****************/
+#define FLASH_OBKEYR_OBKEYR                     ((uint32_t)0xFFFFFFFF) /* Option Byte Key */
+
+/******************  Bit definition for FLASH_STATR register  *******************/
+#define FLASH_STATR_BSY                         ((uint8_t)0x01) /* Busy */
+#define FLASH_STATR_PGERR                       ((uint8_t)0x04) /* Programming Error */
+#define FLASH_STATR_WRPRTERR                    ((uint8_t)0x10) /* Write Protection Error */
+#define FLASH_STATR_EOP                         ((uint8_t)0x20) /* End of operation */
+
+/*******************  Bit definition for FLASH_CTLR register  *******************/
+#define FLASH_CTLR_PG                           ((uint16_t)0x0001)     /* Programming */
+#define FLASH_CTLR_PER                          ((uint16_t)0x0002)     /* Page Erase */
+#define FLASH_CTLR_MER                          ((uint16_t)0x0004)     /* Mass Erase */
+#define FLASH_CTLR_OPTPG                        ((uint16_t)0x0010)     /* Option Byte Programming */
+#define FLASH_CTLR_OPTER                        ((uint16_t)0x0020)     /* Option Byte Erase */
+#define FLASH_CTLR_STRT                         ((uint16_t)0x0040)     /* Start */
+#define FLASH_CTLR_LOCK                         ((uint16_t)0x0080)     /* Lock */
+#define FLASH_CTLR_OPTWRE                       ((uint16_t)0x0200)     /* Option Bytes Write Enable */
+#define FLASH_CTLR_ERRIE                        ((uint16_t)0x0400)     /* Error Interrupt Enable */
+#define FLASH_CTLR_EOPIE                        ((uint16_t)0x1000)     /* End of operation interrupt enable */
+#define FLASH_CTLR_PAGE_PG                      ((uint16_t)0x00010000) /* Page Programming 128Byte */
+#define FLASH_CTLR_PAGE_ER                      ((uint16_t)0x00020000) /* Page Erase 128Byte */
+#define FLASH_CTLR_BUF_LOAD                     ((uint16_t)0x00040000) /* Buffer Load */
+#define FLASH_CTLR_BUF_RST                      ((uint16_t)0x00080000) /* Buffer Reset */
+
+/*******************  Bit definition for FLASH_ADDR register  *******************/
+#define FLASH_ADDR_FAR                          ((uint32_t)0xFFFFFFFF) /* Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define FLASH_OBR_OPTERR                        ((uint16_t)0x0001) /* Option Byte Error */
+#define FLASH_OBR_RDPRT                         ((uint16_t)0x0002) /* Read protection */
+
+#define FLASH_OBR_USER                          ((uint16_t)0x03FC) /* User Option Bytes */
+#define FLASH_OBR_WDG_SW                        ((uint16_t)0x0004) /* WDG_SW */
+#define FLASH_OBR_nRST_STOP                     ((uint16_t)0x0008) /* nRST_STOP */
+#define FLASH_OBR_nRST_STDBY                    ((uint16_t)0x0010) /* nRST_STDBY */
+#define FLASH_OBR_BFB2                          ((uint16_t)0x0020) /* BFB2 */
+
+/******************  Bit definition for FLASH_WPR register  ******************/
+#define FLASH_WPR_WRP                           ((uint32_t)0xFFFFFFFF) /* Write Protect */
+
+/******************  Bit definition for FLASH_RDPR register  *******************/
+#define FLASH_RDPR_RDPR                         ((uint32_t)0x000000FF) /* Read protection option byte */
+#define FLASH_RDPR_nRDPR                        ((uint32_t)0x0000FF00) /* Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define FLASH_USER_USER                         ((uint32_t)0x00FF0000) /* User option byte */
+#define FLASH_USER_nUSER                        ((uint32_t)0xFF000000) /* User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define FLASH_Data0_Data0                       ((uint32_t)0x000000FF) /* User data storage option byte */
+#define FLASH_Data0_nData0                      ((uint32_t)0x0000FF00) /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define FLASH_Data1_Data1                       ((uint32_t)0x00FF0000) /* User data storage option byte */
+#define FLASH_Data1_nData1                      ((uint32_t)0xFF000000) /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRPR0 register  ******************/
+#define FLASH_WRPR0_WRPR0                       ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
+#define FLASH_WRPR0_nWRPR0                      ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR1 register  ******************/
+#define FLASH_WRPR1_WRPR1                       ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
+#define FLASH_WRPR1_nWRPR1                      ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR2 register  ******************/
+#define FLASH_WRPR2_WRPR2                       ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
+#define FLASH_WRPR2_nWRPR2                      ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR3 register  ******************/
+#define FLASH_WRPR3_WRPR3                       ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
+#define FLASH_WRPR3_nWRPR3                      ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                General Purpose and Alternate Function I/O                  */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CFGLR register  *******************/
+#define GPIO_CFGLR_MODE                         ((uint32_t)0x33333333) /* Port x mode bits */
+
+#define GPIO_CFGLR_MODE0                        ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CFGLR_MODE0_0                      ((uint32_t)0x00000001) /* Bit 0 */
+#define GPIO_CFGLR_MODE0_1                      ((uint32_t)0x00000002) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE1                        ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CFGLR_MODE1_0                      ((uint32_t)0x00000010) /* Bit 0 */
+#define GPIO_CFGLR_MODE1_1                      ((uint32_t)0x00000020) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE2                        ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CFGLR_MODE2_0                      ((uint32_t)0x00000100) /* Bit 0 */
+#define GPIO_CFGLR_MODE2_1                      ((uint32_t)0x00000200) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE3                        ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CFGLR_MODE3_0                      ((uint32_t)0x00001000) /* Bit 0 */
+#define GPIO_CFGLR_MODE3_1                      ((uint32_t)0x00002000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE4                        ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CFGLR_MODE4_0                      ((uint32_t)0x00010000) /* Bit 0 */
+#define GPIO_CFGLR_MODE4_1                      ((uint32_t)0x00020000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE5                        ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CFGLR_MODE5_0                      ((uint32_t)0x00100000) /* Bit 0 */
+#define GPIO_CFGLR_MODE5_1                      ((uint32_t)0x00200000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE6                        ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CFGLR_MODE6_0                      ((uint32_t)0x01000000) /* Bit 0 */
+#define GPIO_CFGLR_MODE6_1                      ((uint32_t)0x02000000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE7                        ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CFGLR_MODE7_0                      ((uint32_t)0x10000000) /* Bit 0 */
+#define GPIO_CFGLR_MODE7_1                      ((uint32_t)0x20000000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF                          ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
+
+#define GPIO_CFGLR_CNF0                         ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CFGLR_CNF0_0                       ((uint32_t)0x00000004) /* Bit 0 */
+#define GPIO_CFGLR_CNF0_1                       ((uint32_t)0x00000008) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF1                         ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CFGLR_CNF1_0                       ((uint32_t)0x00000040) /* Bit 0 */
+#define GPIO_CFGLR_CNF1_1                       ((uint32_t)0x00000080) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF2                         ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CFGLR_CNF2_0                       ((uint32_t)0x00000400) /* Bit 0 */
+#define GPIO_CFGLR_CNF2_1                       ((uint32_t)0x00000800) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF3                         ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CFGLR_CNF3_0                       ((uint32_t)0x00004000) /* Bit 0 */
+#define GPIO_CFGLR_CNF3_1                       ((uint32_t)0x00008000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF4                         ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CFGLR_CNF4_0                       ((uint32_t)0x00040000) /* Bit 0 */
+#define GPIO_CFGLR_CNF4_1                       ((uint32_t)0x00080000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF5                         ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CFGLR_CNF5_0                       ((uint32_t)0x00400000) /* Bit 0 */
+#define GPIO_CFGLR_CNF5_1                       ((uint32_t)0x00800000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF6                         ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CFGLR_CNF6_0                       ((uint32_t)0x04000000) /* Bit 0 */
+#define GPIO_CFGLR_CNF6_1                       ((uint32_t)0x08000000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF7                         ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CFGLR_CNF7_0                       ((uint32_t)0x40000000) /* Bit 0 */
+#define GPIO_CFGLR_CNF7_1                       ((uint32_t)0x80000000) /* Bit 1 */
+
+/*******************  Bit definition for GPIO_CFGHR register  *******************/
+#define GPIO_CFGHR_MODE                         ((uint32_t)0x33333333) /* Port x mode bits */
+
+#define GPIO_CFGHR_MODE8                        ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CFGHR_MODE8_0                      ((uint32_t)0x00000001) /* Bit 0 */
+#define GPIO_CFGHR_MODE8_1                      ((uint32_t)0x00000002) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE9                        ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CFGHR_MODE9_0                      ((uint32_t)0x00000010) /* Bit 0 */
+#define GPIO_CFGHR_MODE9_1                      ((uint32_t)0x00000020) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE10                       ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CFGHR_MODE10_0                     ((uint32_t)0x00000100) /* Bit 0 */
+#define GPIO_CFGHR_MODE10_1                     ((uint32_t)0x00000200) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE11                       ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CFGHR_MODE11_0                     ((uint32_t)0x00001000) /* Bit 0 */
+#define GPIO_CFGHR_MODE11_1                     ((uint32_t)0x00002000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE12                       ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CFGHR_MODE12_0                     ((uint32_t)0x00010000) /* Bit 0 */
+#define GPIO_CFGHR_MODE12_1                     ((uint32_t)0x00020000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE13                       ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CFGHR_MODE13_0                     ((uint32_t)0x00100000) /* Bit 0 */
+#define GPIO_CFGHR_MODE13_1                     ((uint32_t)0x00200000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE14                       ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CFGHR_MODE14_0                     ((uint32_t)0x01000000) /* Bit 0 */
+#define GPIO_CFGHR_MODE14_1                     ((uint32_t)0x02000000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE15                       ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CFGHR_MODE15_0                     ((uint32_t)0x10000000) /* Bit 0 */
+#define GPIO_CFGHR_MODE15_1                     ((uint32_t)0x20000000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF                          ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
+
+#define GPIO_CFGHR_CNF8                         ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CFGHR_CNF8_0                       ((uint32_t)0x00000004) /* Bit 0 */
+#define GPIO_CFGHR_CNF8_1                       ((uint32_t)0x00000008) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF9                         ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CFGHR_CNF9_0                       ((uint32_t)0x00000040) /* Bit 0 */
+#define GPIO_CFGHR_CNF9_1                       ((uint32_t)0x00000080) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF10                        ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CFGHR_CNF10_0                      ((uint32_t)0x00000400) /* Bit 0 */
+#define GPIO_CFGHR_CNF10_1                      ((uint32_t)0x00000800) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF11                        ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CFGHR_CNF11_0                      ((uint32_t)0x00004000) /* Bit 0 */
+#define GPIO_CFGHR_CNF11_1                      ((uint32_t)0x00008000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF12                        ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CFGHR_CNF12_0                      ((uint32_t)0x00040000) /* Bit 0 */
+#define GPIO_CFGHR_CNF12_1                      ((uint32_t)0x00080000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF13                        ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CFGHR_CNF13_0                      ((uint32_t)0x00400000) /* Bit 0 */
+#define GPIO_CFGHR_CNF13_1                      ((uint32_t)0x00800000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF14                        ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CFGHR_CNF14_0                      ((uint32_t)0x04000000) /* Bit 0 */
+#define GPIO_CFGHR_CNF14_1                      ((uint32_t)0x08000000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF15                        ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CFGHR_CNF15_0                      ((uint32_t)0x40000000) /* Bit 0 */
+#define GPIO_CFGHR_CNF15_1                      ((uint32_t)0x80000000) /* Bit 1 */
+
+/*******************  Bit definition for GPIO_INDR register  *******************/
+#define GPIO_INDR_IDR0                          ((uint16_t)0x0001) /* Port input data, bit 0 */
+#define GPIO_INDR_IDR1                          ((uint16_t)0x0002) /* Port input data, bit 1 */
+#define GPIO_INDR_IDR2                          ((uint16_t)0x0004) /* Port input data, bit 2 */
+#define GPIO_INDR_IDR3                          ((uint16_t)0x0008) /* Port input data, bit 3 */
+#define GPIO_INDR_IDR4                          ((uint16_t)0x0010) /* Port input data, bit 4 */
+#define GPIO_INDR_IDR5                          ((uint16_t)0x0020) /* Port input data, bit 5 */
+#define GPIO_INDR_IDR6                          ((uint16_t)0x0040) /* Port input data, bit 6 */
+#define GPIO_INDR_IDR7                          ((uint16_t)0x0080) /* Port input data, bit 7 */
+#define GPIO_INDR_IDR8                          ((uint16_t)0x0100) /* Port input data, bit 8 */
+#define GPIO_INDR_IDR9                          ((uint16_t)0x0200) /* Port input data, bit 9 */
+#define GPIO_INDR_IDR10                         ((uint16_t)0x0400) /* Port input data, bit 10 */
+#define GPIO_INDR_IDR11                         ((uint16_t)0x0800) /* Port input data, bit 11 */
+#define GPIO_INDR_IDR12                         ((uint16_t)0x1000) /* Port input data, bit 12 */
+#define GPIO_INDR_IDR13                         ((uint16_t)0x2000) /* Port input data, bit 13 */
+#define GPIO_INDR_IDR14                         ((uint16_t)0x4000) /* Port input data, bit 14 */
+#define GPIO_INDR_IDR15                         ((uint16_t)0x8000) /* Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_OUTDR register  *******************/
+#define GPIO_OUTDR_ODR0                         ((uint16_t)0x0001) /* Port output data, bit 0 */
+#define GPIO_OUTDR_ODR1                         ((uint16_t)0x0002) /* Port output data, bit 1 */
+#define GPIO_OUTDR_ODR2                         ((uint16_t)0x0004) /* Port output data, bit 2 */
+#define GPIO_OUTDR_ODR3                         ((uint16_t)0x0008) /* Port output data, bit 3 */
+#define GPIO_OUTDR_ODR4                         ((uint16_t)0x0010) /* Port output data, bit 4 */
+#define GPIO_OUTDR_ODR5                         ((uint16_t)0x0020) /* Port output data, bit 5 */
+#define GPIO_OUTDR_ODR6                         ((uint16_t)0x0040) /* Port output data, bit 6 */
+#define GPIO_OUTDR_ODR7                         ((uint16_t)0x0080) /* Port output data, bit 7 */
+#define GPIO_OUTDR_ODR8                         ((uint16_t)0x0100) /* Port output data, bit 8 */
+#define GPIO_OUTDR_ODR9                         ((uint16_t)0x0200) /* Port output data, bit 9 */
+#define GPIO_OUTDR_ODR10                        ((uint16_t)0x0400) /* Port output data, bit 10 */
+#define GPIO_OUTDR_ODR11                        ((uint16_t)0x0800) /* Port output data, bit 11 */
+#define GPIO_OUTDR_ODR12                        ((uint16_t)0x1000) /* Port output data, bit 12 */
+#define GPIO_OUTDR_ODR13                        ((uint16_t)0x2000) /* Port output data, bit 13 */
+#define GPIO_OUTDR_ODR14                        ((uint16_t)0x4000) /* Port output data, bit 14 */
+#define GPIO_OUTDR_ODR15                        ((uint16_t)0x8000) /* Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSHR register  *******************/
+#define GPIO_BSHR_BS0                           ((uint32_t)0x00000001) /* Port x Set bit 0 */
+#define GPIO_BSHR_BS1                           ((uint32_t)0x00000002) /* Port x Set bit 1 */
+#define GPIO_BSHR_BS2                           ((uint32_t)0x00000004) /* Port x Set bit 2 */
+#define GPIO_BSHR_BS3                           ((uint32_t)0x00000008) /* Port x Set bit 3 */
+#define GPIO_BSHR_BS4                           ((uint32_t)0x00000010) /* Port x Set bit 4 */
+#define GPIO_BSHR_BS5                           ((uint32_t)0x00000020) /* Port x Set bit 5 */
+#define GPIO_BSHR_BS6                           ((uint32_t)0x00000040) /* Port x Set bit 6 */
+#define GPIO_BSHR_BS7                           ((uint32_t)0x00000080) /* Port x Set bit 7 */
+#define GPIO_BSHR_BS8                           ((uint32_t)0x00000100) /* Port x Set bit 8 */
+#define GPIO_BSHR_BS9                           ((uint32_t)0x00000200) /* Port x Set bit 9 */
+#define GPIO_BSHR_BS10                          ((uint32_t)0x00000400) /* Port x Set bit 10 */
+#define GPIO_BSHR_BS11                          ((uint32_t)0x00000800) /* Port x Set bit 11 */
+#define GPIO_BSHR_BS12                          ((uint32_t)0x00001000) /* Port x Set bit 12 */
+#define GPIO_BSHR_BS13                          ((uint32_t)0x00002000) /* Port x Set bit 13 */
+#define GPIO_BSHR_BS14                          ((uint32_t)0x00004000) /* Port x Set bit 14 */
+#define GPIO_BSHR_BS15                          ((uint32_t)0x00008000) /* Port x Set bit 15 */
+
+#define GPIO_BSHR_BR0                           ((uint32_t)0x00010000) /* Port x Reset bit 0 */
+#define GPIO_BSHR_BR1                           ((uint32_t)0x00020000) /* Port x Reset bit 1 */
+#define GPIO_BSHR_BR2                           ((uint32_t)0x00040000) /* Port x Reset bit 2 */
+#define GPIO_BSHR_BR3                           ((uint32_t)0x00080000) /* Port x Reset bit 3 */
+#define GPIO_BSHR_BR4                           ((uint32_t)0x00100000) /* Port x Reset bit 4 */
+#define GPIO_BSHR_BR5                           ((uint32_t)0x00200000) /* Port x Reset bit 5 */
+#define GPIO_BSHR_BR6                           ((uint32_t)0x00400000) /* Port x Reset bit 6 */
+#define GPIO_BSHR_BR7                           ((uint32_t)0x00800000) /* Port x Reset bit 7 */
+#define GPIO_BSHR_BR8                           ((uint32_t)0x01000000) /* Port x Reset bit 8 */
+#define GPIO_BSHR_BR9                           ((uint32_t)0x02000000) /* Port x Reset bit 9 */
+#define GPIO_BSHR_BR10                          ((uint32_t)0x04000000) /* Port x Reset bit 10 */
+#define GPIO_BSHR_BR11                          ((uint32_t)0x08000000) /* Port x Reset bit 11 */
+#define GPIO_BSHR_BR12                          ((uint32_t)0x10000000) /* Port x Reset bit 12 */
+#define GPIO_BSHR_BR13                          ((uint32_t)0x20000000) /* Port x Reset bit 13 */
+#define GPIO_BSHR_BR14                          ((uint32_t)0x40000000) /* Port x Reset bit 14 */
+#define GPIO_BSHR_BR15                          ((uint32_t)0x80000000) /* Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BCR register  *******************/
+#define GPIO_BCR_BR0                            ((uint16_t)0x0001) /* Port x Reset bit 0 */
+#define GPIO_BCR_BR1                            ((uint16_t)0x0002) /* Port x Reset bit 1 */
+#define GPIO_BCR_BR2                            ((uint16_t)0x0004) /* Port x Reset bit 2 */
+#define GPIO_BCR_BR3                            ((uint16_t)0x0008) /* Port x Reset bit 3 */
+#define GPIO_BCR_BR4                            ((uint16_t)0x0010) /* Port x Reset bit 4 */
+#define GPIO_BCR_BR5                            ((uint16_t)0x0020) /* Port x Reset bit 5 */
+#define GPIO_BCR_BR6                            ((uint16_t)0x0040) /* Port x Reset bit 6 */
+#define GPIO_BCR_BR7                            ((uint16_t)0x0080) /* Port x Reset bit 7 */
+#define GPIO_BCR_BR8                            ((uint16_t)0x0100) /* Port x Reset bit 8 */
+#define GPIO_BCR_BR9                            ((uint16_t)0x0200) /* Port x Reset bit 9 */
+#define GPIO_BCR_BR10                           ((uint16_t)0x0400) /* Port x Reset bit 10 */
+#define GPIO_BCR_BR11                           ((uint16_t)0x0800) /* Port x Reset bit 11 */
+#define GPIO_BCR_BR12                           ((uint16_t)0x1000) /* Port x Reset bit 12 */
+#define GPIO_BCR_BR13                           ((uint16_t)0x2000) /* Port x Reset bit 13 */
+#define GPIO_BCR_BR14                           ((uint16_t)0x4000) /* Port x Reset bit 14 */
+#define GPIO_BCR_BR15                           ((uint16_t)0x8000) /* Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCK0                               ((uint32_t)0x00000001) /* Port x Lock bit 0 */
+#define GPIO_LCK1                               ((uint32_t)0x00000002) /* Port x Lock bit 1 */
+#define GPIO_LCK2                               ((uint32_t)0x00000004) /* Port x Lock bit 2 */
+#define GPIO_LCK3                               ((uint32_t)0x00000008) /* Port x Lock bit 3 */
+#define GPIO_LCK4                               ((uint32_t)0x00000010) /* Port x Lock bit 4 */
+#define GPIO_LCK5                               ((uint32_t)0x00000020) /* Port x Lock bit 5 */
+#define GPIO_LCK6                               ((uint32_t)0x00000040) /* Port x Lock bit 6 */
+#define GPIO_LCK7                               ((uint32_t)0x00000080) /* Port x Lock bit 7 */
+#define GPIO_LCK8                               ((uint32_t)0x00000100) /* Port x Lock bit 8 */
+#define GPIO_LCK9                               ((uint32_t)0x00000200) /* Port x Lock bit 9 */
+#define GPIO_LCK10                              ((uint32_t)0x00000400) /* Port x Lock bit 10 */
+#define GPIO_LCK11                              ((uint32_t)0x00000800) /* Port x Lock bit 11 */
+#define GPIO_LCK12                              ((uint32_t)0x00001000) /* Port x Lock bit 12 */
+#define GPIO_LCK13                              ((uint32_t)0x00002000) /* Port x Lock bit 13 */
+#define GPIO_LCK14                              ((uint32_t)0x00004000) /* Port x Lock bit 14 */
+#define GPIO_LCK15                              ((uint32_t)0x00008000) /* Port x Lock bit 15 */
+#define GPIO_LCKK                               ((uint32_t)0x00010000) /* Lock key */
+
+/******************  Bit definition for AFIO_ECR register  *******************/
+#define AFIO_ECR_PIN                            ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */
+#define AFIO_ECR_PIN_0                          ((uint8_t)0x01) /* Bit 0 */
+#define AFIO_ECR_PIN_1                          ((uint8_t)0x02) /* Bit 1 */
+#define AFIO_ECR_PIN_2                          ((uint8_t)0x04) /* Bit 2 */
+#define AFIO_ECR_PIN_3                          ((uint8_t)0x08) /* Bit 3 */
+
+#define AFIO_ECR_PIN_PX0                        ((uint8_t)0x00) /* Pin 0 selected */
+#define AFIO_ECR_PIN_PX1                        ((uint8_t)0x01) /* Pin 1 selected */
+#define AFIO_ECR_PIN_PX2                        ((uint8_t)0x02) /* Pin 2 selected */
+#define AFIO_ECR_PIN_PX3                        ((uint8_t)0x03) /* Pin 3 selected */
+#define AFIO_ECR_PIN_PX4                        ((uint8_t)0x04) /* Pin 4 selected */
+#define AFIO_ECR_PIN_PX5                        ((uint8_t)0x05) /* Pin 5 selected */
+#define AFIO_ECR_PIN_PX6                        ((uint8_t)0x06) /* Pin 6 selected */
+#define AFIO_ECR_PIN_PX7                        ((uint8_t)0x07) /* Pin 7 selected */
+#define AFIO_ECR_PIN_PX8                        ((uint8_t)0x08) /* Pin 8 selected */
+#define AFIO_ECR_PIN_PX9                        ((uint8_t)0x09) /* Pin 9 selected */
+#define AFIO_ECR_PIN_PX10                       ((uint8_t)0x0A) /* Pin 10 selected */
+#define AFIO_ECR_PIN_PX11                       ((uint8_t)0x0B) /* Pin 11 selected */
+#define AFIO_ECR_PIN_PX12                       ((uint8_t)0x0C) /* Pin 12 selected */
+#define AFIO_ECR_PIN_PX13                       ((uint8_t)0x0D) /* Pin 13 selected */
+#define AFIO_ECR_PIN_PX14                       ((uint8_t)0x0E) /* Pin 14 selected */
+#define AFIO_ECR_PIN_PX15                       ((uint8_t)0x0F) /* Pin 15 selected */
+
+#define AFIO_ECR_PORT                           ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */
+#define AFIO_ECR_PORT_0                         ((uint8_t)0x10) /* Bit 0 */
+#define AFIO_ECR_PORT_1                         ((uint8_t)0x20) /* Bit 1 */
+#define AFIO_ECR_PORT_2                         ((uint8_t)0x40) /* Bit 2 */
+
+#define AFIO_ECR_PORT_PA                        ((uint8_t)0x00) /* Port A selected */
+#define AFIO_ECR_PORT_PB                        ((uint8_t)0x10) /* Port B selected */
+#define AFIO_ECR_PORT_PC                        ((uint8_t)0x20) /* Port C selected */
+#define AFIO_ECR_PORT_PD                        ((uint8_t)0x30) /* Port D selected */
+#define AFIO_ECR_PORT_PE                        ((uint8_t)0x40) /* Port E selected */
+
+#define AFIO_ECR_EVOE                           ((uint8_t)0x80) /* Event Output Enable */
+
+/******************  Bit definition for AFIO_PCFR1register  *******************/
+#define AFIO_PCFR1_SPI1_REMAP                   ((uint32_t)0x00000001) /* SPI1 remapping */
+#define AFIO_PCFR1_I2C1_REMAP                   ((uint32_t)0x00000002) /* I2C1 remapping */
+#define AFIO_PCFR1_USART1_REMAP                 ((uint32_t)0x00000004) /* USART1 remapping */
+#define AFIO_PCFR1_USART2_REMAP                 ((uint32_t)0x00000008) /* USART2 remapping */
+
+#define AFIO_PCFR1_USART3_REMAP                 ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_PCFR1_USART3_REMAP_0               ((uint32_t)0x00000010) /* Bit 0 */
+#define AFIO_PCFR1_USART3_REMAP_1               ((uint32_t)0x00000020) /* Bit 1 */
+
+#define AFIO_PCFR1_USART3_REMAP_NOREMAP         ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP    ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_FULLREMAP       ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_PCFR1_TIM1_REMAP                   ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_PCFR1_TIM1_REMAP_0                 ((uint32_t)0x00000040) /* Bit 0 */
+#define AFIO_PCFR1_TIM1_REMAP_1                 ((uint32_t)0x00000080) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM1_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP      ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP         ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_PCFR1_TIM2_REMAP                   ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_PCFR1_TIM2_REMAP_0                 ((uint32_t)0x00000100) /* Bit 0 */
+#define AFIO_PCFR1_TIM2_REMAP_1                 ((uint32_t)0x00000200) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM2_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1     ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2     ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP         ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_PCFR1_TIM3_REMAP                   ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_PCFR1_TIM3_REMAP_0                 ((uint32_t)0x00000400) /* Bit 0 */
+#define AFIO_PCFR1_TIM3_REMAP_1                 ((uint32_t)0x00000800) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM3_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP      ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP         ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_PCFR1_TIM4_REMAP                   ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_PCFR1_CAN_REMAP                    ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_PCFR1_CAN_REMAP_0                  ((uint32_t)0x00002000) /* Bit 0 */
+#define AFIO_PCFR1_CAN_REMAP_1                  ((uint32_t)0x00004000) /* Bit 1 */
+
+#define AFIO_PCFR1_CAN_REMAP_REMAP1             ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP2             ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP3             ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_PCFR1_PD01_REMAP                   ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCFR1_TIM5CH4_IREMAP               ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */
+#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP           ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC1_ETRGREG_REMAP           ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP           ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGREG_REMAP           ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
+
+#define AFIO_PCFR1_SWJ_CFG                      ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_PCFR1_SWJ_CFG_0                    ((uint32_t)0x01000000) /* Bit 0 */
+#define AFIO_PCFR1_SWJ_CFG_1                    ((uint32_t)0x02000000) /* Bit 1 */
+#define AFIO_PCFR1_SWJ_CFG_2                    ((uint32_t)0x04000000) /* Bit 2 */
+
+#define AFIO_PCFR1_SWJ_CFG_RESET                ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_PCFR1_SWJ_CFG_NOJNTRST             ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE          ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_PCFR1_SWJ_CFG_DISABLE              ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                      ((uint16_t)0x000F) /* EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                      ((uint16_t)0x00F0) /* EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                      ((uint16_t)0x0F00) /* EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                      ((uint16_t)0xF000) /* EXTI 3 configuration */
+
+#define AFIO_EXTICR1_EXTI0_PA                   ((uint16_t)0x0000) /* PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                   ((uint16_t)0x0001) /* PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                   ((uint16_t)0x0002) /* PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                   ((uint16_t)0x0003) /* PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                   ((uint16_t)0x0004) /* PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                   ((uint16_t)0x0005) /* PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                   ((uint16_t)0x0006) /* PG[0] pin */
+
+#define AFIO_EXTICR1_EXTI1_PA                   ((uint16_t)0x0000) /* PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                   ((uint16_t)0x0010) /* PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                   ((uint16_t)0x0020) /* PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                   ((uint16_t)0x0030) /* PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                   ((uint16_t)0x0040) /* PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                   ((uint16_t)0x0050) /* PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                   ((uint16_t)0x0060) /* PG[1] pin */
+
+#define AFIO_EXTICR1_EXTI2_PA                   ((uint16_t)0x0000) /* PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                   ((uint16_t)0x0100) /* PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                   ((uint16_t)0x0200) /* PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                   ((uint16_t)0x0300) /* PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                   ((uint16_t)0x0400) /* PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                   ((uint16_t)0x0500) /* PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                   ((uint16_t)0x0600) /* PG[2] pin */
+
+#define AFIO_EXTICR1_EXTI3_PA                   ((uint16_t)0x0000) /* PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                   ((uint16_t)0x1000) /* PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                   ((uint16_t)0x2000) /* PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                   ((uint16_t)0x3000) /* PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                   ((uint16_t)0x4000) /* PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                   ((uint16_t)0x5000) /* PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                   ((uint16_t)0x6000) /* PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                      ((uint16_t)0x000F) /* EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                      ((uint16_t)0x00F0) /* EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                      ((uint16_t)0x0F00) /* EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                      ((uint16_t)0xF000) /* EXTI 7 configuration */
+
+#define AFIO_EXTICR2_EXTI4_PA                   ((uint16_t)0x0000) /* PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                   ((uint16_t)0x0001) /* PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                   ((uint16_t)0x0002) /* PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                   ((uint16_t)0x0003) /* PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                   ((uint16_t)0x0004) /* PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                   ((uint16_t)0x0005) /* PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                   ((uint16_t)0x0006) /* PG[4] pin */
+
+#define AFIO_EXTICR2_EXTI5_PA                   ((uint16_t)0x0000) /* PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                   ((uint16_t)0x0010) /* PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                   ((uint16_t)0x0020) /* PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                   ((uint16_t)0x0030) /* PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                   ((uint16_t)0x0040) /* PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                   ((uint16_t)0x0050) /* PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                   ((uint16_t)0x0060) /* PG[5] pin */
+
+#define AFIO_EXTICR2_EXTI6_PA                   ((uint16_t)0x0000) /* PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                   ((uint16_t)0x0100) /* PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                   ((uint16_t)0x0200) /* PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                   ((uint16_t)0x0300) /* PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                   ((uint16_t)0x0400) /* PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                   ((uint16_t)0x0500) /* PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                   ((uint16_t)0x0600) /* PG[6] pin */
+
+#define AFIO_EXTICR2_EXTI7_PA                   ((uint16_t)0x0000) /* PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                   ((uint16_t)0x1000) /* PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                   ((uint16_t)0x2000) /* PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                   ((uint16_t)0x3000) /* PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                   ((uint16_t)0x4000) /* PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                   ((uint16_t)0x5000) /* PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                   ((uint16_t)0x6000) /* PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                      ((uint16_t)0x000F) /* EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                      ((uint16_t)0x00F0) /* EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                     ((uint16_t)0x0F00) /* EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                     ((uint16_t)0xF000) /* EXTI 11 configuration */
+
+#define AFIO_EXTICR3_EXTI8_PA                   ((uint16_t)0x0000) /* PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                   ((uint16_t)0x0001) /* PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                   ((uint16_t)0x0002) /* PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                   ((uint16_t)0x0003) /* PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                   ((uint16_t)0x0004) /* PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                   ((uint16_t)0x0005) /* PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                   ((uint16_t)0x0006) /* PG[8] pin */
+
+#define AFIO_EXTICR3_EXTI9_PA                   ((uint16_t)0x0000) /* PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                   ((uint16_t)0x0010) /* PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                   ((uint16_t)0x0020) /* PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                   ((uint16_t)0x0030) /* PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                   ((uint16_t)0x0040) /* PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                   ((uint16_t)0x0050) /* PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                   ((uint16_t)0x0060) /* PG[9] pin */
+
+#define AFIO_EXTICR3_EXTI10_PA                  ((uint16_t)0x0000) /* PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB                  ((uint16_t)0x0100) /* PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC                  ((uint16_t)0x0200) /* PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD                  ((uint16_t)0x0300) /* PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE                  ((uint16_t)0x0400) /* PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF                  ((uint16_t)0x0500) /* PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG                  ((uint16_t)0x0600) /* PG[10] pin */
+
+#define AFIO_EXTICR3_EXTI11_PA                  ((uint16_t)0x0000) /* PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB                  ((uint16_t)0x1000) /* PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC                  ((uint16_t)0x2000) /* PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD                  ((uint16_t)0x3000) /* PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE                  ((uint16_t)0x4000) /* PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF                  ((uint16_t)0x5000) /* PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG                  ((uint16_t)0x6000) /* PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                     ((uint16_t)0x000F) /* EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                     ((uint16_t)0x00F0) /* EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                     ((uint16_t)0x0F00) /* EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                     ((uint16_t)0xF000) /* EXTI 15 configuration */
+
+#define AFIO_EXTICR4_EXTI12_PA                  ((uint16_t)0x0000) /* PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB                  ((uint16_t)0x0001) /* PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC                  ((uint16_t)0x0002) /* PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD                  ((uint16_t)0x0003) /* PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE                  ((uint16_t)0x0004) /* PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF                  ((uint16_t)0x0005) /* PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG                  ((uint16_t)0x0006) /* PG[12] pin */
+
+#define AFIO_EXTICR4_EXTI13_PA                  ((uint16_t)0x0000) /* PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB                  ((uint16_t)0x0010) /* PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC                  ((uint16_t)0x0020) /* PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD                  ((uint16_t)0x0030) /* PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE                  ((uint16_t)0x0040) /* PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF                  ((uint16_t)0x0050) /* PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG                  ((uint16_t)0x0060) /* PG[13] pin */
+
+#define AFIO_EXTICR4_EXTI14_PA                  ((uint16_t)0x0000) /* PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB                  ((uint16_t)0x0100) /* PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC                  ((uint16_t)0x0200) /* PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD                  ((uint16_t)0x0300) /* PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE                  ((uint16_t)0x0400) /* PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF                  ((uint16_t)0x0500) /* PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG                  ((uint16_t)0x0600) /* PG[14] pin */
+
+#define AFIO_EXTICR4_EXTI15_PA                  ((uint16_t)0x0000) /* PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB                  ((uint16_t)0x1000) /* PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC                  ((uint16_t)0x2000) /* PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD                  ((uint16_t)0x3000) /* PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE                  ((uint16_t)0x4000) /* PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF                  ((uint16_t)0x5000) /* PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG                  ((uint16_t)0x6000) /* PG[15] pin */
+
+/******************************************************************************/
+/*                           Independent WATCHDOG                             */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_CTLR register  ********************/
+#define IWDG_KEY                                ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PSCR register  ********************/
+#define IWDG_PR                                 ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */
+#define IWDG_PR_0                               ((uint8_t)0x01) /* Bit 0 */
+#define IWDG_PR_1                               ((uint8_t)0x02) /* Bit 1 */
+#define IWDG_PR_2                               ((uint8_t)0x04) /* Bit 2 */
+
+/*******************  Bit definition for IWDG_RLDR register  *******************/
+#define IWDG_RL                                 ((uint16_t)0x0FFF) /* Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STATR register  ********************/
+#define IWDG_PVU                                ((uint8_t)0x01) /* Watchdog prescaler value update */
+#define IWDG_RVU                                ((uint8_t)0x02) /* Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                      Inter-integrated Circuit Interface                    */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTLR1 register  ********************/
+#define I2C_CTLR1_PE                            ((uint16_t)0x0001) /* Peripheral Enable */
+#define I2C_CTLR1_SMBUS                         ((uint16_t)0x0002) /* SMBus Mode */
+#define I2C_CTLR1_SMBTYPE                       ((uint16_t)0x0008) /* SMBus Type */
+#define I2C_CTLR1_ENARP                         ((uint16_t)0x0010) /* ARP Enable */
+#define I2C_CTLR1_ENPEC                         ((uint16_t)0x0020) /* PEC Enable */
+#define I2C_CTLR1_ENGC                          ((uint16_t)0x0040) /* General Call Enable */
+#define I2C_CTLR1_NOSTRETCH                     ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */
+#define I2C_CTLR1_START                         ((uint16_t)0x0100) /* Start Generation */
+#define I2C_CTLR1_STOP                          ((uint16_t)0x0200) /* Stop Generation */
+#define I2C_CTLR1_ACK                           ((uint16_t)0x0400) /* Acknowledge Enable */
+#define I2C_CTLR1_POS                           ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
+#define I2C_CTLR1_PEC                           ((uint16_t)0x1000) /* Packet Error Checking */
+#define I2C_CTLR1_ALERT                         ((uint16_t)0x2000) /* SMBus Alert */
+#define I2C_CTLR1_SWRST                         ((uint16_t)0x8000) /* Software Reset */
+
+/*******************  Bit definition for I2C_CTLR2 register  ********************/
+#define I2C_CTLR2_FREQ                          ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTLR2_FREQ_0                        ((uint16_t)0x0001) /* Bit 0 */
+#define I2C_CTLR2_FREQ_1                        ((uint16_t)0x0002) /* Bit 1 */
+#define I2C_CTLR2_FREQ_2                        ((uint16_t)0x0004) /* Bit 2 */
+#define I2C_CTLR2_FREQ_3                        ((uint16_t)0x0008) /* Bit 3 */
+#define I2C_CTLR2_FREQ_4                        ((uint16_t)0x0010) /* Bit 4 */
+#define I2C_CTLR2_FREQ_5                        ((uint16_t)0x0020) /* Bit 5 */
+
+#define I2C_CTLR2_ITERREN                       ((uint16_t)0x0100) /* Error Interrupt Enable */
+#define I2C_CTLR2_ITEVTEN                       ((uint16_t)0x0200) /* Event Interrupt Enable */
+#define I2C_CTLR2_ITBUFEN                       ((uint16_t)0x0400) /* Buffer Interrupt Enable */
+#define I2C_CTLR2_DMAEN                         ((uint16_t)0x0800) /* DMA Requests Enable */
+#define I2C_CTLR2_LAST                          ((uint16_t)0x1000) /* DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define I2C_OADDR1_ADD1_7                       ((uint16_t)0x00FE) /* Interface Address */
+#define I2C_OADDR1_ADD8_9                       ((uint16_t)0x0300) /* Interface Address */
+
+#define I2C_OADDR1_ADD0                         ((uint16_t)0x0001) /* Bit 0 */
+#define I2C_OADDR1_ADD1                         ((uint16_t)0x0002) /* Bit 1 */
+#define I2C_OADDR1_ADD2                         ((uint16_t)0x0004) /* Bit 2 */
+#define I2C_OADDR1_ADD3                         ((uint16_t)0x0008) /* Bit 3 */
+#define I2C_OADDR1_ADD4                         ((uint16_t)0x0010) /* Bit 4 */
+#define I2C_OADDR1_ADD5                         ((uint16_t)0x0020) /* Bit 5 */
+#define I2C_OADDR1_ADD6                         ((uint16_t)0x0040) /* Bit 6 */
+#define I2C_OADDR1_ADD7                         ((uint16_t)0x0080) /* Bit 7 */
+#define I2C_OADDR1_ADD8                         ((uint16_t)0x0100) /* Bit 8 */
+#define I2C_OADDR1_ADD9                         ((uint16_t)0x0200) /* Bit 9 */
+
+#define I2C_OADDR1_ADDMODE                      ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define I2C_OADDR2_ENDUAL                       ((uint8_t)0x01) /* Dual addressing mode enable */
+#define I2C_OADDR2_ADD2                         ((uint8_t)0xFE) /* Interface address */
+
+/********************  Bit definition for I2C_DATAR register  ********************/
+#define I2C_DR_DATAR                            ((uint8_t)0xFF) /* 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STAR1 register  ********************/
+#define I2C_STAR1_SB                            ((uint16_t)0x0001) /* Start Bit (Master mode) */
+#define I2C_STAR1_ADDR                          ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */
+#define I2C_STAR1_BTF                           ((uint16_t)0x0004) /* Byte Transfer Finished */
+#define I2C_STAR1_ADD10                         ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */
+#define I2C_STAR1_STOPF                         ((uint16_t)0x0010) /* Stop detection (Slave mode) */
+#define I2C_STAR1_RXNE                          ((uint16_t)0x0040) /* Data Register not Empty (receivers) */
+#define I2C_STAR1_TXE                           ((uint16_t)0x0080) /* Data Register Empty (transmitters) */
+#define I2C_STAR1_BERR                          ((uint16_t)0x0100) /* Bus Error */
+#define I2C_STAR1_ARLO                          ((uint16_t)0x0200) /* Arbitration Lost (master mode) */
+#define I2C_STAR1_AF                            ((uint16_t)0x0400) /* Acknowledge Failure */
+#define I2C_STAR1_OVR                           ((uint16_t)0x0800) /* Overrun/Underrun */
+#define I2C_STAR1_PECERR                        ((uint16_t)0x1000) /* PEC Error in reception */
+#define I2C_STAR1_TIMEOUT                       ((uint16_t)0x4000) /* Timeout or Tlow Error */
+#define I2C_STAR1_SMBALERT                      ((uint16_t)0x8000) /* SMBus Alert */
+
+/*******************  Bit definition for I2C_STAR2 register  ********************/
+#define I2C_STAR2_MSL                           ((uint16_t)0x0001) /* Master/Slave */
+#define I2C_STAR2_BUSY                          ((uint16_t)0x0002) /* Bus Busy */
+#define I2C_STAR2_TRA                           ((uint16_t)0x0004) /* Transmitter/Receiver */
+#define I2C_STAR2_GENCALL                       ((uint16_t)0x0010) /* General Call Address (Slave mode) */
+#define I2C_STAR2_SMBDEFAULT                    ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */
+#define I2C_STAR2_SMBHOST                       ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */
+#define I2C_STAR2_DUALF                         ((uint16_t)0x0080) /* Dual Flag (Slave mode) */
+#define I2C_STAR2_PEC                           ((uint16_t)0xFF00) /* Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CKCFGR register  ********************/
+#define I2C_CKCFGR_CCR                          ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CKCFGR_DUTY                         ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
+#define I2C_CKCFGR_FS                           ((uint16_t)0x8000) /* I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_RTR register  *******************/
+#define I2C_RTR_TRISE                           ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                             Power Control                                  */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CTLR register  ********************/
+#define PWR_CTLR_LPDS                           ((uint16_t)0x0001) /* Low-Power Deepsleep */
+#define PWR_CTLR_PDDS                           ((uint16_t)0x0002) /* Power Down Deepsleep */
+#define PWR_CTLR_CWUF                           ((uint16_t)0x0004) /* Clear Wakeup Flag */
+#define PWR_CTLR_CSBF                           ((uint16_t)0x0008) /* Clear Standby Flag */
+#define PWR_CTLR_PVDE                           ((uint16_t)0x0010) /* Power Voltage Detector Enable */
+
+#define PWR_CTLR_PLS                            ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CTLR_PLS_0                          ((uint16_t)0x0020) /* Bit 0 */
+#define PWR_CTLR_PLS_1                          ((uint16_t)0x0040) /* Bit 1 */
+#define PWR_CTLR_PLS_2                          ((uint16_t)0x0080) /* Bit 2 */
+
+#define PWR_CTLR_PLS_2V2                        ((uint16_t)0x0000) /* PVD level 2.2V */
+#define PWR_CTLR_PLS_2V3                        ((uint16_t)0x0020) /* PVD level 2.3V */
+#define PWR_CTLR_PLS_2V4                        ((uint16_t)0x0040) /* PVD level 2.4V */
+#define PWR_CTLR_PLS_2V5                        ((uint16_t)0x0060) /* PVD level 2.5V */
+#define PWR_CTLR_PLS_2V6                        ((uint16_t)0x0080) /* PVD level 2.6V */
+#define PWR_CTLR_PLS_2V7                        ((uint16_t)0x00A0) /* PVD level 2.7V */
+#define PWR_CTLR_PLS_2V8                        ((uint16_t)0x00C0) /* PVD level 2.8V */
+#define PWR_CTLR_PLS_2V9                        ((uint16_t)0x00E0) /* PVD level 2.9V */
+
+#define PWR_CTLR_DBP                            ((uint16_t)0x0100) /* Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF                             ((uint16_t)0x0001) /* Wakeup Flag */
+#define PWR_CSR_SBF                             ((uint16_t)0x0002) /* Standby Flag */
+#define PWR_CSR_PVDO                            ((uint16_t)0x0004) /* PVD Output */
+#define PWR_CSR_EWUP                            ((uint16_t)0x0100) /* Enable WKUP pin */
+
+/******************************************************************************/
+/*                         Reset and Clock Control                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTLR register  ********************/
+#define RCC_HSION                               ((uint32_t)0x00000001) /* Internal High Speed clock enable */
+#define RCC_HSIRDY                              ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */
+#define RCC_HSITRIM                             ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */
+#define RCC_HSICAL                              ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */
+#define RCC_HSEON                               ((uint32_t)0x00010000) /* External High Speed clock enable */
+#define RCC_HSERDY                              ((uint32_t)0x00020000) /* External High Speed clock ready flag */
+#define RCC_HSEBYP                              ((uint32_t)0x00040000) /* External High Speed clock Bypass */
+#define RCC_CSSON                               ((uint32_t)0x00080000) /* Clock Security System enable */
+#define RCC_PLLON                               ((uint32_t)0x01000000) /* PLL enable */
+#define RCC_PLLRDY                              ((uint32_t)0x02000000) /* PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR0 register  *******************/
+#define RCC_SW                                  ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
+#define RCC_SW_0                                ((uint32_t)0x00000001) /* Bit 0 */
+#define RCC_SW_1                                ((uint32_t)0x00000002) /* Bit 1 */
+
+#define RCC_SW_HSI                              ((uint32_t)0x00000000) /* HSI selected as system clock */
+#define RCC_SW_HSE                              ((uint32_t)0x00000001) /* HSE selected as system clock */
+#define RCC_SW_PLL                              ((uint32_t)0x00000002) /* PLL selected as system clock */
+
+#define RCC_SWS                                 ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_SWS_0                               ((uint32_t)0x00000004) /* Bit 0 */
+#define RCC_SWS_1                               ((uint32_t)0x00000008) /* Bit 1 */
+
+#define RCC_SWS_HSI                             ((uint32_t)0x00000000) /* HSI oscillator used as system clock */
+#define RCC_SWS_HSE                             ((uint32_t)0x00000004) /* HSE oscillator used as system clock */
+#define RCC_SWS_PLL                             ((uint32_t)0x00000008) /* PLL used as system clock */
+
+#define RCC_HPRE                                ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
+#define RCC_HPRE_0                              ((uint32_t)0x00000010) /* Bit 0 */
+#define RCC_HPRE_1                              ((uint32_t)0x00000020) /* Bit 1 */
+#define RCC_HPRE_2                              ((uint32_t)0x00000040) /* Bit 2 */
+#define RCC_HPRE_3                              ((uint32_t)0x00000080) /* Bit 3 */
+
+#define RCC_HPRE_DIV1                           ((uint32_t)0x00000000) /* SYSCLK not divided */
+#define RCC_HPRE_DIV2                           ((uint32_t)0x00000080) /* SYSCLK divided by 2 */
+#define RCC_HPRE_DIV4                           ((uint32_t)0x00000090) /* SYSCLK divided by 4 */
+#define RCC_HPRE_DIV8                           ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */
+#define RCC_HPRE_DIV16                          ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */
+#define RCC_HPRE_DIV64                          ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */
+#define RCC_HPRE_DIV128                         ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */
+#define RCC_HPRE_DIV256                         ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */
+#define RCC_HPRE_DIV512                         ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */
+
+#define RCC_PPRE1                               ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_PPRE1_0                             ((uint32_t)0x00000100) /* Bit 0 */
+#define RCC_PPRE1_1                             ((uint32_t)0x00000200) /* Bit 1 */
+#define RCC_PPRE1_2                             ((uint32_t)0x00000400) /* Bit 2 */
+
+#define RCC_PPRE1_DIV1                          ((uint32_t)0x00000000) /* HCLK not divided */
+#define RCC_PPRE1_DIV2                          ((uint32_t)0x00000400) /* HCLK divided by 2 */
+#define RCC_PPRE1_DIV4                          ((uint32_t)0x00000500) /* HCLK divided by 4 */
+#define RCC_PPRE1_DIV8                          ((uint32_t)0x00000600) /* HCLK divided by 8 */
+#define RCC_PPRE1_DIV16                         ((uint32_t)0x00000700) /* HCLK divided by 16 */
+
+#define RCC_PPRE2                               ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_PPRE2_0                             ((uint32_t)0x00000800) /* Bit 0 */
+#define RCC_PPRE2_1                             ((uint32_t)0x00001000) /* Bit 1 */
+#define RCC_PPRE2_2                             ((uint32_t)0x00002000) /* Bit 2 */
+
+#define RCC_PPRE2_DIV1                          ((uint32_t)0x00000000) /* HCLK not divided */
+#define RCC_PPRE2_DIV2                          ((uint32_t)0x00002000) /* HCLK divided by 2 */
+#define RCC_PPRE2_DIV4                          ((uint32_t)0x00002800) /* HCLK divided by 4 */
+#define RCC_PPRE2_DIV8                          ((uint32_t)0x00003000) /* HCLK divided by 8 */
+#define RCC_PPRE2_DIV16                         ((uint32_t)0x00003800) /* HCLK divided by 16 */
+
+#define RCC_ADCPRE                              ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_ADCPRE_0                            ((uint32_t)0x00004000) /* Bit 0 */
+#define RCC_ADCPRE_1                            ((uint32_t)0x00008000) /* Bit 1 */
+
+#define RCC_ADCPRE_DIV2                         ((uint32_t)0x00000000) /* PCLK2 divided by 2 */
+#define RCC_ADCPRE_DIV4                         ((uint32_t)0x00004000) /* PCLK2 divided by 4 */
+#define RCC_ADCPRE_DIV6                         ((uint32_t)0x00008000) /* PCLK2 divided by 6 */
+#define RCC_ADCPRE_DIV8                         ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */
+
+#define RCC_PLLSRC                              ((uint32_t)0x00010000) /* PLL entry clock source */
+
+#define RCC_PLLXTPRE                            ((uint32_t)0x00020000) /* HSE divider for PLL entry */
+
+#define RCC_PLLMULL                             ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_PLLMULL_0                           ((uint32_t)0x00040000) /* Bit 0 */
+#define RCC_PLLMULL_1                           ((uint32_t)0x00080000) /* Bit 1 */
+#define RCC_PLLMULL_2                           ((uint32_t)0x00100000) /* Bit 2 */
+#define RCC_PLLMULL_3                           ((uint32_t)0x00200000) /* Bit 3 */
+
+#define RCC_PLLSRC_HSI_Div2                     ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_PLLSRC_HSE                          ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */
+
+#define RCC_PLLXTPRE_HSE                        ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */
+#define RCC_PLLXTPRE_HSE_Div2                   ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */
+
+#define RCC_PLLMULL2                            ((uint32_t)0x00000000) /* PLL input clock*2 */
+#define RCC_PLLMULL3                            ((uint32_t)0x00040000) /* PLL input clock*3 */
+#define RCC_PLLMULL4                            ((uint32_t)0x00080000) /* PLL input clock*4 */
+#define RCC_PLLMULL5                            ((uint32_t)0x000C0000) /* PLL input clock*5 */
+#define RCC_PLLMULL6                            ((uint32_t)0x00100000) /* PLL input clock*6 */
+#define RCC_PLLMULL7                            ((uint32_t)0x00140000) /* PLL input clock*7 */
+#define RCC_PLLMULL8                            ((uint32_t)0x00180000) /* PLL input clock*8 */
+#define RCC_PLLMULL9                            ((uint32_t)0x001C0000) /* PLL input clock*9 */
+#define RCC_PLLMULL10                           ((uint32_t)0x00200000) /* PLL input clock10 */
+#define RCC_PLLMULL11                           ((uint32_t)0x00240000) /* PLL input clock*11 */
+#define RCC_PLLMULL12                           ((uint32_t)0x00280000) /* PLL input clock*12 */
+#define RCC_PLLMULL13                           ((uint32_t)0x002C0000) /* PLL input clock*13 */
+#define RCC_PLLMULL14                           ((uint32_t)0x00300000) /* PLL input clock*14 */
+#define RCC_PLLMULL15                           ((uint32_t)0x00340000) /* PLL input clock*15 */
+#define RCC_PLLMULL16                           ((uint32_t)0x00380000) /* PLL input clock*16 */
+#define RCC_USBPRE                              ((uint32_t)0x00400000) /* USB Device prescaler */
+
+#define RCC_CFGR0_MCO                           ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_MCO_0                               ((uint32_t)0x01000000) /* Bit 0 */
+#define RCC_MCO_1                               ((uint32_t)0x02000000) /* Bit 1 */
+#define RCC_MCO_2                               ((uint32_t)0x04000000) /* Bit 2 */
+
+#define RCC_MCO_NOCLOCK                         ((uint32_t)0x00000000) /* No clock */
+#define RCC_CFGR0_MCO_SYSCLK                    ((uint32_t)0x04000000) /* System clock selected as MCO source */
+#define RCC_CFGR0_MCO_HSI                       ((uint32_t)0x05000000) /* HSI clock selected as MCO source */
+#define RCC_CFGR0_MCO_HSE                       ((uint32_t)0x06000000) /* HSE clock selected as MCO source  */
+#define RCC_CFGR0_MCO_PLL                       ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */
+
+/*******************  Bit definition for RCC_INTR register  ********************/
+#define RCC_LSIRDYF                             ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */
+#define RCC_LSERDYF                             ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */
+#define RCC_HSIRDYF                             ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */
+#define RCC_HSERDYF                             ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */
+#define RCC_PLLRDYF                             ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */
+#define RCC_CSSF                                ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */
+#define RCC_LSIRDYIE                            ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */
+#define RCC_LSERDYIE                            ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */
+#define RCC_HSIRDYIE                            ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */
+#define RCC_HSERDYIE                            ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */
+#define RCC_PLLRDYIE                            ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */
+#define RCC_LSIRDYC                             ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */
+#define RCC_LSERDYC                             ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */
+#define RCC_HSIRDYC                             ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */
+#define RCC_HSERDYC                             ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */
+#define RCC_PLLRDYC                             ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */
+#define RCC_CSSC                                ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2PRSTR register  *****************/
+#define RCC_AFIORST                             ((uint32_t)0x00000001) /* Alternate Function I/O reset */
+#define RCC_IOPARST                             ((uint32_t)0x00000004) /* I/O port A reset */
+#define RCC_IOPBRST                             ((uint32_t)0x00000008) /* I/O port B reset */
+#define RCC_IOPCRST                             ((uint32_t)0x00000010) /* I/O port C reset */
+#define RCC_IOPDRST                             ((uint32_t)0x00000020) /* I/O port D reset */
+#define RCC_ADC1RST                             ((uint32_t)0x00000200) /* ADC 1 interface reset */
+
+#define RCC_ADC2RST                             ((uint32_t)0x00000400) /* ADC 2 interface reset */
+
+#define RCC_TIM1RST                             ((uint32_t)0x00000800) /* TIM1 Timer reset */
+#define RCC_SPI1RST                             ((uint32_t)0x00001000) /* SPI 1 reset */
+#define RCC_USART1RST                           ((uint32_t)0x00004000) /* USART1 reset */
+
+#define RCC_IOPERST                             ((uint32_t)0x00000040) /* I/O port E reset */
+
+/*****************  Bit definition for RCC_APB1PRSTR register  *****************/
+#define RCC_TIM2RST                             ((uint32_t)0x00000001) /* Timer 2 reset */
+#define RCC_TIM3RST                             ((uint32_t)0x00000002) /* Timer 3 reset */
+#define RCC_WWDGRST                             ((uint32_t)0x00000800) /* Window Watchdog reset */
+#define RCC_USART2RST                           ((uint32_t)0x00020000) /* USART 2 reset */
+#define RCC_I2C1RST                             ((uint32_t)0x00200000) /* I2C 1 reset */
+
+#define RCC_CAN1RST                             ((uint32_t)0x02000000) /* CAN1 reset */
+
+#define RCC_BKPRST                              ((uint32_t)0x08000000) /* Backup interface reset */
+#define RCC_PWRRST                              ((uint32_t)0x10000000) /* Power interface reset */
+
+#define RCC_TIM4RST                             ((uint32_t)0x00000004) /* Timer 4 reset */
+#define RCC_SPI2RST                             ((uint32_t)0x00004000) /* SPI 2 reset */
+#define RCC_USART3RST                           ((uint32_t)0x00040000) /* USART 3 reset */
+#define RCC_I2C2RST                             ((uint32_t)0x00400000) /* I2C 2 reset */
+
+#define RCC_USBRST                              ((uint32_t)0x00800000) /* USB Device reset */
+
+/******************  Bit definition for RCC_AHBPCENR register  ******************/
+#define RCC_DMA1EN                              ((uint16_t)0x0001) /* DMA1 clock enable */
+#define RCC_SRAMEN                              ((uint16_t)0x0004) /* SRAM interface clock enable */
+#define RCC_FLITFEN                             ((uint16_t)0x0010) /* FLITF clock enable */
+#define RCC_CRCEN                               ((uint16_t)0x0040) /* CRC clock enable */
+#define RCC_USBHD                               ((uint16_t)0x1000)
+
+/******************  Bit definition for RCC_APB2PCENR register  *****************/
+#define RCC_AFIOEN                              ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
+#define RCC_IOPAEN                              ((uint32_t)0x00000004) /* I/O port A clock enable */
+#define RCC_IOPBEN                              ((uint32_t)0x00000008) /* I/O port B clock enable */
+#define RCC_IOPCEN                              ((uint32_t)0x00000010) /* I/O port C clock enable */
+#define RCC_IOPDEN                              ((uint32_t)0x00000020) /* I/O port D clock enable */
+#define RCC_ADC1EN                              ((uint32_t)0x00000200) /* ADC 1 interface clock enable */
+
+#define RCC_ADC2EN                              ((uint32_t)0x00000400) /* ADC 2 interface clock enable */
+
+#define RCC_TIM1EN                              ((uint32_t)0x00000800) /* TIM1 Timer clock enable */
+#define RCC_SPI1EN                              ((uint32_t)0x00001000) /* SPI 1 clock enable */
+#define RCC_USART1EN                            ((uint32_t)0x00004000) /* USART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1PCENR register  ******************/
+#define RCC_TIM2EN                              ((uint32_t)0x00000001) /* Timer 2 clock enabled*/
+#define RCC_TIM3EN                              ((uint32_t)0x00000002) /* Timer 3 clock enable */
+#define RCC_WWDGEN                              ((uint32_t)0x00000800) /* Window Watchdog clock enable */
+#define RCC_USART2EN                            ((uint32_t)0x00020000) /* USART 2 clock enable */
+#define RCC_I2C1EN                              ((uint32_t)0x00200000) /* I2C 1 clock enable */
+
+#define RCC_BKPEN                               ((uint32_t)0x08000000) /* Backup interface clock enable */
+#define RCC_PWREN                               ((uint32_t)0x10000000) /* Power interface clock enable */
+
+#define RCC_USBEN                               ((uint32_t)0x00800000) /* USB Device clock enable */
+
+/*******************  Bit definition for RCC_BDCTLR register  *******************/
+#define RCC_LSEON                               ((uint32_t)0x00000001) /* External Low Speed oscillator enable */
+#define RCC_LSERDY                              ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */
+#define RCC_LSEBYP                              ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */
+
+#define RCC_RTCSEL                              ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_RTCSEL_0                            ((uint32_t)0x00000100) /* Bit 0 */
+#define RCC_RTCSEL_1                            ((uint32_t)0x00000200) /* Bit 1 */
+
+#define RCC_RTCSEL_NOCLOCK                      ((uint32_t)0x00000000) /* No clock */
+#define RCC_RTCSEL_LSE                          ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */
+#define RCC_RTCSEL_LSI                          ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */
+#define RCC_RTCSEL_HSE                          ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_RTCEN                               ((uint32_t)0x00008000) /* RTC clock enable */
+#define RCC_BDRST                               ((uint32_t)0x00010000) /* Backup domain software reset  */
+
+/*******************  Bit definition for RCC_RSTSCKR register  ********************/
+#define RCC_LSION                               ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
+#define RCC_LSIRDY                              ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
+#define RCC_RMVF                                ((uint32_t)0x01000000) /* Remove reset flag */
+#define RCC_PINRSTF                             ((uint32_t)0x04000000) /* PIN reset flag */
+#define RCC_PORRSTF                             ((uint32_t)0x08000000) /* POR/PDR reset flag */
+#define RCC_SFTRSTF                             ((uint32_t)0x10000000) /* Software Reset flag */
+#define RCC_IWDGRSTF                            ((uint32_t)0x20000000) /* Independent Watchdog reset flag */
+#define RCC_WWDGRSTF                            ((uint32_t)0x40000000) /* Window watchdog reset flag */
+#define RCC_LPWRRSTF                            ((uint32_t)0x80000000) /* Low-Power reset flag */
+
+/******************************************************************************/
+/*                             Real-Time Clock                                */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CTLRH register  ********************/
+#define RTC_CTLRH_SECIE                         ((uint8_t)0x01) /* Second Interrupt Enable */
+#define RTC_CTLRH_ALRIE                         ((uint8_t)0x02) /* Alarm Interrupt Enable */
+#define RTC_CTLRH_OWIE                          ((uint8_t)0x04) /* OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CTLRL register  ********************/
+#define RTC_CTLRL_SECF                          ((uint8_t)0x01) /* Second Flag */
+#define RTC_CTLRL_ALRF                          ((uint8_t)0x02) /* Alarm Flag */
+#define RTC_CTLRL_OWF                           ((uint8_t)0x04) /* OverfloW Flag */
+#define RTC_CTLRL_RSF                           ((uint8_t)0x08) /* Registers Synchronized Flag */
+#define RTC_CTLRL_CNF                           ((uint8_t)0x10) /* Configuration Flag */
+#define RTC_CTLRL_RTOFF                         ((uint8_t)0x20) /* RTC operation OFF */
+
+/*******************  Bit definition for RTC_PSCH register  *******************/
+#define RTC_PSCH_PRL                            ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define RTC_PSCL_PRL                            ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define RTC_DIVH_RTC_DIV                        ((uint16_t)0x000F) /* RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define RTC_DIVL_RTC_DIV                        ((uint16_t)0xFFFF) /* RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define RTC_CNTH_RTC_CNT                        ((uint16_t)0xFFFF) /* RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define RTC_CNTL_RTC_CNT                        ((uint16_t)0xFFFF) /* RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRMH register  *******************/
+#define RTC_ALRMH_RTC_ALRM                      ((uint16_t)0xFFFF) /* RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRML register  *******************/
+#define RTC_ALRML_RTC_ALRM                      ((uint16_t)0xFFFF) /* RTC Alarm Low */
+
+/******************************************************************************/
+/*                        Serial Peripheral Interface                         */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTLR1 register  ********************/
+#define SPI_CTLR1_CPHA                          ((uint16_t)0x0001) /* Clock Phase */
+#define SPI_CTLR1_CPOL                          ((uint16_t)0x0002) /* Clock Polarity */
+#define SPI_CTLR1_MSTR                          ((uint16_t)0x0004) /* Master Selection */
+
+#define SPI_CTLR1_BR                            ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTLR1_BR_0                          ((uint16_t)0x0008) /* Bit 0 */
+#define SPI_CTLR1_BR_1                          ((uint16_t)0x0010) /* Bit 1 */
+#define SPI_CTLR1_BR_2                          ((uint16_t)0x0020) /* Bit 2 */
+
+#define SPI_CTLR1_SPE                           ((uint16_t)0x0040) /* SPI Enable */
+#define SPI_CTLR1_LSBFIRST                      ((uint16_t)0x0080) /* Frame Format */
+#define SPI_CTLR1_SSI                           ((uint16_t)0x0100) /* Internal slave select */
+#define SPI_CTLR1_SSM                           ((uint16_t)0x0200) /* Software slave management */
+#define SPI_CTLR1_RXONLY                        ((uint16_t)0x0400) /* Receive only */
+#define SPI_CTLR1_DFF                           ((uint16_t)0x0800) /* Data Frame Format */
+#define SPI_CTLR1_CRCNEXT                       ((uint16_t)0x1000) /* Transmit CRC next */
+#define SPI_CTLR1_CRCEN                         ((uint16_t)0x2000) /* Hardware CRC calculation enable */
+#define SPI_CTLR1_BIDIOE                        ((uint16_t)0x4000) /* Output enable in bidirectional mode */
+#define SPI_CTLR1_BIDIMODE                      ((uint16_t)0x8000) /* Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTLR2 register  ********************/
+#define SPI_CTLR2_RXDMAEN                       ((uint8_t)0x01) /* Rx Buffer DMA Enable */
+#define SPI_CTLR2_TXDMAEN                       ((uint8_t)0x02) /* Tx Buffer DMA Enable */
+#define SPI_CTLR2_SSOE                          ((uint8_t)0x04) /* SS Output Enable */
+#define SPI_CTLR2_ERRIE                         ((uint8_t)0x20) /* Error Interrupt Enable */
+#define SPI_CTLR2_RXNEIE                        ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */
+#define SPI_CTLR2_TXEIE                         ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_STATR register  ********************/
+#define SPI_STATR_RXNE                          ((uint8_t)0x01) /* Receive buffer Not Empty */
+#define SPI_STATR_TXE                           ((uint8_t)0x02) /* Transmit buffer Empty */
+#define SPI_STATR_CHSIDE                        ((uint8_t)0x04) /* Channel side */
+#define SPI_STATR_UDR                           ((uint8_t)0x08) /* Underrun flag */
+#define SPI_STATR_CRCERR                        ((uint8_t)0x10) /* CRC Error flag */
+#define SPI_STATR_MODF                          ((uint8_t)0x20) /* Mode fault */
+#define SPI_STATR_OVR                           ((uint8_t)0x40) /* Overrun flag */
+#define SPI_STATR_BSY                           ((uint8_t)0x80) /* Busy flag */
+
+/********************  Bit definition for SPI_DATAR register  ********************/
+#define SPI_DATAR_DR                            ((uint16_t)0xFFFF) /* Data Register */
+
+/*******************  Bit definition for SPI_CRCR register  ******************/
+#define SPI_CRCR_CRCPOLY                        ((uint16_t)0xFFFF) /* CRC polynomial register */
+
+/******************  Bit definition for SPI_RCRCR register  ******************/
+#define SPI_RCRCR_RXCRC                         ((uint16_t)0xFFFF) /* Rx CRC Register */
+
+/******************  Bit definition for SPI_TCRCR register  ******************/
+#define SPI_TCRCR_TXCRC                         ((uint16_t)0xFFFF) /* Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN                       ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN                      ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0                    ((uint16_t)0x0002) /* Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1                    ((uint16_t)0x0004) /* Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL                       ((uint16_t)0x0008) /* steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD                      ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0                    ((uint16_t)0x0010) /* Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1                    ((uint16_t)0x0020) /* Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC                     ((uint16_t)0x0080) /* PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG                      ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                    ((uint16_t)0x0100) /* Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1                    ((uint16_t)0x0200) /* Bit 1 */
+
+#define SPI_I2SCFGR_I2SE                        ((uint16_t)0x0400) /* I2S Enable */
+#define SPI_I2SCFGR_I2SMOD                      ((uint16_t)0x0800) /* I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV                        ((uint16_t)0x00FF) /* I2S Linear prescaler */
+#define SPI_I2SPR_ODD                           ((uint16_t)0x0100) /* Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE                         ((uint16_t)0x0200) /* Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                    TIM                                     */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CTLR1 register  ********************/
+#define TIM_CEN                                 ((uint16_t)0x0001) /* Counter enable */
+#define TIM_UDIS                                ((uint16_t)0x0002) /* Update disable */
+#define TIM_URS                                 ((uint16_t)0x0004) /* Update request source */
+#define TIM_OPM                                 ((uint16_t)0x0008) /* One pulse mode */
+#define TIM_DIR                                 ((uint16_t)0x0010) /* Direction */
+
+#define TIM_CMS                                 ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CMS_0                               ((uint16_t)0x0020) /* Bit 0 */
+#define TIM_CMS_1                               ((uint16_t)0x0040) /* Bit 1 */
+
+#define TIM_ARPE                                ((uint16_t)0x0080) /* Auto-reload preload enable */
+
+#define TIM_CTLR1_CKD                           ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */
+#define TIM_CKD_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CKD_1                               ((uint16_t)0x0200) /* Bit 1 */
+
+/*******************  Bit definition for TIM_CTLR2 register  ********************/
+#define TIM_CCPC                                ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */
+#define TIM_CCUS                                ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */
+#define TIM_CCDS                                ((uint16_t)0x0008) /* Capture/Compare DMA Selection */
+
+#define TIM_MMS                                 ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
+#define TIM_MMS_0                               ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_MMS_1                               ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_MMS_2                               ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_TI1S                                ((uint16_t)0x0080) /* TI1 Selection */
+#define TIM_OIS1                                ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */
+#define TIM_OIS1N                               ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */
+#define TIM_OIS2                                ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */
+#define TIM_OIS2N                               ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */
+#define TIM_OIS3                                ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */
+#define TIM_OIS3N                               ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */
+#define TIM_OIS4                                ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCFGR register  *******************/
+#define TIM_SMS                                 ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMS_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_SMS_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_SMS_2                               ((uint16_t)0x0004) /* Bit 2 */
+
+#define TIM_TS                                  ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */
+#define TIM_TS_0                                ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_TS_1                                ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_TS_2                                ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_MSM                                 ((uint16_t)0x0080) /* Master/slave mode */
+
+#define TIM_ETF                                 ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */
+#define TIM_ETF_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_ETF_1                               ((uint16_t)0x0200) /* Bit 1 */
+#define TIM_ETF_2                               ((uint16_t)0x0400) /* Bit 2 */
+#define TIM_ETF_3                               ((uint16_t)0x0800) /* Bit 3 */
+
+#define TIM_ETPS                                ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_ETPS_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_ETPS_1                              ((uint16_t)0x2000) /* Bit 1 */
+
+#define TIM_ECE                                 ((uint16_t)0x4000) /* External clock enable */
+#define TIM_ETP                                 ((uint16_t)0x8000) /* External trigger polarity */
+
+/*******************  Bit definition for TIM_DMAINTENR register  *******************/
+#define TIM_UIE                                 ((uint16_t)0x0001) /* Update interrupt enable */
+#define TIM_CC1IE                               ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */
+#define TIM_CC2IE                               ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */
+#define TIM_CC3IE                               ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */
+#define TIM_CC4IE                               ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */
+#define TIM_COMIE                               ((uint16_t)0x0020) /* COM interrupt enable */
+#define TIM_TIE                                 ((uint16_t)0x0040) /* Trigger interrupt enable */
+#define TIM_BIE                                 ((uint16_t)0x0080) /* Break interrupt enable */
+#define TIM_UDE                                 ((uint16_t)0x0100) /* Update DMA request enable */
+#define TIM_CC1DE                               ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */
+#define TIM_CC2DE                               ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */
+#define TIM_CC3DE                               ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */
+#define TIM_CC4DE                               ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */
+#define TIM_COMDE                               ((uint16_t)0x2000) /* COM DMA request enable */
+#define TIM_TDE                                 ((uint16_t)0x4000) /* Trigger DMA request enable */
+
+/********************  Bit definition for TIM_INTFR register  ********************/
+#define TIM_UIF                                 ((uint16_t)0x0001) /* Update interrupt Flag */
+#define TIM_CC1IF                               ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */
+#define TIM_CC2IF                               ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */
+#define TIM_CC3IF                               ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */
+#define TIM_CC4IF                               ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */
+#define TIM_COMIF                               ((uint16_t)0x0020) /* COM interrupt Flag */
+#define TIM_TIF                                 ((uint16_t)0x0040) /* Trigger interrupt Flag */
+#define TIM_BIF                                 ((uint16_t)0x0080) /* Break interrupt Flag */
+#define TIM_CC1OF                               ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */
+#define TIM_CC2OF                               ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */
+#define TIM_CC3OF                               ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */
+#define TIM_CC4OF                               ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_SWEVGR register  ********************/
+#define TIM_UG                                  ((uint8_t)0x01) /* Update Generation */
+#define TIM_CC1G                                ((uint8_t)0x02) /* Capture/Compare 1 Generation */
+#define TIM_CC2G                                ((uint8_t)0x04) /* Capture/Compare 2 Generation */
+#define TIM_CC3G                                ((uint8_t)0x08) /* Capture/Compare 3 Generation */
+#define TIM_CC4G                                ((uint8_t)0x10) /* Capture/Compare 4 Generation */
+#define TIM_COMG                                ((uint8_t)0x20) /* Capture/Compare Control Update Generation */
+#define TIM_TG                                  ((uint8_t)0x40) /* Trigger Generation */
+#define TIM_BG                                  ((uint8_t)0x80) /* Break Generation */
+
+/******************  Bit definition for TIM_CHCTLR1 register  *******************/
+#define TIM_CC1S                                ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CC1S_0                              ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_CC1S_1                              ((uint16_t)0x0002) /* Bit 1 */
+
+#define TIM_OC1FE                               ((uint16_t)0x0004) /* Output Compare 1 Fast enable */
+#define TIM_OC1PE                               ((uint16_t)0x0008) /* Output Compare 1 Preload enable */
+
+#define TIM_OC1M                                ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_OC1M_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_OC1M_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_OC1M_2                              ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_OC1CE                               ((uint16_t)0x0080) /* Output Compare 1Clear Enable */
+
+#define TIM_CC2S                                ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CC2S_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CC2S_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OC2FE                               ((uint16_t)0x0400) /* Output Compare 2 Fast enable */
+#define TIM_OC2PE                               ((uint16_t)0x0800) /* Output Compare 2 Preload enable */
+
+#define TIM_OC2M                                ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_OC2M_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_OC2M_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_OC2M_2                              ((uint16_t)0x4000) /* Bit 2 */
+
+#define TIM_OC2CE                               ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */
+
+#define TIM_IC1PSC                              ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_IC1PSC_0                            ((uint16_t)0x0004) /* Bit 0 */
+#define TIM_IC1PSC_1                            ((uint16_t)0x0008) /* Bit 1 */
+
+#define TIM_IC1F                                ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_IC1F_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_IC1F_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_IC1F_2                              ((uint16_t)0x0040) /* Bit 2 */
+#define TIM_IC1F_3                              ((uint16_t)0x0080) /* Bit 3 */
+
+#define TIM_IC2PSC                              ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_IC2PSC_0                            ((uint16_t)0x0400) /* Bit 0 */
+#define TIM_IC2PSC_1                            ((uint16_t)0x0800) /* Bit 1 */
+
+#define TIM_IC2F                                ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_IC2F_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_IC2F_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_IC2F_2                              ((uint16_t)0x4000) /* Bit 2 */
+#define TIM_IC2F_3                              ((uint16_t)0x8000) /* Bit 3 */
+
+/******************  Bit definition for TIM_CHCTLR2 register  *******************/
+#define TIM_CC3S                                ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CC3S_0                              ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_CC3S_1                              ((uint16_t)0x0002) /* Bit 1 */
+
+#define TIM_OC3FE                               ((uint16_t)0x0004) /* Output Compare 3 Fast enable */
+#define TIM_OC3PE                               ((uint16_t)0x0008) /* Output Compare 3 Preload enable */
+
+#define TIM_OC3M                                ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_OC3M_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_OC3M_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_OC3M_2                              ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_OC3CE                               ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */
+
+#define TIM_CC4S                                ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CC4S_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CC4S_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OC4FE                               ((uint16_t)0x0400) /* Output Compare 4 Fast enable */
+#define TIM_OC4PE                               ((uint16_t)0x0800) /* Output Compare 4 Preload enable */
+
+#define TIM_OC4M                                ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_OC4M_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_OC4M_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_OC4M_2                              ((uint16_t)0x4000) /* Bit 2 */
+
+#define TIM_OC4CE                               ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */
+
+#define TIM_IC3PSC                              ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_IC3PSC_0                            ((uint16_t)0x0004) /* Bit 0 */
+#define TIM_IC3PSC_1                            ((uint16_t)0x0008) /* Bit 1 */
+
+#define TIM_IC3F                                ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_IC3F_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_IC3F_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_IC3F_2                              ((uint16_t)0x0040) /* Bit 2 */
+#define TIM_IC3F_3                              ((uint16_t)0x0080) /* Bit 3 */
+
+#define TIM_IC4PSC                              ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_IC4PSC_0                            ((uint16_t)0x0400) /* Bit 0 */
+#define TIM_IC4PSC_1                            ((uint16_t)0x0800) /* Bit 1 */
+
+#define TIM_IC4F                                ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_IC4F_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_IC4F_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_IC4F_2                              ((uint16_t)0x4000) /* Bit 2 */
+#define TIM_IC4F_3                              ((uint16_t)0x8000) /* Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CC1E                                ((uint16_t)0x0001) /* Capture/Compare 1 output enable */
+#define TIM_CC1P                                ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */
+#define TIM_CC1NE                               ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */
+#define TIM_CC1NP                               ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */
+#define TIM_CC2E                                ((uint16_t)0x0010) /* Capture/Compare 2 output enable */
+#define TIM_CC2P                                ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */
+#define TIM_CC2NE                               ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */
+#define TIM_CC2NP                               ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */
+#define TIM_CC3E                                ((uint16_t)0x0100) /* Capture/Compare 3 output enable */
+#define TIM_CC3P                                ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */
+#define TIM_CC3NE                               ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */
+#define TIM_CC3NP                               ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */
+#define TIM_CC4E                                ((uint16_t)0x1000) /* Capture/Compare 4 output enable */
+#define TIM_CC4P                                ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */
+#define TIM_CC4NP                               ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT                                 ((uint16_t)0xFFFF) /* Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC                                 ((uint16_t)0xFFFF) /* Prescaler Value */
+
+/*******************  Bit definition for TIM_ATRLR register  ********************/
+#define TIM_ARR                                 ((uint16_t)0xFFFF) /* actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RPTCR register  ********************/
+#define TIM_REP                                 ((uint8_t)0xFF) /* Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CH1CVR register  *******************/
+#define TIM_CCR1                                ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CH2CVR register  *******************/
+#define TIM_CCR2                                ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CH3CVR register  *******************/
+#define TIM_CCR3                                ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CH4CVR register  *******************/
+#define TIM_CCR4                                ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_DTG                                 ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_DTG_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_DTG_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_DTG_2                               ((uint16_t)0x0004) /* Bit 2 */
+#define TIM_DTG_3                               ((uint16_t)0x0008) /* Bit 3 */
+#define TIM_DTG_4                               ((uint16_t)0x0010) /* Bit 4 */
+#define TIM_DTG_5                               ((uint16_t)0x0020) /* Bit 5 */
+#define TIM_DTG_6                               ((uint16_t)0x0040) /* Bit 6 */
+#define TIM_DTG_7                               ((uint16_t)0x0080) /* Bit 7 */
+
+#define TIM_LOCK                                ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
+#define TIM_LOCK_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_LOCK_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OSSI                                ((uint16_t)0x0400) /* Off-State Selection for Idle mode */
+#define TIM_OSSR                                ((uint16_t)0x0800) /* Off-State Selection for Run mode */
+#define TIM_BKE                                 ((uint16_t)0x1000) /* Break enable */
+#define TIM_BKP                                 ((uint16_t)0x2000) /* Break Polarity */
+#define TIM_AOE                                 ((uint16_t)0x4000) /* Automatic Output enable */
+#define TIM_MOE                                 ((uint16_t)0x8000) /* Main Output enable */
+
+/*******************  Bit definition for TIM_DMACFGR register  ********************/
+#define TIM_DBA                                 ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */
+#define TIM_DBA_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_DBA_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_DBA_2                               ((uint16_t)0x0004) /* Bit 2 */
+#define TIM_DBA_3                               ((uint16_t)0x0008) /* Bit 3 */
+#define TIM_DBA_4                               ((uint16_t)0x0010) /* Bit 4 */
+
+#define TIM_DBL                                 ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DBL_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_DBL_1                               ((uint16_t)0x0200) /* Bit 1 */
+#define TIM_DBL_2                               ((uint16_t)0x0400) /* Bit 2 */
+#define TIM_DBL_3                               ((uint16_t)0x0800) /* Bit 3 */
+#define TIM_DBL_4                               ((uint16_t)0x1000) /* Bit 4 */
+
+/*******************  Bit definition for TIM_DMAADR register  *******************/
+#define TIM_DMAR_DMAB                           ((uint16_t)0xFFFF) /* DMA register for burst accesses */
+
+/******************************************************************************/
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STATR register  *******************/
+#define USART_STATR_PE                          ((uint16_t)0x0001) /* Parity Error */
+#define USART_STATR_FE                          ((uint16_t)0x0002) /* Framing Error */
+#define USART_STATR_NE                          ((uint16_t)0x0004) /* Noise Error Flag */
+#define USART_STATR_ORE                         ((uint16_t)0x0008) /* OverRun Error */
+#define USART_STATR_IDLE                        ((uint16_t)0x0010) /* IDLE line detected */
+#define USART_STATR_RXNE                        ((uint16_t)0x0020) /* Read Data Register Not Empty */
+#define USART_STATR_TC                          ((uint16_t)0x0040) /* Transmission Complete */
+#define USART_STATR_TXE                         ((uint16_t)0x0080) /* Transmit Data Register Empty */
+#define USART_STATR_LBD                         ((uint16_t)0x0100) /* LIN Break Detection Flag */
+#define USART_STATR_CTS                         ((uint16_t)0x0200) /* CTS Flag */
+
+/*******************  Bit definition for USART_DATAR register  *******************/
+#define USART_DATAR_DR                          ((uint16_t)0x01FF) /* Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_Fraction                  ((uint16_t)0x000F) /* Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa                  ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTLR1 register  *******************/
+#define USART_CTLR1_SBK                         ((uint16_t)0x0001) /* Send Break */
+#define USART_CTLR1_RWU                         ((uint16_t)0x0002) /* Receiver wakeup */
+#define USART_CTLR1_RE                          ((uint16_t)0x0004) /* Receiver Enable */
+#define USART_CTLR1_TE                          ((uint16_t)0x0008) /* Transmitter Enable */
+#define USART_CTLR1_IDLEIE                      ((uint16_t)0x0010) /* IDLE Interrupt Enable */
+#define USART_CTLR1_RXNEIE                      ((uint16_t)0x0020) /* RXNE Interrupt Enable */
+#define USART_CTLR1_TCIE                        ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */
+#define USART_CTLR1_TXEIE                       ((uint16_t)0x0080) /* PE Interrupt Enable */
+#define USART_CTLR1_PEIE                        ((uint16_t)0x0100) /* PE Interrupt Enable */
+#define USART_CTLR1_PS                          ((uint16_t)0x0200) /* Parity Selection */
+#define USART_CTLR1_PCE                         ((uint16_t)0x0400) /* Parity Control Enable */
+#define USART_CTLR1_WAKE                        ((uint16_t)0x0800) /* Wakeup method */
+#define USART_CTLR1_M                           ((uint16_t)0x1000) /* Word length */
+#define USART_CTLR1_UE                          ((uint16_t)0x2000) /* USART Enable */
+#define USART_CTLR1_OVER8                       ((uint16_t)0x8000) /* USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CTLR2 register  *******************/
+#define USART_CTLR2_ADD                         ((uint16_t)0x000F) /* Address of the USART node */
+#define USART_CTLR2_LBDL                        ((uint16_t)0x0020) /* LIN Break Detection Length */
+#define USART_CTLR2_LBDIE                       ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */
+#define USART_CTLR2_LBCL                        ((uint16_t)0x0100) /* Last Bit Clock pulse */
+#define USART_CTLR2_CPHA                        ((uint16_t)0x0200) /* Clock Phase */
+#define USART_CTLR2_CPOL                        ((uint16_t)0x0400) /* Clock Polarity */
+#define USART_CTLR2_CLKEN                       ((uint16_t)0x0800) /* Clock Enable */
+
+#define USART_CTLR2_STOP                        ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */
+#define USART_CTLR2_STOP_0                      ((uint16_t)0x1000) /* Bit 0 */
+#define USART_CTLR2_STOP_1                      ((uint16_t)0x2000) /* Bit 1 */
+
+#define USART_CTLR2_LINEN                       ((uint16_t)0x4000) /* LIN mode enable */
+
+/******************  Bit definition for USART_CTLR3 register  *******************/
+#define USART_CTLR3_EIE                         ((uint16_t)0x0001) /* Error Interrupt Enable */
+#define USART_CTLR3_IREN                        ((uint16_t)0x0002) /* IrDA mode Enable */
+#define USART_CTLR3_IRLP                        ((uint16_t)0x0004) /* IrDA Low-Power */
+#define USART_CTLR3_HDSEL                       ((uint16_t)0x0008) /* Half-Duplex Selection */
+#define USART_CTLR3_NACK                        ((uint16_t)0x0010) /* Smartcard NACK enable */
+#define USART_CTLR3_SCEN                        ((uint16_t)0x0020) /* Smartcard mode enable */
+#define USART_CTLR3_DMAR                        ((uint16_t)0x0040) /* DMA Enable Receiver */
+#define USART_CTLR3_DMAT                        ((uint16_t)0x0080) /* DMA Enable Transmitter */
+#define USART_CTLR3_RTSE                        ((uint16_t)0x0100) /* RTS Enable */
+#define USART_CTLR3_CTSE                        ((uint16_t)0x0200) /* CTS Enable */
+#define USART_CTLR3_CTSIE                       ((uint16_t)0x0400) /* CTS Interrupt Enable */
+#define USART_CTLR3_ONEBIT                      ((uint16_t)0x0800) /* One Bit method */
+
+/******************  Bit definition for USART_GPR register  ******************/
+#define USART_GPR_PSC                           ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */
+#define USART_GPR_PSC_0                         ((uint16_t)0x0001) /* Bit 0 */
+#define USART_GPR_PSC_1                         ((uint16_t)0x0002) /* Bit 1 */
+#define USART_GPR_PSC_2                         ((uint16_t)0x0004) /* Bit 2 */
+#define USART_GPR_PSC_3                         ((uint16_t)0x0008) /* Bit 3 */
+#define USART_GPR_PSC_4                         ((uint16_t)0x0010) /* Bit 4 */
+#define USART_GPR_PSC_5                         ((uint16_t)0x0020) /* Bit 5 */
+#define USART_GPR_PSC_6                         ((uint16_t)0x0040) /* Bit 6 */
+#define USART_GPR_PSC_7                         ((uint16_t)0x0080) /* Bit 7 */
+
+#define USART_GPR_GT                            ((uint16_t)0xFF00) /* Guard time value */
+
+/******************************************************************************/
+/*                            Window WATCHDOG                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTLR register  ********************/
+#define WWDG_CTLR_T                             ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTLR_T0                            ((uint8_t)0x01) /* Bit 0 */
+#define WWDG_CTLR_T1                            ((uint8_t)0x02) /* Bit 1 */
+#define WWDG_CTLR_T2                            ((uint8_t)0x04) /* Bit 2 */
+#define WWDG_CTLR_T3                            ((uint8_t)0x08) /* Bit 3 */
+#define WWDG_CTLR_T4                            ((uint8_t)0x10) /* Bit 4 */
+#define WWDG_CTLR_T5                            ((uint8_t)0x20) /* Bit 5 */
+#define WWDG_CTLR_T6                            ((uint8_t)0x40) /* Bit 6 */
+
+#define WWDG_CTLR_WDGA                          ((uint8_t)0x80) /* Activation bit */
+
+/*******************  Bit definition for WWDG_CFGR register  *******************/
+#define WWDG_CFGR_W                             ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */
+#define WWDG_CFGR_W0                            ((uint16_t)0x0001) /* Bit 0 */
+#define WWDG_CFGR_W1                            ((uint16_t)0x0002) /* Bit 1 */
+#define WWDG_CFGR_W2                            ((uint16_t)0x0004) /* Bit 2 */
+#define WWDG_CFGR_W3                            ((uint16_t)0x0008) /* Bit 3 */
+#define WWDG_CFGR_W4                            ((uint16_t)0x0010) /* Bit 4 */
+#define WWDG_CFGR_W5                            ((uint16_t)0x0020) /* Bit 5 */
+#define WWDG_CFGR_W6                            ((uint16_t)0x0040) /* Bit 6 */
+
+#define WWDG_CFGR_WDGTB                         ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFGR_WDGTB0                        ((uint16_t)0x0080) /* Bit 0 */
+#define WWDG_CFGR_WDGTB1                        ((uint16_t)0x0100) /* Bit 1 */
+
+#define WWDG_CFGR_EWI                           ((uint16_t)0x0200) /* Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STATR register  ********************/
+#define WWDG_STATR_EWIF                         ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                          ENHANCED FUNNCTION                                */
+/******************************************************************************/
+
+/****************************  Enhanced register  *****************************/
+#define EXTEN_USBD_LS                           ((uint32_t)0x00000001) /* Bit 0 */
+#define EXTEN_USBD_PU_EN                        ((uint32_t)0x00000002) /* Bit 1 */
+#define EXTEN_USBHD_IO_EN                       ((uint32_t)0x00000004) /* Bit 2 */
+#define EXTEN_USB_5V_SEL                        ((uint32_t)0x00000008) /* Bit 3 */
+#define EXTEN_PLL_HSI_PRE                       ((uint32_t)0x00000010) /* Bit 4 */
+#define EXTEN_LOCKUP_EN                         ((uint32_t)0x00000040) /* Bit 5 */
+#define EXTEN_LOCKUP_RSTF                       ((uint32_t)0x00000080) /* Bit 7 */
+
+#define EXTEN_ULLDO_TRIM                        ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */
+#define EXTEN_ULLDO_TRIM0                       ((uint32_t)0x00000100) /* Bit 0 */
+#define EXTEN_ULLDO_TRIM1                       ((uint32_t)0x00000200) /* Bit 1 */
+
+#define EXTEN_IDO_TRIM                          ((uint32_t)0x00000400) /* Bit 10 */
+#define EXTEN_WRITE_EN                          ((uint32_t)0x00004000) /* Bit 14 */
+#define EXTEN_SHORT_WAKE                        ((uint32_t)0x00008000) /* Bit 15 */
+
+#define EXTEN_FLASH_CLK_TRIM                    ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */
+#define EXTEN_FLASH_CLK_TRIM0                   ((uint32_t)0x00010000) /* Bit 0 */
+#define EXTEN_FLASH_CLK_TRIM1                   ((uint32_t)0x00020000) /* Bit 1 */
+#define EXTEN_FLASH_CLK_TRIM2                   ((uint32_t)0x00040000) /* Bit 2 */
+
+#include "ch32v10x_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Include/system_ch32v10x.h

@@ -0,0 +1,27 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v10x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer System Header File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __SYSTEM_CH32V10x_H
+#define __SYSTEM_CH32V10x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
+
+/* System_Exported_Functions */
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_SYSTEM_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Source/GCC/startup_ch32v10x.S

@@ -0,0 +1,187 @@
+;/********************************** (C) COPYRIGHT *******************************
+;* File Name          : startup_ch32v10x.s
+;* Author             : WCH
+;* Version            : V1.0.0
+;* Date               : 2020/04/30
+;* Description        : CH32V10x vector table for eclipse toolchain.
+;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+;* SPDX-License-Identifier: Apache-2.0
+;*******************************************************************************/
+
+	.section	.init,"ax",@progbits
+	.global	_start
+	.align	1
+_start:
+	j	handle_reset
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00000013
+	.word 0x00100073
+    .section    .vector,"ax",@progbits
+    .align  1
+_vector_base:
+    .option norvc;
+        j   _start
+    .word   0
+        j   NMI_Handler                 /* NMI Handler */
+        j   HardFault_Handler           /* Hard Fault Handler */
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+    .word   0
+        j   SysTick_Handler            /* SysTick Handler */
+    .word   0
+        j   SW_handler                 /* SW Handler */
+    .word   0
+    /* External Interrupts */
+        j   WWDG_IRQHandler            /* Window Watchdog */
+        j   PVD_IRQHandler             /* PVD through EXTI Line detect */
+        j   TAMPER_IRQHandler          /* TAMPER */
+        j   RTC_IRQHandler             /* RTC */
+        j   FLASH_IRQHandler           /* Flash */
+        j   RCC_IRQHandler             /* RCC */
+        j   EXTI0_IRQHandler           /* EXTI Line 0 */
+        j   EXTI1_IRQHandler           /* EXTI Line 1 */
+        j   EXTI2_IRQHandler           /* EXTI Line 2 */
+        j   EXTI3_IRQHandler           /* EXTI Line 3 */
+        j   EXTI4_IRQHandler           /* EXTI Line 4 */
+        j   DMA1_Channel1_IRQHandler   /* DMA1 Channel 1 */
+        j   DMA1_Channel2_IRQHandler   /* DMA1 Channel 2 */
+        j   DMA1_Channel3_IRQHandler   /* DMA1 Channel 3 */
+        j   DMA1_Channel4_IRQHandler   /* DMA1 Channel 4 */
+        j   DMA1_Channel5_IRQHandler   /* DMA1 Channel 5 */
+        j   DMA1_Channel6_IRQHandler   /* DMA1 Channel 6 */
+        j   DMA1_Channel7_IRQHandler   /* DMA1 Channel 7 */
+        j   ADC1_2_IRQHandler          /* ADC1_2 */
+        .word   0
+        .word   0
+        .word   0
+        .word   0
+        j   EXTI9_5_IRQHandler         /* EXTI Line 9..5 */
+        j   TIM1_BRK_IRQHandler        /* TIM1 Break */
+        j   TIM1_UP_IRQHandler         /* TIM1 Update */
+        j   TIM1_TRG_COM_IRQHandler    /* TIM1 Trigger and Commutation */
+        j   TIM1_CC_IRQHandler         /* TIM1 Capture Compare */
+        j   TIM2_IRQHandler            /* TIM2 */
+        j   TIM3_IRQHandler            /* TIM3 */
+        j   TIM4_IRQHandler            /* TIM4 */
+        j   I2C1_EV_IRQHandler         /* I2C1 Event */
+        j   I2C1_ER_IRQHandler         /* I2C1 Error */
+        j   I2C2_EV_IRQHandler         /* I2C2 Event */
+        j   I2C2_ER_IRQHandler         /* I2C2 Error */
+        j   SPI1_IRQHandler            /* SPI1 */
+        j   SPI2_IRQHandler            /* SPI2 */
+        j   USART1_IRQHandler          /* USART1 */
+        j   USART2_IRQHandler          /* USART2 */
+        j   USART3_IRQHandler          /* USART3 */
+        j   EXTI15_10_IRQHandler       /* EXTI Line 15..10 */
+        j   RTCAlarm_IRQHandler        /* RTC Alarm through EXTI Line */
+        j   USBWakeUp_IRQHandler       /* USB Wakeup from suspend */
+        j   USBHD_IRQHandler           /* USBHD */
+
+    .option rvc;
+
+    .section    .text.vector_handler, "ax", @progbits
+    .weak   NMI_Handler
+    .weak   HardFault_Handler
+    .weak   SysTick_Handler
+    .weak   SW_handler
+    .weak   WWDG_IRQHandler
+    .weak   PVD_IRQHandler
+    .weak   TAMPER_IRQHandler
+    .weak   RTC_IRQHandler
+    .weak   FLASH_IRQHandler
+    .weak   RCC_IRQHandler
+    .weak   EXTI0_IRQHandler
+    .weak   EXTI1_IRQHandler
+    .weak   EXTI2_IRQHandler
+    .weak   EXTI3_IRQHandler
+    .weak   EXTI4_IRQHandler
+    .weak   DMA1_Channel1_IRQHandler
+    .weak   DMA1_Channel2_IRQHandler
+    .weak   DMA1_Channel3_IRQHandler
+    .weak   DMA1_Channel4_IRQHandler
+    .weak   DMA1_Channel5_IRQHandler
+    .weak   DMA1_Channel6_IRQHandler
+    .weak   DMA1_Channel7_IRQHandler
+    .weak   ADC1_2_IRQHandler
+    .weak   EXTI9_5_IRQHandler
+    .weak   TIM1_BRK_IRQHandler
+    .weak   TIM1_UP_IRQHandler
+    .weak   TIM1_TRG_COM_IRQHandler
+    .weak   TIM1_CC_IRQHandler
+    .weak   TIM2_IRQHandler
+    .weak   TIM3_IRQHandler
+    .weak   TIM4_IRQHandler
+    .weak   I2C1_EV_IRQHandler
+    .weak   I2C1_ER_IRQHandler
+    .weak   I2C2_EV_IRQHandler
+    .weak   I2C2_ER_IRQHandler
+    .weak   SPI1_IRQHandler
+    .weak   SPI2_IRQHandler
+    .weak   USART1_IRQHandler
+    .weak   USART2_IRQHandler
+    .weak   USART3_IRQHandler
+    .weak   EXTI15_10_IRQHandler
+    .weak   RTCAlarm_IRQHandler
+    .weak   USBWakeUp_IRQHandler
+    .weak   USBHD_IRQHandler
+
+	.section	.text.handle_reset,"ax",@progbits
+	.weak	handle_reset
+	.align	1
+handle_reset:
+.option push 
+.option	norelax 
+	la gp, __global_pointer$
+.option	pop 
+1:
+	la sp, _eusrstack 
+2:
+	/* Load data section from flash to RAM */
+	la a0, _data_lma
+	la a1, _data_vma
+	la a2, _edata
+	bgeu a1, a2, 2f
+1:
+	lw t0, (a0)
+	sw t0, (a1)
+	addi a0, a0, 4
+	addi a1, a1, 4
+	bltu a1, a2, 1b
+2:
+	/* clear bss section */
+	la a0, _sbss
+	la a1, _ebss
+	bgeu a0, a1, 2f
+1:
+	sw zero, (a0)
+	addi a0, a0, 4
+	bltu a0, a1, 1b
+2:
+	/* disable interrupt */
+  	li t0, 0x1800
+  	csrs mstatus, t0
+	la t0, _vector_base
+  	ori t0, t0, 1
+	csrw mtvec, t0
+
+  	jal  SystemInit  /* ϵͳʱÖÓ³õʼ»¯ */
+	la t0,entry      /* rttµÄÈë¿Ú */
+	csrw mepc, t0
+	mret
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/WCH/CH32V10x/Source/system_ch32v10x.c

@@ -0,0 +1,503 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : system_ch32v10x.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer System Source File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32v10x.h"
+
+/*
+ * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
+ * reset the HSI is used as SYSCLK source).
+ * If none of the define below is enabled, the HSI is used as System clock source.
+ */
+/* #define SYSCLK_FREQ_HSE    HSE_VALUE */
+/* #define SYSCLK_FREQ_24MHz  24000000  */
+/* #define SYSCLK_FREQ_48MHz  48000000  */
+/* #define SYSCLK_FREQ_56MHz  56000000  */
+#define SYSCLK_FREQ_72MHz    72000000
+
+/* Clock Definitions */
+#ifdef SYSCLK_FREQ_HSE
+uint32_t      SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_24MHz
+uint32_t    SystemCoreClock = SYSCLK_FREQ_24MHz; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_48MHz
+uint32_t    SystemCoreClock = SYSCLK_FREQ_48MHz; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_56MHz
+uint32_t    SystemCoreClock = SYSCLK_FREQ_56MHz; /* System Clock Frequency (Core Clock) */
+#elif defined SYSCLK_FREQ_72MHz
+uint32_t    SystemCoreClock = SYSCLK_FREQ_72MHz; /* System Clock Frequency (Core Clock) */
+#else /* HSI Selected as System Clock source */
+uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
+#endif
+
+__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* ch32v10x_system_private_function_proto_types */
+static void SetSysClock(void);
+
+#ifdef SYSCLK_FREQ_HSE
+static void   SetSysClockToHSE(void);
+#elif defined SYSCLK_FREQ_24MHz
+static void SetSysClockTo24(void);
+#elif defined SYSCLK_FREQ_48MHz
+static void SetSysClockTo48(void);
+#elif defined SYSCLK_FREQ_56MHz
+static void SetSysClockTo56(void);
+#elif defined SYSCLK_FREQ_72MHz
+static void SetSysClockTo72(void);
+#endif
+
+/*********************************************************************
+ * @fn      SystemInit
+ *
+ * @brief   Setup the microcontroller system Initialize the Embedded Flash Interface,
+ *        the PLL and update the SystemCoreClock variable.
+ *
+ * @return  none
+ */
+void SystemInit(void)
+{
+    RCC->CTLR |= (uint32_t)0x00000001;
+    RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+    RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+    RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+    RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+    RCC->INTR = 0x009F0000;
+    SetSysClock();
+}
+
+/*********************************************************************
+ * @fn      SystemCoreClockUpdate
+ *
+ * @brief   Update SystemCoreClock variable according to Clock Register Values.
+ *
+ * @return  none
+ */
+void SystemCoreClockUpdate(void)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0;
+
+    tmp = RCC->CFGR0 & RCC_SWS;
+
+    switch(tmp)
+    {
+        case 0x00:
+            SystemCoreClock = HSI_VALUE;
+            break;
+        case 0x04:
+            SystemCoreClock = HSE_VALUE;
+            break;
+        case 0x08:
+            pllmull = RCC->CFGR0 & RCC_PLLMULL;
+            pllsource = RCC->CFGR0 & RCC_PLLSRC;
+            pllmull = (pllmull >> 18) + 2;
+            if(pllsource == 0x00)
+            {
+                SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+            }
+            else
+            {
+                if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
+                {
+                    SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
+                }
+                else
+                {
+                    SystemCoreClock = HSE_VALUE * pllmull;
+                }
+            }
+            break;
+        default:
+            SystemCoreClock = HSI_VALUE;
+            break;
+    }
+
+    tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
+    SystemCoreClock >>= tmp;
+}
+
+/*********************************************************************
+ * @fn      SetSysClock
+ *
+ * @brief   Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClock(void)
+{
+#ifdef SYSCLK_FREQ_HSE
+    SetSysClockToHSE();
+#elif defined SYSCLK_FREQ_24MHz
+    SetSysClockTo24();
+#elif defined SYSCLK_FREQ_48MHz
+    SetSysClockTo48();
+#elif defined SYSCLK_FREQ_56MHz
+    SetSysClockTo56();
+#elif defined SYSCLK_FREQ_72MHz
+    SetSysClockTo72();
+#endif
+
+    /* If none of the define above is enabled, the HSI is used as System clock
+     * source (default after reset)
+     */
+}
+
+#ifdef SYSCLK_FREQ_HSE
+
+/*********************************************************************
+ * @fn      SetSysClockToHSE
+ *
+ * @brief   Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockToHSE(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+        /* Flash 0 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+        /* Select HSE as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
+
+        /* Wait till HSE is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_24MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo24
+ *
+ * @brief   Sets System clock frequency to 24MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo24(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 0 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
+
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL3);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /* If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_48MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo48
+ *
+ * @brief   Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo48(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 1 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
+
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_56MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo56
+ *
+ * @brief   Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo56(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+
+#elif defined SYSCLK_FREQ_72MHz
+
+/*********************************************************************
+ * @fn      SetSysClockTo72
+ *
+ * @brief   Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
+ *
+ * @return  none
+ */
+static void SetSysClockTo72(void)
+{
+    __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+    RCC->CTLR |= ((uint32_t)RCC_HSEON);
+
+    /* Wait till HSE is ready and if Time out is reached exit */
+    do
+    {
+        HSEStatus = RCC->CTLR & RCC_HSERDY;
+        StartUpCounter++;
+    } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+    if((RCC->CTLR & RCC_HSERDY) != RESET)
+    {
+        HSEStatus = (uint32_t)0x01;
+    }
+    else
+    {
+        HSEStatus = (uint32_t)0x00;
+    }
+
+    if(HSEStatus == (uint32_t)0x01)
+    {
+        /* Enable Prefetch Buffer */
+        FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+        /* Flash 2 wait state */
+        FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+        FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+        /* HCLK = SYSCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
+        /* PCLK2 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
+        /* PCLK1 = HCLK */
+        RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
+
+        /*  PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
+                                              RCC_PLLMULL));
+        RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
+        /* Enable PLL */
+        RCC->CTLR |= RCC_PLLON;
+        /* Wait till PLL is ready */
+        while((RCC->CTLR & RCC_PLLRDY) == 0)
+        {
+        }
+        /* Select PLL as system clock source */
+        RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
+        RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+        /* Wait till PLL is used as system clock source */
+        while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
+        {
+        }
+    }
+    else
+    {
+        /*
+         * If HSE fails to start-up, the application will have wrong clock
+         * configuration. User can add here some code to deal with this error
+         */
+    }
+}
+#endif

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/core_riscv.c

@@ -0,0 +1,552 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : core_riscv.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : RISC-V Core Peripheral Access Layer Source File
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include <stdint.h>
+
+/* define compiler specific symbols */
+#if defined(__CC_ARM)
+  #define __ASM       __asm     /*!< asm keyword for ARM Compiler          */
+  #define __INLINE    __inline  /*!< inline keyword for ARM Compiler       */
+
+#elif defined(__ICCARM__)
+  #define __ASM       __asm   /*!< asm keyword for IAR Compiler          */
+  #define __INLINE    inline  /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined(__GNUC__)
+  #define __ASM       __asm   /*!< asm keyword for GNU Compiler          */
+  #define __INLINE    inline  /*!< inline keyword for GNU Compiler       */
+
+#elif defined(__TASKING__)
+  #define __ASM       __asm   /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE    inline  /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*********************************************************************
+ * @fn      __get_FFLAGS
+ *
+ * @brief   Return the Floating-Point Accrued Exceptions
+ *
+ * @return  fflags value
+ */
+uint32_t __get_FFLAGS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""fflags": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FFLAGS
+ *
+ * @brief   Set the Floating-Point Accrued Exceptions
+ *
+ * @param   value  - set FFLAGS value
+ *
+ * @return  none
+ */
+void __set_FFLAGS(uint32_t value)
+{
+    __ASM volatile("csrw fflags, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_FRM
+ *
+ * @brief   Return the Floating-Point Dynamic Rounding Mode
+ *
+ * @return  frm value
+ */
+uint32_t __get_FRM(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""frm": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FRM
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set frm value
+ *
+ * @return  none
+ */
+void __set_FRM(uint32_t value)
+{
+    __ASM volatile("csrw frm, %0" :: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_FCSR
+ *
+ * @brief   Return the Floating-Point Control and Status Register
+ *
+ * @return  fcsr value
+ */
+uint32_t __get_FCSR(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "fcsr" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_FCSR
+ *
+ * @brief   Set the Floating-Point Dynamic Rounding Mode
+ *
+ * @param   value  - set fcsr value
+ *
+ * @return  none
+ */
+void __set_FCSR(uint32_t value)
+{
+    __ASM volatile("csrw fcsr, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MSTATUS
+ *
+ * @brief   Return the Machine Status Register
+ *
+ * @return  mstatus value
+ */
+uint32_t __get_MSTATUS(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mstatus": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MSTATUS
+ *
+ * @brief   Set the Machine Status Register
+ *
+ * @param   value  - set mstatus value
+ *
+ * @return  none
+ */
+void __set_MSTATUS(uint32_t value)
+{
+    __ASM volatile("csrw mstatus, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MISA
+ *
+ * @brief   Return the Machine ISA Register
+ *
+ * @return  misa value
+ */
+uint32_t __get_MISA(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""misa" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set misa value
+ *
+ * @return  none
+ */
+void __set_MISA(uint32_t value)
+{
+    __ASM volatile("csrw misa, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MIE
+ *
+ * @brief   Return the Machine Interrupt Enable Register
+ *
+ * @return  mie value
+ */
+uint32_t __get_MIE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mie": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MISA
+ *
+ * @brief   Set the Machine ISA Register
+ *
+ * @param   value  - set mie value
+ *
+ * @return  none
+ */
+void __set_MIE(uint32_t value)
+{
+    __ASM volatile("csrw mie, %0": : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Trap-Vector Base-Address Register
+ *
+ * @return  mtvec value
+ */
+uint32_t __get_MTVEC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mtvec": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Trap-Vector Base-Address Register
+ *
+ * @param   value  - set mtvec value
+ *
+ * @return  none
+ */
+void __set_MTVEC(uint32_t value)
+{
+    __ASM volatile("csrw mtvec, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MTVEC
+ *
+ * @brief   Return the Machine Seratch Register
+ *
+ * @return  mscratch value
+ */
+uint32_t __get_MSCRATCH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mscratch" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVEC
+ *
+ * @brief   Set the Machine Seratch Register
+ *
+ * @param   value  - set mscratch value
+ *
+ * @return  none
+ */
+void __set_MSCRATCH(uint32_t value)
+{
+    __ASM volatile("csrw mscratch, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MEPC
+ *
+ * @brief   Return the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+uint32_t __get_MEPC(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mepc" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Exception Program Register
+ *
+ * @return  mepc value
+ */
+void __set_MEPC(uint32_t value)
+{
+    __ASM volatile("csrw mepc, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MCAUSE
+ *
+ * @brief   Return the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MCAUSE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mcause": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MEPC
+ *
+ * @brief   Set the Machine Cause Register
+ *
+ * @return  mcause value
+ */
+void __set_MCAUSE(uint32_t value)
+{
+    __ASM volatile("csrw mcause, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MTVAL
+ *
+ * @brief   Return the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+uint32_t __get_MTVAL(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mtval" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MTVAL
+ *
+ * @brief   Set the Machine Trap Value Register
+ *
+ * @return  mtval value
+ */
+void __set_MTVAL(uint32_t value)
+{
+    __ASM volatile("csrw mtval, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MIP
+ *
+ * @brief   Return the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+uint32_t __get_MIP(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mip": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MIP
+ *
+ * @brief   Set the Machine Interrupt Pending Register
+ *
+ * @return  mip value
+ */
+void __set_MIP(uint32_t value)
+{
+    __ASM volatile("csrw mip, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLE
+ *
+ * @brief   Return Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+uint32_t __get_MCYCLE(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0," "mcycle": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLE
+ *
+ * @brief   Set Lower 32 bits of Cycle counter
+ *
+ * @return  mcycle value
+ */
+void __set_MCYCLE(uint32_t value)
+{
+    __ASM volatile("csrw mcycle, %0" : : "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MCYCLEH
+ *
+ * @brief   Return Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+uint32_t __get_MCYCLEH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mcycleh" : "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MCYCLEH
+ *
+ * @brief   Set Upper 32 bits of Cycle counter
+ *
+ * @return  mcycleh value
+ */
+void __set_MCYCLEH(uint32_t value)
+{
+    __ASM volatile("csrw mcycleh, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRET
+ *
+ * @brief   Return Lower 32 bits of Instructions-retired counter
+ *
+ * @return  mcause value
+ */
+uint32_t __get_MINSTRET(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""minstret": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRET
+ *
+ * @brief   Set Lower 32 bits of Instructions-retired counter
+ *
+ * @return  minstret value
+ */
+void __set_MINSTRET(uint32_t value)
+{
+    __ASM volatile("csrw minstret, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MINSTRETH
+ *
+ * @brief   Return Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+uint32_t __get_MINSTRETH(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""minstreth": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __set_MINSTRETH
+ *
+ * @brief   Set Upper 32 bits of Instructions-retired counter
+ *
+ * @return  minstreth value
+ */
+void __set_MINSTRETH(uint32_t value)
+{
+    __ASM volatile("csrw minstreth, %0":: "r"(value));
+}
+
+/*********************************************************************
+ * @fn      __get_MVENDORID
+ *
+ * @brief   Return Vendor ID Register
+ *
+ * @return  mvendorid value
+ */
+uint32_t __get_MVENDORID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mvendorid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MARCHID
+ *
+ * @brief   Return Machine Architecture ID Register
+ *
+ * @return  marchid value
+ */
+uint32_t __get_MARCHID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""marchid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MIMPID
+ *
+ * @brief   Return Machine Implementation ID Register
+ *
+ * @return  mimpid value
+ */
+uint32_t __get_MIMPID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mimpid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_MHARTID
+ *
+ * @brief   Return Hart ID Register
+ *
+ * @return  mhartid value
+ */
+uint32_t __get_MHARTID(void)
+{
+    uint32_t result;
+
+    __ASM volatile("csrr %0,""mhartid": "=r"(result));
+    return (result);
+}
+
+/*********************************************************************
+ * @fn      __get_SP
+ *
+ * @brief   Return SP Register
+ *
+ * @return  SP value
+ */
+uint32_t __get_SP(void)
+{
+    uint32_t result;
+
+    asm volatile("mv %0,""sp": "=r"(result):);
+    return (result);
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/CMSIS/core_riscv.h

@@ -0,0 +1,397 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : core_riscv.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : RISC-V Core Peripheral Access Layer Header File
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CORE_RISCV_H__
+#define __CORE_RISCV_H__
+
+/* IO definitions */
+#ifdef __cplusplus
+  #define     __I     volatile                /*!< defines 'read only' permissions      */
+#else
+  #define     __I     volatile const          /*!< defines 'read only' permissions     */
+#endif
+#define     __O     volatile                  /*!< defines 'write only' permissions     */
+#define     __IO    volatile                  /*!< defines 'read / write' permissions   */
+
+/* Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef __I uint32_t vuc32;  /* Read Only */
+typedef __I uint16_t vuc16;  /* Read Only */
+typedef __I uint8_t vuc8;   /* Read Only */
+
+typedef const uint32_t uc32;  /* Read Only */
+typedef const uint16_t uc16;  /* Read Only */
+typedef const uint8_t uc8;   /* Read Only */
+
+typedef __I int32_t vsc32;  /* Read Only */
+typedef __I int16_t vsc16;  /* Read Only */
+typedef __I int8_t vsc8;   /* Read Only */
+
+typedef const int32_t sc32;  /* Read Only */
+typedef const int16_t sc16;  /* Read Only */
+typedef const int8_t sc8;   /* Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+#define   RV_STATIC_INLINE  static  inline
+
+/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
+typedef struct{
+  __I  uint32_t ISR[8];
+  __I  uint32_t IPR[8];
+  __IO uint32_t ITHRESDR;
+  __IO uint32_t FIBADDRR;
+  __IO uint32_t CFGR;
+  __I  uint32_t GISR;
+  uint8_t RESERVED0[0x10];
+  __IO uint32_t FIOFADDRR[4];
+  uint8_t RESERVED1[0x90];
+  __O  uint32_t IENR[8];
+  uint8_t RESERVED2[0x60];
+  __O  uint32_t IRER[8];
+  uint8_t RESERVED3[0x60];
+  __O  uint32_t IPSR[8];
+  uint8_t RESERVED4[0x60];
+  __O  uint32_t IPRR[8];
+  uint8_t RESERVED5[0x60];
+  __IO uint32_t IACTR[8];
+  uint8_t RESERVED6[0xE0];
+  __IO uint8_t IPRIOR[256];
+  uint8_t RESERVED7[0x810];
+  __IO uint32_t SCTLR;
+}PFIC_Type;
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+  __IO uint32_t CTLR;
+  __IO uint8_t CNTL0;
+  __IO uint8_t CNTL1;
+  __IO uint8_t CNTL2;
+  __IO uint8_t CNTL3;
+  __IO uint8_t CNTH0;
+  __IO uint8_t CNTH1;
+  __IO uint8_t CNTH2;
+  __IO uint8_t CNTH3;
+  __IO uint8_t CMPLR0;
+  __IO uint8_t CMPLR1;
+  __IO uint8_t CMPLR2;
+  __IO uint8_t CMPLR3;
+  __IO uint8_t CMPHR0;
+  __IO uint8_t CMPHR1;
+  __IO uint8_t CMPHR2;
+  __IO uint8_t CMPHR3;
+}SysTick_Type;
+
+
+#define PFIC            ((PFIC_Type *) 0xE000E000 )
+#define NVIC            PFIC
+#define NVIC_KEY1       ((uint32_t)0xFA050000)
+#define	NVIC_KEY2				((uint32_t)0xBCAF0000)
+#define	NVIC_KEY3				((uint32_t)0xBEEF0000)
+
+#define SysTick         ((SysTick_Type *) 0xE000F000)
+
+
+/*********************************************************************
+ * @fn      __NOP
+ *
+ * @brief   nop
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void __NOP()
+{
+  __asm volatile ("nop");
+}
+
+/*********************************************************************
+ * @fn      NVIC_EnableIRQ
+ *
+ * @brief   Enable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn){
+  NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_DisableIRQ
+ *
+ * @brief   Disable Interrupt
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  none
+ */
+RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  uint32_t t;
+
+  t = NVIC->ITHRESDR;
+  NVIC->ITHRESDR = 0x10;
+  NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+  NVIC->ITHRESDR = t;
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetStatusIRQ
+ *
+ * @brief   Get Interrupt Enable State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Enable
+ *          0 - Interrupt Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetPendingIRQ
+ *
+ * @brief   Get Interrupt Pending State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Pending Enable
+ *          0 - Interrupt Pending Disable
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPendingIRQ
+ *
+ * @brief   Set Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_ClearPendingIRQ
+ *
+ * @brief   Clear Interrupt Pending
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+/*********************************************************************
+ * @fn      NVIC_GetActive
+ *
+ * @brief   Get Interrupt Active State
+ *
+ * @param   IRQn: Interrupt Numbers
+ *
+ * @return  1 - Interrupt Active
+ *          0 - Interrupt No Active
+ */
+RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetPriority
+ *
+ * @brief   Set Interrupt Priority
+ *
+ * @param   IRQn - Interrupt Numbers
+ *          priority -
+ *              bit7 - pre-emption priority
+ *              bit6~bit4 - subpriority
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
+{
+  NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
+}
+
+/*********************************************************************
+ * @fn      __WFI
+ *
+ * @brief   Wait for Interrupt
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
+{
+  NVIC->SCTLR &= ~(1<<3);	// wfi
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      __WFE
+ *
+ * @brief   Wait for Events
+ *
+ * @return  None
+ */
+__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
+{
+  NVIC->SCTLR |= (1<<3)|(1<<5);		// (wfi->wfe)+(__sev)
+  asm volatile ("wfi");
+  NVIC->SCTLR |= (1<<3);
+  asm volatile ("wfi");
+}
+
+/*********************************************************************
+ * @fn      NVIC_SetFastIRQ
+ *
+ * @brief   Set VTF Interrupt
+ *
+ * @param   add - VTF interrupt service function base address.
+ *          IRQn -Interrupt Numbers
+ *          num - VTF Interrupt Numbers
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num)
+{
+  if(num > 3)  return ;
+  NVIC->FIBADDRR = addr;
+  NVIC->FIOFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff);
+}
+
+/*********************************************************************
+ * @fn      NVIC_SystemReset
+ *
+ * @brief   Initiate a system reset request
+ *
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_SystemReset(void)
+{
+  NVIC->CFGR = NVIC_KEY3|(1<<7);
+}
+
+/*********************************************************************
+ * @fn      NVIC_HaltPushCfg
+ *
+ * @brief   Enable Hardware Stack
+ *
+ * @param   NewState - DISABLE or ENABLE
+ 
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+  	NVIC->CFGR = NVIC_KEY1;
+  }
+  else{
+  	NVIC->CFGR = NVIC_KEY1|(1<<0);
+  }
+}
+
+/*********************************************************************
+ * @fn      NVIC_INTNestCfg
+ *
+ * @brief   Enable Interrupt Nesting
+ *
+ * @param   NewState - DISABLE or ENABLE
+ 
+ * @return  None
+ */
+RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState)
+{
+  if (NewState != DISABLE)
+  {
+  	NVIC->CFGR = NVIC_KEY1;
+  }
+  else
+  {
+  	NVIC->CFGR = NVIC_KEY1|(1<<1);
+  }
+}
+
+/* Core_Exported_Functions */  
+extern uint32_t __get_FFLAGS(void);
+extern void __set_FFLAGS(uint32_t value);
+extern uint32_t __get_FRM(void);
+extern void __set_FRM(uint32_t value);
+extern uint32_t __get_FCSR(void);
+extern void __set_FCSR(uint32_t value);
+extern uint32_t __get_MSTATUS(void);
+extern void __set_MSTATUS(uint32_t value);
+extern uint32_t __get_MISA(void);
+extern void __set_MISA(uint32_t value);
+extern uint32_t __get_MIE(void);
+extern void __set_MIE(uint32_t value);
+extern uint32_t __get_MTVEC(void);
+extern void __set_MTVEC(uint32_t value);
+extern uint32_t __get_MSCRATCH(void);
+extern void __set_MSCRATCH(uint32_t value);
+extern uint32_t __get_MEPC(void);
+extern void __set_MEPC(uint32_t value);
+extern uint32_t __get_MCAUSE(void);
+extern void __set_MCAUSE(uint32_t value);
+extern uint32_t __get_MTVAL(void);
+extern void __set_MTVAL(uint32_t value);
+extern uint32_t __get_MIP(void);
+extern void __set_MIP(uint32_t value);
+extern uint32_t __get_MCYCLE(void);
+extern void __set_MCYCLE(uint32_t value);
+extern uint32_t __get_MCYCLEH(void);
+extern void __set_MCYCLEH(uint32_t value);
+extern uint32_t __get_MINSTRET(void);
+extern void __set_MINSTRET(uint32_t value);
+extern uint32_t __get_MINSTRETH(void);
+extern void __set_MINSTRETH(uint32_t value);
+extern uint32_t __get_MVENDORID(void);
+extern uint32_t __get_MARCHID(void);
+extern uint32_t __get_MIMPID(void);
+extern uint32_t __get_MHARTID(void);
+extern uint32_t __get_SP(void);
+
+
+#endif/* __CORE_RISCV_H__ */
+
+
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/SConscript

@@ -0,0 +1,40 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+StdPeriph_Driver/src/ch32v10x_adc.c
+StdPeriph_Driver/src/ch32v10x_bkp.c
+StdPeriph_Driver/src/ch32v10x_crc.c
+StdPeriph_Driver/src/ch32v10x_dbgmcu.c
+StdPeriph_Driver/src/ch32v10x_dma.c
+StdPeriph_Driver/src/ch32v10x_exti.c
+StdPeriph_Driver/src/ch32v10x_flash.c
+StdPeriph_Driver/src/ch32v10x_gpio.c
+StdPeriph_Driver/src/ch32v10x_i2c.c
+StdPeriph_Driver/src/ch32v10x_iwdg.c
+StdPeriph_Driver/src/ch32v10x_misc.c
+StdPeriph_Driver/src/ch32v10x_pwr.c
+StdPeriph_Driver/src/ch32v10x_rcc.c
+StdPeriph_Driver/src/ch32v10x_rtc.c
+StdPeriph_Driver/src/ch32v10x_spi.c
+StdPeriph_Driver/src/ch32v10x_tim.c
+StdPeriph_Driver/src/ch32v10x_usart.c
+StdPeriph_Driver/src/ch32v10x_wwdg.c
+CMSIS/core_riscv.c
+CMSIS/WCH/CH32V10x/Source/system_ch32v10x.c
+CMSIS/WCH/CH32V10x/Source/GCC/startup_ch32v10x.S
+""")
+
+path = [
+	cwd + '/CMSIS',
+    cwd + '/CMSIS/WCH/CH32V10x/Include',
+    cwd + '/StdPeriph_Driver/inc']
+
+
+group = DefineGroup('ch32v10x_lib', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x.h

@@ -0,0 +1,3215 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : CH32V10x Device Peripheral Access Layer Header File.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_H
+#define __CH32V10x_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define __MPU_PRESENT             0  /* Other CH32 devices does not provide an MPU */
+#define __Vendor_SysTickConfig    0  /* Set to 1 if different SysTick Config is used */
+
+#define HSE_VALUE                 ((uint32_t)8000000) /* Value of the External oscillator in Hz */
+
+/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
+#define HSE_STARTUP_TIMEOUT       ((uint16_t)0x500) /* Time out for HSE start up */
+
+#define HSI_VALUE                 ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+
+/* Interrupt Number Definition, according to the selected device */
+typedef enum IRQn
+{
+    /******  RISC-V Processor Exceptions Numbers *******************************************************/
+    NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt                             */
+    EXC_IRQn = 3,            /* 4 Exception Interrupt                                */
+    SysTicK_IRQn = 12,       /* 12 System timer Interrupt                            */
+    Software_IRQn = 14,      /* 14 software Interrupt                                */
+
+    /******  RISC-V specific Interrupt Numbers *********************************************************/
+    WWDG_IRQn = 16,          /* Window WatchDog Interrupt                            */
+    PVD_IRQn = 17,           /* PVD through EXTI Line detection Interrupt            */
+    TAMPER_IRQn = 18,        /* Tamper Interrupt                                     */
+    RTC_IRQn = 19,           /* RTC global Interrupt                                 */
+    FLASH_IRQn = 20,         /* FLASH global Interrupt                               */
+    RCC_IRQn = 21,           /* RCC global Interrupt                                 */
+    EXTI0_IRQn = 22,         /* EXTI Line0 Interrupt                                 */
+    EXTI1_IRQn = 23,         /* EXTI Line1 Interrupt                                 */
+    EXTI2_IRQn = 24,         /* EXTI Line2 Interrupt                                 */
+    EXTI3_IRQn = 25,         /* EXTI Line3 Interrupt                                 */
+    EXTI4_IRQn = 26,         /* EXTI Line4 Interrupt                                 */
+    DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt                      */
+    DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt                      */
+    DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt                      */
+    DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt                      */
+    DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt                      */
+    DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt                      */
+    DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt                      */
+    ADC_IRQn = 34,           /* ADC1 global Interrupt                                */
+    EXTI9_5_IRQn = 39,       /* External Line[9:5] Interrupts                        */
+    TIM1_BRK_IRQn = 40,      /* TIM1 Break Interrupt                                 */
+    TIM1_UP_IRQn = 41,       /* TIM1 Update Interrupt                                */
+    TIM1_TRG_COM_IRQn = 42,  /* TIM1 Trigger and Commutation Interrupt               */
+    TIM1_CC_IRQn = 43,       /* TIM1 Capture Compare Interrupt                       */
+    TIM2_IRQn = 44,          /* TIM2 global Interrupt                                */
+    TIM3_IRQn = 45,          /* TIM3 global Interrupt                                */
+    TIM4_IRQn = 46,          /* TIM4 global Interrupt                                */
+    I2C1_EV_IRQn = 47,       /* I2C1 Event Interrupt                                 */
+    I2C1_ER_IRQn = 48,       /* I2C1 Error Interrupt                                 */
+    I2C2_EV_IRQn = 49,       /* I2C2 Event Interrupt                                 */
+    I2C2_ER_IRQn = 50,       /* I2C2 Error Interrupt                                 */
+    SPI1_IRQn = 51,          /* SPI1 global Interrupt                                */
+    SPI2_IRQn = 52,          /* SPI2 global Interrupt                                */
+    USART1_IRQn = 53,        /* USART1 global Interrupt                              */
+    USART2_IRQn = 54,        /* USART2 global Interrupt                              */
+    USART3_IRQn = 55,        /* USART3 global Interrupt                              */
+    EXTI15_10_IRQn = 56,     /* External Line[15:10] Interrupts                      */
+    RTCAlarm_IRQn = 57,      /* RTC Alarm through EXTI Line Interrupt                */
+    USBWakeUp_IRQn = 58,     /* USB WakeUp from suspend through EXTI Line Interrupt  */
+    USBHD_IRQn = 59,         /* USBHD Interrupt                                      */
+
+} IRQn_Type;
+
+#define HardFault_IRQn    EXC_IRQn
+#define ADC1_2_IRQn       ADC_IRQn
+
+#include <stdint.h>
+#include "core_riscv.h"
+#include "system_ch32v10x.h"
+
+/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
+#define HSI_Value             HSI_VALUE
+#define HSE_Value             HSE_VALUE
+#define HSEStartUp_TimeOut    HSE_STARTUP_TIMEOUT
+
+/* Analog to Digital Converter */
+typedef struct
+{
+    __IO uint32_t STATR;
+    __IO uint32_t CTLR1;
+    __IO uint32_t CTLR2;
+    __IO uint32_t SAMPTR1;
+    __IO uint32_t SAMPTR2;
+    __IO uint32_t IOFR1;
+    __IO uint32_t IOFR2;
+    __IO uint32_t IOFR3;
+    __IO uint32_t IOFR4;
+    __IO uint32_t WDHTR;
+    __IO uint32_t WDLTR;
+    __IO uint32_t RSQR1;
+    __IO uint32_t RSQR2;
+    __IO uint32_t RSQR3;
+    __IO uint32_t ISQR;
+    __IO uint32_t IDATAR1;
+    __IO uint32_t IDATAR2;
+    __IO uint32_t IDATAR3;
+    __IO uint32_t IDATAR4;
+    __IO uint32_t RDATAR;
+} ADC_TypeDef;
+
+/* Backup Registers */
+typedef struct
+{
+    uint32_t      RESERVED0;
+    __IO uint16_t DATAR1;
+    uint16_t      RESERVED1;
+    __IO uint16_t DATAR2;
+    uint16_t      RESERVED2;
+    __IO uint16_t DATAR3;
+    uint16_t      RESERVED3;
+    __IO uint16_t DATAR4;
+    uint16_t      RESERVED4;
+    __IO uint16_t DATAR5;
+    uint16_t      RESERVED5;
+    __IO uint16_t DATAR6;
+    uint16_t      RESERVED6;
+    __IO uint16_t DATAR7;
+    uint16_t      RESERVED7;
+    __IO uint16_t DATAR8;
+    uint16_t      RESERVED8;
+    __IO uint16_t DATAR9;
+    uint16_t      RESERVED9;
+    __IO uint16_t DATAR10;
+    uint16_t      RESERVED10;
+    __IO uint16_t OCTLR;
+    uint16_t      RESERVED11;
+    __IO uint16_t TPCTLR;
+    uint16_t      RESERVED12;
+    __IO uint16_t TPCSR;
+    uint16_t      RESERVED13[5];
+    __IO uint16_t DATAR11;
+    uint16_t      RESERVED14;
+    __IO uint16_t DATAR12;
+    uint16_t      RESERVED15;
+    __IO uint16_t DATAR13;
+    uint16_t      RESERVED16;
+    __IO uint16_t DATAR14;
+    uint16_t      RESERVED17;
+    __IO uint16_t DATAR15;
+    uint16_t      RESERVED18;
+    __IO uint16_t DATAR16;
+    uint16_t      RESERVED19;
+    __IO uint16_t DATAR17;
+    uint16_t      RESERVED20;
+    __IO uint16_t DATAR18;
+    uint16_t      RESERVED21;
+    __IO uint16_t DATAR19;
+    uint16_t      RESERVED22;
+    __IO uint16_t DATAR20;
+    uint16_t      RESERVED23;
+    __IO uint16_t DATAR21;
+    uint16_t      RESERVED24;
+    __IO uint16_t DATAR22;
+    uint16_t      RESERVED25;
+    __IO uint16_t DATAR23;
+    uint16_t      RESERVED26;
+    __IO uint16_t DATAR24;
+    uint16_t      RESERVED27;
+    __IO uint16_t DATAR25;
+    uint16_t      RESERVED28;
+    __IO uint16_t DATAR26;
+    uint16_t      RESERVED29;
+    __IO uint16_t DATAR27;
+    uint16_t      RESERVED30;
+    __IO uint16_t DATAR28;
+    uint16_t      RESERVED31;
+    __IO uint16_t DATAR29;
+    uint16_t      RESERVED32;
+    __IO uint16_t DATAR30;
+    uint16_t      RESERVED33;
+    __IO uint16_t DATAR31;
+    uint16_t      RESERVED34;
+    __IO uint16_t DATAR32;
+    uint16_t      RESERVED35;
+    __IO uint16_t DATAR33;
+    uint16_t      RESERVED36;
+    __IO uint16_t DATAR34;
+    uint16_t      RESERVED37;
+    __IO uint16_t DATAR35;
+    uint16_t      RESERVED38;
+    __IO uint16_t DATAR36;
+    uint16_t      RESERVED39;
+    __IO uint16_t DATAR37;
+    uint16_t      RESERVED40;
+    __IO uint16_t DATAR38;
+    uint16_t      RESERVED41;
+    __IO uint16_t DATAR39;
+    uint16_t      RESERVED42;
+    __IO uint16_t DATAR40;
+    uint16_t      RESERVED43;
+    __IO uint16_t DATAR41;
+    uint16_t      RESERVED44;
+    __IO uint16_t DATAR42;
+    uint16_t      RESERVED45;
+} BKP_TypeDef;
+
+/* CRC Calculation Unit */
+typedef struct
+{
+    __IO uint32_t DATAR;
+    __IO uint8_t  IDATAR;
+    uint8_t       RESERVED0;
+    uint16_t      RESERVED1;
+    __IO uint32_t CTLR;
+} CRC_TypeDef;
+
+/* Digital to Analog Converter */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t SWTR;
+    __IO uint32_t R12BDHR1;
+    __IO uint32_t L12BDHR1;
+    __IO uint32_t R8BDHR1;
+    __IO uint32_t R12BDHR2;
+    __IO uint32_t L12BDHR2;
+    __IO uint32_t R8BDHR2;
+    __IO uint32_t RD12BDHR;
+    __IO uint32_t LD12BDHR;
+    __IO uint32_t RD8BDHR;
+    __IO uint32_t DOR1;
+    __IO uint32_t DOR2;
+} DAC_TypeDef;
+
+/* Debug MCU */
+typedef struct
+{
+    __IO uint32_t CFGR0;
+    __IO uint32_t CFGR1;
+} DBGMCU_TypeDef;
+
+/* DMA Controller */
+typedef struct
+{
+    __IO uint32_t CFGR;
+    __IO uint32_t CNTR;
+    __IO uint32_t PADDR;
+    __IO uint32_t MADDR;
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t INTFR;
+    __IO uint32_t INTFCR;
+} DMA_TypeDef;
+
+/* External Interrupt/Event Controller */
+typedef struct
+{
+    __IO uint32_t INTENR;
+    __IO uint32_t EVENR;
+    __IO uint32_t RTENR;
+    __IO uint32_t FTENR;
+    __IO uint32_t SWIEVR;
+    __IO uint32_t INTFR;
+} EXTI_TypeDef;
+
+/* FLASH Registers */
+typedef struct
+{
+    __IO uint32_t ACTLR;
+    __IO uint32_t KEYR;
+    __IO uint32_t OBKEYR;
+    __IO uint32_t STATR;
+    __IO uint32_t CTLR;
+    __IO uint32_t ADDR;
+    __IO uint32_t RESERVED;
+    __IO uint32_t OBR;
+    __IO uint32_t WPR;
+    __IO uint32_t MODEKEYR;
+} FLASH_TypeDef;
+
+/* Option Bytes Registers */
+typedef struct
+{
+    __IO uint16_t RDPR;
+    __IO uint16_t USER;
+    __IO uint16_t Data0;
+    __IO uint16_t Data1;
+    __IO uint16_t WRPR0;
+    __IO uint16_t WRPR1;
+    __IO uint16_t WRPR2;
+    __IO uint16_t WRPR3;
+} OB_TypeDef;
+
+/* General Purpose I/O */
+typedef struct
+{
+    __IO uint32_t CFGLR;
+    __IO uint32_t CFGHR;
+    __IO uint32_t INDR;
+    __IO uint32_t OUTDR;
+    __IO uint32_t BSHR;
+    __IO uint32_t BCR;
+    __IO uint32_t LCKR;
+} GPIO_TypeDef;
+
+/* Alternate Function I/O */
+typedef struct
+{
+    __IO uint32_t ECR;
+    __IO uint32_t PCFR1;
+    __IO uint32_t EXTICR[4];
+    uint32_t      RESERVED0;
+    __IO uint32_t PCFR2;
+} AFIO_TypeDef;
+
+/* Inter Integrated Circuit Interface */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t OADDR1;
+    uint16_t      RESERVED2;
+    __IO uint16_t OADDR2;
+    uint16_t      RESERVED3;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED4;
+    __IO uint16_t STAR1;
+    uint16_t      RESERVED5;
+    __IO uint16_t STAR2;
+    uint16_t      RESERVED6;
+    __IO uint16_t CKCFGR;
+    uint16_t      RESERVED7;
+    __IO uint16_t RTR;
+    uint16_t      RESERVED8;
+} I2C_TypeDef;
+
+/* Independent WatchDog */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t PSCR;
+    __IO uint32_t RLDR;
+    __IO uint32_t STATR;
+} IWDG_TypeDef;
+
+/* Power Control */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CSR;
+} PWR_TypeDef;
+
+/* Reset and Clock Control */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CFGR0;
+    __IO uint32_t INTR;
+    __IO uint32_t APB2PRSTR;
+    __IO uint32_t APB1PRSTR;
+    __IO uint32_t AHBPCENR;
+    __IO uint32_t APB2PCENR;
+    __IO uint32_t APB1PCENR;
+    __IO uint32_t BDCTLR;
+    __IO uint32_t RSTSCKR;
+} RCC_TypeDef;
+
+/* Real-Time Clock */
+typedef struct
+{
+    __IO uint16_t CTLRH;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLRL;
+    uint16_t      RESERVED1;
+    __IO uint16_t PSCRH;
+    uint16_t      RESERVED2;
+    __IO uint16_t PSCRL;
+    uint16_t      RESERVED3;
+    __IO uint16_t DIVH;
+    uint16_t      RESERVED4;
+    __IO uint16_t DIVL;
+    uint16_t      RESERVED5;
+    __IO uint16_t CNTH;
+    uint16_t      RESERVED6;
+    __IO uint16_t CNTL;
+    uint16_t      RESERVED7;
+    __IO uint16_t ALRMH;
+    uint16_t      RESERVED8;
+    __IO uint16_t ALRML;
+    uint16_t      RESERVED9;
+} RTC_TypeDef;
+
+/* Serial Peripheral Interface */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t STATR;
+    uint16_t      RESERVED2;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED3;
+    __IO uint16_t CRCR;
+    uint16_t      RESERVED4;
+    __IO uint16_t RCRCR;
+    uint16_t      RESERVED5;
+    __IO uint16_t TCRCR;
+    uint16_t      RESERVED6;
+    __IO uint16_t I2SCFGR;
+    uint16_t      RESERVED7;
+    __IO uint16_t I2SPR;
+    uint16_t      RESERVED8;
+} SPI_TypeDef;
+
+/* TIM */
+typedef struct
+{
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED0;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED1;
+    __IO uint16_t SMCFGR;
+    uint16_t      RESERVED2;
+    __IO uint16_t DMAINTENR;
+    uint16_t      RESERVED3;
+    __IO uint16_t INTFR;
+    uint16_t      RESERVED4;
+    __IO uint16_t SWEVGR;
+    uint16_t      RESERVED5;
+    __IO uint16_t CHCTLR1;
+    uint16_t      RESERVED6;
+    __IO uint16_t CHCTLR2;
+    uint16_t      RESERVED7;
+    __IO uint16_t CCER;
+    uint16_t      RESERVED8;
+    __IO uint16_t CNT;
+    uint16_t      RESERVED9;
+    __IO uint16_t PSC;
+    uint16_t      RESERVED10;
+    __IO uint16_t ATRLR;
+    uint16_t      RESERVED11;
+    __IO uint16_t RPTCR;
+    uint16_t      RESERVED12;
+    __IO uint16_t CH1CVR;
+    uint16_t      RESERVED13;
+    __IO uint16_t CH2CVR;
+    uint16_t      RESERVED14;
+    __IO uint16_t CH3CVR;
+    uint16_t      RESERVED15;
+    __IO uint16_t CH4CVR;
+    uint16_t      RESERVED16;
+    __IO uint16_t BDTR;
+    uint16_t      RESERVED17;
+    __IO uint16_t DMACFGR;
+    uint16_t      RESERVED18;
+    __IO uint16_t DMAADR;
+    uint16_t      RESERVED19;
+} TIM_TypeDef;
+
+/* Universal Synchronous Asynchronous Receiver Transmitter */
+typedef struct
+{
+    __IO uint16_t STATR;
+    uint16_t      RESERVED0;
+    __IO uint16_t DATAR;
+    uint16_t      RESERVED1;
+    __IO uint16_t BRR;
+    uint16_t      RESERVED2;
+    __IO uint16_t CTLR1;
+    uint16_t      RESERVED3;
+    __IO uint16_t CTLR2;
+    uint16_t      RESERVED4;
+    __IO uint16_t CTLR3;
+    uint16_t      RESERVED5;
+    __IO uint16_t GPR;
+    uint16_t      RESERVED6;
+} USART_TypeDef;
+
+/* Window WatchDog */
+typedef struct
+{
+    __IO uint32_t CTLR;
+    __IO uint32_t CFGR;
+    __IO uint32_t STATR;
+} WWDG_TypeDef;
+
+/* Enhanced Registers */
+typedef struct
+{
+    __IO uint32_t EXTEN_CTR;
+} EXTEN_TypeDef;
+
+/* Peripheral memory map */
+#define FLASH_BASE                              ((uint32_t)0x08000000) /* FLASH base address in the alias region */
+#define SRAM_BASE                               ((uint32_t)0x20000000) /* SRAM base address in the alias region */
+#define PERIPH_BASE                             ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
+
+#define APB1PERIPH_BASE                         (PERIPH_BASE)
+#define APB2PERIPH_BASE                         (PERIPH_BASE + 0x10000)
+#define AHBPERIPH_BASE                          (PERIPH_BASE + 0x20000)
+
+#define TIM2_BASE                               (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE                               (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE                               (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE                               (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE                               (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE                               (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE                              (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE                              (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE                              (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE                                (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE                               (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE                               (APB1PERIPH_BASE + 0x3000)
+#define SPI2_BASE                               (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE                               (APB1PERIPH_BASE + 0x3C00)
+#define USART2_BASE                             (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE                             (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE                              (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE                              (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE                               (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE                               (APB1PERIPH_BASE + 0x5800)
+#define BKP_BASE                                (APB1PERIPH_BASE + 0x6C00)
+#define PWR_BASE                                (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE                                (APB1PERIPH_BASE + 0x7400)
+
+#define AFIO_BASE                               (APB2PERIPH_BASE + 0x0000)
+#define EXTI_BASE                               (APB2PERIPH_BASE + 0x0400)
+#define GPIOA_BASE                              (APB2PERIPH_BASE + 0x0800)
+#define GPIOB_BASE                              (APB2PERIPH_BASE + 0x0C00)
+#define GPIOC_BASE                              (APB2PERIPH_BASE + 0x1000)
+#define GPIOD_BASE                              (APB2PERIPH_BASE + 0x1400)
+#define GPIOE_BASE                              (APB2PERIPH_BASE + 0x1800)
+#define GPIOF_BASE                              (APB2PERIPH_BASE + 0x1C00)
+#define GPIOG_BASE                              (APB2PERIPH_BASE + 0x2000)
+#define ADC1_BASE                               (APB2PERIPH_BASE + 0x2400)
+#define ADC2_BASE                               (APB2PERIPH_BASE + 0x2800)
+#define TIM1_BASE                               (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE                               (APB2PERIPH_BASE + 0x3000)
+#define TIM8_BASE                               (APB2PERIPH_BASE + 0x3400)
+#define USART1_BASE                             (APB2PERIPH_BASE + 0x3800)
+#define ADC3_BASE                               (APB2PERIPH_BASE + 0x3C00)
+#define TIM15_BASE                              (APB2PERIPH_BASE + 0x4000)
+#define TIM16_BASE                              (APB2PERIPH_BASE + 0x4400)
+#define TIM17_BASE                              (APB2PERIPH_BASE + 0x4800)
+#define TIM9_BASE                               (APB2PERIPH_BASE + 0x4C00)
+#define TIM10_BASE                              (APB2PERIPH_BASE + 0x5000)
+#define TIM11_BASE                              (APB2PERIPH_BASE + 0x5400)
+
+#define DMA1_BASE                               (AHBPERIPH_BASE + 0x0000)
+#define DMA1_Channel1_BASE                      (AHBPERIPH_BASE + 0x0008)
+#define DMA1_Channel2_BASE                      (AHBPERIPH_BASE + 0x001C)
+#define DMA1_Channel3_BASE                      (AHBPERIPH_BASE + 0x0030)
+#define DMA1_Channel4_BASE                      (AHBPERIPH_BASE + 0x0044)
+#define DMA1_Channel5_BASE                      (AHBPERIPH_BASE + 0x0058)
+#define DMA1_Channel6_BASE                      (AHBPERIPH_BASE + 0x006C)
+#define DMA1_Channel7_BASE                      (AHBPERIPH_BASE + 0x0080)
+#define DMA2_BASE                               (AHBPERIPH_BASE + 0x0400)
+#define DMA2_Channel1_BASE                      (AHBPERIPH_BASE + 0x0408)
+#define DMA2_Channel2_BASE                      (AHBPERIPH_BASE + 0x041C)
+#define DMA2_Channel3_BASE                      (AHBPERIPH_BASE + 0x0430)
+#define DMA2_Channel4_BASE                      (AHBPERIPH_BASE + 0x0444)
+#define DMA2_Channel5_BASE                      (AHBPERIPH_BASE + 0x0458)
+#define RCC_BASE                                (AHBPERIPH_BASE + 0x1000)
+#define CRC_BASE                                (AHBPERIPH_BASE + 0x3000)
+
+#define FLASH_R_BASE                            (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
+#define OB_BASE                                 ((uint32_t)0x1FFFF800)    /* Flash Option Bytes base address */
+#define DBGMCU_BASE                             ((uint32_t)0xE000D000)
+#define EXTEN_BASE                              ((uint32_t)0x40023800)
+
+/* Peripheral declaration */
+#define TIM2                                    ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3                                    ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4                                    ((TIM_TypeDef *)TIM4_BASE)
+#define TIM5                                    ((TIM_TypeDef *)TIM5_BASE)
+#define TIM6                                    ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7                                    ((TIM_TypeDef *)TIM7_BASE)
+#define TIM12                                   ((TIM_TypeDef *)TIM12_BASE)
+#define TIM13                                   ((TIM_TypeDef *)TIM13_BASE)
+#define TIM14                                   ((TIM_TypeDef *)TIM14_BASE)
+#define RTC                                     ((RTC_TypeDef *)RTC_BASE)
+#define WWDG                                    ((WWDG_TypeDef *)WWDG_BASE)
+#define IWDG                                    ((IWDG_TypeDef *)IWDG_BASE)
+#define SPI2                                    ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3                                    ((SPI_TypeDef *)SPI3_BASE)
+#define USART2                                  ((USART_TypeDef *)USART2_BASE)
+#define USART3                                  ((USART_TypeDef *)USART3_BASE)
+#define UART4                                   ((USART_TypeDef *)UART4_BASE)
+#define UART5                                   ((USART_TypeDef *)UART5_BASE)
+#define I2C1                                    ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2                                    ((I2C_TypeDef *)I2C2_BASE)
+#define BKP                                     ((BKP_TypeDef *)BKP_BASE)
+#define PWR                                     ((PWR_TypeDef *)PWR_BASE)
+#define DAC                                     ((DAC_TypeDef *)DAC_BASE)
+#define AFIO                                    ((AFIO_TypeDef *)AFIO_BASE)
+#define EXTI                                    ((EXTI_TypeDef *)EXTI_BASE)
+#define GPIOA                                   ((GPIO_TypeDef *)GPIOA_BASE)
+#define GPIOB                                   ((GPIO_TypeDef *)GPIOB_BASE)
+#define GPIOC                                   ((GPIO_TypeDef *)GPIOC_BASE)
+#define GPIOD                                   ((GPIO_TypeDef *)GPIOD_BASE)
+#define GPIOE                                   ((GPIO_TypeDef *)GPIOE_BASE)
+#define GPIOF                                   ((GPIO_TypeDef *)GPIOF_BASE)
+#define GPIOG                                   ((GPIO_TypeDef *)GPIOG_BASE)
+#define ADC1                                    ((ADC_TypeDef *)ADC1_BASE)
+#define ADC2                                    ((ADC_TypeDef *)ADC2_BASE)
+#define TIM1                                    ((TIM_TypeDef *)TIM1_BASE)
+#define SPI1                                    ((SPI_TypeDef *)SPI1_BASE)
+#define TIM8                                    ((TIM_TypeDef *)TIM8_BASE)
+#define USART1                                  ((USART_TypeDef *)USART1_BASE)
+#define ADC3                                    ((ADC_TypeDef *)ADC3_BASE)
+#define TIM15                                   ((TIM_TypeDef *)TIM15_BASE)
+#define TIM16                                   ((TIM_TypeDef *)TIM16_BASE)
+#define TIM17                                   ((TIM_TypeDef *)TIM17_BASE)
+#define TIM9                                    ((TIM_TypeDef *)TIM9_BASE)
+#define TIM10                                   ((TIM_TypeDef *)TIM10_BASE)
+#define TIM11                                   ((TIM_TypeDef *)TIM11_BASE)
+#define DMA1                                    ((DMA_TypeDef *)DMA1_BASE)
+#define DMA2                                    ((DMA_TypeDef *)DMA2_BASE)
+#define DMA1_Channel1                           ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
+#define DMA1_Channel2                           ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
+#define DMA1_Channel3                           ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
+#define DMA1_Channel4                           ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
+#define DMA1_Channel5                           ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
+#define DMA1_Channel6                           ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
+#define DMA1_Channel7                           ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
+#define DMA2_Channel1                           ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)
+#define DMA2_Channel2                           ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)
+#define DMA2_Channel3                           ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)
+#define DMA2_Channel4                           ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)
+#define DMA2_Channel5                           ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)
+#define RCC                                     ((RCC_TypeDef *)RCC_BASE)
+#define CRC                                     ((CRC_TypeDef *)CRC_BASE)
+#define FLASH                                   ((FLASH_TypeDef *)FLASH_R_BASE)
+#define OB                                      ((OB_TypeDef *)OB_BASE)
+#define DBGMCU                                  ((DBGMCU_TypeDef *)DBGMCU_BASE)
+#define EXTEN                                   ((EXTEN_TypeDef *)EXTEN_BASE)
+
+/******************************************************************************/
+/*                         Peripheral Registers Bits Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                        Analog to Digital Converter                         */
+/******************************************************************************/
+
+/********************  Bit definition for ADC_STATR register  ********************/
+#define ADC_AWD                                 ((uint8_t)0x01) /* Analog watchdog flag */
+#define ADC_EOC                                 ((uint8_t)0x02) /* End of conversion */
+#define ADC_JEOC                                ((uint8_t)0x04) /* Injected channel end of conversion */
+#define ADC_JSTRT                               ((uint8_t)0x08) /* Injected channel Start flag */
+#define ADC_STRT                                ((uint8_t)0x10) /* Regular channel Start flag */
+
+/*******************  Bit definition for ADC_CTLR1 register  ********************/
+#define ADC_AWDCH                               ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
+#define ADC_AWDCH_0                             ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_AWDCH_1                             ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_AWDCH_2                             ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_AWDCH_3                             ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_AWDCH_4                             ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_EOCIE                               ((uint32_t)0x00000020) /* Interrupt enable for EOC */
+#define ADC_AWDIE                               ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */
+#define ADC_JEOCIE                              ((uint32_t)0x00000080) /* Interrupt enable for injected channels */
+#define ADC_SCAN                                ((uint32_t)0x00000100) /* Scan mode */
+#define ADC_AWDSGL                              ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */
+#define ADC_JAUTO                               ((uint32_t)0x00000400) /* Automatic injected group conversion */
+#define ADC_DISCEN                              ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */
+#define ADC_JDISCEN                             ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */
+
+#define ADC_DISCNUM                             ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
+#define ADC_DISCNUM_0                           ((uint32_t)0x00002000) /* Bit 0 */
+#define ADC_DISCNUM_1                           ((uint32_t)0x00004000) /* Bit 1 */
+#define ADC_DISCNUM_2                           ((uint32_t)0x00008000) /* Bit 2 */
+
+#define ADC_DUALMOD                             ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
+#define ADC_DUALMOD_0                           ((uint32_t)0x00010000) /* Bit 0 */
+#define ADC_DUALMOD_1                           ((uint32_t)0x00020000) /* Bit 1 */
+#define ADC_DUALMOD_2                           ((uint32_t)0x00040000) /* Bit 2 */
+#define ADC_DUALMOD_3                           ((uint32_t)0x00080000) /* Bit 3 */
+
+#define ADC_JAWDEN                              ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */
+#define ADC_AWDEN                               ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */
+
+/*******************  Bit definition for ADC_CTLR2 register  ********************/
+#define ADC_ADON                                ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
+#define ADC_CONT                                ((uint32_t)0x00000002) /* Continuous Conversion */
+#define ADC_CAL                                 ((uint32_t)0x00000004) /* A/D Calibration */
+#define ADC_RSTCAL                              ((uint32_t)0x00000008) /* Reset Calibration */
+#define ADC_DMA                                 ((uint32_t)0x00000100) /* Direct Memory access mode */
+#define ADC_ALIGN                               ((uint32_t)0x00000800) /* Data Alignment */
+
+#define ADC_JEXTSEL                             ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
+#define ADC_JEXTSEL_0                           ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_JEXTSEL_1                           ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_JEXTSEL_2                           ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_JEXTTRIG                            ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */
+
+#define ADC_EXTSEL                              ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
+#define ADC_EXTSEL_0                            ((uint32_t)0x00020000) /* Bit 0 */
+#define ADC_EXTSEL_1                            ((uint32_t)0x00040000) /* Bit 1 */
+#define ADC_EXTSEL_2                            ((uint32_t)0x00080000) /* Bit 2 */
+
+#define ADC_EXTTRIG                             ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */
+#define ADC_JSWSTART                            ((uint32_t)0x00200000) /* Start Conversion of injected channels */
+#define ADC_SWSTART                             ((uint32_t)0x00400000) /* Start Conversion of regular channels */
+#define ADC_TSVREFE                             ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */
+
+/******************  Bit definition for ADC_SAMPTR1 register  *******************/
+#define ADC_SMP10                               ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
+#define ADC_SMP10_0                             ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SMP10_1                             ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SMP10_2                             ((uint32_t)0x00000004) /* Bit 2 */
+
+#define ADC_SMP11                               ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
+#define ADC_SMP11_0                             ((uint32_t)0x00000008) /* Bit 0 */
+#define ADC_SMP11_1                             ((uint32_t)0x00000010) /* Bit 1 */
+#define ADC_SMP11_2                             ((uint32_t)0x00000020) /* Bit 2 */
+
+#define ADC_SMP12                               ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
+#define ADC_SMP12_0                             ((uint32_t)0x00000040) /* Bit 0 */
+#define ADC_SMP12_1                             ((uint32_t)0x00000080) /* Bit 1 */
+#define ADC_SMP12_2                             ((uint32_t)0x00000100) /* Bit 2 */
+
+#define ADC_SMP13                               ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
+#define ADC_SMP13_0                             ((uint32_t)0x00000200) /* Bit 0 */
+#define ADC_SMP13_1                             ((uint32_t)0x00000400) /* Bit 1 */
+#define ADC_SMP13_2                             ((uint32_t)0x00000800) /* Bit 2 */
+
+#define ADC_SMP14                               ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
+#define ADC_SMP14_0                             ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_SMP14_1                             ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_SMP14_2                             ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_SMP15                               ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
+#define ADC_SMP15_0                             ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SMP15_1                             ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SMP15_2                             ((uint32_t)0x00020000) /* Bit 2 */
+
+#define ADC_SMP16                               ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
+#define ADC_SMP16_0                             ((uint32_t)0x00040000) /* Bit 0 */
+#define ADC_SMP16_1                             ((uint32_t)0x00080000) /* Bit 1 */
+#define ADC_SMP16_2                             ((uint32_t)0x00100000) /* Bit 2 */
+
+#define ADC_SMP17                               ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
+#define ADC_SMP17_0                             ((uint32_t)0x00200000) /* Bit 0 */
+#define ADC_SMP17_1                             ((uint32_t)0x00400000) /* Bit 1 */
+#define ADC_SMP17_2                             ((uint32_t)0x00800000) /* Bit 2 */
+
+/******************  Bit definition for ADC_SAMPTR2 register  *******************/
+#define ADC_SMP0                                ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
+#define ADC_SMP0_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SMP0_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SMP0_2                              ((uint32_t)0x00000004) /* Bit 2 */
+
+#define ADC_SMP1                                ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
+#define ADC_SMP1_0                              ((uint32_t)0x00000008) /* Bit 0 */
+#define ADC_SMP1_1                              ((uint32_t)0x00000010) /* Bit 1 */
+#define ADC_SMP1_2                              ((uint32_t)0x00000020) /* Bit 2 */
+
+#define ADC_SMP2                                ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
+#define ADC_SMP2_0                              ((uint32_t)0x00000040) /* Bit 0 */
+#define ADC_SMP2_1                              ((uint32_t)0x00000080) /* Bit 1 */
+#define ADC_SMP2_2                              ((uint32_t)0x00000100) /* Bit 2 */
+
+#define ADC_SMP3                                ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
+#define ADC_SMP3_0                              ((uint32_t)0x00000200) /* Bit 0 */
+#define ADC_SMP3_1                              ((uint32_t)0x00000400) /* Bit 1 */
+#define ADC_SMP3_2                              ((uint32_t)0x00000800) /* Bit 2 */
+
+#define ADC_SMP4                                ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
+#define ADC_SMP4_0                              ((uint32_t)0x00001000) /* Bit 0 */
+#define ADC_SMP4_1                              ((uint32_t)0x00002000) /* Bit 1 */
+#define ADC_SMP4_2                              ((uint32_t)0x00004000) /* Bit 2 */
+
+#define ADC_SMP5                                ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
+#define ADC_SMP5_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SMP5_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SMP5_2                              ((uint32_t)0x00020000) /* Bit 2 */
+
+#define ADC_SMP6                                ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
+#define ADC_SMP6_0                              ((uint32_t)0x00040000) /* Bit 0 */
+#define ADC_SMP6_1                              ((uint32_t)0x00080000) /* Bit 1 */
+#define ADC_SMP6_2                              ((uint32_t)0x00100000) /* Bit 2 */
+
+#define ADC_SMP7                                ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
+#define ADC_SMP7_0                              ((uint32_t)0x00200000) /* Bit 0 */
+#define ADC_SMP7_1                              ((uint32_t)0x00400000) /* Bit 1 */
+#define ADC_SMP7_2                              ((uint32_t)0x00800000) /* Bit 2 */
+
+#define ADC_SMP8                                ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
+#define ADC_SMP8_0                              ((uint32_t)0x01000000) /* Bit 0 */
+#define ADC_SMP8_1                              ((uint32_t)0x02000000) /* Bit 1 */
+#define ADC_SMP8_2                              ((uint32_t)0x04000000) /* Bit 2 */
+
+#define ADC_SMP9                                ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
+#define ADC_SMP9_0                              ((uint32_t)0x08000000) /* Bit 0 */
+#define ADC_SMP9_1                              ((uint32_t)0x10000000) /* Bit 1 */
+#define ADC_SMP9_2                              ((uint32_t)0x20000000) /* Bit 2 */
+
+/******************  Bit definition for ADC_IOFR1 register  *******************/
+#define ADC_JOFFSET1                            ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */
+
+/******************  Bit definition for ADC_IOFR2 register  *******************/
+#define ADC_JOFFSET2                            ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */
+
+/******************  Bit definition for ADC_IOFR3 register  *******************/
+#define ADC_JOFFSET3                            ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */
+
+/******************  Bit definition for ADC_IOFR4 register  *******************/
+#define ADC_JOFFSET4                            ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */
+
+/*******************  Bit definition for ADC_WDHTR register  ********************/
+#define ADC_HT                                  ((uint16_t)0x0FFF) /* Analog watchdog high threshold */
+
+/*******************  Bit definition for ADC_WDLTR register  ********************/
+#define ADC_LT                                  ((uint16_t)0x0FFF) /* Analog watchdog low threshold */
+
+/*******************  Bit definition for ADC_RSQR1 register  *******************/
+#define ADC_SQ13                                ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
+#define ADC_SQ13_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ13_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ13_2                              ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ13_3                              ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ13_4                              ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ14                                ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
+#define ADC_SQ14_0                              ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ14_1                              ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ14_2                              ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ14_3                              ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ14_4                              ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ15                                ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
+#define ADC_SQ15_0                              ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ15_1                              ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ15_2                              ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ15_3                              ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ15_4                              ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ16                                ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
+#define ADC_SQ16_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ16_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ16_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ16_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ16_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_L                                   ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
+#define ADC_L_0                                 ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_L_1                                 ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_L_2                                 ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_L_3                                 ((uint32_t)0x00800000) /* Bit 3 */
+
+/*******************  Bit definition for ADC_RSQR2 register  *******************/
+#define ADC_SQ7                                 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
+#define ADC_SQ7_0                               ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ7_1                               ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ7_2                               ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ7_3                               ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ7_4                               ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ8                                 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
+#define ADC_SQ8_0                               ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ8_1                               ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ8_2                               ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ8_3                               ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ8_4                               ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ9                                 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
+#define ADC_SQ9_0                               ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ9_1                               ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ9_2                               ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ9_3                               ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ9_4                               ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ10                                ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
+#define ADC_SQ10_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ10_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ10_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ10_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ10_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_SQ11                                ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
+#define ADC_SQ11_0                              ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_SQ11_1                              ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_SQ11_2                              ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_SQ11_3                              ((uint32_t)0x00800000) /* Bit 3 */
+#define ADC_SQ11_4                              ((uint32_t)0x01000000) /* Bit 4 */
+
+#define ADC_SQ12                                ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
+#define ADC_SQ12_0                              ((uint32_t)0x02000000) /* Bit 0 */
+#define ADC_SQ12_1                              ((uint32_t)0x04000000) /* Bit 1 */
+#define ADC_SQ12_2                              ((uint32_t)0x08000000) /* Bit 2 */
+#define ADC_SQ12_3                              ((uint32_t)0x10000000) /* Bit 3 */
+#define ADC_SQ12_4                              ((uint32_t)0x20000000) /* Bit 4 */
+
+/*******************  Bit definition for ADC_RSQR3 register  *******************/
+#define ADC_SQ1                                 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
+#define ADC_SQ1_0                               ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_SQ1_1                               ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_SQ1_2                               ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_SQ1_3                               ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_SQ1_4                               ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_SQ2                                 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
+#define ADC_SQ2_0                               ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_SQ2_1                               ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_SQ2_2                               ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_SQ2_3                               ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_SQ2_4                               ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_SQ3                                 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
+#define ADC_SQ3_0                               ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_SQ3_1                               ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_SQ3_2                               ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_SQ3_3                               ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_SQ3_4                               ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_SQ4                                 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
+#define ADC_SQ4_0                               ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_SQ4_1                               ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_SQ4_2                               ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_SQ4_3                               ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_SQ4_4                               ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_SQ5                                 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
+#define ADC_SQ5_0                               ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_SQ5_1                               ((uint32_t)0x00200000) /* Bit 1 */
+#define ADC_SQ5_2                               ((uint32_t)0x00400000) /* Bit 2 */
+#define ADC_SQ5_3                               ((uint32_t)0x00800000) /* Bit 3 */
+#define ADC_SQ5_4                               ((uint32_t)0x01000000) /* Bit 4 */
+
+#define ADC_SQ6                                 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
+#define ADC_SQ6_0                               ((uint32_t)0x02000000) /* Bit 0 */
+#define ADC_SQ6_1                               ((uint32_t)0x04000000) /* Bit 1 */
+#define ADC_SQ6_2                               ((uint32_t)0x08000000) /* Bit 2 */
+#define ADC_SQ6_3                               ((uint32_t)0x10000000) /* Bit 3 */
+#define ADC_SQ6_4                               ((uint32_t)0x20000000) /* Bit 4 */
+
+/*******************  Bit definition for ADC_ISQR register  *******************/
+#define ADC_JSQ1                                ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
+#define ADC_JSQ1_0                              ((uint32_t)0x00000001) /* Bit 0 */
+#define ADC_JSQ1_1                              ((uint32_t)0x00000002) /* Bit 1 */
+#define ADC_JSQ1_2                              ((uint32_t)0x00000004) /* Bit 2 */
+#define ADC_JSQ1_3                              ((uint32_t)0x00000008) /* Bit 3 */
+#define ADC_JSQ1_4                              ((uint32_t)0x00000010) /* Bit 4 */
+
+#define ADC_JSQ2                                ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
+#define ADC_JSQ2_0                              ((uint32_t)0x00000020) /* Bit 0 */
+#define ADC_JSQ2_1                              ((uint32_t)0x00000040) /* Bit 1 */
+#define ADC_JSQ2_2                              ((uint32_t)0x00000080) /* Bit 2 */
+#define ADC_JSQ2_3                              ((uint32_t)0x00000100) /* Bit 3 */
+#define ADC_JSQ2_4                              ((uint32_t)0x00000200) /* Bit 4 */
+
+#define ADC_JSQ3                                ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
+#define ADC_JSQ3_0                              ((uint32_t)0x00000400) /* Bit 0 */
+#define ADC_JSQ3_1                              ((uint32_t)0x00000800) /* Bit 1 */
+#define ADC_JSQ3_2                              ((uint32_t)0x00001000) /* Bit 2 */
+#define ADC_JSQ3_3                              ((uint32_t)0x00002000) /* Bit 3 */
+#define ADC_JSQ3_4                              ((uint32_t)0x00004000) /* Bit 4 */
+
+#define ADC_JSQ4                                ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
+#define ADC_JSQ4_0                              ((uint32_t)0x00008000) /* Bit 0 */
+#define ADC_JSQ4_1                              ((uint32_t)0x00010000) /* Bit 1 */
+#define ADC_JSQ4_2                              ((uint32_t)0x00020000) /* Bit 2 */
+#define ADC_JSQ4_3                              ((uint32_t)0x00040000) /* Bit 3 */
+#define ADC_JSQ4_4                              ((uint32_t)0x00080000) /* Bit 4 */
+
+#define ADC_JL                                  ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
+#define ADC_JL_0                                ((uint32_t)0x00100000) /* Bit 0 */
+#define ADC_JL_1                                ((uint32_t)0x00200000) /* Bit 1 */
+
+/*******************  Bit definition for ADC_IDATAR1 register  *******************/
+#define ADC_IDATAR1_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR2 register  *******************/
+#define ADC_IDATAR2_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR3 register  *******************/
+#define ADC_IDATAR3_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/*******************  Bit definition for ADC_IDATAR4 register  *******************/
+#define ADC_IDATAR4_JDATA                       ((uint16_t)0xFFFF) /* Injected data */
+
+/********************  Bit definition for ADC_RDATAR register  ********************/
+#define ADC_RDATAR_DATA                         ((uint32_t)0x0000FFFF) /* Regular data */
+#define ADC_RDATAR_ADC2DATA                     ((uint32_t)0xFFFF0000) /* ADC2 data */
+
+/******************************************************************************/
+/*                            Backup registers                                */
+/******************************************************************************/
+
+/*******************  Bit definition for BKP_DATAR1 register  ********************/
+#define BKP_DATAR1_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR2 register  ********************/
+#define BKP_DATAR2_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR3 register  ********************/
+#define BKP_DATAR3_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR4 register  ********************/
+#define BKP_DATAR4_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR5 register  ********************/
+#define BKP_DATAR5_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR6 register  ********************/
+#define BKP_DATAR6_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR7 register  ********************/
+#define BKP_DATAR7_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR8 register  ********************/
+#define BKP_DATAR8_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR9 register  ********************/
+#define BKP_DATAR9_D                            ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR10 register  *******************/
+#define BKP_DATAR10_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR11 register  *******************/
+#define BKP_DATAR11_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR12 register  *******************/
+#define BKP_DATAR12_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR13 register  *******************/
+#define BKP_DATAR13_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR14 register  *******************/
+#define BKP_DATAR14_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR15 register  *******************/
+#define BKP_DATAR15_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR16 register  *******************/
+#define BKP_DATAR16_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR17 register  *******************/
+#define BKP_DATAR17_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/******************  Bit definition for BKP_DATAR18 register  ********************/
+#define BKP_DATAR18_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR19 register  *******************/
+#define BKP_DATAR19_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR20 register  *******************/
+#define BKP_DATAR20_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR21 register  *******************/
+#define BKP_DATAR21_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR22 register  *******************/
+#define BKP_DATAR22_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR23 register  *******************/
+#define BKP_DATAR23_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR24 register  *******************/
+#define BKP_DATAR24_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR25 register  *******************/
+#define BKP_DATAR25_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR26 register  *******************/
+#define BKP_DATAR26_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR27 register  *******************/
+#define BKP_DATAR27_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR28 register  *******************/
+#define BKP_DATAR28_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR29 register  *******************/
+#define BKP_DATAR29_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR30 register  *******************/
+#define BKP_DATAR30_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR31 register  *******************/
+#define BKP_DATAR31_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR32 register  *******************/
+#define BKP_DATAR32_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR33 register  *******************/
+#define BKP_DATAR33_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR34 register  *******************/
+#define BKP_DATAR34_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR35 register  *******************/
+#define BKP_DATAR35_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR36 register  *******************/
+#define BKP_DATAR36_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR37 register  *******************/
+#define BKP_DATAR37_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR38 register  *******************/
+#define BKP_DATAR38_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR39 register  *******************/
+#define BKP_DATAR39_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR40 register  *******************/
+#define BKP_DATAR40_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR41 register  *******************/
+#define BKP_DATAR41_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/*******************  Bit definition for BKP_DATAR42 register  *******************/
+#define BKP_DATAR42_D                           ((uint16_t)0xFFFF) /* Backup data */
+
+/******************  Bit definition for BKP_OCTLR register  *******************/
+#define BKP_CAL                                 ((uint16_t)0x007F) /* Calibration value */
+#define BKP_CCO                                 ((uint16_t)0x0080) /* Calibration Clock Output */
+#define BKP_ASOE                                ((uint16_t)0x0100) /* Alarm or Second Output Enable */
+#define BKP_ASOS                                ((uint16_t)0x0200) /* Alarm or Second Output Selection */
+
+/********************  Bit definition for BKP_TPCTLR register  ********************/
+#define BKP_TPE                                 ((uint8_t)0x01) /* TAMPER pin enable */
+#define BKP_TPAL                                ((uint8_t)0x02) /* TAMPER pin active level */
+
+/*******************  Bit definition for BKP_TPCSR register  ********************/
+#define BKP_CTE                                 ((uint16_t)0x0001) /* Clear Tamper event */
+#define BKP_CTI                                 ((uint16_t)0x0002) /* Clear Tamper Interrupt */
+#define BKP_TPIE                                ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */
+#define BKP_TEF                                 ((uint16_t)0x0100) /* Tamper Event Flag */
+#define BKP_TIF                                 ((uint16_t)0x0200) /* Tamper Interrupt Flag */
+
+/******************************************************************************/
+/*                          CRC Calculation Unit                              */
+/******************************************************************************/
+
+/*******************  Bit definition for CRC_DATAR register  *********************/
+#define CRC_DATAR_DR                            ((uint32_t)0xFFFFFFFF) /* Data register bits */
+
+/*******************  Bit definition for CRC_IDATAR register  ********************/
+#define CRC_IDR_IDATAR                          ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */
+
+/********************  Bit definition for CRC_CTLR register  ********************/
+#define CRC_CTLR_RESET                          ((uint8_t)0x01) /* RESET bit */
+
+/******************************************************************************/
+/*                      Digital to Analog Converter                           */
+/******************************************************************************/
+
+/********************  Bit definition for DAC_CTLR register  ********************/
+#define DAC_EN1                                 ((uint32_t)0x00000001) /* DAC channel1 enable */
+#define DAC_BOFF1                               ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */
+#define DAC_TEN1                                ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */
+
+#define DAC_TSEL1                               ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */
+#define DAC_TSEL1_0                             ((uint32_t)0x00000008) /* Bit 0 */
+#define DAC_TSEL1_1                             ((uint32_t)0x00000010) /* Bit 1 */
+#define DAC_TSEL1_2                             ((uint32_t)0x00000020) /* Bit 2 */
+
+#define DAC_WAVE1                               ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_WAVE1_0                             ((uint32_t)0x00000040) /* Bit 0 */
+#define DAC_WAVE1_1                             ((uint32_t)0x00000080) /* Bit 1 */
+
+#define DAC_MAMP1                               ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_MAMP1_0                             ((uint32_t)0x00000100) /* Bit 0 */
+#define DAC_MAMP1_1                             ((uint32_t)0x00000200) /* Bit 1 */
+#define DAC_MAMP1_2                             ((uint32_t)0x00000400) /* Bit 2 */
+#define DAC_MAMP1_3                             ((uint32_t)0x00000800) /* Bit 3 */
+
+#define DAC_DMAEN1                              ((uint32_t)0x00001000) /* DAC channel1 DMA enable */
+#define DAC_EN2                                 ((uint32_t)0x00010000) /* DAC channel2 enable */
+#define DAC_BOFF2                               ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */
+#define DAC_TEN2                                ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */
+
+#define DAC_TSEL2                               ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_TSEL2_0                             ((uint32_t)0x00080000) /* Bit 0 */
+#define DAC_TSEL2_1                             ((uint32_t)0x00100000) /* Bit 1 */
+#define DAC_TSEL2_2                             ((uint32_t)0x00200000) /* Bit 2 */
+
+#define DAC_WAVE2                               ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_WAVE2_0                             ((uint32_t)0x00400000) /* Bit 0 */
+#define DAC_WAVE2_1                             ((uint32_t)0x00800000) /* Bit 1 */
+
+#define DAC_MAMP2                               ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_MAMP2_0                             ((uint32_t)0x01000000) /* Bit 0 */
+#define DAC_MAMP2_1                             ((uint32_t)0x02000000) /* Bit 1 */
+#define DAC_MAMP2_2                             ((uint32_t)0x04000000) /* Bit 2 */
+#define DAC_MAMP2_3                             ((uint32_t)0x08000000) /* Bit 3 */
+
+#define DAC_DMAEN2                              ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */
+
+/*****************  Bit definition for DAC_SWTR register  ******************/
+#define DAC_SWTRIG1                             ((uint8_t)0x01) /* DAC channel1 software trigger */
+#define DAC_SWTRIG2                             ((uint8_t)0x02) /* DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_R12BDHR1 register  ******************/
+#define DAC_DHR12R1                             ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR1 register  ******************/
+#define DAC_DHR12L1                             ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR1 register  ******************/
+#define DAC_DHR8R1                              ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_R12BDHR2 register  ******************/
+#define DAC_DHR12R2                             ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_L12BDHR2 register  ******************/
+#define DAC_DHR12L2                             ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_R8BDHR2 register  ******************/
+#define DAC_DHR8R2                              ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_RD12BDHR register  ******************/
+#define DAC_RD12BDHR_DACC1DHR                   ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */
+#define DAC_RD12BDHR_DACC2DHR                   ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_LD12BDHR register  ******************/
+#define DAC_LD12BDHR_DACC1DHR                   ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */
+#define DAC_LD12BDHR_DACC2DHR                   ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_RD8BDHR register  ******************/
+#define DAC_RD8BDHR_DACC1DHR                    ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */
+#define DAC_RD8BDHR_DACC2DHR                    ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DACC1DOR                            ((uint16_t)0x0FFF) /* DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DACC2DOR                            ((uint16_t)0x0FFF) /* DAC channel2 data output */
+
+/******************************************************************************/
+/*                             DMA Controller                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for DMA_INTFR register  ********************/
+#define DMA_GIF1                                ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */
+#define DMA_TCIF1                               ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */
+#define DMA_HTIF1                               ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */
+#define DMA_TEIF1                               ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */
+#define DMA_GIF2                                ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */
+#define DMA_TCIF2                               ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */
+#define DMA_HTIF2                               ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */
+#define DMA_TEIF2                               ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */
+#define DMA_GIF3                                ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */
+#define DMA_TCIF3                               ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */
+#define DMA_HTIF3                               ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */
+#define DMA_TEIF3                               ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */
+#define DMA_GIF4                                ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */
+#define DMA_TCIF4                               ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */
+#define DMA_HTIF4                               ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */
+#define DMA_TEIF4                               ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */
+#define DMA_GIF5                                ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */
+#define DMA_TCIF5                               ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */
+#define DMA_HTIF5                               ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */
+#define DMA_TEIF5                               ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */
+#define DMA_GIF6                                ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */
+#define DMA_TCIF6                               ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */
+#define DMA_HTIF6                               ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */
+#define DMA_TEIF6                               ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */
+#define DMA_GIF7                                ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */
+#define DMA_TCIF7                               ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */
+#define DMA_HTIF7                               ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
+#define DMA_TEIF7                               ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
+
+/*******************  Bit definition for DMA_INTFCR register  *******************/
+#define DMA_CGIF1                               ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
+#define DMA_CTCIF1                              ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
+#define DMA_CHTIF1                              ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */
+#define DMA_CTEIF1                              ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */
+#define DMA_CGIF2                               ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */
+#define DMA_CTCIF2                              ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */
+#define DMA_CHTIF2                              ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */
+#define DMA_CTEIF2                              ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */
+#define DMA_CGIF3                               ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */
+#define DMA_CTCIF3                              ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */
+#define DMA_CHTIF3                              ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */
+#define DMA_CTEIF3                              ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */
+#define DMA_CGIF4                               ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */
+#define DMA_CTCIF4                              ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */
+#define DMA_CHTIF4                              ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */
+#define DMA_CTEIF4                              ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */
+#define DMA_CGIF5                               ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */
+#define DMA_CTCIF5                              ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */
+#define DMA_CHTIF5                              ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */
+#define DMA_CTEIF5                              ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */
+#define DMA_CGIF6                               ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */
+#define DMA_CTCIF6                              ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */
+#define DMA_CHTIF6                              ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */
+#define DMA_CTEIF6                              ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */
+#define DMA_CGIF7                               ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */
+#define DMA_CTCIF7                              ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */
+#define DMA_CHTIF7                              ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */
+#define DMA_CTEIF7                              ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */
+
+/*******************  Bit definition for DMA_CFGR1 register  *******************/
+#define DMA_CFGR1_EN                            ((uint16_t)0x0001) /* Channel enable*/
+#define DMA_CFGR1_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR1_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR1_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR1_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR1_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR1_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR1_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR1_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR1_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR1_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR1_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR1_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR1_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR1_PL                            ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */
+#define DMA_CFGR1_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR1_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR1_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR2 register  *******************/
+#define DMA_CFGR2_EN                            ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFGR2_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR2_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR2_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR2_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR2_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR2_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR2_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR2_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR2_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR2_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR2_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR2_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR2_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR2_PL                            ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFGR2_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR2_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR2_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFGR3 register  *******************/
+#define DMA_CFGR3_EN                            ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFGR3_TCIE                          ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFGR3_HTIE                          ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFGR3_TEIE                          ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFGR3_DIR                           ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFGR3_CIRC                          ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFGR3_PINC                          ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFGR3_MINC                          ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFGR3_PSIZE                         ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFGR3_PSIZE_0                       ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFGR3_PSIZE_1                       ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFGR3_MSIZE                         ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFGR3_MSIZE_0                       ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFGR3_MSIZE_1                       ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFGR3_PL                            ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFGR3_PL_0                          ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFGR3_PL_1                          ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFGR3_MEM2MEM                       ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG4 register  *******************/
+#define DMA_CFG4_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG4_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG4_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG4_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG4_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG4_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG4_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG4_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG4_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG4_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG4_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG4_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG4_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG4_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG4_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG4_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG4_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG4_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode */
+
+/******************  Bit definition for DMA_CFG5 register  *******************/
+#define DMA_CFG5_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG5_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG5_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG5_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG5_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG5_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG5_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG5_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG5_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG5_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG5_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG5_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG5_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG5_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG5_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG5_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG5_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG5_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode enable */
+
+/*******************  Bit definition for DMA_CFG6 register  *******************/
+#define DMA_CFG6_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG6_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG6_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG6_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG6_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG6_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG6_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG6_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG6_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG6_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG6_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG6_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG6_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG6_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG6_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG6_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG6_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG6_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode */
+
+/*******************  Bit definition for DMA_CFG7 register  *******************/
+#define DMA_CFG7_EN                             ((uint16_t)0x0001) /* Channel enable */
+#define DMA_CFG7_TCIE                           ((uint16_t)0x0002) /* Transfer complete interrupt enable */
+#define DMA_CFG7_HTIE                           ((uint16_t)0x0004) /* Half Transfer interrupt enable */
+#define DMA_CFG7_TEIE                           ((uint16_t)0x0008) /* Transfer error interrupt enable */
+#define DMA_CFG7_DIR                            ((uint16_t)0x0010) /* Data transfer direction */
+#define DMA_CFG7_CIRC                           ((uint16_t)0x0020) /* Circular mode */
+#define DMA_CFG7_PINC                           ((uint16_t)0x0040) /* Peripheral increment mode */
+#define DMA_CFG7_MINC                           ((uint16_t)0x0080) /* Memory increment mode */
+
+#define DMA_CFG7_PSIZE                          ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
+#define DMA_CFG7_PSIZE_0                        ((uint16_t)0x0100) /* Bit 0 */
+#define DMA_CFG7_PSIZE_1                        ((uint16_t)0x0200) /* Bit 1 */
+
+#define DMA_CFG7_MSIZE                          ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
+#define DMA_CFG7_MSIZE_0                        ((uint16_t)0x0400) /* Bit 0 */
+#define DMA_CFG7_MSIZE_1                        ((uint16_t)0x0800) /* Bit 1 */
+
+#define DMA_CFG7_PL                             ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
+#define DMA_CFG7_PL_0                           ((uint16_t)0x1000) /* Bit 0 */
+#define DMA_CFG7_PL_1                           ((uint16_t)0x2000) /* Bit 1 */
+
+#define DMA_CFG7_MEM2MEM                        ((uint16_t)0x4000) /* Memory to memory mode enable */
+
+/******************  Bit definition for DMA_CNTR1 register  ******************/
+#define DMA_CNTR1_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR2 register  ******************/
+#define DMA_CNTR2_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR3 register  ******************/
+#define DMA_CNTR3_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR4 register  ******************/
+#define DMA_CNTR4_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR5 register  ******************/
+#define DMA_CNTR5_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR6 register  ******************/
+#define DMA_CNTR6_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_CNTR7 register  ******************/
+#define DMA_CNTR7_NDT                           ((uint16_t)0xFFFF) /* Number of data to Transfer */
+
+/******************  Bit definition for DMA_PADDR1 register  *******************/
+#define DMA_PADDR1_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR2 register  *******************/
+#define DMA_PADDR2_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR3 register  *******************/
+#define DMA_PADDR3_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR4 register  *******************/
+#define DMA_PADDR4_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR5 register  *******************/
+#define DMA_PADDR5_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR6 register  *******************/
+#define DMA_PADDR6_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_PADDR7 register  *******************/
+#define DMA_PADDR7_PA                           ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
+
+/******************  Bit definition for DMA_MADDR1 register  *******************/
+#define DMA_MADDR1_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR2 register  *******************/
+#define DMA_MADDR2_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR3 register  *******************/
+#define DMA_MADDR3_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR4 register  *******************/
+#define DMA_MADDR4_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR5 register  *******************/
+#define DMA_MADDR5_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR6 register  *******************/
+#define DMA_MADDR6_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************  Bit definition for DMA_MADDR7 register  *******************/
+#define DMA_MADDR7_MA                           ((uint32_t)0xFFFFFFFF) /* Memory Address */
+
+/******************************************************************************/
+/*                    External Interrupt/Event Controller                     */
+/******************************************************************************/
+
+/*******************  Bit definition for EXTI_INTENR register  *******************/
+#define EXTI_INTENR_MR0                         ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */
+#define EXTI_INTENR_MR1                         ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */
+#define EXTI_INTENR_MR2                         ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */
+#define EXTI_INTENR_MR3                         ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */
+#define EXTI_INTENR_MR4                         ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */
+#define EXTI_INTENR_MR5                         ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */
+#define EXTI_INTENR_MR6                         ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */
+#define EXTI_INTENR_MR7                         ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */
+#define EXTI_INTENR_MR8                         ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */
+#define EXTI_INTENR_MR9                         ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */
+#define EXTI_INTENR_MR10                        ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */
+#define EXTI_INTENR_MR11                        ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */
+#define EXTI_INTENR_MR12                        ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */
+#define EXTI_INTENR_MR13                        ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */
+#define EXTI_INTENR_MR14                        ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */
+#define EXTI_INTENR_MR15                        ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */
+#define EXTI_INTENR_MR16                        ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */
+#define EXTI_INTENR_MR17                        ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */
+#define EXTI_INTENR_MR18                        ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */
+#define EXTI_INTENR_MR19                        ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */
+
+/*******************  Bit definition for EXTI_EVENR register  *******************/
+#define EXTI_EVENR_MR0                          ((uint32_t)0x00000001) /* Event Mask on line 0 */
+#define EXTI_EVENR_MR1                          ((uint32_t)0x00000002) /* Event Mask on line 1 */
+#define EXTI_EVENR_MR2                          ((uint32_t)0x00000004) /* Event Mask on line 2 */
+#define EXTI_EVENR_MR3                          ((uint32_t)0x00000008) /* Event Mask on line 3 */
+#define EXTI_EVENR_MR4                          ((uint32_t)0x00000010) /* Event Mask on line 4 */
+#define EXTI_EVENR_MR5                          ((uint32_t)0x00000020) /* Event Mask on line 5 */
+#define EXTI_EVENR_MR6                          ((uint32_t)0x00000040) /* Event Mask on line 6 */
+#define EXTI_EVENR_MR7                          ((uint32_t)0x00000080) /* Event Mask on line 7 */
+#define EXTI_EVENR_MR8                          ((uint32_t)0x00000100) /* Event Mask on line 8 */
+#define EXTI_EVENR_MR9                          ((uint32_t)0x00000200) /* Event Mask on line 9 */
+#define EXTI_EVENR_MR10                         ((uint32_t)0x00000400) /* Event Mask on line 10 */
+#define EXTI_EVENR_MR11                         ((uint32_t)0x00000800) /* Event Mask on line 11 */
+#define EXTI_EVENR_MR12                         ((uint32_t)0x00001000) /* Event Mask on line 12 */
+#define EXTI_EVENR_MR13                         ((uint32_t)0x00002000) /* Event Mask on line 13 */
+#define EXTI_EVENR_MR14                         ((uint32_t)0x00004000) /* Event Mask on line 14 */
+#define EXTI_EVENR_MR15                         ((uint32_t)0x00008000) /* Event Mask on line 15 */
+#define EXTI_EVENR_MR16                         ((uint32_t)0x00010000) /* Event Mask on line 16 */
+#define EXTI_EVENR_MR17                         ((uint32_t)0x00020000) /* Event Mask on line 17 */
+#define EXTI_EVENR_MR18                         ((uint32_t)0x00040000) /* Event Mask on line 18 */
+#define EXTI_EVENR_MR19                         ((uint32_t)0x00080000) /* Event Mask on line 19 */
+
+/******************  Bit definition for EXTI_RTENR register  *******************/
+#define EXTI_RTENR_TR0                          ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */
+#define EXTI_RTENR_TR1                          ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */
+#define EXTI_RTENR_TR2                          ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */
+#define EXTI_RTENR_TR3                          ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */
+#define EXTI_RTENR_TR4                          ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */
+#define EXTI_RTENR_TR5                          ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */
+#define EXTI_RTENR_TR6                          ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */
+#define EXTI_RTENR_TR7                          ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */
+#define EXTI_RTENR_TR8                          ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */
+#define EXTI_RTENR_TR9                          ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */
+#define EXTI_RTENR_TR10                         ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */
+#define EXTI_RTENR_TR11                         ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */
+#define EXTI_RTENR_TR12                         ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */
+#define EXTI_RTENR_TR13                         ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */
+#define EXTI_RTENR_TR14                         ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */
+#define EXTI_RTENR_TR15                         ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */
+#define EXTI_RTENR_TR16                         ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */
+#define EXTI_RTENR_TR17                         ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */
+#define EXTI_RTENR_TR18                         ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */
+#define EXTI_RTENR_TR19                         ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_FTENR register  *******************/
+#define EXTI_FTENR_TR0                          ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */
+#define EXTI_FTENR_TR1                          ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */
+#define EXTI_FTENR_TR2                          ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */
+#define EXTI_FTENR_TR3                          ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */
+#define EXTI_FTENR_TR4                          ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */
+#define EXTI_FTENR_TR5                          ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */
+#define EXTI_FTENR_TR6                          ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */
+#define EXTI_FTENR_TR7                          ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */
+#define EXTI_FTENR_TR8                          ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */
+#define EXTI_FTENR_TR9                          ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */
+#define EXTI_FTENR_TR10                         ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */
+#define EXTI_FTENR_TR11                         ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */
+#define EXTI_FTENR_TR12                         ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */
+#define EXTI_FTENR_TR13                         ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */
+#define EXTI_FTENR_TR14                         ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */
+#define EXTI_FTENR_TR15                         ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */
+#define EXTI_FTENR_TR16                         ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */
+#define EXTI_FTENR_TR17                         ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */
+#define EXTI_FTENR_TR18                         ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */
+#define EXTI_FTENR_TR19                         ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */
+
+/******************  Bit definition for EXTI_SWIEVR register  ******************/
+#define EXTI_SWIEVR_SWIEVR0                     ((uint32_t)0x00000001) /* Software Interrupt on line 0 */
+#define EXTI_SWIEVR_SWIEVR1                     ((uint32_t)0x00000002) /* Software Interrupt on line 1 */
+#define EXTI_SWIEVR_SWIEVR2                     ((uint32_t)0x00000004) /* Software Interrupt on line 2 */
+#define EXTI_SWIEVR_SWIEVR3                     ((uint32_t)0x00000008) /* Software Interrupt on line 3 */
+#define EXTI_SWIEVR_SWIEVR4                     ((uint32_t)0x00000010) /* Software Interrupt on line 4 */
+#define EXTI_SWIEVR_SWIEVR5                     ((uint32_t)0x00000020) /* Software Interrupt on line 5 */
+#define EXTI_SWIEVR_SWIEVR6                     ((uint32_t)0x00000040) /* Software Interrupt on line 6 */
+#define EXTI_SWIEVR_SWIEVR7                     ((uint32_t)0x00000080) /* Software Interrupt on line 7 */
+#define EXTI_SWIEVR_SWIEVR8                     ((uint32_t)0x00000100) /* Software Interrupt on line 8 */
+#define EXTI_SWIEVR_SWIEVR9                     ((uint32_t)0x00000200) /* Software Interrupt on line 9 */
+#define EXTI_SWIEVR_SWIEVR10                    ((uint32_t)0x00000400) /* Software Interrupt on line 10 */
+#define EXTI_SWIEVR_SWIEVR11                    ((uint32_t)0x00000800) /* Software Interrupt on line 11 */
+#define EXTI_SWIEVR_SWIEVR12                    ((uint32_t)0x00001000) /* Software Interrupt on line 12 */
+#define EXTI_SWIEVR_SWIEVR13                    ((uint32_t)0x00002000) /* Software Interrupt on line 13 */
+#define EXTI_SWIEVR_SWIEVR14                    ((uint32_t)0x00004000) /* Software Interrupt on line 14 */
+#define EXTI_SWIEVR_SWIEVR15                    ((uint32_t)0x00008000) /* Software Interrupt on line 15 */
+#define EXTI_SWIEVR_SWIEVR16                    ((uint32_t)0x00010000) /* Software Interrupt on line 16 */
+#define EXTI_SWIEVR_SWIEVR17                    ((uint32_t)0x00020000) /* Software Interrupt on line 17 */
+#define EXTI_SWIEVR_SWIEVR18                    ((uint32_t)0x00040000) /* Software Interrupt on line 18 */
+#define EXTI_SWIEVR_SWIEVR19                    ((uint32_t)0x00080000) /* Software Interrupt on line 19 */
+
+/*******************  Bit definition for EXTI_INTFR register  ********************/
+#define EXTI_INTF_INTF0                         ((uint32_t)0x00000001) /* Pending bit for line 0 */
+#define EXTI_INTF_INTF1                         ((uint32_t)0x00000002) /* Pending bit for line 1 */
+#define EXTI_INTF_INTF2                         ((uint32_t)0x00000004) /* Pending bit for line 2 */
+#define EXTI_INTF_INTF3                         ((uint32_t)0x00000008) /* Pending bit for line 3 */
+#define EXTI_INTF_INTF4                         ((uint32_t)0x00000010) /* Pending bit for line 4 */
+#define EXTI_INTF_INTF5                         ((uint32_t)0x00000020) /* Pending bit for line 5 */
+#define EXTI_INTF_INTF6                         ((uint32_t)0x00000040) /* Pending bit for line 6 */
+#define EXTI_INTF_INTF7                         ((uint32_t)0x00000080) /* Pending bit for line 7 */
+#define EXTI_INTF_INTF8                         ((uint32_t)0x00000100) /* Pending bit for line 8 */
+#define EXTI_INTF_INTF9                         ((uint32_t)0x00000200) /* Pending bit for line 9 */
+#define EXTI_INTF_INTF10                        ((uint32_t)0x00000400) /* Pending bit for line 10 */
+#define EXTI_INTF_INTF11                        ((uint32_t)0x00000800) /* Pending bit for line 11 */
+#define EXTI_INTF_INTF12                        ((uint32_t)0x00001000) /* Pending bit for line 12 */
+#define EXTI_INTF_INTF13                        ((uint32_t)0x00002000) /* Pending bit for line 13 */
+#define EXTI_INTF_INTF14                        ((uint32_t)0x00004000) /* Pending bit for line 14 */
+#define EXTI_INTF_INTF15                        ((uint32_t)0x00008000) /* Pending bit for line 15 */
+#define EXTI_INTF_INTF16                        ((uint32_t)0x00010000) /* Pending bit for line 16 */
+#define EXTI_INTF_INTF17                        ((uint32_t)0x00020000) /* Pending bit for line 17 */
+#define EXTI_INTF_INTF18                        ((uint32_t)0x00040000) /* Pending bit for line 18 */
+#define EXTI_INTF_INTF19                        ((uint32_t)0x00080000) /* Pending bit for line 19 */
+
+/******************************************************************************/
+/*                      FLASH and Option Bytes Registers                      */
+/******************************************************************************/
+
+/*******************  Bit definition for FLASH_ACTLR register  ******************/
+#define FLASH_ACTLR_LATENCY                     ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */
+#define FLASH_ACTLR_LATENCY_0                   ((uint8_t)0x00) /* Bit 0 */
+#define FLASH_ACTLR_LATENCY_1                   ((uint8_t)0x01) /* Bit 0 */
+#define FLASH_ACTLR_LATENCY_2                   ((uint8_t)0x02) /* Bit 1 */
+
+#define FLASH_ACTLR_HLFCYA                      ((uint8_t)0x08) /* Flash Half Cycle Access Enable */
+#define FLASH_ACTLR_PRFTBE                      ((uint8_t)0x10) /* Prefetch Buffer Enable */
+#define FLASH_ACTLR_PRFTBS                      ((uint8_t)0x20) /* Prefetch Buffer Status */
+
+/******************  Bit definition for FLASH_KEYR register  ******************/
+#define FLASH_KEYR_FKEYR                        ((uint32_t)0xFFFFFFFF) /* FPEC Key */
+
+/*****************  Bit definition for FLASH_OBKEYR register  ****************/
+#define FLASH_OBKEYR_OBKEYR                     ((uint32_t)0xFFFFFFFF) /* Option Byte Key */
+
+/******************  Bit definition for FLASH_STATR register  *******************/
+#define FLASH_STATR_BSY                         ((uint8_t)0x01) /* Busy */
+#define FLASH_STATR_PGERR                       ((uint8_t)0x04) /* Programming Error */
+#define FLASH_STATR_WRPRTERR                    ((uint8_t)0x10) /* Write Protection Error */
+#define FLASH_STATR_EOP                         ((uint8_t)0x20) /* End of operation */
+
+/*******************  Bit definition for FLASH_CTLR register  *******************/
+#define FLASH_CTLR_PG                           ((uint16_t)0x0001)     /* Programming */
+#define FLASH_CTLR_PER                          ((uint16_t)0x0002)     /* Page Erase */
+#define FLASH_CTLR_MER                          ((uint16_t)0x0004)     /* Mass Erase */
+#define FLASH_CTLR_OPTPG                        ((uint16_t)0x0010)     /* Option Byte Programming */
+#define FLASH_CTLR_OPTER                        ((uint16_t)0x0020)     /* Option Byte Erase */
+#define FLASH_CTLR_STRT                         ((uint16_t)0x0040)     /* Start */
+#define FLASH_CTLR_LOCK                         ((uint16_t)0x0080)     /* Lock */
+#define FLASH_CTLR_OPTWRE                       ((uint16_t)0x0200)     /* Option Bytes Write Enable */
+#define FLASH_CTLR_ERRIE                        ((uint16_t)0x0400)     /* Error Interrupt Enable */
+#define FLASH_CTLR_EOPIE                        ((uint16_t)0x1000)     /* End of operation interrupt enable */
+#define FLASH_CTLR_PAGE_PG                      ((uint16_t)0x00010000) /* Page Programming 128Byte */
+#define FLASH_CTLR_PAGE_ER                      ((uint16_t)0x00020000) /* Page Erase 128Byte */
+#define FLASH_CTLR_BUF_LOAD                     ((uint16_t)0x00040000) /* Buffer Load */
+#define FLASH_CTLR_BUF_RST                      ((uint16_t)0x00080000) /* Buffer Reset */
+
+/*******************  Bit definition for FLASH_ADDR register  *******************/
+#define FLASH_ADDR_FAR                          ((uint32_t)0xFFFFFFFF) /* Flash Address */
+
+/******************  Bit definition for FLASH_OBR register  *******************/
+#define FLASH_OBR_OPTERR                        ((uint16_t)0x0001) /* Option Byte Error */
+#define FLASH_OBR_RDPRT                         ((uint16_t)0x0002) /* Read protection */
+
+#define FLASH_OBR_USER                          ((uint16_t)0x03FC) /* User Option Bytes */
+#define FLASH_OBR_WDG_SW                        ((uint16_t)0x0004) /* WDG_SW */
+#define FLASH_OBR_nRST_STOP                     ((uint16_t)0x0008) /* nRST_STOP */
+#define FLASH_OBR_nRST_STDBY                    ((uint16_t)0x0010) /* nRST_STDBY */
+#define FLASH_OBR_BFB2                          ((uint16_t)0x0020) /* BFB2 */
+
+/******************  Bit definition for FLASH_WPR register  ******************/
+#define FLASH_WPR_WRP                           ((uint32_t)0xFFFFFFFF) /* Write Protect */
+
+/******************  Bit definition for FLASH_RDPR register  *******************/
+#define FLASH_RDPR_RDPR                         ((uint32_t)0x000000FF) /* Read protection option byte */
+#define FLASH_RDPR_nRDPR                        ((uint32_t)0x0000FF00) /* Read protection complemented option byte */
+
+/******************  Bit definition for FLASH_USER register  ******************/
+#define FLASH_USER_USER                         ((uint32_t)0x00FF0000) /* User option byte */
+#define FLASH_USER_nUSER                        ((uint32_t)0xFF000000) /* User complemented option byte */
+
+/******************  Bit definition for FLASH_Data0 register  *****************/
+#define FLASH_Data0_Data0                       ((uint32_t)0x000000FF) /* User data storage option byte */
+#define FLASH_Data0_nData0                      ((uint32_t)0x0000FF00) /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_Data1 register  *****************/
+#define FLASH_Data1_Data1                       ((uint32_t)0x00FF0000) /* User data storage option byte */
+#define FLASH_Data1_nData1                      ((uint32_t)0xFF000000) /* User data storage complemented option byte */
+
+/******************  Bit definition for FLASH_WRPR0 register  ******************/
+#define FLASH_WRPR0_WRPR0                       ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
+#define FLASH_WRPR0_nWRPR0                      ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR1 register  ******************/
+#define FLASH_WRPR1_WRPR1                       ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
+#define FLASH_WRPR1_nWRPR1                      ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR2 register  ******************/
+#define FLASH_WRPR2_WRPR2                       ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
+#define FLASH_WRPR2_nWRPR2                      ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
+
+/******************  Bit definition for FLASH_WRPR3 register  ******************/
+#define FLASH_WRPR3_WRPR3                       ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
+#define FLASH_WRPR3_nWRPR3                      ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
+
+/******************************************************************************/
+/*                General Purpose and Alternate Function I/O                  */
+/******************************************************************************/
+
+/*******************  Bit definition for GPIO_CFGLR register  *******************/
+#define GPIO_CFGLR_MODE                         ((uint32_t)0x33333333) /* Port x mode bits */
+
+#define GPIO_CFGLR_MODE0                        ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
+#define GPIO_CFGLR_MODE0_0                      ((uint32_t)0x00000001) /* Bit 0 */
+#define GPIO_CFGLR_MODE0_1                      ((uint32_t)0x00000002) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE1                        ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
+#define GPIO_CFGLR_MODE1_0                      ((uint32_t)0x00000010) /* Bit 0 */
+#define GPIO_CFGLR_MODE1_1                      ((uint32_t)0x00000020) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE2                        ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
+#define GPIO_CFGLR_MODE2_0                      ((uint32_t)0x00000100) /* Bit 0 */
+#define GPIO_CFGLR_MODE2_1                      ((uint32_t)0x00000200) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE3                        ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
+#define GPIO_CFGLR_MODE3_0                      ((uint32_t)0x00001000) /* Bit 0 */
+#define GPIO_CFGLR_MODE3_1                      ((uint32_t)0x00002000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE4                        ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
+#define GPIO_CFGLR_MODE4_0                      ((uint32_t)0x00010000) /* Bit 0 */
+#define GPIO_CFGLR_MODE4_1                      ((uint32_t)0x00020000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE5                        ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
+#define GPIO_CFGLR_MODE5_0                      ((uint32_t)0x00100000) /* Bit 0 */
+#define GPIO_CFGLR_MODE5_1                      ((uint32_t)0x00200000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE6                        ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
+#define GPIO_CFGLR_MODE6_0                      ((uint32_t)0x01000000) /* Bit 0 */
+#define GPIO_CFGLR_MODE6_1                      ((uint32_t)0x02000000) /* Bit 1 */
+
+#define GPIO_CFGLR_MODE7                        ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
+#define GPIO_CFGLR_MODE7_0                      ((uint32_t)0x10000000) /* Bit 0 */
+#define GPIO_CFGLR_MODE7_1                      ((uint32_t)0x20000000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF                          ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
+
+#define GPIO_CFGLR_CNF0                         ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
+#define GPIO_CFGLR_CNF0_0                       ((uint32_t)0x00000004) /* Bit 0 */
+#define GPIO_CFGLR_CNF0_1                       ((uint32_t)0x00000008) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF1                         ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
+#define GPIO_CFGLR_CNF1_0                       ((uint32_t)0x00000040) /* Bit 0 */
+#define GPIO_CFGLR_CNF1_1                       ((uint32_t)0x00000080) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF2                         ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
+#define GPIO_CFGLR_CNF2_0                       ((uint32_t)0x00000400) /* Bit 0 */
+#define GPIO_CFGLR_CNF2_1                       ((uint32_t)0x00000800) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF3                         ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
+#define GPIO_CFGLR_CNF3_0                       ((uint32_t)0x00004000) /* Bit 0 */
+#define GPIO_CFGLR_CNF3_1                       ((uint32_t)0x00008000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF4                         ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
+#define GPIO_CFGLR_CNF4_0                       ((uint32_t)0x00040000) /* Bit 0 */
+#define GPIO_CFGLR_CNF4_1                       ((uint32_t)0x00080000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF5                         ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
+#define GPIO_CFGLR_CNF5_0                       ((uint32_t)0x00400000) /* Bit 0 */
+#define GPIO_CFGLR_CNF5_1                       ((uint32_t)0x00800000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF6                         ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
+#define GPIO_CFGLR_CNF6_0                       ((uint32_t)0x04000000) /* Bit 0 */
+#define GPIO_CFGLR_CNF6_1                       ((uint32_t)0x08000000) /* Bit 1 */
+
+#define GPIO_CFGLR_CNF7                         ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
+#define GPIO_CFGLR_CNF7_0                       ((uint32_t)0x40000000) /* Bit 0 */
+#define GPIO_CFGLR_CNF7_1                       ((uint32_t)0x80000000) /* Bit 1 */
+
+/*******************  Bit definition for GPIO_CFGHR register  *******************/
+#define GPIO_CFGHR_MODE                         ((uint32_t)0x33333333) /* Port x mode bits */
+
+#define GPIO_CFGHR_MODE8                        ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
+#define GPIO_CFGHR_MODE8_0                      ((uint32_t)0x00000001) /* Bit 0 */
+#define GPIO_CFGHR_MODE8_1                      ((uint32_t)0x00000002) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE9                        ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
+#define GPIO_CFGHR_MODE9_0                      ((uint32_t)0x00000010) /* Bit 0 */
+#define GPIO_CFGHR_MODE9_1                      ((uint32_t)0x00000020) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE10                       ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
+#define GPIO_CFGHR_MODE10_0                     ((uint32_t)0x00000100) /* Bit 0 */
+#define GPIO_CFGHR_MODE10_1                     ((uint32_t)0x00000200) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE11                       ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
+#define GPIO_CFGHR_MODE11_0                     ((uint32_t)0x00001000) /* Bit 0 */
+#define GPIO_CFGHR_MODE11_1                     ((uint32_t)0x00002000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE12                       ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
+#define GPIO_CFGHR_MODE12_0                     ((uint32_t)0x00010000) /* Bit 0 */
+#define GPIO_CFGHR_MODE12_1                     ((uint32_t)0x00020000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE13                       ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
+#define GPIO_CFGHR_MODE13_0                     ((uint32_t)0x00100000) /* Bit 0 */
+#define GPIO_CFGHR_MODE13_1                     ((uint32_t)0x00200000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE14                       ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
+#define GPIO_CFGHR_MODE14_0                     ((uint32_t)0x01000000) /* Bit 0 */
+#define GPIO_CFGHR_MODE14_1                     ((uint32_t)0x02000000) /* Bit 1 */
+
+#define GPIO_CFGHR_MODE15                       ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
+#define GPIO_CFGHR_MODE15_0                     ((uint32_t)0x10000000) /* Bit 0 */
+#define GPIO_CFGHR_MODE15_1                     ((uint32_t)0x20000000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF                          ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
+
+#define GPIO_CFGHR_CNF8                         ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
+#define GPIO_CFGHR_CNF8_0                       ((uint32_t)0x00000004) /* Bit 0 */
+#define GPIO_CFGHR_CNF8_1                       ((uint32_t)0x00000008) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF9                         ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
+#define GPIO_CFGHR_CNF9_0                       ((uint32_t)0x00000040) /* Bit 0 */
+#define GPIO_CFGHR_CNF9_1                       ((uint32_t)0x00000080) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF10                        ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
+#define GPIO_CFGHR_CNF10_0                      ((uint32_t)0x00000400) /* Bit 0 */
+#define GPIO_CFGHR_CNF10_1                      ((uint32_t)0x00000800) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF11                        ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
+#define GPIO_CFGHR_CNF11_0                      ((uint32_t)0x00004000) /* Bit 0 */
+#define GPIO_CFGHR_CNF11_1                      ((uint32_t)0x00008000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF12                        ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
+#define GPIO_CFGHR_CNF12_0                      ((uint32_t)0x00040000) /* Bit 0 */
+#define GPIO_CFGHR_CNF12_1                      ((uint32_t)0x00080000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF13                        ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
+#define GPIO_CFGHR_CNF13_0                      ((uint32_t)0x00400000) /* Bit 0 */
+#define GPIO_CFGHR_CNF13_1                      ((uint32_t)0x00800000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF14                        ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
+#define GPIO_CFGHR_CNF14_0                      ((uint32_t)0x04000000) /* Bit 0 */
+#define GPIO_CFGHR_CNF14_1                      ((uint32_t)0x08000000) /* Bit 1 */
+
+#define GPIO_CFGHR_CNF15                        ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
+#define GPIO_CFGHR_CNF15_0                      ((uint32_t)0x40000000) /* Bit 0 */
+#define GPIO_CFGHR_CNF15_1                      ((uint32_t)0x80000000) /* Bit 1 */
+
+/*******************  Bit definition for GPIO_INDR register  *******************/
+#define GPIO_INDR_IDR0                          ((uint16_t)0x0001) /* Port input data, bit 0 */
+#define GPIO_INDR_IDR1                          ((uint16_t)0x0002) /* Port input data, bit 1 */
+#define GPIO_INDR_IDR2                          ((uint16_t)0x0004) /* Port input data, bit 2 */
+#define GPIO_INDR_IDR3                          ((uint16_t)0x0008) /* Port input data, bit 3 */
+#define GPIO_INDR_IDR4                          ((uint16_t)0x0010) /* Port input data, bit 4 */
+#define GPIO_INDR_IDR5                          ((uint16_t)0x0020) /* Port input data, bit 5 */
+#define GPIO_INDR_IDR6                          ((uint16_t)0x0040) /* Port input data, bit 6 */
+#define GPIO_INDR_IDR7                          ((uint16_t)0x0080) /* Port input data, bit 7 */
+#define GPIO_INDR_IDR8                          ((uint16_t)0x0100) /* Port input data, bit 8 */
+#define GPIO_INDR_IDR9                          ((uint16_t)0x0200) /* Port input data, bit 9 */
+#define GPIO_INDR_IDR10                         ((uint16_t)0x0400) /* Port input data, bit 10 */
+#define GPIO_INDR_IDR11                         ((uint16_t)0x0800) /* Port input data, bit 11 */
+#define GPIO_INDR_IDR12                         ((uint16_t)0x1000) /* Port input data, bit 12 */
+#define GPIO_INDR_IDR13                         ((uint16_t)0x2000) /* Port input data, bit 13 */
+#define GPIO_INDR_IDR14                         ((uint16_t)0x4000) /* Port input data, bit 14 */
+#define GPIO_INDR_IDR15                         ((uint16_t)0x8000) /* Port input data, bit 15 */
+
+/*******************  Bit definition for GPIO_OUTDR register  *******************/
+#define GPIO_OUTDR_ODR0                         ((uint16_t)0x0001) /* Port output data, bit 0 */
+#define GPIO_OUTDR_ODR1                         ((uint16_t)0x0002) /* Port output data, bit 1 */
+#define GPIO_OUTDR_ODR2                         ((uint16_t)0x0004) /* Port output data, bit 2 */
+#define GPIO_OUTDR_ODR3                         ((uint16_t)0x0008) /* Port output data, bit 3 */
+#define GPIO_OUTDR_ODR4                         ((uint16_t)0x0010) /* Port output data, bit 4 */
+#define GPIO_OUTDR_ODR5                         ((uint16_t)0x0020) /* Port output data, bit 5 */
+#define GPIO_OUTDR_ODR6                         ((uint16_t)0x0040) /* Port output data, bit 6 */
+#define GPIO_OUTDR_ODR7                         ((uint16_t)0x0080) /* Port output data, bit 7 */
+#define GPIO_OUTDR_ODR8                         ((uint16_t)0x0100) /* Port output data, bit 8 */
+#define GPIO_OUTDR_ODR9                         ((uint16_t)0x0200) /* Port output data, bit 9 */
+#define GPIO_OUTDR_ODR10                        ((uint16_t)0x0400) /* Port output data, bit 10 */
+#define GPIO_OUTDR_ODR11                        ((uint16_t)0x0800) /* Port output data, bit 11 */
+#define GPIO_OUTDR_ODR12                        ((uint16_t)0x1000) /* Port output data, bit 12 */
+#define GPIO_OUTDR_ODR13                        ((uint16_t)0x2000) /* Port output data, bit 13 */
+#define GPIO_OUTDR_ODR14                        ((uint16_t)0x4000) /* Port output data, bit 14 */
+#define GPIO_OUTDR_ODR15                        ((uint16_t)0x8000) /* Port output data, bit 15 */
+
+/******************  Bit definition for GPIO_BSHR register  *******************/
+#define GPIO_BSHR_BS0                           ((uint32_t)0x00000001) /* Port x Set bit 0 */
+#define GPIO_BSHR_BS1                           ((uint32_t)0x00000002) /* Port x Set bit 1 */
+#define GPIO_BSHR_BS2                           ((uint32_t)0x00000004) /* Port x Set bit 2 */
+#define GPIO_BSHR_BS3                           ((uint32_t)0x00000008) /* Port x Set bit 3 */
+#define GPIO_BSHR_BS4                           ((uint32_t)0x00000010) /* Port x Set bit 4 */
+#define GPIO_BSHR_BS5                           ((uint32_t)0x00000020) /* Port x Set bit 5 */
+#define GPIO_BSHR_BS6                           ((uint32_t)0x00000040) /* Port x Set bit 6 */
+#define GPIO_BSHR_BS7                           ((uint32_t)0x00000080) /* Port x Set bit 7 */
+#define GPIO_BSHR_BS8                           ((uint32_t)0x00000100) /* Port x Set bit 8 */
+#define GPIO_BSHR_BS9                           ((uint32_t)0x00000200) /* Port x Set bit 9 */
+#define GPIO_BSHR_BS10                          ((uint32_t)0x00000400) /* Port x Set bit 10 */
+#define GPIO_BSHR_BS11                          ((uint32_t)0x00000800) /* Port x Set bit 11 */
+#define GPIO_BSHR_BS12                          ((uint32_t)0x00001000) /* Port x Set bit 12 */
+#define GPIO_BSHR_BS13                          ((uint32_t)0x00002000) /* Port x Set bit 13 */
+#define GPIO_BSHR_BS14                          ((uint32_t)0x00004000) /* Port x Set bit 14 */
+#define GPIO_BSHR_BS15                          ((uint32_t)0x00008000) /* Port x Set bit 15 */
+
+#define GPIO_BSHR_BR0                           ((uint32_t)0x00010000) /* Port x Reset bit 0 */
+#define GPIO_BSHR_BR1                           ((uint32_t)0x00020000) /* Port x Reset bit 1 */
+#define GPIO_BSHR_BR2                           ((uint32_t)0x00040000) /* Port x Reset bit 2 */
+#define GPIO_BSHR_BR3                           ((uint32_t)0x00080000) /* Port x Reset bit 3 */
+#define GPIO_BSHR_BR4                           ((uint32_t)0x00100000) /* Port x Reset bit 4 */
+#define GPIO_BSHR_BR5                           ((uint32_t)0x00200000) /* Port x Reset bit 5 */
+#define GPIO_BSHR_BR6                           ((uint32_t)0x00400000) /* Port x Reset bit 6 */
+#define GPIO_BSHR_BR7                           ((uint32_t)0x00800000) /* Port x Reset bit 7 */
+#define GPIO_BSHR_BR8                           ((uint32_t)0x01000000) /* Port x Reset bit 8 */
+#define GPIO_BSHR_BR9                           ((uint32_t)0x02000000) /* Port x Reset bit 9 */
+#define GPIO_BSHR_BR10                          ((uint32_t)0x04000000) /* Port x Reset bit 10 */
+#define GPIO_BSHR_BR11                          ((uint32_t)0x08000000) /* Port x Reset bit 11 */
+#define GPIO_BSHR_BR12                          ((uint32_t)0x10000000) /* Port x Reset bit 12 */
+#define GPIO_BSHR_BR13                          ((uint32_t)0x20000000) /* Port x Reset bit 13 */
+#define GPIO_BSHR_BR14                          ((uint32_t)0x40000000) /* Port x Reset bit 14 */
+#define GPIO_BSHR_BR15                          ((uint32_t)0x80000000) /* Port x Reset bit 15 */
+
+/*******************  Bit definition for GPIO_BCR register  *******************/
+#define GPIO_BCR_BR0                            ((uint16_t)0x0001) /* Port x Reset bit 0 */
+#define GPIO_BCR_BR1                            ((uint16_t)0x0002) /* Port x Reset bit 1 */
+#define GPIO_BCR_BR2                            ((uint16_t)0x0004) /* Port x Reset bit 2 */
+#define GPIO_BCR_BR3                            ((uint16_t)0x0008) /* Port x Reset bit 3 */
+#define GPIO_BCR_BR4                            ((uint16_t)0x0010) /* Port x Reset bit 4 */
+#define GPIO_BCR_BR5                            ((uint16_t)0x0020) /* Port x Reset bit 5 */
+#define GPIO_BCR_BR6                            ((uint16_t)0x0040) /* Port x Reset bit 6 */
+#define GPIO_BCR_BR7                            ((uint16_t)0x0080) /* Port x Reset bit 7 */
+#define GPIO_BCR_BR8                            ((uint16_t)0x0100) /* Port x Reset bit 8 */
+#define GPIO_BCR_BR9                            ((uint16_t)0x0200) /* Port x Reset bit 9 */
+#define GPIO_BCR_BR10                           ((uint16_t)0x0400) /* Port x Reset bit 10 */
+#define GPIO_BCR_BR11                           ((uint16_t)0x0800) /* Port x Reset bit 11 */
+#define GPIO_BCR_BR12                           ((uint16_t)0x1000) /* Port x Reset bit 12 */
+#define GPIO_BCR_BR13                           ((uint16_t)0x2000) /* Port x Reset bit 13 */
+#define GPIO_BCR_BR14                           ((uint16_t)0x4000) /* Port x Reset bit 14 */
+#define GPIO_BCR_BR15                           ((uint16_t)0x8000) /* Port x Reset bit 15 */
+
+/******************  Bit definition for GPIO_LCKR register  *******************/
+#define GPIO_LCK0                               ((uint32_t)0x00000001) /* Port x Lock bit 0 */
+#define GPIO_LCK1                               ((uint32_t)0x00000002) /* Port x Lock bit 1 */
+#define GPIO_LCK2                               ((uint32_t)0x00000004) /* Port x Lock bit 2 */
+#define GPIO_LCK3                               ((uint32_t)0x00000008) /* Port x Lock bit 3 */
+#define GPIO_LCK4                               ((uint32_t)0x00000010) /* Port x Lock bit 4 */
+#define GPIO_LCK5                               ((uint32_t)0x00000020) /* Port x Lock bit 5 */
+#define GPIO_LCK6                               ((uint32_t)0x00000040) /* Port x Lock bit 6 */
+#define GPIO_LCK7                               ((uint32_t)0x00000080) /* Port x Lock bit 7 */
+#define GPIO_LCK8                               ((uint32_t)0x00000100) /* Port x Lock bit 8 */
+#define GPIO_LCK9                               ((uint32_t)0x00000200) /* Port x Lock bit 9 */
+#define GPIO_LCK10                              ((uint32_t)0x00000400) /* Port x Lock bit 10 */
+#define GPIO_LCK11                              ((uint32_t)0x00000800) /* Port x Lock bit 11 */
+#define GPIO_LCK12                              ((uint32_t)0x00001000) /* Port x Lock bit 12 */
+#define GPIO_LCK13                              ((uint32_t)0x00002000) /* Port x Lock bit 13 */
+#define GPIO_LCK14                              ((uint32_t)0x00004000) /* Port x Lock bit 14 */
+#define GPIO_LCK15                              ((uint32_t)0x00008000) /* Port x Lock bit 15 */
+#define GPIO_LCKK                               ((uint32_t)0x00010000) /* Lock key */
+
+/******************  Bit definition for AFIO_ECR register  *******************/
+#define AFIO_ECR_PIN                            ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */
+#define AFIO_ECR_PIN_0                          ((uint8_t)0x01) /* Bit 0 */
+#define AFIO_ECR_PIN_1                          ((uint8_t)0x02) /* Bit 1 */
+#define AFIO_ECR_PIN_2                          ((uint8_t)0x04) /* Bit 2 */
+#define AFIO_ECR_PIN_3                          ((uint8_t)0x08) /* Bit 3 */
+
+#define AFIO_ECR_PIN_PX0                        ((uint8_t)0x00) /* Pin 0 selected */
+#define AFIO_ECR_PIN_PX1                        ((uint8_t)0x01) /* Pin 1 selected */
+#define AFIO_ECR_PIN_PX2                        ((uint8_t)0x02) /* Pin 2 selected */
+#define AFIO_ECR_PIN_PX3                        ((uint8_t)0x03) /* Pin 3 selected */
+#define AFIO_ECR_PIN_PX4                        ((uint8_t)0x04) /* Pin 4 selected */
+#define AFIO_ECR_PIN_PX5                        ((uint8_t)0x05) /* Pin 5 selected */
+#define AFIO_ECR_PIN_PX6                        ((uint8_t)0x06) /* Pin 6 selected */
+#define AFIO_ECR_PIN_PX7                        ((uint8_t)0x07) /* Pin 7 selected */
+#define AFIO_ECR_PIN_PX8                        ((uint8_t)0x08) /* Pin 8 selected */
+#define AFIO_ECR_PIN_PX9                        ((uint8_t)0x09) /* Pin 9 selected */
+#define AFIO_ECR_PIN_PX10                       ((uint8_t)0x0A) /* Pin 10 selected */
+#define AFIO_ECR_PIN_PX11                       ((uint8_t)0x0B) /* Pin 11 selected */
+#define AFIO_ECR_PIN_PX12                       ((uint8_t)0x0C) /* Pin 12 selected */
+#define AFIO_ECR_PIN_PX13                       ((uint8_t)0x0D) /* Pin 13 selected */
+#define AFIO_ECR_PIN_PX14                       ((uint8_t)0x0E) /* Pin 14 selected */
+#define AFIO_ECR_PIN_PX15                       ((uint8_t)0x0F) /* Pin 15 selected */
+
+#define AFIO_ECR_PORT                           ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */
+#define AFIO_ECR_PORT_0                         ((uint8_t)0x10) /* Bit 0 */
+#define AFIO_ECR_PORT_1                         ((uint8_t)0x20) /* Bit 1 */
+#define AFIO_ECR_PORT_2                         ((uint8_t)0x40) /* Bit 2 */
+
+#define AFIO_ECR_PORT_PA                        ((uint8_t)0x00) /* Port A selected */
+#define AFIO_ECR_PORT_PB                        ((uint8_t)0x10) /* Port B selected */
+#define AFIO_ECR_PORT_PC                        ((uint8_t)0x20) /* Port C selected */
+#define AFIO_ECR_PORT_PD                        ((uint8_t)0x30) /* Port D selected */
+#define AFIO_ECR_PORT_PE                        ((uint8_t)0x40) /* Port E selected */
+
+#define AFIO_ECR_EVOE                           ((uint8_t)0x80) /* Event Output Enable */
+
+/******************  Bit definition for AFIO_PCFR1register  *******************/
+#define AFIO_PCFR1_SPI1_REMAP                   ((uint32_t)0x00000001) /* SPI1 remapping */
+#define AFIO_PCFR1_I2C1_REMAP                   ((uint32_t)0x00000002) /* I2C1 remapping */
+#define AFIO_PCFR1_USART1_REMAP                 ((uint32_t)0x00000004) /* USART1 remapping */
+#define AFIO_PCFR1_USART2_REMAP                 ((uint32_t)0x00000008) /* USART2 remapping */
+
+#define AFIO_PCFR1_USART3_REMAP                 ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
+#define AFIO_PCFR1_USART3_REMAP_0               ((uint32_t)0x00000010) /* Bit 0 */
+#define AFIO_PCFR1_USART3_REMAP_1               ((uint32_t)0x00000020) /* Bit 1 */
+
+#define AFIO_PCFR1_USART3_REMAP_NOREMAP         ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP    ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+#define AFIO_PCFR1_USART3_REMAP_FULLREMAP       ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+
+#define AFIO_PCFR1_TIM1_REMAP                   ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
+#define AFIO_PCFR1_TIM1_REMAP_0                 ((uint32_t)0x00000040) /* Bit 0 */
+#define AFIO_PCFR1_TIM1_REMAP_1                 ((uint32_t)0x00000080) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM1_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP      ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP         ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+
+#define AFIO_PCFR1_TIM2_REMAP                   ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
+#define AFIO_PCFR1_TIM2_REMAP_0                 ((uint32_t)0x00000100) /* Bit 0 */
+#define AFIO_PCFR1_TIM2_REMAP_1                 ((uint32_t)0x00000200) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM2_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1     ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2     ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP         ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+
+#define AFIO_PCFR1_TIM3_REMAP                   ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
+#define AFIO_PCFR1_TIM3_REMAP_0                 ((uint32_t)0x00000400) /* Bit 0 */
+#define AFIO_PCFR1_TIM3_REMAP_1                 ((uint32_t)0x00000800) /* Bit 1 */
+
+#define AFIO_PCFR1_TIM3_REMAP_NOREMAP           ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP      ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP         ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+
+#define AFIO_PCFR1_TIM4_REMAP                   ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */
+
+#define AFIO_PCFR1_CAN_REMAP                    ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
+#define AFIO_PCFR1_CAN_REMAP_0                  ((uint32_t)0x00002000) /* Bit 0 */
+#define AFIO_PCFR1_CAN_REMAP_1                  ((uint32_t)0x00004000) /* Bit 1 */
+
+#define AFIO_PCFR1_CAN_REMAP_REMAP1             ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP2             ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
+#define AFIO_PCFR1_CAN_REMAP_REMAP3             ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
+
+#define AFIO_PCFR1_PD01_REMAP                   ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_PCFR1_TIM5CH4_IREMAP               ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */
+#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP           ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC1_ETRGREG_REMAP           ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP           ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
+#define AFIO_PCFR1_ADC2_ETRGREG_REMAP           ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
+
+#define AFIO_PCFR1_SWJ_CFG                      ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
+#define AFIO_PCFR1_SWJ_CFG_0                    ((uint32_t)0x01000000) /* Bit 0 */
+#define AFIO_PCFR1_SWJ_CFG_1                    ((uint32_t)0x02000000) /* Bit 1 */
+#define AFIO_PCFR1_SWJ_CFG_2                    ((uint32_t)0x04000000) /* Bit 2 */
+
+#define AFIO_PCFR1_SWJ_CFG_RESET                ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
+#define AFIO_PCFR1_SWJ_CFG_NOJNTRST             ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE          ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
+#define AFIO_PCFR1_SWJ_CFG_DISABLE              ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
+
+/*****************  Bit definition for AFIO_EXTICR1 register  *****************/
+#define AFIO_EXTICR1_EXTI0                      ((uint16_t)0x000F) /* EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI1                      ((uint16_t)0x00F0) /* EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI2                      ((uint16_t)0x0F00) /* EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI3                      ((uint16_t)0xF000) /* EXTI 3 configuration */
+
+#define AFIO_EXTICR1_EXTI0_PA                   ((uint16_t)0x0000) /* PA[0] pin */
+#define AFIO_EXTICR1_EXTI0_PB                   ((uint16_t)0x0001) /* PB[0] pin */
+#define AFIO_EXTICR1_EXTI0_PC                   ((uint16_t)0x0002) /* PC[0] pin */
+#define AFIO_EXTICR1_EXTI0_PD                   ((uint16_t)0x0003) /* PD[0] pin */
+#define AFIO_EXTICR1_EXTI0_PE                   ((uint16_t)0x0004) /* PE[0] pin */
+#define AFIO_EXTICR1_EXTI0_PF                   ((uint16_t)0x0005) /* PF[0] pin */
+#define AFIO_EXTICR1_EXTI0_PG                   ((uint16_t)0x0006) /* PG[0] pin */
+
+#define AFIO_EXTICR1_EXTI1_PA                   ((uint16_t)0x0000) /* PA[1] pin */
+#define AFIO_EXTICR1_EXTI1_PB                   ((uint16_t)0x0010) /* PB[1] pin */
+#define AFIO_EXTICR1_EXTI1_PC                   ((uint16_t)0x0020) /* PC[1] pin */
+#define AFIO_EXTICR1_EXTI1_PD                   ((uint16_t)0x0030) /* PD[1] pin */
+#define AFIO_EXTICR1_EXTI1_PE                   ((uint16_t)0x0040) /* PE[1] pin */
+#define AFIO_EXTICR1_EXTI1_PF                   ((uint16_t)0x0050) /* PF[1] pin */
+#define AFIO_EXTICR1_EXTI1_PG                   ((uint16_t)0x0060) /* PG[1] pin */
+
+#define AFIO_EXTICR1_EXTI2_PA                   ((uint16_t)0x0000) /* PA[2] pin */
+#define AFIO_EXTICR1_EXTI2_PB                   ((uint16_t)0x0100) /* PB[2] pin */
+#define AFIO_EXTICR1_EXTI2_PC                   ((uint16_t)0x0200) /* PC[2] pin */
+#define AFIO_EXTICR1_EXTI2_PD                   ((uint16_t)0x0300) /* PD[2] pin */
+#define AFIO_EXTICR1_EXTI2_PE                   ((uint16_t)0x0400) /* PE[2] pin */
+#define AFIO_EXTICR1_EXTI2_PF                   ((uint16_t)0x0500) /* PF[2] pin */
+#define AFIO_EXTICR1_EXTI2_PG                   ((uint16_t)0x0600) /* PG[2] pin */
+
+#define AFIO_EXTICR1_EXTI3_PA                   ((uint16_t)0x0000) /* PA[3] pin */
+#define AFIO_EXTICR1_EXTI3_PB                   ((uint16_t)0x1000) /* PB[3] pin */
+#define AFIO_EXTICR1_EXTI3_PC                   ((uint16_t)0x2000) /* PC[3] pin */
+#define AFIO_EXTICR1_EXTI3_PD                   ((uint16_t)0x3000) /* PD[3] pin */
+#define AFIO_EXTICR1_EXTI3_PE                   ((uint16_t)0x4000) /* PE[3] pin */
+#define AFIO_EXTICR1_EXTI3_PF                   ((uint16_t)0x5000) /* PF[3] pin */
+#define AFIO_EXTICR1_EXTI3_PG                   ((uint16_t)0x6000) /* PG[3] pin */
+
+/*****************  Bit definition for AFIO_EXTICR2 register  *****************/
+#define AFIO_EXTICR2_EXTI4                      ((uint16_t)0x000F) /* EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI5                      ((uint16_t)0x00F0) /* EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI6                      ((uint16_t)0x0F00) /* EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI7                      ((uint16_t)0xF000) /* EXTI 7 configuration */
+
+#define AFIO_EXTICR2_EXTI4_PA                   ((uint16_t)0x0000) /* PA[4] pin */
+#define AFIO_EXTICR2_EXTI4_PB                   ((uint16_t)0x0001) /* PB[4] pin */
+#define AFIO_EXTICR2_EXTI4_PC                   ((uint16_t)0x0002) /* PC[4] pin */
+#define AFIO_EXTICR2_EXTI4_PD                   ((uint16_t)0x0003) /* PD[4] pin */
+#define AFIO_EXTICR2_EXTI4_PE                   ((uint16_t)0x0004) /* PE[4] pin */
+#define AFIO_EXTICR2_EXTI4_PF                   ((uint16_t)0x0005) /* PF[4] pin */
+#define AFIO_EXTICR2_EXTI4_PG                   ((uint16_t)0x0006) /* PG[4] pin */
+
+#define AFIO_EXTICR2_EXTI5_PA                   ((uint16_t)0x0000) /* PA[5] pin */
+#define AFIO_EXTICR2_EXTI5_PB                   ((uint16_t)0x0010) /* PB[5] pin */
+#define AFIO_EXTICR2_EXTI5_PC                   ((uint16_t)0x0020) /* PC[5] pin */
+#define AFIO_EXTICR2_EXTI5_PD                   ((uint16_t)0x0030) /* PD[5] pin */
+#define AFIO_EXTICR2_EXTI5_PE                   ((uint16_t)0x0040) /* PE[5] pin */
+#define AFIO_EXTICR2_EXTI5_PF                   ((uint16_t)0x0050) /* PF[5] pin */
+#define AFIO_EXTICR2_EXTI5_PG                   ((uint16_t)0x0060) /* PG[5] pin */
+
+#define AFIO_EXTICR2_EXTI6_PA                   ((uint16_t)0x0000) /* PA[6] pin */
+#define AFIO_EXTICR2_EXTI6_PB                   ((uint16_t)0x0100) /* PB[6] pin */
+#define AFIO_EXTICR2_EXTI6_PC                   ((uint16_t)0x0200) /* PC[6] pin */
+#define AFIO_EXTICR2_EXTI6_PD                   ((uint16_t)0x0300) /* PD[6] pin */
+#define AFIO_EXTICR2_EXTI6_PE                   ((uint16_t)0x0400) /* PE[6] pin */
+#define AFIO_EXTICR2_EXTI6_PF                   ((uint16_t)0x0500) /* PF[6] pin */
+#define AFIO_EXTICR2_EXTI6_PG                   ((uint16_t)0x0600) /* PG[6] pin */
+
+#define AFIO_EXTICR2_EXTI7_PA                   ((uint16_t)0x0000) /* PA[7] pin */
+#define AFIO_EXTICR2_EXTI7_PB                   ((uint16_t)0x1000) /* PB[7] pin */
+#define AFIO_EXTICR2_EXTI7_PC                   ((uint16_t)0x2000) /* PC[7] pin */
+#define AFIO_EXTICR2_EXTI7_PD                   ((uint16_t)0x3000) /* PD[7] pin */
+#define AFIO_EXTICR2_EXTI7_PE                   ((uint16_t)0x4000) /* PE[7] pin */
+#define AFIO_EXTICR2_EXTI7_PF                   ((uint16_t)0x5000) /* PF[7] pin */
+#define AFIO_EXTICR2_EXTI7_PG                   ((uint16_t)0x6000) /* PG[7] pin */
+
+/*****************  Bit definition for AFIO_EXTICR3 register  *****************/
+#define AFIO_EXTICR3_EXTI8                      ((uint16_t)0x000F) /* EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI9                      ((uint16_t)0x00F0) /* EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI10                     ((uint16_t)0x0F00) /* EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI11                     ((uint16_t)0xF000) /* EXTI 11 configuration */
+
+#define AFIO_EXTICR3_EXTI8_PA                   ((uint16_t)0x0000) /* PA[8] pin */
+#define AFIO_EXTICR3_EXTI8_PB                   ((uint16_t)0x0001) /* PB[8] pin */
+#define AFIO_EXTICR3_EXTI8_PC                   ((uint16_t)0x0002) /* PC[8] pin */
+#define AFIO_EXTICR3_EXTI8_PD                   ((uint16_t)0x0003) /* PD[8] pin */
+#define AFIO_EXTICR3_EXTI8_PE                   ((uint16_t)0x0004) /* PE[8] pin */
+#define AFIO_EXTICR3_EXTI8_PF                   ((uint16_t)0x0005) /* PF[8] pin */
+#define AFIO_EXTICR3_EXTI8_PG                   ((uint16_t)0x0006) /* PG[8] pin */
+
+#define AFIO_EXTICR3_EXTI9_PA                   ((uint16_t)0x0000) /* PA[9] pin */
+#define AFIO_EXTICR3_EXTI9_PB                   ((uint16_t)0x0010) /* PB[9] pin */
+#define AFIO_EXTICR3_EXTI9_PC                   ((uint16_t)0x0020) /* PC[9] pin */
+#define AFIO_EXTICR3_EXTI9_PD                   ((uint16_t)0x0030) /* PD[9] pin */
+#define AFIO_EXTICR3_EXTI9_PE                   ((uint16_t)0x0040) /* PE[9] pin */
+#define AFIO_EXTICR3_EXTI9_PF                   ((uint16_t)0x0050) /* PF[9] pin */
+#define AFIO_EXTICR3_EXTI9_PG                   ((uint16_t)0x0060) /* PG[9] pin */
+
+#define AFIO_EXTICR3_EXTI10_PA                  ((uint16_t)0x0000) /* PA[10] pin */
+#define AFIO_EXTICR3_EXTI10_PB                  ((uint16_t)0x0100) /* PB[10] pin */
+#define AFIO_EXTICR3_EXTI10_PC                  ((uint16_t)0x0200) /* PC[10] pin */
+#define AFIO_EXTICR3_EXTI10_PD                  ((uint16_t)0x0300) /* PD[10] pin */
+#define AFIO_EXTICR3_EXTI10_PE                  ((uint16_t)0x0400) /* PE[10] pin */
+#define AFIO_EXTICR3_EXTI10_PF                  ((uint16_t)0x0500) /* PF[10] pin */
+#define AFIO_EXTICR3_EXTI10_PG                  ((uint16_t)0x0600) /* PG[10] pin */
+
+#define AFIO_EXTICR3_EXTI11_PA                  ((uint16_t)0x0000) /* PA[11] pin */
+#define AFIO_EXTICR3_EXTI11_PB                  ((uint16_t)0x1000) /* PB[11] pin */
+#define AFIO_EXTICR3_EXTI11_PC                  ((uint16_t)0x2000) /* PC[11] pin */
+#define AFIO_EXTICR3_EXTI11_PD                  ((uint16_t)0x3000) /* PD[11] pin */
+#define AFIO_EXTICR3_EXTI11_PE                  ((uint16_t)0x4000) /* PE[11] pin */
+#define AFIO_EXTICR3_EXTI11_PF                  ((uint16_t)0x5000) /* PF[11] pin */
+#define AFIO_EXTICR3_EXTI11_PG                  ((uint16_t)0x6000) /* PG[11] pin */
+
+/*****************  Bit definition for AFIO_EXTICR4 register  *****************/
+#define AFIO_EXTICR4_EXTI12                     ((uint16_t)0x000F) /* EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI13                     ((uint16_t)0x00F0) /* EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI14                     ((uint16_t)0x0F00) /* EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI15                     ((uint16_t)0xF000) /* EXTI 15 configuration */
+
+#define AFIO_EXTICR4_EXTI12_PA                  ((uint16_t)0x0000) /* PA[12] pin */
+#define AFIO_EXTICR4_EXTI12_PB                  ((uint16_t)0x0001) /* PB[12] pin */
+#define AFIO_EXTICR4_EXTI12_PC                  ((uint16_t)0x0002) /* PC[12] pin */
+#define AFIO_EXTICR4_EXTI12_PD                  ((uint16_t)0x0003) /* PD[12] pin */
+#define AFIO_EXTICR4_EXTI12_PE                  ((uint16_t)0x0004) /* PE[12] pin */
+#define AFIO_EXTICR4_EXTI12_PF                  ((uint16_t)0x0005) /* PF[12] pin */
+#define AFIO_EXTICR4_EXTI12_PG                  ((uint16_t)0x0006) /* PG[12] pin */
+
+#define AFIO_EXTICR4_EXTI13_PA                  ((uint16_t)0x0000) /* PA[13] pin */
+#define AFIO_EXTICR4_EXTI13_PB                  ((uint16_t)0x0010) /* PB[13] pin */
+#define AFIO_EXTICR4_EXTI13_PC                  ((uint16_t)0x0020) /* PC[13] pin */
+#define AFIO_EXTICR4_EXTI13_PD                  ((uint16_t)0x0030) /* PD[13] pin */
+#define AFIO_EXTICR4_EXTI13_PE                  ((uint16_t)0x0040) /* PE[13] pin */
+#define AFIO_EXTICR4_EXTI13_PF                  ((uint16_t)0x0050) /* PF[13] pin */
+#define AFIO_EXTICR4_EXTI13_PG                  ((uint16_t)0x0060) /* PG[13] pin */
+
+#define AFIO_EXTICR4_EXTI14_PA                  ((uint16_t)0x0000) /* PA[14] pin */
+#define AFIO_EXTICR4_EXTI14_PB                  ((uint16_t)0x0100) /* PB[14] pin */
+#define AFIO_EXTICR4_EXTI14_PC                  ((uint16_t)0x0200) /* PC[14] pin */
+#define AFIO_EXTICR4_EXTI14_PD                  ((uint16_t)0x0300) /* PD[14] pin */
+#define AFIO_EXTICR4_EXTI14_PE                  ((uint16_t)0x0400) /* PE[14] pin */
+#define AFIO_EXTICR4_EXTI14_PF                  ((uint16_t)0x0500) /* PF[14] pin */
+#define AFIO_EXTICR4_EXTI14_PG                  ((uint16_t)0x0600) /* PG[14] pin */
+
+#define AFIO_EXTICR4_EXTI15_PA                  ((uint16_t)0x0000) /* PA[15] pin */
+#define AFIO_EXTICR4_EXTI15_PB                  ((uint16_t)0x1000) /* PB[15] pin */
+#define AFIO_EXTICR4_EXTI15_PC                  ((uint16_t)0x2000) /* PC[15] pin */
+#define AFIO_EXTICR4_EXTI15_PD                  ((uint16_t)0x3000) /* PD[15] pin */
+#define AFIO_EXTICR4_EXTI15_PE                  ((uint16_t)0x4000) /* PE[15] pin */
+#define AFIO_EXTICR4_EXTI15_PF                  ((uint16_t)0x5000) /* PF[15] pin */
+#define AFIO_EXTICR4_EXTI15_PG                  ((uint16_t)0x6000) /* PG[15] pin */
+
+/******************************************************************************/
+/*                           Independent WATCHDOG                             */
+/******************************************************************************/
+
+/*******************  Bit definition for IWDG_CTLR register  ********************/
+#define IWDG_KEY                                ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */
+
+/*******************  Bit definition for IWDG_PSCR register  ********************/
+#define IWDG_PR                                 ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */
+#define IWDG_PR_0                               ((uint8_t)0x01) /* Bit 0 */
+#define IWDG_PR_1                               ((uint8_t)0x02) /* Bit 1 */
+#define IWDG_PR_2                               ((uint8_t)0x04) /* Bit 2 */
+
+/*******************  Bit definition for IWDG_RLDR register  *******************/
+#define IWDG_RL                                 ((uint16_t)0x0FFF) /* Watchdog counter reload value */
+
+/*******************  Bit definition for IWDG_STATR register  ********************/
+#define IWDG_PVU                                ((uint8_t)0x01) /* Watchdog prescaler value update */
+#define IWDG_RVU                                ((uint8_t)0x02) /* Watchdog counter reload value update */
+
+/******************************************************************************/
+/*                      Inter-integrated Circuit Interface                    */
+/******************************************************************************/
+
+/*******************  Bit definition for I2C_CTLR1 register  ********************/
+#define I2C_CTLR1_PE                            ((uint16_t)0x0001) /* Peripheral Enable */
+#define I2C_CTLR1_SMBUS                         ((uint16_t)0x0002) /* SMBus Mode */
+#define I2C_CTLR1_SMBTYPE                       ((uint16_t)0x0008) /* SMBus Type */
+#define I2C_CTLR1_ENARP                         ((uint16_t)0x0010) /* ARP Enable */
+#define I2C_CTLR1_ENPEC                         ((uint16_t)0x0020) /* PEC Enable */
+#define I2C_CTLR1_ENGC                          ((uint16_t)0x0040) /* General Call Enable */
+#define I2C_CTLR1_NOSTRETCH                     ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */
+#define I2C_CTLR1_START                         ((uint16_t)0x0100) /* Start Generation */
+#define I2C_CTLR1_STOP                          ((uint16_t)0x0200) /* Stop Generation */
+#define I2C_CTLR1_ACK                           ((uint16_t)0x0400) /* Acknowledge Enable */
+#define I2C_CTLR1_POS                           ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
+#define I2C_CTLR1_PEC                           ((uint16_t)0x1000) /* Packet Error Checking */
+#define I2C_CTLR1_ALERT                         ((uint16_t)0x2000) /* SMBus Alert */
+#define I2C_CTLR1_SWRST                         ((uint16_t)0x8000) /* Software Reset */
+
+/*******************  Bit definition for I2C_CTLR2 register  ********************/
+#define I2C_CTLR2_FREQ                          ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
+#define I2C_CTLR2_FREQ_0                        ((uint16_t)0x0001) /* Bit 0 */
+#define I2C_CTLR2_FREQ_1                        ((uint16_t)0x0002) /* Bit 1 */
+#define I2C_CTLR2_FREQ_2                        ((uint16_t)0x0004) /* Bit 2 */
+#define I2C_CTLR2_FREQ_3                        ((uint16_t)0x0008) /* Bit 3 */
+#define I2C_CTLR2_FREQ_4                        ((uint16_t)0x0010) /* Bit 4 */
+#define I2C_CTLR2_FREQ_5                        ((uint16_t)0x0020) /* Bit 5 */
+
+#define I2C_CTLR2_ITERREN                       ((uint16_t)0x0100) /* Error Interrupt Enable */
+#define I2C_CTLR2_ITEVTEN                       ((uint16_t)0x0200) /* Event Interrupt Enable */
+#define I2C_CTLR2_ITBUFEN                       ((uint16_t)0x0400) /* Buffer Interrupt Enable */
+#define I2C_CTLR2_DMAEN                         ((uint16_t)0x0800) /* DMA Requests Enable */
+#define I2C_CTLR2_LAST                          ((uint16_t)0x1000) /* DMA Last Transfer */
+
+/*******************  Bit definition for I2C_OADDR1 register  *******************/
+#define I2C_OADDR1_ADD1_7                       ((uint16_t)0x00FE) /* Interface Address */
+#define I2C_OADDR1_ADD8_9                       ((uint16_t)0x0300) /* Interface Address */
+
+#define I2C_OADDR1_ADD0                         ((uint16_t)0x0001) /* Bit 0 */
+#define I2C_OADDR1_ADD1                         ((uint16_t)0x0002) /* Bit 1 */
+#define I2C_OADDR1_ADD2                         ((uint16_t)0x0004) /* Bit 2 */
+#define I2C_OADDR1_ADD3                         ((uint16_t)0x0008) /* Bit 3 */
+#define I2C_OADDR1_ADD4                         ((uint16_t)0x0010) /* Bit 4 */
+#define I2C_OADDR1_ADD5                         ((uint16_t)0x0020) /* Bit 5 */
+#define I2C_OADDR1_ADD6                         ((uint16_t)0x0040) /* Bit 6 */
+#define I2C_OADDR1_ADD7                         ((uint16_t)0x0080) /* Bit 7 */
+#define I2C_OADDR1_ADD8                         ((uint16_t)0x0100) /* Bit 8 */
+#define I2C_OADDR1_ADD9                         ((uint16_t)0x0200) /* Bit 9 */
+
+#define I2C_OADDR1_ADDMODE                      ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */
+
+/*******************  Bit definition for I2C_OADDR2 register  *******************/
+#define I2C_OADDR2_ENDUAL                       ((uint8_t)0x01) /* Dual addressing mode enable */
+#define I2C_OADDR2_ADD2                         ((uint8_t)0xFE) /* Interface address */
+
+/********************  Bit definition for I2C_DATAR register  ********************/
+#define I2C_DR_DATAR                            ((uint8_t)0xFF) /* 8-bit Data Register */
+
+/*******************  Bit definition for I2C_STAR1 register  ********************/
+#define I2C_STAR1_SB                            ((uint16_t)0x0001) /* Start Bit (Master mode) */
+#define I2C_STAR1_ADDR                          ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */
+#define I2C_STAR1_BTF                           ((uint16_t)0x0004) /* Byte Transfer Finished */
+#define I2C_STAR1_ADD10                         ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */
+#define I2C_STAR1_STOPF                         ((uint16_t)0x0010) /* Stop detection (Slave mode) */
+#define I2C_STAR1_RXNE                          ((uint16_t)0x0040) /* Data Register not Empty (receivers) */
+#define I2C_STAR1_TXE                           ((uint16_t)0x0080) /* Data Register Empty (transmitters) */
+#define I2C_STAR1_BERR                          ((uint16_t)0x0100) /* Bus Error */
+#define I2C_STAR1_ARLO                          ((uint16_t)0x0200) /* Arbitration Lost (master mode) */
+#define I2C_STAR1_AF                            ((uint16_t)0x0400) /* Acknowledge Failure */
+#define I2C_STAR1_OVR                           ((uint16_t)0x0800) /* Overrun/Underrun */
+#define I2C_STAR1_PECERR                        ((uint16_t)0x1000) /* PEC Error in reception */
+#define I2C_STAR1_TIMEOUT                       ((uint16_t)0x4000) /* Timeout or Tlow Error */
+#define I2C_STAR1_SMBALERT                      ((uint16_t)0x8000) /* SMBus Alert */
+
+/*******************  Bit definition for I2C_STAR2 register  ********************/
+#define I2C_STAR2_MSL                           ((uint16_t)0x0001) /* Master/Slave */
+#define I2C_STAR2_BUSY                          ((uint16_t)0x0002) /* Bus Busy */
+#define I2C_STAR2_TRA                           ((uint16_t)0x0004) /* Transmitter/Receiver */
+#define I2C_STAR2_GENCALL                       ((uint16_t)0x0010) /* General Call Address (Slave mode) */
+#define I2C_STAR2_SMBDEFAULT                    ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */
+#define I2C_STAR2_SMBHOST                       ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */
+#define I2C_STAR2_DUALF                         ((uint16_t)0x0080) /* Dual Flag (Slave mode) */
+#define I2C_STAR2_PEC                           ((uint16_t)0xFF00) /* Packet Error Checking Register */
+
+/*******************  Bit definition for I2C_CKCFGR register  ********************/
+#define I2C_CKCFGR_CCR                          ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
+#define I2C_CKCFGR_DUTY                         ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
+#define I2C_CKCFGR_FS                           ((uint16_t)0x8000) /* I2C Master Mode Selection */
+
+/******************  Bit definition for I2C_RTR register  *******************/
+#define I2C_RTR_TRISE                           ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/******************************************************************************/
+/*                             Power Control                                  */
+/******************************************************************************/
+
+/********************  Bit definition for PWR_CTLR register  ********************/
+#define PWR_CTLR_LPDS                           ((uint16_t)0x0001) /* Low-Power Deepsleep */
+#define PWR_CTLR_PDDS                           ((uint16_t)0x0002) /* Power Down Deepsleep */
+#define PWR_CTLR_CWUF                           ((uint16_t)0x0004) /* Clear Wakeup Flag */
+#define PWR_CTLR_CSBF                           ((uint16_t)0x0008) /* Clear Standby Flag */
+#define PWR_CTLR_PVDE                           ((uint16_t)0x0010) /* Power Voltage Detector Enable */
+
+#define PWR_CTLR_PLS                            ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
+#define PWR_CTLR_PLS_0                          ((uint16_t)0x0020) /* Bit 0 */
+#define PWR_CTLR_PLS_1                          ((uint16_t)0x0040) /* Bit 1 */
+#define PWR_CTLR_PLS_2                          ((uint16_t)0x0080) /* Bit 2 */
+
+#define PWR_CTLR_PLS_2V2                        ((uint16_t)0x0000) /* PVD level 2.2V */
+#define PWR_CTLR_PLS_2V3                        ((uint16_t)0x0020) /* PVD level 2.3V */
+#define PWR_CTLR_PLS_2V4                        ((uint16_t)0x0040) /* PVD level 2.4V */
+#define PWR_CTLR_PLS_2V5                        ((uint16_t)0x0060) /* PVD level 2.5V */
+#define PWR_CTLR_PLS_2V6                        ((uint16_t)0x0080) /* PVD level 2.6V */
+#define PWR_CTLR_PLS_2V7                        ((uint16_t)0x00A0) /* PVD level 2.7V */
+#define PWR_CTLR_PLS_2V8                        ((uint16_t)0x00C0) /* PVD level 2.8V */
+#define PWR_CTLR_PLS_2V9                        ((uint16_t)0x00E0) /* PVD level 2.9V */
+
+#define PWR_CTLR_DBP                            ((uint16_t)0x0100) /* Disable Backup Domain write protection */
+
+/*******************  Bit definition for PWR_CSR register  ********************/
+#define PWR_CSR_WUF                             ((uint16_t)0x0001) /* Wakeup Flag */
+#define PWR_CSR_SBF                             ((uint16_t)0x0002) /* Standby Flag */
+#define PWR_CSR_PVDO                            ((uint16_t)0x0004) /* PVD Output */
+#define PWR_CSR_EWUP                            ((uint16_t)0x0100) /* Enable WKUP pin */
+
+/******************************************************************************/
+/*                         Reset and Clock Control                            */
+/******************************************************************************/
+
+/********************  Bit definition for RCC_CTLR register  ********************/
+#define RCC_HSION                               ((uint32_t)0x00000001) /* Internal High Speed clock enable */
+#define RCC_HSIRDY                              ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */
+#define RCC_HSITRIM                             ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */
+#define RCC_HSICAL                              ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */
+#define RCC_HSEON                               ((uint32_t)0x00010000) /* External High Speed clock enable */
+#define RCC_HSERDY                              ((uint32_t)0x00020000) /* External High Speed clock ready flag */
+#define RCC_HSEBYP                              ((uint32_t)0x00040000) /* External High Speed clock Bypass */
+#define RCC_CSSON                               ((uint32_t)0x00080000) /* Clock Security System enable */
+#define RCC_PLLON                               ((uint32_t)0x01000000) /* PLL enable */
+#define RCC_PLLRDY                              ((uint32_t)0x02000000) /* PLL clock ready flag */
+
+/*******************  Bit definition for RCC_CFGR0 register  *******************/
+#define RCC_SW                                  ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
+#define RCC_SW_0                                ((uint32_t)0x00000001) /* Bit 0 */
+#define RCC_SW_1                                ((uint32_t)0x00000002) /* Bit 1 */
+
+#define RCC_SW_HSI                              ((uint32_t)0x00000000) /* HSI selected as system clock */
+#define RCC_SW_HSE                              ((uint32_t)0x00000001) /* HSE selected as system clock */
+#define RCC_SW_PLL                              ((uint32_t)0x00000002) /* PLL selected as system clock */
+
+#define RCC_SWS                                 ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
+#define RCC_SWS_0                               ((uint32_t)0x00000004) /* Bit 0 */
+#define RCC_SWS_1                               ((uint32_t)0x00000008) /* Bit 1 */
+
+#define RCC_SWS_HSI                             ((uint32_t)0x00000000) /* HSI oscillator used as system clock */
+#define RCC_SWS_HSE                             ((uint32_t)0x00000004) /* HSE oscillator used as system clock */
+#define RCC_SWS_PLL                             ((uint32_t)0x00000008) /* PLL used as system clock */
+
+#define RCC_HPRE                                ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
+#define RCC_HPRE_0                              ((uint32_t)0x00000010) /* Bit 0 */
+#define RCC_HPRE_1                              ((uint32_t)0x00000020) /* Bit 1 */
+#define RCC_HPRE_2                              ((uint32_t)0x00000040) /* Bit 2 */
+#define RCC_HPRE_3                              ((uint32_t)0x00000080) /* Bit 3 */
+
+#define RCC_HPRE_DIV1                           ((uint32_t)0x00000000) /* SYSCLK not divided */
+#define RCC_HPRE_DIV2                           ((uint32_t)0x00000080) /* SYSCLK divided by 2 */
+#define RCC_HPRE_DIV4                           ((uint32_t)0x00000090) /* SYSCLK divided by 4 */
+#define RCC_HPRE_DIV8                           ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */
+#define RCC_HPRE_DIV16                          ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */
+#define RCC_HPRE_DIV64                          ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */
+#define RCC_HPRE_DIV128                         ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */
+#define RCC_HPRE_DIV256                         ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */
+#define RCC_HPRE_DIV512                         ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */
+
+#define RCC_PPRE1                               ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
+#define RCC_PPRE1_0                             ((uint32_t)0x00000100) /* Bit 0 */
+#define RCC_PPRE1_1                             ((uint32_t)0x00000200) /* Bit 1 */
+#define RCC_PPRE1_2                             ((uint32_t)0x00000400) /* Bit 2 */
+
+#define RCC_PPRE1_DIV1                          ((uint32_t)0x00000000) /* HCLK not divided */
+#define RCC_PPRE1_DIV2                          ((uint32_t)0x00000400) /* HCLK divided by 2 */
+#define RCC_PPRE1_DIV4                          ((uint32_t)0x00000500) /* HCLK divided by 4 */
+#define RCC_PPRE1_DIV8                          ((uint32_t)0x00000600) /* HCLK divided by 8 */
+#define RCC_PPRE1_DIV16                         ((uint32_t)0x00000700) /* HCLK divided by 16 */
+
+#define RCC_PPRE2                               ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
+#define RCC_PPRE2_0                             ((uint32_t)0x00000800) /* Bit 0 */
+#define RCC_PPRE2_1                             ((uint32_t)0x00001000) /* Bit 1 */
+#define RCC_PPRE2_2                             ((uint32_t)0x00002000) /* Bit 2 */
+
+#define RCC_PPRE2_DIV1                          ((uint32_t)0x00000000) /* HCLK not divided */
+#define RCC_PPRE2_DIV2                          ((uint32_t)0x00002000) /* HCLK divided by 2 */
+#define RCC_PPRE2_DIV4                          ((uint32_t)0x00002800) /* HCLK divided by 4 */
+#define RCC_PPRE2_DIV8                          ((uint32_t)0x00003000) /* HCLK divided by 8 */
+#define RCC_PPRE2_DIV16                         ((uint32_t)0x00003800) /* HCLK divided by 16 */
+
+#define RCC_ADCPRE                              ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
+#define RCC_ADCPRE_0                            ((uint32_t)0x00004000) /* Bit 0 */
+#define RCC_ADCPRE_1                            ((uint32_t)0x00008000) /* Bit 1 */
+
+#define RCC_ADCPRE_DIV2                         ((uint32_t)0x00000000) /* PCLK2 divided by 2 */
+#define RCC_ADCPRE_DIV4                         ((uint32_t)0x00004000) /* PCLK2 divided by 4 */
+#define RCC_ADCPRE_DIV6                         ((uint32_t)0x00008000) /* PCLK2 divided by 6 */
+#define RCC_ADCPRE_DIV8                         ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */
+
+#define RCC_PLLSRC                              ((uint32_t)0x00010000) /* PLL entry clock source */
+
+#define RCC_PLLXTPRE                            ((uint32_t)0x00020000) /* HSE divider for PLL entry */
+
+#define RCC_PLLMULL                             ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
+#define RCC_PLLMULL_0                           ((uint32_t)0x00040000) /* Bit 0 */
+#define RCC_PLLMULL_1                           ((uint32_t)0x00080000) /* Bit 1 */
+#define RCC_PLLMULL_2                           ((uint32_t)0x00100000) /* Bit 2 */
+#define RCC_PLLMULL_3                           ((uint32_t)0x00200000) /* Bit 3 */
+
+#define RCC_PLLSRC_HSI_Div2                     ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */
+#define RCC_PLLSRC_HSE                          ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */
+
+#define RCC_PLLXTPRE_HSE                        ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */
+#define RCC_PLLXTPRE_HSE_Div2                   ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */
+
+#define RCC_PLLMULL2                            ((uint32_t)0x00000000) /* PLL input clock*2 */
+#define RCC_PLLMULL3                            ((uint32_t)0x00040000) /* PLL input clock*3 */
+#define RCC_PLLMULL4                            ((uint32_t)0x00080000) /* PLL input clock*4 */
+#define RCC_PLLMULL5                            ((uint32_t)0x000C0000) /* PLL input clock*5 */
+#define RCC_PLLMULL6                            ((uint32_t)0x00100000) /* PLL input clock*6 */
+#define RCC_PLLMULL7                            ((uint32_t)0x00140000) /* PLL input clock*7 */
+#define RCC_PLLMULL8                            ((uint32_t)0x00180000) /* PLL input clock*8 */
+#define RCC_PLLMULL9                            ((uint32_t)0x001C0000) /* PLL input clock*9 */
+#define RCC_PLLMULL10                           ((uint32_t)0x00200000) /* PLL input clock10 */
+#define RCC_PLLMULL11                           ((uint32_t)0x00240000) /* PLL input clock*11 */
+#define RCC_PLLMULL12                           ((uint32_t)0x00280000) /* PLL input clock*12 */
+#define RCC_PLLMULL13                           ((uint32_t)0x002C0000) /* PLL input clock*13 */
+#define RCC_PLLMULL14                           ((uint32_t)0x00300000) /* PLL input clock*14 */
+#define RCC_PLLMULL15                           ((uint32_t)0x00340000) /* PLL input clock*15 */
+#define RCC_PLLMULL16                           ((uint32_t)0x00380000) /* PLL input clock*16 */
+#define RCC_USBPRE                              ((uint32_t)0x00400000) /* USB Device prescaler */
+
+#define RCC_CFGR0_MCO                           ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
+#define RCC_MCO_0                               ((uint32_t)0x01000000) /* Bit 0 */
+#define RCC_MCO_1                               ((uint32_t)0x02000000) /* Bit 1 */
+#define RCC_MCO_2                               ((uint32_t)0x04000000) /* Bit 2 */
+
+#define RCC_MCO_NOCLOCK                         ((uint32_t)0x00000000) /* No clock */
+#define RCC_CFGR0_MCO_SYSCLK                    ((uint32_t)0x04000000) /* System clock selected as MCO source */
+#define RCC_CFGR0_MCO_HSI                       ((uint32_t)0x05000000) /* HSI clock selected as MCO source */
+#define RCC_CFGR0_MCO_HSE                       ((uint32_t)0x06000000) /* HSE clock selected as MCO source  */
+#define RCC_CFGR0_MCO_PLL                       ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */
+
+/*******************  Bit definition for RCC_INTR register  ********************/
+#define RCC_LSIRDYF                             ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */
+#define RCC_LSERDYF                             ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */
+#define RCC_HSIRDYF                             ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */
+#define RCC_HSERDYF                             ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */
+#define RCC_PLLRDYF                             ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */
+#define RCC_CSSF                                ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */
+#define RCC_LSIRDYIE                            ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */
+#define RCC_LSERDYIE                            ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */
+#define RCC_HSIRDYIE                            ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */
+#define RCC_HSERDYIE                            ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */
+#define RCC_PLLRDYIE                            ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */
+#define RCC_LSIRDYC                             ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */
+#define RCC_LSERDYC                             ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */
+#define RCC_HSIRDYC                             ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */
+#define RCC_HSERDYC                             ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */
+#define RCC_PLLRDYC                             ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */
+#define RCC_CSSC                                ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */
+
+/*****************  Bit definition for RCC_APB2PRSTR register  *****************/
+#define RCC_AFIORST                             ((uint32_t)0x00000001) /* Alternate Function I/O reset */
+#define RCC_IOPARST                             ((uint32_t)0x00000004) /* I/O port A reset */
+#define RCC_IOPBRST                             ((uint32_t)0x00000008) /* I/O port B reset */
+#define RCC_IOPCRST                             ((uint32_t)0x00000010) /* I/O port C reset */
+#define RCC_IOPDRST                             ((uint32_t)0x00000020) /* I/O port D reset */
+#define RCC_ADC1RST                             ((uint32_t)0x00000200) /* ADC 1 interface reset */
+
+#define RCC_ADC2RST                             ((uint32_t)0x00000400) /* ADC 2 interface reset */
+
+#define RCC_TIM1RST                             ((uint32_t)0x00000800) /* TIM1 Timer reset */
+#define RCC_SPI1RST                             ((uint32_t)0x00001000) /* SPI 1 reset */
+#define RCC_USART1RST                           ((uint32_t)0x00004000) /* USART1 reset */
+
+#define RCC_IOPERST                             ((uint32_t)0x00000040) /* I/O port E reset */
+
+/*****************  Bit definition for RCC_APB1PRSTR register  *****************/
+#define RCC_TIM2RST                             ((uint32_t)0x00000001) /* Timer 2 reset */
+#define RCC_TIM3RST                             ((uint32_t)0x00000002) /* Timer 3 reset */
+#define RCC_WWDGRST                             ((uint32_t)0x00000800) /* Window Watchdog reset */
+#define RCC_USART2RST                           ((uint32_t)0x00020000) /* USART 2 reset */
+#define RCC_I2C1RST                             ((uint32_t)0x00200000) /* I2C 1 reset */
+
+#define RCC_CAN1RST                             ((uint32_t)0x02000000) /* CAN1 reset */
+
+#define RCC_BKPRST                              ((uint32_t)0x08000000) /* Backup interface reset */
+#define RCC_PWRRST                              ((uint32_t)0x10000000) /* Power interface reset */
+
+#define RCC_TIM4RST                             ((uint32_t)0x00000004) /* Timer 4 reset */
+#define RCC_SPI2RST                             ((uint32_t)0x00004000) /* SPI 2 reset */
+#define RCC_USART3RST                           ((uint32_t)0x00040000) /* USART 3 reset */
+#define RCC_I2C2RST                             ((uint32_t)0x00400000) /* I2C 2 reset */
+
+#define RCC_USBRST                              ((uint32_t)0x00800000) /* USB Device reset */
+
+/******************  Bit definition for RCC_AHBPCENR register  ******************/
+#define RCC_DMA1EN                              ((uint16_t)0x0001) /* DMA1 clock enable */
+#define RCC_SRAMEN                              ((uint16_t)0x0004) /* SRAM interface clock enable */
+#define RCC_FLITFEN                             ((uint16_t)0x0010) /* FLITF clock enable */
+#define RCC_CRCEN                               ((uint16_t)0x0040) /* CRC clock enable */
+#define RCC_USBHD                               ((uint16_t)0x1000)
+
+/******************  Bit definition for RCC_APB2PCENR register  *****************/
+#define RCC_AFIOEN                              ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
+#define RCC_IOPAEN                              ((uint32_t)0x00000004) /* I/O port A clock enable */
+#define RCC_IOPBEN                              ((uint32_t)0x00000008) /* I/O port B clock enable */
+#define RCC_IOPCEN                              ((uint32_t)0x00000010) /* I/O port C clock enable */
+#define RCC_IOPDEN                              ((uint32_t)0x00000020) /* I/O port D clock enable */
+#define RCC_ADC1EN                              ((uint32_t)0x00000200) /* ADC 1 interface clock enable */
+
+#define RCC_ADC2EN                              ((uint32_t)0x00000400) /* ADC 2 interface clock enable */
+
+#define RCC_TIM1EN                              ((uint32_t)0x00000800) /* TIM1 Timer clock enable */
+#define RCC_SPI1EN                              ((uint32_t)0x00001000) /* SPI 1 clock enable */
+#define RCC_USART1EN                            ((uint32_t)0x00004000) /* USART1 clock enable */
+
+/*****************  Bit definition for RCC_APB1PCENR register  ******************/
+#define RCC_TIM2EN                              ((uint32_t)0x00000001) /* Timer 2 clock enabled*/
+#define RCC_TIM3EN                              ((uint32_t)0x00000002) /* Timer 3 clock enable */
+#define RCC_WWDGEN                              ((uint32_t)0x00000800) /* Window Watchdog clock enable */
+#define RCC_USART2EN                            ((uint32_t)0x00020000) /* USART 2 clock enable */
+#define RCC_I2C1EN                              ((uint32_t)0x00200000) /* I2C 1 clock enable */
+
+#define RCC_BKPEN                               ((uint32_t)0x08000000) /* Backup interface clock enable */
+#define RCC_PWREN                               ((uint32_t)0x10000000) /* Power interface clock enable */
+
+#define RCC_USBEN                               ((uint32_t)0x00800000) /* USB Device clock enable */
+
+/*******************  Bit definition for RCC_BDCTLR register  *******************/
+#define RCC_LSEON                               ((uint32_t)0x00000001) /* External Low Speed oscillator enable */
+#define RCC_LSERDY                              ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */
+#define RCC_LSEBYP                              ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */
+
+#define RCC_RTCSEL                              ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */
+#define RCC_RTCSEL_0                            ((uint32_t)0x00000100) /* Bit 0 */
+#define RCC_RTCSEL_1                            ((uint32_t)0x00000200) /* Bit 1 */
+
+#define RCC_RTCSEL_NOCLOCK                      ((uint32_t)0x00000000) /* No clock */
+#define RCC_RTCSEL_LSE                          ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */
+#define RCC_RTCSEL_LSI                          ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */
+#define RCC_RTCSEL_HSE                          ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */
+
+#define RCC_RTCEN                               ((uint32_t)0x00008000) /* RTC clock enable */
+#define RCC_BDRST                               ((uint32_t)0x00010000) /* Backup domain software reset  */
+
+/*******************  Bit definition for RCC_RSTSCKR register  ********************/
+#define RCC_LSION                               ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
+#define RCC_LSIRDY                              ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
+#define RCC_RMVF                                ((uint32_t)0x01000000) /* Remove reset flag */
+#define RCC_PINRSTF                             ((uint32_t)0x04000000) /* PIN reset flag */
+#define RCC_PORRSTF                             ((uint32_t)0x08000000) /* POR/PDR reset flag */
+#define RCC_SFTRSTF                             ((uint32_t)0x10000000) /* Software Reset flag */
+#define RCC_IWDGRSTF                            ((uint32_t)0x20000000) /* Independent Watchdog reset flag */
+#define RCC_WWDGRSTF                            ((uint32_t)0x40000000) /* Window watchdog reset flag */
+#define RCC_LPWRRSTF                            ((uint32_t)0x80000000) /* Low-Power reset flag */
+
+/******************************************************************************/
+/*                             Real-Time Clock                                */
+/******************************************************************************/
+
+/*******************  Bit definition for RTC_CTLRH register  ********************/
+#define RTC_CTLRH_SECIE                         ((uint8_t)0x01) /* Second Interrupt Enable */
+#define RTC_CTLRH_ALRIE                         ((uint8_t)0x02) /* Alarm Interrupt Enable */
+#define RTC_CTLRH_OWIE                          ((uint8_t)0x04) /* OverfloW Interrupt Enable */
+
+/*******************  Bit definition for RTC_CTLRL register  ********************/
+#define RTC_CTLRL_SECF                          ((uint8_t)0x01) /* Second Flag */
+#define RTC_CTLRL_ALRF                          ((uint8_t)0x02) /* Alarm Flag */
+#define RTC_CTLRL_OWF                           ((uint8_t)0x04) /* OverfloW Flag */
+#define RTC_CTLRL_RSF                           ((uint8_t)0x08) /* Registers Synchronized Flag */
+#define RTC_CTLRL_CNF                           ((uint8_t)0x10) /* Configuration Flag */
+#define RTC_CTLRL_RTOFF                         ((uint8_t)0x20) /* RTC operation OFF */
+
+/*******************  Bit definition for RTC_PSCH register  *******************/
+#define RTC_PSCH_PRL                            ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */
+
+/*******************  Bit definition for RTC_PRLL register  *******************/
+#define RTC_PSCL_PRL                            ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */
+
+/*******************  Bit definition for RTC_DIVH register  *******************/
+#define RTC_DIVH_RTC_DIV                        ((uint16_t)0x000F) /* RTC Clock Divider High */
+
+/*******************  Bit definition for RTC_DIVL register  *******************/
+#define RTC_DIVL_RTC_DIV                        ((uint16_t)0xFFFF) /* RTC Clock Divider Low */
+
+/*******************  Bit definition for RTC_CNTH register  *******************/
+#define RTC_CNTH_RTC_CNT                        ((uint16_t)0xFFFF) /* RTC Counter High */
+
+/*******************  Bit definition for RTC_CNTL register  *******************/
+#define RTC_CNTL_RTC_CNT                        ((uint16_t)0xFFFF) /* RTC Counter Low */
+
+/*******************  Bit definition for RTC_ALRMH register  *******************/
+#define RTC_ALRMH_RTC_ALRM                      ((uint16_t)0xFFFF) /* RTC Alarm High */
+
+/*******************  Bit definition for RTC_ALRML register  *******************/
+#define RTC_ALRML_RTC_ALRM                      ((uint16_t)0xFFFF) /* RTC Alarm Low */
+
+/******************************************************************************/
+/*                        Serial Peripheral Interface                         */
+/******************************************************************************/
+
+/*******************  Bit definition for SPI_CTLR1 register  ********************/
+#define SPI_CTLR1_CPHA                          ((uint16_t)0x0001) /* Clock Phase */
+#define SPI_CTLR1_CPOL                          ((uint16_t)0x0002) /* Clock Polarity */
+#define SPI_CTLR1_MSTR                          ((uint16_t)0x0004) /* Master Selection */
+
+#define SPI_CTLR1_BR                            ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */
+#define SPI_CTLR1_BR_0                          ((uint16_t)0x0008) /* Bit 0 */
+#define SPI_CTLR1_BR_1                          ((uint16_t)0x0010) /* Bit 1 */
+#define SPI_CTLR1_BR_2                          ((uint16_t)0x0020) /* Bit 2 */
+
+#define SPI_CTLR1_SPE                           ((uint16_t)0x0040) /* SPI Enable */
+#define SPI_CTLR1_LSBFIRST                      ((uint16_t)0x0080) /* Frame Format */
+#define SPI_CTLR1_SSI                           ((uint16_t)0x0100) /* Internal slave select */
+#define SPI_CTLR1_SSM                           ((uint16_t)0x0200) /* Software slave management */
+#define SPI_CTLR1_RXONLY                        ((uint16_t)0x0400) /* Receive only */
+#define SPI_CTLR1_DFF                           ((uint16_t)0x0800) /* Data Frame Format */
+#define SPI_CTLR1_CRCNEXT                       ((uint16_t)0x1000) /* Transmit CRC next */
+#define SPI_CTLR1_CRCEN                         ((uint16_t)0x2000) /* Hardware CRC calculation enable */
+#define SPI_CTLR1_BIDIOE                        ((uint16_t)0x4000) /* Output enable in bidirectional mode */
+#define SPI_CTLR1_BIDIMODE                      ((uint16_t)0x8000) /* Bidirectional data mode enable */
+
+/*******************  Bit definition for SPI_CTLR2 register  ********************/
+#define SPI_CTLR2_RXDMAEN                       ((uint8_t)0x01) /* Rx Buffer DMA Enable */
+#define SPI_CTLR2_TXDMAEN                       ((uint8_t)0x02) /* Tx Buffer DMA Enable */
+#define SPI_CTLR2_SSOE                          ((uint8_t)0x04) /* SS Output Enable */
+#define SPI_CTLR2_ERRIE                         ((uint8_t)0x20) /* Error Interrupt Enable */
+#define SPI_CTLR2_RXNEIE                        ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */
+#define SPI_CTLR2_TXEIE                         ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */
+
+/********************  Bit definition for SPI_STATR register  ********************/
+#define SPI_STATR_RXNE                          ((uint8_t)0x01) /* Receive buffer Not Empty */
+#define SPI_STATR_TXE                           ((uint8_t)0x02) /* Transmit buffer Empty */
+#define SPI_STATR_CHSIDE                        ((uint8_t)0x04) /* Channel side */
+#define SPI_STATR_UDR                           ((uint8_t)0x08) /* Underrun flag */
+#define SPI_STATR_CRCERR                        ((uint8_t)0x10) /* CRC Error flag */
+#define SPI_STATR_MODF                          ((uint8_t)0x20) /* Mode fault */
+#define SPI_STATR_OVR                           ((uint8_t)0x40) /* Overrun flag */
+#define SPI_STATR_BSY                           ((uint8_t)0x80) /* Busy flag */
+
+/********************  Bit definition for SPI_DATAR register  ********************/
+#define SPI_DATAR_DR                            ((uint16_t)0xFFFF) /* Data Register */
+
+/*******************  Bit definition for SPI_CRCR register  ******************/
+#define SPI_CRCR_CRCPOLY                        ((uint16_t)0xFFFF) /* CRC polynomial register */
+
+/******************  Bit definition for SPI_RCRCR register  ******************/
+#define SPI_RCRCR_RXCRC                         ((uint16_t)0xFFFF) /* Rx CRC Register */
+
+/******************  Bit definition for SPI_TCRCR register  ******************/
+#define SPI_TCRCR_TXCRC                         ((uint16_t)0xFFFF) /* Tx CRC Register */
+
+/******************  Bit definition for SPI_I2SCFGR register  *****************/
+#define SPI_I2SCFGR_CHLEN                       ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */
+
+#define SPI_I2SCFGR_DATLEN                      ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */
+#define SPI_I2SCFGR_DATLEN_0                    ((uint16_t)0x0002) /* Bit 0 */
+#define SPI_I2SCFGR_DATLEN_1                    ((uint16_t)0x0004) /* Bit 1 */
+
+#define SPI_I2SCFGR_CKPOL                       ((uint16_t)0x0008) /* steady state clock polarity */
+
+#define SPI_I2SCFGR_I2SSTD                      ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */
+#define SPI_I2SCFGR_I2SSTD_0                    ((uint16_t)0x0010) /* Bit 0 */
+#define SPI_I2SCFGR_I2SSTD_1                    ((uint16_t)0x0020) /* Bit 1 */
+
+#define SPI_I2SCFGR_PCMSYNC                     ((uint16_t)0x0080) /* PCM frame synchronization */
+
+#define SPI_I2SCFGR_I2SCFG                      ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */
+#define SPI_I2SCFGR_I2SCFG_0                    ((uint16_t)0x0100) /* Bit 0 */
+#define SPI_I2SCFGR_I2SCFG_1                    ((uint16_t)0x0200) /* Bit 1 */
+
+#define SPI_I2SCFGR_I2SE                        ((uint16_t)0x0400) /* I2S Enable */
+#define SPI_I2SCFGR_I2SMOD                      ((uint16_t)0x0800) /* I2S mode selection */
+
+/******************  Bit definition for SPI_I2SPR register  *******************/
+#define SPI_I2SPR_I2SDIV                        ((uint16_t)0x00FF) /* I2S Linear prescaler */
+#define SPI_I2SPR_ODD                           ((uint16_t)0x0100) /* Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE                         ((uint16_t)0x0200) /* Master Clock Output Enable */
+
+/******************************************************************************/
+/*                                    TIM                                     */
+/******************************************************************************/
+
+/*******************  Bit definition for TIM_CTLR1 register  ********************/
+#define TIM_CEN                                 ((uint16_t)0x0001) /* Counter enable */
+#define TIM_UDIS                                ((uint16_t)0x0002) /* Update disable */
+#define TIM_URS                                 ((uint16_t)0x0004) /* Update request source */
+#define TIM_OPM                                 ((uint16_t)0x0008) /* One pulse mode */
+#define TIM_DIR                                 ((uint16_t)0x0010) /* Direction */
+
+#define TIM_CMS                                 ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
+#define TIM_CMS_0                               ((uint16_t)0x0020) /* Bit 0 */
+#define TIM_CMS_1                               ((uint16_t)0x0040) /* Bit 1 */
+
+#define TIM_ARPE                                ((uint16_t)0x0080) /* Auto-reload preload enable */
+
+#define TIM_CTLR1_CKD                           ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */
+#define TIM_CKD_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CKD_1                               ((uint16_t)0x0200) /* Bit 1 */
+
+/*******************  Bit definition for TIM_CTLR2 register  ********************/
+#define TIM_CCPC                                ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */
+#define TIM_CCUS                                ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */
+#define TIM_CCDS                                ((uint16_t)0x0008) /* Capture/Compare DMA Selection */
+
+#define TIM_MMS                                 ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
+#define TIM_MMS_0                               ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_MMS_1                               ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_MMS_2                               ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_TI1S                                ((uint16_t)0x0080) /* TI1 Selection */
+#define TIM_OIS1                                ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */
+#define TIM_OIS1N                               ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */
+#define TIM_OIS2                                ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */
+#define TIM_OIS2N                               ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */
+#define TIM_OIS3                                ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */
+#define TIM_OIS3N                               ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */
+#define TIM_OIS4                                ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */
+
+/*******************  Bit definition for TIM_SMCFGR register  *******************/
+#define TIM_SMS                                 ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */
+#define TIM_SMS_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_SMS_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_SMS_2                               ((uint16_t)0x0004) /* Bit 2 */
+
+#define TIM_TS                                  ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */
+#define TIM_TS_0                                ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_TS_1                                ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_TS_2                                ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_MSM                                 ((uint16_t)0x0080) /* Master/slave mode */
+
+#define TIM_ETF                                 ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */
+#define TIM_ETF_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_ETF_1                               ((uint16_t)0x0200) /* Bit 1 */
+#define TIM_ETF_2                               ((uint16_t)0x0400) /* Bit 2 */
+#define TIM_ETF_3                               ((uint16_t)0x0800) /* Bit 3 */
+
+#define TIM_ETPS                                ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
+#define TIM_ETPS_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_ETPS_1                              ((uint16_t)0x2000) /* Bit 1 */
+
+#define TIM_ECE                                 ((uint16_t)0x4000) /* External clock enable */
+#define TIM_ETP                                 ((uint16_t)0x8000) /* External trigger polarity */
+
+/*******************  Bit definition for TIM_DMAINTENR register  *******************/
+#define TIM_UIE                                 ((uint16_t)0x0001) /* Update interrupt enable */
+#define TIM_CC1IE                               ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */
+#define TIM_CC2IE                               ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */
+#define TIM_CC3IE                               ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */
+#define TIM_CC4IE                               ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */
+#define TIM_COMIE                               ((uint16_t)0x0020) /* COM interrupt enable */
+#define TIM_TIE                                 ((uint16_t)0x0040) /* Trigger interrupt enable */
+#define TIM_BIE                                 ((uint16_t)0x0080) /* Break interrupt enable */
+#define TIM_UDE                                 ((uint16_t)0x0100) /* Update DMA request enable */
+#define TIM_CC1DE                               ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */
+#define TIM_CC2DE                               ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */
+#define TIM_CC3DE                               ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */
+#define TIM_CC4DE                               ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */
+#define TIM_COMDE                               ((uint16_t)0x2000) /* COM DMA request enable */
+#define TIM_TDE                                 ((uint16_t)0x4000) /* Trigger DMA request enable */
+
+/********************  Bit definition for TIM_INTFR register  ********************/
+#define TIM_UIF                                 ((uint16_t)0x0001) /* Update interrupt Flag */
+#define TIM_CC1IF                               ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */
+#define TIM_CC2IF                               ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */
+#define TIM_CC3IF                               ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */
+#define TIM_CC4IF                               ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */
+#define TIM_COMIF                               ((uint16_t)0x0020) /* COM interrupt Flag */
+#define TIM_TIF                                 ((uint16_t)0x0040) /* Trigger interrupt Flag */
+#define TIM_BIF                                 ((uint16_t)0x0080) /* Break interrupt Flag */
+#define TIM_CC1OF                               ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */
+#define TIM_CC2OF                               ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */
+#define TIM_CC3OF                               ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */
+#define TIM_CC4OF                               ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */
+
+/*******************  Bit definition for TIM_SWEVGR register  ********************/
+#define TIM_UG                                  ((uint8_t)0x01) /* Update Generation */
+#define TIM_CC1G                                ((uint8_t)0x02) /* Capture/Compare 1 Generation */
+#define TIM_CC2G                                ((uint8_t)0x04) /* Capture/Compare 2 Generation */
+#define TIM_CC3G                                ((uint8_t)0x08) /* Capture/Compare 3 Generation */
+#define TIM_CC4G                                ((uint8_t)0x10) /* Capture/Compare 4 Generation */
+#define TIM_COMG                                ((uint8_t)0x20) /* Capture/Compare Control Update Generation */
+#define TIM_TG                                  ((uint8_t)0x40) /* Trigger Generation */
+#define TIM_BG                                  ((uint8_t)0x80) /* Break Generation */
+
+/******************  Bit definition for TIM_CHCTLR1 register  *******************/
+#define TIM_CC1S                                ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
+#define TIM_CC1S_0                              ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_CC1S_1                              ((uint16_t)0x0002) /* Bit 1 */
+
+#define TIM_OC1FE                               ((uint16_t)0x0004) /* Output Compare 1 Fast enable */
+#define TIM_OC1PE                               ((uint16_t)0x0008) /* Output Compare 1 Preload enable */
+
+#define TIM_OC1M                                ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
+#define TIM_OC1M_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_OC1M_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_OC1M_2                              ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_OC1CE                               ((uint16_t)0x0080) /* Output Compare 1Clear Enable */
+
+#define TIM_CC2S                                ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
+#define TIM_CC2S_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CC2S_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OC2FE                               ((uint16_t)0x0400) /* Output Compare 2 Fast enable */
+#define TIM_OC2PE                               ((uint16_t)0x0800) /* Output Compare 2 Preload enable */
+
+#define TIM_OC2M                                ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
+#define TIM_OC2M_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_OC2M_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_OC2M_2                              ((uint16_t)0x4000) /* Bit 2 */
+
+#define TIM_OC2CE                               ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */
+
+#define TIM_IC1PSC                              ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
+#define TIM_IC1PSC_0                            ((uint16_t)0x0004) /* Bit 0 */
+#define TIM_IC1PSC_1                            ((uint16_t)0x0008) /* Bit 1 */
+
+#define TIM_IC1F                                ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
+#define TIM_IC1F_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_IC1F_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_IC1F_2                              ((uint16_t)0x0040) /* Bit 2 */
+#define TIM_IC1F_3                              ((uint16_t)0x0080) /* Bit 3 */
+
+#define TIM_IC2PSC                              ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
+#define TIM_IC2PSC_0                            ((uint16_t)0x0400) /* Bit 0 */
+#define TIM_IC2PSC_1                            ((uint16_t)0x0800) /* Bit 1 */
+
+#define TIM_IC2F                                ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
+#define TIM_IC2F_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_IC2F_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_IC2F_2                              ((uint16_t)0x4000) /* Bit 2 */
+#define TIM_IC2F_3                              ((uint16_t)0x8000) /* Bit 3 */
+
+/******************  Bit definition for TIM_CHCTLR2 register  *******************/
+#define TIM_CC3S                                ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
+#define TIM_CC3S_0                              ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_CC3S_1                              ((uint16_t)0x0002) /* Bit 1 */
+
+#define TIM_OC3FE                               ((uint16_t)0x0004) /* Output Compare 3 Fast enable */
+#define TIM_OC3PE                               ((uint16_t)0x0008) /* Output Compare 3 Preload enable */
+
+#define TIM_OC3M                                ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
+#define TIM_OC3M_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_OC3M_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_OC3M_2                              ((uint16_t)0x0040) /* Bit 2 */
+
+#define TIM_OC3CE                               ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */
+
+#define TIM_CC4S                                ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
+#define TIM_CC4S_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_CC4S_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OC4FE                               ((uint16_t)0x0400) /* Output Compare 4 Fast enable */
+#define TIM_OC4PE                               ((uint16_t)0x0800) /* Output Compare 4 Preload enable */
+
+#define TIM_OC4M                                ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
+#define TIM_OC4M_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_OC4M_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_OC4M_2                              ((uint16_t)0x4000) /* Bit 2 */
+
+#define TIM_OC4CE                               ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */
+
+#define TIM_IC3PSC                              ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
+#define TIM_IC3PSC_0                            ((uint16_t)0x0004) /* Bit 0 */
+#define TIM_IC3PSC_1                            ((uint16_t)0x0008) /* Bit 1 */
+
+#define TIM_IC3F                                ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
+#define TIM_IC3F_0                              ((uint16_t)0x0010) /* Bit 0 */
+#define TIM_IC3F_1                              ((uint16_t)0x0020) /* Bit 1 */
+#define TIM_IC3F_2                              ((uint16_t)0x0040) /* Bit 2 */
+#define TIM_IC3F_3                              ((uint16_t)0x0080) /* Bit 3 */
+
+#define TIM_IC4PSC                              ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
+#define TIM_IC4PSC_0                            ((uint16_t)0x0400) /* Bit 0 */
+#define TIM_IC4PSC_1                            ((uint16_t)0x0800) /* Bit 1 */
+
+#define TIM_IC4F                                ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
+#define TIM_IC4F_0                              ((uint16_t)0x1000) /* Bit 0 */
+#define TIM_IC4F_1                              ((uint16_t)0x2000) /* Bit 1 */
+#define TIM_IC4F_2                              ((uint16_t)0x4000) /* Bit 2 */
+#define TIM_IC4F_3                              ((uint16_t)0x8000) /* Bit 3 */
+
+/*******************  Bit definition for TIM_CCER register  *******************/
+#define TIM_CC1E                                ((uint16_t)0x0001) /* Capture/Compare 1 output enable */
+#define TIM_CC1P                                ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */
+#define TIM_CC1NE                               ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */
+#define TIM_CC1NP                               ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */
+#define TIM_CC2E                                ((uint16_t)0x0010) /* Capture/Compare 2 output enable */
+#define TIM_CC2P                                ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */
+#define TIM_CC2NE                               ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */
+#define TIM_CC2NP                               ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */
+#define TIM_CC3E                                ((uint16_t)0x0100) /* Capture/Compare 3 output enable */
+#define TIM_CC3P                                ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */
+#define TIM_CC3NE                               ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */
+#define TIM_CC3NP                               ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */
+#define TIM_CC4E                                ((uint16_t)0x1000) /* Capture/Compare 4 output enable */
+#define TIM_CC4P                                ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */
+#define TIM_CC4NP                               ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */
+
+/*******************  Bit definition for TIM_CNT register  ********************/
+#define TIM_CNT                                 ((uint16_t)0xFFFF) /* Counter Value */
+
+/*******************  Bit definition for TIM_PSC register  ********************/
+#define TIM_PSC                                 ((uint16_t)0xFFFF) /* Prescaler Value */
+
+/*******************  Bit definition for TIM_ATRLR register  ********************/
+#define TIM_ARR                                 ((uint16_t)0xFFFF) /* actual auto-reload Value */
+
+/*******************  Bit definition for TIM_RPTCR register  ********************/
+#define TIM_REP                                 ((uint8_t)0xFF) /* Repetition Counter Value */
+
+/*******************  Bit definition for TIM_CH1CVR register  *******************/
+#define TIM_CCR1                                ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */
+
+/*******************  Bit definition for TIM_CH2CVR register  *******************/
+#define TIM_CCR2                                ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */
+
+/*******************  Bit definition for TIM_CH3CVR register  *******************/
+#define TIM_CCR3                                ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */
+
+/*******************  Bit definition for TIM_CH4CVR register  *******************/
+#define TIM_CCR4                                ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */
+
+/*******************  Bit definition for TIM_BDTR register  *******************/
+#define TIM_DTG                                 ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_DTG_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_DTG_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_DTG_2                               ((uint16_t)0x0004) /* Bit 2 */
+#define TIM_DTG_3                               ((uint16_t)0x0008) /* Bit 3 */
+#define TIM_DTG_4                               ((uint16_t)0x0010) /* Bit 4 */
+#define TIM_DTG_5                               ((uint16_t)0x0020) /* Bit 5 */
+#define TIM_DTG_6                               ((uint16_t)0x0040) /* Bit 6 */
+#define TIM_DTG_7                               ((uint16_t)0x0080) /* Bit 7 */
+
+#define TIM_LOCK                                ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
+#define TIM_LOCK_0                              ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_LOCK_1                              ((uint16_t)0x0200) /* Bit 1 */
+
+#define TIM_OSSI                                ((uint16_t)0x0400) /* Off-State Selection for Idle mode */
+#define TIM_OSSR                                ((uint16_t)0x0800) /* Off-State Selection for Run mode */
+#define TIM_BKE                                 ((uint16_t)0x1000) /* Break enable */
+#define TIM_BKP                                 ((uint16_t)0x2000) /* Break Polarity */
+#define TIM_AOE                                 ((uint16_t)0x4000) /* Automatic Output enable */
+#define TIM_MOE                                 ((uint16_t)0x8000) /* Main Output enable */
+
+/*******************  Bit definition for TIM_DMACFGR register  ********************/
+#define TIM_DBA                                 ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */
+#define TIM_DBA_0                               ((uint16_t)0x0001) /* Bit 0 */
+#define TIM_DBA_1                               ((uint16_t)0x0002) /* Bit 1 */
+#define TIM_DBA_2                               ((uint16_t)0x0004) /* Bit 2 */
+#define TIM_DBA_3                               ((uint16_t)0x0008) /* Bit 3 */
+#define TIM_DBA_4                               ((uint16_t)0x0010) /* Bit 4 */
+
+#define TIM_DBL                                 ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
+#define TIM_DBL_0                               ((uint16_t)0x0100) /* Bit 0 */
+#define TIM_DBL_1                               ((uint16_t)0x0200) /* Bit 1 */
+#define TIM_DBL_2                               ((uint16_t)0x0400) /* Bit 2 */
+#define TIM_DBL_3                               ((uint16_t)0x0800) /* Bit 3 */
+#define TIM_DBL_4                               ((uint16_t)0x1000) /* Bit 4 */
+
+/*******************  Bit definition for TIM_DMAADR register  *******************/
+#define TIM_DMAR_DMAB                           ((uint16_t)0xFFFF) /* DMA register for burst accesses */
+
+/******************************************************************************/
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */
+/******************************************************************************/
+
+/*******************  Bit definition for USART_STATR register  *******************/
+#define USART_STATR_PE                          ((uint16_t)0x0001) /* Parity Error */
+#define USART_STATR_FE                          ((uint16_t)0x0002) /* Framing Error */
+#define USART_STATR_NE                          ((uint16_t)0x0004) /* Noise Error Flag */
+#define USART_STATR_ORE                         ((uint16_t)0x0008) /* OverRun Error */
+#define USART_STATR_IDLE                        ((uint16_t)0x0010) /* IDLE line detected */
+#define USART_STATR_RXNE                        ((uint16_t)0x0020) /* Read Data Register Not Empty */
+#define USART_STATR_TC                          ((uint16_t)0x0040) /* Transmission Complete */
+#define USART_STATR_TXE                         ((uint16_t)0x0080) /* Transmit Data Register Empty */
+#define USART_STATR_LBD                         ((uint16_t)0x0100) /* LIN Break Detection Flag */
+#define USART_STATR_CTS                         ((uint16_t)0x0200) /* CTS Flag */
+
+/*******************  Bit definition for USART_DATAR register  *******************/
+#define USART_DATAR_DR                          ((uint16_t)0x01FF) /* Data value */
+
+/******************  Bit definition for USART_BRR register  *******************/
+#define USART_BRR_DIV_Fraction                  ((uint16_t)0x000F) /* Fraction of USARTDIV */
+#define USART_BRR_DIV_Mantissa                  ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */
+
+/******************  Bit definition for USART_CTLR1 register  *******************/
+#define USART_CTLR1_SBK                         ((uint16_t)0x0001) /* Send Break */
+#define USART_CTLR1_RWU                         ((uint16_t)0x0002) /* Receiver wakeup */
+#define USART_CTLR1_RE                          ((uint16_t)0x0004) /* Receiver Enable */
+#define USART_CTLR1_TE                          ((uint16_t)0x0008) /* Transmitter Enable */
+#define USART_CTLR1_IDLEIE                      ((uint16_t)0x0010) /* IDLE Interrupt Enable */
+#define USART_CTLR1_RXNEIE                      ((uint16_t)0x0020) /* RXNE Interrupt Enable */
+#define USART_CTLR1_TCIE                        ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */
+#define USART_CTLR1_TXEIE                       ((uint16_t)0x0080) /* PE Interrupt Enable */
+#define USART_CTLR1_PEIE                        ((uint16_t)0x0100) /* PE Interrupt Enable */
+#define USART_CTLR1_PS                          ((uint16_t)0x0200) /* Parity Selection */
+#define USART_CTLR1_PCE                         ((uint16_t)0x0400) /* Parity Control Enable */
+#define USART_CTLR1_WAKE                        ((uint16_t)0x0800) /* Wakeup method */
+#define USART_CTLR1_M                           ((uint16_t)0x1000) /* Word length */
+#define USART_CTLR1_UE                          ((uint16_t)0x2000) /* USART Enable */
+#define USART_CTLR1_OVER8                       ((uint16_t)0x8000) /* USART Oversmapling 8-bits */
+
+/******************  Bit definition for USART_CTLR2 register  *******************/
+#define USART_CTLR2_ADD                         ((uint16_t)0x000F) /* Address of the USART node */
+#define USART_CTLR2_LBDL                        ((uint16_t)0x0020) /* LIN Break Detection Length */
+#define USART_CTLR2_LBDIE                       ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */
+#define USART_CTLR2_LBCL                        ((uint16_t)0x0100) /* Last Bit Clock pulse */
+#define USART_CTLR2_CPHA                        ((uint16_t)0x0200) /* Clock Phase */
+#define USART_CTLR2_CPOL                        ((uint16_t)0x0400) /* Clock Polarity */
+#define USART_CTLR2_CLKEN                       ((uint16_t)0x0800) /* Clock Enable */
+
+#define USART_CTLR2_STOP                        ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */
+#define USART_CTLR2_STOP_0                      ((uint16_t)0x1000) /* Bit 0 */
+#define USART_CTLR2_STOP_1                      ((uint16_t)0x2000) /* Bit 1 */
+
+#define USART_CTLR2_LINEN                       ((uint16_t)0x4000) /* LIN mode enable */
+
+/******************  Bit definition for USART_CTLR3 register  *******************/
+#define USART_CTLR3_EIE                         ((uint16_t)0x0001) /* Error Interrupt Enable */
+#define USART_CTLR3_IREN                        ((uint16_t)0x0002) /* IrDA mode Enable */
+#define USART_CTLR3_IRLP                        ((uint16_t)0x0004) /* IrDA Low-Power */
+#define USART_CTLR3_HDSEL                       ((uint16_t)0x0008) /* Half-Duplex Selection */
+#define USART_CTLR3_NACK                        ((uint16_t)0x0010) /* Smartcard NACK enable */
+#define USART_CTLR3_SCEN                        ((uint16_t)0x0020) /* Smartcard mode enable */
+#define USART_CTLR3_DMAR                        ((uint16_t)0x0040) /* DMA Enable Receiver */
+#define USART_CTLR3_DMAT                        ((uint16_t)0x0080) /* DMA Enable Transmitter */
+#define USART_CTLR3_RTSE                        ((uint16_t)0x0100) /* RTS Enable */
+#define USART_CTLR3_CTSE                        ((uint16_t)0x0200) /* CTS Enable */
+#define USART_CTLR3_CTSIE                       ((uint16_t)0x0400) /* CTS Interrupt Enable */
+#define USART_CTLR3_ONEBIT                      ((uint16_t)0x0800) /* One Bit method */
+
+/******************  Bit definition for USART_GPR register  ******************/
+#define USART_GPR_PSC                           ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */
+#define USART_GPR_PSC_0                         ((uint16_t)0x0001) /* Bit 0 */
+#define USART_GPR_PSC_1                         ((uint16_t)0x0002) /* Bit 1 */
+#define USART_GPR_PSC_2                         ((uint16_t)0x0004) /* Bit 2 */
+#define USART_GPR_PSC_3                         ((uint16_t)0x0008) /* Bit 3 */
+#define USART_GPR_PSC_4                         ((uint16_t)0x0010) /* Bit 4 */
+#define USART_GPR_PSC_5                         ((uint16_t)0x0020) /* Bit 5 */
+#define USART_GPR_PSC_6                         ((uint16_t)0x0040) /* Bit 6 */
+#define USART_GPR_PSC_7                         ((uint16_t)0x0080) /* Bit 7 */
+
+#define USART_GPR_GT                            ((uint16_t)0xFF00) /* Guard time value */
+
+/******************************************************************************/
+/*                            Window WATCHDOG                                 */
+/******************************************************************************/
+
+/*******************  Bit definition for WWDG_CTLR register  ********************/
+#define WWDG_CTLR_T                             ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
+#define WWDG_CTLR_T0                            ((uint8_t)0x01) /* Bit 0 */
+#define WWDG_CTLR_T1                            ((uint8_t)0x02) /* Bit 1 */
+#define WWDG_CTLR_T2                            ((uint8_t)0x04) /* Bit 2 */
+#define WWDG_CTLR_T3                            ((uint8_t)0x08) /* Bit 3 */
+#define WWDG_CTLR_T4                            ((uint8_t)0x10) /* Bit 4 */
+#define WWDG_CTLR_T5                            ((uint8_t)0x20) /* Bit 5 */
+#define WWDG_CTLR_T6                            ((uint8_t)0x40) /* Bit 6 */
+
+#define WWDG_CTLR_WDGA                          ((uint8_t)0x80) /* Activation bit */
+
+/*******************  Bit definition for WWDG_CFGR register  *******************/
+#define WWDG_CFGR_W                             ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */
+#define WWDG_CFGR_W0                            ((uint16_t)0x0001) /* Bit 0 */
+#define WWDG_CFGR_W1                            ((uint16_t)0x0002) /* Bit 1 */
+#define WWDG_CFGR_W2                            ((uint16_t)0x0004) /* Bit 2 */
+#define WWDG_CFGR_W3                            ((uint16_t)0x0008) /* Bit 3 */
+#define WWDG_CFGR_W4                            ((uint16_t)0x0010) /* Bit 4 */
+#define WWDG_CFGR_W5                            ((uint16_t)0x0020) /* Bit 5 */
+#define WWDG_CFGR_W6                            ((uint16_t)0x0040) /* Bit 6 */
+
+#define WWDG_CFGR_WDGTB                         ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */
+#define WWDG_CFGR_WDGTB0                        ((uint16_t)0x0080) /* Bit 0 */
+#define WWDG_CFGR_WDGTB1                        ((uint16_t)0x0100) /* Bit 1 */
+
+#define WWDG_CFGR_EWI                           ((uint16_t)0x0200) /* Early Wakeup Interrupt */
+
+/*******************  Bit definition for WWDG_STATR register  ********************/
+#define WWDG_STATR_EWIF                         ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */
+
+/******************************************************************************/
+/*                          ENHANCED FUNNCTION                                */
+/******************************************************************************/
+
+/****************************  Enhanced register  *****************************/
+#define EXTEN_USBD_LS                           ((uint32_t)0x00000001) /* Bit 0 */
+#define EXTEN_USBD_PU_EN                        ((uint32_t)0x00000002) /* Bit 1 */
+#define EXTEN_USBHD_IO_EN                       ((uint32_t)0x00000004) /* Bit 2 */
+#define EXTEN_USB_5V_SEL                        ((uint32_t)0x00000008) /* Bit 3 */
+#define EXTEN_PLL_HSI_PRE                       ((uint32_t)0x00000010) /* Bit 4 */
+#define EXTEN_LOCKUP_EN                         ((uint32_t)0x00000040) /* Bit 5 */
+#define EXTEN_LOCKUP_RSTF                       ((uint32_t)0x00000080) /* Bit 7 */
+
+#define EXTEN_ULLDO_TRIM                        ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */
+#define EXTEN_ULLDO_TRIM0                       ((uint32_t)0x00000100) /* Bit 0 */
+#define EXTEN_ULLDO_TRIM1                       ((uint32_t)0x00000200) /* Bit 1 */
+
+#define EXTEN_IDO_TRIM                          ((uint32_t)0x00000400) /* Bit 10 */
+#define EXTEN_WRITE_EN                          ((uint32_t)0x00004000) /* Bit 14 */
+#define EXTEN_SHORT_WAKE                        ((uint32_t)0x00008000) /* Bit 15 */
+
+#define EXTEN_FLASH_CLK_TRIM                    ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */
+#define EXTEN_FLASH_CLK_TRIM0                   ((uint32_t)0x00010000) /* Bit 0 */
+#define EXTEN_FLASH_CLK_TRIM1                   ((uint32_t)0x00020000) /* Bit 1 */
+#define EXTEN_FLASH_CLK_TRIM2                   ((uint32_t)0x00040000) /* Bit 2 */
+
+#include "ch32v10x_conf.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_adc.h

@@ -0,0 +1,188 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_adc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      ADC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_ADC_H
+#define __CH32V10x_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* ADC Init structure definition */
+typedef struct
+{
+    uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
+                          dual mode.
+                          This parameter can be a value of @ref ADC_mode */
+
+    FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
+                                         Scan (multichannels) or Single (one channel) mode.
+                                         This parameter can be set to ENABLE or DISABLE */
+
+    FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
+                                               Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+
+    uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
+                                      to digital conversion of regular channels. This parameter
+                                      can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
+
+    uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
+                               This parameter can be a value of @ref ADC_data_align */
+
+    uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
+                                   using the sequencer for regular channel group.
+                                   This parameter must range from 1 to 16. */
+} ADC_InitTypeDef;
+
+/* ADC_mode */
+#define ADC_Mode_Independent                           ((uint32_t)0x00000000)
+#define ADC_Mode_RegInjecSimult                        ((uint32_t)0x00010000)
+#define ADC_Mode_RegSimult_AlterTrig                   ((uint32_t)0x00020000)
+#define ADC_Mode_InjecSimult_FastInterl                ((uint32_t)0x00030000)
+#define ADC_Mode_InjecSimult_SlowInterl                ((uint32_t)0x00040000)
+#define ADC_Mode_InjecSimult                           ((uint32_t)0x00050000)
+#define ADC_Mode_RegSimult                             ((uint32_t)0x00060000)
+#define ADC_Mode_FastInterl                            ((uint32_t)0x00070000)
+#define ADC_Mode_SlowInterl                            ((uint32_t)0x00080000)
+#define ADC_Mode_AlterTrig                             ((uint32_t)0x00090000)
+
+/* ADC_external_trigger_sources_for_regular_channels_conversion */
+#define ADC_ExternalTrigConv_T1_CC1                    ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2                    ((uint32_t)0x00020000)
+#define ADC_ExternalTrigConv_T2_CC2                    ((uint32_t)0x00060000)
+#define ADC_ExternalTrigConv_T3_TRGO                   ((uint32_t)0x00080000)
+#define ADC_ExternalTrigConv_T4_CC4                    ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO        ((uint32_t)0x000C0000)
+
+#define ADC_ExternalTrigConv_T1_CC3                    ((uint32_t)0x00040000)
+#define ADC_ExternalTrigConv_None                      ((uint32_t)0x000E0000)
+
+/* ADC_data_align */
+#define ADC_DataAlign_Right                            ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                             ((uint32_t)0x00000800)
+
+/* ADC_channels */
+#define ADC_Channel_0                                  ((uint8_t)0x00)
+#define ADC_Channel_1                                  ((uint8_t)0x01)
+#define ADC_Channel_2                                  ((uint8_t)0x02)
+#define ADC_Channel_3                                  ((uint8_t)0x03)
+#define ADC_Channel_4                                  ((uint8_t)0x04)
+#define ADC_Channel_5                                  ((uint8_t)0x05)
+#define ADC_Channel_6                                  ((uint8_t)0x06)
+#define ADC_Channel_7                                  ((uint8_t)0x07)
+#define ADC_Channel_8                                  ((uint8_t)0x08)
+#define ADC_Channel_9                                  ((uint8_t)0x09)
+#define ADC_Channel_10                                 ((uint8_t)0x0A)
+#define ADC_Channel_11                                 ((uint8_t)0x0B)
+#define ADC_Channel_12                                 ((uint8_t)0x0C)
+#define ADC_Channel_13                                 ((uint8_t)0x0D)
+#define ADC_Channel_14                                 ((uint8_t)0x0E)
+#define ADC_Channel_15                                 ((uint8_t)0x0F)
+#define ADC_Channel_16                                 ((uint8_t)0x10)
+#define ADC_Channel_17                                 ((uint8_t)0x11)
+
+#define ADC_Channel_TempSensor                         ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                            ((uint8_t)ADC_Channel_17)
+
+/* ADC_sampling_time */
+#define ADC_SampleTime_1Cycles5                        ((uint8_t)0x00)
+#define ADC_SampleTime_7Cycles5                        ((uint8_t)0x01)
+#define ADC_SampleTime_13Cycles5                       ((uint8_t)0x02)
+#define ADC_SampleTime_28Cycles5                       ((uint8_t)0x03)
+#define ADC_SampleTime_41Cycles5                       ((uint8_t)0x04)
+#define ADC_SampleTime_55Cycles5                       ((uint8_t)0x05)
+#define ADC_SampleTime_71Cycles5                       ((uint8_t)0x06)
+#define ADC_SampleTime_239Cycles5                      ((uint8_t)0x07)
+
+/* ADC_external_trigger_sources_for_injected_channels_conversion */
+#define ADC_ExternalTrigInjecConv_T2_TRGO              ((uint32_t)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC1               ((uint32_t)0x00003000)
+#define ADC_ExternalTrigInjecConv_T3_CC4               ((uint32_t)0x00004000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO              ((uint32_t)0x00005000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4    ((uint32_t)0x00006000)
+
+#define ADC_ExternalTrigInjecConv_T1_TRGO              ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4               ((uint32_t)0x00001000)
+#define ADC_ExternalTrigInjecConv_None                 ((uint32_t)0x00007000)
+
+/* ADC_injected_channel_selection */
+#define ADC_InjectedChannel_1                          ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                          ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                          ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                          ((uint8_t)0x20)
+
+/* ADC_analog_watchdog_selection */
+#define ADC_AnalogWatchdog_SingleRegEnable             ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable           ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable      ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable                ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable              ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable        ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                        ((uint32_t)0x00000000)
+
+/* ADC_interrupts_definition */
+#define ADC_IT_EOC                                     ((uint16_t)0x0220)
+#define ADC_IT_AWD                                     ((uint16_t)0x0140)
+#define ADC_IT_JEOC                                    ((uint16_t)0x0480)
+
+/* ADC_flags_definition */
+#define ADC_FLAG_AWD                                   ((uint8_t)0x01)
+#define ADC_FLAG_EOC                                   ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                                  ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                                 ((uint8_t)0x08)
+#define ADC_FLAG_STRT                                  ((uint8_t)0x10)
+
+void       ADC_DeInit(ADC_TypeDef *ADCx);
+void       ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
+void       ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
+void       ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
+void       ADC_ResetCalibration(ADC_TypeDef *ADCx);
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
+void       ADC_StartCalibration(ADC_TypeDef *ADCx);
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
+void       ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
+void       ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
+void       ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void       ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+uint16_t   ADC_GetConversionValue(ADC_TypeDef *ADCx);
+uint32_t   ADC_GetDualModeConversionValue(void);
+void       ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void       ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+void       ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
+void       ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void       ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
+void       ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+uint16_t   ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
+void       ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
+void       ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
+void       ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
+void       ADC_TempSensorVrefintCmd(FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
+void       ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
+ITStatus   ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
+void       ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
+s32        TempSensor_Volt_To_Temper(s32 Value);
+int16_t    Get_CalibrationValue(ADC_TypeDef *ADCx);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_ADC_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_bkp.h

@@ -0,0 +1,91 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_bkp.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      BKP firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_BKP_H
+#define __CH32V10x_BKP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* Tamper_Pin_active_level */
+#define BKP_TamperPinLevel_High           ((uint16_t)0x0000)
+#define BKP_TamperPinLevel_Low            ((uint16_t)0x0001)
+
+/* RTC_output_source_to_output_on_the_Tamper_pin */
+#define BKP_RTCOutputSource_None          ((uint16_t)0x0000)
+#define BKP_RTCOutputSource_CalibClock    ((uint16_t)0x0080)
+#define BKP_RTCOutputSource_Alarm         ((uint16_t)0x0100)
+#define BKP_RTCOutputSource_Second        ((uint16_t)0x0300)
+
+/* Data_Backup_Register */
+#define BKP_DR1                           ((uint16_t)0x0004)
+#define BKP_DR2                           ((uint16_t)0x0008)
+#define BKP_DR3                           ((uint16_t)0x000C)
+#define BKP_DR4                           ((uint16_t)0x0010)
+#define BKP_DR5                           ((uint16_t)0x0014)
+#define BKP_DR6                           ((uint16_t)0x0018)
+#define BKP_DR7                           ((uint16_t)0x001C)
+#define BKP_DR8                           ((uint16_t)0x0020)
+#define BKP_DR9                           ((uint16_t)0x0024)
+#define BKP_DR10                          ((uint16_t)0x0028)
+#define BKP_DR11                          ((uint16_t)0x0040)
+#define BKP_DR12                          ((uint16_t)0x0044)
+#define BKP_DR13                          ((uint16_t)0x0048)
+#define BKP_DR14                          ((uint16_t)0x004C)
+#define BKP_DR15                          ((uint16_t)0x0050)
+#define BKP_DR16                          ((uint16_t)0x0054)
+#define BKP_DR17                          ((uint16_t)0x0058)
+#define BKP_DR18                          ((uint16_t)0x005C)
+#define BKP_DR19                          ((uint16_t)0x0060)
+#define BKP_DR20                          ((uint16_t)0x0064)
+#define BKP_DR21                          ((uint16_t)0x0068)
+#define BKP_DR22                          ((uint16_t)0x006C)
+#define BKP_DR23                          ((uint16_t)0x0070)
+#define BKP_DR24                          ((uint16_t)0x0074)
+#define BKP_DR25                          ((uint16_t)0x0078)
+#define BKP_DR26                          ((uint16_t)0x007C)
+#define BKP_DR27                          ((uint16_t)0x0080)
+#define BKP_DR28                          ((uint16_t)0x0084)
+#define BKP_DR29                          ((uint16_t)0x0088)
+#define BKP_DR30                          ((uint16_t)0x008C)
+#define BKP_DR31                          ((uint16_t)0x0090)
+#define BKP_DR32                          ((uint16_t)0x0094)
+#define BKP_DR33                          ((uint16_t)0x0098)
+#define BKP_DR34                          ((uint16_t)0x009C)
+#define BKP_DR35                          ((uint16_t)0x00A0)
+#define BKP_DR36                          ((uint16_t)0x00A4)
+#define BKP_DR37                          ((uint16_t)0x00A8)
+#define BKP_DR38                          ((uint16_t)0x00AC)
+#define BKP_DR39                          ((uint16_t)0x00B0)
+#define BKP_DR40                          ((uint16_t)0x00B4)
+#define BKP_DR41                          ((uint16_t)0x00B8)
+#define BKP_DR42                          ((uint16_t)0x00BC)
+
+void       BKP_DeInit(void);
+void       BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
+void       BKP_TamperPinCmd(FunctionalState NewState);
+void       BKP_ITConfig(FunctionalState NewState);
+void       BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
+void       BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
+void       BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
+uint16_t   BKP_ReadBackupRegister(uint16_t BKP_DR);
+FlagStatus BKP_GetFlagStatus(void);
+void       BKP_ClearFlag(void);
+ITStatus   BKP_GetITStatus(void);
+void       BKP_ClearITPendingBit(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_BKP_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_crc.h

@@ -0,0 +1,31 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_crc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      CRC firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_CRC_H
+#define __CH32V10x_CRC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+void     CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void     CRC_SetIDRegister(uint8_t IDValue);
+uint8_t  CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_CRC_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_dbgmcu.h

@@ -0,0 +1,41 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_dbgmcu.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      DBGMCU firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_DBGMCU_H
+#define __CH32V10x_DBGMCU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* CFGR0 Register */
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00000004)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00000008)
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000010)
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000020)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000040)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000080)
+
+/* CFGR1 Register */
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_DBGMCU_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_dma.h

@@ -0,0 +1,216 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_dma.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      DMA firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_DMA_H
+#define __CH32V10x_DMA_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* DMA Init structure definition */
+typedef struct
+{
+    uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
+
+    uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
+
+    uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
+                         This parameter can be a value of @ref DMA_data_transfer_direction */
+
+    uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
+                                The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                or DMA_MemoryDataSize members depending in the transfer direction. */
+
+    uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
+                                   This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+    uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
+                               This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+    uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+    uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
+                                    This parameter can be a value of @ref DMA_memory_data_size */
+
+    uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
+                          This parameter can be a value of @ref DMA_circular_normal_mode.
+                          @note: The circular buffer mode cannot be used if the memory-to-memory
+                                data transfer is configured on the selected Channel */
+
+    uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
+                              This parameter can be a value of @ref DMA_priority_level */
+
+    uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+                         This parameter can be a value of @ref DMA_memory_to_memory */
+} DMA_InitTypeDef;
+
+/* DMA_data_transfer_direction */
+#define DMA_DIR_PeripheralDST              ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_incremented_mode */
+#define DMA_PeripheralInc_Enable           ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable          ((uint32_t)0x00000000)
+
+/* DMA_memory_incremented_mode */
+#define DMA_MemoryInc_Enable               ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable              ((uint32_t)0x00000000)
+
+/* DMA_peripheral_data_size */
+#define DMA_PeripheralDataSize_Byte        ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord    ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word        ((uint32_t)0x00000200)
+
+/* DMA_memory_data_size */
+#define DMA_MemoryDataSize_Byte            ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord        ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word            ((uint32_t)0x00000800)
+
+/* DMA_circular_normal_mode */
+#define DMA_Mode_Circular                  ((uint32_t)0x00000020)
+#define DMA_Mode_Normal                    ((uint32_t)0x00000000)
+
+/* DMA_priority_level */
+#define DMA_Priority_VeryHigh              ((uint32_t)0x00003000)
+#define DMA_Priority_High                  ((uint32_t)0x00002000)
+#define DMA_Priority_Medium                ((uint32_t)0x00001000)
+#define DMA_Priority_Low                   ((uint32_t)0x00000000)
+
+/* DMA_memory_to_memory */
+#define DMA_M2M_Enable                     ((uint32_t)0x00004000)
+#define DMA_M2M_Disable                    ((uint32_t)0x00000000)
+
+/* DMA_interrupts_definition */
+#define DMA_IT_TC                          ((uint32_t)0x00000002)
+#define DMA_IT_HT                          ((uint32_t)0x00000004)
+#define DMA_IT_TE                          ((uint32_t)0x00000008)
+
+#define DMA1_IT_GL1                        ((uint32_t)0x00000001)
+#define DMA1_IT_TC1                        ((uint32_t)0x00000002)
+#define DMA1_IT_HT1                        ((uint32_t)0x00000004)
+#define DMA1_IT_TE1                        ((uint32_t)0x00000008)
+#define DMA1_IT_GL2                        ((uint32_t)0x00000010)
+#define DMA1_IT_TC2                        ((uint32_t)0x00000020)
+#define DMA1_IT_HT2                        ((uint32_t)0x00000040)
+#define DMA1_IT_TE2                        ((uint32_t)0x00000080)
+#define DMA1_IT_GL3                        ((uint32_t)0x00000100)
+#define DMA1_IT_TC3                        ((uint32_t)0x00000200)
+#define DMA1_IT_HT3                        ((uint32_t)0x00000400)
+#define DMA1_IT_TE3                        ((uint32_t)0x00000800)
+#define DMA1_IT_GL4                        ((uint32_t)0x00001000)
+#define DMA1_IT_TC4                        ((uint32_t)0x00002000)
+#define DMA1_IT_HT4                        ((uint32_t)0x00004000)
+#define DMA1_IT_TE4                        ((uint32_t)0x00008000)
+#define DMA1_IT_GL5                        ((uint32_t)0x00010000)
+#define DMA1_IT_TC5                        ((uint32_t)0x00020000)
+#define DMA1_IT_HT5                        ((uint32_t)0x00040000)
+#define DMA1_IT_TE5                        ((uint32_t)0x00080000)
+#define DMA1_IT_GL6                        ((uint32_t)0x00100000)
+#define DMA1_IT_TC6                        ((uint32_t)0x00200000)
+#define DMA1_IT_HT6                        ((uint32_t)0x00400000)
+#define DMA1_IT_TE6                        ((uint32_t)0x00800000)
+#define DMA1_IT_GL7                        ((uint32_t)0x01000000)
+#define DMA1_IT_TC7                        ((uint32_t)0x02000000)
+#define DMA1_IT_HT7                        ((uint32_t)0x04000000)
+#define DMA1_IT_TE7                        ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1                        ((uint32_t)0x10000001)
+#define DMA2_IT_TC1                        ((uint32_t)0x10000002)
+#define DMA2_IT_HT1                        ((uint32_t)0x10000004)
+#define DMA2_IT_TE1                        ((uint32_t)0x10000008)
+#define DMA2_IT_GL2                        ((uint32_t)0x10000010)
+#define DMA2_IT_TC2                        ((uint32_t)0x10000020)
+#define DMA2_IT_HT2                        ((uint32_t)0x10000040)
+#define DMA2_IT_TE2                        ((uint32_t)0x10000080)
+#define DMA2_IT_GL3                        ((uint32_t)0x10000100)
+#define DMA2_IT_TC3                        ((uint32_t)0x10000200)
+#define DMA2_IT_HT3                        ((uint32_t)0x10000400)
+#define DMA2_IT_TE3                        ((uint32_t)0x10000800)
+#define DMA2_IT_GL4                        ((uint32_t)0x10001000)
+#define DMA2_IT_TC4                        ((uint32_t)0x10002000)
+#define DMA2_IT_HT4                        ((uint32_t)0x10004000)
+#define DMA2_IT_TE4                        ((uint32_t)0x10008000)
+#define DMA2_IT_GL5                        ((uint32_t)0x10010000)
+#define DMA2_IT_TC5                        ((uint32_t)0x10020000)
+#define DMA2_IT_HT5                        ((uint32_t)0x10040000)
+#define DMA2_IT_TE5                        ((uint32_t)0x10080000)
+
+/* DMA_flags_definition */
+#define DMA1_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7                      ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1                      ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1                      ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1                      ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1                      ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2                      ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2                      ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2                      ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2                      ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3                      ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3                      ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3                      ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3                      ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4                      ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4                      ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4                      ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4                      ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5                      ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5                      ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5                      ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5                      ((uint32_t)0x10080000)
+
+void       DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
+void       DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
+void       DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
+void       DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
+void       DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+void       DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
+uint16_t   DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void       DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus   DMA_GetITStatus(uint32_t DMAy_IT);
+void       DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_DMA_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_exti.h

@@ -0,0 +1,86 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_exti.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      EXTI firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_EXTI_H
+#define __CH32V10x_EXTI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* EXTI mode enumeration */
+typedef enum
+{
+    EXTI_Mode_Interrupt = 0x00,
+    EXTI_Mode_Event = 0x04
+} EXTIMode_TypeDef;
+
+/* EXTI Trigger enumeration */
+typedef enum
+{
+    EXTI_Trigger_Rising = 0x08,
+    EXTI_Trigger_Falling = 0x0C,
+    EXTI_Trigger_Rising_Falling = 0x10
+} EXTITrigger_TypeDef;
+
+/* EXTI Init Structure definition */
+typedef struct
+{
+    uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
+                           This parameter can be any combination of @ref EXTI_Lines */
+
+    EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
+                                   This parameter can be a value of @ref EXTIMode_TypeDef */
+
+    EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+    FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
+                                     This parameter can be set either to ENABLE or DISABLE */
+} EXTI_InitTypeDef;
+
+/* EXTI_Lines */
+#define EXTI_Line0     ((uint32_t)0x00001) /* External interrupt line 0 */
+#define EXTI_Line1     ((uint32_t)0x00002) /* External interrupt line 1 */
+#define EXTI_Line2     ((uint32_t)0x00004) /* External interrupt line 2 */
+#define EXTI_Line3     ((uint32_t)0x00008) /* External interrupt line 3 */
+#define EXTI_Line4     ((uint32_t)0x00010) /* External interrupt line 4 */
+#define EXTI_Line5     ((uint32_t)0x00020) /* External interrupt line 5 */
+#define EXTI_Line6     ((uint32_t)0x00040) /* External interrupt line 6 */
+#define EXTI_Line7     ((uint32_t)0x00080) /* External interrupt line 7 */
+#define EXTI_Line8     ((uint32_t)0x00100) /* External interrupt line 8 */
+#define EXTI_Line9     ((uint32_t)0x00200) /* External interrupt line 9 */
+#define EXTI_Line10    ((uint32_t)0x00400) /* External interrupt line 10 */
+#define EXTI_Line11    ((uint32_t)0x00800) /* External interrupt line 11 */
+#define EXTI_Line12    ((uint32_t)0x01000) /* External interrupt line 12 */
+#define EXTI_Line13    ((uint32_t)0x02000) /* External interrupt line 13 */
+#define EXTI_Line14    ((uint32_t)0x04000) /* External interrupt line 14 */
+#define EXTI_Line15    ((uint32_t)0x08000) /* External interrupt line 15 */
+#define EXTI_Line16    ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17    ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18    ((uint32_t)0x40000)
+#define EXTI_Line19    ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBHD Wakeup event */
+
+void       EXTI_DeInit(void);
+void       EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
+void       EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
+void       EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void       EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus   EXTI_GetITStatus(uint32_t EXTI_Line);
+void       EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_EXTI_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_flash.h

@@ -0,0 +1,155 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_flash.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the FLASH
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_FLASH_H
+#define __CH32V10x_FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* FLASH Status */
+typedef enum
+{
+    FLASH_BUSY = 1,
+    FLASH_ERROR_PG,
+    FLASH_ERROR_WRP,
+    FLASH_COMPLETE,
+    FLASH_TIMEOUT
+} FLASH_Status;
+
+/* Flash_Latency */
+#define FLASH_Latency_0                  ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
+#define FLASH_Latency_1                  ((uint32_t)0x00000001) /* FLASH One Latency cycle */
+#define FLASH_Latency_2                  ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
+
+/* Half_Cycle_Enable_Disable */
+#define FLASH_HalfCycleAccess_Enable     ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable    ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */
+
+/* Prefetch_Buffer_Enable_Disable */
+#define FLASH_PrefetchBuffer_Enable      ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable     ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */
+
+/* Values to be used with CH32V10x Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3           ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7           ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11          ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15         ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19         ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23         ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27         ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31         ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with CH32V10x Medium-density devices */
+#define FLASH_WRProt_Pages32to35         ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39         ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43         ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47         ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51         ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55         ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59         ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63         ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67         ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71         ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75         ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79         ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83         ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87         ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91         ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95         ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99         ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103       ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107       ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111       ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115       ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119       ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123       ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127       ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */
+
+#define FLASH_WRProt_Pages62to255        ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllPages            ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
+
+/* Option_Bytes_IWatchdog */
+#define OB_IWDG_SW                       ((uint16_t)0x0001) /* Software IWDG selected */
+#define OB_IWDG_HW                       ((uint16_t)0x0000) /* Hardware IWDG selected */
+
+/* Option_Bytes_nRST_STOP */
+#define OB_STOP_NoRST                    ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST                      ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+
+/* Option_Bytes_nRST_STDBY  */
+#define OB_STDBY_NoRST                   ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                     ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+
+/* FLASH_Interrupts */
+#define FLASH_IT_ERROR                   ((uint32_t)0x00000400) /* FPEC error interrupt source */
+#define FLASH_IT_EOP                     ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR             FLASH_IT_ERROR         /* FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP               FLASH_IT_EOP           /* End of FLASH BANK1 Operation Interrupt source */
+
+/* FLASH_Flags */
+#define FLASH_FLAG_BSY                   ((uint32_t)0x00000001) /* FLASH Busy flag */
+#define FLASH_FLAG_EOP                   ((uint32_t)0x00000020) /* FLASH End of Operation flag */
+#define FLASH_FLAG_PGERR                 ((uint32_t)0x00000004) /* FLASH Program error flag */
+#define FLASH_FLAG_WRPRTERR              ((uint32_t)0x00000010) /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR                ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY             FLASH_FLAG_BSY       /* FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP             FLASH_FLAG_EOP       /* FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_PGERR           FLASH_FLAG_PGERR     /* FLASH BANK1 Program error flag */
+#define FLASH_FLAG_BANK1_WRPRTERR        FLASH_FLAG_WRPRTERR  /* FLASH BANK1 Write protected error flag */
+
+/*Functions used for all CH32V10x devices*/
+void         FLASH_SetLatency(uint32_t FLASH_Latency);
+void         FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+void         FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer);
+void         FLASH_Unlock(void);
+void         FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_EraseOptionBytes(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages);
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
+uint32_t     FLASH_GetUserOptionByte(void);
+uint32_t     FLASH_GetWriteProtectionOptionByte(void);
+FlagStatus   FLASH_GetReadOutProtectionStatus(void);
+FlagStatus   FLASH_GetPrefetchBufferStatus(void);
+void         FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus   FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void         FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+void         FLASH_Unlock_Fast(void);
+void         FLASH_Lock_Fast(void);
+void         FLASH_BufReset(void);
+void         FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3);
+void         FLASH_ErasePage_Fast(uint32_t Page_Address);
+void         FLASH_ProgramPage_Fast(uint32_t Page_Address);
+
+/* New function used for all CH32V10x devices */
+void         FLASH_UnlockBank1(void);
+void         FLASH_LockBank1(void);
+FLASH_Status FLASH_EraseAllBank1Pages(void);
+FLASH_Status FLASH_GetBank1Status(void);
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_FLASH_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_gpio.h

@@ -0,0 +1,160 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_gpio.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      GPIO firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_GPIO_H
+#define __CH32V10x_GPIO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* Output Maximum frequency selection */
+typedef enum
+{
+    GPIO_Speed_10MHz = 1,
+    GPIO_Speed_2MHz,
+    GPIO_Speed_50MHz
+} GPIOSpeed_TypeDef;
+
+/* Configuration Mode enumeration */
+typedef enum
+{
+    GPIO_Mode_AIN = 0x0,
+    GPIO_Mode_IN_FLOATING = 0x04,
+    GPIO_Mode_IPD = 0x28,
+    GPIO_Mode_IPU = 0x48,
+    GPIO_Mode_Out_OD = 0x14,
+    GPIO_Mode_Out_PP = 0x10,
+    GPIO_Mode_AF_OD = 0x1C,
+    GPIO_Mode_AF_PP = 0x18
+} GPIOMode_TypeDef;
+
+/* GPIO Init structure definition */
+typedef struct
+{
+    uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
+                          This parameter can be any value of @ref GPIO_pins_define */
+
+    GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
+                                     This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+    GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
+                                   This parameter can be a value of @ref GPIOMode_TypeDef */
+} GPIO_InitTypeDef;
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+    Bit_RESET = 0,
+    Bit_SET
+} BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0                     ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_Pin_1                     ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_Pin_2                     ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_Pin_3                     ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_Pin_4                     ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_Pin_5                     ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_Pin_6                     ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_Pin_7                     ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_Pin_8                     ((uint16_t)0x0100) /* Pin 8 selected */
+#define GPIO_Pin_9                     ((uint16_t)0x0200) /* Pin 9 selected */
+#define GPIO_Pin_10                    ((uint16_t)0x0400) /* Pin 10 selected */
+#define GPIO_Pin_11                    ((uint16_t)0x0800) /* Pin 11 selected */
+#define GPIO_Pin_12                    ((uint16_t)0x1000) /* Pin 12 selected */
+#define GPIO_Pin_13                    ((uint16_t)0x2000) /* Pin 13 selected */
+#define GPIO_Pin_14                    ((uint16_t)0x4000) /* Pin 14 selected */
+#define GPIO_Pin_15                    ((uint16_t)0x8000) /* Pin 15 selected */
+#define GPIO_Pin_All                   ((uint16_t)0xFFFF) /* All pins selected */
+
+/* GPIO_Remap_define */
+#define GPIO_Remap_SPI1                ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1                ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1              ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2              ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3       ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3          ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1         ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1            ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2        ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2        ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2            ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3         ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3            ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4                ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1               ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1               ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01                ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
+#define GPIO_Remap_ADC1_ETRGINJ        ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG        ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_NoJTRST         ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */
+#define GPIO_Remap_SWJ_JTAGDisable     ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */
+#define GPIO_Remap_SWJ_Disable         ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF    ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
+                                                                 to TIM2 Internal Trigger 1 for calibration                    \
+                                                                 (only for Connectivity line devices) */
+#define GPIO_Remap_TIM1_DMA            ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */
+#define GPIO_Remap_TIM67_DAC_DMA       ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
+#define GPIO_Remap_MISC                ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \
+                                                                   only for High density Value line devices) */
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA           ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOB           ((uint8_t)0x01)
+#define GPIO_PortSourceGPIOC           ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD           ((uint8_t)0x03)
+#define GPIO_PortSourceGPIOE           ((uint8_t)0x04)
+#define GPIO_PortSourceGPIOF           ((uint8_t)0x05)
+#define GPIO_PortSourceGPIOG           ((uint8_t)0x06)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0                ((uint8_t)0x00)
+#define GPIO_PinSource1                ((uint8_t)0x01)
+#define GPIO_PinSource2                ((uint8_t)0x02)
+#define GPIO_PinSource3                ((uint8_t)0x03)
+#define GPIO_PinSource4                ((uint8_t)0x04)
+#define GPIO_PinSource5                ((uint8_t)0x05)
+#define GPIO_PinSource6                ((uint8_t)0x06)
+#define GPIO_PinSource7                ((uint8_t)0x07)
+#define GPIO_PinSource8                ((uint8_t)0x08)
+#define GPIO_PinSource9                ((uint8_t)0x09)
+#define GPIO_PinSource10               ((uint8_t)0x0A)
+#define GPIO_PinSource11               ((uint8_t)0x0B)
+#define GPIO_PinSource12               ((uint8_t)0x0C)
+#define GPIO_PinSource13               ((uint8_t)0x0D)
+#define GPIO_PinSource14               ((uint8_t)0x0E)
+#define GPIO_PinSource15               ((uint8_t)0x0F)
+
+void     GPIO_DeInit(GPIO_TypeDef *GPIOx);
+void     GPIO_AFIODeInit(void);
+void     GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
+void     GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
+uint8_t  GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
+uint8_t  GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
+void     GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void     GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void     GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void     GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
+void     GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
+void     GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+void     GPIO_EventOutputCmd(FunctionalState NewState);
+void     GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
+void     GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_GPIO_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_i2c.h

@@ -0,0 +1,199 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_i2c.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      I2C firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_I2C_H
+#define __CH32V10x_I2C_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* I2C Init structure definition  */
+typedef struct
+{
+    uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
+                                This parameter must be set to a value lower than 400kHz */
+
+    uint16_t I2C_Mode; /* Specifies the I2C mode.
+                          This parameter can be a value of @ref I2C_mode */
+
+    uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
+                               This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+    uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
+                                 This parameter can be a 7-bit or 10-bit address. */
+
+    uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
+                         This parameter can be a value of @ref I2C_acknowledgement */
+
+    uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+} I2C_InitTypeDef;
+
+/* I2C_mode */
+#define I2C_Mode_I2C                                         ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice                                 ((uint16_t)0x0002)
+#define I2C_Mode_SMBusHost                                   ((uint16_t)0x000A)
+
+/* I2C_duty_cycle_in_fast_mode */
+#define I2C_DutyCycle_16_9                                   ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                                      ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
+
+/* I2C_acknowledgement */
+#define I2C_Ack_Enable                                       ((uint16_t)0x0400)
+#define I2C_Ack_Disable                                      ((uint16_t)0x0000)
+
+/* I2C_transfer_direction */
+#define I2C_Direction_Transmitter                            ((uint8_t)0x00)
+#define I2C_Direction_Receiver                               ((uint8_t)0x01)
+
+/* I2C_acknowledged_address */
+#define I2C_AcknowledgedAddress_7bit                         ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit                        ((uint16_t)0xC000)
+
+/* I2C_registers */
+#define I2C_Register_CTLR1                                   ((uint8_t)0x00)
+#define I2C_Register_CTLR2                                   ((uint8_t)0x04)
+#define I2C_Register_OADDR1                                  ((uint8_t)0x08)
+#define I2C_Register_OADDR2                                  ((uint8_t)0x0C)
+#define I2C_Register_DATAR                                   ((uint8_t)0x10)
+#define I2C_Register_STAR1                                   ((uint8_t)0x14)
+#define I2C_Register_STAR2                                   ((uint8_t)0x18)
+#define I2C_Register_CKCFGR                                  ((uint8_t)0x1C)
+#define I2C_Register_RTR                                     ((uint8_t)0x20)
+
+/* I2C_SMBus_alert_pin_level */
+#define I2C_SMBusAlert_Low                                   ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High                                  ((uint16_t)0xDFFF)
+
+/* I2C_PEC_position */
+#define I2C_PECPosition_Next                                 ((uint16_t)0x0800)
+#define I2C_PECPosition_Current                              ((uint16_t)0xF7FF)
+
+/* I2C_NACK_position */
+#define I2C_NACKPosition_Next                                ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current                             ((uint16_t)0xF7FF)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_BUF                                           ((uint16_t)0x0400)
+#define I2C_IT_EVT                                           ((uint16_t)0x0200)
+#define I2C_IT_ERR                                           ((uint16_t)0x0100)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_SMBALERT                                      ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                                       ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                                        ((uint32_t)0x01001000)
+#define I2C_IT_OVR                                           ((uint32_t)0x01000800)
+#define I2C_IT_AF                                            ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                                          ((uint32_t)0x01000200)
+#define I2C_IT_BERR                                          ((uint32_t)0x01000100)
+#define I2C_IT_TXE                                           ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                                          ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                                         ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                                         ((uint32_t)0x02000008)
+#define I2C_IT_BTF                                           ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                                          ((uint32_t)0x02000002)
+#define I2C_IT_SB                                            ((uint32_t)0x02000001)
+
+/* SR2 register flags  */
+#define I2C_FLAG_DUALF                                       ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                                     ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT                                  ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                                     ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                                         ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                                        ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                                         ((uint32_t)0x00010000)
+
+/* SR1 register flags */
+#define I2C_FLAG_SMBALERT                                    ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                                     ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                                      ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                                         ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                                          ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                                        ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                                        ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                                         ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                                        ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                                       ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                                       ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                                         ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                                        ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                                          ((uint32_t)0x10000001)
+
+/****************I2C Master Events (Events grouped in order of communication)********************/
+
+#define I2C_EVENT_MASTER_MODE_SELECT                         ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED           ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED              ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10                      ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED                       ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                   ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED                    ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/******************I2C Slave Events (Events grouped in order of communication)******************/
+
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED             ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED          ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED       ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED    ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED           ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED                        ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+#define I2C_EVENT_SLAVE_STOP_DETECTED                        ((uint32_t)0x00000010) /* STOPF flag */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED                     ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING                    ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+#define I2C_EVENT_SLAVE_ACK_FAILURE                          ((uint32_t)0x00000400) /* AF flag */
+
+void     I2C_DeInit(I2C_TypeDef *I2Cx);
+void     I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct);
+void     I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct);
+void     I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address);
+void     I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+void     I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data);
+uint8_t  I2C_ReceiveData(I2C_TypeDef *I2Cx);
+void     I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction);
+uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register);
+void     I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition);
+void     I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert);
+void     I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition);
+void     I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState);
+uint8_t  I2C_GetPEC(I2C_TypeDef *I2Cx);
+void     I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState);
+void     I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle);
+
+/****************************************************************************************
+ *                         I2C State Monitoring Functions
+ ****************************************************************************************/
+
+ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT);
+uint32_t    I2C_GetLastEvent(I2C_TypeDef *I2Cx);
+FlagStatus  I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
+
+void     I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
+void     I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_I2C_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_iwdg.h

@@ -0,0 +1,48 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_iwdg.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      IWDG firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_IWDG_H
+#define __CH32V10x_IWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* IWDG_WriteAccess */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+
+/* IWDG_prescaler */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+
+/* IWDG_Flag */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+
+void       IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void       IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void       IWDG_SetReload(uint16_t Reload);
+void       IWDG_ReloadCounter(void);
+void       IWDG_Enable(void);
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_IWDG_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_misc.h

@@ -0,0 +1,46 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_misc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the 
+ *                      miscellaneous firmware library functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/   
+#ifndef __CH32V10X_MISC_H
+#define __CH32V10X_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* NVIC Init Structure definition */	 
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;
+  uint8_t NVIC_IRQChannelPreemptionPriority;
+  uint8_t NVIC_IRQChannelSubPriority;
+  FunctionalState NVIC_IRQChannelCmd;
+} NVIC_InitTypeDef;
+ 
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0           ((uint32_t)0x00)
+#define NVIC_PriorityGroup_1           ((uint32_t)0x01)
+#define NVIC_PriorityGroup_2           ((uint32_t)0x02)
+#define NVIC_PriorityGroup_3           ((uint32_t)0x03)
+#define NVIC_PriorityGroup_4           ((uint32_t)0x04)
+
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_MISC_H */
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_pwr.h

@@ -0,0 +1,57 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_pwr.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the PWR
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_PWR_H
+#define __CH32V10x_PWR_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* PVD_detection_level  */
+#define PWR_PVDLevel_2V2          ((uint32_t)0x00000000)
+#define PWR_PVDLevel_2V3          ((uint32_t)0x00000020)
+#define PWR_PVDLevel_2V4          ((uint32_t)0x00000040)
+#define PWR_PVDLevel_2V5          ((uint32_t)0x00000060)
+#define PWR_PVDLevel_2V6          ((uint32_t)0x00000080)
+#define PWR_PVDLevel_2V7          ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_2V8          ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_2V9          ((uint32_t)0x000000E0)
+
+/* Regulator_state_is_STOP_mode */
+#define PWR_Regulator_ON          ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower    ((uint32_t)0x00000001)
+
+/* STOP_mode_entry */
+#define PWR_STOPEntry_WFI         ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE         ((uint8_t)0x02)
+
+/* PWR_Flag */
+#define PWR_FLAG_WU               ((uint32_t)0x00000001)
+#define PWR_FLAG_SB               ((uint32_t)0x00000002)
+#define PWR_FLAG_PVDO             ((uint32_t)0x00000004)
+
+void       PWR_DeInit(void);
+void       PWR_BackupAccessCmd(FunctionalState NewState);
+void       PWR_PVDCmd(FunctionalState NewState);
+void       PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void       PWR_WakeUpPinCmd(FunctionalState NewState);
+void       PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void       PWR_EnterSTANDBYMode(void);
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void       PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_PWR_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_rcc.h

@@ -0,0 +1,228 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_rcc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the RCC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_RCC_H
+#define __CH32V10x_RCC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* RCC_Exported_Types */
+typedef struct
+{
+    uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
+    uint32_t HCLK_Frequency;   /* returns HCLK clock frequency expressed in Hz */
+    uint32_t PCLK1_Frequency;  /* returns PCLK1 clock frequency expressed in Hz */
+    uint32_t PCLK2_Frequency;  /* returns PCLK2 clock frequency expressed in Hz */
+    uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
+} RCC_ClocksTypeDef;
+
+/* HSE_configuration */
+#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
+#define RCC_HSE_ON                       ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass                   ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_Div2           ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE_Div1           ((uint32_t)0x00010000)
+#define RCC_PLLSource_HSE_Div2           ((uint32_t)0x00030000)
+
+/* PLL_multiplication_factor */
+#define RCC_PLLMul_2                     ((uint32_t)0x00000000)
+#define RCC_PLLMul_3                     ((uint32_t)0x00040000)
+#define RCC_PLLMul_4                     ((uint32_t)0x00080000)
+#define RCC_PLLMul_5                     ((uint32_t)0x000C0000)
+#define RCC_PLLMul_6                     ((uint32_t)0x00100000)
+#define RCC_PLLMul_7                     ((uint32_t)0x00140000)
+#define RCC_PLLMul_8                     ((uint32_t)0x00180000)
+#define RCC_PLLMul_9                     ((uint32_t)0x001C0000)
+#define RCC_PLLMul_10                    ((uint32_t)0x00200000)
+#define RCC_PLLMul_11                    ((uint32_t)0x00240000)
+#define RCC_PLLMul_12                    ((uint32_t)0x00280000)
+#define RCC_PLLMul_13                    ((uint32_t)0x002C0000)
+#define RCC_PLLMul_14                    ((uint32_t)0x00300000)
+#define RCC_PLLMul_15                    ((uint32_t)0x00340000)
+#define RCC_PLLMul_16                    ((uint32_t)0x00380000)
+
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+
+/* APB1_APB2_clock_source */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00000400)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00000500)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00000600)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00000700)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+
+/* USB_Device_clock_source */
+#define RCC_USBCLKSource_PLLCLK_1Div5    ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1     ((uint8_t)0x01)
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2                   ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4                   ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6                   ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8                   ((uint32_t)0x0000C000)
+
+/* LSE_configuration */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+
+/* RTC_clock_source */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div128      ((uint32_t)0x00000300)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1               ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_DMA2               ((uint32_t)0x00000002)
+#define RCC_AHBPeriph_SRAM               ((uint32_t)0x00000004)
+#define RCC_AHBPeriph_FLITF              ((uint32_t)0x00000010)
+#define RCC_AHBPeriph_CRC                ((uint32_t)0x00000040)
+#define RCC_AHBPeriph_FSMC               ((uint32_t)0x00000100)
+#define RCC_AHBPeriph_SDIO               ((uint32_t)0x00000400)
+#define RCC_AHBPeriph_USBHD              ((uint32_t)0x00001000)
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA             ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOB             ((uint32_t)0x00000008)
+#define RCC_APB2Periph_GPIOC             ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD             ((uint32_t)0x00000020)
+#define RCC_APB2Periph_GPIOE             ((uint32_t)0x00000040)
+#define RCC_APB2Periph_GPIOF             ((uint32_t)0x00000080)
+#define RCC_APB2Periph_GPIOG             ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00002000)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15             ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16             ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17             ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00200000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_USB               ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_BKP               ((uint32_t)0x08000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define RCC_APB1Periph_CEC               ((uint32_t)0x40000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock                  ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK                   ((uint8_t)0x04)
+#define RCC_MCO_HSI                      ((uint8_t)0x05)
+#define RCC_MCO_HSE                      ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK_Div2              ((uint8_t)0x07)
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8      ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK           ((uint32_t)0x00000004)
+
+void        RCC_DeInit(void);
+void        RCC_HSEConfig(uint32_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void        RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void        RCC_HSICmd(FunctionalState NewState);
+void        RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
+void        RCC_PLLCmd(FunctionalState NewState);
+void        RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t     RCC_GetSYSCLKSource(void);
+void        RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void        RCC_PCLK1Config(uint32_t RCC_HCLK);
+void        RCC_PCLK2Config(uint32_t RCC_HCLK);
+void        RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+void        RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
+void        RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
+void        RCC_LSEConfig(uint8_t RCC_LSE);
+void        RCC_LSICmd(FunctionalState NewState);
+void        RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void        RCC_RTCCLKCmd(FunctionalState NewState);
+void        RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
+void        RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
+void        RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void        RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void        RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+void        RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void        RCC_BackupResetCmd(FunctionalState NewState);
+void        RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void        RCC_MCOConfig(uint8_t RCC_MCO);
+FlagStatus  RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void        RCC_ClearFlag(void);
+ITStatus    RCC_GetITStatus(uint8_t RCC_IT);
+void        RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_RCC_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_rtc.h

@@ -0,0 +1,51 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_rtc.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the RTC
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_RTC_H
+#define __CH32V10x_RTC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* RTC_interrupts_define */
+#define RTC_IT_OW         ((uint16_t)0x0004) /* Overflow interrupt */
+#define RTC_IT_ALR        ((uint16_t)0x0002) /* Alarm interrupt */
+#define RTC_IT_SEC        ((uint16_t)0x0001) /* Second interrupt */
+
+/* RTC_interrupts_flags */
+#define RTC_FLAG_RTOFF    ((uint16_t)0x0020) /* RTC Operation OFF flag */
+#define RTC_FLAG_RSF      ((uint16_t)0x0008) /* Registers Synchronized flag */
+#define RTC_FLAG_OW       ((uint16_t)0x0004) /* Overflow flag */
+#define RTC_FLAG_ALR      ((uint16_t)0x0002) /* Alarm flag */
+#define RTC_FLAG_SEC      ((uint16_t)0x0001) /* Second flag */
+
+void       RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
+void       RTC_EnterConfigMode(void);
+void       RTC_ExitConfigMode(void);
+uint32_t   RTC_GetCounter(void);
+void       RTC_SetCounter(uint32_t CounterValue);
+void       RTC_SetPrescaler(uint32_t PrescalerValue);
+void       RTC_SetAlarm(uint32_t AlarmValue);
+uint32_t   RTC_GetDivider(void);
+void       RTC_WaitForLastTask(void);
+void       RTC_WaitForSynchro(void);
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
+void       RTC_ClearFlag(uint16_t RTC_FLAG);
+ITStatus   RTC_GetITStatus(uint16_t RTC_IT);
+void       RTC_ClearITPendingBit(uint16_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_RTC_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_spi.h

@@ -0,0 +1,218 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_spi.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      SPI firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_SPI_H
+#define __CH32V10x_SPI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* SPI Init structure definition */
+typedef struct
+{
+    uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
+                               This parameter can be a value of @ref SPI_data_direction */
+
+    uint16_t SPI_Mode; /* Specifies the SPI operating mode.
+                          This parameter can be a value of @ref SPI_mode */
+
+    uint16_t SPI_DataSize; /* Specifies the SPI data size.
+                              This parameter can be a value of @ref SPI_data_size */
+
+    uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
+                          This parameter can be a value of @ref SPI_Clock_Polarity */
+
+    uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
+                          This parameter can be a value of @ref SPI_Clock_Phase */
+
+    uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
+                         hardware (NSS pin) or by software using the SSI bit.
+                         This parameter can be a value of @ref SPI_Slave_Select_management */
+
+    uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
+                                       used to configure the transmit and receive SCK clock.
+                                       This parameter can be a value of @ref SPI_BaudRate_Prescaler.
+                                       @note The communication clock is derived from the master
+                                             clock. The slave clock does not need to be set. */
+
+    uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
+                              This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+    uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
+} SPI_InitTypeDef;
+
+/* I2S Init structure definition */
+typedef struct
+{
+    uint16_t I2S_Mode; /* Specifies the I2S operating mode.
+                          This parameter can be a value of @ref I2S_Mode */
+
+    uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
+                              This parameter can be a value of @ref I2S_Standard */
+
+    uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
+                                This parameter can be a value of @ref I2S_Data_Format */
+
+    uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
+                                This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
+                               This parameter can be a value of @ref I2S_Audio_Frequency */
+
+    uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
+                          This parameter can be a value of @ref I2S_Clock_Polarity */
+} I2S_InitTypeDef;
+
+/* SPI_data_direction */
+#define SPI_Direction_2Lines_FullDuplex    ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly        ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx             ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx             ((uint16_t)0xC000)
+
+/* SPI_mode */
+#define SPI_Mode_Master                    ((uint16_t)0x0104)
+#define SPI_Mode_Slave                     ((uint16_t)0x0000)
+
+/* SPI_data_size */
+#define SPI_DataSize_16b                   ((uint16_t)0x0800)
+#define SPI_DataSize_8b                    ((uint16_t)0x0000)
+
+/* SPI_Clock_Polarity */
+#define SPI_CPOL_Low                       ((uint16_t)0x0000)
+#define SPI_CPOL_High                      ((uint16_t)0x0002)
+
+/* SPI_Clock_Phase */
+#define SPI_CPHA_1Edge                     ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                     ((uint16_t)0x0001)
+
+/* SPI_Slave_Select_management */
+#define SPI_NSS_Soft                       ((uint16_t)0x0200)
+#define SPI_NSS_Hard                       ((uint16_t)0x0000)
+
+/* SPI_BaudRate_Prescaler */
+#define SPI_BaudRatePrescaler_2            ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4            ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8            ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16           ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32           ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64           ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128          ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256          ((uint16_t)0x0038)
+
+/* SPI_MSB_LSB_transmission */
+#define SPI_FirstBit_MSB                   ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                   ((uint16_t)0x0080)
+
+/* I2S_Mode */
+#define I2S_Mode_SlaveTx                   ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                   ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx                  ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx                  ((uint16_t)0x0300)
+
+/* I2S_Standard */
+#define I2S_Standard_Phillips              ((uint16_t)0x0000)
+#define I2S_Standard_MSB                   ((uint16_t)0x0010)
+#define I2S_Standard_LSB                   ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort              ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong               ((uint16_t)0x00B0)
+
+/* I2S_Data_Format */
+#define I2S_DataFormat_16b                 ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended         ((uint16_t)0x0001)
+#define I2S_DataFormat_24b                 ((uint16_t)0x0003)
+#define I2S_DataFormat_32b                 ((uint16_t)0x0005)
+
+/* I2S_MCLK_Output */
+#define I2S_MCLKOutput_Enable              ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable             ((uint16_t)0x0000)
+
+/* I2S_Audio_Frequency */
+#define I2S_AudioFreq_192k                 ((uint32_t)192000)
+#define I2S_AudioFreq_96k                  ((uint32_t)96000)
+#define I2S_AudioFreq_48k                  ((uint32_t)48000)
+#define I2S_AudioFreq_44k                  ((uint32_t)44100)
+#define I2S_AudioFreq_32k                  ((uint32_t)32000)
+#define I2S_AudioFreq_22k                  ((uint32_t)22050)
+#define I2S_AudioFreq_16k                  ((uint32_t)16000)
+#define I2S_AudioFreq_11k                  ((uint32_t)11025)
+#define I2S_AudioFreq_8k                   ((uint32_t)8000)
+#define I2S_AudioFreq_Default              ((uint32_t)2)
+
+/* I2S_Clock_Polarity */
+#define I2S_CPOL_Low                       ((uint16_t)0x0000)
+#define I2S_CPOL_High                      ((uint16_t)0x0008)
+
+/* SPI_I2S_DMA_transfer_requests */
+#define SPI_I2S_DMAReq_Tx                  ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx                  ((uint16_t)0x0001)
+
+/* SPI_NSS_internal_software_management */
+#define SPI_NSSInternalSoft_Set            ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset          ((uint16_t)0xFEFF)
+
+/* SPI_CRC_Transmit_Receive */
+#define SPI_CRC_Tx                         ((uint8_t)0x00)
+#define SPI_CRC_Rx                         ((uint8_t)0x01)
+
+/* SPI_direction_transmit_receive */
+#define SPI_Direction_Rx                   ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                   ((uint16_t)0x4000)
+
+/* SPI_I2S_interrupts_definition */
+#define SPI_I2S_IT_TXE                     ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                    ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                     ((uint8_t)0x50)
+#define SPI_I2S_IT_OVR                     ((uint8_t)0x56)
+#define SPI_IT_MODF                        ((uint8_t)0x55)
+#define SPI_IT_CRCERR                      ((uint8_t)0x54)
+#define I2S_IT_UDR                         ((uint8_t)0x53)
+
+/* SPI_I2S_flags_definition */
+#define SPI_I2S_FLAG_RXNE                  ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                   ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                    ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                       ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                    ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                      ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                   ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                   ((uint16_t)0x0080)
+
+void       SPI_I2S_DeInit(SPI_TypeDef *SPIx);
+void       SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
+void       I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct);
+void       SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
+void       I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
+void       SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+void       I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+void       SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+void       SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+void       SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
+uint16_t   SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
+void       SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
+void       SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
+void       SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
+void       SPI_TransmitCRC(SPI_TypeDef *SPIx);
+void       SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
+uint16_t   SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
+uint16_t   SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
+void       SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
+void       SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus   SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
+void       SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_SPI_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_tim.h

@@ -0,0 +1,506 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_tim.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      TIM firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_TIM_H
+#define __CH32V10x_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* TIM Time Base Init structure definition */
+typedef struct
+{
+    uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
+                               This parameter can be a number between 0x0000 and 0xFFFF */
+
+    uint16_t TIM_CounterMode; /* Specifies the counter mode.
+                                 This parameter can be a value of @ref TIM_Counter_Mode */
+
+    uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
+                            Auto-Reload Register at the next update event.
+                            This parameter must be a number between 0x0000 and 0xFFFF.  */
+
+    uint16_t TIM_ClockDivision; /* Specifies the clock division.
+                                  This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+    uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
+                                      reaches zero, an update event is generated and counting restarts
+                                      from the RCR value (N).
+                                      This means in PWM mode that (N+1) corresponds to:
+                                         - the number of PWM periods in edge-aligned mode
+                                         - the number of half PWM period in center-aligned mode
+                                      This parameter must be a number between 0x00 and 0xFF.
+                                      @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef;
+
+/* TIM Output Compare Init structure definition */
+typedef struct
+{
+    uint16_t TIM_OCMode; /* Specifies the TIM mode.
+                            This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+    uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_state */
+
+    uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
+                                  This parameter can be a value of @ref TIM_Output_Compare_N_state
+                                  @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
+                           This parameter can be a number between 0x0000 and 0xFFFF */
+
+    uint16_t TIM_OCPolarity; /* Specifies the output polarity.
+                                This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+    uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
+                                 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
+                                 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                 @note This parameter is valid only for TIM1 and TIM8. */
+
+    uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
+                                  This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                  @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/* TIM Input Capture Init structure definition */
+typedef struct
+{
+    uint16_t TIM_Channel; /* Specifies the TIM channel.
+                             This parameter can be a value of @ref TIM_Channel */
+
+    uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
+                                This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+    uint16_t TIM_ICSelection; /* Specifies the input.
+                                 This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+    uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
+                                 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+    uint16_t TIM_ICFilter; /* Specifies the input capture filter.
+                              This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/* BDTR structure definition */
+typedef struct
+{
+    uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
+                               This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
+
+    uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
+                               This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
+
+    uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
+                               This parameter can be a value of @ref Lock_level */
+
+    uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
+                              switching-on of the outputs.
+                              This parameter can be a number between 0x00 and 0xFF  */
+
+    uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
+                           This parameter can be a value of @ref Break_Input_enable_disable */
+
+    uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
+                                   This parameter can be a value of @ref Break_Polarity */
+
+    uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
+                                     This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* TIM_Output_Compare_and_PWM_modes */
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+
+/* TIM_One_Pulse_Mode */
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+
+/* TIM_Channel */
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+
+/* TIM_Clock_Division_CKD */
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+
+/* TIM_Counter_Mode */
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+
+/* TIM_Output_Compare_Polarity */
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+
+/* TIM_Output_Compare_N_Polarity */
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+
+/* TIM_Output_Compare_state */
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+
+/* TIM_Output_Compare_N_state */
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+
+/* TIM_Capture_Compare_state */
+#define TIM_CCx_Enable                     ((uint16_t)0x0001)
+#define TIM_CCx_Disable                    ((uint16_t)0x0000)
+
+/* TIM_Capture_Compare_N_state */
+#define TIM_CCxN_Enable                    ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                   ((uint16_t)0x0000)
+
+/* Break_Input_enable_disable */
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+
+/* Break_Polarity */
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+
+/* TIM_AOE_Bit_Set_Reset */
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+
+/* Lock_level */
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+
+/* OSSI_Off_State_Selection_for_Idle_mode_state */
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+
+/* OSSR_Off_State_Selection_for_Run_mode_state */
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Idle_State */
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_N_Idle_State */
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+
+/* TIM_Input_Capture_Polarity */
+#define TIM_ICPolarity_Rising              ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling             ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge            ((uint16_t)0x000A)
+
+/* TIM_Input_Capture_Selection */
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
+                                                                 connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
+                                                                 connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+
+/* TIM_Input_Capture_Prescaler */
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /* Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /* Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /* Capture performed once every 8 events. */
+
+/* TIM_interrupt_sources */
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+
+/* TIM_DMA_Base_address */
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+
+/* TIM_DMA_Burst_Length */
+#define TIM_DMABurstLength_1Transfer       ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers      ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers      ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers      ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers      ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers      ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers      ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers      ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers      ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers     ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers     ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers     ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers     ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers     ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers     ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers     ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers     ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers     ((uint16_t)0x1100)
+
+/* TIM_DMA_sources */
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+
+/* TIM_External_Trigger_Prescaler */
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+
+/* TIM_Internal_Trigger_Selection */
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+
+/* TIM_TIx_External_Clock_Source */
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/* TIM_External_Trigger_Polarity */
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+
+/* TIM_Prescaler_Reload_Mode */
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+
+/* TIM_Forced_Action */
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+
+/* TIM_Encoder_Mode */
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+
+/* TIM_Event_Source */
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+
+/* TIM_Update_Source */
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
+                                                                 or the setting of UG bit, or an update generation  \
+                                                                 through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
+
+/* TIM_Output_Compare_Preload_State */
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Fast_State */
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Clear_State */
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+
+/* TIM_Trigger_Output_Source */
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+
+/* TIM_Slave_Mode */
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+
+/* TIM_Master_Slave_Mode */
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+
+/* TIM_Flags */
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+
+/* TIM_Legacy */
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+
+void       TIM_DeInit(TIM_TypeDef *TIMx);
+void       TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+void       TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
+void       TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
+void       TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void       TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
+void       TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
+void       TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
+void       TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void       TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void       TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
+void       TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void       TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void       TIM_InternalClockConfig(TIM_TypeDef *TIMx);
+void       TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
+void       TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                      uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void       TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                                   uint16_t ExtTRGFilter);
+void       TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
+                                   uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+void       TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                         uint16_t ExtTRGFilter);
+void       TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void       TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
+void       TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
+void       TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
+                                      uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void       TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
+void       TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
+void       TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
+void       TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
+void       TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
+void       TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
+void       TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
+void       TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
+void       TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void       TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+void       TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void       TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
+void       TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
+void       TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
+void       TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
+void       TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
+void       TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
+void       TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
+void       TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
+void       TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
+void       TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
+void       TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
+void       TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
+void       TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
+void       TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
+uint16_t   TIM_GetCapture1(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCapture2(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCapture3(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCapture4(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetCounter(TIM_TypeDef *TIMx);
+uint16_t   TIM_GetPrescaler(TIM_TypeDef *TIMx);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
+void       TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
+ITStatus   TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
+void       TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__CH32V10x_TIM_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_usart.h

@@ -0,0 +1,185 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_usart.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the
+ *                      USART firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_USART_H
+#define __CH32V10x_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* USART Init Structure definition */
+typedef struct
+{
+    uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
+                                The baud rate is computed using the following formula:
+                                 - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
+                                 - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
+
+    uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
+                                  This parameter can be a value of @ref USART_Word_Length */
+
+    uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
+                                This parameter can be a value of @ref USART_Stop_Bits */
+
+    uint16_t USART_Parity; /* Specifies the parity mode.
+                              This parameter can be a value of @ref USART_Parity
+                              @note When parity is enabled, the computed parity is inserted
+                                    at the MSB position of the transmitted data (9th bit when
+                                    the word length is set to 9 data bits; 8th bit when the
+                                    word length is set to 8 data bits). */
+
+    uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
+                            This parameter can be a value of @ref USART_Mode */
+
+    uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/* USART Clock Init Structure definition */
+typedef struct
+{
+    uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
+                             This parameter can be a value of @ref USART_Clock */
+
+    uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
+                            This parameter can be a value of @ref USART_Clock_Polarity */
+
+    uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
+                            This parameter can be a value of @ref USART_Clock_Phase */
+
+    uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* USART_Word_Length */
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+
+/* USART_Stop_Bits */
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+
+/* USART_Parity */
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600)
+
+/* USART_Mode */
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_ORE_RX                      ((uint16_t)0x0325)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE_ER                      ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+
+#define USART_IT_ORE                         USART_IT_ORE_ER
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b       ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b       ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+
+void       USART_DeInit(USART_TypeDef *USARTx);
+void       USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
+void       USART_StructInit(USART_InitTypeDef *USART_InitStruct);
+void       USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
+void       USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
+void       USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
+void       USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+void       USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
+void       USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
+void       USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
+void       USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
+uint16_t   USART_ReceiveData(USART_TypeDef *USARTx);
+void       USART_SendBreak(USART_TypeDef *USARTx);
+void       USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
+void       USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
+void       USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState);
+void       USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
+void       USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
+void       USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
+ITStatus   USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
+void       USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_USART_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_usb.h

@@ -0,0 +1,700 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_usb.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the USB
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_USB_H
+#define __CH32V10x_USB_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef NULL
+  #define NULL    0
+#endif
+
+#ifndef VOID
+  #define VOID    void
+#endif
+#ifndef CONST
+  #define CONST    const
+#endif
+#ifndef BOOL
+typedef unsigned char BOOL;
+#endif
+#ifndef BOOLEAN
+typedef unsigned char BOOLEAN;
+#endif
+#ifndef CHAR
+typedef char CHAR;
+#endif
+#ifndef INT8
+typedef char INT8;
+#endif
+#ifndef INT16
+typedef short INT16;
+#endif
+#ifndef INT32
+typedef long INT32;
+#endif
+#ifndef UINT8
+typedef unsigned char UINT8;
+#endif
+#ifndef UINT16
+typedef unsigned short UINT16;
+#endif
+#ifndef UINT32
+typedef unsigned long UINT32;
+#endif
+#ifndef UINT8V
+typedef unsigned char volatile UINT8V;
+#endif
+#ifndef UINT16V
+typedef unsigned short volatile UINT16V;
+#endif
+#ifndef UINT32V
+typedef unsigned long volatile UINT32V;
+#endif
+
+#ifndef PVOID
+typedef void *PVOID;
+#endif
+#ifndef PCHAR
+typedef char *PCHAR;
+#endif
+#ifndef PCHAR
+typedef const char *PCCHAR;
+#endif
+#ifndef PINT8
+typedef char *PINT8;
+#endif
+#ifndef PINT16
+typedef short *PINT16;
+#endif
+#ifndef PINT32
+typedef long *PINT32;
+#endif
+#ifndef PUINT8
+typedef unsigned char *PUINT8;
+#endif
+#ifndef PUINT16
+typedef unsigned short *PUINT16;
+#endif
+#ifndef PUINT32
+typedef unsigned long *PUINT32;
+#endif
+#ifndef PUINT8V
+typedef volatile unsigned char *PUINT8V;
+#endif
+#ifndef PUINT16V
+typedef volatile unsigned short *PUINT16V;
+#endif
+#ifndef PUINT32V
+typedef volatile unsigned long *PUINT32V;
+#endif
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+/*       USB  */
+#define R32_USB_CONTROL      (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address
+#define R8_USB_CTRL          (*((PUINT8V)(0x40023400)))  // USB base control
+#define RB_UC_HOST_MODE      0x80                        // enable USB host mode: 0=device mode, 1=host mode
+#define RB_UC_LOW_SPEED      0x40                        // enable USB low speed: 0=12Mbps, 1=1.5Mbps
+#define RB_UC_DEV_PU_EN      0x20                        // USB device enable and internal pullup resistance enable
+#define RB_UC_SYS_CTRL1      0x20                        // USB system control high bit
+#define RB_UC_SYS_CTRL0      0x10                        // USB system control low bit
+#define MASK_UC_SYS_CTRL     0x30                        // bit mask of USB system control
+// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control
+//   0 00: disable USB device and disable internal pullup resistance
+//   0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
+//   0 1x: enable USB device and enable internal pullup resistance
+//   1 00: enable USB host and normal status
+//   1 01: enable USB host and force UDP/UDM output SE0 state
+//   1 10: enable USB host and force UDP/UDM output J state
+//   1 11: enable USB host and force UDP/UDM output resume or K state
+#define RB_UC_INT_BUSY       0x08           // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
+#define RB_UC_RESET_SIE      0x04           // force reset USB SIE, need software clear
+#define RB_UC_CLR_ALL        0x02           // force clear FIFO and count of USB
+#define RB_UC_DMA_EN         0x01           // DMA enable and DMA interrupt enable for USB
+
+#define R8_UDEV_CTRL         (*((PUINT8V)(0x40023401))) // USB device physical prot control
+#define RB_UD_PD_DIS         0x80                       // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define RB_UD_DP_PIN         0x20                       // ReadOnly: indicate current UDP pin level
+#define RB_UD_DM_PIN         0x10                       // ReadOnly: indicate current UDM pin level
+#define RB_UD_LOW_SPEED      0x04                       // enable USB physical port low speed: 0=full speed, 1=low speed
+#define RB_UD_GP_BIT         0x02                       // general purpose bit
+#define RB_UD_PORT_EN        0x01                       // enable USB physical port I/O: 0=disable, 1=enable
+
+#define R8_UHOST_CTRL        R8_UDEV_CTRL   // USB host physical prot control
+#define RB_UH_PD_DIS         0x80           // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define RB_UH_DP_PIN         0x20           // ReadOnly: indicate current UDP pin level
+#define RB_UH_DM_PIN         0x10           // ReadOnly: indicate current UDM pin level
+#define RB_UH_LOW_SPEED      0x04           // enable USB port low speed: 0=full speed, 1=low speed
+#define RB_UH_BUS_RESET      0x02           // control USB bus reset: 0=normal, 1=force bus reset
+#define RB_UH_PORT_EN        0x01           // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
+
+#define R8_USB_INT_EN        (*((PUINT8V)(0x40023402))) // USB interrupt enable
+#define RB_UIE_DEV_SOF       0x80                       // enable interrupt for SOF received for USB device mode
+#define RB_UIE_DEV_NAK       0x40                       // enable interrupt for NAK responded for USB device mode
+#define RB_UIE_FIFO_OV       0x10                       // enable interrupt for FIFO overflow
+#define RB_UIE_HST_SOF       0x08                       // enable interrupt for host SOF timer action for USB host mode
+#define RB_UIE_SUSPEND       0x04                       // enable interrupt for USB suspend or resume event
+#define RB_UIE_TRANSFER      0x02                       // enable interrupt for USB transfer completion
+#define RB_UIE_DETECT        0x01                       // enable interrupt for USB device detected event for USB host mode
+#define RB_UIE_BUS_RST       0x01                       // enable interrupt for USB bus reset event for USB device mode
+
+#define R8_USB_DEV_AD        (*((PUINT8V)(0x40023403))) // USB device address
+#define RB_UDA_GP_BIT        0x80                       // general purpose bit
+#define MASK_USB_ADDR        0x7F                       // bit mask for USB device address
+
+#define R32_USB_STATUS       (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status
+#define R8_USB_MIS_ST        (*((PUINT8V)(0x40023405)))  // USB miscellaneous status
+#define RB_UMS_SOF_PRES      0x80                        // RO, indicate host SOF timer presage status
+#define RB_UMS_SOF_ACT       0x40                        // RO, indicate host SOF timer action status for USB host
+#define RB_UMS_SIE_FREE      0x20                        // RO, indicate USB SIE free status
+#define RB_UMS_R_FIFO_RDY    0x10                        // RO, indicate USB receiving FIFO ready status (not empty)
+#define RB_UMS_BUS_RESET     0x08                        // RO, indicate USB bus reset status
+#define RB_UMS_SUSPEND       0x04                        // RO, indicate USB suspend status
+#define RB_UMS_DM_LEVEL      0x02                        // RO, indicate UDM level saved at device attached to USB host
+#define RB_UMS_DEV_ATTACH    0x01                        // RO, indicate device attached status on USB host
+
+#define R8_USB_INT_FG        (*((PUINT8V)(0x40023406))) // USB interrupt flag
+#define RB_U_IS_NAK          0x80                       // RO, indicate current USB transfer is NAK received
+#define RB_U_TOG_OK          0x40                       // RO, indicate current USB transfer toggle is OK
+#define RB_U_SIE_FREE        0x20                       // RO, indicate USB SIE free status
+#define RB_UIF_FIFO_OV       0x10                       // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
+#define RB_UIF_HST_SOF       0x08                       // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
+#define RB_UIF_SUSPEND       0x04                       // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
+#define RB_UIF_TRANSFER      0x02                       // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
+#define RB_UIF_DETECT        0x01                       // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
+#define RB_UIF_BUS_RST       0x01                       // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
+
+#define R8_USB_INT_ST        (*((PUINT8V)(0x40023407))) // USB interrupt status
+#define RB_UIS_IS_NAK        0x80                       // RO, indicate current USB transfer is NAK received for USB device mode
+#define RB_UIS_TOG_OK        0x40                       // RO, indicate current USB transfer toggle is OK
+#define RB_UIS_TOKEN1        0x20                       // RO, current token PID code bit 1 received for USB device mode
+#define RB_UIS_TOKEN0        0x10                       // RO, current token PID code bit 0 received for USB device mode
+#define MASK_UIS_TOKEN       0x30                       // RO, bit mask of current token PID code received for USB device mode
+#define UIS_TOKEN_OUT        0x00
+#define UIS_TOKEN_SOF        0x10
+#define UIS_TOKEN_IN         0x20
+#define UIS_TOKEN_SETUP      0x30
+// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
+//   00: OUT token PID received
+//   01: SOF token PID received
+//   10: IN token PID received
+//   11: SETUP token PID received
+#define MASK_UIS_ENDP        0x0F           // RO, bit mask of current transfer endpoint number for USB device mode
+#define MASK_UIS_H_RES       0x0F           // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
+
+#define R8_USB_RX_LEN        (*((PUINT8V)(0x40023408)))  // USB receiving length
+#define R32_USB_BUF_MODE     (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode
+#define R8_UEP4_1_MOD        (*((PUINT8V)(0x4002340c)))  // endpoint 4/1 mode
+#define RB_UEP1_RX_EN        0x80                        // enable USB endpoint 1 receiving (OUT)
+#define RB_UEP1_TX_EN        0x40                        // enable USB endpoint 1 transmittal (IN)
+#define RB_UEP1_BUF_MOD      0x10                        // buffer mode of USB endpoint 1
+// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
+//   0 0 x:  disable endpoint and disable buffer
+//   1 0 0:  64 bytes buffer for receiving (OUT endpoint)
+//   1 0 1:  dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
+//   0 1 0:  64 bytes buffer for transmittal (IN endpoint)
+//   0 1 1:  dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
+//   1 1 0:  64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
+//   1 1 1:  dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
+#define RB_UEP4_RX_EN        0x08           // enable USB endpoint 4 receiving (OUT)
+#define RB_UEP4_TX_EN        0x04           // enable USB endpoint 4 transmittal (IN)
+// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
+//   0 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+//   1 0:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
+//   0 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
+//   1 1:  single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+//           + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
+
+#define R8_UEP2_3_MOD        (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode
+#define RB_UEP3_RX_EN        0x80                       // enable USB endpoint 3 receiving (OUT)
+#define RB_UEP3_TX_EN        0x40                       // enable USB endpoint 3 transmittal (IN)
+#define RB_UEP3_BUF_MOD      0x10                       // buffer mode of USB endpoint 3
+#define RB_UEP2_RX_EN        0x08                       // enable USB endpoint 2 receiving (OUT)
+#define RB_UEP2_TX_EN        0x04                       // enable USB endpoint 2 transmittal (IN)
+#define RB_UEP2_BUF_MOD      0x01                       // buffer mode of USB endpoint 2
+
+#define R8_UH_EP_MOD         R8_UEP2_3_MOD  //host endpoint mode
+#define RB_UH_EP_TX_EN       0x40           // enable USB host OUT endpoint transmittal
+#define RB_UH_EP_TBUF_MOD    0x10           // buffer mode of USB host OUT endpoint
+// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
+//   0 x:  disable endpoint and disable buffer
+//   1 0:  64 bytes buffer for transmittal (OUT endpoint)
+//   1 1:  dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
+#define RB_UH_EP_RX_EN       0x08           // enable USB host IN endpoint receiving
+#define RB_UH_EP_RBUF_MOD    0x01           // buffer mode of USB host IN endpoint
+// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
+//   0 x:  disable endpoint and disable buffer
+//   1 0:  64 bytes buffer for receiving (IN endpoint)
+//   1 1:  dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
+
+#define R8_UEP5_6_MOD        (*((PUINT8V)(0x4002340e))) // endpoint 5/6 mode
+#define RB_UEP6_RX_EN        0x80                       // enable USB endpoint 6 receiving (OUT)
+#define RB_UEP6_TX_EN        0x40                       // enable USB endpoint 6 transmittal (IN)
+#define RB_UEP6_BUF_MOD      0x10                       // buffer mode of USB endpoint 6
+#define RB_UEP5_RX_EN        0x08                       // enable USB endpoint 5 receiving (OUT)
+#define RB_UEP5_TX_EN        0x04                       // enable USB endpoint 5 transmittal (IN)
+#define RB_UEP5_BUF_MOD      0x01                       // buffer mode of USB endpoint 5
+
+#define R8_UEP7_MOD          (*((PUINT8V)(0x4002340f))) // endpoint 7 mode
+#define RB_UEP7_RX_EN        0x08                       // enable USB endpoint 7 receiving (OUT)
+#define RB_UEP7_TX_EN        0x04                       // enable USB endpoint 7 transmittal (IN)
+#define RB_UEP7_BUF_MOD      0x01                       // buffer mode of USB endpoint 7
+
+#define R16_UEP0_DMA         (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address
+#define R16_UEP1_DMA         (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address
+#define R16_UEP2_DMA         (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address
+#define R16_UH_RX_DMA        R16_UEP2_DMA                // host rx endpoint buffer high address
+#define R16_UEP3_DMA         (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address
+
+#define R16_UEP4_DMA         (*((PUINT16V)(0x40023420))) // endpoint 4 DMA buffer address
+#define R16_UEP5_DMA         (*((PUINT16V)(0x40023424))) // endpoint 5 DMA buffer address
+#define R16_UEP6_DMA         (*((PUINT16V)(0x40023428))) // endpoint 6 DMA buffer address
+#define R16_UEP7_DMA         (*((PUINT16V)(0x4002342c))) // endpoint 7 DMA buffer address
+
+#define R16_UH_TX_DMA        R16_UEP3_DMA                // host tx endpoint buffer high address
+#define R32_USB_EP0_CTRL     (*((PUINT32V)(0x40023430))) // endpoint 0 control & transmittal length
+#define R8_UEP0_T_LEN        (*((PUINT8V)(0x40023430)))  // endpoint 0 transmittal length
+#define R8_UEP0_CTRL         (*((PUINT8V)(0x40023432)))  // endpoint 0 control
+#define R32_USB_EP1_CTRL     (*((PUINT32V)(0x40023434))) // endpoint 1 control & transmittal length
+#define R8_UEP1_T_LEN        (*((PUINT8V)(0x40023434)))  // endpoint 1 transmittal length
+#define R8_UEP1_CTRL         (*((PUINT8V)(0x40023436)))  // endpoint 1 control
+#define RB_UEP_R_TOG         0x80                        // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
+#define RB_UEP_T_TOG         0x40                        // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
+#define RB_UEP_AUTO_TOG      0x10                        // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
+#define RB_UEP_R_RES1        0x08                        // handshake response type high bit for USB endpoint X receiving (OUT)
+#define RB_UEP_R_RES0        0x04                        // handshake response type low bit for USB endpoint X receiving (OUT)
+#define MASK_UEP_R_RES       0x0C                        // bit mask of handshake response type for USB endpoint X receiving (OUT)
+#define UEP_R_RES_ACK        0x00
+#define UEP_R_RES_TOUT       0x04
+#define UEP_R_RES_NAK        0x08
+#define UEP_R_RES_STALL      0x0C
+// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
+//   00: ACK (ready)
+//   01: no response, time out to host, for non-zero endpoint isochronous transactions
+//   10: NAK (busy)
+//   11: STALL (error)
+#define RB_UEP_T_RES1        0x02           // handshake response type high bit for USB endpoint X transmittal (IN)
+#define RB_UEP_T_RES0        0x01           // handshake response type low bit for USB endpoint X transmittal (IN)
+#define MASK_UEP_T_RES       0x03           // bit mask of handshake response type for USB endpoint X transmittal (IN)
+#define UEP_T_RES_ACK        0x00
+#define UEP_T_RES_TOUT       0x01
+#define UEP_T_RES_NAK        0x02
+#define UEP_T_RES_STALL      0x03
+// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
+//   00: DATA0 or DATA1 then expecting ACK (ready)
+//   01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
+//   10: NAK (busy)
+//   11: STALL (error)
+
+#define R8_UH_SETUP          R8_UEP1_CTRL   // host aux setup
+#define RB_UH_PRE_PID_EN     0x80           // USB host PRE PID enable for low speed device via hub
+#define RB_UH_SOF_EN         0x40           // USB host automatic SOF enable
+
+#define R32_USB_EP2_CTRL     (*((PUINT32V)(0x40023438))) // endpoint 2 control & transmittal length
+#define R8_UEP2_T_LEN        (*((PUINT8V)(0x40023438)))  // endpoint 2 transmittal length
+#define R8_UEP2_CTRL         (*((PUINT8V)(0x4002343a)))  // endpoint 2 control
+
+#define R8_UH_EP_PID         R8_UEP2_T_LEN  // host endpoint and PID
+#define MASK_UH_TOKEN        0xF0           // bit mask of token PID for USB host transfer
+#define MASK_UH_ENDP         0x0F           // bit mask of endpoint number for USB host transfer
+
+#define R8_UH_RX_CTRL        R8_UEP2_CTRL   // host receiver endpoint control
+#define RB_UH_R_TOG          0x80           // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
+#define RB_UH_R_AUTO_TOG     0x10           // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define RB_UH_R_RES          0x04           // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
+
+#define R32_USB_EP3_CTRL     (*((PUINT32V)(0x4002343c))) // endpoint 3 control & transmittal length
+#define R8_UEP3_T_LEN        (*((PUINT16V)(0x4002343c))) // endpoint 3 transmittal length
+#define R8_UEP3_CTRL         (*((PUINT8V)(0x4002343e)))  // endpoint 3 control
+#define R8_UH_TX_LEN         (*((PUINT16V)(0x4002343c))) //R8_UEP3_T_LEN				// host transmittal endpoint transmittal length
+
+#define R8_UH_TX_CTRL        R8_UEP3_CTRL   // host transmittal endpoint control
+#define RB_UH_T_TOG          0x40           // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
+#define RB_UH_T_AUTO_TOG     0x10           // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define RB_UH_T_RES          0x01           // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
+
+#define R32_USB_EP4_CTRL     (*((PUINT32V)(0x40023440))) // endpoint 4 control & transmittal length
+#define R8_UEP4_T_LEN        (*((PUINT8V)(0x40023440)))  // endpoint 4 transmittal length
+#define R8_UEP4_CTRL         (*((PUINT8V)(0x40023442)))  // endpoint 4 control
+
+#define R32_USB_EP5_CTRL     (*((PUINT32V)(0x40023444))) // endpoint 5 control & transmittal length
+#define R8_UEP5_T_LEN        (*((PUINT8V)(0x40023444)))  // endpoint 5 transmittal length
+#define R8_UEP5_CTRL         (*((PUINT8V)(0x40023446)))  // endpoint 5 control
+
+#define R32_USB_EP6_CTRL     (*((PUINT32V)(0x40023448))) // endpoint 6 control & transmittal length
+#define R8_UEP6_T_LEN        (*((PUINT8V)(0x40023448)))  // endpoint 6 transmittal length
+#define R8_UEP6_CTRL         (*((PUINT8V)(0x4002344a)))  // endpoint 6 control
+
+#define R32_USB_EP7_CTRL     (*((PUINT32V)(0x4002344c))) // endpoint 7 control & transmittal length
+#define R8_UEP7_T_LEN        (*((PUINT8V)(0x4002344c)))  // endpoint 7 transmittal length
+#define R8_UEP7_CTRL         (*((PUINT8V)(0x4002344e)))  // endpoint 7 control
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__CH32V10x_USB_H
+
+#ifndef __USB_TYPE__
+#define __USB_TYPE__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* USB constant and structure define */
+
+/* USB PID */
+#ifndef USB_PID_SETUP
+  #define USB_PID_NULL     0x00  /* reserved PID */
+  #define USB_PID_SOF      0x05
+  #define USB_PID_SETUP    0x0D
+  #define USB_PID_IN       0x09
+  #define USB_PID_OUT      0x01
+  #define USB_PID_ACK      0x02
+  #define USB_PID_NAK      0x0A
+  #define USB_PID_STALL    0x0E
+  #define USB_PID_DATA0    0x03
+  #define USB_PID_DATA1    0x0B
+  #define USB_PID_PRE      0x0C
+#endif
+
+/* USB standard device request code */
+#ifndef USB_GET_DESCRIPTOR
+  #define USB_GET_STATUS           0x00
+  #define USB_CLEAR_FEATURE        0x01
+  #define USB_SET_FEATURE          0x03
+  #define USB_SET_ADDRESS          0x05
+  #define USB_GET_DESCRIPTOR       0x06
+  #define USB_SET_DESCRIPTOR       0x07
+  #define USB_GET_CONFIGURATION    0x08
+  #define USB_SET_CONFIGURATION    0x09
+  #define USB_GET_INTERFACE        0x0A
+  #define USB_SET_INTERFACE        0x0B
+  #define USB_SYNCH_FRAME          0x0C
+#endif
+
+/* USB hub class request code */
+#ifndef HUB_GET_DESCRIPTOR
+  #define HUB_GET_STATUS        0x00
+  #define HUB_CLEAR_FEATURE     0x01
+  #define HUB_GET_STATE         0x02
+  #define HUB_SET_FEATURE       0x03
+  #define HUB_GET_DESCRIPTOR    0x06
+  #define HUB_SET_DESCRIPTOR    0x07
+#endif
+
+/* USB HID class request code */
+#ifndef HID_GET_REPORT
+  #define HID_GET_REPORT      0x01
+  #define HID_GET_IDLE        0x02
+  #define HID_GET_PROTOCOL    0x03
+  #define HID_SET_REPORT      0x09
+  #define HID_SET_IDLE        0x0A
+  #define HID_SET_PROTOCOL    0x0B
+#endif
+
+/* Bit define for USB request type */
+#ifndef USB_REQ_TYP_MASK
+  #define USB_REQ_TYP_IN          0x80  /* control IN, device to host */
+  #define USB_REQ_TYP_OUT         0x00  /* control OUT, host to device */
+  #define USB_REQ_TYP_READ        0x80  /* control read, device to host */
+  #define USB_REQ_TYP_WRITE       0x00  /* control write, host to device */
+  #define USB_REQ_TYP_MASK        0x60  /* bit mask of request type */
+  #define USB_REQ_TYP_STANDARD    0x00
+  #define USB_REQ_TYP_CLASS       0x20
+  #define USB_REQ_TYP_VENDOR      0x40
+  #define USB_REQ_TYP_RESERVED    0x60
+  #define USB_REQ_RECIP_MASK      0x1F  /* bit mask of request recipient */
+  #define USB_REQ_RECIP_DEVICE    0x00
+  #define USB_REQ_RECIP_INTERF    0x01
+  #define USB_REQ_RECIP_ENDP      0x02
+  #define USB_REQ_RECIP_OTHER     0x03
+#endif
+
+/* USB request type for hub class request */
+#ifndef HUB_GET_HUB_DESCRIPTOR
+  #define HUB_CLEAR_HUB_FEATURE     0x20
+  #define HUB_CLEAR_PORT_FEATURE    0x23
+  #define HUB_GET_BUS_STATE         0xA3
+  #define HUB_GET_HUB_DESCRIPTOR    0xA0
+  #define HUB_GET_HUB_STATUS        0xA0
+  #define HUB_GET_PORT_STATUS       0xA3
+  #define HUB_SET_HUB_DESCRIPTOR    0x20
+  #define HUB_SET_HUB_FEATURE       0x20
+  #define HUB_SET_PORT_FEATURE      0x23
+#endif
+
+/* Hub class feature selectors */
+#ifndef HUB_PORT_RESET
+  #define HUB_C_HUB_LOCAL_POWER      0
+  #define HUB_C_HUB_OVER_CURRENT     1
+  #define HUB_PORT_CONNECTION        0
+  #define HUB_PORT_ENABLE            1
+  #define HUB_PORT_SUSPEND           2
+  #define HUB_PORT_OVER_CURRENT      3
+  #define HUB_PORT_RESET             4
+  #define HUB_PORT_POWER             8
+  #define HUB_PORT_LOW_SPEED         9
+  #define HUB_C_PORT_CONNECTION      16
+  #define HUB_C_PORT_ENABLE          17
+  #define HUB_C_PORT_SUSPEND         18
+  #define HUB_C_PORT_OVER_CURRENT    19
+  #define HUB_C_PORT_RESET           20
+#endif
+
+/* USB descriptor type */
+#ifndef USB_DESCR_TYP_DEVICE
+  #define USB_DESCR_TYP_DEVICE     0x01
+  #define USB_DESCR_TYP_CONFIG     0x02
+  #define USB_DESCR_TYP_STRING     0x03
+  #define USB_DESCR_TYP_INTERF     0x04
+  #define USB_DESCR_TYP_ENDP       0x05
+  #define USB_DESCR_TYP_QUALIF     0x06
+  #define USB_DESCR_TYP_SPEED      0x07
+  #define USB_DESCR_TYP_OTG        0x09
+  #define USB_DESCR_TYP_HID        0x21
+  #define USB_DESCR_TYP_REPORT     0x22
+  #define USB_DESCR_TYP_PHYSIC     0x23
+  #define USB_DESCR_TYP_CS_INTF    0x24
+  #define USB_DESCR_TYP_CS_ENDP    0x25
+  #define USB_DESCR_TYP_HUB        0x29
+#endif
+
+/* USB device class */
+#ifndef USB_DEV_CLASS_HUB
+  #define USB_DEV_CLASS_RESERVED     0x00
+  #define USB_DEV_CLASS_AUDIO        0x01
+  #define USB_DEV_CLASS_COMMUNIC     0x02
+  #define USB_DEV_CLASS_HID          0x03
+  #define USB_DEV_CLASS_MONITOR      0x04
+  #define USB_DEV_CLASS_PHYSIC_IF    0x05
+  #define USB_DEV_CLASS_POWER        0x06
+  #define USB_DEV_CLASS_PRINTER      0x07
+  #define USB_DEV_CLASS_STORAGE      0x08
+  #define USB_DEV_CLASS_HUB          0x09
+  #define USB_DEV_CLASS_VEN_SPEC     0xFF
+#endif
+
+/* USB endpoint type and attributes */
+#ifndef USB_ENDP_TYPE_MASK
+  #define USB_ENDP_DIR_MASK      0x80
+  #define USB_ENDP_ADDR_MASK     0x0F
+  #define USB_ENDP_TYPE_MASK     0x03
+  #define USB_ENDP_TYPE_CTRL     0x00
+  #define USB_ENDP_TYPE_ISOCH    0x01
+  #define USB_ENDP_TYPE_BULK     0x02
+  #define USB_ENDP_TYPE_INTER    0x03
+#endif
+
+#ifndef USB_DEVICE_ADDR
+  #define USB_DEVICE_ADDR    0x02
+#endif
+#ifndef DEFAULT_ENDP0_SIZE
+  #define DEFAULT_ENDP0_SIZE    8  /* default maximum packet size for endpoint 0 */
+#endif
+#ifndef MAX_PACKET_SIZE
+  #define MAX_PACKET_SIZE    64  /* maximum packet size */
+#endif
+#ifndef USB_BO_CBW_SIZE
+  #define USB_BO_CBW_SIZE    0x1F
+  #define USB_BO_CSW_SIZE    0x0D
+#endif
+#ifndef USB_BO_CBW_SIG0
+  #define USB_BO_CBW_SIG0    0x55
+  #define USB_BO_CBW_SIG1    0x53
+  #define USB_BO_CBW_SIG2    0x42
+  #define USB_BO_CBW_SIG3    0x43
+  #define USB_BO_CSW_SIG0    0x55
+  #define USB_BO_CSW_SIG1    0x53
+  #define USB_BO_CSW_SIG2    0x42
+  #define USB_BO_CSW_SIG3    0x53
+#endif
+
+#ifndef __PACKED
+  #define __PACKED    __attribute__((packed))
+#endif
+
+typedef struct __PACKED _USB_SETUP_REQ
+{
+    UINT8  bRequestType;
+    UINT8  bRequest;
+    UINT16 wValue;
+    UINT16 wIndex;
+    UINT16 wLength;
+} USB_SETUP_REQ, *PUSB_SETUP_REQ;
+
+typedef struct __PACKED _USB_DEVICE_DESCR
+{
+    UINT8  bLength;
+    UINT8  bDescriptorType;
+    UINT16 bcdUSB;
+    UINT8  bDeviceClass;
+    UINT8  bDeviceSubClass;
+    UINT8  bDeviceProtocol;
+    UINT8  bMaxPacketSize0;
+    UINT16 idVendor;
+    UINT16 idProduct;
+    UINT16 bcdDevice;
+    UINT8  iManufacturer;
+    UINT8  iProduct;
+    UINT8  iSerialNumber;
+    UINT8  bNumConfigurations;
+} USB_DEV_DESCR, *PUSB_DEV_DESCR;
+
+typedef struct __PACKED _USB_CONFIG_DESCR
+{
+    UINT8  bLength;
+    UINT8  bDescriptorType;
+    UINT16 wTotalLength;
+    UINT8  bNumInterfaces;
+    UINT8  bConfigurationValue;
+    UINT8  iConfiguration;
+    UINT8  bmAttributes;
+    UINT8  MaxPower;
+} USB_CFG_DESCR, *PUSB_CFG_DESCR;
+
+typedef struct __PACKED _USB_INTERF_DESCR
+{
+    UINT8 bLength;
+    UINT8 bDescriptorType;
+    UINT8 bInterfaceNumber;
+    UINT8 bAlternateSetting;
+    UINT8 bNumEndpoints;
+    UINT8 bInterfaceClass;
+    UINT8 bInterfaceSubClass;
+    UINT8 bInterfaceProtocol;
+    UINT8 iInterface;
+} USB_ITF_DESCR, *PUSB_ITF_DESCR;
+
+typedef struct __PACKED _USB_ENDPOINT_DESCR
+{
+    UINT8  bLength;
+    UINT8  bDescriptorType;
+    UINT8  bEndpointAddress;
+    UINT8  bmAttributes;
+    UINT16 wMaxPacketSize;
+    UINT8  bInterval;
+} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
+
+typedef struct __PACKED _USB_CONFIG_DESCR_LONG
+{
+    USB_CFG_DESCR  cfg_descr;
+    USB_ITF_DESCR  itf_descr;
+    USB_ENDP_DESCR endp_descr[1];
+} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
+
+typedef struct __PACKED _USB_HUB_DESCR
+{
+    UINT8 bDescLength;
+    UINT8 bDescriptorType;
+    UINT8 bNbrPorts;
+    UINT8 wHubCharacteristicsL;
+    UINT8 wHubCharacteristicsH;
+    UINT8 bPwrOn2PwrGood;
+    UINT8 bHubContrCurrent;
+    UINT8 DeviceRemovable;
+    UINT8 PortPwrCtrlMask;
+} USB_HUB_DESCR, *PUSB_HUB_DESCR;
+
+typedef struct __PACKED _USB_HID_DESCR
+{
+    UINT8  bLength;
+    UINT8  bDescriptorType;
+    UINT16 bcdHID;
+    UINT8  bCountryCode;
+    UINT8  bNumDescriptors;
+    UINT8  bDescriptorTypeX;
+    UINT8  wDescriptorLengthL;
+    UINT8  wDescriptorLengthH;
+} USB_HID_DESCR, *PUSB_HID_DESCR;
+
+typedef struct __PACKED _UDISK_BOC_CBW
+{ /* command of BulkOnly USB-FlashDisk */
+    UINT32 mCBW_Sig;
+    UINT32 mCBW_Tag;
+    UINT32 mCBW_DataLen; /* uppest byte of data length, always is 0 */
+    UINT8  mCBW_Flag;    /* transfer direction and etc. */
+    UINT8  mCBW_LUN;
+    UINT8  mCBW_CB_Len;     /* length of command block */
+    UINT8  mCBW_CB_Buf[16]; /* command block buffer */
+} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
+
+typedef struct __PACKED _UDISK_BOC_CSW
+{ /* status of BulkOnly USB-FlashDisk */
+    UINT32 mCBW_Sig;
+    UINT32 mCBW_Tag;
+    UINT32 mCSW_Residue; /* return: remainder bytes */ /* uppest byte of remainder length, always is 0 */
+    UINT8  mCSW_Status;                                /* return: result status */
+} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
+
+extern PUINT8 pEP0_RAM_Addr; //ep0(64)
+extern PUINT8 pEP1_RAM_Addr; //ep1_out(64)+ep1_in(64)
+extern PUINT8 pEP2_RAM_Addr; //ep2_out(64)+ep2_in(64)
+extern PUINT8 pEP3_RAM_Addr; //ep3_out(64)+ep3_in(64)
+extern PUINT8 pEP4_RAM_Addr; //ep4_out(64)+ep4_in(64)
+extern PUINT8 pEP5_RAM_Addr; //ep5_out(64)+ep5_in(64)
+extern PUINT8 pEP6_RAM_Addr; //ep6_out(64)+ep6_in(64)
+extern PUINT8 pEP7_RAM_Addr; //ep7_out(64)+ep7_in(64)
+
+#define pSetupReqPak        ((PUSB_SETUP_REQ)pEP0_RAM_Addr)
+#define pEP0_DataBuf        (pEP0_RAM_Addr)
+#define pEP1_OUT_DataBuf    (pEP1_RAM_Addr)
+#define pEP1_IN_DataBuf     (pEP1_RAM_Addr + 64)
+#define pEP2_OUT_DataBuf    (pEP2_RAM_Addr)
+#define pEP2_IN_DataBuf     (pEP2_RAM_Addr + 64)
+#define pEP3_OUT_DataBuf    (pEP3_RAM_Addr)
+#define pEP3_IN_DataBuf     (pEP3_RAM_Addr + 64)
+#define pEP4_OUT_DataBuf    (pEP4_RAM_Addr)
+#define pEP4_IN_DataBuf     (pEP4_RAM_Addr + 64)
+#define pEP5_OUT_DataBuf    (pEP5_RAM_Addr)
+#define pEP5_IN_DataBuf     (pEP5_RAM_Addr + 64)
+#define pEP6_OUT_DataBuf    (pEP6_RAM_Addr)
+#define pEP6_IN_DataBuf     (pEP6_RAM_Addr + 64)
+#define pEP7_OUT_DataBuf    (pEP7_RAM_Addr)
+#define pEP7_IN_DataBuf     (pEP7_RAM_Addr + 64)
+
+void USB_DeviceInit(void);
+void USB_DevTransProcess(void);
+
+void DevEP1_OUT_Deal(UINT8 l);
+void DevEP2_OUT_Deal(UINT8 l);
+void DevEP3_OUT_Deal(UINT8 l);
+void DevEP4_OUT_Deal(UINT8 l);
+void DevEP5_OUT_Deal(UINT8 l);
+void DevEP6_OUT_Deal(UINT8 l);
+void DevEP7_OUT_Deal(UINT8 l);
+
+void DevEP1_IN_Deal(UINT8 l);
+void DevEP2_IN_Deal(UINT8 l);
+void DevEP3_IN_Deal(UINT8 l);
+void DevEP4_IN_Deal(UINT8 l);
+void DevEP5_IN_Deal(UINT8 l);
+void DevEP6_IN_Deal(UINT8 l);
+void DevEP7_IN_Deal(UINT8 l);
+
+#define EP1_GetINSta()    (R8_UEP1_CTRL & UEP_T_RES_NAK)
+#define EP2_GetINSta()    (R8_UEP2_CTRL & UEP_T_RES_NAK)
+#define EP3_GetINSta()    (R8_UEP3_CTRL & UEP_T_RES_NAK)
+#define EP4_GetINSta()    (R8_UEP4_CTRL & UEP_T_RES_NAK)
+#define EP5_GetINSta()    (R8_UEP5_CTRL & UEP_T_RES_NAK)
+#define EP6_GetINSta()    (R8_UEP6_CTRL & UEP_T_RES_NAK)
+#define EP7_GetINSta()    (R8_UEP7_CTRL & UEP_T_RES_NAK)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __USB_TYPE__

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_usb_host.h

@@ -0,0 +1,96 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_usb_host.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the USB
+ *                      Host firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_USBHOST_H
+#define __CH32V10x_USBHOST_H
+
+#include "ch32v10x_usb.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ERR_SUCCESS            0x00
+#define ERR_USB_CONNECT        0x15
+#define ERR_USB_DISCON         0x16
+#define ERR_USB_BUF_OVER       0x17
+#define ERR_USB_DISK_ERR       0x1F
+#define ERR_USB_TRANSFER       0x20
+#define ERR_USB_UNSUPPORT      0xFB
+#define ERR_USB_UNKNOWN        0xFE
+#define ERR_AOA_PROTOCOL       0x41
+
+#define ROOT_DEV_DISCONNECT    0
+#define ROOT_DEV_CONNECTED     1
+#define ROOT_DEV_FAILED        2
+#define ROOT_DEV_SUCCESS       3
+#define DEV_TYPE_KEYBOARD      (USB_DEV_CLASS_HID | 0x20)
+#define DEV_TYPE_MOUSE         (USB_DEV_CLASS_HID | 0x30)
+#define DEF_AOA_DEVICE         0xF0
+#define DEV_TYPE_UNKNOW        0xFF
+
+#define HUB_MAX_PORTS          4
+#define WAIT_USB_TOUT_200US    3000
+
+typedef struct
+{
+    UINT8  DeviceStatus;
+    UINT8  DeviceAddress;
+    UINT8  DeviceSpeed;
+    UINT8  DeviceType;
+    UINT16 DeviceVID;
+    UINT16 DevicePID;
+    UINT8  GpVar[4];
+    UINT8  GpHUBPortNum;
+} _RootHubDev;
+
+extern _RootHubDev ThisUsbDev;
+extern UINT8       UsbDevEndp0Size;
+extern UINT8       FoundNewDev;
+
+extern PUINT8 pHOST_RX_RAM_Addr;
+extern PUINT8 pHOST_TX_RAM_Addr;
+#define pSetupReq    ((PUSB_SETUP_REQ)pHOST_TX_RAM_Addr)
+
+extern const UINT8 SetupGetDevDescr[];
+extern const UINT8 SetupGetCfgDescr[];
+extern const UINT8 SetupSetUsbAddr[];
+extern const UINT8 SetupSetUsbConfig[];
+extern const UINT8 SetupSetUsbInterface[];
+extern const UINT8 SetupClrEndpStall[];
+
+void  DisableRootHubPort(void);
+UINT8 AnalyzeRootHub(void);
+void  SetHostUsbAddr(UINT8 addr);
+void  SetUsbSpeed(UINT8 FullSpeed);
+void  ResetRootHubPort(void);
+UINT8 EnableRootHubPort(void);
+void  SelectHubPort(UINT8 HubPortIndex);
+UINT8 WaitUSB_Interrupt(void);
+UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout);
+UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen);
+void  CopySetupReqPkg(const UINT8 *pReqPkt);
+UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf);
+UINT8 CtrlGetConfigDescr(PUINT8 DataBuf);
+UINT8 CtrlSetUsbAddress(UINT8 addr);
+UINT8 CtrlSetUsbConfig(UINT8 cfg);
+UINT8 CtrlClearEndpStall(UINT8 endp);
+UINT8 CtrlSetUsbIntercace(UINT8 cfg);
+
+void  USB_HostInit(void);
+UINT8 InitRootDevice(PUINT8 DataBuf);
+UINT8 HubGetPortStatus(UINT8 HubPortIndex);                       // 查询HUB端口状态,返回在TxBuffer中
+UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt);   // 设置HUB端口特性
+UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt); // 清除HUB端口特性
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_USBHOST_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/inc/ch32v10x_wwdg.h

@@ -0,0 +1,39 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_wwdg.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for the WWDG
+ *                      firmware library.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_WWDG_H
+#define __CH32V10x_WWDG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "ch32v10x.h"
+
+/* WWDG_Prescaler */
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+
+void       WWDG_DeInit(void);
+void       WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void       WWDG_SetWindowValue(uint8_t WindowValue);
+void       WWDG_EnableIT(void);
+void       WWDG_SetCounter(uint8_t Counter);
+void       WWDG_Enable(uint8_t Counter);
+FlagStatus WWDG_GetFlagStatus(void);
+void       WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CH32V10x_WWDG_H */

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_adc.c

@@ -0,0 +1,1145 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_adc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the ADC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_adc.h"
+#include "ch32v10x_rcc.h"
+
+/* ADC DISCNUM mask */
+#define CTLR1_DISCNUM_Reset              ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CTLR1_DISCEN_Set                 ((uint32_t)0x00000800)
+#define CTLR1_DISCEN_Reset               ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CTLR1_JAUTO_Set                  ((uint32_t)0x00000400)
+#define CTLR1_JAUTO_Reset                ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CTLR1_JDISCEN_Set                ((uint32_t)0x00001000)
+#define CTLR1_JDISCEN_Reset              ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CTLR1_AWDCH_Reset                ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTLR1_AWDMode_Reset              ((uint32_t)0xFF3FFDFF)
+
+/* CTLR1 register Mask */
+#define CTLR1_CLEAR_Mask                 ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CTLR2_ADON_Set                   ((uint32_t)0x00000001)
+#define CTLR2_ADON_Reset                 ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTLR2_DMA_Set                    ((uint32_t)0x00000100)
+#define CTLR2_DMA_Reset                  ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CTLR2_RSTCAL_Set                 ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTLR2_CAL_Set                    ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CTLR2_SWSTART_Set                ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CTLR2_EXTTRIG_Set                ((uint32_t)0x00100000)
+#define CTLR2_EXTTRIG_Reset              ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTLR2_EXTTRIG_SWSTART_Set        ((uint32_t)0x00500000)
+#define CTLR2_EXTTRIG_SWSTART_Reset      ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CTLR2_JEXTSEL_Reset              ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CTLR2_JEXTTRIG_Set               ((uint32_t)0x00008000)
+#define CTLR2_JEXTTRIG_Reset             ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CTLR2_JSWSTART_Set               ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTLR2_JEXTTRIG_JSWSTART_Set      ((uint32_t)0x00208000)
+#define CTLR2_JEXTTRIG_JSWSTART_Reset    ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTLR2_TSVREFE_Set                ((uint32_t)0x00800000)
+#define CTLR2_TSVREFE_Reset              ((uint32_t)0xFF7FFFFF)
+
+/* CTLR2 register Mask */
+#define CTLR2_CLEAR_Mask                 ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define RSQR3_SQ_Set                     ((uint32_t)0x0000001F)
+#define RSQR2_SQ_Set                     ((uint32_t)0x0000001F)
+#define RSQR1_SQ_Set                     ((uint32_t)0x0000001F)
+
+/* RSQR1 register Mask */
+#define RSQR1_CLEAR_Mask                 ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define ISQR_JSQ_Set                     ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define ISQR_JL_Set                      ((uint32_t)0x00300000)
+#define ISQR_JL_Reset                    ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SAMPTR1_SMP_Set                  ((uint32_t)0x00000007)
+#define SAMPTR2_SMP_Set                  ((uint32_t)0x00000007)
+
+/* ADC IDATARx registers offset */
+#define IDATAR_Offset                    ((uint8_t)0x28)
+
+/* ADC1 RDATAR register base address */
+#define RDATAR_ADDRESS                   ((uint32_t)0x4001244C)
+
+/*********************************************************************
+ * @fn      ADC_DeInit
+ *
+ * @brief   Deinitializes the ADCx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  none
+ */
+void ADC_DeInit(ADC_TypeDef *ADCx)
+{
+    if(ADCx == ADC1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_Init
+ *
+ * @brief   Initializes the ADCx peripheral according to the specified
+ *        parameters in the ADC_InitStruct.
+ *
+ * @param   ADCx - where x can be 1  to select the ADC peripheral.
+ *          ADC_InitStruct - pointer to an ADC_InitTypeDef structure that
+ *        contains the configuration information for the specified ADC
+ *        peripheral.
+ *
+ * @return  none
+ */
+void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct)
+{
+    uint32_t tmpreg1 = 0;
+    uint8_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->CTLR1;
+    tmpreg1 &= CTLR1_CLEAR_Mask;
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8));
+    ADCx->CTLR1 = tmpreg1;
+
+    tmpreg1 = ADCx->CTLR2;
+    tmpreg1 &= CTLR2_CLEAR_Mask;
+    tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv |
+            ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+    ADCx->CTLR2 = tmpreg1;
+
+    tmpreg1 = ADCx->RSQR1;
+    tmpreg1 &= RSQR1_CLEAR_Mask;
+    tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1);
+    tmpreg1 |= (uint32_t)tmpreg2 << 20;
+    ADCx->RSQR1 = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_StructInit
+ *
+ * @brief   Fills each ADC_InitStruct member with its default value.
+ *
+ * @param   ADC_InitStruct - pointer to an ADC_InitTypeDef structure that
+ *        contains the configuration information for the specified ADC
+ *        peripheral.
+ *
+ * @return  none
+ */
+void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct)
+{
+    ADC_InitStruct->ADC_Mode = ADC_Mode_Independent;
+    ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+    ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+    ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+    ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+    ADC_InitStruct->ADC_NbrOfChannel = 1;
+}
+
+/*********************************************************************
+ * @fn      ADC_Cmd
+ *
+ * @brief   Enables or disables the specified ADC peripheral.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_ADON_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_ADON_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_DMACmd
+ *
+ * @brief   Enables or disables the specified ADC DMA request.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_DMA_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_DMA_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ITConfig
+ *
+ * @brief   Enables or disables the specified ADC interrupts.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt sources to be enabled or disabled.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState)
+{
+    uint8_t itmask = 0;
+
+    itmask = (uint8_t)ADC_IT;
+
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= itmask;
+    }
+    else
+    {
+        ADCx->CTLR1 &= (~(uint32_t)itmask);
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ResetCalibration
+ *
+ * @brief   Resets the selected ADC calibration registers.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  none
+ */
+void ADC_ResetCalibration(ADC_TypeDef *ADCx)
+{
+    ADCx->CTLR2 |= CTLR2_RSTCAL_Set;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetResetCalibrationStatus
+ *
+ * @brief   Gets the selected ADC reset calibration registers status.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_StartCalibration
+ *
+ * @brief   Starts the selected ADC calibration process.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  None
+ */
+void ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+    ADCx->CTLR2 |= CTLR2_CAL_Set;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetCalibrationStatus
+ *
+ * @brief   Gets the selected ADC calibration status.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_SoftwareStartConvCmd
+ *
+ * @brief   Enables or disables the selected ADC software start conversion.
+ *
+ * @param   ADCx - where x can be 1 or 2 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetSoftwareStartConvStatus
+ *
+ * @brief   Gets the selected ADC Software start conversion Status.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_DiscModeChannelCountConfig
+ *
+ * @brief   Configures the discontinuous mode for the selected ADC regular
+ *        group channel.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          Number - specifies the discontinuous mode regular channel
+ *            count value(1-8).
+ *
+ * @return  None
+ */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->CTLR1;
+    tmpreg1 &= CTLR1_DISCNUM_Reset;
+    tmpreg2 = Number - 1;
+    tmpreg1 |= tmpreg2 << 13;
+    ADCx->CTLR1 = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_DiscModeCmd
+ *
+ * @brief   Enables or disables the discontinuous mode on regular group
+ *        channel for the specified ADC.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_DISCEN_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_DISCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_RegularChannelConfig
+ *
+ * @brief   Configures for the selected ADC regular channel its corresponding
+ *        rank in the sequencer and its sample time.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *          Rank - The rank in the regular group sequencer.
+ *            This parameter must be between 1 to 16.
+ *          ADC_SampleTime - The sample time value to be set for the selected channel.
+ *            ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles.
+ *            ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles.
+ *            ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles.
+ *            ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles.
+ *            ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles.
+ *            ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles.
+ *            ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles.
+ *            ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles.
+ *
+ * @return  None
+ */
+void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+    if(ADC_Channel > ADC_Channel_9)
+    {
+        tmpreg1 = ADCx->SAMPTR1;
+        tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR1 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->SAMPTR2;
+        tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel);
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR2 = tmpreg1;
+    }
+
+    if(Rank < 7)
+    {
+        tmpreg1 = ADCx->RSQR3;
+        tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR3 = tmpreg1;
+    }
+    else if(Rank < 13)
+    {
+        tmpreg1 = ADCx->RSQR2;
+        tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR2 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->RSQR1;
+        tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+        tmpreg1 |= tmpreg2;
+        ADCx->RSQR1 = tmpreg1;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigConvCmd
+ *
+ * @brief   Enables or disables the ADCx conversion through external trigger.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_EXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetConversionValue
+ *
+ * @brief   Returns the last ADCx conversion result data for regular channel.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  ADCx->RDATAR - The Data conversion value.
+ */
+uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx)
+{
+    return (uint16_t)ADCx->RDATAR;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetDualModeConversionValue
+ *
+ * @brief   Returns the last ADC1 and ADC2 conversion result data in dual mode.
+ *
+ * @return  RDATAR_ADDRESS - The Data conversion value.
+ */
+uint32_t ADC_GetDualModeConversionValue(void)
+{
+    return (*(__IO uint32_t *)RDATAR_ADDRESS);
+}
+
+/*********************************************************************
+ * @fn      ADC_AutoInjectedConvCmd
+ *
+ * @brief   Enables or disables the selected ADC automatic injected group
+ *        conversion after regular one.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_JAUTO_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_JAUTO_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedDiscModeCmd
+ *
+ * @brief   Enables or disables the discontinuous mode for injected group
+ *        channel for the specified ADC.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR1 |= CTLR1_JDISCEN_Set;
+    }
+    else
+    {
+        ADCx->CTLR1 &= CTLR1_JDISCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigInjectedConvConfig
+ *
+ * @brief   Configures the ADCx external trigger for injected channels conversion.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_ExternalTrigInjecConv - specifies the ADC trigger to start
+ *        injected conversion.
+ *            ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected.
+ *            ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected.
+ *            ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected.
+ *            ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected.
+ *            ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt
+ *        line 15 event selected.
+ *            ADC_ExternalTrigInjecConv_None: Injected conversion started
+ *        by software and not by external trigger.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR2;
+    tmpreg &= CTLR2_JEXTSEL_Reset;
+    tmpreg |= ADC_ExternalTrigInjecConv;
+    ADCx->CTLR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_ExternalTrigInjectedConvCmd
+ *
+ * @brief   Enables or disables the ADCx injected channels conversion through
+ *        external trigger.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_SoftwareStartInjectedConvCmd
+ *
+ * @brief   Enables or disables the selected ADC start of the injected
+ *        channels conversion.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  None
+ */
+void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set;
+    }
+    else
+    {
+        ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetSoftwareStartInjectedConvCmdStatus
+ *
+ * @brief   Gets the selected ADC Software start injected conversion Status.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return  bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedChannelConfig
+ *
+ * @brief   Configures for the selected ADC injected channel its corresponding
+ *        rank in the sequencer and its sample time.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *          Rank - The rank in the regular group sequencer.
+ *            This parameter must be between 1 to 4.
+ *          ADC_SampleTime - The sample time value to be set for the selected channel.
+ *            ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles.
+ *            ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles.
+ *            ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles.
+ *            ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles.
+ *            ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles.
+ *            ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles.
+ *            ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles.
+ *            ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles.
+ *
+ * @return  None
+ */
+void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+    uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+
+    if(ADC_Channel > ADC_Channel_9)
+    {
+        tmpreg1 = ADCx->SAMPTR1;
+        tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10));
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR1 = tmpreg1;
+    }
+    else
+    {
+        tmpreg1 = ADCx->SAMPTR2;
+        tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel);
+        tmpreg1 &= ~tmpreg2;
+        tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+        tmpreg1 |= tmpreg2;
+        ADCx->SAMPTR2 = tmpreg1;
+    }
+
+    tmpreg1 = ADCx->ISQR;
+    tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20;
+    tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    tmpreg1 &= ~tmpreg2;
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+    tmpreg1 |= tmpreg2;
+    ADCx->ISQR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_InjectedSequencerLengthConfig
+ *
+ * @brief   Configures the sequencer length for injected channels.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          Length - The sequencer length.
+ *            This parameter must be a number between 1 to 4.
+ *
+ * @return  None
+ */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length)
+{
+    uint32_t tmpreg1 = 0;
+    uint32_t tmpreg2 = 0;
+
+    tmpreg1 = ADCx->ISQR;
+    tmpreg1 &= ISQR_JL_Reset;
+    tmpreg2 = Length - 1;
+    tmpreg1 |= tmpreg2 << 20;
+    ADCx->ISQR = tmpreg1;
+}
+
+/*********************************************************************
+ * @fn      ADC_SetInjectedOffset
+ *
+ * @brief   Set the injected channels conversion value offset.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_InjectedChannel: the ADC injected channel to set its offset.
+ *            ADC_InjectedChannel_1 - Injected Channel1 selected.
+ *            ADC_InjectedChannel_2 - Injected Channel2 selected.
+ *            ADC_InjectedChannel_3 - Injected Channel3 selected.
+ *            ADC_InjectedChannel_4 - Injected Channel4 selected.
+ *          Offset - the offset value for the selected ADC injected channel.
+ *            This parameter must be a 12bit value.
+ *
+ * @return  None
+ */
+void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel;
+
+    *(__IO uint32_t *)tmp = (uint32_t)Offset;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetInjectedConversionValue
+ *
+ * @brief   Returns the ADC injected channel conversion result.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_InjectedChannel - the ADC injected channel to set its offset.
+ *            ADC_InjectedChannel_1 - Injected Channel1 selected.
+ *            ADC_InjectedChannel_2 - Injected Channel2 selected.
+ *            ADC_InjectedChannel_3 - Injected Channel3 selected.
+ *            ADC_InjectedChannel_4 - Injected Channel4 selected.
+ *
+ * @return  tmp - The Data conversion value.
+ */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)ADCx;
+    tmp += ADC_InjectedChannel + IDATAR_Offset;
+
+    return (uint16_t)(*(__IO uint32_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogCmd
+ *
+ * @brief   Enables or disables the analog watchdog on single/all regular
+ *        or injected channels.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_AnalogWatchdog - the ADC analog watchdog configuration.
+ *            ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a
+ *        single regular channel.
+ *            ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a
+ *        single injected channel.
+ *            ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog
+ *        on a single regular or injected channel.
+ *            ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on  all
+ *        regular channel.
+ *            ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on  all
+ *        injected channel.
+ *            ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on
+ *        all regular and injected channels.
+ *            ADC_AnalogWatchdog_None - No channel guarded by the analog
+ *        watchdog.
+ *
+ * @return  none
+ */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR1;
+    tmpreg &= CTLR1_AWDMode_Reset;
+    tmpreg |= ADC_AnalogWatchdog;
+    ADCx->CTLR1 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogThresholdsConfig
+ *
+ * @brief   Configures the high and low thresholds of the analog watchdog.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          HighThreshold - the ADC analog watchdog High threshold value.
+ *            This parameter must be a 12bit value.
+ *          LowThreshold - the ADC analog watchdog Low threshold value.
+ *            This parameter must be a 12bit value.
+ *
+ * @return  none
+ */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+    ADCx->WDHTR = HighThreshold;
+    ADCx->WDLTR = LowThreshold;
+}
+
+/*********************************************************************
+ * @fn      ADC_AnalogWatchdogSingleChannelConfig
+ *
+ * @brief   Configures the analog watchdog guarded single channel.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_Channel - the ADC channel to configure.
+ *            ADC_Channel_0 - ADC Channel0 selected.
+ *            ADC_Channel_1 - ADC Channel1 selected.
+ *            ADC_Channel_2 - ADC Channel2 selected.
+ *            ADC_Channel_3 - ADC Channel3 selected.
+ *            ADC_Channel_4 - ADC Channel4 selected.
+ *            ADC_Channel_5 - ADC Channel5 selected.
+ *            ADC_Channel_6 - ADC Channel6 selected.
+ *            ADC_Channel_7 - ADC Channel7 selected.
+ *            ADC_Channel_8 - ADC Channel8 selected.
+ *            ADC_Channel_9 - ADC Channel9 selected.
+ *            ADC_Channel_10 - ADC Channel10 selected.
+ *            ADC_Channel_11 - ADC Channel11 selected.
+ *            ADC_Channel_12 - ADC Channel12 selected.
+ *            ADC_Channel_13 - ADC Channel13 selected.
+ *            ADC_Channel_14 - ADC Channel14 selected.
+ *            ADC_Channel_15 - ADC Channel15 selected.
+ *            ADC_Channel_16 - ADC Channel16 selected.
+ *            ADC_Channel_17 - ADC Channel17 selected.
+ *
+ * @return  None
+ */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = ADCx->CTLR1;
+    tmpreg &= CTLR1_AWDCH_Reset;
+    tmpreg |= ADC_Channel;
+    ADCx->CTLR1 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      ADC_TempSensorVrefintCmd
+ *
+ * @brief   Enables or disables the temperature sensor and Vrefint channel.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        ADC1->CTLR2 |= CTLR2_TSVREFE_Set;
+    }
+    else
+    {
+        ADC1->CTLR2 &= CTLR2_TSVREFE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      ADC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified ADC flag is set or not.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_FLAG - specifies the flag to check.
+ *            ADC_FLAG_AWD - Analog watchdog flag.
+ *            ADC_FLAG_EOC - End of conversion flag.
+ *            ADC_FLAG_JEOC - End of injected group conversion flag.
+ *            ADC_FLAG_JSTRT - Start of injected group conversion flag.
+ *            ADC_FLAG_STRT - Start of regular group conversion flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_ClearFlag
+ *
+ * @brief   Clears the ADCx's pending flags.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_FLAG - specifies the flag to clear.
+ *            ADC_FLAG_AWD - Analog watchdog flag.
+ *            ADC_FLAG_EOC - End of conversion flag.
+ *            ADC_FLAG_JEOC - End of injected group conversion flag.
+ *            ADC_FLAG_JSTRT - Start of injected group conversion flag.
+ *            ADC_FLAG_STRT - Start of regular group conversion flag.
+ *
+ * @return  none
+ */
+void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG)
+{
+    ADCx->STATR = ~(uint32_t)ADC_FLAG;
+}
+
+/*********************************************************************
+ * @fn      ADC_GetITStatus
+ *
+ * @brief   Checks whether the specified ADC interrupt has occurred or not.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt source to check.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *
+ * @return  ITStatus: SET or RESET.
+ */
+ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t itmask = 0, enablestatus = 0;
+
+    itmask = ADC_IT >> 8;
+    enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT);
+
+    if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      ADC_ClearITPendingBit
+ *
+ * @brief   Clears the ADCx's interrupt pending bits.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *          ADC_IT - specifies the ADC interrupt pending bit to clear.
+ *            ADC_IT_EOC - End of conversion interrupt mask.
+ *            ADC_IT_AWD - Analog watchdog interrupt mask.
+ *            ADC_IT_JEOC - End of injected conversion interrupt mask.
+ *
+ * @return  none
+ */
+void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT)
+{
+    uint8_t itmask = 0;
+
+    itmask = (uint8_t)(ADC_IT >> 8);
+    ADCx->STATR = ~(uint32_t)itmask;
+}
+
+/*********************************************************************
+ * @fn      TempSensor_Volt_To_Temper
+ *
+ * @brief   Internal Temperature Sensor Voltage to temperature.
+ *
+ * @param   Value - Voltage Value(mv).
+ *
+ * @return  Temper - Temperature Value.
+ */
+s32 TempSensor_Volt_To_Temper(s32 Value)
+{
+    s32 Temper, Refer_Volt, Refer_Temper;
+    s32 k = 43;
+
+    Refer_Volt = (s32)((*(u32 *)0x1FFFF898) & 0x0000FFFF);
+    Refer_Temper = (s32)(((*(u32 *)0x1FFFF898) >> 16) & 0x0000FFFF);
+
+    Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k;
+
+    return Temper;
+}
+
+/*********************************************************************
+ * @fn      Get_CalibrationValue
+ *
+ * @brief   Get ADCx Calibration Value.
+ *
+ * @param   ADCx - where x can be 1 to select the ADC peripheral.
+ *
+ * @return  CalibrationValue
+ */
+int16_t Get_CalibrationValue(ADC_TypeDef *ADCx)
+{
+    __IO uint8_t  i, j;
+    uint16_t buf[10];
+    __IO uint16_t t;
+
+    for(i = 0; i < 10; i++){
+        ADC_ResetCalibration(ADCx);
+        while(ADC_GetResetCalibrationStatus(ADCx));
+        ADC_StartCalibration(ADCx);
+        while(ADC_GetCalibrationStatus(ADCx));
+        buf[i] = ADCx->RDATAR;
+    }
+
+    for(i = 0; i < 10; i++){
+        for(j = 0; j < 10; j++){
+            if(buf[j] > buf[j + 1]){
+                t = buf[j];
+                buf[j] = buf[j + 1];
+                buf[j] = t;
+            }
+        }
+    }
+
+    t = 0;
+    for(i = 0; i < 6; i++){
+        t += buf[i + 2];
+    }
+
+    t = (t / 6) + ((t % 6) / 3);
+
+    return (int16_t)(2048 - (int16_t)t);
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_bkp.c

@@ -0,0 +1,248 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_bkp.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the BKP firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_bkp.h"
+#include "ch32v10x_rcc.h"
+
+/* BKP registers bit mask */
+
+/* OCTLR register bit mask */
+#define OCTLR_CAL_MASK    ((uint16_t)0xFF80)
+#define OCTLR_MASK        ((uint16_t)0xFC7F)
+
+/*********************************************************************
+ * @fn      BKP_DeInit
+ *
+ * @brief   Deinitializes the BKP peripheral registers to their default reset values.
+ *
+ * @return  none
+ */
+void BKP_DeInit(void)
+{
+    RCC_BackupResetCmd(ENABLE);
+    RCC_BackupResetCmd(DISABLE);
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinLevelConfig
+ *
+ * @brief   Configures the Tamper Pin active level.
+ *
+ * @param   BKP_TamperPinLevel: specifies the Tamper Pin active level.
+ *            BKP_TamperPinLevel_High - Tamper pin active on high level.
+ *            BKP_TamperPinLevel_Low - Tamper pin active on low level.
+ *
+ * @return  none
+ */
+void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
+{
+    if(BKP_TamperPinLevel)
+    {
+        BKP->TPCTLR |= (1 << 1);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 1);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_TamperPinCmd
+ *
+ * @brief   Enables or disables the Tamper Pin activation.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_TamperPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCTLR |= (1 << 0);
+    }
+    else
+    {
+        BKP->TPCTLR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ITConfig
+ *
+ * @brief   Enables or disables the Tamper Pin Interrupt.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void BKP_ITConfig(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        BKP->TPCSR |= (1 << 2);
+    }
+    else
+    {
+        BKP->TPCSR &= ~(1 << 2);
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_RTCOutputConfig
+ *
+ * @brief   Select the RTC output source to output on the Tamper pin.
+ *
+ * @param   BKP_RTCOutputSource - specifies the RTC output source.
+ *            BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
+ *            BKP_RTCOutputSource_CalibClock - output the RTC clock with
+ *        frequency divided by 64 on the Tamper pin.
+ *            BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
+ *        on the Tamper pin.
+ *            BKP_RTCOutputSource_Second - output the RTC Second pulse
+ *        signal on the Tamper pin.
+ *
+ * @return  none
+ */
+void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_MASK;
+    tmpreg |= BKP_RTCOutputSource;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_SetRTCCalibrationValue
+ *
+ * @brief   Sets RTC Clock Calibration value.
+ *
+ * @param   CalibrationValue - specifies the RTC Clock Calibration value.
+ *            This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = BKP->OCTLR;
+    tmpreg &= OCTLR_CAL_MASK;
+    tmpreg |= CalibrationValue;
+    BKP->OCTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      BKP_WriteBackupRegister
+ *
+ * @brief   Writes user data to the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *          Data - data to write.
+ *
+ * @return  none
+ */
+void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+    *(__IO uint32_t *)tmp = Data;
+}
+
+/*********************************************************************
+ * @fn      BKP_ReadBackupRegister
+ *
+ * @brief   Reads data from the specified Data Backup Register.
+ *
+ * @param   BKP_DR - specifies the Data Backup Register.
+ *            This parameter can be BKP_DRx where x=[1, 42].
+ *
+ * @return  none
+ */
+uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)BKP_BASE;
+    tmp += BKP_DR;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      BKP_GetFlagStatus
+ *
+ * @brief   Checks whether the Tamper Pin Event flag is set or not.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus BKP_GetFlagStatus(void)
+{
+    if(BKP->TPCSR & (1 << 8))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearFlag
+ *
+ * @brief   Clears Tamper Pin Event pending flag.
+ *
+ * @return  none
+ */
+void BKP_ClearFlag(void)
+{
+    BKP->TPCSR |= BKP_CTE;
+}
+
+/*********************************************************************
+ * @fn      BKP_GetITStatus
+ *
+ * @brief   Checks whether the Tamper Pin Interrupt has occurred or not.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus BKP_GetITStatus(void)
+{
+    if(BKP->TPCSR & (1 << 9))
+    {
+        return SET;
+    }
+    else
+    {
+        return RESET;
+    }
+}
+
+/*********************************************************************
+ * @fn      BKP_ClearITPendingBit
+ *
+ * @brief   Clears Tamper Pin Interrupt pending bit.
+ *
+ * @return  none
+ */
+void BKP_ClearITPendingBit(void)
+{
+    BKP->TPCSR |= BKP_CTI;
+}
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_crc.c

@@ -0,0 +1,103 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_crc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the CRC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_crc.h"
+
+/*********************************************************************
+ * @fn      CRC_ResetDR
+ *
+ * @brief   Resets the CRC Data register (DR).
+ *
+ * @return  none
+ */
+void CRC_ResetDR(void)
+{
+    CRC->CTLR = CRC_CTLR_RESET;
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given data word(32-bit).
+ *
+ * @param   Data - data word(32-bit) to compute its CRC.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+    CRC->DATAR = Data;
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_CalcBlockCRC
+ *
+ * @brief   Computes the 32-bit CRC of a given buffer of data word(32-bit).
+ *
+ * @param   pBuffer - pointer to the buffer containing the data to be computed.
+ *          BufferLength - length of the buffer to be computed.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+    uint32_t index = 0;
+
+    for(index = 0; index < BufferLength; index++)
+    {
+        CRC->DATAR = pBuffer[index];
+    }
+
+    return (CRC->DATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_GetCRC
+ *
+ * @brief   Returns the current CRC value.
+ *
+ * @return  32-bit CRC.
+ */
+uint32_t CRC_GetCRC(void)
+{
+    return (CRC->IDATAR);
+}
+
+/*********************************************************************
+ * @fn      CRC_SetIDRegister
+ *
+ * @brief   Stores a 8-bit data in the Independent Data(ID) register.
+ *
+ * @param   IDValue - 8-bit value to be stored in the ID register.
+ *
+ * @return  none
+ */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+    CRC->IDATAR = IDValue;
+}
+
+/*********************************************************************
+ * @fn      CRC_GetIDRegister
+ *
+ * @brief   Returns the 8-bit data stored in the Independent Data(ID) register.
+ *
+ * @return  8-bit value of the ID register.
+ */
+uint8_t CRC_GetIDRegister(void)
+{
+    return (CRC->IDATAR);
+}
+
+
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_dbgmcu.c

@@ -0,0 +1,64 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_dbgmcu.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the DBGMCU firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ****************************************************************************************/
+#include "ch32v10x_dbgmcu.h"
+
+/*********************************************************************
+ * @fn      DBGMCU_Config
+ *
+ * @brief   Configures the specified peripheral and low power mode behavior
+ *        when the MCU under Debug mode.
+ *
+ * @param   DBGMCU_Periph - specifies the peripheral and low power mode.
+ *            DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
+ *            DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
+ *            DBGMCU_I2C1_SMBUS_TIMEOUT - I2C1 SMBUS timeout mode stopped when Core is halted
+ *            DBGMCU_I2C2_SMBUS_TIMEOUT - I2C2 SMBUS timeout mode stopped when Core is halted
+ *            DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
+ *            DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
+ *            DBGMCU_TIM3_STOP - TIM3 counter stopped when Core is halted
+ *            DBGMCU_TIM4_STOP - TIM4 counter stopped when Core is halted
+ *            DBGMCU_SLEEP - Keep debugger connection during SLEEP mode
+ *            DBGMCU_STOP - Keep debugger connection during STOP mode
+ *            DBGMCU_STANDBY - Keep debugger connection during STANDBY mode
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+    if((DBGMCU_Periph == DBGMCU_SLEEP) || (DBGMCU_Periph == DBGMCU_STOP) || (DBGMCU_Periph == DBGMCU_STANDBY))
+    {
+        if(NewState != DISABLE)
+        {
+            DBGMCU->CFGR1 |= DBGMCU_Periph;
+        }
+        else
+        {
+            DBGMCU->CFGR1 &= ~DBGMCU_Periph;
+        }
+    }
+    else
+    {
+        if(NewState != DISABLE)
+        {
+            DBGMCU->CFGR0 |= DBGMCU_Periph;
+        }
+        else
+        {
+            DBGMCU->CFGR0 &= ~DBGMCU_Periph;
+        }
+    }
+
+
+
+
+
+
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_dma.c

@@ -0,0 +1,550 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_dma.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the DMA firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_dma.h"
+#include "ch32v10x_rcc.h"
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask    ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA1_Channel2_IT_Mask    ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA1_Channel3_IT_Mask    ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA1_Channel4_IT_Mask    ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA1_Channel5_IT_Mask    ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA1_Channel6_IT_Mask    ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA1_Channel7_IT_Mask    ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_Channel1_IT_Mask    ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA2_Channel2_IT_Mask    ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA2_Channel3_IT_Mask    ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA2_Channel4_IT_Mask    ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA2_Channel5_IT_Mask    ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+
+/* DMA2 FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CFGR_CLEAR_Mask          ((uint32_t)0xFFFF800F)
+
+/*********************************************************************
+ * @fn      DMA_DeInit
+ *
+ * @brief   Deinitializes the DMAy Channelx registers to their default
+ *        reset values.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    DMAy_Channelx->CFGR = 0;
+    DMAy_Channelx->CNTR = 0;
+    DMAy_Channelx->PADDR = 0;
+    DMAy_Channelx->MADDR = 0;
+    if(DMAy_Channelx == DMA1_Channel1)
+    {
+        DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel2)
+    {
+        DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel3)
+    {
+        DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel4)
+    {
+        DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel5)
+    {
+        DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel6)
+    {
+        DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA1_Channel7)
+    {
+        DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel1)
+    {
+        DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel2)
+    {
+        DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel3)
+    {
+        DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
+    }
+    else if(DMAy_Channelx == DMA2_Channel4)
+    {
+        DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
+    }
+    else
+    {
+        if(DMAy_Channelx == DMA2_Channel5)
+        {
+            DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_Init
+ *
+ * @brief   Initializes the DMAy Channelx according to the specified
+ *        parameters in the DMA_InitStruct.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = DMAy_Channelx->CFGR;
+    tmpreg &= CFGR_CLEAR_Mask;
+    tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+              DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+              DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+              DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+    DMAy_Channelx->CFGR = tmpreg;
+    DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
+    DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+    DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/*********************************************************************
+ * @fn      DMA_StructInit
+ *
+ * @brief   Fills each DMA_InitStruct member with its default value.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
+ *        contains the configuration information for the specified DMA Channel.
+ *
+ * @return  none
+ */
+void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
+{
+    DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+    DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+    DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+    DMA_InitStruct->DMA_BufferSize = 0;
+    DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+    DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+    DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+    DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+    DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+    DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+    DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/*********************************************************************
+ * @fn      DMA_Cmd
+ *
+ * @brief   Enables or disables the specified DMAy Channelx.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_ITConfig
+ *
+ * @brief   Enables or disables the specified DMAy Channelx interrupts.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DMA_IT - specifies the DMA interrupts sources to be enabled
+ *        or disabled.
+ *           DMA_IT_TC - Transfer complete interrupt mask
+ *           DMA_IT_HT - Half transfer interrupt mask
+ *           DMA_IT_TE -  Transfer error interrupt mask
+ *          NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        DMAy_Channelx->CFGR |= DMA_IT;
+    }
+    else
+    {
+        DMAy_Channelx->CFGR &= ~DMA_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_SetCurrDataCounter
+ *
+ * @brief   Sets the number of data units in the current DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *          DataNumber - The number of data units in the current DMAy Channelx
+ *        transfer.
+ *
+ * @return  none
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
+{
+    DMAy_Channelx->CNTR = DataNumber;
+}
+
+/*********************************************************************
+ * @fn      DMA_GetCurrDataCounter
+ *
+ * @brief   Returns the number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ *
+ * @param   DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
+ *        1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ *
+ * @return  DataNumber - The number of remaining data units in the current
+ *        DMAy Channelx transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
+{
+    return ((uint16_t)(DMAy_Channelx->CNTR));
+}
+
+/*********************************************************************
+ * @fn      DMA_GetFlagStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx flag is set or not.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    uint32_t   tmpreg = 0;
+
+    if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearFlag
+ *
+ * @brief   Clears the DMAy Channelx's pending flags.
+ *
+ * @param   DMAy_FLAG - specifies the flag to check.
+ *            DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+    if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+    {
+        DMA2->INTFCR = DMAy_FLAG;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_FLAG;
+    }
+}
+
+/*********************************************************************
+ * @fn      DMA_GetITStatus
+ *
+ * @brief   Checks whether the specified DMAy Channelx interrupt has
+ *        occurred or not.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t tmpreg = 0;
+
+    if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+    {
+        tmpreg = DMA2->INTFR;
+    }
+    else
+    {
+        tmpreg = DMA1->INTFR;
+    }
+
+    if((tmpreg & DMAy_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      DMA_ClearITPendingBit
+ *
+ * @brief   Clears the DMAy Channelx's interrupt pending bits.
+ *
+ * @param   DMAy_IT - specifies the DMAy interrupt source to check.
+ *            DMA1_IT_GL1 - DMA1 Channel1 global flag.
+ *            DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
+ *            DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
+ *            DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
+ *            DMA1_IT_GL2 - DMA1 Channel2 global flag.
+ *            DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
+ *            DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
+ *            DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
+ *            DMA1_IT_GL3 - DMA1 Channel3 global flag.
+ *            DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
+ *            DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
+ *            DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
+ *            DMA1_IT_GL4 - DMA1 Channel4 global flag.
+ *            DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
+ *            DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
+ *            DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
+ *            DMA1_IT_GL5 - DMA1 Channel5 global flag.
+ *            DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
+ *            DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
+ *            DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
+ *            DMA1_IT_GL6 - DMA1 Channel6 global flag.
+ *            DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
+ *            DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
+ *            DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
+ *            DMA1_IT_GL7 - DMA1 Channel7 global flag.
+ *            DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
+ *            DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
+ *            DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
+ *            DMA2_IT_GL1 - DMA2 Channel1 global flag.
+ *            DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
+ *            DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
+ *            DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
+ *            DMA2_IT_GL2 - DMA2 Channel2 global flag.
+ *            DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
+ *            DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
+ *            DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
+ *            DMA2_IT_GL3 - DMA2 Channel3 global flag.
+ *            DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
+ *            DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
+ *            DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
+ *            DMA2_IT_GL4 - DMA2 Channel4 global flag.
+ *            DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
+ *            DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
+ *            DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
+ *            DMA2_IT_GL5 - DMA2 Channel5 global flag.
+ *            DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
+ *            DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
+ *            DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
+ *
+ * @return  none
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+    if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+    {
+        DMA2->INTFCR = DMAy_IT;
+    }
+    else
+    {
+        DMA1->INTFCR = DMAy_IT;
+    }
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_exti.c

@@ -0,0 +1,180 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_exti.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the EXTI firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32v10x_exti.h"
+
+/* No interrupt selected */
+#define EXTI_LINENONE    ((uint32_t)0x00000)
+
+/*********************************************************************
+ * @fn      EXTI_DeInit
+ *
+ * @brief   Deinitializes the EXTI peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none.
+ */
+void EXTI_DeInit(void)
+{
+    EXTI->INTENR = 0x00000000;
+    EXTI->EVENR = 0x00000000;
+    EXTI->RTENR = 0x00000000;
+    EXTI->FTENR = 0x00000000;
+    EXTI->INTFR = 0x000FFFFF;
+}
+
+/*********************************************************************
+ * @fn      EXTI_Init
+ *
+ * @brief   Initializes the EXTI peripheral according to the specified
+ *        parameters in the EXTI_InitStruct.
+ *
+ * @param   EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    uint32_t tmp = 0;
+
+    tmp = (uint32_t)EXTI_BASE;
+    if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+    {
+        EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
+        EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
+        if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+        {
+            EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
+            EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
+        }
+        else
+        {
+            tmp = (uint32_t)EXTI_BASE;
+            tmp += EXTI_InitStruct->EXTI_Trigger;
+            *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
+        }
+    }
+    else
+    {
+        tmp += EXTI_InitStruct->EXTI_Mode;
+        *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
+    }
+}
+
+/*********************************************************************
+ * @fn      EXTI_StructInit
+ *
+ * @brief   Fills each EXTI_InitStruct member with its reset value.
+ *
+ * @param   EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
+ *
+ * @return  none.
+ */
+void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
+{
+    EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+    EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+    EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+    EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GenerateSWInterrupt
+ *
+ * @brief   Generates a Software interrupt.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none.
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+    EXTI->SWIEVR |= EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetFlagStatus
+ *
+ * @brief   Checks whether the specified EXTI line flag is set or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+    FlagStatus bitstatus = RESET;
+    if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearFlag
+ *
+ * @brief   Clears the EXTI's line pending flags.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}
+
+/*********************************************************************
+ * @fn      EXTI_GetITStatus
+ *
+ * @brief   Checks whether the specified EXTI line is asserted or not.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = EXTI->INTENR & EXTI_Line;
+    if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      EXTI_ClearITPendingBit
+ *
+ * @brief   Clears the EXTI's line pending bits.
+ *
+ * @param   EXTI_Line - specifies the EXTI lines to be enabled or disabled.
+ *
+ * @return  none
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+    EXTI->INTFR = EXTI_Line;
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_flash.c

@@ -0,0 +1,968 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_flash.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the FLASH firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ***************************************************************************************/
+#include "ch32v10x_flash.h"
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask           ((uint32_t)0x00000038)
+#define ACR_HLFCYA_Mask            ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask            ((uint32_t)0xFFFFFFEF)
+
+/* Flash Access Control Register bits */
+#define ACR_PRFTBS_Mask            ((uint32_t)0x00000020)
+
+/* Flash Control Register bits */
+#define CR_PG_Set                  ((uint32_t)0x00000001)
+#define CR_PG_Reset                ((uint32_t)0x00001FFE)
+#define CR_PER_Set                 ((uint32_t)0x00000002)
+#define CR_PER_Reset               ((uint32_t)0x00001FFD)
+#define CR_MER_Set                 ((uint32_t)0x00000004)
+#define CR_MER_Reset               ((uint32_t)0x00001FFB)
+#define CR_OPTPG_Set               ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset             ((uint32_t)0x00001FEF)
+#define CR_OPTER_Set               ((uint32_t)0x00000020)
+#define CR_OPTER_Reset             ((uint32_t)0x00001FDF)
+#define CR_STRT_Set                ((uint32_t)0x00000040)
+#define CR_LOCK_Set                ((uint32_t)0x00000080)
+#define CR_PAGE_PG                 ((uint32_t)0x00010000)
+#define CR_PAGE_ER                 ((uint32_t)0x00020000)
+#define CR_BUF_LOAD                ((uint32_t)0x00040000)
+#define CR_BUF_RST                 ((uint32_t)0x00080000)
+
+/* FLASH Status Register bits */
+#define SR_BSY                     ((uint32_t)0x00000001)
+#define SR_PGERR                   ((uint32_t)0x00000004)
+#define SR_WRPRTERR                ((uint32_t)0x00000010)
+#define SR_EOP                     ((uint32_t)0x00000020)
+
+/* FLASH Mask */
+#define RDPRT_Mask                 ((uint32_t)0x00000002)
+#define WRP0_Mask                  ((uint32_t)0x000000FF)
+#define WRP1_Mask                  ((uint32_t)0x0000FF00)
+#define WRP2_Mask                  ((uint32_t)0x00FF0000)
+#define WRP3_Mask                  ((uint32_t)0xFF000000)
+#define OB_USER_BFB2               ((uint16_t)0x0008)
+
+/* FLASH Keys */
+#define RDP_Key                    ((uint16_t)0x00A5)
+#define FLASH_KEY1                 ((uint32_t)0x45670123)
+#define FLASH_KEY2                 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS    ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout               ((uint32_t)0x000B0000)
+#define ProgramTimeout             ((uint32_t)0x00002000)
+
+/* Flash Program Vaild Address */
+#define ValidAddrStart             (FLASH_BASE)
+#define ValidAddrEnd               (FLASH_BASE + 0x10000)
+
+/********************************************************************************
+  * @fn            FLASH_SetLatency
+  *
+  * @brief         Sets the code latency value.
+  *
+  * @param         FLASH_Latency - specifies the FLASH Latency value.
+  *                    FLASH_Latency_0 - FLASH Zero Latency cycle
+  *                    FLASH_Latency_1 - FLASH One Latency cycle
+  *                    FLASH_Latency_2 - FLASH Two Latency cycles
+  *
+  * @return         None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = FLASH->ACTLR;
+    tmpreg &= ACR_LATENCY_Mask;
+    tmpreg |= FLASH_Latency;
+    FLASH->ACTLR = tmpreg;
+}
+
+/********************************************************************************
+ * @fn            FLASH_HalfCycleAccessCmd
+ *
+ * @brief          Enables or disables the Half cycle flash access.
+ *
+ * @param          FLASH_HalfCycleAccess - specifies the FLASH Half cycle Access mode.
+ *                   FLASH_HalfCycleAccess_Enable - FLASH Half Cycle Enable
+ *                   FLASH_HalfCycleAccess_Disable - FLASH Half Cycle Disable
+ *
+ * @return         None
+ */
+void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess)
+{
+    FLASH->ACTLR &= ACR_HLFCYA_Mask;
+    FLASH->ACTLR |= FLASH_HalfCycleAccess;
+}
+
+/********************************************************************************
+ * @fn             FLASH_PrefetchBufferCmd
+ *
+ * @brief          Enables or disables the Prefetch Buffer.
+ *
+ * @param          FLASH_PrefetchBuffer - specifies the Prefetch buffer status.
+ *                   FLASH_PrefetchBuffer_Enable - FLASH Prefetch Buffer Enable
+ *                   FLASH_PrefetchBuffer_Disable - FLASH Prefetch Buffer Disable
+ *
+ * @return         None
+ */
+void FLASH_PrefetchBufferCmd(uint32_t FLASH_PrefetchBuffer)
+{
+    FLASH->ACTLR &= ACR_PRFTBE_Mask;
+    FLASH->ACTLR |= FLASH_PrefetchBuffer;
+}
+
+/********************************************************************************
+ * @fn             FLASH_Unlock
+ *
+ * @brief          Unlocks the FLASH Program Erase Controller.
+ *
+ * @return         None
+ */
+void FLASH_Unlock(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/********************************************************************************
+ * @fn             FLASH_UnlockBank1
+ *
+ * @brief          Unlocks the FLASH Bank1 Program Erase Controller.
+ *                 equivalent to FLASH_Unlock function.
+ *
+ * @return         None
+ */
+void FLASH_UnlockBank1(void)
+{
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+}
+
+/********************************************************************************
+ * @fn             FLASH_Lock
+ *
+ * @brief          Locks the FLASH Program Erase Controller.
+ *
+ * @return         None
+ */
+void FLASH_Lock(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/********************************************************************************
+ * @fn             FLASH_LockBank1
+ *
+ * @brief          Locks the FLASH Bank1 Program Erase Controller.
+ *
+ * @return         None
+ */
+void FLASH_LockBank1(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/********************************************************************************
+ * @fn             FLASH_ErasePage
+ *
+ * @brief          Erases a specified FLASH page.
+ *
+ * @param          Page_Address - The page address to be erased.
+ *
+ * @return         FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PER_Set;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_PER_Reset;
+    }
+
+    *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Page_Address & 0xFFFFFFFC) ^ 0x00001000);
+
+    return status;
+}
+
+/********************************************************************************
+ * @fn             FLASH_EraseAllPages
+ *
+ * @brief          Erases all FLASH pages.
+ *
+ * @return         FLASH Status - The returned value can be:FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+
+    return status;
+}
+
+/********************************************************************************
+ * @fn             FLASH_EraseAllBank1Pages
+ *
+ * @brief          Erases all Bank1 FLASH pages.
+ *
+ * @return         FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllBank1Pages(void)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_MER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+
+        status = FLASH_WaitForLastBank1Operation(EraseTimeout);
+
+        FLASH->CTLR &= CR_MER_Reset;
+    }
+    return status;
+}
+
+/********************************************************************************
+ * @fn             FLASH_EraseOptionBytes
+ *
+ * @brief          Erases the FLASH option bytes.
+ *
+ * @return         FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *                 FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseOptionBytes(void)
+{
+    uint16_t rdptmp = RDP_Key;
+
+    FLASH_Status status = FLASH_COMPLETE;
+    if(FLASH_GetReadOutProtectionStatus() != RESET)
+    {
+        rdptmp = 0x00;
+    }
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            OB->RDPR = (uint16_t)rdptmp;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn         FLASH_ProgramWord
+ *
+ * @brief       Programs a word at a specified address.
+ *
+ * @param       Address - specifies the address to be programmed.
+ *              Data - specifies the data to be programmed.
+ *
+ * @return       FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *              FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+    FLASH_Status  status = FLASH_COMPLETE;
+    __IO uint32_t tmp = 0;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+
+        *(__IO uint16_t *)Address = (uint16_t)Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+        if(status == FLASH_COMPLETE)
+        {
+            tmp = Address + 2;
+            *(__IO uint16_t *)tmp = Data >> 16;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+        else
+        {
+            FLASH->CTLR &= CR_PG_Reset;
+        }
+    }
+
+    *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Address & 0xFFFFFFFC) ^ 0x00001000);
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn         FLASH_ProgramHalfWord
+ *
+ * @brief       Programs a half word at a specified address.
+ *
+ * @param       Address - specifies the address to be programmed.
+ *              Data - specifies the data to be programmed.
+ *
+ * @return      FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *             FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_PG_Set;
+        *(__IO uint16_t *)Address = Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        FLASH->CTLR &= CR_PG_Reset;
+    }
+
+    *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Address & 0xFFFFFFFC) ^ 0x00001000);
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn        FLASH_ProgramOptionByteData
+ *
+ * @brief     Programs a half word at a specified Option Byte Data address.
+ *
+ * @param     Address - specifies the address to be programmed.
+ *            Data - specifies the data to be programmed.
+ *
+ * @return    FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *           FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+        FLASH->CTLR |= CR_OPTPG_Set;
+        *(__IO uint16_t *)Address = Data;
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        if(status != FLASH_TIMEOUT)
+        {
+            FLASH->CTLR &= CR_OPTPG_Reset;
+        }
+    }
+
+    *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Address & 0xFFFFFFFC) ^ 0x00001000);
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_EnableWriteProtection
+ *
+ * @brief   Write protects the desired sectors
+ *
+ * @param   FLASH_Sectors - specifies the address of the pages to be write protected.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Pages)
+{
+    uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
+
+    FLASH_Status status = FLASH_COMPLETE;
+
+    FLASH_Pages = (uint32_t)(~FLASH_Pages);
+    WRP0_Data = (uint16_t)(FLASH_Pages & WRP0_Mask);
+    WRP1_Data = (uint16_t)((FLASH_Pages & WRP1_Mask) >> 8);
+    WRP2_Data = (uint16_t)((FLASH_Pages & WRP2_Mask) >> 16);
+    WRP3_Data = (uint16_t)((FLASH_Pages & WRP3_Mask) >> 24);
+
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+        FLASH->CTLR |= CR_OPTPG_Set;
+        if(WRP0_Data != 0xFF)
+        {
+            OB->WRPR0 = WRP0_Data;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+        if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+        {
+            OB->WRPR1 = WRP1_Data;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+        if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
+        {
+            OB->WRPR2 = WRP2_Data;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+
+        if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF))
+        {
+            OB->WRPR3 = WRP3_Data;
+            status = FLASH_WaitForLastOperation(ProgramTimeout);
+        }
+
+        if(status != FLASH_TIMEOUT)
+        {
+            FLASH->CTLR &= CR_OPTPG_Reset;
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ReadOutProtection
+ *
+ * @brief   Enables or disables the read out protection.
+ *
+ * @param   Newstate - new state of the ReadOut Protection(ENABLE or DISABLE).
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+    status = FLASH_WaitForLastOperation(EraseTimeout);
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->OBKEYR = FLASH_KEY1;
+        FLASH->OBKEYR = FLASH_KEY2;
+        FLASH->CTLR |= CR_OPTER_Set;
+        FLASH->CTLR |= CR_STRT_Set;
+        status = FLASH_WaitForLastOperation(EraseTimeout);
+        if(status == FLASH_COMPLETE)
+        {
+            FLASH->CTLR &= CR_OPTER_Reset;
+            FLASH->CTLR |= CR_OPTPG_Set;
+            if(NewState != DISABLE)
+            {
+                OB->RDPR = 0x00;
+            }
+            else
+            {
+                OB->RDPR = RDP_Key;
+            }
+            status = FLASH_WaitForLastOperation(EraseTimeout);
+
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTPG_Reset;
+            }
+        }
+        else
+        {
+            if(status != FLASH_TIMEOUT)
+            {
+                FLASH->CTLR &= CR_OPTER_Reset;
+            }
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_UserOptionByteConfig
+ *
+ * @brief   Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY.
+ *
+ * @param   OB_IWDG - Selects the IWDG mode
+ *            OB_IWDG_SW - Software IWDG selected
+ *            OB_IWDG_HW - Hardware IWDG selected
+ *          OB_STOP - Reset event when entering STOP mode.
+ *            OB_STOP_NoRST - No reset generated when entering in STOP
+ *            OB_STOP_RST - Reset generated when entering in STOP
+ *          OB_STDBY - Reset event when entering Standby mode.
+ *            OB_STDBY_NoRST - No reset generated when entering in STANDBY
+ *            OB_STDBY_RST - Reset generated when entering in STANDBY
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    FLASH->OBKEYR = FLASH_KEY1;
+    FLASH->OBKEYR = FLASH_KEY2;
+    status = FLASH_WaitForLastOperation(ProgramTimeout);
+
+    if(status == FLASH_COMPLETE)
+    {
+        FLASH->CTLR |= CR_OPTPG_Set;
+
+        OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
+
+        status = FLASH_WaitForLastOperation(ProgramTimeout);
+        if(status != FLASH_TIMEOUT)
+        {
+            FLASH->CTLR &= CR_OPTPG_Reset;
+        }
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetUserOptionByte
+ *
+ * @brief   Returns the FLASH User Option Bytes values.
+ *
+ * @return  The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1)
+ *        and RST_STDBY(Bit2).
+ */
+uint32_t FLASH_GetUserOptionByte(void)
+{
+    return (uint32_t)(FLASH->OBR >> 2);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetWriteProtectionOptionByte
+ *
+ * @brief   Returns the FLASH Write Protection Option Bytes Register value.
+ *
+ * @return  The FLASH Write Protection Option Bytes Register value.
+ */
+uint32_t FLASH_GetWriteProtectionOptionByte(void)
+{
+    return (uint32_t)(FLASH->WPR);
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetReadOutProtectionStatus
+ *
+ * @brief   Checks whether the FLASH Read Out Protection Status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetReadOutProtectionStatus(void)
+{
+    FlagStatus readoutstatus = RESET;
+    if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET)
+    {
+        readoutstatus = SET;
+    }
+    else
+    {
+        readoutstatus = RESET;
+    }
+    return readoutstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetPrefetchBufferStatus
+ *
+ * @brief   Checks whether the FLASH Prefetch Buffer status is set or not.
+ *
+ * @return  FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_GetPrefetchBufferStatus(void)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((FLASH->ACTLR & ACR_PRFTBS_Mask) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ITConfig
+ *
+ * @brief   Enables or disables the specified FLASH interrupts.
+ *
+ * @param   FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled.
+ *            FLASH_IT_ERROR - FLASH Error Interrupt
+ *            FLASH_IT_EOP - FLASH end of operation Interrupt
+ *          NewState - new state of the specified Flash interrupts(ENABLE or DISABLE).
+ *
+ * @return  FLASH Prefetch Buffer Status (SET or RESET).
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        FLASH->CTLR |= FLASH_IT;
+    }
+    else
+    {
+        FLASH->CTLR &= ~(uint32_t)FLASH_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetFlagStatus
+ *
+ * @brief   Checks whether the specified FLASH flag is set or not.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flag to check.
+ *            FLASH_FLAG_BSY - FLASH Busy flag
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *            FLASH_FLAG_OPTERR - FLASH Option Byte error flag
+ *
+ * @return  The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(FLASH_FLAG == FLASH_FLAG_OPTERR)
+    {
+        if((FLASH->OBR & FLASH_FLAG_OPTERR) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET)
+        {
+            bitstatus = SET;
+        }
+        else
+        {
+            bitstatus = RESET;
+        }
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_ClearFlag
+ *
+ * @brief   Clears the FLASH's pending flags.
+ *
+ * @param   FLASH_FLAG - specifies the FLASH flags to clear.
+ *            FLASH_FLAG_PGERR - FLASH Program error flag
+ *            FLASH_FLAG_WRPRTERR - FLASH Write protected error flag
+ *            FLASH_FLAG_EOP - FLASH End of Operation flag
+ *
+ * @return  none
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+    FLASH->STATR = FLASH_FLAG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetStatus
+ *
+ * @brief   Returns the FLASH Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_GetBank1Status
+ *
+ * @brief   Returns the FLASH Bank1 Status.
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetBank1Status(void)
+{
+    FLASH_Status flashstatus = FLASH_COMPLETE;
+
+    if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY)
+    {
+        flashstatus = FLASH_BUSY;
+    }
+    else
+    {
+        if((FLASH->STATR & FLASH_FLAG_BANK1_PGERR) != 0)
+        {
+            flashstatus = FLASH_ERROR_PG;
+        }
+        else
+        {
+            if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0)
+            {
+                flashstatus = FLASH_ERROR_WRP;
+            }
+            else
+            {
+                flashstatus = FLASH_COMPLETE;
+            }
+        }
+    }
+    return flashstatus;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastOperation
+ *
+ * @brief   Waits for a Flash operation to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_BUSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_WaitForLastBank1Operation
+ *
+ * @brief   Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur.
+ *
+ * @param   Timeout - FLASH programming Timeout
+ *
+ * @return  FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG,
+ *        FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout)
+{
+    FLASH_Status status = FLASH_COMPLETE;
+
+    status = FLASH_GetBank1Status();
+    while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00))
+    {
+        status = FLASH_GetBank1Status();
+        Timeout--;
+    }
+    if(Timeout == 0x00)
+    {
+        status = FLASH_TIMEOUT;
+    }
+    return status;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Unlock_Fast(void)
+{
+    /* Authorize the FPEC of Bank1 Access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+
+    /* Fast program mode unlock */
+    FLASH->MODEKEYR = FLASH_KEY1;
+    FLASH->MODEKEYR = FLASH_KEY2;
+}
+
+/*********************************************************************
+ * @fn      FLASH_Unlock_Fast
+ *
+ * @brief   Unlocks the Fast Program Erase Mode.
+ *
+ * @return  none
+ */
+void FLASH_Lock_Fast(void)
+{
+    FLASH->CTLR |= CR_LOCK_Set;
+}
+
+/*********************************************************************
+ * @fn      FLASH_BufReset
+ *
+ * @brief   Flash Buffer reset.
+ *
+ * @return  none
+ */
+void FLASH_BufReset(void)
+{
+    FLASH->CTLR |= CR_PAGE_PG;
+    FLASH->CTLR |= CR_BUF_RST;
+    while(FLASH->STATR & SR_BSY)
+        ;
+    FLASH->CTLR &= ~CR_PAGE_PG;
+}
+
+/*********************************************************************
+ * @fn      FLASH_BufLoad
+ *
+ * @brief   Flash Buffer load(128 bit).
+ *
+ * @param   Address - specifies the address to be programmed.
+ *          Data0 - specifies the data0 to be programmed.
+ *          Data1 - specifies the data1 to be programmed.
+ *          Data2 - specifies the data2 to be programmed.
+ *          Data3 - specifies the data3 to be programmed.
+ *
+ * @return  none
+ */
+void FLASH_BufLoad(uint32_t Address, uint32_t Data0, uint32_t Data1, uint32_t Data2, uint32_t Data3)
+{
+    if((Address >= ValidAddrStart) && (Address < ValidAddrEnd))
+    {
+        FLASH->CTLR |= CR_PAGE_PG;
+        *(__IO uint32_t *)(Address + 0x00) = Data0;
+        *(__IO uint32_t *)(Address + 0x04) = Data1;
+        *(__IO uint32_t *)(Address + 0x08) = Data2;
+        *(__IO uint32_t *)(Address + 0x0C) = Data3;
+        FLASH->CTLR |= CR_BUF_LOAD;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_PAGE_PG;
+
+        *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Address & 0xFFFFFFFC) ^ 0x00001000);
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_ErasePage_Fast
+ *
+ * @brief   Erases a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be erased.
+ *
+ * @return  none
+ */
+void FLASH_ErasePage_Fast(uint32_t Page_Address)
+{
+    if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd))
+    {
+        FLASH->CTLR |= CR_PAGE_ER;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_PAGE_ER;
+
+        *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Page_Address & 0xFFFFFFFC) ^ 0x00001000);
+    }
+}
+
+/*********************************************************************
+ * @fn      FLASH_ProgramPage_Fast
+ *
+ * @brief   Program a specified FLASH page (1page = 256Byte).
+ *
+ * @param   Page_Address - The page address to be programed.
+ *
+ * @return  none
+ */
+void FLASH_ProgramPage_Fast(uint32_t Page_Address)
+{
+    if((Page_Address >= ValidAddrStart) && (Page_Address < ValidAddrEnd))
+    {
+        FLASH->CTLR |= CR_PAGE_PG;
+        FLASH->ADDR = Page_Address;
+        FLASH->CTLR |= CR_STRT_Set;
+        while(FLASH->STATR & SR_BSY)
+            ;
+        FLASH->CTLR &= ~CR_PAGE_PG;
+
+        *(__IO uint32_t *)0x40022034 = *(__IO uint32_t *)((Page_Address & 0xFFFFFFFC) ^ 0x00001000);
+    }
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_gpio.c

@@ -0,0 +1,538 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_gpio.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the GPIO firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_gpio.h"
+#include "ch32v10x_rcc.h"
+
+/* MASK */
+#define ECR_PORTPINCONFIG_MASK    ((uint16_t)0xFF80)
+#define LSB_MASK                  ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK      ((uint32_t)0x000F0000)
+#define DBGAFR_SWJCFG_MASK        ((uint32_t)0xF0FFFFFF)
+#define DBGAFR_LOCATION_MASK      ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK       ((uint32_t)0x00100000)
+
+/*********************************************************************
+ * @fn      GPIO_DeInit
+ *
+ * @brief   Deinitializes the GPIOx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_DeInit(GPIO_TypeDef *GPIOx)
+{
+    if(GPIOx == GPIOA)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+    }
+    else if(GPIOx == GPIOB)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+    }
+    else if(GPIOx == GPIOC)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
+    }
+    else if(GPIOx == GPIOD)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
+    }
+    else if(GPIOx == GPIOE)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
+    }
+    else if(GPIOx == GPIOF)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
+    }
+    else
+    {
+        if(GPIOx == GPIOG)
+        {
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
+            RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_AFIODeInit
+ *
+ * @brief   Deinitializes the Alternate Functions (remap, event control
+ *        and EXTI configuration) registers to their default reset values.
+ *
+ * @return  none
+ */
+void GPIO_AFIODeInit(void)
+{
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      GPIO_Init
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
+ *        contains the configuration information for the specified GPIO peripheral.
+ *
+ * @return  none
+ */
+void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
+    uint32_t tmpreg = 0x00, pinmask = 0x00;
+
+    currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
+
+    if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
+    {
+        currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
+    }
+
+    if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
+    {
+        tmpreg = GPIOx->CFGLR;
+
+        for(pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = ((uint32_t)0x01) << pinpos;
+            currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+            if(currentpin == pos)
+            {
+                pos = pinpos << 2;
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= (currentmode << pos);
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BCR = (((uint32_t)0x01) << pinpos);
+                }
+                else
+                {
+                    if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                    {
+                        GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
+                    }
+                }
+            }
+        }
+        GPIOx->CFGLR = tmpreg;
+    }
+
+    if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
+    {
+        tmpreg = GPIOx->CFGHR;
+
+        for(pinpos = 0x00; pinpos < 0x08; pinpos++)
+        {
+            pos = (((uint32_t)0x01) << (pinpos + 0x08));
+            currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
+
+            if(currentpin == pos)
+            {
+                pos = pinpos << 2;
+                pinmask = ((uint32_t)0x0F) << pos;
+                tmpreg &= ~pinmask;
+                tmpreg |= (currentmode << pos);
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
+                {
+                    GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+
+                if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
+                {
+                    GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
+                }
+            }
+        }
+        GPIOx->CFGHR = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_StructInit
+ *
+ * @brief   Fills each GPIO_InitStruct member with its default
+ *
+ * @param   GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
+ *      which will be initialized.
+ *
+ * @return  none
+ */
+void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
+{
+    GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+    GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+    GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputDataBit
+ *
+ * @brief   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @param    GPIO_Pin - specifies the port bit to read.
+ *             This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+    if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadInputData
+ *
+ * @brief   Reads the specified GPIO input data port.
+ *
+ * @param   GPIOx: where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  The input port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint16_t)GPIOx->INDR);
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputDataBit
+ *
+ * @brief   Reads the specified output data port bit.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to read.
+ *            This parameter can be GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint8_t bitstatus = 0x00;
+
+    if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+    {
+        bitstatus = (uint8_t)Bit_SET;
+    }
+    else
+    {
+        bitstatus = (uint8_t)Bit_RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ReadOutputData
+ *
+ * @brief   Reads the specified GPIO output data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *
+ * @return  GPIO output port pin value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
+{
+    return ((uint16_t)GPIOx->OUTDR);
+}
+
+/*********************************************************************
+ * @fn      GPIO_SetBits
+ *
+ * @brief   Sets the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    GPIOx->BSHR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_ResetBits
+ *
+ * @brief   Clears the selected data port bits.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bits to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    GPIOx->BCR = GPIO_Pin;
+}
+
+/*********************************************************************
+ * @fn      GPIO_WriteBit
+ *
+ * @brief   Sets or clears the selected data port bit.
+ *
+ * @param   GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be one of GPIO_Pin_x where x can be (0..15).
+ *          BitVal - specifies the value to be written to the selected bit.
+ *            Bit_SetL - to clear the port pin.
+ *            Bit_SetH - to set the port pin.
+ *
+ * @return  none
+ */
+void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+    if(BitVal != Bit_RESET)
+    {
+        GPIOx->BSHR = GPIO_Pin;
+    }
+    else
+    {
+        GPIOx->BCR = GPIO_Pin;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_Write
+ *
+ * @brief   Writes data to the specified GPIO data port.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          PortVal - specifies the value to be written to the port output data register.
+ *
+ * @return  none
+ */
+void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
+{
+    GPIOx->OUTDR = PortVal;
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinLockConfig
+ *
+ * @brief   Locks GPIO Pins configuration registers.
+ *
+ * @param   GPIOx - where x can be (A..G) to select the GPIO peripheral.
+ *          GPIO_Pin - specifies the port bit to be written.
+ *            This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
+{
+    uint32_t tmp = 0x00010000;
+
+    tmp |= GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    GPIOx->LCKR = GPIO_Pin;
+    GPIOx->LCKR = tmp;
+    tmp = GPIOx->LCKR;
+    tmp = GPIOx->LCKR;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputConfig
+ *
+ * @brief   Selects the GPIO pin used as Event output.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source
+ *        for Event output.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
+ *          GPIO_PinSource - specifies the pin for the Event output.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = AFIO->ECR;
+    tmpreg &= ECR_PORTPINCONFIG_MASK;
+    tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
+    tmpreg |= GPIO_PinSource;
+    AFIO->ECR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      GPIO_EventOutputCmd
+ *
+ * @brief   Enables or disables the Event Output.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_EventOutputCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        AFIO->ECR |= (1 << 7);
+    }
+    else
+    {
+        AFIO->ECR &= ~(1 << 7);
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_PinRemapConfig
+ *
+ * @brief   Changes the mapping of the specified pin.
+ *
+ * @param   GPIO_Remap - selects the pin to remap.
+ *            GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
+ *            GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
+ *            GPIO_Remap_USART1 - USART1 Alternate Function mapping
+ *            GPIO_Remap_USART2 - USART2 Alternate Function mapping
+ *            GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
+ *            GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
+ *            GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
+ *            GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
+ *            GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
+ *            GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
+ *            GPIO_Remap_PD01 - PD01 Alternate Function mapping
+ *            GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
+ *            GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
+ *            GPIO_Remap_ETH - Ethernet remapping
+ *            GPIO_Remap_CAN2 - CAN2 remapping
+ *            GPIO_Remap_MII_RMII_SEL - MII or RMII selection
+ *            GPIO_Remap_SWJ_NoJTRST - Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST
+ *            GPIO_Remap_SWJ_JTAGDisable - JTAG-DP Disabled and SW-DP Enabled
+ *            GPIO_Remap_SWJ_Disable - Full SWJ Disabled (JTAG-DP + SW-DP)
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
+ *        to TIM2 Internal Trigger 1 for calibration
+ *            GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
+ *            GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
+ *            GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
+ *            GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
+ *            GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
+ *            GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
+ *            GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
+ *            GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
+ *            GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
+ *            GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
+{
+    uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
+
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {
+        tmpreg = AFIO->PCFR2;
+    }
+    else
+    {
+        tmpreg = AFIO->PCFR1;
+    }
+
+    tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
+    tmp = GPIO_Remap & LSB_MASK;
+
+    if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
+    {
+        tmpreg &= DBGAFR_SWJCFG_MASK;
+        AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
+    }
+    else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
+    {
+        tmp1 = ((uint32_t)0x03) << tmpmask;
+        tmpreg &= ~tmp1;
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+    }
+    else
+    {
+        tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
+        tmpreg |= ~DBGAFR_SWJCFG_MASK;
+    }
+
+    if(NewState != DISABLE)
+    {
+        tmpreg |= (tmp << ((GPIO_Remap >> 0x15) * 0x10));
+    }
+
+    if((GPIO_Remap & 0x80000000) == 0x80000000)
+    {
+        AFIO->PCFR2 = tmpreg;
+    }
+    else
+    {
+        AFIO->PCFR1 = tmpreg;
+    }
+}
+
+/*********************************************************************
+ * @fn      GPIO_EXTILineConfig
+ *
+ * @brief   Selects the GPIO pin used as EXTI Line.
+ *
+ * @param   GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
+ *            This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
+ *          GPIO_PinSource - specifies the EXTI line to be configured.
+ *            This parameter can be GPIO_PinSourcex where x can be (0..15).
+ *
+ * @return  none
+ */
+void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
+{
+    uint32_t tmp = 0x00;
+
+    tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
+    AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
+}
+
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_i2c.c

@@ -0,0 +1,979 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_i2c.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the I2C firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_i2c.h"
+#include "ch32v10x_rcc.h"
+
+/* I2C SPE mask */
+#define CTLR1_PE_Set             ((uint16_t)0x0001)
+#define CTLR1_PE_Reset           ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTLR1_START_Set          ((uint16_t)0x0100)
+#define CTLR1_START_Reset        ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTLR1_STOP_Set           ((uint16_t)0x0200)
+#define CTLR1_STOP_Reset         ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTLR1_ACK_Set            ((uint16_t)0x0400)
+#define CTLR1_ACK_Reset          ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTLR1_ENGC_Set           ((uint16_t)0x0040)
+#define CTLR1_ENGC_Reset         ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTLR1_SWRST_Set          ((uint16_t)0x8000)
+#define CTLR1_SWRST_Reset        ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTLR1_PEC_Set            ((uint16_t)0x1000)
+#define CTLR1_PEC_Reset          ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTLR1_ENPEC_Set          ((uint16_t)0x0020)
+#define CTLR1_ENPEC_Reset        ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTLR1_ENARP_Set          ((uint16_t)0x0010)
+#define CTLR1_ENARP_Reset        ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTLR1_NOSTRETCH_Set      ((uint16_t)0x0080)
+#define CTLR1_NOSTRETCH_Reset    ((uint16_t)0xFF7F)
+
+/* I2C registers Masks */
+#define CTLR1_CLEAR_Mask         ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTLR2_DMAEN_Set          ((uint16_t)0x0800)
+#define CTLR2_DMAEN_Reset        ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTLR2_LAST_Set           ((uint16_t)0x1000)
+#define CTLR2_LAST_Reset         ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTLR2_FREQ_Reset         ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADD0_Set          ((uint16_t)0x0001)
+#define OADDR1_ADD0_Reset        ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_ENDUAL_Set        ((uint16_t)0x0001)
+#define OADDR2_ENDUAL_Reset      ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADD2_Reset        ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CKCFGR_FS_Set            ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CKCFGR_CCR_Set           ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+#define FLAG_Mask                ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask                ((uint32_t)0x07000000)
+
+/*********************************************************************
+ * @fn      I2C_DeInit
+ *
+ * @brief   Deinitializes the I2Cx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_DeInit(I2C_TypeDef *I2Cx)
+{
+    if(I2Cx == I2C1)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
+    }
+    else
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_Init
+ *
+ * @brief   Initializes the I2Cx peripheral according to the specified
+ *        parameters in the I2C_InitStruct.
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_InitStruct - pointer to a I2C_InitTypeDef structure that
+ *        contains the configuration information for the specified I2C peripheral.
+ *
+ * @return  none
+ */
+void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct)
+{
+    uint16_t tmpreg = 0, freqrange = 0;
+    uint16_t result = 0x04;
+    uint32_t pclk1 = 8000000;
+
+    RCC_ClocksTypeDef rcc_clocks;
+
+    tmpreg = I2Cx->CTLR2;
+    tmpreg &= CTLR2_FREQ_Reset;
+    RCC_GetClocksFreq(&rcc_clocks);
+    pclk1 = rcc_clocks.PCLK1_Frequency;
+    freqrange = (uint16_t)(pclk1 / 1000000);
+    tmpreg |= freqrange;
+    I2Cx->CTLR2 = tmpreg;
+
+    I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    tmpreg = 0;
+
+    if(I2C_InitStruct->I2C_ClockSpeed <= 100000)
+    {
+        result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+
+        if(result < 0x04)
+        {
+            result = 0x04;
+        }
+
+        tmpreg |= result;
+        I2Cx->RTR = freqrange + 1;
+    }
+    else
+    {
+        if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+        {
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+        }
+        else
+        {
+            result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+            result |= I2C_DutyCycle_16_9;
+        }
+
+        if((result & CKCFGR_CCR_Set) == 0)
+        {
+            result |= (uint16_t)0x0001;
+        }
+
+        tmpreg |= (uint16_t)(result | CKCFGR_FS_Set);
+        I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);
+    }
+
+    I2Cx->CKCFGR = tmpreg;
+    I2Cx->CTLR1 |= CTLR1_PE_Set;
+
+    tmpreg = I2Cx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+    I2Cx->CTLR1 = tmpreg;
+
+    I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/*********************************************************************
+ * @fn      I2C_StructInit
+ *
+ * @brief   Fills each I2C_InitStruct member with its default value.
+ *
+ * @param   I2C_InitStruct - pointer to an I2C_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct)
+{
+    I2C_InitStruct->I2C_ClockSpeed = 5000;
+    I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+    I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+    I2C_InitStruct->I2C_OwnAddress1 = 0;
+    I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+    I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/*********************************************************************
+ * @fn      I2C_Cmd
+ *
+ * @brief   Enables or disables the specified I2C peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_PE_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMACmd
+ *
+ * @brief   Enables or disables the specified I2C DMA requests.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= CTLR2_DMAEN_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_DMAEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_DMALastTransferCmd
+ *
+ * @brief   Specifies if the next DMA transfer will be the last one.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= CTLR2_LAST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= CTLR2_LAST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTART
+ *
+ * @brief   Generates I2Cx communication START condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_START_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_START_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GenerateSTOP
+ *
+ * @brief   Generates I2Cx communication STOP condition.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_STOP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_STOP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_AcknowledgeConfig
+ *
+ * @brief   Enables or disables the specified I2C acknowledge feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ACK_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_OwnAddress2Config
+ *
+ * @brief   Configures the specified I2C own address2.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the 7bit I2C own address2.
+ *
+ * @return  none
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = I2Cx->OADDR2;
+    tmpreg &= OADDR2_ADD2_Reset;
+    tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+    I2Cx->OADDR2 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      I2C_DualAddressCmd
+ *
+ * @brief   Enables or disables the specified I2C dual addressing mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->OADDR2 |= OADDR2_ENDUAL_Set;
+    }
+    else
+    {
+        I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GeneralCallCmd
+ *
+ * @brief   Enables or disables the specified I2C general call feature.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENGC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENGC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_ITConfig
+ *
+ * @brief   Enables or disables the specified I2C interrupts.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the I2C interrupts sources to be enabled or disabled.
+ *            I2C_IT_BUF - Buffer interrupt mask.
+ *            I2C_IT_EVT - Event interrupt mask.
+ *            I2C_IT_ERR - Error interrupt mask.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR2 |= I2C_IT;
+    }
+    else
+    {
+        I2Cx->CTLR2 &= (uint16_t)~I2C_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SendData
+ *
+ * @brief   Sends a data byte through the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Data - Byte to be transmitted.
+ *
+ * @return  none
+ */
+void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data)
+{
+    I2Cx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the I2Cx peripheral.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx)
+{
+    return (uint8_t)I2Cx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      I2C_Send7bitAddress
+ *
+ * @brief   Transmits the address byte to select the slave device.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          Address - specifies the slave address which will be transmitted.
+ *          I2C_Direction - specifies whether the I2C device will be a
+ *        Transmitter or a Receiver.
+ *            I2C_Direction_Transmitter - Transmitter mode.
+ *            I2C_Direction_Receiver - Receiver mode.
+ *
+ * @return  none
+ */
+void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+    if(I2C_Direction != I2C_Direction_Transmitter)
+    {
+        Address |= OADDR1_ADD0_Set;
+    }
+    else
+    {
+        Address &= OADDR1_ADD0_Reset;
+    }
+
+    I2Cx->DATAR = Address;
+}
+
+/*********************************************************************
+ * @fn      I2C_ReadRegister
+ *
+ * @brief   Reads the specified I2C register and returns its value.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_Register - specifies the register to read.
+ *            I2C_Register_CTLR1.
+ *            I2C_Register_CTLR2.
+ *            I2C_Register_OADDR1.
+ *            I2C_Register_OADDR2.
+ *            I2C_Register_DATAR.
+ *            I2C_Register_STAR1.
+ *            I2C_Register_STAR2.
+ *            I2C_Register_CKCFGR.
+ *            I2C_Register_RTR.
+ *
+ * @return  none
+ */
+uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register)
+{
+    __IO uint32_t tmp = 0;
+
+    tmp = (uint32_t)I2Cx;
+    tmp += I2C_Register;
+
+    return (*(__IO uint16_t *)tmp);
+}
+
+/*********************************************************************
+ * @fn      I2C_SoftwareResetCmd
+ *
+ * @brief   Enables or disables the specified I2C software reset.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_SWRST_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_SWRST_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_NACKPositionConfig
+ *
+ * @brief   Selects the specified I2C NACK position in master receiver mode.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_NACKPosition - specifies the NACK position.
+ *            I2C_NACKPosition_Next - indicates that the next byte will be
+ *        the last received byte.
+ *            I2C_NACKPosition_Current - indicates that current byte is the
+ *        last received byte.
+ *
+ * @return  none
+ */
+void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition)
+{
+    if(I2C_NACKPosition == I2C_NACKPosition_Next)
+    {
+        I2Cx->CTLR1 |= I2C_NACKPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_NACKPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_SMBusAlertConfig
+ *
+ * @brief   Drives the SMBusAlert pin high or low for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_SMBusAlert - specifies SMBAlert pin level.
+ *            I2C_SMBusAlert_Low - SMBAlert pin driven low.
+ *            I2C_SMBusAlert_High - SMBAlert pin driven high.
+ *
+ * @return  none
+ */
+void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert)
+{
+    if(I2C_SMBusAlert == I2C_SMBusAlert_Low)
+    {
+        I2Cx->CTLR1 |= I2C_SMBusAlert_Low;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_SMBusAlert_High;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_TransmitPEC
+ *
+ * @brief   Enables or disables the specified I2C PEC transfer.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_PEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_PEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_PECPositionConfig
+ *
+ * @brief   Selects the specified I2C PEC position.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_PECPosition - specifies the PEC position.
+ *            I2C_PECPosition_Next - indicates that the next byte is PEC.
+ *            I2C_PECPosition_Current - indicates that current byte is PEC.
+ *
+ * @return  none
+ */
+void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition)
+{
+    if(I2C_PECPosition == I2C_PECPosition_Next)
+    {
+        I2Cx->CTLR1 |= I2C_PECPosition_Next;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= I2C_PECPosition_Current;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CalculatePEC
+ *
+ * @brief   Enables or disables the PEC value calculation of the transferred bytes.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENPEC_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENPEC_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_GetPEC
+ *
+ * @brief   Returns the PEC value for the specified I2C.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  The PEC value.
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx)
+{
+    return ((I2Cx->STAR2) >> 8);
+}
+
+/*********************************************************************
+ * @fn      I2C_ARPCmd
+ *
+ * @brief   Enables or disables the specified I2C ARP.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *            NewState - ENABLE or DISABLE.
+ *
+ * @return  The PEC value.
+ */
+void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_ENARP_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_ENARP_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_StretchClockCmd
+ *
+ * @brief   Enables or disables the specified I2C Clock stretching.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState)
+{
+    if(NewState == DISABLE)
+    {
+        I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set;
+    }
+    else
+    {
+        I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_FastModeDutyCycleConfig
+ *
+ * @brief   Selects the specified I2C fast mode duty cycle.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_DutyCycle - specifies the fast mode duty cycle.
+ *            I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2.
+ *            I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9.
+ *
+ * @return  none
+ */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle)
+{
+    if(I2C_DutyCycle != I2C_DutyCycle_16_9)
+    {
+        I2Cx->CKCFGR &= I2C_DutyCycle_2;
+    }
+    else
+    {
+        I2Cx->CKCFGR |= I2C_DutyCycle_16_9;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2C_CheckEvent
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx- where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_EVENT: specifies the event to be checked.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EV1.
+ *             I2C_EVENT_SLAVE_BYTE_RECEIVED - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EV2.
+ *             (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EV2.
+ *             I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EV3.
+ *             (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EV3.
+ *             I2C_EVENT_SLAVE_ACK_FAILURE - EV3_2.
+ *             I2C_EVENT_SLAVE_STOP_DETECTED - EV4.
+ *             I2C_EVENT_MASTER_MODE_SELECT - EV5.
+ *             I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EV6.
+ *             I2C_EVENT_MASTER_BYTE_RECEIVED - EV7.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTING - EV8.
+ *             I2C_EVENT_MASTER_BYTE_TRANSMITTED - EV8_2.
+ *             I2C_EVENT_MASTER_MODE_ADDRESS10 - EV9.
+ *
+ * @return  none
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT)
+{
+    uint32_t    lastevent = 0;
+    uint32_t    flag1 = 0, flag2 = 0;
+    ErrorStatus status = ERROR;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+
+    lastevent = (flag1 | flag2) & FLAG_Mask;
+
+    if((lastevent & I2C_EVENT) == I2C_EVENT)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    return status;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetLastEvent
+ *
+ * @brief   Returns the last I2Cx Event.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *
+ * @return  none
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx)
+{
+    uint32_t lastevent = 0;
+    uint32_t flag1 = 0, flag2 = 0;
+
+    flag1 = I2Cx->STAR1;
+    flag2 = I2Cx->STAR2;
+    flag2 = flag2 << 16;
+    lastevent = (flag1 | flag2) & FLAG_Mask;
+
+    return lastevent;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetFlagStatus
+ *
+ * @brief   Checks whether the last I2Cx Event is equal to the one passed
+ *        as parameter.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to check.
+ *            I2C_FLAG_DUALF - Dual flag (Slave mode).
+ *            I2C_FLAG_SMBHOST - SMBus host header (Slave mode).
+ *            I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode).
+ *            I2C_FLAG_GENCALL - General call header flag (Slave mode).
+ *            I2C_FLAG_TRA - Transmitter/Receiver flag.
+ *            I2C_FLAG_BUSY - Bus busy flag.
+ *            I2C_FLAG_MSL - Master/Slave flag.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *            I2C_FLAG_TXE - Data register empty flag (Transmitter).
+ *            I2C_FLAG_RXNE- Data register not empty (Receiver) flag.
+ *            I2C_FLAG_STOPF - Stop detection flag (Slave mode).
+ *            I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_FLAG_BTF - Byte transfer finished flag.
+ *            I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL"
+ *        Address matched flag (Slave mode)"ENDA".
+ *            I2C_FLAG_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    FlagStatus    bitstatus = RESET;
+    __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+    i2cxbase = (uint32_t)I2Cx;
+    i2creg = I2C_FLAG >> 28;
+    I2C_FLAG &= FLAG_Mask;
+
+    if(i2creg != 0)
+    {
+        i2cxbase += 0x14;
+    }
+    else
+    {
+        I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+        i2cxbase += 0x18;
+    }
+
+    if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearFlag
+ *
+ * @brief   Clears the I2Cx's pending flags.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_FLAG - specifies the flag to clear.
+ *            I2C_FLAG_SMBALERT - SMBus Alert flag.
+ *            I2C_FLAG_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_FLAG_PECERR - PEC error in reception flag.
+ *            I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_FLAG_AF - Acknowledge failure flag.
+ *            I2C_FLAG_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_FLAG_BERR - Bus error flag.
+ *
+ * @return  none
+ */
+void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG)
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_FLAG & FLAG_Mask;
+    I2Cx->STAR1 = (uint16_t)~flagpos;
+}
+
+/*********************************************************************
+ * @fn      I2C_GetITStatus
+ *
+ * @brief   Checks whether the specified I2C interrupt has occurred or not.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          II2C_IT - specifies the interrupt source to check.
+ *            I2C_IT_SMBALERT - SMBus Alert flag.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error flag.
+ *            I2C_IT_PECERR - PEC error in reception flag.
+ *            I2C_IT_OVR - Overrun/Underrun flag (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure flag.
+ *            I2C_IT_ARLO - Arbitration lost flag (Master mode).
+ *            I2C_IT_BERR - Bus error flag.
+ *            I2C_IT_TXE - Data register empty flag (Transmitter).
+ *            I2C_IT_RXNE - Data register not empty (Receiver) flag.
+ *            I2C_IT_STOPF - Stop detection flag (Slave mode).
+ *            I2C_IT_ADD10 - 10-bit header sent flag (Master mode).
+ *            I2C_IT_BTF - Byte transfer finished flag.
+ *            I2C_IT_ADDR - Address sent flag (Master mode) "ADSL"  Address matched
+ *        flag (Slave mode)"ENDAD".
+ *            I2C_IT_SB - Start bit flag (Master mode).
+ *
+ * @return  none
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint32_t enablestatus = 0;
+
+    enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2));
+    I2C_IT &= FLAG_Mask;
+
+    if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      I2C_ClearITPendingBit
+ *
+ * @brief   Clears the I2Cx interrupt pending bits.
+ *
+ * @param   I2Cx - where x can be 1 or 2 to select the I2C peripheral.
+ *          I2C_IT - specifies the interrupt pending bit to clear.
+ *            I2C_IT_SMBALERT - SMBus Alert interrupt.
+ *            I2C_IT_TIMEOUT - Timeout or Tlow error interrupt.
+ *            I2C_IT_PECERR - PEC error in reception  interrupt.
+ *            I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode).
+ *            I2C_IT_AF - Acknowledge failure interrupt.
+ *            I2C_IT_ARLO - Arbitration lost interrupt (Master mode).
+ *            I2C_IT_BERR - Bus error interrupt.
+ *
+ * @return  none
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT)
+{
+    uint32_t flagpos = 0;
+
+    flagpos = I2C_IT & FLAG_Mask;
+    I2Cx->STAR1 = (uint16_t)~flagpos;
+}
+
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_iwdg.c

@@ -0,0 +1,123 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : ch32v10x_iwdg.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the IWDG firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_iwdg.h"
+
+/* CTLR register bit mask */
+#define CTLR_KEY_Reload    ((uint16_t)0xAAAA)
+#define CTLR_KEY_Enable    ((uint16_t)0xCCCC)
+
+/*********************************************************************
+ * @fn      IWDG_WriteAccessCmd
+ *
+ * @brief   Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
+ *
+ * @param   WDG_WriteAccess - new state of write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
+ *        IWDG_RLDR registers.
+ *            IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
+ *        and IWDG_RLDR registers.
+ *
+ * @return  none
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+    IWDG->CTLR = IWDG_WriteAccess;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetPrescaler
+ *
+ * @brief   Sets IWDG Prescaler value.
+ *
+ * @param   IWDG_Prescaler - specifies the IWDG Prescaler value.
+ *             IWDG_Prescaler_4 - IWDG prescaler set to 4.
+ *             IWDG_Prescaler_8 - IWDG prescaler set to 8.
+ *             IWDG_Prescaler_16 - IWDG prescaler set to 16.
+ *             IWDG_Prescaler_32 - IWDG prescaler set to 32.
+ *             IWDG_Prescaler_64 - IWDG prescaler set to 64.
+ *             IWDG_Prescaler_128 - IWDG prescaler set to 128.
+ *             IWDG_Prescaler_256 - IWDG prescaler set to 256.
+ *
+ * @return  none
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+    IWDG->PSCR = IWDG_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      IWDG_SetReload
+ *
+ * @brief   Sets IWDG Reload value.
+ *
+ * @param   Reload - specifies the IWDG Reload value.
+ *            This parameter must be a number between 0 and 0x0FFF.
+ *
+ * @return  none
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+    IWDG->RLDR = Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_ReloadCounter
+ *
+ * @brief   Reloads IWDG counter with value defined in the reload register.
+ *
+ * @return  none
+ */
+void IWDG_ReloadCounter(void)
+{
+    IWDG->CTLR = CTLR_KEY_Reload;
+}
+
+/*********************************************************************
+ * @fn      IWDG_Enable
+ *
+ * @brief   Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
+ *
+ * @return  none
+ */
+void IWDG_Enable(void)
+{
+    IWDG->CTLR = CTLR_KEY_Enable;
+}
+
+/*********************************************************************
+ * @fn      IWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the specified IWDG flag is set or not.
+ *
+ * @param   IWDG_FLAG - specifies the flag to check.
+ *            IWDG_FLAG_PVU - Prescaler Value Update on going.
+ *            IWDG_FLAG_RVU - Reload Value Update on going.
+ *
+ * @return  none
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_misc.c

@@ -0,0 +1,107 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_misc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the miscellaneous firmware functions .
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32v10x_misc.h"
+
+__IO uint32_t NVIC_Priority_Group = 0;
+
+/*********************************************************************
+ * @fn      NVIC_PriorityGroupConfig
+ *
+ * @brief   Configures the priority grouping - pre-emption priority and subpriority.
+ *
+ * @param   NVIC_PriorityGroup - specifies the priority grouping bits length.
+ *            NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
+ *                                   4 bits for subpriority
+ *            NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
+ *                                   3 bits for subpriority
+ *            NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
+ *                                   2 bits for subpriority
+ *            NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
+ *                                   1 bits for subpriority
+ *            NVIC_PriorityGroup_4 - 4 bits for pre-emption priority
+ *                                   0 bits for subpriority
+ *
+ * @return  none
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+    NVIC_Priority_Group = NVIC_PriorityGroup;
+}
+
+/*********************************************************************
+ * @fn      NVIC_Init
+ *
+ * @brief   Initializes the NVIC peripheral according to the specified parameters in
+ *        the NVIC_InitStruct.
+ *
+ * @param   NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
+ *        configuration information for the specified NVIC peripheral.
+ *
+ * @return  none
+ */
+void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
+{
+    uint8_t tmppre = 0;
+
+    if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
+    {
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
+        {
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
+        }
+        else
+        {
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1)
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
+        }
+        else
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2));
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
+    {
+        if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3)
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority);
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4));
+        }
+        else
+        {
+            tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4));
+            NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4));
+        }
+    }
+    else if(NVIC_Priority_Group == NVIC_PriorityGroup_4)
+    {
+        NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4);
+    }
+
+    if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+    {
+        NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+    else
+    {
+        NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
+    }
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_pwr.c

@@ -0,0 +1,217 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_pwr.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the PWR firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ********************************************************************************/
+#include "ch32v10x_pwr.h"
+#include "ch32v10x_rcc.h"
+
+/* PWR registers bit mask */
+/* CTLR register bit mask */
+#define CTLR_DS_MASK     ((uint32_t)0xFFFFFFFC)
+#define CTLR_PLS_MASK    ((uint32_t)0xFFFFFF1F)
+
+/*********************************************************************
+ * @fn      PWR_DeInit
+ *
+ * @brief   Deinitializes the PWR peripheral registers to their default
+ *        reset values.
+ *
+ * @return  none
+ */
+void PWR_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      PWR_BackupAccessCmd
+ *
+ * @brief   Enables or disables access to the RTC and backup registers.
+ *
+ * @param   NewState - new state of the access to the RTC and backup registers,
+ *            This parameter can be: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CTLR |= (1 << 8);
+    }
+    else
+    {
+        PWR->CTLR &= ~(1 << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_PVDCmd
+ *
+ * @brief   Enables or disables the Power Voltage Detector(PVD).
+ *
+ * @param   NewState - new state of the PVD(ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CTLR |= (1 << 4);
+    }
+    else
+    {
+        PWR->CTLR &= ~(1 << 4);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_PVDLevelConfig
+ *
+ * @brief   Configures the voltage threshold detected by the Power Voltage
+ *        Detector(PVD).
+ *
+ * @param   PWR_PVDLevel - specifies the PVD detection level
+ *            PWR_PVDLevel_2V2 - PVD detection level set to 2.2V
+ *            PWR_PVDLevel_2V3 - PVD detection level set to 2.3V
+ *            PWR_PVDLevel_2V4 - PVD detection level set to 2.4V
+ *            PWR_PVDLevel_2V5 - PVD detection level set to 2.5V
+ *            PWR_PVDLevel_2V6 - PVD detection level set to 2.6V
+ *            PWR_PVDLevel_2V7 - PVD detection level set to 2.7V
+ *            PWR_PVDLevel_2V8 - PVD detection level set to 2.8V
+ *            PWR_PVDLevel_2V9 - PVD detection level set to 2.9V
+ *
+ * @return  none
+ */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_PLS_MASK;
+    tmpreg |= PWR_PVDLevel;
+    PWR->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      PWR_WakeUpPinCmd
+ *
+ * @brief   Enables or disables the WakeUp Pin functionality.
+ *
+ * @param   NewState - new state of the WakeUp Pin functionality
+ *        (ENABLE or DISABLE).
+ *
+ * @return  none
+ */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        PWR->CSR |= (1 << 8);
+    }
+    else
+    {
+        PWR->CSR &= ~(1 << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTOPMode
+ *
+ * @brief   Enters STOP mode.
+ *
+ * @param   PWR_Regulator - specifies the regulator state in STOP mode.
+ *            PWR_Regulator_ON - STOP mode with regulator ON
+ *            PWR_Regulator_LowPower - STOP mode with regulator in low power mode
+ *          PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
+ *            PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
+ *            PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
+ *
+ * @return  none
+ */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = PWR->CTLR;
+    tmpreg &= CTLR_DS_MASK;
+    tmpreg |= PWR_Regulator;
+    PWR->CTLR = tmpreg;
+
+    NVIC->SCTLR |= (1 << 2);
+
+    if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+    {
+        __WFI();
+    }
+    else
+    {
+        __WFE();
+    }
+
+    NVIC->SCTLR &= ~(1 << 2);
+}
+
+/*********************************************************************
+ * @fn      PWR_EnterSTANDBYMode
+ *
+ * @brief   Enters STANDBY mode.
+ *
+ * @return  none
+ */
+void PWR_EnterSTANDBYMode(void)
+{
+    PWR->CTLR |= PWR_CTLR_CWUF;
+    PWR->CTLR |= PWR_CTLR_PDDS;
+    NVIC->SCTLR |= (1 << 2);
+
+    __WFI();
+}
+
+/*********************************************************************
+ * @fn      PWR_GetFlagStatus
+ *
+ * @brief   Checks whether the specified PWR flag is set or not.
+ *
+ * @param   PWR_FLAG - specifies the flag to check.
+ *            PWR_FLAG_WU - Wake Up flag
+ *            PWR_FLAG_SB - StandBy flag
+ *            PWR_FLAG_PVDO - PVD Output
+ *
+ * @return  The new state of PWR_FLAG (SET or RESET).
+ */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      PWR_ClearFlag
+ *
+ * @brief   Clears the PWR's pending flags.
+ *
+ * @param   PWR_FLAG - specifies the flag to clear.
+ *            PWR_FLAG_WU - Wake Up flag
+ *            PWR_FLAG_SB - StandBy flag
+ *
+ * @return  none
+ */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+    PWR->CTLR |= PWR_FLAG << 2;
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_rcc.c

@@ -0,0 +1,938 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_rcc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the RCC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_rcc.h"
+
+/* RCC registers bit address in the alias region */
+#define RCC_OFFSET                 (RCC_BASE - PERIPH_BASE)
+
+/* BDCTLR Register */
+#define BDCTLR_OFFSET              (RCC_OFFSET + 0x20)
+
+/* RCC registers bit mask */
+
+/* CTLR register bit mask */
+#define CTLR_HSEBYP_Reset          ((uint32_t)0xFFFBFFFF)
+#define CTLR_HSEBYP_Set            ((uint32_t)0x00040000)
+#define CTLR_HSEON_Reset           ((uint32_t)0xFFFEFFFF)
+#define CTLR_HSEON_Set             ((uint32_t)0x00010000)
+#define CTLR_HSITRIM_Mask          ((uint32_t)0xFFFFFF07)
+
+#define CFGR0_PLL_Mask             ((uint32_t)0xFFC0FFFF)
+#define CFGR0_PLLMull_Mask         ((uint32_t)0x003C0000)
+#define CFGR0_PLLSRC_Mask          ((uint32_t)0x00010000)
+#define CFGR0_PLLXTPRE_Mask        ((uint32_t)0x00020000)
+#define CFGR0_SWS_Mask             ((uint32_t)0x0000000C)
+#define CFGR0_SW_Mask              ((uint32_t)0xFFFFFFFC)
+#define CFGR0_HPRE_Reset_Mask      ((uint32_t)0xFFFFFF0F)
+#define CFGR0_HPRE_Set_Mask        ((uint32_t)0x000000F0)
+#define CFGR0_PPRE1_Reset_Mask     ((uint32_t)0xFFFFF8FF)
+#define CFGR0_PPRE1_Set_Mask       ((uint32_t)0x00000700)
+#define CFGR0_PPRE2_Reset_Mask     ((uint32_t)0xFFFFC7FF)
+#define CFGR0_PPRE2_Set_Mask       ((uint32_t)0x00003800)
+#define CFGR0_ADCPRE_Reset_Mask    ((uint32_t)0xFFFF3FFF)
+#define CFGR0_ADCPRE_Set_Mask      ((uint32_t)0x0000C000)
+
+/* RSTSCKR register bit mask */
+#define RSTSCKR_RMVF_Set           ((uint32_t)0x01000000)
+
+/* RCC Flag Mask */
+#define FLAG_Mask                  ((uint8_t)0x1F)
+
+/* INTR register byte 2 (Bits[15:8]) base address */
+#define INTR_BYTE2_ADDRESS         ((uint32_t)0x40021009)
+
+/* INTR register byte 3 (Bits[23:16]) base address */
+#define INTR_BYTE3_ADDRESS         ((uint32_t)0x4002100A)
+
+/* CFGR0 register byte 4 (Bits[31:24]) base address */
+#define CFGR0_BYTE4_ADDRESS        ((uint32_t)0x40021007)
+
+/* BDCTLR register base address */
+#define BDCTLR_ADDRESS             (PERIPH_BASE + BDCTLR_OFFSET)
+
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
+
+/*********************************************************************
+ * @fn      RCC_DeInit
+ *
+ * @brief   Resets the RCC clock configuration to the default reset state.
+ *
+ * @return  none
+ */
+void RCC_DeInit(void)
+{
+    RCC->CTLR |= (uint32_t)0x00000001;
+    RCC->CFGR0 &= (uint32_t)0xF8FF0000;
+    RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+    RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+    RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
+    RCC->INTR = 0x009F0000;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSEConfig
+ *
+ * @brief   Configures the External High Speed oscillator (HSE).
+ *
+ * @param   RCC_HSE -
+ *            RCC_HSE_OFF - HSE oscillator OFF.
+ *            RCC_HSE_ON - HSE oscillator ON.
+ *            RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_HSEConfig(uint32_t RCC_HSE)
+{
+    RCC->CTLR &= CTLR_HSEON_Reset;
+    RCC->CTLR &= CTLR_HSEBYP_Reset;
+
+    switch(RCC_HSE)
+    {
+        case RCC_HSE_ON:
+            RCC->CTLR |= CTLR_HSEON_Set;
+            break;
+
+        case RCC_HSE_Bypass:
+            RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_WaitForHSEStartUp
+ *
+ * @brief   Waits for HSE start-up.
+ *
+ * @return  SUCCESS - HSE oscillator is stable and ready to use.
+ *                  ERROR - HSE oscillator not yet ready.
+ */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+    __IO uint32_t StartUpCounter = 0;
+
+    ErrorStatus status = ERROR;
+    FlagStatus  HSEStatus = RESET;
+
+    do
+    {
+        HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+        StartUpCounter++;
+    } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
+
+    if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+    {
+        status = SUCCESS;
+    }
+    else
+    {
+        status = ERROR;
+    }
+
+    return (status);
+}
+
+/*********************************************************************
+ * @fn      RCC_AdjustHSICalibrationValue
+ *
+ * @brief   Adjusts the Internal High Speed oscillator (HSI) calibration value.
+ *
+ * @param   HSICalibrationValue - specifies the calibration trimming value.
+ *                    This parameter must be a number between 0 and 0x1F.
+ *
+ * @return  none
+ */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CTLR;
+    tmpreg &= CTLR_HSITRIM_Mask;
+    tmpreg |= (uint32_t)HSICalibrationValue << 3;
+    RCC->CTLR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_HSICmd
+ *
+ * @brief   Enables or disables the Internal High Speed oscillator (HSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_HSICmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 0);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLConfig
+ *
+ * @brief   Configures the PLL clock source and multiplication factor.
+ *
+ * @param   RCC_PLLSource - specifies the PLL entry clock source.
+ *          RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *          RCC_PLLSource_HSE_Div1 - HSE oscillator clock selected as PLL
+ *        clock entry.
+ *          RCC_PLLSource_HSE_Div2 - HSE oscillator clock divided by 2
+ *        selected as PLL clock entry.
+ *          RCC_PLLMul - specifies the PLL multiplication factor.
+ *          This parameter can be RCC_PLLMul_x where x:[2,16].
+ *
+ * @return  none
+ */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PLL_Mask;
+    tmpreg |= RCC_PLLSource | RCC_PLLMul;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PLLCmd
+ *
+ * @brief   Enables or disables the PLL.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 24);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 24);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_SYSCLKConfig
+ *
+ * @brief   Configures the system clock (SYSCLK).
+ *
+ * @param   RCC_SYSCLKSource - specifies the clock source used as system clock.
+ *            RCC_SYSCLKSource_HSI - HSI selected as system clock.
+ *            RCC_SYSCLKSource_HSE - HSE selected as system clock.
+ *            RCC_SYSCLKSource_PLLCLK - PLL selected as system clock.
+ *
+ * @return  none
+ */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_SW_Mask;
+    tmpreg |= RCC_SYSCLKSource;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetSYSCLKSource
+ *
+ * @brief   Returns the clock source used as system clock.
+ *
+ * @return  0x00 - HSI used as system clock.
+ *          0x04 - HSE used as system clock.
+ *          0x08 - PLL used as system clock.
+ */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+    return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
+}
+
+/*********************************************************************
+ * @fn      RCC_HCLKConfig
+ *
+ * @brief   Configures the AHB clock (HCLK).
+ *
+ * @param   RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
+ *        the system clock (SYSCLK).
+ *            RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
+ *            RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
+ *            RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
+ *            RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
+ *            RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
+ *            RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
+ *            RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
+ *            RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
+ *            RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512.
+ *
+ * @return  none
+ */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_HPRE_Reset_Mask;
+    tmpreg |= RCC_SYSCLK;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK1Config
+ *
+ * @brief   Configures the Low Speed APB clock (PCLK1).
+ *
+ * @param   RCC_HCLK - defines the APB1 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PPRE1_Reset_Mask;
+    tmpreg |= RCC_HCLK;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_PCLK2Config
+ *
+ * @brief   Configures the High Speed APB clock (PCLK2).
+ *
+ * @param   RCC_HCLK - defines the APB2 clock divider. This clock is derived from
+ *        the AHB clock (HCLK).
+ *            RCC_HCLK_Div1 - APB1 clock = HCLK.
+ *            RCC_HCLK_Div2 - APB1 clock = HCLK/2.
+ *            RCC_HCLK_Div4 - APB1 clock = HCLK/4.
+ *            RCC_HCLK_Div8 - APB1 clock = HCLK/8.
+ *            RCC_HCLK_Div16 - APB1 clock = HCLK/16.
+ *
+ * @return  none
+ */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_PPRE2_Reset_Mask;
+    tmpreg |= RCC_HCLK << 3;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_ITConfig
+ *
+ * @brief   Enables or disables the specified RCC interrupts.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt sources to be enabled or disabled.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT;
+    }
+    else
+    {
+        *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_USBCLKConfig
+ *
+ * @brief   Configures the USB clock (USBCLK).
+ *
+ * @param   RCC_USBCLKSource: specifies the USB clock source. This clock is
+ *        derived from the PLL output.
+ *          RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
+ *        clock source.
+ *          RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source.
+ *
+ * @return  none
+ */
+void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
+{
+    if(RCC_USBCLKSource)
+    {
+        RCC->CFGR0 |= (1 << 22);
+    }
+    else
+    {
+        RCC->CFGR0 &= ~(1 << 22);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_ADCCLKConfig
+ *
+ * @brief   Configures the ADC clock (ADCCLK).
+ *
+ * @param   RCC_PCLK2 - defines the ADC clock divider. This clock is derived from
+ *        the APB2 clock (PCLK2).
+ *          RCC_PCLK2_Div2 - ADC clock = PCLK2/2.
+ *          RCC_PCLK2_Div4 - ADC clock = PCLK2/4.
+ *          RCC_PCLK2_Div6 - ADC clock = PCLK2/6.
+ *          RCC_PCLK2_Div8 - ADC clock = PCLK2/8.
+ *
+ * @return  none
+ */
+void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
+{
+    uint32_t tmpreg = 0;
+
+    tmpreg = RCC->CFGR0;
+    tmpreg &= CFGR0_ADCPRE_Reset_Mask;
+    tmpreg |= RCC_PCLK2;
+    RCC->CFGR0 = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      RCC_LSEConfig
+ *
+ * @brief   Configures the External Low Speed oscillator (LSE).
+ *
+ * @param   RCC_LSE - specifies the new state of the LSE.
+ *            RCC_LSE_OFF - LSE oscillator OFF.
+ *            RCC_LSE_ON - LSE oscillator ON.
+ *            RCC_LSE_Bypass - LSE oscillator bypassed with external clock.
+ *
+ * @return  none
+ */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+    *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF;
+    *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF;
+
+    switch(RCC_LSE)
+    {
+        case RCC_LSE_ON:
+            *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON;
+            break;
+
+        case RCC_LSE_Bypass:
+            *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+            break;
+
+        default:
+            break;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_LSICmd
+ *
+ * @brief   Enables or disables the Internal Low Speed oscillator (LSI).
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_LSICmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->RSTSCKR |= (1 << 0);
+    }
+    else
+    {
+        RCC->RSTSCKR &= ~(1 << 0);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKConfig
+ *
+ * @brief   Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
+ *
+ * @param   RCC_RTCCLKSource - specifies the RTC clock source.
+ *            RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
+ *            RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
+ *            RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+    RCC->BDCTLR |= RCC_RTCCLKSource;
+}
+
+/*********************************************************************
+ * @fn      RCC_RTCCLKCmd
+ *
+ * @brief   This function must be used only after the RTC clock was selected
+ *        using the RCC_RTCCLKConfig function.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->BDCTLR |= (1 << 15);
+    }
+    else
+    {
+        RCC->BDCTLR &= ~(1 << 15);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_GetClocksFreq
+ *
+ * @brief   The result of this function could be not correct when using
+ *        fractional value for HSE crystal.
+ *
+ * @param   RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
+ *        the clocks frequencies.
+ *
+ * @return  none
+ */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
+{
+    uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
+
+    tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
+
+    switch(tmp)
+    {
+        case 0x00:
+            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+            break;
+
+        case 0x04:
+            RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+            break;
+
+        case 0x08:
+            pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
+            pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
+            pllmull = (pllmull >> 18) + 2;
+
+            if(pllsource == 0x00)
+            {
+                if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE)
+                {
+                    RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
+                }
+            }
+            else
+            {
+                if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
+                {
+                    RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
+                }
+                else
+                {
+                    RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
+                }
+            }
+            break;
+
+        default:
+            RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+            break;
+    }
+
+    tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
+    tmp = tmp >> 4;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
+    tmp = tmp >> 8;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
+    tmp = tmp >> 11;
+    presc = APBAHBPrescTable[tmp];
+    RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+    tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
+    tmp = tmp >> 14;
+    presc = ADCPrescTable[tmp];
+    RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
+}
+
+/*********************************************************************
+ * @fn      RCC_AHBPeriphClockCmd
+ *
+ * @brief   Enables or disables the AHB peripheral clock.
+ *
+ * @param   RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
+ *            RCC_AHBPeriph_DMA1.
+ *            RCC_AHBPeriph_DMA2.
+ *            RCC_AHBPeriph_SRAM.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->AHBPCENR |= RCC_AHBPeriph;
+    }
+    else
+    {
+        RCC->AHBPCENR &= ~RCC_AHBPeriph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphClockCmd
+ *
+ * @brief   Enables or disables the High Speed APB (APB2) peripheral clock.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_ADC2
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_TIM8
+ *            RCC_APB2Periph_USART1.
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB2PCENR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PCENR &= ~RCC_APB2Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphClockCmd
+ *
+ * @brief   Enables or disables the Low Speed APB (APB1) peripheral clock.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB1PCENR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PCENR &= ~RCC_APB1Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB2PeriphResetCmd
+ *
+ * @brief   Forces or releases High Speed APB (APB2) peripheral reset.
+ *
+ * @param   RCC_APB2Periph - specifies the APB2 peripheral to reset.
+ *            RCC_APB2Periph_AFIO.
+ *            RCC_APB2Periph_GPIOA.
+ *            RCC_APB2Periph_GPIOB.
+ *            RCC_APB2Periph_GPIOC.
+ *            RCC_APB2Periph_GPIOD.
+ *            RCC_APB2Periph_GPIOE
+ *            RCC_APB2Periph_ADC1.
+ *            RCC_APB2Periph_TIM1.
+ *            RCC_APB2Periph_SPI1.
+ *            RCC_APB2Periph_USART1.
+ *          NewState - ENABLE or DISABLE
+ *
+ * @return  none
+ */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB2PRSTR |= RCC_APB2Periph;
+    }
+    else
+    {
+        RCC->APB2PRSTR &= ~RCC_APB2Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_APB1PeriphResetCmd
+ *
+ * @brief   Forces or releases Low Speed APB (APB1) peripheral reset.
+ *
+ * @param   RCC_APB1Periph - specifies the APB1 peripheral to reset.
+ *            RCC_APB1Periph_TIM2.
+ *            RCC_APB1Periph_TIM3.
+ *            RCC_APB1Periph_TIM4.
+ *            RCC_APB1Periph_WWDG.
+ *            RCC_APB1Periph_SPI2.
+ *            RCC_APB1Periph_USART2.
+ *            RCC_APB1Periph_USART3.
+ *            RCC_APB1Periph_I2C1.
+ *            RCC_APB1Periph_I2C2.
+ *            RCC_APB1Periph_USB.
+ *            RCC_APB1Periph_CAN1.
+ *            RCC_APB1Periph_BKP.
+ *            RCC_APB1Periph_PWR.
+ *            RCC_APB1Periph_DAC.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RCC->APB1PRSTR |= RCC_APB1Periph;
+    }
+    else
+    {
+        RCC->APB1PRSTR &= ~RCC_APB1Periph;
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_BackupResetCmd
+ *
+ * @brief   Forces or releases the Backup domain reset.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->BDCTLR |= (1 << 16);
+    }
+    else
+    {
+        RCC->BDCTLR &= ~(1 << 16);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_ClockSecuritySystemCmd
+ *
+ * @brief   Enables or disables the Clock Security System.
+ *
+ * @param   NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+    if(NewState)
+    {
+        RCC->CTLR |= (1 << 19);
+    }
+    else
+    {
+        RCC->CTLR &= ~(1 << 19);
+    }
+}
+
+/*********************************************************************
+ * @fn      RCC_MCOConfig
+ *
+ * @brief   Selects the clock source to output on MCO pin.
+ *
+ * @param   RCC_MCO - specifies the clock source to output.
+ *            RCC_MCO_NoClock - No clock selected.
+ *            RCC_MCO_SYSCLK - System clock selected.
+ *            RCC_MCO_HSI - HSI oscillator clock selected.
+ *            RCC_MCO_HSE - HSE oscillator clock selected.
+ *            RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected.
+ *
+ * @return  none
+ */
+void RCC_MCOConfig(uint8_t RCC_MCO)
+{
+    *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RCC flag is set or not.
+ *
+ * @param   RCC_FLAG - specifies the flag to check.
+ *            RCC_FLAG_HSIRDY - HSI oscillator clock ready.
+ *            RCC_FLAG_HSERDY - HSE oscillator clock ready.
+ *            RCC_FLAG_PLLRDY - PLL clock ready.
+ *            RCC_FLAG_LSERDY - LSE oscillator clock ready.
+ *            RCC_FLAG_LSIRDY - LSI oscillator clock ready.
+ *            RCC_FLAG_PINRST - Pin reset.
+ *            RCC_FLAG_PORRST - POR/PDR reset.
+ *            RCC_FLAG_SFTRST - Software reset.
+ *            RCC_FLAG_IWDGRST - Independent Watchdog reset.
+ *            RCC_FLAG_WWDGRST - Window Watchdog reset.
+ *            RCC_FLAG_LPWRRST - Low Power reset.
+ *
+ * @return  FlagStatus - SET or RESET.
+ */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+    uint32_t tmp = 0;
+    uint32_t statusreg = 0;
+
+    FlagStatus bitstatus = RESET;
+    tmp = RCC_FLAG >> 5;
+
+    if(tmp == 1)
+    {
+        statusreg = RCC->CTLR;
+    }
+    else if(tmp == 2)
+    {
+        statusreg = RCC->BDCTLR;
+    }
+    else
+    {
+        statusreg = RCC->RSTSCKR;
+    }
+
+    tmp = RCC_FLAG & FLAG_Mask;
+
+    if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearFlag
+ *
+ * @brief   Clears the RCC reset flags.
+ *
+ * @return  none
+ */
+void RCC_ClearFlag(void)
+{
+    RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
+}
+
+/*********************************************************************
+ * @fn      RCC_GetITStatus
+ *
+ * @brief   Checks whether the specified RCC interrupt has occurred or not.
+ *
+ * @param   RCC_IT - specifies the RCC interrupt source to check.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  ITStatus - SET or RESET.
+ */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    if((RCC->INTR & RCC_IT) != (uint32_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RCC_ClearITPendingBit
+ *
+ * @brief   Clears the RCC's interrupt pending bits.
+ *
+ * @param   RCC_IT - specifies the interrupt pending bit to clear.
+ *            RCC_IT_LSIRDY - LSI ready interrupt.
+ *            RCC_IT_LSERDY - LSE ready interrupt.
+ *            RCC_IT_HSIRDY - HSI ready interrupt.
+ *            RCC_IT_HSERDY - HSE ready interrupt.
+ *            RCC_IT_PLLRDY - PLL ready interrupt.
+ *            RCC_IT_CSS - Clock Security System interrupt.
+ *
+ * @return  none
+ */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+    *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT;
+}
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_rtc.c

@@ -0,0 +1,273 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_rtc.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the RTC firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ ********************************************************************************/
+#include "ch32v10x_rtc.h"
+
+/* RTC_Private_Defines */
+#define RTC_LSB_MASK     ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
+#define PRLH_MSB_MASK    ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
+
+/*********************************************************************
+ * @fn      RTC_ITConfig
+ *
+ * @brief   Enables or disables the specified RTC interrupts.
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
+ *            RTC_IT_OW - Overflow interrupt
+ *            RTC_IT_ALR - Alarm interrupt
+ *            RTC_IT_SEC - Second interrupt
+ *
+ * @return  NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
+ */
+void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        RTC->CTLRH |= RTC_IT;
+    }
+    else
+    {
+        RTC->CTLRH &= (uint16_t)~RTC_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_EnterConfigMode
+ *
+ * @brief   Enters the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_EnterConfigMode(void)
+{
+    RTC->CTLRL |= RTC_CTLRL_CNF;
+}
+
+/*********************************************************************
+ * @fn      RTC_ExitConfigMode
+ *
+ * @brief   Exits from the RTC configuration mode.
+ *
+ * @return  none
+ */
+void RTC_ExitConfigMode(void)
+{
+    RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
+}
+
+/*********************************************************************
+ * @fn      RTC_GetCounter
+ *
+ * @brief   Gets the RTC counter value
+ *
+ * @return  RTC counter value
+ */
+uint32_t RTC_GetCounter(void)
+{
+    uint16_t high1 = 0, high2 = 0, low = 0;
+
+    high1 = RTC->CNTH;
+    low = RTC->CNTL;
+    high2 = RTC->CNTH;
+
+    if(high1 != high2)
+    {
+        return (((uint32_t)high2 << 16) | RTC->CNTL);
+    }
+    else
+    {
+        return (((uint32_t)high1 << 16) | low);
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_SetCounter
+ *
+ * @brief   Sets the RTC counter value.
+ *
+ * @param   CounterValue - RTC counter new value.
+ *
+ * @return  RTC counter value
+ */
+void RTC_SetCounter(uint32_t CounterValue)
+{
+    RTC_EnterConfigMode();
+    RTC->CNTH = CounterValue >> 16;
+    RTC->CNTL = (CounterValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_SetPrescaler
+ *
+ * @brief   Sets the RTC prescaler value
+ *
+ * @param   PrescalerValue - RTC prescaler new value
+ *
+ * @return  none
+ */
+void RTC_SetPrescaler(uint32_t PrescalerValue)
+{
+    RTC_EnterConfigMode();
+    RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
+    RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_SetAlarm
+ *
+ * @brief   Sets the RTC alarm value
+ *
+ * @param   AlarmValue - RTC alarm new value
+ *
+ * @return  none
+ */
+void RTC_SetAlarm(uint32_t AlarmValue)
+{
+    RTC_EnterConfigMode();
+    RTC->ALRMH = AlarmValue >> 16;
+    RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
+    RTC_ExitConfigMode();
+}
+
+/*********************************************************************
+ * @fn      RTC_GetDivider
+ *
+ * @brief   Gets the RTC divider value
+ *
+ * @return  RTC Divider value
+ */
+uint32_t RTC_GetDivider(void)
+{
+    uint32_t tmp = 0x00;
+    tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16;
+    tmp |= RTC->DIVL;
+    return tmp;
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForLastTask
+ *
+ * @brief   Waits until last write operation on RTC registers has finished
+ *
+ * @return  none
+ */
+void RTC_WaitForLastTask(void)
+{
+    while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_WaitForSynchro
+ *
+ * @brief   Waits until the RTC registers are synchronized with RTC APB clock
+ *
+ * @return  none
+ */
+void RTC_WaitForSynchro(void)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
+    while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
+    {
+    }
+}
+
+/*********************************************************************
+ * @fn      RTC_GetFlagStatus
+ *
+ * @brief   Checks whether the specified RTC flag is set or not
+ *
+ * @param   RTC_FLAG- specifies the flag to check
+ *            RTC_FLAG_RTOFF - RTC Operation OFF flag
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  The new state of RTC_FLAG (SET or RESET)
+ */
+FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+    if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearFlag
+ *
+ * @brief   Clears the RTC's pending flags
+ *
+ * @param   RTC_FLAG - specifies the flag to clear
+ *            RTC_FLAG_RSF - Registers Synchronized flag
+ *            RTC_FLAG_OW - Overflow flag
+ *            RTC_FLAG_ALR - Alarm flag
+ *            RTC_FLAG_SEC - Second flag
+ *
+ * @return  none
+ */
+void RTC_ClearFlag(uint16_t RTC_FLAG)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_FLAG;
+}
+
+/*********************************************************************
+ * @fn      RTC_GetITStatus
+ *
+ * @brief   Checks whether the specified RTC interrupt has occurred or not
+ *
+ * @param   RTC_IT - specifies the RTC interrupts sources to check
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  The new state of the RTC_IT (SET or RESET)
+ */
+ITStatus RTC_GetITStatus(uint16_t RTC_IT)
+{
+    ITStatus bitstatus = RESET;
+
+    bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
+    if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      RTC_ClearITPendingBit
+ *
+ * @brief   Clears the RTC's interrupt pending bits
+ *
+ * @param   RTC_IT - specifies the interrupt pending bit to clear
+ *            RTC_FLAG_OW - Overflow interrupt
+ *            RTC_FLAG_ALR - Alarm interrupt
+ *            RTC_FLAG_SEC - Second interrupt
+ *
+ * @return  none
+ */
+void RTC_ClearITPendingBit(uint16_t RTC_IT)
+{
+    RTC->CTLRL &= (uint16_t)~RTC_IT;
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_spi.c

@@ -0,0 +1,652 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_spi.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the SPI firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *********************************************************************************/
+#include "ch32v10x_spi.h"
+#include "ch32v10x_rcc.h"
+
+/* SPI SPE mask */
+#define CTLR1_SPE_Set         ((uint16_t)0x0040)
+#define CTLR1_SPE_Reset       ((uint16_t)0xFFBF)
+
+/* I2S I2SE mask */
+#define I2SCFGR_I2SE_Set      ((uint16_t)0x0400)
+#define I2SCFGR_I2SE_Reset    ((uint16_t)0xFBFF)
+
+/* SPI CRCNext mask */
+#define CTLR1_CRCNext_Set     ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTLR1_CRCEN_Set       ((uint16_t)0x2000)
+#define CTLR1_CRCEN_Reset     ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTLR2_SSOE_Set        ((uint16_t)0x0004)
+#define CTLR2_SSOE_Reset      ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+#define CTLR1_CLEAR_Mask      ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask    ((uint16_t)0xF040)
+
+/* SPI or I2S mode selection masks */
+#define SPI_Mode_Select       ((uint16_t)0xF7FF)
+#define I2S_Mode_Select       ((uint16_t)0x0800)
+
+/* I2S clock source selection masks */
+#define I2S2_CLOCK_SRC        ((uint32_t)(0x00020000))
+#define I2S3_CLOCK_SRC        ((uint32_t)(0x00040000))
+#define I2S_MUL_MASK          ((uint32_t)(0x0000F000))
+#define I2S_DIV_MASK          ((uint32_t)(0x000000F0))
+
+/*********************************************************************
+ * @fn      SPI_I2S_DeInit
+ *
+ * @brief   Deinitializes the SPIx peripheral registers to their default
+ *        reset values (Affects also the I2Ss).
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
+{
+    if(SPIx == SPI1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+    }
+    else if(SPIx == SPI2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+    else
+    {
+        if(SPIx == SPI3)
+        {
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the SPI_InitStruct.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
+{
+    uint16_t tmpreg = 0;
+
+    tmpreg = SPIx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                         SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
+                         SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
+                         SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+
+    SPIx->CTLR1 = tmpreg;
+    SPIx->I2SCFGR &= SPI_Mode_Select;
+    SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/*********************************************************************
+ * @fn      I2S_Init
+ *
+ * @brief   Initializes the SPIx peripheral according to the specified
+ *        parameters in the I2S_InitStruct.
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *        (configured in I2S mode).
+ *          I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
+ *        contains the configuration information for the specified SPI peripheral
+ *        configured in I2S mode.
+ * @return  none
+ */
+void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
+{
+    uint16_t          tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+    uint32_t          tmp = 0;
+    RCC_ClocksTypeDef RCC_Clocks;
+    uint32_t          sourceclock = 0;
+
+    SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
+    SPIx->I2SPR = 0x0002;
+    tmpreg = SPIx->I2SCFGR;
+
+    if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+    {
+        i2sodd = (uint16_t)0;
+        i2sdiv = (uint16_t)2;
+    }
+    else
+    {
+        if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+        {
+            packetlength = 1;
+        }
+        else
+        {
+            packetlength = 2;
+        }
+
+        if(((uint32_t)SPIx) == SPI2_BASE)
+        {
+            tmp = I2S2_CLOCK_SRC;
+        }
+        else
+        {
+            tmp = I2S3_CLOCK_SRC;
+        }
+
+        RCC_GetClocksFreq(&RCC_Clocks);
+
+        sourceclock = RCC_Clocks.SYSCLK_Frequency;
+
+        if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+        {
+            tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+        }
+        else
+        {
+            tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+        }
+
+        tmp = tmp / 10;
+        i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+        i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+        i2sodd = (uint16_t)(i2sodd << 8);
+    }
+
+    if((i2sdiv < 2) || (i2sdiv > 0xFF))
+    {
+        i2sdiv = 2;
+        i2sodd = 0;
+    }
+
+    SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+    tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                                                      (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                                                                                                           (uint16_t)I2S_InitStruct->I2S_CPOL))));
+    SPIx->I2SCFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_StructInit
+ *
+ * @brief   Fills each SPI_InitStruct member with its default value.
+ *
+ * @param   SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
+{
+    SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+    SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+    SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+    SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+    SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+    SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+    SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+    SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/*********************************************************************
+ * @fn      I2S_StructInit
+ *
+ * @brief   Fills each I2S_InitStruct member with its default value.
+ *
+ * @param   I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
+ *        will be initialized.
+ *
+ * @return  none
+ */
+void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
+{
+    I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+    I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+    I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+    I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+    I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+    I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/*********************************************************************
+ * @fn      SPI_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR1 |= CTLR1_SPE_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_SPE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      I2S_Cmd
+ *
+ * @brief   Enables or disables the specified SPI peripheral (in I2S mode).
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
+    }
+    else
+    {
+        SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ITConfig
+ *
+ * @brief   Enables or disables the specified SPI/I2S interrupts.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
+ *        enabled or disabled.
+ *            SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
+ *            SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
+ *            SPI_I2S_IT_ERR - Error interrupt mask.
+ *          NewState: ENABLE or DISABLE.
+ * @return  none
+ */
+void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+    uint16_t itpos = 0, itmask = 0;
+
+    itpos = SPI_I2S_IT >> 4;
+    itmask = (uint16_t)1 << (uint16_t)itpos;
+
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= itmask;
+    }
+    else
+    {
+        SPIx->CTLR2 &= (uint16_t)~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_DMACmd
+ *
+ * @brief   Enables or disables the SPIx/I2Sx DMA interface.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
+ *        be enabled or disabled.
+ *            SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
+ *            SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= SPI_I2S_DMAReq;
+    }
+    else
+    {
+        SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_SendData
+ *
+ * @brief   Transmits a Data through the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  none
+ */
+void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
+{
+    SPIx->DATAR = Data;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the SPIx/I2Sx peripheral.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          Data - Data to be transmitted.
+ *
+ * @return  SPIx->DATAR - The value of the received data.
+ */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
+{
+    return SPIx->DATAR;
+}
+
+/*********************************************************************
+ * @fn      SPI_NSSInternalSoftwareConfig
+ *
+ * @brief   Configures internally by software the NSS pin for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_NSSInternalSoft -
+ *            SPI_NSSInternalSoft_Set - Set NSS pin internally.
+ *            SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
+ *
+ * @return  none
+ */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
+{
+    if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+    {
+        SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_SSOutputCmd
+ *
+ * @brief   Enables or disables the SS output for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx SS output.
+ *
+ * @return  none
+ */
+void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR2 |= CTLR2_SSOE_Set;
+    }
+    else
+    {
+        SPIx->CTLR2 &= CTLR2_SSOE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_DataSizeConfig
+ *
+ * @brief   Configures the data size for the selected SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_DataSize - specifies the SPI data size.
+ *            SPI_DataSize_16b - Set data frame format to 16bit.
+ *            SPI_DataSize_8b - Set data frame format to 8bit.
+ *
+ * @return  none
+ */
+void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
+{
+    SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
+    SPIx->CTLR1 |= SPI_DataSize;
+}
+
+/*********************************************************************
+ * @fn      SPI_TransmitCRC
+ *
+ * @brief   Transmit the SPIx CRC value.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  none
+ */
+void SPI_TransmitCRC(SPI_TypeDef *SPIx)
+{
+    SPIx->CTLR1 |= CTLR1_CRCNext_Set;
+}
+
+/*********************************************************************
+ * @fn      SPI_CalculateCRC
+ *
+ * @brief   Enables or disables the CRC value calculation of the transferred bytes.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          NewState - new state of the SPIx CRC value calculation.
+ *
+ * @return  none
+ */
+void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        SPIx->CTLR1 |= CTLR1_CRCEN_Set;
+    }
+    else
+    {
+        SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRC
+ *
+ * @brief   Returns the transmit or the receive CRC register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_CRC - specifies the CRC register to be read.
+ *            SPI_CRC_Tx - Selects Tx CRC register.
+ *            SPI_CRC_Rx - Selects Rx CRC register.
+ *
+ * @return  crcreg: The selected CRC register value.
+ */
+uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
+{
+    uint16_t crcreg = 0;
+
+    if(SPI_CRC != SPI_CRC_Rx)
+    {
+        crcreg = SPIx->TCRCR;
+    }
+    else
+    {
+        crcreg = SPIx->RCRCR;
+    }
+
+    return crcreg;
+}
+
+/*********************************************************************
+ * @fn      SPI_GetCRCPolynomial
+ *
+ * @brief   Returns the CRC Polynomial register value for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *
+ * @return  SPIx->CRCR - The CRC Polynomial register value.
+ */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
+{
+    return SPIx->CRCR;
+}
+
+/*********************************************************************
+ * @fn      SPI_BiDirectionalLineConfig
+ *
+ * @brief   Selects the data transfer direction in bi-directional mode
+ *      for the specified SPI.
+ *
+ * @param   SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
+ *          SPI_Direction - specifies the data transfer direction in
+ *        bi-directional mode.
+ *            SPI_Direction_Tx - Selects Tx transmission direction.
+ *            SPI_Direction_Rx - Selects Rx receive direction.
+ *
+ * @return  none
+ */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
+{
+    if(SPI_Direction == SPI_Direction_Tx)
+    {
+        SPIx->CTLR1 |= SPI_Direction_Tx;
+    }
+    else
+    {
+        SPIx->CTLR1 &= SPI_Direction_Rx;
+    }
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetFlagStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S flag is set or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
+ *            SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
+ *            SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
+ *            SPI_I2S_FLAG_BSY - Busy flag.
+ *            SPI_I2S_FLAG_OVR - Overrun flag.
+ *            SPI_FLAG_MODF - Mode Fault flag.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *            I2S_FLAG_UDR - Underrun Error flag.
+ *            I2S_FLAG_CHSIDE - Channel Side flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearFlag
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) flag.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_FLAG - specifies the SPI flag to clear.
+ *            SPI_FLAG_CRCERR - CRC Error flag.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
+{
+    SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_GetITStatus
+ *
+ * @brief   Checks whether the specified SPI/I2S interrupt has occurred or not.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *            - 2 or 3 in I2S mode.
+ *          SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
+ *            SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
+ *            SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
+ *            SPI_I2S_IT_OVR - Overrun interrupt.
+ *            SPI_IT_MODF - Mode Fault interrupt.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *            I2S_IT_UDR - Underrun Error interrupt.
+ *
+ * @return  FlagStatus: SET or RESET.
+ */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+    itmask = SPI_I2S_IT >> 4;
+    itmask = 0x01 << itmask;
+    enablestatus = (SPIx->CTLR2 & itmask);
+
+    if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      SPI_I2S_ClearITPendingBit
+ *
+ * @brief   Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+ *
+ * @param   SPIx - where x can be
+ *            - 1, 2 or 3 in SPI mode.
+ *          SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
+ *            SPI_IT_CRCERR - CRC Error interrupt.
+ *
+ * @return  none
+ */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
+{
+    uint16_t itpos = 0;
+
+    itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+    SPIx->STATR = (uint16_t)~itpos;
+}
+
+
+
+
+
+

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_tim.c

@@ -0,0 +1,2353 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_tim.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the TIM firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_tim.h"
+#include "ch32v10x_rcc.h"
+
+/* TIM registers bit mask */
+#define SMCFGR_ETR_Mask    ((uint16_t)0x00FF)
+#define CHCTLR_Offset      ((uint16_t)0x0018)
+#define CCER_CCE_Set       ((uint16_t)0x0001)
+#define CCER_CCNE_Set      ((uint16_t)0x0004)
+
+static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+
+/*********************************************************************
+ * @fn      TIM_DeInit
+ *
+ * @brief   Deinitializes the TIMx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *
+ * @return  none
+ */
+void TIM_DeInit(TIM_TypeDef *TIMx)
+{
+    if(TIMx == TIM1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
+    }
+    else if(TIMx == TIM2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+    }
+    else if(TIMx == TIM3)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+    }
+    else if(TIMx == TIM4)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_TimeBaseInit
+ *
+ * @brief   Initializes the TIMx Time Base Unit peripheral according to
+ *        the specified parameters in the TIM_TimeBaseInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef
+ *        structure.
+ *
+ * @return  none
+ */
+void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    uint16_t tmpcr1 = 0;
+
+    tmpcr1 = TIMx->CTLR1;
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+    {
+        tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
+        tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+    }
+
+    tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+
+    TIMx->CTLR1 = tmpcr1;
+    TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period;
+    TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+
+    if(TIMx == TIM1)
+    {
+        TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+    }
+
+    TIMx->SWEVGR = TIM_PSCReloadMode_Immediate;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1Init
+ *
+ * @brief   Initializes the TIMx Channel1 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E);
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR1;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S));
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P));
+    tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+    tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+
+    if(TIMx == TIM1)
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP));
+        tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE));
+        tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N));
+
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+        tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR1 = tmpccmrx;
+    TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2Init
+ *
+ * @brief   Initializes the TIMx Channel2 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR1;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S));
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+
+    if(TIMx == TIM1)
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR1 = tmpccmrx;
+    TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3Init
+ *
+ * @brief   Initializes the TIMx Channel3 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR2;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S));
+    tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+
+    if(TIMx == TIM1)
+    {
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+        tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE));
+        tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3));
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR2 = tmpccmrx;
+    TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4Init
+ *
+ * @brief   Initializes the TIMx Channel4 according to the specified
+ *        parameters in the TIM_OCInitStruct.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+
+    TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E));
+    tmpccer = TIMx->CCER;
+    tmpcr2 = TIMx->CTLR2;
+    tmpccmrx = TIMx->CHCTLR2;
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M));
+    tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S));
+    tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+    tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P));
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+
+    if(TIMx == TIM1)
+    {
+        tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4));
+        tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+    }
+
+    TIMx->CTLR2 = tmpcr2;
+    TIMx->CHCTLR2 = tmpccmrx;
+    TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_ICInit
+ *
+ * @brief   IInitializes the TIM peripheral according to the specified
+ *        parameters in the TIM_ICInitStruct.
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+    {
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+    {
+        TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+                   TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_PWMIConfig
+ *
+ * @brief   Configures the TIM peripheral according to the specified
+ *        parameters in the TIM_ICInitStruct to measure an external
+ *        PWM signal.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+    uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+
+    if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+    {
+        icoppositepolarity = TIM_ICPolarity_Falling;
+    }
+    else
+    {
+        icoppositepolarity = TIM_ICPolarity_Rising;
+    }
+
+    if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+    {
+        icoppositeselection = TIM_ICSelection_IndirectTI;
+    }
+    else
+    {
+        icoppositeselection = TIM_ICSelection_DirectTI;
+    }
+
+    if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+    {
+        TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+    else
+    {
+        TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+                   TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+        TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+        TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_BDTRConfig
+ *
+ * @brief   Configures the: Break feature, dead time, Lock level, the OSSI,
+ *      the OSSR State and the AOE(automatic output enable).
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+                 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+                 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+                 TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/*********************************************************************
+ * @fn      TIM_TimeBaseStructInit
+ *
+ * @brief   Fills each TIM_TimeBaseInitStruct member with its default value.
+ *
+ * @param   TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct)
+{
+    TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
+    TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+    TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+    TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+    TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/*********************************************************************
+ * @fn      TIM_OCStructInit
+ *
+ * @brief   Fills each TIM_OCInitStruct member with its default value.
+ *
+ * @param   TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct)
+{
+    TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+    TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+    TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+    TIM_OCInitStruct->TIM_Pulse = 0x0000;
+    TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+    TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+    TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/*********************************************************************
+ * @fn      TIM_ICStructInit
+ *
+ * @brief   Fills each TIM_ICInitStruct member with its default value.
+ *
+ * @param   TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct)
+{
+    TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+    TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+    TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+    TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+    TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/*********************************************************************
+ * @fn      TIM_BDTRStructInit
+ *
+ * @brief   Fills each TIM_BDTRInitStruct member with its default value.
+ *
+ * @param   TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure.
+ *
+ * @return  none
+ */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+    TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+    TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+    TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+    TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+    TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+    TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+    TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/*********************************************************************
+ * @fn      TIM_Cmd
+ *
+ * @brief   Enables or disables the specified TIM peripheral.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_CEN;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN));
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_CtrlPWMOutputs
+ *
+ * @brief   Enables or disables the TIM peripheral Main Outputs.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->BDTR |= TIM_MOE;
+    }
+    else
+    {
+        TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE));
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_ITConfig
+ *
+ * @brief   Enables or disables the specified TIM interrupts.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupts sources to be enabled or disabled.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->DMAINTENR |= TIM_IT;
+    }
+    else
+    {
+        TIMx->DMAINTENR &= (uint16_t)~TIM_IT;
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_GenerateEvent
+ *
+ * @brief   Configures the TIMx event to be generate by software.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupts sources to be enabled or disabled.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource)
+{
+    TIMx->SWEVGR = TIM_EventSource;
+}
+
+/*********************************************************************
+ * @fn      TIM_DMAConfig
+ *
+ * @brief   Configures the TIMx's DMA interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_DMABase: DMA Base address.
+ *            TIM_DMABase_CR.
+ *            TIM_DMABase_CR2.
+ *            TIM_DMABase_SMCR.
+ *            TIM_DMABase_DIER.
+ *            TIM1_DMABase_SR.
+ *            TIM_DMABase_EGR.
+ *            TIM_DMABase_CCMR1.
+ *            TIM_DMABase_CCMR2.
+ *            TIM_DMABase_CCER.
+ *            TIM_DMABase_CNT.
+ *            TIM_DMABase_PSC.
+ *            TIM_DMABase_CCR1.
+ *            TIM_DMABase_CCR2.
+ *            TIM_DMABase_CCR3.
+ *            TIM_DMABase_CCR4.
+ *            TIM_DMABase_BDTR.
+ *            TIM_DMABase_DCR.
+ *          TIM_DMABurstLength - DMA Burst length.
+ *            TIM_DMABurstLength_1Transfer.
+ *            TIM_DMABurstLength_18Transfers.
+ *
+ * @return  none
+ */
+void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+    TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/*********************************************************************
+ * @fn      TIM_DMACmd
+ *
+ * @brief   Enables or disables the TIMx's DMA Requests.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_DMASource - specifies the DMA Request sources.
+ *            TIM_DMA_Update - TIM update Interrupt source.
+ *            TIM_DMA_CC1 - TIM Capture Compare 1 DMA source.
+ *            TIM_DMA_CC2 - TIM Capture Compare 2 DMA source.
+ *            TIM_DMA_CC3 - TIM Capture Compare 3 DMA source.
+ *            TIM_DMA_CC4 - TIM Capture Compare 4 DMA source.
+ *            TIM_DMA_COM - TIM Commutation DMA source.
+ *            TIM_DMA_Trigger - TIM Trigger DMA source.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->DMAINTENR |= TIM_DMASource;
+    }
+    else
+    {
+        TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource;
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_InternalClockConfig
+ *
+ * @brief   Configures the TIMx internal Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *
+ * @return  none
+ */
+void TIM_InternalClockConfig(TIM_TypeDef *TIMx)
+{
+    TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS));
+}
+
+/*********************************************************************
+ * @fn      TIM_ITRxExternalClockConfig
+ *
+ * @brief   Configures the TIMx Internal Trigger as External Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_InputTriggerSource: Trigger source.
+ *            TIM_TS_ITR0 - Internal Trigger 0.
+ *            TIM_TS_ITR1 - Internal Trigger 1.
+ *            TIM_TS_ITR2 - Internal Trigger 2.
+ *            TIM_TS_ITR3 - Internal Trigger 3.
+ *
+ * @return  none
+ */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
+{
+    TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+    TIMx->SMCFGR |= TIM_SlaveMode_External1;
+}
+
+/*********************************************************************
+ * @fn      TIM_TIxExternalClockConfig
+ *
+ * @brief   Configures the TIMx Trigger as External Clock.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_TIxExternalCLKSource - Trigger source.
+ *            TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector.
+ *            TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1.
+ *            TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2.
+ *          TIM_ICPolarity - specifies the TIx Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *             TIM_DMA_COM - TIM Commutation DMA source.
+ *             TIM_DMA_Trigger - TIM Trigger DMA source.
+ *          ICFilter - specifies the filter value.
+ *             This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+    if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+    {
+        TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+    else
+    {
+        TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+    }
+
+    TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+    TIMx->SMCFGR |= TIM_SlaveMode_External1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRClockMode1Config
+ *
+ * @brief   Configures the External clock Mode1.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *             This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
+    tmpsmcr |= TIM_SlaveMode_External1;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
+    tmpsmcr |= TIM_TS_ETRF;
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRClockMode2Config
+ *
+ * @brief   Configures the External clock Mode2.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *            This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+    TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+    TIMx->SMCFGR |= TIM_ECE;
+}
+
+/*********************************************************************
+ * @fn      TIM_ETRConfig
+ *
+ * @brief   Configures the TIMx External Trigger (ETR).
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ExtTRGPrescaler - The external Trigger Prescaler.
+ *            TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF.
+ *            TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2.
+ *            TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4.
+ *            TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8.
+ *          TIM_ExtTRGPolarity - The external Trigger Polarity.
+ *            TIM_ExtTRGPolarity_Inverted - active low or falling edge active.
+ *            TIM_ExtTRGPolarity_NonInverted - active high or rising edge active.
+ *          ExtTRGFilter - External Trigger Filter.
+ *            This parameter must be a value between 0x0 and 0xF.
+ *
+ * @return  none
+ */
+void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter)
+{
+    uint16_t tmpsmcr = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= SMCFGR_ETR_Mask;
+    tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_PrescalerConfig
+ *
+ * @brief   Configures the TIMx Prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          Prescaler - specifies the Prescaler Register value.
+ *          TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
+ *            TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode.
+ *            TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event.
+ *            TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately.
+ *
+ * @return  none
+ */
+void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+    TIMx->PSC = Prescaler;
+    TIMx->SWEVGR = TIM_PSCReloadMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_CounterModeConfig
+ *
+ * @brief   Specifies the TIMx Counter Mode to be used.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_CounterMode - specifies the Counter Mode to be used.
+ *            TIM_CounterMode_Up - TIM Up Counting Mode.
+ *            TIM_CounterMode_Down - TIM Down Counting Mode.
+ *            TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1.
+ *            TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2.
+ *            TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3.
+ *
+ * @return  none
+ */
+void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode)
+{
+    uint16_t tmpcr1 = 0;
+
+    tmpcr1 = TIMx->CTLR1;
+    tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS)));
+    tmpcr1 |= TIM_CounterMode;
+    TIMx->CTLR1 = tmpcr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectInputTrigger
+ *
+ * @brief   Selects the Input Trigger source.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_InputTriggerSource - The Input Trigger source.
+ *            TIM_TS_ITR0 - Internal Trigger 0.
+ *            TIM_TS_ITR1 - Internal Trigger 1.
+ *            TIM_TS_ITR2 - Internal Trigger 2.
+ *            TIM_TS_ITR3 - Internal Trigger 3.
+ *            TIM_TS_TI1F_ED - TI1 Edge Detector.
+ *            TIM_TS_TI1FP1 - Filtered Timer Input 1.
+ *            TIM_TS_TI2FP2 - Filtered Timer Input 2.
+ *            TIM_TS_ETRF - External Trigger input.
+ *
+ * @return  none
+ */
+void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource)
+{
+    uint16_t tmpsmcr = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS));
+    tmpsmcr |= TIM_InputTriggerSource;
+    TIMx->SMCFGR = tmpsmcr;
+}
+
+/*********************************************************************
+ * @fn      TIM_EncoderInterfaceConfig
+ *
+ * @brief   Configures the TIMx Encoder Interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_EncoderMode - specifies the TIMx Encoder Mode.
+ *            TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending
+ *        on TI2FP2 level.
+ *            TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending
+ *        on TI1FP1 level.
+ *            TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and
+ *        TI2FP2 edges depending.
+ *          TIM_IC1Polarity - specifies the IC1 Polarity.
+ *            TIM_ICPolarity_Falling - IC Falling edge.
+ *            TTIM_ICPolarity_Rising - IC Rising edge.
+ *          TIM_IC2Polarity - specifies the IC2 Polarity.
+ *            TIM_ICPolarity_Falling - IC Falling edge.
+ *            TIM_ICPolarity_Rising - IC Rising edge.
+ *
+ * @return  none
+ */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+    uint16_t tmpsmcr = 0;
+    uint16_t tmpccmr1 = 0;
+    uint16_t tmpccer = 0;
+
+    tmpsmcr = TIMx->SMCFGR;
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS));
+    tmpsmcr |= TIM_EncoderMode;
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S)));
+    tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0;
+    tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P)));
+    tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+    TIMx->SMCFGR = tmpsmcr;
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC1Config
+ *
+ * @brief   Forces the TIMx output 1 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC1REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC1REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M);
+    tmpccmr1 |= TIM_ForcedAction;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC2Config
+ *
+ * @brief   Forces the TIMx output 2 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC2REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC2REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M);
+    tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC3Config
+ *
+ * @brief   Forces the TIMx output 3 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC3REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC3REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M);
+    tmpccmr2 |= TIM_ForcedAction;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ForcedOC4Config
+ *
+ * @brief   Forces the TIMx output 4 waveform to active or inactive level.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_ForcedAction - specifies the forced Action to be set to the
+ *        output waveform.
+ *            TIM_ForcedAction_Active - Force active level on OC4REF.
+ *            TIM_ForcedAction_InActive - Force inactive level on OC4REF.
+ *
+ * @return  none
+ */
+void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M);
+    tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ARRPreloadConfig
+ *
+ * @brief   Enables or disables TIMx peripheral Preload register on ARR.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_ARPE;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectCOM
+ *
+ * @brief   Selects the TIM peripheral Commutation event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCUS;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectCCDMA
+ *
+ * @brief   Selects the TIMx peripheral Capture Compare DMA source.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCDS;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_CCPreloadControl
+ *
+ * @brief   DSets or Resets the TIM peripheral Capture Compare Preload Control bit.
+ *        reset values (Affects also the I2Ss).
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_CCPC;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR1.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE);
+    tmpccmr1 |= TIM_OCPreload;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR2.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE);
+    tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR3.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE);
+    tmpccmr2 |= TIM_OCPreload;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4PreloadConfig
+ *
+ * @brief   Enables or disables the TIMx peripheral Preload register on CCR4.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPreload - new state of the TIMx peripheral Preload register.
+ *            TIM_OCPreload_Enable.
+ *            TIM_OCPreload_Disable.
+ *
+ * @return  none
+ */
+void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE);
+    tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 1 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE);
+    tmpccmr1 |= TIM_OCFast;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 2 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE);
+    tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 3 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE);
+    tmpccmr2 |= TIM_OCFast;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4FastConfig
+ *
+ * @brief   Configures the TIMx Output Compare 4 Fast feature.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCFast - new state of the Output Compare Fast Enable Bit.
+ *            TIM_OCFast_Enable - TIM output compare fast enable.
+ *            TIM_OCFast_Disable - TIM output compare fast disable.
+ *
+ * @return  none
+ */
+void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE);
+    tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC1Ref
+ *
+ * @brief   Clears or safeguards the OCREF1 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE);
+    tmpccmr1 |= TIM_OCClear;
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC2Ref
+ *
+ * @brief   Clears or safeguards the OCREF2 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr1 = 0;
+
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE);
+    tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+    TIMx->CHCTLR1 = tmpccmr1;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC3Ref
+ *
+ * @brief   Clears or safeguards the OCREF3 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE);
+    tmpccmr2 |= TIM_OCClear;
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearOC4Ref
+ *
+ * @brief   Clears or safeguards the OCREF4 signal on an external event.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCClear - new state of the Output Compare Clear Enable Bit.
+ *            TIM_OCClear_Enable - TIM Output clear enable.
+ *            TIM_OCClear_Disable - TIM Output clear disable.
+ *
+ * @return  none
+ */
+void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear)
+{
+    uint16_t tmpccmr2 = 0;
+
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE);
+    tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+    TIMx->CHCTLR2 = tmpccmr2;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1PolarityConfig
+ *
+ * @brief   Configures the TIMx channel 1 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPolarity - specifies the OC1 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P);
+    tmpccer |= TIM_OCPolarity;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC1NPolarityConfig
+ *
+ * @brief   Configures the TIMx channel 1 polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC1N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP);
+    tmpccer |= TIM_OCNPolarity;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2PolarityConfig
+ *
+ * @brief   Configures the TIMx channel 2 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 to select the TIM peripheral.
+ *          TIM_OCPolarity - specifies the OC2 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC2NPolarityConfig
+ *
+ * @brief   Configures the TIMx channel 2 polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC1N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP);
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3PolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 3 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OCPolarit - specifies the OC3 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC3NPolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 3N polarity.
+ *
+ * @param   TIMx - where x can be 1 to select the TIM peripheral.
+ *          TIM_OCNPolarity - specifies the OC2N Polarity.
+ *            TIM_OCNPolarity_High - Output Compare active high.
+ *            TIM_OCNPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP);
+    tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_OC4PolarityConfig
+ *
+ * @brief   Configures the TIMx Channel 4 polarity.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OCPolarit - specifies the OC3 Polarity.
+ *            TIM_OCPolarity_High - Output Compare active high.
+ *            TIM_OCPolarity_Low - Output Compare active low.
+ *
+ * @return  none
+ */
+void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity)
+{
+    uint16_t tmpccer = 0;
+
+    tmpccer = TIMx->CCER;
+    tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P);
+    tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TIM_CCxCmd
+ *
+ * @brief   Enables or disables the TIM Capture Compare Channel x.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *            TIM_Channel_4 - TIM Channel 4.
+ *          TIM_CCx - specifies the TIM Channel CCxE bit new state.
+ *            TIM_CCx_Enable.
+ *            TIM_CCx_Disable.
+ *
+ * @return  none
+ */
+void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+    uint16_t tmp = 0;
+
+    tmp = CCER_CCE_Set << TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp;
+    TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/*********************************************************************
+ * @fn      TIM_CCxNCmd
+ *
+ * @brief   Enables or disables the TIM Capture Compare Channel xN.
+ *
+ * @param   TIMx - where x can be 1 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *          TIM_CCxN - specifies the TIM Channel CCxNE bit new state.
+ *            TIM_CCxN_Enable.
+ *            TIM_CCxN_Disable.
+ *
+ * @return  none
+ */
+void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+    uint16_t tmp = 0;
+
+    tmp = CCER_CCNE_Set << TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp;
+    TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOCxM
+ *
+ * @brief   Selects the TIM Output Compare Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_Channel - specifies the TIM Channel.
+ *            TIM_Channel_1 - TIM Channel 1.
+ *            TIM_Channel_2 - TIM Channel 2.
+ *            TIM_Channel_3 - TIM Channel 3.
+ *            TIM_Channel_4 - TIM Channel 4.
+ *          TIM_OCMode - specifies the TIM Output Compare Mode.
+ *            TIM_OCMode_Timing.
+ *            TIM_OCMode_Active.
+ *            TIM_OCMode_Toggle.
+ *            TIM_OCMode_PWM1.
+ *            TIM_OCMode_PWM2.
+ *            TIM_ForcedAction_Active.
+ *            TIM_ForcedAction_InActive.
+ *
+ * @return  none
+ */
+void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+    uint32_t tmp = 0;
+    uint16_t tmp1 = 0;
+
+    tmp = (uint32_t)TIMx;
+    tmp += CHCTLR_Offset;
+    tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
+    TIMx->CCER &= (uint16_t)~tmp1;
+
+    if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3))
+    {
+        tmp += (TIM_Channel >> 1);
+        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M);
+        *(__IO uint32_t *)tmp |= TIM_OCMode;
+    }
+    else
+    {
+        tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1;
+        *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M);
+        *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_UpdateDisableConfig
+ *
+ * @brief   Enables or Disables the TIMx Update event.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR1 |= TIM_UDIS;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_UpdateRequestConfig
+ *
+ * @brief   Configures the TIMx Update Request Interrupt source.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_UpdateSource - specifies the Update source.
+ *            TIM_UpdateSource_Regular.
+ *            TIM_UpdateSource_Global.
+ *
+ * @return  none
+ */
+void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource)
+{
+    if(TIM_UpdateSource != TIM_UpdateSource_Global)
+    {
+        TIMx->CTLR1 |= TIM_URS;
+    }
+    else
+    {
+        TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectHallSensor
+ *
+ * @brief   Enables or disables the TIMx's Hall sensor interface.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        TIMx->CTLR2 |= TIM_TI1S;
+    }
+    else
+    {
+        TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S);
+    }
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOnePulseMode
+ *
+ * @brief   Selects the TIMx's One Pulse Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_OPMode - specifies the OPM Mode to be used.
+ *            TIM_OPMode_Single.
+ *            TIM_OPMode_Repetitive.
+ *
+ * @return  none
+ */
+void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode)
+{
+    TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM);
+    TIMx->CTLR1 |= TIM_OPMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectOutputTrigger
+ *
+ * @brief   Selects the TIMx Trigger Output Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_TRGOSource - specifies the Trigger Output source.
+ *            TIM_TRGOSource_Reset -  The UG bit in the TIM_EGR register is
+ *        used as the trigger output (TRGO).
+ *            TIM_TRGOSource_Enable - The Counter Enable CEN is used as the
+ *        trigger output (TRGO).
+ *            TIM_TRGOSource_Update - The update event is selected as the
+ *        trigger output (TRGO).
+ *            TIM_TRGOSource_OC1 - The trigger output sends a positive pulse
+ *        when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO).
+ *            TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO).
+ *            TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO).
+ *
+ * @return  none
+ */
+void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource)
+{
+    TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS);
+    TIMx->CTLR2 |= TIM_TRGOSource;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectSlaveMode
+ *
+ * @brief   Selects the TIMx Slave Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_SlaveMode - specifies the Timer Slave Mode.
+ *            TIM_SlaveMode_Reset - Rising edge of the selected trigger
+ *        signal (TRGI) re-initializes.
+ *            TIM_SlaveMode_Gated - The counter clock is enabled when the
+ *        trigger signal (TRGI) is high.
+ *            TIM_SlaveMode_Trigger - The counter starts at a rising edge
+ *        of the trigger TRGI.
+ *            TIM_SlaveMode_External1 - Rising edges of the selected trigger
+ *        (TRGI) clock the counter.
+ *
+ * @return  none
+ */
+void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode)
+{
+    TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS);
+    TIMx->SMCFGR |= TIM_SlaveMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SelectMasterSlaveMode
+ *
+ * @brief   Sets or Resets the TIMx Master/Slave Mode.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_MasterSlaveMode - specifies the Timer Master Slave Mode.
+ *            TIM_MasterSlaveMode_Enable - synchronization between the current
+ *        timer and its slaves (through TRGO).
+ *            TIM_MasterSlaveMode_Disable - No action.
+ *
+ * @return  none
+ */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode)
+{
+    TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM);
+    TIMx->SMCFGR |= TIM_MasterSlaveMode;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCounter
+ *
+ * @brief   Sets the TIMx Counter Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Counter - specifies the Counter register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter)
+{
+    TIMx->CNT = Counter;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetAutoreload
+ *
+ * @brief   Sets the TIMx Autoreload Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Autoreload - specifies the Autoreload register new value.
+ *
+ * @return  none
+ */
+void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload)
+{
+    TIMx->ATRLR = Autoreload;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare1
+ *
+ * @brief   Sets the TIMx Capture Compare1 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1)
+{
+    TIMx->CH1CVR = Compare1;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare2
+ *
+ * @brief   Sets the TIMx Capture Compare2 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2)
+{
+    TIMx->CH2CVR = Compare2;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare3
+ *
+ * @brief   Sets the TIMx Capture Compare3 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3)
+{
+    TIMx->CH3CVR = Compare3;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetCompare4
+ *
+ * @brief   Sets the TIMx Capture Compare4 Register value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          Compare1 - specifies the Capture Compare1 register new value.
+ *
+ * @return  none
+ */
+void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4)
+{
+    TIMx->CH4CVR = Compare4;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC1Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 1 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC);
+    TIMx->CHCTLR1 |= TIM_ICPSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC2Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 2 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC);
+    TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC3Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 3 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC);
+    TIMx->CHCTLR2 |= TIM_ICPSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_SetIC4Prescaler
+ *
+ * @brief   Sets the TIMx Input Capture 4 prescaler.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_ICPSC - specifies the Input Capture1 prescaler new value.
+ *            TIM_ICPSC_DIV1 - no prescaler.
+ *            TIM_ICPSC_DIV2 - capture is done once every 2 events.
+ *            TIM_ICPSC_DIV4 - capture is done once every 4 events.
+ *            TIM_ICPSC_DIV8 - capture is done once every 8 events.
+ *
+ * @return  none
+ */
+void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC)
+{
+    TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC);
+    TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/*********************************************************************
+ * @fn      TIM_SetClockDivision
+ *
+ * @brief   Sets the TIMx Clock Division value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_CKD - specifies the clock division value.
+ *            TIM_CKD_DIV1 - TDTS = Tck_tim.
+ *            TIM_CKD_DIV2 - TDTS = 2*Tck_tim.
+ *            TIM_CKD_DIV4 - TDTS = 4*Tck_tim.
+ *
+ * @return  none
+ */
+void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD)
+{
+    TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD);
+    TIMx->CTLR1 |= TIM_CKD;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture1
+ *
+ * @brief   Gets the TIMx Input Capture 1 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH1CVR - Capture Compare 1 Register value.
+ */
+uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH1CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture2
+ *
+ * @brief   Gets the TIMx Input Capture 2 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH2CVR - Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH2CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture2
+ *
+ * @brief   Gets the TIMx Input Capture 2 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH2CVR - Capture Compare 2 Register value.
+ */
+uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH3CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCapture4
+ *
+ * @brief   Gets the TIMx Input Capture 4 value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CH4CVR - Capture Compare 4 Register value.
+ */
+uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx)
+{
+    return TIMx->CH4CVR;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetCounter
+ *
+ * @brief   Gets the TIMx Counter value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->CNT - Counter Register value.
+ */
+uint16_t TIM_GetCounter(TIM_TypeDef *TIMx)
+{
+    return TIMx->CNT;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetPrescaler
+ *
+ * @brief   Gets the TIMx Prescaler value.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *
+ * @return  TIMx->PSC - Prescaler Register value.
+ */
+uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx)
+{
+    return TIMx->PSC;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetFlagStatus
+ *
+ * @brief   Checks whether the specified TIM flag is set or not.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_FLAG - specifies the flag to check.
+ *            TIM_FLAG_Update - TIM update Flag.
+ *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
+ *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
+ *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
+ *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
+ *            TIM_FLAG_COM - TIM Commutation Flag.
+ *            TIM_FLAG_Trigger - TIM Trigger Flag.
+ *            TIM_FLAG_Break - TIM Break Flag.
+ *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
+ *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
+ *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
+ *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
+ *
+ * @return  SET or RESET.
+ */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
+{
+    ITStatus bitstatus = RESET;
+
+    if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearFlag
+ *
+ * @brief   Clears the TIMx's pending flags.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_FLAG - specifies the flag to check.
+ *            TIM_FLAG_Update - TIM update Flag.
+ *            TIM_FLAG_CC1 - TIM Capture Compare 1 Flag.
+ *            TIM_FLAG_CC2 - TIM Capture Compare 2 Flag.
+ *            TIM_FLAG_CC3 - TIM Capture Compare 3 Flag.
+ *            TIM_FLAG_CC4 - TIM Capture Compare 4 Flag.
+ *            TIM_FLAG_COM - TIM Commutation Flag.
+ *            TIM_FLAG_Trigger - TIM Trigger Flag.
+ *            TIM_FLAG_Break - TIM Break Flag.
+ *            TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag.
+ *            TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag.
+ *            TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag.
+ *            TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag.
+ *
+ * @return  none
+ */
+void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG)
+{
+    TIMx->INTFR = (uint16_t)~TIM_FLAG;
+}
+
+/*********************************************************************
+ * @fn      TIM_GetITStatus
+ *
+ * @brief   Checks whether the TIM interrupt has occurred or not.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupt source to check.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *
+ * @return  none
+ */
+ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT)
+{
+    ITStatus bitstatus = RESET;
+    uint16_t itstatus = 0x0, itenable = 0x0;
+
+    itstatus = TIMx->INTFR & TIM_IT;
+
+    itenable = TIMx->DMAINTENR & TIM_IT;
+    if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      TIM_ClearITPendingBit
+ *
+ * @brief   Clears the TIMx's interrupt pending bits.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          TIM_IT - specifies the TIM interrupt source to check.
+ *            TIM_IT_Update - TIM update Interrupt source.
+ *            TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source.
+ *            TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source.
+ *            TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source.
+ *            TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source.
+ *            TIM_IT_COM - TIM Commutation Interrupt source.
+ *            TIM_IT_Trigger - TIM Trigger Interrupt source.
+ *            TIM_IT_Break - TIM Break Interrupt source.
+ *
+ * @return  none
+ */
+void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT)
+{
+    TIMx->INTFR = (uint16_t)~TIM_IT;
+}
+
+/*********************************************************************
+ * @fn      TI1_Config
+ *
+ * @brief   Configure the TI1 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 1 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 1 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E);
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F)));
+
+    TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection);
+    tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E);
+    }
+
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI2_Config
+ *
+ * @brief   Configure the TI2 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 2 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 2 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E);
+    tmpccmr1 = TIMx->CHCTLR1;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 4);
+    tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F)));
+
+    TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8);
+    tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E);
+    }
+
+    TIMx->CHCTLR1 = tmpccmr1;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI3_Config
+ *
+ * @brief   Configure the TI3 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 3 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 3 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E);
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 8);
+    tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F)));
+
+    TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection);
+    tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E);
+    }
+
+    TIMx->CHCTLR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}
+
+/*********************************************************************
+ * @fn      TI4_Config
+ *
+ * @brief   Configure the TI4 as Input.
+ *
+ * @param   TIMx - where x can be 1 to 4 select the TIM peripheral.
+ *          IM_ICPolarity - The Input Polarity.
+ *             TIM_ICPolarity_Rising.
+ *             TIM_ICPolarity_Falling.
+ *          TIM_ICSelection - specifies the input to be used.
+ *             TIM_ICSelection_DirectTI - TIM Input 4 is selected to be
+ *        connected to IC1.
+ *             TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be
+ *        connected to IC2.
+ *             TIM_ICSelection_TRC - TIM Input 4 is selected to be connected
+ *        to TRC.
+ *          TIM_ICFilter - Specifies the Input Capture Filter.
+ *            This parameter must be a value between 0x00 and 0x0F.
+ *
+ * @return  none
+ */
+static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+    uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+    TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E);
+    tmpccmr2 = TIMx->CHCTLR2;
+    tmpccer = TIMx->CCER;
+    tmp = (uint16_t)(TIM_ICPolarity << 12);
+    tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F)));
+
+    TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8);
+    tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+    if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4))
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P));
+        tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E);
+    }
+    else
+    {
+        tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC4NP));
+        tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E);
+    }
+
+    TIMx->CHCTLR2 = tmpccmr2;
+    TIMx->CCER = tmpccer;
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_usart.c

@@ -0,0 +1,815 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_usart.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the USART firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_usart.h"
+#include "ch32v10x_rcc.h"
+
+/* USART_Private_Defines */
+#define CTLR1_UE_Set              ((uint16_t)0x2000) /* USART Enable Mask */
+#define CTLR1_UE_Reset            ((uint16_t)0xDFFF) /* USART Disable Mask */
+
+#define CTLR1_WAKE_Mask           ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
+
+#define CTLR1_RWU_Set             ((uint16_t)0x0002) /* USART mute mode Enable Mask */
+#define CTLR1_RWU_Reset           ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
+#define CTLR1_SBK_Set             ((uint16_t)0x0001) /* USART Break Character send Mask */
+#define CTLR1_CLEAR_Mask          ((uint16_t)0xE9F3) /* USART CR1 Mask */
+#define CTLR2_Address_Mask        ((uint16_t)0xFFF0) /* USART address Mask */
+
+#define CTLR2_LINEN_Set           ((uint16_t)0x4000) /* USART LIN Enable Mask */
+#define CTLR2_LINEN_Reset         ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
+
+#define CTLR2_LBDL_Mask           ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
+#define CTLR2_STOP_CLEAR_Mask     ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
+#define CTLR2_CLOCK_CLEAR_Mask    ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
+
+#define CTLR3_SCEN_Set            ((uint16_t)0x0020) /* USART SC Enable Mask */
+#define CTLR3_SCEN_Reset          ((uint16_t)0xFFDF) /* USART SC Disable Mask */
+
+#define CTLR3_NACK_Set            ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
+#define CTLR3_NACK_Reset          ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
+
+#define CTLR3_HDSEL_Set           ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
+#define CTLR3_HDSEL_Reset         ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
+
+#define CTLR3_IRLP_Mask           ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
+#define CTLR3_CLEAR_Mask          ((uint16_t)0xFCFF) /* USART CR3 Mask */
+
+#define CTLR3_IREN_Set            ((uint16_t)0x0002) /* USART IrDA Enable Mask */
+#define CTLR3_IREN_Reset          ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
+#define GPR_LSB_Mask              ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
+#define GPR_MSB_Mask              ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
+#define IT_Mask                   ((uint16_t)0x001F) /* USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTLR1_OVER8_Set           ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
+#define CTLR1_OVER8_Reset         ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTLR3_ONEBITE_Set         ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
+#define CTLR3_ONEBITE_Reset       ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
+
+/*********************************************************************
+ * @fn      USART_DeInit
+ *
+ * @brief   Deinitializes the USARTx peripheral registers to their default
+ *        reset values.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *
+ * @return  none
+ */
+void USART_DeInit(USART_TypeDef *USARTx)
+{
+    if(USARTx == USART1)
+    {
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+        RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+    }
+    else if(USARTx == USART2)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+    }
+    else if(USARTx == USART3)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+    }
+    else if(USARTx == UART4)
+    {
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+        RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+    }
+    else
+    {
+        if(USARTx == UART5)
+        {
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+            RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+        }
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_Init
+ *
+ * @brief   Initializes the USARTx peripheral according to the specified
+ *        parameters in the USART_InitStruct.
+ *
+ * @param   USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
+ *          USART_InitStruct - pointer to a USART_InitTypeDef structure
+ *        that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
+{
+    uint32_t          tmpreg = 0x00, apbclock = 0x00;
+    uint32_t          integerdivider = 0x00;
+    uint32_t          fractionaldivider = 0x00;
+    uint32_t          usartxbase = 0;
+    RCC_ClocksTypeDef RCC_ClocksStatus;
+
+    if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+    {
+    }
+
+    usartxbase = (uint32_t)USARTx;
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_STOP_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+
+    USARTx->CTLR2 = (uint16_t)tmpreg;
+    tmpreg = USARTx->CTLR1;
+    tmpreg &= CTLR1_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+              USART_InitStruct->USART_Mode;
+    USARTx->CTLR1 = (uint16_t)tmpreg;
+
+    tmpreg = USARTx->CTLR3;
+    tmpreg &= CTLR3_CLEAR_Mask;
+    tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+    USARTx->CTLR3 = (uint16_t)tmpreg;
+
+    RCC_GetClocksFreq(&RCC_ClocksStatus);
+
+    if(usartxbase == USART1_BASE)
+    {
+        apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+    }
+    else
+    {
+        apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+    }
+
+    if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+    {
+        integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));
+    }
+    else
+    {
+        integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
+    }
+    tmpreg = (integerdivider / 100) << 4;
+
+    fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+    if((USARTx->CTLR1 & CTLR1_OVER8_Set) != 0)
+    {
+        tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+    }
+    else
+    {
+        tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+    }
+
+    USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_StructInit
+ *
+ * @brief   Fills each USART_InitStruct member with its default value.
+ *
+ * @param   USART_InitStruct: pointer to a USART_InitTypeDef structure
+ *       which will be initialized.
+ *
+ * @return  none
+ */
+void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
+{
+    USART_InitStruct->USART_BaudRate = 9600;
+    USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+    USART_InitStruct->USART_StopBits = USART_StopBits_1;
+    USART_InitStruct->USART_Parity = USART_Parity_No;
+    USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+    USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockInit
+ *
+ * @brief   Initializes the USARTx peripheral Clock according to the
+ *        specified parameters in the USART_ClockInitStruct .
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
+ *        structure that contains the configuration information for the specified
+ *        USART peripheral.
+ *
+ * @return  none
+ */
+void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+    uint32_t tmpreg = 0x00;
+
+    tmpreg = USARTx->CTLR2;
+    tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
+    tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
+              USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+    USARTx->CTLR2 = (uint16_t)tmpreg;
+}
+
+/*********************************************************************
+ * @fn      USART_ClockStructInit
+ *
+ * @brief   Fills each USART_ClockStructInit member with its default value.
+ *
+ * @param   USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
+ *        structure which will be initialized.
+ *
+ * @return  none
+ */
+void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
+{
+    USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+    USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+    USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+    USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/*********************************************************************
+ * @fn      USART_Cmd
+ *
+ * @brief   Enables or disables the specified USART peripheral.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState: ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_UE_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_UE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_ITConfig
+ *
+ * @brief   Enables or disables the specified USART interrupts.
+ *        reset values (Affects also the I2Ss).
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt sources to be enabled or disabled.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Transmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *            USART_IT_ERR - Error interrupt.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+    uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+    uint32_t usartxbase = 0x00;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    usartxbase = (uint32_t)USARTx;
+    usartreg = (((uint8_t)USART_IT) >> 0x05);
+    itpos = USART_IT & IT_Mask;
+    itmask = (((uint32_t)0x01) << itpos);
+
+    if(usartreg == 0x01)
+    {
+        usartxbase += 0x0C;
+    }
+    else if(usartreg == 0x02)
+    {
+        usartxbase += 0x10;
+    }
+    else
+    {
+        usartxbase += 0x14;
+    }
+
+    if(NewState != DISABLE)
+    {
+        *(__IO uint32_t *)usartxbase |= itmask;
+    }
+    else
+    {
+        *(__IO uint32_t *)usartxbase &= ~itmask;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_DMACmd
+ *
+ * @brief   Enables or disables the USART DMA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_DMAReq - specifies the DMA request.
+ *            USART_DMAReq_Tx - USART DMA transmit request.
+ *            USART_DMAReq_Rx - USART DMA receive request.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= USART_DMAReq;
+    }
+    else
+    {
+        USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SetAddress
+ *
+ * @brief   Sets the address of the USART node.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Address - Indicates the address of the USART node.
+ *
+ * @return  none
+ */
+void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
+{
+    USARTx->CTLR2 &= CTLR2_Address_Mask;
+    USARTx->CTLR2 |= USART_Address;
+}
+
+/*********************************************************************
+ * @fn      USART_WakeUpConfig
+ *
+ * @brief   Selects the USART WakeUp method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_WakeUp - specifies the USART wakeup method.
+ *            USART_WakeUp_IdleLine - WakeUp by an idle line detection.
+ *            USART_WakeUp_AddressMark - WakeUp by an address mark.
+ *
+ * @return  none
+ */
+void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
+{
+    USARTx->CTLR1 &= CTLR1_WAKE_Mask;
+    USARTx->CTLR1 |= USART_WakeUp;
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiverWakeUpCmd
+ *
+ * @brief   Determines if the USART is in mute mode or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_RWU_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_RWU_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_LINBreakDetectLengthConfig
+ *
+ * @brief   Sets the USART LIN Break detection length.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_LINBreakDetectLength - specifies the LIN break detection length.
+ *            USART_LINBreakDetectLength_10b - 10-bit break detection.
+ *            USART_LINBreakDetectLength_11b - 11-bit break detection.
+ *
+ * @return  none
+ */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
+{
+    USARTx->CTLR2 &= CTLR2_LBDL_Mask;
+    USARTx->CTLR2 |= USART_LINBreakDetectLength;
+}
+
+/*********************************************************************
+ * @fn      USART_LINCmd
+ *
+ * @brief   Enables or disables the USART LIN mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR2 |= CTLR2_LINEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR2 &= CTLR2_LINEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SendData
+ *
+ * @brief   Transmits single data through the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          Data - the data to transmit.
+ *
+ * @return  none
+ */
+void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
+{
+    USARTx->DATAR = (Data & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_ReceiveData
+ *
+ * @brief   Returns the most recent received data by the USARTx peripheral.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  The received data.
+ */
+uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
+{
+    return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
+}
+
+/*********************************************************************
+ * @fn      USART_SendBreak
+ *
+ * @brief   Transmits break characters.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *
+ * @return  none
+ */
+void USART_SendBreak(USART_TypeDef *USARTx)
+{
+    USARTx->CTLR1 |= CTLR1_SBK_Set;
+}
+
+/*********************************************************************
+ * @fn      USART_SetGuardTime
+ *
+ * @brief   Sets the specified USART guard time.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_GuardTime - specifies the guard time.
+ *
+ * @return  none
+ */
+void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
+{
+    USARTx->GPR &= GPR_LSB_Mask;
+    USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/*********************************************************************
+ * @fn      USART_SetPrescaler
+ *
+ * @brief   Sets the system clock prescaler.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_Prescaler - specifies the prescaler clock.
+ *
+ * @return  none
+ */
+void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
+{
+    USARTx->GPR &= GPR_MSB_Mask;
+    USARTx->GPR |= USART_Prescaler;
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardCmd
+ *
+ * @brief   Enables or disables the USART Smart Card mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_SCEN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_SCEN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_SmartCardNACKCmd
+ *
+ * @brief   Enables or disables NACK transmission.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_NACK_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_NACK_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_HalfDuplexCmd
+ *
+ * @brief   Enables or disables the USART Half Duplex communication.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *                  NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_HDSEL_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OverSampling8Cmd
+ *
+ * @brief   Enables or disables the USART's 8x oversampling mode.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OverSampling8Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR1 |= CTLR1_OVER8_Set;
+    }
+    else
+    {
+        USARTx->CTLR1 &= CTLR1_OVER8_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_OneBitMethodCmd
+ *
+ * @brief   Enables or disables the USART's one bit sampling method.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_OneBitMethodCmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_ONEBITE_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_ONEBITE_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_IrDAConfig
+ *
+ * @brief   Configures the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IrDAMode - specifies the IrDA mode.
+ *            USART_IrDAMode_LowPower.
+ *            USART_IrDAMode_Normal.
+ *
+ * @return  none
+ */
+void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
+{
+    USARTx->CTLR3 &= CTLR3_IRLP_Mask;
+    USARTx->CTLR3 |= USART_IrDAMode;
+}
+
+/*********************************************************************
+ * @fn      USART_IrDACmd
+ *
+ * @brief   Enables or disables the USART's IrDA interface.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          NewState - ENABLE or DISABLE.
+ *
+ * @return  none
+ */
+void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
+{
+    if(NewState != DISABLE)
+    {
+        USARTx->CTLR3 |= CTLR3_IREN_Set;
+    }
+    else
+    {
+        USARTx->CTLR3 &= CTLR3_IREN_Reset;
+    }
+}
+
+/*********************************************************************
+ * @fn      USART_GetFlagStatus
+ *
+ * @brief   Checks whether the specified USART flag is set or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to check.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TXE - Transmit data register empty flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *            USART_FLAG_IDLE - Idle Line detection flag.
+ *            USART_FLAG_ORE - OverRun Error flag.
+ *            USART_FLAG_NE - Noise Error flag.
+ *            USART_FLAG_FE - Framing Error flag.
+ *            USART_FLAG_PE - Parity Error flag.
+ *
+ * @return  bitstatus: SET or RESET
+ */
+FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
+{
+    FlagStatus bitstatus = RESET;
+
+    if(USART_FLAG == USART_FLAG_CTS)
+    {
+    }
+
+    if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearFlag
+ *
+ * @brief   Clears the USARTx's pending flags.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_FLAG - specifies the flag to clear.
+ *            USART_FLAG_CTS - CTS Change flag.
+ *            USART_FLAG_LBD - LIN Break detection flag.
+ *            USART_FLAG_TC - Transmission Complete flag.
+ *            USART_FLAG_RXNE - Receive data register not empty flag.
+ *
+ * @return  none
+ */
+void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
+{
+    if((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+    {
+    }
+
+    USARTx->STATR = (uint16_t)~USART_FLAG;
+}
+
+/*********************************************************************
+ * @fn      USART_GetITStatus
+ *
+ * @brief   Checks whether the specified USART interrupt has occurred or not.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the USART interrupt source to check.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TXE - Tansmit Data Register empty interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *            USART_IT_IDLE - Idle line detection interrupt.
+ *            USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
+ *            USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
+ *            USART_IT_NE - Noise Error interrupt.
+ *            USART_IT_FE - Framing Error interrupt.
+ *            USART_IT_PE - Parity Error interrupt.
+ *
+ * @return  bitstatus: SET or RESET.
+ */
+ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
+{
+    uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+    ITStatus bitstatus = RESET;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    usartreg = (((uint8_t)USART_IT) >> 0x05);
+    itmask = USART_IT & IT_Mask;
+    itmask = (uint32_t)0x01 << itmask;
+
+    if(usartreg == 0x01)
+    {
+        itmask &= USARTx->CTLR1;
+    }
+    else if(usartreg == 0x02)
+    {
+        itmask &= USARTx->CTLR2;
+    }
+    else
+    {
+        itmask &= USARTx->CTLR3;
+    }
+
+    bitpos = USART_IT >> 0x08;
+    bitpos = (uint32_t)0x01 << bitpos;
+    bitpos &= USARTx->STATR;
+
+    if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
+    {
+        bitstatus = SET;
+    }
+    else
+    {
+        bitstatus = RESET;
+    }
+
+    return bitstatus;
+}
+
+/*********************************************************************
+ * @fn      USART_ClearITPendingBit
+ *
+ * @brief   Clears the USARTx's interrupt pending bits.
+ *
+ * @param   USARTx - where x can be 1, 2, 3 to select the USART peripheral.
+ *          USART_IT - specifies the interrupt pending bit to clear.
+ *            USART_IT_CTS - CTS change interrupt.
+ *            USART_IT_LBD - LIN Break detection interrupt.
+ *            USART_IT_TC - Transmission complete interrupt.
+ *            USART_IT_RXNE - Receive Data register not empty interrupt.
+ *
+ * @return  none
+ */
+void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
+{
+    uint16_t bitpos = 0x00, itmask = 0x00;
+
+    if(USART_IT == USART_IT_CTS)
+    {
+    }
+
+    bitpos = USART_IT >> 0x08;
+    itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+    USARTx->STATR = (uint16_t)~itmask;
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_usb.c

@@ -0,0 +1,170 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_usb.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the USB firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_usb.h"
+#include "ch32v10x_rcc.h"
+#include "debug.h"
+/******************************** USB DEVICE **********************************/
+
+/* Endpoint address */
+PUINT8 pEP0_RAM_Addr;
+PUINT8 pEP1_RAM_Addr;
+PUINT8 pEP2_RAM_Addr;
+PUINT8 pEP3_RAM_Addr;
+PUINT8 pEP4_RAM_Addr;
+PUINT8 pEP5_RAM_Addr;
+PUINT8 pEP6_RAM_Addr;
+PUINT8 pEP7_RAM_Addr;
+
+/*********************************************************************
+ * @fn      USB_DeviceInit
+ *
+ * @brief   Initializes USB device.
+ *
+ * @return  none
+ */
+void USB_DeviceInit(void)
+{
+    R8_USB_CTRL = 0x00;
+
+    R8_UEP4_1_MOD = RB_UEP4_RX_EN | RB_UEP4_TX_EN | RB_UEP1_RX_EN | RB_UEP1_TX_EN;
+    R8_UEP2_3_MOD = RB_UEP2_RX_EN | RB_UEP2_TX_EN | RB_UEP3_RX_EN | RB_UEP3_TX_EN;
+    R8_UEP5_6_MOD = RB_UEP5_RX_EN | RB_UEP5_TX_EN | RB_UEP6_RX_EN | RB_UEP6_TX_EN;
+    R8_UEP7_MOD = RB_UEP7_RX_EN | RB_UEP7_TX_EN;
+
+    R16_UEP0_DMA = (UINT16)(UINT32)pEP0_RAM_Addr;
+    R16_UEP1_DMA = (UINT16)(UINT32)pEP1_RAM_Addr;
+    R16_UEP2_DMA = (UINT16)(UINT32)pEP2_RAM_Addr;
+    R16_UEP3_DMA = (UINT16)(UINT32)pEP3_RAM_Addr;
+    R16_UEP4_DMA = (UINT16)(UINT32)pEP4_RAM_Addr;
+    R16_UEP5_DMA = (UINT16)(UINT32)pEP5_RAM_Addr;
+    R16_UEP6_DMA = (UINT16)(UINT32)pEP6_RAM_Addr;
+    R16_UEP7_DMA = (UINT16)(UINT32)pEP7_RAM_Addr;
+
+    R8_UEP0_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP1_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP2_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP3_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP4_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP5_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP6_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+    R8_UEP7_CTRL = UEP_R_RES_ACK | UEP_T_RES_NAK;
+
+    R8_USB_INT_FG = 0xFF;
+    R8_USB_INT_EN = RB_UIE_SUSPEND | RB_UIE_BUS_RST | RB_UIE_TRANSFER;
+
+    R8_USB_DEV_AD = 0x00;
+    R8_USB_CTRL = RB_UC_DEV_PU_EN | RB_UC_INT_BUSY | RB_UC_DMA_EN;
+    R8_UDEV_CTRL = RB_UD_PD_DIS | RB_UD_PORT_EN;
+}
+
+/*********************************************************************
+ * @fn      DevEP1_IN_Deal
+ *
+ * @brief   Device endpoint1 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP1_IN_Deal(UINT8 l)
+{
+    R8_UEP1_T_LEN = l;
+    R8_UEP1_CTRL = (R8_UEP1_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP2_IN_Deal
+ *
+ * @brief   Device endpoint2 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP2_IN_Deal(UINT8 l)
+{
+    R8_UEP2_T_LEN = l;
+    R8_UEP2_CTRL = (R8_UEP2_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP3_IN_Deal
+ *
+ * @brief   Device endpoint3 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP3_IN_Deal(UINT8 l)
+{
+    R8_UEP3_T_LEN = l;
+    R8_UEP3_CTRL = (R8_UEP3_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP4_IN_Deal
+ *
+ * @brief   Device endpoint4 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP4_IN_Deal(UINT8 l)
+{
+    R8_UEP4_T_LEN = l;
+    R8_UEP4_CTRL = (R8_UEP4_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP5_IN_Deal
+ *
+ * @brief   Device endpoint5 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP5_IN_Deal(UINT8 l)
+{
+    R8_UEP5_T_LEN = l;
+    R8_UEP5_CTRL = (R8_UEP5_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP6_IN_Deal
+ *
+ * @brief   Device endpoint6 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP6_IN_Deal(UINT8 l)
+{
+    R8_UEP6_T_LEN = l;
+    R8_UEP6_CTRL = (R8_UEP6_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}
+
+/*********************************************************************
+ * @fn      DevEP7_IN_Deal
+ *
+ * @brief   Device endpoint7 IN
+ *
+ * @param   l: IN length(<64B)
+ *
+ * @return  none
+ */
+void DevEP7_IN_Deal(UINT8 l)
+{
+    R8_UEP7_T_LEN = l;
+    R8_UEP7_CTRL = (R8_UEP7_CTRL & ~MASK_UEP_T_RES) | UEP_T_RES_ACK;
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_usb_host.c

@@ -0,0 +1,809 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_usb_host.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the USB firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_usb_host.h"
+#include "debug.h"
+
+/******************************** HOST DEVICE **********************************/
+UINT8       UsbDevEndp0Size;
+UINT8       FoundNewDev;
+_RootHubDev ThisUsbDev;
+
+PUINT8       pHOST_RX_RAM_Addr;
+PUINT8       pHOST_TX_RAM_Addr;
+extern UINT8 Com_Buffer[128];
+
+__attribute__((aligned(4))) const UINT8 SetupGetDevDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_DEVICE, 0x00, 0x00, sizeof(USB_DEV_DESCR), 0x00};
+
+__attribute__((aligned(4))) const UINT8 SetupGetCfgDescr[] = {USB_REQ_TYP_IN, USB_GET_DESCRIPTOR, 0x00, USB_DESCR_TYP_CONFIG, 0x00, 0x00, 0x04, 0x00};
+
+__attribute__((aligned(4))) const UINT8 SetupSetUsbAddr[] = {USB_REQ_TYP_OUT, USB_SET_ADDRESS, USB_DEVICE_ADDR, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+__attribute__((aligned(4))) const UINT8 SetupSetUsbConfig[] = {USB_REQ_TYP_OUT, USB_SET_CONFIGURATION, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+__attribute__((aligned(4))) const UINT8 SetupSetUsbInterface[] = {USB_REQ_RECIP_INTERF, USB_SET_INTERFACE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+__attribute__((aligned(4))) const UINT8 SetupClrEndpStall[] = {USB_REQ_TYP_OUT | USB_REQ_RECIP_ENDP, USB_CLEAR_FEATURE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
+
+/*********************************************************************
+ * @fn      DisableRootHubPort( )
+ *
+ * @brief  Disable root hub
+ *
+ * @return  none
+ */
+void DisableRootHubPort(void)
+{
+#ifdef FOR_ROOT_UDISK_ONLY
+    CH103DiskStatus = DISK_DISCONNECT;
+
+#endif
+
+#ifndef DISK_BASE_BUF_LEN
+    ThisUsbDev.DeviceStatus = ROOT_DEV_DISCONNECT;
+    ThisUsbDev.DeviceAddress = 0x00;
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      AnalyzeRootHub
+ *
+ * @brief  Analyze root hub state.
+ *
+ * @return  Error
+ */
+UINT8 AnalyzeRootHub(void)
+{
+    UINT8 s;
+
+    s = ERR_SUCCESS;
+
+    if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH)
+    {
+#ifdef DISK_BASE_BUF_LEN
+        if(CH103DiskStatus == DISK_DISCONNECT
+
+#else
+        if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT
+
+#endif
+           || (R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00)
+        {
+            DisableRootHubPort();
+
+#ifdef DISK_BASE_BUF_LEN
+            CH103DiskStatus = DISK_CONNECT;
+
+#else
+            ThisUsbDev.DeviceSpeed = R8_USB_MIS_ST & RB_UMS_DM_LEVEL ? 0 : 1;
+            ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED;
+
+#endif
+            s = ERR_USB_CONNECT;
+        }
+    }
+
+#ifdef DISK_BASE_BUF_LEN
+    else if(CH103DiskStatus >= DISK_CONNECT)
+    {
+#else
+    else if(ThisUsbDev.DeviceStatus >= ROOT_DEV_CONNECTED)
+    {
+
+#endif
+        DisableRootHubPort();
+        if(s == ERR_SUCCESS)
+            s = ERR_USB_DISCON;
+    }
+
+    return (s);
+}
+
+/*********************************************************************
+ * @fn      SetHostUsbAddr
+ *
+ * @brief  Set USB host address
+ *
+ * @param   addr -  host address
+ *
+ * @return  none
+ */
+void SetHostUsbAddr(UINT8 addr)
+{
+    R8_USB_DEV_AD = (R8_USB_DEV_AD & RB_UDA_GP_BIT) | (addr & MASK_USB_ADDR);
+}
+
+#ifndef FOR_ROOT_UDISK_ONLY
+/*********************************************************************
+ * @fn      SetUsbSpeed
+ *
+ * @brief  Set USB speed.
+ *
+ * @param   FullSpeed - USB speed.
+ *
+ * @return  none
+ */
+void SetUsbSpeed(UINT8 FullSpeed)
+{
+    if(FullSpeed)
+    {
+        R8_USB_CTRL &= ~RB_UC_LOW_SPEED;
+        R8_UH_SETUP &= ~RB_UH_PRE_PID_EN;
+    }
+    else
+    {
+        R8_USB_CTRL |= RB_UC_LOW_SPEED;
+    }
+}
+#endif
+
+/*********************************************************************
+ * @fn      ResetRootHubPort( )
+ *
+ * @brief   Reset root hub
+ *
+ * @return  none
+ */
+void ResetRootHubPort(void)
+{
+    UsbDevEndp0Size = DEFAULT_ENDP0_SIZE;
+    SetHostUsbAddr(0x00);
+    R8_UHOST_CTRL &= ~RB_UH_PORT_EN;
+    SetUsbSpeed(1);
+    R8_UHOST_CTRL = (R8_UHOST_CTRL & ~RB_UH_LOW_SPEED) | RB_UH_BUS_RESET;
+    Delay_Ms(15);
+    R8_UHOST_CTRL = R8_UHOST_CTRL & ~RB_UH_BUS_RESET;
+    Delay_Us(250);
+    R8_USB_INT_FG = RB_UIF_DETECT;
+}
+
+/*********************************************************************
+ * @fn      EnableRootHubPort( )
+ *
+ * @brief   Enable root hub.
+ *
+ * @return  ERROR
+ */
+UINT8 EnableRootHubPort(void)
+{
+#ifdef DISK_BASE_BUF_LEN
+    if(CH103DiskStatus < DISK_CONNECT)
+        CH103DiskStatus = DISK_CONNECT;
+
+#else
+    if(ThisUsbDev.DeviceStatus < ROOT_DEV_CONNECTED)
+        ThisUsbDev.DeviceStatus = ROOT_DEV_CONNECTED;
+
+#endif
+    if(R8_USB_MIS_ST & RB_UMS_DEV_ATTACH)
+    {
+#ifndef DISK_BASE_BUF_LEN
+        if((R8_UHOST_CTRL & RB_UH_PORT_EN) == 0x00)
+        {
+            ThisUsbDev.DeviceSpeed = (R8_USB_MIS_ST & RB_UMS_DM_LEVEL) ? 0 : 1;
+            if(ThisUsbDev.DeviceSpeed == 0)
+                R8_UHOST_CTRL |= RB_UH_LOW_SPEED;
+        }
+
+#endif
+        R8_UHOST_CTRL |= RB_UH_PORT_EN;
+        return (ERR_SUCCESS);
+    }
+
+    return (ERR_USB_DISCON);
+}
+
+/*********************************************************************
+ * @fn      WaitUSB_Interrupt
+ *
+ * @brief   Wait USB Interrput.
+ *
+ * @return  ERROR
+ */
+UINT8 WaitUSB_Interrupt(void)
+{
+    UINT16 i;
+
+    for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--)
+    {
+        ;
+    }
+    return ((R8_USB_INT_FG & RB_UIF_TRANSFER) ? ERR_SUCCESS : ERR_USB_UNKNOWN);
+}
+
+/*********************************************************************
+ * @fn      USBHostTransact
+ *
+ * @brief   USB host transport transaction
+ * @param   endp_pid: endpoint and PID
+ *          tog: Synchronization flag
+ *          timeout: timeout times
+ *
+ * @return  EEROR:
+ *                         ERR_USB_UNKNOWN
+ *          ERR_USB_DISCON
+ *          ERR_USB_CONNECT
+ *          ERR_SUCCESS
+ */
+UINT8 USBHostTransact(UINT8 endp_pid, UINT8 tog, UINT32 timeout)
+{
+    UINT8  TransRetry;
+    UINT8  s, r;
+    UINT16 i;
+
+    R8_UH_RX_CTRL = R8_UH_TX_CTRL = tog;
+    TransRetry = 0;
+
+    do
+    {
+        R8_UH_EP_PID = endp_pid;
+        R8_USB_INT_FG = RB_UIF_TRANSFER;
+        for(i = WAIT_USB_TOUT_200US; i != 0 && (R8_USB_INT_FG & RB_UIF_TRANSFER) == 0; i--)
+            ;
+        R8_UH_EP_PID = 0x00;
+        if((R8_USB_INT_FG & RB_UIF_TRANSFER) == 0)
+        {
+            return (ERR_USB_UNKNOWN);
+        }
+
+        if(R8_USB_INT_FG & RB_UIF_DETECT)
+        {
+            R8_USB_INT_FG = RB_UIF_DETECT;
+            s = AnalyzeRootHub();
+
+            if(s == ERR_USB_CONNECT)
+                FoundNewDev = 1;
+
+#ifdef DISK_BASE_BUF_LEN
+
+            if(CH103DiskStatus == DISK_DISCONNECT)
+                return (ERR_USB_DISCON);
+            if(CH103DiskStatus == DISK_CONNECT)
+                return (ERR_USB_CONNECT);
+
+#else
+            if(ThisUsbDev.DeviceStatus == ROOT_DEV_DISCONNECT)
+                return (ERR_USB_DISCON);
+            if(ThisUsbDev.DeviceStatus == ROOT_DEV_CONNECTED)
+                return (ERR_USB_CONNECT);
+
+#endif
+            Delay_Us(200);
+        }
+
+        if(R8_USB_INT_FG & RB_UIF_TRANSFER)
+        {
+            if(R8_USB_INT_ST & RB_UIS_TOG_OK)
+                return (ERR_SUCCESS);
+            r = R8_USB_INT_ST & MASK_UIS_H_RES;
+            if(r == USB_PID_STALL)
+                return (r | ERR_USB_TRANSFER);
+
+            if(r == USB_PID_NAK)
+            {
+                if(timeout == 0)
+                    return (r | ERR_USB_TRANSFER);
+                if(timeout < 0xFFFF)
+                    timeout--;
+                --TransRetry;
+            }
+            else
+                switch(endp_pid >> 4)
+                {
+                    case USB_PID_SETUP:
+
+                    case USB_PID_OUT:
+                        if(r)
+                            return (r | ERR_USB_TRANSFER);
+                        break;
+
+                    case USB_PID_IN:
+                        if(r == USB_PID_DATA0 && r == USB_PID_DATA1)
+                        {
+                        }
+                        else if(r)
+                            return (r | ERR_USB_TRANSFER);
+                        break;
+
+                    default:
+                        return (ERR_USB_UNKNOWN);
+                }
+        }
+        else
+        {
+            R8_USB_INT_FG = 0xFF;
+        }
+        Delay_Us(15);
+    } while(++TransRetry < 3);
+
+    return (ERR_USB_TRANSFER);
+}
+
+/*********************************************************************
+ * @fn      HostCtrlTransfer
+ *
+ * @brief  Host control transport.
+ *
+ * @param   DataBuf : Receive or send data buffer.
+ *          RetLen  : Data length.
+ *
+ * @return  ERR_USB_BUF_OVER IN
+ *          ERR_SUCCESS
+ */
+UINT8 HostCtrlTransfer(PUINT8 DataBuf, PUINT8 RetLen)
+{
+    UINT16 RemLen = 0;
+    UINT8  s, RxLen, RxCnt, TxCnt;
+    PUINT8 pBuf;
+    PUINT8 pLen;
+
+    pBuf = DataBuf;
+    pLen = RetLen;
+    Delay_Us(200);
+    if(pLen)
+        *pLen = 0;
+
+    R8_UH_TX_LEN = sizeof(USB_SETUP_REQ);
+    s = USBHostTransact(USB_PID_SETUP << 4 | 0x00, 0x00, 200000 / 20);
+    if(s != ERR_SUCCESS)
+        return (s);
+    R8_UH_RX_CTRL = R8_UH_TX_CTRL = RB_UH_R_TOG | RB_UH_R_AUTO_TOG | RB_UH_T_TOG | RB_UH_T_AUTO_TOG;
+    R8_UH_TX_LEN = 0x01;
+    RemLen = pSetupReq->wLength;
+
+    if(RemLen && pBuf)
+    {
+        if(pSetupReq->bRequestType & USB_REQ_TYP_IN)
+        {
+            while(RemLen)
+            {
+                Delay_Us(200);
+                s = USBHostTransact(USB_PID_IN << 4 | 0x00, R8_UH_RX_CTRL, 200000 / 20);
+                if(s != ERR_SUCCESS)
+                    return (s);
+                RxLen = R8_USB_RX_LEN < RemLen ? R8_USB_RX_LEN : RemLen;
+                RemLen -= RxLen;
+                if(pLen)
+                    *pLen += RxLen;
+
+                for(RxCnt = 0; RxCnt != RxLen; RxCnt++) {
+                    *pBuf = pHOST_RX_RAM_Addr[RxCnt];
+                    pBuf++;
+                }
+
+                if(R8_USB_RX_LEN == 0 || (R8_USB_RX_LEN & (UsbDevEndp0Size - 1)))
+                    break;
+            }
+            R8_UH_TX_LEN = 0x00;
+        }
+        else
+        {
+            while(RemLen)
+            {
+                Delay_Us(200);
+                R8_UH_TX_LEN = RemLen >= UsbDevEndp0Size ? UsbDevEndp0Size : RemLen;
+
+                for(TxCnt = 0; TxCnt != R8_UH_TX_LEN; TxCnt++){
+                    pHOST_TX_RAM_Addr[TxCnt] = *pBuf;
+                    pBuf++;
+                }
+
+                s = USBHostTransact(USB_PID_OUT << 4 | 0x00, R8_UH_TX_CTRL, 200000 / 20);
+                if(s != ERR_SUCCESS)
+                    return (s);
+                RemLen -= R8_UH_TX_LEN;
+                if(pLen)
+                    *pLen += R8_UH_TX_LEN;
+            }
+        }
+    }
+
+    Delay_Us(200);
+    s = USBHostTransact((R8_UH_TX_LEN ? USB_PID_IN << 4 | 0x00 : USB_PID_OUT << 4 | 0x00), RB_UH_R_TOG | RB_UH_T_TOG, 200000 / 20);
+    if(s != ERR_SUCCESS)
+        return (s);
+    if(R8_UH_TX_LEN == 0)
+        return (ERR_SUCCESS);
+    if(R8_USB_RX_LEN == 0)
+        return (ERR_SUCCESS);
+
+    return (ERR_USB_BUF_OVER);
+}
+
+/*********************************************************************
+ * @fn      CopySetupReqPkg
+ *
+ * @brief  Copy setup request package.
+ *
+ * @param   pReqPkt: setup request package address.
+ *
+ * @return  none
+ */
+void CopySetupReqPkg(const UINT8 *pReqPkt)
+{
+    UINT8 i;
+
+    for(i = 0; i != sizeof(USB_SETUP_REQ); i++) {
+        ((PUINT8)pSetupReq)[i] = *pReqPkt;
+        pReqPkt++;
+    }
+}
+
+/*********************************************************************
+ * @fn      CtrlGetDeviceDescr
+ *
+ * @brief  Get device descrptor.
+ *
+ * @param   DataBuf: Data buffer.
+ *
+ * @return  ERR_USB_BUF_OVER
+ *          ERR_SUCCESS
+ */
+UINT8 CtrlGetDeviceDescr(PUINT8 DataBuf)
+{
+    UINT8 s;
+    UINT8 len;
+
+    UsbDevEndp0Size = DEFAULT_ENDP0_SIZE;
+    CopySetupReqPkg(SetupGetDevDescr);
+    s = HostCtrlTransfer(DataBuf, &len);
+
+    if(s != ERR_SUCCESS)
+        return (s);
+    UsbDevEndp0Size = ((PUSB_DEV_DESCR)DataBuf)->bMaxPacketSize0;
+    if(len < ((PUSB_SETUP_REQ)SetupGetDevDescr)->wLength)
+        return (ERR_USB_BUF_OVER);
+
+    return (ERR_SUCCESS);
+}
+
+/*********************************************************************
+ * @fn      CtrlGetConfigDescr
+ *
+ * @brief  Get configration descrptor.
+ *
+ * @param   DataBuf: Data buffer.
+ *
+ * @return  ERR_USB_BUF_OVER
+ *          ERR_SUCCESS
+ */
+UINT8 CtrlGetConfigDescr(PUINT8 DataBuf)
+{
+    UINT8 s;
+    UINT8 len;
+
+    CopySetupReqPkg(SetupGetCfgDescr);
+    s = HostCtrlTransfer(DataBuf, &len);
+    if(s != ERR_SUCCESS)
+        return (s);
+    if(len < ((PUSB_SETUP_REQ)SetupGetCfgDescr)->wLength)
+        return (ERR_USB_BUF_OVER);
+
+    len = ((PUSB_CFG_DESCR)DataBuf)->wTotalLength;
+    CopySetupReqPkg(SetupGetCfgDescr);
+    pSetupReq->wLength = len;
+    s = HostCtrlTransfer(DataBuf, &len);
+    if(s != ERR_SUCCESS)
+        return (s);
+
+    return (ERR_SUCCESS);
+}
+
+/*********************************************************************
+ * @fn      CtrlSetUsbAddress
+ *
+ * @brief   Set USB device address.
+ *
+ * @param   addr: Device address.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlSetUsbAddress(UINT8 addr)
+{
+    UINT8 s;
+
+    CopySetupReqPkg(SetupSetUsbAddr);
+    pSetupReq->wValue = addr;
+    s = HostCtrlTransfer(NULL, NULL);
+    if(s != ERR_SUCCESS)
+        return (s);
+    SetHostUsbAddr(addr);
+    Delay_Ms(10);
+
+    return (ERR_SUCCESS);
+}
+
+/*********************************************************************
+ * @fn      CtrlSetUsbConfig
+ *
+ * @brief   Set usb configration.
+ *
+ * @param   cfg: Configration Value.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlSetUsbConfig(UINT8 cfg)
+{
+    CopySetupReqPkg(SetupSetUsbConfig);
+    pSetupReq->wValue = cfg;
+    return (HostCtrlTransfer(NULL, NULL));
+}
+
+/*********************************************************************
+ * @fn      CtrlClearEndpStall
+ *
+ * @brief   Clear endpoint STALL.
+ *
+ * @param   endp: Endpoint address.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlClearEndpStall(UINT8 endp)
+{
+    CopySetupReqPkg(SetupClrEndpStall);
+    pSetupReq->wIndex = endp;
+    return (HostCtrlTransfer(NULL, NULL));
+}
+
+/*********************************************************************
+ * @fn      CtrlSetUsbIntercace
+ *
+ * @brief   Set USB Interface configration.
+ *
+ * @param   cfg: Configration value.
+ *
+ * @return  ERR_SUCCESS
+ */
+UINT8 CtrlSetUsbIntercace(UINT8 cfg)
+{
+    CopySetupReqPkg(SetupSetUsbInterface);
+    pSetupReq->wValue = cfg;
+    return (HostCtrlTransfer(NULL, NULL));
+}
+
+/*********************************************************************
+ * @fn      USB_HostInit
+ *
+ * @brief   Initializes USB host mode.
+ *
+ * @return  ERR_SUCCESS
+ */
+void USB_HostInit(void)
+{
+    R8_USB_CTRL = RB_UC_HOST_MODE;
+    R8_UHOST_CTRL = 0;
+    R8_USB_DEV_AD = 0x00;
+    R8_UH_EP_MOD = RB_UH_EP_TX_EN | RB_UH_EP_RX_EN;
+    R16_UH_RX_DMA = (UINT16)(UINT32)pHOST_RX_RAM_Addr;
+    R16_UH_TX_DMA = (UINT16)(UINT32)pHOST_TX_RAM_Addr;
+
+    R8_UH_RX_CTRL = 0x00;
+    R8_UH_TX_CTRL = 0x00;
+    R8_USB_CTRL = RB_UC_HOST_MODE | RB_UC_INT_BUSY | RB_UC_DMA_EN;
+    R8_UH_SETUP = RB_UH_SOF_EN;
+    R8_USB_INT_FG = 0xFF;
+    DisableRootHubPort();
+    R8_USB_INT_EN = RB_UIE_TRANSFER | RB_UIE_DETECT;
+
+    FoundNewDev = 0;
+}
+
+/*********************************************************************
+ * @fn      InitRootDevice
+ *
+ * @brief   Initializes USB root hub.
+ *
+ * @param   DataBuf: Data buffer.
+ *
+ * @return  ERROR
+ */
+UINT8 InitRootDevice(PUINT8 DataBuf)
+{
+    UINT8 i, s;
+    UINT8 cfg, dv_cls, if_cls;
+
+    ResetRootHubPort();
+
+    for(i = 0, s = 0; i < 100; i++)
+    {
+        Delay_Ms(1);
+        if(EnableRootHubPort() == ERR_SUCCESS)
+        {
+            i = 0;
+            s++;
+            if(s > 100)
+                break;
+        }
+    }
+
+    if(i)
+    {
+        DisableRootHubPort();
+        return (ERR_USB_DISCON);
+    }
+
+    SetUsbSpeed(ThisUsbDev.DeviceSpeed);
+
+    s = CtrlGetDeviceDescr(DataBuf);
+
+    if(s == ERR_SUCCESS)
+    {
+        ThisUsbDev.DeviceVID = ((PUSB_DEV_DESCR)DataBuf)->idVendor;
+        ThisUsbDev.DevicePID = ((PUSB_DEV_DESCR)DataBuf)->idProduct;
+        dv_cls = ((PUSB_DEV_DESCR)DataBuf)->bDeviceClass;
+
+        s = CtrlSetUsbAddress(((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue);
+
+        if(s == ERR_SUCCESS)
+        {
+            ThisUsbDev.DeviceAddress = ((PUSB_SETUP_REQ)SetupSetUsbAddr)->wValue;
+
+            s = CtrlGetConfigDescr(DataBuf);
+
+            if(s == ERR_SUCCESS)
+            {
+                cfg = ((PUSB_CFG_DESCR)DataBuf)->bConfigurationValue;
+                if_cls = ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceClass;
+
+                if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_STORAGE))
+                {
+#ifdef FOR_ROOT_UDISK_ONLY
+                    CH103DiskStatus = DISK_USB_ADDR;
+                    return (ERR_SUCCESS);
+                }
+                else
+                    return (ERR_USB_UNSUPPORT);
+
+#else
+                    s = CtrlSetUsbConfig(cfg);
+
+                    if(s == ERR_SUCCESS)
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        ThisUsbDev.DeviceType = USB_DEV_CLASS_STORAGE;
+                        SetUsbSpeed(1);
+                        return (ERR_SUCCESS);
+                    }
+                }
+                else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_PRINTER) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass == 0x01)
+                {
+                    s = CtrlSetUsbConfig(cfg);
+                    if(s == ERR_SUCCESS)
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        ThisUsbDev.DeviceType = USB_DEV_CLASS_PRINTER;
+                        SetUsbSpeed(1);
+                        return (ERR_SUCCESS);
+                    }
+                }
+                else if((dv_cls == 0x00) && (if_cls == USB_DEV_CLASS_HID) && ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceSubClass <= 0x01)
+                {
+                    if_cls = ((PUSB_CFG_DESCR_LONG)DataBuf)->itf_descr.bInterfaceProtocol;
+                    s = CtrlSetUsbConfig(cfg);
+                    if(s == ERR_SUCCESS)
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        if(if_cls == 1)
+                        {
+                            ThisUsbDev.DeviceType = DEV_TYPE_KEYBOARD;
+                            SetUsbSpeed(1);
+                            return (ERR_SUCCESS);
+                        }
+                        else if(if_cls == 2)
+                        {
+                            ThisUsbDev.DeviceType = DEV_TYPE_MOUSE;
+                            SetUsbSpeed(1);
+                            return (ERR_SUCCESS);
+                        }
+                        s = ERR_USB_UNSUPPORT;
+                    }
+                }
+                else
+                {
+                    s = CtrlSetUsbConfig(cfg);
+                    if(s == ERR_SUCCESS)
+                    {
+                        ThisUsbDev.DeviceStatus = ROOT_DEV_SUCCESS;
+                        ThisUsbDev.DeviceType = DEV_TYPE_UNKNOW;
+                        SetUsbSpeed(1);
+                        return (ERR_SUCCESS);
+                    }
+                }
+
+#endif
+            }
+        }
+    }
+
+#ifdef FOR_ROOT_UDISK_ONLY
+    CH103DiskStatus = DISK_CONNECT;
+
+#else
+    ThisUsbDev.DeviceStatus = ROOT_DEV_FAILED;
+
+#endif
+
+    SetUsbSpeed(1);
+
+    return (s);
+}
+
+/*********************************************************************
+ * @fn      HubGetPortStatus
+ *
+ * @brief   查询HUB端口状态,返回在Com_Buffer中
+ *
+ * @param   UINT8 HubPortIndex
+ *
+ * @return  ERR_SUCCESS 成功
+ *          ERR_USB_BUF_OVER 长度错误
+ */
+UINT8 HubGetPortStatus(UINT8 HubPortIndex)
+{
+    UINT8 s;
+    UINT8 len;
+
+    pSetupReq->bRequestType = HUB_GET_PORT_STATUS;
+    pSetupReq->bRequest = HUB_GET_STATUS;
+    pSetupReq->wValue = 0x0000;
+    pSetupReq->wIndex = 0x0000 | HubPortIndex;
+    pSetupReq->wLength = 0x0004;
+    s = HostCtrlTransfer(Com_Buffer, &len); // 执行控制传输
+    if(s != ERR_SUCCESS)
+    {
+        return (s);
+    }
+    if(len < 4)
+    {
+        return (ERR_USB_BUF_OVER); // 描述符长度错误
+    }
+
+    return (ERR_SUCCESS);
+}
+
+/*********************************************************************
+ * @fn      HubSetPortFeature
+ *
+ * @brief   设置HUB端口特性
+ *
+ * @param   UINT8 HubPortIndex
+ *          UINT8 FeatureSelt
+ *
+ * @return  ERR_SUCCESS 成功
+ */
+UINT8 HubSetPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt)
+{
+    pSetupReq->bRequestType = HUB_SET_PORT_FEATURE;
+    pSetupReq->bRequest = HUB_SET_FEATURE;
+    pSetupReq->wValue = 0x0000 | FeatureSelt;
+    pSetupReq->wIndex = 0x0000 | HubPortIndex;
+    pSetupReq->wLength = 0x0000;
+    return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输
+}
+
+/*********************************************************************
+ * @fn      HubClearPortFeature
+ *
+ * @brief   清除HUB端口特性
+ *
+ * @param   UINT8 HubPortIndex
+ *          UINT8 FeatureSelt
+ *
+ * @return  ERR_SUCCESS 成功
+ */
+UINT8 HubClearPortFeature(UINT8 HubPortIndex, UINT8 FeatureSelt)
+{
+    pSetupReq->bRequestType = HUB_CLEAR_PORT_FEATURE;
+    pSetupReq->bRequest = HUB_CLEAR_FEATURE;
+    pSetupReq->wValue = 0x0000 | FeatureSelt;
+    pSetupReq->wIndex = 0x0000 | HubPortIndex;
+    pSetupReq->wLength = 0x0000;
+    return (HostCtrlTransfer(NULL, NULL)); // 执行控制传输
+}

bsp/wch/risc-v/Libraries/CH32V10x_StdPeriph_Driver/StdPeriph_Driver/src/ch32v10x_wwdg.c

@@ -0,0 +1,139 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_wwdg.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file provides all the WWDG firmware functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ **********************************************************************************/
+#include "ch32v10x_wwdg.h"
+#include "ch32v10x_rcc.h"
+
+/* CTLR register bit mask */
+#define CTLR_WDGA_Set      ((uint32_t)0x00000080)
+
+/* CFGR register bit mask */
+#define CFGR_WDGTB_Mask    ((uint32_t)0xFFFFFE7F)
+#define CFGR_W_Mask        ((uint32_t)0xFFFFFF80)
+#define BIT_Mask           ((uint8_t)0x7F)
+
+/*********************************************************************
+ * @fn      WWDG_DeInit
+ *
+ * @brief   Deinitializes the WWDG peripheral registers to their default reset values
+ *
+ * @return  none
+ */
+void WWDG_DeInit(void)
+{
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetPrescaler
+ *
+ * @brief   Sets the WWDG Prescaler
+ *
+ * @param   WWDG_Prescaler - specifies the WWDG Prescaler
+ *            WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1
+ *            WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2
+ *            WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4
+ *            WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8
+ *
+ * @return  none
+ */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+    uint32_t tmpreg = 0;
+    tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask;
+    tmpreg |= WWDG_Prescaler;
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetWindowValue
+ *
+ * @brief   Sets the WWDG window value
+ *
+ * @param   WindowValue - specifies the window value to be compared to the
+ *        downcounter,which must be lower than 0x80
+ *
+ * @return  none
+ */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+    __IO uint32_t tmpreg = 0;
+
+    tmpreg = WWDG->CFGR & CFGR_W_Mask;
+
+    tmpreg |= WindowValue & (uint32_t)BIT_Mask;
+
+    WWDG->CFGR = tmpreg;
+}
+
+/*********************************************************************
+ * @fn      WWDG_EnableIT
+ *
+ * @brief   Enables the WWDG Early Wakeup interrupt(EWI)
+ *
+ * @return  none
+ */
+void WWDG_EnableIT(void)
+{
+    WWDG->CFGR |= (1 << 9);
+}
+
+/*********************************************************************
+ * @fn      WWDG_SetCounter
+ *
+ * @brief   Sets the WWDG counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ *
+ * @return  none
+ */
+void WWDG_SetCounter(uint8_t Counter)
+{
+    WWDG->CTLR = Counter & BIT_Mask;
+}
+
+/*********************************************************************
+ * @fn      WWDG_Enable
+ *
+ * @brief   Enables WWDG and load the counter value
+ *
+ * @param   Counter - specifies the watchdog counter value,which must be a
+ *        number between 0x40 and 0x7F
+ * @return  none
+ */
+void WWDG_Enable(uint8_t Counter)
+{
+    WWDG->CTLR = CTLR_WDGA_Set | Counter;
+}
+
+/*********************************************************************
+ * @fn      WWDG_GetFlagStatus
+ *
+ * @brief   Checks whether the Early Wakeup interrupt flag is set or not
+ *
+ * @return  The new state of the Early Wakeup interrupt flag (SET or RESET)
+ */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+    return (FlagStatus)(WWDG->STATR);
+}
+
+/*********************************************************************
+ * @fn      WWDG_ClearFlag
+ *
+ * @brief   Clears Early Wakeup interrupt flag
+ *
+ * @return  none
+ */
+void WWDG_ClearFlag(void)
+{
+    WWDG->STATR = (uint32_t)RESET;
+}

bsp/wch/risc-v/Libraries/Kconfig

@@ -0,0 +1,8 @@
+config SOC_RISCV_FAMILY_CH32
+    bool
+
+config SOC_RISCV_SERIES_CH32V103
+    bool
+    select ARCH_RISCV
+    select SOC_RISCV_FAMILY_CH32
+    

bsp/wch/risc-v/Libraries/ch32_drivers/SConscript

@@ -0,0 +1,29 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+""")
+
+
+if  GetDepend('SOC_RISCV_SERIES_CH32V103'):
+
+    if GetDepend('RT_USING_PIN'):
+        src += ['drv_gpio.c']
+
+    if GetDepend(['RT_USING_SERIAL', 'BSP_USING_UART']):
+        src += ['drv_usart.c']
+
+
+
+
+
+path =  [cwd]
+
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.c

@@ -0,0 +1,776 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2017-10-20     ZYH            the first version
+ * 2017-11-15     ZYH            update to 3.0.0
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+#include <rtthread.h>
+#include "drivers/pin.h"
+
+
+#ifdef RT_USING_PIN
+#define __CH32_PIN(index, gpio, gpio_index) {index, GPIO##gpio##_CLK_ENABLE, GPIO##gpio, GPIO_Pin_##gpio_index}
+#define __CH32_PIN_DEFAULT  {-1, 0, 0, 0}
+
+#define PIN_MODE_INPUT_AIN      0x05
+#define PIN_MODE_OUTPUT_AF_OD   0x06
+#define PIN_MODE_OUTPUT_AF_PP   0x07
+
+static void GPIOA_CLK_ENABLE(void)
+{
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+}
+
+static void GPIOB_CLK_ENABLE(void)
+{
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+}
+
+#if (CH32V10X_PIN_NUMBERS >36)
+static void GPIOC_CLK_ENABLE(void)
+{
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
+}
+#endif
+
+#if (CH32V10X_PIN_NUMBERS >48)
+static void GPIOD_CLK_ENABLE(void)
+{
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOD, ENABLE);
+}
+#endif
+
+#if (CH32V10X_PIN_NUMBERS >64)
+static void GPIOE_CLK_ENABLE(void)
+{
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE, ENABLE);
+}
+#endif
+
+
+
+
+
+/* STM32 GPIO driver */
+struct pin_index
+{
+    int index;
+    void (*rcc)(void);
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+static const struct pin_index pins[] =
+{
+#if (CH32V10X_PIN_NUMBERS == 36)
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(7, A, 0),
+    __CH32_PIN(8, A, 1),
+    __CH32_PIN(9, A, 2),
+    __CH32_PIN(10, A, 3),
+    __CH32_PIN(11, A, 4),
+    __CH32_PIN(12, A, 5),
+    __CH32_PIN(13, A, 6),
+    __CH32_PIN(14, A, 7),
+    __CH32_PIN(15, B, 0),
+    __CH32_PIN(16, B, 1),
+    __CH32_PIN(17, B, 2),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(20, A, 8),
+    __CH32_PIN(21, A, 9),
+    __CH32_PIN(22, A, 10),
+    __CH32_PIN(23, A, 11),
+    __CH32_PIN(24, A, 12),
+    __CH32_PIN(25, A, 13),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(28, A, 14),
+    __CH32_PIN(29, A, 15),
+    __CH32_PIN(30, B, 3),
+    __CH32_PIN(31, B, 4),
+    __CH32_PIN(32, B, 5),
+    __CH32_PIN(33, B, 6),
+    __CH32_PIN(34, B, 7),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+#endif
+#if (CH32V10X_PIN_NUMBERS == 48)
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(2, C, 13),
+    __CH32_PIN(3, C, 14),
+    __CH32_PIN(4, C, 15),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(10, A, 0),
+    __CH32_PIN(11, A, 1),
+    __CH32_PIN(12, A, 2),
+    __CH32_PIN(13, A, 3),
+    __CH32_PIN(14, A, 4),
+    __CH32_PIN(15, A, 5),
+    __CH32_PIN(16, A, 6),
+    __CH32_PIN(17, A, 7),
+    __CH32_PIN(18, B, 0),
+    __CH32_PIN(19, B, 1),
+    __CH32_PIN(20, B, 2),
+    __CH32_PIN(21, B, 10),
+    __CH32_PIN(22, B, 11),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(25, B, 12),
+    __CH32_PIN(26, B, 13),
+    __CH32_PIN(27, B, 14),
+    __CH32_PIN(28, B, 15),
+    __CH32_PIN(29, A, 8),
+    __CH32_PIN(30, A, 9),
+    __CH32_PIN(31, A, 10),
+    __CH32_PIN(32, A, 11),
+    __CH32_PIN(33, A, 12),
+    __CH32_PIN(34, A, 13),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(37, A, 14),
+    __CH32_PIN(38, A, 15),
+    __CH32_PIN(39, B, 3),
+    __CH32_PIN(40, B, 4),
+    __CH32_PIN(41, B, 5),
+    __CH32_PIN(42, B, 6),
+    __CH32_PIN(43, B, 7),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(45, B, 8),
+    __CH32_PIN(46, B, 9),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+#endif
+
+#if (CH32V10X_PIN_NUMBERS == 64)
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(2, C, 13),
+    __CH32_PIN(3, C, 14),
+    __CH32_PIN(4, C, 15),
+    __CH32_PIN(5, D, 0),
+    __CH32_PIN(6, D, 1),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(8, C, 0),
+    __CH32_PIN(9, C, 1),
+    __CH32_PIN(10, C, 2),
+    __CH32_PIN(11, C, 3),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(14, A, 0),
+    __CH32_PIN(15, A, 1),
+    __CH32_PIN(16, A, 2),
+    __CH32_PIN(17, A, 3),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(20, A, 4),
+    __CH32_PIN(21, A, 5),
+    __CH32_PIN(22, A, 6),
+    __CH32_PIN(23, A, 7),
+    __CH32_PIN(24, C, 4),
+    __CH32_PIN(25, C, 5),
+    __CH32_PIN(26, B, 0),
+    __CH32_PIN(27, B, 1),
+    __CH32_PIN(28, B, 2),
+    __CH32_PIN(29, B, 10),
+    __CH32_PIN(30, B, 11),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(33, B, 12),
+    __CH32_PIN(34, B, 13),
+    __CH32_PIN(35, B, 14),
+    __CH32_PIN(36, B, 15),
+    __CH32_PIN(37, C, 6),
+    __CH32_PIN(38, C, 7),
+    __CH32_PIN(39, C, 8),
+    __CH32_PIN(40, C, 9),
+    __CH32_PIN(41, A, 8),
+    __CH32_PIN(42, A, 9),
+    __CH32_PIN(43, A, 10),
+    __CH32_PIN(44, A, 11),
+    __CH32_PIN(45, A, 12),
+    __CH32_PIN(46, A, 13),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(49, A, 14),
+    __CH32_PIN(50, A, 15),
+    __CH32_PIN(51, C, 10),
+    __CH32_PIN(52, C, 11),
+    __CH32_PIN(53, C, 12),
+    __CH32_PIN(54, D, 2),
+    __CH32_PIN(55, B, 3),
+    __CH32_PIN(56, B, 4),
+    __CH32_PIN(57, B, 5),
+    __CH32_PIN(58, B, 6),
+    __CH32_PIN(59, B, 7),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(61, B, 8),
+    __CH32_PIN(62, B, 9),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+#endif
+#if (CH32V10X_PIN_NUMBERS == 100)
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(1, E, 2),
+    __CH32_PIN(2, E, 3),
+    __CH32_PIN(3, E, 4),
+    __CH32_PIN(4, E, 5),
+    __CH32_PIN(5, E, 6),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(7, C, 13),
+    __CH32_PIN(8, C, 14),
+    __CH32_PIN(9, C, 15),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(15, C, 0),
+    __CH32_PIN(16, C, 1),
+    __CH32_PIN(17, C, 2),
+    __CH32_PIN(18, C, 3),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(23, A, 0),
+    __CH32_PIN(24, A, 1),
+    __CH32_PIN(25, A, 2),
+    __CH32_PIN(26, A, 3),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(29, A, 4),
+    __CH32_PIN(30, A, 5),
+    __CH32_PIN(31, A, 6),
+    __CH32_PIN(32, A, 7),
+    __CH32_PIN(33, C, 4),
+    __CH32_PIN(34, C, 5),
+    __CH32_PIN(35, B, 0),
+    __CH32_PIN(36, B, 1),
+    __CH32_PIN(37, B, 2),
+    __CH32_PIN(38, E, 7),
+    __CH32_PIN(39, E, 8),
+    __CH32_PIN(40, E, 9),
+    __CH32_PIN(41, E, 10),
+    __CH32_PIN(42, E, 11),
+    __CH32_PIN(43, E, 12),
+    __CH32_PIN(44, E, 13),
+    __CH32_PIN(45, E, 14),
+    __CH32_PIN(46, E, 15),
+    __CH32_PIN(47, B, 10),
+    __CH32_PIN(48, B, 11),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(51, B, 12),
+    __CH32_PIN(52, B, 13),
+    __CH32_PIN(53, B, 14),
+    __CH32_PIN(54, B, 15),
+    __CH32_PIN(55, D, 8),
+    __CH32_PIN(56, D, 9),
+    __CH32_PIN(57, D, 10),
+    __CH32_PIN(58, D, 11),
+    __CH32_PIN(59, D, 12),
+    __CH32_PIN(60, D, 13),
+    __CH32_PIN(61, D, 14),
+    __CH32_PIN(62, D, 15),
+    __CH32_PIN(63, C, 6),
+    __CH32_PIN(64, C, 7),
+    __CH32_PIN(65, C, 8),
+    __CH32_PIN(66, C, 9),
+    __CH32_PIN(67, A, 8),
+    __CH32_PIN(68, A, 9),
+    __CH32_PIN(69, A, 10),
+    __CH32_PIN(70, A, 11),
+    __CH32_PIN(71, A, 12),
+    __CH32_PIN(72, A, 13),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(76, A, 14),
+    __CH32_PIN(77, A, 15),
+    __CH32_PIN(78, C, 10),
+    __CH32_PIN(79, C, 11),
+    __CH32_PIN(80, C, 12),
+    __CH32_PIN(81, D, 0),
+    __CH32_PIN(82, D, 1),
+    __CH32_PIN(83, D, 2),
+    __CH32_PIN(84, D, 3),
+    __CH32_PIN(85, D, 4),
+    __CH32_PIN(86, D, 5),
+    __CH32_PIN(87, D, 6),
+    __CH32_PIN(88, D, 7),
+    __CH32_PIN(89, B, 3),
+    __CH32_PIN(90, B, 4),
+    __CH32_PIN(91, B, 5),
+    __CH32_PIN(92, B, 6),
+    __CH32_PIN(93, B, 7),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN(95, B, 8),
+    __CH32_PIN(96, B, 9),
+    __CH32_PIN(97, E, 0),
+    __CH32_PIN(98, E, 1),
+    __CH32_PIN_DEFAULT,
+    __CH32_PIN_DEFAULT,
+#endif
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t pinbit;
+    IRQn_Type irqno;
+};
+static const struct pin_irq_map pin_irq_map[] =
+{
+    {GPIO_Pin_0, EXTI0_IRQn},
+    {GPIO_Pin_1, EXTI1_IRQn},
+    {GPIO_Pin_2, EXTI2_IRQn},
+    {GPIO_Pin_3, EXTI3_IRQn},
+    {GPIO_Pin_4, EXTI4_IRQn},
+    {GPIO_Pin_5, EXTI9_5_IRQn},
+    {GPIO_Pin_6, EXTI9_5_IRQn},
+    {GPIO_Pin_7, EXTI9_5_IRQn},
+    {GPIO_Pin_8, EXTI9_5_IRQn},
+    {GPIO_Pin_9, EXTI9_5_IRQn},
+    {GPIO_Pin_10, EXTI15_10_IRQn},
+    {GPIO_Pin_11, EXTI15_10_IRQn},
+    {GPIO_Pin_12, EXTI15_10_IRQn},
+    {GPIO_Pin_13, EXTI15_10_IRQn},
+    {GPIO_Pin_14, EXTI15_10_IRQn},
+    {GPIO_Pin_15, EXTI15_10_IRQn},
+};
+struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+    { -1, 0, RT_NULL, RT_NULL},
+};
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+    return index;
+};
+
+void ch32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+    GPIO_WriteBit(index->gpio, index->pin, (BitAction)value);
+}
+
+int ch32_pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+    value = PIN_LOW;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+    value = GPIO_ReadInputDataBit(index->gpio, index->pin);
+    return value;
+}
+
+void ch32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef GPIO_InitStruct;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+    rt_kprintf("get pin index\r\n");
+    /* GPIO Periph clock enable */
+    index->rcc();
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.GPIO_Pin = index->pin;
+    GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_PP;
+    }
+    else if (mode == PIN_MODE_INPUT_AIN)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AIN;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
+//        GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* output setting: od. */
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+//        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_Out_OD;
+    }
+    else if (mode == PIN_MODE_OUTPUT_AF_OD)
+    {
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_OD;
+    }
+    else if (mode == PIN_MODE_OUTPUT_AF_PP)
+    {
+        GPIO_InitStruct.GPIO_Mode = GPIO_Mode_AF_PP;
+    }
+
+    GPIO_Init(index->gpio, &GPIO_InitStruct);
+}
+
+
+rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
+{
+    int i;
+    for (i = 0; i < 32; i++)
+    {
+        if ((0x01 << i) == bit)
+        {
+            return i;
+        }
+    }
+    return -1;
+}
+
+rt_inline const struct pin_irq_map *get_pin_irq_map(uint32_t pinbit)
+{
+    rt_int32_t mapindex = bit2bitno(pinbit);
+    if (mapindex < 0 || mapindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_NULL;
+    }
+    return &pin_irq_map[mapindex];
+};
+rt_err_t ch32_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                              rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t ch32_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    irqindex = bit2bitno(index->pin);
+    if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+    {
+        return RT_ENOSYS;
+    }
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+    return RT_EOK;
+}
+
+rt_err_t ch32_pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                              rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    const struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef GPIO_InitStruct;
+    EXTI_InitTypeDef EXTI_InitStructure;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        irqindex = bit2bitno(index->pin);
+        if (irqindex < 0 || irqindex >= ITEM_NUM(pin_irq_map))
+        {
+            return RT_ENOSYS;
+        }
+        level = rt_hw_interrupt_disable();
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+        irqmap = &pin_irq_map[irqindex];
+        /* GPIO Periph clock enable */
+        index->rcc();
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO,ENABLE);
+
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStruct.GPIO_Pin = index->pin;
+        GPIO_InitStruct.GPIO_Speed = GPIO_Speed_50MHz;
+
+        EXTI_InitStructure.EXTI_Line=index->pin;/* �ⲿ�ж��ߺ����źŶ�Ӧ */
+        EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
+        EXTI_InitStructure.EXTI_LineCmd = ENABLE;
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPD;
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IPU;
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            GPIO_InitStruct.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+            EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+            break;
+        }
+
+        GPIO_Init(index->gpio, &GPIO_InitStruct);
+        EXTI_Init(&EXTI_InitStructure);
+        NVIC_SetPriority(irqmap->irqno,5<<4);
+        NVIC_EnableIRQ( irqmap->irqno );
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        irqmap = get_pin_irq_map(index->pin);
+        if (irqmap == RT_NULL)
+        {
+            return RT_ENOSYS;
+        }
+        NVIC_DisableIRQ(irqmap->irqno);
+    }
+    else
+    {
+        return RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _ch32_pin_ops =
+{
+    ch32_pin_mode,
+    ch32_pin_write,
+    ch32_pin_read,
+    ch32_pin_attach_irq,
+    ch32_pin_dettach_irq,
+    ch32_pin_irq_enable,
+};
+
+int rt_hw_pin_init(void)
+{
+    int result;
+    result = rt_device_pin_register("pin", &_ch32_pin_ops, RT_NULL);
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+    pin_irq_hdr(bit2bitno(GPIO_Pin));
+}
+
+
+void EXTI0_IRQHandler(void) __attribute__((interrupt()));
+void EXTI1_IRQHandler(void) __attribute__((interrupt()));
+void EXTI3_IRQHandler(void) __attribute__((interrupt()));
+void EXTI4_IRQHandler(void) __attribute__((interrupt()));
+void EXTI9_5_IRQHandler(void) __attribute__((interrupt()));
+
+void EXTI0_IRQHandler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+
+    if(EXTI_GetITStatus(EXTI_Line0)!=RESET)
+    {
+        HAL_GPIO_EXTI_Callback(GPIO_Pin_0);
+        EXTI_ClearITPendingBit(EXTI_Line0);
+    }
+
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+void EXTI1_IRQHandler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    if(EXTI_GetITStatus(EXTI_Line1)!=RESET)
+    {
+        HAL_GPIO_EXTI_Callback(GPIO_Pin_1);
+        EXTI_ClearITPendingBit(EXTI_Line1);
+    }
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+void EXTI2_IRQHandler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    if(EXTI_GetITStatus(EXTI_Line2)!=RESET)
+    {
+        HAL_GPIO_EXTI_Callback(GPIO_Pin_2);
+        EXTI_ClearITPendingBit(EXTI_Line2);
+    }
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+void EXTI3_IRQHandler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    if(EXTI_GetITStatus(EXTI_Line3)!=RESET)
+    {
+        HAL_GPIO_EXTI_Callback(GPIO_Pin_3);
+        EXTI_ClearITPendingBit(EXTI_Line3);
+    }
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+void EXTI4_IRQHandler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    if(EXTI_GetITStatus(EXTI_Line4)!=RESET)
+    {
+        HAL_GPIO_EXTI_Callback(GPIO_Pin_4);
+        EXTI_ClearITPendingBit(EXTI_Line4);
+    }
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+void EXTI9_5_IRQHandler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+    if( (EXTI_GetITStatus(EXTI_Line5)!=RESET)|| \
+        (EXTI_GetITStatus(EXTI_Line6)!=RESET)|| \
+        (EXTI_GetITStatus(EXTI_Line7)!=RESET)|| \
+        (EXTI_GetITStatus(EXTI_Line8)!=RESET)|| \
+        (EXTI_GetITStatus(EXTI_Line9)!=RESET) )
+    {
+    HAL_GPIO_EXTI_Callback(GPIO_Pin_5);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin_6);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin_7);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin_8);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin_9);
+    EXTI_ClearITPendingBit(EXTI_Line5|EXTI_Line6|EXTI_Line7|EXTI_Line8|EXTI_Line9);
+    }
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+#endif

bsp/wch/risc-v/Libraries/ch32_drivers/drv_gpio.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-08-10     charlown           first version
+ */
+
+#ifndef DRV_GPIO_H__
+#define DRV_GPIO_H__
+
+int rt_hw_pin_init(void);
+
+#endif

bsp/wch/risc-v/Libraries/ch32_drivers/drv_usart.c

@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2010-03-29     Bernard      remove interrupt Tx and DMA Rx mode
+ * 2013-05-13     aozima       update for kehong-lingtai.
+ * 2015-01-31     armink       make sure the serial transmit complete in putc()
+ * 2016-05-13     armink       add DMA Rx mode
+ * 2017-01-19     aubr.cool    add interrupt Tx mode
+ * 2017-04-13     aubr.cool    correct Rx parity err
+ * 2017-10-20     ZYH          porting to HAL Libraries(with out DMA)
+ * 2017-11-15     ZYH          update to 3.0.0
+ */
+
+#include "board.h"
+#include <rtdevice.h>
+#include <drv_usart.h>
+
+/*  uart driver */
+struct ch32_uart
+{
+    USART_InitTypeDef huart;
+    USART_TypeDef *USARTx;
+    IRQn_Type irq;
+};
+
+static rt_err_t ch32_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct ch32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct ch32_uart *)serial->parent.user_data;
+    uart->huart.USART_BaudRate             = cfg->baud_rate;
+    uart->huart.USART_HardwareFlowControl  = USART_HardwareFlowControl_None;
+    uart->huart.USART_Mode                 = USART_Mode_Rx|USART_Mode_Tx;
+
+    switch (cfg->data_bits)
+    {
+    case DATA_BITS_8:
+        uart->huart.USART_WordLength = USART_WordLength_8b;
+        break;
+    case DATA_BITS_9:
+        uart->huart.USART_WordLength = USART_WordLength_9b;
+        break;
+    default:
+        uart->huart.USART_WordLength = USART_WordLength_8b;
+        break;
+    }
+    switch (cfg->stop_bits)
+    {
+    case STOP_BITS_1:
+        uart->huart.USART_StopBits   = USART_StopBits_1;
+        break;
+    case STOP_BITS_2:
+        uart->huart.USART_StopBits   = USART_StopBits_2;
+        break;
+    default:
+        uart->huart.USART_StopBits   = USART_StopBits_1;
+        break;
+    }
+    switch (cfg->parity)
+    {
+    case PARITY_NONE:
+        uart->huart.USART_Parity    = USART_Parity_No;
+        break;
+    case PARITY_ODD:
+        uart->huart.USART_Parity    = USART_Parity_Odd;
+        break;
+    case PARITY_EVEN:
+        uart->huart.USART_Parity    = USART_Parity_Even;
+        break;
+    default:
+        uart->huart.USART_Parity     = USART_Parity_No;
+        break;
+    }
+
+    if(uart->USARTx == USART1)
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1|RCC_APB2Periph_GPIOA, ENABLE);
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+        USART_Init(uart->USARTx,&uart->huart);
+        USART_Cmd(uart->USARTx, ENABLE);
+    }
+
+    return RT_EOK;
+}
+
+static rt_err_t ch32_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct ch32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct ch32_uart *)serial->parent.user_data;
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        /* disable rx irq */
+        NVIC_DisableIRQ(uart->irq);
+        /* disable interrupt */
+        USART_ITConfig(uart->USARTx,USART_IT_RXNE,DISABLE);
+        break;
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        /* enable rx irq */
+        NVIC_EnableIRQ(uart->irq);
+        /* enable interrupt */
+        USART_ITConfig(uart->USARTx, USART_IT_RXNE,ENABLE);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int ch32_putc(struct rt_serial_device *serial, char c)
+{
+    struct ch32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct ch32_uart *)serial->parent.user_data;
+    while (USART_GetFlagStatus(uart->USARTx, USART_FLAG_TC) == RESET);
+    uart->USARTx->DATAR = c;
+    return 1;
+}
+
+static int ch32_getc(struct rt_serial_device *serial)
+{
+    int ch;
+    struct ch32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct ch32_uart *)serial->parent.user_data;
+    ch = -1;
+    if (USART_GetFlagStatus(uart->USARTx, USART_FLAG_RXNE) != RESET)
+    {
+        ch = uart->USARTx->DATAR & 0xff;
+    }
+    return ch;
+}
+
+
+rt_size_t ch32dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    return RT_EOK;
+}
+
+
+/**
+ * Uart common interrupt process. This need add to uart ISR.
+ *
+ * @param serial serial device
+ */
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct ch32_uart *uart = (struct ch32_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    if (USART_GetITStatus(uart->USARTx, USART_IT_RXNE) != RESET)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        USART_ClearITPendingBit(uart->USARTx, USART_IT_RXNE);
+    }
+}
+
+static const struct rt_uart_ops ch32_uart_ops =
+{
+    ch32_configure,
+    ch32_control,
+    ch32_putc,
+    ch32_getc,
+    ch32dma_transmit
+};
+
+#if defined(BSP_USING_UART1)
+/* UART1 device driver structure */
+struct ch32_uart uart1;
+struct rt_serial_device serial1;
+
+
+
+void USART1_IRQHandler(void) __attribute__((interrupt()));
+void USART1_IRQHandler(void)
+{
+    GET_INT_SP();
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&serial1);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+
+    FREE_INT_SP();
+}
+#endif /* BSP_USING_UART1 */
+
+
+
+
+int rt_hw_usart_init(void)
+{
+    struct ch32_uart *uart;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+
+#if defined(BSP_USING_UART1)
+    uart=&uart1;
+    uart->irq=USART1_IRQn;
+    uart->USARTx=USART1;
+
+    config.baud_rate = BAUD_RATE_115200;
+    serial1.ops      =  &ch32_uart_ops;
+    serial1.config   =  config;
+
+    uart->huart.USART_BaudRate             = 115200;
+    uart->huart.USART_HardwareFlowControl  = USART_HardwareFlowControl_None;
+    uart->huart.USART_Mode                 = USART_Mode_Rx|USART_Mode_Tx;
+    uart->huart.USART_WordLength           = USART_WordLength_8b;
+    uart->huart.USART_StopBits             = USART_StopBits_1;
+    uart->huart.USART_Parity               = USART_Parity_No;
+
+    if(uart->USARTx == USART1)
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1|RCC_APB2Periph_GPIOA, ENABLE);
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+        USART_Init(uart->USARTx,&uart->huart);
+        USART_Cmd(uart->USARTx, ENABLE);
+   }
+
+    /* register UART1 device */
+    rt_hw_serial_register(&serial1, "uart1",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          uart);
+#endif /* BSP_USING_UART1 */
+
+    return 0;
+}
+INIT_BOARD_EXPORT(rt_hw_usart_init);
+

bsp/wch/risc-v/Libraries/ch32_drivers/drv_usart.h

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+#ifndef __USART_H__
+#define __USART_H__
+#include "rthw.h"
+#include "rtthread.h"
+
+int rt_hw_usart_init(void);
+#endif

bsp/wch/risc-v/ch32v103r-evt/.config

@@ -0,0 +1,653 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+# CONFIG_RT_USING_OVERFLOW_CHECK is not set
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_PRINTF_LONGLONG is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x40100
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=1024
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_ULOG_FILE is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# POSIX extension functions
+#
+# CONFIG_PKG_USING_POSIX_GETLINE is not set
+# CONFIG_PKG_USING_POSIX_WCWIDTH is not set
+# CONFIG_PKG_USING_POSIX_ITOA is not set
+# CONFIG_PKG_USING_POSIX_STRINGS is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_RTDUINO is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+CONFIG_SOC_RISCV_FAMILY_CH32=y
+CONFIG_SOC_RISCV_SERIES_CH32V103=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_CH32V103R8=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Board extended module Drivers
+#

bsp/wch/risc-v/ch32v103r-evt/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../Libraries/Kconfig"
+source "board/Kconfig"

bsp/wch/risc-v/ch32v103r-evt/README.md

@@ -0,0 +1,167 @@
+# ch32v103r-evt BSP 说明
+## 开发板简介
+
+ch32v103r-evt 是基于 CH32V103 MCU 推出了一款开发板，包含 WCH-Link 调试器，具有丰富的外设，比较适合入门学习 RISC-V 架构。
+
+开发板图片
+
+<img src="figures/2022-03-27_182300.bmp" alt="2022-03-27_182300" style="zoom:50%;" />
+
+基本硬件资源：
+
+- 青稞 V3A 处理器，最高 80MHz 系统主频；
+- 支持单周期乘法和硬件除法；
+- 20KB SRAM，64KB CodeFlash；
+- 供电范围：2.7V ~ 5.5V，GPIO同步供电电压；
+- 多种低功耗模式：睡眠/停止/待机；
+- 上电/断电复位（POR/PDR）；
+- 可编程电压监测器（PVD）；
+- 7通道 DMA 控制器；
+- 16路 TouchKey 通道监测；
+- 16路12位 ADC 转换通道；
+- 7个定时器；
+- 1个 USB2.0 主机/设备接口（全速和低速）；
+- 2个 IIC 接口（支持 SMBus/PMBus）；
+- 3个 USART 接口；
+- 2个 SPI 接口（支持 Master 和 Slave 模式）；
+- 51个 I/O 口，所有的 I/O 口都可以映射到16个外部中断；
+- CRC 计算单元，96位芯片唯一 ID；
+- 串行单线调试（SWD）接口；
+- 封装形式：LQFP64M、LQFP48、QFN48。
+
+更多信息和资源请访问 [WCH CHV103](http://www.wch.cn/products/CH32V103.html?)
+
+## 编译说明
+
+板级包支持 RISC-V GCC 开发环境，以下是具体版本信息：
+
+| IDE/编译器 | 已测试版本           |
+| ---------- | -------------------- |
+| GCC        | WCH RISC-V GCC 8.2.0 |
+
+
+## 外设支持
+
+本 BSP 目前对外设驱动的支持情况如下：
+
+| 驱动      | 支持情况 |            备注            |
+| --------- | -------- | :------------------------:|
+| UART      | 支持     | USART 1       |
+| GPIO      | 支持     | PA0...PE15                  |
+
+
+### IO在板级支持包中的映射情况
+
+| IO号 | 板级包中的定义 |
+| ---- | -------------- |
+| PA9(默认与板载wch-link串口相连)  | USART1_TX      |
+| PA10(默认与板载wch-link串口相连) | USART1_RX      |
+
+
+
+## 使用说明
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+### 快速上手
+
+本 BSP 为开发者提供 SCons编译配置。下面介绍如何将系统运行起来。
+
+#### SCons 编译
+
+需要先正确配置 RISC-V GCC 位置，推荐使用 RT_Studio 软件包里的
+
+```
+import os
+ARCH     = 'risc-v'
+CPU      = 'ch32v1'
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'D:/Softwares/RT_ThreadStudio/repo/Extract/ToolChain_Support_Packages/WCH/RISC-V-GCC-WCH/8.2.0/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+# if os.getenv('RTT_EXEC_PATH'):
+    # EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+```
+
+开始 scons 编译
+
+```
+LT@DESKTOP-WIN10 E:\WorkSpaces\rt-thread\bsp\wch\risc-v\ch32v103r-evt                             
+>scons                                                                                           
+scons: Reading SConscript files ...                                                               
+Newlib version:3.0.0                                                                              
+scons: done reading SConscript files.                                                             
+scons: Building targets ...                                                                       
+scons: building associated VariantDir targets: build                                              
+CC build\applications\main.o                                                                      
+CC build\board\board.o                                                                            
+CC build\board\ch32v10x_it.o                                                                      
+....                            
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_misc.o                              
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_pwr.o                               
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_rcc.o                               
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_rtc.o                               
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_spi.o                               
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_tim.o                               
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_usart.o                             
+CC build\libraries\ch32_library\StdPeriph_Driver\src\ch32v10x_wwdg.o                              
+LINK rtthread.elf                                                                                 
+riscv-none-embed-objcopy -O binary rtthread.elf rtthread.bin                                      
+riscv-none-embed-size rtthread.elf                                                                
+text    data     bss     dec     hex filename                                                  
+63540     392    8080   72012   1194c rtthread.elf                                              
+scons: done building targets.                                                                     
+```
+
+#### 硬件连接
+
+使用数据线连接板载 wch-link 到 PC，打开电源开关。
+
+#### 下载
+
+打开WCH_RISC-V_Programmer下载软件，选择bsp目录下生成的`rtthread.bin` 文件,单击执行进行下载。
+
+![image-20220404205018822](figures/image-20220404205018822.png)
+
+>  WCH_RISC-V_Programmer下载软件 可以从 MRS IDE中直接导出
+
+#### 运行结果
+
+
+在终端工具里打开板载 wch-link 串口（WCHDapLink SERIAL，默认115200-8-1-N），复位设备后，在串口上可以看到 RT-Thread 的输出信息:
+
+```bash
+
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.1.0 build Apr  4 2022 16:57:50
+ 2006 - 2022 Copyright by RT-Thread team
+
+ MCU: CH32V103C8T6
+ SysClk: 72000000Hz
+ www.wch.cn
+msh >ps
+thread   pri  status      sp     stack size max used left tick  error
+-------- ---  ------- ---------- ----------  ------  ---------- ---
+tshell    20  running 0x00000140 0x00000400    83%   0x00000003 000
+tidle0    31  ready   0x000000b0 0x00000100    70%   0x00000002 000
+timer      4  suspend 0x000000e0 0x00000200    43%   0x00000009 000
+main      10  suspend 0x00000140 0x00000800    20%   0x0000000f 000
+```
+
+## 联系人信息
+
+维护人:
+
+- [blta](https://github.com/blta)

bsp/wch/risc-v/ch32v103r-evt/SConscript

@@ -0,0 +1,15 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/wch/risc-v/ch32v103r-evt/SConstruct

@@ -0,0 +1,64 @@
+import os
+import sys
+import rtconfig
+from SCons.Script import *
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+try:
+    from building import *
+except:
+    print('Cannot found RT-Thread root directory, please check RTT_ROOT')
+    print(RTT_ROOT)
+    exit(-1)
+
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+    env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+    env.Replace(ARFLAGS = [''])
+    env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map')
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/Libraries'):
+    libraries_path_prefix = SDK_ROOT + '/Libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/Libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+ch32_library = 'CH32V10x_StdPeriph_Driver'
+rtconfig.BSP_LIBRARY_TYPE = ch32_library
+
+bsp_vdir = 'build'
+library_vdir = 'build/libraries'
+
+# include libraries
+objs.extend(SConscript(os.path.join(libraries_path_prefix, ch32_library, 'SConscript'), variant_dir=library_vdir + '/ch32_library', duplicate=0))
+
+# common include drivers
+objs.extend(SConscript(os.path.join(libraries_path_prefix, 'ch32_drivers', 'SConscript'), variant_dir=library_vdir + '/ch32_drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/wch/risc-v/ch32v103r-evt/applications/SConscript

@@ -0,0 +1,17 @@
+# RT-Thread building script for component
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+
+# add the general drivers.
+src = Split("""
+main.c
+""")
+
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/wch/risc-v/ch32v103r-evt/applications/main.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-04-03     WCH          first version
+ * 2022-04-05     Blta         modify some formats
+ */
+#include <rtthread.h>
+#include <board.h>
+
+
+/* Global typedef */
+
+/* Global define */
+
+/* LED0(PA1) usd pin device */
+#define LED0_PIN    15
+
+/* Global Variable */
+
+/* LED1 initialization */
+void LED1_BLINK_INIT(void)
+{
+    GPIO_InitTypeDef GPIO_InitStructure = {0};
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+}
+
+/* main thread */
+int main(void)
+{
+    rt_kprintf("\r\n MCU: CH32V103C8T6\r\n");
+    rt_kprintf(" SysClk: %dHz\r\n", SystemCoreClock);
+    rt_kprintf(" www.wch.cn\r\n");
+    LED1_BLINK_INIT();
+
+    GPIO_ResetBits(GPIOA, GPIO_Pin_0);
+    while(1)
+    {
+        GPIO_SetBits(GPIOA, GPIO_Pin_0);
+        rt_thread_mdelay(500);
+
+        GPIO_ResetBits(GPIOA, GPIO_Pin_0);
+        rt_thread_mdelay(500);
+    }
+}
+
+/* led cmd  */
+int led(void)
+{
+    rt_uint8_t count;
+
+    rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
+
+    for(count = 0; count < 10; count++)
+    {
+        rt_pin_write(LED0_PIN, PIN_LOW);
+        rt_kprintf("led on, count : %d\r\n", count);
+        rt_thread_mdelay(500);
+
+        rt_pin_write(LED0_PIN, PIN_HIGH);
+        rt_kprintf("led off\r\n");
+        rt_thread_mdelay(500);
+    }
+    return 0;
+}
+MSH_CMD_EXPORT(led, RT - Thread first led sample by using I / O driver);

bsp/wch/risc-v/ch32v103r-evt/board/Kconfig

@@ -0,0 +1,32 @@
+menu "Hardware Drivers Config"
+
+config SOC_CH32V103R8
+    bool
+    select SOC_RISCV_SERIES_CH32V103
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+menu "On-chip Peripheral Drivers"
+
+config BSP_USING_UART
+    bool "using onchip usart"
+    select RT_USING_SERIAL
+    default n
+
+    if BSP_USING_UART
+        config BSP_USING_UART1
+        bool "using uart1"
+        default n
+    endif
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu

bsp/wch/risc-v/ch32v103r-evt/board/SConscript

@@ -0,0 +1,19 @@
+import os
+import rtconfig
+from building import *
+
+Import('SDK_LIB')
+
+cwd = GetCurrentDir()
+
+# add general drivers
+src = Split('''
+board.c
+debug.c
+ch32v10x_it.c
+''')
+
+path =  [cwd]
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+Return('group')

bsp/wch/risc-v/ch32v103r-evt/board/board.c

@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2017-07-24     Tanek        the first version
+ * 2018-11-12     Ernest Chen  modify copyright
+ */
+
+#include "board.h"
+
+#include <stdint.h>
+#include "drv_usart.h"
+
+#include <rthw.h>
+#include <rtthread.h>
+
+
+/* Updates the variable SystemCoreClock and must be called
+ * whenever the core clock is changed during program execution.
+ */
+extern void SystemCoreClockUpdate(void);
+
+/* core clock */
+extern uint32_t SystemCoreClock;
+
+volatile rt_uint32_t g_ticks=0;
+
+static uint32_t _SysTick_Config(rt_uint32_t ticks)
+{
+    g_ticks=ticks;
+    /* disable hardware pushing stack automatically and disable interrupt nesting */
+    PFIC->CFGR=0xFA050003;
+    NVIC_SetPriority(SysTicK_IRQn,0xf0);
+    NVIC_SetPriority(Software_IRQn,0xf0);
+    SysTick->CTLR=0;
+    SysTick->CNTL0=0;SysTick->CNTL1=0;SysTick->CNTL2=0;SysTick->CNTL3=0;
+    SysTick->CNTH0=0;SysTick->CNTH1=0;SysTick->CNTH2=0;SysTick->CNTH3=0;
+    SysTick->CMPLR0=(rt_uint8_t)(g_ticks-1);
+    SysTick->CMPLR1=(rt_uint8_t)((g_ticks-1)>>8);
+    SysTick->CMPLR2=(rt_uint8_t)((g_ticks-1)>>16);
+    SysTick->CMPLR3=(rt_uint8_t)((g_ticks-1)>>24);
+    SysTick->CMPHR0=0;SysTick->CMPHR1=0;SysTick->CMPHR2=0;SysTick->CMPHR3=0;
+    SysTick->CTLR=0x1;
+    NVIC_EnableIRQ(SysTicK_IRQn);
+    NVIC_EnableIRQ(Software_IRQn);
+    return 0;
+}
+
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+#define RT_HEAP_SIZE (1024)
+/* heap default size: 4K(1024 * 4) */
+static uint32_t rt_heap[RT_HEAP_SIZE];
+RT_WEAK void *rt_heap_begin_get(void)
+{
+    return rt_heap;
+}
+
+RT_WEAK void *rt_heap_end_get(void)
+{
+    return rt_heap + RT_HEAP_SIZE;
+}
+#endif
+
+/**
+ * This function will initial your board.
+ */
+void rt_hw_board_init()
+{
+    /* System Clock Update */
+    SystemCoreClockUpdate();
+
+    /* System Tick Configuration, systick clock is HCLK/8 */
+    _SysTick_Config(SystemCoreClock / 8 / RT_TICK_PER_SECOND);
+    /* Call components board initial (use INIT_BOARD_EXPORT()) */
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+#if defined(RT_USING_USER_MAIN) && defined(RT_USING_HEAP)
+    rt_system_heap_init(rt_heap_begin_get(), rt_heap_end_get());
+#endif
+
+#ifdef RT_USING_CONSOLE
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+}
+
+
+void SysTick_Handler(void) __attribute__((interrupt()));
+void SysTick_Handler(void)
+{
+    GET_INT_SP();
+    /* enter interrupt */
+    rt_interrupt_enter();
+    SysTick->CTLR=0;
+    SysTick->CNTL0=0;SysTick->CNTL1=0;SysTick->CNTL2=0;SysTick->CNTL3=0;
+    SysTick->CNTH0=0;SysTick->CNTH1=0;SysTick->CNTH2=0;SysTick->CNTH3=0;
+    SysTick->CTLR=0x1;
+    rt_tick_increase();
+    /* leave interrupt */
+    rt_interrupt_leave();
+    FREE_INT_SP();
+
+}

bsp/wch/risc-v/ch32v103r-evt/board/board.h

@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2017-10-20     ZYH          emmm...setup for HAL Libraries
+ */
+
+/* <<< Use Configuration Wizard in Context Menu >>> */
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "ch32v10x.h"
+#include <rthw.h>
+#include "drivers/pin.h"
+#define CH32V10X_PIN_NUMBERS   64
+
+/* board configuration */
+#define SRAM_SIZE  20
+#define SRAM_END (0x20000000 + SRAM_SIZE * 1024)
+
+extern int _ebss;
+#define HEAP_BEGIN  ((void *)&_ebss)
+#define HEAP_END    (SRAM_END-_stack_size)
+
+
+/* extern volatile unsigned long  interrupter_sp_saver */
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */

bsp/wch/risc-v/ch32v103r-evt/board/ch32v10x_conf.h

@@ -0,0 +1,41 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_conf.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : Library configuration file.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_CONF_H
+#define __CH32V10x_CONF_H
+
+#include "ch32v10x_adc.h"
+#include "ch32v10x_bkp.h"
+#include "ch32v10x_crc.h"
+#include "ch32v10x_dbgmcu.h"
+#include "ch32v10x_dma.h"
+#include "ch32v10x_exti.h"
+#include "ch32v10x_flash.h"
+#include "ch32v10x_gpio.h"
+#include "ch32v10x_i2c.h"
+#include "ch32v10x_iwdg.h"
+#include "ch32v10x_pwr.h"
+#include "ch32v10x_rcc.h"
+#include "ch32v10x_rtc.h"
+#include "ch32v10x_spi.h"
+#include "ch32v10x_tim.h"
+#include "ch32v10x_usart.h"
+#include "ch32v10x_wwdg.h"
+#include "ch32v10x_usb.h"
+#include "ch32v10x_usb_host.h"
+#include "ch32v10x_it.h"
+#include "ch32v10x_misc.h"
+
+
+#endif /* __CH32V10x_CONF_H */
+
+
+
+
+

bsp/wch/risc-v/ch32v103r-evt/board/ch32v10x_it.c

@@ -0,0 +1,54 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_it.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : Main Interrupt Service Routines.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "ch32v10x_it.h"
+#include "board.h"
+#include <rtthread.h>
+
+void NMI_Handler(void) __attribute__((interrupt()));
+void HardFault_Handler(void) __attribute__((interrupt()));
+
+/*********************************************************************
+ * @fn      NMI_Handler
+ *
+ * @brief   This function handles NMI exception.
+ *
+ * @return  none
+ */
+void NMI_Handler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+
+    rt_kprintf(" NMI Handler\r\n");
+
+    rt_interrupt_leave();
+    FREE_INT_SP();
+}
+
+/*********************************************************************
+ * @fn      HardFault_Handler
+ *
+ * @brief   This function handles Hard Fault exception.
+ *
+ * @return  none
+ */
+void HardFault_Handler(void)
+{
+    GET_INT_SP();
+    rt_interrupt_enter();
+
+    rt_kprintf(" hardfult\r\n");
+    rt_interrupt_leave();
+    FREE_INT_SP();
+
+
+}
+
+

bsp/wch/risc-v/ch32v103r-evt/board/ch32v10x_it.h

@@ -0,0 +1,20 @@
+/********************************** (C) COPYRIGHT *******************************
+ * File Name          : ch32v10x_it.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains the headers of the interrupt handlers.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __CH32V10x_IT_H
+#define __CH32V10x_IT_H
+
+#include "debug.h"
+
+#define GET_INT_SP()   asm("csrrw sp,mscratch,sp")
+#define FREE_INT_SP()  asm("csrrw sp,mscratch,sp")
+
+#endif /* __CH32V10x_IT_H */
+
+

bsp/wch/risc-v/ch32v103r-evt/board/debug.c

@@ -0,0 +1,199 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : debug.c
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for UART
+ *                      Printf , Delay functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#include "debug.h"
+
+static uint8_t  p_us = 0;
+static uint16_t p_ms = 0;
+
+/*********************************************************************
+ * @fn      Delay_Init
+ *
+ * @brief   Initializes Delay Funcation.
+ *
+ * @return  none
+ */
+void Delay_Init(void)
+{
+    p_us = SystemCoreClock / 8000000;
+    p_ms = (uint16_t)p_us * 1000;
+}
+
+/*********************************************************************
+ * @fn      Delay_Us
+ *
+ * @brief   Microsecond Delay Time.
+ *
+ * @param   n - Microsecond number.
+ *
+ * @return  None
+ */
+void Delay_Us(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->CTLR = 0;
+    i = (uint32_t)n * p_us;
+
+    SysTick->CNTL0 = 0;
+    SysTick->CNTL1 = 0;
+    SysTick->CNTL2 = 0;
+    SysTick->CNTL3 = 0;
+    SysTick->CTLR = 1;
+
+    while((*(__IO uint32_t *)0xE000F004) <= i)
+    {
+        ;
+    }
+
+}
+
+/*********************************************************************
+ * @fn      Delay_Ms
+ *
+ * @brief   Millisecond Delay Time.
+ *
+ * @param   n - Millisecond number.
+ *
+ * @return  None
+ */
+void Delay_Ms(uint32_t n)
+{
+    uint32_t i;
+
+    SysTick->CTLR = 0;
+    i = (uint32_t)n * p_ms;
+
+    SysTick->CNTL0 = 0;
+    SysTick->CNTL1 = 0;
+    SysTick->CNTL2 = 0;
+    SysTick->CNTL3 = 0;
+    SysTick->CTLR = 1;
+
+    while((*(__IO uint32_t *)0xE000F004) <= i) ;
+}
+
+/*********************************************************************
+ * @fn      USART_Printf_Init
+ *
+ * @brief   Initializes the USARTx peripheral.
+ *
+ * @param   baudrate - USART communication baud rate.
+ *
+ * @return  None
+ */
+void USART_Printf_Init(uint32_t baudrate)
+{
+    GPIO_InitTypeDef  GPIO_InitStructure;
+    USART_InitTypeDef USART_InitStructure;
+
+#if(DEBUG == DEBUG_UART1)
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART2)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+#elif(DEBUG == DEBUG_UART3)
+    RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
+
+    GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
+    GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+    GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+    GPIO_Init(GPIOB, &GPIO_InitStructure);
+
+#endif
+
+    USART_InitStructure.USART_BaudRate = baudrate;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Tx;
+
+#if(DEBUG == DEBUG_UART1)
+    USART_Init(USART1, &USART_InitStructure);
+    USART_Cmd(USART1, ENABLE);
+
+#elif(DEBUG == DEBUG_UART2)
+    USART_Init(USART2, &USART_InitStructure);
+    USART_Cmd(USART2, ENABLE);
+
+#elif(DEBUG == DEBUG_UART3)
+    USART_Init(USART3, &USART_InitStructure);
+    USART_Cmd(USART3, ENABLE);
+
+#endif
+}
+
+/*********************************************************************
+ * @fn      _write
+ *
+ * @brief   Support Printf Function
+ *
+ * @param   *buf - UART send Data.
+ *          size - Data length.
+ *
+ * @return  size - Data length
+ */
+__attribute__((used))
+int _write(int fd, char *buf, int size)
+{
+    int i;
+
+    for(i = 0; i < size; i++){
+#if(DEBUG == DEBUG_UART1)
+        while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
+        USART_SendData(USART1, *buf++);
+#elif(DEBUG == DEBUG_UART2)
+        while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
+        USART_SendData(USART2, *buf++);
+#elif(DEBUG == DEBUG_UART3)
+        while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
+        USART_SendData(USART3, *buf++);
+#endif
+    }
+
+    return size;
+}
+
+/*********************************************************************
+ * @fn      _sbrk
+ *
+ * @brief   Change the spatial position of data segment.
+ *
+ * @return  size: Data length
+ */
+void *_sbrk(ptrdiff_t incr)
+{
+    extern char _end[];
+    extern char _heap_end[];
+    static char *curbrk = _end;
+
+    if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
+    return NULL - 1;
+
+    curbrk += incr;
+    return curbrk - incr;
+}
+
+
+

bsp/wch/risc-v/ch32v103r-evt/board/debug.h

@@ -0,0 +1,32 @@
+/********************************** (C) COPYRIGHT  *******************************
+ * File Name          : debug.h
+ * Author             : WCH
+ * Version            : V1.0.0
+ * Date               : 2020/04/30
+ * Description        : This file contains all the functions prototypes for UART
+ *                      Printf , Delay functions.
+ * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ *******************************************************************************/
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+#include "stdio.h"
+#include "ch32v10x.h"
+
+/* UART Printf Definition */
+#define DEBUG_UART1    1
+#define DEBUG_UART2    2
+#define DEBUG_UART3    3
+
+/* DEBUG UATR Definition */
+#define DEBUG          DEBUG_UART1
+//#define DEBUG   DEBUG_UART2
+//#define DEBUG   DEBUG_UART3
+
+void Delay_Init(void);
+void Delay_Us(uint32_t n);
+void Delay_Ms(uint32_t n);
+void USART_Printf_Init(uint32_t baudrate);
+
+#endif /* __DEBUG_H */

bsp/wch/risc-v/ch32v103r-evt/rtconfig.h

@@ -0,0 +1,192 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40100
+#define ARCH_RISCV
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 1024
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* POSIX extension functions */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+
+/* AI packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+#define SOC_RISCV_FAMILY_CH32
+#define SOC_RISCV_SERIES_CH32V103
+
+/* Hardware Drivers Config */
+
+#define SOC_CH32V103R8
+
+/* On-chip Peripheral Drivers */
+
+#define BSP_USING_UART
+#define BSP_USING_UART1
+
+/* Onboard Peripheral Drivers */
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/wch/risc-v/ch32v103r-evt/rtconfig.py

@@ -0,0 +1,62 @@
+import os
+ARCH     = 'risc-v'
+CPU      = 'ch32v1'
+# toolchains options
+CROSS_TOOL  = 'gcc'
+
+#------- toolchains path -------------------------------------------------------
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'D:/Softwares/RT_ThreadStudio/repo/Extract/ToolChain_Support_Packages/WCH/RISC-V-GCC-WCH/8.2.0/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+# if os.getenv('RTT_EXEC_PATH'):
+    # EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+CORE = 'risc-v'
+MAP_FILE = 'rtthread.map'
+LINK_FILE = './board/linker_scripts/link.lds'
+TARGET_NAME = 'rtthread.bin'
+
+#------- GCC settings ----------------------------------------------------------
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'riscv-none-embed-'
+    CC = PREFIX + 'gcc'
+    CXX= PREFIX + 'g++'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -march=rv32imac -mabi=ilp32 -DUSE_PLIC -DUSE_M_TIME -DNO_INIT -mcmodel=medany -msmall-data-limit=8 -L.  -nostartfiles  -lc '
+    CFLAGS = DEVICE
+    CFLAGS += ' -save-temps=obj'
+    AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE
+    LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
+    LFLAGS += ' -T ' + LINK_FILE
+    LFLAGS += ' -Wl,-wrap=memset'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n'
+    POST_ACTION += SIZE + ' $TARGET\n'

bsp/wch/risc-v/tools/sdk_dist.py

@@ -0,0 +1,36 @@
+import os
+import sys
+import shutil
+cwd_path = os.getcwd()
+sys.path.append(os.path.join(os.path.dirname(cwd_path), 'rt-thread', 'tools'))
+
+# BSP dist function
+def dist_do_building(BSP_ROOT, dist_dir):
+    from mkdist import bsp_copy_files
+    import rtconfig
+
+    print("=> copy ch32 bsp library")
+    library_dir = os.path.join(dist_dir, 'Libraries')
+    library_path = os.path.join(os.path.dirname(BSP_ROOT), 'Libraries')
+    bsp_copy_files(os.path.join(library_path, rtconfig.BSP_LIBRARY_TYPE),
+                   os.path.join(library_dir, rtconfig.BSP_LIBRARY_TYPE))
+
+    print("=> copy bsp drivers")
+    bsp_copy_files(os.path.join(library_path, 'ch32_drivers'), os.path.join(library_dir, 'ch32_drivers'))
+    shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
+# change RTT_ROOT in Kconfig
+    if not os.path.isfile(os.path.join(dist_dir, 'Kconfig')):
+        return
+
+    with open(os.path.join(dist_dir, 'Kconfig'), 'r') as f:
+        data = f.readlines()
+    with open(os.path.join(dist_dir, 'Kconfig'), 'w') as f:
+        found = 0
+        for line in data:
+            if line.find('RTT_ROOT') != -1:
+                found = 1
+            if line.find('../Libraries') != -1 and found:
+                position = line.find('../Libraries')
+                line = line[0:position] + 'Libraries/Kconfig"\n'
+                found = 0
+            f.write(line)

libcpu/risc-v/SConscript

@@ -16,6 +16,8 @@ elif rtconfig.CPU == "nuclei" :
     group = group
 elif rtconfig.CPU == "virt64" :
     group = group
+elif rtconfig.CPU == "ch32v1" :
+    group = group    
 else :
     group = group + SConscript(os.path.join('common', 'SConscript'))
 

libcpu/risc-v/ch32v1/SConscript

@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')

libcpu/risc-v/ch32v1/context_gcc.S

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ */
+
+#include "cpuport.h"
+
+/*
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch_to(rt_ubase_t to);
+ * #endif
+ * a0 --> to
+ * a1 --> to_thread
+ */
+    .globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    /* first save interrupt stack */
+	la t0, _eusrstack
+	addi t0, t0, -512
+    csrw mscratch,t0
+
+    LOAD sp, (a0)
+    LOAD a0,   2 * REGBYTES(sp)
+    csrw mstatus, a0
+    j    rt_hw_context_switch_exit
+
+
+/*
+ * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
+ * a0 --> from
+ * a1 --> to
+ */
+	.globl rt_hw_context_switch
+rt_hw_context_switch:
+	/* switch in thread */
+#ifdef ARCH_RISCV_FPU
+	addi sp, sp, -32*FREGBYTES
+
+    FSTORE  f0, 0 * FREGBYTES(sp)
+    FSTORE  f1, 1 * FREGBYTES(sp)
+    FSTORE  f2, 2 * FREGBYTES(sp)
+    FSTORE  f3, 3 * FREGBYTES(sp)
+    FSTORE  f4, 4 * FREGBYTES(sp)
+    FSTORE  f5, 5 * FREGBYTES(sp)
+    FSTORE  f6, 6 * FREGBYTES(sp)
+    FSTORE  f7, 7 * FREGBYTES(sp)
+    FSTORE  f8, 8 * FREGBYTES(sp)
+    FSTORE  f9, 9 * FREGBYTES(sp)
+    FSTORE  f10, 10 * FREGBYTES(sp)
+    FSTORE  f11, 11 * FREGBYTES(sp)
+    FSTORE  f12, 12 * FREGBYTES(sp)
+    FSTORE  f13, 13 * FREGBYTES(sp)
+    FSTORE  f14, 14 * FREGBYTES(sp)
+    FSTORE  f15, 15 * FREGBYTES(sp)
+    FSTORE  f16, 16 * FREGBYTES(sp)
+    FSTORE  f17, 17 * FREGBYTES(sp)
+    FSTORE  f18, 18 * FREGBYTES(sp)
+    FSTORE  f19, 19 * FREGBYTES(sp)
+    FSTORE  f20, 20 * FREGBYTES(sp)
+    FSTORE  f21, 21 * FREGBYTES(sp)
+    FSTORE  f22, 22 * FREGBYTES(sp)
+    FSTORE  f23, 23 * FREGBYTES(sp)
+    FSTORE  f24, 24 * FREGBYTES(sp)
+    FSTORE  f25, 25 * FREGBYTES(sp)
+    FSTORE  f26, 26 * FREGBYTES(sp)
+    FSTORE  f27, 27 * FREGBYTES(sp)
+    FSTORE  f28, 28 * FREGBYTES(sp)
+    FSTORE  f29, 29 * FREGBYTES(sp)
+    FSTORE  f30, 30 * FREGBYTES(sp)
+    FSTORE  f31, 31 * FREGBYTES(sp)
+#endif
+
+	addi sp, sp, -32 * REGBYTES
+	/* save from sp */
+	STORE sp,   0(a0)
+	/* save ra to epc */
+	STORE x1,   0 * REGBYTES(sp)
+	STORE x1,   1 * REGBYTES(sp)
+	STORE x5,   5 * REGBYTES(sp)
+
+	csrr  t0,  mstatus
+	andi  t0, t0, 8
+	/* if MIE be enabled,set MPIE */
+	beqz  t0, 1f
+	li    t0, 0x80
+
+1:  STORE t0,   2 * REGBYTES(sp)
+	STORE x4,   4 * REGBYTES(sp)
+
+	STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+	/* get "to" thread sp */
+	LOAD  sp,  0(a1)
+	j  rt_hw_context_switch_exit
+
+
+.global rt_hw_context_switch_exit
+rt_hw_context_switch_exit:
+    /* resw ra to mepc */
+    LOAD a0,   0 * REGBYTES(sp)
+    csrw mepc, a0
+
+    LOAD x1,   1 * REGBYTES(sp)
+	/* keep machine mode */
+	li    a0,      0x1800
+	csrs  mstatus, a0
+	/* resume MPIE */
+	LOAD  a0,      2*REGBYTES(sp)
+    csrs  mstatus, a0
+
+    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x5,   5 * REGBYTES(sp)
+    LOAD x6,   6 * REGBYTES(sp)
+    LOAD x7,   7 * REGBYTES(sp)
+    LOAD x8,   8 * REGBYTES(sp)
+    LOAD x9,   9 * REGBYTES(sp)
+    LOAD x10, 10 * REGBYTES(sp)
+    LOAD x11, 11 * REGBYTES(sp)
+    LOAD x12, 12 * REGBYTES(sp)
+    LOAD x13, 13 * REGBYTES(sp)
+    LOAD x14, 14 * REGBYTES(sp)
+    LOAD x15, 15 * REGBYTES(sp)
+    LOAD x16, 16 * REGBYTES(sp)
+    LOAD x17, 17 * REGBYTES(sp)
+    LOAD x18, 18 * REGBYTES(sp)
+    LOAD x19, 19 * REGBYTES(sp)
+    LOAD x20, 20 * REGBYTES(sp)
+    LOAD x21, 21 * REGBYTES(sp)
+    LOAD x22, 22 * REGBYTES(sp)
+    LOAD x23, 23 * REGBYTES(sp)
+    LOAD x24, 24 * REGBYTES(sp)
+    LOAD x25, 25 * REGBYTES(sp)
+    LOAD x26, 26 * REGBYTES(sp)
+    LOAD x27, 27 * REGBYTES(sp)
+    LOAD x28, 28 * REGBYTES(sp)
+    LOAD x29, 29 * REGBYTES(sp)
+    LOAD x30, 30 * REGBYTES(sp)
+    LOAD x31, 31 * REGBYTES(sp)
+    addi sp,  sp, 32 * REGBYTES
+
+ /* load float reg */
+#ifdef ARCH_RISCV_FPU
+
+    FLOAD   f0, 0 * FREGBYTES(sp)
+    FLOAD   f1, 1 * FREGBYTES(sp)
+    FLOAD   f2, 2 * FREGBYTES(sp)
+    FLOAD   f3, 3 * FREGBYTES(sp)
+    FLOAD   f4, 4 * FREGBYTES(sp)
+    FLOAD   f5, 5 * FREGBYTES(sp)
+    FLOAD   f6, 6 * FREGBYTES(sp)
+    FLOAD   f7, 7 * FREGBYTES(sp)
+    FLOAD   f8, 8 * FREGBYTES(sp)
+    FLOAD   f9, 9 * FREGBYTES(sp)
+    FLOAD   f10, 10 * FREGBYTES(sp)
+    FLOAD   f11, 11 * FREGBYTES(sp)
+    FLOAD   f12, 12 * FREGBYTES(sp)
+    FLOAD   f13, 13 * FREGBYTES(sp)
+    FLOAD   f14, 14 * FREGBYTES(sp)
+    FLOAD   f15, 15 * FREGBYTES(sp)
+    FLOAD   f16, 16 * FREGBYTES(sp)
+    FLOAD   f17, 17 * FREGBYTES(sp)
+    FLOAD   f18, 18 * FREGBYTES(sp)
+    FLOAD   f19, 19 * FREGBYTES(sp)
+    FLOAD   f20, 20 * FREGBYTES(sp)
+    FLOAD   f21, 21 * FREGBYTES(sp)
+    FLOAD   f22, 22 * FREGBYTES(sp)
+    FLOAD   f23, 23 * FREGBYTES(sp)
+    FLOAD   f24, 24 * FREGBYTES(sp)
+    FLOAD   f25, 25 * FREGBYTES(sp)
+    FLOAD   f26, 26 * FREGBYTES(sp)
+    FLOAD   f27, 27 * FREGBYTES(sp)
+    FLOAD   f28, 28 * FREGBYTES(sp)
+    FLOAD   f29, 29 * FREGBYTES(sp)
+    FLOAD   f30, 30 * FREGBYTES(sp)
+    FLOAD   f31, 31 * FREGBYTES(sp)
+    addi    sp, sp, 32 * FREGBYTES
+#endif
+
+    mret

libcpu/risc-v/ch32v1/cpuport.c

@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "ch32v10x.h"
+#include "cpuport.h"
+
+#ifndef RT_USING_SMP
+volatile rt_ubase_t  rt_interrupt_from_thread = 0;
+volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
+volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
+#endif
+
+struct rt_hw_stack_frame
+{
+    rt_ubase_t epc;        /* epc - epc    - program counter                     */
+    rt_ubase_t ra;         /* x1  - ra     - return address for jumps            */
+    rt_ubase_t mstatus;    /*              - machine status register             */
+    rt_ubase_t gp;         /* x3  - gp     - global pointer                      */
+    rt_ubase_t tp;         /* x4  - tp     - thread pointer                      */
+    rt_ubase_t t0;         /* x5  - t0     - temporary register 0                */
+    rt_ubase_t t1;         /* x6  - t1     - temporary register 1                */
+    rt_ubase_t t2;         /* x7  - t2     - temporary register 2                */
+    rt_ubase_t s0_fp;      /* x8  - s0/fp  - saved register 0 or frame pointer   */
+    rt_ubase_t s1;         /* x9  - s1     - saved register 1                    */
+    rt_ubase_t a0;         /* x10 - a0     - return value or function argument 0 */
+    rt_ubase_t a1;         /* x11 - a1     - return value or function argument 1 */
+    rt_ubase_t a2;         /* x12 - a2     - function argument 2                 */
+    rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
+    rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
+    rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
+    rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
+    rt_ubase_t a7;         /* x17 - s7     - function argument 7                 */
+    rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
+    rt_ubase_t s3;         /* x19 - s3     - saved register 3                    */
+    rt_ubase_t s4;         /* x20 - s4     - saved register 4                    */
+    rt_ubase_t s5;         /* x21 - s5     - saved register 5                    */
+    rt_ubase_t s6;         /* x22 - s6     - saved register 6                    */
+    rt_ubase_t s7;         /* x23 - s7     - saved register 7                    */
+    rt_ubase_t s8;         /* x24 - s8     - saved register 8                    */
+    rt_ubase_t s9;         /* x25 - s9     - saved register 9                    */
+    rt_ubase_t s10;        /* x26 - s10    - saved register 10                   */
+    rt_ubase_t s11;        /* x27 - s11    - saved register 11                   */
+    rt_ubase_t t3;         /* x28 - t3     - temporary register 3                */
+    rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
+    rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
+    rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+
+/* float register */
+#ifdef ARCH_RISCV_FPU
+    rv_floatreg_t f0;      /* f0  */
+    rv_floatreg_t f1;      /* f1  */
+    rv_floatreg_t f2;      /* f2  */
+    rv_floatreg_t f3;      /* f3  */
+    rv_floatreg_t f4;      /* f4  */
+    rv_floatreg_t f5;      /* f5  */
+    rv_floatreg_t f6;      /* f6  */
+    rv_floatreg_t f7;      /* f7  */
+    rv_floatreg_t f8;      /* f8  */
+    rv_floatreg_t f9;      /* f9  */
+    rv_floatreg_t f10;     /* f10 */
+    rv_floatreg_t f11;     /* f11 */
+    rv_floatreg_t f12;     /* f12 */
+    rv_floatreg_t f13;     /* f13 */
+    rv_floatreg_t f14;     /* f14 */
+    rv_floatreg_t f15;     /* f15 */
+    rv_floatreg_t f16;     /* f16 */
+    rv_floatreg_t f17;     /* f17 */
+    rv_floatreg_t f18;     /* f18 */
+    rv_floatreg_t f19;     /* f19 */
+    rv_floatreg_t f20;     /* f20 */
+    rv_floatreg_t f21;     /* f21 */
+    rv_floatreg_t f22;     /* f22 */
+    rv_floatreg_t f23;     /* f23 */
+    rv_floatreg_t f24;     /* f24 */
+    rv_floatreg_t f25;     /* f25 */
+    rv_floatreg_t f26;     /* f26 */
+    rv_floatreg_t f27;     /* f27 */
+    rv_floatreg_t f28;     /* f28 */
+    rv_floatreg_t f29;     /* f29 */
+    rv_floatreg_t f30;     /* f30 */
+    rv_floatreg_t f31;     /* f31 */
+#endif
+};
+
+/*
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void       *tentry,
+                             void       *parameter,
+                             rt_uint8_t *stack_addr,
+                             void       *texit)
+{
+    struct rt_hw_stack_frame *frame;
+    rt_uint8_t *stk;
+    int i;
+
+    stk  = stack_addr + sizeof(rt_ubase_t);
+    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
+    stk -= sizeof(struct rt_hw_stack_frame);
+
+    frame = (struct rt_hw_stack_frame *)stk;
+
+    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
+    {
+        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
+    }
+
+    frame->ra = (rt_ubase_t)texit;
+    frame->a0 = (rt_ubase_t)parameter;
+    frame->epc = (rt_ubase_t)tentry;
+
+    /* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
+    frame->mstatus = 0x00001880;
+    return stk;
+}
+
+/*
+ * trigger soft interrupt
+ */
+void sw_setpend(void)
+{
+    NVIC_SetPendingIRQ(Software_IRQn);
+}
+
+/*
+ * clear soft interrupt
+ */
+void sw_clearpend(void)
+{
+    NVIC_ClearPendingIRQ(Software_IRQn);
+}
+
+/*
+ * disable interrupt and save mstatus
+ */
+rt_base_t rt_hw_interrupt_disable(void)
+{
+    rt_base_t value = 0;
+    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
+    return value;
+}
+
+/*
+ * enable interrupt and resume mstatus
+ */
+void rt_hw_interrupt_enable(rt_base_t level)
+{
+    asm("csrw mstatus, %0": :"r"(level));
+}
+
+
+/*
+ * #ifdef RT_USING_SMP
+ * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
+ * #else
+ * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
+ * #endif
+ */
+void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
+{
+    if (rt_thread_switch_interrupt_flag == 0)
+        rt_interrupt_from_thread = from;
+
+    rt_interrupt_to_thread = to;
+    rt_thread_switch_interrupt_flag = 1;
+    /* switch just in sw_handler */
+    sw_setpend();
+}
+
+
+
+/* shutdown CPU */
+void rt_hw_cpu_shutdown(void)
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}

libcpu/risc-v/ch32v1/cpuport.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ */
+
+#ifndef CPUPORT_H__
+#define CPUPORT_H__
+
+/* bytes of register width  */
+//#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+
+#ifdef ARCH_CPU_64BIT
+#define STORE                   sd
+#define LOAD                    ld
+#define REGBYTES                8
+#else
+#define STORE                   sw
+#define LOAD                    lw
+#define REGBYTES                4
+#endif
+
+/* FPU */
+#ifdef ARCH_RISCV_FPU
+#ifdef ARCH_RISCV_FPU_D
+#define FSTORE                  fsd
+#define FLOAD                   fld
+#define FREGBYTES               8
+#define rv_floatreg_t           rt_int64_t
+#endif
+#ifdef ARCH_RISCV_FPU_S
+#define FSTORE                  fsw
+#define FLOAD                   flw
+#define FREGBYTES               4
+#define rv_floatreg_t           rt_int32_t
+#endif
+#endif
+
+#endif

libcpu/risc-v/ch32v1/interrupt_gcc.S

@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ */
+ 
+#include "cpuport.h"
+
+.global SW_handler
+.align 2
+SW_handler:
+    /* save all from thread context */
+#ifdef ARCH_RISCV_FPU
+    addi    sp, sp, -32 * FREGBYTES
+    FSTORE  f0, 0 * FREGBYTES(sp)
+    FSTORE  f1, 1 * FREGBYTES(sp)
+    FSTORE  f2, 2 * FREGBYTES(sp)
+    FSTORE  f3, 3 * FREGBYTES(sp)
+    FSTORE  f4, 4 * FREGBYTES(sp)
+    FSTORE  f5, 5 * FREGBYTES(sp)
+    FSTORE  f6, 6 * FREGBYTES(sp)
+    FSTORE  f7, 7 * FREGBYTES(sp)
+    FSTORE  f8, 8 * FREGBYTES(sp)
+    FSTORE  f9, 9 * FREGBYTES(sp)
+    FSTORE  f10, 10 * FREGBYTES(sp)
+    FSTORE  f11, 11 * FREGBYTES(sp)
+    FSTORE  f12, 12 * FREGBYTES(sp)
+    FSTORE  f13, 13 * FREGBYTES(sp)
+    FSTORE  f14, 14 * FREGBYTES(sp)
+    FSTORE  f15, 15 * FREGBYTES(sp)
+    FSTORE  f16, 16 * FREGBYTES(sp)
+    FSTORE  f17, 17 * FREGBYTES(sp)
+    FSTORE  f18, 18 * FREGBYTES(sp)
+    FSTORE  f19, 19 * FREGBYTES(sp)
+    FSTORE  f20, 20 * FREGBYTES(sp)
+    FSTORE  f21, 21 * FREGBYTES(sp)
+    FSTORE  f22, 22 * FREGBYTES(sp)
+    FSTORE  f23, 23 * FREGBYTES(sp)
+    FSTORE  f24, 24 * FREGBYTES(sp)
+    FSTORE  f25, 25 * FREGBYTES(sp)
+    FSTORE  f26, 26 * FREGBYTES(sp)
+    FSTORE  f27, 27 * FREGBYTES(sp)
+    FSTORE  f28, 28 * FREGBYTES(sp)
+    FSTORE  f29, 29 * FREGBYTES(sp)
+    FSTORE  f30, 30 * FREGBYTES(sp)
+    FSTORE  f31, 31 * FREGBYTES(sp)
+#endif
+
+    addi sp, sp, -32 * REGBYTES
+    STORE x5,   5 * REGBYTES(sp)
+
+    /* saved MPIE */
+ 	li    t0,   0x80
+    STORE t0,   2 * REGBYTES(sp)
+
+    STORE x1,   1 * REGBYTES(sp)
+    STORE x4,   4 * REGBYTES(sp)
+    STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+    /* switch to interrupt stack */
+	csrrw sp,mscratch,sp
+    call  rt_interrupt_enter
+    /* clear interrupt */
+    jal   sw_clearpend
+    call  rt_interrupt_leave
+    /* switch to from thread stack */
+	csrrw sp,mscratch,sp
+
+    /* if rt_thread_switch_interrupt_flag=1,then clear it  */
+    la    s0, rt_thread_switch_interrupt_flag
+    lw    s2, 0(s0)
+    beqz  s2, 1f
+    sw    zero, 0(s0)
+#1:
+    csrr  a0, mepc
+    STORE a0, 0 * REGBYTES(sp)
+
+    la    s0, rt_interrupt_from_thread
+    LOAD  s1, 0(s0)
+    STORE sp, 0(s1)
+
+    la    s0, rt_interrupt_to_thread
+    LOAD  s1, 0(s0)
+    LOAD  sp, 0(s1)
+
+    LOAD  a0,  0 * REGBYTES(sp)
+    csrw  mepc, a0
+
+1:  LOAD  x1,   1 * REGBYTES(sp)
+
+	li t0,0x1800
+	csrs mstatus, t0
+	LOAD t0, 2*REGBYTES(sp)
+	csrs mstatus, t0
+
+    LOAD  x4,   4 * REGBYTES(sp)
+    LOAD  x5,   5 * REGBYTES(sp)
+    LOAD  x6,   6 * REGBYTES(sp)
+    LOAD  x7,   7 * REGBYTES(sp)
+    LOAD  x8,   8 * REGBYTES(sp)
+    LOAD  x9,   9 * REGBYTES(sp)
+    LOAD  x10, 10 * REGBYTES(sp)
+    LOAD  x11, 11 * REGBYTES(sp)
+    LOAD  x12, 12 * REGBYTES(sp)
+    LOAD  x13, 13 * REGBYTES(sp)
+    LOAD  x14, 14 * REGBYTES(sp)
+    LOAD  x15, 15 * REGBYTES(sp)
+    LOAD  x16, 16 * REGBYTES(sp)
+    LOAD  x17, 17 * REGBYTES(sp)
+    LOAD  x18, 18 * REGBYTES(sp)
+    LOAD  x19, 19 * REGBYTES(sp)
+    LOAD  x20, 20 * REGBYTES(sp)
+    LOAD  x21, 21 * REGBYTES(sp)
+    LOAD  x22, 22 * REGBYTES(sp)
+    LOAD  x23, 23 * REGBYTES(sp)
+    LOAD  x24, 24 * REGBYTES(sp)
+    LOAD  x25, 25 * REGBYTES(sp)
+    LOAD  x26, 26 * REGBYTES(sp)
+    LOAD  x27, 27 * REGBYTES(sp)
+    LOAD  x28, 28 * REGBYTES(sp)
+    LOAD  x29, 29 * REGBYTES(sp)
+    LOAD  x30, 30 * REGBYTES(sp)
+    LOAD  x31, 31 * REGBYTES(sp)
+    addi  sp, sp, 32 * REGBYTES
+
+    /* load float reg */
+#ifdef ARCH_RISCV_FPU
+    FLOAD   f0, 0 * FREGBYTES(sp)
+    FLOAD   f1, 1 * FREGBYTES(sp)
+    FLOAD   f2, 2 * FREGBYTES(sp)
+    FLOAD   f3, 3 * FREGBYTES(sp)
+    FLOAD   f4, 4 * FREGBYTES(sp)
+    FLOAD   f5, 5 * FREGBYTES(sp)
+    FLOAD   f6, 6 * FREGBYTES(sp)
+    FLOAD   f7, 7 * FREGBYTES(sp)
+    FLOAD   f8, 8 * FREGBYTES(sp)
+    FLOAD   f9, 9 * FREGBYTES(sp)
+    FLOAD   f10, 10 * FREGBYTES(sp)
+    FLOAD   f11, 11 * FREGBYTES(sp)
+    FLOAD   f12, 12 * FREGBYTES(sp)
+    FLOAD   f13, 13 * FREGBYTES(sp)
+    FLOAD   f14, 14 * FREGBYTES(sp)
+    FLOAD   f15, 15 * FREGBYTES(sp)
+    FLOAD   f16, 16 * FREGBYTES(sp)
+    FLOAD   f17, 17 * FREGBYTES(sp)
+    FLOAD   f18, 18 * FREGBYTES(sp)
+    FLOAD   f19, 19 * FREGBYTES(sp)
+    FLOAD   f20, 20 * FREGBYTES(sp)
+    FLOAD   f21, 21 * FREGBYTES(sp)
+    FLOAD   f22, 22 * FREGBYTES(sp)
+    FLOAD   f23, 23 * FREGBYTES(sp)
+    FLOAD   f24, 24 * FREGBYTES(sp)
+    FLOAD   f25, 25 * FREGBYTES(sp)
+    FLOAD   f26, 26 * FREGBYTES(sp)
+    FLOAD   f27, 27 * FREGBYTES(sp)
+    FLOAD   f28, 28 * FREGBYTES(sp)
+    FLOAD   f29, 29 * FREGBYTES(sp)
+    FLOAD   f30, 30 * FREGBYTES(sp)
+    FLOAD   f31, 31 * FREGBYTES(sp)
+    addi    sp, sp, 32 * FREGBYTES
+#endif
+    mret