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@@ -203,7 +203,7 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
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spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
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spi_handle->Init.TIMode = SPI_TIMODE_DISABLE;
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spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi_handle->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
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spi_handle->State = HAL_SPI_STATE_RESET;
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spi_handle->State = HAL_SPI_STATE_RESET;
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-#ifdef SOC_SERIES_STM32L4
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+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
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spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
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spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
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#endif
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#endif
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@@ -212,7 +212,8 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
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return RT_EIO;
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return RT_EIO;
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}
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}
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-#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0)|| defined(SOC_SERIES_STM32F7)
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+#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F0) \
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+ || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32G0)
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SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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SET_BIT(spi_handle->Instance->CR2, SPI_RXFIFO_THRESHOLD_HF);
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#endif
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#endif
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@@ -389,7 +390,7 @@ static int rt_hw_spi_bus_init(void)
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spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
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spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
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spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
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-#elif defined(SOC_SERIES_STM32L4)
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
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spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
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spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
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#endif
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#endif
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spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
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spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
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@@ -408,7 +409,7 @@ static int rt_hw_spi_bus_init(void)
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{
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{
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rt_uint32_t tmpreg = 0x00U;
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rt_uint32_t tmpreg = 0x00U;
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-#if defined(SOC_SERIES_STM32F1)
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+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0)
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/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
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/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
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SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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@@ -427,7 +428,7 @@ static int rt_hw_spi_bus_init(void)
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spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
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spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
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spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
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spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
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-#elif defined(SOC_SERIES_STM32L4)
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+#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0)
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spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
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spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
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#endif
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#endif
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spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
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@@ -446,7 +447,7 @@ static int rt_hw_spi_bus_init(void)
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{
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{
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rt_uint32_t tmpreg = 0x00U;
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rt_uint32_t tmpreg = 0x00U;
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-#if defined(SOC_SERIES_STM32F1)
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+#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0)
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/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
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/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
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SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
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