[bsp] add core-v-mcu bsp (#6705)

* add core-v-mcu bsp

* 规范bsp格式 添加readme

* 修改readme

Co-authored-by: 1516081466@qq.com <ws051000>

bsp/core-v-mcu/Libraries/Kconfig

@@ -0,0 +1,7 @@
+config SOC_RISCV_FAMILY_Core_V
+    bool
+
+config SOC_RISCV_SERIES_Core_V
+    bool
+    select ARCH_RISCV
+    select SOC_RISCV_FAMILY_Core_V

bsp/core-v-mcu/Libraries/core_v_drivers/SConscript

@@ -0,0 +1,21 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+cwd = GetCurrentDir()
+
+src = Split("""
+source/udma_uart_driver.c
+""")
+
+if  GetDepend('SOC_RISCV_FAMILY_Core_V'):
+
+    if GetDepend('BSP_USING_UART'):
+        src += ['source/drv_usart.c']
+
+path = [
+	cwd + '/include']
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/core-v-mcu/Libraries/core_v_drivers/include/camera.h

@@ -0,0 +1,33 @@
+#ifndef __CAMERA_H__
+#define __CAMERA_H__
+
+//#include <FreeRTOS.h>
+#include <queue.h>
+#include "himax.h"
+
+
+typedef struct {
+	volatile uint32_t *rx_saddr; // 0x00
+	volatile uint32_t rx_size; 	 // 0x04
+	volatile uint32_t rx_cfg;    // 0x08
+	volatile uint32_t rx_initcfg;// 0x0C
+	volatile uint32_t *tx_saddr; // 0x10
+	volatile uint32_t tx_size;   // 0x14
+	volatile uint32_t tx_cfg;    // 0x18
+	volatile uint32_t tx_initcfg;// 0x1C
+	volatile uint32_t cfg_glob;  // 0x20
+	volatile uint32_t cfg_ll;    // 0x24
+	volatile uint32_t cfg_ur;    // 0x28
+	volatile uint32_t cfg_size;  // 0x2C
+	volatile uint32_t cfg_filter;// 0x30
+	volatile uint32_t vsync_pol; // 0x34
+
+} camera_struct_t;
+
+typedef struct {
+	uint16_t addr;
+	uint8_t data;
+}reg_cfg_t;
+
+
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_log.h

@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-15     SummerGift   first version
+ */
+
+/*
+ * NOTE: DO NOT include this file on the header file.
+ */
+
+#ifndef LOG_TAG
+#define DBG_TAG               "drv"
+#else
+#define DBG_TAG               LOG_TAG
+#endif /* LOG_TAG */
+
+#ifdef DRV_DEBUG
+#define DBG_LVL               DBG_LOG
+#else
+#define DBG_LVL               DBG_INFO
+#endif /* DRV_DEBUG */
+
+#include <rtdbg.h>

bsp/core-v-mcu/Libraries/core_v_drivers/include/drv_usart.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-08     WangShun     the first version
+ */
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
+#include <rtthread.h>
+#include "rtdevice.h"
+#include <rthw.h>
+
+/* corev config class */
+struct corev_uart_config
+{
+    const char *name;
+};
+
+/* corevs uart dirver class */
+struct corev_uart
+{
+    struct corev_uart_config *config;
+    struct rt_serial_device serial;
+};
+
+extern void uart_rx_isr (void *id);
+int rt_hw_usart_init(void);
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/himax.h

@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Copyright (C) 2018 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __HIMAX_H__
+#define __HIMAX_H__
+
+/*
+ *  HIMAX camera macros
+ */
+// Register address
+// Read only registers
+#define         MODEL_ID_H          0x0000
+#define         MODEL_ID_L          0x0001
+#define         FRAME_COUNT         0x0005
+#define         PIXEL_ORDER         0x0006
+// R&W registers
+// Sensor mode control
+#define         MODE_SELECT         0x0100
+#define         IMG_ORIENTATION     0x0101
+#define         SW_RESET            0x0103
+#define         GRP_PARAM_HOLD      0x0104
+// Sensor exposure gain control
+#define         INTEGRATION_H       0x0202
+#define         INTEGRATION_L       0x0203
+#define         ANALOG_GAIN         0x0205
+#define         DIGITAL_GAIN_H      0x020E
+#define         DIGITAL_GAIN_L      0x020F
+// Frame timing control
+#define         FRAME_LEN_LINES_H   0x0340
+#define         FRAME_LEN_LINES_L   0x0341
+#define         LINE_LEN_PCK_H      0x0342
+#define         LINE_LEN_PCK_L      0x0343
+// Binning mode control
+#define         READOUT_X           0x0383
+#define         READOUT_Y           0x0387
+#define         BINNING_MODE        0x0390
+// Test pattern control
+#define         TEST_PATTERN_MODE   0x0601
+// Black level control
+#define         BLC_CFG             0x1000
+#define         BLC_TGT             0x1003
+#define         BLI_EN              0x1006
+#define         BLC2_TGT            0x1007
+//  Sensor reserved
+#define         DPC_CTRL            0x1008
+#define         SINGLE_THR_HOT      0x100B
+#define         SINGLE_THR_COLD     0x100C
+// VSYNC,HSYNC and pixel shift register
+#define         VSYNC_HSYNC_PIXEL_SHIFT_EN  0x1012
+// Automatic exposure gain control
+#define         AE_CTRL             0x2100
+#define         AE_TARGET_MEAN      0x2101
+#define         AE_MIN_MEAN         0x2102
+#define         CONVERGE_IN_TH      0x2103
+#define         CONVERGE_OUT_TH     0x2104
+#define         MAX_INTG_H          0x2105
+#define         MAX_INTG_L          0x2106
+#define         MIN_INTG            0x2107
+#define         MAX_AGAIN_FULL      0x2108
+#define         MAX_AGAIN_BIN2      0x2109
+#define         MIN_AGAIN           0x210A
+#define         MAX_DGAIN           0x210B
+#define         MIN_DGAIN           0x210C
+#define         DAMPING_FACTOR      0x210D
+#define         FS_CTRL             0x210E
+#define         FS_60HZ_H           0x210F
+#define         FS_60HZ_L           0x2110
+#define         FS_50HZ_H           0x2111
+#define         FS_50HZ_L           0x2112
+#define         FS_HYST_TH          0x2113
+// Motion detection control
+#define         MD_CTRL             0x2150
+#define         I2C_CLEAR           0x2153
+#define         WMEAN_DIFF_TH_H     0x2155
+#define         WMEAN_DIFF_TH_M     0x2156
+#define         WMEAN_DIFF_TH_L     0x2157
+#define         MD_THH              0x2158
+#define         MD_THM1             0x2159
+#define         MD_THM2             0x215A
+#define         MD_THL              0x215B
+//  Sensor timing control
+#define         QVGA_WIN_EN         0x3010
+#define         SIX_BIT_MODE_EN     0x3011
+#define         PMU_AUTOSLEEP_FRAMECNT  0x3020
+#define         ADVANCE_VSYNC       0x3022
+#define         ADVANCE_HSYNC       0x3023
+#define         EARLY_GAIN          0x3035
+//  IO and clock control
+#define         BIT_CONTROL         0x3059
+#define         OSC_CLK_DIV         0x3060
+#define         ANA_Register_11     0x3061
+#define         IO_DRIVE_STR        0x3062
+#define         IO_DRIVE_STR2       0x3063
+#define         ANA_Register_14     0x3064
+#define         OUTPUT_PIN_STATUS_CONTROL   0x3065
+#define         ANA_Register_17     0x3067
+#define         PCLK_POLARITY       0x3068
+
+/*
+ * Useful value of Himax registers
+ */
+#define         HIMAX_RESET         0x01
+#define         Pclk_rising_edge    0x00
+#define         Pclk_falling_edge   0x01
+
+#define         BYPASS_BIGEND       5
+
+enum{
+    HIMAX_Standby = 0x0,
+    HIMAX_Streaming = 0x1,        // I2C triggered streaming enable
+    HIMAX_Streaming2 = 0x3,       // Output N frames
+    HIMAX_Streaming3 = 0x5        // Hardware Trigger
+};
+
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_cam_driver.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_cam_reg_defs.h"
+
+typedef enum {
+		kCamReset,
+		kCamID,
+		kCamInit,
+		kCamFrame
+} udma_cam_control_type_t;
+
+typedef enum {
+	kSPIm_Cfg 	    = (0x0 << 28),
+	kSPIm_SOT	    = (0x1 << 28),
+	kSPIm_SendCmd	= (0x2 << 28),
+	kSPIm_Dummy	    = (0x4 << 28),
+	kSPIm_Wait		= (0x5 << 28),
+	kSPIm_TxData	= (0x6 << 28),
+	kSPIm_RxData  	= (0x7 << 28),
+	kSPIm_Repeat	= (0x8 << 28),
+	kSPIm_EOT		= (0x9 << 28),
+	kSPIm_RepeatEnd = (0xa << 28),
+	kSPIm_RxCheck	= (0xb << 28),
+	kSPIm_FDX 		= (0xc << 28),
+	kSPIm_UCA 		= (0xd << 28),
+	kSPIm_UCS 		= (0xe << 28)
+
+} cam_cmd_t;
+
+
+uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam);
+void cam_open (uint8_t cam_id);
+
+
+// helper functions
+void _himaxRegWrite(unsigned int addr, unsigned char value);
+
+#endif /* DRIVERS_INCLUDE_UDMA_CAM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_i2cm_driver.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+#define SEMAPHORE_WAIT_TIME_IN_MS	10
+
+typedef enum {
+		kI2cmReset
+} udma_i2cm_control_type_t;
+
+typedef enum {
+	kI2cmCmdStart 	= 0x00,
+	kI2cmCmdStop	= 0x20,
+	kI2cmCmdRdAck	= 0x40,
+	kI2cmCmdRdNack	= 0x60,
+	kI2cmCmdWr		= 0x80,
+	kI2cmCmdWait	= 0xA0,
+	kI2cmCmdRpt		= 0xC0,
+	kI2cmCmdCfg		= 0xE0,
+	kI2cmCmdWaitEvt	= 0x10,
+} i2cm_cmd_t;
+
+uint16_t udma_i2cm_open (uint8_t i2c_id, uint32_t i2c_clk_freq);
+uint16_t udma_i2cm_close (uint8_t i2c_id);
+uint16_t udma_i2cm_control(uint8_t i2c_id, udma_i2cm_control_type_t control_type, void* pparam);
+uint8_t udma_i2cm_write(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t write_len, uint8_t* write_data, bool more_follows);
+uint8_t udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
+uint8_t udma_i2cm_16read8(uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
+
+
+
+// helper functions
+uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2c_id, uint8_t i2c_addr, uint8_t reg_addr);
+uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2c_id, uint8_t i2c_addr, uint16_t reg_addr);
+uint8_t _udma_i2cm_read(uint8_t i2c_id, uint8_t i2c_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows);
+uint8_t _udma_i2cm_send_stop(uint8_t i2c_id);
+
+#endif /* DRIVERS_INCLUDE_UDMA_I2CM_DRIVER_H_ */
+

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_qspi_driver.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+typedef enum {
+		kQSPImReset
+} udma_qspim_control_type_t;
+
+typedef enum {
+	kSPIm_Cfg 	    = (0x0 << 28),
+	kSPIm_SOT	    = (0x1 << 28),
+	kSPIm_SendCmd	= (0x2 << 28),
+	kSPIm_Dummy	    = (0x4 << 28),
+	kSPIm_Wait		= (0x5 << 28),
+	kSPIm_TxData	= (0x6 << 28),
+	kSPIm_RxData  	= (0x7 << 28),
+	kSPIm_Repeat	= (0x8 << 28),
+	kSPIm_EOT		= (0x9 << 28),
+	kSPIm_RepeatEnd = (0xa << 28),
+	kSPIm_RxCheck	= (0xb << 28),
+	kSPIm_FDX 		= (0xc << 28),
+	kSPIm_UCA 		= (0xd << 28),
+	kSPIm_UCS 		= (0xe << 28)
+
+} spim_cmd_t;
+
+uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t spi_clk_freq);
+uint16_t udma_qspim_close (uint8_t qspim_id);
+uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam);
+void udma_qspim_write(uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
+void udma_qspim_read(uint8_t qspim_id,  uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
+uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd);
+uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs);
+void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
+void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
+uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs);
+uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs);
+
+// helper functions
+
+
+#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_sdio_driver.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
+#define DRIVERS_INCLUDE_UDMA_SDIO_DRIVER_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+typedef enum {
+		kSDIOmReset
+} udma_sdio_control_type_t;
+/*
+typedef enum {
+	kSPIm_Cfg 	    = (0x0 << 28),
+	kSPIm_SOT	    = (0x1 << 28),
+	kSPIm_SendCmd	= (0x2 << 28),
+	kSPIm_Dummy	    = (0x4 << 28),
+	kSPIm_Wait		= (0x5 << 28),
+	kSPIm_TxData	= (0x6 << 28),
+	kSPIm_RxData  	= (0x7 << 28),
+	kSPIm_Repeat	= (0x8 << 28),
+	kSPIm_EOT		= (0x9 << 28),
+	kSPIm_RepeatEnd = (0xa << 28),
+	kSPIm_RxCheck	= (0xb << 28),
+	kSPIm_FDX 		= (0xc << 28),
+	kSPIm_UCA 		= (0xd << 28),
+	kSPIm_UCS 		= (0xe << 28)
+
+} spim_cmd_t;
+*/
+uint16_t udma_sdio_open (uint8_t sdio_id);
+uint16_t udma_sdio_close (uint8_t sdio_id);
+uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam);
+uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf);
+void udma_sdio_write(uint8_t sdio_id, uint8_t cs, uint16_t write_len, uint8_t* write_data);
+void udma_sdio_read(uint8_t sdio_id,  uint8_t cs, uint16_t read_len, uint8_t* read_buffer);
+uint8_t udma_flash_erase(uint8_t sdio_id, uint8_t cs, uint32_t addr, uint8_t cmd);
+uint32_t udma_flash_readid(uint8_t sdio_id, uint8_t cs);
+void udma_flash_read(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) ;
+void udma_flash_write(uint8_t sdio_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t write_len ) ;
+uint32_t udma_flash_reset_enable(uint8_t sdio_id, uint8_t cs);
+uint32_t udma_flash_reset_memory(uint8_t sdio_id, uint8_t cs);
+
+uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
+uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen);
+void udma_sdio_clearDataSetup(uint8_t sdio_id);
+
+// helper functions
+
+
+#endif /* DRIVERS_INCLUDE_UDMA_QSPIM_DRIVER_H_ */

bsp/core-v-mcu/Libraries/core_v_drivers/include/udma_uart_driver.h

@@ -0,0 +1,39 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ 
+#ifndef __UDMA_UART_DRIVER_H_
+#define __UDMA_UART_DRIVER_H_
+
+#include "stdint.h"
+
+#include "hal_udma_ctrl_reg_defs.h"
+
+typedef enum {
+		kUartDataValid
+} udma_uart_control_type_t;
+
+uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate);
+uint16_t udma_uart_close (uint8_t uart_id);
+uint16_t udma_uart_write(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
+uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer);
+uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
+uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer);
+uint8_t udma_uart_getchar(uint8_t uart_id);
+uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam);
+
+#endif //__UDMA_UART_DRIVER_H_

bsp/core-v-mcu/Libraries/core_v_drivers/source/drv_usart.c

@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-08     WangShun          the first version
+ */
+
+#include "board.h"
+#include <rtdevice.h>
+#include <drv_usart.h>
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_uart_reg_defs.h"
+#include "udma_uart_driver.h"
+#include <string.h>
+#include "core-v-mcu-config.h"
+
+#ifdef RT_USING_SERIAL
+//#define DRV_DEBUG
+#define LOG_TAG              "drv.uart"
+#include <drv_log.h>
+
+#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && !defined(BSP_USING_UART4) && \
+    !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) 
+    #error "Please define at least one BSP_USING_UARTx"
+    /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
+#endif
+
+extern char u1buffer[128], u0buffer[128];
+extern  int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
+extern UdmaUart_t *puart0 ;
+extern UdmaUart_t *puart1 ;
+
+enum
+{
+    UART1_INDEX,
+};
+
+struct corev_uart_config uart_config[1] =
+{
+   {
+     "uart1"
+   }
+};
+
+struct corev_uart uart_obj[1] = {0};
+
+static rt_err_t corev_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+     return RT_EOK;
+}
+
+static rt_err_t corev_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    return RT_EOK;
+}
+
+uint16_t rt_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->status_b.tx_busy) {
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1;
+
+	return 0;
+}
+
+static int corev_putc(struct rt_serial_device *serial, char c)
+{
+	char put_data =c;
+    struct corev_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct corev_uart *)serial->parent.user_data;
+    rt_writeraw(0, 1,&put_data);
+
+    return 1;
+}
+
+static int corev_getc(struct rt_serial_device *serial)
+{
+    signed char ch;
+    struct corev_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct corev_uart *)serial->parent.user_data;
+    ch = -1;
+
+	UdmaUart_t*	puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + 0 * UDMA_CH_SIZE);
+
+	if (puart->valid_b.rx_data_valid == 1) {
+		ch = puart->data_b.rx_data & 0xff;
+	}
+
+    return (int)ch;
+}
+
+rt_size_t corevdma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    return RT_EOK;
+}
+
+ void uart_isr(struct rt_serial_device *serial)
+{
+    struct corev_uart *uart = (struct corev_uart *) serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+}
+
+static const struct rt_uart_ops corev_uart_ops =
+{
+    corev_configure,
+    corev_control,
+    corev_putc,
+    corev_getc,
+    corevdma_transmit
+};
+
+void uart_rx_isr (void *id){
+	rt_interrupt_enter();
+	if (id == 6) {
+		while (*(int*)0x1a102130) {
+			u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
+			u1wrptr &= 0x7f;
+		}
+	}
+	if (id == 2) {//use this uart
+		while (puart0->valid) {
+			uart_isr(&(uart_obj[UART1_INDEX].serial));
+		}
+	}
+	rt_interrupt_leave();
+}
+
+int rt_hw_usart_init(void)
+{
+    rt_size_t obj_num = 1;
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t result = 0;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        /* init UART object */
+        uart_obj[i].config        = &uart_config[i];
+        uart_obj[i].serial.ops    = &corev_uart_ops;
+        uart_obj[i].serial.config = config;
+
+        /* register UART device */
+        result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                       RT_DEVICE_FLAG_RDWR
+                                       | RT_DEVICE_FLAG_INT_RX
+                                       ,&uart_obj[i]);
+        RT_ASSERT(result == RT_EOK);
+    }
+    return result;
+}
+
+#endif /* RT_USING_SERIAL */

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_cam_driver.c

@@ -0,0 +1,240 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <drivers/include/camera.h>
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_cam_reg_defs.h"
+
+#include <drivers/include/udma_cam_driver.h>
+#include <drivers/include/udma_i2cm_driver.h>
+
+#include "drivers/include/himax.h"
+#include "drivers/include/camera.h"
+
+reg_cfg_t himaxRegInit[] = {
+    {BLC_TGT, 0x08},            //  BLC target :8  at 8 bit mode
+    {BLC2_TGT, 0x08},           //  BLI target :8  at 8 bit mode
+    {0x3044, 0x0A},             //  Increase CDS time for settling
+    {0x3045, 0x00},             //  Make symetric for cds_tg and rst_tg
+    {0x3047, 0x0A},             //  Increase CDS time for settling
+    {0x3050, 0xC0},             //  Make negative offset up to 4x
+    {0x3051, 0x42},
+    {0x3052, 0x50},
+    {0x3053, 0x00},
+    {0x3054, 0x03},             //  tuning sf sig clamping as lowest
+    {0x3055, 0xF7},             //  tuning dsun
+    {0x3056, 0xF8},             //  increase adc nonoverlap clk
+    {0x3057, 0x29},             //  increase adc pwr for missing code
+    {0x3058, 0x1F},             //  turn on dsun
+    {0x3059, 0x1E},
+    {0x3064, 0x00},
+    {0x3065, 0x04},             //  pad pull 0
+
+    {BLC_CFG, 0x43},            //  BLC_on, IIR
+
+    {0x1001, 0x43},             //  BLC dithering en
+    {0x1002, 0x43},             //  blc_darkpixel_thd
+    {0x0350, 0x00},             //  Dgain Control
+    {BLI_EN, 0x01},             //  BLI enable
+    {0x1003, 0x00},             //  BLI Target [Def: 0x20]
+
+    {DPC_CTRL, 0x01},           //  DPC option 0: DPC off   1 : mono   3 : bayer1   5 : bayer2
+    {0x1009, 0xA0},             //  cluster hot pixel th
+    {0x100A, 0x60},             //  cluster cold pixel th
+    {SINGLE_THR_HOT, 0x90},     //  single hot pixel th
+    {SINGLE_THR_COLD, 0x40},    //  single cold pixel th
+    {0x1012, 0x00},             //  Sync. shift disable
+    {0x2000, 0x07},
+    {0x2003, 0x00},
+    {0x2004, 0x1C},
+    {0x2007, 0x00},
+    {0x2008, 0x58},
+    {0x200B, 0x00},
+    {0x200C, 0x7A},
+    {0x200F, 0x00},
+    {0x2010, 0xB8},
+    {0x2013, 0x00},
+    {0x2014, 0x58},
+    {0x2017, 0x00},
+    {0x2018, 0x9B},
+
+    {AE_CTRL,        0x01},      //Automatic Exposure Gain Control
+    {AE_TARGET_MEAN, 0x3C},      //AE target mean [Def: 0x3C]
+    {AE_MIN_MEAN,    0x0A},      //AE min target mean [Def: 0x0A]
+
+    {INTEGRATION_H,  0x00},      //Integration H [Def: 0x01]
+    {INTEGRATION_L,  0x60},      //Integration L [Def: 0x08]
+    {ANALOG_GAIN,    0x00},      //Analog Global Gain
+    {DAMPING_FACTOR, 0x20},      //Damping Factor [Def: 0x20]
+    {DIGITAL_GAIN_H, 0x01},      //Digital Gain High [Def: 0x01]
+    {DIGITAL_GAIN_L, 0x00},      //Digital Gain Low [Def: 0x00]
+
+    {0x2103, 0x03},
+
+    {0x2104, 0x05},
+    {0x2105, 0x01},
+
+    {0x2106, 0x54},
+
+    {0x2108, 0x03},
+    {0x2109, 0x04},
+
+    {0x210B, 0xC0},
+    {0x210E, 0x00}, //Flicker Control
+    {0x210F, 0x00},
+    {0x2110, 0x3C},
+    {0x2111, 0x00},
+    {0x2112, 0x32},
+
+    {0x2150, 0x30},
+    {0x0340, 0x02},
+    {0x0341, 0x16},
+    {0x0342, 0x01},
+    {0x0343, 0x78},
+    {0x3010, 0x01},
+    {0x0383, 0x01},
+    {0x0387, 0x01},
+    {0x0390, 0x00},
+    {0x3011, 0x70},
+    {0x3059, 0x02},
+    {0x3060, 0x01},
+//    {0x3060, 0x25}, //Clock gating and clock divisors
+    {0x3068, 0x20}, //PCLK0 polarity
+    {IMG_ORIENTATION, 0x01}, // change the orientation
+    {0x0104, 0x01},
+    {0x0100, 0x01},
+	//{0x0601, 0x11}	//Test pattern walking ones
+	//{0x0601, 0x01}	//Test pattern colour bar
+};
+
+SemaphoreHandle_t  cam_semaphore_rx;
+static uint8_t cam;
+static void camISR() {
+
+}
+void cam_open (uint8_t cam_id)
+{
+	int i = 0;
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
+
+	//psdio_regs->clk_div_b.clk_div = 5;
+	//psdio_regs->clk_div_b.valid = 1;
+	hal_setpinmux(21, 0);
+	hal_setpinmux(22, 0);
+	hal_setpinmux(25, 0);
+	for(i=0; i<8; i++ )
+	{
+		//set pin muxes to sdio functionality
+		 hal_setpinmux(29+i, 0);
+	}
+
+	/* See if already initialized */
+	if (cam_semaphore_rx != NULL ){
+		return;
+	}
+
+	/* Set semaphore */
+	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	cam_semaphore_rx = shSemaphoreHandle;
+
+
+	/* Set handlers. */
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_CAM_RX(cam_id), camISR, cam_semaphore_rx);
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_CAM_RX(cam_id));
+
+	/* configure */
+	cam = 0x48; // Himax address
+	udma_cam_control(kCamReset, NULL);
+
+	return;
+}
+uint16_t udma_cam_control(udma_cam_control_type_t control_type, void* pparam) {
+	short retval = 0;
+	uint16_t i;
+	SemaphoreHandle_t shSemaphoreHandle;
+	camera_struct_t *camera;
+	//camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
+	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
+	shSemaphoreHandle = cam_semaphore_rx;
+
+	switch (control_type) {
+	case kCamReset:
+		_himaxRegWrite(SW_RESET, HIMAX_RESET);
+		break;
+	case kCamID:
+		udma_i2cm_16read8(0, cam, MODEL_ID_H, 2, &retval, 0);
+		retval = (retval >> 8) & 0xff | (retval <<8);
+		break;
+	case kCamInit:
+	    for(i=0; i<(sizeof(himaxRegInit)/sizeof(reg_cfg_t)); i++){
+	        _himaxRegWrite(himaxRegInit[i].addr, himaxRegInit[i].data);
+	    }
+	    camera->cfg_ll = 0<<16 | 0;
+	    	camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
+	    	camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
+	    	camera->cfg_size = 324;
+	    	camera->vsync_pol = 1;
+	    	camera->cfg_glob = (0 << 0) | //  framedrop disabled
+	    			(000000 << 1) | // number of frames to drop
+	    			(0 << 7) | // Frame slice disabled
+	    			(004 << 8) | // Format binary 100 = ByPass little endian
+	    			(0000 << 11);  // Shift value ignored in bypass
+
+	    break;
+	case kCamFrame:
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		camera->rx_saddr = pparam;
+		camera->rx_size = (244*324);
+		camera->rx_cfg = 0x12;  // start 16-bit transfers
+    	camera->cfg_glob = camera->cfg_glob |
+    			(1 << 31) ; // enable 1 == go
+
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+    	camera->cfg_glob = camera->cfg_glob &
+    			(0x7fffffff) ; // enable 1 == go
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+	}
+	return retval;
+}
+
+void _himaxRegWrite(unsigned int addr, unsigned char value){
+	uint8_t naddr;
+	uint16_t data;
+	naddr = (addr>>8) & 0xff;
+	data = (value << 8) | (addr & 0xff);
+	udma_i2cm_write (0, cam, naddr, 2, &data, 0);
+   //     i2c_16write8(cam,addr,value);
+}

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_i2cm_driver.c

@@ -0,0 +1,355 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_i2cm_reg_defs.h"
+
+#include <drivers/include/udma_i2cm_driver.h>
+
+#define  unuse_freertos_in_i2cm
+
+
+SemaphoreHandle_t  i2cm_semaphores_rx[N_I2CM];
+SemaphoreHandle_t  i2cm_semaphores_tx[N_I2CM];
+
+void i2cmTXHandler(void *arg)
+{
+	uint32_t lCounter = 0;
+
+	lCounter++;
+}
+
+void i2cmRXHandler(void *arg)
+{
+	uint32_t lCounter = 0;
+
+	lCounter++;
+}
+
+static uint8_t aucclkdiv[2];
+
+uint16_t udma_i2cm_open (uint8_t i2cm_id, uint32_t clk_freq) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint32_t					clk_divisor;
+
+	/* See if already initialized */
+	if (i2cm_semaphores_rx[i2cm_id] != NULL || i2cm_semaphores_tx[i2cm_id] != NULL) {
+		return 1;
+	}
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+
+	/* Set semaphore */
+	#ifndef unuse_freertos_in_i2cm
+	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	i2cm_semaphores_rx[i2cm_id] = shSemaphoreHandle;
+
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	i2cm_semaphores_tx[i2cm_id] = shSemaphoreHandle;
+	#endif
+	/* Set handlers. */
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_RX(i2cm_id), i2cmRXHandler/*NULL*/, i2cm_semaphores_rx[i2cm_id]);
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_I2C_TX(i2cm_id), i2cmTXHandler/*NULL*/, i2cm_semaphores_tx[i2cm_id]);
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_RX(i2cm_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_I2C_TX(i2cm_id));
+
+	/* configure */
+	clk_divisor = 5000000/clk_freq;
+	aucclkdiv[0] = (clk_divisor >> 0) & 0xFF;
+	aucclkdiv[1] = (clk_divisor >> 8) & 0xFF;
+
+	return 0;
+}
+
+uint16_t udma_i2cm_control(uint8_t i2cm_id, udma_i2cm_control_type_t control_type, void* pparam) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kI2cmReset:
+		pudma_ctrl->reg_rst |= (UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_I2CM0_CLKEN << i2cm_id);
+		break;
+	default:
+		configASSERT(0);
+	}
+	return 0;
+}
+
+static uint8_t auccmd_rx[16];
+
+uint8_t udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
+	_udma_i2cm_write_addr_plus_regaddr(i2cm_id, i2cm_addr, reg_addr);
+	return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
+}
+uint8_t udma_i2cm_16read8(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
+	_udma_i2cm_write_addr_plus_reg16addr(i2cm_id, i2cm_addr, reg_addr);
+	return _udma_i2cm_read(i2cm_id, i2cm_addr, read_len, read_buffer, more_follows);
+}
+
+static uint8_t auccmd_tx[32];
+uint8_t udma_i2cm_write (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr, uint16_t write_len, uint8_t *write_data,  bool more_follows) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_tx;
+	uint8_t*					pdata = write_data;
+	SemaphoreHandle_t 			shSemaphoreHandleTx = i2cm_semaphores_tx[i2cm_id];
+	uint8_t lStatus = pdFALSE;
+
+	configASSERT(write_len < 256);
+
+	if( xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE ) // Wait for any prior transmission to complete
+	{
+		*pcmd++ = kI2cmCmdCfg;
+		*pcmd++ = aucclkdiv[1];
+		*pcmd++ = aucclkdiv[0];
+		*pcmd++ = kI2cmCmdStart;			// Put Start transaction on I2C bus
+		*pcmd++ = kI2cmCmdRpt; 				// Set up for several writes: i2cm_CMD_RPT
+		*pcmd++ = (uint8_t)(write_len + 2);	// I@CM_ADDR + REG_ADDR + data
+		*pcmd++ = kI2cmCmdWr; 				// Command to repeat: I2C CMD_WR
+		*pcmd++ = i2cm_addr & 0xfe; 		// Clear R/WRbar bit from i2c device's address to indicate write
+		*pcmd++ = reg_addr;					// Target address for following data
+		for (int i = 0; i != write_len; i++) {
+			*pcmd++ = *pdata++;
+		}
+		pi2cm_regs->tx_saddr = auccmd_tx;
+		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA transaction is completed
+		xSemaphoreTake( shSemaphoreHandleTx, SEMAPHORE_WAIT_TIME_IN_MS );
+		xSemaphoreGive( shSemaphoreHandleTx );
+
+		if (!more_follows) {
+			_udma_i2cm_send_stop(i2cm_id);
+		}
+		lStatus = pdTRUE;
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandleTx );
+	}
+	return lStatus;
+}
+
+uint8_t _udma_i2cm_write_addr_plus_regaddr (uint8_t i2cm_id, uint8_t i2cm_addr, uint8_t reg_addr) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_tx;
+	uint8_t lStatus = pdFALSE;
+
+	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		pi2cm_regs->tx_cfg_b.en = 0;
+		*pcmd++ = kI2cmCmdCfg;
+		*pcmd++ = aucclkdiv[1];
+		*pcmd++ = aucclkdiv[0];
+		*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
+		*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
+		*pcmd++ = i2cm_addr & 0xfe; 	// Clear R/WRbar bit from i2c device's address to indicate write
+		*pcmd++ = kI2cmCmdWr; 		// I2C CMD_WR
+		pi2cm_regs->tx_saddr = auccmd_tx;
+		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA operation is completed
+		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+		{
+			//pi2cm_regs->tx_cfg_b.en = 0;
+			pcmd = auccmd_tx;
+			*pcmd++ = reg_addr;
+			pi2cm_regs->tx_saddr = auccmd_tx;
+			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+			pi2cm_regs->tx_cfg_b.en = 1;
+
+			// Block until UDMA operation is completed
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+			lStatus = pdTRUE;
+		}
+		else
+		{
+			xSemaphoreGive( shSemaphoreHandle );
+		}
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+	}
+	return lStatus;
+}
+uint8_t _udma_i2cm_write_addr_plus_reg16addr (uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t reg_addr) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_tx;
+	uint8_t lStatus = pdFALSE;
+
+	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		pi2cm_regs->tx_cfg_b.en = 0;
+		*pcmd++ = kI2cmCmdCfg;
+		*pcmd++ = aucclkdiv[1];
+		*pcmd++ = aucclkdiv[0];
+		*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
+		*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
+		*pcmd++ = i2cm_addr & 0xfe; 	// Clear R/WRbar bit from i2c device's address to indicate write
+		*pcmd++ = kI2cmCmdRpt;  // 2 byte register address
+		*pcmd++ = 2;
+		*pcmd++ = kI2cmCmdWr; 		// I2C CMD_WR
+		pi2cm_regs->tx_saddr = auccmd_tx;
+		pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA operation is completed
+		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+		{
+			//pi2cm_regs->tx_cfg_b.en = 0;
+			pcmd = auccmd_tx;
+			*pcmd++ = reg_addr & 0xff;
+			*pcmd++ = (reg_addr >> 8) & 0xff;
+			pi2cm_regs->tx_saddr = auccmd_tx;
+			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_tx);
+			pi2cm_regs->tx_cfg_b.en = 1;
+
+			// Block until UDMA operation is completed
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+
+			lStatus = pdTRUE;
+		}
+		else
+		{
+			xSemaphoreGive( shSemaphoreHandle );
+		}
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+	}
+	return lStatus;
+}
+
+
+uint8_t _udma_i2cm_read(uint8_t i2cm_id, uint8_t i2cm_addr, uint16_t read_len, uint8_t* read_buffer, bool more_follows) {
+	UdmaI2cm_t*					pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	uint8_t*					pcmd = auccmd_rx;
+	uint8_t lStatus = pdFALSE;
+
+	configASSERT(read_len < 256);
+
+	SemaphoreHandle_t shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+		if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+		{
+			pi2cm_regs->tx_cfg_b.en = 0;
+			*pcmd++ = kI2cmCmdCfg;
+			*pcmd++ = aucclkdiv[1];
+			*pcmd++ = aucclkdiv[0];
+			*pcmd++ = kI2cmCmdStart;		// Put Start transaction on I2C bus
+			*pcmd++ = kI2cmCmdWr;		// Write device's address (next byte)
+			*pcmd++ = i2cm_addr | 0x01;	// Device's address with read bit set
+			if (read_len > 1) {				// Do len-1 reads with ACK, and follow by 1 read with NACK
+				*pcmd++ = kI2cmCmdRpt;		// Tell controller to repeat the following command
+				*pcmd++ = (uint8_t)(read_len - 1);		// len-1 times
+				*pcmd++ = kI2cmCmdRdAck;		// command to repeat is read with ack
+			}
+			*pcmd++ = kI2cmCmdRdNack;	// Read last byte with NACK to indicate the end of the read
+
+			//
+			pi2cm_regs->rx_saddr = read_buffer;
+			pi2cm_regs->rx_size = read_len;
+			pi2cm_regs->rx_cfg_b.en = 1;
+
+			pi2cm_regs->tx_saddr = auccmd_rx;
+			pi2cm_regs->tx_size = (uint32_t)(pcmd - auccmd_rx);
+			pi2cm_regs->tx_cfg_b.en = 1;
+
+			// Block until UDMA operation is complete
+			shSemaphoreHandle = i2cm_semaphores_rx[i2cm_id];
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+
+			shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+
+			xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+			xSemaphoreGive( shSemaphoreHandle );
+
+			if (!more_follows) {
+				_udma_i2cm_send_stop(i2cm_id);
+			}
+			lStatus = pdTRUE;
+		}
+		else
+		{
+			xSemaphoreGive( shSemaphoreHandle );
+			lStatus = pdFALSE;
+		}
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+		lStatus = pdFALSE;
+	}
+	return lStatus;
+}
+
+static uint8_t auci2cm_stop_seq[] = {
+		kI2cmCmdStop,	kI2cmCmdWait, 0x0
+};
+
+uint8_t _udma_i2cm_send_stop(uint8_t i2cm_id) {
+	UdmaI2cm_t*			pi2cm_regs = (UdmaI2cm_t*)(UDMA_CH_ADDR_I2CM + i2cm_id * UDMA_CH_SIZE);
+	SemaphoreHandle_t 	shSemaphoreHandle = i2cm_semaphores_tx[i2cm_id];
+	uint8_t lStatus = pdFALSE;
+
+	if( xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS ) == pdTRUE )
+	{
+		pi2cm_regs->tx_saddr = auci2cm_stop_seq;
+		pi2cm_regs->tx_size = sizeof(auci2cm_stop_seq);
+		pi2cm_regs->tx_cfg_b.en = 1;
+
+		// Block until UDMA transaction is completed
+		xSemaphoreTake( shSemaphoreHandle, SEMAPHORE_WAIT_TIME_IN_MS );
+		xSemaphoreGive( shSemaphoreHandle );
+		lStatus = pdTRUE;
+	}
+	else
+	{
+		xSemaphoreGive( shSemaphoreHandle );
+	}
+	return lStatus;
+}

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_qspi_driver.c

@@ -0,0 +1,686 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_qspi_reg_defs.h"
+#include <drivers/include/udma_qspi_driver.h>
+
+
+
+
+SemaphoreHandle_t  qspim_semaphores_rx[N_QSPIM];
+SemaphoreHandle_t  qspim_semaphores_tx[N_QSPIM];
+SemaphoreHandle_t  qspim_semaphores_cmd[N_QSPIM];
+SemaphoreHandle_t  qspim_semaphores_eot[N_QSPIM];
+
+uint8_t aucclkdiv;
+static unsigned int isr_count;
+void spi_tx_isr() {
+	isr_count += 0x1;
+}
+void spi_rx_isr() {
+	isr_count += 0x100;
+}
+void spi_cmd_isr() {
+	isr_count += 0x10000;
+}
+void spi_eot_isr() {
+	isr_count += 0x1000000;
+}
+
+uint16_t udma_qspim_open (uint8_t qspim_id, uint32_t clk_freq) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaQspi_t*					pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t					clk_divisor;
+
+	/* See if already initialized */
+	if (qspim_semaphores_rx[qspim_id] != NULL || qspim_semaphores_tx[qspim_id] != NULL) {
+		return 1;
+	}
+	/* Enable reset and enable uart clock */
+	if( qspim_id == 0 )
+	{
+		pudma_ctrl->reg_rst |= ( UDMA_CTRL_QSPIM0_CLKEN ) ;
+		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM0_CLKEN);
+		pudma_ctrl->reg_cg |= (UDMA_CTRL_QSPIM0_CLKEN );
+	}
+	else if( qspim_id == 1 )
+	{
+#if(NEW_BIT_FILE == 1 )
+		pudma_ctrl->reg_rst |= ( UDMA_CTRL_QSPIM1_CLKEN ) ;
+		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM1_CLKEN);
+		pudma_ctrl->reg_cg |= (UDMA_CTRL_QSPIM1_CLKEN );
+#endif
+	}
+
+
+	/* Set semaphore */
+	SemaphoreHandle_t shSemaphoreHandle;		// FreeRTOS.h has a define for xSemaphoreHandle, so can't use that
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	qspim_semaphores_rx[qspim_id] = shSemaphoreHandle;
+
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	qspim_semaphores_tx[qspim_id] = shSemaphoreHandle;
+
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	qspim_semaphores_cmd[qspim_id] = shSemaphoreHandle;
+
+	shSemaphoreHandle = xSemaphoreCreateBinary();
+	configASSERT(shSemaphoreHandle);
+	xSemaphoreGive(shSemaphoreHandle);
+	qspim_semaphores_eot[qspim_id] = shSemaphoreHandle;
+
+	/* Set handlers. */
+	isr_count = 0;
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_RX(qspim_id), spi_rx_isr, qspim_semaphores_rx[qspim_id]);
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_TX(qspim_id), spi_tx_isr, qspim_semaphores_tx[qspim_id]);
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_CMD(qspim_id), spi_cmd_isr, qspim_semaphores_cmd[qspim_id]);
+	pi_fc_event_handler_set(SOC_EVENT_UDMA_SPIM_EOT(qspim_id), spi_eot_isr, qspim_semaphores_eot[qspim_id]);
+
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_RX(qspim_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_TX(qspim_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_CMD(qspim_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_SPIM_EOT(qspim_id));
+
+	/* configure */
+	aucclkdiv = 5000000/clk_freq;
+
+	return 0;
+}
+
+uint16_t udma_qspim_control(uint8_t qspim_id, udma_qspim_control_type_t control_type, void* pparam) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaQspi_t*					pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kQSPImReset:
+		if( qspim_id == 0 )
+		{
+			pudma_ctrl->reg_rst |= (UDMA_CTRL_QSPIM0_CLKEN);
+			pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM0_CLKEN);
+		}
+		else if( qspim_id == 1 )
+		{
+#if(NEW_BIT_FILE == 1 )
+			pudma_ctrl->reg_rst |= (UDMA_CTRL_QSPIM1_CLKEN);
+			pudma_ctrl->reg_rst &= ~(UDMA_CTRL_QSPIM1_CLKEN);
+#endif
+		}
+		break;
+	default:
+		configASSERT(0);
+	}
+	return 0;
+}
+
+static uint32_t auccmd[16];
+
+void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+
+		configASSERT(read_len < 256);
+
+		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;  //cs 1
+		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->rx_saddr = read_buffer;
+		pqspim_regs->rx_size = read_len;
+		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		// Block until UDMA operation is complete
+		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+}
+
+
+void udma_qspim_write (uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t *write_data) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint32_t tmp_size;
+		configASSERT(write_len < 256);
+
+		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.clr = 1;
+		pqspim_regs->tx_cfg_b.clr = 1;
+		pqspim_regs->cmd_cfg_b.clr = 1;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_TxData | 0x0470000 | write_len -1;
+		*pcmd++ = kSPIm_EOT | 1; // generate event
+
+
+		pqspim_regs->tx_saddr = write_data;
+		pqspim_regs->tx_size = write_len;
+		pqspim_regs->tx_cfg_b.datasize = 2;
+		pqspim_regs->tx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+
+
+
+
+		// Block until UDMA operation is complete
+		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+}
+
+uint32_t udma_flash_reset_enable(uint8_t qspim_id, uint8_t cs)
+{
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint32_t result = 0;
+
+	udma_qspim_control(qspim_id, (udma_qspim_control_type_t) kQSPImReset , (void*) 0);
+
+	pqspim_regs->cmd_cfg_b.en = 0;
+
+	pqspim_regs->cmd_cfg_b.clr = 1;
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70066); // reset enable command
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	return result;
+}
+
+uint32_t udma_flash_reset_memory(uint8_t qspim_id, uint8_t cs)
+{
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint32_t result = 0;
+
+	udma_qspim_control(qspim_id, (udma_qspim_control_type_t) kQSPImReset , (void*) 0);
+
+	pqspim_regs->cmd_cfg_b.en = 0;
+
+	pqspim_regs->cmd_cfg_b.clr = 1;
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70099); // reset memory command
+
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	return result;
+}
+
+static uint8_t rx_data[16];
+uint32_t udma_flash_readid(uint8_t qspim_id, uint8_t cs) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint32_t result = 0;
+
+	pqspim_regs->rx_cfg_b.en = 0;
+	pqspim_regs->tx_cfg_b.en = 0;
+	pqspim_regs->cmd_cfg_b.en = 0;
+
+	pqspim_regs->rx_cfg_b.clr = 1;
+	pqspim_regs->tx_cfg_b.clr = 1;
+	pqspim_regs->cmd_cfg_b.clr = 1;
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x7009f); // readid command
+	*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->rx_saddr = &rx_data;
+	pqspim_regs->rx_size = 4;
+	pqspim_regs->rx_cfg_b.en = 1;
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	while (pqspim_regs->rx_size != 0) {}
+
+	result = *(uint32_t *) rx_data;
+	return result;
+}
+
+uint8_t udma_flash_erase(uint8_t qspim_id, uint8_t cs, uint32_t addr, uint8_t cmd) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	union { uint32_t w; uint8_t b[4]; } result;
+	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+    switch (cmd) {
+    case 0: cmd = 0x20;break;  // subsector (4k erase)
+    case 1: cmd = 0xd8;break; // sector erase (64K)
+    case 2: cmd == 0xc7;break; // bulk erase
+    default: configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+    	return 0xff;
+
+    }
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_SendCmd | (0x70006) ; // write enable command
+//		*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+//		pqspim_regs->rx_saddr = &result.w;
+//		pqspim_regs->rx_size = 0;
+//		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+		pcmd = auccmd;
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_SendCmd | (0x70000) | cmd; // write enable command
+		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((addr >> 8) & 0xffff);
+		*pcmd++ = kSPIm_SendCmd | (0x70000) | (addr & 0xff);
+//		*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		result.b[0] = 0;
+		while ((result.b[0] & 0x80) == 0x0) {
+
+			pqspim_regs->rx_cfg_b.en = 0;
+			pqspim_regs->tx_cfg_b.en = 0;
+			pqspim_regs->cmd_cfg_b.en = 0;
+			pcmd = auccmd;
+			*pcmd++ = kSPIm_Cfg | aucclkdiv;
+			*pcmd++ = kSPIm_SOT | cs;
+			*pcmd++ = kSPIm_SendCmd | (0x70070); // read flag register
+			*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
+			*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+			pqspim_regs->rx_saddr = &result.w;
+			pqspim_regs->rx_size = 4;
+			pqspim_regs->rx_cfg_b.en = 1;
+
+			pqspim_regs->cmd_saddr = auccmd;
+			pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+			pqspim_regs->cmd_cfg_b.en = 1;
+			configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		}
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+		pcmd = auccmd;
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_SendCmd | (0x70004); // write disable
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+		return result.b[0];
+}
+
+void udma_flash_read(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+
+	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+	shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT;
+		*pcmd++ = kSPIm_SendCmd | (0x70003);  // read command
+		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((flash_addr >> 8) & 0xffff);
+		*pcmd++ = kSPIm_SendCmd | (0x70000) | (flash_addr & 0xff);
+		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->rx_saddr = l2addr;
+		pqspim_regs->rx_size = read_len;
+		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+
+}
+void udma_flash_read_quad(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,uint8_t *l2addr,uint16_t read_len ) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+
+	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+	shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT;
+		//*pcmd++ = kSPIm_SendCmd | (0x7000B);  // read command
+		*pcmd++ = kSPIm_SendCmd | (0x7006B);
+		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((flash_addr >> 8) & 0xffff);
+		*pcmd++ = kSPIm_SendCmd | (0x70000) | (flash_addr & 0xff);
+		//*pcmd++ = kSPIm_Dummy | 0x001F0000;
+		*pcmd++ = kSPIm_Dummy | 0x00070000;
+		//*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_RxData | (0x08470000 | (read_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->rx_saddr = l2addr;
+		pqspim_regs->rx_size = read_len;
+		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+
+}
+void udma_flash_write(uint8_t qspim_id, uint8_t cs, uint32_t flash_addr,
+		uint8_t *l2addr, uint16_t write_len ) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+
+	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+	shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+	pqspim_regs->rx_cfg_b.en = 0;
+	pqspim_regs->tx_cfg_b.en = 0;
+	pqspim_regs->cmd_cfg_b.en = 0;
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70006) ; // write enable command
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		pcmd = auccmd;
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT;
+		*pcmd++ = kSPIm_SendCmd | (0x70002);  // program command
+		*pcmd++ = kSPIm_SendCmd | (0xf0000) | ((flash_addr >> 8) & 0xffff);
+		*pcmd++ = kSPIm_SendCmd | (0x70000) | (flash_addr & 0xff);
+		*pcmd++ = kSPIm_TxData | (0x00470000 | (write_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->tx_saddr = l2addr;
+		pqspim_regs->tx_size = write_len;
+		pqspim_regs->tx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+
+		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+uint8_t test;
+		test = 1;
+				while ((test & 0x3) == 0x1) {
+
+					pqspim_regs->rx_cfg_b.en = 0;
+					pqspim_regs->tx_cfg_b.en = 0;
+					pqspim_regs->cmd_cfg_b.en = 0;
+					pcmd = auccmd;
+					*pcmd++ = kSPIm_Cfg | aucclkdiv;
+					*pcmd++ = kSPIm_SOT | cs;
+					*pcmd++ = kSPIm_SendCmd | (0x70005); // read status register
+					*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
+					*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+					pqspim_regs->rx_saddr = l2addr;
+					pqspim_regs->rx_size = 4;
+					pqspim_regs->rx_cfg_b.en = 1;
+
+					pqspim_regs->cmd_saddr = auccmd;
+					pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+					pqspim_regs->cmd_cfg_b.en = 1;
+					configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+					test = l2addr[0] & 0xff;
+				}
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		pcmd = auccmd;
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_SendCmd | (0x70004) ; // write disable command
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+}
+
+/*
+ * https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/QSPI-flash-programming-how-to-activate-qspi-in-quad-mode/td-p/871253
+ * to enable the quad mode
+1. send ENTER QUAD INPUT/OUTPUT MODE command 0x35h
+2. send write enable cmd 0x06
+3. to write into enhanced volatile configuration register - send  0x61 command.
+4. 0x7F is written in the above register to activate in quad mode
+5. poll the configuration register i.e read the enhanced volatile config register command is 0x65 and wait untill it
+becomes 0X7F
+6. then configure the controller in quad mode and send the multiple read id code 0XAF to read the ID code on all the four lines.
+ */
+void udma_flash_enterQuadIOMode(uint8_t qspim_id, uint8_t cs )
+{
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint8_t test = 0;
+	uint8_t l2addr[4] = {0};
+
+	SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	//shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+	//configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+	shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+	pqspim_regs->rx_cfg_b.en = 0;
+	pqspim_regs->tx_cfg_b.en = 0;
+	pqspim_regs->cmd_cfg_b.en = 0;
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70035) ; // Enter QUAD command
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70006) ; // write enable command
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70061) ; // write Enhanced volatile register 0x61
+	*pcmd++ = kSPIm_SendCmd | (0x7007F) ;
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+	while ((test & 0xFF) != 0x7F) {
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+		pcmd = auccmd;
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_SendCmd | (0x70065); // read status register
+		*pcmd++ = kSPIm_RxData | (0x00470000 | (4-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->rx_saddr = l2addr;
+		pqspim_regs->rx_size = 4;
+		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		test = l2addr[0] & 0xff;
+	}
+	pqspim_regs->rx_cfg_b.en = 0;
+	pqspim_regs->tx_cfg_b.en = 0;
+	pqspim_regs->cmd_cfg_b.en = 0;
+
+	pcmd = auccmd;
+	*pcmd++ = kSPIm_Cfg | aucclkdiv;
+	*pcmd++ = kSPIm_SOT | cs;
+	*pcmd++ = kSPIm_SendCmd | (0x70004) ; // write disable command
+	*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+	pqspim_regs->cmd_saddr = auccmd;
+	pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+	pqspim_regs->cmd_cfg_b.en = 1;
+
+	shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+	configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+	configASSERT( xSemaphoreGive( shSemaphoreHandle) == pdTRUE );
+}
+

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_sdio_driver.c

@@ -0,0 +1,266 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdint.h>
+#include <stdbool.h>
+//#include "FreeRTOS.h"
+#include "semphr.h"
+
+#include "target/core-v-mcu/include/core-v-mcu-config.h"
+#include "hal/include/hal_fc_event.h"
+#include "hal/include/hal_udma_ctrl_reg_defs.h"
+#include "hal/include/hal_udma_sdio_reg_defs.h"
+#include <drivers/include/udma_sdio_driver.h>
+
+#define BLOCK_SIZE 512
+
+uint16_t udma_sdio_open (uint8_t sdio_id)
+{
+	int i = 0;
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaSdio_t*					psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+
+	psdio_regs->clk_div_b.clk_div = 7;//5;
+	psdio_regs->clk_div_b.valid = 1;
+	//Restore pin muxes
+	for(i=0; i<6; i++ )
+	{
+		//set pin muxes to sdio functionality
+		 hal_setpinmux(37+i, 0);
+	}
+	return 0;
+}
+
+uint16_t udma_sdio_control(uint8_t sdio_id, udma_sdio_control_type_t control_type, void* pparam) {
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+	UdmaSdio_t*					psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kSDIOmReset:
+		pudma_ctrl->reg_rst |= (UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+		pudma_ctrl->reg_rst &= ~(UDMA_CTRL_SDIO0_CLKEN << sdio_id);
+		break;
+	default:
+		configASSERT(0);
+	}
+	return 0;
+}
+
+void udma_sdio_clearDataSetup(uint8_t sdio_id)
+{
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+	psdio_regs->data_setup = 0x00000000;
+}
+uint8_t udma_sdio_writeBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
+{
+	uint8_t lSts = 0;
+	uint32_t lData = 0;
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	psdio_regs->tx_cfg_b.clr = 1;
+	psdio_regs->tx_cfg_b.en = 0;
+	psdio_regs->tx_cfg_b.datasize = 2;
+
+	psdio_regs->tx_saddr = aBuf;
+	psdio_regs->tx_size = aBufLen;
+
+	lData = 0;
+	psdio_regs->data_setup = 0x00000000;
+	lData |= 1 << 0;	//Data Enable - Enable data transfer for current command
+	lData |= 0 << 1;	//RWN: Set transfer direction 1 read; 0 write
+	lData |= 1 << 2;	//QUAD mode: Use quad mode.
+	lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
+	lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
+
+	psdio_regs->data_setup = lData;
+
+	psdio_regs->tx_cfg_b.en = 1;
+}
+
+uint8_t udma_sdio_readBlockData(uint8_t sdio_id, uint32_t aNumOfBlocks, uint32_t *aBuf, uint32_t aBufLen)
+{
+	uint8_t lSts = 0;
+	uint32_t lData = 0;
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	psdio_regs->rx_cfg_b.clr = 1;
+	psdio_regs->rx_cfg_b.en = 0;
+	psdio_regs->rx_cfg_b.datasize = 2;
+
+	psdio_regs->rx_saddr = aBuf;
+	psdio_regs->rx_size = aBufLen;
+
+	lData = 0;
+	psdio_regs->data_setup = 0x00000000;
+	lData |= 1 << 0;	//Data Enable - Enable data transfer for current command
+	lData |= 1 << 1;	//RWN: Set transfer direction 1 read; 0 write
+	lData |= 1 << 2;	//QUAD mode: Use quad mode.
+	lData |= ( aNumOfBlocks - 1 ) << 8; //Number of blocks
+	lData |= ( BLOCK_SIZE - 1 ) << 16; //Block size
+
+	psdio_regs->data_setup = lData;
+
+	psdio_regs->rx_cfg_b.en = 1;
+
+}
+
+uint8_t udma_sdio_sendCmd(uint8_t sdio_id, uint8_t aCmdOpCode, uint8_t aRspType, uint32_t aCmdArgument, uint32_t *aResponseBuf)
+{
+	uint8_t lSts = 0;
+	uint32_t lData = 0;
+	uint32_t lLoopCounter = 0;
+	UdmaSdio_t *psdio_regs = (UdmaSdio_t*)(UDMA_CH_ADDR_SDIO + sdio_id * UDMA_CH_SIZE);
+
+	lData |= (aRspType & REG_CMD_OP_CMD_RSP_TYPE_MASK ) << REG_CMD_OP_CMD_RSP_TYPE_LSB;
+	lData |= ( aCmdOpCode & REG_CMD_OP_CMD_OP_MASK ) << REG_CMD_OP_CMD_OP_LSB;
+	psdio_regs->cmd_op = lData;
+
+	//psdio_regs->cmd_op_b.cmd_op = ( aCmdOpCode & 0x3F );
+	//psdio_regs->cmd_op_b.cmd_rsp_type = ( aRspType & 0x07 );
+	psdio_regs->cmd_arg = aCmdArgument;
+
+	psdio_regs->start = 1;
+
+	while( ( ( psdio_regs->status & ( REG_STATUS_EOT_MASK << REG_STATUS_EOT_LSB ) ) >> REG_STATUS_EOT_LSB ) == 0 )
+	{
+		if( ( ( psdio_regs->status & ( REG_STATUS_ERROR_MASK << REG_STATUS_ERROR_LSB ) ) >> REG_STATUS_ERROR_LSB ) == 1 )
+		{
+			lSts = (psdio_regs->status & ( REG_STATUS_CMD_ERR_STATUS_MASK << REG_STATUS_CMD_ERR_STATUS_LSB ) ) >> REG_STATUS_CMD_ERR_STATUS_LSB;
+			break;
+		}
+		else
+		{
+			if(++lLoopCounter >= 0x00010000 )
+			{
+				lSts = 5;
+				break;
+			}
+		}
+	}
+
+	psdio_regs->status_b.eot = 1;	//Write 1 to EOT bit to clear it.
+
+
+	if( aResponseBuf )
+	{
+		aResponseBuf[0] = psdio_regs->rsp0;
+		aResponseBuf[1] = psdio_regs->rsp1;
+		aResponseBuf[2] = psdio_regs->rsp2;
+		aResponseBuf[3] = psdio_regs->rsp3;
+
+	}
+	return lSts;
+}
+#if 0
+static uint32_t auccmd[16];
+
+void udma_qspim_read(uint8_t qspim_id, uint8_t cs, uint16_t read_len, uint8_t* read_buffer) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+
+		configASSERT(read_len < 256);
+
+		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.en = 0;
+		pqspim_regs->tx_cfg_b.en = 0;
+		pqspim_regs->cmd_cfg_b.en = 0;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;  //cs 1
+		*pcmd++ = kSPIm_RxData | (0x00470000 | (read_len-1)) ; // 4 words recieved
+		*pcmd++ = kSPIm_EOT  | 1; // generate event
+
+		pqspim_regs->rx_saddr = read_buffer;
+		pqspim_regs->rx_size = read_len;
+		pqspim_regs->rx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+		// Block until UDMA operation is complete
+		shSemaphoreHandle = qspim_semaphores_rx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+}
+
+
+void udma_qspim_write (uint8_t qspim_id, uint8_t cs, uint16_t write_len, uint8_t *write_data) {
+	UdmaQspi_t*	pqspim_regs = (UdmaQspi_t*)(UDMA_CH_ADDR_QSPIM + qspim_id * UDMA_CH_SIZE);
+	uint32_t*	pcmd = auccmd;
+	uint32_t tmp_size;
+		configASSERT(write_len < 256);
+
+		SemaphoreHandle_t shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+
+		pqspim_regs->rx_cfg_b.clr = 1;
+		pqspim_regs->tx_cfg_b.clr = 1;
+		pqspim_regs->cmd_cfg_b.clr = 1;
+
+		*pcmd++ = kSPIm_Cfg | aucclkdiv;
+		*pcmd++ = kSPIm_SOT | cs;
+		*pcmd++ = kSPIm_TxData | 0x0470000 | write_len -1;
+		*pcmd++ = kSPIm_EOT | 1; // generate event
+
+
+		pqspim_regs->tx_saddr = write_data;
+		pqspim_regs->tx_size = write_len-1;
+		pqspim_regs->tx_cfg_b.datasize = 2;
+		pqspim_regs->tx_cfg_b.en = 1;
+
+		pqspim_regs->cmd_saddr = auccmd;
+		pqspim_regs->cmd_size = (uint32_t)(pcmd - auccmd)*4;
+		pqspim_regs->cmd_cfg_b.en = 1;
+
+
+
+
+
+		// Block until UDMA operation is complete
+		shSemaphoreHandle = qspim_semaphores_tx[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_cmd[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+		shSemaphoreHandle = qspim_semaphores_eot[qspim_id];
+		configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+		configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+}
+
+#endif

bsp/core-v-mcu/Libraries/core_v_drivers/source/udma_uart_driver.c

@@ -0,0 +1,217 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "core-v-mcu-config.h"
+#include <string.h>
+#include "hal_fc_event.h"
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_uart_reg_defs.h"
+#include <drv_usart.h>
+#include <stdint.h>
+//#include "FreeRTOS.h"
+//#include "semphr.h"
+#include "core-v-mcu-config.h"
+#include "udma_uart_driver.h"
+#include "rtthread.h"
+//#include <ringbuffer.h>
+//#include "ipc/ringbuffer.h" 
+#include "rtdevice.h" 
+#define  unuse_freertos_in_uart
+
+
+//SemaphoreHandle_t  uart_semaphores_rx[N_UART];
+//SemaphoreHandle_t  uart_semaphores_tx[N_UART];
+char u1buffer[128], u0buffer[128];
+int u1rdptr, u1wrptr, u0rdptr,u0wrptr;
+UdmaUart_t *puart0 = (UdmaUart_t*)(UDMA_CH_ADDR_UART);
+UdmaUart_t *puart1 = (UdmaUart_t*)(UDMA_CH_ADDR_UART + UDMA_CH_SIZE);
+
+uint16_t outdata(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->status_b.tx_busy) {  // ToDo: Why is this necessary?  Thought the semaphore should have protected
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1; //enable the transfer
+
+	return 0;
+}
+
+// ringbuffer  
+#define UART_RX_BUFFER_LEN 16
+rt_uint8_t uart_rxbuffer[UART_RX_BUFFER_LEN]={0};
+struct rt_ringbuffer uart_rxTCB;
+struct rt_semaphore  shell_rx_semaphore;
+
+// extern struct ch32_uart_config uart_config[];
+// extern void uart_isr(struct rt_serial_device *serial);
+// extern struct ch32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] ;
+// extern UART1_INDEX;
+char n_data[]="\r\n";
+// void uart_rx_isr (void *id){
+// 	rt_interrupt_enter();
+// 	if (id == 6) {
+// 		while (*(int*)0x1a102130) {
+// 			u1buffer[u1wrptr++] = puart1->data_b.rx_data & 0xff;
+// 			u1wrptr &= 0x7f;
+// 		}
+// 	}
+// 	if (id == 2) {
+// 		while (puart0->valid) {
+// 			//u0buffer[u0wrptr++] = puart0->data_b.rx_data & 0xff;
+// 			//u0wrptr &= 0x7f;
+// 			//outdata(0,sizeof(u0buffer),u0buffer);
+// 			//outdata(0,sizeof(n_data),n_data);
+// 			//rt_ringbuffer_putchar(&uart_rxTCB,puart0->data_b.rx_data & 0xff);
+// 			//u0wrptr=0;
+// 			uart_isr(&(uart_obj[UART1_INDEX].serial));
+// 		}
+// 		//rt_sem_release(&shell_rx_semaphore);
+// 	}
+// 	rt_interrupt_leave();
+// }
+uint8_t uart_getchar (uint8_t id) {
+	uint8_t retval;
+	if (id == 1) {
+		while (u1rdptr == u1wrptr) ;
+		retval = u1buffer[u1rdptr++];
+		u1rdptr &= 0x7f;
+	}
+	if (id == 0) {
+		while (u0rdptr == u0wrptr) ;
+		retval = u0buffer[u0rdptr++];
+		u0rdptr &= 0x7f;
+	}
+	return retval;
+}
+
+void uart_rx_isr (void *id);
+uint16_t udma_uart_open (uint8_t uart_id, uint32_t xbaudrate) {
+	UdmaUart_t*				puart;
+	volatile UdmaCtrl_t*		pudma_ctrl = (UdmaCtrl_t*)UDMA_CH_ADDR_CTRL;
+
+	/* See if already initialized */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_UART0_CLKEN << uart_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_UART0_CLKEN << uart_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_UART0_CLKEN << uart_id);
+
+
+	user_pi_fc_event_handler_set(SOC_EVENT_UART_RX(uart_id), uart_rx_isr);
+
+
+	/* Enable SOC events propagation to FC. */
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UART_RX(uart_id));
+	hal_soc_eu_set_fc_mask(SOC_EVENT_UDMA_UART_TX(uart_id));
+
+	/* configure */
+	puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+	puart->uart_setup_b.div = (uint16_t)(5000000/xbaudrate);
+	puart->uart_setup_b.bits = 3; // 8-bits
+
+	puart->irq_en_b.rx_irq_en = 1;
+	puart->uart_setup_b.en_tx = 1;
+	puart->uart_setup_b.en_rx = 1;
+	puart->uart_setup_b.rx_clean_fifo = 1;
+	
+	if (uart_id == 1) {
+		 u1rdptr = 0;
+	 	 u1wrptr = 0;
+	}
+	if (uart_id == 0) {
+		 u0rdptr = 0;
+	 	 u0wrptr = 0;
+	}
+
+	return 0;
+}
+
+uint16_t udma_uart_writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	// SemaphoreHandle_t shSemaphoreHandle = uart_semaphores_tx[uart_id];
+	// if( xSemaphoreTake( shSemaphoreHandle, 1000000 ) != pdTRUE ) {
+	// 	return 1;
+	// }
+
+	while (puart->status_b.tx_busy) {  // ToDo: Why is this necessary?  Thought the semaphore should have protected
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1; //enable the transfer
+
+	return 0;
+}
+
+uint16_t udma_uart_read(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer) {
+	uint16_t ret = 0;
+	uint8_t last_char = 0;
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+
+	while ( (ret < (read_len - 2)) && (last_char != 0xd)) {
+		if (puart->valid_b.rx_data_valid == 1) {
+			last_char = (uint8_t)(puart->data_b.rx_data & 0xff);
+			if (last_char == 0xd)  // if cr add
+				read_buffer[ret++] = 0xa;  // linefeed
+			read_buffer[ret++] = last_char;
+		}
+	}
+	read_buffer[ret] = '\0';
+	return ret--;
+}
+
+uint16_t udma_uart_readraw(uint8_t uart_id, uint16_t read_len, uint8_t* read_buffer) {
+	uint16_t ret = 0;
+	uint8_t last_char = 0;
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while ( ret < read_len ) {
+		if (puart->valid_b.rx_data_valid == 1) {
+			last_char = (uint8_t)(puart->data_b.rx_data & 0xff);
+			read_buffer[ret++] = last_char;
+		}
+	}
+	return ret--;
+}
+
+uint8_t udma_uart_getchar(uint8_t uart_id) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->valid_b.rx_data_valid == 0) {
+	}
+	return (puart->data_b.rx_data & 0xff);
+}
+
+uint16_t udma_uart_control(uint8_t uart_id, udma_uart_control_type_t control_type, void* pparam) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	switch(control_type) {
+	case kUartDataValid:
+		if (uart_id == 0)
+			return !(u0rdptr == u0wrptr);
+		if (uart_id == 1)
+			return !(u1rdptr == u1wrptr);
+		return puart->valid_b.rx_data_valid;
+	default:
+		return 0xFFFF;
+	}
+	return 0;
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/SConscript

@@ -0,0 +1,31 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+core_v_hal/source/hal_apb_i2cs.c
+core_v_hal/source/hal_fc_event.c
+core_v_hal/source/hal_fll.c
+core_v_hal/source/hal_fll_pi.c
+core_v_hal/source/hal_gpio.c
+core_v_hal/source/hal_gpio_pulp.c
+core_v_hal/source/hal_irq.c
+core_v_hal/source/hal_pinmux.c
+core_v_hal/source/hal_pinmux1.c
+core_v_hal/source/hal_soc_eu.c
+core_v_hal/source/hal_timer_irq.c
+bmsis/core-v-mcu/source/core-v-mcu.c
+bmsis/core-v-mcu/source/crt0.S
+bmsis/core-v-mcu/source/vectors.S
+""")
+
+path = [
+	cwd + '/bmsis/core-v-mcu/include',
+    cwd + '/core_v_hal/include']
+
+group = DefineGroup('core_v_hal_lib', src, depend = [''], CPPPATH = path)
+
+Return('group')

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/bits.h

@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2011-2014, Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __BITS_H
+#define __BITS_H
+
+#include <stdbool.h>
+
+/* Helper to pass a int as a pointer or vice-versa. */
+#define POINTER_TO_UINT(x) ((uintptr_t) (x))
+#define UINT_TO_POINTER(x) ((void *) (uintptr_t) (x))
+#define POINTER_TO_INT(x)  ((intptr_t) (x))
+#define INT_TO_POINTER(x)  ((void *) (intptr_t) (x))
+
+#if !(defined (__CHAR_BIT__) && defined (__SIZEOF_LONG__))
+#	error Missing required predefined macros for BITS_PER_LONG calculation
+#endif
+
+#define BITS_PER_LONG	(__CHAR_BIT__ * __SIZEOF_LONG__)
+/* Create a contiguous bitmask starting at bit position @l and ending at
+ * position @h.
+ */
+#define GENMASK(h, l) \
+	(((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
+
+/* KB, MB, GB */
+#define KB(x) ((x) << 10)
+#define MB(x) (KB(x) << 10)
+#define GB(x) (MB(x) << 10)
+
+/* KHZ, MHZ */
+#define KHZ(x) ((x) * 1000)
+#define MHZ(x) (KHZ(x) * 1000)
+
+#ifndef BIT
+#if defined(_ASMLANGUAGE)
+#define BIT(n)  (1 << (n))
+#else
+#define BIT(n)  (1UL << (n))
+#endif
+#endif
+
+/**
+ * @brief Macro sets or clears bit depending on boolean value
+ *
+ * @param var Variable to be altered
+ * @param bit Bit number
+ * @param set Value 0 clears bit, any other value sets bit
+ */
+#define WRITE_BIT(var, bit, set) \
+	((var) = (set) ? ((var) | BIT(bit)) : ((var) & ~BIT(bit)))
+
+#define BIT_MASK(n) (BIT(n) - 1)
+
+#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-config.h

@@ -0,0 +1,284 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __CORE_V_MCU_CONFIG_H_
+#define __CORE_V_MCU_CONFIG_H_
+#define NEW_BIT_FILE	1
+#define OLD_BIT_FILE	0
+
+#if (NEW_BIT_FILE == 1 )
+#define BUILD_DATE 0x20220127
+#define BUILD_TIME 0x00215431
+
+#define FAKE_PLL		0
+#define PERCEPTIA_PLL	1
+//  SOC options
+#define N_IO                 48
+#define N_SYSIO              3
+#define N_GPIO               32  
+#define N_APBIO              51
+#define NBIT_PADCFG          6
+#define NBIT_PADMUX          2
+#define N_UART               2
+#define N_QSPIM              2      // two QSPI  master 
+#define N_I2CM               2          // two I2C master  
+#define N_I2SC               0
+#define N_CSI2               0
+#define N_HYPER              0
+#define N_SDIO               1
+#define N_CAM                1
+#define N_JTAG               0
+#define N_MRAM               0
+#define N_FILTER             1
+#define N_FPGA               0
+#define N_EXT_PER            0
+#define N_EFPGA_TCDM_PORTS   4
+#define N_FPGAIO             43
+#define N_EFPGA_EVENTS       16
+
+//  UDMA configuration information
+#define UDMA_START_ADDR         0x1A102000
+#define UDMA_CH_SIZE            (0x80)
+//  peripheral channel definitions
+#define UDMA_CH_ADDR_CTRL       (0x1A102000)
+#define UDMA_CH_ADDR_UART       (0x1A102000 + 1 * 0x80)
+#define UDMA_UART_ID(id)        (0 + id)
+#define UDMA_CH_ADDR_UART0      (0x1A102000 + 1 * 0x80)
+#define UDMA_CH_ADDR_UART1      (0x1A102000 + 2 * 0x80)
+#define UDMA_CH_ADDR_QSPIM      (0x1A102000 + 3 * 0x80)
+#define UDMA_QSPIM_ID(id)       (2 + id)
+#define UDMA_CH_ADDR_QSPIM0     (0x1A102000 + 3 * 0x80)
+#define UDMA_CH_ADDR_QSPIM1     (0x1A102000 + 4 * 0x80)
+#define UDMA_CH_ADDR_I2CM       (0x1A102000 + 5 * 0x80)
+#define UDMA_I2CM_ID(id)        (4 + id)
+#define UDMA_CH_ADDR_I2CM0      (0x1A102000 + 5 * 0x80)
+#define UDMA_CH_ADDR_I2CM1      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_I2SC       (0x1A102000 + 7 * 0x80)
+#define UDMA_I2SC_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_I2SC0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_CSI2       (0x1A102000 + 7 * 0x80)
+#define UDMA_CSI2_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_CSI20      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_HYPER      (0x1A102000 + 7 * 0x80)
+#define UDMA_HYPER_ID(id)       (6 + id)
+#define UDMA_CH_ADDR_HYPER0     (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_SDIO       (0x1A102000 + 7 * 0x80)
+#define UDMA_SDIO_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_SDIO0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_CAM        (0x1A102000 + 8 * 0x80)
+#define UDMA_CAM_ID(id)         (7 + id)
+#define UDMA_CH_ADDR_CAM0       (0x1A102000 + 8 * 0x80)
+#define UDMA_CH_ADDR_JTAG       (0x1A102000 + 9 * 0x80)
+#define UDMA_JTAG_ID(id)        (8 + id)
+#define UDMA_CH_ADDR_JTAG0      (0x1A102000 + 9 * 0x80)
+#define UDMA_CH_ADDR_MRAM       (0x1A102000 + 9 * 0x80)
+#define UDMA_MRAM_ID(id)        (8 + id)
+#define UDMA_CH_ADDR_MRAM0      (0x1A102000 + 9 * 0x80)
+#define UDMA_CH_ADDR_FILTER     (0x1A102000 + 9 * 0x80)
+#define UDMA_FILTER_ID(id)      (8 + id)
+#define UDMA_CH_ADDR_FILTER0    (0x1A102000 + 9 * 0x80)
+#define UDMA_CH_ADDR_FPGA       (0x1A102000 + 10 * 0x80)
+#define UDMA_FPGA_ID(id)        (9 + id)
+#define UDMA_CH_ADDR_FPGA0      (0x1A102000 + 10 * 0x80)
+#define UDMA_CH_ADDR_EXT_PER    (0x1A102000 + 10 * 0x80)
+#define UDMA_EXT_PER_ID(id)     (9 + id)
+#define UDMA_CH_ADDR_EXT_PER0   (0x1A102000 + 10 * 0x80)
+
+//  Peripheral clock enable masks
+#define UDMA_CTRL_UART0_CLKEN      (1 << 0)
+#define UDMA_CTRL_UART1_CLKEN      (1 << 1)
+#define UDMA_CTRL_QSPIM0_CLKEN     (1 << 2)
+#define UDMA_CTRL_QSPIM1_CLKEN     (1 << 3)
+#define UDMA_CTRL_I2CM0_CLKEN      (1 << 4)
+#define UDMA_CTRL_I2CM1_CLKEN      (1 << 5)
+#define UDMA_CTRL_I2SC0_CLKEN      (1 << 6)
+#define UDMA_CTRL_CSI20_CLKEN      (1 << 6)
+#define UDMA_CTRL_HYPER0_CLKEN     (1 << 6)
+#define UDMA_CTRL_SDIO0_CLKEN      (1 << 6)
+#define UDMA_CTRL_CAM0_CLKEN       (1 << 7)
+#define UDMA_CTRL_JTAG0_CLKEN      (1 << 8)
+#define UDMA_CTRL_MRAM0_CLKEN      (1 << 8)
+#define UDMA_CTRL_FILTER0_CLKEN    (1 << 8)
+#define UDMA_CTRL_FPGA0_CLKEN      (1 << 9)
+#define UDMA_CTRL_EXT_PER0_CLKEN   (1 << 9)
+
+//  FLL configuration information
+#define FLL1_START_ADDR 0x1A100000
+
+#define FLL2_START_ADDR 0x1A100020
+
+#define FLL3_START_ADDR 0x1A100040
+
+
+//  GPIO configuration information
+#define GPIO_START_ADDR 0x1A101000
+
+#define SOC_EVENT_GEN_START_ADDR 0x1A106000
+//  I2C Slave configuration information
+#define I2CS_START_ADDR 0x1A107000
+
+//  EFPGAIO configuration information
+#define EFPGAIO_START_ADDR 0x1A300000
+
+//  SOC controller configuration information
+#define SOC_CTRL_START_ADDR 0x1A104000
+
+//  Event Unit (Interrupts) configuration information
+#define EU_START_ADDR 0x1A109000
+
+//  Timer configuration information
+#define TIMER_START_ADDR 0x1A10B000
+
+//  AdvTimer configuration information
+#define ADV_TIMER_START_ADDR 0x1A105000
+
+//  EFPGA configuration information (FCB)
+#define EFPGA_CONFIG_START_ADDR 0x1A200000
+
+#elif (OLD_BIT_FILE == 1)
+
+#define BUILD_DATE 0x20210623
+#define BUILD_TIME 0x00111431
+
+#define FAKE_PLL		0
+#define PERCEPTIA_PLL	1
+
+//  SOC options
+#define N_IO                 48
+#define N_SYSIO              3
+#define N_GPIO               32
+#define N_APBIO              50
+#define NBIT_PADCFG          6
+#define NBIT_PADMUX          2
+#define N_UART               2
+#define N_QSPIM              1
+#define N_I2CM               2
+#define N_I2SC               0
+#define N_CSI2               0
+#define N_HYPER              0
+#define N_SDIO               1
+#define N_CAM                1
+#define N_JTAG               0
+#define N_MRAM               0
+#define N_FILTER             1
+#define N_FPGA               1
+#define N_EXT_PER            0
+#define N_EFPGA_TCDM_PORTS   4
+#define N_FPGAIO             43
+#define N_EFPGA_EVENTS       16
+
+//  UDMA configuration information
+#define UDMA_START_ADDR         0x1A102000
+#define UDMA_CH_SIZE            (0x80)
+//  peripheral channel definitions
+#define UDMA_CH_ADDR_CTRL       (0x1A102000)
+#define UDMA_CH_ADDR_UART       (0x1A102000 + 1 * 0x80)
+#define UDMA_UART_ID(id)        (0 + id)
+#define UDMA_CH_ADDR_UART0      (0x1A102000 + 1 * 0x80)
+#define UDMA_CH_ADDR_UART1      (0x1A102000 + 2 * 0x80)
+#define UDMA_CH_ADDR_QSPIM      (0x1A102000 + 3 * 0x80)
+#define UDMA_QSPIM_ID(id)       (2 + id)
+#define UDMA_CH_ADDR_QSPIM0     (0x1A102000 + 3 * 0x80)
+#define UDMA_CH_ADDR_I2CM       (0x1A102000 + 4 * 0x80)
+#define UDMA_I2CM_ID(id)        (3 + id)
+#define UDMA_CH_ADDR_I2CM0      (0x1A102000 + 4 * 0x80)
+#define UDMA_CH_ADDR_I2CM1      (0x1A102000 + 5 * 0x80)
+#define UDMA_CH_ADDR_I2SC       (0x1A102000 + 6 * 0x80)
+#define UDMA_I2SC_ID(id)        (5 + id)
+#define UDMA_CH_ADDR_I2SC0      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_CSI2       (0x1A102000 + 6 * 0x80)
+#define UDMA_CSI2_ID(id)        (5 + id)
+#define UDMA_CH_ADDR_CSI20      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_HYPER      (0x1A102000 + 6 * 0x80)
+#define UDMA_HYPER_ID(id)       (5 + id)
+#define UDMA_CH_ADDR_HYPER0     (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_SDIO       (0x1A102000 + 6 * 0x80)
+#define UDMA_SDIO_ID(id)        (5 + id)
+#define UDMA_CH_ADDR_SDIO0      (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_CAM        (0x1A102000 + 7 * 0x80)
+#define UDMA_CAM_ID(id)         (6 + id)
+#define UDMA_CH_ADDR_CAM0       (0x1A102000 + 6 * 0x80)
+#define UDMA_CH_ADDR_JTAG       (0x1A102000 + 7 * 0x80)
+#define UDMA_JTAG_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_JTAG0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_MRAM       (0x1A102000 + 7 * 0x80)
+#define UDMA_MRAM_ID(id)        (6 + id)
+#define UDMA_CH_ADDR_MRAM0      (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_FILTER     (0x1A102000 + 7 * 0x80)
+#define UDMA_FILTER_ID(id)      (6 + id)
+#define UDMA_CH_ADDR_FILTER0    (0x1A102000 + 7 * 0x80)
+#define UDMA_CH_ADDR_FPGA       (0x1A102000 + 8 * 0x80)
+#define UDMA_FPGA_ID(id)        (7 + id)
+#define UDMA_CH_ADDR_FPGA0      (0x1A102000 + 8 * 0x80)
+#define UDMA_CH_ADDR_EXT_PER    (0x1A102000 + 9 * 0x80)
+#define UDMA_EXT_PER_ID(id)     (8 + id)
+#define UDMA_CH_ADDR_EXT_PER0   (0x1A102000 + 9 * 0x80)
+
+//  Peripheral clock enable masks
+#define UDMA_CTRL_UART0_CLKEN      (1 << 0)
+#define UDMA_CTRL_UART1_CLKEN      (1 << 1)
+#define UDMA_CTRL_QSPIM0_CLKEN     (1 << 2)
+#define UDMA_CTRL_I2CM0_CLKEN      (1 << 3)
+#define UDMA_CTRL_I2CM1_CLKEN      (1 << 4)
+#define UDMA_CTRL_I2SC0_CLKEN      (1 << 5)
+#define UDMA_CTRL_CSI20_CLKEN      (1 << 5)
+#define UDMA_CTRL_HYPER0_CLKEN     (1 << 5)
+#define UDMA_CTRL_SDIO0_CLKEN      (1 << 5)
+#define UDMA_CTRL_CAM0_CLKEN       (1 << 6)
+#define UDMA_CTRL_JTAG0_CLKEN      (1 << 6)
+#define UDMA_CTRL_MRAM0_CLKEN      (1 << 6)
+#define UDMA_CTRL_FILTER0_CLKEN    (1 << 6)
+#define UDMA_CTRL_FPGA0_CLKEN      (1 << 7)
+#define UDMA_CTRL_EXT_PER0_CLKEN   (1 << 8)
+
+//  FLL configuration information
+#define FLL1_START_ADDR 0x1A100000
+
+#define FLL2_START_ADDR 0x1A100020
+
+#define FLL3_START_ADDR 0x1A100040
+
+//  GPIO configuration information
+#define GPIO_START_ADDR 0x1A101000
+
+#define SOC_EVENT_GEN_START_ADDR 0x1A106000
+//  I2C Slave configuration information
+#define I2CS_START_ADDR 0x1A107000
+
+//  EFPGAIO configuration information
+#define EFPGAIO_START_ADDR 0x1A300000
+
+//  SOC controller configuration information
+#define SOC_CTRL_START_ADDR 0x1A104000
+
+//  Event Unit (Interrupts) configuration information
+#define EU_START_ADDR 0x1A109000
+
+//  Timer configuration information
+#define TIMER_START_ADDR 0x1A10B000
+
+//  AdvTimer configuration information
+#define ADV_TIMER_START_ADDR 0x1A105000
+
+//  EFPGA configuration information (FCB)
+#define EFPGA_CONFIG_START_ADDR 0x1A200000
+#endif
+
+#endif //__CORE_V_MCU_CONFIG_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-events.h

@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_
+
+
+
+#include "core-v-mcu-properties.h"
+
+/* Events offsets. */
+#define UDMA_EVENT_OFFSET_RX            (0U)
+#define UDMA_EVENT_OFFSET_TX            (1U)
+#define EVENT_UART_RX            (2U)
+#define EVENT_UART_ERR            (3U)
+
+#define UDMA_EVENT_OFFSET_SPI_CMD       (2)
+#define UDMA_EVENT_OFFSET_SPI_EOT       (3)
+
+/* Number of events per peripheral. */
+#define UDMA_CHANNEL_NB_EVENTS_LOG2     (2)
+#define UDMA_CHANNEL_NB_EVENTS          (1 << UDMA_CHANNEL_NB_EVENTS_LOG2)
+
+/* Number of SW events. */
+#define NB_SW_EVENTS                    (8)
+
+/*! @brief FC events (aka IRQ lines)*/
+#define FC_EVENT_SW(id)                 (id & (NB_SW_EVENTS - 1))
+#define FC_EVENT_DMA_EVT                (8)
+#define FC_EVENT_DMA                    (9)
+#define FC_EVENT_TIMER0                 (10) /* Timer low.  */
+#define SYSTICK_IRQN                    FC_EVENT_TIMER0
+#define FC_EVENT_TIMER1                 (11) /* Timer high. */
+/* #define FC_EVENT_EU_HWCE                (12) */
+
+/*
+ * SoC event unit events: Many events get implicitely muxed into this interrupt.
+ * A user that gets such an interrupt has to check the event unit's registers to
+ * see what happened
+ */
+#define FC_EVENT_SOC_EVENT              (27)
+/* #define FC_EVENT_MPU_ERROR              (28) */
+/*
+ * Event queue error: If we don't process event unit events quickly enough
+ * internal fifos can overflow and we get this error interrupt
+ */
+#define FC_EVENT_FC_QUEUE_ERROR         (29)
+#define FC_EVENT_HP0                runn     (30)
+#define FC_EVENT_HP1                    (31)
+
+/*! @name SoC events  */
+/*! @brief Number of FC_Events. */
+#define SOC_EU_NB_FC_EVENTS             (168)
+
+/*! @brief UDMA events */
+/* SPIM */
+#define SOC_EVENT_UDMA_SPIM_RX(id)      ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_SPIM_TX(id)      ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+#define SOC_EVENT_UDMA_SPIM_CMD(id)     ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_CMD)
+#define SOC_EVENT_UDMA_SPIM_EOT(id)     ((UDMA_QSPIM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_SPI_EOT)
+/* HYPER */
+/* #define SOC_EVENT_UDMA_HYPER_RX(id)     ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
+/* #define SOC_EVENT_UDMA_HYPER_TX(id)     ((UDMA_HYPER_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
+/* UART */
+#define SOC_EVENT_UDMA_UART_RX(id)      ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_UART_TX(id)      ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+#define SOC_EVENT_UART_RX(id)           ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_RX)
+#define SOC_EVENT_UART_ERR(id)           ((UDMA_UART_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + EVENT_UART_ERR)
+/* I2C */
+#define SOC_EVENT_UDMA_I2C_RX(id)       ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_I2C_TX(id)       ((UDMA_I2CM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+/* DMACPY */
+/* #define SOC_EVENT_UDMA_DMACPY_RX(id)    ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX) */
+/* #define SOC_EVENT_UDMA_DMACPY_TX(id)    ((UDMA_DMACPY_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX) */
+/* I2S */
+#define SOC_EVENT_UDMA_I2S_RX(id)       ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+#define SOC_EVENT_UDMA_I2S_TX(id)       ((UDMA_I2S_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_TX)
+/* CPI */
+#define SOC_EVENT_UDMA_CAM_RX(id)       ((UDMA_CAM_ID(id) << UDMA_CHANNEL_NB_EVENTS_LOG2) + UDMA_EVENT_OFFSET_RX)
+
+/* UDMA EOT & error events. */
+//#define SOC_EVENT_UDMA_I2C_ERROR(id)  (26 + id)
+
+/*! @brief PMU events, no pmu*/
+/* #define SOC_EVENT_PMU_CLUSTER_POWER     (31) */
+/* #define SOC_EVENT_PMU_CLUSTER_CG        (35) */
+/* #define SOC_EVENT_PMU_DLC_BRIDGE_PICL   (36) */
+/* #define SOC_EVENT_PMU_DLC_BRIDGE_SCU    (37) */
+/* #define SOC_EVENT_PWM(id)               (38 + id) */
+#define SOC_EVENT_GPIO                  (139)
+#define SOC_EVENT_HWPE0                 (140)
+#define SOC_EVENT_HWPE1                 (141)
+/* #define SOC_EVENT_RTC_APB               (43) */
+/* #define SOC_EVENT_RTC                   (44) */
+
+#define SOC_EVENT_SW(id)                (160 + (id & (NB_SW_EVENTS - 1)))
+#define SOC_EVENT_REF32K_CLK_RISE       (168)
+
+/* @brief Cluster events */
+#define CL_EVENT_SW(id)                 (id & (NB_SW_EVENTS - 1))
+#define CL_EVENT_DMA0                   (8)
+#define CL_EVENT_DMA1                   (9)
+#define CL_EVENT_TIMER0_LO              (10)
+#define CL_EVENT_TIMER0_HI              (11)
+#define CL_EVENT_ACC0                   (12)
+#define CL_EVENT_ACC1                   (13)
+#define CL_EVENT_ACC2                   (14)
+#define CL_EVENT_ACC3                   (15)
+#define CL_EVENT_BAR                    (16)
+#define CL_EVENT_MUTEX                  (17)
+#define CL_EVENT_DISPATCH               (18)
+/* #define CL_EVENT_CLUSTER0               (22) */
+/* #define CL_EVENT_CLUSTER1               (23) */
+#define CL_EVENT_SOC_EVT                (30) /* adapted */
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_EVENTS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-memory-map.h

@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_
+
+#include "core-v-mcu-properties.h"
+/* Memories */
+/* FC memory. */
+#define FC_TCDM_ADDR                                (0x1B000000)
+#if (ARCHI_HAS_FC_ALIAS)
+#define FC_TCDM_ADDR_ALIAS                          (0x00000000)
+#endif  /* ARCHI_HAS_FC_ALIAS */
+
+/* L2 memory */
+#define L2_SHARED_ADDR                              (0x1C000000)
+#if (ARCHI_HAS_L2_ALIAS)
+#define L2_SHARED_ADDR_ALIAS                        (0x00000000)
+#endif  /* ARCHI_HAS_L2_ALIAS */
+
+/* L1 cluster memory */
+#define CL_L1_ADDR                                  (0x10000000)
+#if (ARCHI_HAS_CL_L1_ALIAS)
+#define CL_L1_ADDR_ALIAS                            (0x00000000)
+#endif  /* ARCHI_HAS_CL_L1_ALIAS */
+
+/* L1 cluster TS */
+#if (ARCHI_HAS_CL_L1_TS)
+#define L2_PRIV0_TS_ADDR                            (0x10100000)
+#endif  /* ARCHI_HAS_CL_L1_TS */
+
+/* ROM memory (8 KiB)*/
+#define ROM_ADDR                                    (0x1A000000)
+#define ROM_SIZE                                    (0x00002000)
+
+/* Cluster */
+#define ARCHI_CLUSTER_ADDR                          (0x00000000)
+#define ARCHI_CLUSTER_SIZE                          (0x00400000)
+#define ARCHI_CLUSTER_GLOBAL_ADDR(cid)              (0x10000000 + (cid)*ARCHI_CLUSTER_SIZE)
+#define ARCHI_CLUSTER_PERIPHERALS_OFFSET            (0x00200000)
+
+/* Cluster peripherals */
+#define ARCHI_TIMER_SIZE                            (0x00000800)
+
+#define ARCHI_CLUSTER_CTRL_OFFSET                   (0x00000000)
+#define ARCHI_TIMER_OFFSET                          (0x00000400)
+#define ARCHI_EU_OFFSET                             (0x00000800)
+#define ARCHI_HWCE_OFFSET                           (0x00001000)
+#define ARCHI_ICACHE_CTRL_OFFSET                    (0x00001400)
+#define ARCHI_MCHAN_EXT_OFFSET                      (0x00001800)
+
+#define ARCHI_CLUSTER_PERIPHERALS_ADDR              (ARCHI_CLUSTER_ADDR + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
+#define ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid)  (ARCHI_CLUSTER_GLOBAL_ADDR(cid) + ARCHI_CLUSTER_PERIPHERALS_OFFSET)
+
+#define ARCHI_CLUSTER_CTRL_ADDR                     (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_CLUSTER_CTRL_OFFSET)
+#define ARCHI_CLUSTER_TIMER_ADDR                    (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_TIMER_OFFSET)
+#define ARCHI_ICACHE_CTRL_ADDR                      (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_ICACHE_CTRL_OFFSET)
+#define ARCHI_EU_ADDR                               (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_EU_OFFSET)
+#define ARCHI_HWCE_ADDR                             (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_HWCE_OFFSET)
+#define ARCHI_MCHAN_EXT_ADDR                        (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0) + ARCHI_MCHAN_EXT_OFFSET)
+
+#define ARCHI_DEMUX_PERIPHERALS_OFFSET        (0x204000)
+#define ARCHI_EU_DEMUX_OFFSET                 (0x00000)
+#define ARCHI_MCHAN_DEMUX_OFFSET              (0x00400)
+
+#define ARCHI_DEMUX_PERIPHERALS_ADDR          (ARCHI_CLUSTER_GLOBAL_ADDR(0) + ARCHI_DEMUX_PERIPHERALS_OFFSET)
+#define ARCHI_EU_DEMUX_ADDR                   (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_EU_DEMUX_OFFSET)
+#define ARCHI_MCHAN_DEMUX_ADDR                (ARCHI_DEMUX_PERIPHERALS_ADDR + ARCHI_MCHAN_DEMUX_OFFSET)
+
+
+/* SoC peripherals */
+#define SOC_PERIPHERALS_ADDR                        (0x1A100000)
+
+#define SOC_FLL_OFFSET                              (0x00000000)
+#define CL_FLL_OFFSET                               (0x00000800)
+#define GPIO_OFFSET                                 (0x00001000)
+#define UDMA_OFFSET                                 (0x00002000)
+#define APB_SOC_CTRL_OFFSET                         (0x00004000)
+#define ADV_TIMER_OFFSET                            (0x00005000) /* PWM. */
+#define SOC_EU_OFFSET                               (0x00006000)
+#define FC_IRQ_OFFSET                               (0x00009800)
+/* #define FC_IRQ_OFFSET                               (0x00009000) */ /* valid mirror address */
+#define FC_TIMER_OFFSET                             (0x0000B000)
+#define FC_HWPE_OFFSET                              (0x0000C000)
+#define STDOUT_OFFSET                               (0x0000F000)
+#define DEBUG_OFFSET                                (0x00010000)
+
+#define SOC_FLL_ADDR                                (SOC_PERIPHERALS_ADDR + SOC_FLL_OFFSET)
+#define CL_FLL_ADDR                                 (SOC_PERIPHERALS_ADDR + CL_FLL_OFFSET)
+#define GPIO_ADDR                                   (SOC_PERIPHERALS_ADDR + GPIO_OFFSET)
+#define UDMA_CTRL_ADDR                              (SOC_PERIPHERALS_ADDR + UDMA_OFFSET)
+#define APB_SOC_CTRL_ADDR                           (SOC_PERIPHERALS_ADDR + APB_SOC_CTRL_OFFSET)
+#define ADV_TIMER_ADDR                              (SOC_PERIPHERALS_ADDR + ADV_TIMER_OFFSET)
+#define SOC_EU_ADDR                                 (SOC_PERIPHERALS_ADDR + SOC_EU_OFFSET)
+#define FC_IRQ_ADDR                                 (SOC_PERIPHERALS_ADDR + FC_IRQ_OFFSET)
+#define FC_TIMER_ADDR                               (SOC_PERIPHERALS_ADDR + FC_TIMER_OFFSET)
+#define FC_HWPE_ADDR                                (SOC_PERIPHERALS_ADDR + FC_HWPE_OFFSET)
+#define STDOUT_ADDR                                 (SOC_PERIPHERALS_ADDR + STDOUT_OFFSET)
+#define DEBUG_ADDR                                  (SOC_PERIPHERALS_ADDR + DEBUG_OFFSET)
+
+/* UDMA peripherals */
+/* #define UDMA_GC_ADDR                                (UDMA_CTRL_ADDR + 0x780) */
+/* UDMA base peripheral addr = UDMA base address + UDMA ctrl. */
+#define UDMA_PERIPH_BASE_ADDR                       (UDMA_CTRL_ADDR + 0x80)
+#define UDMA_SPIM(id)                               (UDMA_PERIPH_BASE_ADDR + (UDMA_SPIM_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_HYPER(id)                              (UDMA_PERIPH_BASE_ADDR + (UDMA_HYPER_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_UART(id)                               (UDMA_PERIPH_BASE_ADDR + (UDMA_UART_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_I2C(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_I2C_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_DMACPY(id)                             (UDMA_PERIPH_BASE_ADDR + (UDMA_DMACPY_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_I2S(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_I2S_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+#define UDMA_CPI(id)                                (UDMA_PERIPH_BASE_ADDR + (UDMA_CPI_ID(id) << UDMA_PERIPH_SIZE_LOG2))
+
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_MEMORY_MAP_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-periph.h

@@ -0,0 +1,1414 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/*!
+ * @file periph.h
+ * @version 1.0
+ * @date 2017-07-19
+ * @brief CMSIS Peripheral Access Layer for PULP
+ *
+ * CMSIS Peripheral Access Layer for PULP
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PERIPH_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PERIPH_H_                       /**< Symbol preventing repeated inclusion */
+
+#include "pmsis_gcc.h"
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS  32                  /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  FC_NOTIFY_CLUSTER_EVENT      = 0,                /**< Software event interrupt */
+  CLUSTER_NOTIFY_FC_EVENT      = 1,                /**< Software event interrupt */
+  FC_SW_NOTIFY_BRIDGE_EVENT    = 2,                /**< Software event interrupt */
+  FC_SW_NOTIFY_EVENT           = 3,                /**< Software event interrupt */
+  CLUSTER_NOTIFY_FC_IRQN       = 4,                /**< Software event interrupt */
+  DMA_SW_IRQN                  = 6,
+  PENDSV_IRQN                  = 7,                /**< Software event U -> M PendSV interrupt */
+
+  /* Device specific interrupts */
+  DMA_EVT_IRQN                 = 8,                /**< DMA event interrupt */
+  DMA_IRQN                     = 9,                /**< DMA interrupt */
+  FC_TIMER0_IRQN               = 10,               /**< FC timer0 event interrupt */
+  SYSTICK_IRQN                 = 10,               /**< PULP U -> M System Tick Interrupt */
+  FC_TIMER1_IRQN               = 11,               /**< FC timer1 interrupt */
+
+  /* misc */
+  FC_CLK_REF_EVENT             = 14,              /**< Reference clock edge event */
+  FC_GPIO_EVENT                = 15,              /**< GPIO event */
+
+  /* advanced timer events */
+  FC_ADV_TIMER0_EVENT          = 17,              /**< Advanced Timer 0 event */
+  FC_ADV_TIMER1_EVENT          = 18,              /**< Advanced Timer 1 event */
+  FC_ADV_TIMER2_EVENT          = 19,              /**< Advanced Timer 2 event */
+  FC_ADV_TIMER3_EVENT          = 20,              /**< Advanced Timer 3 event */
+
+  /* CLUSTER_NOT_BUSY_EVENT       = 21, */
+  /* CLUSTER_POK_EVENT            = 22, */
+  /* CLUSTER_CG_OK_EVENT          = 23, */
+
+  /* PICL_OK_EVENT                = 24, */
+  /* SCU_OK_EVENT                 = 25, */
+
+  FC_SOC_EVENT                 = 26,              /**< Event unit new event */
+
+  FC_QUEUE_ERROR_EVENT         = 29,              /**< Event unit queue overflow event */
+
+  FC_HP_EVENT1                 = 30,
+  FC_HP_EVENT0                 = 31
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- PULP Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PULP_Core_Configuration PULP Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               0         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  0         /**< Defines if an FPU is present or not */
+
+#include "core_pulp.h"              /* Core Peripheral Access Layer */
+
+#ifdef FEATURE_CLUSTER
+#include "core_pulp_cluster.h"              /* Cluster Access Layer */
+#endif
+
+/*!
+ * @}
+ */ /* end of group PULP_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup udma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+
+/*!
+ * @}
+ */ /* end of group udma_request */
+
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+/* ----------------------------------------------------------------------------
+   -- FLL_CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLL_CTRL_Peripheral_Access_Layer FLL_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** FLL_CTRL - Registers Layout Typedef */
+/* TODO: looks like pulp has 3 fll */
+typedef struct {
+  __IO  uint32_t FLL_STATUS;            /**< FLL_CTRL Status register, offset: 0x00 */
+  __IO  uint32_t FLL_CONF1;                 /**< FLL_CTRL Configuration1 register, offset: 0x04 */
+  __IO  uint32_t FLL_CONF2;                 /**< FLL_CTRL Configuration2 register, offset: 0x08 */
+  __IO  uint32_t FLL_INTEGRATOR;            /**< FLL_CTRL INTEGRATOR register, offset: 0x0C */
+} FLL_CTRL_Type;
+
+/* TODO: removed this register, see if it still exists */
+/* __IO  uint32_t FLL_CONVERGE;*/              /**< FLL_CTRL Fll Converge register, offset: 0x20 */
+
+/* ----------------------------------------------------------------------------
+   -- FLL_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLL_CTRL_Register_Masks FLL_CTRL Register Masks
+ * @{
+ */
+/*! @name FLL_STATUS - FLL_CTRL status register */
+#define FLL_CTRL_STATUS_MULTI_FACTOR_MASK              (0xFFFFU)
+#define FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT             (0U)
+#define FLL_CTRL_STATUS_MULTI_FACTOR(x)                (((uint32_t)(((uint32_t)(x)) /* << FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT */)) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK)
+#define READ_FLL_CTRL_STATUS_MULTI_FACTOR(x)           (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_STATUS_MULTI_FACTOR_MASK)) /*>> FLL_CTRL_STATUS_MULTI_FACTOR_SHIFT*/)
+
+/*! @name SOC_CONF1 - FLL_CTRL configuration 1 register */
+#define FLL_CTRL_CONF1_MULTI_FACTOR_MASK           (0xFFFFU)
+#define FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT          (0U)
+#define FLL_CTRL_CONF1_MULTI_FACTOR(x)             (((uint32_t)(((uint32_t)(x)) /* << FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT */)) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK)
+#define READ_FLL_CTRL_CONF1_MULTI_FACTOR(x)        (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_MULTI_FACTOR_MASK)) /*>> FLL_CTRL_CONF1_MULTI_FACTOR_SHIFT*/)
+
+#define FLL_CTRL_CONF1_DCO_INPUT_MASK              (0x3FF0000U)
+#define FLL_CTRL_CONF1_DCO_INPUT_SHIFT             (16U)
+#define FLL_CTRL_CONF1_DCO_INPUT(x)                (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_DCO_INPUT_SHIFT)) & FLL_CTRL_CONF1_DCO_INPUT_MASK)
+#define READ_FLL_CTRL_CONF1_DCO_INPUT(x)           (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_DCO_INPUT_MASK)) >> FLL_CTRL_CONF1_DCO_INPUT_SHIFT)
+
+#define FLL_CTRL_CONF1_CLK_OUT_DIV_MASK            (0x3C000000U)
+#define FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT           (26U)
+#define FLL_CTRL_CONF1_CLK_OUT_DIV(x)              (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT)) & FLL_CTRL_CONF1_CLK_OUT_DIV_MASK)
+#define READ_FLL_CTRL_CONF1_CLK_OUT_DIV(x)         (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_CLK_OUT_DIV_MASK)) >> FLL_CTRL_CONF1_CLK_OUT_DIV_SHIFT)
+
+#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK         (0x40000000U)
+#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT        (30U)
+#define FLL_CTRL_CONF1_OUTPUT_LOCK_EN(x)           (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT)) & FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK)
+#define READ_FLL_CTRL_CONF1_OUTPUT_LOCK_EN(x)      (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK)) >> FLL_CTRL_CONF1_OUTPUT_LOCK_EN_SHIFT)
+
+#define FLL_CTRL_CONF1_MODE_MASK                   (0x80000000U)
+#define FLL_CTRL_CONF1_MODE_SHIFT                  (31U)
+#define FLL_CTRL_CONF1_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF1_MODE_SHIFT)) & FLL_CTRL_CONF1_MODE_MASK)
+#define READ_FLL_CTRL_CONF1_MODE(x)                (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF1_MODE_MASK)) >> FLL_CTRL_CONF1_MODE_SHIFT)
+
+/*! @name SOC_CONF2 - FLL_CTRL configuration 2 register */
+#define FLL_CTRL_CONF2_LOOPGAIN_MASK               (0xFU)
+#define FLL_CTRL_CONF2_LOOPGAIN_SHIF  T            (0U)
+#define FLL_CTRL_CONF2_LOOPGAIN(x)                 (((uint32_t)(((uint32_t)(x)) /* << FLL_CTRL_CONF2_LOOPGAIN_SHIFT */)) & FLL_CTRL_CONF2_LOOPGAIN_MASK)
+#define READ_FLL_CTRL_CONF2_LOOPGAIN(x)            (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_LOOPGAIN_MASK))/* >> FLL_CTRL_CONF2_LOOPGAIN_SHIFT*/)
+
+#define FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK        (0x3F0U)
+#define FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT       (4U)
+#define FLL_CTRL_CONF2_DEASSERT_CYCLES(x)          (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT)) & FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK)
+#define READ_FLL_CTRL_CONF2_DEASSERT_CYCLES(x)     (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_DEASSERT_CYCLES_MASK)) >> FLL_CTRL_CONF2_DEASSERT_CYCLES_SHIFT)
+
+#define FLL_CTRL_CONF2_ASSERT_CYCLES_MASK          (0xFC00U)
+#define FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT         (10U)
+#define FLL_CTRL_CONF2_ASSERT_CYCLES(x)            (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT)) & FLL_CTRL_CONF2_ASSERT_CYCLES_MASK)
+#define READ_FLL_CTRL_CONF2_ASSERT_CYCLES(x)       (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_ASSERT_CYCLES_MASK)) >> FLL_CTRL_CONF2_ASSERT_CYCLES_SHIFT)
+
+#define FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK         (0xFFF0000U)
+#define FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT        (16U)
+#define FLL_CTRL_CONF2_LOCK_TOLERANCE(x)           (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT)) & FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK)
+#define READ_FLL_CTRL_CONF2_LOCK_TOLERANCE(x)      (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK)) >> FLL_CTRL_CONF2_LOCK_TOLERANCE_SHIFT)
+
+#define FLL_CTRL_CONF2_CONF_CLK_SEL_MASK           (0x20000000U)
+#define FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT          (29U)
+#define FLL_CTRL_CONF2_CONF_CLK_SEL(x)             (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT)) & FLL_CTRL_CONF2_CONF_CLK_SEL_MASK)
+#define READ_FLL_CTRL_CONF2_CONF_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_CONF_CLK_SEL_MASK)) >> FLL_CTRL_CONF2_CONF_CLK_SEL_SHIFT)
+
+#define FLL_CTRL_CONF2_OPEN_LOOP_MASK              (0x40000000U)
+#define FLL_CTRL_CONF2_OPEN_LOOP_SHIFT             (30U)
+#define FLL_CTRL_CONF2_OPEN_LOOP(x)                (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_OPEN_LOOP_SHIFT)) & FLL_CTRL_CONF2_OPEN_LOOP_MASK)
+#define READ_FLL_CTRL_CONF2_OPEN_LOOP(x)           (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_OPEN_LOOP_MASK)) >> FLL_CTRL_CONF2_OPEN_LOOP_SHIFT)
+
+#define FLL_CTRL_CONF2_DITHERING_MASK              (0x80000000U)
+#define FLL_CTRL_CONF2_DITHERING_SHIFT             (31U)
+#define FLL_CTRL_CONF2_DITHERING(x)                (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CONF2_DITHERING_SHIFT)) & FLL_CTRL_CONF2_DITHERING_MASK)
+#define READ_FLL_CTRL_CONF2_DITHERING(x)           (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CONF2_DITHERING_MASK)) >> FLL_CTRL_CONF2_DITHERING_SHIFT)
+
+/*! @name SOC_INTEGRATOR - FLL_CTRL configuration 2 register */
+#define FLL_CTRL_INTEGRATOR_FRACT_PART_MASK        (0xFFC0U)
+#define FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT       (6U)
+#define FLL_CTRL_INTEGRATOR_FRACT_PART(x)          (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT)) & FLL_CTRL_INTEGRATOR_FRACT_PART_MASK)
+#define READ_FLL_CTRL_INTEGRATOR_FRACT_PART(x)     (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_INTEGRATOR_FRACT_PART_MASK)) >> FLL_CTRL_INTEGRATOR_FRACT_PART_SHIFT)
+
+#define FLL_CTRL_INTEGRATOR_INT_PART_MASK          (0x3FF0000U)
+#define FLL_CTRL_INTEGRATOR_INT_PART_SHIFT         (16U)
+#define FLL_CTRL_INTEGRATOR_INT_PART(x)            (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_INTEGRATOR_INT_PART_SHIFT)) & FLL_CTRL_INTEGRATOR_INT_PART_MASK)
+#define READ_FLL_CTRL_INTEGRATOR_INT_PART(x)       (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_INTEGRATOR_INT_PART_MASK)) >> FLL_CTRL_INTEGRATOR_INT_PART_SHIFT)
+
+/*! @name FLL_CONVERGE - FLL_CTRL configuration 2 register */
+#define FLL_CTRL_SOC_FLL_CONV_MASK                 (0x1U)
+#define FLL_CTRL_SOC_FLL_CONV_SHIFT                (0U)
+#define FLL_CTRL_SOC_FLL_CONV(x)                   (((uint32_t)(((uint32_t)(x)) /*<< FLL_CTRL_SOC_FLL_CONV_SHIFT */)) & FLL_CTRL_SOC_FLL_CONV_MASK)
+#define READ_FLL_CTRL_SOC_FLL_CONV(x)              (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_SOC_FLL_CONV_MASK)) /*>> FLL_CTRL_SOC_FLL_CONV_SHIFT*/)
+
+#define FLL_CTRL_CLUSTER_FLL_CONV_MASK             (0x2U)
+#define FLL_CTRL_CLUSTER_FLL_CONV_SHIFT            (1U)
+#define FLL_CTRL_CLUSTER_FLL_CONV(x)               (((uint32_t)(((uint32_t)(x)) << FLL_CTRL_CLUSTER_FLL_CONV_SHIFT)) & FLL_CTRL_CLUSTER_FLL_CONV_MASK)
+#define READ_FLL_CTRL_CLUSTER_FLL_CONV(x)          (((uint32_t)(((uint32_t)(x)) & FLL_CTRL_CLUSTER_FLL_CONV_MASK)) >> FLL_CTRL_CLUSTER_FLL_CONV_SHIFT)
+
+
+/*!
+ * @}
+ */ /* end of group FLL_CTRL_Register_Masks */
+
+/* The number of FLL */
+#define FLL_NUM       ARCHI_NB_FLL
+/* The FLL reference frequency*/
+#define FLL_REF_CLK   ARCHI_REF_CLOCK
+
+
+/* FLL_CTRL - Peripheral instance base addresses */
+/** Peripheral FLL_CTRL base address */
+#define FLL_CTRL_BASE                                (SOC_PERIPHERALS_ADDR)
+/** Peripheral FLL_CTRL base pointer */
+#define FLL_CTRL                                     ((FLL_CTRL_Type *)FLL_CTRL_BASE)
+/** Array initializer of FLL_CTRL base addresses */
+#define FLL_CTRL_BASE_ADDRS                          { FLL_CTRL_BASE }
+/** Array initializer of FLL_CTRL base pointers */
+#define FLL_CTRL_BASE_PTRS                           { FLL_CTRL }
+
+/*!
+ * @}
+ */ /* end of group FLL_CTRL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+#include "hal_gpio_periph.h"
+#define gpio(id) (((gpio_t *) GPIO_ADDR) + id)
+
+
+
+/* ----------------------------------------------------------------------------
+   -- UDMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UDMA_Peripheral_Access_Layer  UDMA Peripheral Access Layer
+ * @{
+ */
+
+/** UDMA - General Register Layout Typedef */
+typedef struct {
+  __IO uint32_t RX_SADDR;                          /**< RX UDMA buffer transfer address register, offset: 0x0 */
+  __IO uint32_t RX_SIZE;                           /**< RX UDMA buffer transfer size register, offset: 0x4 */
+  __IO uint32_t RX_CFG;                            /**< RX UDMA transfer configuration register, offset: 0x8 */
+  __IO uint32_t RX_INITCFG;                        /**< Reserved, offset: 0xC */
+  __IO uint32_t TX_SADDR;                          /**< TX UDMA buffer transfer address register, offset: 0x10 */
+  __IO uint32_t TX_SIZE;                           /**< TX UDMA buffer transfer size register, offset: 0x14 */
+  __IO uint32_t TX_CFG;                            /**< TX UDMA transfer configuration register, offset: 0x18 */
+  __IO uint32_t TX_INITCFG;                        /**< Reserved, offset: 0x1C */
+
+} UDMA_Type;
+
+#include "hal_udma_core_periph.h"
+/* ----------------------------------------------------------------------------
+   -- UDMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UDMA_Register_Masks UDMA Register Masks
+ * @{
+ */
+/*! @name RX_SADDR - RX TX UDMA buffer transfer address register */
+#define UDMA_SADDR_ADDR_MASK                 (0xFFFFU)
+#define UDMA_SADDR_ADDR_SHIFT                (0U)
+#define UDMA_SADDR_ADDR(x)                   (((uint32_t)(((uint32_t)(x)) /*<< UDMA_SADDR_ADDR_SHIFT*/)) & UDMA_SADDR_ADDR_MASK)
+
+/*! @name RX_SIZE - RX TX UDMA buffer transfer size register */
+#define UDMA_SIZE_SIZE_MASK                  (0x1FFFFU)
+#define UDMA_SIZE_SIZE_SHIFT                 (0U)
+#define UDMA_SIZE_SIZE(x)                    (((uint32_t)(((uint32_t)(x)) << UDMA_SIZE_SIZE_SHIFT)) & UDMA_SIZE_SIZE_MASK)
+
+
+/*! @name RX_CFG - RX TX UDMA transfer configuration register */
+#define UDMA_CFG_CONTINOUS_MASK              (0x1U)
+#define UDMA_CFG_CONTINOUS_SHIFT             (0U)
+#define UDMA_CFG_CONTINOUS(x)                (((uint32_t)(((uint32_t)(x)) /*<< UDMA_CFG_CONTINOUS_SHIFT*/)) & UDMA_CFG_CONTINOUS_MASK)
+#define UDMA_CFG_DATA_SIZE_MASK              (0x6U)
+#define UDMA_CFG_DATA_SIZE_SHIFT             (1U)
+#define UDMA_CFG_DATA_SIZE(x)                (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_DATA_SIZE_SHIFT)) & UDMA_CFG_DATA_SIZE_MASK)
+#define UDMA_CFG_EN_MASK                     (0x10U)
+#define UDMA_CFG_EN_SHIFT                    (4U)
+#define UDMA_CFG_EN(x)                       (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_EN_SHIFT)) & UDMA_CFG_EN_MASK)
+#define UDMA_CFG_PENDING_MASK                (0x20U)
+#define UDMA_CFG_PENDING_SHIFT               (5U)
+#define UDMA_CFG_PENDING(x)                  (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_PENDING_SHIFT)) & UDMA_CFG_PENDING_MASK)
+#define UDMA_CFG_CLR_MASK                    (0x20U)
+#define UDMA_CFG_CLR_SHIFT                   (5U)
+#define UDMA_CFG_CLR(x)                      (((uint32_t)(((uint32_t)(x)) << UDMA_CFG_CLR_SHIFT)) & UDMA_CFG_CLR_MASK)
+
+/*!
+ * @}
+ */ /* end of group UDMA_Register_Masks */
+
+
+/* UDMA - Peripheral instance base addresses */
+/** Peripheral UDMA base address 0x1A102080 */
+#define UDMA_BASE                                UDMA_PERIPH_BASE_ADDR
+/** Peripheral UDMA events number */
+/* TODO: check those */
+#define UDMA_EVENTS_NUM                          19
+/** Peripheral UDMA channel number */
+#define UDMA_CHANNEL_NUM                         10
+
+/*!
+ * @}
+ */ /* end of group UDMA_Peripheral_Access_Layer */
+
+
+
+
+/* ----------------------------------------------------------------------------
+   -- UDMA Global Configuration Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UDMA_GC_Peripheral_Access_Layer UDMA_GC Peripheral Access Layer
+ * @{
+ */
+
+/** UDMA Global configuration - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CG;                          /**< UDMA_GC clock gating register, offset: 0x0 */
+  __IO uint32_t EVTIN;                       /**< UDMA_GC input event register, offset: 0x04 */
+} UDMA_GC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UDMA_GC Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup UDMA_GC_Register_Masks UDMA_GC Register Masks
+ * @{
+ */
+
+/*! @name UDMA_GC - UDMA event in register, User chooses which events can come to UDMA as reference events, support up to 4 choices */
+#define UDMA_GC_EVTIN_CHOICE0_MASK                  (0xFFU)
+#define UDMA_GC_EVTIN_CHOICE0_SHIFT                 (0U)
+#define UDMA_GC_EVTIN_CHOICE0(x)                    (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE0_SHIFT)) & UDMA_GC_EVTIN_CHOICE0_MASK)
+
+#define UDMA_GC_EVTIN_CHOICE1_MASK                  (0xFF00U)
+#define UDMA_GC_EVTIN_CHOICE1_SHIFT                 (8U)
+#define UDMA_GC_EVTIN_CHOICE1(x)                    (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE1_SHIFT)) & UDMA_GC_EVTIN_CHOICE1_MASK)
+
+#define UDMA_GC_EVTIN_CHOICE2_MASK                  (0xFF0000U)
+#define UDMA_GC_EVTIN_CHOICE2_SHIFT                 (16U)
+#define UDMA_GC_EVTIN_CHOICE2(x)                    (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE2_SHIFT)) & UDMA_GC_EVTIN_CHOICE2_MASK)
+
+#define UDMA_GC_EVTIN_CHOICE3_MASK                  (0xFF000000)
+#define UDMA_GC_EVTIN_CHOICE3_SHIFT                 (24U)
+#define UDMA_GC_EVTIN_CHOICE3(x)                    (((uint32_t)(((uint32_t)(x)) << UDMA_GC_EVTIN_CHOICE3_SHIFT)) & UDMA_GC_EVTIN_CHOICE3_MASK)
+
+#define UDMA_GC_EVTIN_MASK(evt_in)                  (evt_in&0xFF)
+#define UDMA_GC_EVTIN_SHIFT_ID(id)                  (id*8)
+
+/*!
+ * @}
+ */ /* end of group UDMA_GC_Register_Masks */
+
+
+/* UDMA Global configuration - instance base addresses */
+/** Global configuration UDMA base address */
+#define UDMA_GC_BASE                              (UDMA_CTRL_ADDR)
+#define UDMA_GC                            ((UDMA_GC_Type *)UDMA_GC_BASE)
+
+/*!
+ * @}
+ */ /* end of group UDMA_GC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+#include "hal_spi_periph.h"
+
+
+/* ----------------------------------------------------------------------------
+   -- HYPERBUS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+#include "core-v-mcu-memory-map.h"
+ #include "core-v-mcu-events.h"
+/* #include "periph/hyper_periph.h" */
+#define hyperbus(id) ((hyperbus_t *) UDMA_HYPER(id))
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+#include "hal_uart_periph.h"
+#define uart(id) ((uart_t *) UDMA_UART(id))
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+#include "hal_i2c_periph.h"
+#define i2c(id) ((i2c_t *) UDMA_I2C(id))
+
+
+/* ----------------------------------------------------------------------------
+   -- DMACPY Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/* #include "periph/dmacpy_periph.h" */
+#define dmacpy(id) ((dmacpy_t *) UDMA_DMACPY(id))
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+//#include "periph/i2s_periph.h"
+#define i2s(id) ((i2s_t *) UDMA_I2S(id))
+
+
+/* ----------------------------------------------------------------------------
+   -- CPI Peripheral
+   ---------------------------------------------------------------------------- */
+/* #include "periph/cpi_periph.h" */
+#define cpi(id) ((cpi_t *) UDMA_CPI(id))
+
+
+
+/* ----------------------------------------------------------------------------
+   -- SOC_CTRL Peripheral
+   ---------------------------------------------------------------------------- */
+#include "hal_soc_ctrl_periph.h"
+#define soc_ctrl ((soc_ctrl_t *) APB_SOC_CTRL_ADDR)
+
+/* TODO: Remove this instance.  */
+/* SOC_CTRL - Peripheral instance base addresses */
+/** Peripheral SOC_CTRL base address */
+#define SOC_CTRL_BASE                                (SOC_PERIPHERALS_ADDR + 0x4000u)
+
+
+/* ----------------------------------------------------------------------------
+   -- PMU CTRL Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_CTRL_Peripheral_Access_Layer PMU_CTRL Peripheral Access Layer
+ * @{
+ */
+
+/** PMU - General Register Layout Typedef */
+typedef struct {
+  __IO uint32_t RAR_DCDC;                     /**< PMU CTRL control register, offset: 0x000 */
+  __IO uint32_t SLEEP_CTRL;                   /**< PMU CTRL sleep control register, offset: 0x004 */
+  __IO uint32_t FORCE;                        /**< PMU CTRL register, offset: 0x008 */
+
+} PMU_CTRL_Type;
+
+
+/* ----------------------------------------------------------------------------
+   -- PMU_CTRL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_CTRL_Register_Masks PMU_CTRL Register Masks
+ * @{
+ */
+/*! @name RAR_DCDC - PMU control register */
+#define PMU_CTRL_RAR_DCDC_NV_MASK         (0x1FU)
+#define PMU_CTRL_RAR_DCDC_NV_SHIFT        (0U)
+#define PMU_CTRL_RAR_DCDC_NV(x)           (((uint32_t)(((uint32_t)(x)) /* << PMU_CTRL_RAR_DCDC_NV_SHIFT*/)) & PMU_CTRL_RAR_DCDC_NV_MASK)
+#define READ_PMU_CTRL_RAR_DCDC_NV(x)      (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_NV_MASK)) /*>> PMU_CTRL_RAR_DCDC_NV_SHIFT*/)
+#define PMU_CTRL_RAR_DCDC_MV_MASK         (0x1F00U)
+#define PMU_CTRL_RAR_DCDC_MV_SHIFT        (8U)
+#define PMU_CTRL_RAR_DCDC_MV(x)           (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_RAR_DCDC_MV_SHIFT)) & PMU_CTRL_RAR_DCDC_MV_MASK)
+#define READ_PMU_CTRL_RAR_DCDC_MV(x)      (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_MV_MASK)) >> PMU_CTRL_RAR_DCDC_MV_SHIFT)
+#define PMU_CTRL_RAR_DCDC_LV_MASK         (0x1F0000U)
+#define PMU_CTRL_RAR_DCDC_LV_SHIFT        (16U)
+#define PMU_CTRL_RAR_DCDC_LV(x)           (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_RAR_DCDC_LV_SHIFT)) & PMU_CTRL_RAR_DCDC_LV_MASK)
+#define READ_PMU_CTRL_RAR_DCDC_LV(x)      (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_LV_MASK)) >> PMU_CTRL_RAR_DCDC_LV_SHIFT)
+#define PMU_CTRL_RAR_DCDC_RV_MASK         (0x1F000000U)
+#define PMU_CTRL_RAR_DCDC_RV_SHIFT        (24U)
+#define PMU_CTRL_RAR_DCDC_RV(x)           (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_RAR_DCDC_RV_SHIFT)) & PMU_CTRL_RAR_DCDC_RV_MASK)
+#define READ_PMU_CTRL_RAR_DCDC_RV(x)      (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_RAR_DCDC_RV_MASK)) >> PMU_CTRL_RAR_DCDC_RV_SHIFT)
+
+/*! @name SLEEP_CTRL - PMU control register */
+#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK         (0xFU)
+#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT        (0U)
+#define PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x)           (((uint32_t)(((uint32_t)(x)) /* << PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT*/)) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET(x)      (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_MASK)) /*>> PMU_CTRL_SLEEP_CTRL_CFG_MEM_RET_SHIFT*/)
+
+#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK     (0x10U)
+#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT    (4U)
+#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x)       (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET(x)  (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_MASK)) >> PMU_CTRL_SLEEP_CTRL_CFG_FLL_SOC_RET_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK  (0x20U)
+#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT (5U)
+#define PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x)    (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET(x)   (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_MASK)) >> PMU_CTRL_SLEEP_CTRL_CFG_FLL_CLUSTER_RET_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK      (0x7C0U)
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT     (6U)
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x)        (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL(x)   (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_MASK)) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_SEL_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK     (0x1800U)
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT    (11U)
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x)       (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE(x)  (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_MASK)) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_TYPE_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK       (0x2000U)
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT      (13U)
+#define PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x)         (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN(x)    (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_MASK)) >> PMU_CTRL_SLEEP_CTRL_EXT_WAKE_EN_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK            (0xC000U)
+#define PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT           (14U)
+#define PMU_CTRL_SLEEP_CTRL_WAKEUP(x)              (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT)) & PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_WAKEUP(x)         (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_WAKEUP_MASK)) >> PMU_CTRL_SLEEP_CTRL_WAKEUP_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK           (0x10000U)
+#define PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT          (16U)
+#define PMU_CTRL_SLEEP_CTRL_BOOT_L2(x)             (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT)) & PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_BOOT_L2(x)        (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_BOOT_L2_MASK)) >> PMU_CTRL_SLEEP_CTRL_BOOT_L2_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_REBOOT_MASK            (0xC0000U)
+#define PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT           (18U)
+#define PMU_CTRL_SLEEP_CTRL_REBOOT(x)              (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT)) & PMU_CTRL_SLEEP_CTRL_REBOOT_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_REBOOT(x)         (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_REBOOT_MASK)) >> PMU_CTRL_SLEEP_CTRL_REBOOT_SHIFT)
+
+#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK      (0x100000U)
+#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT     (20U)
+#define PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x)        (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT)) & PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK)
+#define READ_PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP(x)   (((uint32_t)(((uint32_t)(x)) & PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_MASK)) >> PMU_CTRL_SLEEP_CTRL_CLUSTER_WAKEUP_SHIFT)
+
+/*! @name FORCE - PMU control register */
+#define PMU_CTRL_FORCE_MEM_RET_MASK                (0xFU)
+#define PMU_CTRL_FORCE_MEM_RET_SHIFT               (0U)
+#define PMU_CTRL_FORCE_MEM_RET(x)                  (((uint32_t)(((uint32_t)(x)) /* << PMU_CTRL_FORCE_MEM_RET_SHIFT*/)) & PMU_CTRL_FORCE_MEM_RET_MASK)
+
+#define PMU_CTRL_FORCE_MEM_PWD_MASK                (0xF0U)
+#define PMU_CTRL_FORCE_MEM_PWD_SHIFT               (4U)
+#define PMU_CTRL_FORCE_MEM_PWD(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_FORCE_MEM_PWD_SHIFT)) & PMU_CTRL_FORCE_MEM_PWD_MASK)
+
+#define PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK        (0x100U)
+#define PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT       (8U)
+#define PMU_CTRL_FORCE_FLL_CLUSTER_RET(x)          (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_FORCE_FLL_CLUSTER_RET_SHIFT)) & PMU_CTRL_FORCE_FLL_CLUSTER_RET_MASK)
+
+#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK        (0x200U)
+#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT       (9U)
+#define PMU_CTRL_FORCE_FLL_CLUSTER_PWD(x)          (((uint32_t)(((uint32_t)(x)) << PMU_CTRL_FORCE_FLL_CLUSTER_PWD_SHIFT)) & PMU_CTRL_FORCE_FLL_CLUSTER_PWD_MASK)
+
+/*!
+ * @}
+ */ /* end of group PMU_CTRL_Register_Masks */
+
+
+/* PMU CTRL- Peripheral instance base addresses */
+/** Peripheral PMU CTRL base address */
+#define PMU_CTRL_BASE                               (SOC_CTRL_BASE + 0x0100u)
+/** Peripheral PMU_CTRL0 base pointer */
+#define PMU_CTRL                                    ((PMU_CTRL_Type *)PMU_CTRL_BASE)
+/** Array initializer of PMU_CTRL base addresses */
+#define PMU_CTRL_BASE_ADDRS                         { PMU_CTRL_BASE }
+/** Array initializer of PMU_CTRL base pointers */
+#define PMU_CTRL_BASE_PTRS                          { PMU_CTRL }
+
+/*!
+ * @}
+ */ /* end of group PMU_CTRL_Peripheral_Access_Layer */
+
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO  uint32_t PADFUN[4];                       /**< PORT pad function register 0, offset: 0x000 */
+  __IO  uint32_t SLEEP_PADCFG[4];                 /**< PORT sleep pad configuration register 0, offset: 0x010 */
+  __IO  uint32_t PAD_SLEEP;                       /**< PORT pad sleep register, offset: 0x020 */
+  __IO  uint32_t _reserved0[7];                   /**< reserved, offset: 0x010 */
+  __IO  uint32_t PADCFG[16];                      /**< PORT pad configuration register 0, offset: 0x040 */
+
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks GPIO Register Masks
+ * @{
+ */
+#define GPIO_NUM                                 32
+
+/*! @name PADFUN - GPIO pad mux registers */
+#define PORT_PADFUN_MUX_MASK                     (0x3U)
+#define PORT_PADFUN_MUX_SHIFT                    (0U)
+#define PORT_PADFUN_MUX(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_PADFUN_MUX_SHIFT)) & PORT_PADFUN_MUX_MASK)
+
+/*! @name PADCFG - GPIO pad configuration registers */
+#define PORT_PADCFG_PULL_EN_MASK                 (0x1U)
+#define PORT_PADCFG_PULL_EN_SHIFT                (0U)
+#define PORT_PADCFG_PULL_EN(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_PADCFG_PULL_EN_SHIFT)) & PORT_PADCFG_PULL_EN_MASK)
+#define PORT_PADCFG_DRIVE_STRENGTH_MASK          (0x2U)
+#define PORT_PADCFG_DRIVE_STRENGTH_SHIFT         (1U)
+#define PORT_PADCFG_DRIVE_STRENGTH(x)            (((uint32_t)(((uint32_t)(x)) << PORT_PADCFG_DRIVE_STRENGTH_SHIFT)) & PORT_PADCFG_DRIVE_STRENGTH_MASK)
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                              (SOC_CTRL_BASE + 0x0140u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                   ((PORT_Type *)PORTA_BASE)
+/** Array initializer of PORT base addresses */
+#define PORT_BASE_ADDRS                         { PORTA_BASE }
+/** Array initializer of PORT base pointers */
+#define PORT_BASE_PTRS                          { PORTA }
+
+/*!
+ * @}
+ */ /* end of group PORT_Access_Layer */
+
+
+
+/* ----------------------------------------------------------------------------
+   -- IO POWER DOMAINS ISOLATION Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IO_ISO_Peripheral_Access_Layer IO_ISO Peripheral Access Layer
+ * @{
+ */
+
+/** IO_ISO - Register Layout Typedef */
+typedef struct {
+  __IO  uint32_t GPIO_ISO;                       /**< IO_ISO GPIO power domains isolation, offset: 0x000 */
+  __IO  uint32_t CAM_ISO;                        /**< IO_ISO Cemera power domains isolation, offset: 0x004 */
+  __IO  uint32_t LVDS_ISO;                       /**< IO_ISO LVDS power domains isolation, offset: 0x008 */
+
+} IO_ISO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- IO_ISO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IO_ISO_Register_Masks GPIO Register Masks
+ * @{
+ */
+#define IO_ISO_GPIO_ISO_MASK                 (0x1U)
+#define IO_ISO_GPIO_ISO_SHIFT                (0U)
+#define IO_ISO_GPIO_ISO(x)                   (((uint32_t)(((uint32_t)(x)) /* << IO_ISO_GPIO_ISO_SHIFT */)) & IO_ISO_GPIO_ISO_MASK)
+
+#define IO_ISO_CAM_ISO_MASK                 (0x1U)
+#define IO_ISO_CAM_ISO_SHIFT                (0U)
+#define IO_ISO_CAM_ISO(x)                   (((uint32_t)(((uint32_t)(x)) /* << IO_ISO_CAM_ISO_SHIFT */)) & IO_ISO_CAM_ISO_MASK)
+
+#define IO_ISO_LVDS_ISO_MASK                 (0x1U)
+#define IO_ISO_LVDS_ISO_SHIFT                (0U)
+#define IO_ISO_LVDS_ISO(x)                   (((uint32_t)(((uint32_t)(x)) /* << IO_ISO_LVDS_ISO_SHIFT */)) & IO_ISO_LVDS_ISO_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group IO_ISO_Register_Masks */
+
+
+/* IO_ISO - Peripheral instance base addresses */
+/** Peripheral IO_ISO base address */
+#define IO_ISO_BASE                               (SOC_CTRL_BASE + 0x01C0u)
+/** Peripheral IO_ISO base pointer */
+#define IO_ISO                                    ((IO_ISO_Type *)IO_ISO_BASE)
+/** Array initializer of IO_ISO base addresses */
+#define IO_ISO_BASE_ADDRS                         { IO_ISO_BASE }
+/** Array initializer of IO_ISO base pointers */
+#define IO_ISO_BASE_PTRS                          { IO_ISO }
+
+/*!
+ * @}
+ */ /* end of group IO_ISO_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PWM Peripheral
+   ---------------------------------------------------------------------------- */
+#include "hal_pwm_periph.h"
+#include "hal_pwm_ctrl_periph.h"
+#define pwm(id) ((pwm_t *) (ADV_TIMER_ADDR + (id << 6)))
+#define pwm_ctrl ((pwm_ctrl_t *) (ADV_TIMER_ADDR + 0x100))
+
+
+
+/* ----------------------------------------------------------------------------
+   -- SOCEU (SOC EVENT UNIT) Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SOCEU_Peripheral_Access_Layer SOCEU Peripheral Access Layer
+ * @{
+ */
+
+/** SOCEU - Register Layout Typedef */
+typedef struct {
+  __IO  uint32_t EVENT;                          /**< SOCEU event register, offset: 0x00 */
+  __IO  uint32_t FC_MASK0;                       /**< SOCEU fc mask 0 register, offset: 0x04 */
+  __IO  uint32_t FC_MASK1;                       /**< SOCEU fc mask 1 register, offset: 0x08 */
+  __IO  uint32_t FC_MASK2;                       /**< SOCEU fc mask 2 register, offset: 0x0c */
+  __IO  uint32_t FC_MASK3;                       /**< SOCEU fc mask 3 register, offset: 0x10 */
+  __IO  uint32_t FC_MASK4;                       /**< SOCEU fc mask 4 register, offset: 0x14 */
+  __IO  uint32_t FC_MASK5;                       /**< SOCEU fc mask 5 register, offset: 0x18 */
+  __IO  uint32_t FC_MASK6;                       /**< SOCEU fc mask 6 register, offset: 0x1c */
+  __IO  uint32_t FC_MASK7;                       /**< SOCEU fc mask 7 register, offset: 0x20 */
+  __IO  uint32_t CL_MASK0;                       /**< SOCEU cluster mask 0 register, offset: 0x24 */
+  __IO  uint32_t CL_MASK1;                       /**< SOCEU cluster mask 1 register, offset: 0x28 */
+  __IO  uint32_t CL_MASK2;                       /**< SOCEU cluster mask 2 register, offset: 0x2C */
+  __IO  uint32_t CL_MASK3;                       /**< SOCEU cluster mask 3 register, offset: 0x30 */
+  __IO  uint32_t CL_MASK4;                       /**< SOCEU cluster mask 4 register, offset: 0x34 */
+  __IO  uint32_t CL_MASK5;                       /**< SOCEU cluster mask 5 register, offset: 0x38 */
+  __IO  uint32_t CL_MASK6;                       /**< SOCEU cluster mask 6 register, offset: 0x3C */
+  __IO  uint32_t CL_MASK7;                       /**< SOCEU cluster mask 7 register, offset: 0x40 */
+  __IO  uint32_t PR_MASK0;                       /**< SOCEU propagate mask MSB register, offset: 0x44 */
+  __IO  uint32_t PR_MASK1;                       /**< SOCEU propagate mask MSB register, offset: 0x48 */
+  __IO  uint32_t PR_MASK2;                       /**< SOCEU propagate mask MSB register, offset: 0x4c */
+  __IO  uint32_t PR_MASK3;                       /**< SOCEU propagate mask MSB register, offset: 0x50 */
+  __IO  uint32_t PR_MASK4;                       /**< SOCEU propagate mask MSB register, offset: 0x54 */
+  __IO  uint32_t PR_MASK5;                       /**< SOCEU propagate mask MSB register, offset: 0x58 */
+  __IO  uint32_t PR_MASK6;                       /**< SOCEU propagate mask MSB register, offset: 0x5c */
+  __IO  uint32_t PR_MASK7;                       /**< SOCEU propagate mask MSB register, offset: 0x60 */
+  __IO  uint32_t ERR_MASK0;                      /**< SOCEU error mask MSB register, offset: 0x64 */
+  __IO  uint32_t ERR_MASK1;                      /**< SOCEU error mask MSB register, offset: 0x68 */
+  __IO  uint32_t ERR_MASK2;                      /**< SOCEU error mask MSB register, offset: 0x6c */
+  __IO  uint32_t ERR_MASK3;                      /**< SOCEU error mask MSB register, offset: 0x70 */
+  __IO  uint32_t ERR_MASK4;                      /**< SOCEU error mask MSB register, offset: 0x74 */
+  __IO  uint32_t ERR_MASK5;                      /**< SOCEU error mask MSB register, offset: 0x78 */
+  __IO  uint32_t ERR_MASK6;                      /**< SOCEU error mask MSB register, offset: 0x7c */
+  __IO  uint32_t ERR_MASK7;                      /**< SOCEU error mask MSB register, offset: 0x80 */
+  __IO  uint32_t TIMER_SEL_HI;                   /**< SOCEU timer high register, offset: 0x84 */
+  __IO  uint32_t TIMER_SEL_LO;                   /**< SOCEU timer low register, offset: 0x88 */
+} SOCEU_Type;
+
+#define SOC_EVENT_OFFSET 0x00
+#define SOC_FC_MASK0_OFFSET 0x04
+#define SOC_CL_MASK0_OFFSET 0x24
+#define SOC_PR_MASK0_OFFSET 0x44
+#define SOC_ERR_MASK0_OFFSET 0x64
+
+/* ----------------------------------------------------------------------------
+   -- SOCEU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SOCEU_Register_Masks SOCEU Register Masks
+ * @{
+ */
+/* The SOC events number */
+#define SOC_EVENTS_NUM              0x08
+/*!
+ * @}
+ */ /* end of group SOCEU_Register_Masks */
+
+
+/* SOCEU - Peripheral instance base addresses */
+/** Peripheral SOCEU base address */
+#define SOCEU_BASE                               SOC_EU_ADDR
+/** Peripheral SOCEU base pointer */
+#define SOCEU                                    ((SOCEU_Type *)SOCEU_BASE)
+/** Array initializer of SOCEU base addresses */
+#define SOCEU_BASE_ADDRS                         { SOCEU_BASE }
+/** Array initializer of SOCEU base pointers */
+#define SOCEU_BASE_PTRS                          { SOCEU }
+
+/*!
+ * @}
+ */ /* end of group SOCEU_Peripheral_Access_Layer */
+
+
+
+/* ----------------------------------------------------------------------------
+   -- SW EVENT TRIGGER Register Address
+   ---------------------------------------------------------------------------- */
+
+#define EU_EVT_GETCLUSTERBASE(coreId)     (0x00200800u + (coreId << 6))
+
+
+/* ----------------------------------------------------------------------------
+   -- PMU DLC Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMU_DLC_Peripheral_Access_Layer PMU_DLC Peripheral Access_Layer
+ * @{
+ */
+
+/** PMU - General Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCTRL;                          /**< PMU DLC control register, offset: 0x00 */
+  __IO uint32_t PRDATA;                         /**< PMU DLC data register, offset: 0x04 */
+  __IO uint32_t DLC_SR;                         /**< PMU DLC register, offset: 0x08 */
+  __IO uint32_t DLC_IMR;                        /**< PMU DLC register, offset: 0x0C */
+  __IO uint32_t DLC_IFR;                        /**< PMU DLC register, offset: 0x10 */
+  __IO uint32_t DLC_IOIFR;                      /**< PMU DLC register, offset: 0x14 */
+  __IO uint32_t DLC_IDIFR;                      /**< PMU DLC register, offset: 0x18 */
+  __IO uint32_t DLC_IMCIFR;                     /**< PMU DLC register, offset: 0x1C */
+
+} PMU_DLC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SOCEU Register Masks
+   ---------------------------------------------------------------------------- */
+/*!
+ * @addtogroup PMU_DLC_Register_Masks PMU_DLC Register Masks
+ * @{
+ */
+
+/*! @name PCTRL - PMU DLC PICL control register */
+#define PMU_DLC_PCTRL_START_MASK              (0x1U)
+#define PMU_DLC_PCTRL_START_SHIFT             (0U)
+#define PMU_DLC_PCTRL_START(x)                (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_PCTRL_START_SHIFT */)) & PMU_DLC_PCTRL_START_MASK)
+#define PMU_DLC_PCTRL_PADDR_MASK              (0x7FFEU)
+#define PMU_DLC_PCTRL_PADDR_SHIFT             (1U)
+#define PMU_DLC_PCTRL_PADDR(x)                (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PCTRL_PADDR_SHIFT)) & PMU_DLC_PCTRL_PADDR_MASK)
+#define PMU_DLC_PCTRL_DIR_MASK                (0x8000U)
+#define PMU_DLC_PCTRL_DIR_SHIFT               (15U)
+#define PMU_DLC_PCTRL_DIR(x)                  (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PCTRL_DIR_SHIFT)) & PMU_DLC_PCTRL_DIR_MASK)
+#define PMU_DLC_PCTRL_PWDATA_MASK             (0xFFFF0000U)
+#define PMU_DLC_PCTRL_PWDATA_SHIFT            (16U)
+#define PMU_DLC_PCTRL_PWDATA(x)               (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PCTRL_PWDATA_SHIFT)) & PMU_DLC_PCTRL_PWDATA_MASK)
+
+/*! @name PRDATA - PMU DLC PICL data read register */
+#define PMU_DLC_PRDATA_PRDATA_MASK            (0xFFU)
+#define PMU_DLC_PRDATA_PRDATA_SHIFT           (0U)
+#define PMU_DLC_PRDATA_PRDATA(x)              (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_PRDATA_PRDATA_SHIFT */)) & PMU_DLC_PRDATA_PRDATA_MASK)
+
+/*! @name SR - PMU DLC DLC Status register */
+#define PMU_DLC_SR_PICL_BUSY_MASK             (0x1U)
+#define PMU_DLC_SR_PICL_BUSY_SHIFT            (0U)
+#define PMU_DLC_SR_PICL_BUSY(x)               (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_SR_PICL_BUSY_SHIFT */)) & PMU_DLC_SR_PICL_BUSY_MASK)
+#define PMU_DLC_SR_SCU_BUSY_MASK              (0x2U)
+#define PMU_DLC_SR_SCU_BUSY_SHIFT             (1U)
+#define PMU_DLC_SR_SCU_BUSY(x)                (((uint32_t)(((uint32_t)(x)) << PMU_DLC_SR_SCU_BUSY_SHIFT)) & PMU_DLC_SR_SCU_BUSY_MASK)
+
+/*! @name IMR - PMU DLC Interrupt mask register */
+#define PMU_DLC_IMR_ICU_OK_MASK_MASK          (0x1U)
+#define PMU_DLC_IMR_ICU_OK_MASK_SHIFT         (0U)
+#define PMU_DLC_IMR_ICU_OK_MASK(x)            (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_IMR_ICU_OK_MASK_SHIFT */)) & PMU_DLC_IMR_ICU_OK_MASK_MASK)
+#define PMU_DLC_IMR_ICU_DELAYED_MASK_MASK     (0x2U)
+#define PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT    (1U)
+#define PMU_DLC_IMR_ICU_DELAYED_MASK(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_ICU_DELAYED_MASK_SHIFT)) & PMU_DLC_IMR_ICU_DELAYED_MASK_MASK)
+#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK     (0x4U)
+#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT    (2U)
+#define PMU_DLC_IMR_ICU_MODE_CHANGED_MASK(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_SHIFT)) & PMU_DLC_IMR_ICU_MODE_CHANGED_MASK_MASK)
+#define PMU_DLC_IMR_PICL_OK_MASK_MASK         (0x8U)
+#define PMU_DLC_IMR_PICL_OK_MASK_SHIFT        (3U)
+#define PMU_DLC_IMR_PICL_OK_MASK(x)           (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_PICL_OK_MASK_SHIFT)) & PMU_DLC_IMR_PICL_OK_MASK_MASK)
+#define PMU_DLC_IMR_SCU_OK_MASK_MASK          (0x10U)
+#define PMU_DLC_IMR_SCU_OK_MASK_SHIFT         (4U)
+#define PMU_DLC_IMR_SCU_OK_MASK(x)            (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMR_SCU_OK_MASK_SHIFT)) & PMU_DLC_IMR_SCU_OK_MASK_MASK)
+
+/*! @name IFR - PMU DLC Interrupt flag register */
+#define PMU_DLC_IFR_ICU_OK_FLAG_MASK          (0x1U)
+#define PMU_DLC_IFR_ICU_OK_FLAG_SHIFT         (0U)
+#define PMU_DLC_IFR_ICU_OK_FLAG(x)            (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_IFR_ICU_OK_FLAG_SHIFT */)) & PMU_DLC_IFR_ICU_OK_FLAG_MASK)
+#define PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK     (0x2U)
+#define PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT    (1U)
+#define PMU_DLC_IFR_ICU_DELAYED_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_ICU_DELAYED_FLAG_SHIFT)) & PMU_DLC_IFR_ICU_DELAYED_FLAG_MASK)
+#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK     (0x4U)
+#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT    (2U)
+#define PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_SHIFT)) & PMU_DLC_IFR_ICU_MODE_CHANGED_FLAG_MASK)
+#define PMU_DLC_IFR_PICL_OK_FLAG_MASK         (0x8U)
+#define PMU_DLC_IFR_PICL_OK_FLAG_SHIFT        (3U)
+#define PMU_DLC_IFR_PICL_OK_FLAG(x)           (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_PICL_OK_FLAG_SHIFT)) & PMU_DLC_IFR_PICL_OK_FLAG_MASK)
+#define PMU_DLC_IFR_SCU_OK_FLAG_MASK          (0x10U)
+#define PMU_DLC_IFR_SCU_OK_FLAG_SHIFT         (4U)
+#define PMU_DLC_IFR_SCU_OK_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IFR_SCU_OK_FLAG_SHIFT)) & PMU_DLC_IFR_SCU_OK_FLAG_MASK)
+
+/*! @name IOIFR - PMU DLC icu_ok interrupt flag register */
+#define PMU_DLC_IOIFR_ICU_OK_FLAG_MASK          (0xFFFFFFFEU)
+#define PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT         (1U)
+#define PMU_DLC_IOIFR_ICU_OK_FLAG(x)            (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IOIFR_ICU_OK_FLAG_SHIFT)) & PMU_DLC_IOIFR_ICU_OK_FLAG_MASK)
+
+/*! @name IDIFR - PMU DLC icu_delayed interrupt flag register */
+#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK     (0xFFFFFFFEU)
+#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT    (1U)
+#define PMU_DLC_IDIFR_ICU_DELAYED_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IDIFR_ICU_DELAYED_FLAG_SHIFT)) & PMU_DLC_IDIFR_ICU_DELAYED_FLAG_MASK)
+
+/*! @name IMCIFR - PMU DLC icu_mode changed interrupt flag register */
+#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK     (0xFFFFFFFEU)
+#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT    (1U)
+#define PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_SHIFT)) & PMU_DLC_IMCIFR_ICU_MODE_CHANGED_FLAG_MASK)
+
+/*! @name PCTRL_PADDR The address to write in the DLC_PADDR register is CHIP_SEL_ADDR[4:0] concatenated with REG_ADDR[4:0]. */
+#define PMU_DLC_PICL_REG_ADDR_MASK          (0x1FU)
+#define PMU_DLC_PICL_REG_ADDR_SHIFT         (0U)
+#define PMU_DLC_PICL_REG_ADDR(x)            (((uint32_t)(((uint32_t)(x)) /* << PMU_DLC_PICL_REG_ADDR_SHIFT */)) & PMU_DLC_PICL_REG_ADDR_MASK)
+#define PMU_DLC_PICL_CHIP_SEL_ADDR_MASK     (0x3E0U)
+#define PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT    (5U)
+#define PMU_DLC_PICL_CHIP_SEL_ADDR(x)       (((uint32_t)(((uint32_t)(x)) << PMU_DLC_PICL_CHIP_SEL_ADDR_SHIFT)) & PMU_DLC_PICL_CHIP_SEL_ADDR_MASK)
+
+/* CHIP_SEL_ADDR[4:0]*/
+#define  PICL_WIU_ADDR         0x00
+#define  PICL_ICU_ADDR         0x01
+
+/* REG_ADDR[4:0]*/
+#define  WIU_ISPMR_0           (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x00))
+#define  WIU_ISPMR_1           (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x01))
+#define  WIU_IFR_0             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x02))
+#define  WIU_IFR_1             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x03))
+#define  WIU_ICR_0             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x04))
+#define  WIU_ICR_1             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x05))
+#define  WIU_ICR_2             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x06))
+#define  WIU_ICR_3             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x07))
+#define  WIU_ICR_4             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x08))
+#define  WIU_ICR_5             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x09))
+#define  WIU_ICR_6             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0A))
+#define  WIU_ICR_7             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0B))
+#define  WIU_ICR_8             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0C))
+#define  WIU_ICR_9             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0D))
+#define  WIU_ICR_10            (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0E))
+#define  WIU_ICR_11            (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x0F))
+#define  WIU_ICR_12            (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x10))
+#define  WIU_ICR_13            (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x11))
+#define  WIU_ICR_14            (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x12))
+#define  WIU_ICR_15            (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_WIU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x13))
+
+/* REG_ADDR[4:0]*/
+#define  ICU_CR                (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x00))
+#define  ICU_MR                (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x01))
+#define  ICU_ISMR              (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x02))
+#define  ICU_DMR_0             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x03))
+#define  ICU_DMA_1             (PMU_DLC_PICL_CHIP_SEL_ADDR(PICL_ICU_ADDR) | PMU_DLC_PICL_REG_ADDR(0x04))
+
+/*!
+ * @}
+ */ /* end of group PMU_DLC_Register_Masks */
+
+/* PMU DLC- Peripheral instance base addresses */
+/** Peripheral PMU DLC base address */
+#define PMU_DLC_BASE                                (SOC_PERIPHERALS_ADDR + 0x7000u)
+/** Peripheral PMU_DLC base pointer */
+#define PMU_DLC                                     ((PMU_DLC_Type *)PMU_DLC_BASE)
+/** Array initializer of PMU_DLC base addresses */
+#define PMU_DLC_BASE_ADDRS                          { PMU_DLC_BASE }
+/** Array initializer of PMU_DLC base pointers */
+#define PMU_DLC_BASE_PTRS                           { PMU_DLC }
+
+/*!
+ * @}
+ */ /* end of group PMU_DLC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC_APB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+/* #include "periph/rtc_periph.h" */
+/* #define rtc(id) ((rtc_t *) RTC_ADDR) */
+
+
+/* ----------------------------------------------------------------------------
+   -- EFUSE CTRL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EFUSE_CTRL_Peripheral_Access_Layer EFUSE_CTRL Peripheral Access Layer
+ * @{
+ */
+
+
+
+//#include "periph/efuse_periph.h"
+
+/* EFUSE_CTRL - Peripheral instance base addresses */
+/** Peripheral EFUSE_CTRL base address */
+#define EFUSE_CTRL_BASE                               (SOC_PERIPHERALS_ADDR + 0x09000u)
+/** Peripheral EFUSE_CTRL base pointer */
+#define efuse_ctrl                                    ((efuse_ctrl_t *)EFUSE_CTRL_BASE)
+/** Array initializer of EFUSE_CTRL base addresses */
+#define EFUSE_CTRL_BASE_ADDRS                         { EFUSE_CTRL_BASE }
+/** Array initializer of EFUSE_CTRL base pointers */
+#define EFUSE_CTRL_BASE_PTRS                          { EFUSE_CTRL }
+
+/*!
+ * @}
+ */ /* end of group EFUSE_CTRL_Peripheral_Access_Layer */
+
+
+/* EFUSE_REGS - Peripheral instance base addresses */
+/** Peripheral EFUSE_REGS base address */
+#define EFUSE_REGS_BASE                                (SOC_PERIPHERALS_ADDR + 0x09200u)
+/** Peripheral EFUSE_REGS base pointer */
+#define efuse_regs                                     ((efuse_regs_t *)EFUSE_REGS_BASE)
+#define efuse_regs_array                               ((int32_t*)EFUSE_REGS_BASE)
+/** Array initializer of EFUSE_REGS base addresses */
+#define EFUSE_REGS_BASE_ADDRS                          { EFUSE_REGS_BASE }
+/** Array initializer of EFUSE_REGS base pointers */
+#define EFUSE_REGS_BASE_PTRS                           { EFUSE_REGS }/*!
+ * @}
+ */ /* end of group EFUSE_CTRL_Peripheral_Access_Layer */
+
+
+
+/* ----------------------------------------------------------------------------
+   -- EFUSE REG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EFUSE_REGS_Peripheral_Access_Layer EFUSE_REGS Peripheral Access Layer
+ * @{
+ */
+
+/** EFUSE_REGS - Registers Layout Typedef */
+typedef struct {
+  __IO  uint32_t INFO;                    /**< EFUSE INFO register, offset: 0x000 */
+  __IO  uint32_t INFO2;                   /**< EFUSE_INFO2 register, offset: 0x004 */
+  __IO  uint32_t AES_KEY[16];             /**< EFUSE_AES_KEY registers, offset: 0x008 */
+  __IO  uint32_t AES_IV[8];               /**< EFUSE_AES_IV registers, offset: 0x048 */
+  __IO  uint32_t WAIT_XTAL_DELTA_LSB;     /**< EFUSE_WAIT_XTAL_DELTA_LSB register, offset: 0x068 */
+  __IO  uint32_t WAIT_XTAL_DELTA_MSB;     /**< EFUSE_WAIT_XTAL_DELTA_MSB register, offset: 0x06C */
+  __IO  uint32_t WAIT_XTAL_MIN;           /**< EFUSE_WAIT_XTAL_MIN registers, offset: 0x070 */
+  __IO  uint32_t WAIT_XTAL_MAX;           /**< EFUSE_WAIT_XTAL_MAX registers, offset: 0x074 */
+  __IO  uint32_t HYPER_RDS_DELAY;         /**< EFUSE_WAIT_XTAL_MAX registers, offset: 0x078 */
+  __IO  uint32_t FLL_FREQ;                /**< EFUSE_FLL_FREQ registers, offset: 0x07C */
+  __IO  uint32_t FLL_TOLERANCE;           /**< EFUSE_FLL_TOLERANCE registers, offset: 0x080 */
+  __IO  uint32_t FLL_ASSERT_CYCLE;        /**< EFUSE_FLL_ASSERT_CYCLE registers, offset: 0x084 */
+  __IO  uint32_t _reserved[6];            /**< EFUSE_reserved registers, offset: 0x088 */
+  __IO  uint32_t USER_REG[88];            /**< EFUSE_USER_REG, offset: 0x0A0 */
+} EFUSE_REGS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EFUSE_REGS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EFUSE_REGS_Register_Masks EFUSE_REGS Register Masks
+ * @{
+ */
+/*! @name INFO - EFUSE information register */
+#define EFUSE_INFO_PLT_MASK                           (0x07U)
+#define EFUSE_INFO_PLT_SHIFT                          (0U)
+#define EFUSE_INFO_PLT(x)                             (((uint32_t)(((uint32_t)(x)) /* << EFUSE_INFO_PLT_SHIFT */)) & EFUSE_INFO_PLT_MASK)
+
+#define EFUSE_INFO_BOOT_MASK                          (0x38U)
+#define EFUSE_INFO_BOOT_SHIFT                         (3U)
+#define EFUSE_INFO_BOOT(x)                            (((uint32_t)(((uint32_t)(x)) << EFUSE_INFO_BOOT_SHIFT)) & EFUSE_INFO_BOOT_MASK)
+
+#define EFUSE_INFO_ENCRYPTED_MASK                     (0x40U)
+#define EFUSE_INFO_ENCRYPTED_SHIFT                    (6U)
+#define EFUSE_INFO_ENCRYPTED(x)                       (((uint32_t)(((uint32_t)(x)) << EFUSE_INFO_ENCRYPTED_SHIFT)) & EFUSE_INFO_ENCRYPTED_MASK)
+
+#define EFUSE_INFO_WAIT_XTAL_MASK                     (0x80U)
+#define EFUSE_INFO_WAIT_XTAL_SHIFT                    (7U)
+#define EFUSE_INFO_WAIT_XTAL(x)                       (((uint32_t)(((uint32_t)(x)) << EFUSE_INFO_WAIT_XTAL_SHIFT)) & EFUSE_INFO_WAIT_XTAL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EFUSE_REGS_Register_Masks */
+
+
+/* EFUSE_REGS - Peripheral instance base addresses */
+/** Peripheral EFUSE_REGS base address */
+#define EFUSE_REGS_BASE                                (SOC_PERIPHERALS_ADDR + 0x09200u)
+/** Peripheral EFUSE_REGS base pointer */
+#define EFUSE_REGS                                     ((EFUSE_REGS_Type *)EFUSE_REGS_BASE)
+/** Array initializer of EFUSE_REGS base addresses */
+#define EFUSE_REGS_BASE_ADDRS                          { EFUSE_REGS_BASE }
+/** Array initializer of EFUSE_REGS base pointers */
+#define EFUSE_REGS_BASE_PTRS                           { EFUSE_REGS }
+
+/*!
+ * @}
+ */ /* end of group EFUSE_REGS_Peripheral_Access_Layer */
+
+
+
+/* ----------------------------------------------------------------------------
+   -- FC_STDOUT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FC_STDOUT_Peripheral_Access_Layer FC_STDOUT Peripheral Access Layer
+ * @{
+ */
+
+/** FC_STDOUT - Registers Layout Typedef */
+typedef struct {
+  __IO  uint32_t PUTC[16];                    /**< FC_STDOUT INFO register, offset: 0x000 */
+} FC_STDOUT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FC_STDOUT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FC_STDOUT_Register_Masks FC_STDOUT Register Masks
+ * @{
+ */
+/*! @name INFO - FC_STDOUT information register */
+
+/*!
+ * @}
+ */ /* end of group FC_STDOUT_Register_Masks */
+
+
+/* FC_STDOUT - Peripheral instance base addresses */
+/** Peripheral FC_STDOUT base address */
+#define FC_STDOUT_BASE                                (SOC_PERIPHERALS_ADDR + 0x10000u + (FC_CLUSTER_ID << 7))
+/** Peripheral FC_STDOUT base pointer */
+#define FC_STDOUT                                     ((FC_STDOUT_Type *)FC_STDOUT_BASE)
+/** Array initializer of FC_STDOUT base addresses */
+#define FC_STDOUT_BASE_ADDRS                          { FC_STDOUT_BASE }
+/** Array initializer of FC_STDOUT base pointers */
+#define FC_STDOUT_BASE_PTRS                           { FC_STDOUT }
+
+/*!
+ * @}
+ */ /* end of group FC_STDOUT_Peripheral_Access_Layer */
+
+
+#ifdef FEATURE_CLUSTER
+/* ----------------------------------------------------------------------------
+   -- CLUSTER_STDOUT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLUSTER_STDOUT_Peripheral_Access_Layer CLUSTER_STDOUT Peripheral Access Layer
+ * @{
+ */
+
+/** CLUSTER_STDOUT - Registers Layout Typedef */
+typedef struct {
+  __IO  uint32_t PUTC[16];                    /**< CLUSTER_STDOUT INFO register, offset: 0x000 */
+} CLUSTER_STDOUT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CLUSTER_STDOUT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CLUSTER_STDOUT_Register_Masks CLUSTER_STDOUT Register Masks
+ * @{
+ */
+/*! @name INFO - CLUSTER_STDOUT information register */
+
+/*!
+ * @}
+ */ /* end of group CLUSTER_STDOUT_Register_Masks */
+
+
+/* CLUSTER_STDOUT - Peripheral instance base addresses */
+/** Peripheral CLUSTER_STDOUT base address */
+#define CLUSTER_STDOUT_BASE                                (SOC_PERIPHERALS_ADDR + 0x10000u)
+/** Peripheral CLUSTER_STDOUT base pointer */
+#define CLUSTER_STDOUT                                     ((CLUSTER_STDOUT_Type *)CLUSTER_STDOUT_BASE)
+/** Array initializer of CLUSTER_STDOUT base addresses */
+#define CLUSTER_STDOUT_BASE_ADDRS                          { CLUSTER_STDOUT_BASE }
+/** Array initializer of CLUSTER_STDOUT base pointers */
+#define CLUSTER_STDOUT_BASE_PTRS                           { CLUSTER_STDOUT }
+
+/*!
+ * @}
+ */ /* end of group CLUSTER_STDOUT_Peripheral_Access_Layer */
+
+
+
+
+/* ----------------------------------------------------------------------------
+   -- HWCE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup HWCE Peripheral_Access_Layer HWCE Peripheral Access Layer
+ * @{
+ */
+
+/** HWCE - Registers Layout Typedef */
+typedef struct {
+    __IO  uint32_t HWCE_TRIGGER_REG;              /**< HWCE Trigger register, offset: 0x00 */
+    __IO  uint32_t HWCE_ACQUIRE_REG;              /**< HWCE Acquire register, offset: 0x04 */
+    __IO  uint32_t HWCE_FINISHED_REG;             /**< HWCE Finished register, offset: 0x08 */
+    __IO  uint32_t HWCE_STATUS_REG;               /**< HWCE Status register, offset: 0x0C */
+    __IO  uint32_t HWCE_RUNNING_JOB_REG;          /**< HWCE Running Job register, offset: 0x10 */
+    __IO  uint32_t HWCE_SOFT_CLEAR_REG;           /**< HWCE Soft_Clear register, offset: 0x14 */
+    __IO  uint32_t _reserved0[2];                 /**< HWCE Non used registers, offser: 0x18 */
+    __IO  uint32_t HWCE_GEN_CONFIG0_REG;          /**< HWCE Gen_Config0 register, offset: 0x20 */
+    __IO  uint32_t HWCE_GEN_CONFIG1_REG;          /**< HWCE Gen_Config1 register, offset: 0x24 */
+    __IO  uint32_t _reserved1[6];                 /**< HWCE unused registers, offset: 0x28 */
+    __IO  uint32_t HWCE_Y_TRANS_SIZE_REG;         /**< HWCE Y_Trans_Size register, offset: 0x40 */
+    __IO  uint32_t HWCE_Y_LINE_STRIDE_LENGTH_REG; /**< HWCE Y_Line_Stride_Length register, offset: 0x44 */
+    __IO  uint32_t HWCE_Y_FEAT_STRIDE_LENGTH_REG; /**< HWCE Y_Feat_Stride_Length register, offset: 0x48 */
+    __IO  uint32_t HWCE_Y_OUT_3_REG;              /**< HWCE Y_Out_3 register, offset: 0x4C */
+    __IO  uint32_t HWCE_Y_OUT_2_REG;              /**< HWCE Y_Out_2 register, offset: 0x50 */
+    __IO  uint32_t HWCE_Y_OUT_1_REG;              /**< HWCE Y_Out_1 register, offset: 0x54 */
+    __IO  uint32_t HWCE_Y_OUT_0_REG;              /**< HWCE Y_Out_0 register, offset: 0x58 */
+    __IO  uint32_t HWCE_Y_IN_3_REG;               /**< HWCE Y_In_3 register, offset: 0x5C */
+    __IO  uint32_t HWCE_Y_IN_2_REG;               /**< HWCE Y_In_2 register, offset: 0x60 */
+    __IO  uint32_t HWCE_Y_IN_1_REG;               /**< HWCE Y_In_1 register, offset: 0x64 */
+    __IO  uint32_t HWCE_Y_IN_0_REG;               /**< HWCE Y_In_0 register, offset: 0x68 */
+    __IO  uint32_t HWCE_X_TRANS_SIZE_REG;         /**< HWCE X_Trans_Size register, offset: 0x6C */
+    __IO  uint32_t HWCE_X_LINE_STRIDE_LENGTH_REG; /**< HWCE X_Line_Stride_Length register, offset: 0x70 */
+    __IO  uint32_t HWCE_X_FEAT_STRIDE_LENGTH_REG; /**< HWCE X_Feat_Stride_Length register, offset: 0x74 */
+    __IO  uint32_t HWCE_X_IN_REG;                 /**< HWCE X_In register, offset: 0x78 */
+    __IO  uint32_t HWCE_W_REG;                    /**< HWCE W register, offset: 0x7C */
+    __IO  uint32_t HWCE_JOB_CONFIG0_REG;          /**< HWCE Job_Config0 register, offset: 0x80 */
+    __IO  uint32_t HWCE_JOB_CONFIG1_REG;          /**< HWCE Job_Config1 register, offset: 0x84 */
+} HWCE_Type;
+
+
+/* ----------------------------------------------------------------------------
+   -- HWCE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup HWCE_Register_Masks HWCE Register Masks
+ * @{
+ */
+/*! @name INFO - HWCE information register */
+/* Internal registers */
+#define HWCE_TRIGGER              ( 0x00 )
+#define HWCE_ACQUIRE              ( 0x04 )
+#define HWCE_FINISHED             ( 0x08 )
+#define HWCE_STATUS               ( 0x0C )
+#define HWCE_RUNNING_JOB          ( 0x10 )
+#define HWCE_SOFT_CLEAR           ( 0x14 )
+#define HWCE_GEN_CONFIG0          ( 0x20 )
+#define HWCE_GEN_CONFIG1          ( 0x24 )
+
+/* Configuration registers */
+#define HWCE_Y_TRANS_SIZE         ( 0x40 )
+#define HWCE_Y_LINE_STRIDE_LENGTH ( 0x44 )
+#define HWCE_Y_FEAT_STRIDE_LENGTH ( 0x48 )
+#define HWCE_Y_OUT_3_BASE_ADDR    ( 0x4C )
+#define HWCE_Y_OUT_2_BASE_ADDR    ( 0x50 )
+#define HWCE_Y_OUT_1_BASE_ADDR    ( 0x54 )
+#define HWCE_Y_OUT_0_BASE_ADDR    ( 0x58 )
+#define HWCE_Y_IN_3_BASE_ADDR     ( 0x5C )
+#define HWCE_Y_IN_2_BASE_ADDR     ( 0x60 )
+#define HWCE_Y_IN_1_BASE_ADDR     ( 0x64 )
+#define HWCE_Y_IN_0_BASE_ADDR     ( 0x68 )
+#define HWCE_X_TRANS_SIZE         ( 0x6C )
+#define HWCE_X_LINE_STRIDE_LENGTH ( 0x70 )
+#define HWCE_X_FEAT_STRIDE_LENGTH ( 0x74 )
+#define HWCE_X_IN_BASE_ADDR       ( 0x78 )
+#define HWCE_W_BASE_ADDR          ( 0x7C )
+#define HWCE_JOB_CONFIG0          ( 0x80 )
+#define HWCE_JOB_CONFIG1          ( 0x84 )
+
+#define HWCE_NB_IO_REGS           ( 18 )
+
+#define HWCE_ACQUIRE_CONTEXT_COPY ( -3 )
+#define HWCE_ACQUIRE_LOCKED       ( -2 )
+#define HWCE_ACQUIRE_QUEUE_FULL   ( -1 )
+#define HWCE_ACQUIRE_READY        ( 0 )
+
+#define HWCE_GEN_CONFIG0_WSTRIDE(x)           ((x) >> 16)
+#define HWCE_GEN_CONFIG0_NCP(x)               (((x) >> 13) & 0x1)
+#define HWCE_GEN_CONFIG0_CONV(x)              (((x) >> 11) & 0x3)
+#define HWCE_GEN_CONFIG0_VECT(x)              (((x) >> 9) & 0x3)
+#define HWCE_GEN_CONFIG0_UNS(x)               (((x) >> 8) & 1)
+#define HWCE_GEN_CONFIG0_NY(x)                (((x) >> 7) & 1)
+#define HWCE_GEN_CONFIG0_NF(x)                (((x) >> 6) & 1)
+#define HWCE_GEN_CONFIG0_QF(x)                ((x) & 0x3f)
+
+#define HWCE_GEN_CONFIG0_CONV_5x5 ( 0 )
+#define HWCE_GEN_CONFIG0_CONV_3x3 ( 1 )
+#define HWCE_GEN_CONFIG0_CONV_4x7 ( 2 )
+
+#define HWCE_GEN_CONFIG0_VECT_1   ( 0 )
+#define HWCE_GEN_CONFIG0_VECT_2   ( 1 )
+#define HWCE_GEN_CONFIG0_VECT_4   ( 2 )
+
+#define HWCE_GEN_CONFIG1_PIXSHIFTR(x)         (((x) >> 16) & 0x1F)
+#define HWCE_GEN_CONFIG1_PIXMODE(x)           (((x) >> 8) & 0x3)
+#define HWCE_GEN_CONFIG1_PIXSHIFTL(x)         (((x) >> 0) & 0x1F)
+
+#define HWCE_JOB_CONFIG0_NOYCONST(x)          ((x) >> 16)
+#define HWCE_JOB_CONFIG0_LBUFLEN(x)           ((x) & 0x3ff)
+
+#define HWCE_JOB_CONFIG1_LO(x)                (((x) >> 24) & 0x1)
+#define HWCE_JOB_CONFIG1_WIF(x)               (((x) >> 16) & 0x3F)
+#define HWCE_JOB_CONFIG1_WOF(x)               (((x) >> 8) & 0x1F)
+#define HWCE_JOB_CONFIG1_VECT_DISABLE_MASK(x) (((x) >> 0) & 0xF)
+
+#define HWCE_JOB_STRIDE(x)                    ((x) >> 16)
+#define HWCE_JOB_LENGTH(x)                    ((x) & 0xffff)
+
+  /*!
+   * @}
+   */ /* end of group HWCE_Register_Masks */
+
+
+/* HWCE - Peripheral instance base addresses */
+/** Peripheral HWCE base address */
+#define HWCE_BASE                                (CORE_PERI_BASE + 0x00001000)
+/** Peripheral HWCE base pointer */
+#define HWCE                                     ((HWCE_Type *) HWCE_BASE)
+/** Array initializer of HWCE base addresses */
+#define HWCE_BASE_ADDRS                          { HWCE_BASE }
+/** Array initializer of HWCE base pointers */
+#define HWCE_BASE_PTRS                           { HWCE }
+
+/*!
+ * @}
+ */ /* end of group HWCE_Peripheral_Access_Layer */
+
+
+#endif
+
+
+/*
+** End of section using anonymous unions
+*/
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+
+
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h

@@ -0,0 +1,188 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_
+
+
+//#include "pmsis/rtos/os_frontend_api/os.h"
+//#include "pmsis/backend/implementation_specific_defines.h"
+//#include "pmsis/backend/pmsis_backend_native_task_api.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function declaration
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API implementation
+ ******************************************************************************/
+
+//static inline int pmsis_kickoff(void *arg)
+//{
+//    return __os_native_kickoff(arg);
+//}
+
+//static inline void pmsis_exit(int err)
+//{
+//    __os_native_exit(err);
+//}
+
+//static inline void *pmsis_task_create(void (*entry)(void*),
+//        void *arg,
+//        char *name,
+//        int priority)
+//{
+//    return __os_native_api_create_task(entry, arg, name, priority);
+//}
+
+//static inline void pmsis_task_suspend(void *task_handler)
+//{
+//    __os_native_task_t *task = (__os_native_task_t *) task_handler;
+//    __os_native_task_suspend(task);
+//}
+
+//static inline void pi_yield()
+//{
+//    __os_native_yield();
+//}
+
+//static inline int disable_irq(void)
+//{
+//    hal_compiler_barrier();
+//    return __os_native_api_disable_irq();
+//}
+
+//static inline void restore_irq(int irq_enable)
+//{
+//    hal_compiler_barrier();
+//    __os_native_api_restore_irq(irq_enable);
+//}
+//
+//static inline int pi_sem_init(pi_sem_t *sem)
+//{
+//    hal_compiler_barrier();
+//    return  __os_native_api_sem_init(sem);
+//}
+//
+//static inline int pi_sem_deinit(pi_sem_t *sem)
+//{
+//    hal_compiler_barrier();
+//    return  __os_native_api_sem_deinit(sem);
+//}
+//
+//static inline void pi_sem_take(pi_sem_t *sem)
+//{
+//    hal_compiler_barrier();
+//    sem->take(sem->sem_object);
+//}
+//
+//static inline void pi_sem_give(pi_sem_t *sem)
+//{
+//    sem->give(sem->sem_object);
+//    hal_compiler_barrier();
+//}
+
+//static inline void pmsis_mutex_take(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    int irq_enabled;
+//    volatile int mutex_free=0;
+//    while (!mutex_free)
+//    {
+//        irq_enabled = disable_irq();
+//        hal_compiler_barrier();
+//        mutex_free = !((volatile uint32_t)mutex->mutex_object);
+//        hal_compiler_barrier();
+//        restore_irq(irq_enabled);
+//    }
+//    irq_enabled = disable_irq();
+//    mutex->mutex_object = (void*)1;
+//    restore_irq(irq_enabled);
+//#else
+//    mutex->take(mutex->mutex_object);
+//#endif
+//}
+//
+//static inline void pmsis_mutex_release(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    int irq_enabled = disable_irq();
+//    hal_compiler_barrier();
+//    mutex->mutex_object = (void*)0;
+//    hal_compiler_barrier();
+//    restore_irq(irq_enabled);
+//#else
+//    mutex->release(mutex->mutex_object);
+//    hal_compiler_barrier();
+//#endif
+//}
+//
+//static inline int pmsis_mutex_init(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    mutex->mutex_object = (void*)0;
+//    return 0;
+//#else
+//    return  __os_native_api_mutex_init(mutex);
+//#endif
+//}
+//
+//static inline int pmsis_mutex_deinit(pmsis_mutex_t *mutex)
+//{
+//    hal_compiler_barrier();
+//#ifdef __NO_NATIVE_MUTEX__
+//    mutex->mutex_object = (void*)0;
+//    return 0;
+//#else
+//    return  __os_native_api_mutex_deinit(mutex);
+//#endif
+//}
+//
+//static inline void pmsis_spinlock_init(pmsis_spinlock_t *spinlock)
+//{
+//    hal_compiler_barrier();
+//    spinlock->lock = 0;
+//}
+//
+//static inline void pmsis_spinlock_take(pmsis_spinlock_t *spinlock)
+//{
+//    int irq_enabled = disable_irq();
+//    hal_compiler_barrier();
+//    spinlock->lock = 1;
+//    hal_compiler_barrier();
+//    restore_irq(irq_enabled);
+//}
+//
+//static inline void pmsis_spinlock_release(pmsis_spinlock_t *spinlock)
+//{
+//    int irq_enabled = disable_irq();
+//    hal_compiler_barrier();
+//    spinlock->lock = 0;
+//    hal_compiler_barrier();
+//    restore_irq(irq_enabled);
+//}
+
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_RTOS_OS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pmsis.h

@@ -0,0 +1,68 @@
+/*
+ * Copyright 2019 GreenWaves Technologies
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_
+
+#include <stddef.h>
+#include <inttypes.h>
+
+/* Debug helper. */
+#ifdef DEBUG
+#define DEBUG_PRINTF printf
+#else
+#define DEBUG_PRINTF(...) ((void) 0)
+#endif  /* DEBUG */
+
+#if (!defined(HW_VERIF_ONLY))
+
+/* Backend includes. */
+//#include "pmsis/backend/implementation_specific_defines.h"
+//#include "hal/include/hal_target.h"
+/* pmsis_api includes. */
+//#include "pmsis/device.h"
+//#include "pmsis/task.h"
+//#include "pmsis_types.h"
+//#include "../../../pmsis_api/include/pmsis/rtos/rtos-orig.h"
+//#include "pmsis/rtos/assert.h"
+//#include "pmsis/mem_slab.h"
+
+/* PMSIS includes. */
+//#include "pmsis/implem/debug.h"
+//#include "pmsis/implem/drivers/drivers_data.h"
+//#include "hal/include/hal_pmsis_drivers.h"
+	#include "hal_fc_event.h"
+	#include "hal_fll_pi.h"
+	#include "hal_i2c_internal.h"
+	#include "hal_uart_internal.h"
+//#include "pmsis/rtos/os/pmsis_task.h"
+//#include "pmsis/rtos/os/pmsis_freq.h"
+//#include "target/core-v-mcu/include/core-v-mcu-pmsis-rtos-os.h"
+//#include "hal/include/hal_native_task_api.h"
+#if defined(FEATURE_CLUSTER)
+//#include "pmsis/implem/cluster/cluster.h"
+#endif  /* FEATURE_CLUSTER */
+
+#endif  /* HW_VERIF_ONLY */
+
+/* Hal includes. */
+//#include "pmsis/implem/hal/hal.h"
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PMSIS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-properties.h

@@ -0,0 +1,124 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_
+
+
+/* PULP defs */
+#define PULP
+
+#define ARCHI_FPGA_FREQUENCY 5000000
+
+/* hardware modules */
+#define ARCHI_NUM_TIMER 1
+#define ARCHI_NUM_FLL 2
+
+#define ARCHI_REF_CLOCK_LOG2 15
+#define ARCHI_REF_CLOCK	(1 << ARCHI_REF_CLOCK_LOG2)
+
+#define ARCHI_NB_FLL	  3
+
+#define __RT_FLL_CL	2
+#define __RT_FLL_PERIPH 1
+#define __RT_FLL_FC	0
+
+#define __RT_FREQ_DOMAIN_FC	0
+#define __RT_FREQ_DOMAIN_CL	2
+#define __RT_FREQ_DOMAIN_PERIPH 1
+#define RT_FREQ_NB_DOMAIN	3
+
+/* Cores & cluster */
+/* FC */
+#define ARCHI_FC_CID                (32)
+
+/* Cluster */
+#define ARCHI_HAS_CLUSTER           (1)
+#define ARCHI_CL_CID(id)            (id)
+#define ARCHI_CLUSTER_NB_PE         (8) /* Processing elements. */
+
+/* Memories */
+/* FC memory */
+#define ARCHI_HAS_FC_TCDM           (1)
+#define ARCHI_HAS_FC_ALIAS          (1)
+#define FC_TCDM_SIZE                (0x00004000) /* 16kB. */
+
+/* L2 memory */
+#define ARCHI_HAS_L2_ALIAS          (0)
+#define L2_SHARED_SIZE              (0x00080000) /* 512kB. */
+
+/* L1 cluster memory */
+#define ARCHI_HAS_CL_L1_ALIAS       (1)
+#define CL_L1_SIZE                  (0x00010000) /* 64kB. */
+
+/* L1 cluster TS */
+#define ARCHI_HAS_CL_L1_TS          (1)
+
+
+
+/* TODO: fix this table */
+/* UDMA peripherals */
+// #define UDMA_HAS_SPIM               (1)
+// #define UDMA_HAS_HYPER              (0)
+// #define UDMA_HAS_UART               (1)
+// #define UDMA_HAS_I2C                (1)
+// #define UDMA_HAS_DMACPY             (0)
+// #define UDMA_HAS_I2S                (1)
+// #define UDMA_HAS_CPI                (1)
+
+/* TODO: fix this table */
+/* Number of UDMA peripherals */
+// #define UDMA_NB_SPIM                (2)
+// #define UDMA_NB_HYPER               (0)
+// #define UDMA_NB_UART                (1)
+// #define UDMA_NB_I2C                 (2)
+// #define UDMA_NB_DMACPY              (0)
+// #define UDMA_NB_I2S                 (1)
+// #define UDMA_NB_CPI                 (1)
+
+/* TODO: fix this table */
+/* #define UDMA_NB_PERIPH              ((UDMA_HAS_SPIM ? UDMA_NB_SPIM) + \ */
+/*                                      (UDMA_HAS_HYPER ? UDMA_NB_HYPER) + \ */
+/*                                      (UDMA_HAS_UART ? UDMA_NB_UART) + \ */
+/*                                      (UDMA_HAS_I2C ? UDMA_NB_I2C) + \ */
+/*                                      (UDMA_HAS_DMACPY ? UDMA_NB_DMACPY) + \ */
+/*                                      (UDMA_HAS_I2S ? UDMA_NB_I2S) + \ */
+/*                                      (UDMA_HAS_CPI ? UDMA_NB_CPI)) */
+#define UDMA_NB_PERIPH              (10)
+/* Size of each UDMA peripheral */
+#define UDMA_PERIPH_SIZE_LOG2       (7)
+#define UDMA_PERIPH_SIZE            (1 << UDMA_PERIPH_SIZE_LOG2)
+
+/* UDMA peripherals ID, this maps to PER_ID_* in udma_subsystem.sv */
+//#define UDMA_SPIM_ID(id)            (1   + (id))
+/* #define UDMA_HYPER_ID(id)           (3   + (id)) */
+//#define UDMA_UART_ID(id)            (0   + (id))
+//#define UDMA_I2C_ID(id)             (2   + (id))
+/* #define UDMA_DMACPY_ID(id)          (7   + (id)) */
+//#define ARCHI_UDMA_FILTER_ID(id)          (7  + (id))
+////#define UDMA_I2S_ID(id)             (5  + (id))
+//#define UDMA_CPI_ID(id)             (6  + (id))
+//#define UDMA_SDIO_ID(id)            (4   + (id))
+
+
+/* Pads & GPIO. */
+// #define ARCHI_NB_PAD                (48)
+// #define ARCHI_NB_GPIO               (32)
+
+/* PWM. */
+/* #define ARCHI_NB_PWM                (4) */
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PROPERTIES_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-pulp-mem-map.h

@@ -0,0 +1,82 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_
+
+
+
+/*
+ * SOC PERIPHERALS
+ */
+
+#define PULP_SOC_PERIPHERALS_ADDR 0x1A100000
+
+#define PULP_FC_TIMER_SIZE 0x00000800
+
+#define PULP_FLL_OFFSET		 0x00000000
+#define PULP_GPIO_OFFSET	 0x00001000
+#define PULP_UDMA_OFFSET	 0x00002000
+#define PULP_APB_SOC_CTRL_OFFSET 0x00004000
+#define PULP_ADV_TIMER_OFFSET	 0x00005000
+#define PULP_SOC_EU_OFFSET	 0x00006000
+#define PULP_FC_IRQ_OFFSET	 0x00009800
+/* #define PULP_FC_IRQ_OFFSET	 0x00009000 */ /* this is a mirror of above */
+#define PULP_FC_TIMER_OFFSET 0x0000B000
+#define PULP_FC_HWPE_OFFSET  0x0000C000
+#define PULP_STDOUT_OFFSET   0x0000F000
+#define PULP_DEBUG_OFFSET    0x00010000
+
+#define PULP_FLL_ADDR  (PULP_SOC_PERIPHERALS_ADDR + PULP_FLL_OFFSET)
+#define PULP_GPIO_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_GPIO_OFFSET)
+#define PULP_UDMA_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_UDMA_OFFSET)
+#define PULP_APB_SOC_CTRL_ADDR                                                 \
+	(PULP_SOC_PERIPHERALS_ADDR + PULP_APB_SOC_CTRL_OFFSET)
+#define PULP_ADV_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_ADV_TIMER_OFFSET)
+#define PULP_SOC_EU_ADDR    (PULP_SOC_PERIPHERALS_ADDR + PULP_SOC_EU_OFFSET)
+#define PULP_FC_IRQ_ADDR    (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_IRQ_OFFSET)
+/* #define PULP_FC_ITC_ADDR   (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_ITC_OFFSET) */
+#define PULP_FC_TIMER_ADDR (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_TIMER_OFFSET)
+#define PULP_FC_HWPE_ADDR  (PULP_SOC_PERIPHERALS_ADDR + PULP_FC_HWPE_OFFSET)
+#define PULP_STDOUT_ADDR   (PULP_SOC_PERIPHERALS_ADDR + PULP_STDOUT_OFFSET)
+
+#define PULP_FLL_AREA_SIZE 0x00000010
+
+/*
+ * CLUSTER
+ */
+
+#define PULP_CLUSTER_ADDR	      0x00000000
+#define PULP_CLUSTER_SIZE	      0x00400000
+#define PULP_CLUSTER_GLOBAL_ADDR(cid) (0x10000000 + (cid)*PULP_CLUSTER_SIZE)
+
+/*
+ * CLUSTER PERIPHERALS
+ */
+
+#define PULP_CLUSTER_PERIPHERALS_OFFSET 0x00200000
+
+#define PULP_TIMER_OFFSET 0x00000400
+
+#define PULP_CLUSTER_PERIPHERALS_ADDR                                          \
+	(PULP_CLUSTER_ADDR + PULP_CLUSTER_PERIPHERALS_OFFSET)
+#define PULP_CLUSTER_PERIPHERALS_GLOBAL_ADDR(cid)                              \
+	(PULP_CLUSTER_GLOBAL_ADDR(cid) + PULP_CLUSTER_PERIPHERALS_OFFSET)
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_PULP_MEM_MAP_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-system.h

@@ -0,0 +1,36 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+/* Description: Platform system level functions */
+
+#ifndef _CORE_V_MCU_SYSTEM_H
+#define _CORE_V_MCU_SYSTEM_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+//#include "FreeRTOSConfig.h"
+
+
+extern volatile uint32_t system_core_clock;
+
+void system_init (void);
+void system_core_clock_update (void);
+
+#endif  /* _CORE_V_MCU_SYSTEM_H */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core-v-mcu-target.h

@@ -0,0 +1,104 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Author: Robert Balas */
+
+#ifndef TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_
+#define TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_
+
+#include "core_pulp.h"
+#include "core_utils.h"
+#include "core-v-mcu-periph.h"
+//#include "pmsis/targets/periph.h"
+
+static inline void hal_compiler_barrier()
+{
+    asm volatile ("" : : : "memory");
+}
+
+static inline void hal_write32(volatile void *addr, uint32_t value)
+{
+    asm volatile ("" : : : "memory");
+    *((volatile uint32_t *)addr) = value;
+    asm volatile ("" : : : "memory");
+}
+
+static inline void hal_write8(volatile void *addr, uint32_t value)
+{
+    asm volatile ("" : : : "memory");
+    *((volatile uint8_t *)addr) = value;
+    asm volatile ("" : : : "memory");
+}
+
+static inline void hal_or32(volatile void *addr, uint32_t value)
+{
+    asm volatile ("" : : : "memory");
+    *((volatile uint32_t *)addr) |= value;
+    asm volatile ("" : : : "memory");
+}
+
+static inline void hal_and32(volatile void *addr, uint32_t value)
+{
+    asm volatile ("" : : : "memory");
+    *((volatile uint32_t *)addr) &= value;
+    asm volatile ("" : : : "memory");
+}
+
+static inline uint32_t hal_read32(volatile void *addr)
+{
+    asm volatile ("" : : : "memory");
+    uint32_t ret = *((volatile uint32_t *)addr);
+    asm volatile ("" : : : "memory");
+    return ret;
+}
+
+static inline uint8_t hal_read8(volatile void *addr)
+{
+    asm volatile ("" : : : "memory");
+    uint8_t ret = *((volatile uint8_t *)addr);
+    asm volatile ("" : : : "memory");
+    return ret;
+}
+
+static inline uint32_t pi_core_id()
+{
+    return __native_core_id();
+}
+
+static inline uint32_t pi_cluster_id()
+{
+    return __native_cluster_id();
+}
+
+static inline uint32_t pi_is_fc()
+{
+    return __native_is_fc();
+}
+
+static inline uint32_t pi_nb_cluster_cores()
+{
+    return  ARCHI_CLUSTER_NB_PE;
+}
+
+static inline int pi_cl_cluster_nb_cores()
+{
+    return  ARCHI_CLUSTER_NB_PE;
+}
+
+
+#endif /* TARGET_CORE_V_MCU_INCLUDE_CORE_V_MCU_TARGET_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp.h

@@ -0,0 +1,1483 @@
+/**************************************************************************//**
+ * @file     core_pulp.h
+ * @brief    CMSIS PULP Core Peripheral Access Layer Header File
+ * @version  V0.0.1
+ * @date     04. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 GreenWaves Technologies SAS. All rights reserved.
+ * Copyright (c) 2020 ETH Zurich
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CORE_PULP_H_GENERIC__
+#define __CORE_PULP_H_GENERIC__
+
+#include <stdint.h>
+#include <assert.h>
+#include "core-v-mcu-memory-map.h"
+
+#include "pmsis_gcc.h"
+//#include "cores/TARGET_RISCV_32/csr.h"
+#include "csr.h"
+//#include "cores/TARGET_RISCV_32/bits.h"
+#include "bits.h"
+//#include "cores/TARGET_RISCV_32/pulp_io.h"
+#include "pulp_io.h"
+#include "core-v-mcu-periph.h"
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup PULP
+  @{
+ */
+
+/*  CMSIS PULP definitions */
+#define __PULP_CMSIS_VERSION_MAIN  ( 5U)                                  /*!< [31:16] CMSIS HAL main version */
+#define __PULP_CMSIS_VERSION_SUB   ( 0U)                                  /*!< [15:0]  CMSIS HAL sub version */
+#define __PULP_CMSIS_VERSION       ((__PULP_CMSIS_VERSION_MAIN << 16U) | \
+				    __PULP_CMSIS_VERSION_SUB           )  /*!< CMSIS HAL version number */
+
+#define __PULP_V                   (1U)                                   /*!< PULP Core Version */
+
+#include "pmsis_gcc.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_PULP_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_PULP_H_DEPENDANT
+#define __CORE_PULP_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __PULP_REV
+    #define __PULP_REV               0x0000U
+    #warning "__PULP_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          0U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group PULP */
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+******************************************************************************/
+/**
+   \defgroup CMSIS_core_register Defines and Type Definitions
+   \brief Type definitions and defines for PULP processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+#define MSTATUS_ADDR    0x300             /*!< Machine Status Register */
+#define MISA_ADDR       0x301             /*!< ISA and Extensions Register */
+#define MIE_ADDR	0x304             /*!< Machine interrupt enable Register */
+#define MTVEC_ADDR      0x305             /*!< Machine Trap-handler Base Address Register */
+#define MSCRATCH_ADDR   0x340             /*!< Machine Scratch Register */
+#define MEPC_ADDR       0x341             /*!< Machine Exception Program Counter Register */
+#define MCAUSE_ADDR     0x342             /*!< Machine Trap Cause Register */
+#define MTVAL_ADDR      0x343             /*!< Machine Trap Value Register */
+#define MIP_ADDR        0x344             /*!< Machine Interrupt Pending Register */
+#define PMPCFG0_ADDR    0x3a0             /*!< PMP Configuration Register 0 */
+#define PMPADDR0_ADDR   0x3b0             /*!< PMP Address Register 0 */
+
+#define MVENDORID_ADDR  0xF11             /*!< Vendor ID Register */
+#define MARCHID_ADDR    0xF12             /*!< Architecture ID Register */
+#define MIMPID_ADDR     0xF13             /*!< Implementation ID Register */
+#define MHARTID_ADDR    0xF14             /*!< Hardware Thread ID Register */
+
+#define PCER_ADDR       0x7E0             /*!< Performance Counter Event Register */
+#define PCMR_ADDR       0x7E1             /*!< Performance Counter Mode Register */
+
+/* #ifndef ASIC */
+#define PERF_CYCLE_OFFSET      0x00       /*!< Performance Counter Counter CYCLE Register */
+#define PERF_INSTR_OFFSET      0x01       /*!< Performance Counter Counter INSTR Register */
+#define PERF_LD_STALL_OFFSET   0x02       /*!< Performance Counter Counter LD_STALL Register */
+#define PERF_JR_STALL_OFFSET   0x03       /*!< Performance Counter Counter JR_STALL Register */
+#define PERF_IMISS_OFFSET      0x04       /*!< Performance Counter Counter IMISS Register */
+#define PERF_LD_OFFSET         0x05       /*!< Performance Counter Counter LD Register */
+#define PERF_ST_OFFSET         0x06       /*!< Performance Counter Counter ST Register */
+#define PERF_JUMP_OFFSET       0x07       /*!< Performance Counter Counter JUMP Register */
+#define PERF_BRANCH_OFFSET     0x08       /*!< Performance Counter Counter BRANCH Register */
+#define PERF_BTAKEN_OFFSET     0x09       /*!< Performance Counter Counter BTAKEN Register */
+#define PERF_RVC_OFFSET        0x0A       /*!< Performance Counter Counter RVC Register */
+#define PERF_LD_EXT_OFFSET     0x0B       /*!< Performance Counter Counter LD_EXT Register */
+#define PERF_ST_EXT_OFFSET     0x0C       /*!< Performance Counter Counter ST_EXT Register */
+#define PERF_LD_EXT_CYC_OFFSET 0x0D       /*!< Performance Counter Counter LD_EXT_CYC Register */
+#define PERF_ST_EXT_CYC_OFFSET 0x0E       /*!< Performance Counter Counter ST_EXT_CYC Register */
+#define PERF_TCDM_COUNT_OFFSET 0x0F       /*!< Performance Counter Counter TCDM_CONT Register */
+/* #endif */
+#define PERF_ALL_OFFSET        0x1F       /*!< Performance Counter Counter ALL Register, used to reset all counters */
+
+#define PCCR_ADDR(x)    (0x780 + x)       /*!< Performance Counter Counter access */
+
+#define HWLP_S0_ADDR    0x7C0             /*!< Hardware Loop Start0 Register */
+#define HWLP_E0_ADDR    0x7C1             /*!< Hardware Loop End0 Register */
+#define HWLP_C0_ADDR    0x7C2             /*!< Hardware Loop Count0 Register */
+#define HWLP_S1_ADDR    0x7C3             /*!< Hardware Loop Start1 Register */
+#define HWLP_E1_ADDR    0x7C4             /*!< Hardware Loop End1 Register */
+#define HWLP_C1_ADDR    0x7C5             /*!< Hardware Loop Count1 Register */
+
+#define UEPC_ADDR       0x041             /*!< User Exception Program Counter Register */
+#define CPRIV_ADDR      0xC10             /*!< Current Privilege Level Register (unofficial) */
+#define UCAUSE_ADDR     0x042             /*!< FC User Trap Cause Register */
+
+/**
+  \brief  Union type to access the Vendor ID Register (MVENDORID).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t OFFSET:7;                   /*!< bit:  0..6   */
+    uint32_t BANK:25;                    /*!< bit:  7..31  */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} MVENDORID_Type;
+
+/* MVENDORID Register Definitions */
+#define MVENDORID_BANK_Pos                 7U                                            /*!< MVENDORID: BANK Position */
+#define MVENDORID_BANK_Msk                 (0x1FFFFFFUL /*<< MVENDORID_BANK_Pos*/)       /*!< MVENDORID: BANK Mask */
+
+#define MVENDORID_OFFSET_Pos               0U                                            /*!< MVENDORID: OFFSET Position */
+#define MVENDORID_OFFSET_Msk               (0x7FUL /*<< MVENDORID_OFFSET_Pos*/)          /*!< MVENDORID: OFFSET Mask */
+
+
+/**
+  \brief  Union type to access the Hart ID Register (MHARTID).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t OFFSET:5;                   /*!< bit:  0..4  Hardware thread id */
+    uint32_t BANK:27;                    /*!< bit:  5..31 Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} MHARTID_Type;
+
+/* MHARTID Register Definitions */
+#define MHARTID_BANK_Pos                 0U                                            /*!< MHARTID: BANK Position */
+#define MHARTID_BANK_Msk                 (0x1FUL /*<< MHARTID_BANK_Pos*/)              /*!< MHARTID: BANK Mask */
+
+
+/**
+  \brief  Union type to access the ISA and Extensions Register (MISA).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t EXTENSION:26;               /*!< bit:  0.. 25  ISA Extension */
+    uint32_t WIRI:4;                     /*!< bit:  26..29  Reserved */
+    uint32_t MXL:2;                      /*!< bit:  30..31  Machine XLEN */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} MISA_Type;
+
+/* MISA Register Definitions */
+#define MISA_MXL_Pos                       30U                                          /*!< MISA: MXL Position */
+#define MISA_MXL_Msk                       (0x3UL << MISA_MXL_Pos)                      /*!< MISA: MXL Mask */
+
+#define MISA_EXTENSION_Pos                 0U                                           /*!< MISA: EXTENSION Position */
+#define MISA_EXTENSION_Msk                 (0x3FFFFFFUL /*<< MISA_EXTENSION_Pos*/)      /*!< MISA: EXTENSION Mask */
+
+
+/**
+   \brief  Union type to access the Machine Mode Status Register (MSTATUS).
+*/
+typedef union
+{
+  struct
+  {
+    uint32_t UIE:1;                      /*!< bit:  0       User Interrupt-enable bit */
+    uint32_t SIE:1;                      /*!< bit:  1       Supervisor Interrupt-enable bit */
+    uint32_t WPRI0:1;                    /*!< bit:  2       Reserved */
+    uint32_t MIE:1;                      /*!< bit:  3       Machine Interrupt-enable bit */
+    uint32_t UPIE:1;                     /*!< bit:  4       Prior User Interrupt-enable bit on trap */
+    uint32_t SPIE:1;                     /*!< bit:  5       Prior Supervisor Interrupt-enable bit on trap */
+    uint32_t WPRI1:1;                    /*!< bit:  6       Reserved */
+    uint32_t MPIE:1;                     /*!< bit:  7       Prior Machine Interrupt-enable bit on trap */
+    uint32_t SPP:1;                      /*!< bit:  8       Supervisor previous privilege value, up to supervisor mode*/
+    uint32_t WPRI2:2;                    /*!< bit:  9, 10   Reserved */
+    uint32_t MPP:2;                      /*!< bit:  11, 12  Supervise previous privilege value, up to machine mode */
+    uint32_t FS:2;                       /*!< bit:  13, 14  Reserved */
+    uint32_t XS:2;                       /*!< bit:  15, 16  Reserved */
+    uint32_t MPRV:1;                     /*!< bit:  17      Reserved */
+    uint32_t SUM:1;                      /*!< bit:  18      Reserved */
+    uint32_t MXR:1;                      /*!< bit:  19      Reserved */
+    uint32_t TVM:1;                      /*!< bit:  20      Reserved */
+    uint32_t TW:1;                       /*!< bit:  21      Reserved */
+    uint32_t TSR:1;                      /*!< bit:  22      Reserved */
+    uint32_t WPRI3:8;                    /*!< bit:  23..30  Reserved */
+    uint32_t SD:1;                       /*!< bit:  31      Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} MSTATUS_Type;
+
+
+/* MSTATUS Register Definitions */
+#define MSTATUS_SD_Pos                         31U                                            /*!< MSTATUS: SD Position */
+#define MSTATUS_SD_Msk                         (1UL << MSTATUS_SD_Pos)                        /*!< MSTATUS: SD Mask */
+
+#define MSTATUS_TSR_Pos                        22U                                            /*!< MSTATUS: TSR Position */
+#define MSTATUS_TSR_Msk                        (1UL << MSTATUS_TSR_Pos)                       /*!< MSTATUS: TSR Mask */
+
+#define MSTATUS_TW_Pos                         21U                                            /*!< MSTATUS: TW Position */
+#define MSTATUS_TW_Msk                         (1UL << MSTATUS_TW_Pos)                        /*!< MSTATUS: TW Mask */
+
+#define MSTATUS_TVM_Pos                        20U                                            /*!< MSTATUS: TVM Position */
+#define MSTATUS_TVM_Msk                        (1UL << MSTATUS_TVM_Pos)                       /*!< MSTATUS: TVM Mask */
+
+#define MSTATUS_MXR_Pos                        19U                                            /*!< MSTATUS: MXR Position */
+#define MSTATUS_MXR_Msk                        (1UL << MSTATUS_MXR_Pos)                       /*!< MSTATUS: MXR Mask */
+
+#define MSTATUS_SUM_Pos                        18U                                            /*!< MSTATUS: SUM Position */
+#define MSTATUS_SUM_Msk                        (1UL << MSTATUS_SUM_Pos)                       /*!< MSTATUS: SUM Mask */
+
+#define MSTATUS_MPRV_Pos                       17U                                            /*!< MSTATUS: MPRV Position */
+#define MSTATUS_MPRV_Msk                       (1UL << MSTATUS_MPRV_Pos)                      /*!< MSTATUS: MPRV Mask */
+
+#define MSTATUS_XS_Pos                         15U                                            /*!< MSTATUS: XS Position */
+#define MSTATUS_XS_Msk                         (3UL << MSTATUS_XS_Pos)                        /*!< MSTATUS: XS Mask */
+
+#define MSTATUS_FS_Pos                         13U                                            /*!< MSTATUS: FS Position */
+#define MSTATUS_FS_Msk                         (3UL << MSTATUS_FS_Pos)                        /*!< MSTATUS: FS Mask */
+
+#define MSTATUS_MPP_Pos                        11U                                            /*!< MSTATUS: MPP Position */
+#define MSTATUS_MPP_Msk                        (3UL << MSTATUS_MPP_Pos)                       /*!< MSTATUS: MPP Mask */
+
+#define MSTATUS_SPP_Pos                        8U                                             /*!< MSTATUS: SPP Position */
+#define MSTATUS_SPP_Msk                        (1UL << MSTATUS_SPP_Pos)                       /*!< MSTATUS: SPP Mask */
+
+#define MSTATUS_MPIE_Pos                       7U                                             /*!< MSTATUS: MPIE Position */
+#define MSTATUS_MPIE_Msk                       (1UL << MSTATUS_MPIE_Pos)                      /*!< MSTATUS: MPIE Mask */
+
+#define MSTATUS_SPIE_Pos                       5U                                             /*!< MSTATUS: SPIE Position */
+#define MSTATUS_SPIE_Msk                       (1UL << MSTATUS_SPIE_Pos)                      /*!< MSTATUS: SPIE Mask */
+
+#define MSTATUS_UPIE_Pos                        4U                                            /*!< MSTATUS: UPIE Position */
+#define MSTATUS_UPIE_Msk                        (1UL << MSTATUS_UPIE_Pos)                     /*!< MSTATUS: UPIE Mask */
+
+#define MSTATUS_MIE_Pos                         3U                                            /*!< MSTATUS: MIE Position */
+#define MSTATUS_MIE_Msk                         (1UL << MSTATUS_MIE_Pos)                      /*!< MSTATUS: MIE Mask */
+
+#define MSTATUS_SIE_Pos                         1U                                            /*!< MSTATUS: SIE Position */
+#define MSTATUS_SIE_Msk                         (1UL << MSTATUS_SIE_Pos)                      /*!< MSTATUS: SIE Mask */
+
+#define MSTATUS_UIE_Pos                         0U                                            /*!< MSTATUS: UIE Position */
+#define MSTATUS_UIE_Msk                         (1UL /* << MSTATUS_UIE_Pos */)                /*!< MSTATUS: UIE Mask */
+
+/**
+  \brief  Union type to access the Machine Trap-Vector Baser-Address Register (MTVEC).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t MODE:2;                     /*!< bit:  0..1  vector mode */
+    uint32_t BASE:30;                    /*!< bit:  2..31 vector base address */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} MTVEC_Type;
+
+/* MTVEC Register Definitions */
+#define MTVEC_BASE_Pos                 2U                                            /*!< MTVEC: BASE Position */
+#define MTVEC_BASE_Msk                 (0x3FFFFFFFUL << MTVEC_BASE_Pos)              /*!< MTVEC: BASE Mask */
+
+#define MTVEC_MODE_Pos                 0U                                            /*!< MTVEC: MODE Position */
+#define MTVEC_MODE_Msk                 (0x3UL /*<< MTVEC_MODE_Pos*/)                 /*!< MTVEC: MODE Mask */
+
+
+/**
+  \brief  Union type to access the Machine Trap Cause Register (MCAUSE).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t EC:31;                       /*!< bit: 0..30  Exception code */
+    uint32_t IRQ:1;                      /*!< bit:  31 Interrupt flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} MCAUSE_Type;
+
+/* MCAUSE Register Definitions */
+#define MCAUSE_IRQ_Pos                31U                                            /*!< MCAUSE: IRQ Position */
+#define MCAUSE_IRQ_Msk                (0x1UL << MCAUSE_IRQ_Pos)                      /*!< MCAUSE: IRQ Mask */
+
+#define MCAUSE_EC_Pos                 0U                                             /*!< MCAUSE: EC Position */
+#define MCAUSE_EC_Msk                 (0x1FFFFFFFUL /*<< MCAUSE_EC_Pos*/)                  /*!< MCAUSE: EC Mask */
+
+
+/**
+  \brief  Union type to access the Current Privilege Level Register (CPRIV).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t PRIV:2;                     /*!< bit:  0..1  Current privilege level */
+    uint32_t _reserved0:30;               /*!< bit:  2..31 Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CPRIV_Type;
+
+/* CPRIV Register Definitions */
+#define CPRIV_PRIV_Pos                 0U                                            /*!< CPRIV: PRIV Position */
+#define CPRIV_PRIV_Msk                 (0x3UL /*<< CPRIV_PRIV_Pos*/)                 /*!< CPRIV: PRIV Mask */
+
+
+/**
+  \brief  Union type to access the Performance Counter Mode Register (PCMR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t GLBEN:1;                    /*!< bit:  0  Enbable all Performance counter */
+    uint32_t SATU:1;                     /*!< bit:  1  Use saturating arithmetic */
+    uint32_t _reserved0:30;              /*!< bit:  2..31 Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} PCMR_Type;
+
+/* PCMR Register Definitions */
+#define PCMR_GLBEN_Pos                 0U                                            /*!< PCMR: GLBEN Position */
+#define PCMR_GLBEN_Msk                 (0x1UL /*<< PCMR_GLBEN_Pos*/)                 /*!< PCMR: GLBEN Mask */
+
+#define PCMR_SATU_Pos                  1U                                            /*!< PCMR: SATU Position */
+#define PCMR_SATU_Msk                  (0x1UL << PCMR_SATU_Pos)                 /*!< PCMR: SATU Mask */
+
+
+/**
+  \brief  Union type to access the Performance Counter Event Register (PCER).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t CYCLE:1;                     /*!< bit:  0  CYCLE */
+    uint32_t INSTR:1;                     /*!< bit:  1  INSTR */
+    uint32_t LD_STALL:1;                  /*!< bit:  2  LD_STALL */
+    uint32_t JMP_STALL:1;                 /*!< bit:  3  JMP_STALL */
+    uint32_t IMISS:1;                     /*!< bit:  4  IMISS */
+    uint32_t WBRANCH:1;                   /*!< bit:  5  WBRANCH */
+    uint32_t WBRANCH_CYC:1;               /*!< bit:  6  WBRANCH_CYC */
+    uint32_t LD:1;                        /*!< bit:  7  LD */
+    uint32_t ST:1;                        /*!< bit:  8  ST */
+    uint32_t JUMP:1;                      /*!< bit:  9  JUMP */
+    uint32_t BRANCH:1;                    /*!< bit:  10  BRANCH */
+    uint32_t DELAY_SLOT:1;                /*!< bit:  11  DELAY_SLOT */
+    uint32_t LD_EXT:1;                    /*!< bit:  12  LD_EXT */
+    uint32_t ST_EXT:1;                    /*!< bit:  13  ST_EXT */
+    uint32_t LD_EXT_CYC:1;                /*!< bit:  14  LD_EXT_CYC */
+    uint32_t ST_EXT_CYC:1;                /*!< bit:  15  ST_EXT_CYC */
+    uint32_t TCDM_CONT:1;                 /*!< bit:  16  TCDM_CONT */
+    uint32_t _reserved0:15;               /*!< bit:  17..31 Reserved */
+  } b;                                    /*!< Structure used for bit  access */
+  uint32_t w;                             /*!< Type      used for word access */
+} PCER_Type;
+
+/* PCER Register Definitions */
+#define PCER_CYCLE_Pos                 0U                                            /*!< PCER: CYCLE Position */
+#define PCER_CYCLE_Msk                 (0x1UL /*<< PCER_CYCLE_Pos*/)                 /*!< PCER: CYCLE Mask */
+
+#define PCER_INSTR_Pos                 1U                                            /*!< PCER: _INSTR Position */
+#define PCER_INSTR_Msk                 (0x1UL << PCER_INSTR_Pos)                     /*!< PCER: _INSTR Mask */
+
+#define PCER_LD_STALL_Pos              2U                                            /*!< PCER: LD_STALL Position */
+#define PCER_LD_STALL_Msk              (0x1UL << PCER_LD_STALL_Pos)                  /*!< PCER: LD_STALL Mask */
+
+#define PCER_JMP_STALL_Pos             3U                                            /*!< PCER: JMP_STALL Position */
+#define PCER_JMP_STALL_Msk             (0x1UL << PCER_JMP_STALL_Pos)                 /*!< PCER: JMP_STALL Mask */
+
+#define PCER_IMISS_Pos                 4U                                            /*!< PCER: IMISS Position */
+#define PCER_IMISS_Msk                 (0x1UL << PCER_IMISS_Pos)                     /*!< PCER: IMISS Mask */
+
+#define PCER_WBRANCH_Pos               5U                                            /*!< PCER: WBRANCH Position */
+#define PCER_WBRANCH_Msk               (0x1UL << PCER_WBRANCH_Pos)                   /*!< PCER: WBRANCH Mask */
+
+#define PCER_WBRANCH_CYC_Pos           6U                                            /*!< PCER: WBRANCH_CYC Position */
+#define PCER_WBRANCH_CYC_Msk           (0x1UL << PCER_WBRANCH_CYC_Pos)               /*!< PCER: WBRANCH_CYC Mask */
+
+#define PCER_LD_Pos                    7U                                            /*!< PCER: LD Position */
+#define PCER_LD_Msk                    (0x1UL << PCER_LD_Pos)                        /*!< PCER: LD Mask */
+
+#define PCER_ST_Pos                    8U                                            /*!< PCER: ST Position */
+#define PCER_ST_Msk                    (0x1UL << PCER_ST_Pos)                        /*!< PCER: ST Mask */
+
+#define PCER_JUMP_Pos                  9U                                            /*!< PCER: JUMP Position */
+#define PCER_JUMP_Msk                  (0x1UL << PCER_JUMP_Pos)                      /*!< PCER: JUMP Mask */
+
+#define PCER_BRANCH_Pos                10U                                           /*!< PCER: BRANCH Position */
+#define PCER_BRANCH_Msk                (0x1UL << PCER_BRANCH_Pos)                    /*!< PCER: BRANCH Mask */
+
+#define PCER_DELAY_SLOT_Pos            11U                                           /*!< PCER: DELAY_SLOT Position */
+#define PCER_DELAY_SLOT_Msk            (0x1UL << PCER_DELAY_SLOT_Pos)                /*!< PCER: DELAY_SLOT Mask */
+
+#define PCER_LD_EXT_Pos                12U                                           /*!< PCER: LD_EXT Position */
+#define PCER_LD_EXT_Msk                (0x1UL << PCER_LD_EXT_Pos)                    /*!< PCER: LD_EXT Mask */
+
+#define PCER_ST_EXT_Pos                13U                                           /*!< PCER: ST_EXT Position */
+#define PCER_ST_EXT_Msk                (0x1UL << PCER_ST_EXT_Pos)                    /*!< PCER: ST_EXT Mask */
+
+#define PCER_LD_EXT_CYC_Pos            14U                                           /*!< PCER: LD_EXT_CYC Position */
+#define PCER_LD_EXT_CYC_Msk            (0x1UL << PCER_LD_EXT_CYC_Pos)                /*!< PCER: LD_EXT_CYC Mask */
+
+#define PCER_ST_EXT_CYC_Pos            15U                                           /*!< PCER: ST_EXT_CYC Position */
+#define PCER_ST_EXT_CYC_Msk            (0x1UL << PCER_ST_EXT_CYC_Pos)                /*!< PCER: ST_EXT_CYC Mask */
+
+#define PCER_TCDM_CONT_Pos             16U                                           /*!< PCER: TCDM_CONT Position */
+#define PCER_TCDM_CONT_Msk             (0x1UL << PCER_TCDM_CONT_Pos)                 /*!< PCER: TCDM_CONT Mask */
+
+#define PCER_EVENTS_NUM                17U                                           /*!< PCER: All events number */
+/*@} end of group CMSIS_CORE */
+
+
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+*/
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM  uint32_t MASK;                    /**< Interrupt Controller mask register, offset: 0x00 */
+  __IOM  uint32_t MASK_SET;                /**< Interrupt Controller mask set register, offset: 0x04 */
+  __IOM  uint32_t MASK_CLEAR;              /**< Interrupt Controller mask clear register, offset: 0x08 */
+  __IOM  uint32_t IRQ;                     /**< Interrupt Controller irq register, offset: 0x0C */
+  __IOM  uint32_t IRQ_SET;                 /**< Interrupt Controller irq set register, offset: 0x10 */
+  __IOM  uint32_t IRQ_CLEAR;               /**< Interrupt Controller irq clear register, offset: 0x14 */
+  __IOM  uint32_t ACK;                     /**< Interrupt Controller ack register, offset: 0x18 */
+  __IOM  uint32_t ACK_SET;                 /**< Interrupt Controller ack set register, offset: 0x1C */
+  __IOM  uint32_t ACK_CLEAR;               /**< Interrupt Controller ack clear register, offset: 0x20 */
+  __IOM  uint32_t FIFO;                    /**< Interrupt Controller soc event fifo register, offset: 0x24 */
+}  NVIC_Type;
+/*@} end of group CMSIS_NVIC */
+
+#define IRQ_REG_MASK_OFFSET	  0x000
+#define IRQ_REG_MASK_SET_OFFSET	  0x004
+#define IRQ_REG_MASK_CLEAR_OFFSET 0x008
+#define IRQ_REG_INT_OFFSET	  0x00C
+#define IRQ_REG_INT_SET_OFFSET	  0x010
+#define IRQ_REG_INT_CLEAR_OFFSET  0x014
+#define IRQ_REG_ACK_OFFSET	  0x018
+#define IRQ_REG_ACK_SET_OFFSET	  0x01C
+#define IRQ_REG_ACK_CLEAR_OFFSET  0x020
+#define IRQ_REG_FIFO_OFFSET	  0x024
+
+/* Interrupt line masks: these interrupts directly go to the core (after being
+ * serialized as reqest + id). We refer to these interrupts with the prefix IRQ.
+ * Events on the other we strictly use to refer to "interrupts/events" that are
+ * signaled through (muxed) EU SoC interrupts (IRQ_FC_EVT_SOC_EVT) and need
+ * additional handling by the user through the Event Unit.
+ */
+#define IRQ_FC_EVT_SW0	      BIT(0)
+#define IRQ_FC_EVT_SW1	      BIT(1)
+#define IRQ_FC_EVT_SW2	      BIT(2)
+#define IRQ_FC_EVT_SW3	      BIT(3)
+#define IRQ_FC_EVT_SW4	      BIT(4)
+#define IRQ_FC_EVT_SW5	      BIT(5)
+#define IRQ_FC_EVT_SW6	      BIT(6)
+#define IRQ_FC_EVT_SW7	      BIT(7)
+#define IRQ_FC_EVT_DMA_PE_EVT BIT(8)
+#define IRQ_FC_EVT_DMA_PE_IRQ BIT(9)
+#define IRQ_FC_EVT_TIMER0_LO  BIT(10)
+#define IRQ_FC_EVT_TIMER0_HI  BIT(11)
+#define IRQ_FC_EVT_PF	      BIT(12)
+#define IRQ_FC_EVT_CLK_REF    BIT(14)
+#define IRQ_FC_EVT_GPIO	      BIT(15)
+/* doesn't exist in pulp */
+/*#define IRQ_FC_EVT_RTC		   16 */
+#define IRQ_FC_EVT_ADV_TIMER0 BIT(17)
+#define IRQ_FC_EVT_ADV_TIMER1 BIT(18)
+#define IRQ_FC_EVT_ADV_TIMER2 BIT(19)
+#define IRQ_FC_EVT_ADV_TIMER3 BIT(20)
+/* doesn't exist in pulp */
+/* #define IRQ_FC_EVT_CLUSTER_NOT_BUSY 21 */
+/* #define IRQ_FC_EVT_CLUSTER_POK	   22 */
+/* #define IRQ_FC_EVT_CLUSTER_CG_OK	   23 */
+/* #define IRQ_FC_EVT_PICL_OK     24 */
+/* #define IRQ_FC_EVT_SCU_OK      25 */
+/*
+ * SoC event unit events: Many events get implicitely muxed into this interrupt.
+ * A user that gets such an interrupt has to check the event unit's registers to
+ * see what happened
+ */
+#define IRQ_FC_EVT_SOC_EVT BIT(26)
+/*
+ * Event queue error: If we don't process event unit events quickly enough
+ * internal fifos can overflow and we get this error interrupt
+ */
+#define IRQ_FC_EVT_QUIRQE_ERROR BIT(29)
+/* High priority peripheral events: these are hardcoded to directly go to the
+ * core using a dedicated interrupt line
+ */
+#define IRQ_FC_EVT_PERIPH0 BIT(30)
+#define IRQ_FC_EVT_PERIPH1 BIT(31)
+
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CFG_REG_LO;                   /*!< Offset: 0x000 (R/W)  SysTick Configuration Register for lower 32-bits */
+  __IOM uint32_t CFG_REG_HI;                   /*!< Offset: 0x004 (R/W)  SysTick Configuration Register for high 32-bits */
+  __IOM uint32_t VALUE_LO;                     /*!< Offset: 0x008 (R/W)  SysTick Timer Value Register for low 32-bits */
+  __IOM uint32_t VALUE_HI;                     /*!< Offset: 0x00C (R/W)  SysTick Timer Value Register for high 32-bits */
+  __IOM uint32_t CMP_LO;                       /*!< Offset: 0x010 (R/W)  SysTick Timer comparator Register for low 32-bits */
+  __IOM uint32_t CMP_HI;                       /*!< Offset: 0x014 (R/W)  SysTick Timer comparator Register for high 32-bits */
+  __OM  uint32_t START_LO;                     /*!< Offset: 0x014 (R/W)  SysTick Timer start Register for low 32-bits */
+  __OM  uint32_t START_HI;                     /*!< Offset: 0x014 (R/W)  SysTick Timer start Register for high 32-bits */
+  __OM  uint32_t RESET_LO;                     /*!< Offset: 0x014 (R/W)  SysTick Timer reset Register for low 32-bits */
+  __OM  uint32_t RESET_HI;                     /*!< Offset: 0x014 (R/W)  SysTick Timer reset Register for high 32-bits */
+
+} SysTick_Type, timer_periph_t;
+
+/**
+  \brief  Structure type to access the System Timer Low.
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                         /*!< Offset: 0x000 (R/W)  TIMERL Configuration Register for lower 32-bits */
+	uint32_t _reserved0;                   /*!< Offset: 0x004 (R/W)  Empty Registers */
+  __IOM uint32_t VALUE;                        /*!< Offset: 0x008 (R/W)  TIMERL Timer Value Register for low 32-bits */
+	uint32_t _reserved1;                   /*!< Offset: 0x00C (R/W)  Empty Registers */
+  __IOM uint32_t COMPARE;                      /*!< Offset: 0x010 (R/W)  TIMERL Timer comparator Register for low 32-bits */
+	uint32_t _reserved2;                   /*!< Offset: 0x014 (R/W)  Empty Registers */
+  __OM  uint32_t START;                        /*!< Offset: 0x014 (R/W)  SysTick Timer start Register for low 32-bits */
+	uint32_t _reserved3;                   /*!< Offset: 0x014 (R/W)  Empty Registers */
+  __OM  uint32_t RESET;                        /*!< Offset: 0x014 (R/W)  SysTick Timer reset Register for low 32-bits */
+} TimerL_Type;
+
+/**
+  \brief  Structure type to access the System Timer Low.
+ */
+typedef struct
+{
+	uint32_t _reserved0;                   /*!< Offset: 0x000 (R/W)  Empty Registers */
+  __IOM uint32_t CTRL;                         /*!< Offset: 0x004 (R/W)  TIMERH Configuration Register for high 32-bits */
+	uint32_t _reserved1;                   /*!< Offset: 0x008 (R/W)  Empty Registers */
+  __IOM uint32_t VALUE;                        /*!< Offset: 0x00C (R/W)  TIMERH Timer Value Register for high 32-bits */
+	uint32_t _reserved2;                   /*!< Offset: 0x010 (R/W)  Empty Registers */
+  __IOM uint32_t COMPARE;                      /*!< Offset: 0x014 (R/W)  TIMERH Timer comparator Register for high 32-bits */
+	uint32_t _reserved3;                   /*!< Offset: 0x014 (R/W)  Empty Registers */
+  __OM  uint32_t START;                        /*!< Offset: 0x014 (R/W)  SysTick Timer start Register for high 32-bits */
+	uint32_t _reserved4;                   /*!< Offset: 0x014 (R/W)  Empty Registers */
+  __OM  uint32_t RESET;                        /*!< Offset: 0x014 (R/W)  SysTick Timer reset Register for high 32-bits */
+} TimerH_Type;
+
+
+/* TIMERL configuration low Register Definitions */
+#define TIMERL_CFG_REG_LOW_64BIT_Pos         31U                                            /*!< TIMERL CFG_REG_LOW: 64BIT Position */
+#define TIMERL_CFG_REG_LOW_64BIT_Msk         (1UL << TIMERL_CFG_REG_LOW_64BIT_Pos)         /*!< TIMERL CFG_REG_LOW: 64BIT Mask */
+
+#define TIMERL_CFG_REG_LOW_PRESCALER_Pos     8U                                             /*!< TIMERL CFG_REG_LOW: PRESCALER Position */
+#define TIMERL_CFG_REG_LOW_PRESCALER_Msk     (FFUL << TIMERL_CFG_REG_LOW_PRESCALER_Pos)    /*!< TIMERL CFG_REG_LOW: PRESCALER Mask */
+
+#define TIMERL_CFG_REG_LOW_CLKS_Pos          7U                                             /*!< TIMERL CFG_REG_LOW: CLKS Position */
+#define TIMERL_CFG_REG_LOW_CLKS_Msk          (1UL << TIMERL_CFG_REG_LOW_CLKS_Pos)          /*!< TIMERL CFG_REG_LOW: CLKS Mask */
+
+#define TIMERL_CFG_REG_LOW_PRESCALERE_Pos    6U                                             /*!< TIMERL CFG_REG_LOW: PRESCALERE Position */
+#define TIMERL_CFG_REG_LOW_PRESCALERE_Msk    (1UL << TIMERL_CFG_REG_LOW_PRESCALERE_Pos)    /*!< TIMERL CFG_REG_LOW: PRESCALERE Mask */
+
+#define TIMERL_CFG_REG_LOW_ONE_SHOT_Pos      5U                                             /*!< TIMERL CFG_REG_LOW: ONE_SHOT Position */
+#define TIMERL_CFG_REG_LOW_ONE_SHOT_Msk      (1UL << TIMERL_CFG_REG_LOW_ONE_SHOT_Pos)      /*!< TIMERL CFG_REG_LOW: ONE_SHOT Mask */
+
+#define TIMERL_CFG_REG_LOW_CMP_CLR_Pos       4U                                             /*!< TIMERL CFG_REG_LOW: CMP_CLR Position */
+#define TIMERL_CFG_REG_LOW_CMP_CLR_Msk       (1UL << TIMERL_CFG_REG_LOW_CMP_CLR_Pos)       /*!< TIMERL CFG_REG_LOW: CMP_CLR Mask */
+
+#define TIMERL_CFG_REG_LOW_IEM_Pos           3U                                             /*!< TIMERL CFG_REG_LOW: IEM Position */
+#define TIMERL_CFG_REG_LOW_IEM_Msk           (1UL << TIMERL_CFG_REG_LOW_IEM_Pos)           /*!< TIMERL CFG_REG_LOW: IEM Mask */
+
+#define TIMERL_CFG_REG_LOW_IRQE_Pos          2U                                             /*!< TIMERL CFG_REG_LOW: IRQE Position */
+#define TIMERL_CFG_REG_LOW_IRQE_Msk          (1UL << TIMERL_CFG_REG_LOW_IRQE_Pos)          /*!< TIMERL CFG_REG_LOW: IRQE Mask */
+
+#define TIMERL_CFG_REG_LOW_RESET_Pos         1U                                             /*!< TIMERL CFG_REG_LOW: RESET Position */
+#define TIMERL_CFG_REG_LOW_RESET_Msk         (1UL << TIMERL_CFG_REG_LOW_RESET_Pos)         /*!< TIMERL CFG_REG_LOW: RESET Mask */
+
+#define TIMERL_CFG_REG_LOW_ENABLE_Pos        0U                                             /*!< TIMERL CFG_REG_LOW: ENABLE Position */
+#define TIMERL_CFG_REG_LOW_ENABLE_Msk        (1UL << TIMERL_CFG_REG_LOW_ENABLE_Pos)        /*!< TIMERL CFG_REG_LOW: ENABLE Mask */
+
+/* TIMERH configuration high Register Definitions */
+#define TIMERH_CFG_REG_HIGH_ERCLK_Pos        7U                                             /*!< TIMERH CFG_REG_HIGH: Enable ref clock Position */
+#define TIMERH_CFG_REG_HIGH_ERCLK_Msk        (1UL << TIMERH_CFG_REG_HIGH_ERCLK_Pos)        /*!< TIMERH CFG_REG_HIGH: Enable ref clock Mask */
+
+#define TIMERH_CFG_REG_HIGH_PRESCALERE_Pos   6U                                             /*!< TIMERH CFG_REG_HIGH: PRESCALERE Position */
+#define TIMERH_CFG_REG_HIGH_PRESCALERE_Msk   (1UL << TIMERH_CFG_REG_HIGH_PRESCALERE_Pos)   /*!< TIMERH CFG_REG_HIGH: PRESCALERE Mask */
+
+#define TIMERH_CFG_REG_HIGH_ONE_SHOT_Pos     5U                                             /*!< TIMERH CFG_REG_HIGH: ONE_SHOT Position */
+#define TIMERH_CFG_REG_HIGH_ONE_SHOT_Msk     (1UL << TIMERH_CFG_REG_HIGH_ONE_SHOT_Pos)     /*!< TIMERH CFG_REG_HIGH: ONE_SHOT Mask */
+
+#define TIMERH_CFG_REG_HIGH_CMP_CLR_Pos      4U                                             /*!< TIMERH CFG_REG_HIGH: CMP_CLR Position */
+#define TIMERH_CFG_REG_HIGH_CMP_CLR_Msk      (1UL << TIMERH_CFG_REG_HIGH_CMP_CLR_Pos)      /*!< TIMERH CFG_REG_HIGH: CMP_CLR Mask */
+
+#define TIMERH_CFG_REG_HIGH_IEM_Pos          3U                                             /*!< TIMERH CFG_REG_HIGH: IEM Position */
+#define TIMERH_CFG_REG_HIGH_IEM_Msk          (1UL << TIMERH_CFG_REG_HIGH_IEM_Pos)          /*!< TIMERH CFG_REG_HIGH: IEM Mask */
+
+#define TIMERH_CFG_REG_HIGH_IRQE_Pos         2U                                             /*!< TIMERH CFG_REG_HIGH: IRQE Position */
+#define TIMERH_CFG_REG_HIGH_IRQE_Msk         (1UL << TIMERH_CFG_REG_HIGH_IRQE_Pos)         /*!< TIMERH CFG_REG_HIGH: IRQE Mask */
+
+#define TIMERH_CFG_REG_HIGH_RESET_Pos        1U                                             /*!< TIMERH CFG_REG_HIGH: RESET Position */
+#define TIMERH_CFG_REG_HIGH_RESET_Msk        (1UL << TIMERH_CFG_REG_HIGH_RESET_Pos)        /*!< TIMERH CFG_REG_HIGH: RESET Mask */
+
+#define TIMERH_CFG_REG_HIGH_ENABLE_Pos       0U                                             /*!< TIMERH CFG_REG_HIGH: ENABLE Position */
+#define TIMERH_CFG_REG_HIGH_ENABLE_Msk       (1UL << /*TIMERH_CFG_REG_HIGH_ENABLE_Pos*/)   /*!< TIMERH CFG_REG_HIGH: ENABLE Mask */
+
+
+/* SysTick configuration low Register Definitions */
+#define SysTick_CFG_REG_LOW_64BIT_Pos         TIMERL_CFG_REG_LOW_64BIT_Pos
+#define SysTick_CFG_REG_LOW_64BIT_Msk         TIMERL_CFG_REG_LOW_64BIT_Msk
+
+#define SysTick_CFG_REG_LOW_PRESCALER_Pos     TIMERL_CFG_REG_LOW_PRESCALER_Pos
+#define SysTick_CFG_REG_LOW_PRESCALER_Msk     TIMERL_CFG_REG_LOW_PRESCALER_Msk
+
+#define SysTick_CFG_REG_LOW_CLKS_Pos          TIMERL_CFG_REG_LOW_CLKS_Pos
+#define SysTick_CFG_REG_LOW_CLKS_Msk          TIMERL_CFG_REG_LOW_CLKS_Msk
+
+#define SysTick_CFG_REG_LOW_PRESCALERE_Pos    TIMERL_CFG_REG_LOW_PRESCALERE_Pos
+#define SysTick_CFG_REG_LOW_PRESCALERE_Msk    TIMERL_CFG_REG_LOW_PRESCALERE_Msk
+
+#define SysTick_CFG_REG_LOW_ONE_SHOT_Pos      TIMERL_CFG_REG_LOW_ONE_SHOT_Pos
+#define SysTick_CFG_REG_LOW_ONE_SHOT_Msk      TIMERL_CFG_REG_LOW_ONE_SHOT_Msk
+
+#define SysTick_CFG_REG_LOW_CMP_CLR_Pos       TIMERL_CFG_REG_LOW_CMP_CLR_Pos
+#define SysTick_CFG_REG_LOW_CMP_CLR_Msk       TIMERL_CFG_REG_LOW_CMP_CLR_Msk
+
+#define SysTick_CFG_REG_LOW_IEM_Pos           TIMERL_CFG_REG_LOW_IEM_Pos
+#define SysTick_CFG_REG_LOW_IEM_Msk           TIMERL_CFG_REG_LOW_IEM_Msk
+
+#define SysTick_CFG_REG_LOW_IRQE_Pos          TIMERL_CFG_REG_LOW_IRQE_Pos
+#define SysTick_CFG_REG_LOW_IRQE_Msk          TIMERL_CFG_REG_LOW_IRQE_Msk
+
+#define SysTick_CFG_REG_LOW_RESET_Pos         TIMERL_CFG_REG_LOW_RESET_Pos
+#define SysTick_CFG_REG_LOW_RESET_Msk         TIMERL_CFG_REG_LOW_RESET_Msk
+
+#define SysTick_CFG_REG_LOW_ENABLE_Pos        TIMERL_CFG_REG_LOW_ENABLE_Pos
+#define SysTick_CFG_REG_LOW_ENABLE_Msk        TIMERL_CFG_REG_LOW_ENABLE_Msk
+
+/* SysTick configuration high Register Definitions */
+#define SysTick_CFG_REG_HIGH_ERCLK_Pos        TIMERH_CFG_REG_HIGH_ERCLK_Pos
+#define SysTick_CFG_REG_HIGH_ERCLK_Msk        TIMERH_CFG_REG_HIGH_ERCLK_Msk
+
+#define SysTick_CFG_REG_HIGH_PRESCALERE_Pos   TIMERH_CFG_REG_HIGH_PRESCALERE_Pos
+#define SysTick_CFG_REG_HIGH_PRESCALERE_Msk   TIMERH_CFG_REG_HIGH_PRESCALERE_Msk
+
+#define SysTick_CFG_REG_HIGH_ONE_SHOT_Pos     TIMERH_CFG_REG_HIGH_ONE_SHOT_Pos
+#define SysTick_CFG_REG_HIGH_ONE_SHOT_Msk     TIMERH_CFG_REG_HIGH_ONE_SHOT_Msk
+
+#define SysTick_CFG_REG_HIGH_CMP_CLR_Pos      TIMERH_CFG_REG_HIGH_CMP_CLR_Pos
+#define SysTick_CFG_REG_HIGH_CMP_CLR_Msk      TIMERH_CFG_REG_HIGH_CMP_CLR_Msk
+
+#define SysTick_CFG_REG_HIGH_IEM_Pos          TIMERH_CFG_REG_HIGH_IEM_Pos
+#define SysTick_CFG_REG_HIGH_IEM_Msk          TIMERH_CFG_REG_HIGH_IEM_Msk
+
+#define SysTick_CFG_REG_HIGH_IRQE_Pos         TIMERH_CFG_REG_HIGH_IRQE_Pos
+#define SysTick_CFG_REG_HIGH_IRQE_Msk         TIMERH_CFG_REG_HIGH_IRQE_Msk
+
+#define SysTick_CFG_REG_HIGH_RESET_Pos        TIMERH_CFG_REG_HIGH_RESET_Pos
+#define SysTick_CFG_REG_HIGH_RESET_Msk        TIMERH_CFG_REG_HIGH_RESET_Msk
+
+#define SysTick_CFG_REG_HIGH_ENABLE_Pos       TIMERH_CFG_REG_HIGH_ENABLE_Pos
+#define SysTick_CFG_REG_HIGH_ENABLE_Msk       TIMERH_CFG_REG_HIGH_ENABLE_Msk
+/*@} end of group CMSIS_SysTick */
+
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#error "PULP doesn't have an MPU"
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IOM uint32_t MPU_ENABLE;                 /*!< Offset: 0x000 (R/W)  MPU Enable Register */
+  __IOM uint32_t _reserved0[15];             /*!< Offset: 0x004 (R/W)  Empty Registers */
+  __IOM uint32_t FC_TCDM_RULE[8];            /*!< Offset: 0x040 (R/W)  MPU FC TCMD Rules Registers */
+  __IOM uint32_t _reserved1[8];              /*!< Offset: 0x060 (R/W)  Empty Registers */
+  __IOM uint32_t L2_RULE[8];                 /*!< Offset: 0x080 (R/W)  MPU L2 Rules Registers */
+  __IOM uint32_t _reserved2[8];              /*!< Offset: 0x0A0 (R/W)  Empty Registers */
+  __IOM uint32_t APB_RULE[8];                /*!< Offset: 0x0C0 (R/W)  MPU APB Rules Registers */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_ENABLE_Pos               0U                                            /*!< MPU TYPE: ENABLE Position */
+#define MPU_TYPE_ENABLE_Msk               (0x1L /*<< MPU_TYPE_ENABLE_Pos*/)             /*!< MPU TYPE: ENABLE Mask */
+
+#define MPU_TYPE_RULE_STATE_Pos           0U                                            /*!< MPU TYPE: RULE_STATE Position */
+#define MPU_TYPE_RULE_STATE_Msk           (0x1L /*<< MPU_TYPE_RULE_STATE_Pos*/)             /*!< MPU TYPE: RULE_STATE Mask */
+
+#define MPU_TYPE_RULE_SIZE_Pos            1U                                            /*!< MPU TYPE: RULE_SIZE Position */
+#define MPU_TYPE_RULE_SIZE_Msk            (0x3FFFL << MPU_TYPE_RULE_SIZE_Pos)           /*!< MPU TYPE: RULE_SIZE Mask */
+
+#define MPU_TYPE_RULE_BASE_Pos            15U                                           /*!< MPU TYPE: RULE_BASE Position */
+#define MPU_TYPE_RULE_BASE_Msk            (0x7FFFL << MPU_TYPE_RULE_BASE_Pos)           /*!< MPU TYPE: RULE_BASE Mask */
+
+#define MPU_TYPE_RULE_AREA_Pos            30U                                           /*!< MPU TYPE: RULE_AREA Position */
+#define MPU_TYPE_RULE_AREA_Msk            (0x3L << MPU_TYPE_RULE_AREA_Pos)              /*!< MPU TYPE: RULE_AREA Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+/* #define CL_PERI_BASE        (0x10000000UL) */
+
+#define FC_BASE             (0x1B000000UL)                             /*!< FC Base Address */
+
+#define SOC_ROM_BASE        ROM_ADDR                                   /*!< SOC ROM Base Address */
+// phasing out
+//#define SOC_PERI_BASE       SOC_PERIPHERALS_ADDR                       /*!< SOC Peripherals Base Address */
+
+#define CORE_PERI_BASE      (0x00200000UL)                             /*!< RISC Core Peripheral Base Address */
+#define CORE_SCB_BASE       (CORE_PERI_BASE)                           /*!< RISC Core System Control Block Base Address */
+#define CORE_SCBC_BASE      (CORE_PERI_BASE +  0x1400UL)               /*!< RISC Core System Control Block Cache Base Address */
+
+#define CORE_EU_BASE        (0x00200800UL)                             /*!< RISC Core Event Unit Base Address */
+#define CORE_EU_BARRIER_BASE         (CORE_EU_BASE + 0x0400UL)         /*!< RISC Core Event Unit HW Barrier Base Address */
+#define CORE_EU_SW_EVENTS_BASE       (CORE_EU_BASE + 0x0600UL)         /*!< RISC Core Event Unit SW Events Base Address */
+#define CORE_EU_SOC_EVENTS_BASE      (CORE_EU_BASE + 0x0700UL)         /*!< RISC Core Event Unit SOC Events Base Address */
+#define CORE_EU_EXT_EVENTS_BASE      (CORE_EU_BASE + 0x0780UL)         /*!< RISC Core Event Unit External Events Base Address */
+
+
+#define CORE_EU_DEMUX_BASE  (0x00204000UL)                             /*!< RISC Core Event Unit Demux Base Address */
+#define CORE_EU_CORE_DEMUX_BASE      (CORE_EU_DEMUX_BASE)              /*!< RISC Core Event Unit Core Demux Base Address */
+#define CORE_EU_SEC_DEMUX_BASE       (CORE_EU_DEMUX_BASE + 0x0040UL)   /*!< RISC Core Event Unit Security Demux Base Address */
+#define CORE_EU_LOOP_DEMUX_BASE      (CORE_EU_DEMUX_BASE + 0x0060UL)   /*!< RISC Core Event Unit Loop Demux Base Address */
+#define CORE_EU_DISPATCH_DEMUX_BASE  (CORE_EU_DEMUX_BASE + 0x0080UL)   /*!< RISC Core Event Unit Dispatch Demux Base Address */
+#define CORE_EU_MUTEX_DEMUX_BASE     (CORE_EU_DEMUX_BASE + 0x00C0UL)   /*!< RISC Core Event Unit Mutex Demux Base Address */
+#define CORE_EU_SW_EVENTS_DEMUX_BASE (CORE_EU_DEMUX_BASE + 0x0100UL)   /*!< RISC Core Event Unit SW Event Demux Base Address */
+#define CORE_EU_BARRIER_DEMUX_BASE   (CORE_EU_DEMUX_BASE + 0x0200UL)   /*!< RISC Core Event Unit HW Barrier Demux Base Address */
+
+
+#define CORE_MCHAN_BASE     (CORE_EU_DEMUX_BASE + 0x0400UL)            /*!< RISC Core DMAMCHAN Base Address between L2 and Cluster TCDM */
+
+/* FC core Memory map */
+#define FC_SCBC_BASE        (FC_BASE + CORE_SCBC_BASE)                 /*!< FC System Control Block Cache Base Address */
+
+#define FC_EU_BARRIER_BASE         (FC_BASE + CORE_EU_BARRIER_BASE)    /*!< FC Event Unit HW Barrier Base Address */
+#define FC_EU_SW_EVENTS_BASE       (FC_BASE + CORE_EU_SW_EVENTS_BASE)  /*!< FC Event Unit SW Events Base Address */
+#define FC_EU_SOC_EVENTS_BASE      (FC_BASE + CORE_EU_SOC_EVENTS_BASE) /*!< FC Event Unit SOC Events Base Address */
+#define FC_EU_EXT_EVENTS_BASE      (FC_BASE + CORE_EU_EXT_EVENTS_BASE) /*!< FC Event Unit EXT Events Base Address */
+
+
+#define FC_EU_CORE_DEMUX_BASE      (FC_BASE + CORE_EU_CORE_DEMUX_BASE)        /*!< FC Event Unit Core Demux Base Address */
+#define FC_EU_SEC_DEMUX_BASE       (FC_BASE + CORE_EU_SEC_DEMUX_BASE)         /*!< FC Event Unit Security Demux Base Address */
+#define FC_EU_LOOP_DEMUX_BASE      (FC_BASE + CORE_EU_LOOP_DEMUX_BASE)        /*!< FC Event Unit Loop Demux Base Address */
+#define FC_EU_DISPATCH_DEMUX_BASE  (FC_BASE + CORE_EU_DISPATCH_DEMUX_BASE)    /*!< FC Event Unit Dispatch Demux Base Address */
+#define FC_EU_MUTEX_DEMUX_BASE     (FC_BASE + CORE_EU_MUTEX_DEMUX_BASE)       /*!< FC Event Unit Mutex Demux Base Address */
+#define FC_EU_SW_EVENTS_DEMUX_BASE (FC_BASE + CORE_EU_SW_EVENTS_DEMUX_BASE)   /*!< FC Event Unit SW Events Demux Base Address */
+#define FC_EU_BARRIER_DEMUX_BASE   (FC_BASE + CORE_EU_BARRIER_DEMUX_BASE)     /*!< FC Event Unit Barrier Demux Base Address */
+
+#define FC_MCHAN_BASE              (FC_BASE + CORE_MCHAN_BASE)                /*!< FC DMAMCHAN Base Address between L2 and Cluster TCDM */
+
+#define SCBC                ((SCBC_Type   *)   CORE_SCBC_BASE )               /*!< Icache SCBC configuration struct */
+
+/* Core Structrue definitions */
+#define SysTick             ((SysTick_Type *) FC_TIMER_ADDR)    /*!< SysTick configuration struct */
+#define TIMERL              ((TimerL_Type  *) FC_TIMER_ADDR)    /*!< SysTick configuration struct */
+#define TIMERH              ((TimerH_Type  *) FC_TIMER_ADDR)    /*!< SysTick configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+  #define FC_MPU_BASE       (FC_BASE + CORE_PERI_BASE + 0x4400UL)         /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     FC_MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#define EU_SW_EVENTS         ((EU_SW_EVENTS_DEMUX_Type   *)  CORE_EU_SW_EVENTS_BASE)          /*!< EU_SW_EVENTS_DEMUX configuration struct */
+#define EU_SOC_EVENTS        ((EU_SOC_EVENTS_Type   *)      CORE_EU_SOC_EVENTS_BASE)          /*!< EU_SW_EVENTS_DEMUX configuration struct */
+
+
+#define NVIC                ((NVIC_Type   *)      FC_IRQ_ADDR)                       /*!< NVIC configuration struct */
+
+#define EU_CORE_DEMUX       ((EU_CORE_DEMUX_Type   *)      CORE_EU_CORE_DEMUX_BASE)         /*!< EU_CORE_DEMUX configuration struct */
+#define EU_SEC_DEMUX        ((EU_SEC_DEMUX_Type   *)       CORE_EU_SEC_DEMUX_BASE)          /*!< EU_SEC_DEMUX configuration struct */
+#define EU_LOOP_DEMUX       ((EU_LOOP_DEMUX_Type   *)      CORE_EU_LOOP_DEMUX_BASE)         /*!< EU_LOOP_DEMUX configuration struct */
+#define EU_DISPATCH_DEMUX   ((EU_DISPATCH_DEMUX_Type   *)  CORE_EU_DISPATCH_DEMUX_BASE)     /*!< EU_DISPATCH_DEMUX configuration struct */
+#define EU_MUTEX_DEMUX      ((EU_MUTEX_DEMUX_Type   *)     CORE_EU_MUTEX_DEMUX_BASE)        /*!< EU_MUTEX_DEMUX configuration struct */
+#define EU_SW_EVENTS_DEMUX  ((EU_SW_EVENTS_DEMUX_Type   *) CORE_EU_SW_EVENTS_DEMUX_BASE)    /*!< EU_SW_EVENTS_DEMUX configuration struct */
+#define EU_BARRIER_DEMUX(id) ((EU_BARRIER_DEMUX_Type   *)   (CORE_EU_BARRIER_DEMUX_BASE+(id*sizeof(EU_BARRIER_DEMUX_Type))))      /*!< EU_BARRIER_DEMUX configuration struct */
+#define DMAMCHAN            ((DMAMCHAN_Type   *)   CORE_MCHAN_BASE)                              /*!< MCHAN DMA configuration struct */
+#define DMAMCHAN_COMPRESSOR ((decompressor_t *) CORE_MCHAN_COMPRESSOR_BASE)
+
+#define FC_EU_SW_EVENTS      ((EU_SW_EVENTS_DEMUX_Type   *)  FC_EU_SW_EVENTS_BASE)            /*!< EU_SW_EVENTS_DEMUX configuration struct */
+
+/** FC_CLUSTER_ID Definitions */
+#define FC_CLUSTER_ID                 32                /**< FC CLuster ID */
+/*@} */
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core Function Access
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+/**
+  \brief   Get PRIVLVL Register
+  \details Returns the content of the PRIVLVL Register.
+  \return               PRIVLVL Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CPRIV(void)
+{
+    uint32_t result = csr_read(CPRIV_ADDR);
+    return result;
+}
+
+/**
+  \brief   Restore the MIE bit
+  \details Restore the MIE bit of MSTATUS
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __restore_irq(int irq)
+{
+    // We are in machine mode, already mask all interrupt, so just set MIE = irq
+    /* __builtin_pulp_spr_write(0x300, irq); */
+    csr_write(MSTATUS_ADDR, irq);
+}
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by setting the MPIE-bit in the MSTATUS.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
+{
+    csr_read_set(MSTATUS_ADDR, BIT(MSTATUS_MIE_Pos));
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by clearing the MPIE-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__attribute__((always_inline)) __STATIC_INLINE int __disable_irq(void)
+{
+    uint32_t val = csr_read_clear(MSTATUS_ADDR, BIT(MSTATUS_MIE_Pos));
+    return val;
+}
+
+/**
+  \brief   Set ustatus Register
+  \details Writes the given value to the ustatus Register.
+  \param [in]    control  ustatus Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_USTATUS(uint32_t control)
+{
+    assert(0);
+}
+
+/**
+  \brief   Set mstatus Register
+  \details Writes the given value to the mstatus Register.
+  \param [in]    control  mstatus Register value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSTATUS(uint32_t control)
+{
+    csr_write(MSTATUS_ADDR, control);
+}
+
+/**
+  \brief   Get MCAUSE Register
+  \details Returns the content of the MCAUSE Register.
+  \return               MCAUSE Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MCAUSE(void)
+{
+    uint32_t result = csr_read(MCAUSE_ADDR);
+    return result;
+}
+
+/**
+  \brief   Get UCAUSE Register
+  \details Returns the content of the UCAUSE Register.
+  \return               UCAUSE Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_UCAUSE(void)
+{
+    uint32_t result = csr_read(UCAUSE_ADDR);
+    return result;
+}
+
+/**
+  \brief   Get MSTATUS Register
+  \details Returns the content of the MSTATUS Register.
+  \return               MSTATUS Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSTATUS(void)
+{
+    uint32_t result = csr_read(MSTATUS_ADDR);
+    return result;
+}
+
+
+/**
+  \brief   Get USTATUS Register
+  \details Returns the content of the USTATUS Register.
+  \return               USTATUS Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_USTATUS(void)
+{
+    assert(0);
+}
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
+{
+    assert(0);
+  /* register uint32_t result; */
+
+  /* __ASM volatile ("lw %0, (userStack)"  : "=r" (result) ); */
+  /* return(result); */
+}
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+    assert(0);
+  /* __ASM volatile ("sw %0, (userStack)(x0)"  :: "r" (topOfProcStack) ); */
+}
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
+{
+    assert(0);
+  /* register uint32_t result; */
+
+  /* __ASM volatile ("lw %0, (kernelStack)" : "=r" (result) ); */
+  /* return(result); */
+}
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+    assert(0);
+    /*__ASM volatile ("sw %0, (kernelStack)(x0)"  :: "r" (topOfMainStack) ); */
+}
+
+/**
+  \brief   Get the running mode is User Mode
+  \details Read 0xC10 privilege register
+  \return               Is User mode
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __is_U_Mode()
+{
+    uint32_t mode = csr_read(CPRIV_ADDR);
+    return ((mode & 0x3) == 0);
+}
+
+/**
+  \brief   Get the running mode is Machine Mode
+  \details Read 0xC10 privilege register
+  \return               Is Machine mode
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __is_M_Mode()
+{
+    uint32_t mode = csr_read(CPRIV_ADDR);
+    return ((mode & 0x3) == 1);
+}
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+/* keeps this for backwards compatibility */
+  #define NVIC_EnableIRQ              __irq_enable
+  #define NVIC_GetEnableIRQ           __irq_get_enable
+  #define NVIC_DisableIRQ             __irq_disable
+  #define NVIC_GetPendingIRQ          __irq_get_pending
+  #define NVIC_SetPendingIRQ          __irq_set_pending
+  #define NVIC_ClearPendingIRQ        __irq_clear_pending
+  #define NVIC_GetActive              __irq_get_active
+  #define NVIC_SystemReset            __irq_system_reset
+/* saner names for irqs */
+  #define irqn_enable                 __irq_enable
+  #define irqn_get_enable             __irq_get_enable
+  #define irqn_disable                __irq_disable
+  #define irqn_get_pending            __irq_get_pending
+  #define irqn_set_pending            __irq_set_pending
+  #define irqn_clear_pending          __irq_clear_pending
+  #define irqn_get_active             __irq_get_active
+  #define irqn_system_reset           __irq_system_reset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+   #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __irq_set_vector
+  #define NVIC_GetVector              __irq_get_vector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          0
+#define NVIC_M_IRQ_OFFSET            32
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __irq_enable(IRQn_Type IRQn)
+{
+  /* U mode does not has the right */
+  /* NVIC->MASK_SET = (1UL << IRQn); */
+  writew(1UL << IRQn, (uintptr_t)(FC_IRQ_ADDR + IRQ_REG_MASK_SET_OFFSET));
+}
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __irq_get_enable(IRQn_Type IRQn)
+{
+  /* U mode does not has the right */
+  /* return ((uint32_t)((NVIC->MASK_IRQ & (1UL << IRQn)) ? 1UL : 0UL)); */
+  uint32_t mask = readw((uintptr_t)(FC_IRQ_ADDR + IRQ_REG_MASK_OFFSET));
+  return (mask >> IRQn) & 1;
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __irq_disable(IRQn_Type IRQn)
+{
+  /* U mode does not has the right */
+  /* NVIC->MASK_IRQ_AND = (1UL << IRQn); */
+  writew(1UL << IRQn, (uintptr_t)(FC_IRQ_ADDR + IRQ_REG_MASK_CLEAR_OFFSET));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __irq_get_pending(IRQn_Type IRQn)
+{
+    /* return(0U); */
+    uint32_t pending = readw((uintptr_t)(FC_IRQ_ADDR + IRQ_REG_INT_OFFSET));
+    return (pending >> IRQn) & 1;
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __irq_set_pending(IRQn_Type IRQn)
+{
+  writew(1UL << IRQn,(uintptr_t)(FC_IRQ_ADDR + IRQ_REG_INT_SET_OFFSET));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __irq_clear_pending(IRQn_Type IRQn)
+{
+  writew(1UL << IRQn,(uintptr_t)(FC_IRQ_ADDR + IRQ_REG_INT_CLEAR_OFFSET));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __irq_get_active(IRQn_Type IRQn)
+{
+  assert(0);
+  /* U mode does not has the right */
+  /* return ((uint32_t)((NVIC->STATUS & (1UL << IRQn)) ? 1UL : 0UL)); */
+  /* TODO */
+  return -1;
+}
+
+__STATIC_INLINE uint32_t __irq_forge_it_vect(uint32_t ItBaseAddr, uint32_t ItIndex, uint32_t ItHandler)
+
+{
+  assert(0);
+  /* Prepare 32bit container to be stored at
+   *(ItBaseAddr+ItIndex) containing a relative jump from
+    (ItBaseAddr+ItIndex) to Handler */
+
+  uint32_t S = ((uint32_t) ItHandler - (ItBaseAddr+ItIndex*4));
+  uint32_t R = 0x6F; /* Jal opcode with x0 as target, eg no return */
+
+  /* Forge JAL x0, Address: with Address = S => Bin[31:0] = [S20
+  | S10:1 | S11 | S19:12 | 00000 01101111] */
+
+
+  R = __BIT_INSERT(R, __BIT_EXTRACT(S,  1, 20),  1, 31);
+  R = __BIT_INSERT(R, __BIT_EXTRACT(S, 10,  1), 10, 21);
+  R = __BIT_INSERT(R, __BIT_EXTRACT(S,  1, 11),  1, 20);
+  R = __BIT_INSERT(R, __BIT_EXTRACT(S,  8, 12),  8, 12);
+
+  return R;
+}
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+	   The interrupt number can be positive to specify a device specific interrupt,
+	   or negative to specify a processor exception.
+	   VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __irq_set_vector(IRQn_Type IRQn, uint32_t vector)
+{
+  assert(0);
+  /*
+  volatile uint32_t *vectors;
+
+  if((__get_CPRIV() & CPRIV_PRIV_Msk) != 0U) {
+    vectors = (uint32_t *)(__builtin_pulp_spr_read(0x305));
+  } else {
+    vectors = (uint32_t *)(0x1C000000);
+  }
+  vectors[IRQn] = __NVIC_ForgeItVect((uint32_t)vectors, IRQn, vector);
+  */
+}
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+	   The interrupt number can be positive to specify a device specific interrupt,
+	   or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __irq_get_vector(IRQn_Type IRQn)
+{
+  assert(0);
+  /*
+  volatile uint32_t *vectors;
+  if((__get_CPRIV() & CPRIV_PRIV_Msk) != 0U) {
+    vectors = (uint32_t *)(__builtin_pulp_spr_read(0x305));
+  } else {
+    vectors = (uint32_t *)(0x1C000000);
+  }
+  return vectors[IRQn];
+  */
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void __irq_system_reset(void)
+{
+  assert(0);
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+#error "PULP doens't support MPU"
+#include "mpu_gap.h"
+
+#endif
+
+/* ##########################   CORE ID functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_IDFunctionInterface
+  \defgroup CMSIS_Core_IDFunctions ID Functions
+  \brief    Functions that manage Cluster and Core ID.
+  @{
+ */
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __core_ID() {
+  /* encoding of mhartid: {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
+  uint32_t mhartid = csr_read(MHARTID_ADDR);
+  return mhartid & 0x01f;
+
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __cluster_ID() {
+  /* encoding of mhartid {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
+  uint32_t mhartid = csr_read(MHARTID_ADDR);
+  return (mhartid >> 5) & 0x3f;
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __is_FC() {
+#ifndef FEATURE_CLUSTER
+  return 1;
+#else
+  return ( __cluster_ID() == FC_CLUSTER_ID);
+#endif
+}
+/*@} end of CMSIS_Core_IDFunctions */
+
+
+
+/* ##########################   CORE ID functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_PerformanceFunctionInterface
+  \defgroup CMSIS_Core_PerformanceFunctions Performance Functions
+  \brief    Functions that manage Core performance.
+  @{
+ */
+
+/* Configure the active events. eventMask is an OR of events got through SPR_PCER_EVENT_MASK */
+__attribute__((always_inline)) __STATIC_INLINE void __PCER_Set(uint32_t eventMask)
+{
+    csr_write(PCER_ADDR, eventMask);
+}
+
+/* Return events configuration */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __PCER_Get()
+{
+    uint32_t result = csr_read(PCER_ADDR);
+    return result;
+}
+
+/* Configure the mode. confMask is an OR of all SPR_PCMR_* macros */
+__attribute__((always_inline)) __STATIC_INLINE void __PCMR_Set(uint32_t value)
+{
+    csr_write(PCMR_ADDR, value);
+}
+
+/* Get the PCMR */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __PCMR_Get()
+{
+    uint32_t result = csr_read(PCER_ADDR);
+    return result;
+}
+
+/* Return the value of the specified counter */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __PCCRs_Get(const uint32_t counterId)
+{
+  uint32_t value = 0;
+
+  switch (counterId)
+  {
+      /* CYCLE */
+  case PERF_CYCLE_OFFSET: __ASM volatile ("csrr %0, 0x780" : "=r" (value)); break;
+      /* INSTR */
+  case PERF_INSTR_OFFSET: __ASM volatile ("csrr %0, 0x781" : "=r" (value)); break;
+      /* LD_STALL */
+  case PERF_LD_STALL_OFFSET: __ASM volatile ("csrr %0, 0x782" : "=r" (value)); break;
+      /* JR_STALL */
+  case PERF_JR_STALL_OFFSET: __ASM volatile ("csrr %0, 0x783" : "=r" (value)); break;
+      /* IMISS */
+  case PERF_IMISS_OFFSET: __ASM volatile ("csrr %0, 0x784" : "=r" (value)); break;
+      /* LD */
+  case PERF_LD_OFFSET: __ASM volatile ("csrr %0, 0x785" : "=r" (value)); break;
+      /* ST */
+  case PERF_ST_OFFSET: __ASM volatile ("csrr %0, 0x786" : "=r" (value)); break;
+      /* JUMP */
+  case PERF_JUMP_OFFSET: __ASM volatile ("csrr %0, 0x787" : "=r" (value)); break;
+      /* BRANCH */
+  case PERF_BRANCH_OFFSET: __ASM volatile ("csrr %0, 0x788" : "=r" (value)); break;
+      /* BTAKEN */
+  case PERF_BTAKEN_OFFSET: __ASM volatile ("csrr %0, 0x789" : "=r" (value)); break;
+      /* RVC */
+  case PERF_RVC_OFFSET: __ASM volatile ("csrr %0, 0x78A" : "=r" (value)); break;
+      /* LD_EXT */
+  case PERF_LD_EXT_OFFSET: __ASM volatile ("csrr %0, 0x78B" : "=r" (value)); break;
+      /* ST_EXT */
+  case PERF_ST_EXT_OFFSET: __ASM volatile ("csrr %0, 0x78C" : "=r" (value)); break;
+      /* LD_EXT_CYC */
+  case PERF_LD_EXT_CYC_OFFSET: __ASM volatile ("csrr %0, 0x78D" : "=r" (value)); break;
+      /* ST_EXT_CYC */
+  case PERF_ST_EXT_CYC_OFFSET: __ASM volatile ("csrr %0, 0x78E" : "=r" (value)); break;
+      /* TCDM_COUNT */
+  case PERF_TCDM_COUNT_OFFSET: __ASM volatile ("csrr %0, 0x78F" : "=r" (value)); break;
+  }
+  return value;
+}
+
+/* Special Register, a write to this register will set all counter to the supplied value */
+__attribute__((always_inline)) __STATIC_INLINE void __PCCR31_Set(uint32_t value)
+{
+    __ASM volatile ("csrw 0x79F, %0" :: "r" (value));
+}
+
+/*@} end of CMSIS_Core_PerformanceFunctions */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_PULP_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_pulp_cluster.h

@@ -0,0 +1,457 @@
+/******************************************************************************
+ * @file     core_pulp_cluster.h
+ * @brief    CMSIS PULP Core Cluster  Peripheral Access Layer Header File
+ * @version  V0.0.1
+ * @date     04. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017 GreenWaves Technologies SAS. All rights reserved.
+ * Copyright (c) 2020 ETH Zurich
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CLUSTER_PULP_H_GENERIC__
+#define __CLUSTER_PULP_H_GENERIC__
+
+#ifdef FEATURE_CLUSTER
+
+//#include "cores/TARGET_RISCV_32/core_pulp.h"
+#include "core_pulp.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+#define CLUSTER_ID                    0                 /**< CLuster ID */
+#define CLUSTER_CORES_NUM             8                 /**< CLuster cores number */
+
+#define CLUSTER_HW_MUTEX_NUM           1
+/** SoC events statically reserved by the runtime*/
+#define FC_CLUSTER_SW_NOTIF_EVENT      0                /**< Used to notify FC*/
+#define CLUSTER_CLUSTER_SW_NOTIF_EVENT 1                /**< Used to notify CLUSTER*/
+
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+   /**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __OM uint32_t EOC;                   /*!< Offset: 0x000 (R/W ) CPUID Base Register */
+  __IOM uint32_t _reserved0;           /*!< Offset: 0x004 (R/W)  reserved Register */
+  __IOM uint32_t FETCH_EN;             /*!< Offset: 0x008 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t _reserved1;           /*!< Offset: 0x00C (R/W)  reserved Register */
+  __OM  uint32_t EVENT;                /*!< Offset: 0x010 (W)  Event out Register */
+  __IOM uint32_t _reserved2[3];        /*!< Offset: 0x014 (R/W)  reserved Register */
+  __OM  uint32_t CLUSTER_CG;           /*!< Offset: 0x020 (R/W)  Event out Register */
+  __IOM uint32_t _reserved3[7];        /*!< Offset: 0x024 (R/W)  reserved Registers */
+  __IOM uint32_t BOOT_ADDR[8];         /*!< Offset: 0x040 (R/W)  Vector Table Offset Register */
+} SCB_Type;
+
+/* SCB Registers Definitions */
+#define SCB_EOC_Pos                    0U                               /*!< SCB EOC Position */
+#define SCB_EOC_Msk                    (1UL /* << SCB_EOC_Pos*/)         /*!< SCB EOC Mask */
+
+#define SCB_FETCH_EN_Pos               0U                               /*!< SCB FETCH_EN Position */
+#define SCB_FETCH_EN_Msk               (1UL /* << SCB_FETCH_EN_Pos*/)    /*!< SCB FETCH_EN Mask */
+/*@} end of group CMSIS_FC_CTRL */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCBC     System Control Block for Icache (SCBC)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+typedef struct
+{
+  __IOM uint32_t ICACHE_ENABLE;            /*!< Offset: 0x00 (R/W ) Cluster Icache Enable Register  */
+  __IOM uint32_t ICACHE_FLUSH;             /*!< Offset: 0x04 (R/W)  Cluster Icache Flush Register */
+  __IOM uint32_t ICACHE_LX_SEL_FLUSH;      /*!< Offset: 0x08 (R/W)  Cluster Icache Level-X Flush Register or FC Flush Selected Address Register*/
+  __IOM uint32_t ICACHE_SEL_FLUSH_STATUS;  /*!< Offset: 0x0C (R/W)  Cluster Icache Flush Selected Address Register or FC ICACHE status */
+  __IOM uint32_t ICACHE_CNTS_CLEAR;        /*!< Offset: 0x10 (R/W)  Cluster Icache is private Icache */
+  __IOM uint32_t ICACHE_CNTS_ENABLE;       /*!< Offset: 0x10 (R/W)  Cluster Icache is private Icache */
+} SCBC_Type;
+
+/* SCBC Registers Definitions */
+#define SCBC_ENABLE_Pos                    0U                               /*!< SCBC_ENABLE Position */
+#define SCBC_ENABLE_Msk                    (1UL /* << SCBC_ENABLE_Pos*/)         /*!< SCBC_ENABLE Mask */
+
+#define SCBC_STATUS_Pos                    0U                               /*!< SCBC_STATUS Position */
+#define SCBC_STATUS_Msk                    (1UL /* << SCBC_STATUS_Pos*/)         /*!< SCBC_STATUS Mask */
+
+/*@} end of group CMSIS_SCBC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_CORE_DEMUX     Event Unit Core
+  \brief    Type definitions for the event unit core Registers
+  @{
+ */
+/**
+  \brief  Structure type to access the EU_CORE_DEMUX.
+ */
+
+typedef struct {
+  __IOM  uint32_t MASK;                    /**< EU_DEMUX mask register, offset: 0x00 */
+  __IOM  uint32_t MASK_AND;                /**< EU_DEMUX mask and register, offset: 0x04 */
+  __IOM  uint32_t MASK_OR;                 /**< EU_DEMUX mask or register, offset: 0x08 */
+  __IOM  uint32_t MASK_IRQ;                /**< EU_DEMUX mask irq register, offset: 0x0C */
+  __IOM  uint32_t MASK_IRQ_AND;            /**< EU_DEMUX mask irq and register, offset: 0x10 */
+  __IOM  uint32_t MASK_IRQ_OR;             /**< EU_DEMUX mask irq or register, offset: 0x14 */
+  __IOM  uint32_t STATUS;                  /**< EU_DEMUX Status register, offset: 0x18 */
+  __IOM  uint32_t BUFFER;                  /**< EU_DEMUX buffer register, offset: 0x1C */
+  __IOM  uint32_t BUFFER_MASKED;           /**< EU_DEMUX buffer masked register, offset: 0x20 */
+  __IOM  uint32_t BUFFER_IRQ_MASKED;       /**< EU_DEMUX buffer irq masked register, offset: 0x24 */
+  __IOM  uint32_t BUFFER_CLEAR;            /**< EU_DEMUX buffer clear register, offset: 0x28 */
+  __IOM  uint32_t SW_EVENTS_MASK;          /**< EU_DEMUX software event mask register, offset: 0x2C */
+  __IOM  uint32_t SW_EVENTS_MASK_AND;      /**< EU_DEMUX software event mask and register, offset: 0x30 */
+  __IOM  uint32_t SW_EVENTS_MASK_OR;       /**< EU_DEMUX software event mask or register, offset: 0x34 */
+  __IOM  uint32_t EVENT_WAIT;              /**< EU_DEMUX event wait register, offset: 0x38 */
+  __IOM  uint32_t EVENT_WAIT_CLEAR;        /**< EU_DEMUX event wait clear register, offset: 0x3C */
+  __IOM  uint32_t MASK_SEC_IRQ;            /**< EU_DEMUX mask sec irq register, offset: 0x40 */
+
+} EU_CORE_DEMUX_Type;
+
+/*@} end of group CMSIS_EU_CORE_DEMUX */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_SEC_DEMUX     Event Unit Security
+  \brief    Type definitions for the event unit security Registers
+  @{
+ */
+/**
+  \brief  Structure type to access the EU_SEC_DEMUX.
+ */
+typedef struct {
+  __IOM  uint32_t MASK;             /**< EU_SEC_DEMUX mask register, offset: 0x00 */
+  __IOM  uint32_t MASK_AND;         /**< EU_SEC_DEMUX mask and register, offset: 0x04 */
+  __IOM  uint32_t MASK_OR;          /**< EU_SEC_DEMUX mask or register, offset: 0x08 */
+} EU_SEC_DEMUX_Type;
+
+#define EU_SEC_ELEM_NUM                 8
+
+/*@} end of group CMSIS_EU_DEMUX */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_LOOP_DEMUX     Event Unit Loop
+  \brief    Type definitions for the event unit Loop Registers
+  @{
+ */
+/**
+  \brief  Structure type to access the EU_LOOP_DEMUX.
+ */
+typedef struct {
+  __IOM  uint32_t STATE;             /**< EU_LOOP_DEMUX state register, offset: 0x00 */
+  __IOM  uint32_t START;             /**< EU_LOOP_DEMUX start register, offset: 0x04 */
+  __IOM  uint32_t END;               /**< EU_LOOP_DEMUX end register, offset: 0x08 */
+  __IOM  uint32_t INCR;              /**< EU_LOOP_DEMUX increment register, offset: 0x0C */
+  __IOM  uint32_t CHUNK;             /**< EU_LOOP_DEMUX chunk register, offset: 0x10 */
+  __IOM  uint32_t EPOCH;             /**< EU_LOOP_DEMUX epoch register, offset: 0x14 */
+  __IOM  uint32_t SINGLE;            /**< EU_LOOP_DEMUX single register, offset: 0x18 */
+} EU_LOOP_DEMUX_Type;
+
+#define    EU_LOOP_DEMUX_DONE_                        0x0
+#define    EU_LOOP_DEMUX_LOCKED_                      0x1
+#define    EU_LOOP_DEMUX_SKIP_                        0x2
+
+/*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_SW_EVENTS_DEMUX     Event Unit Loop
+  \brief    Type definitions for the event unit Loop Registers
+  @{
+ */
+/**
+  \brief  Structure type to access the EU_SW_EVENTS_DEMUX.
+ */
+typedef struct {
+  __IOM  uint32_t TRIGGER_SET[8];             /**< EU_SW_EVENTS_DEMUX trigger set register, offset: 0x00 */
+  __IOM  uint32_t _reserved0[8];              /*!< Offset: 0x20 (R/W)  Empty Registers */
+  __IOM  uint32_t TRIGGER_WAIT[8];            /**< EU_SW_EVENTS_DEMUX trigger wait register, offset: 0x40 */
+  __IOM  uint32_t _reserved1[8];              /*!< Offset: 0x60 (R/W)  Empty Registers */
+  __IOM  uint32_t TRIGGER_CLR[8];             /**< EU_SW_EVENTS_DEMUX trigger clear register, offset: 0x80 */
+} EU_SW_EVENTS_DEMUX_Type;
+
+
+/*@} end of group CMSIS_EU_SW_EVENTS_DEMUX */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_DISPATCH_DEMUX     Event Unit Dispatch
+  \brief    Type definitions for the event unit Dispatch Registers
+  @{
+ */
+typedef struct {
+  __IOM  uint32_t FIFO_ACCESS;             /**< EU_DISPATCH_DEMUX fifo access register, offset: 0x00 */
+  __IOM  uint32_t TEAM_CONFIG;             /**< EU_DISPATCH_DEMUX team config register, offset: 0x04 */
+} EU_DISPATCH_DEMUX_Type;
+
+#define EU_DISPATCH_DEMUX_ELEM_NUM                 8
+
+/*@} end of group CMSIS_EU_DISPATCH_DEMUX */
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_MUTEX_DEMUX     Event Unit Hardware Mutex
+  \brief    Type definitions for the event unit Dispatch Registers
+  @{
+ */
+typedef struct {
+  __IOM  uint32_t MUTEX[1];                    /**< EU_MUTEX_DEMUX mutex register, offset: 0x00 */
+} EU_MUTEX_DEMUX_Type;
+
+#define EU_MUTEX_DEMUX_ELEM_NUM                    1
+
+/*@} end of group CMSIS_EU_MUTEX_DEMUX */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_BARRIER_DEMUX     Event Unit Barrier
+  \brief    Type definitions for the event unit Barrier Registers
+  @{
+ */
+typedef struct {
+  __IOM  uint32_t TRIGGER_MASK;             /**< EU_BARRIER_DEMUX triger mask register, offset: 0x00 */
+  __IOM  uint32_t STATUS;                   /**< EU_BARRIER_DEMUX status register, offset: 0x04 */
+  __IOM  uint32_t STATUS_SUMMRY;            /**< EU_BARRIER_DEMUX status summary register, offset: 0x08 */
+  __IOM  uint32_t TARGET_MASK;              /**< EU_BARRIER_DEMUX target mask register, offset: 0x0C */
+  __IOM  uint32_t TRIGGER;                  /**< EU_BARRIER_DEMUX trigger register, offset: 0x10 */
+  __IOM  uint32_t TRIGGER_SET;              /**< EU_BARRIER_DEMUX trigger set register, offset: 0x14 */
+  __IOM  uint32_t TRIGGER_WAIT;             /**< EU_BARRIER_DEMUX trigger wait register, offset: 0x18 */
+  __IOM  uint32_t TRIGGER_WAIT_CLEAR;       /**< EU_BARRIER_DEMUX trigger clear register, offset: 0x1C */
+
+} EU_BARRIER_DEMUX_Type;
+/* We have only one HW Barrier  */
+
+/*@} end of group CMSIS_EU_BARRIER_DEMUX */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_EU_SOC_EVENTS     Event Unit Barrier
+  \brief    Type definitions for the event unit Barrier Registers
+  @{
+ */
+typedef struct {
+  __IM  uint32_t CURRENT_EVENT;             /**< EU_SOC_EVENTS current event register, offset: 0x00 */
+
+} EU_SOC_EVENTS_Type;
+/* We have only one HW Barrier  */
+
+#define EU_CURRENT_VALID_BIT_MASK                  (0x80000000U)
+#define EU_CURRENT_VALID_BIT_SHIFT                 (31U)
+#define EU_CURRENT_VALID_BIT(x)                    (((uint32_t)(((uint32_t)(x)) << EU_CURRENT_VALID_BIT_SHIFT)) & EU_CURRENT_VALID_BIT_MASK)
+
+#define EU_CURRENT_SOC_EVENT_MASK                  0xFF
+
+/*@} end of group CMSIS_EU_SOC_EVENTS */
+
+
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+   /**
+  \brief  Structure type to access the direct memory access (DMAMCHAN).
+ */
+typedef struct
+{
+  __IOM uint32_t CMD;                   /*!< Offset: 0x00 (R/W ) DMAMCHAN Command Base Register */
+  __IOM uint32_t STATUS;                /*!< Offset: 0x04 (R/W)  DMAMCHAN Channle Status Register */
+} DMAMCHAN_Type;
+
+/* DMAMCHAN Registers Definitions */
+#define DMAMCHAN_CMD_TID_Pos                    0U                               /*!< DMAMCHAN TID Position */
+#define DMAMCHAN_CMD_TID_Msk                    (0xFUL /* << DMAMCHAN_CMD_TID_Pos*/)  /*!< DMAMCHAN TID Mask */
+
+#define DMAMCHAN_CMD_BLE_Pos                    21U                              /*!< DMAMCHAN Broadcast Lines Enable Position */
+#define DMAMCHAN_CMD_BLE_Msk                    (1UL << DMAMCHAN_CMD_BLE_Pos)    /*!< DMAMCHAN CMD Broadcast Lines Enable Mask */
+
+#define DMAMCHAN_CMD_ILE_Pos                    20U                              /*!< DMAMCHAN Intrrupt Line EnableID Position */
+#define DMAMCHAN_CMD_ILE_Msk                    (1UL << DMAMCHAN_CMD_ILE_Pos)    /*!< DMAMCHAN Intrrupt Line Enable Mask */
+
+#define DMAMCHAN_CMD_ELE_Pos                    19U                              /*!< DMAMCHAN CMD Event Line Enable Position */
+#define DMAMCHAN_CMD_ELE_Msk                    (1UL << DMAMCHAN_CMD_ELE_Pos)    /*!< DMAMCHAN CMD Event Line Enable Mask */
+
+#define DMAMCHAN_CMD_2D_Pos                     18U                              /*!< DMAMCHAN CMD 2D transfer Position */
+#define DMAMCHAN_CMD_2D_Msk                     (1UL << DMAMCHAN_CMD_2D_Pos)     /*!< DMAMCHAN CMD 2D transfer Mask */
+
+#define DMAMCHAN_CMD_INC_Pos                    17U                              /*!< DMAMCHAN CMD Increment Position */
+#define DMAMCHAN_CMD_INC_Msk                    (1UL << DMAMCHAN_CMD_INC_Pos)    /*!< DMAMCHAN CMD Increment Mask */
+
+#define DMAMCHAN_CMD_TYP_Pos                    16U                              /*!< DMAMCHAN CMD Type Position */
+#define DMAMCHAN_CMD_TYP_Msk                    (1UL << DMAMCHAN_CMD_TYP_Pos)    /*!< DMAMCHAN CMD Type Mask */
+
+#define DMAMCHAN_CMD_LEN_Pos                    0U                               /*!< DMAMCHAN CMD Length Position */
+#define DMAMCHAN_CMD_LEN_Msk                    (0xFFUL /*<< DMAMCHAN_EOC_Pos*/) /*!< DMAMCHAN CMD Length Mask */
+
+#define DMAMCHAN_CMD_2D_STRIDE_Pos              16U                               /*!< DMAMCHAN CMD 2D STRIDE Position */
+#define DMAMCHAN_CMD_2D_STRIDE_Msk              (0xFFUL << DMAMCHAN_CMD_2D_STRIDE_Pos) /*!< DMAMCHAN CMD 2D STRIDE Mask */
+
+#define DMAMCHAN_CMD_2D_COUNT_Pos               0U                               /*!< DMAMCHAN CMD 2D COUNT Position */
+#define DMAMCHAN_CMD_2D_COUNT_Msk               (0xFFUL /* << DMAMCHAN_CMD_2D_COUNT_Pos*/)  /*!< DMAMCHAN CMD 2D COUNT Mask */
+
+/*@} end of group CMSIS_DMAMCHAN */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+   /**
+  \brief  Structure type to access the direct memory access compressor (DMAMCHAN).
+ */
+typedef struct
+{
+    /*!< Offset: 0x00 (W ) Compressor TCDM Address Register */
+    __O uint32_t TCDM_ADDRESS;
+    /*!< Offset: 0x04 (W ) Compressor L2 Address Register */
+    __O uint32_t L2_ADDRESS;
+    /*!< Offset: 0x08 (W ) Compressor configuration Register */
+    __O uint32_t CONFIG;
+    // 0xC
+    __IOM uint32_t PAD0;
+    /*!< Offset: 0x10 (W ) Compressor LUT patterns Register */
+    __O uint32_t LUT;
+    /*!< Offset: 0x14 (W ) Compressor compression special value Register */
+    __O uint32_t SPECIAL;
+    /*!< Offset: 0x18 (R ) Compressor readen bits Register */
+    __I uint32_t BIT_READ;
+    /*!< Offset: 0x1C (W ) Compressor transfer direction Register */
+    __O uint32_t DIRECTION;
+} DMAMCHAN_COMPRESSOR_Type;
+
+typedef struct {
+    __O uint32_t TCDM_ADDR;
+    __O uint32_t L2_ADDR;
+    __O uint32_t CONF_REG;
+    __I uint32_t STAT_REG;
+    __O uint32_t LUT_REG;
+    __O uint32_t SYMBOL_REG;
+    __O uint32_t BIT_READ_REG;
+    __O uint32_t MODE_REG;
+    __O uint32_t SW_RST_REG;
+    __O uint32_t CLKEN_REG;
+    __O uint32_t TRIGGER_REG;
+    __IOM uint32_t PAD0;
+    __O uint32_t L2_COUNT_REG;
+    __O uint32_t L2_STRIDE_REG;
+    __O uint32_t TCDM_COUNT_REG;
+    __O uint32_t TCDM_STRIDE_REG;
+} decompressor_t;
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CLUSTER_EU_CORES    Cluster Event Unit Cores
+  \brief    Type definitions for the event unit core Registers
+  @{
+ */
+/**
+  \brief  Structure type to access the CLUSTER_EU_CORES.
+ */
+
+typedef struct {
+  EU_CORE_DEMUX_Type CORES[CLUSTER_CORES_NUM];          /*!< Offset: 0x000 (R/W)  Cluster Event Unit cores */
+
+} CLUSTER_EU_CORES_Type;
+
+/*@} end of group CMSIS_CLUSTER_EU_CORE */
+
+#define CLUSTER_DISPATCH_IS_ENTRY_MASK               (0x1U)
+#define CLUSTER_DISPATCH_IS_ENTRY_SHIFT              (0U)
+#define CLUSTER_DISPATCH_IS_ENTRY(x)                 (((uint32_t)(((uint32_t)(x)) /* << CLUSTER_DISPATCH_IS_ENTRY_SHIFT */)) & CLUSTER_DISPATCH_IS_ENTRY_MASK)
+
+#define CLUSTER_DISPATCH_ENTRY_ADDR_MASK             (0x7FFFFFFEU)
+#define CLUSTER_DISPATCH_ENTRY_ADDR_SHIFT            (1U)
+#define CLUSTER_DISPATCH_ADDR_ENTRY(x)               (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_ENTRY_ADDR_SHIFT)) & CLUSTER_DISPATCH_ENTRY_ADDR_MASK)
+
+#define CLUSTER_DISPATCH_ENTRY_MASK                  (0x7FFFFFFFU)
+#define CLUSTER_DISPATCH_ENTRY_SHIFT                 (0U)
+#define CLUSTER_DISPATCH_ENTRY(x)                    (((uint32_t)(((uint32_t)(x)) /*<< CLUSTER_DISPATCH_ENTRY_SHIFT*/)) & CLUSTER_DISPATCH_ENTRY_MASK)
+#define READ_CLUSTER_DISPATCH_ENTRY(x)               (((uint32_t)(((uint32_t)(x)) & CLUSTER_DISPATCH_ENTRY_MASK)) /*>> CLUSTER_DISPATCH_ENTRY_SHIFT*/)
+
+#define CLUSTER_DISPATCH_IS_JOB_MASK                 (0x80000000U)
+#define CLUSTER_DISPATCH_IS_JOB_SHIFT                (31U)
+#define CLUSTER_DISPATCH_IS_JOB(x)                   (((uint32_t)(((uint32_t)(x)) << CLUSTER_DISPATCH_IS_JOB_SHIFT)) & CLUSTER_DISPATCH_IS_JOB_MASK)
+
+
+/* Memory map */
+
+#define CLUSTER_BASE                    (ARCHI_CLUSTER_GLOBAL_ADDR(0)) /*!< CLUSTER Base Address */
+
+#define CLUSTER_SCB_BASE                (ARCHI_CLUSTER_PERIPHERALS_GLOBAL_ADDR(0)) /*!< CLUSTER System Control Block Base Address */
+#define CLUSTER_SCBC_BASE               (ARCHI_ICACHE_CTRL_ADDR)                   /*!< CLUSTER System Control Block Cache Base Address */
+#define CLUSTER_SysTick_BASE            (ARCHI_CLUSTER_TIMER_ADDR)              /*!< CLUSTER SysTick Base Address */
+
+#define CLUSTER_EU_BARRIER_BASE         (ARCHI_EU_ADDR + 0x400UL) /*!< CLUSTER Event Unit HW Barrier Base Address */
+#define CLUSTER_EU_SW_EVENTS_BASE       (ARCHI_EU_ADDR + 0x600UL) /*!< CLUSTER Event Unit SW Events Base Address */
+#define CLUSTER_EU_SOC_EVENTS_BASE      (ARCHI_EU_ADDR + 0x700UL) /*!< CLUSTER Event Unit SOC Events Base Address */
+#define CLUSTER_EU_EXT_EVENTS_BASE      (ARCHI_EU_ADDR + 0x780UL) /*!< CLUSTER Event Unit EXT Events Base Address */
+
+
+#define CLUSTER_EU_CORE_DEMUX_BASE      (ARCHI_DEMUX_PERIPHERALS_ADDR)        /*!< CLUSTER Event Unit Core Demux Base Address */
+#define CLUSTER_EU_SEC_DEMUX_BASE       (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x040UL)  /*!< CLUSTER Event Unit Security Demux Base Address */
+#define CLUSTER_EU_LOOP_DEMUX_BASE      (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x060UL)  /*!< CLUSTER Event Unit Loop Demux Base Address */
+#define CLUSTER_EU_DISPATCH_DEMUX_BASE  (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x080UL)  /*!< CLUSTER Event Unit Dispatch Demux Base Address */
+#define CLUSTER_EU_MUTEX_DEMUX_BASE     (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x0C0UL)  /*!< CLUSTER Event Unit Mutex Demux Base Address */
+#define CLUSTER_EU_SW_EVENTS_DEMUX_BASE (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x100UL)  /*!< CLUSTER Event Unit SW Events Demux Base Address */
+#define CLUSTER_EU_BARRIER_DEMUX_BASE   (ARCHI_DEMUX_PREIPHERALS_ADDR + 0x200UL)  /*!< CLUSTER Event Unit Barrier Demux Base Address */
+
+
+/* Cluster Core Structrue definitions */
+#define CLUSTER_EU_SW_EVENTS      ((EU_SW_EVENTS_DEMUX_Type   *)  CLUSTER_EU_SW_EVENTS_BASE) /*!< EU_SW_EVENTS_DEMUX configuration struct */
+#define EU_CORES    ((CLUSTER_EU_CORES_Type   *)   ARCHI_EU_ADDR)             /*!< CLUSTER_EU_CORES configuration struct */
+#define SCB         ((SCB_Type   *)    CLUSTER_SCB_BASE )                     /*!< CLUSTER SCB configuration struct */
+#define CLUSTER_SCBC  ((SCBC_Type   *)  CLUSTER_SCBC_BASE )                   /*!< CLUSTER SCBC configuration struct */
+
+#define CLUSTER_SysTick             ((SysTick_Type   *)     CLUSTER_SysTick_BASE  )   /*!< SysTick configuration struct */
+#define CLUSTER_TIMERL              ((TimerL_Type    *)     CLUSTER_SysTick_BASE  )   /*!< SysTick configuration struct */
+#define CLUSTER_TIMERH              ((TimerH_Type    *)     CLUSTER_SysTick_BASE  )   /*!< SysTick configuration struct */
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif /* __CLUSTER_PULP_H_GENERIC */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/core_utils.h

@@ -0,0 +1,51 @@
+/*
+ * Copyright 2020 Greenwaves Technologies
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __PMSIS_CORE_UTILS__
+#define __PMSIS_CORE_UTILS__
+
+#include "csr.h"
+
+/** FC_CLUSTER_ID Definitions */
+#define FC_CLUSTER_ID                 32                /**< FC CLuster ID */
+
+/**
+  \ingroup  CMSIS_Core_IDFunctionInterface
+  \defgroup CMSIS_Core_IDFunctions ID Functions
+  \brief    Functions that manage Cluster and Core ID.
+  @{
+ */
+
+static inline uint32_t __native_core_id() {
+  /* encoding of mhartid: {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
+  uint32_t mhartid = csr_read(MHARTID_ADDR);
+  return mhartid & 0x01f;
+}
+
+static inline uint32_t __native_cluster_id() {
+  /* encoding of mhartid {21'b0, cluster_id_i[5:0], 1'b0, core_id_i[3:0]} */
+  uint32_t mhartid = csr_read(MHARTID_ADDR);
+  return 0 ;//(mhartid >> 5) & 0x3f;
+}
+
+static inline uint32_t __native_is_fc() {
+  return ( __native_cluster_id() == FC_CLUSTER_ID);
+}
+
+#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/csr.h

@@ -0,0 +1,86 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+/* Description: CSR access macros */
+
+#ifndef __CSR_H
+#define __CSR_H
+
+#include "bits.h"
+
+/* TODO: complete this */
+#define CSR_MSTATUS  0x300
+#define CSR_MISA     0x301
+#define CSR_MIE	     0x304
+#define CSR_MTVEC    0x305
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC     0x341
+#define CSR_MCAUSE   0x342
+#define CSR_MTVAL    0x343
+#define CSR_MIP	     0x344
+#define CSR_PMPCFG0  0x3a0
+#define CSR_PMPADDR0 0x3b0
+#define CSR_MHARTID  0xf14
+
+/* TODO: complete this */
+#define MSTATUS_IE BIT(3)
+
+#define __CSR_EXPAND(x) #x
+
+#define csr_read(csr)                                                          \
+	({                                                                     \
+		register unsigned long __val;                                  \
+		asm volatile("csrr %0, " __CSR_EXPAND(csr)                     \
+			     : "=r"(__val)                                     \
+			     :                                                 \
+			     : "memory");                                      \
+		__val;                                                         \
+	})
+
+#define csr_write(csr, val)                                                    \
+	({                                                                     \
+		unsigned long __val = (unsigned long)(val);                    \
+		asm volatile("csrw " __CSR_EXPAND(csr) ", %0"                  \
+			     :                                                 \
+			     : "rK"(__val)                                     \
+			     : "memory");                                      \
+	})
+
+/* TODO: I hope this properly does a memory barrier with the "memory" hint */
+#define csr_read_clear(csr, val)                                               \
+	({                                                                     \
+		unsigned long __val = (unsigned long)(val);                    \
+		asm volatile("csrrc %0, " __CSR_EXPAND(csr) ", %1"             \
+			     : "=r"(__val)                                     \
+			     : "rK"(__val)                                     \
+			     : "memory");                                      \
+		__val;                                                         \
+	})
+
+#define csr_read_set(csr, val)                                                 \
+	({                                                                     \
+		unsigned long __val = (unsigned long)(val);                    \
+		asm volatile("csrrs %0, " __CSR_EXPAND(csr) ", %1"             \
+			     : "=r"(__val)                                     \
+			     : "rK"(__val)                                     \
+			     : "memory");                                      \
+		__val;                                                         \
+	})
+
+#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pmsis_gcc.h

@@ -0,0 +1,452 @@
+/**************************************************************************//**
+ * @file     pmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.0.2
+ * @date     4. April 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2020 ETH Zurich
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+/*
+   Modifications copyright (C) 2018 GreenWaves Technologies
+
+   - Add __RISCV_ARCH_GAP__ macro define
+   - Delete and Change some Cortex-M registers access functions, and replace them by
+     RISC-V 32-bit GAP8 registers access functions
+   - Add some GAP8 builtin functions
+*/
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+#include <stdint.h>
+
+#define __RISCV_ARCH_PULP__ 1
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((noreturn))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+
+#define __get_BASEPRI()      0
+#define __get_PRIMASK()      1
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
+//{
+//  __ASM volatile ("nop");
+//}
+#define __NOP()                             __ASM volatile ("nop")       /* This implementation generates debug information */
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
+//{
+//  __ASM volatile ("wfi");
+//}
+#define __WFI()                             __ASM volatile ("wfi")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
+//{
+//  __ASM volatile ("wfe");
+//}
+#define __WFE()                             __ASM volatile ("wfe")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
+//{
+//  __ASM volatile ("sev");
+//}
+#define __SEV()                             __ASM volatile ("sev")       /* This implementation generates debug information */
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
+{
+  //  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
+{
+//  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
+{
+  //  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ             __builtin_clz
+
+
+/**
+  \ingroup PULP_BUILTIN_MARCO
+  @{
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ExtInsMaskFast(uint32_t size, uint32_t offset) { return ((((size - 1))<<5) | (offset)); }
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ExtInsMaskSafe(uint32_t size, uint32_t offset) { return ((((size - 1) & 0x1F)<<5) | (offset & 0x1F)); }
+
+/*! @brief Packing of scalars into vectors */
+#define __VEC_PACK2(x, y)                     __builtin_pulp_pack2((int16_t)  x, (int16_t)  y)
+#define __VEC_PACKU2(x, y)                    __builtin_pulp_pack2((uint16_t) x, (uint16_t) y)
+#define __VEC_PACK4(x, y, z, t)               __builtin_pulp_pack4((int8_t)   x, (int8_t)   y, (int8_t)  z, (int8_t)  t)
+#define __VEC_PACKU4(x, y, z, t)              __builtin_pulp_pack4((uint8_t)  x, (uint8_t)  y, (uint8_t) z, (uint8_t) t)
+
+/*! @brief Max */
+#define __MAX(x, y)              __builtin_pulp_maxsi((x), (y))
+#define __MAX2(x, y)             __builtin_pulp_max2(x, y)
+#define __MAX4(x, y)             __builtin_pulp_max4(x, y)
+
+#define __MAXU2(x, y)            __builtin_pulp_maxu2(x, y)
+#define __MAXU4(x, y)            __builtin_pulp_maxu4(x, y)
+
+/*! @brief Min */
+#define __MIN2(x, y)             __builtin_pulp_min2(x, y)
+#define __MIN4(x, y)             __builtin_pulp_min4(x, y)
+
+#define __MINU2(x, y)            __builtin_pulp_minu2(x, y)
+#define __MINU4(x, y)            __builtin_pulp_minu4(x, y)
+
+/*! @brief Clip */
+#define __CLIP(x, precision)     __builtin_pulp_clip(x, -(1<<(precision)), (1<<precision)-1)
+#define __CLIPU(x, precision)    __builtin_pulp_clipu(x, 0, (1<<precision)-1)
+
+/*! @brief Abs */
+#define __ABS2(x)                __builtin_pulp_abs2(x)
+#define __ABS4(x)                __builtin_pulp_abs4(x)
+
+/* Unary minus */
+#define __NEG2(x)                __builtin_pulp_neg2(x)
+#define __NEG4(x)                __builtin_pulp_neg4(x)
+
+/* Addition */
+#define __ADD2(x, y)             __builtin_pulp_add2(x, y)
+#define __ADD4(x, y)             __builtin_pulp_add4(x, y)
+
+/* Substraction */
+#define __SUB2(x, y)             __builtin_pulp_sub2(x, y)
+#define __SUB4(x, y)             __builtin_pulp_sub4(x, y)
+
+/* Average */
+#define __AVG2(x, y)             __builtin_pulp_avg2(x, y)
+#define __AVG4(x, y)             __builtin_pulp_avg4(x, y)
+
+/* Average unsigned */
+#define __AVGU2(x, y)            __builtin_pulp_avgu2(x, y)
+#define __AVGU4(x, y)            __builtin_pulp_avgu4(x, y)
+
+/* Bitwise and */
+#define __AND2(x, y)             __builtin_pulp_and2(x, y)
+#define __AND4(x, y)             __builtin_pulp_and4(x, y)
+
+/* Bitwise or */
+#define __OR2(x, y)              __builtin_pulp_or2(x, y)
+#define __OR4(x, y)              __builtin_pulp_or4(x, y)
+
+/* Bitwise exor */
+#define __EXOR2(x, y)            __builtin_pulp_exor2(x, y)
+#define __EXOR4(x, y)            __builtin_pulp_exor4(x, y)
+
+/* Logical shift right */
+#define __SRL2(x, y)             __builtin_pulp_srl2(x, y)
+#define __SRL4(x, y)             __builtin_pulp_srl4(x, y)
+
+/* Arithmetic shift right */
+#define __SRA2(x, y)             __builtin_pulp_sra2(x, y)
+#define __SRA4(x, y)             __builtin_pulp_sra4(x, y)
+
+/* Logical shift left */
+#define __SLL2(x, y)             __builtin_pulp_sll2(x, y)
+#define __SLL4(x, y)             __builtin_pulp_sll4(x, y)
+
+/*! @brief Mac */
+#define __MAC(acc, x, y)         __builtin_pulp_mac(x, y, acc)
+#define __MSU(acc, x, y)         __builtin_pulp_msu(x, y, acc)
+#define __MACS(acc, x, y)        __builtin_pulp_macs(x, y, acc)
+#define __MACHHS(acc, x, y)      __builtin_pulp_machhs(x, y, acc)
+#define __MACU(acc, x, y)        __builtin_pulp_macu(x, y, acc)
+#define __MACHHU(acc, x, y)      __builtin_pulp_machhu(x, y, acc)
+
+#define __MACSN(acc, x, y, n)      __builtin_pulp_macsN(x, y, acc, n)
+#define __MACUN(acc, x, y, n)      __builtin_pulp_macuN(x, y, acc, n)
+#define __MACSRN(acc, x, y, n)     __builtin_pulp_macsRN(x, y, acc, n, (1<<(n-1)))
+#define __MACURN(acc, x, y, n)     __builtin_pulp_macuRN(x, y, acc, n, (1<<(n-1)))
+
+#define __MACHHSN(acc, x, y, n)    __builtin_pulp_machhsN(x, y, acc, n)
+#define __MACHHUN(acc, x, y, n)    __builtin_pulp_machhuN(x, y, acc, n)
+#define __MACHHSRN(acc, x, y, n)   __builtin_pulp_machhsN(x, y, acc, n, (1<<(n-1)))
+#define __MACHHURN(acc, x, y, n)   __builtin_pulp_machhuN(x, y, acc, n, (1<<(n-1)))
+
+/*! @brief Multiplications */
+#define __MULS(x, y)            __builtin_pulp_muls(x, y)
+#define __MULU(x, y)            __builtin_pulp_mulu(x, y)
+#define __MULHHS(x, y)          __builtin_pulp_mulhhs(x, y)
+#define __MULHHU(x, y)          __builtin_pulp_mulhhu(x, y)
+
+#define __MULSN(x, y, n)        __builtin_pulp_mulsN(x, y, n)
+#define __MULSRN(x, y, n)       __builtin_pulp_mulsRN(x, y, n, (1<<(n-1)))
+#define __MULUN(x, y, n)        __builtin_pulp_muluN(x, y, n)
+#define __MULURN(x, y, n)       __builtin_pulp_muluRN(x, y, n, (1<<(n-1)))
+
+#define __MULHHSN(x, y, n)      __builtin_pulp_mulhhsN(x, y, n)
+#define __MULHHSRN(x, y, n)     __builtin_pulp_mulhhsRN(x, y, n, (1<<(n-1)))
+#define __MULHHUN(x, y, n)      __builtin_pulp_mulhhuN(x, y, n)
+#define __MULHHURN(x, y, n)     __builtin_pulp_mulhhuRN(x, y, n, (1<<(n-1)))
+
+/*! @brief Vectorial product and sum of products */
+#define __DOTP2(x, y)           __builtin_pulp_dotsp2(x, y)
+#define __DOTPU2(x, y)          __builtin_pulp_dotup2(x, y)
+#define __DOTPUS2(x, y)         __builtin_pulp_dotusp2(x, y)
+
+#define __SUM_DOTP2(x, y, z)    __builtin_pulp_sdotsp2(x, y, z)
+#define __SUM_DOTPU2(x, y, z)   __builtin_pulp_sdotup2(x, y, z)
+#define __SUM_DOTPUS2(x, y, z)  __builtin_pulp_sdotusp2(x, y, z)
+
+#define __DOTP4(x, y)           __builtin_pulp_dotsp4(x, y)
+#define __DOTPU4(x, y)          __builtin_pulp_dotup4(x, y)
+#define __DOTPUS4(x, y)         __builtin_pulp_dotusp4(x, y)
+
+#define __SUM_DOTP4(x, y, z)    __builtin_pulp_sdotsp4(x, y, z)
+#define __SUM_DOTPU4(x, y, z)   __builtin_pulp_sdotup4(x, y, z)
+#define __SUM_DOTPUS4(x, y, z)  __builtin_pulp_sdotusp4(x, y, z)
+
+
+/*! @brief Complex Multiplication, Q15x15 into Q15, with optional post scaling by 1 or 2 */
+#define __CPLX_MULS(x, y)        __builtin_pulp_cplxmuls(x, y)
+#define __CPLX_MULS_DIV2(x, y)   __builtin_pulp_cplxmulsdiv2(x, y)
+#define __CPLX_MULS_DIV4(x, y)   __builtin_pulp_cplxmulsdiv4(x, y)
+
+/*! @brief Complex conjugate */
+#define __CPLX_CONJ(x)           __builtin_pulp_cplx_conj(x)
+
+/*! @brief Complex rotation by -pi/2 */
+#define __CPLX_MJ(x)             __builtin_pulp_cplxmjrot2(x)
+
+/*! @brief Complex substration, result rotated by -pi/2 */
+#define __SUB2_ROTMJ(x, y)       __builtin_pulp_sub2rotmj(x, y)
+
+/*! @brief Complex addition with post scaling by 1 or 2 */
+#define __ADD2_DIV2(x, y)        __builtin_pulp_add2div2(x, y)
+#define __ADD2_DIV4(x, y)        __builtin_pulp_add2div4(x, y)
+
+/*! @brief Complex subtraction with post scaling by 1 or 2 */
+#define __SUB2_DIV2(x, y)        __builtin_pulp_sub2div2(x, y)
+#define __SUB2_DIV4(x, y)        __builtin_pulp_sub2div4(x, y)
+
+/*! @brief Viterbi Max and Viterbi Select, pair of Q15 */
+#define __VIT_MAX(x, y)          __builtin_pulp_vitmax2(x, y)
+#define __VIT_SEL(x, y)          __builtin_pulp_vitsel2(x, y)
+
+/*! @brief Position of the most significant bit of x */
+#define __FL1(x)                 __builtin_pulp_fl1(x)
+
+/*! @brief Number of sign bits */
+#define __CLB(x)                 __builtin_pulp_clb(x)
+
+/*! @brief Bit Extraction */
+#define __BIT_EXTRACT(src, size, off)           __builtin_pulp_bextract(src, size, off)
+#define __BIT_EXTRACTU(src, size, off)          __builtin_pulp_bextractu(src, size, off)
+
+#define __BIT_EXTRACT_R(src, size, off)         __builtin_pulp_bextract_r(src,  __ExtInsMaskFast(size, off))
+#define __BIT_EXTRACTU_R(src, size, off)        __builtin_pulp_bextractu_r(src, __ExtInsMaskFast(size, off))
+
+#define __BIT_EXTRACT_R_SAFE(src, size, off)    __builtin_pulp_bextract_r(src,  __ExtInsMaskSafe(size, off))
+#define __BIT_EXTRACTU_R_SAFE(src, size, off)   __builtin_pulp_bextractu_r(src, __ExtInsMaskSafe(size, off))
+
+/*! @brief Bit insertion */
+#define __BIT_INSERT(dst, src, size, off)        __builtin_pulp_binsert(dst, ~(((1<<size)-1)<<off), src, (((1<<size)-1)<<off), off)
+#define __BIT_INSERT_R(dst, src, size, off)      __builtin_pulp_binsert_r(dst, src, __ExtInsMaskFast(size, off))
+#define __BIT_INSERT_R_SAFE(dst, src, size, off) __builtin_pulp_binsert_r(dst, src, __ExtInsMaskSafe(size, off))
+
+/*! @brief 1 bit rotation to the right, 32 bits input */
+#define __ROTR(x)                                __builtin_pulp_rotr(x)
+
+/*! @brief Add with normalization and rounding */
+#define __ADD_ROUND_NORM(x, y, scale)            __builtin_pulp_addRN(x, y, scale, (1<<(scale-1)))
+#define __ADD_ROUND_NORM_REG(x, y, scale)        __builtin_pulp_addRN_r(x, y, scale)
+#define __ADD_ROUND_NORMU(x, y, scale)           __builtin_pulp_adduRN(x, y, scale, (1<<(scale-1)))
+#define __ADD_ROUND_NORMU_REG(x, y, scale)       __builtin_pulp_adduRN_r(x, y, scale)
+
+/*! @brief Normalization and rounding */
+#define __ROUND_NORM(x, scale)                   __builtin_pulp_addRN(x, 0, scale, (1<<(scale-1)))
+#define __ROUND_NORM_REG(x, scale)               __builtin_pulp_addRN_r(x, 0, scale)
+#define __ROUND_NORMU(x, scale)                  __builtin_pulp_adduRN(x, 0, scale, (1<<(scale-1)))
+#define __ROUND_NORMU_REG(x, scale)              __builtin_pulp_adduRN_r(x, 0, scale)
+/*@} end of group PULP_BUILTIN_MARCO */
+
+/**
+  \ingroup PULP_VECTOR_TYPE
+  @{
+ */
+typedef   signed short v2s   __attribute__((vector_size (4)));
+typedef unsigned short v2u   __attribute__((vector_size (4)));
+
+typedef   signed char  v4s   __attribute__((vector_size (4)));
+typedef unsigned char  v4u   __attribute__((vector_size (4)));
+
+typedef signed char    v4qi   __attribute__((vector_size (4)));
+typedef unsigned char  v4qu   __attribute__((vector_size (4)));
+
+typedef signed short   v2hi   __attribute__((vector_size (4)));
+typedef unsigned short v2hu   __attribute__((vector_size (4)));
+/*@} end of group PULP_VECTOR_TYPE */
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/pulp_io.h

@@ -0,0 +1,97 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+/* Description: Register I/O access
+ */
+
+#ifndef __PULP_IO_H
+#define __PULP_IO_H
+
+#include <stdint.h>
+
+/* generic I/O write */
+static inline void writeb(uint8_t val, uintptr_t addr)
+{
+	asm volatile("sb %0, 0(%1)"
+		     :
+		     : "r"(val), "r"((volatile uint8_t *)addr));
+}
+
+static inline void writeh(uint16_t val, uintptr_t addr)
+{
+	asm volatile("sh %0, 0(%1)"
+		     :
+		     : "r"(val), "r"((volatile uint16_t *)addr));
+}
+
+static inline void writew(uint32_t val, uintptr_t addr)
+{
+	asm volatile("sw %0, 0(%1)"
+		     :
+		     : "r"(val), "r"((volatile uint32_t *)addr));
+}
+
+static inline void writed(uint64_t val, uintptr_t addr)
+{
+	asm volatile("sd %0, 0(%1)"
+		     :
+		     : "r"(val), "r"((volatile uint64_t *)addr));
+}
+
+/* generic I/O read */
+static inline uint8_t readb(const uintptr_t addr)
+{
+	uint8_t val;
+
+	asm volatile("lb %0, 0(%1)"
+		     : "=r"(val)
+		     : "r"((const volatile uint8_t *)addr));
+	return val;
+}
+
+static inline uint16_t readh(const uintptr_t addr)
+{
+	uint16_t val;
+
+	asm volatile("lh %0, 0(%1)"
+		     : "=r"(val)
+		     : "r"((const volatile uint16_t *)addr));
+	return val;
+}
+
+static inline uint32_t readw(const uintptr_t addr)
+{
+	uint32_t val;
+
+	asm volatile("lw %0, 0(%1)"
+		     : "=r"(val)
+		     : "r"((const volatile uint32_t *)addr));
+	return val;
+}
+
+static inline uint64_t readd(const uintptr_t addr)
+{
+	uint64_t val;
+
+	asm volatile("ld %0, 0(%1)"
+		     : "=r"(val)
+		     : "r"((const volatile uint64_t *)addr));
+	return val;
+}
+#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_core-v-mcu_metal.h

@@ -0,0 +1,63 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#ifndef __SYSTEM_PULPISSIMO_RI5CY_METAL_H
+#define __SYSTEM_PULPISSIMO_RI5CY_METAL_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+//#include "FreeRTOSConfig.h"
+
+/* PULPissimo defs */
+#define PULPISSIMO
+
+#define ARCHI_FPGA_FREQUENCY 5000000
+
+#define ARCHI_REF_CLOCK_LOG2 15
+#define ARCHI_REF_CLOCK	     (1 << ARCHI_REF_CLOCK_LOG2)
+
+/* hardware modules */
+#define ARCHI_NUM_TIMER 1
+#define ARCHI_NUM_FLL 2
+
+/* TODO: clean up those macros */
+#define ARCHI_FPGA_FREQUENCY 5000000
+
+#define ARCHI_REF_CLOCK_LOG2 15
+#define ARCHI_REF_CLOCK	     (1 << ARCHI_REF_CLOCK_LOG2)
+
+#define ARCHI_NB_FLL	  2
+#define RT_FREQ_NB_DOMAIN 2
+
+#define __RT_FLL_CL	2
+#define __RT_FLL_PERIPH 1
+#define __RT_FLL_FC	0
+
+#define __RT_FREQ_DOMAIN_FC	0
+#define __RT_FREQ_DOMAIN_CL	2
+#define __RT_FREQ_DOMAIN_PERIPH 1
+#define RT_FREQ_NB_DOMAIN	2
+
+extern volatile uint32_t system_core_clock;
+
+void pulp_sys_init (void);
+void system_core_clock_update (void);
+
+#endif  /* __SYSTEM_PULPISSIMO_RI5CY_H */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_metal.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#include "system_core-v-mcu_metal.h"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/include/system_pmsis.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#include "system_pulpissimo_ri5cy.h"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/core-v-mcu.c

@@ -0,0 +1,462 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022-12-08     WangShun     Remove FreeRTOS related code and add RT-Thread code
+ */
+
+#include <stdint.h>
+#include <assert.h>
+
+#include <core_pulp_cluster.h>
+#include <core-v-mcu-config.h>
+
+//#include "pmsis/implem/drivers/fc_event/fc_event.h"
+#include "hal_fc_event.h"
+/* TODO: weird include */
+#include "core-v-mcu-properties.h"
+#include "hal_irq.h"
+#include "hal_soc_eu.h"
+#include "hal_apb_soc_ctrl_reg_defs.h"
+#include "udma_uart_driver.h"
+#include "udma_i2cm_driver.h"
+#include "udma_qspi_driver.h"
+#include "hal_apb_i2cs.h"
+#include "hal_udma_ctrl_reg_defs.h"
+#include "hal_udma_uart_reg_defs.h"
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "rtconfig.h"
+#define FOR_SIMULATION_TESTING 0
+
+#if (FOR_SIMULATION_TESTING == 1)
+
+typedef struct
+{
+	volatile uint32_t *rx_saddr;  // 0x00
+	volatile uint32_t rx_size;    // 0x04
+	volatile uint32_t rx_cfg;     // 0x08
+	volatile uint32_t rx_initcfg; // 0x0C
+	volatile uint32_t *tx_saddr;  // 0x10
+	volatile uint32_t tx_size;    // 0x14
+	volatile uint32_t tx_cfg;     // 0x18
+	volatile uint32_t tx_initcfg; // 0x1C
+	volatile uint32_t cfg_glob;   // 0x20
+	volatile uint32_t cfg_ll;     // 0x24
+	volatile uint32_t cfg_ur;     // 0x28
+	volatile uint32_t cfg_size;   // 0x2C
+	volatile uint32_t cfg_filter; // 0x30
+	volatile uint32_t vsync_pol;  // 0x34
+
+} camera_struct_t;
+
+void forSimulationTesting(void);
+#endif
+
+//FLASH_DEVICE_OBJECT gFlashDeviceObject[N_QSPIM];
+uint8_t gQSPIFlashPresentFlg[N_QSPIM] = {0};
+uint8_t gMicronFlashDetectedFlg[N_QSPIM] = {0};
+
+/* test some assumptions we make about compiler settings */
+static_assert(sizeof(uintptr_t) == 4,
+	      "uintptr_t is not 4 bytes. Make sure you are using -mabi=ilp32*");
+
+/* Allocate heap to special section. Note that we have no references in the
+ * whole program to this variable (since its just here to allocate space in the
+ * section for our heap), so when using LTO it will be removed. We force it to
+ * stay with the "used" attribute
+ */
+__attribute__((section(".heap"), used)) uint8_t ucHeap[configTOTAL_HEAP_SIZE];
+
+/* Inform linker script about .heap section size. Note: GNU ld seems to
+ * internally represent integers with the bfd_vma type, that is a type that can
+ * contain memory addresses (typdefd to some int type depending on the
+ * architecture). uint32_t seems to me the most fitting candidate for rv32.
+ */
+uint32_t __heap_size = configTOTAL_HEAP_SIZE;
+
+volatile uint32_t system_core_clock = 5000000u;
+
+
+/* interrupt handling */
+void timer_irq_handler(uint32_t mcause);
+void undefined_handler(uint32_t mcause);
+extern void fc_soc_event_handler1(uint32_t mcause);
+void (*isr_table[32])(uint32_t);
+void flash_readid(const struct cli_cmd_entry *pEntry);
+/**
+ * Board init code. Always call this before anything else.
+ */
+
+uint8_t setFLLFrequencyInIntegerMode(uint8_t aFLLNum, uint8_t aRefFreqInMHz, uint16_t aMultiplier, uint8_t aDivideRatio_R_Prescale, uint8_t aPS0_L1, uint8_t aPS0_L2)
+{
+	uint8_t lSts = 0;
+	volatile uint32_t *lPLLStartAddress = (uint32_t *)NULL;
+	uint32_t lCounter = 0;
+	uint32_t lCfgVal = 0;
+
+	uint8_t lPS0_L1 = aPS0_L1 & 0x03;
+	uint8_t lPS0_L2 = aPS0_L2 & 0xFF;
+
+	if (aFLLNum == 0)
+		lPLLStartAddress = (uint32_t *)FLL1_START_ADDR;
+	else if (aFLLNum == 1)
+		lPLLStartAddress = (uint32_t *)FLL2_START_ADDR;
+	else if (aFLLNum == 2)
+		lPLLStartAddress = (uint32_t *)FLL3_START_ADDR;
+	else
+		lPLLStartAddress = (uint32_t *)NULL;
+
+	if (lPLLStartAddress != NULL)
+	{
+		if ((aRefFreqInMHz >= 5) && (aRefFreqInMHz <= 500))
+		{
+			if ((aMultiplier > 0) && (aMultiplier < 2048))
+			{
+				if (aDivideRatio_R_Prescale < 16)
+				{
+					*lPLLStartAddress |= (1 << 19);	     // Bypass on;
+					*lPLLStartAddress |= (1 << 2);	     // Reset high
+					*lPLLStartAddress &= ~(1 << 2);	     // Reset low;
+					*lPLLStartAddress &= ~(1 << 18);     // PS0_EN is set to low
+					*lPLLStartAddress |= (lPS0_L1 << 0); // PS0_L1 0 which gives L01 = 1
+					*lPLLStartAddress |= (lPS0_L2 << 4); // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
+					*lPLLStartAddress |= (0 << 12);	     // PS0_L2_INT 0 and PS0_L2_FRAC 0 which gives L02 = 1
+
+					// FLL1 Config 1 register not configuring PS1
+					*(lPLLStartAddress + 1) = 0;
+
+					// FLL1 Config 2 register
+					lCfgVal = 0;
+					lCfgVal |= (aMultiplier << 4);		    // MULT_INT	0x28 = 40 (40*10 = 400MHz) Multiplier cannot hold 0
+					lCfgVal |= (1 << 27);			    // INTEGER_MODE is enabled
+					lCfgVal |= (aDivideRatio_R_Prescale << 28); // PRESCALE value (Divide Ratio R = 1)
+
+					*(lPLLStartAddress + 2) = lCfgVal;
+
+					// FLL1 Config 3 register not configuring SSC
+					*(lPLLStartAddress + 3) = 0;
+
+					// FLL1 Config 4 register
+					*(lPLLStartAddress + 4) = 0x64;
+
+					// FLL1 Config 5 register
+					*(lPLLStartAddress + 5) = 0x269;
+
+					*lPLLStartAddress |= (1 << 2);	// Reset high
+					*lPLLStartAddress |= (1 << 18); // PS0_EN;
+					// lCounter = 0;
+					while ((*(lPLLStartAddress + 4) & 0x80000000) == 0) // Wait for lock detect to go high
+					{
+						lCounter++;
+						if (lCounter >= 0x00010000)
+						{
+							lSts = 5; // Unable to achieve lock
+							lCounter = 0;
+							break;
+						}
+					}
+					if (lSts == 0)
+						*(lPLLStartAddress) &= ~(1 << 19); // Bypass off;
+				}
+				else
+				{
+					lSts = 1; // aDivideRatio_R_Prescale
+				}
+			}
+			else
+			{
+				lSts = 2; // Invalid aMultiplier
+			}
+		}
+		else
+		{
+			lSts = 3; // Invalid reference freq
+		}
+	}
+	else
+	{
+		lSts = 4; // Invalid PLL number
+	}
+	return lSts;
+}
+
+int handler_count[32];
+uint32_t gSpecialHandlingIRQCnt = 0;
+uint8_t gQSPIIdNum = 0;
+
+void system_init(void)
+{
+	uint32_t lFlashID = 0;
+	SocCtrl_t *soc = APB_SOC_CTRL_ADDR;
+	soc->soft_reset = 1;
+	uint32_t val = 0;
+	uint8_t i = 0;
+	timer_irq_disable();
+
+	uint32_t *lFFL1StartAddress = (uint32_t *)FLL1_START_ADDR;
+	uint32_t *lFFL2StartAddress = (uint32_t *)FLL2_START_ADDR;
+	uint32_t *lFFL3StartAddress = (uint32_t *)FLL3_START_ADDR;
+
+	setFLLFrequencyInIntegerMode(0, 10, 40, 1, 0, 1); // 400
+
+	setFLLFrequencyInIntegerMode(1, 10, 40, 1, 0, 2); // 200
+
+	setFLLFrequencyInIntegerMode(2, 10, 40, 1, 0, 4); // 100
+
+	/* Hook up isr table. This table is temporary until we figure out how to  do proper vectored interrupts. */
+	for (int i = 0; i < 32; i++)
+	{
+		isr_table[i] = undefined_handler;
+		handler_count[i] = 0;
+	}
+	isr_table[0x7] = timer_irq_handler;
+	isr_table[0xb] = (void (*)(uint32_t))fc_soc_event_handler1; // 11 for cv32
+
+	/* mtvec is set in crt0.S */
+
+	/* deactivate all soc events as they are enabled by default */
+	pulp_soc_eu_event_init();
+
+	/* Setup soc events handler. */
+	// pi_fc_event_handler_init(FC_SOC_EVENT);
+	pi_fc_event_handler_init(11);
+
+	/* TODO: I$ enable*/
+	/* enable core level interrupt (mie) */
+	//irq_clint_enable();
+
+	val = csr_read(CSR_MIE);
+
+	/* TODO: enable uart */
+	for (uint8_t id = 0; id != N_UART; id++)
+	{
+		udma_uart_open(id, 115200);
+	}
+	#if 0  
+	for (uint8_t id = 0; id != N_I2CM; id++)
+	{
+		udma_i2cm_open(id, 400000); // 200000
+	} 
+	for (i = 0; i < N_QSPIM; i++)
+	{
+		setQspimPinMux(i);
+		udma_qspim_open(i, 2500000);
+		udma_qspim_control((uint8_t)i, (udma_qspim_control_type_t)kQSPImReset, (void *)0);
+
+		lFlashID = udma_flash_readid(i, 0);
+		if ((lFlashID == 0xFFFFFFFF) || (lFlashID == 0))
+		{
+			gQSPIFlashPresentFlg[i] = 0;
+		}
+		else
+		{
+			gQSPIFlashPresentFlg[i] = 1;
+			if ((lFlashID & 0xFF) == 0x20)
+			{
+				gMicronFlashDetectedFlg[i] = 1;
+				gQSPIIdNum = 0;
+			}
+			else
+				gMicronFlashDetectedFlg[i] = 0;
+		}
+		restoreQspimPinMux(i);
+	}
+	#endif
+
+#if (FOR_SIMULATION_TESTING == 1)
+	forSimulationTesting();
+#endif
+
+	// hal_set_apb_i2cs_slave_on_off(1);
+	// if (hal_get_apb_i2cs_slave_address() != MY_I2C_SLAVE_ADDRESS)
+	// hal_set_apb_i2cs_slave_address(MY_I2C_SLAVE_ADDRESS);
+}
+
+void system_core_clock_update(void)
+{
+	system_core_clock = pi_fll_get_frequency(FLL_SOC, 0);
+}
+
+void system_core_clock_get(void)
+{
+	system_core_clock_update();
+	return;
+}
+
+uint16_t Writeraw(uint8_t uart_id, uint16_t write_len, uint8_t* write_buffer) {
+	UdmaUart_t*				puart = (UdmaUart_t*)(UDMA_CH_ADDR_UART + uart_id * UDMA_CH_SIZE);
+
+	while (puart->status_b.tx_busy) {  // ToDo: Why is this necessary?  Thought the semaphore should have protected
+	}
+
+	puart->tx_saddr = (uint32_t)write_buffer;
+	puart->tx_size = write_len;
+	puart->tx_cfg_b.en = 1; //enable the transfer
+
+	return 0;
+}
+
+void timer_irq_handler(uint32_t mcause)
+{
+#warning requires critical section if interrupt nesting is used.
+	rt_interrupt_enter();
+	rt_tick_increase();
+	rt_interrupt_leave();
+}
+
+void vSystemIrqHandler(uint32_t mcause)
+{
+	isr_table[mcause & 0x1f](mcause & 0x1f);
+}
+
+void undefined_handler(uint32_t mcause)
+{
+	uint32_t RegReadVal = 0;
+#ifdef __PULP_USE_LIBC
+	abort();
+#else
+	if ((mcause == 18) || (mcause == 19) || (mcause == 31))
+	{
+		gSpecialHandlingIRQCnt++;
+		if (gSpecialHandlingIRQCnt >= 20)
+		{
+			RegReadVal = csr_read(CSR_MIE);
+			if ((RegReadVal & BIT(mcause)) != 0) // Check if the event interrupt mask is open.
+			{
+				// close the event interrupt mask.
+				csr_read_clear(CSR_MIE, BIT(mcause));
+			}
+		}
+	}
+	else
+	{
+		handler_count[mcause]++;
+	}
+#endif
+}
+
+void rt_systick_config(void)
+{
+	extern int timer_irq_init(uint32_t ticks);
+	timer_irq_init(ARCHI_FPGA_FREQUENCY / RT_TICK_PER_SECOND);
+}
+
+#if (FOR_SIMULATION_TESTING == 1)
+uint8_t gCamDataBuf[1024];
+
+void udma_cam_open(uint8_t cam_id)
+{
+	int i = 0;
+	volatile UdmaCtrl_t *pudma_ctrl = (UdmaCtrl_t *)UDMA_CH_ADDR_CTRL;
+
+	/* Enable reset and enable uart clock */
+	pudma_ctrl->reg_rst |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
+	pudma_ctrl->reg_rst &= ~(UDMA_CTRL_CAM0_CLKEN << cam_id);
+	pudma_ctrl->reg_cg |= (UDMA_CTRL_CAM0_CLKEN << cam_id);
+
+	// psdio_regs->clk_div_b.clk_div = 5;
+	// psdio_regs->clk_div_b.valid = 1;
+	hal_setpinmux(21, 0); // cam0_vsync
+	hal_setpinmux(22, 0); // cam0_hsync
+	hal_setpinmux(25, 0); // cam0_clk
+	for (i = 0; i < 8; i++)
+	{
+		// set pin muxes to cam functionality
+		hal_setpinmux(29 + i, 0);
+	}
+	return;
+}
+
+void cam_interface_init(uint16_t x, uint16_t y, uint8_t aBitMode)
+{
+	camera_struct_t *camera;
+
+	uint16_t lXCoordOfUpperRightCorner = 0; // X coordinate of upper right corner of slice
+	uint16_t lYCoordOfUpperRightCorner = 0; // Y coordinate of upper right corner of slice
+
+	lXCoordOfUpperRightCorner = x + 3;
+	lYCoordOfUpperRightCorner = y + 3;
+	// camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
+	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
+	camera->cfg_ll = 0 << 16 | 0;
+	camera->cfg_ur = ((lYCoordOfUpperRightCorner << 16) | lXCoordOfUpperRightCorner);
+	// camera->cfg_ur = 323<<16 | 243; // 320 x 240 ?
+	camera->cfg_filter = (1 << 16) | (1 << 8) | 1;
+	// camera->cfg_size = 324;
+	camera->cfg_size = y + 4;
+	camera->vsync_pol = 1;
+	if (aBitMode == 1)
+	{
+		camera->cfg_glob |= (1 << 17);
+	}
+	else if (aBitMode == 4)
+	{
+		camera->cfg_glob |= (1 << 16);
+	}
+	else if (aBitMode == 8)
+	{
+		camera->cfg_glob |= (0 << 0);
+	}
+	camera->cfg_glob |= (0 << 0) |	    //  framedrop disabled
+			    (000000 << 1) | // number of frames to drop
+			    (0 << 7) |	    // Frame slice disabled
+			    (004 << 8) |    // Format binary 100 = ByPass little endian
+			    (0000 << 11);   // Shift value ignored in bypass
+}
+
+uint8_t cam_grab_frame(int x, int y, uint8_t *pparam)
+{
+	uint32_t lCounter = 0;
+	uint8_t lStatus = 0;
+	uint16_t lX = x + 4;
+	uint16_t lY = y + 4;
+
+	camera_struct_t *camera;
+	// camera = (camera_struct_t *)0x1A102300;  // Peripheral 5?
+	camera = (camera_struct_t *)(UDMA_CH_ADDR_CAM + 0 * UDMA_CH_SIZE);
+
+	camera->rx_saddr = pparam;
+	camera->rx_size = (lX * lY);
+	camera->rx_cfg = 0x12;				  // start 16-bit transfers
+	camera->cfg_glob |= camera->cfg_glob | (1 << 31); // enable 1 == go
+
+	lCounter = 0;
+	while (camera->rx_size != 0)
+	{
+		lCounter++;
+		if (lCounter >= 0x00100000)
+		{
+			lStatus = 3; // Time out
+			break;
+		}
+	}
+	// configASSERT( xSemaphoreTake( shSemaphoreHandle, 1000000 ) == pdTRUE );
+	camera->cfg_glob = camera->cfg_glob & (0x7fffffff); // enable 1 == go
+	// configASSERT( xSemaphoreGive( shSemaphoreHandle ) == pdTRUE );
+	return lStatus;
+}
+
+void forSimulationTesting(void)
+{
+	udma_cam_open(0);
+	cam_interface_init(240, 320, 8);
+	cam_grab_frame(240, 320, gCamDataBuf);
+}
+#endif

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/crt0.S

@@ -0,0 +1,93 @@
+/*
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause
+ */
+
+/* Copyright (c) 2017  SiFive Inc. All rights reserved.
+ * Copyright (c) 2019  ETH Zürich and University of Bologna
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the FreeBSD License.   This program is distributed in the hope that
+ * it will be useful, but WITHOUT ANY WARRANTY expressed or implied,
+ * including the implied warranties of MERCHANTABILITY or FITNESS FOR
+ * A PARTICULAR PURPOSE.  A copy of this license is available at
+ * http://www.opensource.org/licenses.
+ */
+
+/* entry point */
+.section .text.start
+.global _start
+.type _start, @function
+
+_start:
+/* initialize global pointer */
+.option push
+.option norelax
+1:	auipc gp, %pcrel_hi(__global_pointer$)
+	addi  gp, gp, %pcrel_lo(1b)
+.option pop
+
+#if defined(ARCHI_HAS_CLUSTER)
+	/* TODO */
+#endif
+/* initialize stack pointer */
+	la sp, __stack_top
+
+	/*or a0, a0, 0*/
+	and a0, a0, 0
+	csrw mie, a0 // disable interrupts
+	csrr a0, mie
+/* set vector table address */
+	la a0, __vector_start
+	or a0, a0, 1 /* enable vectored mode (hardcoded anyway for CV32E40P) */
+	csrw mtvec, a0
+
+/* clear the bss segment */
+	la t0, __bss_start
+        la t1, __bss_end
+/* TODO: optionally compile this out to speed simulation */
+1:
+	sw zero,0(t0)
+	addi t0, t0, 4
+	bltu t0, t1, 1b
+
+/* new-style constructors and destructors */
+#if defined(__PULP_USE_LIBC)
+	la a0, __libc_fini_array
+	call atexit
+	call __libc_init_array
+#endif
+
+/* call main */
+	lw a0, 0(sp)                    /* a0 = argc */
+	addi a1, sp, __SIZEOF_POINTER__ /* a1 = argv */
+	li a2, 0                        /* a2 = envp = NULL */
+	call entry
+	tail exit
+
+.size  _start, .-_start
+
+.global _init
+.type   _init, @function
+.global _fini
+.type   _fini, @function
+_init:
+_fini:
+ /* These don't have to do anything since we use init_array/fini_array. Prevent
+    missing symbol error */
+	ret
+.size  _init, .-_init
+.size _fini, .-_fini

bsp/core-v-mcu/Libraries/core_v_hal_libraries/bmsis/core-v-mcu/source/vectors.S

@@ -0,0 +1,129 @@
+/*
+* Copyright 2019 ETH Zürich and University of Bologna
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+*     http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*
+* SPDX-License-Identifier: Apache-2.0
+* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+* Change Logs:
+* Date           Author       Notes
+* 2022-12-08     WangShun     Remove FreeRTOS related code and add RT-Thread code
+*/
+.extern IRQ_Handler
+#ifdef PULP_FREERTOS_VECTORED_CONTEXT_SWITCH
+.extern	freertos_risc_v_ctxt_handler
+#endif
+#ifdef __HACK_FIRMWARE_OPT1 /* TODO: properly do this with weak symbols */
+.extern TIMER1_IRQ_handler
+#endif
+.extern fc_soc_event_handler
+.section .vectors, "ax"
+.option norvc
+vector_table:
+	j IRQ_Handler  // irq0
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler  // irq3
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler //ctxt_handler  // irq 7 mtime or timer
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler // IRQ_Handler
+	j IRQ_Handler // irq 11 Machine (event Fifo)
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler
+	j IRQ_Handler // IRQ16
+	j IRQ_Handler // IRQ17
+	j IRQ_Handler // IRQ18
+	j IRQ_Handler // IRQ19
+	j IRQ_Handler // IRQ20
+	j IRQ_Handler // IRQ21
+	j IRQ_Handler // IRQ22
+	j IRQ_Handler // IRQ23
+	j IRQ_Handler // IRQ24
+	j IRQ_Handler // IRQ25
+	j IRQ_Handler // IRQ26
+	j IRQ_Handler // IRQ27
+	j IRQ_Handler // IRQ28
+	j IRQ_Handler // IRQ29
+	j IRQ_Handler // IRQ30
+    j IRQ_Handler // IRQ30
+
+/* this is fixed to 0x8000, used for PULP_SECURE=0. We redirect this entry to the
+new vector table (which is at mtvec) */
+/* .section .legacy_irq, "ax" */
+/*	j vector_table */
+/*	j __no_irq_handler */
+/*	j __no_irq_handler */
+/*	j __no_irq_handler */
+
+.section .text.vecs
+/* exception handling */
+__no_irq_handler:
+	la a0, no_exception_handler_msg
+	jal ra, puts
+	j __no_irq_handler
+
+sw_irq_handler:
+	csrr t0, mcause
+	slli t0, t0, 1  /* shift off the high bit */
+	srli t0, t0, 1
+	li t1, 2
+	beq t0, t1, handle_illegal_insn
+	li t1, 11
+	beq t0, t1, handle_ecall
+	li t1, 3
+	beq t0, t1, handle_ebreak
+	j handle_unknown
+
+handle_ecall:
+	la a0, ecall_msg
+	jal ra, puts
+	j end_handler
+
+handle_ebreak:
+	la a0, ebreak_msg
+	jal ra, puts
+	j end_handler
+
+handle_illegal_insn:
+	la a0, illegal_insn_msg
+	jal ra, puts
+	j end_handler
+
+handle_unknown:
+	la a0, unknown_msg
+	jal ra, puts
+	j end_handler
+
+end_handler:
+	csrr a0, mepc
+	addi a0, a0, 4
+	csrw mepc, a0
+	mret
+
+.section .rodata
+illegal_insn_msg:
+	.string "illegal instruction exception handler entered\n"
+ecall_msg:
+	.string "ecall exception handler entered\n"
+ebreak_msg:
+	.string "ebreak exception handler entered\n"
+unknown_msg:
+	.string "unknown exception handler entered\n"
+no_exception_handler_msg:
+	.string "no exception handler installed\n"

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/adv_timer_unit_reg_defs.h

@@ -0,0 +1,805 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __ADV_TIMER_UNIT_H_
+#define __ADV_TIMER_UNIT_H_
+
+//---------------------------------//
+//
+// Module: ADV_TIMER_UNIT
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t timer_0_cmd_register;
+    struct {
+      __IO uint32_t  start_command :  1;
+      __IO uint32_t  stop_command :  1;
+      __IO uint32_t  update_command :  1;
+      __IO uint32_t  reset_command :  1;
+      __IO uint32_t  arm_command :  1;
+      __IO uint32_t  reserved1  : 27;
+    } timer_0_cmd_register_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t timer_0_config_register;
+    struct {
+      __IO uint32_t  input_source_sel :  8;
+      __IO uint32_t  trigger_mode_sel :  3;
+      __IO uint32_t  clock_sel  :  1;
+      __IO uint32_t  up_down_counter_sel :  1;
+      __IO uint32_t  reserved2  :  3;
+      __IO uint32_t  prescaler_value :  8;
+      __IO uint32_t  reserved1  :  8;
+    } timer_0_config_register_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t timer_0_threshold_register;
+    struct {
+      __IO uint32_t  threshold_low : 16;
+      __IO uint32_t  threshold_high : 16;
+    } timer_0_threshold_register_b;
+  };
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t timer_0_threshold_channel_0_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_0_threshold_channel_0_reg_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t timer_0_threshold_channel_1_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_0_threshold_channel_1_reg_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t timer_0_threshold_channel_2_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_0_threshold_channel_2_reg_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t timer_0_threshold_channel_3_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_0_threshold_channel_3_reg_b;
+  };
+
+  // Offset = 0x001c
+  union {
+    __IO uint32_t timer_0_threshold_channel_0_lut;
+  };
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t timer_0_threshold_channel_1_lut;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t timer_0_threshold_channel_2_lut;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t timer_0_threshold_channel_3_lut;
+  };
+
+  // Offset = 0x002c
+  union {
+    __IO uint32_t timer_0_counter_status_register;
+    struct {
+      __IO uint32_t  counter_value : 16;
+      __IO uint32_t  reserved1  : 16;
+    } timer_0_counter_status_register_b;
+  };
+  __I uint32_t    unused0[4];
+
+  // Offset = 0x0040
+  union {
+    __IO uint32_t timer_1_cmd_register;
+    struct {
+      __IO uint32_t  start_command :  1;
+      __IO uint32_t  stop_command :  1;
+      __IO uint32_t  update_command :  1;
+      __IO uint32_t  reset_command :  1;
+      __IO uint32_t  arm_command :  1;
+      __IO uint32_t  reserved1  : 27;
+    } timer_1_cmd_register_b;
+  };
+
+  // Offset = 0x0044
+  union {
+    __IO uint32_t timer_1_config_register;
+    struct {
+      __IO uint32_t  input_source_sel :  8;
+      __IO uint32_t  trigger_mode_sel :  3;
+      __IO uint32_t  clock_sel  :  1;
+      __IO uint32_t  up_down_counter_sel :  1;
+      __IO uint32_t  reserved2  :  3;
+      __IO uint32_t  prescaler_value :  8;
+      __IO uint32_t  reserved1  :  8;
+    } timer_1_config_register_b;
+  };
+
+  // Offset = 0x0048
+  union {
+    __IO uint32_t timer_1_threshold_register;
+    struct {
+      __IO uint32_t  threshold_low : 16;
+      __IO uint32_t  threshold_high : 16;
+    } timer_1_threshold_register_b;
+  };
+
+  // Offset = 0x004c
+  union {
+    __IO uint32_t timer_1_threshold_channel_0_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_1_threshold_channel_0_reg_b;
+  };
+
+  // Offset = 0x0050
+  union {
+    __IO uint32_t timer_1_threshold_channel_1_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_1_threshold_channel_1_reg_b;
+  };
+
+  // Offset = 0x0054
+  union {
+    __IO uint32_t timer_1_threshold_channel_2_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_1_threshold_channel_2_reg_b;
+  };
+
+  // Offset = 0x0058
+  union {
+    __IO uint32_t timer_1_threshold_channel_3_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_1_threshold_channel_3_reg_b;
+  };
+
+  // Offset = 0x005c
+  union {
+    __IO uint32_t timer_1_threshold_channel_0_lut;
+  };
+
+  // Offset = 0x0060
+  union {
+    __IO uint32_t timer_1_threshold_channel_1_lut;
+  };
+
+  // Offset = 0x0064
+  union {
+    __IO uint32_t timer_1_threshold_channel_2_lut;
+  };
+
+  // Offset = 0x0068
+  union {
+    __IO uint32_t timer_1_threshold_channel_3_lut;
+  };
+
+  // Offset = 0x006c
+  union {
+    __IO uint32_t timer_1_counter_status_register;
+    struct {
+      __IO uint32_t  counter_value : 16;
+      __IO uint32_t  reserved1  : 16;
+    } timer_1_counter_status_register_b;
+  };
+  __I uint32_t    unused1[4];
+
+  // Offset = 0x0080
+  union {
+    __IO uint32_t timer_2_cmd_register;
+    struct {
+      __IO uint32_t  start_command :  1;
+      __IO uint32_t  stop_command :  1;
+      __IO uint32_t  update_command :  1;
+      __IO uint32_t  reset_command :  1;
+      __IO uint32_t  arm_command :  1;
+      __IO uint32_t  reserved1  : 27;
+    } timer_2_cmd_register_b;
+  };
+
+  // Offset = 0x0084
+  union {
+    __IO uint32_t timer_2_config_register;
+    struct {
+      __IO uint32_t  input_source_sel :  8;
+      __IO uint32_t  trigger_mode_sel :  3;
+      __IO uint32_t  clock_sel  :  1;
+      __IO uint32_t  up_down_counter_sel :  1;
+      __IO uint32_t  reserved2  :  3;
+      __IO uint32_t  prescaler_value :  8;
+      __IO uint32_t  reserved1  :  8;
+    } timer_2_config_register_b;
+  };
+
+  // Offset = 0x0088
+  union {
+    __IO uint32_t timer_2_threshold_register;
+    struct {
+      __IO uint32_t  threshold_low : 16;
+      __IO uint32_t  threshold_high : 16;
+    } timer_2_threshold_register_b;
+  };
+
+  // Offset = 0x008c
+  union {
+    __IO uint32_t timer_2_threshold_channel_0_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_2_threshold_channel_0_reg_b;
+  };
+
+  // Offset = 0x0090
+  union {
+    __IO uint32_t timer_2_threshold_channel_1_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_2_threshold_channel_1_reg_b;
+  };
+
+  // Offset = 0x0094
+  union {
+    __IO uint32_t timer_2_threshold_channel_2_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_2_threshold_channel_2_reg_b;
+  };
+
+  // Offset = 0x0098
+  union {
+    __IO uint32_t timer_2_threshold_channel_3_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_2_threshold_channel_3_reg_b;
+  };
+
+  // Offset = 0x009c
+  union {
+    __IO uint32_t timer_2_threshold_channel_0_lut;
+  };
+
+  // Offset = 0x00a0
+  union {
+    __IO uint32_t timer_2_threshold_channel_1_lut;
+  };
+
+  // Offset = 0x00a4
+  union {
+    __IO uint32_t timer_2_threshold_channel_2_lut;
+  };
+
+  // Offset = 0x00a8
+  union {
+    __IO uint32_t timer_2_threshold_channel_3_lut;
+  };
+
+  // Offset = 0x00ac
+  union {
+    __IO uint32_t timer_2_counter_status_register;
+    struct {
+      __IO uint32_t  counter_value : 16;
+      __IO uint32_t  reserved1  : 16;
+    } timer_2_counter_status_register_b;
+  };
+  __I uint32_t    unused2[4];
+
+  // Offset = 0x00c0
+  union {
+    __IO uint32_t timer_3_cmd_register;
+    struct {
+      __IO uint32_t  start_command :  1;
+      __IO uint32_t  stop_command :  1;
+      __IO uint32_t  update_command :  1;
+      __IO uint32_t  reset_command :  1;
+      __IO uint32_t  arm_command :  1;
+      __IO uint32_t  reserved1  : 27;
+    } timer_3_cmd_register_b;
+  };
+
+  // Offset = 0x00c4
+  union {
+    __IO uint32_t timer_3_config_register;
+    struct {
+      __IO uint32_t  input_source_sel :  8;
+      __IO uint32_t  trigger_mode_sel :  3;
+      __IO uint32_t  clock_sel  :  1;
+      __IO uint32_t  up_down_counter_sel :  1;
+      __IO uint32_t  reserved2  :  3;
+      __IO uint32_t  prescaler_value :  8;
+      __IO uint32_t  reserved1  :  8;
+    } timer_3_config_register_b;
+  };
+
+  // Offset = 0x00c8
+  union {
+    __IO uint32_t timer_3_threshold_register;
+    struct {
+      __IO uint32_t  threshold_low : 16;
+      __IO uint32_t  threshold_high : 16;
+    } timer_3_threshold_register_b;
+  };
+
+  // Offset = 0x00cc
+  union {
+    __IO uint32_t timer_3_threshold_channel_0_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_3_threshold_channel_0_reg_b;
+  };
+
+  // Offset = 0x00d0
+  union {
+    __IO uint32_t timer_3_threshold_channel_1_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_3_threshold_channel_1_reg_b;
+  };
+
+  // Offset = 0x00d4
+  union {
+    __IO uint32_t timer_3_threshold_channel_2_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_3_threshold_channel_2_reg_b;
+  };
+
+  // Offset = 0x00d8
+  union {
+    __IO uint32_t timer_3_threshold_channel_3_reg;
+    struct {
+      __IO uint32_t  threshold_value : 16;
+      __IO uint32_t  threshold_mode :  3;
+      __IO uint32_t  reserved1  : 13;
+    } timer_3_threshold_channel_3_reg_b;
+  };
+
+  // Offset = 0x00dc
+  union {
+    __IO uint32_t timer_3_threshold_channel_0_lut;
+  };
+
+  // Offset = 0x00e0
+  union {
+    __IO uint32_t timer_3_threshold_channel_1_lut;
+  };
+
+  // Offset = 0x00e4
+  union {
+    __IO uint32_t timer_3_threshold_channel_2_lut;
+  };
+
+  // Offset = 0x00e8
+  union {
+    __IO uint32_t timer_3_threshold_channel_3_lut;
+  };
+
+  // Offset = 0x00ec
+  union {
+    __IO uint32_t timer_3_counter_status_register;
+    struct {
+      __IO uint32_t  counter_value : 16;
+      __IO uint32_t  reserved1  : 16;
+    } timer_3_counter_status_register_b;
+  };
+  __I uint32_t    unused3[4];
+
+  // Offset = 0x0100
+  union {
+    __IO uint32_t adv_timer_event_cfg_register;
+    struct {
+      __IO uint32_t  event0_sel :  4;
+      __IO uint32_t  event1_sel :  4;
+      __IO uint32_t  event2_sel :  4;
+      __IO uint32_t  event3_sel :  4;
+      __IO uint32_t  event_enable :  4;
+      __IO uint32_t  reserved1  : 12;
+    } adv_timer_event_cfg_register_b;
+  };
+
+  // Offset = 0x0104
+  union {
+    __IO uint32_t adv_timer_cfg_register;
+    struct {
+      __IO uint32_t  adv_timer_enable :  4;
+      __IO uint32_t  reserved1  : 28;
+    } adv_timer_cfg_register_b;
+  };
+} AdvTimerUnit_t;
+
+
+#define REG_TIMER_0_CMD_REGISTER       0x000
+#define   REG_TIMER_0_CMD_REGISTER_RESERVED1_LSB   5
+#define   REG_TIMER_0_CMD_REGISTER_RESERVED1_MASK  0x7ffffff
+#define   REG_TIMER_0_CMD_REGISTER_ARM_COMMAND_LSB 4
+#define   REG_TIMER_0_CMD_REGISTER_ARM_COMMAND_MASK 0x1
+#define   REG_TIMER_0_CMD_REGISTER_RESET_COMMAND_LSB 3
+#define   REG_TIMER_0_CMD_REGISTER_RESET_COMMAND_MASK 0x1
+#define   REG_TIMER_0_CMD_REGISTER_UPDATE_COMMAND_LSB 2
+#define   REG_TIMER_0_CMD_REGISTER_UPDATE_COMMAND_MASK 0x1
+#define   REG_TIMER_0_CMD_REGISTER_STOP_COMMAND_LSB 1
+#define   REG_TIMER_0_CMD_REGISTER_STOP_COMMAND_MASK 0x1
+#define   REG_TIMER_0_CMD_REGISTER_START_COMMAND_LSB 0
+#define   REG_TIMER_0_CMD_REGISTER_START_COMMAND_MASK 0x1
+#define REG_TIMER_0_CONFIG_REGISTER    0x004
+#define   REG_TIMER_0_CONFIG_REGISTER_RESERVED1_LSB 24
+#define   REG_TIMER_0_CONFIG_REGISTER_RESERVED1_MASK 0xff
+#define   REG_TIMER_0_CONFIG_REGISTER_PRESCALER_VALUE_LSB 16
+#define   REG_TIMER_0_CONFIG_REGISTER_PRESCALER_VALUE_MASK 0xff
+#define   REG_TIMER_0_CONFIG_REGISTER_RESERVED2_LSB 13
+#define   REG_TIMER_0_CONFIG_REGISTER_RESERVED2_MASK 0x7
+#define   REG_TIMER_0_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_LSB 12
+#define   REG_TIMER_0_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_MASK 0x1
+#define   REG_TIMER_0_CONFIG_REGISTER_CLOCK_SEL_LSB 11
+#define   REG_TIMER_0_CONFIG_REGISTER_CLOCK_SEL_MASK 0x1
+#define   REG_TIMER_0_CONFIG_REGISTER_TRIGGER_MODE_SEL_LSB 8
+#define   REG_TIMER_0_CONFIG_REGISTER_TRIGGER_MODE_SEL_MASK 0x7
+#define   REG_TIMER_0_CONFIG_REGISTER_INPUT_SOURCE_SEL_LSB 0
+#define   REG_TIMER_0_CONFIG_REGISTER_INPUT_SOURCE_SEL_MASK 0xff
+#define REG_TIMER_0_THRESHOLD_REGISTER 0x008
+#define   REG_TIMER_0_THRESHOLD_REGISTER_THRESHOLD_HIGH_LSB 16
+#define   REG_TIMER_0_THRESHOLD_REGISTER_THRESHOLD_HIGH_MASK 0xffff
+#define   REG_TIMER_0_THRESHOLD_REGISTER_THRESHOLD_LOW_LSB 0
+#define   REG_TIMER_0_THRESHOLD_REGISTER_THRESHOLD_LOW_MASK 0xffff
+#define REG_TIMER_0_THRESHOLD_CHANNEL_0_REG 0x00C
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_0_REG_RESERVED1_LSB 19
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_0_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_0_THRESHOLD_CHANNEL_1_REG 0x010
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_1_REG_RESERVED1_LSB 19
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_1_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_0_THRESHOLD_CHANNEL_2_REG 0x014
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_2_REG_RESERVED1_LSB 19
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_2_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_0_THRESHOLD_CHANNEL_3_REG 0x018
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_3_REG_RESERVED1_LSB 19
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_3_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_0_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_0_THRESHOLD_CHANNEL_0_LUT 0x01C
+#define REG_TIMER_0_THRESHOLD_CHANNEL_1_LUT 0x020
+#define REG_TIMER_0_THRESHOLD_CHANNEL_2_LUT 0x024
+#define REG_TIMER_0_THRESHOLD_CHANNEL_3_LUT 0x028
+#define REG_TIMER_0_COUNTER_STATUS_REGISTER 0x02C
+#define   REG_TIMER_0_COUNTER_STATUS_REGISTER_RESERVED1_LSB 16
+#define   REG_TIMER_0_COUNTER_STATUS_REGISTER_RESERVED1_MASK 0xffff
+#define   REG_TIMER_0_COUNTER_STATUS_REGISTER_COUNTER_VALUE_LSB 0
+#define   REG_TIMER_0_COUNTER_STATUS_REGISTER_COUNTER_VALUE_MASK 0xffff
+#define REG_TIMER_1_CMD_REGISTER       0x040
+#define   REG_TIMER_1_CMD_REGISTER_RESERVED1 _LSB  5
+#define   REG_TIMER_1_CMD_REGISTER_RESERVED1 _MASK 0x7ffffff
+#define   REG_TIMER_1_CMD_REGISTER_ARM_COMMAND_LSB 4
+#define   REG_TIMER_1_CMD_REGISTER_ARM_COMMAND_MASK 0x1
+#define   REG_TIMER_1_CMD_REGISTER_RESET_COMMAND_LSB 3
+#define   REG_TIMER_1_CMD_REGISTER_RESET_COMMAND_MASK 0x1
+#define   REG_TIMER_1_CMD_REGISTER_UPDATE_COMMAND_LSB 2
+#define   REG_TIMER_1_CMD_REGISTER_UPDATE_COMMAND_MASK 0x1
+#define   REG_TIMER_1_CMD_REGISTER_STOP_COMMAND_LSB 1
+#define   REG_TIMER_1_CMD_REGISTER_STOP_COMMAND_MASK 0x1
+#define   REG_TIMER_1_CMD_REGISTER_START_COMMAND_LSB 0
+#define   REG_TIMER_1_CMD_REGISTER_START_COMMAND_MASK 0x1
+#define REG_TIMER_1_CONFIG_REGISTER    0x044
+#define   REG_TIMER_1_CONFIG_REGISTER_RESERVED1_LSB 24
+#define   REG_TIMER_1_CONFIG_REGISTER_RESERVED1_MASK 0xff
+#define   REG_TIMER_1_CONFIG_REGISTER_PRESCALER_VALUE_LSB 16
+#define   REG_TIMER_1_CONFIG_REGISTER_PRESCALER_VALUE_MASK 0xff
+#define   REG_TIMER_1_CONFIG_REGISTER_RESERVED2_LSB 13
+#define   REG_TIMER_1_CONFIG_REGISTER_RESERVED2_MASK 0x7
+#define   REG_TIMER_1_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_LSB 12
+#define   REG_TIMER_1_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_MASK 0x1
+#define   REG_TIMER_1_CONFIG_REGISTER_CLOCK_SEL_LSB 11
+#define   REG_TIMER_1_CONFIG_REGISTER_CLOCK_SEL_MASK 0x1
+#define   REG_TIMER_1_CONFIG_REGISTER_TRIGGER_MODE_SEL_LSB 8
+#define   REG_TIMER_1_CONFIG_REGISTER_TRIGGER_MODE_SEL_MASK 0x7
+#define   REG_TIMER_1_CONFIG_REGISTER_INPUT_SOURCE_SEL_LSB 0
+#define   REG_TIMER_1_CONFIG_REGISTER_INPUT_SOURCE_SEL_MASK 0xff
+#define REG_TIMER_1_THRESHOLD_REGISTER 0x048
+#define   REG_TIMER_1_THRESHOLD_REGISTER_THRESHOLD_HIGH_LSB 16
+#define   REG_TIMER_1_THRESHOLD_REGISTER_THRESHOLD_HIGH_MASK 0xffff
+#define   REG_TIMER_1_THRESHOLD_REGISTER_THRESHOLD_LOW_LSB 0
+#define   REG_TIMER_1_THRESHOLD_REGISTER_THRESHOLD_LOW_MASK 0xffff
+#define REG_TIMER_1_THRESHOLD_CHANNEL_0_REG 0x04C
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_0_REG_RESERVED1_LSB 19
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_0_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_1_THRESHOLD_CHANNEL_1_REG 0x050
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_1_REG_RESERVED1_LSB 19
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_1_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_1_THRESHOLD_CHANNEL_2_REG 0x054
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_2_REG_RESERVED1_LSB 19
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_2_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_1_THRESHOLD_CHANNEL_3_REG 0x058
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_3_REG_RESERVED1_LSB 19
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_3_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_1_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_1_THRESHOLD_CHANNEL_0_LUT 0x05C
+#define REG_TIMER_1_THRESHOLD_CHANNEL_1_LUT 0x060
+#define REG_TIMER_1_THRESHOLD_CHANNEL_2_LUT 0x064
+#define REG_TIMER_1_THRESHOLD_CHANNEL_3_LUT 0x068
+#define REG_TIMER_1_COUNTER_STATUS_REGISTER 0x06C
+#define   REG_TIMER_1_COUNTER_STATUS_REGISTER_RESERVED1_LSB 16
+#define   REG_TIMER_1_COUNTER_STATUS_REGISTER_RESERVED1_MASK 0xffff
+#define   REG_TIMER_1_COUNTER_STATUS_REGISTER_COUNTER_VALUE_LSB 0
+#define   REG_TIMER_1_COUNTER_STATUS_REGISTER_COUNTER_VALUE_MASK 0xffff
+#define REG_TIMER_2_CMD_REGISTER       0x080
+#define   REG_TIMER_2_CMD_REGISTER_RESERVED1_LSB   5
+#define   REG_TIMER_2_CMD_REGISTER_RESERVED1_MASK  0x7ffffff
+#define   REG_TIMER_2_CMD_REGISTER_ARM_COMMAND_LSB 4
+#define   REG_TIMER_2_CMD_REGISTER_ARM_COMMAND_MASK 0x1
+#define   REG_TIMER_2_CMD_REGISTER_RESET_COMMAND_LSB 3
+#define   REG_TIMER_2_CMD_REGISTER_RESET_COMMAND_MASK 0x1
+#define   REG_TIMER_2_CMD_REGISTER_UPDATE_COMMAND_LSB 2
+#define   REG_TIMER_2_CMD_REGISTER_UPDATE_COMMAND_MASK 0x1
+#define   REG_TIMER_2_CMD_REGISTER_STOP_COMMAND_LSB 1
+#define   REG_TIMER_2_CMD_REGISTER_STOP_COMMAND_MASK 0x1
+#define   REG_TIMER_2_CMD_REGISTER_START_COMMAND_LSB 0
+#define   REG_TIMER_2_CMD_REGISTER_START_COMMAND_MASK 0x1
+#define REG_TIMER_2_CONFIG_REGISTER    0x084
+#define   REG_TIMER_2_CONFIG_REGISTER_RESERVED1_LSB 24
+#define   REG_TIMER_2_CONFIG_REGISTER_RESERVED1_MASK 0xff
+#define   REG_TIMER_2_CONFIG_REGISTER_PRESCALER_VALUE_LSB 16
+#define   REG_TIMER_2_CONFIG_REGISTER_PRESCALER_VALUE_MASK 0xff
+#define   REG_TIMER_2_CONFIG_REGISTER_RESERVED2_LSB 13
+#define   REG_TIMER_2_CONFIG_REGISTER_RESERVED2_MASK 0x7
+#define   REG_TIMER_2_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_LSB 12
+#define   REG_TIMER_2_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_MASK 0x1
+#define   REG_TIMER_2_CONFIG_REGISTER_CLOCK_SEL_LSB 11
+#define   REG_TIMER_2_CONFIG_REGISTER_CLOCK_SEL_MASK 0x1
+#define   REG_TIMER_2_CONFIG_REGISTER_TRIGGER_MODE_SEL_LSB 8
+#define   REG_TIMER_2_CONFIG_REGISTER_TRIGGER_MODE_SEL_MASK 0x7
+#define   REG_TIMER_2_CONFIG_REGISTER_INPUT_SOURCE_SEL_LSB 0
+#define   REG_TIMER_2_CONFIG_REGISTER_INPUT_SOURCE_SEL_MASK 0xff
+#define REG_TIMER_2_THRESHOLD_REGISTER 0x088
+#define   REG_TIMER_2_THRESHOLD_REGISTER_THRESHOLD_HIGH_LSB 16
+#define   REG_TIMER_2_THRESHOLD_REGISTER_THRESHOLD_HIGH_MASK 0xffff
+#define   REG_TIMER_2_THRESHOLD_REGISTER_THRESHOLD_LOW_LSB 0
+#define   REG_TIMER_2_THRESHOLD_REGISTER_THRESHOLD_LOW_MASK 0xffff
+#define REG_TIMER_2_THRESHOLD_CHANNEL_0_REG 0x08C
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_0_REG_RESERVED1_LSB 19
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_0_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_2_THRESHOLD_CHANNEL_1_REG 0x090
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_1_REG_RESERVED1_LSB 19
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_1_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_2_THRESHOLD_CHANNEL_2_REG 0x094
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_2_REG_RESERVED1_LSB 19
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_2_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_2_THRESHOLD_CHANNEL_3_REG 0x098
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_3_REG_RESERVED1_LSB 19
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_3_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_2_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_2_THRESHOLD_CHANNEL_0_LUT 0x09C
+#define REG_TIMER_2_THRESHOLD_CHANNEL_1_LUT 0x0A0
+#define REG_TIMER_2_THRESHOLD_CHANNEL_2_LUT 0x0A4
+#define REG_TIMER_2_THRESHOLD_CHANNEL_3_LUT 0x0A8
+#define REG_TIMER_2_COUNTER_STATUS_REGISTER 0x0AC
+#define   REG_TIMER_2_COUNTER_STATUS_REGISTER_RESERVED1_LSB 16
+#define   REG_TIMER_2_COUNTER_STATUS_REGISTER_RESERVED1_MASK 0xffff
+#define   REG_TIMER_2_COUNTER_STATUS_REGISTER_COUNTER_VALUE_LSB 0
+#define   REG_TIMER_2_COUNTER_STATUS_REGISTER_COUNTER_VALUE_MASK 0xffff
+#define REG_TIMER_3_CMD_REGISTER       0x0C0
+#define   REG_TIMER_3_CMD_REGISTER_RESERVED1_LSB   5
+#define   REG_TIMER_3_CMD_REGISTER_RESERVED1_MASK  0x7ffffff
+#define   REG_TIMER_3_CMD_REGISTER_ARM_COMMAND_LSB 4
+#define   REG_TIMER_3_CMD_REGISTER_ARM_COMMAND_MASK 0x1
+#define   REG_TIMER_3_CMD_REGISTER_RESET_COMMAND_LSB 3
+#define   REG_TIMER_3_CMD_REGISTER_RESET_COMMAND_MASK 0x1
+#define   REG_TIMER_3_CMD_REGISTER_UPDATE_COMMAND_LSB 2
+#define   REG_TIMER_3_CMD_REGISTER_UPDATE_COMMAND_MASK 0x1
+#define   REG_TIMER_3_CMD_REGISTER_STOP_COMMAND_LSB 1
+#define   REG_TIMER_3_CMD_REGISTER_STOP_COMMAND_MASK 0x1
+#define   REG_TIMER_3_CMD_REGISTER_START_COMMAND_LSB 0
+#define   REG_TIMER_3_CMD_REGISTER_START_COMMAND_MASK 0x1
+#define REG_TIMER_3_CONFIG_REGISTER    0x0C4
+#define   REG_TIMER_3_CONFIG_REGISTER_RESERVED1_LSB 24
+#define   REG_TIMER_3_CONFIG_REGISTER_RESERVED1_MASK 0xff
+#define   REG_TIMER_3_CONFIG_REGISTER_PRESCALER_VALUE_LSB 16
+#define   REG_TIMER_3_CONFIG_REGISTER_PRESCALER_VALUE_MASK 0xff
+#define   REG_TIMER_3_CONFIG_REGISTER_RESERVED2_LSB 13
+#define   REG_TIMER_3_CONFIG_REGISTER_RESERVED2_MASK 0x7
+#define   REG_TIMER_3_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_LSB 12
+#define   REG_TIMER_3_CONFIG_REGISTER_UP_DOWN_COUNTER_SEL_MASK 0x1
+#define   REG_TIMER_3_CONFIG_REGISTER_CLOCK_SEL_LSB 11
+#define   REG_TIMER_3_CONFIG_REGISTER_CLOCK_SEL_MASK 0x1
+#define   REG_TIMER_3_CONFIG_REGISTER_TRIGGER_MODE_SEL_LSB 8
+#define   REG_TIMER_3_CONFIG_REGISTER_TRIGGER_MODE_SEL_MASK 0x7
+#define   REG_TIMER_3_CONFIG_REGISTER_INPUT_SOURCE_SEL_LSB 0
+#define   REG_TIMER_3_CONFIG_REGISTER_INPUT_SOURCE_SEL_MASK 0xff
+#define REG_TIMER_3_THRESHOLD_REGISTER 0x0C8
+#define   REG_TIMER_3_THRESHOLD_REGISTER_THRESHOLD_HIGH_LSB 16
+#define   REG_TIMER_3_THRESHOLD_REGISTER_THRESHOLD_HIGH_MASK 0xffff
+#define   REG_TIMER_3_THRESHOLD_REGISTER_THRESHOLD_LOW_LSB 0
+#define   REG_TIMER_3_THRESHOLD_REGISTER_THRESHOLD_LOW_MASK 0xffff
+#define REG_TIMER_3_THRESHOLD_CHANNEL_0_REG 0x0CC
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_0_REG_RESERVED1_LSB 19
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_0_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_0_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_0_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_3_THRESHOLD_CHANNEL_1_REG 0x0D0
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_1_REG_RESERVED1_LSB 19
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_1_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_1_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_1_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_3_THRESHOLD_CHANNEL_2_REG 0x0D4
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_2_REG_RESERVED1_LSB 19
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_2_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_2_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_2_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_3_THRESHOLD_CHANNEL_3_REG 0x0D8
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_3_REG_RESERVED1_LSB 19
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_3_REG_RESERVED1_MASK 0x1fff
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_LSB 16
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_3_REG_THRESHOLD_MODE_MASK 0x7
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_LSB 0
+#define   REG_TIMER_3_THRESHOLD_CHANNEL_3_REG_THRESHOLD_VALUE_MASK 0xffff
+#define REG_TIMER_3_THRESHOLD_CHANNEL_0_LUT 0x0DC
+#define REG_TIMER_3_THRESHOLD_CHANNEL_1_LUT 0x0E0
+#define REG_TIMER_3_THRESHOLD_CHANNEL_2_LUT 0x0E4
+#define REG_TIMER_3_THRESHOLD_CHANNEL_3_LUT 0x0E8
+#define REG_TIMER_3_COUNTER_STATUS_REGISTER 0x0EC
+#define   REG_TIMER_3_COUNTER_STATUS_REGISTER_RESERVED1_LSB 16
+#define   REG_TIMER_3_COUNTER_STATUS_REGISTER_RESERVED1_MASK 0xffff
+#define   REG_TIMER_3_COUNTER_STATUS_REGISTER_COUNTER_VALUE_LSB 0
+#define   REG_TIMER_3_COUNTER_STATUS_REGISTER_COUNTER_VALUE_MASK 0xffff
+#define REG_ADV_TIMER_EVENT_CFG_REGISTER 0x100
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_RESERVED1_LSB 20
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_RESERVED1_MASK 0xfff
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT_ENABLE_LSB 16
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT_ENABLE_MASK 0xf
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT3_SEL_LSB 12
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT3_SEL_MASK 0xf
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT2_SEL_LSB 8
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT2_SEL_MASK 0xf
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT1_SEL_LSB 4
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT1_SEL_MASK 0xf
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT0_SEL_LSB 0
+#define   REG_ADV_TIMER_EVENT_CFG_REGISTER_EVENT0_SEL_MASK 0xf
+#define REG_ADV_TIMER_CFG_REGISTER     0x104
+#define   REG_ADV_TIMER_CFG_REGISTER_RESERVED1_LSB 4
+#define   REG_ADV_TIMER_CFG_REGISTER_RESERVED1_MASK 0xfffffff
+#define   REG_ADV_TIMER_CFG_REGISTER_ADV_TIMER_ENABLE_LSB 0
+#define   REG_ADV_TIMER_CFG_REGISTER_ADV_TIMER_ENABLE_MASK 0xf
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __ADV_TIMER_UNIT_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/efpga_template_reg_defs.h

@@ -0,0 +1,1454 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __EFPGA_H_
+#define __EFPGA_H_
+
+//---------------------------------//
+//
+// Module: eFPGA
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t tcdm_ctl_p0;
+    struct {
+      __IO uint32_t  tcdm_addr_p0 : 20;
+      __IO uint32_t  tcdm_be_p0 :  4;
+      __IO uint32_t             :  7;
+      __IO uint32_t  tcdm_wen_p0 :  1;
+    } tcdm_ctl_p0_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t tcdm_ctl_p1;
+    struct {
+      __IO uint32_t  tcdm_addr_p1 : 20;
+      __IO uint32_t  tcdm_be_p1 :  4;
+      __IO uint32_t             :  7;
+      __IO uint32_t  tcdm_wen_p1 :  1;
+    } tcdm_ctl_p1_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t tcdm_ctl_p2;
+    struct {
+      __IO uint32_t  tcdm_addr_p2 : 20;
+      __IO uint32_t  tcdm_be_p2 :  4;
+      __IO uint32_t             :  7;
+      __IO uint32_t  tcdm_wen_p2 :  1;
+    } tcdm_ctl_p2_b;
+  };
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t tcdm_ctl_p3;
+    struct {
+      __IO uint32_t  tcdm_addr_p3 : 20;
+      __IO uint32_t  tcdm_be_p3 :  4;
+      __IO uint32_t             :  7;
+      __IO uint32_t  tcdm_wen_p3 :  1;
+    } tcdm_ctl_p3_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t m0_m0_control;
+    struct {
+      __IO uint32_t  m0_m0_outsel :  6;
+      __IO uint32_t             :  6;
+      __IO uint32_t  m0_m0_mode :  2;
+      __IO uint32_t  m0_m0_osel :  1;
+      __IO uint32_t  m0_m0_csel :  1;
+      __IO uint32_t  m0_m0_rnd  :  1;
+      __IO uint32_t  m0_m0_clr  :  1;
+      __IO uint32_t  m0_m0_sat  :  1;
+      __IO uint32_t             : 12;
+      __IO uint32_t  m0_m0_reset :  1;
+    } m0_m0_control_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t m0_m1_control;
+    struct {
+      __IO uint32_t  m0_m1_outsel :  6;
+      __IO uint32_t             :  6;
+      __IO uint32_t  m0_m1_mode :  2;
+      __IO uint32_t  m0_m1_osel :  1;
+      __IO uint32_t  m0_m1_csel :  1;
+      __IO uint32_t  m0_m1_rnd  :  1;
+      __IO uint32_t  m0_m1_clr  :  1;
+      __IO uint32_t  m0_m1_sat  :  1;
+      __IO uint32_t             : 12;
+      __IO uint32_t  m0_m1_reset :  1;
+    } m0_m1_control_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t m1_m0_control;
+    struct {
+      __IO uint32_t  m1_m0_outsel :  6;
+      __IO uint32_t             :  6;
+      __IO uint32_t  m1_m0_mode :  2;
+      __IO uint32_t  m1_m0_osel :  1;
+      __IO uint32_t  m1_m0_csel :  1;
+      __IO uint32_t  m1_m0_rnd  :  1;
+      __IO uint32_t  m1_m0_clr  :  1;
+      __IO uint32_t  m1_m1_sat  :  1;
+      __IO uint32_t             : 12;
+      __IO uint32_t  m1_m0_reset :  1;
+    } m1_m0_control_b;
+  };
+
+  // Offset = 0x001c
+  union {
+    __IO uint32_t m1_m1_control;
+    struct {
+      __IO uint32_t  m1_m1_outsel :  6;
+      __IO uint32_t             :  6;
+      __IO uint32_t  m1_m1_mode :  2;
+      __IO uint32_t  m1_m1_osel :  1;
+      __IO uint32_t  m1_m1_csel :  1;
+      __IO uint32_t  m1_m1_rnd  :  1;
+      __IO uint32_t  m1_m1_clr  :  1;
+      __IO uint32_t  m1_m1_sat  :  1;
+      __IO uint32_t             : 12;
+      __IO uint32_t  m1_m1_reset :  1;
+    } m1_m1_control_b;
+  };
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t m0_ram_control;
+    struct {
+      __IO uint32_t  m0_oper0_rmode :  2;
+      __IO uint32_t  m0_oper0_wmode :  2;
+      __IO uint32_t  m0_oper1_rmode :  2;
+      __IO uint32_t  m0_oper1_wmode :  2;
+      __IO uint32_t  m0_coef_rmode :  2;
+      __IO uint32_t  m0_coef_wmode :  2;
+      __IO uint32_t  m0_oper0_wdsel :  1;
+      __IO uint32_t  m0_oper1_wdsel :  1;
+      __IO uint32_t  m0_coef_wdsel :  1;
+    } m0_ram_control_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t m1_ram_control;
+    struct {
+      __IO uint32_t  m1_oper0_rmode :  2;
+      __IO uint32_t  m1_oper0_wmode :  2;
+      __IO uint32_t  m1_oper1_rmode :  2;
+      __IO uint32_t  m1_oper1_wmode :  2;
+      __IO uint32_t  m1_coef_rmode :  2;
+      __IO uint32_t  m1_coef_wmode :  2;
+      __IO uint32_t  m1_oper0_wdsel :  1;
+      __IO uint32_t  m1_oper1_wdsel :  1;
+      __IO uint32_t  m1_coef_wdsel :  1;
+    } m1_ram_control_b;
+  };
+  __I uint32_t    unused0[2];
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t m0_m0_clken;
+    struct {
+      __IO uint32_t  m0_m0_clken :  1;
+    } m0_m0_clken_b;
+  };
+
+  // Offset = 0x0034
+  union {
+    __IO uint32_t m0_m1_clken;
+    struct {
+      __IO uint32_t  m0_m1_clken :  1;
+    } m0_m1_clken_b;
+  };
+
+  // Offset = 0x0038
+  union {
+    __IO uint32_t m1_m0_clken;
+    struct {
+      __IO uint32_t  m1_m0_clken :  1;
+    } m1_m0_clken_b;
+  };
+
+  // Offset = 0x003c
+  union {
+    __IO uint32_t m1_m1_clken;
+    struct {
+      __IO uint32_t  m1_m1_clken :  1;
+    } m1_m1_clken_b;
+  };
+
+  // Offset = 0x0040
+  union {
+    __IO uint32_t fpgaio_out31_00;
+    struct {
+      __IO uint32_t  fpgaio_o_0 :  1;
+      __IO uint32_t  fpgaio_o_1 :  1;
+      __IO uint32_t  fpgaio_o_2 :  1;
+      __IO uint32_t  fpgaio_o_3 :  1;
+      __IO uint32_t  fpgaio_o_4 :  1;
+      __IO uint32_t  fpgaio_o_5 :  1;
+      __IO uint32_t  fpgaio_o_6 :  1;
+      __IO uint32_t  fpgaio_o_7 :  1;
+      __IO uint32_t  fpgaio_o_8 :  1;
+      __IO uint32_t  fpgaio_o_9 :  1;
+      __IO uint32_t  fpgaio_o_10 :  1;
+      __IO uint32_t  fpgaio_o_11 :  1;
+      __IO uint32_t  fpgaio_o_12 :  1;
+      __IO uint32_t  fpgaio_o_13 :  1;
+      __IO uint32_t  fpgaio_o_14 :  1;
+      __IO uint32_t  fpgaio_o_15 :  1;
+      __IO uint32_t  fpgaio_o_16 :  1;
+      __IO uint32_t  fpgaio_o_17 :  1;
+      __IO uint32_t  fpgaio_o_18 :  1;
+      __IO uint32_t  fpgaio_o_19 :  1;
+      __IO uint32_t  fpgaio_o_20 :  1;
+      __IO uint32_t  fpgaio_o_21 :  1;
+      __IO uint32_t  fpgaio_o_22 :  1;
+      __IO uint32_t  fpgaio_o_23 :  1;
+      __IO uint32_t  fpgaio_o_24 :  1;
+      __IO uint32_t  fpgaio_o_25 :  1;
+      __IO uint32_t  fpgaio_o_26 :  1;
+      __IO uint32_t  fpgaio_o_27 :  1;
+      __IO uint32_t  fpgaio_o_28 :  1;
+      __IO uint32_t  fpgaio_o_29 :  1;
+      __IO uint32_t  fpgaio_o_30 :  1;
+      __IO uint32_t  fpgaio_o_31 :  1;
+    } fpgaio_out31_00_b;
+  };
+
+  // Offset = 0x0044
+  union {
+    __IO uint32_t fpgaio_out63_32;
+    struct {
+      __IO uint32_t  fpgaio_o_32 :  1;
+      __IO uint32_t  fpgaio_o_33 :  1;
+      __IO uint32_t  fpgaio_o_34 :  1;
+      __IO uint32_t  fpgaio_o_35 :  1;
+      __IO uint32_t  fpgaio_o_36 :  1;
+      __IO uint32_t  fpgaio_o_37 :  1;
+      __IO uint32_t  fpgaio_o_38 :  1;
+      __IO uint32_t  fpgaio_o_39 :  1;
+      __IO uint32_t  fpgaio_o_40 :  1;
+      __IO uint32_t  fpgaio_o_41 :  1;
+      __IO uint32_t  fpgaio_o_42 :  1;
+      __IO uint32_t  fpgaio_o_43 :  1;
+      __IO uint32_t  fpgaio_o_44 :  1;
+      __IO uint32_t  fpgaio_o_45 :  1;
+      __IO uint32_t  fpgaio_o_46 :  1;
+      __IO uint32_t  fpgaio_o_47 :  1;
+      __IO uint32_t  fpgaio_o_48 :  1;
+      __IO uint32_t  fpgaio_o_49 :  1;
+      __IO uint32_t  fpgaio_o_50 :  1;
+      __IO uint32_t  fpgaio_o_51 :  1;
+      __IO uint32_t  fpgaio_o_52 :  1;
+      __IO uint32_t  fpgaio_o_53 :  1;
+      __IO uint32_t  fpgaio_o_54 :  1;
+      __IO uint32_t  fpgaio_o_55 :  1;
+      __IO uint32_t  fpgaio_o_56 :  1;
+      __IO uint32_t  fpgaio_o_57 :  1;
+      __IO uint32_t  fpgaio_o_58 :  1;
+      __IO uint32_t  fpgaio_o_59 :  1;
+      __IO uint32_t  fpgaio_o_60 :  1;
+      __IO uint32_t  fpgaio_o_61 :  1;
+      __IO uint32_t  fpgaio_o_62 :  1;
+      __IO uint32_t  fpgaio_o_63 :  1;
+    } fpgaio_out63_32_b;
+  };
+
+  // Offset = 0x0048
+  union {
+    __IO uint32_t fpgaio_out79_64;
+    struct {
+      __IO uint32_t  fpgaio_o_64 :  1;
+      __IO uint32_t  fpgaio_o_65 :  1;
+      __IO uint32_t  fpgaio_o_66 :  1;
+      __IO uint32_t  fpgaio_o_67 :  1;
+      __IO uint32_t  fpgaio_o_68 :  1;
+      __IO uint32_t  fpgaio_o_69 :  1;
+      __IO uint32_t  fpgaio_o_70 :  1;
+      __IO uint32_t  fpgaio_o_71 :  1;
+      __IO uint32_t  fpgaio_o_72 :  1;
+      __IO uint32_t  fpgaio_o_73 :  1;
+      __IO uint32_t  fpgaio_o_74 :  1;
+      __IO uint32_t  fpgaio_o_75 :  1;
+      __IO uint32_t  fpgaio_o_76 :  1;
+      __IO uint32_t  fpgaio_o_77 :  1;
+      __IO uint32_t  fpgaio_o_78 :  1;
+      __IO uint32_t  fpgaio_o_79 :  1;
+    } fpgaio_out79_64_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0050
+  union {
+    __IO uint32_t fpgaio_oe31_00;
+    struct {
+      __IO uint32_t  fpgaio_oe_0 :  1;
+      __IO uint32_t  fpgaio_oe_1 :  1;
+      __IO uint32_t  fpgaio_oe_2 :  1;
+      __IO uint32_t  fpgaio_oe_3 :  1;
+      __IO uint32_t  fpgaio_oe_4 :  1;
+      __IO uint32_t  fpgaio_oe_5 :  1;
+      __IO uint32_t  fpgaio_oe_6 :  1;
+      __IO uint32_t  fpgaio_oe_7 :  1;
+      __IO uint32_t  fpgaio_oe_8 :  1;
+      __IO uint32_t  fpgaio_oe_9 :  1;
+      __IO uint32_t  fpgaio_oe_10 :  1;
+      __IO uint32_t  fpgaio_oe_11 :  1;
+      __IO uint32_t  fpgaio_oe_12 :  1;
+      __IO uint32_t  fpgaio_oe_13 :  1;
+      __IO uint32_t  fpgaio_oe_14 :  1;
+      __IO uint32_t  fpgaio_oe_15 :  1;
+      __IO uint32_t  fpgaio_oe_16 :  1;
+      __IO uint32_t  fpgaio_oe_17 :  1;
+      __IO uint32_t  fpgaio_oe_18 :  1;
+      __IO uint32_t  fpgaio_oe_19 :  1;
+      __IO uint32_t  fpgaio_oe_20 :  1;
+      __IO uint32_t  fpgaio_oe_21 :  1;
+      __IO uint32_t  fpgaio_oe_22 :  1;
+      __IO uint32_t  fpgaio_oe_23 :  1;
+      __IO uint32_t  fpgaio_oe_24 :  1;
+      __IO uint32_t  fpgaio_oe_25 :  1;
+      __IO uint32_t  fpgaio_oe_26 :  1;
+      __IO uint32_t  fpgaio_oe_27 :  1;
+      __IO uint32_t  fpgaio_oe_28 :  1;
+      __IO uint32_t  fpgaio_oe_29 :  1;
+      __IO uint32_t  fpgaio_oe_30 :  1;
+      __IO uint32_t  fpgaio_oe_31 :  1;
+    } fpgaio_oe31_00_b;
+  };
+
+  // Offset = 0x0054
+  union {
+    __IO uint32_t fpgaio_oe63_32;
+    struct {
+      __IO uint32_t  fpgaio_oe_32 :  1;
+      __IO uint32_t  fpgaio_oe_33 :  1;
+      __IO uint32_t  fpgaio_oe_34 :  1;
+      __IO uint32_t  fpgaio_oe_35 :  1;
+      __IO uint32_t  fpgaio_oe_36 :  1;
+      __IO uint32_t  fpgaio_oe_37 :  1;
+      __IO uint32_t  fpgaio_oe_38 :  1;
+      __IO uint32_t  fpgaio_oe_39 :  1;
+      __IO uint32_t  fpgaio_oe_40 :  1;
+      __IO uint32_t  fpgaio_oe_41 :  1;
+      __IO uint32_t  fpgaio_oe_42 :  1;
+      __IO uint32_t  fpgaio_oe_43 :  1;
+      __IO uint32_t  fpgaio_oe_44 :  1;
+      __IO uint32_t  fpgaio_oe_45 :  1;
+      __IO uint32_t  fpgaio_oe_46 :  1;
+      __IO uint32_t  fpgaio_oe_47 :  1;
+      __IO uint32_t  fpgaio_oe_48 :  1;
+      __IO uint32_t  fpgaio_oe_49 :  1;
+      __IO uint32_t  fpgaio_oe_50 :  1;
+      __IO uint32_t  fpgaio_oe_51 :  1;
+      __IO uint32_t  fpgaio_oe_52 :  1;
+      __IO uint32_t  fpgaio_oe_53 :  1;
+      __IO uint32_t  fpgaio_oe_54 :  1;
+      __IO uint32_t  fpgaio_oe_55 :  1;
+      __IO uint32_t  fpgaio_oe_56 :  1;
+      __IO uint32_t  fpgaio_oe_57 :  1;
+      __IO uint32_t  fpgaio_oe_58 :  1;
+      __IO uint32_t  fpgaio_oe_59 :  1;
+      __IO uint32_t  fpgaio_oe_60 :  1;
+      __IO uint32_t  fpgaio_oe_61 :  1;
+      __IO uint32_t  fpgaio_oe_62 :  1;
+      __IO uint32_t  fpgaio_oe_63 :  1;
+    } fpgaio_oe63_32_b;
+  };
+
+  // Offset = 0x0058
+  union {
+    __IO uint32_t fpgaio_oe79_64;
+    struct {
+      __IO uint32_t  fpgaio_oe_64 :  1;
+      __IO uint32_t  fpgaio_oe_65 :  1;
+      __IO uint32_t  fpgaio_oe_66 :  1;
+      __IO uint32_t  fpgaio_oe_67 :  1;
+      __IO uint32_t  fpgaio_oe_68 :  1;
+      __IO uint32_t  fpgaio_oe_69 :  1;
+      __IO uint32_t  fpgaio_oe_70 :  1;
+      __IO uint32_t  fpgaio_oe_71 :  1;
+      __IO uint32_t  fpgaio_oe_72 :  1;
+      __IO uint32_t  fpgaio_oe_73 :  1;
+      __IO uint32_t  fpgaio_oe_74 :  1;
+      __IO uint32_t  fpgaio_oe_75 :  1;
+      __IO uint32_t  fpgaio_oe_76 :  1;
+      __IO uint32_t  fpgaio_oe_77 :  1;
+      __IO uint32_t  fpgaio_oe_78 :  1;
+      __IO uint32_t  fpgaio_oe_79 :  1;
+    } fpgaio_oe79_64_b;
+  };
+  __I uint32_t    unused2[1];
+
+  // Offset = 0x0060
+  union {
+    __IO uint32_t fpgaio_in31_00;
+    struct {
+      __IO uint32_t  fpgaio_i_0 :  1;
+      __IO uint32_t  fpgaio_i_1 :  1;
+      __IO uint32_t  fpgaio_i_2 :  1;
+      __IO uint32_t  fpgaio_i_3 :  1;
+      __IO uint32_t  fpgaio_i_4 :  1;
+      __IO uint32_t  fpgaio_i_5 :  1;
+      __IO uint32_t  fpgaio_i_6 :  1;
+      __IO uint32_t  fpgaio_i_7 :  1;
+      __IO uint32_t  fpgaio_i_8 :  1;
+      __IO uint32_t  fpgaio_i_9 :  1;
+      __IO uint32_t  fpgaio_i_10 :  1;
+      __IO uint32_t  fpgaio_i_11 :  1;
+      __IO uint32_t  fpgaio_i_12 :  1;
+      __IO uint32_t  fpgaio_i_13 :  1;
+      __IO uint32_t  fpgaio_i_14 :  1;
+      __IO uint32_t  fpgaio_i_15 :  1;
+      __IO uint32_t  fpgaio_i_16 :  1;
+      __IO uint32_t  fpgaio_i_17 :  1;
+      __IO uint32_t  fpgaio_i_18 :  1;
+      __IO uint32_t  fpgaio_i_19 :  1;
+      __IO uint32_t  fpgaio_i_20 :  1;
+      __IO uint32_t  fpgaio_i_21 :  1;
+      __IO uint32_t  fpgaio_i_22 :  1;
+      __IO uint32_t  fpgaio_i_23 :  1;
+      __IO uint32_t  fpgaio_i_24 :  1;
+      __IO uint32_t  fpgaio_i_25 :  1;
+      __IO uint32_t  fpgaio_i_26 :  1;
+      __IO uint32_t  fpgaio_i_27 :  1;
+      __IO uint32_t  fpgaio_i_28 :  1;
+      __IO uint32_t  fpgaio_i_29 :  1;
+      __IO uint32_t  fpgaio_i_30 :  1;
+      __IO uint32_t  fpgaio_i_31 :  1;
+    } fpgaio_in31_00_b;
+  };
+
+  // Offset = 0x0064
+  union {
+    __IO uint32_t fpgaio_in63_32;
+    struct {
+      __IO uint32_t  fpgaio_i_32 :  1;
+      __IO uint32_t  fpgaio_i_33 :  1;
+      __IO uint32_t  fpgaio_i_34 :  1;
+      __IO uint32_t  fpgaio_i_35 :  1;
+      __IO uint32_t  fpgaio_i_36 :  1;
+      __IO uint32_t  fpgaio_i_37 :  1;
+      __IO uint32_t  fpgaio_i_38 :  1;
+      __IO uint32_t  fpgaio_i_39 :  1;
+      __IO uint32_t  fpgaio_i_40 :  1;
+      __IO uint32_t  fpgaio_i_41 :  1;
+      __IO uint32_t  fpgaio_i_42 :  1;
+      __IO uint32_t  fpgaio_i_43 :  1;
+      __IO uint32_t  fpgaio_i_44 :  1;
+      __IO uint32_t  fpgaio_i_45 :  1;
+      __IO uint32_t  fpgaio_i_46 :  1;
+      __IO uint32_t  fpgaio_i_47 :  1;
+      __IO uint32_t  fpgaio_i_48 :  1;
+      __IO uint32_t  fpgaio_i_49 :  1;
+      __IO uint32_t  fpgaio_i_50 :  1;
+      __IO uint32_t  fpgaio_i_51 :  1;
+      __IO uint32_t  fpgaio_i_52 :  1;
+      __IO uint32_t  fpgaio_i_53 :  1;
+      __IO uint32_t  fpgaio_i_54 :  1;
+      __IO uint32_t  fpgaio_i_55 :  1;
+      __IO uint32_t  fpgaio_i_56 :  1;
+      __IO uint32_t  fpgaio_i_57 :  1;
+      __IO uint32_t  fpgaio_i_58 :  1;
+      __IO uint32_t  fpgaio_i_59 :  1;
+      __IO uint32_t  fpgaio_i_60 :  1;
+      __IO uint32_t  fpgaio_i_61 :  1;
+      __IO uint32_t  fpgaio_i_62 :  1;
+      __IO uint32_t  fpgaio_i_63 :  1;
+    } fpgaio_in63_32_b;
+  };
+
+  // Offset = 0x0068
+  union {
+    __IO uint32_t fpgaio_in79_64;
+    struct {
+      __IO uint32_t  fpgaio_i_64 :  1;
+      __IO uint32_t  fpgaio_i_65 :  1;
+      __IO uint32_t  fpgaio_i_66 :  1;
+      __IO uint32_t  fpgaio_i_67 :  1;
+      __IO uint32_t  fpgaio_i_68 :  1;
+      __IO uint32_t  fpgaio_i_69 :  1;
+      __IO uint32_t  fpgaio_i_70 :  1;
+      __IO uint32_t  fpgaio_i_71 :  1;
+      __IO uint32_t  fpgaio_i_72 :  1;
+      __IO uint32_t  fpgaio_i_73 :  1;
+      __IO uint32_t  fpgaio_i_74 :  1;
+      __IO uint32_t  fpgaio_i_75 :  1;
+      __IO uint32_t  fpgaio_i_76 :  1;
+      __IO uint32_t  fpgaio_i_77 :  1;
+      __IO uint32_t  fpgaio_i_78 :  1;
+      __IO uint32_t  fpgaio_i_79 :  1;
+    } fpgaio_in79_64_b;
+  };
+
+  // Offset = 0x006c
+  union {
+    __IO uint32_t fpga_event15_00;
+    struct {
+      __IO uint32_t  event_0    :  1;
+      __IO uint32_t  event_1    :  1;
+      __IO uint32_t  event_2    :  1;
+      __IO uint32_t  event_3    :  1;
+      __IO uint32_t  event_4    :  1;
+      __IO uint32_t  event_5    :  1;
+      __IO uint32_t  event_6    :  1;
+      __IO uint32_t  event_7    :  1;
+      __IO uint32_t  event_8    :  1;
+      __IO uint32_t  event_9    :  1;
+      __IO uint32_t  event_10   :  1;
+      __IO uint32_t  event_11   :  1;
+      __IO uint32_t  event_12   :  1;
+      __IO uint32_t  event_13   :  1;
+      __IO uint32_t  event_14   :  1;
+      __IO uint32_t  event_15   :  1;
+    } fpga_event15_00_b;
+  };
+  __I uint32_t    unused3[4];
+
+  // Offset = 0x0080
+  union {
+    __IO uint32_t tcdm_run_p0;
+    struct {
+      __IO uint32_t  tcdm_wdata_p0 : 32;
+    } tcdm_run_p0_b;
+  };
+
+  // Offset = 0x0084
+  union {
+    __IO uint32_t tcdm_run_p1;
+    struct {
+      __IO uint32_t  tcdm_wdata_p0 : 32;
+    } tcdm_run_p1_b;
+  };
+
+  // Offset = 0x0088
+  union {
+    __IO uint32_t tcdm_run_p2;
+    struct {
+      __IO uint32_t  tcdm_wdata_p0 : 32;
+    } tcdm_run_p2_b;
+  };
+
+  // Offset = 0x008c
+  union {
+    __IO uint32_t tcdm_run_p3;
+    struct {
+      __IO uint32_t  tcdm_wdata_p0 : 32;
+    } tcdm_run_p3_b;
+  };
+
+  // Offset = 0x0090
+  union {
+    __IO uint32_t m0_m0_odata;
+    struct {
+      __IO uint32_t  odata      : 32;
+    } m0_m0_odata_b;
+  };
+
+  // Offset = 0x0094
+  union {
+    __IO uint32_t m0_m1_odata;
+    struct {
+      __IO uint32_t  odata      : 32;
+    } m0_m1_odata_b;
+  };
+
+  // Offset = 0x0098
+  union {
+    __IO uint32_t m0_m0_cdata;
+    struct {
+      __IO uint32_t  cdata      : 32;
+    } m0_m0_cdata_b;
+  };
+
+  // Offset = 0x009c
+  union {
+    __IO uint32_t m0_m1_cdata;
+    struct {
+      __IO uint32_t  cdata      : 32;
+    } m0_m1_cdata_b;
+  };
+
+  // Offset = 0x00a0
+  union {
+    __IO uint32_t m1_m0_odata;
+    struct {
+      __IO uint32_t  odata      : 32;
+    } m1_m0_odata_b;
+  };
+
+  // Offset = 0x00a4
+  union {
+    __IO uint32_t m1_m1_odata;
+    struct {
+      __IO uint32_t  odata      : 32;
+    } m1_m1_odata_b;
+  };
+
+  // Offset = 0x00a8
+  union {
+    __IO uint32_t m1_m0_cdata;
+    struct {
+      __IO uint32_t  cdata      : 32;
+    } m1_m0_cdata_b;
+  };
+
+  // Offset = 0x00ac
+  union {
+    __IO uint32_t m1_m1_cdata;
+    struct {
+      __IO uint32_t  cdata      : 32;
+    } m1_m1_cdata_b;
+  };
+  __I uint32_t    unused4[20];
+
+  // Offset = 0x0100
+  union {
+    __IO uint32_t m0_m0_multout;
+    struct {
+      __IO uint32_t  multout    : 32;
+    } m0_m0_multout_b;
+  };
+
+  // Offset = 0x0104
+  union {
+    __IO uint32_t m0_m1_multout;
+    struct {
+      __IO uint32_t  multout    : 32;
+    } m0_m1_multout_b;
+  };
+
+  // Offset = 0x0108
+  union {
+    __IO uint32_t m1_m0_multout;
+    struct {
+      __IO uint32_t  multout    : 32;
+    } m1_m0_multout_b;
+  };
+
+  // Offset = 0x010c
+  union {
+    __IO uint32_t m1_m01multout;
+    struct {
+      __IO uint32_t  multout    : 32;
+    } m1_m01multout_b;
+  };
+  __I uint32_t    unused5[956];
+
+  // Offset = 0x1000
+  union {
+    __IO uint32_t m0_oper0[0x400];
+  };
+  __I uint32_t    unused6[1023];
+
+  // Offset = 0x2000
+  union {
+    __IO uint32_t m0_oper1[0x400];
+  };
+  __I uint32_t    unused7[1023];
+
+  // Offset = 0x3000
+  union {
+    __IO uint32_t m0_coef[0x400];
+  };
+  __I uint32_t    unused8[1023];
+
+  // Offset = 0x4000
+  union {
+    __IO uint32_t m1_oper0[0x400];
+  };
+  __I uint32_t    unused9[1023];
+
+  // Offset = 0x5000
+  union {
+    __IO uint32_t m1_oper1[0x400];
+  };
+  __I uint32_t    unused10[1023];
+
+  // Offset = 0x6000
+  union {
+    __IO uint32_t m1_coef[0x400];
+  };
+} Efpga_t;
+
+
+#define REG_TCDM_CTL_P0                0x00
+#define   REG_TCDM_CTL_P0_tcdm_wen_p0_LSB          31
+#define   REG_TCDM_CTL_P0_tcdm_wen_p0_MASK         0x1
+#define   REG_TCDM_CTL_P0_tcdm_be_p0_LSB           20
+#define   REG_TCDM_CTL_P0_tcdm_be_p0_MASK          0xf
+#define   REG_TCDM_CTL_P0_tcdm_addr_p0_LSB         0
+#define   REG_TCDM_CTL_P0_tcdm_addr_p0_MASK        0xfffff
+#define REG_TCDM_CTL_P1                0x04
+#define   REG_TCDM_CTL_P1_tcdm_wen_p1_LSB          31
+#define   REG_TCDM_CTL_P1_tcdm_wen_p1_MASK         0x1
+#define   REG_TCDM_CTL_P1_tcdm_be_p1_LSB           20
+#define   REG_TCDM_CTL_P1_tcdm_be_p1_MASK          0xf
+#define   REG_TCDM_CTL_P1_tcdm_addr_p1_LSB         0
+#define   REG_TCDM_CTL_P1_tcdm_addr_p1_MASK        0xfffff
+#define REG_TCDM_CTL_P2                0x08
+#define   REG_TCDM_CTL_P2_tcdm_wen_p2_LSB          31
+#define   REG_TCDM_CTL_P2_tcdm_wen_p2_MASK         0x1
+#define   REG_TCDM_CTL_P2_tcdm_be_p2_LSB           20
+#define   REG_TCDM_CTL_P2_tcdm_be_p2_MASK          0xf
+#define   REG_TCDM_CTL_P2_tcdm_addr_p2_LSB         0
+#define   REG_TCDM_CTL_P2_tcdm_addr_p2_MASK        0xfffff
+#define REG_TCDM_CTL_P3                0x0C
+#define   REG_TCDM_CTL_P3_tcdm_wen_p3_LSB          31
+#define   REG_TCDM_CTL_P3_tcdm_wen_p3_MASK         0x1
+#define   REG_TCDM_CTL_P3_tcdm_be_p3_LSB           20
+#define   REG_TCDM_CTL_P3_tcdm_be_p3_MASK          0xf
+#define   REG_TCDM_CTL_P3_tcdm_addr_p3_LSB         0
+#define   REG_TCDM_CTL_P3_tcdm_addr_p3_MASK        0xfffff
+#define REG_M0_M0_CONTROL              0x10
+#define   REG_M0_M0_CONTROL_m0_m0_reset_LSB        31
+#define   REG_M0_M0_CONTROL_m0_m0_reset_MASK       0x1
+#define   REG_M0_M0_CONTROL_m0_m0_sat_LSB          18
+#define   REG_M0_M0_CONTROL_m0_m0_sat_MASK         0x1
+#define   REG_M0_M0_CONTROL_m0_m0_clr_LSB          17
+#define   REG_M0_M0_CONTROL_m0_m0_clr_MASK         0x1
+#define   REG_M0_M0_CONTROL_m0_m0_rnd_LSB          16
+#define   REG_M0_M0_CONTROL_m0_m0_rnd_MASK         0x1
+#define   REG_M0_M0_CONTROL_m0_m0_csel_LSB         15
+#define   REG_M0_M0_CONTROL_m0_m0_csel_MASK        0x1
+#define   REG_M0_M0_CONTROL_m0_m0_osel_LSB         14
+#define   REG_M0_M0_CONTROL_m0_m0_osel_MASK        0x1
+#define   REG_M0_M0_CONTROL_m0_m0_mode_LSB         12
+#define   REG_M0_M0_CONTROL_m0_m0_mode_MASK        0x3
+#define   REG_M0_M0_CONTROL_m0_m0_outsel_LSB       0
+#define   REG_M0_M0_CONTROL_m0_m0_outsel_MASK      0x3f
+#define REG_M0_M1_CONTROL              0x14
+#define   REG_M0_M1_CONTROL_m0_m1_reset_LSB        31
+#define   REG_M0_M1_CONTROL_m0_m1_reset_MASK       0x1
+#define   REG_M0_M1_CONTROL_m0_m1_sat_LSB          18
+#define   REG_M0_M1_CONTROL_m0_m1_sat_MASK         0x1
+#define   REG_M0_M1_CONTROL_m0_m1_clr_LSB          17
+#define   REG_M0_M1_CONTROL_m0_m1_clr_MASK         0x1
+#define   REG_M0_M1_CONTROL_m0_m1_rnd_LSB          16
+#define   REG_M0_M1_CONTROL_m0_m1_rnd_MASK         0x1
+#define   REG_M0_M1_CONTROL_m0_m1_csel_LSB         15
+#define   REG_M0_M1_CONTROL_m0_m1_csel_MASK        0x1
+#define   REG_M0_M1_CONTROL_m0_m1_osel_LSB         14
+#define   REG_M0_M1_CONTROL_m0_m1_osel_MASK        0x1
+#define   REG_M0_M1_CONTROL_m0_m1_mode_LSB         12
+#define   REG_M0_M1_CONTROL_m0_m1_mode_MASK        0x3
+#define   REG_M0_M1_CONTROL_m0_m1_outsel_LSB       0
+#define   REG_M0_M1_CONTROL_m0_m1_outsel_MASK      0x3f
+#define REG_M1_M0_CONTROL              0x18
+#define   REG_M1_M0_CONTROL_m1_m0_reset_LSB        31
+#define   REG_M1_M0_CONTROL_m1_m0_reset_MASK       0x1
+#define   REG_M1_M0_CONTROL_m1_m1_sat_LSB          18
+#define   REG_M1_M0_CONTROL_m1_m1_sat_MASK         0x1
+#define   REG_M1_M0_CONTROL_m1_m0_clr_LSB          17
+#define   REG_M1_M0_CONTROL_m1_m0_clr_MASK         0x1
+#define   REG_M1_M0_CONTROL_m1_m0_rnd_LSB          16
+#define   REG_M1_M0_CONTROL_m1_m0_rnd_MASK         0x1
+#define   REG_M1_M0_CONTROL_m1_m0_csel_LSB         15
+#define   REG_M1_M0_CONTROL_m1_m0_csel_MASK        0x1
+#define   REG_M1_M0_CONTROL_m1_m0_osel_LSB         14
+#define   REG_M1_M0_CONTROL_m1_m0_osel_MASK        0x1
+#define   REG_M1_M0_CONTROL_m1_m0_mode_LSB         12
+#define   REG_M1_M0_CONTROL_m1_m0_mode_MASK        0x3
+#define   REG_M1_M0_CONTROL_m1_m0_outsel_LSB       0
+#define   REG_M1_M0_CONTROL_m1_m0_outsel_MASK      0x3f
+#define REG_M1_M1_CONTROL              0x1C
+#define   REG_M1_M1_CONTROL_m1_m1_reset_LSB        31
+#define   REG_M1_M1_CONTROL_m1_m1_reset_MASK       0x1
+#define   REG_M1_M1_CONTROL_m1_m1_sat_LSB          18
+#define   REG_M1_M1_CONTROL_m1_m1_sat_MASK         0x1
+#define   REG_M1_M1_CONTROL_m1_m1_clr_LSB          17
+#define   REG_M1_M1_CONTROL_m1_m1_clr_MASK         0x1
+#define   REG_M1_M1_CONTROL_m1_m1_rnd_LSB          16
+#define   REG_M1_M1_CONTROL_m1_m1_rnd_MASK         0x1
+#define   REG_M1_M1_CONTROL_m1_m1_csel_LSB         15
+#define   REG_M1_M1_CONTROL_m1_m1_csel_MASK        0x1
+#define   REG_M1_M1_CONTROL_m1_m1_osel_LSB         14
+#define   REG_M1_M1_CONTROL_m1_m1_osel_MASK        0x1
+#define   REG_M1_M1_CONTROL_m1_m1_mode_LSB         12
+#define   REG_M1_M1_CONTROL_m1_m1_mode_MASK        0x3
+#define   REG_M1_M1_CONTROL_m1_m1_outsel_LSB       0
+#define   REG_M1_M1_CONTROL_m1_m1_outsel_MASK      0x3f
+#define REG_M0_RAM_CONTROL             0x20
+#define   REG_M0_RAM_CONTROL_m0_coef_wdsel_LSB     14
+#define   REG_M0_RAM_CONTROL_m0_coef_wdsel_MASK    0x1
+#define   REG_M0_RAM_CONTROL_m0_oper1_wdsel_LSB    13
+#define   REG_M0_RAM_CONTROL_m0_oper1_wdsel_MASK   0x1
+#define   REG_M0_RAM_CONTROL_m0_oper0_wdsel_LSB    12
+#define   REG_M0_RAM_CONTROL_m0_oper0_wdsel_MASK   0x1
+#define   REG_M0_RAM_CONTROL_m0_coef_wmode_LSB     10
+#define   REG_M0_RAM_CONTROL_m0_coef_wmode_MASK    0x3
+#define   REG_M0_RAM_CONTROL_m0_coef_rmode_LSB     8
+#define   REG_M0_RAM_CONTROL_m0_coef_rmode_MASK    0x3
+#define   REG_M0_RAM_CONTROL_m0_oper1_wmode_LSB    6
+#define   REG_M0_RAM_CONTROL_m0_oper1_wmode_MASK   0x3
+#define   REG_M0_RAM_CONTROL_m0_oper1_rmode_LSB    4
+#define   REG_M0_RAM_CONTROL_m0_oper1_rmode_MASK   0x3
+#define   REG_M0_RAM_CONTROL_m0_oper0_wmode_LSB    2
+#define   REG_M0_RAM_CONTROL_m0_oper0_wmode_MASK   0x3
+#define   REG_M0_RAM_CONTROL_m0_oper0_rmode_LSB    0
+#define   REG_M0_RAM_CONTROL_m0_oper0_rmode_MASK   0x3
+#define REG_M1_RAM_CONTROL             0x24
+#define   REG_M1_RAM_CONTROL_m1_coef_wdsel_LSB     14
+#define   REG_M1_RAM_CONTROL_m1_coef_wdsel_MASK    0x1
+#define   REG_M1_RAM_CONTROL_m1_oper1_wdsel_LSB    13
+#define   REG_M1_RAM_CONTROL_m1_oper1_wdsel_MASK   0x1
+#define   REG_M1_RAM_CONTROL_m1_oper0_wdsel_LSB    12
+#define   REG_M1_RAM_CONTROL_m1_oper0_wdsel_MASK   0x1
+#define   REG_M1_RAM_CONTROL_m1_coef_wmode_LSB     10
+#define   REG_M1_RAM_CONTROL_m1_coef_wmode_MASK    0x3
+#define   REG_M1_RAM_CONTROL_m1_coef_rmode_LSB     8
+#define   REG_M1_RAM_CONTROL_m1_coef_rmode_MASK    0x3
+#define   REG_M1_RAM_CONTROL_m1_oper1_wmode_LSB    6
+#define   REG_M1_RAM_CONTROL_m1_oper1_wmode_MASK   0x3
+#define   REG_M1_RAM_CONTROL_m1_oper1_rmode_LSB    4
+#define   REG_M1_RAM_CONTROL_m1_oper1_rmode_MASK   0x3
+#define   REG_M1_RAM_CONTROL_m1_oper0_wmode_LSB    2
+#define   REG_M1_RAM_CONTROL_m1_oper0_wmode_MASK   0x3
+#define   REG_M1_RAM_CONTROL_m1_oper0_rmode_LSB    0
+#define   REG_M1_RAM_CONTROL_m1_oper0_rmode_MASK   0x3
+#define REG_M0_M0_CLKEN                0x30
+#define   REG_M0_M0_CLKEN_m0_m0_clken_LSB          0
+#define   REG_M0_M0_CLKEN_m0_m0_clken_MASK         0x1
+#define REG_M0_M1_CLKEN                0x34
+#define   REG_M0_M1_CLKEN_m0_m1_clken_LSB          0
+#define   REG_M0_M1_CLKEN_m0_m1_clken_MASK         0x1
+#define REG_M1_M0_CLKEN                0x38
+#define   REG_M1_M0_CLKEN_m1_m0_clken_LSB          0
+#define   REG_M1_M0_CLKEN_m1_m0_clken_MASK         0x1
+#define REG_M1_M1_CLKEN                0x3C
+#define   REG_M1_M1_CLKEN_m1_m1_clken_LSB          0
+#define   REG_M1_M1_CLKEN_m1_m1_clken_MASK         0x1
+#define REG_FPGAIO_OUT31_00            0x40
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_31_LSB      31
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_31_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_30_LSB      30
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_30_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_29_LSB      29
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_29_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_28_LSB      28
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_28_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_27_LSB      27
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_27_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_26_LSB      26
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_26_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_25_LSB      25
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_25_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_24_LSB      24
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_24_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_23_LSB      23
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_23_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_22_LSB      22
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_22_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_21_LSB      21
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_21_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_20_LSB      20
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_20_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_19_LSB      19
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_19_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_18_LSB      18
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_18_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_17_LSB      17
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_17_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_16_LSB      16
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_16_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_15_LSB      15
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_15_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_14_LSB      14
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_14_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_13_LSB      13
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_13_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_12_LSB      12
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_12_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_11_LSB      11
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_11_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_10_LSB      10
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_10_MASK     0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_9_LSB       9
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_9_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_8_LSB       8
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_8_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_7_LSB       7
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_7_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_6_LSB       6
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_6_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_5_LSB       5
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_5_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_4_LSB       4
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_4_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_3_LSB       3
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_3_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_2_LSB       2
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_2_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_1_LSB       1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_1_MASK      0x1
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_0_LSB       0
+#define   REG_FPGAIO_OUT31_00_fpgaio_o_0_MASK      0x1
+#define REG_FPGAIO_OUT63_32            0x44
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_63_LSB      31
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_63_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_62_LSB      30
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_62_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_61_LSB      29
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_61_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_60_LSB      28
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_60_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_59_LSB      27
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_59_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_58_LSB      26
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_58_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_57_LSB      25
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_57_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_56_LSB      24
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_56_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_55_LSB      23
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_55_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_54_LSB      22
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_54_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_53_LSB      21
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_53_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_52_LSB      20
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_52_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_51_LSB      19
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_51_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_50_LSB      18
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_50_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_49_LSB      17
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_49_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_48_LSB      16
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_48_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_47_LSB      15
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_47_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_46_LSB      14
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_46_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_45_LSB      13
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_45_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_44_LSB      12
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_44_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_43_LSB      11
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_43_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_42_LSB      10
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_42_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_41_LSB      9
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_41_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_40_LSB      8
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_40_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_39_LSB      7
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_39_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_38_LSB      6
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_38_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_37_LSB      5
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_37_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_36_LSB      4
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_36_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_35_LSB      3
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_35_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_34_LSB      2
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_34_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_33_LSB      1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_33_MASK     0x1
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_32_LSB      0
+#define   REG_FPGAIO_OUT63_32_fpgaio_o_32_MASK     0x1
+#define REG_FPGAIO_OUT79_64            0x48
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_79_LSB      15
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_79_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_78_LSB      14
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_78_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_77_LSB      13
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_77_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_76_LSB      12
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_76_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_75_LSB      11
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_75_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_74_LSB      10
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_74_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_73_LSB      9
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_73_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_72_LSB      8
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_72_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_71_LSB      7
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_71_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_70_LSB      6
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_70_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_69_LSB      5
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_69_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_68_LSB      4
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_68_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_67_LSB      3
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_67_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_66_LSB      2
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_66_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_65_LSB      1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_65_MASK     0x1
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_64_LSB      0
+#define   REG_FPGAIO_OUT79_64_fpgaio_o_64_MASK     0x1
+#define REG_FPGAIO_OE31_00             0x50
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_31_LSB      31
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_31_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_30_LSB      30
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_30_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_29_LSB      29
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_29_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_28_LSB      28
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_28_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_27_LSB      27
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_27_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_26_LSB      26
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_26_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_25_LSB      25
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_25_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_24_LSB      24
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_24_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_23_LSB      23
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_23_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_22_LSB      22
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_22_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_21_LSB      21
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_21_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_20_LSB      20
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_20_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_19_LSB      19
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_19_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_18_LSB      18
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_18_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_17_LSB      17
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_17_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_16_LSB      16
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_16_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_15_LSB      15
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_15_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_14_LSB      14
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_14_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_13_LSB      13
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_13_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_12_LSB      12
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_12_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_11_LSB      11
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_11_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_10_LSB      10
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_10_MASK     0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_9_LSB       9
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_9_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_8_LSB       8
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_8_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_7_LSB       7
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_7_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_6_LSB       6
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_6_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_5_LSB       5
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_5_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_4_LSB       4
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_4_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_3_LSB       3
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_3_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_2_LSB       2
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_2_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_1_LSB       1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_1_MASK      0x1
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_0_LSB       0
+#define   REG_FPGAIO_OE31_00_fpgaio_oe_0_MASK      0x1
+#define REG_FPGAIO_OE63_32             0x54
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_63_LSB      31
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_63_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_62_LSB      30
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_62_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_61_LSB      29
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_61_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_60_LSB      28
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_60_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_59_LSB      27
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_59_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_58_LSB      26
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_58_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_57_LSB      25
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_57_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_56_LSB      24
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_56_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_55_LSB      23
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_55_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_54_LSB      22
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_54_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_53_LSB      21
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_53_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_52_LSB      20
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_52_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_51_LSB      19
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_51_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_50_LSB      18
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_50_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_49_LSB      17
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_49_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_48_LSB      16
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_48_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_47_LSB      15
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_47_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_46_LSB      14
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_46_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_45_LSB      13
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_45_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_44_LSB      12
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_44_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_43_LSB      11
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_43_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_42_LSB      10
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_42_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_41_LSB      9
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_41_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_40_LSB      8
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_40_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_39_LSB      7
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_39_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_38_LSB      6
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_38_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_37_LSB      5
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_37_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_36_LSB      4
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_36_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_35_LSB      3
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_35_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_34_LSB      2
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_34_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_33_LSB      1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_33_MASK     0x1
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_32_LSB      0
+#define   REG_FPGAIO_OE63_32_fpgaio_oe_32_MASK     0x1
+#define REG_FPGAIO_OE79_64             0x58
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_79_LSB      15
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_79_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_78_LSB      14
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_78_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_77_LSB      13
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_77_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_76_LSB      12
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_76_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_75_LSB      11
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_75_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_74_LSB      10
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_74_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_73_LSB      9
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_73_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_72_LSB      8
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_72_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_71_LSB      7
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_71_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_70_LSB      6
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_70_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_69_LSB      5
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_69_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_68_LSB      4
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_68_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_67_LSB      3
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_67_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_66_LSB      2
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_66_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_65_LSB      1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_65_MASK     0x1
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_64_LSB      0
+#define   REG_FPGAIO_OE79_64_fpgaio_oe_64_MASK     0x1
+#define REG_FPGAIO_IN31_00             0x60
+#define   REG_FPGAIO_IN31_00_fpgaio_i_31_LSB       31
+#define   REG_FPGAIO_IN31_00_fpgaio_i_31_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_30_LSB       30
+#define   REG_FPGAIO_IN31_00_fpgaio_i_30_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_29_LSB       29
+#define   REG_FPGAIO_IN31_00_fpgaio_i_29_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_28_LSB       28
+#define   REG_FPGAIO_IN31_00_fpgaio_i_28_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_27_LSB       27
+#define   REG_FPGAIO_IN31_00_fpgaio_i_27_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_26_LSB       26
+#define   REG_FPGAIO_IN31_00_fpgaio_i_26_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_25_LSB       25
+#define   REG_FPGAIO_IN31_00_fpgaio_i_25_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_24_LSB       24
+#define   REG_FPGAIO_IN31_00_fpgaio_i_24_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_23_LSB       23
+#define   REG_FPGAIO_IN31_00_fpgaio_i_23_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_22_LSB       22
+#define   REG_FPGAIO_IN31_00_fpgaio_i_22_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_21_LSB       21
+#define   REG_FPGAIO_IN31_00_fpgaio_i_21_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_20_LSB       20
+#define   REG_FPGAIO_IN31_00_fpgaio_i_20_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_19_LSB       19
+#define   REG_FPGAIO_IN31_00_fpgaio_i_19_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_18_LSB       18
+#define   REG_FPGAIO_IN31_00_fpgaio_i_18_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_17_LSB       17
+#define   REG_FPGAIO_IN31_00_fpgaio_i_17_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_16_LSB       16
+#define   REG_FPGAIO_IN31_00_fpgaio_i_16_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_15_LSB       15
+#define   REG_FPGAIO_IN31_00_fpgaio_i_15_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_14_LSB       14
+#define   REG_FPGAIO_IN31_00_fpgaio_i_14_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_13_LSB       13
+#define   REG_FPGAIO_IN31_00_fpgaio_i_13_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_12_LSB       12
+#define   REG_FPGAIO_IN31_00_fpgaio_i_12_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_11_LSB       11
+#define   REG_FPGAIO_IN31_00_fpgaio_i_11_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_10_LSB       10
+#define   REG_FPGAIO_IN31_00_fpgaio_i_10_MASK      0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_9_LSB        9
+#define   REG_FPGAIO_IN31_00_fpgaio_i_9_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_8_LSB        8
+#define   REG_FPGAIO_IN31_00_fpgaio_i_8_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_7_LSB        7
+#define   REG_FPGAIO_IN31_00_fpgaio_i_7_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_6_LSB        6
+#define   REG_FPGAIO_IN31_00_fpgaio_i_6_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_5_LSB        5
+#define   REG_FPGAIO_IN31_00_fpgaio_i_5_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_4_LSB        4
+#define   REG_FPGAIO_IN31_00_fpgaio_i_4_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_3_LSB        3
+#define   REG_FPGAIO_IN31_00_fpgaio_i_3_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_2_LSB        2
+#define   REG_FPGAIO_IN31_00_fpgaio_i_2_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_1_LSB        1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_1_MASK       0x1
+#define   REG_FPGAIO_IN31_00_fpgaio_i_0_LSB        0
+#define   REG_FPGAIO_IN31_00_fpgaio_i_0_MASK       0x1
+#define REG_FPGAIO_IN63_32             0x64
+#define   REG_FPGAIO_IN63_32_fpgaio_i_63_LSB       31
+#define   REG_FPGAIO_IN63_32_fpgaio_i_63_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_62_LSB       30
+#define   REG_FPGAIO_IN63_32_fpgaio_i_62_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_61_LSB       29
+#define   REG_FPGAIO_IN63_32_fpgaio_i_61_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_60_LSB       28
+#define   REG_FPGAIO_IN63_32_fpgaio_i_60_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_59_LSB       27
+#define   REG_FPGAIO_IN63_32_fpgaio_i_59_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_58_LSB       26
+#define   REG_FPGAIO_IN63_32_fpgaio_i_58_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_57_LSB       25
+#define   REG_FPGAIO_IN63_32_fpgaio_i_57_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_56_LSB       24
+#define   REG_FPGAIO_IN63_32_fpgaio_i_56_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_55_LSB       23
+#define   REG_FPGAIO_IN63_32_fpgaio_i_55_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_54_LSB       22
+#define   REG_FPGAIO_IN63_32_fpgaio_i_54_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_53_LSB       21
+#define   REG_FPGAIO_IN63_32_fpgaio_i_53_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_52_LSB       20
+#define   REG_FPGAIO_IN63_32_fpgaio_i_52_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_51_LSB       19
+#define   REG_FPGAIO_IN63_32_fpgaio_i_51_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_50_LSB       18
+#define   REG_FPGAIO_IN63_32_fpgaio_i_50_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_49_LSB       17
+#define   REG_FPGAIO_IN63_32_fpgaio_i_49_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_48_LSB       16
+#define   REG_FPGAIO_IN63_32_fpgaio_i_48_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_47_LSB       15
+#define   REG_FPGAIO_IN63_32_fpgaio_i_47_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_46_LSB       14
+#define   REG_FPGAIO_IN63_32_fpgaio_i_46_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_45_LSB       13
+#define   REG_FPGAIO_IN63_32_fpgaio_i_45_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_44_LSB       12
+#define   REG_FPGAIO_IN63_32_fpgaio_i_44_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_43_LSB       11
+#define   REG_FPGAIO_IN63_32_fpgaio_i_43_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_42_LSB       10
+#define   REG_FPGAIO_IN63_32_fpgaio_i_42_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_41_LSB       9
+#define   REG_FPGAIO_IN63_32_fpgaio_i_41_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_40_LSB       8
+#define   REG_FPGAIO_IN63_32_fpgaio_i_40_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_39_LSB       7
+#define   REG_FPGAIO_IN63_32_fpgaio_i_39_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_38_LSB       6
+#define   REG_FPGAIO_IN63_32_fpgaio_i_38_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_37_LSB       5
+#define   REG_FPGAIO_IN63_32_fpgaio_i_37_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_36_LSB       4
+#define   REG_FPGAIO_IN63_32_fpgaio_i_36_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_35_LSB       3
+#define   REG_FPGAIO_IN63_32_fpgaio_i_35_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_34_LSB       2
+#define   REG_FPGAIO_IN63_32_fpgaio_i_34_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_33_LSB       1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_33_MASK      0x1
+#define   REG_FPGAIO_IN63_32_fpgaio_i_32_LSB       0
+#define   REG_FPGAIO_IN63_32_fpgaio_i_32_MASK      0x1
+#define REG_FPGAIO_IN79_64             0x68
+#define   REG_FPGAIO_IN79_64_fpgaio_i_79_LSB       15
+#define   REG_FPGAIO_IN79_64_fpgaio_i_79_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_78_LSB       14
+#define   REG_FPGAIO_IN79_64_fpgaio_i_78_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_77_LSB       13
+#define   REG_FPGAIO_IN79_64_fpgaio_i_77_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_76_LSB       12
+#define   REG_FPGAIO_IN79_64_fpgaio_i_76_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_75_LSB       11
+#define   REG_FPGAIO_IN79_64_fpgaio_i_75_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_74_LSB       10
+#define   REG_FPGAIO_IN79_64_fpgaio_i_74_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_73_LSB       9
+#define   REG_FPGAIO_IN79_64_fpgaio_i_73_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_72_LSB       8
+#define   REG_FPGAIO_IN79_64_fpgaio_i_72_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_71_LSB       7
+#define   REG_FPGAIO_IN79_64_fpgaio_i_71_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_70_LSB       6
+#define   REG_FPGAIO_IN79_64_fpgaio_i_70_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_69_LSB       5
+#define   REG_FPGAIO_IN79_64_fpgaio_i_69_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_68_LSB       4
+#define   REG_FPGAIO_IN79_64_fpgaio_i_68_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_67_LSB       3
+#define   REG_FPGAIO_IN79_64_fpgaio_i_67_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_66_LSB       2
+#define   REG_FPGAIO_IN79_64_fpgaio_i_66_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_65_LSB       1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_65_MASK      0x1
+#define   REG_FPGAIO_IN79_64_fpgaio_i_64_LSB       0
+#define   REG_FPGAIO_IN79_64_fpgaio_i_64_MASK      0x1
+#define REG_FPGA_EVENT15_00            0x6C
+#define   REG_FPGA_EVENT15_00_Event_15_LSB         15
+#define   REG_FPGA_EVENT15_00_Event_15_MASK        0x1
+#define   REG_FPGA_EVENT15_00_Event_14_LSB         14
+#define   REG_FPGA_EVENT15_00_Event_14_MASK        0x1
+#define   REG_FPGA_EVENT15_00_Event_13_LSB         13
+#define   REG_FPGA_EVENT15_00_Event_13_MASK        0x1
+#define   REG_FPGA_EVENT15_00_Event_12_LSB         12
+#define   REG_FPGA_EVENT15_00_Event_12_MASK        0x1
+#define   REG_FPGA_EVENT15_00_Event_11_LSB         11
+#define   REG_FPGA_EVENT15_00_Event_11_MASK        0x1
+#define   REG_FPGA_EVENT15_00_Event_10_LSB         10
+#define   REG_FPGA_EVENT15_00_Event_10_MASK        0x1
+#define   REG_FPGA_EVENT15_00_Event_9_LSB          9
+#define   REG_FPGA_EVENT15_00_Event_9_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_8_LSB          8
+#define   REG_FPGA_EVENT15_00_Event_8_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_7_LSB          7
+#define   REG_FPGA_EVENT15_00_Event_7_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_6_LSB          6
+#define   REG_FPGA_EVENT15_00_Event_6_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_5_LSB          5
+#define   REG_FPGA_EVENT15_00_Event_5_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_4_LSB          4
+#define   REG_FPGA_EVENT15_00_Event_4_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_3_LSB          3
+#define   REG_FPGA_EVENT15_00_Event_3_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_2_LSB          2
+#define   REG_FPGA_EVENT15_00_Event_2_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_1_LSB          1
+#define   REG_FPGA_EVENT15_00_Event_1_MASK         0x1
+#define   REG_FPGA_EVENT15_00_Event_0_LSB          0
+#define   REG_FPGA_EVENT15_00_Event_0_MASK         0x1
+#define REG_TCDM_RUN_P0                0x80
+#define   REG_TCDM_RUN_P0_tcdm_wdata_p0_LSB        0
+#define   REG_TCDM_RUN_P0_tcdm_wdata_p0_MASK       0xffffffff
+#define REG_TCDM_RUN_P1                0x84
+#define   REG_TCDM_RUN_P1_tcdm_wdata_p0_LSB        0
+#define   REG_TCDM_RUN_P1_tcdm_wdata_p0_MASK       0xffffffff
+#define REG_TCDM_RUN_P2                0x88
+#define   REG_TCDM_RUN_P2_tcdm_wdata_p0_LSB        0
+#define   REG_TCDM_RUN_P2_tcdm_wdata_p0_MASK       0xffffffff
+#define REG_TCDM_RUN_P3                0x8C
+#define   REG_TCDM_RUN_P3_tcdm_wdata_p0_LSB        0
+#define   REG_TCDM_RUN_P3_tcdm_wdata_p0_MASK       0xffffffff
+#define REG_M0_M0_ODATA                0x90
+#define   REG_M0_M0_ODATA_odata_LSB                0
+#define   REG_M0_M0_ODATA_odata_MASK               0xffffffff
+#define REG_M0_M1_ODATA                0x94
+#define   REG_M0_M1_ODATA_odata_LSB                0
+#define   REG_M0_M1_ODATA_odata_MASK               0xffffffff
+#define REG_M0_M0_CDATA                0x98
+#define   REG_M0_M0_CDATA_cdata_LSB                0
+#define   REG_M0_M0_CDATA_cdata_MASK               0xffffffff
+#define REG_M0_M1_CDATA                0x9C
+#define   REG_M0_M1_CDATA_cdata_LSB                0
+#define   REG_M0_M1_CDATA_cdata_MASK               0xffffffff
+#define REG_M1_M0_ODATA                0xA0
+#define   REG_M1_M0_ODATA_odata_LSB                0
+#define   REG_M1_M0_ODATA_odata_MASK               0xffffffff
+#define REG_M1_M1_ODATA                0xA4
+#define   REG_M1_M1_ODATA_odata_LSB                0
+#define   REG_M1_M1_ODATA_odata_MASK               0xffffffff
+#define REG_M1_M0_CDATA                0xA8
+#define   REG_M1_M0_CDATA_cdata_LSB                0
+#define   REG_M1_M0_CDATA_cdata_MASK               0xffffffff
+#define REG_M1_M1_CDATA                0xAC
+#define   REG_M1_M1_CDATA_cdata_LSB                0
+#define   REG_M1_M1_CDATA_cdata_MASK               0xffffffff
+#define REG_M0_M0_MULTOUT              0x100
+#define   REG_M0_M0_MULTOUT_multout_LSB            0
+#define   REG_M0_M0_MULTOUT_multout_MASK           0xffffffff
+#define REG_M0_M1_MULTOUT              0x104
+#define   REG_M0_M1_MULTOUT_multout_LSB            0
+#define   REG_M0_M1_MULTOUT_multout_MASK           0xffffffff
+#define REG_M1_M0_MULTOUT              0x108
+#define   REG_M1_M0_MULTOUT_multout_LSB            0
+#define   REG_M1_M0_MULTOUT_multout_MASK           0xffffffff
+#define REG_M1_M1_MULTOUT              0x10C
+#define   REG_M1_M01MULTOUT_multout_LSB            0
+#define   REG_M1_M01MULTOUT_multout_MASK           0xffffffff
+#define REG_M0_OPER0                   0x1000
+#define REG_M0_OPER1                   0x2000
+#define REG_M0_COEF                    0x3000
+#define REG_M1_OPER0                   0x4000
+#define REG_M1_OPER1                   0x5000
+#define REG_M1_COEF                    0x6000
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __EFPGA_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_event_cntrl_reg_defs.h

@@ -0,0 +1,299 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __APB_EVENT_CNTRL_H_
+#define __APB_EVENT_CNTRL_H_
+
+//---------------------------------//
+//
+// Module: APB_EVENT_CNTRL
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t apb_events;
+    struct {
+      __IO uint32_t  apb_event  : 16;
+    } apb_events_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t event_mask0;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask0_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t event_mask1;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask1_b;
+  };
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t event_mask2;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask2_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t event_mask3;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask3_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t event_mask4;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask4_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t event_mask5;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask5_b;
+  };
+
+  // Offset = 0x001c
+  union {
+    __IO uint32_t event_mask6;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask6_b;
+  };
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t event_mask7;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_mask7_b;
+  };
+  __I uint32_t    unused0[16];
+
+  // Offset = 0x0064
+  union {
+    __IO uint32_t event_err0;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_err  :  2;
+    } event_err0_b;
+  };
+
+  // Offset = 0x0068
+  union {
+    __IO uint32_t event_err1;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err1_b;
+  };
+
+  // Offset = 0x006c
+  union {
+    __IO uint32_t event_err2;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err2_b;
+  };
+
+  // Offset = 0x0070
+  union {
+    __IO uint32_t event_err3;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err3_b;
+  };
+
+  // Offset = 0x0074
+  union {
+    __IO uint32_t event_err4;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err4_b;
+  };
+
+  // Offset = 0x0078
+  union {
+    __IO uint32_t event_err5;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err5_b;
+  };
+
+  // Offset = 0x007c
+  union {
+    __IO uint32_t event_err6;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err6_b;
+  };
+
+  // Offset = 0x0080
+  union {
+    __IO uint32_t event_err7;
+    struct {
+      __IO uint32_t             : 30;
+      __IO uint32_t  event_enable :  2;
+    } event_err7_b;
+  };
+
+  // Offset = 0x0084
+  union {
+    __IO uint32_t timer_lo_event;
+    struct {
+      __IO uint32_t  event      :  8;
+    } timer_lo_event_b;
+  };
+
+  // Offset = 0x0088
+  union {
+    __IO uint32_t timer_hi_event;
+    struct {
+      __IO uint32_t  event      :  8;
+    } timer_hi_event_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0090
+  union {
+    __IO uint32_t event_fifo;
+    struct {
+      __IO uint32_t  event_id   :  8;
+    } event_fifo_b;
+  };
+} ApbEventCntrl_t;
+
+
+#define REG_APB_EVENTS                 0x000
+#define   REG_APB_EVENTS_apb_event_LSB             0
+#define   REG_APB_EVENTS_apb_event_MASK            0xffff
+#define REG_EVENT_MASK0                0x004
+#define   REG_EVENT_MASK0_event_enable_LSB         30
+#define   REG_EVENT_MASK0_event_enable_MASK        0x3
+#define REG_EVENT_MASK1                0x008
+#define   REG_EVENT_MASK1_event_enable_LSB         30
+#define   REG_EVENT_MASK1_event_enable_MASK        0x3
+#define REG_EVENT_MASK2                0x00C
+#define   REG_EVENT_MASK2_event_enable_LSB         30
+#define   REG_EVENT_MASK2_event_enable_MASK        0x3
+#define REG_EVENT_MASK3                0x010
+#define   REG_EVENT_MASK3_event_enable_LSB         30
+#define   REG_EVENT_MASK3_event_enable_MASK        0x3
+#define REG_EVENT_MASK4                0x014
+#define   REG_EVENT_MASK4_event_enable_LSB         30
+#define   REG_EVENT_MASK4_event_enable_MASK        0x3
+#define REG_EVENT_MASK5                0x018
+#define   REG_EVENT_MASK5_event_enable_LSB         30
+#define   REG_EVENT_MASK5_event_enable_MASK        0x3
+#define REG_EVENT_MASK6                0x01C
+#define   REG_EVENT_MASK6_event_enable_LSB         30
+#define   REG_EVENT_MASK6_event_enable_MASK        0x3
+#define REG_EVENT_MASK7                0x020
+#define   REG_EVENT_MASK7_event_enable_LSB         30
+#define   REG_EVENT_MASK7_event_enable_MASK        0x3
+#define REG_EVENT_ERR0                 0x064
+#define   REG_EVENT_ERR0_event_err_LSB             30
+#define   REG_EVENT_ERR0_event_err_MASK            0x3
+#define REG_EVENT_ERR1                 0x068
+#define   REG_EVENT_ERR1_event_enable_LSB          30
+#define   REG_EVENT_ERR1_event_enable_MASK         0x3
+#define REG_EVENT_ERR2                 0x06C
+#define   REG_EVENT_ERR2_event_enable_LSB          30
+#define   REG_EVENT_ERR2_event_enable_MASK         0x3
+#define REG_EVENT_ERR3                 0x070
+#define   REG_EVENT_ERR3_event_enable_LSB          30
+#define   REG_EVENT_ERR3_event_enable_MASK         0x3
+#define REG_EVENT_ERR4                 0x074
+#define   REG_EVENT_ERR4_event_enable_LSB          30
+#define   REG_EVENT_ERR4_event_enable_MASK         0x3
+#define REG_EVENT_ERR5                 0x078
+#define   REG_EVENT_ERR5_event_enable_LSB          30
+#define   REG_EVENT_ERR5_event_enable_MASK         0x3
+#define REG_EVENT_ERR6                 0x07C
+#define   REG_EVENT_ERR6_event_enable_LSB          30
+#define   REG_EVENT_ERR6_event_enable_MASK         0x3
+#define REG_EVENT_ERR7                 0x080
+#define   REG_EVENT_ERR7_event_enable_LSB          30
+#define   REG_EVENT_ERR7_event_enable_MASK         0x3
+#define REG_TIMER_LO_EVENT             0x0084
+#define   REG_TIMER_LO_EVENT_event_LSB             0
+#define   REG_TIMER_LO_EVENT_event_MASK            0xff
+#define REG_TIMER_HI_EVENT             0x0088
+#define   REG_TIMER_HI_EVENT_event_LSB             0
+#define   REG_TIMER_HI_EVENT_event_MASK            0xff
+#define REG_EVENT_FIFO                 0x090
+#define   REG_EVENT_FIFO_EVENT_ID_LSB              0
+#define   REG_EVENT_FIFO_EVENT_ID_MASK             0xff
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __APB_EVENT_CNTRL_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_gpio_reg_defs.h

@@ -0,0 +1,259 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __APB_GPIO_H_
+#define __APB_GPIO_H_
+
+//---------------------------------//
+//
+// Module: APB_GPIO
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t setgpio;
+    struct {
+      __IO uint32_t  gpio_num   :  8;
+    } setgpio_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t clrgpio;
+    struct {
+      __IO uint32_t  gpio_num   :  8;
+    } clrgpio_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t toggpio;
+    struct {
+      __IO uint32_t  gpio_num   :  8;
+    } toggpio_b;
+  };
+  __I uint32_t    unused0[1];
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t pin0;
+    struct {
+      __IO uint32_t  gpio_value : 32;
+    } pin0_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t pin1;
+    struct {
+      __IO uint32_t  gpio_value : 32;
+    } pin1_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t pin2;
+    struct {
+      __IO uint32_t  gpio_value : 32;
+    } pin2_b;
+  };
+
+  // Offset = 0x001c
+  union {
+    __IO uint32_t pin3;
+    struct {
+      __IO uint32_t  gpio_value : 32;
+    } pin3_b;
+  };
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t out0;
+    struct {
+      __IO uint32_t  value      : 32;
+    } out0_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t out1;
+    struct {
+      __IO uint32_t  value      : 32;
+    } out1_b;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t out2;
+    struct {
+      __IO uint32_t  value      : 32;
+    } out2_b;
+  };
+
+  // Offset = 0x002c
+  union {
+    __IO uint32_t out3;
+    struct {
+      __IO uint32_t  value      : 32;
+    } out3_b;
+  };
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t setsel;
+    struct {
+      __IO uint32_t  gpio_num   :  8;
+    } setsel_b;
+  };
+
+  // Offset = 0x0034
+  union {
+    __IO uint32_t rdstat;
+    struct {
+      __IO uint32_t  gpio_sel   :  8;
+      __IO uint32_t  output     :  1;
+      __IO uint32_t             :  3;
+      __IO uint32_t  input      :  1;
+      __IO uint32_t             :  3;
+      __IO uint32_t  inten      :  1;
+      __IO uint32_t  inttype    :  3;
+      __IO uint32_t             :  4;
+      __IO uint32_t  mode       :  2;
+    } rdstat_b;
+  };
+
+  // Offset = 0x0038
+  union {
+    __IO uint32_t setmode;
+    struct {
+      __IO uint32_t  gpio_num   :  8;
+      __IO uint32_t             : 16;
+      __IO uint32_t  mode       :  2;
+    } setmode_b;
+  };
+
+  // Offset = 0x003c
+  union {
+    __IO uint32_t setint;
+    struct {
+      __IO uint32_t  gpio_num   :  8;
+      __IO uint32_t             :  8;
+      __IO uint32_t  intenable  :  1;
+      __IO uint32_t  inttype    :  3;
+    } setint_b;
+  };
+  union {
+     __IO uint32_t intack;
+     struct {
+       __IO uint32_t  gpio_num   :  8;
+       __IO uint32_t             :  24;
+     } intack_b;
+  };
+} ApbGpio_t;
+
+
+#define REG_SETGPIO                    0x00
+#define   REG_SETGPIO_gpio_num_LSB                 0
+#define   REG_SETGPIO_gpio_num_MASK                0xff
+#define REG_CLRGPIO                    0x04
+#define   REG_CLRGPIO_gpio_num_LSB                 0
+#define   REG_CLRGPIO_gpio_num_MASK                0xff
+#define REG_TOGGPIO                    0x08
+#define   REG_TOGGPIO_gpio_num_LSB                 0
+#define   REG_TOGGPIO_gpio_num_MASK                0xff
+#define REG_PIN0                       0x10
+#define   REG_PIN0_gpio_value_LSB                  0
+#define   REG_PIN0_gpio_value_MASK                 0xffffffff
+#define REG_PIN1                       0x14
+#define   REG_PIN1_gpio_value_LSB                  0
+#define   REG_PIN1_gpio_value_MASK                 0xffffffff
+#define REG_PIN2                       0x18
+#define   REG_PIN2_gpio_value_LSB                  0
+#define   REG_PIN2_gpio_value_MASK                 0xffffffff
+#define REG_PIN3                       0x1C
+#define   REG_PIN3_gpio_value_LSB                  0
+#define   REG_PIN3_gpio_value_MASK                 0xffffffff
+#define REG_OUT0                       0x20
+#define   REG_OUT0_value_LSB                       0
+#define   REG_OUT0_value_MASK                      0xffffffff
+#define REG_OUT1                       0x24
+#define   REG_OUT1_value_LSB                       0
+#define   REG_OUT1_value_MASK                      0xffffffff
+#define REG_OUT2                       0x28
+#define   REG_OUT2_value_LSB                       0
+#define   REG_OUT2_value_MASK                      0xffffffff
+#define REG_OUT3                       0x2C
+#define   REG_OUT3_value_LSB                       0
+#define   REG_OUT3_value_MASK                      0xffffffff
+#define REG_SETSEL                     0x30
+#define   REG_SETSEL_gpio_num_LSB                  0
+#define   REG_SETSEL_gpio_num_MASK                 0xff
+#define REG_RDSTAT                     0x34
+#define   REG_RDSTAT_mode_LSB                      24
+#define   REG_RDSTAT_mode_MASK                     0x3
+#define   REG_RDSTAT_INTTYPE_LSB                   16
+#define   REG_RDSTAT_INTTYPE_MASK                  0x7
+#define   REG_RDSTAT_INPUT_LSB                     12
+#define   REG_RDSTAT_INPUT_MASK                    0x1
+#define   REG_RDSTAT_OUTPUT_LSB                    8
+#define   REG_RDSTAT_OUTPUT_MASK                   0x1
+#define REG_SETMODE                    0x38
+#define   REG_SETMODE_mode_LSB                     24
+#define   REG_SETMODE_mode_MASK                    0x3
+#define   REG_SETMODE_gpio_num_LSB                 0
+#define   REG_SETMODE_gpio_num_MASK                0xff
+#define REG_SETINT                     0x3C
+#define   REG_SETINT_INTTYPE_LSB                   17
+#define   REG_SETINT_INTTYPE_MASK                  0x7
+#define   REG_SETINT_INTENABLE_LSB                 16
+#define   REG_SETINT_INTENABLE_MASK                0x1
+#define   REG_SETINT_gpio_num_LSB                  0
+#define   REG_SETINT_gpio_num_MASK                 0xff
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __APB_GPIO_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_i2cs.h

@@ -0,0 +1,74 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __HAL_APB_I2CS_H__
+#define __HAL_APB_I2CS_H__
+
+#include "stdint.h"
+
+#define MY_I2C_SLAVE_ADDRESS 		0x62
+#define MY_I2C_SLAVE_ADDRESS_7BIT 	(0x62 << 1)
+
+#define I2C_MASTER_REG_DEV_ADDRESS								0x00
+#define I2C_MASTER_REG_ENABLE									0x01
+#define I2C_MASTER_REG_DEBOUNCE_LENGTH							0x02
+#define I2C_MASTER_REG_SCL_DELAY_LENGTH							0x03
+#define I2C_MASTER_REG_SDA_DELAY_LENGTH							0x04
+#define I2C_MASTER_REG_MSG_I2C_APB								0x10
+#define I2C_MASTER_REG_MSG_I2C_APB_STATUS						0x11
+#define I2C_MASTER_REG_MSG_APB_I2C								0x12
+#define I2C_MASTER_REG_MSG_APB_I2C_STATUS						0x13
+#define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_DATA_PORT				0x20
+#define I2C_MASTER_REG_FIFO_I2C_APB_READ_DATA_PORT				0x21
+#define I2C_MASTER_REG_FIFO_I2C_APB_FLUSH						0x22
+#define I2C_MASTER_REG_FIFO_I2C_APB_WRITE_FLAGS					0x23
+#define I2C_MASTER_REG_FIFO_I2C_APB_READ_FLAGS					0x24
+#define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_DATA_PORT				0x30
+#define I2C_MASTER_REG_FIFO_APB_I2C_READ_DATA_PORT				0x31
+#define I2C_MASTER_REG_FIFO_APB_I2C_FLUSH						0x32
+#define I2C_MASTER_REG_FIFO_APB_I2C_WRITE_FLAGS					0x33
+#define I2C_MASTER_REG_FIFO_APB_I2C_READ_FLAGS					0x34
+#define I2C_MASTER_REG_INTERRUPT_STATUS							0x40
+#define I2C_MASTER_REG_INTERRUPT_ENABLE							0x41
+#define I2C_MASTER_REG_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT		0x42
+#define I2C_MASTER_REG_INTERRUPT_APB_I2C_READ_FLAGS_SELECT		0x43
+#define I2C_MASTER_REG_INTERRUPT_TO_APB_STATUS					0x50
+#define I2C_MASTER_REG_INTERRUPT_TO_APB_ENABLE					0x51
+#define I2C_MASTER_REG_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT 	0x52
+#define I2C_MASTER_REG_INTERRUPT_I2C_APB_READ_FLAGS_SELECT		0x53
+
+uint8_t hal_get_apb_i2cs_slave_address(void);
+void hal_set_apb_i2cs_slave_address(uint8_t aSlaveAddress);
+uint8_t hal_set_apb_i2cs_slave_on_off(uint8_t aStatus);
+uint8_t hal_get_i2cs_fifo_i2c_apb_read_data_port(void);
+void hal_set_i2cs_fifo_apb_i2c_write_data_port(uint8_t aData);
+uint8_t hal_get_i2cs_fifo_i2c_apb_write_flags(void);
+uint8_t hal_get_i2cs_fifo_i2c_apb_read_flags(void);
+uint8_t hal_get_i2cs_fifo_apb_i2c_read_flags(void);
+uint8_t hal_get_i2cs_fifo_apb_i2c_write_flags(void);
+uint8_t hal_get_i2cs_msg_i2c_apb(void);
+uint8_t hal_get_i2cs_msg_i2c_apb_status(void);
+void hal_set_i2cs_msg_apb_i2c(uint8_t aData);
+uint8_t hal_get_i2cs_msg_apb_i2c_status(void);
+void hal_i2cs_fifo_i2c_apb_FIFO_flush(void);
+void hal_i2cs_fifo_apb_i2c_FIFO_flush(void);
+
+
+#endif // __HAL_APB_I2CS_H__

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_i2cs_reg_defs.h

@@ -0,0 +1,513 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __APB_I2CS_H_
+#define __APB_I2CS_H_
+
+//---------------------------------//
+//
+// Module: APB_I2CS
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t i2cs_dev_address;
+    struct {
+      __IO uint32_t  slave_addr :  7;
+      __IO uint32_t  reserved   :  1;
+    } i2cs_dev_address_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t i2cs_enable;
+    struct {
+      __IO uint32_t  ip_enable  :  1;
+      __IO uint32_t  reserved   :  7;
+    } i2cs_enable_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t i2cs_debounce_length;
+    struct {
+      __IO uint32_t  deb_len    :  8;
+    } i2cs_debounce_length_b;
+  };
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t i2cs_scl_delay_length;
+    struct {
+      __IO uint32_t  scl_dly_len :  8;
+    } i2cs_scl_delay_length_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t i2cs_sda_delay_length;
+    struct {
+      __IO uint32_t  sda_dly_len :  8;
+    } i2cs_sda_delay_length_b;
+  };
+  __I uint32_t    unused0[11];
+
+  // Offset = 0x0040
+  union {
+    __IO uint32_t i2cs_msg_i2c_apb;
+    struct {
+      __IO uint32_t  i2c_to_apb :  8;
+    } i2cs_msg_i2c_apb_b;
+  };
+
+  // Offset = 0x0044
+  union {
+    __IO uint32_t i2cs_msg_i2c_apb_status;
+    struct {
+      __IO uint32_t  i2c_to_apb_status :  1;
+      __IO uint32_t  reserved   :  7;
+    } i2cs_msg_i2c_apb_status_b;
+  };
+
+  // Offset = 0x0048
+  union {
+    __IO uint32_t i2cs_msg_apb_i2c;
+    struct {
+      __IO uint32_t  apb_to_i2c :  8;
+    } i2cs_msg_apb_i2c_b;
+  };
+
+  // Offset = 0x004c
+  union {
+    __IO uint32_t i2cs_msg_apb_i2c_status;
+    struct {
+      __IO uint32_t  apb_to_i2c_status :  1;
+      __IO uint32_t  reserved   :  7;
+    } i2cs_msg_apb_i2c_status_b;
+  };
+  __I uint32_t    unused1[12];
+
+  // Offset = 0x0080
+  union {
+    __IO uint32_t i2cs_fifo_i2c_apb_write_data_port;
+    struct {
+      __IO uint32_t  i2c_apb_write_data_port : 32;
+    } i2cs_fifo_i2c_apb_write_data_port_b;
+  };
+
+  // Offset = 0x0084
+  union {
+    __IO uint32_t i2cs_fifo_i2c_apb_read_data_port;
+    struct {
+      __IO uint32_t  i2c_apb_read_data_port : 32;
+    } i2cs_fifo_i2c_apb_read_data_port_b;
+  };
+
+  // Offset = 0x0088
+  union {
+    __IO uint32_t i2cs_fifo_i2c_apb_flush;
+    struct {
+      __IO uint32_t  enable     :  1;
+      __IO uint32_t  reserved   :  7;
+    } i2cs_fifo_i2c_apb_flush_b;
+  };
+
+  // Offset = 0x008c
+  union {
+    __IO uint32_t i2cs_fifo_i2c_apb_write_flags;
+    struct {
+      __IO uint32_t  flags      :  3;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_fifo_i2c_apb_write_flags_b;
+  };
+
+  // Offset = 0x0090
+  union {
+    __IO uint32_t i2cs_fifo_i2c_apb_read_flags;
+    struct {
+      __IO uint32_t  flags      :  3;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_fifo_i2c_apb_read_flags_b;
+  };
+  __I uint32_t    unused2[11];
+
+  // Offset = 0x00c0
+  union {
+    __IO uint32_t i2cs_fifo_apb_i2c_write_data_port;
+    struct {
+      __IO uint32_t  i2c_apb_write_data_port : 32;
+    } i2cs_fifo_apb_i2c_write_data_port_b;
+  };
+
+  // Offset = 0x00c4
+  union {
+    __IO uint32_t i2cs_fifo_apb_i2c_read_data_port;
+    struct {
+      __IO uint32_t  i2c_apb_read_data_port : 32;
+    } i2cs_fifo_apb_i2c_read_data_port_b;
+  };
+
+  // Offset = 0x00c8
+  union {
+    __IO uint32_t i2cs_fifo_apb_i2c_flush;
+    struct {
+      __IO uint32_t  enable     :  1;
+      __IO uint32_t  reserved   :  7;
+    } i2cs_fifo_apb_i2c_flush_b;
+  };
+
+  // Offset = 0x00cc
+  union {
+    __IO uint32_t i2cs_fifo_apb_i2c_write_flags;
+    struct {
+      __IO uint32_t  flags      :  3;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_fifo_apb_i2c_write_flags_b;
+  };
+
+  // Offset = 0x00d0
+  union {
+    __IO uint32_t i2cs_fifo_apb_i2c_read_flags;
+    struct {
+      __IO uint32_t  flags      :  3;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_fifo_apb_i2c_read_flags_b;
+  };
+  __I uint32_t    unused3[11];
+
+  // Offset = 0x0100
+  union {
+    __IO uint32_t i2cs_interrupt_status;
+    struct {
+      __IO uint32_t  apb_i2c_message_available :  1;
+      __IO uint32_t  apb_i2c_fifo_read_status :  1;
+      __IO uint32_t  i2c_apb_fifo_write_status :  1;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_interrupt_status_b;
+  };
+
+  // Offset = 0x0104
+  union {
+    __IO uint32_t i2cs_interrupt_enable;
+    struct {
+      __IO uint32_t  apb_i2c_message_available_int_enable :  1;
+      __IO uint32_t  apb_i2c_fifo_read_status_int_enable :  1;
+      __IO uint32_t  i2c_apb_fifo_write_status_int_enable :  1;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_interrupt_enable_b;
+  };
+
+  // Offset = 0x0108
+  union {
+    __IO uint32_t i2cs_interrupt_i2c_apb_write_flags_select;
+    struct {
+      __IO uint32_t  write_flag_128_space_avail :  1;
+      __IO uint32_t  write_flag_64_127_space_avail :  1;
+      __IO uint32_t  write_flag_32_63_space_avail :  1;
+      __IO uint32_t  write_flag_8_31_space_avail :  1;
+      __IO uint32_t  write_flag_4_7_space_avail :  1;
+      __IO uint32_t  write_flag_2_3_space_avail :  1;
+      __IO uint32_t  write_flag_1_space_avail :  1;
+      __IO uint32_t  write_flag_full :  1;
+    } i2cs_interrupt_i2c_apb_write_flags_select_b;
+  };
+
+  // Offset = 0x010c
+  union {
+    __IO uint32_t i2cs_interrupt_apb_i2c_read_flags_select;
+    struct {
+      __IO uint32_t  read_flag_empty :  1;
+      __IO uint32_t  read_flag_1_space_avail :  1;
+      __IO uint32_t  read_flag_2_3_space_avail :  1;
+      __IO uint32_t  read_flag_4_7_space_avail :  1;
+      __IO uint32_t  read_flag_8_31_space_avail :  1;
+      __IO uint32_t  read_flag_32_63_space_avail :  1;
+      __IO uint32_t  read_flag_64_127_space_avail :  1;
+      __IO uint32_t  read_flag_128_space_avail :  1;
+    } i2cs_interrupt_apb_i2c_read_flags_select_b;
+  };
+  __I uint32_t    unused4[12];
+
+  // Offset = 0x0140
+  union {
+    __IO uint32_t i2cs_interrupt_to_apb_status;
+    struct {
+      __IO uint32_t  new_i2c_apb_msg_avail :  1;
+      __IO uint32_t  i2c_apb_fifo_read_status :  1;
+      __IO uint32_t  apb_i2c_fifo_write_status :  1;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_interrupt_to_apb_status_b;
+  };
+
+  // Offset = 0x0144
+  union {
+    __IO uint32_t i2cs_interrupt_to_apb_enable;
+    struct {
+      __IO uint32_t  new_i2c_apb_msg_avail_enable :  1;
+      __IO uint32_t  i2c_apb_fifo_read_status_enable :  1;
+      __IO uint32_t  apb_i2c_fifo_write_status_enable :  1;
+      __IO uint32_t  reserved   :  5;
+    } i2cs_interrupt_to_apb_enable_b;
+  };
+
+  // Offset = 0x0148
+  union {
+    __IO uint32_t i2cs_interrupt_apb_i2c_write_flags_select;
+    struct {
+      __IO uint32_t  write_flag_128_space_avail :  1;
+      __IO uint32_t  write_flag_64_127_space_avail :  1;
+      __IO uint32_t  write_flag_32_63_space_avail :  1;
+      __IO uint32_t  write_flag_8_31_space_avail :  1;
+      __IO uint32_t  write_flag_4_7_space_avail :  1;
+      __IO uint32_t  write_flag_2_3_space_avail :  1;
+      __IO uint32_t  write_flag_1_space_avail :  1;
+      __IO uint32_t  write_flag_full :  1;
+    } i2cs_interrupt_apb_i2c_write_flags_select_b;
+  };
+
+  // Offset = 0x014c
+  union {
+    __IO uint32_t i2cs_interrupt_i2c_apb_read_flags_select;
+    struct {
+      __IO uint32_t  read_flag_empty :  1;
+      __IO uint32_t  read_flag_1_space_avail :  1;
+      __IO uint32_t  read_flag_2_3_space_avail :  1;
+      __IO uint32_t  read_flag_4_7_space_avail :  1;
+      __IO uint32_t  read_flag_8_31_space_avail :  1;
+      __IO uint32_t  read_flag_32_63_space_avail :  1;
+      __IO uint32_t  read_flag_64_127_space_avail :  1;
+      __IO uint32_t  read_flag_128_space_avail :  1;
+    } i2cs_interrupt_i2c_apb_read_flags_select_b;
+  };
+} ApbI2cs_t;
+
+
+#define REG_I2CS_DEV_ADDRESS           0x000
+#define   REG_I2CS_DEV_ADDRESS_RESERVED_LSB        7
+#define   REG_I2CS_DEV_ADDRESS_RESERVED_MASK       0x1
+#define   REG_I2CS_DEV_ADDRESS_SLAVE_ADDR_LSB      0
+#define   REG_I2CS_DEV_ADDRESS_SLAVE_ADDR_MASK     0x7f
+#define REG_I2CS_ENABLE                0x004
+#define   REG_I2CS_ENABLE_RESERVED_LSB             1
+#define   REG_I2CS_ENABLE_RESERVED_MASK            0x7f
+#define   REG_I2CS_ENABLE_IP_ENABLE_LSB            0
+#define   REG_I2CS_ENABLE_IP_ENABLE_MASK           0x1
+#define REG_I2CS_DEBOUNCE_LENGTH       0x008
+#define   REG_I2CS_DEBOUNCE_LENGTH_DEB_LEN_LSB     0
+#define   REG_I2CS_DEBOUNCE_LENGTH_DEB_LEN_MASK    0xff
+#define REG_I2CS_SCL_DELAY_LENGTH      0x00C
+#define   REG_I2CS_SCL_DELAY_LENGTH_SCL_DLY_LEN_LSB 0
+#define   REG_I2CS_SCL_DELAY_LENGTH_SCL_DLY_LEN_MASK 0xff
+#define REG_I2CS_SDA_DELAY_LENGTH      0x010
+#define   REG_I2CS_SDA_DELAY_LENGTH_SDA_DLY_LEN_LSB 0
+#define   REG_I2CS_SDA_DELAY_LENGTH_SDA_DLY_LEN_MASK 0xff
+#define REG_I2CS_MSG_I2C_APB           0x040
+#define   REG_I2CS_MSG_I2C_APB_I2C_TO_APB_LSB      0
+#define   REG_I2CS_MSG_I2C_APB_I2C_TO_APB_MASK     0xff
+#define REG_I2CS_MSG_I2C_APB_STATUS    0x044
+#define   REG_I2CS_MSG_I2C_APB_STATUS_RESERVED_LSB 1
+#define   REG_I2CS_MSG_I2C_APB_STATUS_RESERVED_MASK 0x7f
+#define   REG_I2CS_MSG_I2C_APB_STATUS_I2C_TO_APB_STATUS_LSB 0
+#define   REG_I2CS_MSG_I2C_APB_STATUS_I2C_TO_APB_STATUS_MASK 0x1
+#define REG_I2CS_MSG_APB_I2C           0x048
+#define   REG_I2CS_MSG_APB_I2C_APB_TO_I2C_LSB      0
+#define   REG_I2CS_MSG_APB_I2C_APB_TO_I2C_MASK     0xff
+#define REG_I2CS_MSG_APB_I2C_STATUS    0x04C
+#define   REG_I2CS_MSG_APB_I2C_STATUS_RESERVED_LSB 1
+#define   REG_I2CS_MSG_APB_I2C_STATUS_RESERVED_MASK 0x7f
+#define   REG_I2CS_MSG_APB_I2C_STATUS_APB_TO_I2C_STATUS_LSB 0
+#define   REG_I2CS_MSG_APB_I2C_STATUS_APB_TO_I2C_STATUS_MASK 0x1
+#define REG_I2CS_FIFO_I2C_APB_WRITE_DATA_PORT 0x080
+#define   REG_I2CS_FIFO_I2C_APB_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_LSB 0
+#define   REG_I2CS_FIFO_I2C_APB_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_MASK 0xffffffff
+#define REG_I2CS_FIFO_I2C_APB_READ_DATA_PORT 0x084
+#define   REG_I2CS_FIFO_I2C_APB_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_LSB 0
+#define   REG_I2CS_FIFO_I2C_APB_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_MASK 0xffffffff
+#define REG_I2CS_FIFO_I2C_APB_FLUSH    0x088
+#define   REG_I2CS_FIFO_I2C_APB_FLUSH_RESERVED_LSB 1
+#define   REG_I2CS_FIFO_I2C_APB_FLUSH_RESERVED_MASK 0x7f
+#define   REG_I2CS_FIFO_I2C_APB_FLUSH_ENABLE_LSB   0
+#define   REG_I2CS_FIFO_I2C_APB_FLUSH_ENABLE_MASK  0x1
+#define REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS 0x08C
+#define   REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_RESERVED_LSB 3
+#define   REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_RESERVED_MASK 0x1f
+#define   REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_FLAGS_LSB 0
+#define   REG_I2CS_FIFO_I2C_APB_WRITE_FLAGS_FLAGS_MASK 0x7
+#define REG_I2CS_FIFO_I2C_APB_READ_FLAGS 0x090
+#define   REG_I2CS_FIFO_I2C_APB_READ_FLAGS_RESERVED_LSB 3
+#define   REG_I2CS_FIFO_I2C_APB_READ_FLAGS_RESERVED_MASK 0x1f
+#define   REG_I2CS_FIFO_I2C_APB_READ_FLAGS_FLAGS_LSB 0
+#define   REG_I2CS_FIFO_I2C_APB_READ_FLAGS_FLAGS_MASK 0x7
+#define REG_I2CS_FIFO_APB_I2C_WRITE_DATA_PORT 0x0C0
+#define   REG_I2CS_FIFO_APB_I2C_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_LSB 0
+#define   REG_I2CS_FIFO_APB_I2C_WRITE_DATA_PORT_I2C_APB_WRITE_DATA_PORT_MASK 0xffffffff
+#define REG_I2CS_FIFO_APB_I2C_READ_DATA_PORT 0x0C4
+#define   REG_I2CS_FIFO_APB_I2C_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_LSB 0
+#define   REG_I2CS_FIFO_APB_I2C_READ_DATA_PORT_I2C_APB_READ_DATA_PORT_MASK 0xffffffff
+#define REG_I2CS_FIFO_APB_I2C_FLUSH    0x0C8
+#define   REG_I2CS_FIFO_APB_I2C_FLUSH_RESERVED_LSB 1
+#define   REG_I2CS_FIFO_APB_I2C_FLUSH_RESERVED_MASK 0x7f
+#define   REG_I2CS_FIFO_APB_I2C_FLUSH_ENABLE_LSB   0
+#define   REG_I2CS_FIFO_APB_I2C_FLUSH_ENABLE_MASK  0x1
+#define REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS 0x0CC
+#define   REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_RESERVED_LSB 3
+#define   REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_RESERVED_MASK 0x1f
+#define   REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_FLAGS_LSB 0
+#define   REG_I2CS_FIFO_APB_I2C_WRITE_FLAGS_FLAGS_MASK 0x7
+#define REG_I2CS_FIFO_APB_I2C_READ_FLAGS 0x0D0
+#define   REG_I2CS_FIFO_APB_I2C_READ_FLAGS_RESERVED_LSB 3
+#define   REG_I2CS_FIFO_APB_I2C_READ_FLAGS_RESERVED_MASK 0x1f
+#define   REG_I2CS_FIFO_APB_I2C_READ_FLAGS_FLAGS_LSB 0
+#define   REG_I2CS_FIFO_APB_I2C_READ_FLAGS_FLAGS_MASK 0x7
+#define REG_I2CS_INTERRUPT_STATUS      0x100
+#define   REG_I2CS_INTERRUPT_STATUS_RESERVED_LSB   3
+#define   REG_I2CS_INTERRUPT_STATUS_RESERVED_MASK  0x1f
+#define   REG_I2CS_INTERRUPT_STATUS_I2C_APB_FIFO_WRITE_STATUS_LSB 2
+#define   REG_I2CS_INTERRUPT_STATUS_I2C_APB_FIFO_WRITE_STATUS_MASK 0x1
+#define   REG_I2CS_INTERRUPT_STATUS_APB_I2C_FIFO_READ_STATUS_LSB 1
+#define   REG_I2CS_INTERRUPT_STATUS_APB_I2C_FIFO_READ_STATUS_MASK 0x1
+#define   REG_I2CS_INTERRUPT_STATUS_APB_I2C_MESSAGE_AVAILABLE_LSB 0
+#define   REG_I2CS_INTERRUPT_STATUS_APB_I2C_MESSAGE_AVAILABLE_MASK 0x1
+#define REG_I2CS_INTERRUPT_ENABLE      0x104
+#define   REG_I2CS_INTERRUPT_ENABLE_RESERVED_LSB   3
+#define   REG_I2CS_INTERRUPT_ENABLE_RESERVED_MASK  0x1f
+#define   REG_I2CS_INTERRUPT_ENABLE_I2C_APB_FIFO_WRITE_STATUS_INT_ENABLE_LSB 2
+#define   REG_I2CS_INTERRUPT_ENABLE_I2C_APB_FIFO_WRITE_STATUS_INT_ENABLE_MASK 0x1
+#define   REG_I2CS_INTERRUPT_ENABLE_APB_I2C_FIFO_READ_STATUS_INT_ENABLE_LSB 1
+#define   REG_I2CS_INTERRUPT_ENABLE_APB_I2C_FIFO_READ_STATUS_INT_ENABLE_MASK 0x1
+#define   REG_I2CS_INTERRUPT_ENABLE_APB_I2C_MESSAGE_AVAILABLE_INT_ENABLE_LSB 0
+#define   REG_I2CS_INTERRUPT_ENABLE_APB_I2C_MESSAGE_AVAILABLE_INT_ENABLE_MASK 0x1
+#define REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT 0x108
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_LSB 7
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_LSB 6
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_LSB 5
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_LSB 4
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_LSB 3
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_LSB 2
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_LSB 1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_LSB 0
+#define   REG_I2CS_INTERRUPT_I2C_APB_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_MASK 0x1
+#define REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT 0x10C
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_LSB 7
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_LSB 6
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_LSB 5
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_LSB 4
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_LSB 3
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_LSB 2
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_LSB 1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_EMPTY_LSB 0
+#define   REG_I2CS_INTERRUPT_APB_I2C_READ_FLAGS_SELECT_READ_FLAG_EMPTY_MASK 0x1
+#define REG_I2CS_INTERRUPT_TO_APB_STATUS 0x140
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_RESERVED_LSB 3
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_RESERVED_MASK 0x1f
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_APB_I2C_FIFO_WRITE_STATUS_LSB 2
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_APB_I2C_FIFO_WRITE_STATUS_MASK 0x1
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_I2C_APB_FIFO_READ_STATUS_LSB 1
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_I2C_APB_FIFO_READ_STATUS_MASK 0x1
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_NEW_I2C_APB_MSG_AVAIL_LSB 0
+#define   REG_I2CS_INTERRUPT_TO_APB_STATUS_NEW_I2C_APB_MSG_AVAIL_MASK 0x1
+#define REG_I2CS_INTERRUPT_TO_APB_ENABLE 0x144
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_RESERVED_LSB 3
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_RESERVED_MASK 0x1f
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_APB_I2C_FIFO_WRITE_STATUS_ENABLE_LSB 2
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_APB_I2C_FIFO_WRITE_STATUS_ENABLE_MASK 0x1
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_I2C_APB_FIFO_READ_STATUS_ENABLE_LSB 1
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_I2C_APB_FIFO_READ_STATUS_ENABLE_MASK 0x1
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_NEW_I2C_APB_MSG_AVAIL_ENABLE_LSB 0
+#define   REG_I2CS_INTERRUPT_TO_APB_ENABLE_NEW_I2C_APB_MSG_AVAIL_ENABLE_MASK 0x1
+#define REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT 0x148
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_LSB 7
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_FULL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_LSB 6
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_1_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_LSB 5
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_2_3_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_LSB 4
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_4_7_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_LSB 3
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_8_31_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_LSB 2
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_32_63_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_LSB 1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_64_127_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_LSB 0
+#define   REG_I2CS_INTERRUPT_APB_I2C_WRITE_FLAGS_SELECT_WRITE_FLAG_128_SPACE_AVAIL_MASK 0x1
+#define REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT 0x14C
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_LSB 7
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_128_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_LSB 6
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_64_127_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_LSB 5
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_32_63_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_LSB 4
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_8_31_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_LSB 3
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_4_7_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_LSB 2
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_2_3_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_LSB 1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_1_SPACE_AVAIL_MASK 0x1
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_EMPTY_LSB 0
+#define   REG_I2CS_INTERRUPT_I2C_APB_READ_FLAGS_SELECT_READ_FLAG_EMPTY_MASK 0x1
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __APB_I2CS_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_interrupt_cntrl_reg_defs.h

@@ -0,0 +1,441 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __APB_INTERRUPT_CNTRL_H_
+#define __APB_INTERRUPT_CNTRL_H_
+
+//---------------------------------//
+//
+// Module: APB_INTERRUPT_CNTRL
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t reg_mask;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_mask_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t reg_mask_set;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_mask_set_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t reg_mask_clear;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_mask_clear_b;
+  };
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t reg_int;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_int_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t reg_int_set;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_int_set_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t reg_int_clear;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_int_clear_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t reg_ack;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_ack_b;
+  };
+
+  // Offset = 0x001c
+  union {
+    __IO uint32_t reg_ack_set;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_ack_set_b;
+  };
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t reg_ack_clear;
+    struct {
+      __IO uint32_t  reserved   :  7;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  unused2    :  8;
+      __IO uint32_t  timer_lo_event :  1;
+      __IO uint32_t  timer_hi_event :  1;
+      __IO uint32_t  gpio_event :  1;
+      __IO uint32_t  adv_timer_evens :  4;
+      __IO uint32_t  ref_change_event :  1;
+      __IO uint32_t  unused1    :  5;
+      __IO uint32_t  fc_err_events :  1;
+      __IO uint32_t  fc_hp_events :  2;
+    } reg_ack_clear_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t reg_fifo;
+    struct {
+      __IO uint32_t  event_id   :  8;
+    } reg_fifo_b;
+  };
+} ApbInterruptCntrl_t;
+
+
+#define REG_REG_MASK                   0x000
+#define   REG_REG_MASK_fc_hp_events_LSB            30
+#define   REG_REG_MASK_fc_hp_events_MASK           0x3
+#define   REG_REG_MASK_fc_err_events_LSB           29
+#define   REG_REG_MASK_fc_err_events_MASK          0x1
+#define   REG_REG_MASK_unused1_LSB                 24
+#define   REG_REG_MASK_unused1_MASK                0x1f
+#define   REG_REG_MASK_ref_change_event_LSB        23
+#define   REG_REG_MASK_ref_change_event_MASK       0x1
+#define   REG_REG_MASK_adv_timer_evens_LSB         19
+#define   REG_REG_MASK_adv_timer_evens_MASK        0xf
+#define   REG_REG_MASK_gpio_event_LSB              18
+#define   REG_REG_MASK_gpio_event_MASK             0x1
+#define   REG_REG_MASK_timer_hi_event_LSB          17
+#define   REG_REG_MASK_timer_hi_event_MASK         0x1
+#define   REG_REG_MASK_timer_lo_event_LSB          16
+#define   REG_REG_MASK_timer_lo_event_MASK         0x1
+#define   REG_REG_MASK_unused2_LSB                 8
+#define   REG_REG_MASK_unused2_MASK                0xff
+#define   REG_REG_MASK_timer_lo_event_LSB          7
+#define   REG_REG_MASK_timer_lo_event_MASK         0x1
+#define   REG_REG_MASK_reserved_LSB                0
+#define   REG_REG_MASK_reserved_MASK               0x7f
+#define REG_REG_MASK_SET               0x004
+#define   REG_REG_MASK_SET_fc_hp_events_LSB        30
+#define   REG_REG_MASK_SET_fc_hp_events_MASK       0x3
+#define   REG_REG_MASK_SET_fc_err_events_LSB       29
+#define   REG_REG_MASK_SET_fc_err_events_MASK      0x1
+#define   REG_REG_MASK_SET_unused1_LSB             24
+#define   REG_REG_MASK_SET_unused1_MASK            0x1f
+#define   REG_REG_MASK_SET_ref_change_event_LSB    23
+#define   REG_REG_MASK_SET_ref_change_event_MASK   0x1
+#define   REG_REG_MASK_SET_adv_timer_evens_LSB     19
+#define   REG_REG_MASK_SET_adv_timer_evens_MASK    0xf
+#define   REG_REG_MASK_SET_gpio_event_LSB          18
+#define   REG_REG_MASK_SET_gpio_event_MASK         0x1
+#define   REG_REG_MASK_SET_timer_hi_event_LSB      17
+#define   REG_REG_MASK_SET_timer_hi_event_MASK     0x1
+#define   REG_REG_MASK_SET_timer_lo_event_LSB      16
+#define   REG_REG_MASK_SET_timer_lo_event_MASK     0x1
+#define   REG_REG_MASK_SET_unused2_LSB             8
+#define   REG_REG_MASK_SET_unused2_MASK            0xff
+#define   REG_REG_MASK_SET_timer_lo_event_LSB      7
+#define   REG_REG_MASK_SET_timer_lo_event_MASK     0x1
+#define   REG_REG_MASK_SET_reserved_LSB            0
+#define   REG_REG_MASK_SET_reserved_MASK           0x7f
+#define REG_REG_MASK_CLEAR             0x008
+#define   REG_REG_MASK_CLEAR_fc_hp_events_LSB      30
+#define   REG_REG_MASK_CLEAR_fc_hp_events_MASK     0x3
+#define   REG_REG_MASK_CLEAR_fc_err_events_LSB     29
+#define   REG_REG_MASK_CLEAR_fc_err_events_MASK    0x1
+#define   REG_REG_MASK_CLEAR_unused1_LSB           24
+#define   REG_REG_MASK_CLEAR_unused1_MASK          0x1f
+#define   REG_REG_MASK_CLEAR_ref_change_event_LSB  23
+#define   REG_REG_MASK_CLEAR_ref_change_event_MASK 0x1
+#define   REG_REG_MASK_CLEAR_adv_timer_evens_LSB   19
+#define   REG_REG_MASK_CLEAR_adv_timer_evens_MASK  0xf
+#define   REG_REG_MASK_CLEAR_gpio_event_LSB        18
+#define   REG_REG_MASK_CLEAR_gpio_event_MASK       0x1
+#define   REG_REG_MASK_CLEAR_timer_hi_event_LSB    17
+#define   REG_REG_MASK_CLEAR_timer_hi_event_MASK   0x1
+#define   REG_REG_MASK_CLEAR_timer_lo_event_LSB    16
+#define   REG_REG_MASK_CLEAR_timer_lo_event_MASK   0x1
+#define   REG_REG_MASK_CLEAR_unused2_LSB           8
+#define   REG_REG_MASK_CLEAR_unused2_MASK          0xff
+#define   REG_REG_MASK_CLEAR_timer_lo_event_LSB    7
+#define   REG_REG_MASK_CLEAR_timer_lo_event_MASK   0x1
+#define   REG_REG_MASK_CLEAR_reserved_LSB          0
+#define   REG_REG_MASK_CLEAR_reserved_MASK         0x7f
+#define REG_REG_INT                    0x00C
+#define   REG_REG_INT_fc_hp_events_LSB             30
+#define   REG_REG_INT_fc_hp_events_MASK            0x3
+#define   REG_REG_INT_fc_err_events_LSB            29
+#define   REG_REG_INT_fc_err_events_MASK           0x1
+#define   REG_REG_INT_unused1_LSB                  24
+#define   REG_REG_INT_unused1_MASK                 0x1f
+#define   REG_REG_INT_ref_change_event_LSB         23
+#define   REG_REG_INT_ref_change_event_MASK        0x1
+#define   REG_REG_INT_adv_timer_evens_LSB          19
+#define   REG_REG_INT_adv_timer_evens_MASK         0xf
+#define   REG_REG_INT_gpio_event_LSB               18
+#define   REG_REG_INT_gpio_event_MASK              0x1
+#define   REG_REG_INT_timer_hi_event_LSB           17
+#define   REG_REG_INT_timer_hi_event_MASK          0x1
+#define   REG_REG_INT_timer_lo_event_LSB           16
+#define   REG_REG_INT_timer_lo_event_MASK          0x1
+#define   REG_REG_INT_unused2_LSB                  8
+#define   REG_REG_INT_unused2_MASK                 0xff
+#define   REG_REG_INT_timer_lo_event_LSB           7
+#define   REG_REG_INT_timer_lo_event_MASK          0x1
+#define   REG_REG_INT_reserved_LSB                 0
+#define   REG_REG_INT_reserved_MASK                0x7f
+#define REG_REG_INT_SET                0x010
+#define   REG_REG_INT_SET_fc_hp_events_LSB         30
+#define   REG_REG_INT_SET_fc_hp_events_MASK        0x3
+#define   REG_REG_INT_SET_fc_err_events_LSB        29
+#define   REG_REG_INT_SET_fc_err_events_MASK       0x1
+#define   REG_REG_INT_SET_unused1_LSB              24
+#define   REG_REG_INT_SET_unused1_MASK             0x1f
+#define   REG_REG_INT_SET_ref_change_event_LSB     23
+#define   REG_REG_INT_SET_ref_change_event_MASK    0x1
+#define   REG_REG_INT_SET_adv_timer_evens_LSB      19
+#define   REG_REG_INT_SET_adv_timer_evens_MASK     0xf
+#define   REG_REG_INT_SET_gpio_event_LSB           18
+#define   REG_REG_INT_SET_gpio_event_MASK          0x1
+#define   REG_REG_INT_SET_timer_hi_event_LSB       17
+#define   REG_REG_INT_SET_timer_hi_event_MASK      0x1
+#define   REG_REG_INT_SET_timer_lo_event_LSB       16
+#define   REG_REG_INT_SET_timer_lo_event_MASK      0x1
+#define   REG_REG_INT_SET_unused2_LSB              8
+#define   REG_REG_INT_SET_unused2_MASK             0xff
+#define   REG_REG_INT_SET_timer_lo_event_LSB       7
+#define   REG_REG_INT_SET_timer_lo_event_MASK      0x1
+#define   REG_REG_INT_SET_reserved_LSB             0
+#define   REG_REG_INT_SET_reserved_MASK            0x7f
+#define REG_REG_INT_CLEAR              0x014
+#define   REG_REG_INT_CLEAR_fc_hp_events_LSB       30
+#define   REG_REG_INT_CLEAR_fc_hp_events_MASK      0x3
+#define   REG_REG_INT_CLEAR_fc_err_events_LSB      29
+#define   REG_REG_INT_CLEAR_fc_err_events_MASK     0x1
+#define   REG_REG_INT_CLEAR_unused1_LSB            24
+#define   REG_REG_INT_CLEAR_unused1_MASK           0x1f
+#define   REG_REG_INT_CLEAR_ref_change_event_LSB   23
+#define   REG_REG_INT_CLEAR_ref_change_event_MASK  0x1
+#define   REG_REG_INT_CLEAR_adv_timer_evens_LSB    19
+#define   REG_REG_INT_CLEAR_adv_timer_evens_MASK   0xf
+#define   REG_REG_INT_CLEAR_gpio_event_LSB         18
+#define   REG_REG_INT_CLEAR_gpio_event_MASK        0x1
+#define   REG_REG_INT_CLEAR_timer_hi_event_LSB     17
+#define   REG_REG_INT_CLEAR_timer_hi_event_MASK    0x1
+#define   REG_REG_INT_CLEAR_timer_lo_event_LSB     16
+#define   REG_REG_INT_CLEAR_timer_lo_event_MASK    0x1
+#define   REG_REG_INT_CLEAR_unused2_LSB            8
+#define   REG_REG_INT_CLEAR_unused2_MASK           0xff
+#define   REG_REG_INT_CLEAR_timer_lo_event_LSB     7
+#define   REG_REG_INT_CLEAR_timer_lo_event_MASK    0x1
+#define   REG_REG_INT_CLEAR_reserved_LSB           0
+#define   REG_REG_INT_CLEAR_reserved_MASK          0x7f
+#define REG_REG_ACK                    0x018
+#define   REG_REG_ACK_fc_hp_events_LSB             30
+#define   REG_REG_ACK_fc_hp_events_MASK            0x3
+#define   REG_REG_ACK_fc_err_events_LSB            29
+#define   REG_REG_ACK_fc_err_events_MASK           0x1
+#define   REG_REG_ACK_unused1_LSB                  24
+#define   REG_REG_ACK_unused1_MASK                 0x1f
+#define   REG_REG_ACK_ref_change_event_LSB         23
+#define   REG_REG_ACK_ref_change_event_MASK        0x1
+#define   REG_REG_ACK_adv_timer_evens_LSB          19
+#define   REG_REG_ACK_adv_timer_evens_MASK         0xf
+#define   REG_REG_ACK_gpio_event_LSB               18
+#define   REG_REG_ACK_gpio_event_MASK              0x1
+#define   REG_REG_ACK_timer_hi_event_LSB           17
+#define   REG_REG_ACK_timer_hi_event_MASK          0x1
+#define   REG_REG_ACK_timer_lo_event_LSB           16
+#define   REG_REG_ACK_timer_lo_event_MASK          0x1
+#define   REG_REG_ACK_unused2_LSB                  8
+#define   REG_REG_ACK_unused2_MASK                 0xff
+#define   REG_REG_ACK_timer_lo_event_LSB           7
+#define   REG_REG_ACK_timer_lo_event_MASK          0x1
+#define   REG_REG_ACK_reserved_LSB                 0
+#define   REG_REG_ACK_reserved_MASK                0x7f
+#define REG_REG_ACK_SET                0x01C
+#define   REG_REG_ACK_SET_fc_hp_events_LSB         30
+#define   REG_REG_ACK_SET_fc_hp_events_MASK        0x3
+#define   REG_REG_ACK_SET_fc_err_events_LSB        29
+#define   REG_REG_ACK_SET_fc_err_events_MASK       0x1
+#define   REG_REG_ACK_SET_unused1_LSB              24
+#define   REG_REG_ACK_SET_unused1_MASK             0x1f
+#define   REG_REG_ACK_SET_ref_change_event_LSB     23
+#define   REG_REG_ACK_SET_ref_change_event_MASK    0x1
+#define   REG_REG_ACK_SET_adv_timer_evens_LSB      19
+#define   REG_REG_ACK_SET_adv_timer_evens_MASK     0xf
+#define   REG_REG_ACK_SET_gpio_event_LSB           18
+#define   REG_REG_ACK_SET_gpio_event_MASK          0x1
+#define   REG_REG_ACK_SET_timer_hi_event_LSB       17
+#define   REG_REG_ACK_SET_timer_hi_event_MASK      0x1
+#define   REG_REG_ACK_SET_timer_lo_event_LSB       16
+#define   REG_REG_ACK_SET_timer_lo_event_MASK      0x1
+#define   REG_REG_ACK_SET_unused2_LSB              8
+#define   REG_REG_ACK_SET_unused2_MASK             0xff
+#define   REG_REG_ACK_SET_timer_lo_event_LSB       7
+#define   REG_REG_ACK_SET_timer_lo_event_MASK      0x1
+#define   REG_REG_ACK_SET_reserved_LSB             0
+#define   REG_REG_ACK_SET_reserved_MASK            0x7f
+#define REG_REG_ACK_CLEAR              0x020
+#define   REG_REG_ACK_CLEAR_fc_hp_events_LSB       30
+#define   REG_REG_ACK_CLEAR_fc_hp_events_MASK      0x3
+#define   REG_REG_ACK_CLEAR_fc_err_events_LSB      29
+#define   REG_REG_ACK_CLEAR_fc_err_events_MASK     0x1
+#define   REG_REG_ACK_CLEAR_unused1_LSB            24
+#define   REG_REG_ACK_CLEAR_unused1_MASK           0x1f
+#define   REG_REG_ACK_CLEAR_ref_change_event_LSB   23
+#define   REG_REG_ACK_CLEAR_ref_change_event_MASK  0x1
+#define   REG_REG_ACK_CLEAR_adv_timer_evens_LSB    19
+#define   REG_REG_ACK_CLEAR_adv_timer_evens_MASK   0xf
+#define   REG_REG_ACK_CLEAR_gpio_event_LSB         18
+#define   REG_REG_ACK_CLEAR_gpio_event_MASK        0x1
+#define   REG_REG_ACK_CLEAR_timer_hi_event_LSB     17
+#define   REG_REG_ACK_CLEAR_timer_hi_event_MASK    0x1
+#define   REG_REG_ACK_CLEAR_timer_lo_event_LSB     16
+#define   REG_REG_ACK_CLEAR_timer_lo_event_MASK    0x1
+#define   REG_REG_ACK_CLEAR_unused2_LSB            8
+#define   REG_REG_ACK_CLEAR_unused2_MASK           0xff
+#define   REG_REG_ACK_CLEAR_timer_lo_event_LSB     7
+#define   REG_REG_ACK_CLEAR_timer_lo_event_MASK    0x1
+#define   REG_REG_ACK_CLEAR_reserved_LSB           0
+#define   REG_REG_ACK_CLEAR_reserved_MASK          0x7f
+#define REG_REG_FIFO                   0x024
+#define   REG_REG_FIFO_EVENT_ID_LSB                0
+#define   REG_REG_FIFO_EVENT_ID_MASK               0xff
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __APB_INTERRUPT_CNTRL_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc.h

@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2020 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Description: SoC configuration registers (apb_soc_ctrl)
+ * Authors: Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ *          Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#ifndef HAL_INCLUDE_HAL_APB_SOC_H_
+#define HAL_INCLUDE_HAL_APB_SOC_H_
+
+
+
+#define APB_SOC_BOOT_OTHER    0
+#define APB_SOC_BOOT_JTAG     1
+#define APB_SOC_BOOT_SPI      2
+#define APB_SOC_BOOT_ROM      3
+#define APB_SOC_BOOT_PRELOAD  4
+#define APB_SOC_BOOT_HYPER    5
+#define APB_SOC_BOOT_SPIM     6
+#define APB_SOC_BOOT_SPIM_QPI 7
+
+#define APB_SOC_PLT_OTHER   0
+#define APB_SOC_PLT_FPGA    1
+#define APB_SOC_PLT_RTL     2
+#define APB_SOC_PLT_VP      3
+#define APB_SOC_PLT_CHIP    4
+
+//PADs configuration is made of 8bits out of which only the first 6 are used
+//bit0    enable pull UP
+//bit1    enable pull DOWN
+//bit2    enable ST
+//bit3    enable SlewRate Limit
+//bit4..5 Driving Strength
+//bit6..7 not used
+
+#define APB_SOC_BOOTADDR_OFFSET   0x04
+#define APB_SOC_INFO_OFFSET       0x00 //contains number of cores [31:16] and clusters [15:0]
+#define APB_SOC_INFOEXTD_OFFSET   0x04 //not used at the moment
+#define APB_SOC_NOTUSED0_OFFSET   0x08 //not used at the moment
+#define APB_SOC_CLUSTER_ISOLATE_OFFSET   0x0C //not used at the moment
+
+#define	APB_SOC_PADFUN0_OFFSET	  0x10
+#define	APB_SOC_PADCFG0_OFFSET	  0x20
+
+#define APB_SOC_PADFUN_OFFSET(g)   (APB_SOC_PADFUN0_OFFSET+(g)*4) //sets the mux for pins  g*16+0 (bits [1:0]) to g*16+15 (bits [31:30])
+#define APB_SOC_PADFUN_NO(pad)     ((pad) >> 4)
+#define APB_SOC_PADFUN_PAD(padfun) ((padfun)*16)
+#define APB_SOC_PADFUN_SIZE        2
+#define ARCHI_APB_SOC_PADFUN_NB          4
+#define APB_SOC_PADFUN_BIT(pad)    (((pad) & 0xF) << 1)
+
+#define APB_SOC_PADCFG_OFFSET(g)   (APB_SOC_PADCFG0_OFFSET+(g)*4) //sets config for pin  g*4+0(bits [7:0]) to pin  g*4+3(bits [31:24])
+#define APB_SOC_PADCFG_NO(pad)     ((pad) >> 2)
+#define APB_SOC_PADCFG_PAD(padfun) ((padfun)*4)
+#define APB_SOC_PADCFG_SIZE        8
+#define APB_SOC_PADCFG_BIT(pad)    (((pad) & 0x3) << 3)
+
+#define APB_SOC_PWRCMD_OFFSET     0x60 //change power mode(not funtional yet)
+#define APB_SOC_PWRCFG_OFFSET     0x64 //configures power modes(not funtional yet)
+#define APB_SOC_PWRREG_OFFSET     0x68 //32 bit GP register used by power pngmt routines to see if is hard or cold reboot
+#define APB_SOC_BUSY_OFFSET       0x6C //not used at the moment
+#define APB_SOC_MMARGIN_OFFSET    0x70 //memory margin pins(not used at the moment)
+#define APB_SOC_JTAG_REG          0x74 // R/W register for interaction with the the chip environment
+#define APB_SOC_L2_SLEEP_OFFSET   0x78 //memory margin pins(not used at the moment)
+#define APB_SOC_NOTUSED3_OFFSET   0x7C //not used at the moment
+#define APB_SOC_CLKDIV0_OFFSET    0x80 //soc clock divider(to be removed)
+#define APB_SOC_CLKDIV1_OFFSET    0x84 //cluster clock divider(to be removed)
+#define APB_SOC_CLKDIV2_OFFSET    0x88 //not used at the moment
+#define APB_SOC_CLKDIV3_OFFSET    0x8C //not used at the moment
+#define APB_SOC_CLKDIV4_OFFSET    0x90 //not used at the moment
+#define APB_SOC_NOTUSED4_OFFSET   0x94 //not used at the moment
+#define APB_SOC_NOTUSED5_OFFSET   0x98 //not used at the moment
+#define APB_SOC_NOTUSED6_OFFSET   0x9C //not used at the moment
+#define APB_SOC_CORESTATUS_OFFSET 0xA0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
+#define APB_SOC_CORESTATUS_RO_OFFSET 0xC0 //32bit GP register to be used during testing to return EOC(bit[31]) and status(bit[30:0])
+#define APB_SOC_PADS_CONFIG       0xC4
+
+#define APB_SOC_PADS_CONFIG_BOOTSEL_BIT 0
+
+#define APB_SOC_JTAG_REG_EXT_BIT   8
+#define APB_SOC_JTAG_REG_EXT_WIDTH 4
+
+#define APB_SOC_JTAG_REG_LOC_BIT   0
+#define APB_SOC_JTAG_REG_LOC_WIDTH 4
+
+#define APB_SOC_INFO_CORES_OFFSET    (APB_SOC_INFO_OFFSET + 2)
+#define APB_SOC_INFO_CLUSTERS_OFFSET (APB_SOC_INFO_OFFSET)
+
+#define APB_SOC_STATUS_EOC_BIT  31
+#define APB_SOC_NB_CORE_BIT     16
+
+
+#define APB_SOC_BYPASS_OFFSET   0x70
+
+#define APB_SOC_BYPASS_CLOCK_GATE_BIT 10
+#define APB_SOC_BYPASS_CLUSTER_STATE_BIT 3
+#define APB_SOC_BYPASS_USER0_BIT       14
+#define APB_SOC_BYPASS_USER1_BIT       15
+
+
+#define APB_SOC_FLL_CTRL_OFFSET         0xD0
+#define APB_SOC_CLKDIV_SOC_OFFSET       0xD4
+#define APB_SOC_CLKDIV_CLUSTER_OFFSET   0xD8
+#define APB_SOC_CLKDIV_PERIPH_OFFSET    0xDC
+
+
+#define APB_SOC_FLL_CTRL_SOC_BIT        0
+#define APB_SOC_FLL_CTRL_CLUSTER_BIT    1
+#define APB_SOC_FLL_CTRL_PERIPH_BIT     2
+
+
+#define APB_SOC_RTC_OFFSET     0x1D0
+
+
+#endif /* HAL_INCLUDE_HAL_APB_SOC_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc_ctrl_reg_defs.h

@@ -0,0 +1,365 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SOC_CTRL_H_
+#define __SOC_CTRL_H_
+
+//---------------------------------//
+//
+// Module: SOC_CTRL
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t info;
+    struct {
+      __IO uint32_t  n_clusters : 16;
+      __IO uint32_t  n_cores    : 16;
+    } info_b;
+  };
+  __I uint32_t    unused0[2];
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t build_date;
+    struct {
+      __IO uint32_t  day        :  8;
+      __IO uint32_t  month      :  8;
+      __IO uint32_t  year       : 16;
+    } build_date_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t build_time;
+    struct {
+      __IO uint32_t  seconds    :  8;
+      __IO uint32_t  minutes    :  8;
+      __IO uint32_t  hour       :  8;
+    } build_time_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t io_cfg0;
+    struct {
+      __IO uint32_t  n_io       :  8;
+      __IO uint32_t  n_sysio    :  8;
+      __IO uint32_t  n_gpio     :  8;
+    } io_cfg0_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t io_cfg1;
+    struct {
+      __IO uint32_t  nbit_padcfg :  8;
+      __IO uint32_t  nbit_padmux :  8;
+    } io_cfg1_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t per_cfg0;
+    struct {
+      __IO uint32_t  n_uart     :  8;
+      __IO uint32_t  n_qspim    :  8;
+      __IO uint32_t  n_i2cm     :  8;
+      __IO uint32_t  n_i2sc     :  8;
+    } per_cfg0_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t per_cfg1;
+    struct {
+      __IO uint32_t  n_sdio     :  8;
+      __IO uint32_t  n_cam      :  8;
+    } per_cfg1_b;
+  };
+  __I uint32_t    unused2[19];
+
+  // Offset = 0x0074
+  union {
+    __IO uint32_t jtagreg;
+  };
+  __I uint32_t    unused3[10];
+
+  // Offset = 0x00a0
+  union {
+    __IO uint32_t corestatus;
+    struct {
+      __IO uint32_t  status     : 31;
+      __IO uint32_t  eoc        :  1;
+    } corestatus_b;
+  };
+  __I uint32_t    unused4[7];
+
+  // Offset = 0x00c0
+  union {
+    __IO uint32_t cs_ro;
+    struct {
+      __IO uint32_t  status     : 31;
+      __IO uint32_t  eoc        :  1;
+    } cs_ro_b;
+  };
+
+  // Offset = 0x00c4
+  union {
+    __IO uint32_t bootsel;
+  };
+
+  // Offset = 0x00c8
+  union {
+    __IO uint32_t clksel;
+  };
+  __I uint32_t    unused5[3];
+
+  // Offset = 0x00d8
+  union {
+    __IO uint32_t clk_div_clu;
+  };
+  __I uint32_t    unused6[1];
+
+  // Offset = 0x00e0
+  union {
+    __IO uint32_t rto_peripheral_error;
+    struct {
+      __IO uint32_t  fll_rto    :  1;
+      __IO uint32_t  gpio_rto   :  1;
+      __IO uint32_t  udma_rto   :  1;
+      __IO uint32_t  soc_control_rto :  1;
+      __IO uint32_t  adv_timer_rto :  1;
+      __IO uint32_t  event_gen_rto :  1;
+      __IO uint32_t  i2cs_rto   :  1;
+      __IO uint32_t  timer_rto  :  1;
+      __IO uint32_t  fcb_rto    :  1;
+    } rto_peripheral_error_b;
+  };
+
+  // Offset = 0x00e4
+  union {
+    __IO uint32_t ready_timeout_count;
+    struct {
+      __IO uint32_t  count      : 20;
+    } ready_timeout_count_b;
+  };
+
+  // Offset = 0x00e8
+  union {
+    __IO uint32_t reset_type1_efpga;
+    struct {
+      __IO uint32_t  reset_lt   :  1;
+      __IO uint32_t  reset_rt   :  1;
+      __IO uint32_t  reset_rb   :  1;
+      __IO uint32_t  reset_lb   :  1;
+    } reset_type1_efpga_b;
+  };
+
+  // Offset = 0x00ec
+  union {
+    __IO uint32_t enable_in_out_efpga;
+    struct {
+      __IO uint32_t  enable_tcdm_p0 :  1;
+      __IO uint32_t  enable_tcdm_p1 :  1;
+      __IO uint32_t  enable_tcdm_p2 :  1;
+      __IO uint32_t  enable_tcdm_p3 :  1;
+      __IO uint32_t  enable_soc_access :  1;
+      __IO uint32_t  enable_events :  1;
+    } enable_in_out_efpga_b;
+  };
+
+  // Offset = 0x00f0
+  union {
+    __IO uint32_t efpga_control_in;
+  };
+
+  // Offset = 0x00f4
+  union {
+    __IO uint32_t efpga_status_out;
+  };
+
+  // Offset = 0x00f8
+  union {
+    __IO uint32_t efpga_version;
+  };
+
+  // Offset = 0x00fc
+  union {
+    __IO uint32_t soft_reset;
+  };
+  __I uint32_t    unused7[192];
+
+  // Offset = 0x0400
+  union {
+    __IO uint32_t io_ctrl[48];
+    struct {
+      __IO uint32_t  mux        :  2;
+      __IO uint32_t             :  6;
+      __IO uint32_t  cfg        :  6;
+    } io_ctrl_b[48];
+  };
+} SocCtrl_t;
+
+
+#define REG_INFO                       0x0000
+#define   REG_INFO_N_CORES_LSB                     16
+#define   REG_INFO_N_CORES_MASK                    0xffff
+#define   REG_INFO_N_CLUSTERS_LSB                  0
+#define   REG_INFO_N_CLUSTERS_MASK                 0xffff
+#define REG_BUILD_DATE                 0x000C
+#define   REG_BUILD_DATE_YEAR_LSB                  16
+#define   REG_BUILD_DATE_YEAR_MASK                 0xffff
+#define   REG_BUILD_DATE_MONTH_LSB                 8
+#define   REG_BUILD_DATE_MONTH_MASK                0xff
+#define   REG_BUILD_DATE_DAY_LSB                   0
+#define   REG_BUILD_DATE_DAY_MASK                  0xff
+#define REG_BUILD_TIME                 0x0010
+#define   REG_BUILD_TIME_HOUR_LSB                  16
+#define   REG_BUILD_TIME_HOUR_MASK                 0xff
+#define   REG_BUILD_TIME_MINUTES_LSB               8
+#define   REG_BUILD_TIME_MINUTES_MASK              0xff
+#define   REG_BUILD_TIME_SECONDS_LSB               0
+#define   REG_BUILD_TIME_SECONDS_MASK              0xff
+#define REG_IO_CFG0                    0x0014
+#define   REG_IO_CFG0_N_GPIO_LSB                   16
+#define   REG_IO_CFG0_N_GPIO_MASK                  0xff
+#define   REG_IO_CFG0_N_SYSIO_LSB                  8
+#define   REG_IO_CFG0_N_SYSIO_MASK                 0xff
+#define   REG_IO_CFG0_N_IO_LSB                     0
+#define   REG_IO_CFG0_N_IO_MASK                    0xff
+#define REG_IO_CFG1                    0x0018
+#define   REG_IO_CFG1_NBIT_PADMUX_LSB              8
+#define   REG_IO_CFG1_NBIT_PADMUX_MASK             0xff
+#define   REG_IO_CFG1_NBIT_PADCFG_LSB              0
+#define   REG_IO_CFG1_NBIT_PADCFG_MASK             0xff
+#define REG_PER_CFG0                   0x0020
+#define   REG_PER_CFG0_N_I2SC_LSB                  24
+#define   REG_PER_CFG0_N_I2SC_MASK                 0xff
+#define   REG_PER_CFG0_N_I2CM_LSB                  16
+#define   REG_PER_CFG0_N_I2CM_MASK                 0xff
+#define   REG_PER_CFG0_N_QSPIM_LSB                 8
+#define   REG_PER_CFG0_N_QSPIM_MASK                0xff
+#define   REG_PER_CFG0_N_UART_LSB                  0
+#define   REG_PER_CFG0_N_UART_MASK                 0xff
+#define REG_PER_CFG1                   0x0024
+#define   REG_PER_CFG1_N_CAM_LSB                   8
+#define   REG_PER_CFG1_N_CAM_MASK                  0xff
+#define   REG_PER_CFG1_N_SDIO_LSB                  0
+#define   REG_PER_CFG1_N_SDIO_MASK                 0xff
+#define REG_JTAGREG                    0x0074
+#define REG_CORESTATUS                 0x00A0
+#define   REG_CORESTATUS_EOC_LSB                   31
+#define   REG_CORESTATUS_EOC_MASK                  0x1
+#define   REG_CORESTATUS_STATUS_LSB                0
+#define   REG_CORESTATUS_STATUS_MASK               0x7fffffff
+#define REG_CS_RO                      0x00C0
+#define   REG_CS_RO_EOC_LSB                        31
+#define   REG_CS_RO_EOC_MASK                       0x1
+#define   REG_CS_RO_STATUS_LSB                     0
+#define   REG_CS_RO_STATUS_MASK                    0x7fffffff
+#define REG_BOOTSEL                    0x00C4
+#define REG_CLKSEL                     0x00C8
+#define REG_CLK_DIV_CLU                0x00D8
+#define REG_RTO_PERIPHERAL_ERROR       0x00E0
+#define   REG_RTO_PERIPHERAL_ERROR_FCB_RTO_LSB     8
+#define   REG_RTO_PERIPHERAL_ERROR_FCB_RTO_MASK    0x1
+#define   REG_RTO_PERIPHERAL_ERROR_TIMER_RTO_LSB   7
+#define   REG_RTO_PERIPHERAL_ERROR_TIMER_RTO_MASK  0x1
+#define   REG_RTO_PERIPHERAL_ERROR_I2CS_RTO_LSB    6
+#define   REG_RTO_PERIPHERAL_ERROR_I2CS_RTO_MASK   0x1
+#define   REG_RTO_PERIPHERAL_ERROR_EVENT_GEN_RTO_LSB 5
+#define   REG_RTO_PERIPHERAL_ERROR_EVENT_GEN_RTO_MASK 0x1
+#define   REG_RTO_PERIPHERAL_ERROR_ADV_TIMER_RTO_LSB 4
+#define   REG_RTO_PERIPHERAL_ERROR_ADV_TIMER_RTO_MASK 0x1
+#define   REG_RTO_PERIPHERAL_ERROR_SOC_CONTROL_RTO_LSB 3
+#define   REG_RTO_PERIPHERAL_ERROR_SOC_CONTROL_RTO_MASK 0x1
+#define   REG_RTO_PERIPHERAL_ERROR_UDMA_RTO_LSB    2
+#define   REG_RTO_PERIPHERAL_ERROR_UDMA_RTO_MASK   0x1
+#define   REG_RTO_PERIPHERAL_ERROR_GPIO_RTO_LSB    1
+#define   REG_RTO_PERIPHERAL_ERROR_GPIO_RTO_MASK   0x1
+#define   REG_RTO_PERIPHERAL_ERROR_FLL_RTO_LSB     0
+#define   REG_RTO_PERIPHERAL_ERROR_FLL_RTO_MASK    0x1
+#define REG_READY_TIMEOUT_COUNT        0x00E4
+#define   REG_READY_TIMEOUT_COUNT_COUNT_LSB        0
+#define   REG_READY_TIMEOUT_COUNT_COUNT_MASK       0xfffff
+#define REG_RESET_TYPE1_EFPGA          0x00E8
+#define   REG_RESET_TYPE1_EFPGA_RESET_LB_LSB       3
+#define   REG_RESET_TYPE1_EFPGA_RESET_LB_MASK      0x1
+#define   REG_RESET_TYPE1_EFPGA_RESET_RB_LSB       2
+#define   REG_RESET_TYPE1_EFPGA_RESET_RB_MASK      0x1
+#define   REG_RESET_TYPE1_EFPGA_RESET_RT_LSB       1
+#define   REG_RESET_TYPE1_EFPGA_RESET_RT_MASK      0x1
+#define   REG_RESET_TYPE1_EFPGA_RESET_LT_LSB       0
+#define   REG_RESET_TYPE1_EFPGA_RESET_LT_MASK      0x1
+#define REG_ENABLE_IN_OUT_EFPGA        0x00EC
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_EVENTS_LSB 5
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_EVENTS_MASK 0x1
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_SOC_ACCESS_LSB 4
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_SOC_ACCESS_MASK 0x1
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P3_LSB 3
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P3_MASK 0x1
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P2_LSB 2
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P2_MASK 0x1
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P1_LSB 1
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P1_MASK 0x1
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P0_LSB 0
+#define   REG_ENABLE_IN_OUT_EFPGA_ENABLE_TCDM_P0_MASK 0x1
+#define REG_EFPGA_CONTROL_IN           0x00F0
+#define REG_EFPGA_STATUS_OUT           0x00F4
+#define REG_EFPGA_VERSION              0x00F8
+#define REG_SOFT_RESET                 0x00FC
+#define REG_IO_CTRL                    0x0400
+#define   REG_IO_CTRL_CFG_LSB                      8
+#define   REG_IO_CTRL_CFG_MASK                     0x3f
+#define   REG_IO_CTRL_MUX_LSB                      0
+#define   REG_IO_CTRL_MUX_MASK                     0x3
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __SOC_CTRL_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_soc_ctrl_regs.h

@@ -0,0 +1,207 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SOC_CTRL_H_
+#define __SOC_CTRL_H_
+
+//---------------------------------//
+//
+// Module: SOC_CTRL
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t info;
+    struct {
+      __IO uint32_t  n_clusters : 16;
+      __IO uint32_t  n_cores    : 16;
+    } info_b;
+  };
+  __I uint32_t    unused0[2];
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t build_date;
+    struct {
+      __IO uint32_t  day        :  8;
+      __IO uint32_t  month      :  8;
+      __IO uint32_t  year       : 16;
+    } build_date_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t build_time;
+    struct {
+      __IO uint32_t  seconds    :  8;
+      __IO uint32_t  minutes    :  8;
+      __IO uint32_t  hour       :  8;
+    } build_time_b;
+  };
+  __I uint32_t    unused1[24];
+
+  // Offset = 0x0074
+  union {
+    __IO uint32_t jtagreg;
+  };
+  __I uint32_t    unused2[10];
+
+  // Offset = 0x00a0
+  union {
+    __IO uint32_t corestatus;
+    struct {
+      __IO uint32_t  status     : 31;
+      __IO uint32_t  eoc        :  1;
+    } corestatus_b;
+  };
+  __I uint32_t    unused3[7];
+
+  // Offset = 0x00c0
+  union {
+    __IO uint32_t cs_ro;
+    struct {
+      __IO uint32_t  status     : 31;
+      __IO uint32_t  eoc        :  1;
+    } cs_ro_b;
+  };
+
+  // Offset = 0x00c4
+  union {
+    __IO uint32_t bootsel;
+  };
+
+  // Offset = 0x00c8
+  union {
+    __IO uint32_t clksel;
+  };
+  __I uint32_t    unused4[3];
+
+  // Offset = 0x00d8
+  union {
+    __IO uint32_t clk_div_clu;
+  };
+  __I uint32_t    unused5[1];
+
+  // Offset = 0x00e0
+  union {
+    __IO uint32_t sel_clk_dc_fifo_efpga;
+  };
+
+  // Offset = 0x00e4
+  union {
+    __IO uint32_t clk_gating_dc_fifo_efpga;
+  };
+
+  // Offset = 0x00e8
+  union {
+    __IO uint32_t reset_type1_efpga;
+  };
+
+  // Offset = 0x00ec
+  union {
+    __IO uint32_t enable_in_out_efpga;
+  };
+  __I uint32_t    unused6[196];
+
+  // Offset = 0x0400
+  union {
+    __IO uint32_t io_ctrl[48];
+    struct {
+      __IO uint32_t  mux        :  2;
+      __IO uint32_t             :  6;
+      __IO uint32_t  cfg        :  6;
+    } io_ctrl_b[48];
+  };
+} SocCtrl_t;
+
+
+#define REG_INFO                       0x0000
+#define   REG_INFO_N_CORES_LSB                     16
+#define   REG_INFO_N_CORES_MASK                    0xffff
+#define   REG_INFO_N_CLUSTERS_LSB                  0
+#define   REG_INFO_N_CLUSTERS_MASK                 0xffff
+#define REG_BUILD_DATE                 0x000C
+#define   REG_BUILD_DATE_YEAR_LSB                  16
+#define   REG_BUILD_DATE_YEAR_MASK                 0xffff
+#define   REG_BUILD_DATE_MONTH_LSB                 8
+#define   REG_BUILD_DATE_MONTH_MASK                0xff
+#define   REG_BUILD_DATE_DAY_LSB                   0
+#define   REG_BUILD_DATE_DAY_MASK                  0xff
+#define REG_BUILD_TIME                 0x0010
+#define   REG_BUILD_TIME_HOUR_LSB                  16
+#define   REG_BUILD_TIME_HOUR_MASK                 0xff
+#define   REG_BUILD_TIME_MINUTES_LSB               8
+#define   REG_BUILD_TIME_MINUTES_MASK              0xff
+#define   REG_BUILD_TIME_SECONDS_LSB               0
+#define   REG_BUILD_TIME_SECONDS_MASK              0xff
+#define REG_JTAGREG                    0x0074
+#define REG_CORESTATUS                 0x00A0
+#define   REG_CORESTATUS_EOC_LSB                   31
+#define   REG_CORESTATUS_EOC_MASK                  0x1
+#define   REG_CORESTATUS_STATUS_LSB                0
+#define   REG_CORESTATUS_STATUS_MASK               0x7fffffff
+#define REG_CS_RO                      0x00C0
+#define   REG_CS_RO_EOC_LSB                        31
+#define   REG_CS_RO_EOC_MASK                       0x1
+#define   REG_CS_RO_STATUS_LSB                     0
+#define   REG_CS_RO_STATUS_MASK                    0x7fffffff
+#define REG_BOOTSEL                    0x00C4
+#define REG_CLKSEL                     0x00C8
+#define REG_CLK_DIV_CLU                0x00D8
+#define REG_SEL_CLK_DC_FIFO_EFPGA      0x00E0
+#define REG_CLK_GATING_DC_FIFO_EFPGA   0x00E4
+#define REG_RESET_TYPE1_EFPGA          0x00E8
+#define REG_ENABLE_IN_OUT_EFPGA        0x00EC
+#define REG_IO_CTRL                    0x0400
+#define   REG_IO_CTRL_CFG_LSB                      8
+#define   REG_IO_CTRL_CFG_MASK                     0x3f
+#define   REG_IO_CTRL_MUX_LSB                      0
+#define   REG_IO_CTRL_MUX_MASK                     0x3
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __SOC_CTRL_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_apb_timer_unit_reg_defs.h

@@ -0,0 +1,233 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __APB_TIMER_UNIT_H_
+#define __APB_TIMER_UNIT_H_
+
+//---------------------------------//
+//
+// Module: APB_TIMER_UNIT
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t cfg_reg_lo;
+    struct {
+      __IO uint32_t  enable_bit :  1;
+      __IO uint32_t  reset_bit  :  1;
+      __IO uint32_t  irq_bit    :  1;
+      __IO uint32_t  iem_bit    :  1;
+      __IO uint32_t  cmp_clr_bit :  1;
+      __IO uint32_t  one_shot_bit :  1;
+      __IO uint32_t  prescaler_en_bit :  1;
+      __IO uint32_t  ref_clk_en_bit :  1;
+      __IO uint32_t  prescaler_count :  8;
+      __IO uint32_t             : 14;
+      __IO uint32_t  mode_mtime_bit :  1;
+      __IO uint32_t  mode_64_bit :  1;
+    } cfg_reg_lo_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t cfg_reg_hi;
+    struct {
+      __IO uint32_t  enable_bit :  1;
+      __IO uint32_t  reset_bit  :  1;
+      __IO uint32_t  irq_bit    :  1;
+      __IO uint32_t  iem_bit    :  1;
+      __IO uint32_t  cmp_clr_bit :  1;
+      __IO uint32_t  one_shot_bit :  1;
+      __IO uint32_t  prescaler_en_bit :  1;
+      __IO uint32_t  ref_clk_en_bit :  1;
+      __IO uint32_t  prescaler_count :  8;
+      __IO uint32_t             : 14;
+      __IO uint32_t  mode_mtime_bit :  1;
+      __IO uint32_t  mode_64_bit :  1;
+    } cfg_reg_hi_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t timer_val_lo;
+    struct {
+      __IO uint32_t  timer_val_lo : 32;
+    } timer_val_lo_b;
+  };
+
+  // Offset = 0x000c
+  union {
+    __IO uint32_t timer_val_hi;
+    struct {
+      __IO uint32_t  timer_val_hi : 32;
+    } timer_val_hi_b;
+  };
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t timer_cmp_lo;
+    struct {
+      __IO uint32_t  timer_cmp_lo : 32;
+    } timer_cmp_lo_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t timer_cmp_hi;
+    struct {
+      __IO uint32_t  timer_cmp_hi : 32;
+    } timer_cmp_hi_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t timer_start_lo;
+    struct {
+      __IO uint32_t  timer_start_lo :  1;
+    } timer_start_lo_b;
+  };
+
+  // Offset = 0x001c
+  union {
+    __IO uint32_t timer_start_hi;
+    struct {
+      __IO uint32_t  timer_start_hi :  1;
+    } timer_start_hi_b;
+  };
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t timer_reset_lo;
+    struct {
+      __IO uint32_t  timer_reset_lo :  1;
+    } timer_reset_lo_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t timer_reset_hi;
+    struct {
+      __IO uint32_t  timer_reset_hi :  1;
+    } timer_reset_hi_b;
+  };
+} ApbTimerUnit_t;
+
+
+#define REG_CFG_REG_LO                 0x000
+#define   REG_CFG_REG_LO_MODE_64_BIT_LSB           31
+#define   REG_CFG_REG_LO_MODE_64_BIT_MASK          0x1
+#define   REG_CFG_REG_LO_MODE_MTIME_BIT_LSB        30
+#define   REG_CFG_REG_LO_MODE_MTIME_BIT_MASK       0x1
+#define   REG_CFG_REG_LO_PRESCALER_COUNT_LSB       8
+#define   REG_CFG_REG_LO_PRESCALER_COUNT_MASK      0xff
+#define   REG_CFG_REG_LO_REF_CLK_EN_BIT_LSB        7
+#define   REG_CFG_REG_LO_REF_CLK_EN_BIT_MASK       0x1
+#define   REG_CFG_REG_LO_PRESCALER_EN_BIT_LSB      6
+#define   REG_CFG_REG_LO_PRESCALER_EN_BIT_MASK     0x1
+#define   REG_CFG_REG_LO_ONE_SHOT_BIT_LSB          5
+#define   REG_CFG_REG_LO_ONE_SHOT_BIT_MASK         0x1
+#define   REG_CFG_REG_LO_CMP_CLR_BIT_LSB           4
+#define   REG_CFG_REG_LO_CMP_CLR_BIT_MASK          0x1
+#define   REG_CFG_REG_LO_IEM_BIT_LSB               3
+#define   REG_CFG_REG_LO_IEM_BIT_MASK              0x1
+#define   REG_CFG_REG_LO_IRQ_BIT_LSB               2
+#define   REG_CFG_REG_LO_IRQ_BIT_MASK              0x1
+#define   REG_CFG_REG_LO_RESET_BIT_LSB             1
+#define   REG_CFG_REG_LO_RESET_BIT_MASK            0x1
+#define   REG_CFG_REG_LO_ENABLE_BIT_LSB            0
+#define   REG_CFG_REG_LO_ENABLE_BIT_MASK           0x1
+#define REG_CFG_REG_HI                 0x004
+#define   REG_CFG_REG_HI_MODE_64_BIT_LSB           31
+#define   REG_CFG_REG_HI_MODE_64_BIT_MASK          0x1
+#define   REG_CFG_REG_HI_MODE_MTIME_BIT_LSB        30
+#define   REG_CFG_REG_HI_MODE_MTIME_BIT_MASK       0x1
+#define   REG_CFG_REG_HI_PRESCALER_COUNT_LSB       8
+#define   REG_CFG_REG_HI_PRESCALER_COUNT_MASK      0xff
+#define   REG_CFG_REG_HI_REF_CLK_EN_BIT_LSB        7
+#define   REG_CFG_REG_HI_REF_CLK_EN_BIT_MASK       0x1
+#define   REG_CFG_REG_HI_PRESCALER_EN_BIT_LSB      6
+#define   REG_CFG_REG_HI_PRESCALER_EN_BIT_MASK     0x1
+#define   REG_CFG_REG_HI_ONE_SHOT_BIT_LSB          5
+#define   REG_CFG_REG_HI_ONE_SHOT_BIT_MASK         0x1
+#define   REG_CFG_REG_HI_CMP_CLR_BIT_LSB           4
+#define   REG_CFG_REG_HI_CMP_CLR_BIT_MASK          0x1
+#define   REG_CFG_REG_HI_IEM_BIT_LSB               3
+#define   REG_CFG_REG_HI_IEM_BIT_MASK              0x1
+#define   REG_CFG_REG_HI_IRQ_BIT_LSB               2
+#define   REG_CFG_REG_HI_IRQ_BIT_MASK              0x1
+#define   REG_CFG_REG_HI_RESET_BIT_LSB             1
+#define   REG_CFG_REG_HI_RESET_BIT_MASK            0x1
+#define   REG_CFG_REG_HI_ENABLE_BIT_LSB            0
+#define   REG_CFG_REG_HI_ENABLE_BIT_MASK           0x1
+#define REG_TIMER_VAL_LO               0x008
+#define   REG_TIMER_VAL_LO_TIMER_VAL_LO_LSB        0
+#define   REG_TIMER_VAL_LO_TIMER_VAL_LO_MASK       0xffffffff
+#define REG_TIMER_VAL_HI               0x00C
+#define   REG_TIMER_VAL_HI_TIMER_VAL_HI_LSB        0
+#define   REG_TIMER_VAL_HI_TIMER_VAL_HI_MASK       0xffffffff
+#define REG_TIMER_CMP_LO               0x010
+#define   REG_TIMER_CMP_LO_TIMER_CMP_LO_LSB        0
+#define   REG_TIMER_CMP_LO_TIMER_CMP_LO_MASK       0xffffffff
+#define REG_TIMER_CMP_HI               0x014
+#define   REG_TIMER_CMP_HI_TIMER_CMP_HI_LSB        0
+#define   REG_TIMER_CMP_HI_TIMER_CMP_HI_MASK       0xffffffff
+#define REG_TIMER_START_LO             0x018
+#define   REG_TIMER_START_LO_TIMER_START_LO_LSB    0
+#define   REG_TIMER_START_LO_TIMER_START_LO_MASK   0x1
+#define REG_TIMER_START_HI             0x01C
+#define   REG_TIMER_START_HI_TIMER_START_HI_LSB    0
+#define   REG_TIMER_START_HI_TIMER_START_HI_MASK   0x1
+#define REG_TIMER_RESET_LO             0x020
+#define   REG_TIMER_RESET_LO_TIMER_RESET_LO_LSB    0
+#define   REG_TIMER_RESET_LO_TIMER_RESET_LO_MASK   0x1
+#define REG_TIMER_RESET_HI             0x024
+#define   REG_TIMER_RESET_HI_TIMER_RESET_HI_LSB    0
+#define   REG_TIMER_RESET_HI_TIMER_RESET_HI_MASK   0x1
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __APB_TIMER_UNIT_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fc_event.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef HAL_INCLUDE_HAL_FC_EVENT_H_
+#define HAL_INCLUDE_HAL_FC_EVENT_H_
+
+#include "core-v-mcu-pmsis.h"
+
+/*!
+ * @addtogroup FC_EventHandler
+ * @{
+ */
+
+/*******************************************************************************
+ * Variables, macros, structures,... definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#define NB_SOC_EVENTS    ( SOC_EU_NB_FC_EVENTS )
+
+typedef void (*pi_fc_event_handler_t)(void* arg);
+
+void pi_fc_event_handler_init(uint32_t fc_event_irq);
+
+/*!
+ * @brief FC event handler.
+ *
+ * This function pops an event and executes the handler corresponding to the event.
+ */
+void fc_soc_event_handler(void);
+
+//void pi_fc_event_handler_set(uint32_t event_id, pi_fc_event_handler_t event_handler, SemaphoreHandle_t semaphoreHandle);//This function based on  freertos 
+
+void user_pi_fc_event_handler_set(uint32_t event_id,pi_fc_event_handler_t event_handler);
+
+void pi_fc_event_handler_clear(uint32_t event_id);
+
+void clear_fc_event_handler(uint32_t event_id);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+
+#endif /* HAL_INCLUDE_HAL_FC_EVENT_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fll.h

@@ -0,0 +1,240 @@
+/*
+ * Copyright (C) 2018 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_FLL_H_
+#define HAL_INCLUDE_HAL_FLL_H_
+
+
+#define FLL_STATUS_OFFSET        0x000
+#define FLL_CONF1_OFFSET         0x004
+#define FLL_CONF2_OFFSET         0x008
+#define FLL_INTEGRATOR_OFFSET    0x00C
+
+
+#define FLL_STATUS_MULT_FACTOR_BIT                 0
+#define FLL_STATUS_MULT_FACTOR_WIDTH               16
+#define FLL_STATUS_MULT_FACTOR_MASK                (0xFFFF)
+
+
+
+#define FLL_CONF1_MODE_BIT                       31
+#define FLL_CONF1_MODE_WIDTH                     1
+#define FLL_CONF1_MODE_MASK                      (0x80000000)
+
+#define FLL_CONF1_LOCK_BIT                       30
+#define FLL_CONF1_LOCK_WIDTH                     1
+#define FLL_CONF1_LOCK_MASK                      (0x40000000)
+
+#define FLL_CONF1_DIV_BIT                        26
+#define FLL_CONF1_DIV_WIDTH                      4
+#define FLL_CONF1_DIV_MASK                       (0x3C000000)
+
+#define FLL_CONF1_DCO_BIT                        16
+#define FLL_CONF1_DCO_WIDTH                      10
+#define FLL_CONF1_DCO_MASK                       (0x03FF0000)
+
+#define FLL_CONF1_MULT_FACTOR_BIT                0
+#define FLL_CONF1_MULT_FACTOR_WIDTH              16
+#define FLL_CONF1_MULT_FACTOR_MASK               (0xFFFF)
+
+#define FLL_CONF1_MODE_STANDALONE                0
+#define FLL_CONF1_MODE_NORMAL                    1
+
+
+
+#define FLL_CONF2_GAIN_BIT                       0
+#define FLL_CONF2_GAIN_WIDTH                     4
+#define FLL_CONF2_GAIN_MASK                      (0x0000000F)
+
+#define FLL_CONF2_DEASSERT_CYCLES_BIT            4
+#define FLL_CONF2_DEASSERT_CYCLES_WIDTH          6
+#define FLL_CONF2_DEASSERT_CYCLES_MASK           (0x000003F0)
+
+#define FLL_CONF2_ASSERT_CYCLES_BIT              10
+#define FLL_CONF2_ASSERT_CYCLES_WIDTH            6
+#define FLL_CONF2_ASSERT_CYCLES_MASK             (0x0000FC00)
+
+#define FLL_CONF2_TOLERANCE_BIT                  16
+#define FLL_CONF2_TOLERANCE_WIDTH                12
+#define FLL_CONF2_TOLERANCE_MASK                 (0x0FFF0000)
+
+#define FLL_CONF2_STA_CLOCK_BIT                  29
+#define FLL_CONF2_STA_CLOCK_WIDTH                1
+#define FLL_CONF2_STA_CLOCK_MASK                 (0x20000000)
+
+#define FLL_CONF2_OPEN_LOOP_BIT                  30
+#define FLL_CONF2_OPEN_LOOP_WIDTH                1
+#define FLL_CONF2_OPEN_LOOP_MASK                 (0x40000000)
+
+#define FLL_CONF2_DITHERING_BIT                  31
+#define FLL_CONF2_DITHERING_WIDTH                1
+#define FLL_CONF2_DITHERING_MASK                 (0x80000000)
+
+
+
+#define FLL_INTEGRATOR_INT_BIT                       16
+#define FLL_INTEGRATOR_INT_WIDTH                     10
+#define FLL_INTEGRATOR_INT_MASK                      (0x03FF0000)
+
+#define FLL_INTEGRATOR_FRACT_BIT                     6
+#define FLL_INTEGRATOR_FRACT_WIDTH                   10
+#define FLL_INTEGRATOR_FRACT_MASK                    (0x0000FFC0)
+
+
+
+#if !defined(LANGUAGE_ASSEMBLY) && !defined(_ASMLANGUAGE)
+
+typedef union {
+  struct {
+    unsigned int actual_mult_factor:16;  /* Fll current multiplication factor */
+    unsigned int reserved:16;
+  };
+  unsigned int raw;
+} fll_reg_status_t;
+
+typedef union {
+  struct {
+    unsigned int mult_factor:16;      /* Fll requested multiplication factor, reset: 0x5f5.
+                                         If RefClk=32768 and Div=2 Freq= 24.98 MHz */
+    unsigned int dco_input:10;        /* DCO input code for stand alone mode, reset: 0x121 */
+    unsigned int clock_out_divider:4; /* Fll clock output divider, reset: 0x1 e.g div 2 */
+    unsigned int output_lock_enable:1;/* Fll output gated by lock signal (active high), reset 1 */
+    unsigned int mode:1;              /* Fll mode. 0: stand alone (unlocked), 1: normal, reset 0 */
+  };
+  unsigned int raw;
+} fll_reg_conf1_t;
+
+typedef union {
+  struct {
+    unsigned int loop_gain:4;         /* Fll loop gain, reset: 0x9 */
+    unsigned int de_assert_cycles:6;  /* Normal mode: number of refclock unstable cycles till lock de-assert
+                                         Standalone mode: lower 6 bits of lock assert counter. Reset: 0x10 */
+    unsigned int assert_cycles:6;     /* Normal mode: number of refclock stable cycles till lock assert
+                                         Standalone mode: upper 6 bits of lock assert counter. Reset: 0x10 */
+    unsigned int lock_tolerance:12;   /* Lock tolerance: margin arounf the target mult factor where clock is
+                                         considered as stable. Reset: 0x200
+                                         With Fmax=250Mhw (Div=2^4), Fmin=32K (Div=2^15)
+                                         Tolerance: 32K*(512/16)=1.048MHz .. 512 Hz */
+    unsigned int pad:1;
+    unsigned int config_clock_sel:1;  /* Select ref clock when mode = standalone, 0:RefClock, 1: DcoOut. Reset:1 */
+    unsigned int open_loop:1;         /* When 1 clock operates in open loop when locked */
+    unsigned int dithering:1;         /* When 1 Dithering is enabled */
+  };
+  unsigned int raw;
+} fll_reg_conf2_t;
+
+typedef union {
+  struct {
+    unsigned int pad1:6;
+    unsigned int state_fract_part:10; /* Integrator state: fractional part (dithering input unit) */
+    unsigned int state_int_part:10;   /* Integratot state: integer part (DCO input bits) */
+    unsigned int pad2:6;
+  };
+  unsigned int raw;
+} fll_reg_integrator_t;
+
+#endif
+
+
+
+#define FLL_STATUS_MULT_FACTOR_GET(value)          ((((unsigned int)(value)) >> 0) & 0xFFFF)
+#define FLL_STATUS_MULT_FACTOR_SET(dst,src,factor) (__BITINSERT((dst),(src),16,0))
+#define FLL_STATUS_MULT_FACTOR(factor)             ((factor) << 16)
+
+
+#define FLL_CONF1_MODE_GET(value)                ((((unsigned int)(value)) >> 16) & 0x1)
+#define FLL_CONF1_MODE_SET(dst,src)              (__BITINSERT((dst),(src),1,31))
+#define FLL_CONF1_MODE(factor)                   ((factor) << 31)
+
+#define FLL_CONF1_LOCK_GET(value)                ((((unsigned int)(value)) >> 16) & 0x1)
+#define FLL_CONF1_LOCK_SET(dst,src)              (__BITINSERT((dst),(src),30,1))
+#define FLL_CONF1_LOCK(factor)                   ((factor) << 30)
+
+#define FLL_CONF1_DIV_GET(value)                 ((((unsigned int)(value)) >> 26) & 0xF)
+#define FLL_CONF1_DIV_SET(dst,src)               (__BITINSERT((dst),(src),26,4))
+#define FLL_CONF1_DIV(factor)                    ((factor) << 26)
+
+#define FLL_CONF1_DCO_GET(value)                 ((((unsigned int)(value)) >> 16) & 0x3FF)
+#define FLL_CONF1_DCO_SET(dst,src)               (__BITINSERT((dst),(src),16,10))
+#define FLL_CONF1_DCO(factor)                    ((factor) << 16)
+
+#define FLL_CONF1_MULT_FACTOR_GET(value)         ((((unsigned int)(value)) >> 0) &0xFFFF)
+#define FLL_CONF1_MULT_FACTOR_SET(dst,src)       (__BITINSERT((dst),(src),0,16))
+#define FLL_CONF1_MULT_FACTOR(factor)            ((factor) << 0)
+
+
+
+#define FLL_CONF2_GAIN_GET(value)                ((((unsigned int)(value)) >> 0) & 0xF)
+#define FLL_CONF2_GAIN_SET(dst,src)              (__BITINSERT((dst),(src),4,0))
+#define FLL_CONF2_GAIN(value)                    ((value) << 0)
+
+#define FLL_CONF2_ASSERT_CYCLES_GET(value)       ((((unsigned int)(value)) >> 4) & 0x3F)
+#define FLL_CONF2_ASSERT_CYCLES_SET(dst,src)     (__BITINSERT((dst),(src),6,4))
+#define FLL_CONF2_ASSERT_CYCLES(value)           ((value) << 4)
+
+#define FLL_CONF2_DEASSERT_CYCLES_GET(value)     ((((unsigned int)(value)) >> 10) & 0x3F)
+#define FLL_CONF2_DEASSERT_CYCLES_SET(dst,src)   (__BITINSERT((dst),(src),6,10))
+#define FLL_CONF2_DEASSERT_CYCLES(value)         ((value) << 10)
+
+#define FLL_CONF2_TOLERANCE_GET(value)           ((((unsigned int)(value)) >> 16) & 0xFFF)
+#define FLL_CONF2_TOLERANCE_SET(dst,src)         (__BITINSERT((dst),(src),12,16))
+#define FLL_CONF2_TOLERANCE(value)               ((value) << 16)
+
+#define FLL_CONF2_STA_CLOCK_GET(value)           ((((unsigned int)(value)) >> 29) & 0x1)
+#define FLL_CONF2_STA_CLOCK_SET(dst,src)         (__BITINSERT((dst),(src),1,29))
+#define FLL_CONF2_STA_CLOCK(value)               ((value) << 29)
+
+#define FLL_CONF2_OPEN_LOOP_GET(value)           ((((unsigned int)(value)) >> 30) & 0x1)
+#define FLL_CONF2_OPEN_LOOP_SET(dst,src)         (__BITINSERT((dst),(src),1,30))
+#define FLL_CONF2_OPEN_LOOP(value)               ((value) << 30)
+
+#define FLL_CONF2_DITHER_GET(value)              ((((unsigned int)(value)) >> 31) & 0x1)
+#define FLL_CONF2_DITHER_SET(dst,src)            (__BITINSERT((dst),(src),1,31))
+#define FLL_CONF2_DITHER(value)                  ((value) << 31)
+
+
+
+#define FLL_INTEGRATOR_FRACT_GET(value)          ((((unsigned int)(value)) >> 6) & 0x3FF)
+#define FLL_INTEGRATOR_FRACT_SET(dst,src)        (__BITINSERT((dst),(src),6,10))
+#define FLL_INTEGRATOR_FRACT(value)              ((value) << 6)
+
+#define FLL_INTEGRATOR_INT_GET(value)          ((((unsigned int)(value)) >> 16) & 0x3FF)
+#define FLL_INTEGRATOR_INT_SET(dst,src)        (__BITINSERT((dst),(src),16,10))
+#define FLL_INTEGRATOR_INT(value)              ((value) << 16)
+
+
+
+
+
+
+/* Maximum Log2(DCO Frequency) */
+#define FLL_LOG2_MAXDCO     29
+/* Maximum Log2(Clok Divider) */
+#define FLL_LOG2_MAXDIV     15
+/* Maximum Log2(Multiplier) */
+#define FLL_LOG2_MAXM       (FLL_LOG2_MAXDCO - ARCHI_REF_CLOCK_LOG2)
+
+
+/* TODO: doc */
+void pulp_fll_init(void);
+unsigned int __fll_init(int fll);
+unsigned int __rt_fll_set_freq(int fll, unsigned int frequency);
+
+
+#endif /* HAL_INCLUDE_HAL_FLL_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_fll_pi.h

@@ -0,0 +1,151 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef HAL_INCLUDE_HAL_FLL_PI_H_
+#define HAL_INCLUDE_HAL_FLL_PI_H_
+
+//#include "pmsis/targets/target.h"
+#include "core-v-mcu-target.h"
+
+/*!
+ * @addtogroup fll
+ * @{
+ */
+
+#define DCDC_OPER_POINTS    (4)
+
+#define DCDC_DEFAULT_NV     (1200)
+#define DCDC_DEFAULT_MV     (1200)
+#define DCDC_DEFAULT_LV     (1000)
+#define DCDC_DEFAULT_RET    (800)
+#define DCDC_RANGE          (5)
+#define DCDC_RANGE_MASK     (0x1F)
+#define DCDC_BASE_VALUE     (550)
+#define DCDC_STEP           (50)
+
+#define MAX_DCDC_VARIATION  ((int32_t) (0.1*32767))
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define    FLL_LV_MAX_FREQUENCY       150000000
+#define    FLL_NV_MAX_FREQUENCY       250000000
+#define    FLL_SOC_MIN_FREQUENCY      150000000
+#define    FLL_SOC_MAX_FREQUENCY      250000000
+#define    FLL_CLUSTER_MIN_FREQUENCY   87000000
+#define    FLL_CLUSTER_MAX_FREQUENCY  175000000
+
+#define    FLL_SOC_FV_SLOPE       ((FLL_SOC_MAX_FREQUENCY - FLL_SOC_MIN_FREQUENCY) / (DCDC_DEFAULT_NV - DCDC_DEFAULT_LV))
+#define    FLL_CLUSTER_FV_SLOPE   ((FLL_CLUSTER_MAX_FREQUENCY - FLL_CLUSTER_MIN_FREQUENCY) / (DCDC_DEFAULT_NV - DCDC_DEFAULT_LV))
+
+typedef enum _fll_type
+{
+    FLL_SOC     = 0,
+    FLL_PERI    = 1,
+    FLL_CLUSTER = 2
+} fll_type_t;
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief Initialize one FLL.
+ *
+ * @param which_fll       SoC's or Cluster's fll.
+ * @param ret_state       Retention state.
+ *
+ * @note .
+ */
+void pi_fll_init(fll_type_t which_fll, uint32_t ret_state);
+
+/*!
+ * @brief Deinitalize one FLL.
+ *
+ * @param which_fll       SoC's or Cluster's fll.
+ *
+ * @note .
+ */
+void pi_fll_deinit(fll_type_t which_fll);
+
+/*!
+ * @brief Clean all FLL configuration.
+ *
+ * @note .
+ */
+void pi_fll_clear();
+
+
+/*!
+ * @brief Set specific FLL to wanted frequency.
+ *
+ * @param which_fll       SoC's or Cluster's fll.
+ * @param frequency       The frequency value to set.
+ * @param check           Check frequency.
+ *
+ * @note .
+ * @return check result of frequency.
+ */
+int pi_fll_set_frequency(fll_type_t which_fll, uint32_t frequency, int check);
+
+/*!
+ * @brief Get specific FLL's frequency.
+ *
+ * @param which_fll       SoC's or Cluster's fll.
+ *
+ * @note .
+ * @return frequency value.
+ */
+int pi_fll_get_frequency(fll_type_t which_fll, uint8_t real);
+
+/*!
+ * @brief Calculate FC SOC domain's max frequency with certain voltage
+ *
+ * @param  voltage  Given voltage
+ *
+ * @return max frquency.
+ */
+static inline int pi_fll_soc_max_freq_at_V(int voltage)
+{
+    return (FLL_SOC_MIN_FREQUENCY + (voltage - DCDC_DEFAULT_LV) * FLL_SOC_FV_SLOPE);
+}
+
+/*!
+ * @brief Calculate cluster domain's max frequency with certain voltage
+ *
+ * @param  voltage  Given voltage
+ *
+ * @return max frquency.
+ */
+static inline int pi_fll_cluster_max_freq_at_V(int voltage)
+{
+    return (FLL_CLUSTER_MIN_FREQUENCY + (voltage - DCDC_DEFAULT_LV) * FLL_CLUSTER_FV_SLOPE);
+}
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+
+
+#endif /* HAL_INCLUDE_HAL_FLL_PI_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef HAL_INCLUDE_HAL_GPIO_H_
+#define HAL_INCLUDE_HAL_GPIO_H_
+
+typedef enum {
+	CLEAR,
+	SET,
+	TOGGLE
+}efpgaio_enum_typedef;
+
+typedef struct {
+	uint8_t		mode;
+	uint32_t	int_type;
+	uint8_t		in_val;
+	uint8_t		out_val;
+	uint32_t	int_en;
+	uint32_t	number;
+}gpio_hal_typedef;
+
+
+
+void hal_write_gpio(uint8_t gpio_num, uint8_t value);
+void hal_set_gpio(uint8_t gpio_num);
+void hal_clr_gpio(uint8_t gpio_num);
+void hal_toggle_gpio(uint8_t gpio_num);
+void hal_gpio_int_ack (uint8_t int_gpio_num);
+void hal_set_gpio_num(uint8_t gpio_num);
+void hal_read_gpio_status(gpio_hal_typedef *hgpio);
+void hal_read_gpio_status_raw(uint8_t gpio_num, uint32_t* register_value);
+void hal_set_gpio_mode(uint8_t gpio_num, uint8_t gpio_mode);
+void hal_set_gpio_interrupt(uint8_t gpio_num, uint8_t interrupt_type, uint8_t interrupt_enable);
+void hal_enable_gpio_interrupt(uint8_t gpio_num);
+void hal_disable_gpio_interrupt(uint8_t gpio_num);
+
+void hal_efpgaio_output(uint8_t gpio_num, efpgaio_enum_typedef value);
+void hal_efpgaio_outen(uint8_t gpio_num, efpgaio_enum_typedef value);
+void hal_efpgaio_event(uint8_t gpio_num);
+void hal_efpgaio_status(gpio_hal_typedef *efpgaio);
+
+#endif /* HAL_INCLUDE_HAL_GPIO_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio_periph.h

@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef HAL_INCLUDE_HAL_GPIO_PERIPH_H_
+#define HAL_INCLUDE_HAL_GPIO_PERIPH_H_
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** GPIO_Type Register Layout Typedef */
+typedef struct
+{
+	volatile uint32_t paddir; /**< GPIO pad direction configuration register. */
+	volatile uint32_t gpioen; /**< GPIO pad enable configuration register. */
+	volatile uint32_t padin; /**< GPIO pad input value register. */
+	volatile uint32_t padout; /**< GPIO pad output value register. */
+	volatile uint32_t padoutset; /**< GPIO pad output set register. */
+	volatile uint32_t padoutclr; /**< GPIO pad output clear register. */
+	volatile uint32_t inten; /**< GPIO pad interrupt enable configuration register. */
+	volatile uint32_t inttype[2]; /**< GPIO pad interrupt type bit 0 & 1 configuration register. */
+	volatile uint32_t intstatus; /**< GPIO pad interrupt status register. */
+	volatile uint32_t padcfg[4]; /**< GPIO pad pin configuration register : 0-7, 8-15, 16-23, 23-31. */
+} gpio_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name PADDIR */
+/* GPIO direction configuration bitfield:
+  - bit[i]=1'b0: Input mode for GPIO[i]
+  - bit[i]=1'b1: Output mode for GPIO[i] */
+#define GPIO_PADDIR_DIR_MASK                                         (0xffffffff)
+#define GPIO_PADDIR_DIR_SHIFT                                        (0)
+#define GPIO_PADDIR_DIR(val)                                         (((uint32_t)(((uint32_t)(val)) << GPIO_PADDIR_DIR_SHIFT)) & GPIO_PADDIR_DIR_MASK)
+
+
+/*! @name GPIOEN */
+/* GPIO clock enable configuration bitfield:
+  - bit[i]=1'b0: disable clock for GPIO[i]
+  - bit[i]=1'b1: enable clock for GPIO[i]
+  GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled.
+  Clock must be enabled for a GPIO if it's direction is configured in input mode. */
+#define GPIO_GPIOEN_GPIOEN_MASK                                      (0xffffffff)
+#define GPIO_GPIOEN_GPIOEN_SHIFT                                     (0)
+#define GPIO_GPIOEN_GPIOEN(val)                                      (((uint32_t)(((uint32_t)(val)) << GPIO_GPIOEN_GPIOEN_SHIFT)) & GPIO_GPIOEN_GPIOEN_MASK)
+
+
+/*! @name PADIN */
+/* GPIO input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. */
+#define GPIO_PADIN_DATA_IN_MASK                                      (0xffffffff)
+#define GPIO_PADIN_DATA_IN_SHIFT                                     (0)
+#define GPIO_PADIN_DATA_IN(val)                                      (((uint32_t)(((uint32_t)(val)) << GPIO_PADIN_DATA_IN_SHIFT)) & GPIO_PADIN_DATA_IN_MASK)
+
+
+/*! @name PADOUT */
+/* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */
+#define GPIO_PADOUT_DATA_OUT_MASK                                    (0xffffffff)
+#define GPIO_PADOUT_DATA_OUT_SHIFT                                   (0)
+#define GPIO_PADOUT_DATA_OUT(val)                                    (((uint32_t)(((uint32_t)(val)) << GPIO_PADOUT_DATA_OUT_SHIFT)) & GPIO_PADOUT_DATA_OUT_MASK)
+
+
+/*! @name PADOUTSET */
+/* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */
+#define GPIO_PADOUTSET_DATA_OUT_MASK                                    (0xffffffff)
+#define GPIO_PADOUTSET_DATA_OUT_SHIFT                                   (0)
+#define GPIO_PADOUTSET_DATA_OUT(val)                                    (((uint32_t)(((uint32_t)(val)) << GPIO_PADOUTSET_DATA_OUT_SHIFT)) & GPIO_PADOUTSET_DATA_OUT_MASK)
+
+
+/*! @name PADOUTCLEAR */
+/* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */
+#define GPIO_PADOUTCLR_DATA_OUT_MASK                                    (0xffffffff)
+#define GPIO_PADOUTCLR_DATA_OUT_SHIFT                                   (0)
+#define GPIO_PADOUTCLR_DATA_OUT(val)                                    (((uint32_t)(((uint32_t)(val)) << GPIO_PADOUTCLR_DATA_OUT_SHIFT)) & GPIO_PADOUTCLR_DATA_OUT_MASK)
+
+
+/*! @name INTEN */
+/* GPIO interrupt enable configuration bitfield:
+  - bit[i]=1'b0: disable interrupt for GPIO[i]
+  - bit[i]=1'b1: enable interrupt for GPIO[i] */
+#define GPIO_INTEN_INTEN_MASK                                        (0xffffffff)
+#define GPIO_INTEN_INTEN_SHIFT                                       (0)
+#define GPIO_INTEN_INTEN(val)                                        (((uint32_t)(((uint32_t)(val)) << GPIO_INTEN_INTEN_SHIFT)) & GPIO_INTEN_INTEN_MASK)
+
+
+/*! @name INTTYPE0 */
+/* GPIO[15:0] interrupt type configuration bitfield:
+  - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i]
+  - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i]
+  - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i]
+  - bit[2*i+1:2*i]=2'b11: RFU */
+#define GPIO_INTTYPE_INTTYPE_MASK                                    (0xffffffff)
+#define GPIO_INTTYPE_INTTYPE_SHIFT                                   (0)
+#define GPIO_INTTYPE_INTTYPE(val)                                    (((uint32_t)(((uint32_t)(val)) << GPIO_INTTYPE_INTTYPE_SHIFT)) & GPIO_INTTYPE_INTTYPE_MASK)
+
+
+/*! @name INTSTATUS */
+/* GPIO Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. */
+#define GPIO_INTSTATUS_INTSTATUS_MASK                                (0xffffffff)
+#define GPIO_INTSTATUS_INTSTATUS_SHIFT                               (0)
+#define GPIO_INTSTATUS_INTSTATUS(val)                                (((uint32_t)(((uint32_t)(val)) << GPIO_INTSTATUS_INTSTATUS_SHIFT)) & GPIO_INTSTATUS_INTSTATUS_MASK)
+
+
+/*! @name PADCFG */
+/* GPIO[i] pull activation configuration bitfield:
+  - 1'b0: pull disabled
+  - 1'b1: pull enabled */
+#define GPIO_PADCFG_GPIO_PE_MASK                                     (0x1)
+#define GPIO_PADCFG_GPIO_PE_SHIFT                                    (0)
+#define GPIO_PADCFG_GPIO_PE(val)                                     (((uint32_t)(((uint32_t)(val)) << GPIO_PADCFG_GPIO_PE_SHIFT)) & GPIO_PADCFG_GPIO_PE_MASK)
+
+
+/* GPIO[i] drive strength configuration bitfield:
+  - 1'b0: low drive strength
+  - 1'b1: high drive strength */
+#define GPIO_PADCFG_GPIO_DS_MASK                                     (0x2)
+#define GPIO_PADCFG_GPIO_DS_SHIFT                                    (1)
+#define GPIO_PADCFG_GPIO_DS(val)                                     (((uint32_t)(((uint32_t)(val)) << GPIO_PADCFG_GPIO_DS_SHIFT)) & GPIO_PADCFG_GPIO_DS_MASK)
+
+
+/*! @name PADDIR */
+typedef union
+{
+    struct
+    {
+	/* GPIO direction configuration bitfield:
+	- bit[i]=1'b0: Input mode for GPIO[i]
+	- bit[i]=1'b1: Output mode for GPIO[i] */
+	uint32_t dir:32;
+    } field;
+    uint32_t word;
+} gpio_paddir_t;
+
+/*! @name PADIN */
+typedef union
+{
+    struct
+    {
+	/* GPIO input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. */
+	uint32_t data_in:32;
+    } field;
+    uint32_t word;
+} gpio_padin_t;
+
+/*! @name PADOUT */
+typedef union
+{
+    struct
+    {
+	/* GPIO output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. */
+	uint32_t data_out:32;
+    } field;
+    uint32_t word;
+} gpio_padout_t;
+
+/*! @name INTEN */
+typedef union
+{
+    struct
+    {
+	/* GPIO interrupt enable configuration bitfield:
+	- bit[i]=1'b0: disable interrupt for GPIO[i]
+	- bit[i]=1'b1: enable interrupt for GPIO[i] */
+	uint32_t inten:32;
+    } field;
+    uint32_t word;
+} gpio_inten_t;
+
+/*! @name INTTYPE */
+typedef union
+{
+    struct
+    {
+	/* GPIO[15:0] interrupt type configuration bitfield:
+	- bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i]
+	- bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i]
+	- bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i]
+	- bit[2*i+1:2*i]=2'b11: RFU */
+	uint32_t inttype:32;
+    } field;
+    uint32_t word;
+} gpio_inttype0_t;
+
+/*! @name INTSTATUS */
+typedef union
+{
+    struct
+    {
+	/* GPIO Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. */
+	uint32_t intstatus:32;
+    } field;
+    uint32_t word;
+} gpio_intstatus_t;
+
+/*! @name GPIOEN */
+typedef union
+{
+    struct
+    {
+	/* GPIO clock enable configuration bitfield:
+	- bit[i]=1'b0: disable clock for GPIO[i]
+	- bit[i]=1'b1: enable clock for GPIO[i]
+	GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled.
+	Clock must be enabled for a GPIO if it's direction is configured in input mode. */
+	uint32_t gpioen:32;
+    } field;
+    uint32_t word;
+} gpio_gpioen_t;
+
+/*! @name PADCFG */
+typedef union
+{
+    struct
+    {
+	/* GPIO[0] pull activation configuration bitfield:
+	- 1'b0: pull disabled
+	- 1'b1: pull enabled */
+	uint32_t gpio0_pe:1;
+	/* GPIO[0] drive strength configuration bitfield:
+	- 1'b0: low drive strength
+	- 1'b1: high drive strength */
+	uint32_t gpio0_ds:1;
+	uint32_t reserved_0:6;
+	/* GPIO[1] pull activation configuration bitfield:
+	- 1'b0: pull disabled
+	- 1'b1: pull enabled */
+	uint32_t gpio1_pe:1;
+	/* GPIO[1] drive strength configuration bitfield:
+	- 1'b0: low drive strength
+	- 1'b1: high drive strength */
+	uint32_t gpio1_ds:1;
+	uint32_t reserved_1:6;
+	/* GPIO[2] pull activation configuration bitfield:
+	- 1'b0: pull disabled
+	- 1'b1: pull enabled */
+	uint32_t gpio2_pe:1;
+	/* GPIO[2] drive strength configuration bitfield:
+	- 1'b0: low drive strength
+	- 1'b1: high drive strength */
+	uint32_t gpio2_ds:1;
+	uint32_t reserved_2:6;
+	/* GPIO[3] pull activation configuration bitfield:
+	- 1'b0: pull disabled
+	- 1'b1: pull enabled */
+	uint32_t gpio3_pe:1;
+	/* GPIO[3] drive strength configuration bitfield:
+	- 1'b0: low drive strength
+	- 1'b1: high drive strength */
+	uint32_t gpio3_ds:1;
+    } field;
+    uint32_t word;
+} gpio_padcfg_t;
+
+
+/* ----------------------------------------------------------------------------
+
+ CMD IDs and macros
+
+----------------------------------------------------------------------------*/
+
+#endif /* HAL_INCLUDE_HAL_GPIO_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_gpio_pulp.h

@@ -0,0 +1,350 @@
+/*
+ * Copyright (C) 2020 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * Copyright (c) 2019-2020 Nordic Semiconductor ASA
+ * Copyright (c) 2019 Piotr Mienkowski
+ * Copyright (c) 2017 ARM Ltd
+ * Copyright (c) 2015-2016 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Driver to control and configure the PULP GPIO pins */
+/* Author: Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ *         Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#ifndef HAL_INCLUDE_HAL_GPIO_PULP_H_
+#define HAL_INCLUDE_HAL_GPIO_PULP_H_
+
+
+
+#include <stdint.h>
+#include <assert.h>
+
+#include "pulp_io.h"
+#include "hal_pinmux1.h"
+#include "core-v-mcu-pulp-mem-map.h"
+
+/* TODO: static assert on expected register sequence */
+//
+// REGISTERS
+//
+
+// GPIO pad direction configuration register.
+#define GPIO_PADDIR_OFFSET 0x0
+
+// GPIO enable register.
+#define GPIO_GPIOEN_OFFSET 0x4
+
+// GPIO pad input value register.
+#define GPIO_PADIN_OFFSET 0x8
+
+// GPIO pad output value register.
+#define GPIO_PADOUT_OFFSET 0xc
+
+// GPIO pad output set register.
+#define GPIO_PADOUTSET_OFFSET 0x10
+
+// GPIO pad output clear register.
+#define GPIO_PADOUTCLR_OFFSET 0x14
+
+// GPIO pad interrupt enable configuration register.
+#define GPIO_INTEN_OFFSET 0x18
+
+// GPIO pad interrupt type gpio 0 to 15 register.
+#define GPIO_INTTYPE0_OFFSET 0x1c
+
+// GPIO pad interrupt type gpio 16 to 31 register.
+#define GPIO_INTTYPE1_OFFSET 0x20
+
+// GPIO pad interrupt status register.
+#define GPIO_INTSTATUS_OFFSET 0x24
+
+// GPIO pad pin 0 to 7 configuration register.
+#define GPIO_PADCFG0_OFFSET 0x28
+
+// GPIO pad pin 8 to 15 configuration register.
+#define GPIO_PADCFG1_OFFSET 0x2c
+
+// GPIO pad pin 16 to 23 configuration register.
+#define GPIO_PADCFG2_OFFSET 0x30
+
+// GPIO pad pin 24 to 31 configuration register.
+#define GPIO_PADCFG3_OFFSET 0x34
+
+// GPIO pad direction configuration register.
+#define GPIO_PADDIR_32_63_OFFSET 0x38
+
+// GPIO enable register.
+#define GPIO_GPIOEN_32_63_OFFSET 0x3c
+
+// GPIO pad input value register.
+#define GPIO_PADIN_32_63_OFFSET 0x40
+
+// GPIO pad output value register.
+#define GPIO_PADOUT_32_63_OFFSET 0x44
+
+// GPIO pad output set register.
+#define GPIO_PADOUTSET_32_63_OFFSET 0x48
+
+// GPIO pad output clear register.
+#define GPIO_PADOUTCLR_32_63_OFFSET 0x4c
+
+// GPIO pad interrupt enable configuration register.
+#define GPIO_INTEN_32_63_OFFSET 0x50
+
+// GPIO pad interrupt type gpio 32 to 47 register.
+#define GPIO_INTTYPE_32_47_OFFSET 0x54
+
+// GPIO pad interrupt type gpio 48 to 63 register.
+#define GPIO_INTTYPE_48_63_OFFSET 0x58
+
+// GPIO pad interrupt status register.
+#define GPIO_INTSTATUS_32_63_OFFSET 0x5c
+
+// GPIO pad pin 32 to 39 configuration register.
+#define GPIO_PADCFG_32_39_OFFSET 0x60
+
+// GPIO pad pin 40 to 47 configuration register.
+#define GPIO_PADCFG_40_47_OFFSET 0x64
+
+// GPIO pad pin 48 to 55 configuration register.
+#define GPIO_PADCFG_48_55_OFFSET 0x68
+
+// GPIO pad pin 56 to 63 configuration register.
+#define GPIO_PADCFG_56_63_OFFSET 0x6c
+
+//
+// REGISTERS FIELDS
+//
+
+// GPIO[31:0] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W)
+#define GPIO_PADDIR_DIR_BIT   0
+#define GPIO_PADDIR_DIR_WIDTH 32
+#define GPIO_PADDIR_DIR_MASK  0xffffffff
+
+// GPIO[31:0] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled.  Clock must be enabled for a GPIO if it's direction is configured in input mode. (access: R/W)
+#define GPIO_GPIOEN_GPIOEN_BIT	 0
+#define GPIO_GPIOEN_GPIOEN_WIDTH 32
+#define GPIO_GPIOEN_GPIOEN_MASK	 0xffffffff
+
+// GPIO[31:0] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. (access: R)
+#define GPIO_PADIN_DATA_IN_BIT	 0
+#define GPIO_PADIN_DATA_IN_WIDTH 32
+#define GPIO_PADIN_DATA_IN_MASK	 0xffffffff
+
+// GPIO[31:0] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. (access: R/W)
+#define GPIO_PADOUT_DATA_OUT_BIT   0
+#define GPIO_PADOUT_DATA_OUT_WIDTH 32
+#define GPIO_PADOUT_DATA_OUT_MASK  0xffffffff
+
+// GPIO[31:0] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 (access: W)
+#define GPIO_PADOUTSET_DATA_SET_BIT   0
+#define GPIO_PADOUTSET_DATA_SET_WIDTH 32
+#define GPIO_PADOUTSET_DATA_SET_MASK  0xffffffff
+
+// GPIO[31:0] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] (access: W)
+#define GPIO_PADOUTCLR_DATA_CLEAR_BIT	0
+#define GPIO_PADOUTCLR_DATA_CLEAR_WIDTH 32
+#define GPIO_PADOUTCLR_DATA_CLEAR_MASK	0xffffffff
+
+// GPIO[31:0] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W)
+#define GPIO_INTEN_INTEN_BIT   0
+#define GPIO_INTEN_INTEN_WIDTH 32
+#define GPIO_INTEN_INTEN_MASK  0xffffffff
+
+// GPIO[15:0] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W)
+#define GPIO_INTTYPE0_INTTYPE0_BIT   0
+#define GPIO_INTTYPE0_INTTYPE0_WIDTH 32
+#define GPIO_INTTYPE0_INTTYPE0_MASK  0xffffffff
+
+// GPIO[31:16] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W)
+#define GPIO_INTTYPE1_INTTYPE1_BIT   0
+#define GPIO_INTTYPE1_INTTYPE1_WIDTH 32
+#define GPIO_INTTYPE1_INTTYPE1_MASK  0xffffffff
+
+// GPIO[31:0] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. (access: R)
+#define GPIO_INTSTATUS_INTSTATUS_BIT   0
+#define GPIO_INTSTATUS_INTSTATUS_WIDTH 32
+#define GPIO_INTSTATUS_INTSTATUS_MASK  0xffffffff
+
+// GPIO[0] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W)
+#define GPIO_PADCFG0_GPIO0_CFG_BIT   0
+#define GPIO_PADCFG0_GPIO0_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO0_CFG_MASK  0xf
+
+// GPIO[0] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W)
+#define GPIO_PADCFG0_GPIO1_CFG_BIT   4
+#define GPIO_PADCFG0_GPIO1_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO1_CFG_MASK  0xf0
+
+// GPIO[1] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W)
+#define GPIO_PADCFG0_GPIO2_CFG_BIT   8
+#define GPIO_PADCFG0_GPIO2_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO2_CFG_MASK  0xf00
+
+// GPIO[1] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W)
+#define GPIO_PADCFG0_GPIO3_CFG_BIT   12
+#define GPIO_PADCFG0_GPIO3_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO3_CFG_MASK  0xf000
+
+// GPIO[2] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W)
+#define GPIO_PADCFG0_GPIO4_CFG_BIT   16
+#define GPIO_PADCFG0_GPIO4_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO4_CFG_MASK  0xf0000
+
+// GPIO[2] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W)
+#define GPIO_PADCFG0_GPIO5_CFG_BIT   20
+#define GPIO_PADCFG0_GPIO5_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO5_CFG_MASK  0xf00000
+
+// GPIO[3] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W)
+#define GPIO_PADCFG0_GPIO6_CFG_BIT   24
+#define GPIO_PADCFG0_GPIO6_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO6_CFG_MASK  0xf000000
+
+// GPIO[3] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W)
+#define GPIO_PADCFG0_GPIO7_CFG_BIT   28
+#define GPIO_PADCFG0_GPIO7_CFG_WIDTH 4
+#define GPIO_PADCFG0_GPIO7_CFG_MASK  0xf0000000
+
+// GPIO[4] pull activation configuration bitfield: - 1'b0: pull disabled - 1'b1: pull enabled (access: R/W)
+#define GPIO_PADCFG1_GPIO4_PE_BIT   0
+#define GPIO_PADCFG1_GPIO4_PE_WIDTH 1
+#define GPIO_PADCFG1_GPIO4_PE_MASK  0x1
+
+// GPIO[4] drive strength configuration bitfield: - 1'b0: low drive strength - 1'b1: high drive strength (access: R/W)
+#define GPIO_PADCFG1_GPIO4_DS_BIT   1
+#define GPIO_PADCFG1_GPIO4_DS_WIDTH 1
+#define GPIO_PADCFG1_GPIO4_DS_MASK  0x2
+
+// GPIO[63:32] direction configuration bitfield: - bit[i]=1'b0: Input mode for GPIO[i] - bit[i]=1'b1: Output mode for GPIO[i] (access: R/W)
+#define GPIO_PADDIR_32_63_DIR_BIT   0
+#define GPIO_PADDIR_32_63_DIR_WIDTH 32
+#define GPIO_PADDIR_32_63_DIR_MASK  0xffffffff
+
+// GPIO[63:32] clock enable configuration bitfield: - bit[i]=1'b0: disable clock for GPIO[i] - bit[i]=1'b1: enable clock for GPIO[i] GPIOs are gathered by groups of 4. The clock gating of one group is done only if all 4 GPIOs are disabled.  Clock must be enabled for a GPIO if it's direction is configured in input mode. (access: R/W)
+#define GPIO_GPIOEN_32_63_GPIOEN_BIT   0
+#define GPIO_GPIOEN_32_63_GPIOEN_WIDTH 32
+#define GPIO_GPIOEN_32_63_GPIOEN_MASK  0xffffffff
+
+// GPIO[63:32] input data read bitfield. DATA_IN[i] corresponds to input data of GPIO[i]. (access: R)
+#define GPIO_PADIN_32_63_DATA_IN_BIT   0
+#define GPIO_PADIN_32_63_DATA_IN_WIDTH 32
+#define GPIO_PADIN_32_63_DATA_IN_MASK  0xffffffff
+
+// GPIO[63:32] output data read bitfield. DATA_OUT[i] corresponds to output data set on GPIO[i]. (access: R/W)
+#define GPIO_PADOUT_32_63_DATA_OUT_BIT	 0
+#define GPIO_PADOUT_32_63_DATA_OUT_WIDTH 32
+#define GPIO_PADOUT_32_63_DATA_OUT_MASK	 0xffffffff
+
+// GPIO[63:32] set bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Sets GPIO[i] to 1 (access: W)
+#define GPIO_PADOUTSET_32_63_DATA_SET_BIT   0
+#define GPIO_PADOUTSET_32_63_DATA_SET_WIDTH 32
+#define GPIO_PADOUTSET_32_63_DATA_SET_MASK  0xffffffff
+
+// GPIO[63:32] clear bitfield: - bit[i]=1'b0: No change for GPIO[i] - bit[i]=1'b1: Clears GPIO[i] (access: W)
+#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_BIT   0
+#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_WIDTH 32
+#define GPIO_PADOUTCLR_32_63_DATA_CLEAR_MASK  0xffffffff
+
+// GPIO[63:32] interrupt enable configuration bitfield: - bit[i]=1'b0: disable interrupt for GPIO[i] - bit[i]=1'b1: enable interrupt for GPIO[i] (access: R/W)
+#define GPIO_INTEN_32_63_INTEN_BIT   0
+#define GPIO_INTEN_32_63_INTEN_WIDTH 32
+#define GPIO_INTEN_32_63_INTEN_MASK  0xffffffff
+
+// GPIO[47:32] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W)
+#define GPIO_INTTYPE_32_47_INTTYPE0_BIT	  0
+#define GPIO_INTTYPE_32_47_INTTYPE0_WIDTH 32
+#define GPIO_INTTYPE_32_47_INTTYPE0_MASK  0xffffffff
+
+// GPIO[63:48] interrupt type configuration bitfield: - bit[2*i+1:2*i]=2'b00: interrupt on falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b01: interrupt on rising edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b10: interrupt on rising and falling edge for GPIO[16+i] - bit[2*i+1:2*i]=2'b11: RFU (access: R/W)
+#define GPIO_INTTYPE_48_63_INTTYPE1_BIT	  0
+#define GPIO_INTTYPE_48_63_INTTYPE1_WIDTH 32
+#define GPIO_INTTYPE_48_63_INTTYPE1_MASK  0xffffffff
+
+// GPIO[63:32] Interrupt status flags bitfield. INTSTATUS[i]=1 when interrupt received on GPIO[i]. INTSTATUS is cleared when it is red. GPIO interrupt line is also cleared when INTSTATUS register is red. (access: R)
+#define GPIO_INTSTATUS_32_63_INTSTATUS_BIT   0
+#define GPIO_INTSTATUS_32_63_INTSTATUS_WIDTH 32
+#define GPIO_INTSTATUS_32_63_INTSTATUS_MASK  0xffffffff
+
+/* required for gpio_pin_conf_pad() */
+static_assert((GPIO_PADCFG0_OFFSET + 0x4 == GPIO_PADCFG1_OFFSET) &&
+		      (GPIO_PADCFG1_OFFSET + 0x4 == GPIO_PADCFG2_OFFSET) &&
+		      (GPIO_PADCFG2_OFFSET + 0x4 == GPIO_PADCFG3_OFFSET),
+	      "GPIO_PADCFG*_OFFSET has unexpected addresses (spacing)");
+
+/* this API is from gpio.h of zephyr */
+
+/* this is custom */
+/** Enables internal pull */
+#define GPIO_PULL_ENABLE (1U << 1)
+
+/** Enables high drive strength */
+#define GPIO_DRIVE_STRENGTH_HIGH (1U << 1)
+
+/* this is zephyr */
+/** Enables pin as input. */
+#define GPIO_INPUT (1U << 8)
+
+/** Enables pin as output, no change to the output state. */
+#define GPIO_OUTPUT (1U << 9)
+
+/** Disables pin for both input and output. */
+#define GPIO_DISCONNECTED 0
+
+/** @cond INTERNAL_HIDDEN */
+
+/* Initializes output to a low state. */
+#define GPIO_OUTPUT_INIT_LOW (1U << 10)
+
+/* Initializes output to a high state. */
+#define GPIO_OUTPUT_INIT_HIGH (1U << 11)
+
+/* Initializes output based on logic level */
+#define GPIO_OUTPUT_INIT_LOGICAL (1U << 12)
+
+/** @endcond */
+
+/** Configures GPIO pin as output and initializes it to a low state. */
+#define GPIO_OUTPUT_LOW (GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW)
+/** Configures GPIO pin as output and initializes it to a high state. */
+#define GPIO_OUTPUT_HIGH (GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH)
+/** Configures GPIO pin as output and initializes it to a logic 0. */
+#define GPIO_OUTPUT_INACTIVE                                                   \
+	(GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_LOGICAL)
+/** Configures GPIO pin as output and initializes it to a logic 1. */
+#define GPIO_OUTPUT_ACTIVE                                                     \
+	(GPIO_OUTPUT | GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOGICAL)
+
+int gpio_pin_conf_pad(int pin, uint32_t flags);
+
+
+/* for now we only handle the gpio from 0-31 and ignore 32-63 */
+int gpio_pin_configure(int pin, uint32_t flags);
+int gpio_port_get_raw(uint32_t *value);
+int gpio_port_set_masked_raw(uint32_t mask, uint32_t value);
+int gpio_port_set_bits_raw(uint32_t mask);
+int gpio_port_clear_bits_raw(uint32_t mask);
+int gpio_port_toggle_bits(uint32_t mask);
+int gpio_pin_get_raw(int pin);
+int gpio_pin_set_raw(int pin, int value);
+int gpio_pin_toggle(int pin);
+
+
+#endif /* HAL_INCLUDE_HAL_GPIO_PULP_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_internal.h

@@ -0,0 +1,103 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef HAL_INCLUDE_HAL_I2C_INTERNAL_H_
+#define HAL_INCLUDE_HAL_I2C_INTERNAL_H_
+
+
+
+#include "core-v-mcu-pmsis.h"
+//#include "pmsis/task.h"
+#include "hal_i2c_pi.h"
+//#include "hal/include/hal_pmsis_hal.h"
+//#include "pmsis/implem/hal/hal_pmsis_hal.h"
+//#include "pmsis/implem/hal/hal.h"
+#include "hal_soc_eu_periph.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Max length of a i2c request/data buffer. */
+#define MAX_SIZE               (0xFF)
+/* Length of i2c cmd buffer. */
+#define __PI_I2C_CMD_BUFF_SIZE (16)
+/* Lenght of i2c stop command sequence. */
+#define __PI_I2C_STOP_CMD_SIZE (3)
+
+struct i2c_transfer_s
+{
+    uint8_t *buffer;
+    uint32_t size;
+    pi_i2c_xfer_flags_e flags;
+    int8_t device_id;
+    udma_channel_e channel;
+};
+
+struct i2c_pending_transfer_s
+{
+    uint32_t pending_buffer;
+    uint32_t pending_size;
+    uint32_t pending_repeat;
+    uint32_t pending_repeat_size;
+    pi_i2c_xfer_flags_e flags;
+    int8_t device_id;
+    udma_channel_e channel;
+};
+
+struct i2c_cb_args_s
+{
+    struct pi_task *cb;
+    struct i2c_transfer_s transfer;
+    struct i2c_cb_args_s *next;
+};
+
+struct i2c_driver_fifo_s
+{
+    /* Best to use only one queue since both RX & TX can be used at the same time. */
+    struct pi_task *hw_buffer[2];                 /* RX + TX */
+    struct i2c_cb_args_s *fifo_head;              /* Head of SW fifo waiting transfers. */
+    struct i2c_cb_args_s *fifo_tail;              /* Tail of SW fifo waiting transfers. */
+    struct i2c_pending_transfer_s *pending;       /* RX + TX. */
+    uint32_t cs;                                  /* Chip select i2c device. */
+    uint32_t max_baudrate;                        /* Max baudrate for the selected i2c chip. */
+    uint32_t div;                                 /* Clock divider for the selected i2c chip. */
+    uint32_t i2c_cmd_index;                       /* Number of commands in i2c_cmd_seq. */
+    uint8_t i2c_cmd_seq[__PI_I2C_CMD_BUFF_SIZE];  /* Command sequence. */
+    uint8_t i2c_stop_send;                        /* Set if a stop command sequence should be sent. */
+    uint8_t i2c_stop_seq[__PI_I2C_STOP_CMD_SIZE]; /* Command STOP sequence. */
+};
+
+/*******************************************************************************
+ * Driver data
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Function declaration
+ ******************************************************************************/
+
+/* Copy in UDMA. */
+void __pi_i2c_copy(struct i2c_driver_fifo_s *fifo, struct i2c_transfer_s *transfer, struct pi_task *task);
+
+/* Handler. */
+void i2c_handler(void *arg);
+
+/* Clock divider. */
+uint32_t __pi_i2c_get_clk_div(uint32_t baudrate);
+
+#endif /* HAL_INCLUDE_HAL_I2C_INTERNAL_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_periph.h

@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef HAL_INCLUDE_HAL_I2C_PERIPH_H_
+#define HAL_INCLUDE_HAL_I2C_PERIPH_H_
+
+#include "hal_udma_core_periph.h"
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** I2C_Type Register Layout Typedef */
+typedef struct i2c
+{
+	udma_channel_t rx; /**< UDMA RX channels struct. */
+	udma_channel_t tx; /**< UDMA RX channels struct. */
+	udma_channel_t cmd; /**< UDMA RX channels struct. */
+	volatile uint32_t status; /**< Status register. */
+	volatile uint32_t setup; /**< Configuration register. */
+} i2c_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name STATUS */
+/* I2C bus busy status flag:
+  - 1'b0: no transfer on-going
+  - 1'b1: transfer on-going */
+#define I2C_STATUS_BUSY_MASK                                         (0x1)
+#define I2C_STATUS_BUSY_SHIFT                                        (0)
+#define I2C_STATUS_BUSY(val)                                         (((uint32_t)(((uint32_t)(val)) << I2C_STATUS_BUSY_SHIFT)) & I2C_STATUS_BUSY_MASK)
+
+/* I2C arbitration lost status flag:
+  - 1'b0: no error
+  - 1'b1: arbitration lost error */
+#define I2C_STATUS_ARB_LOST_MASK                                     (0x2)
+#define I2C_STATUS_ARB_LOST_SHIFT                                    (1)
+#define I2C_STATUS_ARB_LOST(val)                                     (((uint32_t)(((uint32_t)(val)) << I2C_STATUS_ARB_LOST_SHIFT)) & I2C_STATUS_ARB_LOST_MASK)
+
+
+/*! @name SETUP */
+/* Reset command used to abort the on-going transfer and clear busy and arbitration lost status flags. */
+#define I2C_SETUP_DO_RST_MASK                                        (0x1)
+#define I2C_SETUP_DO_RST_SHIFT                                       (0)
+#define I2C_SETUP_DO_RST(val)                                        (((uint32_t)(((uint32_t)(val)) << I2C_SETUP_DO_RST_SHIFT)) & I2C_SETUP_DO_RST_MASK)
+
+
+/*! @name STATUS */
+typedef union
+{
+    struct
+    {
+        /* I2C bus busy status flag:
+        - 1'b0: no transfer on-going
+        - 1'b1: transfer on-going */
+        uint32_t busy:1;
+        /* I2C arbitration lost status flag:
+        - 1'b0: no error
+        - 1'b1: arbitration lost error */
+        uint32_t arb_lost:1;
+    } field;
+    uint32_t word;
+} i2c_status_t;
+
+/*! @name SETUP */
+typedef union
+{
+    struct
+    {
+        /* Reset command used to abort the on-going transfer and clear busy and arbitration lost status flags. */
+        uint32_t do_rst:1;
+    } field;
+    uint32_t word;
+} i2c_setup_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- CMD IDs and macros --
+   ---------------------------------------------------------------------------- */
+#define I2C_CMD_MASK     (0xF0U)
+#define I2C_CMD_SHIFT    (4U)
+
+#define I2C_CMD_START    (((uint32_t)(((uint32_t)(0x0)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x00
+#define I2C_CMD_WAIT_EV  (((uint32_t)(((uint32_t)(0x1)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x10
+#define I2C_CMD_STOP     (((uint32_t)(((uint32_t)(0x2)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x20
+#define I2C_CMD_RD_ACK   (((uint32_t)(((uint32_t)(0x4)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x40
+#define I2C_CMD_RD_NACK  (((uint32_t)(((uint32_t)(0x6)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x60
+#define I2C_CMD_WR       (((uint32_t)(((uint32_t)(0x8)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0x80
+#define I2C_CMD_WAIT     (((uint32_t)(((uint32_t)(0xA)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0xA0
+#define I2C_CMD_RPT      (((uint32_t)(((uint32_t)(0xC)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0xC0
+#define I2C_CMD_CFG      (((uint32_t)(((uint32_t)(0xE)) << I2C_CMD_SHIFT)) & I2C_CMD_MASK) // 0xE0
+
+#endif /* HAL_INCLUDE_HAL_I2C_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_i2c_pi.h

@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2018 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef HAL_INCLUDE_HAL_I2C_PI_H_
+#define HAL_INCLUDE_HAL_I2C_PI_H_
+
+
+
+//#include "pmsis/pmsis_types.h"
+#include "hal_pmsis_types.h"
+
+/**
+* @ingroup groupDrivers
+*/
+
+
+/**
+ * @defgroup I2C I2C
+ *
+ * The I2C driver provides support for transferring data between an external
+ * I2C device and the chip running this driver.
+ *
+ */
+
+/**
+ * @addtogroup I2C
+ * @{
+ */
+
+/**@{*/
+
+/// @cond IMPLEM
+
+#define __PI_I2C_CTRL_SET_MAX_BAUDRATE_BIT 0
+
+/// @endcond
+
+/** \struct pi_i2c_conf_t
+ * \brief I2C master configuration structure.
+ *
+ * This structure is used to pass the desired I2C configuration to the runtime
+ * when opening a device.
+ */
+typedef struct pi_i2c_conf
+{
+    pi_device_e device;  /* Device type. */
+    uint8_t itf;            /*!< Specifies on which I2C interface the device is
+      connected. */
+    int8_t cs;               /*!< i2c slave address (7 bits on MSB), the
+      runtime will take care of the LSB of read and write. */
+    int8_t is_slave;
+    uint16_t slave_addr;
+    uint16_t gap_slave_addr0;
+    uint16_t gap_slave_addr1;
+    uint32_t max_baudrate;   /*!< Maximum baudrate for the I2C bitstream which
+      can be used with the opened device . */
+} pi_i2c_conf_t;
+
+
+/** \enum pi_i2c_xfer_flags_e
+ * \brief Properties for I2C transfers
+ *
+ * This is used to specify additional behaviors when transfering data through
+ * I2C.
+ */
+typedef enum {
+  PI_I2C_XFER_STOP     = 0<<0,   /*!< Generate a STOP bit at the end of the
+    transfer. */
+  PI_I2C_XFER_NO_STOP  = 1<<0,   /*!< Don't generate a STOP bit at the end of
+    the transfer. */
+  PI_I2C_XFER_START    = 0<<1,    /*!< Generate a START bit at the beginning of
+    the transfer. */
+  PI_I2C_XFER_NO_START = 1<<1    /*!< Don't generate a START bit at the
+    beginning of the transfer. */
+} pi_i2c_xfer_flags_e;
+
+/** \enum pi_i2c_ioctl_e
+ * \brief Commands for pi_i2c_control.
+ *
+ * This is used to tell which command to execute through pi_i2c_control.
+ */
+typedef enum {
+  PI_I2C_CTRL_SET_MAX_BAUDRATE  = 1 << __PI_I2C_CTRL_SET_MAX_BAUDRATE_BIT, /*!<
+    Change maximum baudrate. */
+} pi_i2c_ioctl_e;
+
+/** \brief Initialize an I2C configuration with default values.
+ *
+ * This function can be called to get default values for all parameters before
+ * setting some of them. The structure containing the configuration must be
+ * kept alive until the I2C device is opened.
+ *
+ * \param conf A pointer to the I2C configuration.
+ */
+void pi_i2c_conf_init(pi_i2c_conf_t *conf);
+
+/** \brief Open an I2C device.
+ *
+ * This function must be called before the Hyperbus device can be used.
+ * It will do all the needed configuration to make it usable and initialize
+ * the handle used to refer to this opened device when calling other functions.
+ *
+ * \param device    A pointer to the device structure of the device to open.
+ *   This structure is allocated by the called and must be kept alive until the
+ *   device is closed.
+ * \return          0 if the operation is successfull, -1 if there was an error.
+ */
+int pi_i2c_open(struct pi_device *device);
+
+/** \brief Close an opened I2C device.
+ *
+ * This function can be called to close an opened I2C device once it is
+ * not needed anymore, in order to free all allocated resources. Once this
+ * function is called, the device is not accessible anymore and must be opened
+ * again before being used.
+ *
+ * \param device    The device structure of the device to close.
+ */
+void pi_i2c_close (struct pi_device *device);
+
+/** \brief Dynamically change the device configuration.
+ *
+ * This function can be called to change part of the device configuration after
+ * it has been opened.
+ *
+ * \param device  A pointer to the structure describing the device.
+ * \param cmd     The command which specifies which parameters of the driver to
+ * modify and for some of them also their values. The command must be one of
+ * those defined in pi_i2c_ioctl_e.
+ * \param arg       An additional value which is required for some parameters
+ * when they are set.
+ */
+void pi_i2c_ioctl(struct pi_device *device, uint32_t cmd, void *arg);
+
+/** \brief Enqueue a burst read copy from the I2C (from I2C device to chip).
+ *
+ * This function can be used to read at least 1 byte of data from the I2C
+ * device. The copy will make a synchronous transfer between the I2C and one of
+ * the chip memory.
+ * The caller is blocked until the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device  A pointer to the structure describing the device.
+ * \param rx_buff The address in the chip where the received data must be
+ *   written.
+ * \param length  The size in bytes of the copy.
+ * \param flags  Specify additional transfer behaviors like start and stop bits
+ *   management.
+ */
+void pi_i2c_read(struct pi_device *device, uint8_t *rx_buff, int length,
+  pi_i2c_xfer_flags_e flags);
+
+/** \brief Enqueue a burst write copy to the I2C (from chip to I2C device).
+ *
+ * This function can be used to write at least 1 byte of data to the I2C device.
+ * The copy will make a synchronous transfer between the I2C and one of the
+ * chip memory.
+ * The caller is blocked until the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device    A pointer to the structure describing the device.
+ * \param tx_data     The address in the chip where the data to be sent is read.
+ * \param length      The size in bytes of the copy.
+ * \param flags  Specify additional transfer behaviors like start and stop bits
+ *   management.
+ */
+void pi_i2c_write(struct pi_device *device, uint8_t *tx_data, int length,
+  pi_i2c_xfer_flags_e flags);
+
+/** \brief Enqueue an asynchronous burst read copy from the I2C (from I2C
+ * device to chip).
+ *
+ * This function can be used to read at least 1 byte of data from the I2C
+ * device.
+ * The copy will make an asynchronous transfer between the I2C and one of the
+ * chip memory.
+ * A task must be specified in order to specify how the caller should be
+ * notified when the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device  A pointer to the structure describing the device.
+ * \param rx_buff  The address in the chip where the received data must be
+ *   written.
+ * \param length   The size in bytes of the copy.
+ * \param flags  Specify additional transfer behaviors like start and stop
+ *   bits management.
+ * \param task        The task used to notify the end of transfer.
+   See the documentation of pi_task_t for more details.
+ */
+void pi_i2c_read_async(struct pi_device *device, uint8_t *rx_buff, int length,
+  pi_i2c_xfer_flags_e flags, pi_task_t *task);
+
+/** \brief Enqueue a burst write copy to the I2C (from chip to I2C device).
+ *
+ * This function can be used to write at least 1 byte of data to the I2C device.
+ * The copy will make an asynchronous transfer between the I2C and one of the
+ * chip memory.
+ * A task must be specified in order to specify how the caller should be
+ * notified when the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device    A pointer to the structure describing the device.
+ * \param tx_data   The address in the chip where the data to be sent is read.
+ * \param length    The size in bytes of the copy
+ * \param flags  Specify additional transfer behaviors like start and stop bits
+ *   management.
+ * \param task        The task used to notify the end of transfer.
+   See the documentation of pi_task_t for more details.
+ */
+void pi_i2c_write_async(struct pi_device *device, uint8_t *tx_data, int length,
+  pi_i2c_xfer_flags_e flags, pi_task_t *task);
+
+//!@}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_INCLUDE_HAL_I2C_PI_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_irq.h

@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Interrupt controller definitions */
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_IRQ_H_
+#define HAL_INCLUDE_HAL_IRQ_H_
+
+
+
+#include "bits.h"
+
+#define IRQ_REG_MASK_OFFSET	  0x000
+#define IRQ_REG_MASK_SET_OFFSET	  0x004
+#define IRQ_REG_MASK_CLEAR_OFFSET 0x008
+#define IRQ_REG_INT_OFFSET	  0x00C
+#define IRQ_REG_INT_SET_OFFSET	  0x010
+#define IRQ_REG_INT_CLEAR_OFFSET  0x014
+#define IRQ_REG_ACK_OFFSET	  0x018
+#define IRQ_REG_ACK_SET_OFFSET	  0x01C
+#define IRQ_REG_ACK_CLEAR_OFFSET  0x020
+#define IRQ_REG_FIFO_OFFSET	  0x024
+
+/* Interrupt line masks: these interrupts directly go to the core (after being
+ * serialized as reqest + id). We refer to these interrupts with the prefix IRQ.
+ * Events on the other we strictly use to refer to "interrupts/events" that are
+ * signaled through (muxed) EU SoC interrupts (IRQ_FC_EVT_SOC_EVT) and need
+ * additional handling by the user through the Event Unit.
+ */
+#define IRQ_FC_EVT_SW0	      BIT(0)
+#define IRQ_FC_EVT_SW1	      BIT(1)
+#define IRQ_FC_EVT_SW2	      BIT(2)
+#define IRQ_FC_EVT_SW3	      BIT(3)
+#define IRQ_FC_EVT_SW4	      BIT(4)
+#define IRQ_FC_EVT_SW5	      BIT(5)
+#define IRQ_FC_EVT_SW6	      BIT(6)
+#define IRQ_FC_EVT_SW7	      BIT(7)
+#define IRQ_FC_EVT_DMA_PE_EVT BIT(8)
+#define IRQ_FC_EVT_DMA_PE_IRQ BIT(9)
+#define IRQ_FC_EVT_TIMER0_LO  BIT(10)
+#define IRQ_FC_EVT_TIMER0_HI  BIT(11)
+#define IRQ_FC_EVT_PF	      BIT(12)
+#define IRQ_FC_EVT_CLK_REF    BIT(14)
+#define IRQ_FC_EVT_GPIO	      BIT(15)
+
+/* is not in PULPissimo */
+/*#define IRQ_FC_EVT_RTC		   16 */
+
+#define IRQ_FC_EVT_ADV_TIMER0 BIT(17)
+#define IRQ_FC_EVT_ADV_TIMER1 BIT(18)
+#define IRQ_FC_EVT_ADV_TIMER2 BIT(19)
+#define IRQ_FC_EVT_ADV_TIMER3 BIT(20)
+
+/* is not in PULPissimo */
+/* #define IRQ_FC_EVT_CLUSTER_NOT_BUSY 21 */
+/* #define IRQ_FC_EVT_CLUSTER_POK	   22 */
+/* #define IRQ_FC_EVT_CLUSTER_CG_OK	   23 */
+/* #define IRQ_FC_EVT_PICL_OK     24 */
+/* #define IRQ_FC_EVT_SCU_OK      25 */
+
+/*
+ * SoC event unit events: Many events get implicitely muxed into this interrupt.
+ * A user that gets such an interrupt has to check the event unit's registers to
+ * see what happened
+ */
+#define IRQ_FC_EVT_SOC_EVT BIT(26)
+/*
+ * Event queue error: If we don't process event unit events quickly enough
+ * internal fifos can overflow and we get this error interrupt
+ */
+#define IRQ_FC_EVT_QUIRQE_ERROR BIT(29)
+/* High priority peripheral events: these are hardcoded to directly go to the
+ * core using a dedicated interrupt line
+ */
+#define IRQ_FC_EVT_PERIPH0 BIT(30)
+#define IRQ_FC_EVT_PERIPH1 BIT(31)
+
+/* TODO: doc */
+void irq_mask(uint32_t mask);
+void irq_enable(uint32_t mask);
+void irq_disable(uint32_t mask);
+uint32_t irq_clint_disable();
+uint32_t irq_clint_enable();
+void pulp_irq_init();
+
+#endif /* HAL_INCLUDE_HAL_IRQ_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pinmux.h

@@ -0,0 +1,28 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+
+#ifndef HAL_INCLUDE_HAL_PINMUX_H_
+#define HAL_INCLUDE_HAL_PINMUX_H_
+
+void hal_setpullup(uint8_t io_num, uint8_t on);
+void hal_setpinmux(uint8_t io_num, uint8_t mux_sel);
+uint8_t hal_getpinmux(uint8_t io_num);
+
+#endif /* HAL_INCLUDE_HAL_PINMUX_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pinmux1.h

@@ -0,0 +1,47 @@
+#ifndef HAL_INCLUDE_HAL_PINMUX1_H_
+#define HAL_INCLUDE_HAL_PINMUX1_H_
+
+/*
+ * Copyright (C) 2020 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Driver to control and configure pad mux */
+
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch) */
+
+#include <stdint.h>
+
+#include "pulp_io.h"
+#include "hal_apb_soc.h"
+#include "core-v-mcu-pulp-mem-map.h"
+
+#define PINMUX_FUNC_A 0
+#define PINMUX_FUNC_B 1
+#define PINMUX_FUNC_C 2
+#define PINMUX_FUNC_D 3
+/* This doesn't exist on PULP */
+#define PINMUX_FUNC_E 4
+#define PINMUX_FUNC_F 5
+#define PINMUX_FUNC_G 6
+#define PINMUX_FUNC_H 7
+
+int pinmux_pin_set(int pin, uint32_t func);
+
+int pinmux_pin_get(int pin, uint32_t *func);
+
+
+#endif /* HAL_INCLUDE_HAL_PINMUX1_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_drivers-obs.h

@@ -0,0 +1,55 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_
+#define HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_
+
+/* PMSIS api includes. */
+/* Chips specifics. */
+//#include "pmsis/chips/gap8/perf.h"
+
+/* Drivers. */
+//#include "pmsis/drivers/cpi.h"
+//#include "pmsis/drivers/dmacpy.h"
+//#include "../../pmsis_api/include/pmsis/drivers/uart-orig.h"
+//#include "pmsis/drivers/gpio.h"
+//#include "pmsis/drivers/hyperbus.h"
+//#include "pmsis/drivers/i2c.h"
+//#include "pmsis/drivers/i2s.h"
+//#include "pmsis/drivers/pad.h"
+//#include "pmsis/drivers/perf.h"
+//#include "pmsis/drivers/pwm.h"
+//#include "pmsis/drivers/rtc.h"
+//#include "pmsis/drivers/spi.h"
+#include "hal_fc_event.h"
+#include "hal_fll_pi.h"
+//#include "pmsis/implem/drivers/perf/perf.h"
+//#include "pmsis/implem/drivers/pmu/pmu.h"
+//#include "pmsis/implem/drivers/pwm/pwm_internal.h"
+//#include "pmsis/implem/drivers/rtc/rtc_internal.h"
+//#include "pmsis/implem/drivers/timer/timer.h"
+//#include "pmsis/implem/drivers/udma/cpi/cpi_internal.h"
+//#include "pmsis/implem/drivers/udma/dmacpy/dmacpy_internal.h"
+//#include "pmsis/implem/drivers/udma/hyperbus/hyperbus_internal.h"
+#include "hal_i2c_internal.h"
+//#include "pmsis/implem/drivers/udma/i2s/i2s_internal.h"
+#include "hal_uart_internal.h"
+
+
+#endif /* HAL_INCLUDE_HAL_PMSIS_DRIVERS_OBS_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_hal.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file shall be used for verification purpose only. */
+
+#ifndef HAL_INCLUDE_HAL_PMSIS_HAL_H_
+#define HAL_INCLUDE_HAL_PMSIS_HAL_H_
+
+
+/* Hal includes. */
+
+/* Event unit. */
+//#include "event_unit/event_unit.h"
+
+/* Efuse */
+/* #include "efuse/pmsis_efuse.h" */
+
+/* GPIO. */
+#include "gpio/gpio.h"
+
+/* PWM */
+#include "pwm/pwm.h"
+#include "pwm/pwm_ctrl.h"
+
+/* RTC */
+/* #include "rtc/rtc.h" */
+
+/* Soc_ctrl. */
+#include "soc_ctrl/soc_ctrl_pad.h"
+
+/* Soc events generator. */
+#include "soc_eu/soc_eu.h"
+
+/* UDMA. */
+#include "udma/udma_core.h"
+/* #include "udma/udma_cpi.h" */
+#include "udma/udma_ctrl.h"
+/* #include "udma/udma_dmacpy.h" */
+/* #include "udma/udma_hyper.h" */
+#include "udma/udma_i2c.h"
+#include "udma/udma_i2s.h"
+#include "udma/udma_spim.h"
+#include "udma/udma_uart.h"
+
+/* Cluster. */
+/* DMA. */
+#include "dma/dma.h"
+
+#endif /* HAL_INCLUDE_HAL_PMSIS_HAL_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_types.h

@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2018 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef HAL_INCLUDE_HAL_PMSIS_TYPES_H_
+#define HAL_INCLUDE_HAL_PMSIS_TYPES_H_
+#include "inttypes.h"
+#include "sys/types.h"
+
+/**
+ * @defgroup groupDrivers Drivers
+ */
+
+
+/// @cond IMPLEM
+
+/**
+ * @ingroup PMSIS_OS
+ */
+
+/**
+ * @defgroup PMSISTypes PMSIS common types
+ */
+
+/**
+ * @addtogroup PMSISTypes
+ * @{
+ */
+
+/**@{*/
+
+struct pi_device;
+struct pmsis_event_kernel_wrap;
+
+// device type placed at the top of conf
+typedef enum {
+    PI_DEVICE_UNKWN_TYPE,
+    PI_DEVICE_CLUSTER_TYPE,
+    PI_DEVICE_HYPERBUS_TYPE,
+    PI_DEVICE_SPI_TYPE,
+    PI_DEVICE_CPI_TYPE,
+    PI_DEVICE_I2C_TYPE,
+    PI_DEVICE_GPIO_TYPE,
+    PI_DEVICE_PWM_TYPE
+} pi_device_e;
+
+typedef struct pi_task pi_task_t;
+
+typedef void (*callback_t)(void *arg);
+
+typedef struct spinlock {
+    int32_t *lock_ptr; // with test and set mask
+    int32_t *release_ptr; // standard pointer
+} spinlock_t;
+
+typedef struct pi_device_config {
+    const char *name; // to open, FIXME: device tree
+    // initialize the device struct (api+ init data) using init_conf
+    int (*init)(struct pi_device *device);
+    const void *init_conf;
+} pi_device_config_t;
+
+// device struct, it wont stay here
+typedef struct pi_device {
+    struct pi_device_api *api; // function pointers
+    void *config; // driver conf: might be filled either using device tree or manually
+    void *data; // driver data
+} pi_device_t;
+
+
+typedef uint32_t (*device_rw_func)(struct pi_device *device, uintptr_t size,
+        const void *addr, const void *buffer);
+
+typedef uint32_t (*device_ioctl_func)(struct pi_device *device,
+        uint32_t func_id,
+        void *arg);
+
+typedef uint32_t (*device_rw_func_async)(struct pi_device *device,
+        uintptr_t size, const void *addr, const void *buffer, pi_task_t *async);
+
+typedef uint32_t (*device_ioctl_func_async)(struct pi_device *device,
+        uint32_t func_id, void *arg, pi_task_t *async);
+
+typedef int (*open_func)(struct pi_device *device);
+typedef int (*close_func)(struct pi_device *device);
+
+typedef int (*open_func_async)(struct pi_device *device,
+        pi_task_t *async);
+typedef int (*close_func_async)(struct pi_device *device, pi_task_t *async);
+
+// pmsis device minimal api: used for basic inheritance
+typedef struct pi_device_api
+{
+    int (*open)(struct pi_device *device);
+    int (*close)(struct pi_device *device);
+    int (*open_async)(struct pi_device *device, pi_task_t *async);
+    int (*close_async)(struct pi_device *device, pi_task_t *async);
+    ssize_t (*read)(struct pi_device *device, uint32_t ext_addr,
+                    void *buffer, uint32_t size, pi_task_t *async);
+    ssize_t (*write)(struct pi_device *device, uint32_t ext_addr,
+                     const void *buffer, uint32_t size, pi_task_t *async);
+    int (*ioctl)(struct pi_device *device, uint32_t func_id, void *arg);
+    int (*ioctl_async)(struct pi_device *device, uint32_t func_id,
+                       void *arg, pi_task_t *async);
+    void *specific_api;
+} pi_device_api_t;
+
+#ifndef IMPLEM_MUTEX_OBJECT_TYPE
+#define IMPLEM_MUTEX_OBJECT_TYPE \
+    void* mutex_object;
+#endif
+
+/** Memory slab allocator */
+typedef struct pi_mem_slab pi_mem_slab_t;
+
+/** Task types **/
+typedef void (*__pmsis_mutex_func)(void *mutex_object);
+
+typedef struct pmsis_mutex {
+    IMPLEM_MUTEX_OBJECT_TYPE
+    __pmsis_mutex_func take;
+    __pmsis_mutex_func release;
+} pmsis_mutex_t, pi_mutex_t;
+
+
+#ifndef IMPLEM_SEM_OBJECT_TYPE
+#define IMPLEM_SEM_OBJECT_TYPE \
+    void* sem_object;
+#endif
+
+/** Task types **/
+typedef void (*__pi_sem_func)(void *sem_object);
+
+typedef struct pi_sem {
+    IMPLEM_SEM_OBJECT_TYPE
+    __pi_sem_func take;
+    __pi_sem_func give;
+} pi_sem_t;
+
+typedef struct pmsis_spinlock {
+    uint32_t lock;
+} pmsis_spinlock_t;
+
+struct pmsis_event_kernel_wrap {
+    void *__os_native_task;
+    void (*event_kernel_main)(struct pmsis_event_kernel_wrap*);
+    // real event kernel (might be just an api stub for pulpOS)
+    void *priv;
+};
+
+enum pi_task_id {
+    PI_TASK_CALLBACK_ID,
+    PI_TASK_NONE_ID,
+};
+
+
+/// @endcond
+
+#endif /* HAL_INCLUDE_HAL_PMSIS_TYPES_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pmsis_types_pi.h

@@ -0,0 +1,62 @@
+/*
+ * hal_pmsis_types.h
+ *
+ *  Created on: Feb 20, 2021
+ *      Author: qlblue
+ */
+
+#ifndef HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_
+#define HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_
+
+/*
+ * Copyright 2019 GreenWaves Technologies
+ * Copyright 2020 ETH Zurich
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __PMSIS_IMPLEM_PMSIS_TYPES_H__
+#define __PMSIS_IMPLEM_PMSIS_TYPES_H__
+
+//#include "pmsis/pmsis_types.h"
+#include "hal_pmsis_types.h"
+
+#ifndef PI_TASK_IMPLEM
+#define PI_TASK_IMPLEM \
+    int8_t destroy;
+#endif
+
+#ifndef PI_TASK_IMPLEM_NB_DATA
+#define PI_TASK_IMPLEM_NB_DATA 8
+#endif  /* PI_TASK_IMPLEM_NB_DATA */
+
+typedef struct pi_task
+{
+    // Warning, might be accessed inline in asm, and thus can not be moved
+    uintptr_t arg[4];
+    int32_t id;
+    uint32_t data[PI_TASK_IMPLEM_NB_DATA];
+    pi_sem_t wait_on;
+    struct pi_task *next;
+    volatile int8_t done;
+    int8_t core_id;
+    int8_t cluster_id;
+    PI_TASK_IMPLEM;
+} pi_task_t;
+
+#endif  /* __PMSIS_IMPLEM_PMSIS_TYPES_H__ */
+
+
+#endif /* HAL_INCLUDE_HAL_PMSIS_TYPES_PI_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pwm_ctrl_periph.h

@@ -0,0 +1,239 @@
+/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. */
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_
+#define HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_
+
+
+
+
+/* ----------------------------------------------------------------------------
+   -- PWM_CTRL Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** PWM_CTRL_Type Register Layout Typedef */
+typedef struct
+{
+    volatile uint32_t event_cfg; /**< ADV_TIMERS events configuration register. */
+    volatile uint32_t cg; /**< ADV_TIMERS channels clock gating configuration register. */
+} pwm_ctrl_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- PWM_CTRL Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name EVENT_CFG */
+/* ADV_TIMER output event 0 source configuration bitfiled:
+  - 4'h0: ADV_TIMER0 channel 0.
+  - 4'h1: ADV_TIMER0 channel 1.
+  - 4'h2: ADV_TIMER0 channel 2.
+  - 4'h3: ADV_TIMER0 channel 3.
+  - 4'h4: ADV_TIMER1 channel 0.
+  - 4'h5: ADV_TIMER1 channel 1.
+  - 4'h6: ADV_TIMER1 channel 2.
+  - 4'h7: ADV_TIMER1 channel 3.
+  - 4'h8: ADV_TIMER2 channel 0.
+  - 4'h9: ADV_TIMER2 channel 1.
+  - 4'hA: ADV_TIMER2 channel 2.
+  - 4'hB: ADV_TIMER2 channel 3.
+  - 4'hC: ADV_TIMER3 channel 0.
+  - 4'hD: ADV_TIMER3 channel 1.
+  - 4'hE: ADV_TIMER3 channel 2.
+  - 4'hF: ADV_TIMER3 channel 3. */
+#define PWM_CTRL_EVENT_CFG_SEL0_MASK                                 (0xf)
+#define PWM_CTRL_EVENT_CFG_SEL0_SHIFT                                (0)
+#define PWM_CTRL_EVENT_CFG_SEL0(val)                                 (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL0_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL0_MASK)
+
+/* ADV_TIMER output event 1 source configuration bitfiled:
+  - 4'h0: ADV_TIMER0 channel 0.
+  - 4'h1: ADV_TIMER0 channel 1.
+  - 4'h2: ADV_TIMER0 channel 2.
+  - 4'h3: ADV_TIMER0 channel 3.
+  - 4'h4: ADV_TIMER1 channel 0.
+  - 4'h5: ADV_TIMER1 channel 1.
+  - 4'h6: ADV_TIMER1 channel 2.
+  - 4'h7: ADV_TIMER1 channel 3.
+  - 4'h8: ADV_TIMER2 channel 0.
+  - 4'h9: ADV_TIMER2 channel 1.
+  - 4'hA: ADV_TIMER2 channel 2.
+  - 4'hB: ADV_TIMER2 channel 3.
+  - 4'hC: ADV_TIMER3 channel 0.
+  - 4'hD: ADV_TIMER3 channel 1.
+  - 4'hE: ADV_TIMER3 channel 2.
+  - 4'hF: ADV_TIMER3 channel 3. */
+#define PWM_CTRL_EVENT_CFG_SEL1_MASK                                 (0xf0)
+#define PWM_CTRL_EVENT_CFG_SEL1_SHIFT                                (4)
+#define PWM_CTRL_EVENT_CFG_SEL1(val)                                 (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL1_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL1_MASK)
+
+/* ADV_TIMER output event 2 source configuration bitfiled:
+  - 4'h0: ADV_TIMER0 channel 0.
+  - 4'h1: ADV_TIMER0 channel 1.
+  - 4'h2: ADV_TIMER0 channel 2.
+  - 4'h3: ADV_TIMER0 channel 3.
+  - 4'h4: ADV_TIMER1 channel 0.
+  - 4'h5: ADV_TIMER1 channel 1.
+  - 4'h6: ADV_TIMER1 channel 2.
+  - 4'h7: ADV_TIMER1 channel 3.
+  - 4'h8: ADV_TIMER2 channel 0.
+  - 4'h9: ADV_TIMER2 channel 1.
+  - 4'hA: ADV_TIMER2 channel 2.
+  - 4'hB: ADV_TIMER2 channel 3.
+  - 4'hC: ADV_TIMER3 channel 0.
+  - 4'hD: ADV_TIMER3 channel 1.
+  - 4'hE: ADV_TIMER3 channel 2.
+  - 4'hF: ADV_TIMER3 channel 3. */
+#define PWM_CTRL_EVENT_CFG_SEL2_MASK                                 (0xf00)
+#define PWM_CTRL_EVENT_CFG_SEL2_SHIFT                                (8)
+#define PWM_CTRL_EVENT_CFG_SEL2(val)                                 (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL2_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL2_MASK)
+
+/* ADV_TIMER output event 3 source configuration bitfiled:
+  - 4'h0: ADV_TIMER0 channel 0.
+  - 4'h1: ADV_TIMER0 channel 1.
+  - 4'h2: ADV_TIMER0 channel 2.
+  - 4'h3: ADV_TIMER0 channel 3.
+  - 4'h4: ADV_TIMER1 channel 0.
+  - 4'h5: ADV_TIMER1 channel 1.
+  - 4'h6: ADV_TIMER1 channel 2.
+  - 4'h7: ADV_TIMER1 channel 3.
+  - 4'h8: ADV_TIMER2 channel 0.
+  - 4'h9: ADV_TIMER2 channel 1.
+  - 4'hA: ADV_TIMER2 channel 2.
+  - 4'hB: ADV_TIMER2 channel 3.
+  - 4'hC: ADV_TIMER3 channel 0.
+  - 4'hD: ADV_TIMER3 channel 1.
+  - 4'hE: ADV_TIMER3 channel 2.
+  - 4'hF: ADV_TIMER3 channel 3. */
+#define PWM_CTRL_EVENT_CFG_SEL3_MASK                                 (0xf000)
+#define PWM_CTRL_EVENT_CFG_SEL3_SHIFT                                (12)
+#define PWM_CTRL_EVENT_CFG_SEL3(val)                                 (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_SEL3_SHIFT)) & PWM_CTRL_EVENT_CFG_SEL3_MASK)
+
+/* ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation. */
+#define PWM_CTRL_EVENT_CFG_ENA_MASK                                  (0xf0000)
+#define PWM_CTRL_EVENT_CFG_ENA_SHIFT                                 (16)
+#define PWM_CTRL_EVENT_CFG_ENA(val)                                  (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_EVENT_CFG_ENA_SHIFT)) & PWM_CTRL_EVENT_CFG_ENA_MASK)
+
+
+/*! @name CG */
+/* ADV_TIMER clock gating configuration bitfield.
+  - ENA[i]=0: clock gate ADV_TIMERi.
+  - ENA[i]=1: enable ADV_TIMERi.  */
+#define PWM_CTRL_CG_ENA_MASK                                         (0xffff)
+#define PWM_CTRL_CG_ENA_SHIFT                                        (0)
+#define PWM_CTRL_CG_ENA(val)                                         (((uint32_t)(((uint32_t)(val)) << PWM_CTRL_CG_ENA_SHIFT)) & PWM_CTRL_CG_ENA_MASK)
+
+
+/*! @name EVENT_CFG */
+typedef union
+{
+    struct
+    {
+        /* ADV_TIMER output event 0 source configuration bitfiled:
+        - 4'h0: ADV_TIMER0 channel 0.
+        - 4'h1: ADV_TIMER0 channel 1.
+        - 4'h2: ADV_TIMER0 channel 2.
+        - 4'h3: ADV_TIMER0 channel 3.
+        - 4'h4: ADV_TIMER1 channel 0.
+        - 4'h5: ADV_TIMER1 channel 1.
+        - 4'h6: ADV_TIMER1 channel 2.
+        - 4'h7: ADV_TIMER1 channel 3.
+        - 4'h8: ADV_TIMER2 channel 0.
+        - 4'h9: ADV_TIMER2 channel 1.
+        - 4'hA: ADV_TIMER2 channel 2.
+        - 4'hB: ADV_TIMER2 channel 3.
+        - 4'hC: ADV_TIMER3 channel 0.
+        - 4'hD: ADV_TIMER3 channel 1.
+        - 4'hE: ADV_TIMER3 channel 2.
+        - 4'hF: ADV_TIMER3 channel 3. */
+        uint32_t sel0:4;
+        /* ADV_TIMER output event 1 source configuration bitfiled:
+        - 4'h0: ADV_TIMER0 channel 0.
+        - 4'h1: ADV_TIMER0 channel 1.
+        - 4'h2: ADV_TIMER0 channel 2.
+        - 4'h3: ADV_TIMER0 channel 3.
+        - 4'h4: ADV_TIMER1 channel 0.
+        - 4'h5: ADV_TIMER1 channel 1.
+        - 4'h6: ADV_TIMER1 channel 2.
+        - 4'h7: ADV_TIMER1 channel 3.
+        - 4'h8: ADV_TIMER2 channel 0.
+        - 4'h9: ADV_TIMER2 channel 1.
+        - 4'hA: ADV_TIMER2 channel 2.
+        - 4'hB: ADV_TIMER2 channel 3.
+        - 4'hC: ADV_TIMER3 channel 0.
+        - 4'hD: ADV_TIMER3 channel 1.
+        - 4'hE: ADV_TIMER3 channel 2.
+        - 4'hF: ADV_TIMER3 channel 3. */
+        uint32_t sel1:4;
+        /* ADV_TIMER output event 2 source configuration bitfiled:
+        - 4'h0: ADV_TIMER0 channel 0.
+        - 4'h1: ADV_TIMER0 channel 1.
+        - 4'h2: ADV_TIMER0 channel 2.
+        - 4'h3: ADV_TIMER0 channel 3.
+        - 4'h4: ADV_TIMER1 channel 0.
+        - 4'h5: ADV_TIMER1 channel 1.
+        - 4'h6: ADV_TIMER1 channel 2.
+        - 4'h7: ADV_TIMER1 channel 3.
+        - 4'h8: ADV_TIMER2 channel 0.
+        - 4'h9: ADV_TIMER2 channel 1.
+        - 4'hA: ADV_TIMER2 channel 2.
+        - 4'hB: ADV_TIMER2 channel 3.
+        - 4'hC: ADV_TIMER3 channel 0.
+        - 4'hD: ADV_TIMER3 channel 1.
+        - 4'hE: ADV_TIMER3 channel 2.
+        - 4'hF: ADV_TIMER3 channel 3. */
+        uint32_t sel2:4;
+        /* ADV_TIMER output event 3 source configuration bitfiled:
+        - 4'h0: ADV_TIMER0 channel 0.
+        - 4'h1: ADV_TIMER0 channel 1.
+        - 4'h2: ADV_TIMER0 channel 2.
+        - 4'h3: ADV_TIMER0 channel 3.
+        - 4'h4: ADV_TIMER1 channel 0.
+        - 4'h5: ADV_TIMER1 channel 1.
+        - 4'h6: ADV_TIMER1 channel 2.
+        - 4'h7: ADV_TIMER1 channel 3.
+        - 4'h8: ADV_TIMER2 channel 0.
+        - 4'h9: ADV_TIMER2 channel 1.
+        - 4'hA: ADV_TIMER2 channel 2.
+        - 4'hB: ADV_TIMER2 channel 3.
+        - 4'hC: ADV_TIMER3 channel 0.
+        - 4'hD: ADV_TIMER3 channel 1.
+        - 4'hE: ADV_TIMER3 channel 2.
+        - 4'hF: ADV_TIMER3 channel 3. */
+        uint32_t sel3:4;
+        /* ADV_TIMER output event enable configuration bitfield. ENA[i]=1 enables output event i generation. */
+        uint32_t ena:4;
+    } field;
+    uint32_t word;
+} pwm_ctrl_event_cfg_t;
+
+/*! @name CG */
+typedef union
+{
+    struct
+    {
+        /* ADV_TIMER clock gating configuration bitfield.
+        - ENA[i]=0: clock gate ADV_TIMERi.
+        - ENA[i]=1: enable ADV_TIMERi.  */
+        uint32_t ena:16;
+    } field;
+    uint32_t word;
+} pwm_ctrl_cg_t;
+
+
+#endif /* HAL_INCLUDE_HAL_PWM_CTRL_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_pwm_periph.h

@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_PWM_PERIPH_H_
+#define HAL_INCLUDE_HAL_PWM_PERIPH_H_
+
+
+
+
+
+/* ----------------------------------------------------------------------------
+   -- PWM Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** PWM_Type Register Layout Typedef */
+typedef struct
+{
+    volatile uint32_t cmd;             /**< ADV_TIMER0 command register. */
+    volatile uint32_t config;          /**< ADV_TIMER0 configuration register. */
+    volatile uint32_t threshold;       /**< ADV_TIMER0 threshold configuration register. */
+    volatile uint32_t ch_threshold[4]; /**< ADV_TIMER0 channel threshold configuration register. */
+    volatile uint32_t ch_lut[4];       /**< ADV_TIMER0 channel LUT configuration register. */
+    volatile uint32_t counter;         /**< ADV_TIMER0 counter register. */
+} pwm_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- PWM Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name CMD */
+/* ADV_TIMER0 start command bitfield. */
+#define PWM_CMD_START_MASK                                           (0x1)
+#define PWM_CMD_START_SHIFT                                          (0)
+#define PWM_CMD_START(val)                                           (((uint32_t)(((uint32_t)(val)) << PWM_CMD_START_SHIFT)) & PWM_CMD_START_MASK)
+
+/* ADV_TIMER0 stop command bitfield. */
+#define PWM_CMD_STOP_MASK                                            (0x2)
+#define PWM_CMD_STOP_SHIFT                                           (1)
+#define PWM_CMD_STOP(val)                                            (((uint32_t)(((uint32_t)(val)) << PWM_CMD_STOP_SHIFT)) & PWM_CMD_STOP_MASK)
+
+/* ADV_TIMER0 update command bitfield. */
+#define PWM_CMD_UPDATE_MASK                                          (0x4)
+#define PWM_CMD_UPDATE_SHIFT                                         (2)
+#define PWM_CMD_UPDATE(val)                                          (((uint32_t)(((uint32_t)(val)) << PWM_CMD_UPDATE_SHIFT)) & PWM_CMD_UPDATE_MASK)
+
+/* ADV_TIMER0 reset command bitfield. */
+#define PWM_CMD_RESET_MASK                                           (0x8)
+#define PWM_CMD_RESET_SHIFT                                          (3)
+#define PWM_CMD_RESET(val)                                           (((uint32_t)(((uint32_t)(val)) << PWM_CMD_RESET_SHIFT)) & PWM_CMD_RESET_MASK)
+
+/* ADV_TIMER0 arm command bitfield. */
+#define PWM_CMD_ARM_MASK                                             (0x10)
+#define PWM_CMD_ARM_SHIFT                                            (4)
+#define PWM_CMD_ARM(val)                                             (((uint32_t)(((uint32_t)(val)) << PWM_CMD_ARM_SHIFT)) & PWM_CMD_ARM_MASK)
+
+
+/*! @name CONFIG */
+/* ADV_TIMER0 input source configuration bitfield:
+  - 0-31: GPIO[0] to GPIO[31]
+  - 32-35: Channel 0 to 3 of ADV_TIMER0
+  - 36-39: Channel 0 to 3 of ADV_TIMER1
+  - 40-43: Channel 0 to 3 of ADV_TIMER2
+  - 44-47: Channel 0 to 3 of ADV_TIMER3 */
+#define PWM_CONFIG_INSEL_MASK                                        (0xff)
+#define PWM_CONFIG_INSEL_SHIFT                                       (0)
+#define PWM_CONFIG_INSEL(val)                                        (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_INSEL_SHIFT)) & PWM_CONFIG_INSEL_MASK)
+
+/* ADV_TIMER0 trigger mode configuration bitfield:
+  - 3'h0: trigger event at each clock cycle.
+  - 3'h1: trigger event if input source is 0
+  - 3'h2: trigger event if input source is 1
+  - 3'h3: trigger event on input source rising edge
+  - 3'h4: trigger event on input source falling edge
+  - 3'h5: trigger event on input source falling or rising edge
+  - 3'h6: trigger event on input source rising edge when armed
+  - 3'h7: trigger event on input source falling edge when armed */
+#define PWM_CONFIG_MODE_MASK                                         (0x700)
+#define PWM_CONFIG_MODE_SHIFT                                        (8)
+#define PWM_CONFIG_MODE(val)                                         (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_MODE_SHIFT)) & PWM_CONFIG_MODE_MASK)
+
+/* ADV_TIMER0 clock source configuration bitfield:
+  - 1'b0: FLL
+  - 1'b1: reference clock at 32kHz */
+#define PWM_CONFIG_CLKSEL_MASK                                       (0x800)
+#define PWM_CONFIG_CLKSEL_SHIFT                                      (11)
+#define PWM_CONFIG_CLKSEL(val)                                       (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_CLKSEL_SHIFT)) & PWM_CONFIG_CLKSEL_MASK)
+
+/* ADV_TIMER0 center-aligned mode configuration bitfield:
+  - 1'b0: The counter counts up and down alternatively.
+  - 1'b1: The counter counts up and resets to 0 when reach threshold. */
+#define PWM_CONFIG_UPDOWNSEL_MASK                                    (0x1000)
+#define PWM_CONFIG_UPDOWNSEL_SHIFT                                   (12)
+#define PWM_CONFIG_UPDOWNSEL(val)                                    (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_UPDOWNSEL_SHIFT)) & PWM_CONFIG_UPDOWNSEL_MASK)
+
+/* ADV_TIMER0 prescaler value configuration bitfield. */
+#define PWM_CONFIG_PRESC_MASK                                        (0xff0000)
+#define PWM_CONFIG_PRESC_SHIFT                                       (16)
+#define PWM_CONFIG_PRESC(val)                                        (((uint32_t)(((uint32_t)(val)) << PWM_CONFIG_PRESC_SHIFT)) & PWM_CONFIG_PRESC_MASK)
+
+
+/*! @name THRESHOLD */
+/* ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. */
+#define PWM_THRESHOLD_TH_LO_MASK                                     (0xffff)
+#define PWM_THRESHOLD_TH_LO_SHIFT                                    (0)
+#define PWM_THRESHOLD_TH_LO(val)                                     (((uint32_t)(((uint32_t)(val)) << PWM_THRESHOLD_TH_LO_SHIFT)) & PWM_THRESHOLD_TH_LO_MASK)
+
+/* ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value. */
+#define PWM_THRESHOLD_TH_HI_MASK                                     (0xffff0000)
+#define PWM_THRESHOLD_TH_HI_SHIFT                                    (16)
+#define PWM_THRESHOLD_TH_HI(val)                                     (((uint32_t)(((uint32_t)(val)) << PWM_THRESHOLD_TH_HI_SHIFT)) & PWM_THRESHOLD_TH_HI_MASK)
+
+
+/*! @name CH_THRESHOLD */
+/* ADV_TIMER0 channel 0 threshold configuration bitfield. */
+#define PWM_CH_THRESHOLD_TH_MASK                                     (0xffff)
+#define PWM_CH_THRESHOLD_TH_SHIFT                                    (0)
+#define PWM_CH_THRESHOLD_TH(val)                                     (((uint32_t)(((uint32_t)(val)) << PWM_CH_THRESHOLD_TH_SHIFT)) & PWM_CH_THRESHOLD_TH_MASK)
+
+/* ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+  - 3'h0: set.
+  - 3'h1: toggle then next threshold match action is clear.
+  - 3'h2: set then next threshold match action is clear.
+  - 3'h3: toggle.
+  - 3'h4: clear.
+  - 3'h5: toggle then next threshold match action is set.
+  - 3'h6: clear then next threshold match action is set. */
+#define PWM_CH_THRESHOLD_MODE_MASK                                   (0x70000)
+#define PWM_CH_THRESHOLD_MODE_SHIFT                                  (16)
+#define PWM_CH_THRESHOLD_MODE(val)                                   (((uint32_t)(((uint32_t)(val)) << PWM_CH_THRESHOLD_MODE_SHIFT)) & PWM_CH_THRESHOLD_MODE_MASK)
+
+
+/*! @name CH_LUT */
+
+/*! @name COUNTER */
+
+/*! @name CMD */
+typedef union
+{
+    struct
+    {
+        /* ADV_TIMER0 start command bitfield. */
+        uint32_t start:1;
+        /* ADV_TIMER0 stop command bitfield. */
+        uint32_t stop:1;
+        /* ADV_TIMER0 update command bitfield. */
+        uint32_t update:1;
+        /* ADV_TIMER0 reset command bitfield. */
+        uint32_t reset:1;
+        /* ADV_TIMER0 arm command bitfield. */
+        uint32_t arm:1;
+    } field;
+    uint32_t word;
+} pwm_cmd_t;
+
+/*! @name CONFIG */
+typedef union
+{
+    struct
+    {
+        /* ADV_TIMER0 input source configuration bitfield:
+        - 0-31: GPIO[0] to GPIO[31]
+        - 32-35: Channel 0 to 3 of ADV_TIMER0
+        - 36-39: Channel 0 to 3 of ADV_TIMER1
+        - 40-43: Channel 0 to 3 of ADV_TIMER2
+        - 44-47: Channel 0 to 3 of ADV_TIMER3 */
+        uint32_t insel:8;
+        /* ADV_TIMER0 trigger mode configuration bitfield:
+        - 3'h0: trigger event at each clock cycle.
+        - 3'h1: trigger event if input source is 0
+        - 3'h2: trigger event if input source is 1
+        - 3'h3: trigger event on input source rising edge
+        - 3'h4: trigger event on input source falling edge
+        - 3'h5: trigger event on input source falling or rising edge
+        - 3'h6: trigger event on input source rising edge when armed
+        - 3'h7: trigger event on input source falling edge when armed */
+        uint32_t mode:3;
+        /* ADV_TIMER0 clock source configuration bitfield:
+        - 1'b0: FLL
+        - 1'b1: reference clock at 32kHz */
+        uint32_t clksel:1;
+        /* ADV_TIMER0 center-aligned mode configuration bitfield:
+        - 1'b0: The counter counts up and down alternatively.
+        - 1'b1: The counter counts up and resets to 0 when reach threshold. */
+        uint32_t updownsel:1;
+        uint32_t reserved_0:3;
+        /* ADV_TIMER0 prescaler value configuration bitfield. */
+        uint32_t presc:8;
+    } field;
+    uint32_t word;
+} pwm_config_t;
+
+/*! @name THRESHOLD */
+typedef union
+{
+    struct
+    {
+        /* ADV_TIMER0 threshold low part configuration bitfield. It defines start counter value. */
+        uint32_t th_lo:16;
+        /* ADV_TIMER0 threshold high part configuration bitfield. It defines end counter value. */
+        uint32_t th_hi:16;
+    } field;
+    uint32_t word;
+} pwm_threshold_t;
+
+/*! @name CH_THRESHOLD */
+typedef union
+{
+    struct
+    {
+        /* ADV_TIMER0 channel 0 threshold configuration bitfield. */
+        uint32_t th:16;
+        /* ADV_TIMER0 channel 0 threshold match action on channel output signal configuration bitfield:
+        - 3'h0: set.
+        - 3'h1: toggle then next threshold match action is clear.
+        - 3'h2: set then next threshold match action is clear.
+        - 3'h3: toggle.
+        - 3'h4: clear.
+        - 3'h5: toggle then next threshold match action is set.
+        - 3'h6: clear then next threshold match action is set. */
+        uint32_t mode:3;
+    } field;
+    uint32_t word;
+} pwm_ch_threshold_t;
+
+/*! @name CH_LUT */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} pwm_ch_lut_t;
+
+/*! @name COUNTER */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} pwm_counter_t;
+
+
+#endif /* HAL_INCLUDE_HAL_PWM_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_ctrl_periph.h

@@ -0,0 +1,1132 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_SOC_CTRL_PERIPH_H_
+#define HAL_INCLUDE_HAL_SOC_CTRL_PERIPH_H_
+
+
+
+/* ----------------------------------------------------------------------------
+   -- SOC_CTRL Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** SOC_CTRL_Type Register Layout Typedef */
+typedef struct
+{
+    volatile uint32_t info; /**< Core information register. */
+    volatile uint32_t _reserved_0[2]; /**< Reserved/Unused. */
+    volatile uint32_t cl_isolate; /**< Isolate cluster register. */
+    volatile uint32_t _reserved_1[23]; /**< Reserved/Unused. */
+    volatile uint32_t cl_busy; /**< Cluster busy register. */
+    volatile uint32_t cl_bypass; /**< Cluster PMU bypass configuration register. */
+    volatile uint32_t jtagreg; /**< JTAG external register. */
+    volatile uint32_t l2_sleep; /**< L2 sleep configuration register. */
+    volatile uint32_t sleep_ctrl; /**< Alias for SAFE_PMU_SLEEPCTRL. */
+    volatile uint32_t _reserved_2[8]; /**< Reserved/Unused. */
+    volatile uint32_t corestatus; /**< EOC and chip status register. */
+    volatile uint32_t _reserved_30[7]; /**< Reserved/Unused. */
+    volatile uint32_t corestatus_ro; /**< EOC and chip status register read mirror. */
+    volatile uint32_t _reserved_3[15]; /**< Reserved/Unused. */
+    volatile uint32_t safe_pmu_rar; /**< DC/DC configuration register. */
+    volatile uint32_t safe_pmu_sleepctrl; /**< Sleep modes configuration register. */
+    volatile uint32_t safe_pmu_force; /**< L2 rententive state configuration. */
+    volatile uint32_t _reserved_4[13]; /**< Reserved/Unused. */
+    volatile uint32_t safe_padfun[4]; /**< Mux config register : pad 0-15, 16-31, 32-47, 48-63. */
+    volatile uint32_t safe_sleeppadcfg[4]; /**< Sleep config register : pad 0-15, 16-31, 32-47, 48-63. */
+    volatile uint32_t safe_padsleep; /**< Enable Sleep mode for pads. */
+    volatile uint32_t _reserved_5[7]; /**< Reserved/Unused. */
+    volatile uint32_t safe_padcfg[16]; /**< Function register : pad 0-3, 4-7, 8-11,..., 56-59, 60-63. */
+    volatile uint32_t reg_gpio_iso; /**< GPIO power domain pad input isolation register. */
+    volatile uint32_t reg_cam_iso; /**< CAM power domain pad input isolation register. */
+    volatile uint32_t reg_lvds_iso; /**< LVDS power domain pad input isolation register. */
+} soc_ctrl_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- SOC_CTRL Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name INFO */
+/* Number of clusters */
+#define SOC_CTRL_INFO_NB_CL_MASK                                     (0xffff)
+#define SOC_CTRL_INFO_NB_CL_SHIFT                                    (0)
+#define SOC_CTRL_INFO_NB_CL(val)                                     (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_INFO_NB_CL_SHIFT)) & SOC_CTRL_INFO_NB_CL_MASK)
+
+/* Number of cores */
+#define SOC_CTRL_INFO_NB_CORES_MASK                                  (0xffff0000)
+#define SOC_CTRL_INFO_NB_CORES_SHIFT                                 (16)
+#define SOC_CTRL_INFO_NB_CORES(val)                                  (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_INFO_NB_CORES_SHIFT)) & SOC_CTRL_INFO_NB_CORES_MASK)
+
+
+/*! @name CL_ISOLATE */
+/* Isolate cluster. Inhibits AXI transactions from cluster to SoC:
+  - 1'b0:  Disable
+  - 1'b1: Enable */
+#define SOC_CTRL_CL_ISOLATE_EN_MASK                                  (0x1)
+#define SOC_CTRL_CL_ISOLATE_EN_SHIFT                                 (0)
+#define SOC_CTRL_CL_ISOLATE_EN(val)                                  (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_ISOLATE_EN_SHIFT)) & SOC_CTRL_CL_ISOLATE_EN_MASK)
+
+
+/*! @name CL_BUSY */
+/* Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) */
+#define SOC_CTRL_CL_BUSY_BUSY_MASK                                   (0x1)
+#define SOC_CTRL_CL_BUSY_BUSY_SHIFT                                  (0)
+#define SOC_CTRL_CL_BUSY_BUSY(val)                                   (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BUSY_BUSY_SHIFT)) & SOC_CTRL_CL_BUSY_BUSY_MASK)
+
+
+/*! @name CL_BYPASS */
+/* Bypass Maestro PMU controller configuration bitfield:
+  - 1’b0: disabled
+  - 1’b1: enabled */
+#define SOC_CTRL_CL_BYPASS_BYP_POW_MASK                              (0x1)
+#define SOC_CTRL_CL_BYPASS_BYP_POW_SHIFT                             (0)
+#define SOC_CTRL_CL_BYPASS_BYP_POW(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_BYP_POW_SHIFT)) & SOC_CTRL_CL_BYPASS_BYP_POW_MASK)
+
+/* Bypass Maestro PMU configuration selection configuration bitfield:
+  - 1’b0: use default
+  - 1’b1: use user configuration (bitfields from bits 3 to 15 of CL_BYPASS register) */
+#define SOC_CTRL_CL_BYPASS_BYP_CFG_MASK                              (0x2)
+#define SOC_CTRL_CL_BYPASS_BYP_CFG_SHIFT                             (1)
+#define SOC_CTRL_CL_BYPASS_BYP_CFG(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_BYP_CFG_SHIFT)) & SOC_CTRL_CL_BYPASS_BYP_CFG_MASK)
+
+/* Cluster state configuration and status bitfield:
+  - 1’b0: off
+  - 1’b1: on
+  Status information is correct only when bypass mode is enabled. */
+#define SOC_CTRL_CL_BYPASS_CL_STATE_MASK                             (0x8)
+#define SOC_CTRL_CL_BYPASS_CL_STATE_SHIFT                            (3)
+#define SOC_CTRL_CL_BYPASS_CL_STATE(val)                             (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_CL_STATE_SHIFT)) & SOC_CTRL_CL_BYPASS_CL_STATE_MASK)
+
+/* Max current allowed on cluster TRC configuration bitfield. */
+#define SOC_CTRL_CL_BYPASS_CURRSET_MASK                              (0x70)
+#define SOC_CTRL_CL_BYPASS_CURRSET_SHIFT                             (4)
+#define SOC_CTRL_CL_BYPASS_CURRSET(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_CURRSET_SHIFT)) & SOC_CTRL_CL_BYPASS_CURRSET_MASK)
+
+/* Number of REFCLK 32kHz after cluster power ok has arised to release TR isolation configuration bitfield. */
+#define SOC_CTRL_CL_BYPASS_PROG_DEL_MASK                             (0x180)
+#define SOC_CTRL_CL_BYPASS_PROG_DEL_SHIFT                            (7)
+#define SOC_CTRL_CL_BYPASS_PROG_DEL(val)                             (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_PROG_DEL_SHIFT)) & SOC_CTRL_CL_BYPASS_PROG_DEL_MASK)
+
+/* Bypass cluster clock and reset control by Maestro PMU configuration bitfield:
+  - 1’b0: disabled
+  - 1’b1: enabled */
+#define SOC_CTRL_CL_BYPASS_BYP_CLK_MASK                              (0x200)
+#define SOC_CTRL_CL_BYPASS_BYP_CLK_SHIFT                             (9)
+#define SOC_CTRL_CL_BYPASS_BYP_CLK(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_BYP_CLK_SHIFT)) & SOC_CTRL_CL_BYPASS_BYP_CLK_MASK)
+
+/* Cluster clock gate configuration bitfield:
+  - 1’b0: disabled
+  - 1’b1: enabled
+  It should always be used before switching cluster FLL to shutdown or retentive mode. */
+#define SOC_CTRL_CL_BYPASS_CG_MASK                                   (0x400)
+#define SOC_CTRL_CL_BYPASS_CG_SHIFT                                  (10)
+#define SOC_CTRL_CL_BYPASS_CG(val)                                   (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_CG_SHIFT)) & SOC_CTRL_CL_BYPASS_CG_MASK)
+#define READ_SOC_CTRL_CL_BYPASS_CG(val)                              (((uint32_t)(((uint32_t)(val)) & SOC_CTRL_CL_BYPASS_CG_MASK)) >> SOC_CTRL_CL_BYPASS_CG_SHIFT)
+
+/* Cluster FLL shutdown configuration bitfield:
+  - 1’b0: FLL on
+  - 1’b1: FLL shutdown mode */
+#define SOC_CTRL_CL_BYPASS_FLL_PWD_MASK                              (0x800)
+#define SOC_CTRL_CL_BYPASS_FLL_PWD_SHIFT                             (11)
+#define SOC_CTRL_CL_BYPASS_FLL_PWD(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_FLL_PWD_SHIFT)) & SOC_CTRL_CL_BYPASS_FLL_PWD_MASK)
+
+/* Cluster FLL retentive configuration bitfield:
+  - 1’b0: FLL on
+  - 1’b1: FLL retentive mode */
+#define SOC_CTRL_CL_BYPASS_FLL_RET_MASK                              (0x1000)
+#define SOC_CTRL_CL_BYPASS_FLL_RET_SHIFT                             (12)
+#define SOC_CTRL_CL_BYPASS_FLL_RET(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_FLL_RET_SHIFT)) & SOC_CTRL_CL_BYPASS_FLL_RET_MASK)
+
+/* Cluster reset configuration bitfield:
+  - 1’b0: nothing
+  - 1’b1: reset the cluster */
+#define SOC_CTRL_CL_BYPASS_RST_MASK                                  (0x2000)
+#define SOC_CTRL_CL_BYPASS_RST_SHIFT                                 (13)
+#define SOC_CTRL_CL_BYPASS_RST(val)                                  (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_RST_SHIFT)) & SOC_CTRL_CL_BYPASS_RST_MASK)
+
+/* ? */
+#define SOC_CTRL_CL_BYPASS_BYP_ISO_MASK                              (0x4000)
+#define SOC_CTRL_CL_BYPASS_BYP_ISO_SHIFT                             (14)
+#define SOC_CTRL_CL_BYPASS_BYP_ISO(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_BYP_ISO_SHIFT)) & SOC_CTRL_CL_BYPASS_BYP_ISO_MASK)
+
+/* ? */
+#define SOC_CTRL_CL_BYPASS_PWISO_MASK                                (0x8000)
+#define SOC_CTRL_CL_BYPASS_PWISO_SHIFT                               (15)
+#define SOC_CTRL_CL_BYPASS_PWISO(val)                                (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_PWISO_SHIFT)) & SOC_CTRL_CL_BYPASS_PWISO_MASK)
+#define READ_SOC_CTRL_CL_BYPASS_PWISO(val)                           (((uint32_t)(((uint32_t)(val)) & SOC_CTRL_CL_BYPASS_PWISO_MASK)) >> SOC_CTRL_CL_BYPASS_PWISO_SHIFT)
+
+/* Cluster power ok from cluster TRC status bitfield */
+#define SOC_CTRL_CL_BYPASS_TRCPOWOK_MASK                             (0x10000)
+#define SOC_CTRL_CL_BYPASS_TRCPOWOK_SHIFT                            (16)
+#define SOC_CTRL_CL_BYPASS_TRCPOWOK(val)                             (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_TRCPOWOK_SHIFT)) & SOC_CTRL_CL_BYPASS_TRCPOWOK_MASK)
+
+/* Cluster power down from Maestro PMU status bitfield. */
+#define SOC_CTRL_CL_BYPASS_PMUPOWDOWN_MASK                           (0x20000)
+#define SOC_CTRL_CL_BYPASS_PMUPOWDOWN_SHIFT                          (17)
+#define SOC_CTRL_CL_BYPASS_PMUPOWDOWN(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CL_BYPASS_PMUPOWDOWN_SHIFT)) & SOC_CTRL_CL_BYPASS_PMUPOWDOWN_MASK)
+
+
+/*! @name JTAGREG */
+/* JTAG internal register used for synchronisation from external debugger */
+#define SOC_CTRL_JTAGREG_INT_SYNC_MASK                               (0x1)
+#define SOC_CTRL_JTAGREG_INT_SYNC_SHIFT                              (0)
+#define SOC_CTRL_JTAGREG_INT_SYNC(val)                               (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_JTAGREG_INT_SYNC_SHIFT)) & SOC_CTRL_JTAGREG_INT_SYNC_MASK)
+#define READ_SOC_CTRL_JTAGREG_INT_SYNC(val)                          (((uint32_t)(((uint32_t)(val)) & SOC_CTRL_JTAGREG_INT_SYNC_MASK)) >> SOC_CTRL_JTAGREG_INT_SYNC_SHIFT)
+
+/* JTAG internal register used for selecting boot mode configuration from external debugger */
+#define SOC_CTRL_JTAGREG_INT_BT_MD_MASK                              (0xe)
+#define SOC_CTRL_JTAGREG_INT_BT_MD_SHIFT                             (1)
+#define SOC_CTRL_JTAGREG_INT_BT_MD(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_JTAGREG_INT_BT_MD_SHIFT)) & SOC_CTRL_JTAGREG_INT_BT_MD_MASK)
+#define READ_SOC_CTRL_JTAGREG_INT_BT_MD(val)                         (((uint32_t)(((uint32_t)(val)) & SOC_CTRL_JTAGREG_INT_BT_MD_MASK)) >> SOC_CTRL_JTAGREG_INT_BT_MD_SHIFT)
+
+/* JTAG external register used for synchronisation from external debugger */
+#define SOC_CTRL_JTAGREG_EXT_SYNC_MASK                               (0x100)
+#define SOC_CTRL_JTAGREG_EXT_SYNC_SHIFT                              (8)
+#define SOC_CTRL_JTAGREG_EXT_SYNC(val)                               (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_JTAGREG_EXT_SYNC_SHIFT)) & SOC_CTRL_JTAGREG_EXT_SYNC_MASK)
+#define READ_SOC_CTRL_JTAGREG_EXT_SYNC(val)                          (((uint32_t)(((uint32_t)(val)) & SOC_CTRL_JTAGREG_EXT_SYNC_MASK)) >> SOC_CTRL_JTAGREG_EXT_SYNC_SHIFT)
+
+/* JTAG external register used for selecting boot mode configuration from external debugger */
+#define SOC_CTRL_JTAGREG_EXT_BT_MD_MASK                              (0xe00)
+#define SOC_CTRL_JTAGREG_EXT_BT_MD_SHIFT                             (9)
+#define SOC_CTRL_JTAGREG_EXT_BT_MD(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_JTAGREG_EXT_BT_MD_SHIFT)) & SOC_CTRL_JTAGREG_EXT_BT_MD_MASK)
+#define READ_SOC_CTRL_JTAGREG_EXT_BT_MD(val)                         (((uint32_t)(((uint32_t)(val)) & SOC_CTRL_JTAGREG_EXT_BT_MD_MASK)) >> SOC_CTRL_JTAGREG_EXT_BT_MD_SHIFT)
+
+
+/*! @name L2_SLEEP */
+/* L2 memory sleep configuration */
+#define SOC_CTRL_L2_SLEEP_L2_SLEEP_MASK                              (0x1)
+#define SOC_CTRL_L2_SLEEP_L2_SLEEP_SHIFT                             (0)
+#define SOC_CTRL_L2_SLEEP_L2_SLEEP(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_L2_SLEEP_L2_SLEEP_SHIFT)) & SOC_CTRL_L2_SLEEP_L2_SLEEP_MASK)
+
+
+/*! @name SLEEP_CTRL */
+/* Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) */
+#define SOC_CTRL_SLEEP_CTRL_SLEEP_CTRL_MASK                          (0xffffffff)
+#define SOC_CTRL_SLEEP_CTRL_SLEEP_CTRL_SHIFT                         (0)
+#define SOC_CTRL_SLEEP_CTRL_SLEEP_CTRL(val)                          (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SLEEP_CTRL_SLEEP_CTRL_SHIFT)) & SOC_CTRL_SLEEP_CTRL_SLEEP_CTRL_MASK)
+
+
+/*! @name CORESTATUS */
+/* EOC and chip status register */
+#define SOC_CTRL_CORESTATUS_STATUS_MASK                              (0xffffffff)
+#define SOC_CTRL_CORESTATUS_STATUS_SHIFT                             (0)
+#define SOC_CTRL_CORESTATUS_STATUS(val)                              (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CORESTATUS_STATUS_SHIFT)) & SOC_CTRL_CORESTATUS_STATUS_MASK)
+
+
+/*! @name CORESTATUS_RO */
+/* EOC and chip status register */
+#define SOC_CTRL_CORESTATUS_RO_STATUS_MASK                           (0xffffffff)
+#define SOC_CTRL_CORESTATUS_RO_STATUS_SHIFT                          (0)
+#define SOC_CTRL_CORESTATUS_RO_STATUS(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_CORESTATUS_RO_STATUS_SHIFT)) & SOC_CTRL_CORESTATUS_RO_STATUS_MASK)
+
+
+/*! @name SAFE_PMU_RAR */
+/* DC/DC Nominal Voltage setting */
+#define SOC_CTRL_SAFE_PMU_RAR_NV_VOLT_MASK                           (0x1f)
+#define SOC_CTRL_SAFE_PMU_RAR_NV_VOLT_SHIFT                          (0)
+#define SOC_CTRL_SAFE_PMU_RAR_NV_VOLT(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_RAR_NV_VOLT_SHIFT)) & SOC_CTRL_SAFE_PMU_RAR_NV_VOLT_MASK)
+
+/* DC/DC Medium Voltage setting (not used) */
+#define SOC_CTRL_SAFE_PMU_RAR_MV_VOLT_MASK                           (0x1f00)
+#define SOC_CTRL_SAFE_PMU_RAR_MV_VOLT_SHIFT                          (8)
+#define SOC_CTRL_SAFE_PMU_RAR_MV_VOLT(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_RAR_MV_VOLT_SHIFT)) & SOC_CTRL_SAFE_PMU_RAR_MV_VOLT_MASK)
+
+/* DC/DC Low Voltage setting */
+#define SOC_CTRL_SAFE_PMU_RAR_LV_VOLT_MASK                           (0x1f0000)
+#define SOC_CTRL_SAFE_PMU_RAR_LV_VOLT_SHIFT                          (16)
+#define SOC_CTRL_SAFE_PMU_RAR_LV_VOLT(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_RAR_LV_VOLT_SHIFT)) & SOC_CTRL_SAFE_PMU_RAR_LV_VOLT_MASK)
+
+/* DC/DC Retentive Voltage setting */
+#define SOC_CTRL_SAFE_PMU_RAR_RV_VOLT_MASK                           (0x1f000000)
+#define SOC_CTRL_SAFE_PMU_RAR_RV_VOLT_SHIFT                          (24)
+#define SOC_CTRL_SAFE_PMU_RAR_RV_VOLT(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_RAR_RV_VOLT_SHIFT)) & SOC_CTRL_SAFE_PMU_RAR_RV_VOLT_MASK)
+
+
+/*! @name SAFE_PMU_SLEEPCTRL */
+/* Configure retention mode for region 0 of L2 memory:
+  - 1'b0: Non retentive
+  - 1'b1: Retentive */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R0_MASK                       (0x1)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R0_SHIFT                      (0)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R0(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R0_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R0_MASK)
+
+/* Configure retention mode for region 1 of L2 memory:
+  - 1'b0: Non retentive
+  - 1'b1: Retentive */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R1_MASK                       (0x2)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R1_SHIFT                      (1)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R1(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R1_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R1_MASK)
+
+/* Configure retention mode for region 2 of L2 memory:
+  - 1'b0: Non retentive
+  - 1'b1: Retentive */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R2_MASK                       (0x4)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R2_SHIFT                      (2)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R2(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R2_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R2_MASK)
+
+/* Configure retention mode for region 3 of L2 memory:
+  - 1'b0: Non retentive
+  - 1'b1: Retentive */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R3_MASK                       (0x8)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R3_SHIFT                      (3)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R3(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R3_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_L2_R3_MASK)
+
+/* Configure retention mode for SoC FLL:
+  - 1'b0: Non retentive
+  - 1'b1: Retentive */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_SOC_FLL_MASK                     (0x10)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_SOC_FLL_SHIFT                    (4)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_SOC_FLL(val)                     (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_SOC_FLL_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_SOC_FLL_MASK)
+
+/* Configure retention mode for cluster FLL:
+  - 1'b0: Non retentive
+  - 1'b1: Retentive */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_FLL_MASK                      (0x20)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_FLL_SHIFT                     (5)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_FLL(val)                      (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_FLL_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_FLL_MASK)
+
+/* Select external wake-up source (GPIO ID):
+  - 5'b00000: GPIO 0
+  - 5'b00001: GPIO 1
+  - 5'b00010: GPIO 2
+  - 5'b00011: GPIO 3
+  - 5'b00100: GPIO 4
+  - 5'b00101: GPIO 5
+  - 5'b00110: GPIO 6
+  - 5'b00111: GPIO 7
+  - 5'b01000: GPIO 8
+  - 5'b01001: GPIO 9
+  - 5'b01010: GPIO 10
+  - 5'b01011: GPIO 11
+  - 5'b01100: GPIO 12
+  - 5'b01101: GPIO 13
+  - 5'b01110: GPIO 14
+  - 5'b01111: GPIO 15
+  - 5'b10000: GPIO 16
+  - 5'b10001: GPIO 17
+  - 5'b10010: GPIO 18
+  - 5'b10011: GPIO 19
+  - 5'b10100: GPIO 20
+  - 5'b10101: GPIO 21
+  - 5'b10110: GPIO 22
+  - 5'b10111: GPIO 23
+  - 5'b11000: GPIO 24
+  - 5'b11001: GPIO 25
+  - 5'b11010: GPIO 26
+  - 5'b11011: GPIO 27
+  - 5'b11100: GPIO 28
+  - 5'b11101: GPIO 29
+  - 5'b11110: GPIO 30
+  - 5'b11111: GPIO 31 */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_MASK                 (0x7c0)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_SHIFT                (6)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC(val)                 (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_SRC_MASK)
+
+/* Select external wake-up  mode:
+  - 2'b00: rise event
+  - 2'b01: fall event
+  - 2'b10: high level
+  - 2'b11: low level */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_MASK                (0x1800)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_SHIFT               (11)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE(val)                (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_TYPE_MASK)
+
+/* Enable external wake-up;
+  - 1'b0; external wake-up disabled
+  - 1'b1: external wake-up enabled */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_MASK                  (0x2000)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_SHIFT                 (13)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN(val)                  (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTWAKE_EN_MASK)
+
+/* Power state to restore after warm boot
+  - 1'b0: SoC_LV
+  - 1'b1: SoC_HV */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_WAKESTATE_MASK                   (0x4000)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_WAKESTATE_SHIFT                  (14)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_WAKESTATE(val)                   (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_WAKESTATE_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_WAKESTATE_MASK)
+
+/* Warm bootmode:
+  - 1'b0: Boot from ROM
+  - 1'b1: Boot from L2 */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTDEV_MASK                       (0x10000)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTDEV_SHIFT                      (16)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTDEV(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTDEV_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTDEV_MASK)
+
+/* External wake-up interrupt status (automatically resetted after read)
+  - 1'b0: wake-up triggered by RTC
+  - 1'b1: wake-up triggered by external event */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTINT_MASK                      (0x20000)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTINT_SHIFT                     (17)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTINT(val)                      (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTINT_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_EXTINT_MASK)
+
+/* Select boot type:
+  - 2'b00: cold boot
+  - 2'b01: deep sleep
+  - 2'b10: retentive deep sleep */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTTYPE_MASK                      (0xc0000)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTTYPE_SHIFT                     (18)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTTYPE(val)                      (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTTYPE_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_BTTYPE_MASK)
+
+/* Cluster state to restore after warm boot:
+  - 1’b0: off
+  - 1’b1: on */
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_WAKE_MASK                     (0x100000)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_WAKE_SHIFT                    (20)
+#define SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_WAKE(val)                     (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_WAKE_SHIFT)) & SOC_CTRL_SAFE_PMU_SLEEPCTRL_CL_WAKE_MASK)
+
+
+/*! @name SAFE_PMU_FORCE */
+/* Force retentive state on region 0 of L2 memory:
+  1'b0: not state retentive
+  1'b1: state retentive */
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R0_MASK                       (0x1)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R0_SHIFT                      (0)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R0(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R0_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R0_MASK)
+
+/* Force retentive state on region 1 of L2 memory:
+  1'b0: not state retentive
+  1'b1: state retentive */
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R1_MASK                       (0x2)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R1_SHIFT                      (1)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R1(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R1_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R1_MASK)
+
+/* Force retentive state on region 2 of L2 memory:
+  1'b0: not state retentive
+  1'b1: state retentive */
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R2_MASK                       (0x4)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R2_SHIFT                      (2)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R2(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R2_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R2_MASK)
+
+/* Force retentive state on region 3 of L2 memory:
+  1'b0: not state retentive
+  1'b1: state retentive */
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R3_MASK                       (0x8)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R3_SHIFT                      (3)
+#define SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R3(val)                       (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R3_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_RET_L2_R3_MASK)
+
+/* Force power down on region 0 of L2 memory:
+  1'b0: power up
+  1'b1: power down */
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R0_MASK                        (0x10)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R0_SHIFT                       (4)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R0(val)                        (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R0_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R0_MASK)
+
+/* Force power down on region 1 of L2 memory:
+  1'b0: power up
+  1'b1: power down */
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R1_MASK                        (0x20)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R1_SHIFT                       (5)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R1(val)                        (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R1_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R1_MASK)
+
+/* Force power down on region 2 of L2 memory:
+  1'b0: power up
+  1'b1: power down */
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R2_MASK                        (0x40)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R2_SHIFT                       (6)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R2(val)                        (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R2_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R2_MASK)
+
+/* Force power down on region 3 of L2 memory:
+  1'b0: power up
+  1'b1: power down */
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R3_MASK                        (0x80)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R3_SHIFT                       (7)
+#define SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R3(val)                        (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R3_SHIFT)) & SOC_CTRL_SAFE_PMU_FORCE_PD_L2_R3_MASK)
+
+
+/*! @name SAFE_PADFUN */
+/* Configure pad's functionnality :
+  2'b00: Alternate 0, default.
+  2'b01: Alternate 1, GPIO.
+  2'b10: Alternate 2.
+  2'b11: Alternate 3. */
+/* Shift by 2 to the left the position to get to right pad config. */
+#define SOC_CTRL_SAFE_PADFUN_FUNC_MASK                               (0xffffffff)
+#define SOC_CTRL_SAFE_PADFUN_FUNC_SHIFT                              (0)
+#define SOC_CTRL_SAFE_PADFUN_FUNC(val)                               (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PADFUN_FUNC_SHIFT)) & SOC_CTRL_SAFE_PADFUN_FUNC_MASK)
+
+
+/*! @name SAFE_SLEEPPADCFG */
+/* Configure pad's sleep state & direction.
+  Pos & 0x1 = State:
+  1'b0: input or output low.
+  1'b1: input or output high.
+  Pos & 0x0 = Direction:
+  1'b0: input.
+  1'b1: output. */
+#define SOC_CTRL_SAFE_SLEEPPADCFG_DIR_MASK                           (0x1)
+#define SOC_CTRL_SAFE_SLEEPPADCFG_DIR_SHIFT                          (0)
+#define SOC_CTRL_SAFE_SLEEPPADCFG_DIR(val)                           (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_SLEEPPADCFG_DIR_SHIFT)) & SOC_CTRL_SAFE_SLEEPPADCFG_DIR_MASK)
+
+#define SOC_CTRL_SAFE_SLEEPPADCFG_STATE_MASK                         (0x2)
+#define SOC_CTRL_SAFE_SLEEPPADCFG_STATE_SHIFT                        (1)
+#define SOC_CTRL_SAFE_SLEEPPADCFG_STATE(val)                         (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_SLEEPPADCFG_STATE_SHIFT)) & SOC_CTRL_SAFE_SLEEPPADCFG_STATE_MASK)
+
+
+/*! @name SAFE_PADSLEEP */
+/* Enable pad sleep mode:
+  1'b0: disable
+  1'b1: enable */
+#define SOC_CTRL_SAFE_PADSLEEP_EN_MASK                               (0x1)
+#define SOC_CTRL_SAFE_PADSLEEP_EN_SHIFT                              (0)
+#define SOC_CTRL_SAFE_PADSLEEP_EN(val)                               (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PADSLEEP_EN_SHIFT)) & SOC_CTRL_SAFE_PADSLEEP_EN_MASK)
+
+
+/*! @name SAFE_PADCFG */
+/* Set pull activation.
+  1'b0: pull disabled.
+  1'b1: pull enabled. */
+#define SOC_CTRL_SAFE_PADCFG_PULL_EN_MASK                            (0x1)
+#define SOC_CTRL_SAFE_PADCFG_PULL_EN_SHIFT                           (0)
+#define SOC_CTRL_SAFE_PADCFG_PULL_EN(val)                            (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PADCFG_PULL_EN_SHIFT)) & SOC_CTRL_SAFE_PADCFG_PULL_EN_MASK)
+
+/* Set drive strength.
+  1'b0: low drive strength.
+  1'b1: high drive strength. */
+#define SOC_CTRL_SAFE_PADCFG_DRIVE_STRENGTH_MASK                     (0x2)
+#define SOC_CTRL_SAFE_PADCFG_DRIVE_STRENGTH_SHIFT                    (1)
+#define SOC_CTRL_SAFE_PADCFG_DRIVE_STRENGTH(val)                     (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_SAFE_PADCFG_DRIVE_STRENGTH_SHIFT)) & SOC_CTRL_SAFE_PADCFG_DRIVE_STRENGTH_MASK)
+
+
+/*! @name REG_GPIO_ISO */
+/* Configuration of GPIO domain pads isolation:
+  - 1'b0: not isolated
+  - 1'b1: isolated */
+#define SOC_CTRL_REG_GPIO_ISO_ISO_MASK                               (0x1)
+#define SOC_CTRL_REG_GPIO_ISO_ISO_SHIFT                              (0)
+#define SOC_CTRL_REG_GPIO_ISO_ISO(val)                               (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_REG_GPIO_ISO_ISO_SHIFT)) & SOC_CTRL_REG_GPIO_ISO_ISO_MASK)
+
+
+/*! @name REG_CAM_ISO */
+/* Configuration of CAM domain pads isolation:
+  - 1'b0: not isolated
+  - 1'b1: isolated */
+#define SOC_CTRL_REG_CAM_ISO_ISO_MASK                                (0x1)
+#define SOC_CTRL_REG_CAM_ISO_ISO_SHIFT                               (0)
+#define SOC_CTRL_REG_CAM_ISO_ISO(val)                                (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_REG_CAM_ISO_ISO_SHIFT)) & SOC_CTRL_REG_CAM_ISO_ISO_MASK)
+
+
+/*! @name REG_LVDS_ISO */
+/* Configuration of LVDS domain pads isolation:
+  - 1'b0: not isolated
+  - 1'b1: isolated */
+#define SOC_CTRL_REG_LVDS_ISO_ISO_MASK                               (0x1)
+#define SOC_CTRL_REG_LVDS_ISO_ISO_SHIFT                              (0)
+#define SOC_CTRL_REG_LVDS_ISO_ISO(val)                               (((uint32_t)(((uint32_t)(val)) << SOC_CTRL_REG_LVDS_ISO_ISO_SHIFT)) & SOC_CTRL_REG_LVDS_ISO_ISO_MASK)
+
+
+/*! @name INFO */
+typedef union
+{
+    struct
+    {
+        /* Number of clusters */
+        uint32_t nb_cl:16;
+        /* Number of cores */
+        uint32_t nb_cores:16;
+    } field;
+    uint32_t word;
+} soc_ctrl_info_t;
+
+/*! @name NOTUSED0 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_notused0_t;
+
+/*! @name NOTUSED1 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_notused1_t;
+
+/*! @name CL_ISOLATE */
+typedef union
+{
+    struct
+    {
+        /* Isolate cluster. Inhibits AXI transactions from cluster to SoC:
+        - 1'b0:  Disable
+        - 1'b1: Enable */
+        uint32_t en:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_cl_isolate_t;
+
+/*! @name CL_BUSY */
+typedef union
+{
+    struct
+    {
+        /* Cluster busy flag (i.e. It's 1 if there is at least 1 active block in the cluster) */
+        uint32_t busy:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_cl_busy_t;
+
+/*! @name CL_BYPASS */
+typedef union
+{
+    struct
+    {
+        /* Bypass Maestro PMU controller configuration bitfield:
+        - 1’b0: disabled
+        - 1’b1: enabled */
+        uint32_t byp_pow:1;
+        /* Bypass Maestro PMU configuration selection configuration bitfield:
+        - 1’b0: use default
+        - 1’b1: use user configuration (bitfields from bits 3 to 15 of CL_BYPASS register) */
+        uint32_t byp_cfg:1;
+        uint32_t reserved_0:1;
+        /* Cluster state configuration and status bitfield:
+        - 1’b0: off
+        - 1’b1: on
+        Status information is correct only when bypass mode is enabled. */
+        uint32_t cl_state:1;
+        /* Max current allowed on cluster TRC configuration bitfield. */
+        uint32_t currset:3;
+        /* Number of REFCLK 32kHz after cluster power ok has arised to release TR isolation configuration bitfield. */
+        uint32_t prog_del:2;
+        /* Bypass cluster clock and reset control by Maestro PMU configuration bitfield:
+        - 1’b0: disabled
+        - 1’b1: enabled */
+        uint32_t byp_clk:1;
+        /* Cluster clock gate configuration bitfield:
+        - 1’b0: disabled
+        - 1’b1: enabled
+        It should always be used before switching cluster FLL to shutdown or retentive mode. */
+        uint32_t cg:1;
+        /* Cluster FLL shutdown configuration bitfield:
+        - 1’b0: FLL on
+        - 1’b1: FLL shutdown mode */
+        uint32_t fll_pwd:1;
+        /* Cluster FLL retentive configuration bitfield:
+        - 1’b0: FLL on
+        - 1’b1: FLL retentive mode */
+        uint32_t fll_ret:1;
+        /* Cluster reset configuration bitfield:
+        - 1’b0: nothing
+        - 1’b1: reset the cluster */
+        uint32_t rst:1;
+        /* ? */
+        uint32_t byp_iso:1;
+        /* ? */
+        uint32_t pwiso:1;
+        /* Cluster power ok from cluster TRC status bitfield */
+        uint32_t trcpowok:1;
+        /* Cluster power down from Maestro PMU status bitfield. */
+        uint32_t pmupowdown:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_cl_bypass_t;
+
+/*! @name JTAGREG */
+typedef union
+{
+    struct
+    {
+        /* JTAG internal register used for synchronisation from external debugger */
+        uint32_t int_sync:1;
+        /* JTAG internal register used for selecting boot mode configuration from external debugger */
+        uint32_t int_bt_md:3;
+        uint32_t reserved_0:4;
+        /* JTAG external register used for synchronisation from external debugger */
+        uint32_t ext_sync:1;
+        /* JTAG external register used for selecting boot mode configuration from external debugger */
+        uint32_t ext_bt_md:3;
+    } field;
+    uint32_t word;
+} soc_ctrl_jtagreg_t;
+
+/*! @name L2_SLEEP */
+typedef union
+{
+    struct
+    {
+        /* L2 memory sleep configuration */
+        uint32_t l2_sleep:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_l2_sleep_t;
+
+/*! @name SLEEP_CTRL */
+typedef union
+{
+    struct
+    {
+        /* Alias for SAFE_PMU_SLEEPCTRL(i.e. will be accessible in 1 clock cycle) */
+        uint32_t sleep_ctrl:32;
+    } field;
+    uint32_t word;
+} soc_ctrl_sleep_ctrl_t;
+
+/*! @name CORESTATUS */
+typedef union
+{
+    struct
+    {
+        /* EOC and chip status register */
+        uint32_t status:32;
+    } field;
+    uint32_t word;
+} soc_ctrl_corestatus_t;
+
+/*! @name CORESTATUS_RO */
+typedef union
+{
+    struct
+    {
+        /* EOC and chip status register */
+        uint32_t status:32;
+    } field;
+    uint32_t word;
+} soc_ctrl_corestatus_ro_t;
+
+/*! @name SAFE_PMU_RAR */
+typedef union
+{
+    struct
+    {
+        /* DC/DC Nominal Voltage setting */
+        uint32_t nv_volt:5;
+        uint32_t reserved_0:3;
+        /* DC/DC Medium Voltage setting (not used) */
+        uint32_t mv_volt:5;
+        uint32_t reserved_1:3;
+        /* DC/DC Low Voltage setting */
+        uint32_t lv_volt:5;
+        uint32_t reserved_2:3;
+        /* DC/DC Retentive Voltage setting */
+        uint32_t rv_volt:5;
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_pmu_rar_t;
+
+/*! @name SAFE_PMU_SLEEPCTRL */
+typedef union
+{
+    struct
+    {
+        /* Configure retention mode for region 0 of L2 memory:
+        - 1'b0: Non retentive
+        - 1'b1: Retentive */
+        uint32_t l2_r0:1;
+        /* Configure retention mode for region 1 of L2 memory:
+        - 1'b0: Non retentive
+        - 1'b1: Retentive */
+        uint32_t l2_r1:1;
+        /* Configure retention mode for region 2 of L2 memory:
+        - 1'b0: Non retentive
+        - 1'b1: Retentive */
+        uint32_t l2_r2:1;
+        /* Configure retention mode for region 3 of L2 memory:
+        - 1'b0: Non retentive
+        - 1'b1: Retentive */
+        uint32_t l2_r3:1;
+        /* Configure retention mode for SoC FLL:
+        - 1'b0: Non retentive
+        - 1'b1: Retentive */
+        uint32_t soc_fll:1;
+        /* Configure retention mode for cluster FLL:
+        - 1'b0: Non retentive
+        - 1'b1: Retentive */
+        uint32_t cl_fll:1;
+        /* Select external wake-up source (GPIO ID):
+        - 5'b00000: GPIO 0
+        - 5'b00001: GPIO 1
+        - 5'b00010: GPIO 2
+        - 5'b00011: GPIO 3
+        - 5'b00100: GPIO 4
+        - 5'b00101: GPIO 5
+        - 5'b00110: GPIO 6
+        - 5'b00111: GPIO 7
+        - 5'b01000: GPIO 8
+        - 5'b01001: GPIO 9
+        - 5'b01010: GPIO 10
+        - 5'b01011: GPIO 11
+        - 5'b01100: GPIO 12
+        - 5'b01101: GPIO 13
+        - 5'b01110: GPIO 14
+        - 5'b01111: GPIO 15
+        - 5'b10000: GPIO 16
+        - 5'b10001: GPIO 17
+        - 5'b10010: GPIO 18
+        - 5'b10011: GPIO 19
+        - 5'b10100: GPIO 20
+        - 5'b10101: GPIO 21
+        - 5'b10110: GPIO 22
+        - 5'b10111: GPIO 23
+        - 5'b11000: GPIO 24
+        - 5'b11001: GPIO 25
+        - 5'b11010: GPIO 26
+        - 5'b11011: GPIO 27
+        - 5'b11100: GPIO 28
+        - 5'b11101: GPIO 29
+        - 5'b11110: GPIO 30
+        - 5'b11111: GPIO 31 */
+        uint32_t extwake_src:5;
+        /* Select external wake-up  mode:
+        - 2'b00: rise event
+        - 2'b01: fall event
+        - 2'b10: high level
+        - 2'b11: low level */
+        uint32_t extwake_type:2;
+        /* Enable external wake-up;
+        - 1'b0; external wake-up disabled
+        - 1'b1: external wake-up enabled */
+        uint32_t extwake_en:1;
+        uint32_t reserved_0:1;
+        /* - */
+        uint32_t wakestate:1;
+        /* Warm bootmode:
+        - 1'b0: Boot from ROM
+        - 1'b1: Boot from L2 */
+        uint32_t btdev:1;
+        /* External wake-up interrupt status (automatically resetted after read)
+        - 1'b0: wake-up triggered by RTC
+        - 1'b1: wake-up triggered by external event */
+        uint32_t extint:1;
+        /* Select boot type:
+        - 2'b00: cold boot
+        - 2'b01: deep sleep
+        - 2'b10: retentive deep sleep */
+        uint32_t bttype:2;
+        /* Cluster state to restore after warm boot:
+        - 1’b0: off
+        - 1’b1: on */
+        uint32_t cl_wake:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_pmu_sleepctrl_t;
+
+/*! @name SAFE_PMU_FORCE */
+typedef union
+{
+    struct
+    {
+        /* Force retentive state on region 0 of L2 memory:
+        1'b0: not state retentive
+        1'b1: state retentive */
+        uint32_t ret_l2_r0:1;
+        /* Force retentive state on region 1 of L2 memory:
+        1'b0: not state retentive
+        1'b1: state retentive */
+        uint32_t ret_l2_r1:1;
+        /* Force retentive state on region 2 of L2 memory:
+        1'b0: not state retentive
+        1'b1: state retentive */
+        uint32_t ret_l2_r2:1;
+        /* Force retentive state on region 3 of L2 memory:
+        1'b0: not state retentive
+        1'b1: state retentive */
+        uint32_t ret_l2_r3:1;
+        /* Force power down on region 0 of L2 memory:
+        1'b0: power up
+        1'b1: power down */
+        uint32_t pd_l2_r0:1;
+        /* Force power down on region 1 of L2 memory:
+        1'b0: power up
+        1'b1: power down */
+        uint32_t pd_l2_r1:1;
+        /* Force power down on region 2 of L2 memory:
+        1'b0: power up
+        1'b1: power down */
+        uint32_t pd_l2_r2:1;
+        /* Force power down on region 3 of L2 memory:
+        1'b0: power up
+        1'b1: power down */
+        uint32_t pd_l2_r3:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_pmu_force_t;
+
+/*! @name SAFE_PADFUN0 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padfun0_t;
+
+/*! @name SAFE_PADFUN1 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padfun1_t;
+
+/*! @name SAFE_PADFUN2 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padfun2_t;
+
+/*! @name SAFE_PADFUN3 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padfun3_t;
+
+/*! @name SAFE_SLEEPPADCFG0 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_sleeppadcfg0_t;
+
+/*! @name SAFE_SLEEPPADCFG1 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_sleeppadcfg1_t;
+
+/*! @name SAFE_SLEEPPADCFG2 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_sleeppadcfg2_t;
+
+/*! @name SAFE_SLEEPPADCFG3 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_sleeppadcfg3_t;
+
+/*! @name SAFE_PADSLEEP */
+typedef union
+{
+    struct
+    {
+        /* Enable pad sleep mode:
+        1'b0: disable
+        1'b1: enable */
+        uint32_t en:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padsleep_t;
+
+/*! @name SAFE_PADCFG0 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg0_t;
+
+/*! @name SAFE_PADCFG1 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg1_t;
+
+/*! @name SAFE_PADCFG2 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg2_t;
+
+/*! @name SAFE_PADCFG3 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg3_t;
+
+/*! @name SAFE_PADCFG4 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg4_t;
+
+/*! @name SAFE_PADCFG5 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg5_t;
+
+/*! @name SAFE_PADCFG6 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg6_t;
+
+/*! @name SAFE_PADCFG7 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg7_t;
+
+/*! @name SAFE_PADCFG8 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg8_t;
+
+/*! @name SAFE_PADCFG9 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg9_t;
+
+/*! @name SAFE_PADCFG10 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg10_t;
+
+/*! @name SAFE_PADCFG11 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg11_t;
+
+/*! @name SAFE_PADCFG12 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg12_t;
+
+/*! @name SAFE_PADCFG13 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg13_t;
+
+/*! @name SAFE_PADCFG14 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg14_t;
+
+/*! @name SAFE_PADCFG15 */
+typedef union
+{
+    struct
+    {
+    } field;
+    uint32_t word;
+} soc_ctrl_safe_padcfg15_t;
+
+/*! @name REG_GPIO_ISO */
+typedef union
+{
+    struct
+    {
+        /* Configuration of GPIO domain pads isolation:
+        - 1'b0: not isolated
+        - 1'b1: isolated */
+        uint32_t iso:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_reg_gpio_iso_t;
+
+/*! @name REG_CAM_ISO */
+typedef union
+{
+    struct
+    {
+        /* Configuration of CAM domain pads isolation:
+        - 1'b0: not isolated
+        - 1'b1: isolated */
+        uint32_t iso:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_reg_cam_iso_t;
+
+/*! @name REG_LVDS_ISO */
+typedef union
+{
+    struct
+    {
+        /* Configuration of LVDS domain pads isolation:
+        - 1'b0: not isolated
+        - 1'b1: isolated */
+        uint32_t iso:1;
+    } field;
+    uint32_t word;
+} soc_ctrl_reg_lvds_iso_t;
+
+
+#endif /* HAL_INCLUDE_HAL_SOC_CTRL_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_eu.h

@@ -0,0 +1,157 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_SOC_EU_H_
+#define HAL_INCLUDE_HAL_SOC_EU_H_
+
+
+/*
+ * SOC EVENTS
+ */
+
+/* Let's remove for the time being the SOC_EU* macros from the pulp-sdk and use
+ * the ones form pulp-runtime
+ */
+
+/*
+#define SOC_EU_EVENT_PERIPH_EVT_NB 160
+
+#define SOC_EU_EVENT_SW_NB (8)
+
+#define SOC_EU_EVENT_NB_TOTAL 256
+
+#define SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT_LOG2 2
+#define SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT                                       \
+	(1 << SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT_LOG2)
+#define SOC_EU_EVENT_UDMA_FIRST_EVT 0
+#define SOC_EU_EVENT_UDMA_NB_EVT                                               \
+	(SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT * EU_NB_PERIPH)
+#define SOC_EU_EVENT_UDMA_NB_TGEN_EVT 6
+
+#define SOC_EU_EVENT_PERIPH_FIRST_EVT(x) ((x)*SOC_EU_EVENT_UDMA_NB_CHANNEL_EVT)
+
+#define SOC_EU_EVENT_UART0_RX	   0
+#define SOC_EU_EVENT_UART0_TX	   1
+#define SOC_EU_EVENT_UART0_EOT	   2
+#define SOC_EU_EVENT_UART0_RX_DATA 3
+
+#define SOC_EU_EVENT_SPIM0_RX  4
+#define SOC_EU_EVENT_SPIM0_TX  5
+#define SOC_EU_EVENT_SPIM0_CMD 6
+#define SOC_EU_EVENT_SPIM0_EOT 7
+
+#define SOC_EU_EVENT_I2C0_RX 8
+#define SOC_EU_EVENT_I2C0_TX 9
+
+#define SOC_EU_EVENT_I2C1_RX 12
+#define SOC_EU_EVENT_I2C1_TX 13
+
+#define SOC_EU_EVENT_SDIO0_RX 16
+#define SOC_EU_EVENT_SDIO0_TX 17
+
+#define SOC_EU_EVENT_I2S0_RX 20
+#define SOC_EU_EVENT_I2S0_TX 21
+
+#define SOC_EU_EVENT_CPI0_RX 24
+
+#define SOC_EU_EVENT_FILTER0_RX 28
+#define SOC_EU_EVENT_FILTER0_TX 29
+
+#define SOC_EU_EVENT_CLUSTER_ON_OFF   31
+#define SOC_EU_EVENT_MSP	      37
+#define SOC_EU_EVENT_ICU_MODE_CHANGED 37
+#define SOC_EU_EVENT_ICU_OK	      37
+#define SOC_EU_EVENT_ICU_DELAYED      37
+#define SOC_EU_EVENT_CLUSTER_CG_OK    35
+#define SOC_EU_EVENT_PICL_OK	      36
+#define SOC_EU_EVENT_SCU_OK	      37
+#define SOC_EU_EVENT_PMU_FIRST_EVENT  SOC_EU_EVENT_CLUSTER_ON_OFF
+#define SOC_EU_EVENT_PMU_NB_EVENTS    7
+
+#define SOC_EU_EVENT_GPIO 42
+
+#define SOC_EU_EVENT_NB_I2S_CHANNELS  4
+#define SOC_EU_EVENT_NB_UDMA_CHANNELS 19
+
+#define SOC_EU_EVENT_FCHWPE0 140
+#define SOC_EU_EVENT_FCHWPE1 141
+
+#define SOC_EU_EVENT_SW_EVENT0 48
+#define SOC_EU_EVENT_SW_EVENT1 49
+#define SOC_EU_EVENT_SW_EVENT2 50
+#define SOC_EU_EVENT_SW_EVENT3 51
+#define SOC_EU_EVENT_SW_EVENT4 52
+#define SOC_EU_EVENT_SW_EVENT5 53
+#define SOC_EU_EVENT_SW_EVENT6 54
+#define SOC_EU_EVENT_SW_EVENT7 55
+
+#define SOC_EU_EVENT_NB 8
+
+#define SOC_EU_EVENT_REF_CLK_RISE 56
+*/
+
+#define SOC_EU_EVENT	   0x00
+#define SOC_FC_FIRST_MASK  0x04
+#define SOC_CL_FIRST_MASK  0x24
+#define SOC_PR_FIRST_MASK  0x44
+#define SOC_ERR_FIRST_MASK 0x64
+#define SOC_TIMER_SEL_HI   0x84
+#define SOC_TIMER_SEL_LO   0x88
+
+#define SOC_EU_EVENT_0 0x1
+#define SOC_EU_EVENT_1 0x2
+#define SOC_EU_EVENT_2 0x4
+#define SOC_EU_EVENT_3 0x8
+#define SOC_EU_EVENT_4 0x10
+#define SOC_EU_EVENT_5 0x20
+#define SOC_EU_EVENT_6 0x40
+#define SOC_EU_EVENT_7 0x80
+
+#define SOC_TIMER_SEL_ENABLE_SHIFT 31
+#define SOC_TIMER_SEL_EVT_SHIFT	   0
+#define SOC_TIMER_SEL_EVT_WIDTH	   8
+#define SOC_TIMER_SEL_EVT_MASK	   ((~0U) >> (32 - SOC_TIMER_SEL_EVT_WIDTH))
+// #define SOC_TIMER_SEL_EVT_MASK    0xff
+
+#define SOC_TIMER_SEL_ENABLE_DISABLED 0
+#define SOC_TIMER_SEL_ENABLE_ENABLED  1
+
+#define SOC_TIMER_SEL_ENABLE_DIS   (0 << SOC_TIMER_SEL_ENABLE_SHIFT)
+#define SOC_TIMER_SEL_ENABLE_ENA   (1 << SOC_TIMER_SEL_ENABLE_SHIFT)
+#define SOC_TIMER_SEL_EVT_VAL(val) ((val) << SOC_TIMER_SEL_EVT_SHIFT)
+
+// related to XX_FIRST_MASK registers
+#define SOC_NB_EVENT_REGS    8
+#define SOC_NB_EVENT_TARGETS 3
+
+#define SOC_FC_MASK(x) (SOC_FC_FIRST_MASK + (x)*4)
+#define SOC_CL_MASK(x) (SOC_CL_FIRST_MASK + (x)*4)
+#define SOC_PR_MASK(x) (SOC_PR_FIRST_MASK + (x)*4)
+
+/* TODO: doc */
+void soc_eu_mask_set(uint32_t offset, uint32_t mask);
+uint32_t soc_eu_mask_get(uint32_t offset);
+void pulp_soc_eu_event_init();
+
+
+#endif /* HAL_INCLUDE_HAL_SOC_EU_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_soc_eu_periph.h

@@ -0,0 +1,241 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef HAL_INCLUDE_HAL_SOC_EU_PERIPH_H_
+#define HAL_INCLUDE_HAL_SOC_EU_PERIPH_H_
+
+//#include "pmsis/targets/target.h"
+#include "core-v-mcu-target.h"
+//#include "cores/TARGET_RISCV_32/pulp_io.h"
+#include "pulp_io.h"
+
+/*!
+ * @addtogroup soc_eu
+ * @{
+ */
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* FC SOC domain events, all delegated by FC_SOC_EVENT_IRQn = 27 */
+/* TODO: garbage collect this */
+#define    UDMA_EVENT_LVDS_RX              0
+#define    UDMA_EVENT_LVDS_TX              1
+#define    UDMA_EVENT_SPIM0_RX             2
+#define    UDMA_EVENT_SPIM0_TX             3
+#define    UDMA_EVENT_SPIM1_RX             4
+#define    UDMA_EVENT_SPIM1_TX             5
+#define    UDMA_EVENT_HYPERBUS_RX          6
+#define    UDMA_EVENT_HYPERBUS_TX          7
+#define    UDMA_EVENT_UART_RX              8
+#define    UDMA_EVENT_UART_TX              9
+#define    UDMA_EVENT_I2C0_RX              10
+#define    UDMA_EVENT_I2C0_TX              11
+#define    UDMA_EVENT_I2C1_RX              12
+#define    UDMA_EVENT_I2C1_TX              13
+#define    UDMA_EVENT_DMACPY_RX            14
+#define    UDMA_EVENT_DMACPY_TX            15
+#define    UDMA_EVENT_SAI_CH0              16
+#define    UDMA_EVENT_SAI_CH1              17
+#define    UDMA_EVENT_CPI_RX               18
+#define    UDMA_EVENT_RESERVED0            19
+
+#define    UDMA_EVENT_LVDS_GEN0            20
+#define    UDMA_EVENT_LVDS_GEN1            21
+#define    UDMA_EVENT_SPIM0_EOT            22
+#define    UDMA_EVENT_SPIM1_EOT            23
+#define    UDMA_EVENT_HYPERBUS_RESERVED    24
+#define    UDMA_EVENT_UART_RESERVED        25
+#define    UDMA_EVENT_I2C0_ERROR           26
+#define    UDMA_EVENT_I2C1_ERROR           27
+#define    UDMA_EVENT_I2S_RESERVED         28
+#define    UDMA_EVENT_CAM_RESERVED         29
+#define    UDMA_EVENT_RESERVED1            30
+
+#define    PMU_EVENT_CLUSTER_POWER_ON      31
+#define    PMU_EVENT_CLUSTER_RESERVED0     32
+#define    PMU_EVENT_CLUSTER_RESERVED1     33
+#define    PMU_EVENT_CLUSTER_RESERVED2     34
+#define    PMU_EVENT_CLUSTER_CLOCK_GATING  35
+#define    PMU_DLC_EVENT_BRIDGE_PICL_OK    36
+#define    PMU_DLC_EVENT_BRIDGE_SCU_OK     37
+#define    PMU_EVENTS_NUM                  7
+
+#define    PWM0_EVENT                      38
+#define    PWM1_EVENT                      39
+#define    PWM2_EVENT                      40
+#define    PWM3_EVENT                      41
+#define    GPIO_EVENT                      42              /**< GPIO group interrupt */
+#define    RTC_APB_EVENT                   43
+#define    RTC_EVENT                       44
+#define    EVENT_RESERVED0                 45
+#define    EVENT_RESERVED1                 46
+#define    EVENT_RESERVED2                 47
+
+#define    SOC_SW_EVENT0                   48              /**< GAP8 SOC SW Event0 */
+#define    SOC_SW_EVENT1                   49              /**< GAP8 SOC SW Event1 */
+#define    SOC_SW_EVENT2                   50              /**< GAP8 SOC SW Event2 */
+#define    SOC_SW_EVENT3                   51              /**< GAP8 SOC SW Event3 */
+#define    SOC_SW_EVENT4                   52              /**< GAP8 SOC SW Event4 */
+#define    SOC_SW_EVENT5                   53              /**< GAP8 SOC SW Event5 */
+#define    SOC_SW_EVENT6                   54              /**< GAP8 SOC SW Event6 */
+#define    SOC_SW_EVENT7                   55              /**< GAP8 SOC SW Event7 */
+#define    REF32K_CLK_RISE_EVENT           56              /**< GAP8 SOC EU SW Event Reference 32K Clock event */
+
+/*******************************************************************************
+ * APIs
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+static inline void soc_eu_fc_write(uint32_t val, uint32_t reg)
+{
+	writew(val, (uintptr_t)(SOC_EU_ADDR + SOC_FC_MASK0_OFFSET + reg));
+}
+
+static inline uint32_t soc_eu_fc_read(uint32_t reg)
+{
+	return readw((uintptr_t)(SOC_EU_ADDR + SOC_FC_MASK0_OFFSET + reg));
+}
+
+static inline void soc_eu_cl_write(uint32_t val, uint32_t reg)
+{
+	writew(val, (uintptr_t)(SOC_EU_ADDR + SOC_CL_MASK0_OFFSET + reg));
+}
+
+static inline uint32_t soc_eu_cl_read(uint32_t reg)
+{
+	return readw((uintptr_t)(SOC_EU_ADDR + SOC_CL_MASK0_OFFSET + reg));
+}
+
+static inline void soc_eu_pr_write(uint32_t val, uint32_t reg)
+{
+	writew(val, (uintptr_t)(SOC_EU_ADDR + SOC_PR_MASK0_OFFSET + reg));
+}
+
+static inline uint32_t soc_eu_pr_read(uint32_t reg)
+{
+	return readw((uintptr_t)(SOC_EU_ADDR + SOC_PR_MASK0_OFFSET + reg));
+}
+
+static inline void hal_soc_eu_set_fc_mask(int evt) {
+	if (evt >= 256 || evt < 0)
+		return;
+
+	int shift = evt % 32;
+	uint32_t reg_offset = evt/32 * 4;
+	soc_eu_fc_write(soc_eu_fc_read(reg_offset) & ~(1 << shift), reg_offset);
+}
+
+static inline void hal_soc_eu_set_pr_mask(int evt) {
+	if (evt >= 256 || evt < 0)
+		return;
+
+	int shift = evt % 32;
+	uint32_t reg_offset = evt/32 * 4;
+	soc_eu_pr_write(soc_eu_pr_read(reg_offset) & ~(1 << shift), reg_offset);
+}
+
+static inline void hal_soc_eu_set_cl_mask(int clusterId, int evt) {
+	if (evt >= 256 || evt < 0)
+		return;
+
+	int shift = evt % 32;
+	uint32_t reg_offset = evt/32 * 4;
+	soc_eu_cl_write(soc_eu_cl_read(reg_offset) & ~(1 << shift), reg_offset);
+}
+
+static inline void hal_soc_eu_clear_fc_mask(int evt) {
+	if (evt >= 256 || evt < 0)
+		return;
+
+	int shift = evt % 32;
+	uint32_t reg_offset = evt/32 * 4;
+	soc_eu_fc_write(soc_eu_fc_read(reg_offset) | (1 << shift), reg_offset);
+}
+
+static inline void hal_soc_eu_clear_pr_mask(int evt) {
+	if (evt >= 256 || evt < 0)
+		return;
+
+	int shift = evt % 32;
+	uint32_t reg_offset = evt/32 * 4;
+	soc_eu_pr_write(soc_eu_pr_read(reg_offset) | (1 << shift), reg_offset);
+}
+
+static inline void hal_soc_eu_clear_cl_mask(int clusterId, int evt) {
+	if (evt >= 256 || evt < 0)
+		return;
+
+	int shift = evt % 32;
+	uint32_t reg_offset = evt/32 * 4;
+	soc_eu_cl_write(soc_eu_cl_read(reg_offset) | (1 << shift), reg_offset);
+}
+
+
+static inline void hal_soc_eu_set_mask(uint32_t mask) {
+	writew(mask, (uintptr_t)(SOC_EU_ADDR + SOC_EVENT_OFFSET));
+}
+
+static inline void hal_soc_eu_configure(int cluster, int event, int active) {
+	abort();
+	/* TODO: implement this */
+/* #if SOC_SW_EVENT0 < 32 */
+/*     uint32_t mask = (cluster == FC_CLUSTER_ID) ? (SOCEU->FC_MASK_LSB) : (SOCEU->CL_MASK_LSB); */
+/*     int fullEvent = event - SOC_SW_EVENT0; */
+
+/*     if (!active) */
+/*       mask = mask | (1<<fullEvent); */
+/*     else */
+/*       mask = mask & ~(1<<fullEvent); */
+
+/*     if (cluster == FC_CLUSTER_ID) */
+/*       SOCEU->FC_MASK_LSB = mask; */
+/*     else */
+/*       SOCEU->CL_MASK_LSB = mask; */
+/* #else */
+/*     uint32_t mask = (cluster == FC_CLUSTER_ID) ? (SOCEU->FC_MASK_MSB) : (SOCEU->CL_MASK_MSB); */
+/*     int fullEvent = event + SOC_SW_EVENT0 - 32; */
+
+/*     if (!active) */
+/*       mask = mask | (1<<fullEvent); */
+/*     else */
+/*       mask = mask & ~(1<<fullEvent); */
+
+/*     if (cluster == FC_CLUSTER_ID) */
+/*       SOCEU->FC_MASK_MSB = mask; */
+/*     else */
+/*       SOCEU->CL_MASK_MSB = mask; */
+/* #endif */
+}
+
+/* static inline int SOC_EU_ReserveConfig(int cluster, int event) { */
+/*   if (_bitfield_reserve(&soc_events_mask, event)) return -1; */
+/*   SOC_EU_Configure(cluster, event, 1); */
+/*   return 0; */
+/* } */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/* @} */
+
+
+#endif /* HAL_INCLUDE_HAL_SOC_EU_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_spi_periph.h

@@ -0,0 +1,336 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef HAL_INCLUDE_HAL_SPI_PERIPH_H_
+#define HAL_INCLUDE_HAL_SPI_PERIPH_H_
+
+
+
+#include "hal_udma_core_periph.h"
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** SPI_Type Register Layout Typedef */
+typedef struct {
+	udma_channel_t rx; /**< UDMA RX channels struct. */
+	udma_channel_t tx; /**< UDMA RX channels struct. */
+	udma_channel_t cmd; /**< UDMA RX channels struct. */
+} spi_t;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/* SPI command fields offset, mask, value definition */
+/* SPI commands fields offsets */
+#define SPI_CMD_ID_OFFSET 28
+
+/* COMMON definitions */
+#define SPI_CMD_QPI_ENA		  1
+#define SPI_CMD_QPI_DIS		  0
+#define SPI_CMD_LSB_FIRST	  1
+#define SPI_CMD_MSB_FIRST	  0
+#define SPI_CMD_4_WORD_PER_TRANSF 2
+#define SPI_CMD_2_WORD_PER_TRANSF 1
+#define SPI_CMD_1_WORD_PER_TRANSF 0
+#define SPI_CMD_DATA_WITDH(val)	  (val)
+#define SPI_CMD_CMD_SIZE(val)	  (val)
+
+/* CFG */
+#define SPI_CMD_CFG_CLK_DIV_OFFSET 0
+#define SPI_CMD_CFG_CLK_DIV_WIDTH  8
+#define SPI_CMD_CFG_CPHA_OFFSET	   8
+#define SPI_CMD_CFG_CPOL_OFFSET	   9
+
+#define SPI_CMD_CFG_CLKDIV(val) (val)
+#define SPI_CMD_CFG_CPOL_POS	1
+#define SPI_CMD_CFG_CPOL_NEG	0
+#define SPI_CMD_CFG_CPHA_STD	1
+#define SPI_CMD_CFG_CPHA_OPP	0
+
+/* SOT */
+#define SPI_CMD_SOT_CS_OFFSET 0
+#define SPI_CMD_SOT_CS_WIDTH  2
+
+#define SPI_CMD_SOT_CS0 0
+#define SPI_CMD_SOT_CS1 1
+#define SPI_CMD_SOT_CS2 2
+#define SPI_CMD_SOT_CS3 3
+
+/* SEND_CMD */
+#define SPI_CMD_SEND_CMD_CMD_OFFSET  0
+#define SPI_CMD_SEND_CMD_CMD_WIDTH   16
+#define SPI_CMD_SEND_CMD_SIZE_OFFSET 16
+#define SPI_CMD_SEND_CMD_SIZE_WIDTH  4
+#define SPI_CMD_SEND_CMD_QPI_OFFSET  27
+
+/* SEND_CMD */
+#define SPI_CMD_SEND_BITS_BITS_OFFSET 0
+#define SPI_CMD_SEND_BITS_BITS_WIDTH  16
+#define SPI_CMD_SEND_BITS_SIZE_OFFSET 16
+#define SPI_CMD_SEND_BITS_SIZE_WIDTH  4
+#define SPI_CMD_SEND_BITS_QPI_OFFSET  27
+
+/* SEND_ADDR */
+#define SPI_CMD_SEND_ADDR_SIZE_OFFSET 16
+#define SPI_CMD_SEND_ADDR_SIZE_WIDTH  5
+#define SPI_CMD_SEND_ADDR_QPI_OFFSET  27
+
+#define SPI_CMD_SEND_ADDR_VALUE(value) (value)
+
+/* SEND_DUMMY */
+#define SPI_CMD_DUMMY_CYCLE_OFFSET 16
+#define SPI_CMD_DUMMY_CYCLE_WIDTH  5
+
+/* TX_DATA */
+#define SPI_CMD_TX_DATA_SIZE_OFFSET	 0
+#define SPI_CMD_TX_DATA_SIZE_WIDTH	 16
+#define SPI_CMD_TX_DATA_QPI_OFFSET	 27
+#define SPI_CMD_TX_DATA_WORDTRANS_OFFSET 21
+#define SPI_CMD_TX_DATA_WORDTRANS_WIDTH	 2
+#define SPI_CMD_TX_DATA_LSBFIRST_OFFSET	 26
+#define SPI_CMD_TX_DATA_BITSWORD_OFFSET	 16
+#define SPI_CMD_TX_DATA_BITSWORD_WIDTH	 5
+
+/* RX_DATA */
+#define SPI_CMD_RX_DATA_SIZE_OFFSET	 0
+#define SPI_CMD_RX_DATA_SIZE_WIDTH	 16
+#define SPI_CMD_RX_DATA_QPI_OFFSET	 27
+#define SPI_CMD_RX_DATA_WORDTRANS_OFFSET 21
+#define SPI_CMD_RX_DATA_WORDTRANS_WIDTH	 2
+#define SPI_CMD_RX_DATA_LSBFIRST_OFFSET	 26
+#define SPI_CMD_RX_DATA_BITSWORD_OFFSET	 16
+#define SPI_CMD_RX_DATA_BITSWORD_WIDTH	 5
+
+/* RPT */
+#define SPI_CMD_RPT_NB_OFFSET 0
+#define SPI_CMD_RPT_NB_WIDTH  16
+
+/* EOT */
+#define SPI_CMD_EOT_GEN_EVT_OFFSET 0
+#define SPI_CMD_EOT_CS_KEEP_OFFSET 1
+
+#define SPI_CMD_EOT_EVENT_ENA 1
+#define SPI_CMD_EOT_EVENT_DIS 0
+
+/* WAIT */
+#define SPI_CMD_WAIT_EVENT_OFFSET 0
+#define SPI_CMD_WAIT_EVENT_WIDTH  2
+
+/* RX_CHECK */
+#define SPI_CMD_RX_CHECK_VALUE_OFFSET 0
+#define SPI_CMD_RX_CHECK_VALUE_WIDTH  16
+
+#define SPI_CMD_RX_CHECK_SIZE_OFFSET 16
+#define SPI_CMD_RX_CHECK_SIZE_WIDTH  4
+
+#define SPI_CMD_RX_CHECK_MODE_OFFSET 24
+#define SPI_CMD_RX_CHECK_MODE_WIDTH  2
+
+#define SPI_CMD_RX_CHECK_BYTE_ALIGN_OFFSET 26
+
+#define SPI_CMD_RX_CHECK_QPI_OFFSET 27
+
+#define SPI_CMD_RX_CHECK_MODE_MATCH 0
+#define SPI_CMD_RX_CHECK_MODE_ONES  1
+#define SPI_CMD_RX_CHECK_MODE_ZEROS 2
+#define SPI_CMD_RX_CHECK_MODE_MASK  3
+
+/* FULL DUPLEX */
+#define SPI_CMD_FUL_SIZE_OFFSET	     0
+#define SPI_CMD_FUL_SIZE_WIDTH	     16
+#define SPI_CMD_FUL_WORDTRANS_OFFSET 21
+#define SPI_CMD_FUL_WORDTRANS_WIDTH  2
+#define SPI_CMD_FUL_LSBFIRST_OFFSET  26
+#define SPI_CMD_FUL_BITSWORD_OFFSET  16
+#define SPI_CMD_FUL_BITSWORD_WIDTH   5
+
+#define SPI_CMD_SETUP_UC_TXRXEN_OFFSET 27
+#define SPI_CMD_SETUP_UC_DS_OFFSET     25
+
+/* ----------------------------------------------------------------------------
+   -- SPI CMD IDs and macros --
+   ---------------------------------------------------------------------------- */
+
+/*! @name CMD_CFG */
+/* Channel continuous mode:
+  - 1'b0: disable
+  - 1'b1: enable
+  At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */
+#define UDMA_CORE_CMD_CFG_CONTINOUS_MASK  (0x1)
+#define UDMA_CORE_CMD_CFG_CONTINOUS_SHIFT (0)
+#define UDMA_CORE_CMD_CFG_CONTINOUS(val)                                       \
+	(((uint32_t)(((uint32_t)(val))                                         \
+		     << UDMA_CORE_CMD_CFG_CONTINOUS_SHIFT)) &                  \
+	 UDMA_CORE_CMD_CFG_CONTINOUS_MASK)
+
+/* Channel transfer size used to increment uDMA buffer address pointer:
+  - 2'b00: +1 (8 bits)
+  - 2'b01: +2 (16 bits)
+  - 2'b10: +4 (32 bits)
+  - 2'b11: +0 */
+#define UDMA_CORE_CMD_CFG_DATASIZE_MASK	 (0x6)
+#define UDMA_CORE_CMD_CFG_DATASIZE_SHIFT (1)
+#define UDMA_CORE_CMD_CFG_DATASIZE(val)                                        \
+	(((uint32_t)(((uint32_t)(val)) << UDMA_CORE_CMD_CFG_DATASIZE_SHIFT)) & \
+	 UDMA_CORE_CMD_CFG_DATASIZE_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_CMD_CFG_RESERVED_0_MASK  (0x8)
+#define UDMA_CORE_CMD_CFG_RESERVED_0_SHIFT (3)
+#define UDMA_CORE_CMD_CFG_RESERVED_0(val)                                      \
+	(((uint32_t)(((uint32_t)(val))                                         \
+		     << UDMA_CORE_CMD_CFG_RESERVED_0_SHIFT)) &                 \
+	 UDMA_CORE_CMD_CFG_RESERVED_0_MASK)
+
+/* Channel enable and start transfer:
+  - 1'b0: disable
+  - 1'b1: enable
+  This signal is used also to queue a transfer if one is already ongoing. */
+#define UDMA_CORE_CMD_CFG_EN_MASK  (0x10)
+#define UDMA_CORE_CMD_CFG_EN_SHIFT (4)
+#define UDMA_CORE_CMD_CFG_EN(val)                                              \
+	(((uint32_t)(((uint32_t)(val)) << UDMA_CORE_CMD_CFG_EN_SHIFT)) &       \
+	 UDMA_CORE_CMD_CFG_EN_MASK)
+
+/* Transfer pending in queue status flag:
+  - 1'b0: no pending transfer in the queue
+  - 1'b1: pending transfer in the queue */
+#define UDMA_CORE_CMD_CFG_PENDING_MASK	(0x20)
+#define UDMA_CORE_CMD_CFG_PENDING_SHIFT (5)
+#define UDMA_CORE_CMD_CFG_PENDING(val)                                         \
+	(((uint32_t)(((uint32_t)(val)) << UDMA_CORE_CMD_CFG_PENDING_SHIFT)) &  \
+	 UDMA_CORE_CMD_CFG_PENDING_MASK)
+
+/* Channel clear and stop transfer:
+  - 1'b0: disable
+  - 1'b1: stop and clear the on-going transfer */
+#define UDMA_CORE_CMD_CFG_CLR_MASK  (0x20)
+#define UDMA_CORE_CMD_CFG_CLR_SHIFT (5)
+#define UDMA_CORE_CMD_CFG_CLR(val)                                             \
+	(((uint32_t)(((uint32_t)(val)) << UDMA_CORE_CMD_CFG_CLR_SHIFT)) &      \
+	 UDMA_CORE_CMD_CFG_CLR_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_CMD_CFG_RESERVED_1_MASK  (0xffffff80)
+#define UDMA_CORE_CMD_CFG_RESERVED_1_SHIFT (7)
+#define UDMA_CORE_CMD_CFG_RESERVED_1(val)                                      \
+	(((uint32_t)(((uint32_t)(val))                                         \
+		     << UDMA_CORE_CMD_CFG_RESERVED_1_SHIFT)) &                 \
+	 UDMA_CORE_CMD_CFG_RESERVED_1_MASK)
+
+/*! @name CMD_INITCFG */
+/* Reserved/Not used. */
+#define UDMA_CORE_CMD_INITCFG_RESERVED_0_MASK  (0xffffffff)
+#define UDMA_CORE_CMD_INITCFG_RESERVED_0_SHIFT (0)
+#define UDMA_CORE_CMD_INITCFG_RESERVED_0(val)                                  \
+	(((uint32_t)(((uint32_t)(val))                                         \
+		     << UDMA_CORE_CMD_INITCFG_RESERVED_0_SHIFT)) &             \
+	 UDMA_CORE_CMD_INITCFG_RESERVED_0_MASK)
+
+#define SPI_CMD_CFG_ID	     0x0 /* Sets the configuration for the SPI Master IP. */
+#define SPI_CMD_SOT_ID	     0x1 /* Sets the Chip Select (CS). */
+#define SPI_CMD_SEND_CMD_ID  0x2 /* Transmits a configurable size command. */
+#define SPI_CMD_SEND_BITS_ID 0x2 /* Transmits a configurable size command. */
+#define SPI_CMD_SEND_ADDR_ID 0x3 /* Transmits a configurable size address. */
+#define SPI_CMD_DUMMY_ID                                                       \
+	0x4 /* Receives a number of dummy bits (not sent to the rx interface). */
+#define SPI_CMD_WAIT_ID                                                        \
+	0x5 /* Waits an external event to move to the next instruction. */
+#define SPI_CMD_TX_DATA_ID 0x6 /* Sends data (max 64Kbits). */
+#define SPI_CMD_RX_DATA_ID 0x7 /* Receives data (max 64Kbits). */
+#define SPI_CMD_RPT_ID	   0x8 /* Repeat the next transfer N times. */
+#define SPI_CMD_EOT_ID	   0x9 /* Clears the Chip Select (CS). */
+#define SPI_CMD_RPT_END_ID 0xA /* End of the repeat loop command. */
+#define SPI_CMD_RX_CHECK_ID                                                    \
+	0xB /* Check up ot 16 bits of data against an expected value. */
+#define SPI_CMD_FULL_DUPL_ID 0xC /* Activate full duplex mode. */
+
+#define SPI_CMD_CFG(clockDiv, cpol, cpha)                                      \
+	((SPI_CMD_CFG_ID << SPI_CMD_ID_OFFSET) |                               \
+	 ((cpol) << SPI_CMD_CFG_CPOL_OFFSET) |                                 \
+	 ((cpha) << SPI_CMD_CFG_CPHA_OFFSET) |                                 \
+	 ((clockDiv) << SPI_CMD_CFG_CLK_DIV_OFFSET))
+#define SPI_CMD_SOT(cs)                                                        \
+	((SPI_CMD_SOT_ID << SPI_CMD_ID_OFFSET) |                               \
+	 ((cs) << SPI_CMD_SOT_CS_OFFSET))
+#define SPI_CMD_SEND_CMD(cmd, bits, qpi)                                       \
+	((SPI_CMD_SEND_CMD_ID << SPI_CMD_ID_OFFSET) |                          \
+	 ((qpi) << SPI_CMD_SEND_CMD_QPI_OFFSET) |                              \
+	 (((bits)-1) << SPI_CMD_SEND_CMD_SIZE_OFFSET) | (cmd & 0xFFFF))
+#define SPI_CMD_SEND_BITS(data, bits, qpi)                                     \
+	((SPI_CMD_SEND_CMD_ID << SPI_CMD_ID_OFFSET) |                          \
+	 ((qpi) << SPI_CMD_SEND_CMD_QPI_OFFSET) |                              \
+	 (((bits)-1) << SPI_CMD_SEND_CMD_SIZE_OFFSET) | (data & 0xFFFF))
+#define SPI_CMD_DUMMY(cycles)                                                  \
+	((SPI_CMD_DUMMY_ID << SPI_CMD_ID_OFFSET) |                             \
+	 (((cycles)-1) << SPI_CMD_DUMMY_CYCLE_OFFSET))
+
+#define SPI_CMD_SETUP_UCA(txrxen, ds, addr)                                    \
+	((SPI_CMD_SETUP_UCA_ID << SPI_CMD_ID_OFFSET) |                         \
+	 ((txrxen) << SPI_CMD_SETUP_UC_TXRXEN_OFFSET) | ((int)addr & 0xFFFFF))
+#define SPI_CMD_SETUP_UCS(txrxen, ds, size)                                    \
+	((SPI_CMD_SETUP_UCS_ID << SPI_CMD_ID_OFFSET) |                         \
+	 ((txrxen) << SPI_CMD_SETUP_UC_TXRXEN_OFFSET) |                        \
+	 ((ds) << SPI_CMD_SETUP_UC_DS_OFFSET) | (size & 0xFFFF))
+
+#define SPI_CMD_TX_DATA(words, wordstrans, bitsword, qpi, lsbfirst)            \
+	((SPI_CMD_TX_DATA_ID << SPI_CMD_ID_OFFSET) |                           \
+	 ((qpi) << SPI_CMD_TX_DATA_QPI_OFFSET) |                               \
+	 ((wordstrans) << SPI_CMD_TX_DATA_WORDTRANS_OFFSET) |                  \
+	 ((bitsword - 1) << SPI_CMD_TX_DATA_BITSWORD_OFFSET) |                 \
+	 (((words)-1) << SPI_CMD_TX_DATA_SIZE_OFFSET) |                        \
+	 ((lsbfirst) << SPI_CMD_TX_DATA_LSBFIRST_OFFSET))
+#define SPI_CMD_RX_DATA(words, wordstrans, bitsword, qpi, lsbfirst)            \
+	((SPI_CMD_RX_DATA_ID << SPI_CMD_ID_OFFSET) |                           \
+	 ((qpi) << SPI_CMD_RX_DATA_QPI_OFFSET) |                               \
+	 ((wordstrans) << SPI_CMD_RX_DATA_WORDTRANS_OFFSET) |                  \
+	 ((bitsword - 1) << SPI_CMD_RX_DATA_BITSWORD_OFFSET) |                 \
+	 (((words)-1) << SPI_CMD_RX_DATA_SIZE_OFFSET) |                        \
+	 ((lsbfirst) << SPI_CMD_RX_DATA_LSBFIRST_OFFSET))
+#define SPI_CMD_RPT(iter)                                                      \
+	((SPI_CMD_RPT_ID << SPI_CMD_ID_OFFSET) |                               \
+	 ((iter) << SPI_CMD_RPT_NB_OFFSET))
+#define SPI_CMD_EOT(evt, cs_keep)                                              \
+	((SPI_CMD_EOT_ID << SPI_CMD_ID_OFFSET) |                               \
+	 ((evt) << SPI_CMD_EOT_GEN_EVT_OFFSET) |                               \
+	 ((cs_keep) << SPI_CMD_EOT_CS_KEEP_OFFSET))
+
+#define SPI_CMD_RX_CHECK(mode, bits, value, qpi, byte_align)                   \
+	((SPI_CMD_RX_CHECK_ID << SPI_CMD_ID_OFFSET) |                          \
+	 ((value) << SPI_CMD_RX_CHECK_VALUE_OFFSET) |                          \
+	 ((mode) << SPI_CMD_RX_CHECK_MODE_OFFSET) |                            \
+	 (((bits)-1) << SPI_CMD_RX_CHECK_SIZE_OFFSET) |                        \
+	 ((byte_align) << SPI_CMD_RX_CHECK_BYTE_ALIGN_OFFSET) |                \
+	 ((qpi) << SPI_CMD_RX_CHECK_QPI_OFFSET))
+
+#define SPI_CMD_WAIT(event)                                                    \
+	((SPI_CMD_WAIT_ID << SPI_CMD_ID_OFFSET) |                              \
+	 ((event) << SPI_CMD_WAIT_EVENT_OFFSET))
+#define SPI_CMD_RPT_END() ((SPI_CMD_RPT_END_ID << SPI_CMD_ID_OFFSET))
+#define SPI_CMD_FUL(words, wordstrans, bitsword, lsbfirst)                     \
+	((SPI_CMD_FUL_ID << SPI_CMD_ID_OFFSET) |                               \
+	 ((wordstrans) << SPI_CMD_FUL_WORDTRANS_OFFSET) |                      \
+	 ((bitsword - 1) << SPI_CMD_FUL_BITSWORD_OFFSET) |                     \
+	 (((words)-1) << SPI_CMD_FUL_SIZE_OFFSET) |                            \
+	 ((lsbfirst) << SPI_CMD_FUL_LSBFIRST_OFFSET))
+
+
+#endif /* HAL_INCLUDE_HAL_SPI_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_timer.h

@@ -0,0 +1,225 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ */
+
+#ifndef HAL_INCLUDE_HAL_TIMER_H_
+#define HAL_INCLUDE_HAL_TIMER_H_
+
+
+
+#include "bits.h"
+
+/* Timer Low Configuration register. */
+#define TIMER_CFG_LO_OFFSET 0x0
+
+/* Timer High Configuration register. */
+#define TIMER_CFG_HI_OFFSET 0x4
+
+/* Timer Low counter value register. */
+#define TIMER_CNT_LO_OFFSET 0x8
+
+/* Timer High counter value register. */
+#define TIMER_CNT_HI_OFFSET 0xc
+
+/* Timer Low comparator value register. */
+#define TIMER_CMP_LO_OFFSET 0x10
+
+/* Timer High comparator value register. */
+#define TIMER_CMP_HI_OFFSET 0x14
+
+/* Start Timer Low counting register. */
+#define TIMER_START_LO_OFFSET 0x18
+
+/* Start Timer High counting register. */
+#define TIMER_START_HI_OFFSET 0x1c
+
+/* Reset Timer Low counter register. */
+#define TIMER_RESET_LO_OFFSET 0x20
+
+/* Reset Timer High counter register. */
+#define TIMER_RESET_HI_OFFSET 0x24
+
+/* Timer low enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled
+ * (access: R/W) */
+#define TIMER_CFG_LO_ENABLE_BIT	  0
+#define TIMER_CFG_LO_ENABLE_WIDTH 1
+#define TIMER_CFG_LO_ENABLE_MASK  0x1
+
+/* Timer low counter reset command bitfield. Cleared after Timer Low reset
+ * execution. (access: R/W) */
+#define TIMER_CFG_LO_RESET_BIT	 1
+#define TIMER_CFG_LO_RESET_WIDTH 1
+#define TIMER_CFG_LO_RESET_MASK	 0x2
+
+/* Timer low compare match interrupt enable configuration bitfield: - 1'b0:
+ * disabled - 1'b1: enabled (access: R/W) */
+#define TIMER_CFG_LO_IRQEN_BIT	 2
+#define TIMER_CFG_LO_IRQEN_WIDTH 1
+#define TIMER_CFG_LO_IRQEN_MASK	 0x4
+
+/* Timer low input event mask configuration bitfield: - 1'b0: disabled - 1'b1:
+ * enabled (access: R/W) */
+#define TIMER_CFG_LO_IEM_BIT   3
+#define TIMER_CFG_LO_IEM_WIDTH 1
+#define TIMER_CFG_LO_IEM_MASK  0x8
+
+/* Timer low continuous mode configuration bitfield: - 1'b0: Continue mode -
+ * continue incrementing Timer low counter when compare match with CMP_LO
+ * occurs. - 1'b1: Cycle mode - reset Timer low counter when compare match with
+ * CMP_LO occurs. (access: R/W) */
+#define TIMER_CFG_LO_MODE_BIT	4
+#define TIMER_CFG_LO_MODE_WIDTH 1
+#define TIMER_CFG_LO_MODE_MASK	0x10
+
+/* Timer low one shot configuration bitfield: - 1'b0: let Timer low enabled
+ * counting when compare match with CMP_LO occurs. - 1'b1: disable Timer low
+ * when compare match with CMP_LO occurs. (access: R/W) */
+#define TIMER_CFG_LO_ONE_S_BIT	 5
+#define TIMER_CFG_LO_ONE_S_WIDTH 1
+#define TIMER_CFG_LO_ONE_S_MASK	 0x20
+
+/* Timer low prescaler enable configuration bitfield:- 1'b0: disabled - 1'b1:
+ * enabled (access: R/W) */
+#define TIMER_CFG_LO_PEN_BIT   6
+#define TIMER_CFG_LO_PEN_WIDTH 1
+#define TIMER_CFG_LO_PEN_MASK  0x40
+
+/* Timer low clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler - 1'b1: Reference clock at 32kHz (access: R/W) */
+#define TIMER_CFG_LO_CCFG_BIT	7
+#define TIMER_CFG_LO_CCFG_WIDTH 1
+#define TIMER_CFG_LO_CCFG_MASK	0x80
+
+/* Timer low prescaler value bitfield. Ftimer = Fclk / (1 + PRESC_VAL) (access:
+ * R/W) */
+#define TIMER_CFG_LO_PVAL_BIT	8
+#define TIMER_CFG_LO_PVAL_WIDTH 8
+#define TIMER_CFG_LO_PVAL_MASK	0xff00
+
+/* Timer low + Timer high 64bit cascaded mode configuration bitfield. (access:
+ * R/W) */
+#define TIMER_CFG_LO_CASC_BIT	31
+#define TIMER_CFG_LO_CASC_WIDTH 1
+#define TIMER_CFG_LO_CASC_MASK	0x80000000
+
+/* Timer high enable configuration bitfield: - 1'b0: disabled - 1'b1: enabled
+ * (access: R/W) */
+#define TIMER_CFG_HI_ENABLE_BIT	  0
+#define TIMER_CFG_HI_ENABLE_WIDTH 1
+#define TIMER_CFG_HI_ENABLE_MASK  0x1
+
+/* Timer high counter reset command bitfield. Cleared after Timer high reset
+ * execution. (access: W) */
+#define TIMER_CFG_HI_RESET_BIT	 1
+#define TIMER_CFG_HI_RESET_WIDTH 1
+#define TIMER_CFG_HI_RESET_MASK	 0x2
+
+/* Timer high compare match interrupt enable configuration bitfield: - 1'b0:
+ * disabled - 1'b1: enabled (access: R/W) */
+#define TIMER_CFG_HI_IRQEN_BIT	 2
+#define TIMER_CFG_HI_IRQEN_WIDTH 1
+#define TIMER_CFG_HI_IRQEN_MASK	 0x4
+
+/* Timer high input event mask configuration bitfield: - 1'b0: disabled - 1'b1:
+ * enabled (access: R/W) */
+#define TIMER_CFG_HI_IEM_BIT   3
+#define TIMER_CFG_HI_IEM_WIDTH 1
+#define TIMER_CFG_HI_IEM_MASK  0x8
+
+/* Timer high continuous mode configuration bitfield: - 1'b0: Continue mode -
+ * continue incrementing Timer high counter when compare match with CMP_LO
+ * occurs. - 1'b1: Cycle mode - reset Timer high counter when compare match with
+ * CMP_LO occurs. (access: R/W) */
+#define TIMER_CFG_HI_MODE_BIT	4
+#define TIMER_CFG_HI_MODE_WIDTH 1
+#define TIMER_CFG_HI_MODE_MASK	0x10
+
+/* Timer high one shot configuration bitfield: - 1'b0: let Timer high enabled
+ * counting when compare match with CMP_LO occurs. - 1'b1: disable Timer high
+ * when compare match with CMP_LO occurs. (access: R/W) */
+#define TIMER_CFG_HI_ONE_S_BIT	 5
+#define TIMER_CFG_HI_ONE_S_WIDTH 1
+#define TIMER_CFG_HI_ONE_S_MASK	 0x20
+
+/* Timer high prescaler enable configuration bitfield: - 1'b0: disabled - 1'b1:
+ * enabled (access: R/W) */
+#define TIMER_CFG_HI_PEN_BIT   6
+#define TIMER_CFG_HI_PEN_WIDTH 1
+#define TIMER_CFG_HI_PEN_MASK  0x40
+
+
+/* Timer high clock source configuration bitfield: - 1'b0: FLL or FLL+Prescaler
+ * - 1'b1: Reference clock at 32kHz (access: R/W) */
+#define TIMER_CFG_HI_CCFG_BIT	  7
+#define TIMER_CFG_HI_CCFG_WIDTH 1
+#define TIMER_CFG_HI_CCFG_MASK  0x80
+
+/* Timer Low counter value bitfield. (access: R/W) */
+#define TIMER_CNT_LO_CNT_LO_BIT	  0
+#define TIMER_CNT_LO_CNT_LO_WIDTH 32
+#define TIMER_CNT_LO_CNT_LO_MASK  0xffffffff
+
+/* Timer High counter value bitfield. (access: R/W) */
+#define TIMER_CNT_HI_CNT_HI_BIT	  0
+#define TIMER_CNT_HI_CNT_HI_WIDTH 32
+#define TIMER_CNT_HI_CNT_HI_MASK  0xffffffff
+
+/* Timer Low comparator value bitfield. (access: R/W) */
+#define TIMER_CMP_LO_CMP_LO_BIT	  0
+#define TIMER_CMP_LO_CMP_LO_WIDTH 32
+#define TIMER_CMP_LO_CMP_LO_MASK  0xffffffff
+
+/* Timer High comparator value bitfield. (access: R/W) */
+#define TIMER_CMP_HI_CMP_HI_BIT	  0
+#define TIMER_CMP_HI_CMP_HI_WIDTH 32
+#define TIMER_CMP_HI_CMP_HI_MASK  0xffffffff
+
+/* Timer Low start command bitfield. When executed, CFG_LO.ENABLE is set.
+ * (access: W) */
+#define TIMER_START_LO_STRT_LO_BIT   0
+#define TIMER_START_LO_STRT_LO_WIDTH 1
+#define TIMER_START_LO_STRT_LO_MASK  0x1
+
+/* Timer High start command bitfield. When executed, CFG_HI.ENABLE is set.
+ * (access: W) */
+#define TIMER_START_HI_STRT_HI_BIT   0
+#define TIMER_START_HI_STRT_HI_WIDTH 1
+#define TIMER_START_HI_STRT_HI_MASK  0x1
+
+/* Timer Low counter reset command bitfield. When executed, CFG_LO.RESET is set.
+ * (access: W) */
+#define TIMER_RESET_LO_RST_LO_BIT   0
+#define TIMER_RESET_LO_RST_LO_WIDTH 1
+#define TIMER_RESET_LO_RST_LO_MASK  0x1
+
+/* Timer High counter reset command bitfield. When executed, CFG_HI.RESET is
+ * set. (access: W) */
+#define TIMER_RESET_HI_RST_HI_BIT   0
+#define TIMER_RESET_HI_RST_HI_WIDTH 1
+#define TIMER_RESET_HI_RST_HI_MASK  0x1
+
+struct pulp_timer {
+	unsigned int current_time;
+	unsigned int flags;
+	void *base;
+};
+
+
+#endif /* HAL_INCLUDE_HAL_TIMER_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_timer_irq.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch) */
+
+#ifndef HAL_INCLUDE_HAL_TIMER_IRQ_H_
+#define HAL_INCLUDE_HAL_TIMER_IRQ_H_
+
+#include <stdint.h>
+
+int timer_irq_init(uint32_t ticks);
+
+int timer_irq_set_timeout(uint32_t ticks, bool idle);
+
+uint32_t timer_irq_clock_elapsed();
+
+uint32_t timer_irq_cycle_get_32();
+
+
+#endif /* HAL_INCLUDE_HAL_TIMER_IRQ_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_internal.h

@@ -0,0 +1,178 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef HAL_INCLUDE_HAL_UART_INTERNAL_H_
+#define HAL_INCLUDE_HAL_UART_INTERNAL_H_
+
+//#include "../../pmsis_api/include/pmsis/drivers/uart-orig.h"
+#include "hal_uart_pi.h"
+#include "core-v-mcu-pmsis.h"
+//#include "pmsis/task.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+#define UART_TX_BUFFER_SIZE     16
+#define UART_DEFAULT_PRE_ALLOC_EVT 5
+
+#define NB_UART 1
+
+#ifndef UART_DRIVER_DATA_IMPLEM_SPECIFC
+    #define UART_DRIVER_DATA_IMPLEM_SPECIFC
+#endif
+
+
+/*
+ * pi_task:
+ * data[0] = l2_buf
+ * data[1] = size
+ * data[2] = channel
+ * data[3] = repeat_size
+ * data[4] = device_id (used for delegation)
+ */
+struct uart_itf_data_s
+{
+    struct pi_task *fifo_head[2]; /*!< 0 = RX | 1 = TX. */
+    struct pi_task *fifo_tail[2]; /*!< 0 = RX | 1 = TX. */
+    uint32_t nb_open;             /*!< Number of times device has been opened. */
+    uint32_t device_id;           /*!< Device ID. */
+    UART_DRIVER_DATA_IMPLEM_SPECIFC
+};
+
+/*******************************************************************************
+ * Driver data
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Function declaration
+ ******************************************************************************/
+
+/**
+ * \brief Initialize conf struct.
+ *
+ * This function initializes a config struct with default values.
+ *
+ * \param conf           Pointer to struct pi_uart_conf.
+ */
+void __pi_uart_conf_init(struct pi_uart_conf *conf);
+
+/**
+ * \brief Open a device.
+ *
+ * This function opens a device.
+ * A conf struct and a pointer to store UART driver info should be given.
+ *
+ * \para driver_data     Pointer to store driver info.
+ * \param conf           Pointer to struct pi_uart_conf.
+ *
+ * \retval 0            If operation is successfull.
+ * \retval ERRNO        An error code otherwise.
+ */
+int32_t __pi_uart_open(struct uart_itf_data_s **driver_data,
+                       struct pi_uart_conf *conf);
+
+/**
+ * \brief Close a device.
+ *
+ * This function closes an opened device.
+ *
+ * \param driver_data    Pointer to driver info.
+ */
+void __pi_uart_close(struct uart_itf_data_s *driver_data);
+
+/**
+ * \brief Ioctl commands.
+ *
+ * This function allows to configure a device using ioctl commands.
+ *
+ * \param driver_data    Pointer to driver info.
+ * \param cmd            Ioctl command.
+ * \param arg            Ioctl command arg.
+ *
+ * \retval -1            If wrong ioctl command.
+ * \retval Value         Value depending on ioctl command.
+ */
+int32_t __pi_uart_ioctl(struct uart_itf_data_s *driver_data, uint32_t cmd,
+                        void *arg);
+
+/**
+ * \brief Transfer data.
+ *
+ * This function allows to send/receive data using the periph.
+ * The transfer is executed immediately if there is no current transfer or no
+ * pending transfer. Otherwise, the transfer is enqueued in a fifo.
+ *
+ * \param driver_data    Pointer to driver info.
+ * \param l2_buf         Address of data buffer.
+ * \param size           Size of data buffer.
+ * \param channel        Direction of transfer.
+ * \param task           Event task used to notify end of transfer.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval -1            Otherwise.
+ */
+int32_t __pi_uart_copy(struct uart_itf_data_s *driver_data, uint32_t l2_buf,
+                       uint32_t size, udma_channel_e channel,
+                       struct pi_task *task);
+
+/**
+ * \brief Transfer data.
+ *
+ * This function allows to send data using the periph.
+ * The transfer is executed immediately if there is no current transfer or no
+ * pending transfer. Otherwise, the transfer is enqueued in a fifo.
+ *
+ * \param driver_data    Pointer to driver info.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data buffer.
+ * \param task           Event task used to notify end of transfer.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval -1            Otherwise.
+ */
+static inline int __pi_uart_write(struct uart_itf_data_s *data, void *buffer,
+                                  uint32_t size, pi_task_t *callback)
+{
+    return __pi_uart_copy(data, (uint32_t) buffer, size, TX_CHANNEL, callback);
+}
+
+/**
+ * \brief Transfer data.
+ *
+ * This function allows to receive data using the periph.
+ * The transfer is executed immediately if there is no current transfer or no
+ * pending transfer. Otherwise, the transfer is enqueued in a fifo.
+ *
+ * \param driver_data    Pointer to driver info.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data buffer.
+ * \param task           Event task used to notify end of transfer.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval -1            Otherwise.
+ */
+static inline int __pi_uart_read(struct uart_itf_data_s *data, void *buffer,
+                                 uint32_t size, pi_task_t *callback)
+{
+   return  __pi_uart_copy(data, (uint32_t) buffer, size, RX_CHANNEL, callback);
+}
+
+
+
+#endif /* HAL_INCLUDE_HAL_UART_INTERNAL_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_periph.h

@@ -0,0 +1,154 @@
+/* THIS FILE HAS BEEN GENERATED, DO NOT MODIFY IT. */
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef HAL_INCLUDE_HAL_UART_PERIPH_H_
+#define HAL_INCLUDE_HAL_UART_PERIPH_H_
+#include "hal_udma_core_periph.h"
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** UART_Type Register Layout Typedef */
+typedef struct
+{
+	udma_channel_t rx; /**< UDMA RX channels struct. */
+	udma_channel_t tx; /**< UDMA TX channels struct. */
+	volatile uint32_t status; /**< Status register */
+	volatile uint32_t setup; /**< Configuration register */
+} uart_t;
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name STATUS */
+/* TX busy status flag */
+#define UART_STATUS_TX_BUSY_MASK                                     (0x1)
+#define UART_STATUS_TX_BUSY_SHIFT                                    (0)
+#define UART_STATUS_TX_BUSY(val)                                     (((uint32_t)(((uint32_t)(val)) << UART_STATUS_TX_BUSY_SHIFT)) & UART_STATUS_TX_BUSY_MASK)
+
+/* RX busy status flag */
+#define UART_STATUS_RX_BUSY_MASK                                     (0x2)
+#define UART_STATUS_RX_BUSY_SHIFT                                    (1)
+#define UART_STATUS_RX_BUSY(val)                                     (((uint32_t)(((uint32_t)(val)) << UART_STATUS_RX_BUSY_SHIFT)) & UART_STATUS_RX_BUSY_MASK)
+
+/* RX parity error status flag */
+#define UART_STATUS_RX_PE_MASK                                       (0x4)
+#define UART_STATUS_RX_PE_SHIFT                                      (2)
+#define UART_STATUS_RX_PE(val)                                       (((uint32_t)(((uint32_t)(val)) << UART_STATUS_RX_PE_SHIFT)) & UART_STATUS_RX_PE_MASK)
+
+
+/*! @name SETUP */
+/* Set parity generation and check:
+  - 1'b0: disable
+  - 1'b1: enable */
+#define UART_SETUP_PARITY_ENA_MASK                                   (0x1)
+#define UART_SETUP_PARITY_ENA_SHIFT                                  (0)
+#define UART_SETUP_PARITY_ENA(val)                                   (((uint32_t)(((uint32_t)(val)) << UART_SETUP_PARITY_ENA_SHIFT)) & UART_SETUP_PARITY_ENA_MASK)
+
+/* Set character length:
+  - 2'b00: 5 bits
+  - 2'b01: 6 bits
+  - 2'b10: 7 bits
+  - 2'b11: 8 bits */
+#define UART_SETUP_BIT_LENGTH_MASK                                   (0x6)
+#define UART_SETUP_BIT_LENGTH_SHIFT                                  (1)
+#define UART_SETUP_BIT_LENGTH(val)                                   (((uint32_t)(((uint32_t)(val)) << UART_SETUP_BIT_LENGTH_SHIFT)) & UART_SETUP_BIT_LENGTH_MASK)
+
+/* Set stop bits length:
+  - 2'b0: 1 stop bit
+  - 2'b1: 2 stop bits */
+#define UART_SETUP_STOP_BITS_MASK                                    (0x8)
+#define UART_SETUP_STOP_BITS_SHIFT                                   (3)
+#define UART_SETUP_STOP_BITS(val)                                    (((uint32_t)(((uint32_t)(val)) << UART_SETUP_STOP_BITS_SHIFT)) & UART_SETUP_STOP_BITS_MASK)
+
+/* Set TX transceiver state:
+  - 1'b0: disable
+  - 1'b1: enable */
+#define UART_SETUP_TX_ENA_MASK                                       (0x100)
+#define UART_SETUP_TX_ENA_SHIFT                                      (8)
+#define UART_SETUP_TX_ENA(val)                                       (((uint32_t)(((uint32_t)(val)) << UART_SETUP_TX_ENA_SHIFT)) & UART_SETUP_TX_ENA_MASK)
+
+/* Set RX transceiver state:
+  - 1'b0: disable
+  - 1'b1: enable */
+#define UART_SETUP_RX_ENA_MASK                                       (0x200)
+#define UART_SETUP_RX_ENA_SHIFT                                      (9)
+#define UART_SETUP_RX_ENA(val)                                       (((uint32_t)(((uint32_t)(val)) << UART_SETUP_RX_ENA_SHIFT)) & UART_SETUP_RX_ENA_MASK)
+
+/* Sets the clock divider ratio for the baud rate generator. */
+#define UART_SETUP_CLKDIV_MASK                                       (0xffff0000)
+#define UART_SETUP_CLKDIV_SHIFT                                      (16)
+#define UART_SETUP_CLKDIV(val)                                       (((uint32_t)(((uint32_t)(val)) << UART_SETUP_CLKDIV_SHIFT)) & UART_SETUP_CLKDIV_MASK)
+
+
+/*! @name STATUS */
+typedef union
+{
+    struct
+    {
+        /* TX busy status flag */
+        uint32_t tx_busy:1;
+        /* RX busy status flag */
+        uint32_t rx_busy:1;
+        /* RX parity error status flag */
+        uint32_t rx_pe:1;
+    } field;
+    uint32_t word;
+} uart_status_t;
+
+/*! @name SETUP */
+typedef union
+{
+    struct
+    {
+        /* Set parity generation and check:
+        - 1'b0: disable
+        - 1'b1: enable */
+        uint32_t parity_ena:1;
+        /* Set character length:
+        - 2'b00: 5 bits
+        - 2'b01: 6 bits
+        - 2'b10: 7 bits
+        - 2'b11: 8 bits */
+        uint32_t bit_length:2;
+        /* Set stop bits length:
+        - 2'b0: 1 stop bit
+        - 2'b1: 2 stop bits */
+        uint32_t stop_bits:1;
+        uint32_t reserved_0:4;
+        /* Set TX transceiver state:
+        - 1'b0: disable
+        - 1'b1: enable */
+        uint32_t tx_ena:1;
+        /* Set RX transceiver state:
+        - 1'b0: disable
+        - 1'b1: enable */
+        uint32_t rx_ena:1;
+        uint32_t reserved_1:6;
+        /* Sets the clock divider ratio for the baud rate generator. */
+        uint32_t clkdiv:16;
+    } field;
+    uint32_t word;
+} uart_setup_t;
+
+
+#endif /* HAL_INCLUDE_HAL_UART_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_uart_pi.h

@@ -0,0 +1,436 @@
+/*
+ * Copyright (C) 2018 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+
+#ifndef __PMSIS_DRIVERS_UART_H__
+#define __PMSIS_DRIVERS_UART_H__
+
+//#include "pmsis/pmsis_types.h"
+#include "hal_pmsis_types.h"
+
+/**
+ * @ingroup groupDrivers
+ */
+
+/**
+ * @defgroup UART UART
+ *
+ * \brief UART Universal Asynchronous Receiver Transmitter
+ *
+ * This API provides support for transferring data between an external UART
+ * device and the processor running this driver.
+ *
+ */
+
+/**
+ * @addtogroup UART
+ * @{
+ */
+
+/**
+ * \struct pi_uart_conf
+ *
+ * \brief UART device configuration structure.
+ *
+ * This structure is used to pass the desired UART configuration to the runtime
+ * when opening the device.
+ */
+struct pi_uart_conf
+{
+    uint32_t baudrate_bps;  /*!< Required baudrate, in baud per second. */
+    uint8_t stop_bit_count; /*!< Number of stop bits, 1 stop bit (default) or
+                              2 stop bits  */
+    uint8_t parity_mode;    /*!< 1 to activate it, 0 to deactivate it. */
+    uint8_t word_size;      /*!< Word size, in bits. */
+    uint8_t enable_rx;      /*!< 1 to activate reception, 0 to deactivate it. */
+    uint8_t enable_tx;      /*!< 1 to activate transmission, 0 to deactivate it. */
+    uint8_t uart_id;        /*!< Uart interface ID. */
+    uint8_t use_ctrl_flow;  /*!< 1 to activate control flow. */
+    uint8_t is_usart;       /*!< 1 to activate usart */
+};
+
+/**
+ * \enum pi_uart_stop_bits
+ *
+ * \brief Stop bits enum.
+ */
+enum pi_uart_stop_bits
+{
+    PI_UART_STOP_BITS_ONE = 0,  /*!< One stop bit. */
+    PI_UART_STOP_BITS_TWO = 1   /*!< Two stop bits. */
+};
+
+/**
+ * \enum pi_uart_parity_mode
+ *
+ * \brief Parity mode enum.
+ */
+enum pi_uart_parity_mode
+{
+    PI_UART_PARITY_DISABLE = 0, /*!< Disable parity mode. */
+    PI_UART_PARITY_ENABLE  = 1  /*!< Enable parity mode. */
+};
+
+/**
+ * \enum pi_uart_word_size
+ *
+ * \brief Bit length of each word.
+ */
+enum pi_uart_word_size
+{
+    PI_UART_WORD_SIZE_5_BITS = 0, /*!< 5 bits length. */
+    PI_UART_WORD_SIZE_6_BITS = 1, /*!< 6 bits length. */
+    PI_UART_WORD_SIZE_7_BITS = 2, /*!< 7 bits length. */
+    PI_UART_WORD_SIZE_8_BITS = 3  /*!< 8 bits length. */
+};
+
+
+/**
+ * \enum pi_uart_ioctl_cmd
+ *
+ * \brief UART ioctl commands.
+ *
+ * UART ioctl commands to configure, enable device.
+ */
+enum pi_uart_ioctl_cmd
+{
+    /**
+     * \brief Setup UART device.
+     *
+     * Setup UART with given conf.
+     * The parameter for this command is a struct pi_uart_conf.
+     *
+     * \param conf       Pointer to struct pi_uart_conf.
+     */
+    PI_UART_IOCTL_CONF_SETUP = 0,
+    /**
+     * \brief Abort RX transfers.
+     *
+     * Disable RX channel, abort current RX transfert,
+     * and flush all pending transferts.
+     *
+     * \note This function disables reception channel after clearing UDMA
+     *       channels. In order to send again data, the reception channel
+     *       must re-enabled.
+     */
+    PI_UART_IOCTL_ABORT_RX   = 1,
+    /**
+     * \brief Abort TX transfers.
+     *
+     * Disable TX channel, abort current TX transfert,
+     * and flush all pending transferts.
+     *
+     * \note This function disables transmission channel after clearing UDMA
+     *       channels. In order to send again data, the transmission channel
+     *       must re-enabled.
+     */
+    PI_UART_IOCTL_ABORT_TX   = 2,
+    /**
+     * \brief Enable reception.
+     *
+     * This command enables reception on UART device.
+     */
+    PI_UART_IOCTL_ENABLE_RX  = 3,
+    /**
+     * \brief Enable transmission.
+     *
+     * This command enables transmission on UART device.
+     */
+    PI_UART_IOCTL_ENABLE_TX  = 4
+};
+
+/**
+ * \brief UART cluster request structure.
+ *
+ * This structure is used by the runtime to manage a cluster remote copy with
+ * the UART. It must be instantiated once for each copy and must be kept
+ * alive until the copy is finished. It can be instantiated as a normal
+ * variable, for example as a global variable, a local one on the stack,
+ * or through a memory allocator.
+ */
+typedef struct pi_cl_uart_req_s pi_cl_uart_req_t;
+
+/**
+ * \brief Initialize a UART configuration with default values.
+ *
+ * This function can be called to get default values for all parameters before
+ * setting some of them.
+ * The structure containing the configuration must be kept alive until the uart
+ * device is opened.
+ *
+ * \param conf           Pointer to the UART configuration.
+ */
+void pi_uart_conf_init(struct pi_uart_conf *conf);
+
+/**
+ * \brief Open a UART device.
+ *
+ * This function must be called before the UART device can be used.
+ * It will do all the needed configuration to make it usable and initialize
+ * the handle used to refer to this opened device when calling other functions.
+ *
+ * \param device         Pointer to device structure of the device to open.
+ *
+ * \retval 0             If the operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ *
+ * \note This structure is allocated by the called and must be kept alive until the
+ *       device is closed.
+ */
+int pi_uart_open(struct pi_device *device);
+
+/**
+ * \brief Close an opened UART device.
+ *
+ * This function can be called to close an opened UART device once it is
+ * not needed anymore, in order to free all allocated resources. Once this
+ * function is called, the device is not accessible anymore and must be opened
+ * again before being used.
+ *
+ * \param device         Pointer to device structure of the device to close.
+ */
+void pi_uart_close(struct pi_device *device);
+
+/**
+ * \brief Dynamically change device configuration.
+ *
+ * This function allows to send different commands to UART device.
+ * The commands are listed above, cf. enum pi_uart_ioctl_cmd.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param cmd            Ioctl command.
+ * \param arg            Ioctl command args.
+ *
+ * \retval -1            If wrong ioctl command.
+ * \retval Value         Otherwise return value depending on ioctl command.
+ */
+int pi_uart_ioctl(struct pi_device *device, uint32_t cmd, void *arg);
+
+/**
+ * \brief Write data to an UART.
+ *
+ * This writes data to the specified UART.
+ * The caller is blocked until the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data to copy in bytes.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_write(struct pi_device *device, void *buffer, uint32_t size);
+
+/**
+ * \brief Read data from an UART.
+ *
+ * This reads data from the specified UART.
+ * The caller is blocked until the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data to copy in bytes.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_read(struct pi_device *device, void *buffer, uint32_t size);
+
+/**
+ * \brief Write a byte to an UART.
+ *
+ * This writes a byte to the specified UART.
+ * The caller is blocked until the transfer is finished.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param byte         Pointer to data buffer.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_write_byte(struct pi_device *device, uint8_t *byte);
+
+/**
+ * \brief Read a byte from an UART.
+ *
+ * This reads a byte from the specified UART.
+ * The caller is blocked until the transfer is finished.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param byte           Pointer to data buffer.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_read_byte(struct pi_device *device, uint8_t *byte);
+
+/**
+ * \brief Write data to an UART asynchronously.
+ *
+ * This writes data to the specified UART asynchronously.
+ * A task must be specified in order to specify how the caller should be
+ * notified when the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data to copy in bytes.
+ * \param callback       Event task used to notify the end of transfer. See the
+ *                       documentation of pi_task_t for more details.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_write_async(struct pi_device *device, void *buffer, uint32_t size,
+                        pi_task_t* callback);
+
+/**
+ * \brief Read data from an UART asynchronously.
+ *
+ * This reads data from the specified UART asynchronously.
+ * A task must be specified in order to specify how the caller should be
+ * notified when the transfer is finished.
+ * Depending on the chip, there may be some restrictions on the memory which
+ * can be used. Check the chip-specific documentation for more details.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data to copy in bytes.
+ * \param callback       Event task used to notify the end of transfer. See the
+ *                       documentation of pi_task_t for more details.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_read_async(struct pi_device *device, void *buffer, uint32_t size,
+                       pi_task_t* callback);
+
+/**
+ * \brief Write a byte to an UART asynchronously.
+ *
+ * This writes a byte to the specified UART asynchronously.
+ * A task must be specified in order to specify how the caller should be
+ * notified when the transfer is finished.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param byte           Pointer to data buffer.
+ * \param callback       Event task used to notify the end of transfer. See the
+ *                       documentation of pi_task_t for more details.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_uart_write_byte_async(struct pi_device *device, uint8_t *byte, pi_task_t* callback);
+
+
+/**
+ * \brief Write data to an UART from cluster side.
+ *
+ * This function implements the same feature as pi_uart_write but can be called
+ * from cluster side in order to expose the feature on the cluster.
+ * A pointer to a request structure must be provided so that the runtime can
+ * properly do the remote call.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data to copy in bytes.
+ * \param req            Request structure used for termination.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_cl_uart_write(pi_device_t *device, void *buffer, uint32_t size, pi_cl_uart_req_t *req);
+
+/**
+ * \brief Write a byte to an UART from cluster side.
+ *
+ * This function implements the same feature as pi_uart_write_byte but can be
+ * called from cluster side in order to expose the feature on the cluster.
+ * A pointer to a request structure must be provided so that the runtime can
+ * properly do the remote call.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param byte           Pointer to data buffer.
+ * \param req            Request structure used for termination.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_cl_uart_write_byte(pi_device_t *device, uint8_t *byte, pi_cl_uart_req_t *req);
+
+/**
+ * \brief Wait until the specified UART cluster write request has finished.
+ *
+ * This blocks the calling core until the specified cluster remote copy is
+ * finished.
+ *
+ * \param req            Request structure used for termination.
+ */
+//static inline void pi_cl_uart_write_wait(pi_cl_uart_req_t *req);
+
+/**
+ * \brief Read a byte from an UART from cluster side.
+ *
+ * This function implements the same feature as pi_uart_read_byte but can be
+ * called from cluster side in order to expose the feature on the cluster.
+ * A pointer to a request structure must be provided so that the runtime can
+ * properly do the remote call.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param buffer         Pointer to data buffer.
+ * \param size           Size of data to copy in bytes.
+ * \param req            Request structure used for termination.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_cl_uart_read(pi_device_t *device, void *buffer, uint32_t size, pi_cl_uart_req_t *req);
+
+/**
+ * \brief Read a byte from an UART.
+ *
+ * This reads a byte from the specified UART.
+ * The caller is blocked until the transfer is finished.
+ *
+ * \param device         Pointer to device descriptor of the UART device.
+ * \param byte           Pointer to data buffer.
+ * \param req            Request structure used for termination.
+ *
+ * \retval 0             If operation is successfull.
+ * \retval ERRNO         An error code otherwise.
+ */
+int pi_cl_uart_read_byte(pi_device_t *device, uint8_t *byte, pi_cl_uart_req_t *req);
+
+/**
+ * \brief Wait until the specified UART cluster read request has finished.
+ *
+ * This blocks the calling core until the specified cluster remote copy is
+ * finished.
+ *
+ * \param req            Request structure used for termination.
+ */
+//static inline void pi_cl_uart_read_wait(pi_cl_uart_req_t *req);
+
+/**
+ * @}
+ */
+
+#endif  /* __PMSIS_DRIVERS_UART_H__ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_cam_reg_defs.h

@@ -0,0 +1,204 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_CAMERA_H_
+#define __UDMA_CAMERA_H_
+
+//---------------------------------//
+//
+// Module: UDMA_CAMERA
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t rx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 32;
+    } rx_saddr_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t rx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } rx_size_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t rx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } rx_cfg_b;
+  };
+  __I uint32_t    unused0[5];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t cfg_glob;
+    struct {
+      __IO uint32_t  framedrop_en :  1;
+      __IO uint32_t  framedrop_val :  6;
+      __IO uint32_t  framewindow_en :  1;
+      __IO uint32_t  format     :  3;
+      __IO uint32_t  shift      :  4;
+      __IO uint32_t             : 16;
+      __IO uint32_t  en         :  1;
+    } cfg_glob_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t cfg_ll;
+    struct {
+      __IO uint32_t  framewindow_llx : 16;
+      __IO uint32_t  framewindow_lly : 16;
+    } cfg_ll_b;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t cfg_ur;
+    struct {
+      __IO uint32_t  framewindow_urx : 16;
+      __IO uint32_t  framewindow_ury : 16;
+    } cfg_ur_b;
+  };
+
+  // Offset = 0x002c
+  union {
+    __IO uint32_t cfg_size;
+    struct {
+      __IO uint32_t             : 16;
+      __IO uint32_t  rowlen     : 16;
+    } cfg_size_b;
+  };
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t cfg_filter;
+    struct {
+      __IO uint32_t             :  8;
+      __IO uint32_t  b_coeff    :  8;
+      __IO uint32_t  g_coeff    :  8;
+      __IO uint32_t  r_coeff    :  8;
+    } cfg_filter_b;
+  };
+
+  // Offset = 0x0034
+  union {
+    __IO uint32_t vsync_polarity;
+    struct {
+      __IO uint32_t  vsync_polarity :  1;
+    } vsync_polarity_b;
+  };
+} UdmaCamera_t;
+
+
+#define REG_RX_SADDR                   0x00
+#define   REG_RX_SADDR_SADDR_LSB                   0
+#define   REG_RX_SADDR_SADDR_MASK                  0xffffffff
+#define REG_RX_SIZE                    0x04
+#define   REG_RX_SIZE_SIZE_LSB                     0
+#define   REG_RX_SIZE_SIZE_MASK                    0xffff
+#define REG_RX_CFG                     0x08
+#define   REG_RX_CFG_CLR_LSB                       5
+#define   REG_RX_CFG_CLR_MASK                      0x1
+#define   REG_RX_CFG_PENDING_LSB                   5
+#define   REG_RX_CFG_PENDING_MASK                  0x1
+#define   REG_RX_CFG_EN_LSB                        4
+#define   REG_RX_CFG_EN_MASK                       0x1
+#define   REG_RX_CFG_DATASIZE_LSB                  1
+#define   REG_RX_CFG_DATASIZE_MASK                 0x3
+#define   REG_RX_CFG_CONTINUOUS_LSB                0
+#define   REG_RX_CFG_CONTINUOUS_MASK               0x1
+#define REG_CFG_GLOB                   0x20
+#define   REG_CFG_GLOB_EN_LSB                      31
+#define   REG_CFG_GLOB_EN_MASK                     0x1
+#define   REG_CFG_GLOB_SHIFT_LSB                   11
+#define   REG_CFG_GLOB_SHIFT_MASK                  0xf
+#define   REG_CFG_GLOB_FORMAT_LSB                  8
+#define   REG_CFG_GLOB_FORMAT_MASK                 0x7
+#define   REG_CFG_GLOB_FRAMEWINDOW_EN_LSB          7
+#define   REG_CFG_GLOB_FRAMEWINDOW_EN_MASK         0x1
+#define   REG_CFG_GLOB_FRAMEDROP_VAL_LSB           1
+#define   REG_CFG_GLOB_FRAMEDROP_VAL_MASK          0x3f
+#define   REG_CFG_GLOB_FRAMEDROP_EN_LSB            0
+#define   REG_CFG_GLOB_FRAMEDROP_EN_MASK           0x1
+#define REG_CFG_LL                     0x24
+#define   REG_CFG_LL_FRAMEWINDOW_LLY_LSB           16
+#define   REG_CFG_LL_FRAMEWINDOW_LLY_MASK          0xffff
+#define   REG_CFG_LL_FRAMEWINDOW_LLX_LSB           0
+#define   REG_CFG_LL_FRAMEWINDOW_LLX_MASK          0xffff
+#define REG_CFG_UR                     0x28
+#define   REG_CFG_UR_FRAMEWINDOW_URY_LSB           16
+#define   REG_CFG_UR_FRAMEWINDOW_URY_MASK          0xffff
+#define   REG_CFG_UR_FRAMEWINDOW_URX_LSB           0
+#define   REG_CFG_UR_FRAMEWINDOW_URX_MASK          0xffff
+#define REG_CFG_SIZE                   0x2C
+#define   REG_CFG_SIZE_ROWLEN_LSB                  16
+#define   REG_CFG_SIZE_ROWLEN_MASK                 0xffff
+#define REG_CFG_FILTER                 0x30
+#define   REG_CFG_FILTER_R_COEFF_LSB               16
+#define   REG_CFG_FILTER_R_COEFF_MASK              0xff
+#define   REG_CFG_FILTER_G_COEFF_LSB               8
+#define   REG_CFG_FILTER_G_COEFF_MASK              0xff
+#define   REG_CFG_FILTER_B_COEFF_LSB               8
+#define   REG_CFG_FILTER_B_COEFF_MASK              0xff
+#define REG_VSYNC_POLARITY             0x34
+#define   REG_VSYNC_POLARITY_VSYNC_POLARITY_LSB    0
+#define   REG_VSYNC_POLARITY_VSYNC_POLARITY_MASK   0x1
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_CAMERA_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_core_periph.h

@@ -0,0 +1,384 @@
+/*
+ * Copyright (C) 2019 ETH Zurich, University of Bologna
+ * and GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef HAL_INCLUDE_HAL_UDMA_CORE_PERIPH_H_
+#define HAL_INCLUDE_HAL_UDMA_CORE_PERIPH_H_
+
+#include <stdint.h>
+
+/* ----------------------------------------------------------------------------
+   -- UDMA_CORE Peripheral Access Layer --
+   ---------------------------------------------------------------------------- */
+
+/** UDMA_CORE_Type Register Layout Typedef */
+/* TODO: refactor this really not good code */
+typedef struct
+{
+	volatile uint32_t saddr; /**< RX/TX/CMD Channel uDMA transfer address of associated buffer */
+	volatile uint32_t size; /**< RX/TX/CMD Channel uDMA transfer size of buffer */
+	volatile uint32_t cfg; /**< RX/TX/CMD Channel uDMA transfer configuration */
+	volatile uint32_t initcfg; /**< Not used. */
+} udma_channel_t;
+
+
+typedef enum
+{
+	RX_CHANNEL      = 0,
+	TX_CHANNEL      = 1,
+	COMMAND_CHANNEL = 2
+} udma_channel_e;
+
+/* ----------------------------------------------------------------------------
+   -- UDMA_CORE Register Bitfield Access --
+   ---------------------------------------------------------------------------- */
+
+/*! @name RX_SADDR */
+/* Configure pointer to memory buffer:
+  - Read: value of the pointer until transfer is over. Else returns 0
+  - Write: set Address Pointer to memory buffer start address */
+#define UDMA_CORE_RX_SADDR_RX_SADDR_MASK                             (0x1fffff)
+#define UDMA_CORE_RX_SADDR_RX_SADDR_SHIFT                            (0)
+#define UDMA_CORE_RX_SADDR_RX_SADDR(val)                             (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SADDR_RX_SADDR_SHIFT)) & UDMA_CORE_RX_SADDR_RX_SADDR_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_RX_SADDR_RESERVED_0_MASK                           (0xffe00000)
+#define UDMA_CORE_RX_SADDR_RESERVED_0_SHIFT                          (21)
+#define UDMA_CORE_RX_SADDR_RESERVED_0(val)                           (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SADDR_RESERVED_0_SHIFT)) & UDMA_CORE_RX_SADDR_RESERVED_0_MASK)
+
+
+/*! @name RX_SIZE */
+/* Buffer size in byte. (128kBytes maximum)
+  - Read: buffer size left
+  - Write: set buffer size */
+#define UDMA_CORE_RX_SIZE_RX_SIZE_MASK                               (0xfffff)
+#define UDMA_CORE_RX_SIZE_RX_SIZE_SHIFT                              (0)
+#define UDMA_CORE_RX_SIZE_RX_SIZE(val)                               (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SIZE_RX_SIZE_SHIFT)) & UDMA_CORE_RX_SIZE_RX_SIZE_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_RX_SIZE_RESERVED_0_MASK                            (0xfff00000)
+#define UDMA_CORE_RX_SIZE_RESERVED_0_SHIFT                           (20)
+#define UDMA_CORE_RX_SIZE_RESERVED_0(val)                            (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_SIZE_RESERVED_0_SHIFT)) & UDMA_CORE_RX_SIZE_RESERVED_0_MASK)
+
+
+/*! @name RX_CFG */
+/* Channel continuous mode:
+  - 1'b0: disable
+  - 1'b1: enable
+  At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */
+#define UDMA_CORE_RX_CFG_CONTINOUS_MASK                              (0x1)
+#define UDMA_CORE_RX_CFG_CONTINOUS_SHIFT                             (0)
+#define UDMA_CORE_RX_CFG_CONTINOUS(val)                              (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_CONTINOUS_SHIFT)) & UDMA_CORE_RX_CFG_CONTINOUS_MASK)
+
+/* Channel transfer size used to increment uDMA buffer address pointer:
+  - 2'b00: +1 (8 bits)
+  - 2'b01: +2 (16 bits)
+  - 2'b10: +4 (32 bits)
+  - 2'b11: +0 */
+#define UDMA_CORE_RX_CFG_DATASIZE_MASK                               (0x6)
+#define UDMA_CORE_RX_CFG_DATASIZE_SHIFT                              (1)
+#define UDMA_CORE_RX_CFG_DATASIZE(val)                               (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_DATASIZE_SHIFT)) & UDMA_CORE_RX_CFG_DATASIZE_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_RX_CFG_RESERVED_0_MASK                             (0x8)
+#define UDMA_CORE_RX_CFG_RESERVED_0_SHIFT                            (3)
+#define UDMA_CORE_RX_CFG_RESERVED_0(val)                             (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_RESERVED_0_SHIFT)) & UDMA_CORE_RX_CFG_RESERVED_0_MASK)
+
+/* Channel enable and start transfer:
+  - 1'b0: disable
+  - 1'b1: enable
+  This signal is used also to queue a transfer if one is already ongoing. */
+#define UDMA_CORE_RX_CFG_EN_MASK                                     (0x10)
+#define UDMA_CORE_RX_CFG_EN_SHIFT                                    (4)
+#define UDMA_CORE_RX_CFG_EN(val)                                     (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_EN_SHIFT)) & UDMA_CORE_RX_CFG_EN_MASK)
+
+/* Transfer pending in queue status flag:
+  - 1'b0: no pending transfer in the queue
+  - 1'b1: pending transfer in the queue */
+#define UDMA_CORE_RX_CFG_PENDING_MASK                                (0x20)
+#define UDMA_CORE_RX_CFG_PENDING_SHIFT                               (5)
+#define UDMA_CORE_RX_CFG_PENDING(val)                                (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_PENDING_SHIFT)) & UDMA_CORE_RX_CFG_PENDING_MASK)
+
+/* Channel clear and stop transfer:
+  - 1'b0: disable
+  - 1'b1: stop and clear the on-going transfer */
+#define UDMA_CORE_RX_CFG_CLR_MASK                                    (0x40)
+#define UDMA_CORE_RX_CFG_CLR_SHIFT                                   (6)
+#define UDMA_CORE_RX_CFG_CLR(val)                                    (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_CLR_SHIFT)) & UDMA_CORE_RX_CFG_CLR_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_RX_CFG_RESERVED_1_MASK                             (0xffffff80)
+#define UDMA_CORE_RX_CFG_RESERVED_1_SHIFT                            (7)
+#define UDMA_CORE_RX_CFG_RESERVED_1(val)                             (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_CFG_RESERVED_1_SHIFT)) & UDMA_CORE_RX_CFG_RESERVED_1_MASK)
+
+
+/*! @name RX_INITCFG */
+/* Reserved/Not used. */
+#define UDMA_CORE_RX_INITCFG_RESERVED_0_MASK                         (0xffffffff)
+#define UDMA_CORE_RX_INITCFG_RESERVED_0_SHIFT                        (0)
+#define UDMA_CORE_RX_INITCFG_RESERVED_0(val)                         (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_RX_INITCFG_RESERVED_0_SHIFT)) & UDMA_CORE_RX_INITCFG_RESERVED_0_MASK)
+
+
+/*! @name TX_SADDR */
+/* Configure pointer to memory buffer:
+  - Read: value of the pointer until transfer is over. Else returns 0
+  - Write: set Address Pointer to memory buffer start address */
+#define UDMA_CORE_TX_SADDR_TX_SADDR_MASK                             (0x1fffff)
+#define UDMA_CORE_TX_SADDR_TX_SADDR_SHIFT                            (0)
+#define UDMA_CORE_TX_SADDR_TX_SADDR(val)                             (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SADDR_TX_SADDR_SHIFT)) & UDMA_CORE_TX_SADDR_TX_SADDR_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_TX_SADDR_RESERVED_0_MASK                           (0xffe00000)
+#define UDMA_CORE_TX_SADDR_RESERVED_0_SHIFT                          (21)
+#define UDMA_CORE_TX_SADDR_RESERVED_0(val)                           (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SADDR_RESERVED_0_SHIFT)) & UDMA_CORE_TX_SADDR_RESERVED_0_MASK)
+
+
+/*! @name TX_SIZE */
+/* Buffer size in byte. (128kBytes maximum)
+  - Read: buffer size left
+  - Write: set buffer size */
+#define UDMA_CORE_TX_SIZE_TX_SIZE_MASK                               (0xfffff)
+#define UDMA_CORE_TX_SIZE_TX_SIZE_SHIFT                              (0)
+#define UDMA_CORE_TX_SIZE_TX_SIZE(val)                               (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SIZE_TX_SIZE_SHIFT)) & UDMA_CORE_TX_SIZE_TX_SIZE_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_TX_SIZE_RESERVED_0_MASK                            (0xfff00000)
+#define UDMA_CORE_TX_SIZE_RESERVED_0_SHIFT                           (20)
+#define UDMA_CORE_TX_SIZE_RESERVED_0(val)                            (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_SIZE_RESERVED_0_SHIFT)) & UDMA_CORE_TX_SIZE_RESERVED_0_MASK)
+
+
+/*! @name TX_CFG */
+/* Channel continuous mode:
+  - 1'b0: disable
+  - 1'b1: enable
+  At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */
+#define UDMA_CORE_TX_CFG_CONTINOUS_MASK                              (0x1)
+#define UDMA_CORE_TX_CFG_CONTINOUS_SHIFT                             (0)
+#define UDMA_CORE_TX_CFG_CONTINOUS(val)                              (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_CONTINOUS_SHIFT)) & UDMA_CORE_TX_CFG_CONTINOUS_MASK)
+
+/* Channel transfer size used to increment uDMA buffer address pointer:
+  - 2'b00: +1 (8 bits)
+  - 2'b01: +2 (16 bits)
+  - 2'b10: +4 (32 bits)
+  - 2'b11: +0 */
+#define UDMA_CORE_TX_CFG_DATASIZE_MASK                               (0x6)
+#define UDMA_CORE_TX_CFG_DATASIZE_SHIFT                              (1)
+#define UDMA_CORE_TX_CFG_DATASIZE(val)                               (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_DATASIZE_SHIFT)) & UDMA_CORE_TX_CFG_DATASIZE_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_TX_CFG_RESERVED_0_MASK                             (0x8)
+#define UDMA_CORE_TX_CFG_RESERVED_0_SHIFT                            (3)
+#define UDMA_CORE_TX_CFG_RESERVED_0(val)                             (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_RESERVED_0_SHIFT)) & UDMA_CORE_TX_CFG_RESERVED_0_MASK)
+
+/* Channel enable and start transfer:
+  - 1'b0: disable
+  - 1'b1: enable
+  This signal is used also to queue a transfer if one is already ongoing. */
+#define UDMA_CORE_TX_CFG_EN_MASK                                     (0x10)
+#define UDMA_CORE_TX_CFG_EN_SHIFT                                    (4)
+#define UDMA_CORE_TX_CFG_EN(val)                                     (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_EN_SHIFT)) & UDMA_CORE_TX_CFG_EN_MASK)
+
+/* Transfer pending in queue status flag:
+  - 1'b0: no pending transfer in the queue
+  - 1'b1: pending transfer in the queue */
+#define UDMA_CORE_TX_CFG_PENDING_MASK                                (0x20)
+#define UDMA_CORE_TX_CFG_PENDING_SHIFT                               (5)
+#define UDMA_CORE_TX_CFG_PENDING(val)                                (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_PENDING_SHIFT)) & UDMA_CORE_TX_CFG_PENDING_MASK)
+
+/* Channel clear and stop transfer:
+  - 1'b0: disable
+  - 1'b1: stop and clear the on-going transfer */
+#define UDMA_CORE_TX_CFG_CLR_MASK                                    (0x40)
+#define UDMA_CORE_TX_CFG_CLR_SHIFT                                   (6)
+#define UDMA_CORE_TX_CFG_CLR(val)                                    (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_CLR_SHIFT)) & UDMA_CORE_TX_CFG_CLR_MASK)
+
+/* Reserved/Not used. */
+#define UDMA_CORE_TX_CFG_RESERVED_1_MASK                             (0xffffff80)
+#define UDMA_CORE_TX_CFG_RESERVED_1_SHIFT                            (7)
+#define UDMA_CORE_TX_CFG_RESERVED_1(val)                             (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_CFG_RESERVED_1_SHIFT)) & UDMA_CORE_TX_CFG_RESERVED_1_MASK)
+
+
+/*! @name TX_INITCFG */
+/* Reserved/Not used. */
+#define UDMA_CORE_TX_INITCFG_RESERVED_0_MASK                         (0xffffffff)
+#define UDMA_CORE_TX_INITCFG_RESERVED_0_SHIFT                        (0)
+#define UDMA_CORE_TX_INITCFG_RESERVED_0(val)                         (((uint32_t)(((uint32_t)(val)) << UDMA_CORE_TX_INITCFG_RESERVED_0_SHIFT)) & UDMA_CORE_TX_INITCFG_RESERVED_0_MASK)
+
+
+
+
+/*! @name RX_SADDR */
+typedef union
+{
+    struct
+    {
+        /* Configure pointer to memory buffer:
+        - Read: value of the pointer until transfer is over. Else returns 0
+        - Write: set Address Pointer to memory buffer start address */
+        uint32_t rx_saddr:21;
+        /* Reserved/Not used. */
+        uint32_t reserved_0:11;
+    } field;
+    uint32_t word;
+} udma_core_rx_saddr_t;
+
+/*! @name RX_SIZE */
+typedef union
+{
+    struct
+    {
+        /* Buffer size in byte. (128kBytes maximum)
+        - Read: buffer size left
+        - Write: set buffer size */
+        uint32_t rx_size:20;
+        /* Reserved/Not used. */
+        uint32_t reserved_0:12;
+    } field;
+    uint32_t word;
+} udma_core_rx_size_t;
+
+/*! @name RX_CFG */
+typedef union
+{
+    struct
+    {
+        /* Channel continuous mode:
+        - 1'b0: disable
+        - 1'b1: enable
+        At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */
+        uint32_t continous:1;
+        /* Channel transfer size used to increment uDMA buffer address pointer:
+        - 2'b00: +1 (8 bits)
+        - 2'b01: +2 (16 bits)
+        - 2'b10: +4 (32 bits)
+        - 2'b11: +0 */
+        uint32_t datasize:2;
+        /* Reserved/Not used. */
+        uint32_t reserved_0:1;
+        /* Channel enable and start transfer:
+        - 1'b0: disable
+        - 1'b1: enable
+        This signal is used also to queue a transfer if one is already ongoing. */
+        uint32_t en:1;
+        /* Transfer pending in queue status flag:
+        - 1'b0: no pending transfer in the queue
+        - 1'b1: pending transfer in the queue */
+        uint32_t pending:1;
+        /* Channel clear and stop transfer:
+        - 1'b0: disable
+        - 1'b1: stop and clear the on-going transfer */
+        uint32_t clr:1;
+        /* Reserved/Not used. */
+        uint32_t reserved_1:25;
+    } field;
+    uint32_t word;
+} udma_core_rx_cfg_t;
+
+/*! @name RX_INITCFG */
+typedef union
+{
+    struct
+    {
+        /* Reserved/Not used. */
+        uint32_t reserved_0:32;
+    } field;
+    uint32_t word;
+} udma_core_rx_initcfg_t;
+
+/*! @name TX_SADDR */
+typedef union
+{
+    struct
+    {
+        /* Configure pointer to memory buffer:
+        - Read: value of the pointer until transfer is over. Else returns 0
+        - Write: set Address Pointer to memory buffer start address */
+        uint32_t tx_saddr:21;
+        /* Reserved/Not used. */
+        uint32_t reserved_0:11;
+    } field;
+    uint32_t word;
+} udma_core_tx_saddr_t;
+
+/*! @name TX_SIZE */
+typedef union
+{
+    struct
+    {
+        /* Buffer size in byte. (128kBytes maximum)
+        - Read: buffer size left
+        - Write: set buffer size */
+        uint32_t tx_size:20;
+        /* Reserved/Not used. */
+        uint32_t reserved_0:12;
+    } field;
+    uint32_t word;
+} udma_core_tx_size_t;
+
+/*! @name TX_CFG */
+typedef union
+{
+    struct
+    {
+        /* Channel continuous mode:
+        - 1'b0: disable
+        - 1'b1: enable
+        At the end of the buffer the uDMA reloads the address and size and starts a new transfer. */
+        uint32_t continous:1;
+        /* Channel transfer size used to increment uDMA buffer address pointer:
+        - 2'b00: +1 (8 bits)
+        - 2'b01: +2 (16 bits)
+        - 2'b10: +4 (32 bits)
+        - 2'b11: +0 */
+        uint32_t datasize:2;
+        /* Reserved/Not used. */
+        uint32_t reserved_0:1;
+        /* Channel enable and start transfer:
+        - 1'b0: disable
+        - 1'b1: enable
+        This signal is used also to queue a transfer if one is already ongoing. */
+        uint32_t en:1;
+        /* Transfer pending in queue status flag:
+        - 1'b0: no pending transfer in the queue
+        - 1'b1: pending transfer in the queue */
+        uint32_t pending:1;
+        /* Channel clear and stop transfer:
+        - 1'b0: disable
+        - 1'b1: stop and clear the on-going transfer */
+        uint32_t clr:1;
+        /* Reserved/Not used. */
+        uint32_t reserved_1:25;
+    } field;
+    uint32_t word;
+} udma_core_tx_cfg_t;
+
+/*! @name TX_INITCFG */
+typedef union
+{
+    struct
+    {
+        /* Reserved/Not used. */
+        uint32_t reserved_0:32;
+    } field;
+    uint32_t word;
+} udma_core_tx_initcfg_t;
+
+
+#define UDMA_CORE_CFG_DATASIZE_8                                     (0x0)
+#define UDMA_CORE_CFG_DATASIZE_16                                    (0x1)
+#define UDMA_CORE_CFG_DATASIZE_32                                    (0x2)
+
+#endif /* HAL_INCLUDE_HAL_UDMA_CORE_PERIPH_H_ */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_ctrl_reg_defs.h

@@ -0,0 +1,103 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_CTRL_H_
+#define __UDMA_CTRL_H_
+
+//---------------------------------//
+//
+// Module: UDMA_CTRL
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t reg_cg;
+    struct {
+      __IO uint32_t  periph_clk_enable : 32;
+    } reg_cg_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t reg_cfg_evt;
+    struct {
+      __IO uint32_t  cmp_event0 :  8;
+      __IO uint32_t  cmp_event1 :  8;
+      __IO uint32_t  cmp_event2 :  8;
+      __IO uint32_t  cmp_event3 :  8;
+    } reg_cfg_evt_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t reg_rst;
+    struct {
+      __IO uint32_t  periph_reset : 32;
+    } reg_rst_b;
+  };
+} UdmaCtrl_t;
+
+
+#define REG_REG_CG                     0x000
+#define   REG_REG_CG_PERIPH_CLK_ENABLE_LSB         0
+#define   REG_REG_CG_PERIPH_CLK_ENABLE_MASK        0xffffffff
+#define REG_REG_CFG_EVT                0x004
+#define   REG_REG_CFG_EVT_CMP_EVENT3_LSB           24
+#define   REG_REG_CFG_EVT_CMP_EVENT3_MASK          0xff
+#define   REG_REG_CFG_EVT_CMP_EVENT2_LSB           16
+#define   REG_REG_CFG_EVT_CMP_EVENT2_MASK          0xff
+#define   REG_REG_CFG_EVT_CMP_EVENT1_LSB           8
+#define   REG_REG_CFG_EVT_CMP_EVENT1_MASK          0xff
+#define   REG_REG_CFG_EVT_CMP_EVENT0_LSB           0
+#define   REG_REG_CFG_EVT_CMP_EVENT0_MASK          0xff
+#define REG_REG_RST                    0x008
+#define   REG_REG_RST_PERIPH_RESET_LSB             0
+#define   REG_REG_RST_PERIPH_RESET_MASK            0xffffffff
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_CTRL_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_i2cm_reg_defs.h

@@ -0,0 +1,174 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_I2CM_H_
+#define __UDMA_I2CM_H_
+
+//---------------------------------//
+//
+// Module: UDMA_I2CM
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t rx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } rx_saddr_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t rx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } rx_size_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t rx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t             :  3;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } rx_cfg_b;
+  };
+  __I uint32_t    unused0[1];
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t tx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } tx_saddr_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t tx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } tx_size_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t tx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t             :  3;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } tx_cfg_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t status;
+    struct {
+      __IO uint32_t  busy       :  1;
+      __IO uint32_t  al         :  1;
+    } status_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t setup;
+    struct {
+      __IO uint32_t  reset      :  1;
+    } setup_b;
+  };
+} UdmaI2cm_t;
+
+
+#define REG_RX_SADDR                   0x00
+#define   REG_RX_SADDR_SADDR_LSB                   0
+#define   REG_RX_SADDR_SADDR_MASK                  0xfff
+#define REG_RX_SIZE                    0x04
+#define   REG_RX_SIZE_SIZE_LSB                     0
+#define   REG_RX_SIZE_SIZE_MASK                    0xffff
+#define REG_RX_CFG                     0x08
+#define   REG_RX_CFG_CLR_LSB                       6
+#define   REG_RX_CFG_CLR_MASK                      0x1
+#define   REG_RX_CFG_PENDING_LSB                   5
+#define   REG_RX_CFG_PENDING_MASK                  0x1
+#define   REG_RX_CFG_EN_LSB                        4
+#define   REG_RX_CFG_EN_MASK                       0x1
+#define   REG_RX_CFG_CONTINUOUS_LSB                0
+#define   REG_RX_CFG_CONTINUOUS_MASK               0x1
+#define REG_TX_SADDR                   0x10
+#define   REG_TX_SADDR_SADDR_LSB                   0
+#define   REG_TX_SADDR_SADDR_MASK                  0xfff
+#define REG_TX_SIZE                    0x14
+#define   REG_TX_SIZE_SIZE_LSB                     0
+#define   REG_TX_SIZE_SIZE_MASK                    0xffff
+#define REG_TX_CFG                     0x18
+#define   REG_TX_CFG_CLR_LSB                       6
+#define   REG_TX_CFG_CLR_MASK                      0x1
+#define   REG_TX_CFG_PENDING_LSB                   5
+#define   REG_TX_CFG_PENDING_MASK                  0x1
+#define   REG_TX_CFG_EN_LSB                        4
+#define   REG_TX_CFG_EN_MASK                       0x1
+#define   REG_TX_CFG_CONTINUOUS_LSB                0
+#define   REG_TX_CFG_CONTINUOUS_MASK               0x1
+#define REG_STATUS                     0x20
+#define   REG_STATUS_AL_LSB                        1
+#define   REG_STATUS_AL_MASK                       0x1
+#define   REG_STATUS_BUSY_LSB                      0
+#define   REG_STATUS_BUSY_MASK                     0x1
+#define REG_SETUP                      0x24
+#define   REG_SETUP_RESET_LSB                      0
+#define   REG_SETUP_RESET_MASK                     0x1
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_I2CM_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_qspi_reg_defs.h

@@ -0,0 +1,213 @@
+ /*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_QSPI_H_
+#define __UDMA_QSPI_H_
+
+//---------------------------------//
+//
+// Module: UDMA_QSPI
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t rx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } rx_saddr_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t rx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } rx_size_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t rx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } rx_cfg_b;
+  };
+  __I uint32_t    unused0[1];
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t tx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } tx_saddr_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t tx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } tx_size_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t tx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } tx_cfg_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t cmd_saddr;
+    struct {
+      __IO uint32_t  saddr      : 32;
+    } cmd_saddr_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t cmd_size;
+    struct {
+      __IO uint32_t  size       : 21;
+    } cmd_size_b;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t cmd_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } cmd_cfg_b;
+  };
+  __I uint32_t    unused2[1];
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t status;
+    struct {
+      __IO uint32_t  busy       :  2;
+    } status_b;
+  };
+} UdmaQspi_t;
+
+
+#define REG_RX_SADDR                   0x00
+#define   REG_RX_SADDR_SADDR_LSB                   0
+#define   REG_RX_SADDR_SADDR_MASK                  0xfff
+#define REG_RX_SIZE                    0x04
+#define   REG_RX_SIZE_SIZE_LSB                     0
+#define   REG_RX_SIZE_SIZE_MASK                    0xffff
+#define REG_RX_CFG                     0x08
+#define   REG_RX_CFG_CLR_LSB                       6
+#define   REG_RX_CFG_CLR_MASK                      0x1
+#define   REG_RX_CFG_PENDING_LSB                   5
+#define   REG_RX_CFG_PENDING_MASK                  0x1
+#define   REG_RX_CFG_EN_LSB                        4
+#define   REG_RX_CFG_EN_MASK                       0x1
+#define   REG_RX_CFG_DATASIZE_LSB                  1
+#define   REG_RX_CFG_DATASIZE_MASK                 0x3
+#define   REG_RX_CFG_CONTINUOUS_LSB                0
+#define   REG_RX_CFG_CONTINUOUS_MASK               0x1
+#define REG_TX_SADDR                   0x10
+#define   REG_TX_SADDR_SADDR_LSB                   0
+#define   REG_TX_SADDR_SADDR_MASK                  0xfff
+#define REG_TX_SIZE                    0x14
+#define   REG_TX_SIZE_SIZE_LSB                     0
+#define   REG_TX_SIZE_SIZE_MASK                    0xffff
+#define REG_TX_CFG                     0x18
+#define   REG_TX_CFG_CLR_LSB                       6
+#define   REG_TX_CFG_CLR_MASK                      0x1
+#define   REG_TX_CFG_PENDING_LSB                   5
+#define   REG_TX_CFG_PENDING_MASK                  0x1
+#define   REG_TX_CFG_EN_LSB                        4
+#define   REG_TX_CFG_EN_MASK                       0x1
+#define   REG_TX_CFG_DATASIZE_LSB                  1
+#define   REG_TX_CFG_DATASIZE_MASK                 0x3
+#define   REG_TX_CFG_CONTINUOUS_LSB                0
+#define   REG_TX_CFG_CONTINUOUS_MASK               0x1
+#define REG_CMD_SADDR                  0x20
+#define   REG_CMD_SADDR_SADDR_LSB                  0
+#define   REG_CMD_SADDR_SADDR_MASK                 0xffffffff
+#define REG_CMD_SIZE                   0x24
+#define   REG_CMD_SIZE_SIZE_LSB                    0
+#define   REG_CMD_SIZE_SIZE_MASK                   0x1fffff
+#define REG_CMD_CFG                    0x28
+#define   REG_CMD_CFG_CLR_LSB                      6
+#define   REG_CMD_CFG_CLR_MASK                     0x1
+#define   REG_CMD_CFG_PENDING_LSB                  5
+#define   REG_CMD_CFG_PENDING_MASK                 0x1
+#define   REG_CMD_CFG_EN_LSB                       4
+#define   REG_CMD_CFG_EN_MASK                      0x1
+#define   REG_CMD_CFG_DATASIZE_LSB                 1
+#define   REG_CMD_CFG_DATASIZE_MASK                0x3
+#define   REG_CMD_CFG_CONTINUOUS_LSB               0
+#define   REG_CMD_CFG_CONTINUOUS_MASK              0x1
+#define REG_STATUS                     0x30
+#define   REG_STATUS_BUSY_LSB                      0
+#define   REG_STATUS_BUSY_MASK                     0x3
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_QSPI_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_sdio_reg_defs.h

@@ -0,0 +1,292 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_SDIO_H_
+#define __UDMA_SDIO_H_
+
+//---------------------------------//
+//
+// Module: UDMA_SDIO
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t rx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 32;	// 21 localparam L2_AWIDTH_NOAL = L2_ADDR_WIDTH + 2;
+    } rx_saddr_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t rx_size;
+    struct {
+      __IO uint32_t  size       : 20;//16; //should be 20 bit. udma 1MB addressing.
+    } rx_size_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t rx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      //__IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } rx_cfg_b;
+  };
+  __I uint32_t    unused0[1];
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t tx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } tx_saddr_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t tx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } tx_size_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t tx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      //__IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } tx_cfg_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t cmd_op;
+    struct {
+      __IO uint32_t  cmd_rsp_type :  3;
+      __IO uint32_t             :  5;
+      __IO uint32_t  cmd_op     :  6;
+    } cmd_op_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t cmd_arg;
+    struct {
+      __IO uint32_t  cmd_arg    : 32;
+    } cmd_arg_b;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t data_setup;
+    struct {
+      __IO uint32_t  data_en    :  1;
+      __IO uint32_t  data_rwn   :  1;
+      __IO uint32_t  data_quad  :  1;
+      __IO uint32_t             :  5;
+      __IO uint32_t  block_num  :  8;
+      __IO uint32_t  block_size : 10;
+    } data_setup_b;
+  };
+
+  // Offset = 0x002c
+  union {
+    __IO uint32_t start;
+    struct {
+      __IO uint32_t  start      :  1;
+    } start_b;
+  };
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t rsp0;
+    struct {
+      __IO uint32_t  rsp0       : 32;
+    } rsp0_b;
+  };
+
+  // Offset = 0x0034
+  union {
+    __IO uint32_t rsp1;
+    struct {
+      __IO uint32_t  rsp1       : 32;
+    } rsp1_b;
+  };
+
+  // Offset = 0x0038
+  union {
+    __IO uint32_t rsp2;
+    struct {
+      __IO uint32_t  rsp2       : 32;
+    } rsp2_b;
+  };
+
+  // Offset = 0x003c
+  union {
+    __IO uint32_t rsp3;
+    struct {
+      __IO uint32_t  rsp3       : 32;
+    } rsp3_b;
+  };
+
+  // Offset = 0x0040
+  union {
+    __IO uint32_t clk_div;
+    struct {
+      __IO uint32_t  clk_div    :  8;
+      __IO uint32_t  valid      :  1;
+    } clk_div_b;
+  };
+
+  // Offset = 0x0044
+  union {
+    __IO uint32_t status;
+    struct {
+      __IO uint32_t  eot        :  1;
+      __IO uint32_t  error      :  1;
+      __IO uint32_t             : 14;
+      __IO uint32_t  cmd_err_status :  6;
+    } status_b;
+  };
+} UdmaSdio_t;
+
+
+#define REG_RX_SADDR                   0x00
+#define   REG_RX_SADDR_SADDR_LSB                   0
+#define   REG_RX_SADDR_SADDR_MASK                  0xffffffff
+#define REG_RX_SIZE                    0x04
+#define   REG_RX_SIZE_SIZE_LSB                     0
+#define   REG_RX_SIZE_SIZE_MASK                    0xffff
+#define REG_RX_CFG                     0x08
+#define   REG_RX_CFG_CLR_LSB                       5
+#define   REG_RX_CFG_CLR_MASK                      0x1
+#define   REG_RX_CFG_PENDING_LSB                   5
+#define   REG_RX_CFG_PENDING_MASK                  0x1
+#define   REG_RX_CFG_EN_LSB                        4
+#define   REG_RX_CFG_EN_MASK                       0x1
+#define   REG_RX_CFG_DATASIZE_LSB                  1
+#define   REG_RX_CFG_DATASIZE_MASK                 0x3
+#define   REG_RX_CFG_CONTINUOUS_LSB                0
+#define   REG_RX_CFG_CONTINUOUS_MASK               0x1
+#define REG_TX_SADDR                   0x10
+#define   REG_TX_SADDR_SADDR_LSB                   0
+#define   REG_TX_SADDR_SADDR_MASK                  0xfff
+#define REG_TX_SIZE                    0x14
+#define   REG_TX_SIZE_SIZE_LSB                     0
+#define   REG_TX_SIZE_SIZE_MASK                    0xffff
+#define REG_TX_CFG                     0x18
+#define   REG_TX_CFG_CLR_LSB                       5
+#define   REG_TX_CFG_CLR_MASK                      0x1
+#define   REG_TX_CFG_PENDING_LSB                   5
+#define   REG_TX_CFG_PENDING_MASK                  0x1
+#define   REG_TX_CFG_EN_LSB                        4
+#define   REG_TX_CFG_EN_MASK                       0x1
+#define   REG_TX_CFG_DATASIZE_LSB                  1
+#define   REG_TX_CFG_DATASIZE_MASK                 0x3
+#define   REG_TX_CFG_CONTINUOUS_LSB                0
+#define   REG_TX_CFG_CONTINUOUS_MASK               0x1
+#define REG_CMD_OP                     0x20
+#define   REG_CMD_OP_CMD_OP_LSB                    8
+#define   REG_CMD_OP_CMD_OP_MASK                   0x3f
+#define   REG_CMD_OP_CMD_RSP_TYPE_LSB              0
+#define   REG_CMD_OP_CMD_RSP_TYPE_MASK             0x7
+#define REG_CMD_ARG                    0x24
+#define   REG_CMD_ARG_CMD_ARG_LSB                  0
+#define   REG_CMD_ARG_CMD_ARG_MASK                 0xffffffff
+#define REG_DATA_SETUP                 0x28
+#define   REG_DATA_SETUP_BLOCK_SIZE_LSB            16
+#define   REG_DATA_SETUP_BLOCK_SIZE_MASK           0x3ff
+#define   REG_DATA_SETUP_BLOCK_NUM_LSB             8
+#define   REG_DATA_SETUP_BLOCK_NUM_MASK            0xff
+#define   REG_DATA_SETUP_DATA_QUAD_LSB             2
+#define   REG_DATA_SETUP_DATA_QUAD_MASK            0x1
+#define   REG_DATA_SETUP_DATA_RWN_LSB              1
+#define   REG_DATA_SETUP_DATA_RWN_MASK             0x1
+#define   REG_DATA_SETUP_DATA_EN_LSB               0
+#define   REG_DATA_SETUP_DATA_EN_MASK              0x1
+#define REG_START                      0x2C
+#define   REG_START_START_LSB                      0
+#define   REG_START_START_MASK                     0x1
+#define REG_RSP0                       0x30
+#define   REG_RSP0_RSP0_LSB                        0
+#define   REG_RSP0_RSP0_MASK                       0xffffffff
+#define REG_RSP1                       0x34
+#define   REG_RSP1_RSP1_LSB                        0
+#define   REG_RSP1_RSP1_MASK                       0xffffffff
+#define REG_RSP2                       0x38
+#define   REG_RSP2_RSP2_LSB                        0
+#define   REG_RSP2_RSP2_MASK                       0xffffffff
+#define REG_RSP3                       0x3C
+#define   REG_RSP3_RSP3_LSB                        0
+#define   REG_RSP3_RSP3_MASK                       0xffffffff
+#define REG_CLK_DIV                    0x40
+#define   REG_CLK_DIV_VALID_LSB                    8
+#define   REG_CLK_DIV_VALID_MASK                   0x1
+#define   REG_CLK_DIV_CLK_DIV_LSB                  0
+#define   REG_CLK_DIV_CLK_DIV_MASK                 0xff
+#define REG_STATUS                     0x44
+#define   REG_STATUS_CMD_ERR_STATUS_LSB            16
+#define   REG_STATUS_CMD_ERR_STATUS_MASK           0x3f
+#define   REG_STATUS_ERROR_LSB                     1
+#define   REG_STATUS_ERROR_MASK                    0x1
+#define   REG_STATUS_EOT_LSB                       0
+#define   REG_STATUS_EOT_MASK                      0x1
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_SDIO_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/hal_udma_uart_reg_defs.h

@@ -0,0 +1,247 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_UART_H_
+#define __UDMA_UART_H_
+
+//---------------------------------//
+//
+// Module: UDMA_UART
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t rx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } rx_saddr_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t rx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } rx_size_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t rx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t             :  3;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } rx_cfg_b;
+  };
+  __I uint32_t    unused0[1];
+
+  // Offset = 0x0010
+  union {
+    __IO uint32_t tx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 12;
+    } tx_saddr_b;
+  };
+
+  // Offset = 0x0014
+  union {
+    __IO uint32_t tx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } tx_size_b;
+  };
+
+  // Offset = 0x0018
+  union {
+    __IO uint32_t tx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t             :  3;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } tx_cfg_b;
+  };
+  __I uint32_t    unused1[1];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t status;
+    struct {
+      __IO uint32_t  tx_busy    :  1;
+      __IO uint32_t  rx_busy    :  1;
+    } status_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t uart_setup;
+    struct {
+      __IO uint32_t  parity_en  :  1;
+      __IO uint32_t  bits       :  2;
+      __IO uint32_t  stop_bits  :  1;
+      __IO uint32_t  rx_polling_en :  1;
+      __IO uint32_t  rx_clean_fifo :  1;
+      __IO uint32_t             :  2;
+      __IO uint32_t  en_tx      :  1;
+      __IO uint32_t  en_rx      :  1;
+      __IO uint32_t             :  6;
+      __IO uint32_t  div        : 16;
+    } uart_setup_b;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t error;
+    struct {
+      __IO uint32_t  overflow_err :  1;
+      __IO uint32_t  parity_err :  1;
+    } error_b;
+  };
+
+  // Offset = 0x002c
+  union {
+    __IO uint32_t irq_en;
+    struct {
+      __IO uint32_t  rx_irq_en  :  1;
+      __IO uint32_t  err_irq_en :  1;
+    } irq_en_b;
+  };
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t valid;
+    struct {
+      __IO uint32_t  rx_data_valid :  1;
+    } valid_b;
+  };
+
+  // Offset = 0x0034
+  union {
+    __IO uint32_t data;
+    struct {
+      __IO uint32_t  rx_data    :  8;
+    } data_b;
+  };
+} UdmaUart_t;
+
+
+#define REG_RX_SADDR                   0x00
+#define   REG_RX_SADDR_SADDR_LSB                   0
+#define   REG_RX_SADDR_SADDR_MASK                  0xfff
+#define REG_RX_SIZE                    0x04
+#define   REG_RX_SIZE_SIZE_LSB                     0
+#define   REG_RX_SIZE_SIZE_MASK                    0xffff
+#define REG_RX_CFG                     0x08
+#define   REG_RX_CFG_CLR_LSB                       6
+#define   REG_RX_CFG_CLR_MASK                      0x1
+#define   REG_RX_CFG_PENDING_LSB                   5
+#define   REG_RX_CFG_PENDING_MASK                  0x1
+#define   REG_RX_CFG_EN_LSB                        4
+#define   REG_RX_CFG_EN_MASK                       0x1
+#define   REG_RX_CFG_CONTINUOUS_LSB                0
+#define   REG_RX_CFG_CONTINUOUS_MASK               0x1
+#define REG_TX_SADDR                   0x10
+#define   REG_TX_SADDR_SADDR_LSB                   0
+#define   REG_TX_SADDR_SADDR_MASK                  0xfff
+#define REG_TX_SIZE                    0x14
+#define   REG_TX_SIZE_SIZE_LSB                     0
+#define   REG_TX_SIZE_SIZE_MASK                    0xffff
+#define REG_TX_CFG                     0x18
+#define   REG_TX_CFG_CLR_LSB                       6
+#define   REG_TX_CFG_CLR_MASK                      0x1
+#define   REG_TX_CFG_PENDING_LSB                   5
+#define   REG_TX_CFG_PENDING_MASK                  0x1
+#define   REG_TX_CFG_EN_LSB                        4
+#define   REG_TX_CFG_EN_MASK                       0x1
+#define   REG_TX_CFG_CONTINUOUS_LSB                0
+#define   REG_TX_CFG_CONTINUOUS_MASK               0x1
+#define REG_STATUS                     0x20
+#define   REG_STATUS_RX_BUSY_LSB                   1
+#define   REG_STATUS_RX_BUSY_MASK                  0x1
+#define   REG_STATUS_TX_BUSY_LSB                   0
+#define   REG_STATUS_TX_BUSY_MASK                  0x1
+#define REG_UART_SETUP                 0x24
+#define   REG_UART_SETUP_DIV_LSB                   16
+#define   REG_UART_SETUP_DIV_MASK                  0xffff
+#define   REG_UART_SETUP_EN_RX_LSB                 9
+#define   REG_UART_SETUP_EN_RX_MASK                0x1
+#define   REG_UART_SETUP_EN_TX_LSB                 8
+#define   REG_UART_SETUP_EN_TX_MASK                0x1
+#define   REG_UART_SETUP_RX_CLEAN_FIFO_LSB         5
+#define   REG_UART_SETUP_RX_CLEAN_FIFO_MASK        0x1
+#define   REG_UART_SETUP_RX_POLLING_EN_LSB         4
+#define   REG_UART_SETUP_RX_POLLING_EN_MASK        0x1
+#define   REG_UART_SETUP_STOP_BITS_LSB             3
+#define   REG_UART_SETUP_STOP_BITS_MASK            0x1
+#define   REG_UART_SETUP_BITS_LSB                  1
+#define   REG_UART_SETUP_BITS_MASK                 0x3
+#define   REG_UART_SETUP_PARITY_EN_LSB             0
+#define   REG_UART_SETUP_PARITY_EN_MASK            0x1
+#define REG_ERROR                      0x28
+#define   REG_ERROR_PARITY_ERR_LSB                 1
+#define   REG_ERROR_PARITY_ERR_MASK                0x1
+#define   REG_ERROR_OVERFLOW_ERR_LSB               0
+#define   REG_ERROR_OVERFLOW_ERR_MASK              0x1
+#define REG_IRQ_EN                     0x2C
+#define   REG_IRQ_EN_ERR_IRQ_EN_LSB                1
+#define   REG_IRQ_EN_ERR_IRQ_EN_MASK               0x1
+#define   REG_IRQ_EN_RX_IRQ_EN_LSB                 0
+#define   REG_IRQ_EN_RX_IRQ_EN_MASK                0x1
+#define REG_VALID                      0x30
+#define   REG_VALID_RX_DATA_VALID_LSB              0
+#define   REG_VALID_RX_DATA_VALID_MASK             0x1
+#define REG_DATA                       0x34
+#define   REG_DATA_RX_DATA_LSB                     0
+#define   REG_DATA_RX_DATA_MASK                    0xff
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_UART_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/include/udma_camera_reg_defs.h

@@ -0,0 +1,204 @@
+/*
+ * This is a generated file
+ * 
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UDMA_CAMERA_H_
+#define __UDMA_CAMERA_H_
+
+//---------------------------------//
+//
+// Module: UDMA_CAMERA
+//
+//---------------------------------//
+
+#ifndef __IO
+#define __IO volatile
+#endif
+
+#ifndef __I
+#define __I volatile
+#endif
+
+#ifndef __O
+#define __O volatile
+#endif
+
+#include "stdint.h"
+
+typedef struct {
+
+  // Offset = 0x0000
+  union {
+    __IO uint32_t rx_saddr;
+    struct {
+      __IO uint32_t  saddr      : 32;
+    } rx_saddr_b;
+  };
+
+  // Offset = 0x0004
+  union {
+    __IO uint32_t rx_size;
+    struct {
+      __IO uint32_t  size       : 16;
+    } rx_size_b;
+  };
+
+  // Offset = 0x0008
+  union {
+    __IO uint32_t rx_cfg;
+    struct {
+      __IO uint32_t  continuous :  1;
+      __IO uint32_t  datasize   :  2;
+      __IO uint32_t             :  1;
+      __IO uint32_t  en         :  1;
+      __IO uint32_t  pending    :  1;
+      __IO uint32_t  clr        :  1;
+    } rx_cfg_b;
+  };
+  __I uint32_t    unused0[5];
+
+  // Offset = 0x0020
+  union {
+    __IO uint32_t cfg_glob;
+    struct {
+      __IO uint32_t  framedrop_en :  1;
+      __IO uint32_t  framedrop_val :  6;
+      __IO uint32_t  framewindow_en :  1;
+      __IO uint32_t  format     :  3;
+      __IO uint32_t  shift      :  4;
+      __IO uint32_t             : 16;
+      __IO uint32_t  en         :  1;
+    } cfg_glob_b;
+  };
+
+  // Offset = 0x0024
+  union {
+    __IO uint32_t cfg_ll;
+    struct {
+      __IO uint32_t  framewindow_llx : 16;
+      __IO uint32_t  framewindow_lly : 16;
+    } cfg_ll_b;
+  };
+
+  // Offset = 0x0028
+  union {
+    __IO uint32_t cfg_ur;
+    struct {
+      __IO uint32_t  framewindow_urx : 16;
+      __IO uint32_t  framewindow_ury : 16;
+    } cfg_ur_b;
+  };
+
+  // Offset = 0x002c
+  union {
+    __IO uint32_t cfg_size;
+    struct {
+      __IO uint32_t             : 16;
+      __IO uint32_t  rowlen     : 16;
+    } cfg_size_b;
+  };
+
+  // Offset = 0x0030
+  union {
+    __IO uint32_t cfg_filter;
+    struct {
+      __IO uint32_t             :  8;
+      __IO uint32_t  b_coeff    :  8;
+      __IO uint32_t  g_coeff    :  8;
+      __IO uint32_t  r_coeff    :  8;
+    } cfg_filter_b;
+  };
+
+  // Offset = 0x0034
+  union {
+    __IO uint32_t vsync_polarity;
+    struct {
+      __IO uint32_t  vsync_polarity :  1;
+    } vsync_polarity_b;
+  };
+} UdmaCamera_t;
+
+
+#define REG_RX_SADDR                   0x00
+#define   REG_RX_SADDR_SADDR_LSB                   0
+#define   REG_RX_SADDR_SADDR_MASK                  0xffffffff
+#define REG_RX_SIZE                    0x04
+#define   REG_RX_SIZE_SIZE_LSB                     0
+#define   REG_RX_SIZE_SIZE_MASK                    0xffff
+#define REG_RX_CFG                     0x08
+#define   REG_RX_CFG_CLR_LSB                       5
+#define   REG_RX_CFG_CLR_MASK                      0x1
+#define   REG_RX_CFG_PENDING_LSB                   5
+#define   REG_RX_CFG_PENDING_MASK                  0x1
+#define   REG_RX_CFG_EN_LSB                        4
+#define   REG_RX_CFG_EN_MASK                       0x1
+#define   REG_RX_CFG_DATASIZE_LSB                  1
+#define   REG_RX_CFG_DATASIZE_MASK                 0x3
+#define   REG_RX_CFG_CONTINUOUS_LSB                0
+#define   REG_RX_CFG_CONTINUOUS_MASK               0x1
+#define REG_CFG_GLOB                   0x20
+#define   REG_CFG_GLOB_EN_LSB                      31
+#define   REG_CFG_GLOB_EN_MASK                     0x1
+#define   REG_CFG_GLOB_SHIFT_LSB                   11
+#define   REG_CFG_GLOB_SHIFT_MASK                  0xf
+#define   REG_CFG_GLOB_FORMAT_LSB                  8
+#define   REG_CFG_GLOB_FORMAT_MASK                 0x7
+#define   REG_CFG_GLOB_FRAMEWINDOW_EN_LSB          7
+#define   REG_CFG_GLOB_FRAMEWINDOW_EN_MASK         0x1
+#define   REG_CFG_GLOB_FRAMEDROP_VAL_LSB           1
+#define   REG_CFG_GLOB_FRAMEDROP_VAL_MASK          0x3f
+#define   REG_CFG_GLOB_FRAMEDROP_EN_LSB            0
+#define   REG_CFG_GLOB_FRAMEDROP_EN_MASK           0x1
+#define REG_CFG_LL                     0x24
+#define   REG_CFG_LL_FRAMEWINDOW_LLY_LSB           16
+#define   REG_CFG_LL_FRAMEWINDOW_LLY_MASK          0xffff
+#define   REG_CFG_LL_FRAMEWINDOW_LLX_LSB           0
+#define   REG_CFG_LL_FRAMEWINDOW_LLX_MASK          0xffff
+#define REG_CFG_UR                     0x28
+#define   REG_CFG_UR_FRAMEWINDOW_URY_LSB           16
+#define   REG_CFG_UR_FRAMEWINDOW_URY_MASK          0xffff
+#define   REG_CFG_UR_FRAMEWINDOW_URX_LSB           0
+#define   REG_CFG_UR_FRAMEWINDOW_URX_MASK          0xffff
+#define REG_CFG_SIZE                   0x2C
+#define   REG_CFG_SIZE_ROWLEN_LSB                  16
+#define   REG_CFG_SIZE_ROWLEN_MASK                 0xffff
+#define REG_CFG_FILTER                 0x30
+#define   REG_CFG_FILTER_R_COEFF_LSB               16
+#define   REG_CFG_FILTER_R_COEFF_MASK              0xff
+#define   REG_CFG_FILTER_G_COEFF_LSB               8
+#define   REG_CFG_FILTER_G_COEFF_MASK              0xff
+#define   REG_CFG_FILTER_B_COEFF_LSB               8
+#define   REG_CFG_FILTER_B_COEFF_MASK              0xff
+#define REG_VSYNC_POLARITY             0x34
+#define   REG_VSYNC_POLARITY_VSYNC_POLARITY_LSB    0
+#define   REG_VSYNC_POLARITY_VSYNC_POLARITY_MASK   0x1
+
+#ifndef __REGFIELD_OPS_
+#define __REGFIELD_OPS_
+static inline uint32_t regfield_read(uint32_t reg, uint32_t mask, uint32_t lsb) {
+  return (reg >> lsb) & mask;
+}
+static inline uint32_t regfield_write(uint32_t reg, uint32_t mask, uint32_t lsb, uint32_t value) {
+  reg &= ~(mask << lsb);
+  reg |= (value & mask) << lsb;
+  return reg;
+}
+#endif  // __REGFIELD_OPS_
+
+#endif // __UDMA_CAMERA_H_

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_apb_i2cs.c

@@ -0,0 +1,123 @@
+#include "core-v-mcu-config.h"
+#include "hal_apb_i2cs_reg_defs.h"
+
+
+uint8_t hal_get_apb_i2cs_slave_address(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_dev_address_b.slave_addr;
+}
+
+void hal_set_apb_i2cs_slave_address(uint8_t aSlaveAddress)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
+	apbI2cSlave->i2cs_dev_address_b.slave_addr = aSlaveAddress;
+}
+
+uint8_t hal_set_apb_i2cs_slave_on_off(uint8_t aStatus)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	if( aStatus == 1 )
+		apbI2cSlave->i2cs_enable_b.ip_enable = 1;
+	else if( aStatus == 0 )
+		apbI2cSlave->i2cs_enable_b.ip_enable = 0;
+	return (uint8_t)apbI2cSlave->i2cs_enable_b.ip_enable;
+}
+
+
+uint8_t hal_get_i2cs_fifo_i2c_apb_read_data_port(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_fifo_i2c_apb_read_data_port;
+}
+
+void hal_set_i2cs_fifo_apb_i2c_write_data_port(uint8_t aData)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
+	apbI2cSlave->i2cs_fifo_apb_i2c_write_data_port = aData;
+}
+
+uint8_t hal_get_i2cs_fifo_i2c_apb_write_flags(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_fifo_i2c_apb_write_flags;
+}
+
+
+uint8_t hal_get_i2cs_fifo_i2c_apb_read_flags(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_fifo_i2c_apb_read_flags;
+}
+
+uint8_t hal_get_i2cs_fifo_apb_i2c_read_flags(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_fifo_apb_i2c_read_flags;
+}
+
+uint8_t hal_get_i2cs_fifo_apb_i2c_write_flags(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_fifo_apb_i2c_write_flags;
+}
+
+
+uint8_t hal_get_i2cs_msg_i2c_apb(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
+	return (apbI2cSlave->i2cs_msg_i2c_apb);
+}
+
+uint8_t hal_get_i2cs_msg_i2c_apb_status(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_msg_i2c_apb_status;
+}
+
+
+void hal_set_i2cs_msg_apb_i2c(uint8_t aData)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*) I2CS_START_ADDR;
+	apbI2cSlave->i2cs_msg_apb_i2c = aData;
+}
+
+uint8_t hal_get_i2cs_msg_apb_i2c_status(void)
+{
+
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	return (uint8_t )apbI2cSlave->i2cs_msg_apb_i2c_status;
+}
+
+
+void hal_i2cs_fifo_i2c_apb_FIFO_flush(void)
+{
+	int i = 0;
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	apbI2cSlave->i2cs_fifo_i2c_apb_flush_b.enable = 1;
+	for( i=0; i<1000; i++);
+	apbI2cSlave->i2cs_fifo_i2c_apb_flush_b.enable = 0;
+	for( i=0; i<1000; i++);
+}
+
+void hal_i2cs_fifo_apb_i2c_FIFO_flush(void)
+{
+	int i = 0;
+	ApbI2cs_t *apbI2cSlave = (ApbI2cs_t*)I2CS_START_ADDR;
+	apbI2cSlave->i2cs_fifo_apb_i2c_flush_b.enable = 1;
+	for( i=0; i<1000; i++);
+	apbI2cSlave->i2cs_fifo_apb_i2c_flush_b.enable = 0;
+	for( i=0; i<1000; i++);
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fc_event.c

@@ -0,0 +1,119 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * hal_fc_event.c
+ *
+ *  Created on: Feb 19, 2021
+ *      Author: qlblue
+ */
+
+//#include "pmsis/implem/drivers/fc_event/fc_event.h"
+#include "hal_fc_event.h"
+//#include "pmsis/implem/hal/hal.h"
+#include "hal_soc_eu_periph.h"
+//#include "pmsis/implem/drivers/pmsis_it.h"
+//#include "FreeRTOS.h"
+//#include "semphr.h"
+#include "rtthread.h"
+
+#define unuse_freertos_in_event
+/*******************************************************************************
+ * Variables, macros, structures,... definition
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Function definition
+ ******************************************************************************/
+
+static void fc_event_null_event(void *arg);
+
+static volatile pi_fc_event_handler_t fc_event_handlers[SOC_EU_NB_FC_EVENTS];
+//static SemaphoreHandle_t  fc_event_semaphores[SOC_EU_NB_FC_EVENTS];
+
+static void fc_event_null_event(void *arg)
+{
+	return;
+}
+
+void pi_fc_event_handler_init(uint32_t fc_event_irq)
+{
+	/* TODO: fix this mess, that should be 8 32-bit writes */
+	/* open the mask for fc_soc_event irq */
+	for (int i = 0; i < SOC_EU_NB_FC_EVENTS; i++) {
+		pi_fc_event_handler_clear(i);
+	}
+	/* NVIC_SetVector(fc_event_irq, (uint32_t)__handler_wrapper_light_fc_event_handler);*/
+	//irqn_enable(fc_event_irq);
+}
+
+#if 0  
+void pi_fc_event_handler_set(uint32_t event_id,
+			     pi_fc_event_handler_t event_handler,
+					SemaphoreHandle_t semaphoreHandle)
+{
+	if (event_handler != NULL) {
+		fc_event_handlers[event_id] = event_handler;
+	}
+	if (semaphoreHandle != NULL) {
+		fc_event_semaphores[event_id] = semaphoreHandle;
+	}
+}
+#endif 
+
+void user_pi_fc_event_handler_set(uint32_t event_id,
+			     pi_fc_event_handler_t event_handler)
+{
+	if (event_handler != NULL) {
+		fc_event_handlers[event_id] = event_handler;
+	}
+}
+
+void pi_fc_event_handler_clear(uint32_t event_id)
+{
+	fc_event_handlers[event_id] = (pi_fc_event_handler_t)fc_event_null_event;
+	//fc_event_semaphores[event_id] = NULL;// remove  from  project 
+}
+
+/* TODO: Use Eric's FIRQ ABI */
+void fc_soc_event_handler1 (uint32_t mcause)
+{
+	uint32_t val = 0;
+	//static BaseType_t xHigherPriorityTaskWoken;
+
+	uint32_t event_id = *(uint32_t*)(0x1a106090); // new event fifo address
+
+	event_id &= 0xFF;
+
+	/* redirect to handler with jump table */
+	if (fc_event_handlers[event_id] != NULL) {
+		fc_event_handlers[event_id]((void *)event_id);
+	}
+	#if 0
+	if (fc_event_semaphores[event_id] != NULL) {
+		/* Unblock the task by releasing the semaphore. */
+		#ifdef  unuse_freertos_in_event
+		 SemaphoreHandle_t xSemaphoreHandle = fc_event_semaphores[event_id];
+		 xSemaphoreGiveFromISR( xSemaphoreHandle, &xHigherPriorityTaskWoken );
+		 //rt_schedule();
+		 //portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		 //__asm volatile( "ecall" );
+		#endif 
+	}
+	#endif
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fll.c

@@ -0,0 +1,208 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ * Copyright (C) 2019 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* FLL driver code for PULPissimo */
+/* Author: Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ *         Eric Flamand (eric.flamand@greenwaves-technologies.com)
+ *         Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#include <pulp_io.h>
+#include <stdint.h>
+
+#include "system_metal.h"
+#include "core-v-mcu-pulp-mem-map.h"
+#include "hal_fll.h"
+
+#define __MAX(a, b)                                                            \
+	({                                                                     \
+		typeof(a) _a = (a);                                            \
+		typeof(b) _b = (b);                                            \
+		_a > _b ? _a : _b;                                             \
+	})
+
+#define __FL1(x) (31 - __builtin_clz((x)))
+
+int __rt_fll_freq[ARCHI_NB_FLL];
+static char __rt_fll_is_on[ARCHI_NB_FLL];
+int __rt_freq_domains[RT_FREQ_NB_DOMAIN];
+
+void pulp_fll_init(void)
+{
+	for (int i = 0; i < ARCHI_NB_FLL; i++) {
+		__rt_fll_freq[i] = 0;
+		__rt_fll_is_on[i] = 0;
+	}
+
+	__rt_freq_domains[__RT_FREQ_DOMAIN_FC] = __fll_init(__RT_FLL_FC);
+	__rt_freq_domains[__RT_FREQ_DOMAIN_PERIPH] =
+		__fll_init(__RT_FLL_PERIPH);
+}
+
+static unsigned int __rt_fll_get_mult_div_from_freq(unsigned int freq,
+						    unsigned int *mult,
+						    unsigned int *div)
+{
+	unsigned int fref = ARCHI_REF_CLOCK;
+	unsigned int Log2M = __FL1(freq) - __FL1(fref);
+	unsigned int D = __MAX(1, (FLL_LOG2_MAXM - Log2M) >> 1);
+	unsigned int M = (freq << D) / fref;
+	unsigned int fres;
+
+#if 0 /* PULP_CHIP == CHIP_QUENTIN */
+
+	/* TODO on quentin, the fll never converges (e.g. a mult factor of 15000 is
+	 * not working), check what is the maximum value we can use
+	 */
+	while (M >= 10000) {
+		M >>= 1;
+		D--;
+	};
+
+	if (D == 0) fres = fref*M;
+	else fres = (fref*M + (1<<(D-1)))>>D;   /* Rounding */
+
+#else
+	fres = (fref * M + (1 << (D - 1))) >> D; /* Rounding */
+#endif
+
+	*mult = M;
+	*div = D + 1;
+	return fres;
+}
+
+static unsigned int __rt_fll_get_freq_from_mult_div(unsigned int mult,
+						    unsigned int div)
+{
+	// FreqOut = Fref * Mult/2^(Div-1)	With Mult on 16 bits and Div on 4 bits
+	unsigned int fref = ARCHI_REF_CLOCK;
+	unsigned int fres = (fref * mult) >> (div - 1);
+	return fres;
+}
+
+unsigned int __fll_init(int fll)
+{
+	//rt_trace(RT_TRACE_INIT, "Initializing FLL (fll: %d)\n", fll);
+
+	fll_reg_conf1_t reg1 = {
+		.raw = readw((uintptr_t)(PULP_FLL_ADDR + FLL_CONF1_OFFSET +
+					  fll * PULP_FLL_AREA_SIZE))
+	};
+
+	/* Only lock the fll if it is not already done by the boot code */
+	if (reg1.mode == 0) {
+		/* Set Clock Ref lock assert count */
+		fll_reg_conf2_t reg2 = {
+			.raw = readw((uintptr_t)(PULP_FLL_ADDR +
+						  FLL_CONF2_OFFSET +
+						  fll * PULP_FLL_AREA_SIZE))
+		};
+
+		reg2.assert_cycles = 6;
+		reg2.lock_tolerance = 0x50;
+		writew(reg2.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF2_OFFSET +
+					      fll * PULP_FLL_AREA_SIZE));
+		/*
+		* In order to lock the fll faster, we first setup an approximated
+		* frequency while we are in open loop as it is set immediately.
+		* Then starting from this frequency, we should reach the target one
+		* in lock mode faster.
+		* We are in open loop, prime the fll forcing dco input, approx 70 MHz
+		*/
+		//rt_trace(RT_TRACE_INIT, "Priming FLL in open loop (fll: %d)\n",
+		//	 fll);
+		fll_reg_integrator_t reg_int = {
+			.raw = readw((uintptr_t)(PULP_FLL_ADDR +
+						  FLL_INTEGRATOR_OFFSET +
+						  fll * PULP_FLL_AREA_SIZE))
+		};
+
+/* TODO: quick hack to prevent 0 == 0 in next macro */
+#ifndef PULP_CHIP
+#define PULP_CHIP 1
+#endif
+
+#if PULP_CHIP == CHIP_QUENTIN || PULP_CHIP == CHIP_KERBIN
+#error "Touching bad FLL code path"
+		/* TODO: don't know how to choose the right, 332 is too agressive for
+		 * quentin and the fll is never converging
+		 */
+		reg_int.state_int_part = 100;
+#else
+		reg_int.state_int_part = 332;
+#endif
+
+		writew(reg_int.raw,
+		       (uintptr_t)(PULP_FLL_ADDR + FLL_INTEGRATOR_OFFSET +
+				    fll * PULP_FLL_AREA_SIZE));
+
+		/* Lock Fll */
+		reg1.output_lock_enable = 1;
+		reg1.mode = 1;
+		writew(reg1.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF1_OFFSET +
+					      fll * PULP_FLL_AREA_SIZE));
+	}
+
+	/* In case the FLL frequency was set while it was off, update it immediately */
+	/* TODO */
+	unsigned int freq = __rt_fll_freq[fll];
+	if (freq) {
+		__rt_fll_set_freq(fll, freq);
+	} else {
+		freq = __rt_fll_get_freq_from_mult_div(reg1.mult_factor,
+						       reg1.clock_out_divider);
+		__rt_fll_freq[fll] = freq;
+	}
+
+	__rt_fll_is_on[fll] = 1;
+
+	//rt_trace(RT_TRACE_INIT, "FLL is locked (fll: %d, freq: %d)\n", fll,
+	// freq);
+
+	return freq;
+}
+
+unsigned int __rt_fll_set_freq(int fll, unsigned int frequency)
+{
+	/* Synchronize with bridge so that it does not try to access the chip
+	 * while we are changing the frequency
+	 */
+	// if (fll == __RT_FLL_FC)
+	// 	__rt_bridge_req_shutdown();
+
+	unsigned int real_freq, mult, div;
+	real_freq = __rt_fll_get_mult_div_from_freq(frequency, &mult, &div);
+
+	__rt_fll_freq[fll] = real_freq;
+	if (__rt_fll_is_on[fll]) {
+		fll_reg_conf1_t reg1 = {
+			.raw = readw((uintptr_t)(PULP_FLL_ADDR +
+						  FLL_CONF1_OFFSET +
+						  fll * PULP_FLL_AREA_SIZE))
+		};
+
+		reg1.mult_factor = mult;
+		reg1.clock_out_divider = div;
+
+		writew(reg1.raw, (uintptr_t)(PULP_FLL_ADDR + FLL_CONF1_OFFSET +
+					      fll * PULP_FLL_AREA_SIZE));
+	}
+
+	return real_freq;
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_fll_pi.c

@@ -0,0 +1,206 @@
+/*
+ * Copyright 2020 GreenWaves Technologies
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include "hal_fll_pi.h"
+/* TODO: abstract this */
+#include "core-v-mcu-system.h"
+#include <rtthread.h>
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*
+ * Fll control
+ * FreqOut = Fref * Mult/2^(Div-1)
+ * With Mult on 16 bits and Div on 4 bits
+ */
+
+/* Maximum Log2(DCO Frequency) */
+#define FLL_LOG2_MAXDCO 29
+/* Maximum Log2(Clok Divider) */
+#define FLL_LOG2_MAXDIV 15
+/* Log2(FLL_REF_CLK=32768) */
+#define FLL_LOG2_REFCLK ARCHI_REF_CLOCK_LOG2
+/* Maximum Log2(Multiplier) */
+#define FLL_LOG2_MAXM (FLL_LOG2_MAXDCO - FLL_LOG2_REFCLK)
+
+/* TODO: we are patching over these macros to make them independent of pulp-gcc */
+#define __MAX(a, b)                                                            \
+	({                                                                     \
+		typeof(a) _a = (a);                                            \
+		typeof(b) _b = (b);                                            \
+		_a > _b ? _a : _b;                                             \
+	})
+
+#define __FL1(x) (31 - __builtin_clz((x)))
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static volatile uint32_t flls_frequency[FLL_NUM];
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static uint32_t fll_get_mult_div_from_frequency(uint32_t freq, uint32_t *mult,
+						uint32_t *div)
+{
+	unsigned int fref = FLL_REF_CLK;
+	unsigned int Log2M = __FL1(freq) - __FL1(fref);
+	unsigned int D = __MAX(1, (FLL_LOG2_MAXM - Log2M) >> 1);
+	unsigned int M = (freq << D) / fref;
+	unsigned int fres;
+
+	fres = (fref * M + (1 << (D - 1))) >> D; /* Rounding */
+
+	*mult = M;
+	*div = D + 1;
+	return fres;
+}
+
+static uint32_t fll_get_frequency_from_mult_div(uint32_t mult, uint32_t div)
+{
+	/* FreqOut = Fref * Mult/2^(Div-1)    With Mult on 16 bits and Div on 4 bits */
+	uint32_t fref = FLL_REF_CLK;
+	uint32_t fres = (div == 0) ? (fref * mult) : (fref * mult) >> (div - 1);
+	return fres;
+}
+
+int pi_fll_set_frequency(fll_type_t which_fll, uint32_t frequency, int check)
+{
+	uint32_t mult, div;
+	uint32_t reg1;
+
+	int irq = __disable_irq();
+
+	/* Frequency calculation from theory */
+	fll_get_mult_div_from_frequency(frequency, &mult, &div);
+
+	/* update mult and div */
+	/* TODO: check if fll is on */
+	reg1 = FLL_CTRL[which_fll].FLL_CONF1;
+
+	reg1 &= ~FLL_CTRL_CONF1_MULTI_FACTOR_MASK;
+	reg1 |= FLL_CTRL_CONF1_MULTI_FACTOR(mult);
+	reg1 &= ~FLL_CTRL_CONF1_CLK_OUT_DIV_MASK;
+	reg1 |= FLL_CTRL_CONF1_CLK_OUT_DIV(div);
+
+	FLL_CTRL[which_fll].FLL_CONF1 = reg1;
+
+	/* finalize */
+	if (which_fll == FLL_SOC)
+		system_core_clock_update();
+
+	flls_frequency[which_fll] = frequency;
+
+	__restore_irq(irq);
+
+	return frequency;
+}
+
+void pi_fll_init(fll_type_t which_fll, uint32_t ret_state)
+{
+	uint32_t reg1;
+
+	if (ret_state) {
+		pi_fll_get_frequency(which_fll, 1);
+	} else {
+		reg1 = FLL_CTRL[which_fll].FLL_CONF1;
+
+		/*
+		 * Don't set the gain and integrator in case it has already been
+		 * set by the boot code as it totally blocks the fll on the RTL
+		 * platform. The boot code is anyway setting the same
+		 * configuration.
+		 */
+		if (!READ_FLL_CTRL_CONF1_MODE(reg1)) {
+			/* set clock ref lock assert count */
+			uint32_t reg2 = FLL_CTRL[which_fll].FLL_CONF2;
+			reg2 &= ~FLL_CTRL_CONF2_ASSERT_CYCLES_MASK;
+			reg2 |= FLL_CTRL_CONF2_ASSERT_CYCLES(0x6);
+			reg2 &= ~FLL_CTRL_CONF2_LOCK_TOLERANCE_MASK;
+			reg2 |= FLL_CTRL_CONF2_LOCK_TOLERANCE(0x50);
+			FLL_CTRL[which_fll].FLL_CONF2 = reg2;
+
+			/*
+			 * In order to lock the fll faster, we first setup an
+			 * approximated frequency while we are in open loop as
+			 * it is set immediately. Then starting from this
+			 * frequency, we should reach the target one in lock
+			 * mode faster. We are in open loop, prime the fll
+			 * forcing dco input, approx 70 MHz
+			 */
+			uint32_t regint = FLL_CTRL[which_fll].FLL_INTEGRATOR;
+			regint &= ~FLL_CTRL_INTEGRATOR_INT_PART_MASK;
+			regint |= FLL_CTRL_INTEGRATOR_INT_PART(332);
+			FLL_CTRL[which_fll].FLL_INTEGRATOR = regint;
+
+			/* Lock FLL */
+			reg1 &= ~FLL_CTRL_CONF1_OUTPUT_LOCK_EN_MASK;
+			reg1 |= FLL_CTRL_CONF1_OUTPUT_LOCK_EN(1);
+			reg1 &= ~FLL_CTRL_CONF1_MODE_MASK;
+			reg1 |= FLL_CTRL_CONF1_MODE(1);
+			FLL_CTRL[which_fll].FLL_CONF1 = reg1;
+		}
+
+		/*
+		 * In case the FLL frequency was set while it was off, update it
+		 * immediately
+		 */
+		uint32_t freq = flls_frequency[which_fll];
+		if (freq) {
+			if (pi_fll_set_frequency(which_fll, freq, 0))
+				abort();
+		} else {
+			freq = fll_get_frequency_from_mult_div(
+				READ_FLL_CTRL_CONF1_MULTI_FACTOR(reg1),
+				READ_FLL_CTRL_CONF1_CLK_OUT_DIV(reg1));
+			flls_frequency[which_fll] = DEFAULT_SYSTEM_CLOCK; //freq;
+		}
+		/* TODO: see if we need this
+		if (pi_fll_set_frequency(which_fll, DEFAULT_SYSTEM_CLOCK, 0) ==
+		    -1)
+			exit(-1);
+*/
+	}
+}
+
+int pi_fll_get_frequency(fll_type_t which_fll, uint8_t real)
+{
+	if (real) {
+		/* Frequency calculation from real world */
+		int real_freq = 0;
+		real_freq = fll_get_frequency_from_mult_div(
+			FLL_CTRL[which_fll].FLL_STATUS,
+			READ_FLL_CTRL_CONF1_CLK_OUT_DIV(
+				FLL_CTRL[which_fll].FLL_CONF1));
+
+		/* Update Frequency */
+		flls_frequency[which_fll] = real_freq;
+	}
+	return flls_frequency[which_fll];
+}
+
+void pi_fll_deinit(fll_type_t which_fll)
+{
+	flls_frequency[which_fll] = 0;
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_gpio.c

@@ -0,0 +1,239 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ //#include "FreeRTOS.h"
+ //#include "FreeRTOSConfig.h"
+ //#include "kernel/include/task.h"		// Needed for configASSERT
+
+ #include "core-v-mcu-config.h"
+ #include "efpga_template_reg_defs.h"
+ #include "hal_apb_gpio_reg_defs.h"
+ #include "hal_gpio.h"
+
+
+void hal_efpgaio_output(uint8_t efpgaio_num, efpgaio_enum_typedef value) {
+
+Efpga_t *efpga = (Efpga_t*)EFPGAIO_START_ADDR;
+
+switch(value) {
+	case CLEAR:
+		if (efpgaio_num < 32)
+			efpga->fpgaio_out31_00 &= ~(1 << efpgaio_num) ;
+		else if (efpgaio_num < 64)
+			efpga->fpgaio_out63_32 &= ~(1 << (efpgaio_num-32)) ;
+		else if (efpgaio_num < 80)
+			efpga->fpgaio_out79_64 &= ~(1 << (efpgaio_num-64)) ;
+		break;
+	case SET:
+		if (efpgaio_num < 32)
+			efpga->fpgaio_out31_00 |= (1 << efpgaio_num) ;
+		else if (efpgaio_num < 64)
+			efpga->fpgaio_out63_32 |= (1 << (efpgaio_num-32)) ;
+		else if (efpgaio_num < 80)
+			efpga->fpgaio_out79_64 |= (1 << (efpgaio_num-64)) ;
+		break;
+	case TOGGLE:
+		if (efpgaio_num < 32)
+			efpga->fpgaio_out31_00 ^= (1 << efpgaio_num) ;
+		else if (efpgaio_num < 64)
+			efpga->fpgaio_out63_32 ^= (1 << (efpgaio_num-32)) ;
+		else if (efpgaio_num < 80)
+			efpga->fpgaio_out79_64 ^= (1 << (efpgaio_num-64)) ;
+		break;
+
+	default:
+		break;
+ }
+}
+
+void hal_efpgaio_outen(uint8_t efpgaio_num, efpgaio_enum_typedef value) {
+
+	Efpga_t *efpga = (Efpga_t*)EFPGAIO_START_ADDR;
+
+	switch(value) {
+		case CLEAR:
+			if (efpgaio_num < 32)
+				efpga->fpgaio_oe31_00 &= ~(1 << efpgaio_num) ;
+			else if (efpgaio_num < 64)
+				efpga->fpgaio_oe63_32 &= ~(1 << (efpgaio_num-32)) ;
+			else if (efpgaio_num < 80)
+				efpga->fpgaio_oe79_64 &= ~(1 << (efpgaio_num-64)) ;
+			break;
+		case SET:
+			if (efpgaio_num < 32)
+				efpga->fpgaio_oe31_00 |= (1 << efpgaio_num) ;
+			else if (efpgaio_num < 64)
+				efpga->fpgaio_oe63_32 |= (1 << (efpgaio_num-32)) ;
+			else if (efpgaio_num < 80)
+				efpga->fpgaio_oe79_64 |= (1 << (efpgaio_num-64)) ;
+			break;
+		default:
+			break;
+ }
+}
+
+int hal_efpgaio_input(uint8_t efpgaio_num) {
+ int retval=-1;
+	Efpga_t *efpga = (Efpga_t*)EFPGAIO_START_ADDR;
+	if (efpgaio_num < 32)
+		retval = (efpga->fpgaio_in31_00 >> efpgaio_num) & 0x1 ;
+	else if (efpgaio_num < 64)
+		retval = (efpga->fpgaio_in63_32 >> (efpgaio_num-32)) & 0x1 ;
+	else if (efpgaio_num < 80)
+		retval = (efpga->fpgaio_in79_64 >> (efpgaio_num-64)) & 0x1 ;
+}
+
+void hal_efpgaio_event(uint8_t event_num) {
+
+	Efpga_t *efpga = (Efpga_t*)EFPGAIO_START_ADDR;
+	efpga->fpga_event15_00 |= (1 << event_num);
+	efpga->fpga_event15_00 &= ~(1 << event_num);
+
+}
+
+void hal_efpgaio_status(gpio_hal_typedef *hgpio){
+	Efpga_t *efpga = (Efpga_t*)EFPGAIO_START_ADDR;
+	if (hgpio->number < 32) {
+		hgpio->out_val  = (efpga->fpgaio_out31_00 >> hgpio->number) & 0x1;
+		hgpio->in_val   = (efpga->fpgaio_in31_00  >> hgpio->number) & 0x1;
+		hgpio->mode = (efpga->fpgaio_oe31_00  >> hgpio->number) & 0x1;
+	} else if (hgpio->number < 64) {
+		hgpio->out_val  = (efpga->fpgaio_out63_32 >> (hgpio->number - 32)) & 0x1;
+		hgpio->in_val   = (efpga->fpgaio_in63_32  >> (hgpio->number - 32)) & 0x1;
+		hgpio->mode = (efpga->fpgaio_oe63_32  >> (hgpio->number - 32)) & 0x1;
+	} else if (hgpio->number < 64) {
+		hgpio->out_val  = (efpga->fpgaio_out79_64 >> (hgpio->number - 64)) & 0x1;
+		hgpio->in_val   = (efpga->fpgaio_in79_64  >> (hgpio->number - 64)) & 0x1;
+		hgpio->mode = (efpga->fpgaio_oe79_64  >> (hgpio->number - 64)) & 0x1;
+	}
+}
+
+
+void hal_write_gpio(uint8_t gpio_num, uint8_t value) {
+	if (value) {
+		hal_set_gpio(gpio_num);
+	} else {
+		hal_clr_gpio(gpio_num);
+	}
+}
+
+void hal_set_gpio(uint8_t gpio_num) {
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+
+	papbgpio->setgpio_b.gpio_num = gpio_num;
+}
+
+void hal_clr_gpio(uint8_t gpio_num) {
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+
+	papbgpio->clrgpio_b.gpio_num = gpio_num;
+}
+
+void hal_toggle_gpio(uint8_t gpio_num) {
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+
+	papbgpio->toggpio_b.gpio_num = gpio_num;
+}
+
+void hal_set_gpio_num(uint8_t gpio_num){
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	unsigned int value = 0xff;
+
+	while ((value & 0xff) != gpio_num) {
+		papbgpio->setsel= gpio_num;		// Set address for following reads
+		value = papbgpio->rdstat;
+	}
+}
+
+void hal_read_gpio_status(gpio_hal_typedef *hgpio){
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	unsigned int value = 0xff;
+
+	while ((value & 0xff) != hgpio->number) {
+		papbgpio->setsel_b.gpio_num = hgpio->number;		// Set address for following reads
+		value = papbgpio->rdstat;
+	}
+	hgpio->mode = (uint8_t)((value >> 24) & 0x3); //papbgpio->rdstat_b.mode;
+	hgpio->int_type = (uint8_t)((value >> 17) & 0x7); //papbgpio->rdstat_b.inttype;
+	hgpio->int_en = (uint8_t)((value >> 16) & 0x1); //papbgpio->rdstat_b.inten;
+	hgpio->in_val = (uint8_t)((value >> 12) & 0x1); //papbgpio->rdstat_b.input;
+	hgpio->out_val = (uint8_t)((value >> 8) & 0x1); //papbgpio->rdstat_b.output;
+	hgpio->number = (uint8_t)((value >> 0) & 0xFF); //papbgpio->rdstat_b.number;
+
+}
+
+void hal_read_gpio_status_raw(uint8_t gpio_num, uint32_t* register_value){
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	unsigned int value = 0xff;
+
+	while ((value & 0xff) != gpio_num) {
+		papbgpio->setsel_b.gpio_num = gpio_num;		// Set address for following reads
+		value = papbgpio->rdstat;
+	}
+
+	*register_value = value;
+}
+
+void hal_gpio_int_ack (uint8_t gpio_num) {
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	papbgpio->intack = gpio_num;
+}
+
+void hal_set_gpio_mode(uint8_t gpio_num, uint8_t gpio_mode){
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	unsigned int value = gpio_num;
+	value = (value & 0xfcffffff) | (gpio_mode << 24);
+	//papbgpio->setmode_b.gpio_num = gpio_num;  //ToDo: is there a race here -- do we need to write both at same time?
+	//papbgpio->setmode_b.mode = gpio_mode;
+	papbgpio->setmode = value;
+}
+
+void hal_set_gpio_interrupt(uint8_t gpio_num, uint8_t interrupt_type, uint8_t interrupt_enable){
+	unsigned int regval;
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	regval = papbgpio->setint;
+	regval = regval & 0xFFF0FF00;
+
+	regval = regval | (((interrupt_type & REG_SETINT_INTTYPE_MASK) << REG_SETINT_INTTYPE_LSB ) |
+			 ((interrupt_enable & REG_SETINT_INTENABLE_MASK) << REG_SETINT_INTENABLE_LSB) |
+			 ((gpio_num & REG_SETINT_gpio_num_MASK ) << REG_SETINT_gpio_num_LSB));
+
+	papbgpio->setint = regval;
+}
+
+void hal_enable_gpio_interrupt(uint8_t gpio_num){
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	unsigned int regval = papbgpio->setint;
+	regval = regval & (~(REG_SETINT_gpio_num_MASK << REG_SETINT_gpio_num_LSB));
+	regval = regval & (~(REG_SETINT_INTENABLE_MASK << REG_SETINT_INTENABLE_LSB));
+	regval = regval | (((0x1 & REG_SETINT_INTENABLE_MASK) << REG_SETINT_INTENABLE_LSB) |
+			 ((gpio_num & REG_SETINT_gpio_num_MASK ) << REG_SETINT_gpio_num_LSB));
+
+	papbgpio->setint = regval;
+}
+
+void hal_disable_gpio_interrupt(uint8_t gpio_num) {
+
+	ApbGpio_t*	papbgpio = (ApbGpio_t*)GPIO_START_ADDR;
+	unsigned int regval = papbgpio->setint;
+	regval = regval & (~(REG_SETINT_gpio_num_MASK << REG_SETINT_gpio_num_LSB));
+	regval = regval & (~(REG_SETINT_INTENABLE_MASK << REG_SETINT_INTENABLE_LSB));
+	regval = regval | ((gpio_num & REG_SETINT_gpio_num_MASK ) << REG_SETINT_gpio_num_LSB);
+
+	papbgpio->setint = regval;
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_gpio_pulp.c

@@ -0,0 +1,171 @@
+/*
+ * Copyright (C) 2020 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* Driver to control and configure the PULP GPIO pins */
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#include <stdint.h>
+#include <assert.h>
+#include <hal_gpio_pulp.h>
+#include <hal_pinmux1.h>
+#include <bits.h>
+#include <pulp_io.h>
+
+#include "core-v-mcu-pulp-mem-map.h"
+
+int gpio_pin_conf_pad(int pin, uint32_t flags)
+{
+	assert(0 <= pin && pin < 32);
+
+	/* this is only correct if the static assert in gpio.h regarding padcfg*
+	 * registers doesn't fail
+	 */
+	uintptr_t pad_conf_reg =
+		(((uintptr_t)pin & 0xf) >> 3) * 4 +
+		(uintptr_t)(PULP_GPIO_ADDR + GPIO_PADCFG0_OFFSET);
+	uint32_t pad_shift = (pin & 0x3) << 3; /* (0,1) (8,9) (16,17) (24,25) */
+	uint32_t val = (flags & GPIO_PULL_ENABLE) |
+		       (flags & GPIO_DRIVE_STRENGTH_HIGH) << 1;
+
+	writew(val << pad_shift, pad_conf_reg);
+
+	return 0;
+}
+
+/* for now we only handle the gpio from 0-31 and ignore 32-63 */
+int gpio_pin_configure(int pin, uint32_t flags)
+{
+	/* check for misconfigurations */
+	assert(!((flags & GPIO_INPUT) && (flags & GPIO_OUTPUT)));
+
+	/* set pad mux to gpio */
+	pinmux_pin_set(pin, PINMUX_FUNC_B);
+
+	/* configure pad pull and drive */
+	gpio_pin_conf_pad(pin, flags);
+
+	/* configure direction */
+	uint32_t pads = readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADDIR_OFFSET));
+	WRITE_BIT(pads, pin, flags & GPIO_OUTPUT);
+	writew(pads, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADDIR_OFFSET));
+
+	/* default value to prevent glitches */
+	if (flags & GPIO_OUTPUT_INIT_HIGH)
+		gpio_pin_set_raw(pin, 1);
+
+	if (flags & GPIO_OUTPUT_INIT_LOW)
+		gpio_pin_set_raw(pin, 0);
+
+	/* control pad clock gating: need to enable clock for inputs */
+	uint32_t en = readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_GPIOEN_OFFSET));
+	WRITE_BIT(en, pin, GPIO_INPUT);
+	writew(en, (uintptr_t)(PULP_GPIO_ADDR + GPIO_GPIOEN_OFFSET));
+
+	return 0;
+}
+
+inline int gpio_port_get_raw(uint32_t *value)
+{
+	/* this api is a bit dumb but the return value is mean to signal an
+	 * error. This never happens in our implementation.
+	 */
+	*value = readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADIN_OFFSET));
+
+	return 0;
+}
+
+inline int gpio_port_set_masked_raw(uint32_t mask, uint32_t value)
+{
+	uint32_t outval =
+		readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+	writew((outval & ~mask) | (value & mask),
+	       (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+
+	return 0;
+}
+
+inline int gpio_port_set_bits_raw(uint32_t mask)
+{
+	uint32_t outval =
+		readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+	writew(outval | mask, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+
+	return 0;
+}
+
+inline int gpio_port_clear_bits_raw(uint32_t mask)
+{
+	uint32_t outval =
+		readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+	writew(outval & ~mask,
+	       (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+
+	return 0;
+}
+
+inline int gpio_port_toggle_bits(uint32_t mask)
+{
+	uint32_t outval =
+		readw((uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+	writew(outval ^ mask, (uintptr_t)(PULP_GPIO_ADDR + GPIO_PADOUT_OFFSET));
+
+	return 0;
+}
+
+inline int gpio_pin_get_raw(int pin)
+{
+	assert(0 <= pin && pin < 32);
+
+	uint32_t value = 0;
+	int ret = gpio_port_get_raw(&value);
+	if (!ret)
+		ret = (value & BIT(pin)) != 0;
+
+	return ret;
+}
+
+inline int gpio_pin_set_raw(int pin, int value)
+{
+	assert(0 <= pin && pin < 32);
+
+	if (value != 0)
+		gpio_port_set_bits_raw(BIT(pin));
+	else
+		gpio_port_clear_bits_raw(BIT(pin));
+
+	return 0;
+}
+
+inline int gpio_pin_toggle(int pin)
+{
+	return gpio_port_toggle_bits(BIT(pin));
+}
+/* TODO: gpio interrupt handling and configuration */
+/* static inline int gpio_pin_interrupt_configure() */
+/* { */
+/* } */
+
+/* static inline int gpio_manage_callback(){ */
+
+/* } */
+/* static inline int gpio_enable_callback(){ */
+
+/* } */
+/* static inline int gpio_disable_callback(){ */
+
+/* } */

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_irq.c

@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+/* Driver to control and configure the PULP IRQ (apb_interrupt_control)*/
+
+#include <csr.h>
+#include <pulp_io.h>
+#include <stdint.h>
+
+#include "core-v-mcu-pulp-mem-map.h"
+#include "hal_irq.h"
+
+/* utility functions for PULPs external interrupt controller */
+void irq_mask(uint32_t mask)
+{
+	writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_OFFSET));
+}
+
+void irq_enable(uint32_t mask)
+{
+	writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_SET_OFFSET));
+}
+
+void irq_disable(uint32_t mask)
+{
+	writew(mask, (uintptr_t)(PULP_FC_IRQ_ADDR + IRQ_REG_MASK_CLEAR_OFFSET));
+}
+
+/* utility functions for the core level interrupt (CLINT) described in the
+ * RISC-V privileged specification */
+
+uint32_t irq_clint_disable()
+{
+	uint32_t val = csr_read_clear(CSR_MSTATUS, MSTATUS_IE);
+	return val;
+}
+
+uint32_t irq_clint_enable()
+{
+	uint32_t val = 0;
+	val = csr_read(CSR_MSTATUS);
+
+	val = csr_read_set(CSR_MSTATUS, MSTATUS_IE);
+	//csr_write(CSR_MIE, BIT(25));
+	val = csr_read(CSR_MSTATUS);
+	return val;
+}
+
+/* TODO: make this a constructor? */
+void irq_init()
+{
+	/* the debug module could have enabled irq so we disable it during
+	 * initialization
+	 */
+	irq_disable(0xffffffff);
+}
+

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_pinmux.c

@@ -0,0 +1,46 @@
+/*
+ * Copyright 2021 QuickLogic
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ 
+ //#include "FreeRTOS.h"
+ //#include "FreeRTOSConfig.h"
+//#include "kernel/include/task.h"		// Needed for configASSERT
+ 
+ #include "core-v-mcu-config.h"
+ #include "hal_apb_soc_ctrl_regs.h"
+ #include "hal_pinmux.h"
+
+ void hal_setpullup(uint8_t io_num, uint8_t on) {
+ 	SocCtrl_t*		psoc_ctrl = SOC_CTRL_START_ADDR;
+
+ 	configASSERT (io_num < N_IO);
+	psoc_ctrl->io_ctrl_b[io_num].cfg = on;
+ }
+ 
+ void hal_setpinmux(uint8_t io_num, uint8_t mux_sel) {
+ 	SocCtrl_t*		psoc_ctrl = SOC_CTRL_START_ADDR;
+ 	
+ 	configASSERT (io_num < N_IO);
+	psoc_ctrl->io_ctrl_b[io_num].mux = mux_sel;
+ }
+ 
+ uint8_t hal_getpinmux(uint8_t io_num) {
+ 	SocCtrl_t*		psoc_ctrl = SOC_CTRL_START_ADDR;
+ 	
+ 	configASSERT (io_num < N_IO);
+	return psoc_ctrl->io_ctrl_b[io_num].mux;
+ }

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_pinmux1.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2020 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ * Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+/* Driver to control and configure pad mux */
+
+#include <stdint.h>
+#include <assert.h>
+#include <hal_pinmux1.h>
+#include <pulp_io.h>
+
+#include "core-v-mcu-pulp-mem-map.h"
+#include "hal_apb_soc.h"
+
+/* TODO: we only support pin 0-31 */
+
+int pinmux_pin_set(int pin, uint32_t func)
+{
+	assert(0 <= pin && pin < 32);
+
+	uintptr_t padfun_reg =
+		((pin & 0xf) >> 4) * 4 +
+		(PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADFUN0_OFFSET);
+	uint32_t padfun_shift = (pin & 0x7) << 1; /* 16 pads a 2 bits per reg */
+	writew((func & 0x3) << padfun_shift, padfun_reg);
+
+	return 0;
+}
+
+int pinmux_pin_get(int pin, uint32_t *func)
+{
+	assert(0 <= pin && pin < 32);
+
+	uintptr_t padfun_reg =
+		((pin & 0xf) >> 4) * 4 +
+		(PULP_APB_SOC_CTRL_ADDR + APB_SOC_PADFUN0_OFFSET);
+	uint32_t padfun_shift = (pin & 0x7) << 1; /* 16 pads a 2 bits per reg */
+	uint32_t padfunval = readw(padfun_reg);
+	*func = (padfunval >> padfun_shift) & 0x3;
+	return 0;
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_soc_eu.c

@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Driver to control and configure the PULP event unit */
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ */
+
+#include <pulp_io.h>
+#include <stdint.h>
+#include "core-v-mcu-config.h"
+#include "core-v-mcu-memory-map.h" //ToDo: this should be merged into config.h
+#include "hal_soc_eu.h"
+
+void soc_eu_mask_set(uint32_t offset, uint32_t mask)
+{
+	writew(mask, (uintptr_t)(SOC_EU_ADDR + offset));
+}
+
+uint32_t soc_eu_mask_get(uint32_t offset)
+{
+	return readw((uintptr_t)(SOC_EU_ADDR + offset));
+}
+
+/* void soc_eu_irq_mask_set(uint32_t mask) */
+/* { */
+/* 	writew(mask, PULP_SOC_EU_ADDR + ) */
+/* } */
+
+/* uint32_t soc_eu_irq_mask_get() */
+/* { */
+/* } */
+
+void pulp_soc_eu_event_init()
+{
+	/* deactivate all soc events */
+	for (int i = 0; i < SOC_NB_EVENT_REGS; i++) {
+		soc_eu_mask_set(SOC_FC_FIRST_MASK + i * 4, 0xffffffff);
+	}
+}

bsp/core-v-mcu/Libraries/core_v_hal_libraries/core_v_hal/source/hal_timer_irq.c

@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2019 ETH Zurich and University of Bologna
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Driver to configure PULP timer as periodic interrupt source */
+/* Author: Robert Balas (balasr@iis.ee.ethz.ch)
+ *         Germain Haugou (germain.haugou@iis.ee.ethz.ch)
+ */
+
+#include <bits.h>
+#include <pulp_io.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "core-v-mcu-pulp-mem-map.h"
+#include "hal_timer.h"
+#include "hal_timer_irq.h"
+//#include "FreeRTOSConfig.h"
+
+/* TODO: used to measure elapsed time since last "visit" */
+static uint32_t last_count;
+int timer_irq_disable(){
+	writew (0,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET));
+	writew (0,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_HI_OFFSET));
+
+}
+
+int timer_irq_init(uint32_t ticks)
+{
+	/* TODO: enable soc_eu timer interrupt */
+
+	/* set the interrupt interval */
+	timer_irq_set_timeout(ticks, false);
+
+	/* We use only one of the 32-bit timer, leaving the other half available
+	 * as an additional timer. We didn't opt for using both together as
+	 * 64-bit timer.
+	 *
+	 * Enable timer, use 32khz ref clock as source. Timer will reset
+	 * automatically to zero after causing an interrupt.
+	 */
+/* use high timer for now as int actually gets to cpu */
+#ifdef configMTIME_BASE_ADDRESS
+	writew(0xc000000f,(uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET));
+#else
+	writew(TIMER_CFG_LO_ENABLE_MASK | TIMER_CFG_LO_RESET_MASK |
+		       TIMER_CFG_LO_MODE_MASK |
+		       TIMER_CFG_LO_IRQEN_MASK,
+	       (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CFG_LO_OFFSET));
+#endif
+
+	return 0;
+}
+
+int timer_irq_set_timeout(uint32_t ticks, bool idle)
+{
+	(void)idle;
+	/* fast reset, value doesn't matter */
+
+	writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_LO_OFFSET));
+	writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_LO_OFFSET));
+	writew(1, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_RESET_HI_OFFSET));
+//	writew(ticks, (uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CMP_HI_OFFSET));
+
+	return 0;
+}
+
+/* TODO: implement */
+uint32_t timer_irq_clock_elapsed()
+{
+	return 0;
+}
+
+uint32_t timer_irq_cycle_get_32()
+{
+	return readw((uintptr_t)(PULP_FC_TIMER_ADDR + TIMER_CNT_LO_OFFSET));
+
+}

bsp/core-v-mcu/core-v-cv32e40p/.config

@@ -0,0 +1,955 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=4
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+# CONFIG_RT_USING_OVERFLOW_CHECK is not set
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+# CONFIG_RT_KSERVICE_USING_STDLIB is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+# CONFIG_RT_DEBUG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+# CONFIG_RT_SERIAL_USING_DMA is not set
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_WIFI is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_SOC_RISCV_FAMILY_Core_V=y
+CONFIG_SOC_RISCV_SERIES_Core_V=y
+
+#
+# Hardware Drivers Config
+#
+CONFIG_SOC_Core_V_MCU=y
+
+#
+# On-chip Peripheral Drivers
+#
+CONFIG_BSP_USING_GPIO=y
+CONFIG_BSP_USING_UART=y
+CONFIG_BSP_USING_UART1=y
+
+#
+# Onboard Peripheral Drivers
+#
+
+#
+# Board extended module Drivers
+#
+
+#
+# Onboard System Settings
+#
+CONFIG_DEFAULT_SYSTEM_CLOCK=5000000u
+CONFIG_configTOTAL_HEAP_SIZE="( unsigned int) (64 * 1024 )"

bsp/core-v-mcu/core-v-cv32e40p/Kconfig

@@ -0,0 +1,21 @@
+mainmenu "RT-Thread Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "../Libraries/Kconfig"
+source "board/Kconfig"