[update] add GBE dirver for stm32mp1dk1

bsp/stm32/libraries/STM32MPxx_HAL/SConscript

@@ -54,8 +54,8 @@ if GetDepend(['RT_USING_CAN']):
 #    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_tim_ex.c']
 #    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_lptim.c']
 
-if GetDepend(['BSP_USING_ETH']):
-    src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c']
+# if GetDepend(['BSP_USING_ETH']):
+#     src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_eth.c']
 
 if GetDepend(['BSP_USING_WWDG']):
     src += ['STM32MP1xx_HAL_Driver/Src/stm32mp1xx_hal_wwdg.c']

bsp/stm32/stm32mp157a-st-discovery/board/Kconfig

@@ -50,8 +50,12 @@ menu "Onboard Peripheral Drivers"
             config RS485_UART_DEVICE_NAME
             string "the uart name for rs485"
             default "uart3"
-
         endif
+    
+    config BSP_USING_GBE
+        bool "Enable Ethernet"
+        default n
+        select RT_USING_LWIP
 
 endmenu
 
@@ -196,7 +200,7 @@ menu "On-chip Peripheral Drivers"
                         range 1 176
                         default 117
                 endif
-	    menuconfig BSP_USING_I2C3
+            menuconfig BSP_USING_I2C3
                 bool "Enable I2C3 BUS (software simulation)"
                 default n
                 if BSP_USING_I2C3
@@ -210,6 +214,21 @@ menu "On-chip Peripheral Drivers"
                         range 1 191
                         default 181
                 endif
+            menuconfig BSP_USING_I2C4
+                bool "Enable I2C2 BUS (software simulation)"
+                default n
+                if BSP_USING_I2C4
+                    comment "Notice: PD12 --> 60; PF15 --> 95" 
+                    config BSP_I2C4_SCL_PIN
+                        int "i2c4 scl pin number"
+                        range 1 191
+                        default 60
+                    config BSP_I2C4_SDA_PIN
+                        int "I2C4 sda pin number"
+                        range 1 191
+                        default 95
+                endif
+
         endif
 
     menuconfig BSP_USING_SPI

bsp/stm32/stm32mp157a-st-discovery/board/SConscript

@@ -40,6 +40,9 @@ if GetDepend(['BSP_USING_PMIC']):
 if GetDepend(['BSP_USING_RS485']):
     src += Glob('ports/drv_rs485.c')
 
+if GetDepend(['BSP_USING_GBE']):
+    src += Glob('ports/drv_eth.c')
+
 if GetDepend(['BSP_USING_OPENAMP']):
     src +=  Glob('CubeMX_Config/CM4/Src/ipcc.c')
     src +=  Glob('CubeMX_Config/CM4/Src/openamp.c')

bsp/stm32/stm32mp157a-st-discovery/board/linker_scripts/link.icf

@@ -5,7 +5,7 @@
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 /*-Memory Regions-*/
 define symbol __ICFEDIT_region_text_start__ = 0x10000000;
-define symbol __ICFEDIT_region_text_end__   = 0x1001FFFF;
+define symbol __ICFEDIT_region_text_end__   = 0x1002FFFF;
 define symbol __ICFEDIT_region_data_start__ = 0x10030000;
 define symbol __ICFEDIT_region_data_end__   = 0x1003FFFF;
 /*-Sizes-*/

bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.c

@@ -0,0 +1,882 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-07-20     thread-liu        the first version
+ */
+
+#include "board.h"
+#include "drv_config.h"
+#include <netif/ethernetif.h>
+#include "lwipopts.h"
+#include "drv_eth.h"
+
+#if defined(BSP_USING_GBE)
+
+#define DRV_DEBUG
+//#define ETH_RX_DUMP
+//#define ETH_TX_DUMP
+#define LOG_TAG             "drv.emac"
+#include <drv_log.h>
+
+#define MAX_ADDR_LEN 6
+rt_base_t level;
+
+#define TX_ADD_BASE         0x2FFC3000
+#define RX_ADD_BASE         0x2FFC5000
+#define TX_DMA_ADD_BASE     0x2FFC7000
+#define RX_DMA_ADD_BASE     0x2FFC7100
+
+#if defined(__ICCARM__)
+/* transmit buffer */
+#pragma location = TX_ADD_BASE
+static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE];
+/* Receive buffer */
+#pragma location = RX_ADD_BASE
+static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE];
+/* Transmit DMA descriptors */
+#pragma location = TX_DMA_ADD_BASE
+static TxDmaDesc txDmaDesc[ETH_TXBUFNB];
+/* Receive DMA descriptors */
+#pragma location = RX_DMA_ADD_BASE
+static RxDmaDesc rxDmaDesc[ETH_RXBUFNB];
+
+#elif defined(__CC_ARM) || defined(__CLANG_ARM)
+/* transmit buffer */
+static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE)));
+/* Receive buffer */
+static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE)));
+/* Transmit DMA descriptors */
+static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE)));
+/* Receive DMA descriptors */
+static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE)));
+
+#elif defined ( __GNUC__ )
+/* transmit buffer */
+static rt_uint8_t txBuffer[ETH_TXBUFNB][ETH_TX_BUF_SIZE] __attribute__((at(TX_ADD_BASE)));
+/* Receive buffer */
+static rt_uint8_t rxBuffer[ETH_RXBUFNB][ETH_RX_BUF_SIZE] __attribute__((at(RX_ADD_BASE)));
+/* Transmit DMA descriptors */
+static TxDmaDesc txDmaDesc[ETH_TXBUFNB] __attribute__((at(TX_DMA_ADD_BASE)));
+/* Receive DMA descriptors */
+static RxDmaDesc rxDmaDesc[ETH_RXBUFNB] __attribute__((at(RX_DMA_ADD_BASE)));
+#endif
+
+/* Current transmit descriptor */
+static rt_uint8_t txIndex = 0;
+/* Current receive descriptor */
+static rt_uint8_t rxIndex = 0;
+
+/* eth rx event */
+static struct rt_event rx_event = {0};
+
+#define ETH_TIME_OUT 100000
+
+struct rt_stm32_eth
+{
+    /* inherit from ethernet device */
+    struct eth_device parent;
+#ifndef PHY_USING_INTERRUPT_MODE
+    rt_timer_t poll_link_timer;
+#endif
+    /* interface address info, hw address */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];
+    /* eth speed */
+    rt_uint32_t    eth_speed;
+    /* eth duplex mode */
+    rt_uint32_t    eth_mode;
+};
+static struct rt_stm32_eth stm32_eth_device = {0};
+
+#if defined(ETH_RX_DUMP) || defined(ETH_TX_DUMP)
+#define __is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ')
+static void dump_hex(const rt_uint8_t *ptr, rt_size_t buflen)
+{
+    unsigned char *buf = (unsigned char *)ptr;
+    int i, j;
+
+    for (i = 0; i < buflen; i += 16)
+    {
+        rt_kprintf("%08X: ", i);
+
+        for (j = 0; j < 16; j++)
+        {
+            if (i + j < buflen)
+            {
+                rt_kprintf("%02X ", buf[i + j]);
+            }
+            else
+            {
+                rt_kprintf("   ");
+            }
+        }
+        rt_kprintf(" ");
+
+        for (j = 0; j < 16; j++)
+        {
+            if (i + j < buflen)
+            {
+                rt_kprintf("%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
+            }
+        }
+        rt_kprintf("\n");
+    }
+}
+#endif
+
+static rt_err_t phy_write_reg(uint8_t phy_addr, uint8_t reg_addr, uint16_t reg_value)
+{
+    uint32_t temp;
+    volatile uint32_t tickstart = 0;
+    /* Take care not to alter MDC clock configuration */
+    temp = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
+    /* Set up a write operation */
+    temp |= ETH_MACMDIOAR_GOC_Val(1) | ETH_MACMDIOAR_GB;
+    /* PHY address */
+    temp |= (phy_addr << 21) & ETH_MACMDIOAR_PA;
+    /* Register address */
+    temp |= (reg_addr << 16) & ETH_MACMDIOAR_RDA;
+
+    /* Data to be written in the PHY register */
+    ETH->MACMDIODR = reg_value & ETH_MACMDIODR_GD;
+
+    /* Start a write operation */
+    ETH->MACMDIOAR = temp;
+    /* Wait for the write to complete */
+    tickstart = rt_tick_get();
+    while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
+    {
+        /* judge timeout */
+        if((rt_tick_get() - tickstart) > ETH_TIME_OUT)
+        {
+            LOG_E("PHY write reg %02x date %04x timeout!", reg_addr, reg_value);
+            return -RT_ETIMEOUT;
+        }
+    }
+    
+    return RT_EOK;
+}
+
+static uint16_t phy_read_reg(uint8_t phy_addr, uint8_t reg_addr)
+{
+    uint16_t reg_value = 0;
+    uint32_t status = 0;
+    volatile uint32_t tickstart = 0;
+    
+    /* Take care not to alter MDC clock configuration */
+    status = ETH->MACMDIOAR & ETH_MACMDIOAR_CR;
+    /* Set up a read operation */
+    status |= ETH_MACMDIOAR_GOC_Val(3) | ETH_MACMDIOAR_GB;
+    /* PHY address */
+    status |= (phy_addr << 21) & ETH_MACMDIOAR_PA;
+    /* Register address */
+    status |= (reg_addr << 16) & ETH_MACMDIOAR_RDA;
+
+    /* Start a read operation */
+    ETH->MACMDIOAR = status;
+    /* Wait for the read to complete */
+    tickstart = rt_tick_get();
+    while((ETH->MACMDIOAR & ETH_MACMDIOAR_GB) != 0)
+    {
+        /* judge timeout */
+        if((rt_tick_get() - tickstart) > ETH_TIME_OUT)
+        {
+            LOG_E("PHY read reg %02x timeout!", reg_addr);
+            return RT_ETIMEOUT;
+        }
+    }
+
+    /* Get register value */
+    reg_value = ETH->MACMDIODR & ETH_MACMDIODR_GD;
+
+    return reg_value;
+}
+
+static rt_err_t update_mac_mode(rt_uint32_t eth_speed, rt_uint32_t eth_mode)
+{
+   uint32_t status;
+
+   /* Read current MAC configuration */
+   status = ETH->MACCR;
+
+   if (eth_speed == PHY_1000M)
+   {
+      status &= ~ETH_MACCR_PS;
+      status &= ~ETH_MACCR_FES;
+   }
+   else if (eth_speed == PHY_100M)
+   {
+      status |= ETH_MACCR_PS;
+      status |= ETH_MACCR_FES;
+   }
+   /* 10M */
+   else
+   {
+      status |= ETH_MACCR_PS;
+      status &= ~ETH_MACCR_FES;
+   }
+
+   if (eth_mode == PHY_FULL_DUPLEX)
+   {
+      status |= ETH_MACCR_DM;
+   }
+   else
+   {
+      status &= ~ETH_MACCR_DM;
+   }
+
+   /* Update MAC configuration register */
+   ETH->MACCR = status;
+
+   return RT_EOK;
+}
+
+static void HAL_ETH_MspInit(void)
+{
+    GPIO_InitTypeDef GPIO_InitStruct = {0};
+    RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+    
+    if(IS_ENGINEERING_BOOT_MODE())
+    {
+        /** Initializes the peripherals clock 
+        */
+        PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ETH;
+        PeriphClkInit.EthClockSelection = RCC_ETHCLKSOURCE_PLL4;
+        if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+        {
+            Error_Handler();
+        }
+    }
+  
+    /* Enable SYSCFG clock */
+    __HAL_RCC_SYSCFG_CLK_ENABLE();
+    
+    /* Enable GPIO clocks */
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+    __HAL_RCC_GPIOE_CLK_ENABLE();
+    __HAL_RCC_GPIOG_CLK_ENABLE();
+
+    /* Select RGMII interface mode */
+    HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RGMII);
+    
+    /* Enable Ethernet MAC clock */
+    __HAL_RCC_ETH1MAC_CLK_ENABLE();
+    __HAL_RCC_ETH1TX_CLK_ENABLE();
+    __HAL_RCC_ETH1RX_CLK_ENABLE();
+    
+    /**ETH1 GPIO Configuration
+    PA1     ------>  ETH1_RX_CLK
+    PA7     ------>  ETH1_RX_CTL
+    PB0     ------>  ETH1_RXD2
+    PB1     ------>  ETH1_RXD3
+    PC4     ------>  ETH1_RXD0
+    PC5     ------>  ETH1_RXD1
+    PA2     ------>  ETH1_MDIO
+    PB11    ------>  ETH1_TX_CTL
+    PC1     ------>  ETH1_MDC
+    PC2     ------>  ETH1_TXD2
+    PE2     ------>  ETH1_TXD3
+    PG4     ------>  ETH1_GTX_CLK
+    PG5     ------>  ETH1_CLK125
+    PG13    ------>  ETH1_TXD0
+    PG14    ------>  ETH1_TXD1
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_11;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_2|GPIO_PIN_4|GPIO_PIN_5;
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_2;
+    HAL_GPIO_Init(GPIOE, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5|GPIO_PIN_13|GPIO_PIN_14;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); 
+
+    /* ETH interrupt Init */
+    HAL_NVIC_SetPriority(ETH1_IRQn, 0x01, 0x00);
+    HAL_NVIC_EnableIRQ(ETH1_IRQn);
+    
+    /* Configure PHY_RST (PG0) */
+    GPIO_InitStruct.Pin = GPIO_PIN_0;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_PULLUP;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
+
+    /* Reset PHY transceiver */
+    HAL_GPIO_WritePin(GPIOG, GPIO_PIN_0, GPIO_PIN_RESET);
+    rt_thread_mdelay(20);
+    HAL_GPIO_WritePin(GPIOG, GPIO_PIN_0, GPIO_PIN_SET);
+    rt_thread_mdelay(20);
+}
+
+static rt_err_t rt_stm32_eth_init(rt_device_t dev)
+{
+    RT_ASSERT(dev != RT_NULL);
+    
+    rt_uint32_t status, i;
+    volatile rt_uint32_t tickstart = 0;
+    rt_uint8_t  *macAddr = &stm32_eth_device.dev_addr[0];
+    
+    /* Initialize TX descriptor index */
+    txIndex = 0;
+    /* Initialize RX descriptor index */
+    rxIndex = 0;
+
+    HAL_ETH_MspInit();
+
+    /* Reset Ethernet MAC peripheral */
+    __HAL_RCC_ETH1MAC_FORCE_RESET();
+    __HAL_RCC_ETH1MAC_RELEASE_RESET();
+
+    /* Ethernet Software reset */
+    ETH->DMAMR |= ETH_DMAMR_SWR;
+    /* Wait for the reset to complete */
+    tickstart = rt_tick_get();
+    while (READ_BIT(ETH->DMAMR, ETH_DMAMR_SWR))
+    {
+        if(((HAL_GetTick() - tickstart ) > ETH_TIME_OUT))
+        {
+            LOG_E("ETH software reset timeout!");
+            return RT_ERROR;
+        }
+    }
+
+    /* Adjust MDC clock range depending on HCLK frequency */
+    ETH->MACMDIOAR = ETH_MACMDIOAR_CR_Val(5);
+
+    /* Use default MAC configuration */
+    ETH->MACCR = ETH_MACCR_DO;
+
+    /* Set the MAC address of the station */
+    ETH->MACA0LR = ((macAddr[3] << 24) | (macAddr[2] << 16) | (macAddr[1] << 8) | macAddr[0]);
+    ETH->MACA0HR = ((macAddr[5] << 8) | macAddr[4]);
+
+    /* The MAC supports 3 additional addresses for unicast perfect filtering */
+    ETH->MACA1LR = 0;
+    ETH->MACA1HR = 0;
+    ETH->MACA2LR = 0;
+    ETH->MACA2HR = 0;
+    ETH->MACA3LR = 0;
+    ETH->MACA3HR = 0;
+    
+    /* Initialize hash table */
+    ETH->MACHT0R = 0;
+    ETH->MACHT1R = 0;
+    
+    /* Configure the receive filter */
+    ETH->MACPFR = ETH_MACPFR_HPF | ETH_MACPFR_HMC;
+    
+    /* Disable flow control */
+    ETH->MACQ0TXFCR = 0;
+    ETH->MACRXFCR   = 0;
+    
+    /* Enable the first RX queue */
+    ETH->MACRXQC0R = ETH_MACRXQC0R_RXQ0EN_Val(1);
+    
+    /* Configure DMA operating mode */
+    ETH->DMAMR = ETH_DMAMR_INTM_Val(0) | ETH_DMAMR_PR_Val(0);
+    
+    /* Configure system bus mode */
+    ETH->DMASBMR |= ETH_DMASBMR_AAL;
+    
+    /* The DMA takes the descriptor table as contiguous */
+    ETH->DMAC0CR = ETH_DMAC0CR_DSL_Val(0);
+    
+    /* Configure TX features */
+    ETH->DMAC0TXCR = ETH_DMAC0TXCR_TXPBL_Val(1);
+
+    /* Configure RX features */
+    ETH->DMAC0RXCR = ETH_DMAC0RXCR_RXPBL_Val(1) | ETH_DMAC0RXCR_RBSZ_Val(ETH_RX_BUF_SIZE);
+
+    /* Enable store and forward mode for transmission */
+    ETH->MTLTXQ0OMR = ETH_MTLTXQ0OMR_TQS_Val(7) | ETH_MTLTXQ0OMR_TXQEN_Val(2) | ETH_MTLTXQ0OMR_TSF;
+
+    /* Enable store and forward mode for reception */
+    ETH->MTLRXQ0OMR = ETH_MTLRXQ0OMR_RQS_Val(7) | ETH_MTLRXQ0OMR_RSF;
+
+    /* Initialize TX DMA descriptor list */
+    for (i = 0; i < ETH_TXBUFNB; i++)
+    {
+        /* The descriptor is initially owned by the application */
+        txDmaDesc[i].tdes0 = 0;
+        txDmaDesc[i].tdes1 = 0;
+        txDmaDesc[i].tdes2 = 0;
+        txDmaDesc[i].tdes3 = 0;
+    }
+
+    /* Initialize RX DMA descriptor list */
+    for (i = 0; i < ETH_RXBUFNB; i++)
+    {
+        /* The descriptor is initially owned by the DMA */
+        rxDmaDesc[i].rdes0 = (uint32_t) rxBuffer[i];
+        rxDmaDesc[i].rdes1 = 0;
+        rxDmaDesc[i].rdes2 = 0;
+        rxDmaDesc[i].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
+    }
+    
+    /* Set Transmit Descriptor List Address Register */
+    ETH->DMAC0TXDLAR = (uint32_t) &txDmaDesc[0];
+    /* Length of the transmit descriptor ring */
+    ETH->DMAC0TXRLR = ETH_TXBUFNB - 1;
+    
+    /* Set Receive Descriptor List Address Register */
+    ETH->DMAC0RXDLAR = (uint32_t) &rxDmaDesc[0];
+    /* Length of the receive descriptor ring */
+    ETH->DMAC0RXRLR = ETH_RXBUFNB - 1;
+
+    /* Prevent interrupts from being generated when the transmit statistic
+     * counters reach half their maximum value */
+    ETH->MMCTXIMR = ETH_MMCTXIMR_TXLPITRCIM | ETH_MMCTXIMR_TXLPIUSCIM | ETH_MMCTXIMR_TXGPKTIM | ETH_MMCTXIMR_TXMCOLGPIM | ETH_MMCTXIMR_TXSCOLGPIM;
+    
+    /* Prevent interrupts from being generated when the receive statistic
+     * counters reach half their maximum value */
+    ETH->MMCRXIMR = ETH_MMCRXIMR_RXLPITRCIM | ETH_MMCRXIMR_RXLPIUSCIM | ETH_MMCRXIMR_RXUCGPIM | ETH_MMCRXIMR_RXALGNERPIM | ETH_MMCRXIMR_RXCRCERPIM;
+   
+    /* Disable MAC interrupts */
+    ETH->MACIER = 0;
+    
+    /* Enable the desired DMA interrupts */
+    ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE;
+    
+    /* Enable MAC transmission and reception */
+    ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
+   
+    /* Enable DMA transmission and reception */
+    ETH->DMAC0TXCR |= ETH_DMAC0TXCR_ST;
+    ETH->DMAC0RXCR |= ETH_DMAC0RXCR_SR;
+   
+    /* Reset PHY transceiver */
+    phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR, RTL8211F_BMCR_RESET);
+    status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR);
+    /* Wait for the reset to complete */
+    tickstart = rt_tick_get();
+    while (status & RTL8211F_BMCR_RESET)
+    {
+        if((rt_tick_get() - tickstart) > ETH_TIME_OUT)
+        {
+            LOG_E("PHY software reset timeout!");
+            return RT_ETIMEOUT;
+        }
+        else
+        {
+            status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMCR);
+        } 
+    }
+    
+    /* The PHY will generate interrupts when link status changes are detected */
+    phy_write_reg(RTL8211F_PHY_ADDR, RTL8211F_INER, RTL8211F_INER_AN_COMPLETE | RTL8211F_INER_LINK_STATUS);
+
+    return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    LOG_D("emac open");
+    return RT_EOK;
+}
+
+static rt_err_t rt_stm32_eth_close(rt_device_t dev)
+{
+    LOG_D("emac close");
+    return RT_EOK;
+}
+
+static rt_size_t rt_stm32_eth_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
+{
+    LOG_D("emac read");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_size_t rt_stm32_eth_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
+{
+    LOG_D("emac write");
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
+}
+
+static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
+{
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) 
+        {
+            rt_memcpy(args, stm32_eth_device.dev_addr, 6);
+        }
+        else 
+        {
+            return -RT_ERROR;
+        }
+        break;
+
+    default :
+        break;
+    }
+
+    return RT_EOK;
+}
+
+rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
+{
+    uint32_t framelen = 0;
+    struct pbuf *q = RT_NULL;
+    
+    /* Copy user data to the transmit buffer */
+    for (q = p; q != NULL; q = q->next)
+    {
+        /* Make sure the current buffer is available for writing */
+        if((txDmaDesc[txIndex].tdes3 & ETH_TDES3_OWN) != 0)
+        {
+            LOG_D("buffer not valid");
+            return ERR_USE;
+        }
+        
+        level = rt_hw_interrupt_disable();
+        rt_memcpy(&txBuffer[txIndex][framelen], q->payload, q->len);
+        framelen += q->len;
+        rt_hw_interrupt_enable(level);
+        
+        /* Check the frame length */
+        if (framelen > ETH_TX_BUF_SIZE - 1)
+        {
+            LOG_D(" tx buffer frame length over : %d", framelen);
+            return ERR_USE;
+        }
+    }
+    
+#ifdef ETH_TX_DUMP
+        rt_kprintf("Tx dump, len= %d\r\n", framelen);
+        dump_hex(txBuffer[txIndex], framelen);
+#endif
+
+    /* Set the start address of the buffer */
+    txDmaDesc[txIndex].tdes0 = (uint32_t)txBuffer[txIndex];
+    /* Write the number of bytes to send */
+    txDmaDesc[txIndex].tdes2 = ETH_TDES2_IOC | (framelen & ETH_TDES2_B1L);
+    /* Give the ownership of the descriptor to the DMA */
+    txDmaDesc[txIndex].tdes3 = ETH_TDES3_OWN | ETH_TDES3_FD | ETH_TDES3_LD;
+
+    /* Data synchronization barrier */
+    __DSB();
+
+    /* Clear TBU flag to resume processing */
+    ETH->DMAC0SR = ETH_DMAC0SR_TBU;
+    /* Instruct the DMA to poll the transmit descriptor list */
+    ETH->DMAC0TXDTPR = 0;
+    
+    if (++txIndex > ETH_TXBUFNB - 1)
+    {
+        txIndex = 0;
+    }
+
+    return ERR_OK;
+}
+
+struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
+{
+    rt_uint32_t framelength = 0;
+    uint32_t framelen = 0;
+    struct pbuf *p = RT_NULL, *q = RT_NULL;
+
+    /* The current buffer is available for reading */
+    if (!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_OWN)) 
+    {
+        /* FD and LD flags should be set */
+        if ((rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_FD) && (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_LD))
+            {
+                /* Make sure no error occurred */
+                if(!(rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_ES))
+                {
+                    /* Retrieve the length of the frame */
+                    framelength = rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL;
+                    /* check the frame length */
+                    framelength = (framelength > ETH_RX_BUF_SIZE) ? ETH_RX_BUF_SIZE : framelength;
+
+                    p = pbuf_alloc(PBUF_RAW, framelength, PBUF_RAM);
+                    if (p != NULL)
+                    {
+                        for (q = p; q != NULL; q = q->next)
+                        {
+                            level=rt_hw_interrupt_disable();
+                            rt_memcpy(q->payload, &rxBuffer[rxIndex][framelen], q->len);
+                            framelen += q->len;
+                            rt_hw_interrupt_enable(level);
+                            
+                            if (framelen > framelength)
+                            {
+                                LOG_E("frame len is too long!");
+                                return RT_NULL;
+                            }
+                        }
+                    }
+                }
+                else
+                {
+                    /* The received packet contains an error */
+                    LOG_D("the received packet contains an error!");
+                    return RT_NULL;
+                }
+                
+            }
+        else
+        {
+            /* The packet is not valid */
+            LOG_D("the packet is not valid");
+            return RT_NULL;
+        }
+
+        /* Set the start address of the buffer */
+        rxDmaDesc[rxIndex].rdes0 = (uint32_t)rxBuffer[rxIndex];
+        /* Give the ownership of the descriptor back to the DMA */
+        rxDmaDesc[rxIndex].rdes3 = ETH_RDES3_OWN | ETH_RDES3_IOC | ETH_RDES3_BUF1V;
+        
+#ifdef ETH_RX_DUMP
+        rt_kprintf("Rx dump, len= %d\r\n", framelen);
+        dump_hex(rxBuffer[rxIndex], framelen);
+#endif
+        /* Increment index and wrap around if necessary */
+        if (++rxIndex > ETH_RXBUFNB - 1)
+        {
+            rxIndex = 0;
+        }
+        /* Clear RBU flag to resume processing */
+        ETH->DMAC0SR = ETH_DMAC0SR_RBU;
+        /* Instruct the DMA to poll the receive descriptor list */
+        ETH->DMAC0RXDTPR = 0;
+    }
+    
+    return p;
+}
+
+void ETH1_IRQHandler(void)
+{
+    rt_uint32_t status = 0;
+    
+    /* enter interrupt */
+    rt_interrupt_enter();
+    /* Read DMA status register */
+    status = ETH->DMAC0SR;
+    /* Frame transmitted */
+    if (status & ETH_DMAC0SR_TI)
+    {
+        /* Clear the Eth DMA Tx IT pending bits */
+        ETH->DMAC0SR = ETH_DMAC0SR_TI;
+    }
+    /* Frame received */
+    else if (status & ETH_DMAC0SR_RI)
+    {
+        /* Disable RIE interrupt */
+        ETH->DMAC0IER &= ~ETH_DMAC0IER_RIE;
+        
+        rt_event_send(&rx_event, status);
+    }
+    /* ETH DMA Error */
+    if (status & ETH_DMAC0SR_AIS)
+    {
+        ETH->DMAC0IER &= ~ETH_DMAC0IER_AIE;
+        LOG_E("eth dam err");
+    }
+    /* Clear the interrupt flags */
+    ETH->DMAC0SR = ETH_DMAC0SR_NIS;
+    
+    /* leave interrupt */
+    rt_interrupt_leave();
+
+}
+
+static void phy_linkchange()
+{
+    rt_uint32_t status = 0;
+
+	/* Read status register to acknowledge the interrupt */
+    status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_INSR);
+	
+
+    if (status & (RTL8211F_BMSR_LINK_STATUS | RTL8211F_INSR_AN_COMPLETE))
+    {
+	    status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
+    	status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_BMSR);
+        if (status & RTL8211F_BMSR_LINK_STATUS)
+        {
+            LOG_D("link up");  
+
+			status = phy_read_reg(RTL8211F_PHY_ADDR, RTL8211F_PHYSR);
+            switch (status & RTL8211F_PHYSR_SPEED)
+            {
+            case RTL8211F_PHYSR_SPEED_10MBPS:
+              {
+                LOG_D("speed: 10M");
+                stm32_eth_device.eth_speed |= PHY_10M;
+              }
+            break;
+            
+            case RTL8211F_PHYSR_SPEED_100MBPS:
+              {
+                LOG_D("speed: 100M");
+                stm32_eth_device.eth_speed |= PHY_100M;
+              }
+            break;
+            
+            case RTL8211F_PHYSR_SPEED_1000MBPS:
+              {
+                LOG_D("speed: 1000M");
+                stm32_eth_device.eth_speed |= PHY_1000M;
+              }
+            break;
+            
+            /* Unknown speed */
+            default:
+                rt_kprintf("Invalid speed.");
+            break;    
+            }
+
+            stm32_eth_device.eth_mode = (status & RTL8211F_PHYSR_DUPLEX)? PHY_FULL_DUPLEX : PHY_HALF_DUPLEX ;
+
+            update_mac_mode(stm32_eth_device.eth_speed, stm32_eth_device.eth_mode);
+            /* send link up. */
+            eth_device_linkchange(&stm32_eth_device.parent, RT_TRUE);
+        }
+        else
+        {
+            LOG_I("link down");
+            eth_device_linkchange(&stm32_eth_device.parent, RT_FALSE);
+        }
+    }
+}
+
+#ifdef PHY_USING_INTERRUPT_MODE
+static void eth_phy_isr(void *args)
+{
+    rt_uint32_t status = 0;
+
+    phy_read_reg(RTL8211F_PHY_ADDR, PHY_INTERRUPT_FLAG_REG, (uint32_t *)&status);
+    LOG_D("phy interrupt status reg is 0x%X", status);
+
+    phy_linkchange();
+}
+#endif /* PHY_USING_INTERRUPT_MODE */
+
+static void phy_monitor_thread_entry(void *parameter)
+{
+    rt_uint32_t status = 0;
+    phy_linkchange();
+#ifdef PHY_USING_INTERRUPT_MODE
+    /* configuration intterrupt pin */
+    rt_pin_mode(PHY_INT_PIN, PIN_MODE_INPUT_PULLUP);
+    rt_pin_attach_irq(PHY_INT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_isr, (void *)"callbackargs");
+    rt_pin_irq_enable(PHY_INT_PIN, PIN_IRQ_ENABLE);
+
+    /* enable phy interrupt */
+    phy_write_reg(RTL8211F_PHY_ADDR, PHY_INTERRUPT_MASK_REG, PHY_INT_MASK);
+#if defined(PHY_INTERRUPT_CTRL_REG)
+    phy_write_reg( RTL8211F_PHY_ADDR, PHY_INTERRUPT_CTRL_REG, PHY_INTERRUPT_EN);
+#endif
+#else /* PHY_USING_INTERRUPT_MODE */
+    stm32_eth_device.poll_link_timer = rt_timer_create("phylnk", (void (*)(void*))phy_linkchange,
+                                        NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC);
+    if (!stm32_eth_device.poll_link_timer || rt_timer_start(stm32_eth_device.poll_link_timer) != RT_EOK)
+    {
+        LOG_E("Start link change detection timer failed");
+    }
+#endif /* PHY_USING_INTERRUPT_MODE */
+    while(1)
+    {
+        if (rt_event_recv(&rx_event, 0xffffffff, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
+                      RT_WAITING_FOREVER, &status) == RT_EOK)
+        {
+            /* check dma rx buffer */
+            if (ETH->DMAC0SR & ETH_DMAC0SR_RI)
+            {
+                /* Clear interrupt flag */
+                ETH->DMAC0SR = ETH_DMAC0SR_RI;
+                /* Process all pending packets */
+                while (rxDmaDesc[rxIndex].rdes3 & ETH_RDES3_PL)
+                {
+                    /* trigger lwip receive thread */
+                    eth_device_ready(&(stm32_eth_device.parent));
+                }
+            }
+            
+            /* enable DMA interrupts */
+            ETH->DMAC0IER = ETH_DMAC0IER_NIE | ETH_DMAC0IER_RIE | ETH_DMAC0IER_TIE; 
+        }
+    }
+}
+
+/* Register the EMAC device */
+static int rt_hw_stm32_eth_init(void)
+{
+    rt_err_t state = RT_EOK;
+    
+    /* OUI 00-80-E1 STMICROELECTRONICS. */
+    stm32_eth_device.dev_addr[0] = 0x00;
+    stm32_eth_device.dev_addr[1] = 0x80;
+    stm32_eth_device.dev_addr[2] = 0xE1;
+    /* generate MAC addr from 96bit unique ID (only for test). */
+    stm32_eth_device.dev_addr[3] = *(rt_uint8_t *)(UID_BASE + 4);
+    stm32_eth_device.dev_addr[4] = *(rt_uint8_t *)(UID_BASE + 2);
+    stm32_eth_device.dev_addr[5] = *(rt_uint8_t *)(UID_BASE + 0);
+
+    stm32_eth_device.parent.parent.init      = rt_stm32_eth_init;
+    stm32_eth_device.parent.parent.open      = rt_stm32_eth_open;
+    stm32_eth_device.parent.parent.close     = rt_stm32_eth_close;
+    stm32_eth_device.parent.parent.read      = rt_stm32_eth_read;
+    stm32_eth_device.parent.parent.write     = rt_stm32_eth_write;
+    stm32_eth_device.parent.parent.control   = rt_stm32_eth_control;
+    stm32_eth_device.parent.parent.user_data = RT_NULL;
+
+    stm32_eth_device.parent.eth_rx = rt_stm32_eth_rx;
+    stm32_eth_device.parent.eth_tx = rt_stm32_eth_tx;
+
+    rt_event_init(&rx_event, "eth_rx", RT_IPC_FLAG_FIFO);
+    
+    /* register eth device */
+    state = eth_device_init(&(stm32_eth_device.parent), "e0");
+    if (RT_EOK == state)
+    {
+        LOG_D("emac device init success");
+    }
+    else
+    {
+        LOG_E("emac device init faild: %d", state);
+        state = -RT_ERROR;
+    }
+
+    /* start phy monitor */
+    rt_thread_t tid;
+    tid = rt_thread_create("phy",
+                           phy_monitor_thread_entry,
+                           RT_NULL,
+                           1024,
+                           RT_THREAD_PRIORITY_MAX - 2,
+                           2);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        state = -RT_ERROR;
+    }
+
+    return state;
+}
+INIT_DEVICE_EXPORT(rt_hw_stm32_eth_init);
+
+#endif

bsp/stm32/stm32mp157a-st-discovery/board/ports/drv_eth.h

@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2020-07-20     thread-liu        the first version
+ */
+
+#ifndef __DRV_ETH_H__
+#define __DRV_ETH_H__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+#include <board.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct
+{
+  uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100/1000 Mbps.
+                                                           This parameter can be a value of @ref ETH_Speed */
+  uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */
+} ETH_MACConfigTypeDef;
+
+/**
+ * @brief Transmit descriptor
+ **/
+typedef struct
+{
+   uint32_t tdes0;
+   uint32_t tdes1;
+   uint32_t tdes2;
+   uint32_t tdes3;
+} TxDmaDesc;
+
+/**
+ * @brief Receive descriptor
+ **/
+typedef struct
+{
+   uint32_t rdes0;
+   uint32_t rdes1;
+   uint32_t rdes2;
+   uint32_t rdes3;
+} RxDmaDesc;
+
+enum {
+    PHY_LINK        = (1 << 0),
+    PHY_10M         = (1 << 1),
+    PHY_100M        = (1 << 2),
+    PHY_1000M       = (1 << 3),
+    PHY_FULL_DUPLEX = (1 << 4),
+    PHY_HALF_DUPLEX = (1 << 5)
+};
+
+
+#define RTL8211F_PHY_ADDR       1           /* PHY address */
+
+#define ETH_TXBUFNB             4           /* 4 Tx buffers of size ETH_TX_BUF_SIZE */
+#define ETH_TX_BUF_SIZE         1536        /* buffer size for transmit */
+#define ETH_RXBUFNB             4           /* 4 Rx buffers of size ETH_RX_BUF_SIZE */
+#define ETH_RX_BUF_SIZE         1536        /* buffer size for receive */
+
+#define ETH_MMC_INTERRUPT_MASK_TXLPITRCIM_Msk ETH_MMCTXIMR_TXLPITRCIM_Msk /* ETH_MMCTXIMR register  */
+
+/* Register access macros */
+#define ETH_MACRXQC0R_RXQ0EN_Val(n)     (((n) << ETH_MACRXQC0R_RXQ0EN_Pos) & ETH_MACRXQC0R_RXQ0EN_Msk)
+#define ETH_MACMDIOAR_CR_Val(n)         (((n) << ETH_MACMDIOAR_CR_Pos) & ETH_MACMDIOAR_CR_Msk)
+#define ETH_MACMDIOAR_GOC_Val(n)        (((n) << ETH_MACMDIOAR_GOC_Pos) & ETH_MACMDIOAR_GOC_Msk)
+#define ETH_MTLTXQ0OMR_TQS_Val(n)       (((n) << ETH_MTLTXQ0OMR_TQS_Pos) & ETH_MTLTXQ0OMR_TQS_Msk)
+#define ETH_MTLTXQ0OMR_TXQEN_Val(n)     (((n) << ETH_MTLTXQ0OMR_TXQEN_Pos) & ETH_MTLTXQ0OMR_TXQEN_Msk)
+#define ETH_MTLRXQ0OMR_RQS_Val(n)       (((n) << ETH_MTLRXQ0OMR_RQS_Pos) & ETH_MTLRXQ0OMR_RQS_Msk)
+#define ETH_DMAMR_INTM_Val(n)           (((n) << ETH_DMAMR_INTM_Pos) & ETH_DMAMR_INTM_Msk)
+#define ETH_DMAMR_PR_Val(n)             (((n) << ETH_DMAMR_PR_Pos) & ETH_DMAMR_PR_Msk)
+#define ETH_DMAC0CR_DSL_Val(n)          (((n) << ETH_DMAC0CR_DSL_Pos) & ETH_DMAC0CR_DSL_Msk)
+#define ETH_DMAC0TXCR_TXPBL_Val(n)      (((n) << ETH_DMAC0TXCR_TXPBL_Pos) & ETH_DMAC0TXCR_TXPBL_Msk)
+#define ETH_DMAC0RXCR_RXPBL_Val(n)      (((n) << ETH_DMAC0RXCR_RXPBL_Pos) & ETH_DMAC0RXCR_RXPBL_Msk)
+#define ETH_DMAC0RXCR_RBSZ_Val(n)       (((n) << ETH_DMAC0RXCR_RBSZ_Pos) & ETH_DMAC0RXCR_RBSZ_Msk)
+
+/* Transmit normal descriptor (read format) */
+#define ETH_TDES0_BUF1AP        0xFFFFFFFF
+#define ETH_TDES1_BUF2AP        0xFFFFFFFF
+#define ETH_TDES2_IOC           0x80000000
+#define ETH_TDES2_TTSE          0x40000000
+#define ETH_TDES2_B2L           0x3FFF0000
+#define ETH_TDES2_VTIR          0x0000C000
+#define ETH_TDES2_B1L           0x00003FFF
+#define ETH_TDES3_OWN           0x80000000
+#define ETH_TDES3_CTXT          0x40000000
+#define ETH_TDES3_FD            0x20000000
+#define ETH_TDES3_LD            0x10000000
+#define ETH_TDES3_CPC           0x0C000000
+#define ETH_TDES3_SAIC          0x03800000
+#define ETH_TDES3_THL           0x00780000
+#define ETH_TDES3_TSE           0x00040000
+#define ETH_TDES3_CIC           0x00030000
+#define ETH_TDES3_FL            0x00007FFF
+
+/* Transmit normal descriptor (write-back format) */
+#define ETH_TDES0_TTSL          0xFFFFFFFF
+#define ETH_TDES1_TTSH          0xFFFFFFFF
+#define ETH_TDES3_OWN           0x80000000
+#define ETH_TDES3_CTXT          0x40000000
+#define ETH_TDES3_FD            0x20000000
+#define ETH_TDES3_LD            0x10000000
+#define ETH_TDES3_TTSS          0x00020000
+#define ETH_TDES3_ES            0x00008000
+#define ETH_TDES3_JT            0x00004000
+#define ETH_TDES3_FF            0x00002000
+#define ETH_TDES3_PCE           0x00001000
+#define ETH_TDES3_LOC           0x00000800
+#define ETH_TDES3_NC            0x00000400
+#define ETH_TDES3_LC            0x00000200
+#define ETH_TDES3_EC            0x00000100
+#define ETH_TDES3_CC            0x000000F0
+#define ETH_TDES3_ED            0x00000008
+#define ETH_TDES3_UF            0x00000004
+#define ETH_TDES3_DB            0x00000002
+#define ETH_TDES3_IHE           0x00000001
+
+/* Transmit context descriptor           */
+#define ETH_TDES0_TTSL          0xFFFFFFFF
+#define ETH_TDES1_TTSH          0xFFFFFFFF
+#define ETH_TDES2_IVT           0xFFFF0000
+#define ETH_TDES2_MSS           0x00003FFF
+#define ETH_TDES3_OWN           0x80000000
+#define ETH_TDES3_CTXT          0x40000000
+#define ETH_TDES3_OSTC          0x08000000
+#define ETH_TDES3_TCMSSV        0x04000000
+#define ETH_TDES3_CDE           0x00800000
+#define ETH_TDES3_IVLTV         0x00020000
+#define ETH_TDES3_VLTV          0x00010000
+#define ETH_TDES3_VT            0x0000FFFF
+
+/* Receive normal descriptor (read format) */
+#define ETH_RDES0_BUF1AP        0xFFFFFFFF
+#define ETH_RDES2_BUF2AP        0xFFFFFFFF
+#define ETH_RDES3_OWN           0x80000000
+#define ETH_RDES3_IOC           0x40000000
+#define ETH_RDES3_BUF2V         0x02000000
+#define ETH_RDES3_BUF1V         0x01000000
+
+/* Receive normal descriptor (write-back format) */
+#define ETH_RDES0_IVT           0xFFFF0000
+#define ETH_RDES0_OVT           0x0000FFFF
+#define ETH_RDES1_OPC           0xFFFF0000
+#define ETH_RDES1_TD            0x00008000
+#define ETH_RDES1_TSA           0x00004000
+#define ETH_RDES1_PV            0x00002000
+#define ETH_RDES1_PFT           0x00001000
+#define ETH_RDES1_PMT           0x00000F00
+#define ETH_RDES1_IPCE          0x00000080
+#define ETH_RDES1_IPCB          0x00000040
+#define ETH_RDES1_IPV6          0x00000020
+#define ETH_RDES1_IPV4          0x00000010
+#define ETH_RDES1_IPHE          0x00000008
+#define ETH_RDES1_PT            0x00000007
+#define ETH_RDES2_L3L4FM        0xE0000000
+#define ETH_RDES2_L4FM          0x10000000
+#define ETH_RDES2_L3FM          0x08000000
+#define ETH_RDES2_MADRM         0x07F80000
+#define ETH_RDES2_HF            0x00040000
+#define ETH_RDES2_DAF           0x00020000
+#define ETH_RDES2_SAF           0x00010000
+#define ETH_RDES2_VF            0x00008000
+#define ETH_RDES2_ARPRN         0x00000400
+#define ETH_RDES3_OWN           0x80000000
+#define ETH_RDES3_CTXT          0x40000000
+#define ETH_RDES3_FD            0x20000000
+#define ETH_RDES3_LD            0x10000000
+#define ETH_RDES3_RS2V          0x08000000
+#define ETH_RDES3_RS1V          0x04000000
+#define ETH_RDES3_RS0V          0x02000000
+#define ETH_RDES3_CE            0x01000000
+#define ETH_RDES3_GP            0x00800000
+#define ETH_RDES3_RWT           0x00400000
+#define ETH_RDES3_OE            0x00200000
+#define ETH_RDES3_RE            0x00100000
+#define ETH_RDES3_DE            0x00080000
+#define ETH_RDES3_LT            0x00070000
+#define ETH_RDES3_ES            0x00008000
+#define ETH_RDES3_PL            0x00007FFF
+
+/* Receive context descriptor */
+#define ETH_RDES0_RTSL          0xFFFFFFFF
+#define ETH_RDES1_RTSH          0xFFFFFFFF
+#define ETH_RDES3_OWN           0x80000000
+#define ETH_RDES3_CTXT          0x40000000
+
+#define RTL8211F_BMCR     ((uint16_t)0x0000U) /* Basic Mode Control Register. */
+#define RTL8211F_BMSR     ((uint16_t)0x0001U) /* Basic Mode Status Register. */
+#define RTL8211F_PHYID1   ((uint16_t)0x0002U) /* PHY Identifier Register 1. */
+#define RTL8211F_PHYID2   ((uint16_t)0x0003U) /* PHY Identifier Register 2. */
+#define RTL8211F_ANAR     ((uint16_t)0x0004U) /* Auto-Negotiation Advertising Register. */
+#define RTL8211F_ANLPAR   ((uint16_t)0x0005U) /* Auto-Negotiation Link Partner Ability Register. */
+#define RTL8211F_ANER     ((uint16_t)0x0006U) /* Auto-Negotiation Expansion Register.*/
+#define RTL8211F_ANNPTR   ((uint16_t)0x0007U) /* Auto-Negotiation Next Page Transmit Register.*/
+#define RTL8211F_ANNPRR   ((uint16_t)0x0008U) /* Auto-Negotiation Next Page Receive Register. */
+#define RTL8211F_GBCR     ((uint16_t)0x0009U) /* 1000Base-T Control Register. */
+#define RTL8211F_GBSR     ((uint16_t)0x000AU) /* 1000Base-T Status Register. */
+#define RTL8211F_MMDACR   ((uint16_t)0x000DU) /* MMD Access Control Register. */
+#define RTL8211F_MMDAADR  ((uint16_t)0x000EU) /* MMD Access Address Data Register. */
+#define RTL8211F_GBESR    ((uint16_t)0x000FU) /* 1000Base-T Extended Status Register. */
+#define RTL8211F_LCR      ((uint16_t)0x0010U) /* LED Control Register. */
+#define RTL8211F_INER     ((uint16_t)0x0012U) /* Interrupt Enable Register. */
+#define RTL8211F_PHYSCR   ((uint16_t)0x0014U) /* PHY Special Cofig Register */
+#define RTL8211F_PHYCR1   ((uint16_t)0x0018U) /* PHY Specific Control Register 1. */
+#define RTL8211F_PHYCR2   ((uint16_t)0x0019U) /* PHY Specific Control Register 2. */
+#define RTL8211F_PHYSR    ((uint16_t)0x001AU) /* PHY Specific Status Register. */
+#define RTL8211F_INSR     ((uint16_t)0x001DU) /* Interrupt Status Register. */
+#define RTL8211F_PAGSR    ((uint16_t)0x001FU) /* Page Select Register. */
+
+/* Basic Mode Control register */
+#define RTL8211F_BMCR_RESET                    0x8000
+#define RTL8211F_BMCR_LOOPBACK                 0x4000
+#define RTL8211F_BMCR_SPEED_SEL_LSB            0x2000
+#define RTL8211F_BMCR_AN_EN                    0x1000
+#define RTL8211F_BMCR_POWER_DOWN               0x0800
+#define RTL8211F_BMCR_ISOLATE                  0x0400
+#define RTL8211F_BMCR_RESTART_AN               0x0200
+#define RTL8211F_BMCR_DUPLEX_MODE              0x0100
+#define RTL8211F_BMCR_COL_TEST                 0x0080
+#define RTL8211F_BMCR_SPEED_SEL_MSB            0x0040
+#define RTL8211F_BMCR_UNI_DIR_EN               0x0020
+
+/* Basic Mode Status register */
+#define RTL8211F_BMSR_100BT4                   0x8000
+#define RTL8211F_BMSR_100BTX_FD                0x4000
+#define RTL8211F_BMSR_100BTX_HD                0x2000
+#define RTL8211F_BMSR_10BT_FD                  0x1000
+#define RTL8211F_BMSR_10BT_HD                  0x0800
+#define RTL8211F_BMSR_100BT2_FD                0x0400
+#define RTL8211F_BMSR_100BT2_HD                0x0200
+#define RTL8211F_BMSR_EXTENDED_STATUS          0x0100
+#define RTL8211F_BMSR_UNI_DIR_CAPABLE          0x0080
+#define RTL8211F_BMSR_PREAMBLE_SUPPR           0x0040
+#define RTL8211F_BMSR_AN_COMPLETE              0x0020
+#define RTL8211F_BMSR_REMOTE_FAULT             0x0010
+#define RTL8211F_BMSR_AN_CAPABLE               0x0008
+#define RTL8211F_BMSR_LINK_STATUS              0x0004
+#define RTL8211F_BMSR_JABBER_DETECT            0x0002
+#define RTL8211F_BMSR_EXTENDED_CAPABLE         0x0001
+
+/* PHY Identifier 1 register */
+#define RTL8211F_PHYID1_OUI_MSB                0xFFFF
+#define RTL8211F_PHYID1_OUI_MSB_DEFAULT        0x001C
+
+/* PHY Identifier 2 register */
+#define RTL8211F_PHYID2_OUI_LSB                0xFC00
+#define RTL8211F_PHYID2_OUI_LSB_DEFAULT        0xC800
+#define RTL8211F_PHYID2_MODEL_NUM              0x03F0
+#define RTL8211F_PHYID2_MODEL_NUM_DEFAULT      0x0110
+#define RTL8211F_PHYID2_REVISION_NUM           0x000F
+#define RTL8211F_PHYID2_REVISION_NUM_DEFAULT   0x0006
+
+/* Auto-Negotiation Advertisement register */
+#define RTL8211F_ANAR_NEXT_PAGE                0x8000
+#define RTL8211F_ANAR_REMOTE_FAULT             0x2000
+#define RTL8211F_ANAR_ASYM_PAUSE               0x0800
+#define RTL8211F_ANAR_PAUSE                    0x0400
+#define RTL8211F_ANAR_100BT4                   0x0200
+#define RTL8211F_ANAR_100BTX_FD                0x0100
+#define RTL8211F_ANAR_100BTX_HD                0x0080
+#define RTL8211F_ANAR_10BT_FD                  0x0040
+#define RTL8211F_ANAR_10BT_HD                  0x0020
+#define RTL8211F_ANAR_SELECTOR                 0x001F
+#define RTL8211F_ANAR_SELECTOR_DEFAULT         0x0001
+
+/* Auto-Negotiation Link Partner Ability register */
+#define RTL8211F_ANLPAR_NEXT_PAGE              0x8000
+#define RTL8211F_ANLPAR_ACK                    0x4000
+#define RTL8211F_ANLPAR_REMOTE_FAULT           0x2000
+#define RTL8211F_ANLPAR_ASYM_PAUSE             0x0800
+#define RTL8211F_ANLPAR_PAUSE                  0x0400
+#define RTL8211F_ANLPAR_100BT4                 0x0200
+#define RTL8211F_ANLPAR_100BTX_FD              0x0100
+#define RTL8211F_ANLPAR_100BTX_HD              0x0080
+#define RTL8211F_ANLPAR_10BT_FD                0x0040
+#define RTL8211F_ANLPAR_10BT_HD                0x0020
+#define RTL8211F_ANLPAR_SELECTOR               0x001F
+#define RTL8211F_ANLPAR_SELECTOR_DEFAULT       0x0001
+
+/* Auto-Negotiation Expansion register */
+#define RTL8211F_ANER_RX_NP_LOCATION_ABLE      0x0040
+#define RTL8211F_ANER_RX_NP_LOCATION           0x0020
+#define RTL8211F_ANER_PAR_DETECT_FAULT         0x0010
+#define RTL8211F_ANER_LP_NEXT_PAGE_ABLE        0x0008
+#define RTL8211F_ANER_NEXT_PAGE_ABLE           0x0004
+#define RTL8211F_ANER_PAGE_RECEIVED            0x0002
+#define RTL8211F_ANER_LP_AN_ABLE               0x0001
+
+/* Auto-Negotiation Next Page Transmit register */
+#define RTL8211F_ANNPTR_NEXT_PAGE              0x8000
+#define RTL8211F_ANNPTR_MSG_PAGE               0x2000
+#define RTL8211F_ANNPTR_ACK2                   0x1000
+#define RTL8211F_ANNPTR_TOGGLE                 0x0800
+#define RTL8211F_ANNPTR_MESSAGE                0x07FF
+
+/* Auto-Negotiation Next Page Receive register */
+#define RTL8211F_ANNPRR_NEXT_PAGE              0x8000
+#define RTL8211F_ANNPRR_ACK                    0x4000
+#define RTL8211F_ANNPRR_MSG_PAGE               0x2000
+#define RTL8211F_ANNPRR_ACK2                   0x1000
+#define RTL8211F_ANNPRR_TOGGLE                 0x0800
+#define RTL8211F_ANNPRR_MESSAGE                0x07FF
+
+/* 1000Base-T Control register */
+#define RTL8211F_GBCR_TEST_MODE                0xE000
+#define RTL8211F_GBCR_MS_MAN_CONF_EN           0x1000
+#define RTL8211F_GBCR_MS_MAN_CONF_VAL          0x0800
+#define RTL8211F_GBCR_PORT_TYPE                0x0400
+#define RTL8211F_GBCR_1000BT_FD                0x0200
+
+/* 1000Base-T Status register */
+#define RTL8211F_GBSR_MS_CONF_FAULT            0x8000
+#define RTL8211F_GBSR_MS_CONF_RES              0x4000
+#define RTL8211F_GBSR_LOCAL_RECEIVER_STATUS    0x2000
+#define RTL8211F_GBSR_REMOTE_RECEIVER_STATUS   0x1000
+#define RTL8211F_GBSR_LP_1000BT_FD             0x0800
+#define RTL8211F_GBSR_LP_1000BT_HD             0x0400
+#define RTL8211F_GBSR_IDLE_ERR_COUNT           0x00FF
+
+/* MMD Access Control register */
+#define RTL8211F_MMDACR_FUNC                   0xC000
+#define RTL8211F_MMDACR_FUNC_ADDR              0x0000
+#define RTL8211F_MMDACR_FUNC_DATA_NO_POST_INC  0x4000
+#define RTL8211F_MMDACR_FUNC_DATA_POST_INC_RW  0x8000
+#define RTL8211F_MMDACR_FUNC_DATA_POST_INC_W   0xC000
+#define RTL8211F_MMDACR_DEVAD                  0x001F
+
+/* 1000Base-T Extended Status register */
+#define RTL8211F_GBESR_1000BX_FD               0x8000
+#define RTL8211F_GBESR_1000BX_HD               0x4000
+#define RTL8211F_GBESR_1000BT_FD               0x2000
+#define RTL8211F_GBESR_1000BT_HD               0x1000
+
+/* Interrupt Enable register */
+#define RTL8211F_INER_JABBER                   0x0400
+#define RTL8211F_INER_ALDPS_STATE              0x0200
+#define RTL8211F_INER_PME                      0x0080
+#define RTL8211F_INER_PHY_REG_ACCESS           0x0020
+#define RTL8211F_INER_LINK_STATUS              0x0010
+#define RTL8211F_INER_AN_COMPLETE              0x0008
+#define RTL8211F_INER_PAGE_RECEIVED            0x0004
+#define RTL8211F_INER_AN_ERROR                 0x0001
+
+/* PHY Specific Control 1 register */
+#define RTL8211F_PHYCR1_PHYAD_0_EN             0x2000
+#define RTL8211F_PHYCR1_MDI_MODE_MANUAL_CONFIG 0x0200
+#define RTL8211F_PHYCR1_MDI_MODE               0x0100
+#define RTL8211F_PHYCR1_TX_CRS_EN              0x0080
+#define RTL8211F_PHYCR1_PHYAD_NON_ZERO_DETECT  0x0040
+#define RTL8211F_PHYCR1_PREAMBLE_CHECK_EN      0x0010
+#define RTL8211F_PHYCR1_JABBER_DETECT_EN       0x0008
+#define RTL8211F_PHYCR1_ALDPS_EN               0x0004
+
+/* PHY Specific Control 2 register */
+#define RTL8211F_PHYCR2_CLKOUT_FREQ_SEL        0x0800
+#define RTL8211F_PHYCR2_CLKOUT_SSC_EN          0x0080
+#define RTL8211F_PHYCR2_RXC_SSC_EN             0x0008
+#define RTL8211F_PHYCR2_RXC_EN                 0x0002
+#define RTL8211F_PHYCR2_CLKOUT_EN              0x0001
+
+/* PHY Specific Status register */
+#define RTL8211F_PHYSR_ALDPS_STATE             0x4000
+#define RTL8211F_PHYSR_MDI_PLUG                0x2000
+#define RTL8211F_PHYSR_NWAY_EN                 0x1000
+#define RTL8211F_PHYSR_MASTER_MODE             0x0800
+#define RTL8211F_PHYSR_EEE_CAPABLE             0x0100
+#define RTL8211F_PHYSR_RX_FLOW_EN              0x0080
+#define RTL8211F_PHYSR_TX_FLOW_EN              0x0040
+#define RTL8211F_PHYSR_SPEED                   0x0030
+#define RTL8211F_PHYSR_SPEED_10MBPS            0x0000
+#define RTL8211F_PHYSR_SPEED_100MBPS           0x0010
+#define RTL8211F_PHYSR_SPEED_1000MBPS          0x0020
+#define RTL8211F_PHYSR_DUPLEX                  0x0008
+#define RTL8211F_PHYSR_LINK                    0x0004
+#define RTL8211F_PHYSR_MDI_CROSSOVER_STATUS    0x0002
+#define RTL8211F_PHYSR_JABBER                  0x0001
+
+/* Interrupt Status register */
+#define RTL8211F_INSR_JABBER                   0x0400
+#define RTL8211F_INSR_ALDPS_STATE              0x0200
+#define RTL8211F_INSR_PME                      0x0080
+#define RTL8211F_INSR_PHY_REG_ACCESS           0x0020
+#define RTL8211F_INSR_LINK_STATUS              0x0010
+#define RTL8211F_INSR_AN_COMPLETE              0x0008
+#define RTL8211F_INSR_PAGE_RECEIVED            0x0004
+#define RTL8211F_INSR_AN_ERROR                 0x0001
+
+/* Page Select register */
+#define RTL8211F_PAGSR_PAGE_SEL                0x0007
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif