Merge pull request #1524 from TanekLiang/imxrt-update-new-sdk

[bsp][imxrt1052-evk] update sdk to EVKB

bsp/imxrt1052-evk/.config

@@ -84,6 +84,7 @@ CONFIG_FINSH_CMD_SIZE=80
 CONFIG_FINSH_USING_MSH=y
 CONFIG_FINSH_USING_MSH_DEFAULT=y
 # CONFIG_FINSH_USING_MSH_ONLY is not set
+CONFIG_FINSH_ARG_MAX=10
 
 #
 # Device virtual file system
@@ -129,6 +130,7 @@ CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_I2C=y
 CONFIG_RT_USING_I2C_BITOPS=y
 CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 CONFIG_RT_USING_RTC=y
@@ -144,6 +146,7 @@ CONFIG_RT_USING_SPI=y
 # CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_AUDIO is not set
 
 #
 # Using USB
@@ -157,7 +160,6 @@ CONFIG_RT_USING_SPI=y
 CONFIG_RT_USING_LIBC=y
 # CONFIG_RT_USING_PTHREADS is not set
 # CONFIG_RT_USING_POSIX is not set
-# CONFIG_HAVE_SYS_SIGNALS is not set
 
 #
 # Network stack
@@ -199,6 +201,8 @@ CONFIG_RT_LWIP_TCP_WND=8196
 CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
 CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
 CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
+# CONFIG_LWIP_NO_RX_THREAD is not set
+# CONFIG_LWIP_NO_TX_THREAD is not set
 CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
 CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
 CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
@@ -238,20 +242,6 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # RT-Thread online packages
 #
 
-#
-# system packages
-#
-
-#
-# RT-Thread GUI Engine
-#
-# CONFIG_PKG_USING_GUIENGINE is not set
-# CONFIG_PKG_USING_PERSIMMON is not set
-# CONFIG_PKG_USING_LWEXT4 is not set
-# CONFIG_PKG_USING_PARTITION is not set
-# CONFIG_PKG_USING_SQLITE is not set
-# CONFIG_PKG_USING_RTI is not set
-
 #
 # IoT - internet of things
 #
@@ -260,6 +250,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
 # CONFIG_PKG_USING_LJSON is not set
 # CONFIG_PKG_USING_EZXML is not set
 # CONFIG_PKG_USING_NANOPB is not set
@@ -281,6 +272,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_ONENET is not set
 
 #
 # security packages
@@ -299,6 +291,7 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # multimedia packages
 #
 # CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
 
 #
 # tools packages
@@ -307,7 +300,32 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
-# CONFIG_PKG_USING_IPERF is not set
+
+#
+# system packages
+#
+
+#
+# RT-Thread GUI Engine
+#
+# CONFIG_PKG_USING_GUIENGINE is not set
+# CONFIG_PKG_USING_GUIENGINE_V200 is not set
+# CONFIG_PKG_USING_GUIENGINE_LATEST_VERSION is not set
+# CONFIG_GUIENGINE_IMAGE_LODEPNG is not set
+# CONFIG_GUIENGINE_IMAGE_PNG is not set
+# CONFIG_PKG_USING_PERSIMMON is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+
+#
+# peripheral libraries and drivers
+#
+# CONFIG_PKG_USING_STM32F4_HAL is not set
+# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
 
 #
 # miscellaneous packages
@@ -316,16 +334,48 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_MINILZO is not set
 # CONFIG_PKG_USING_QUICKLZ is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
-# CONFIG_PKG_USING_SAMPLES is not set
 # CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_DSTR is not set
+
+#
+# sample package
+#
+# CONFIG_PKG_USING_SAMPLES is not set
 
 #
 # example package: hello
 #
 # CONFIG_PKG_USING_HELLO is not set
+
+#
+# Privated Packages of RealThread
+#
+# CONFIG_PKG_USING_CODEC is not set
+# CONFIG_PKG_USING_PLAYER is not set
+# CONFIG_PKG_USING_PERSIMMON_SRC is not set
+
+#
+# Network Utilities
+#
+# CONFIG_PKG_USING_MDNS is not set
+# CONFIG_PKG_USING_UPNP is not set
+# CONFIG_PKG_USING_WLAN_WICED_SRC is not set
+# CONFIG_PKG_USING_CLOUDSDK is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_POWER_MANAGER is not set
+# CONFIG_PKG_USING_RT_OTA is not set
+# CONFIG_PKG_USING_RT_AT is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_RTINSIGHT is not set
 CONFIG_SOC_IMXRT1052=y
+CONFIG_BOARD_USING_HYPERFLASH=y
+# CONFIG_BOARD_USING_QSPIFLASH is not set
 CONFIG_BOARD_RT1050_EVK=y
 # CONFIG_BOARD_RT1050_FIRE is not set
+# CONFIG_BOARD_RT1050_ShareBoard is not set
+# CONFIG_BOARD_RT1050_ATK is not set
+# CONFIG_BOARD_RT1050_SeeedStudio is not set
 
 #
 # RT1050 Bsp Config
@@ -365,14 +415,14 @@ CONFIG_LPSPI4_SDI_GPIO_1=y
 # CONFIG_RT_USING_SPI_FLASH is not set
 
 #
-# Select i2c bus drivers
+# Select iic bus drivers
 #
-CONFIG_LPI2C_CLOCK_SOURCE_DIVIDER=4
-CONFIG_RT_USING_I2C1=y
-# CONFIG_RT_USING_I2C1_BITOPS is not set
-# CONFIG_RT_USING_I2C2 is not set
-# CONFIG_RT_USING_I2C3 is not set
-# CONFIG_RT_USING_I2C4 is not set
+CONFIG_RT_USING_HW_I2C1=y
+CONFIG_HW_I2C1_BADURATE_100kHZ=y
+# CONFIG_HW_I2C1_BADURATE_400kHZ is not set
+# CONFIG_RT_USING_HW_I2C2 is not set
+# CONFIG_RT_USING_HW_I2C3 is not set
+# CONFIG_RT_USING_HW_I2C4 is not set
 
 #
 # Select lcd driver

bsp/imxrt1052-evk/Libraries/MIMXRT1052_features.h

@@ -1,37 +1,44 @@
 /*
 ** ###################################################################
 **     Version:             rev. 0.1, 2017-01-10
-**     Build:               b171017
+**     Build:               b180509
 **
 **     Abstract:
 **         Chip specific module features.
 **
+**     The Clear BSD License
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2017 NXP
-**     Redistribution and use in source and binary forms, with or without modification,
-**     are permitted provided that the following conditions are met:
+**     Copyright 2016-2018 NXP
+**     All rights reserved.
 **
-**     1. Redistributions of source code must retain the above copyright notice, this list
-**       of conditions and the following disclaimer.
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
 **
-**     2. Redistributions in binary form must reproduce the above copyright notice, this
-**       list of conditions and the following disclaimer in the documentation and/or
-**       other materials provided with the distribution.
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
 **
-**     3. Neither the name of the copyright holder nor the names of its
-**       contributors may be used to endorse or promote products derived from this
-**       software without specific prior written permission.
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
 **
-**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 **
 **     http:                 www.nxp.com
 **     mail:                 support@nxp.com
@@ -48,532 +55,110 @@
 
 /* SOC module features */
 
-/* @brief ACMP availability on the SoC. */
-#define FSL_FEATURE_SOC_ACMP_COUNT (0)
 /* @brief ADC availability on the SoC. */
 #define FSL_FEATURE_SOC_ADC_COUNT (2)
-/* @brief ADC12 availability on the SoC. */
-#define FSL_FEATURE_SOC_ADC12_COUNT (0)
-/* @brief ADC16 availability on the SoC. */
-#define FSL_FEATURE_SOC_ADC16_COUNT (0)
-/* @brief ADC_5HC availability on the SoC. */
-#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0)
-/* @brief AES availability on the SoC. */
-#define FSL_FEATURE_SOC_AES_COUNT (0)
-/* @brief AFE availability on the SoC. */
-#define FSL_FEATURE_SOC_AFE_COUNT (0)
-/* @brief AGC availability on the SoC. */
-#define FSL_FEATURE_SOC_AGC_COUNT (0)
-/* @brief AIPS availability on the SoC. */
-#define FSL_FEATURE_SOC_AIPS_COUNT (0)
 /* @brief AIPSTZ availability on the SoC. */
 #define FSL_FEATURE_SOC_AIPSTZ_COUNT (4)
-/* @brief ANATOP availability on the SoC. */
-#define FSL_FEATURE_SOC_ANATOP_COUNT (0)
 /* @brief AOI availability on the SoC. */
 #define FSL_FEATURE_SOC_AOI_COUNT (2)
-/* @brief APBH availability on the SoC. */
-#define FSL_FEATURE_SOC_APBH_COUNT (0)
-/* @brief ASMC availability on the SoC. */
-#define FSL_FEATURE_SOC_ASMC_COUNT (0)
-/* @brief ASRC availability on the SoC. */
-#define FSL_FEATURE_SOC_ASRC_COUNT (0)
-/* @brief ASYNC_SYSCON availability on the SoC. */
-#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (0)
-/* @brief ATX availability on the SoC. */
-#define FSL_FEATURE_SOC_ATX_COUNT (0)
-/* @brief AXBS availability on the SoC. */
-#define FSL_FEATURE_SOC_AXBS_COUNT (0)
-/* @brief BCH availability on the SoC. */
-#define FSL_FEATURE_SOC_BCH_COUNT (0)
-/* @brief BLEDP availability on the SoC. */
-#define FSL_FEATURE_SOC_BLEDP_COUNT (0)
-/* @brief BOD availability on the SoC. */
-#define FSL_FEATURE_SOC_BOD_COUNT (0)
-/* @brief CAAM availability on the SoC. */
-#define FSL_FEATURE_SOC_CAAM_COUNT (0)
-/* @brief CADC availability on the SoC. */
-#define FSL_FEATURE_SOC_CADC_COUNT (0)
-/* @brief CALIB availability on the SoC. */
-#define FSL_FEATURE_SOC_CALIB_COUNT (0)
-/* @brief CAN availability on the SoC. */
-#define FSL_FEATURE_SOC_CAN_COUNT (0)
-/* @brief CAU availability on the SoC. */
-#define FSL_FEATURE_SOC_CAU_COUNT (0)
-/* @brief CAU3 availability on the SoC. */
-#define FSL_FEATURE_SOC_CAU3_COUNT (0)
 /* @brief CCM availability on the SoC. */
 #define FSL_FEATURE_SOC_CCM_COUNT (1)
 /* @brief CCM_ANALOG availability on the SoC. */
 #define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
-/* @brief CHRG availability on the SoC. */
-#define FSL_FEATURE_SOC_CHRG_COUNT (0)
-/* @brief CLKCTL0 availability on the SoC. */
-#define FSL_FEATURE_SOC_CLKCTL0_COUNT (0)
-/* @brief CLKCTL1 availability on the SoC. */
-#define FSL_FEATURE_SOC_CLKCTL1_COUNT (0)
 /* @brief CMP availability on the SoC. */
 #define FSL_FEATURE_SOC_CMP_COUNT (4)
-/* @brief CMT availability on the SoC. */
-#define FSL_FEATURE_SOC_CMT_COUNT (0)
-/* @brief CNC availability on the SoC. */
-#define FSL_FEATURE_SOC_CNC_COUNT (0)
-/* @brief COP availability on the SoC. */
-#define FSL_FEATURE_SOC_COP_COUNT (0)
-/* @brief CRC availability on the SoC. */
-#define FSL_FEATURE_SOC_CRC_COUNT (0)
-/* @brief CS availability on the SoC. */
-#define FSL_FEATURE_SOC_CS_COUNT (0)
 /* @brief CSI availability on the SoC. */
 #define FSL_FEATURE_SOC_CSI_COUNT (1)
-/* @brief CT32B availability on the SoC. */
-#define FSL_FEATURE_SOC_CT32B_COUNT (0)
-/* @brief CTI availability on the SoC. */
-#define FSL_FEATURE_SOC_CTI_COUNT (0)
-/* @brief CTIMER availability on the SoC. */
-#define FSL_FEATURE_SOC_CTIMER_COUNT (0)
-/* @brief DAC availability on the SoC. */
-#define FSL_FEATURE_SOC_DAC_COUNT (0)
-/* @brief DAC32 availability on the SoC. */
-#define FSL_FEATURE_SOC_DAC32_COUNT (0)
 /* @brief DCDC availability on the SoC. */
 #define FSL_FEATURE_SOC_DCDC_COUNT (1)
 /* @brief DCP availability on the SoC. */
 #define FSL_FEATURE_SOC_DCP_COUNT (1)
-/* @brief DDR availability on the SoC. */
-#define FSL_FEATURE_SOC_DDR_COUNT (0)
-/* @brief DDRC availability on the SoC. */
-#define FSL_FEATURE_SOC_DDRC_COUNT (0)
-/* @brief DDRC_MP availability on the SoC. */
-#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0)
-/* @brief DDR_PHY availability on the SoC. */
-#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0)
-/* @brief DMA availability on the SoC. */
-#define FSL_FEATURE_SOC_DMA_COUNT (0)
 /* @brief DMAMUX availability on the SoC. */
 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
-/* @brief DMIC availability on the SoC. */
-#define FSL_FEATURE_SOC_DMIC_COUNT (0)
-/* @brief DRY availability on the SoC. */
-#define FSL_FEATURE_SOC_DRY_COUNT (0)
-/* @brief DSPI availability on the SoC. */
-#define FSL_FEATURE_SOC_DSPI_COUNT (0)
-/* @brief ECSPI availability on the SoC. */
-#define FSL_FEATURE_SOC_ECSPI_COUNT (0)
 /* @brief EDMA availability on the SoC. */
 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
-/* @brief EEPROM availability on the SoC. */
-#define FSL_FEATURE_SOC_EEPROM_COUNT (0)
-/* @brief EIM availability on the SoC. */
-#define FSL_FEATURE_SOC_EIM_COUNT (0)
-/* @brief EMC availability on the SoC. */
-#define FSL_FEATURE_SOC_EMC_COUNT (0)
-/* @brief EMVSIM availability on the SoC. */
-#define FSL_FEATURE_SOC_EMVSIM_COUNT (0)
 /* @brief ENC availability on the SoC. */
 #define FSL_FEATURE_SOC_ENC_COUNT (4)
 /* @brief ENET availability on the SoC. */
 #define FSL_FEATURE_SOC_ENET_COUNT (1)
-/* @brief EPDC availability on the SoC. */
-#define FSL_FEATURE_SOC_EPDC_COUNT (0)
-/* @brief EPIT availability on the SoC. */
-#define FSL_FEATURE_SOC_EPIT_COUNT (0)
-/* @brief ESAI availability on the SoC. */
-#define FSL_FEATURE_SOC_ESAI_COUNT (0)
 /* @brief EWM availability on the SoC. */
 #define FSL_FEATURE_SOC_EWM_COUNT (1)
-/* @brief FB availability on the SoC. */
-#define FSL_FEATURE_SOC_FB_COUNT (0)
-/* @brief FGPIO availability on the SoC. */
-#define FSL_FEATURE_SOC_FGPIO_COUNT (0)
-/* @brief FLASH availability on the SoC. */
-#define FSL_FEATURE_SOC_FLASH_COUNT (0)
 /* @brief FLEXCAN availability on the SoC. */
 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
-/* @brief FLEXCOMM availability on the SoC. */
-#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (0)
 /* @brief FLEXIO availability on the SoC. */
 #define FSL_FEATURE_SOC_FLEXIO_COUNT (2)
 /* @brief FLEXRAM availability on the SoC. */
 #define FSL_FEATURE_SOC_FLEXRAM_COUNT (1)
 /* @brief FLEXSPI availability on the SoC. */
 #define FSL_FEATURE_SOC_FLEXSPI_COUNT (1)
-/* @brief FMC availability on the SoC. */
-#define FSL_FEATURE_SOC_FMC_COUNT (0)
-/* @brief FREQME availability on the SoC. */
-#define FSL_FEATURE_SOC_FREQME_COUNT (0)
-/* @brief FSKDT availability on the SoC. */
-#define FSL_FEATURE_SOC_FSKDT_COUNT (0)
-/* @brief FSP availability on the SoC. */
-#define FSL_FEATURE_SOC_FSP_COUNT (0)
-/* @brief FTFA availability on the SoC. */
-#define FSL_FEATURE_SOC_FTFA_COUNT (0)
-/* @brief FTFE availability on the SoC. */
-#define FSL_FEATURE_SOC_FTFE_COUNT (0)
-/* @brief FTFL availability on the SoC. */
-#define FSL_FEATURE_SOC_FTFL_COUNT (0)
-/* @brief FTM availability on the SoC. */
-#define FSL_FEATURE_SOC_FTM_COUNT (0)
-/* @brief FTMRA availability on the SoC. */
-#define FSL_FEATURE_SOC_FTMRA_COUNT (0)
-/* @brief FTMRE availability on the SoC. */
-#define FSL_FEATURE_SOC_FTMRE_COUNT (0)
-/* @brief FTMRH availability on the SoC. */
-#define FSL_FEATURE_SOC_FTMRH_COUNT (0)
-/* @brief GINT availability on the SoC. */
-#define FSL_FEATURE_SOC_GINT_COUNT (0)
 /* @brief GPC availability on the SoC. */
 #define FSL_FEATURE_SOC_GPC_COUNT (1)
-/* @brief GPC_PGC availability on the SoC. */
-#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0)
-/* @brief GPIO availability on the SoC. */
-#define FSL_FEATURE_SOC_GPIO_COUNT (0)
-/* @brief GPMI availability on the SoC. */
-#define FSL_FEATURE_SOC_GPMI_COUNT (0)
 /* @brief GPT availability on the SoC. */
 #define FSL_FEATURE_SOC_GPT_COUNT (2)
-/* @brief HASH availability on the SoC. */
-#define FSL_FEATURE_SOC_HASH_COUNT (0)
-/* @brief HSADC availability on the SoC. */
-#define FSL_FEATURE_SOC_HSADC_COUNT (0)
-/* @brief I2C availability on the SoC. */
-#define FSL_FEATURE_SOC_I2C_COUNT (0)
 /* @brief I2S availability on the SoC. */
 #define FSL_FEATURE_SOC_I2S_COUNT (3)
-/* @brief ICS availability on the SoC. */
-#define FSL_FEATURE_SOC_ICS_COUNT (0)
-/* @brief IEE availability on the SoC. */
-#define FSL_FEATURE_SOC_IEE_COUNT (0)
-/* @brief IEER availability on the SoC. */
-#define FSL_FEATURE_SOC_IEER_COUNT (0)
 /* @brief IGPIO availability on the SoC. */
 #define FSL_FEATURE_SOC_IGPIO_COUNT (5)
-/* @brief II2C availability on the SoC. */
-#define FSL_FEATURE_SOC_II2C_COUNT (0)
-/* @brief INPUTMUX availability on the SoC. */
-#define FSL_FEATURE_SOC_INPUTMUX_COUNT (0)
-/* @brief INTMUX availability on the SoC. */
-#define FSL_FEATURE_SOC_INTMUX_COUNT (0)
-/* @brief IOCON availability on the SoC. */
-#define FSL_FEATURE_SOC_IOCON_COUNT (0)
 /* @brief IOMUXC availability on the SoC. */
 #define FSL_FEATURE_SOC_IOMUXC_COUNT (1)
 /* @brief IOMUXC_GPR availability on the SoC. */
 #define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (1)
-/* @brief IOMUXC_LPSR availability on the SoC. */
-#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0)
-/* @brief IOMUXC_LPSR_GPR availability on the SoC. */
-#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0)
 /* @brief IOMUXC_SNVS availability on the SoC. */
 #define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (1)
-/* @brief IOPCTL availability on the SoC. */
-#define FSL_FEATURE_SOC_IOPCTL_COUNT (0)
-/* @brief IPWM availability on the SoC. */
-#define FSL_FEATURE_SOC_IPWM_COUNT (0)
-/* @brief IRQ availability on the SoC. */
-#define FSL_FEATURE_SOC_IRQ_COUNT (0)
-/* @brief IUART availability on the SoC. */
-#define FSL_FEATURE_SOC_IUART_COUNT (0)
-/* @brief KBI availability on the SoC. */
-#define FSL_FEATURE_SOC_KBI_COUNT (0)
 /* @brief KPP availability on the SoC. */
 #define FSL_FEATURE_SOC_KPP_COUNT (1)
-/* @brief L2CACHEC availability on the SoC. */
-#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0)
-/* @brief LCD availability on the SoC. */
-#define FSL_FEATURE_SOC_LCD_COUNT (0)
-/* @brief LCDC availability on the SoC. */
-#define FSL_FEATURE_SOC_LCDC_COUNT (0)
 /* @brief LCDIF availability on the SoC. */
 #define FSL_FEATURE_SOC_LCDIF_COUNT (1)
-/* @brief LDO availability on the SoC. */
-#define FSL_FEATURE_SOC_LDO_COUNT (0)
-/* @brief LLWU availability on the SoC. */
-#define FSL_FEATURE_SOC_LLWU_COUNT (0)
-/* @brief LMEM availability on the SoC. */
-#define FSL_FEATURE_SOC_LMEM_COUNT (0)
-/* @brief LPADC availability on the SoC. */
-#define FSL_FEATURE_SOC_LPADC_COUNT (0)
-/* @brief LPCMP availability on the SoC. */
-#define FSL_FEATURE_SOC_LPCMP_COUNT (0)
-/* @brief LPDAC availability on the SoC. */
-#define FSL_FEATURE_SOC_LPDAC_COUNT (0)
 /* @brief LPI2C availability on the SoC. */
 #define FSL_FEATURE_SOC_LPI2C_COUNT (4)
-/* @brief LPIT availability on the SoC. */
-#define FSL_FEATURE_SOC_LPIT_COUNT (0)
-/* @brief LPSCI availability on the SoC. */
-#define FSL_FEATURE_SOC_LPSCI_COUNT (0)
 /* @brief LPSPI availability on the SoC. */
 #define FSL_FEATURE_SOC_LPSPI_COUNT (4)
-/* @brief LPTMR availability on the SoC. */
-#define FSL_FEATURE_SOC_LPTMR_COUNT (0)
-/* @brief LPTPM availability on the SoC. */
-#define FSL_FEATURE_SOC_LPTPM_COUNT (0)
 /* @brief LPUART availability on the SoC. */
 #define FSL_FEATURE_SOC_LPUART_COUNT (8)
-/* @brief LTC availability on the SoC. */
-#define FSL_FEATURE_SOC_LTC_COUNT (0)
-/* @brief MAILBOX availability on the SoC. */
-#define FSL_FEATURE_SOC_MAILBOX_COUNT (0)
-/* @brief MC availability on the SoC. */
-#define FSL_FEATURE_SOC_MC_COUNT (0)
-/* @brief MCG availability on the SoC. */
-#define FSL_FEATURE_SOC_MCG_COUNT (0)
-/* @brief MCGLITE availability on the SoC. */
-#define FSL_FEATURE_SOC_MCGLITE_COUNT (0)
-/* @brief MCM availability on the SoC. */
-#define FSL_FEATURE_SOC_MCM_COUNT (0)
-/* @brief MIPI_CSI2 availability on the SoC. */
-#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0)
-/* @brief MIPI_CSI2RX availability on the SoC. */
-#define FSL_FEATURE_SOC_MIPI_CSI2RX_COUNT (0)
-/* @brief MIPI_DSI availability on the SoC. */
-#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0)
-/* @brief MIPI_DSI_HOST availability on the SoC. */
-#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0)
-/* @brief MMAU availability on the SoC. */
-#define FSL_FEATURE_SOC_MMAU_COUNT (0)
-/* @brief MMCAU availability on the SoC. */
-#define FSL_FEATURE_SOC_MMCAU_COUNT (0)
-/* @brief MMDC availability on the SoC. */
-#define FSL_FEATURE_SOC_MMDC_COUNT (0)
-/* @brief MMDVSQ availability on the SoC. */
-#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
-/* @brief MPU availability on the SoC. */
-#define FSL_FEATURE_SOC_MPU_COUNT (0)
-/* @brief MRT availability on the SoC. */
-#define FSL_FEATURE_SOC_MRT_COUNT (0)
-/* @brief MSCAN availability on the SoC. */
-#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
-/* @brief MSCM availability on the SoC. */
-#define FSL_FEATURE_SOC_MSCM_COUNT (0)
-/* @brief MTB availability on the SoC. */
-#define FSL_FEATURE_SOC_MTB_COUNT (0)
-/* @brief MTBDWT availability on the SoC. */
-#define FSL_FEATURE_SOC_MTBDWT_COUNT (0)
-/* @brief MU availability on the SoC. */
-#define FSL_FEATURE_SOC_MU_COUNT (0)
-/* @brief NFC availability on the SoC. */
-#define FSL_FEATURE_SOC_NFC_COUNT (0)
 /* @brief OCOTP availability on the SoC. */
 #define FSL_FEATURE_SOC_OCOTP_COUNT (1)
-/* @brief OPAMP availability on the SoC. */
-#define FSL_FEATURE_SOC_OPAMP_COUNT (0)
-/* @brief OTPC availability on the SoC. */
-#define FSL_FEATURE_SOC_OTPC_COUNT (0)
-/* @brief OSC availability on the SoC. */
-#define FSL_FEATURE_SOC_OSC_COUNT (0)
-/* @brief OSC32 availability on the SoC. */
-#define FSL_FEATURE_SOC_OSC32_COUNT (0)
-/* @brief OTFAD availability on the SoC. */
-#define FSL_FEATURE_SOC_OTFAD_COUNT (0)
-/* @brief PCC availability on the SoC. */
-#define FSL_FEATURE_SOC_PCC_COUNT (0)
-/* @brief PCIE_PHY_CMN availability on the SoC. */
-#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0)
-/* @brief PCIE_PHY_TRSV availability on the SoC. */
-#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0)
-/* @brief PDB availability on the SoC. */
-#define FSL_FEATURE_SOC_PDB_COUNT (0)
-/* @brief PGA availability on the SoC. */
-#define FSL_FEATURE_SOC_PGA_COUNT (0)
-/* @brief PIMCTL availability on the SoC. */
-#define FSL_FEATURE_SOC_PIMCTL_COUNT (0)
-/* @brief PINT availability on the SoC. */
-#define FSL_FEATURE_SOC_PINT_COUNT (0)
 /* @brief PIT availability on the SoC. */
 #define FSL_FEATURE_SOC_PIT_COUNT (1)
-/* @brief PMC availability on the SoC. */
-#define FSL_FEATURE_SOC_PMC_COUNT (0)
 /* @brief PMU availability on the SoC. */
 #define FSL_FEATURE_SOC_PMU_COUNT (1)
-/* @brief POWERQUAD availability on the SoC. */
-#define FSL_FEATURE_SOC_POWERQUAD_COUNT (0)
-/* @brief PORT availability on the SoC. */
-#define FSL_FEATURE_SOC_PORT_COUNT (0)
-/* @brief PROP availability on the SoC. */
-#define FSL_FEATURE_SOC_PROP_COUNT (0)
 /* @brief PWM availability on the SoC. */
 #define FSL_FEATURE_SOC_PWM_COUNT (4)
-/* @brief PWT availability on the SoC. */
-#define FSL_FEATURE_SOC_PWT_COUNT (0)
 /* @brief PXP availability on the SoC. */
 #define FSL_FEATURE_SOC_PXP_COUNT (1)
-/* @brief QDDKEY availability on the SoC. */
-#define FSL_FEATURE_SOC_QDDKEY_COUNT (0)
-/* @brief QDEC availability on the SoC. */
-#define FSL_FEATURE_SOC_QDEC_COUNT (0)
-/* @brief QuadSPI availability on the SoC. */
-#define FSL_FEATURE_SOC_QuadSPI_COUNT (0)
-/* @brief RCM availability on the SoC. */
-#define FSL_FEATURE_SOC_RCM_COUNT (0)
-/* @brief RDC availability on the SoC. */
-#define FSL_FEATURE_SOC_RDC_COUNT (0)
-/* @brief RDC_SEMAPHORE availability on the SoC. */
-#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0)
-/* @brief RFSYS availability on the SoC. */
-#define FSL_FEATURE_SOC_RFSYS_COUNT (0)
-/* @brief RFVBAT availability on the SoC. */
-#define FSL_FEATURE_SOC_RFVBAT_COUNT (0)
-/* @brief RIT availability on the SoC. */
-#define FSL_FEATURE_SOC_RIT_COUNT (0)
-/* @brief RNG availability on the SoC. */
-#define FSL_FEATURE_SOC_RNG_COUNT (0)
-/* @brief RNGB availability on the SoC. */
-#define FSL_FEATURE_SOC_RNGB_COUNT (0)
-/* @brief ROM availability on the SoC. */
-#define FSL_FEATURE_SOC_ROM_COUNT (0)
 /* @brief ROMC availability on the SoC. */
 #define FSL_FEATURE_SOC_ROMC_COUNT (1)
-/* @brief RSIM availability on the SoC. */
-#define FSL_FEATURE_SOC_RSIM_COUNT (0)
-/* @brief RSTCTL0 availability on the SoC. */
-#define FSL_FEATURE_SOC_RSTCTL0_COUNT (0)
-/* @brief RSTCTL1 availability on the SoC. */
-#define FSL_FEATURE_SOC_RSTCTL1_COUNT (0)
-/* @brief RTC availability on the SoC. */
-#define FSL_FEATURE_SOC_RTC_COUNT (0)
-/* @brief SCG availability on the SoC. */
-#define FSL_FEATURE_SOC_SCG_COUNT (0)
-/* @brief SCI availability on the SoC. */
-#define FSL_FEATURE_SOC_SCI_COUNT (0)
-/* @brief SCT availability on the SoC. */
-#define FSL_FEATURE_SOC_SCT_COUNT (0)
-/* @brief SDHC availability on the SoC. */
-#define FSL_FEATURE_SOC_SDHC_COUNT (0)
-/* @brief SDIF availability on the SoC. */
-#define FSL_FEATURE_SOC_SDIF_COUNT (0)
-/* @brief SDIO availability on the SoC. */
-#define FSL_FEATURE_SOC_SDIO_COUNT (0)
-/* @brief SDMA availability on the SoC. */
-#define FSL_FEATURE_SOC_SDMA_COUNT (0)
-/* @brief SDMAARM availability on the SoC. */
-#define FSL_FEATURE_SOC_SDMAARM_COUNT (0)
-/* @brief SDMABP availability on the SoC. */
-#define FSL_FEATURE_SOC_SDMABP_COUNT (0)
-/* @brief SDMACORE availability on the SoC. */
-#define FSL_FEATURE_SOC_SDMACORE_COUNT (0)
-/* @brief SDMCORE availability on the SoC. */
-#define FSL_FEATURE_SOC_SDMCORE_COUNT (0)
-/* @brief SDRAM availability on the SoC. */
-#define FSL_FEATURE_SOC_SDRAM_COUNT (0)
-/* @brief SEMA4 availability on the SoC. */
-#define FSL_FEATURE_SOC_SEMA4_COUNT (0)
-/* @brief SEMA42 availability on the SoC. */
-#define FSL_FEATURE_SOC_SEMA42_COUNT (0)
 /* @brief SEMC availability on the SoC. */
 #define FSL_FEATURE_SOC_SEMC_COUNT (1)
-/* @brief SHA availability on the SoC. */
-#define FSL_FEATURE_SOC_SHA_COUNT (0)
-/* @brief SIM availability on the SoC. */
-#define FSL_FEATURE_SOC_SIM_COUNT (0)
-/* @brief SJC availability on the SoC. */
-#define FSL_FEATURE_SOC_SJC_COUNT (0)
-/* @brief SLCD availability on the SoC. */
-#define FSL_FEATURE_SOC_SLCD_COUNT (0)
-/* @brief SMARTCARD availability on the SoC. */
-#define FSL_FEATURE_SOC_SMARTCARD_COUNT (0)
-/* @brief SMC availability on the SoC. */
-#define FSL_FEATURE_SOC_SMC_COUNT (0)
 /* @brief SNVS availability on the SoC. */
 #define FSL_FEATURE_SOC_SNVS_COUNT (1)
-/* @brief SPBA availability on the SoC. */
-#define FSL_FEATURE_SOC_SPBA_COUNT (0)
 /* @brief SPDIF availability on the SoC. */
 #define FSL_FEATURE_SOC_SPDIF_COUNT (1)
-/* @brief SPI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPI_COUNT (0)
-/* @brief SPIFI availability on the SoC. */
-#define FSL_FEATURE_SOC_SPIFI_COUNT (0)
-/* @brief SPM availability on the SoC. */
-#define FSL_FEATURE_SOC_SPM_COUNT (0)
 /* @brief SRC availability on the SoC. */
 #define FSL_FEATURE_SOC_SRC_COUNT (1)
-/* @brief SYSCON availability on the SoC. */
-#define FSL_FEATURE_SOC_SYSCON_COUNT (0)
-/* @brief SYSCTL0 availability on the SoC. */
-#define FSL_FEATURE_SOC_SYSCTL0_COUNT (0)
-/* @brief SYSCTL1 availability on the SoC. */
-#define FSL_FEATURE_SOC_SYSCTL1_COUNT (0)
 /* @brief TEMPMON availability on the SoC. */
 #define FSL_FEATURE_SOC_TEMPMON_COUNT (1)
 /* @brief TMR availability on the SoC. */
 #define FSL_FEATURE_SOC_TMR_COUNT (4)
-/* @brief TPM availability on the SoC. */
-#define FSL_FEATURE_SOC_TPM_COUNT (0)
-/* @brief TRGMUX availability on the SoC. */
-#define FSL_FEATURE_SOC_TRGMUX_COUNT (0)
-/* @brief TRIAMP availability on the SoC. */
-#define FSL_FEATURE_SOC_TRIAMP_COUNT (0)
 /* @brief TRNG availability on the SoC. */
 #define FSL_FEATURE_SOC_TRNG_COUNT (1)
 /* @brief TSC availability on the SoC. */
 #define FSL_FEATURE_SOC_TSC_COUNT (1)
-/* @brief TSI availability on the SoC. */
-#define FSL_FEATURE_SOC_TSI_COUNT (0)
-/* @brief TSTMR availability on the SoC. */
-#define FSL_FEATURE_SOC_TSTMR_COUNT (0)
-/* @brief UART availability on the SoC. */
-#define FSL_FEATURE_SOC_UART_COUNT (0)
-/* @brief USART availability on the SoC. */
-#define FSL_FEATURE_SOC_USART_COUNT (0)
-/* @brief USB availability on the SoC. */
-#define FSL_FEATURE_SOC_USB_COUNT (0)
 /* @brief USBHS availability on the SoC. */
 #define FSL_FEATURE_SOC_USBHS_COUNT (2)
-/* @brief USBDCD availability on the SoC. */
-#define FSL_FEATURE_SOC_USBDCD_COUNT (0)
-/* @brief USBFSH availability on the SoC. */
-#define FSL_FEATURE_SOC_USBFSH_COUNT (0)
-/* @brief USBHSD availability on the SoC. */
-#define FSL_FEATURE_SOC_USBHSD_COUNT (0)
-/* @brief USBHSDCD availability on the SoC. */
-#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0)
-/* @brief USBHSH availability on the SoC. */
-#define FSL_FEATURE_SOC_USBHSH_COUNT (0)
 /* @brief USBNC availability on the SoC. */
 #define FSL_FEATURE_SOC_USBNC_COUNT (2)
 /* @brief USBPHY availability on the SoC. */
 #define FSL_FEATURE_SOC_USBPHY_COUNT (2)
-/* @brief USB_HSIC availability on the SoC. */
-#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0)
-/* @brief USB_OTG availability on the SoC. */
-#define FSL_FEATURE_SOC_USB_OTG_COUNT (0)
-/* @brief USBVREG availability on the SoC. */
-#define FSL_FEATURE_SOC_USBVREG_COUNT (0)
 /* @brief USDHC availability on the SoC. */
 #define FSL_FEATURE_SOC_USDHC_COUNT (2)
-/* @brief UTICK availability on the SoC. */
-#define FSL_FEATURE_SOC_UTICK_COUNT (0)
-/* @brief VIU availability on the SoC. */
-#define FSL_FEATURE_SOC_VIU_COUNT (0)
-/* @brief VREF availability on the SoC. */
-#define FSL_FEATURE_SOC_VREF_COUNT (0)
-/* @brief VFIFO availability on the SoC. */
-#define FSL_FEATURE_SOC_VFIFO_COUNT (0)
 /* @brief WDOG availability on the SoC. */
 #define FSL_FEATURE_SOC_WDOG_COUNT (2)
-/* @brief WKPU availability on the SoC. */
-#define FSL_FEATURE_SOC_WKPU_COUNT (0)
-/* @brief WWDT availability on the SoC. */
-#define FSL_FEATURE_SOC_WWDT_COUNT (0)
-/* @brief XBAR availability on the SoC. */
-#define FSL_FEATURE_SOC_XBAR_COUNT (0)
 /* @brief XBARA availability on the SoC. */
 #define FSL_FEATURE_SOC_XBARA_COUNT (1)
 /* @brief XBARB availability on the SoC. */
 #define FSL_FEATURE_SOC_XBARB_COUNT (2)
-/* @brief XCVR availability on the SoC. */
-#define FSL_FEATURE_SOC_XCVR_COUNT (0)
-/* @brief XRDC availability on the SoC. */
-#define FSL_FEATURE_SOC_XRDC_COUNT (0)
-/* @brief XTALOSC availability on the SoC. */
-#define FSL_FEATURE_SOC_XTALOSC_COUNT (0)
 /* @brief XTALOSC24M availability on the SoC. */
 #define FSL_FEATURE_SOC_XTALOSC24M_COUNT (1)
-/* @brief ZLL availability on the SoC. */
-#define FSL_FEATURE_SOC_ZLL_COUNT (0)
 
 /* ADC module features */
 
@@ -582,6 +167,11 @@
 /* @brief Remove ALT Clock selection feature. */
 #define FSL_FEATURE_ADC_SUPPORT_ALTCLK_REMOVE (1)
 
+/* ADC_ETC module features */
+
+/* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
+#define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
+
 /* AOI module features */
 
 /* @brief Maximum value of input mux. */
@@ -666,6 +256,29 @@
 /* @brief Has Additional 1588 Timer Channel Interrupt. */
 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (0)
 
+/* FLEXIO module features */
+
+/* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */
+#define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1)
+/* @brief Has Pin Data Input Register (FLEXIO_PIN) */
+#define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1)
+/* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (1)
+/* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (1)
+/* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */
+#define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (1)
+/* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (1)
+/* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */
+#define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (1)
+/* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */
+#define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (1)
+/* @brief Reset value of the FLEXIO_VERID register */
+#define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010001)
+/* @brief Reset value of the FLEXIO_PARAM register */
+#define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x2200404)
+
 /* FLEXRAM module features */
 
 /* @brief Bank size */
@@ -697,6 +310,15 @@
 /* @brief Supports IRQ 0-31. */
 #define FSL_FEATURE_GPC_HAS_IRQ_0_31 (1)
 
+/* IGPIO module features */
+
+/* @brief Has data register set DR_SET. */
+#define FSL_FEATURE_IGPIO_HAS_DR_SET (1)
+/* @brief Has data register clear DR_CLEAR. */
+#define FSL_FEATURE_IGPIO_HAS_DR_CLEAR (1)
+/* @brief Has data register toggle DR_TOGGLE. */
+#define FSL_FEATURE_IGPIO_HAS_DR_TOGGLE (1)
+
 /* LCDIF module features */
 
 /* @brief LCDIF does not support alpha support. */
@@ -912,7 +534,7 @@
 /* @brief There is CORE0_RST bit in SCR register. */
 #define FSL_FEATURE_SRC_HAS_SCR_CORE0_RST (1)
 /* @brief There is LOCKUP_RST bit in SCR register. */
-#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (1)
+#define FSL_FEATURE_SRC_HAS_SCR_LOCKUP_RST (0)
 /* @brief There is SWRC bit in SCR register. */
 #define FSL_FEATURE_SRC_HAS_SCR_SWRC (0)
 /* @brief There is EIM_RST bit in SCR register. */

bsp/imxrt1052-evk/Libraries/SConscript

@@ -12,7 +12,7 @@ src += Glob('common/chip/*.c')
 src += [cwd + '/system_MIMXRT1052.c']
 
 CPPPATH = [ cwd, cwd + '/drivers', cwd + '/utilities', cwd + '/CMSIS/Include']
-CPPDEFINES = ['CPU_MIMXRT1052DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
+CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1']
 
 # add for startup script 
 if rtconfig.CROSS_TOOL == 'gcc':

bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_adc.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.adc_12b1msps_sar"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_adc.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,11 @@
 
 #include "fsl_adc_etc.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.adc_etc"
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -90,7 +99,11 @@ void ADC_ETC_Init(ADC_ETC_Type *base, const adc_etc_config_t *config)
     /* Set ADC_ETC_CTRL register. */
     tmp32 = ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(config->TSC0triggerPriority) |
             ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(config->TSC1triggerPriority) |
-            ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask);
+            ADC_ETC_CTRL_PRE_DIVIDER(config->clockPreDivider) | ADC_ETC_CTRL_TRIG_ENABLE(config->XBARtriggerMask)
+#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
+            | ADC_ETC_CTRL_DMA_MODE_SEL(config->dmaMode)
+#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
+        ;
     if (config->enableTSCBypass)
     {
         tmp32 |= ADC_ETC_CTRL_TSC_BYPASS_MASK;
@@ -124,6 +137,9 @@ void ADC_ETC_GetDefaultConfig(adc_etc_config_t *config)
     config->enableTSCBypass = true;
     config->enableTSC0Trigger = false;
     config->enableTSC1Trigger = false;
+#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
+    config->dmaMode = kADC_ETC_TrigDMAWithLatchedSignal;
+#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
     config->TSC0triggerPriority = 0U;
     config->TSC1triggerPriority = 0U;
     config->clockPreDivider = 0U;

bsp/imxrt1052-evk/Libraries/drivers/fsl_adc_etc.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -87,6 +91,17 @@ typedef enum _adc_etc_interrupt_enable
     kADC_ETC_Done2InterruptEnable = 3U, /* Enable the DONE2 interrupt when ADC conversions complete. */
 } adc_etc_interrupt_enable_t;
 
+#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
+/*!
+* @brief DMA mode selection.
+*/
+typedef enum _adc_etc_dma_mode_selection
+{
+    kADC_ETC_TrigDMAWithLatchedSignal = 0U,  /* Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared. */
+    kADC_ETC_TrigDMAWithPulsedSignal = 1U,   /* Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only. */
+} adc_etc_dma_mode_selection_t;
+#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
+
 /*!
  * @brief ADC_ETC configuration.
  */
@@ -96,6 +111,9 @@ typedef struct _adc_etc_config
                                      Otherwise TSC would trigger ADC through ADC_ETC. */
     bool enableTSC0Trigger;       /* Enable external TSC0 trigger. It is valid when enableTSCBypass = false. */
     bool enableTSC1Trigger;       /* Enable external TSC1 trigger. It is valid when enableTSCBypass = false.*/
+#if defined(FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL) && FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL
+    adc_etc_dma_mode_selection_t dmaMode; /* Select the ADC_ETC DMA mode. */ 
+#endif /*FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL*/
     uint32_t TSC0triggerPriority; /* External TSC0 trigger priority, 7 is highest, 0 is lowest. */
     uint32_t TSC1triggerPriority; /* External TSC1 trigger priority, 7 is highest, 0 is lowest. */
     uint32_t clockPreDivider;     /* Pre-divider for trig delay and interval. Available range is 0-255.

bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.aipstz"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_aipstz.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -68,7 +72,7 @@ typedef enum _aipstz_peripheral_access_control {
     kAIPSTZ_PeripheralAllowUntrustedMaster = 1U,
     kAIPSTZ_PeripheralWriteProtected = (1U << 1),
     kAIPSTZ_PeripheralRequireSupervisor = (1U << 2),
-    kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 2)
+    kAIPSTZ_PeripheralAllowBufferedWrite = (1U << 3)
 } aipstz_peripheral_access_control_t;
 
 /*! @brief List of AIPSTZ peripherals. Organized by register offset for higher 32 bits, width for the 8-15 bits and shift for lower 8 bits.*/

bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -29,6 +33,12 @@
  */
 #include "fsl_aoi.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.aoi"
+#endif
+
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_aoi.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.bee"
+#endif
+
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_bee.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,7 +37,13 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cache_armv7_m7"
+#endif
+
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #define L2CACHE_OPERATION_TIMEOUT 0xFFFFFU
 #define L2CACHE_8WAYS_MASK 0xFFU
 #define L2CACHE_16WAYS_MASK 0xFFFFU
@@ -126,7 +136,7 @@ static void L2CACHE_SetAndWaitBackGroundOperate(uint32_t auxCtlReg, uint32_t reg
     /* Set the opeartion for all ways/entries of the cache. */
     *(uint32_t *)regAddr = mask;
     /* Waiting for until the operation is complete. */
-    while ((*(uint32_t *)regAddr & mask) && timeout)
+    while ((*(volatile uint32_t *)regAddr & mask) && timeout)
     {
         __ASM("nop");
         timeout--;
@@ -397,7 +407,7 @@ void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable)
         L2CACHEC->LOCKDOWN[masterId].REG9_I_LOCKDOWN = istrReg & ~mask;
     }
 }
-#endif  /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
+#endif  /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
 {
@@ -420,41 +430,41 @@ void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte)
 
 void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
     L2CACHE_InvalidateByRange(address, size_byte);
 #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
-#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
    L1CACHE_InvalidateICacheByRange(address, size_byte);
 }
 
 void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte)
 {
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
     L2CACHE_InvalidateByRange(address, size_byte);
 #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
-#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
     L1CACHE_InvalidateDCacheByRange(address, size_byte);
 }
 
 void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte)
 {
     L1CACHE_CleanDCacheByRange(address, size_byte);
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
     L2CACHE_CleanByRange(address, size_byte);
 #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
-#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 }
 
 void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte)
 {
     L1CACHE_CleanInvalidateDCacheByRange(address, size_byte);
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #if defined(FSL_SDK_DISBLE_L2CACHE_PRESENT) && !FSL_SDK_DISBLE_L2CACHE_PRESENT
     L2CACHE_CleanInvalidateByRange(address, size_byte);
 #endif /* !FSL_SDK_DISBLE_L2CACHE_PRESENT */
-#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT > 0 */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_cache.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -47,15 +51,15 @@
 #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
 /*@}*/
 
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 #ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
 #define FSL_SDK_DISBLE_L2CACHE_PRESENT   0
 #endif
-#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 
 /*! @brief Number of level 2 cache controller ways. */
 typedef enum _l2cache_way_num
@@ -133,7 +137,7 @@ typedef struct _l2cache_config
     /* ------------------------ other settings -------------------------------------- */
     l2cache_writealloc_t  writeAlloc;/*!< Write allcoate force option. */     
 } l2cache_config_t;
-#endif  /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
+#endif  /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -286,7 +290,7 @@ static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32
 }
 /*@}*/
 
-#if (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0)
+#if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
 /*!
  * @name Control for L2 pl310 cache
  *@{
@@ -414,7 +418,7 @@ void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
 
 /*@}*/
-#endif /* (FSL_FEATURE_SOC_L2CACHEC_COUNT > 0) */
+#endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
 
 /*!
  * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)

bsp/imxrt1052-evk/Libraries/drivers/fsl_clock.c

@@ -1,8 +1,11 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -27,12 +31,11 @@
  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "fsl_common.h"
 #include "fsl_clock.h"
-
-/*******************************************************************************
- * Definitions
- ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.clock"
+#endif
 
 /*******************************************************************************
  * Variables
@@ -47,9 +50,17 @@ uint32_t g_rtcXtalFreq;
  * Prototypes
  ******************************************************************************/
 
+/*!
+ * @brief Get the periph clock frequency.
+ *
+ * @return Periph clock frequency in Hz.
+ */
+static uint32_t CLOCK_GetPeriphClkFreq(void);
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
+
 static uint32_t CLOCK_GetPeriphClkFreq(void)
 {
     uint32_t freq;
@@ -70,6 +81,9 @@ static uint32_t CLOCK_GetPeriphClkFreq(void)
                 break;
 
             case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
+                freq = CLOCK_GetPllFreq(kCLOCK_PllSys);
+                break;
+
             case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
             default:
                 freq = 0U;
@@ -100,7 +114,8 @@ static uint32_t CLOCK_GetPeriphClkFreq(void)
 
             /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
             case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
-                freq = CLOCK_GetPllFreq(kCLOCK_PllArm) / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
+                freq = CLOCK_GetPllFreq(kCLOCK_PllArm) /
+                       (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
                 break;
 
             default:
@@ -158,10 +173,11 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
     switch (name)
     {
         case kCLOCK_CpuClk:
-            /* Periph_clk ---> AHB Clock */
+        /* Periph_clk ---> AHB Clock */
         case kCLOCK_AhbClk:
             /* Periph_clk ---> AHB Clock */
-            freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
+            freq =
+                CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
             break;
 
         case kCLOCK_SemcClk:
@@ -190,7 +206,8 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
 
         case kCLOCK_IpgClk:
             /* Periph_clk ---> AHB Clock ---> IPG Clock */
-            freq = CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
+            freq =
+                CLOCK_GetPeriphClkFreq() / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U);
             freq /= (((CCM->CBCDR & CCM_CBCDR_IPG_PODF_MASK) >> CCM_CBCDR_IPG_PODF_SHIFT) + 1U);
             break;
 
@@ -237,13 +254,10 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
             freq = CLOCK_GetSysPfdFreq(kCLOCK_Pfd3);
             break;
         case kCLOCK_EnetPll0Clk:
-            freq = CLOCK_GetPllFreq(kCLOCK_PllEnet0);
+            freq = CLOCK_GetPllFreq(kCLOCK_PllEnet);
             break;
         case kCLOCK_EnetPll1Clk:
-            freq = CLOCK_GetPllFreq(kCLOCK_PllEnet1);
-            break;
-        case kCLOCK_EnetPll2Clk:
-            freq = CLOCK_GetPllFreq(kCLOCK_PllEnet2);
+            freq = CLOCK_GetPllFreq(kCLOCK_PllEnet25M);
             break;
         case kCLOCK_AudioPllClk:
             freq = CLOCK_GetPllFreq(kCLOCK_PllAudio);
@@ -259,14 +273,76 @@ uint32_t CLOCK_GetFreq(clock_name_t name)
     return freq;
 }
 
+bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
+{
+    CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
+    USB1->USBCMD |= USBHS_USBCMD_RST_MASK;
+    for (volatile uint32_t i = 0; i < 400000;
+         i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
+    {
+        __ASM("nop");
+    }
+    PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) |
+                   (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
+    return true;
+}
+
+bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
+{
+    CCM->CCGR6 |= CCM_CCGR6_CG0_MASK;
+    USB2->USBCMD |= USBHS_USBCMD_RST_MASK;
+    for (volatile uint32_t i = 0; i < 400000;
+         i++) /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
+    {
+        __ASM("nop");
+    }
+    PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) |
+                   (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
+    return true;
+}
+
+bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
+{
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
+    if (CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
+    {
+        CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; 
+    }
+    else
+    {
+        CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
+    }
+    USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
+    USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
+
+    USBPHY1->PWD = 0;
+    USBPHY1->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
+                     USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK;
+    return true;
+}
+
+void CLOCK_DisableUsbhs0PhyPllClock(void)
+{
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK; 
+    USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
+}
+
 void CLOCK_InitArmPll(const clock_arm_pll_config_t *config)
 {
-    CCM_ANALOG->PLL_ARM = CCM_ANALOG_PLL_ARM_ENABLE_MASK |
-                          CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider);
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_ARM = (CCM_ANALOG->PLL_ARM & (~CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)) |
+                          CCM_ANALOG_PLL_ARM_BYPASS_MASK | CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(config->src);
+
+    CCM_ANALOG->PLL_ARM =
+        (CCM_ANALOG->PLL_ARM & (~(CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK | CCM_ANALOG_PLL_ARM_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_ARM_ENABLE_MASK | CCM_ANALOG_PLL_ARM_DIV_SELECT(config->loopDivider);
 
     while ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_ARM &= ~CCM_ANALOG_PLL_ARM_BYPASS_MASK;
 }
 
 void CLOCK_DeinitArmPll(void)
@@ -276,12 +352,20 @@ void CLOCK_DeinitArmPll(void)
 
 void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
 {
-    CCM_ANALOG->PLL_SYS = CCM_ANALOG_PLL_SYS_ENABLE_MASK |
-                          CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_SYS = (CCM_ANALOG->PLL_SYS & (~CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)) |
+                          CCM_ANALOG_PLL_SYS_BYPASS_MASK | CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(config->src);
+
+    CCM_ANALOG->PLL_SYS =
+        (CCM_ANALOG->PLL_SYS & (~(CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK | CCM_ANALOG_PLL_SYS_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_SYS_ENABLE_MASK | CCM_ANALOG_PLL_SYS_DIV_SELECT(config->loopDivider);
 
     while ((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_BYPASS_MASK;
 }
 
 void CLOCK_DeinitSysPll(void)
@@ -291,14 +375,20 @@ void CLOCK_DeinitSysPll(void)
 
 void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config)
 {
-    CCM_ANALOG->PLL_USB1 = CCM_ANALOG_PLL_USB1_ENABLE_MASK      |
-                           CCM_ANALOG_PLL_USB1_POWER_MASK       |
-                           CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK |
-                           CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider);
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)) |
+                           CCM_ANALOG_PLL_USB1_BYPASS_MASK | CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(config->src);
+
+    CCM_ANALOG->PLL_USB1 = (CCM_ANALOG->PLL_USB1 & (~CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)) |
+                           CCM_ANALOG_PLL_USB1_ENABLE_MASK | CCM_ANALOG_PLL_USB1_POWER_MASK |
+                           CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB1_DIV_SELECT(config->loopDivider);
 
     while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK;
 }
 
 void CLOCK_DeinitUsb1Pll(void)
@@ -308,14 +398,20 @@ void CLOCK_DeinitUsb1Pll(void)
 
 void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config)
 {
-    CCM_ANALOG->PLL_USB2 = CCM_ANALOG_PLL_USB2_ENABLE_MASK      |
-                           CCM_ANALOG_PLL_USB2_POWER_MASK       |
-                           CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK |
-                           CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider);
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)) |
+                           CCM_ANALOG_PLL_USB2_BYPASS_MASK | CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(config->src);
+
+    CCM_ANALOG->PLL_USB2 = (CCM_ANALOG->PLL_USB2 & (~CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)) |
+                           CCM_ANALOG_PLL_USB2_ENABLE_MASK | CCM_ANALOG_PLL_USB2_POWER_MASK |
+                           CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK | CCM_ANALOG_PLL_USB2_DIV_SELECT(config->loopDivider);
 
     while ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_BYPASS_MASK;
 }
 
 void CLOCK_DeinitUsb2Pll(void)
@@ -328,6 +424,10 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
     uint32_t pllAudio;
     uint32_t misc2 = 0;
 
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_AUDIO = (CCM_ANALOG->PLL_AUDIO & (~CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_AUDIO_BYPASS_MASK | CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(config->src);
+
     CCM_ANALOG->PLL_AUDIO_NUM = CCM_ANALOG_PLL_AUDIO_NUM_A(config->numerator);
     CCM_ANALOG->PLL_AUDIO_DENOM = CCM_ANALOG_PLL_AUDIO_DENOM_B(config->denominator);
 
@@ -348,7 +448,9 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
      * |         16          |            0                |        3         |
      * ------------------------------------------------------------------------
      */
-    pllAudio = CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider);
+    pllAudio =
+        (CCM_ANALOG->PLL_AUDIO & (~(CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK | CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_AUDIO_ENABLE_MASK | CCM_ANALOG_PLL_AUDIO_DIV_SELECT(config->loopDivider);
 
     switch (config->postDivider)
     {
@@ -376,14 +478,17 @@ void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
             break;
     }
 
-    CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK))
-                      | misc2;
+    CCM_ANALOG->MISC2 =
+        (CCM_ANALOG->MISC2 & ~(CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK | CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)) | misc2;
 
     CCM_ANALOG->PLL_AUDIO = pllAudio;
 
     while ((CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_AUDIO &= ~CCM_ANALOG_PLL_AUDIO_BYPASS_MASK;
 }
 
 void CLOCK_DeinitAudioPll(void)
@@ -396,6 +501,10 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
     uint32_t pllVideo;
     uint32_t misc2 = 0;
 
+    /* Bypass PLL first */
+    CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+                            CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(config->src);
+
     CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(config->numerator);
     CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(config->denominator);
 
@@ -416,7 +525,9 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
      * |         16          |            0                |        3         |
      * ------------------------------------------------------------------------
      */
-    pllVideo = CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider);
+    pllVideo =
+        (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+        CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(config->loopDivider);
 
     switch (config->postDivider)
     {
@@ -451,6 +562,9 @@ void CLOCK_InitVideoPll(const clock_video_pll_config_t *config)
     while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
 }
 
 void CLOCK_DeinitVideoPll(void)
@@ -460,30 +574,32 @@ void CLOCK_DeinitVideoPll(void)
 
 void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config)
 {
-    uint32_t enet_pll = CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT(config->loopDivider1) |
-                        CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT(config->loopDivider0);
+    uint32_t enet_pll = CCM_ANALOG_PLL_ENET_DIV_SELECT(config->loopDivider);
 
-    if (config->enableClkOutput0)
-    {
-        enet_pll |= CCM_ANALOG_PLL_ENET_ENET1_125M_EN_MASK;
-    }
+    CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)) |
+                           CCM_ANALOG_PLL_ENET_BYPASS_MASK | CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(config->src);
 
-    if (config->enableClkOutput1)
+    if (config->enableClkOutput)
     {
-        enet_pll |= CCM_ANALOG_PLL_ENET_ENET2_125M_EN_MASK;
+        enet_pll |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
     }
 
-    if (config->enableClkOutput2)
+    if (config->enableClkOutput25M)
     {
         enet_pll |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
     }
 
-    CCM_ANALOG->PLL_ENET = enet_pll;
+    CCM_ANALOG->PLL_ENET =
+        (CCM_ANALOG->PLL_ENET & (~(CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK | CCM_ANALOG_PLL_ENET_POWERDOWN_MASK))) |
+        enet_pll;
 
     /* Wait for stable */
     while ((CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_LOCK_MASK) == 0)
     {
     }
+
+    /* Disable Bypass */
+    CCM_ANALOG->PLL_ENET &= ~CCM_ANALOG_PLL_ENET_BYPASS_MASK;
 }
 
 void CLOCK_DeinitEnetPll(void)
@@ -498,24 +614,38 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
     uint64_t freqTmp;
 
     const uint32_t enetRefClkFreq[] = {
-        25000000U, /* 25M */
-        50000000U, /* 50M */
+        25000000U,  /* 25M */
+        50000000U,  /* 50M */
         100000000U, /* 100M */
-        125000000U /* 125M */
+        125000000U  /* 125M */
     };
 
+    /* check if PLL is enabled */
+    if (!CLOCK_IsPllEnabled(CCM_ANALOG, pll))
+    {
+        return 0U;
+    }
+
+    /* get pll reference clock */
+    freq = CLOCK_GetPllBypassRefClk(CCM_ANALOG, pll);
+
+    /* check if pll is bypassed */
+    if (CLOCK_IsPllBypassed(CCM_ANALOG, pll))
+    {
+        return freq;
+    }
+
     switch (pll)
     {
         case kCLOCK_PllArm:
-            freq = ((CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
-                                         CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
+            freq = ((freq * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
+                             CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >>
+                    1U);
             break;
-
         case kCLOCK_PllSys:
-            freq = CLOCK_GetOscFreq();
-
             /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
-            freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
+            freqTmp =
+                ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM));
 
             if (CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
             {
@@ -530,16 +660,16 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
             break;
 
         case kCLOCK_PllUsb1:
-            freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
+            freq = (freq * ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) ? 22U : 20U));
             break;
 
         case kCLOCK_PllAudio:
-            freq = CLOCK_GetOscFreq();
-
             /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
-            divSelect = (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
+            divSelect =
+                (CCM_ANALOG->PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT;
 
-            freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
+            freqTmp =
+                ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_AUDIO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_AUDIO_DENOM));
 
             freq = freq * divSelect + (uint32_t)freqTmp;
 
@@ -589,12 +719,12 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
             break;
 
         case kCLOCK_PllVideo:
-            freq = CLOCK_GetOscFreq();
-
             /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
-            divSelect = (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
+            divSelect =
+                (CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT;
 
-            freqTmp = ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
+            freqTmp =
+                ((uint64_t)freq * ((uint64_t)(CCM_ANALOG->PLL_VIDEO_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_VIDEO_DENOM));
 
             freq = freq * divSelect + (uint32_t)freqTmp;
 
@@ -642,28 +772,20 @@ uint32_t CLOCK_GetPllFreq(clock_pll_t pll)
                     break;
             }
             break;
-
-        case kCLOCK_PllEnet0:
-            divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_MASK)
-                      >> CCM_ANALOG_PLL_ENET_ENET0_DIV_SELECT_SHIFT;
-            freq = enetRefClkFreq[divSelect];
-            break;
-
-        case kCLOCK_PllEnet1:
-            divSelect = (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_MASK)
-                      >> CCM_ANALOG_PLL_ENET_ENET1_DIV_SELECT_SHIFT;
+        case kCLOCK_PllEnet:
+            divSelect =
+                (CCM_ANALOG->PLL_ENET & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK) >> CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT;
             freq = enetRefClkFreq[divSelect];
             break;
 
-        case kCLOCK_PllEnet2:
-            /* ref_enetpll2 if fixed at 25MHz. */
+        case kCLOCK_PllEnet25M:
+            /* ref_enetpll1 if fixed at 25MHz. */
             freq = 25000000UL;
             break;
 
         case kCLOCK_PllUsb2:
-            freq = (CLOCK_GetOscFreq() * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U));
+            freq = (freq * ((CCM_ANALOG->PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK) ? 22U : 20U));
             break;
-
         default:
             freq = 0U;
             break;
@@ -677,7 +799,8 @@ void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac)
     uint32_t pfdIndex = (uint32_t)pfd;
     uint32_t pfd528;
 
-    pfd528 = CCM_ANALOG->PFD_528 & ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex));
+    pfd528 = CCM_ANALOG->PFD_528 &
+             ~((CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) << (8 * pfdIndex));
 
     /* Disable the clock output first. */
     CCM_ANALOG->PFD_528 = pfd528 | (CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK << (8 * pfdIndex));
@@ -696,7 +819,8 @@ void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac)
     uint32_t pfdIndex = (uint32_t)pfd;
     uint32_t pfd480;
 
-    pfd480 = CCM_ANALOG->PFD_480 & ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex));
+    pfd480 = CCM_ANALOG->PFD_480 &
+             ~((CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK | CCM_ANALOG_PFD_480_PFD0_FRAC_MASK) << (8 * pfdIndex));
 
     /* Disable the clock output first. */
     CCM_ANALOG->PFD_480 = pfd480 | (CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK << (8 * pfdIndex));
@@ -765,78 +889,29 @@ uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd)
 
         default:
             freq = 0U;
-		    break;
+            break;
     }
     freq *= 18U;
 
     return freq;
 }
 
-bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq)
-{
-    CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ;
-    USB1->USBCMD |= USBHS_USBCMD_RST_MASK;
-    for (volatile uint32_t i = 0; i < 400000; i++)    /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
-    {
-        __ASM("nop");
-    }
-    PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
-    return true;
-}
-
-
-bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq)
-{
-    CCM->CCGR6 |= CCM_CCGR6_CG0_MASK ;
-    USB2->USBCMD |= USBHS_USBCMD_RST_MASK;
-    for (volatile uint32_t i = 0; i < 400000; i++)    /* Add a delay between RST and RS so make sure there is a DP pullup sequence*/
-    {
-        __ASM("nop");
-    }
-    PMU->REG_3P0 = (PMU->REG_3P0 & (~PMU_REG_3P0_OUTPUT_TRG_MASK)) | (PMU_REG_3P0_OUTPUT_TRG(0x17) | PMU_REG_3P0_ENABLE_LINREG_MASK);
-    return true;
-}
-
-
-bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
-{
-    const clock_usb_pll_config_t g_ccmConfigUsbPll  = {.loopDivider = 0U};
-    CLOCK_InitUsb1Pll(&g_ccmConfigUsbPll);
-    USBPHY1->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */
-    USBPHY1->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
-
-    USBPHY1->PWD  = 0;
-    USBPHY1->CTRL |=
-    USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK |
-    USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
-    USBPHY_CTRL_ENUTMILEVEL2_MASK |
-    USBPHY_CTRL_ENUTMILEVEL3_MASK;
-    return true;
-}
 bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq)
 {
-    const clock_usb_pll_config_t g_ccmConfigUsbPll  = {.loopDivider = 0U};
+    const clock_usb_pll_config_t g_ccmConfigUsbPll = {.loopDivider = 0U};
     CLOCK_InitUsb2Pll(&g_ccmConfigUsbPll);
-    USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK;         /* release PHY from reset */
+    USBPHY2->CTRL &= ~USBPHY_CTRL_SFTRST_MASK; /* release PHY from reset */
     USBPHY2->CTRL &= ~USBPHY_CTRL_CLKGATE_MASK;
 
-    USBPHY2->PWD  = 0;
-    USBPHY2->CTRL |=
-            USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK |
-            USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
-            USBPHY_CTRL_ENUTMILEVEL2_MASK |
-            USBPHY_CTRL_ENUTMILEVEL3_MASK;
+    USBPHY2->PWD = 0;
+    USBPHY2->CTRL |= USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK | USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK |
+                     USBPHY_CTRL_ENUTMILEVEL2_MASK | USBPHY_CTRL_ENUTMILEVEL3_MASK;
 
     return true;
 }
-void CLOCK_DisableUsbhs0PhyPllClock(void)
-{
-    CLOCK_DeinitUsb1Pll();
-    USBPHY1->CTRL |= USBPHY_CTRL_CLKGATE_MASK;          /* Set to 1U to gate clocks */
 
-}
 void CLOCK_DisableUsbhs1PhyPllClock(void)
 {
-    CLOCK_DeinitUsb2Pll();
-    USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK;          /* Set to 1U to gate clocks */
+    CCM_ANALOG->PLL_USB2 &= ~CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK; 
+    USBPHY2->CTRL |= USBPHY_CTRL_CLKGATE_MASK; /* Set to 1U to gate clocks */
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_cmp.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cmp"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_cmp.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_common.c

@@ -1,10 +1,13 @@
 /*
+* The Clear BSD License
 * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016 NXP
 * All rights reserved.
 *
+* 
 * Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
+* are permitted (subject to the limitations in the disclaimer below) provided
+*  that the following conditions are met:
 *
 * o Redistributions of source code must retain the above copyright notice, this list
 *   of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
 *   contributors may be used to endorse or promote products derived from this
 *   software without specific prior written permission.
 *
+* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -38,6 +42,12 @@ typedef struct _mem_align_control_block
     uint16_t    offset;         /*!< offset from aligned adress to real address */
 } mem_align_cb_t;
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+
 #ifndef __GIC_PRIO_BITS
 #if defined(ENABLE_RAM_VECTOR_TABLE)
 uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
@@ -99,30 +109,50 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 
 void EnableDeepSleepIRQ(IRQn_Type interrupt)
 {
-    uint32_t index = 0;
     uint32_t intNumber = (uint32_t)interrupt;
-    while (intNumber >= 32u)
+
+#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
     {
-        index++;
-        intNumber -= 32u;
+        SYSCON->STARTERP1 = 1u << intNumber;
     }
+#else
+    {
+        uint32_t index = 0;
 
-    SYSCON->STARTERSET[index] = 1u << intNumber;
+        while (intNumber >= 32u)
+        {
+            index++;
+            intNumber -= 32u;
+        }
+
+        SYSCON->STARTERSET[index] = 1u << intNumber;
+    }
+#endif                    /* FSL_FEATURE_STARTER_DISCONTINUOUS */
     EnableIRQ(interrupt); /* also enable interrupt at NVIC */
 }
 
 void DisableDeepSleepIRQ(IRQn_Type interrupt)
 {
-    uint32_t index = 0;
     uint32_t intNumber = (uint32_t)interrupt;
-    while (intNumber >= 32u)
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+#if (defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && (FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS == 1))
     {
-        index++;
-        intNumber -= 32u;
+        SYSCON->STARTERP1 &= ~(1u << intNumber);
     }
+#else
+    {
+        uint32_t index = 0;
 
-    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
-    SYSCON->STARTERCLR[index] = 1u << intNumber;
+        while (intNumber >= 32u)
+        {
+            index++;
+            intNumber -= 32u;
+        }
+
+        SYSCON->STARTERCLR[index] = 1u << intNumber;
+    }
+#endif /* FSL_FEATURE_STARTER_DISCONTINUOUS */
 }
 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_common.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -65,14 +69,16 @@
 /*@}*/
 
 /* Debug console type definition. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U     /*!< No debug console.             */
-#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U     /*!< Debug console base on UART.   */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART 2U   /*!< Debug console base on LPUART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI 3U    /*!< Debug console base on LPSCI.  */
-#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U   /*!< Debug console base on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U    /*!< Debug console base on i.MX UART. */
-#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U   /*!< Debug console base on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE          0U      /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console base on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console base on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console base on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console base on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console base on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console base on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console base on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console base on SWO. */
 
 /*! @brief Status group numbers. */
 enum _status_groups
@@ -140,6 +146,7 @@ enum _status_groups
     kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
     kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
     kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */
     kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
     kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
     kStatusGroup_SEMC = 100,                   /*!< Group number for SEMC status codes. */    
@@ -175,6 +182,13 @@ typedef int32_t status_t;
 #include "fsl_reset.h"
 #endif
 
+/*
+ * Macro guard for whether to use default weak IRQ implementation in drivers
+ */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
 /*! @name Min/max macros */
 /* @{ */
 #if !defined(MIN)
@@ -273,13 +287,6 @@ _Pragma("diag_suppress=Pm120")
     ((unsigned int)((var) + ((alignbytes)-1)) & (unsigned int)(~(unsigned int)((alignbytes)-1)))
 /* @} */
 
-/*! Function to allocate/free L1 cache aligned memory using the malloc/free. */
-void *SDK_Malloc(size_t size, size_t alignbytes);
-
-void SDK_Free(void *ptr);
-
-/* @} */
-
 /*! @name Non-cacheable region definition macros */
 /* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
  * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
@@ -339,6 +346,37 @@ void SDK_Free(void *ptr);
 #endif
 /* @} */
 
+/*! @name Time sensitive region */
+/* @{ */
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"))) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+#else
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#else
+#error Toolchain not supported.
+#endif    
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -511,6 +549,24 @@ void SDK_Free(void *ptr);
     void DisableDeepSleepIRQ(IRQn_Type interrupt);
 #endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
 
+    /*!
+     * @brief Allocate memory with given alignment and aligned size.
+     *
+     * This is provided to support the dynamically allocated memory
+     * used in cache-able region.
+     * @param size The length required to malloc.
+     * @param alignbytes The alignment size.
+     * @retval The allocated memory.
+     */    
+    void *SDK_Malloc(size_t size, size_t alignbytes);
+    
+    /*!
+     * @brief Free memory.
+     *
+     * @param ptr The memory to be release.
+     */ 
+    void SDK_Free(void *ptr);    
+
 #if defined(__cplusplus)
 }
 #endif

bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.csi"
+#endif
+
+
 /* Two frame buffer loaded to CSI register at most. */
 #define CSI_MAX_ACTIVE_FRAME_NUM 2
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_csi.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_dcdc.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dcdc_1"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -330,13 +340,12 @@ void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regula
 void DCDC_BootIntoDCM(DCDC_Type *base)
 {
     base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
-    base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U) |
+    base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x4U) |
                  DCDC_REG2_DCM_SET_CTRL_MASK;
 }
 
 void DCDC_BootIntoCCM(DCDC_Type *base)
 {
     base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
-    base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U) |
-                 DCDC_REG2_DCM_SET_CTRL_MASK;
+    base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_dcdc.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dcp"
+#endif
+
+
 /*! Compile time sizeof() check */
 #define BUILD_ASSURE(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_dcp.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.dmamux"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_dmamux.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.edma"
+#endif
+
+
 #define EDMA_TRANSFER_ENABLED_MASK 0x80U
 
 /*******************************************************************************
@@ -711,8 +721,10 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
             */
             if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
             {
+                /* Clear the DREQ bits for the dynamic scatter gather */
+                tcdRegs->CSR |= DMA_CSR_DREQ_MASK;
                 /* Enable scatter/gather also in the TCD registers. */
-                csr = (tcdRegs->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
+                csr = tcdRegs->CSR | DMA_CSR_ESG_MASK;
                 /* Must write the CSR register one-time, because the transfer maybe finished anytime. */
                 tcdRegs->CSR = csr;
                 /*
@@ -727,6 +739,7 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
                 */
                 if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
                 {
+                    tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
                     return kStatus_Success;
                 }
                 /*

bsp/imxrt1052-evk/Libraries/drivers/fsl_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -52,7 +56,7 @@
 #define DMA_DCHPRI_INDEX(channel) (((channel) & ~0x03U) | (3 - ((channel)&0x03U)))
 
 /*! @brief Get the pointer of DCHPRIn */
-#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&(base->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
+#define DMA_DCHPRIn(base, channel) ((volatile uint8_t *)&((base)->DCHPRI3))[DMA_DCHPRI_INDEX(channel)]
 
 /*! @brief eDMA transfer configuration */
 typedef enum _edma_transfer_size
@@ -60,6 +64,7 @@ typedef enum _edma_transfer_size
     kEDMA_TransferSize1Bytes = 0x0U,  /*!< Source/Destination data transfer size is 1 byte every time */
     kEDMA_TransferSize2Bytes = 0x1U,  /*!< Source/Destination data transfer size is 2 bytes every time */
     kEDMA_TransferSize4Bytes = 0x2U,  /*!< Source/Destination data transfer size is 4 bytes every time */
+    kEDMA_TransferSize8Bytes = 0x3U,  /*!< Source/Destination data transfer size is 8 bytes every time */
     kEDMA_TransferSize16Bytes = 0x4U, /*!< Source/Destination data transfer size is 16 bytes every time */
     kEDMA_TransferSize32Bytes = 0x5U, /*!< Source/Destination data transfer size is 32 bytes every time */
 } edma_transfer_size_t;
@@ -242,7 +247,24 @@ typedef struct _edma_tcd
 /*! @brief Callback for eDMA */
 struct _edma_handle;
 
-/*! @brief Define callback function for eDMA. */
+/*! @brief Define callback function for eDMA.
+ *
+ * This callback function is called in the EDMA interrupt handle.
+ * In normal mode, run into callback function means the transfer users need is done.
+ * In scatter gather mode, run into callback function means a transfer control block (tcd) is finished. Not
+ * all transfer finished, users can get the finished tcd numbers using interface EDMA_GetUnusedTCDNumber.
+ *
+ * @param handle EDMA handle pointer, users shall not touch the values inside.
+ * @param userData The callback user paramter pointer. Users can use this paramter to involve things users need to
+ *                 change in EDMA callback function.
+ * @param transferDone If the current loaded transfer done. In normal mode it means if all transfer done. In scatter
+ *                     gather mode, this paramter shows is the current transfer block in EDMA regsiter is done. As the
+ *                     load of core is different, it will be different if the new tcd loaded into EDMA registers while
+ *                     this callback called. If true, it always means new tcd still not loaded into registers, while
+ *                     false means new tcd already loaded into registers.
+ * @param tcds How many tcds are done from the last callback. This parameter only used in scatter gather mode. It
+ *             tells user how many tcds are finished between the last callback and this.
+ */
 typedef void (*edma_callback)(struct _edma_handle *handle, void *userData, bool transferDone, uint32_t tcds);
 
 /*! @brief eDMA transfer handle structure */
@@ -702,7 +724,7 @@ static inline void EDMA_TriggerChannelStart(DMA_Type *base, uint32_t channel)
  * @brief Gets the remaining major loop count from the eDMA current channel TCD.
  *
  * This function checks the TCD (Task Control Descriptor) status for a specified
- * eDMA channel and returns the the number of major loop count that has not finished.
+ * eDMA channel and returns the number of major loop count that has not finished.
  *
  * @param base eDMA peripheral base address.
  * @param channel eDMA channel number.
@@ -774,7 +796,10 @@ void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel);
 /*!
  * @brief Installs the TCDs memory pool into the eDMA handle.
  *
- * This function is called after the EDMA_CreateHandle to use scatter/gather feature.
+ * This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
+ * while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
+ * (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
+ * Users need to preapre tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
  *
  * @param handle eDMA handle pointer.
  * @param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
@@ -786,7 +811,7 @@ void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t
  * @brief Installs a callback function for the eDMA transfer.
  *
  * This callback is called in the eDMA IRQ handler. Use the callback to do something after
- * the current major loop transfer completes.
+ * the current major loop transfer completes. This function will be called every time one tcd finished transfer.
  *
  * @param handle eDMA handle pointer.
  * @param callback eDMA callback function pointer.
@@ -824,8 +849,8 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
  * @brief Submits the eDMA transfer request.
  *
  * This function submits the eDMA transfer request according to the transfer configuration structure.
- * If submitting the transfer request repeatedly, this function packs an unprocessed request as
- * a TCD and enables scatter/gather feature to process it in the next time.
+ * In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
+ * The tcd pools is setup by call function EDMA_InstallTCDMemory before.
  *
  * @param handle eDMA handle pointer.
  * @param config Pointer to eDMA transfer configuration structure.

bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_elcdif.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.elcdif"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -286,10 +296,6 @@ status_t ELCDIF_UpdateLut(
     for (i = 0; i < count; i++)
     {
         *regLutData = lutData[i];
-
-        for (volatile uint32_t j = 0; j < 0x80; j++)
-        {
-        }
     }
 
     return kStatus_Success;

bsp/imxrt1052-evk/Libraries/drivers/fsl_elcdif.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,6 +37,12 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.enc"
+#endif
+
 #define ENC_CTRL_W1C_FLAGS (ENC_CTRL_HIRQ_MASK | ENC_CTRL_XIRQ_MASK | ENC_CTRL_DIRQ_MASK | ENC_CTRL_CMPIRQ_MASK)
 #define ENC_CTRL2_W1C_FLAGS (ENC_CTRL2_SABIRQ_MASK | ENC_CTRL2_ROIRQ_MASK | ENC_CTRL2_RUIRQ_MASK)
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_enc.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -303,6 +307,22 @@ void ENC_DoSoftwareLoadInitialPositionValue(ENC_Type *base);
  */
 void ENC_SetSelfTestConfig(ENC_Type *base, const enc_self_test_config_t *config);
 
+/*!
+ * @brief Enable watchdog for ENC module.
+ *
+ * @param base ENC peripheral base address
+ * @param enable Enables or disables the watchdog
+ */
+void ENC_EnableWatchdog(ENC_Type *base, bool enable);
+
+/*!
+ * @brief Set initial position value for ENC module.
+ *
+ * @param base ENC peripheral base address
+ * @param value Positive initial value
+ */
+void ENC_SetInitialPositionValue(ENC_Type *base, uint32_t value);
+
 /* @} */
 
 /*!

bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -36,6 +40,12 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.enet"
+#endif
+
 /*! @brief IPv4 PTP message IP version offset. */
 #define ENET_PTP1588_IPVERSION_OFFSET 0x0EU
 /*! @brief IPv4 PTP message UDP protocol offset. */
@@ -99,7 +109,9 @@
 /*! @brief NanoSecond in one second. */
 #define ENET_NANOSECOND_ONE_SECOND 1000000000U
 /*! @brief Define a common clock cycle delays used for time stamp capture. */
-#define ENET_1588TIME_DELAY_COUNT 38U
+#ifndef ENET_1588TIME_DELAY_COUNT
+#define ENET_1588TIME_DELAY_COUNT 10U
+#endif
 
 /*! @brief Defines the macro for converting constants from host byte order to network byte order. */
 #define ENET_HTONS(n) __REV16(n)
@@ -793,6 +805,12 @@ static void ENET_SetRxBufferDescriptors(enet_handle_t *handle, const enet_config
 #else
             rxBuffer = buffCfg->rxBufferAlign;
 #endif
+
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+            /* Invalidate rx buffers before DMA transfer data into them. */
+           DCACHE_InvalidateByRange((uint32_t)rxBuffer,  (buffCfg->rxBdNumber * rxBuffSizeAlign));
+#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
+
             for (count = 0; count < buffCfg->rxBdNumber; count++)
             {
                 /* Set data buffer and the length. */
@@ -1172,24 +1190,18 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
     else
     {
         /* A frame on one buffer or several receive buffers are both considered. */
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-        /* Add the cache invalidate maintain. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
         address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
 #else
         address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */        
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+        /* Add the cache invalidate maintain. */
         DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]);
-#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
-/* A frame on one buffer or several receive buffers are both considered. */
+#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */        
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         enet_ptp_time_data_t ptpTimestamp;
-        bool isPtpEventMessage = false;
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-        address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+        bool isPtpEventMessage = false;    
         /* Parse the PTP message according to the header message. */
         isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false);
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
@@ -1205,11 +1217,6 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
                 {
                     /* Copy the frame to user's buffer without FCS. */
                     len = curBuffDescrip->length - offset;
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                    address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                    address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
                     memcpy(data + offset, (void *)address, len);
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
                     /* Store the PTP 1588 timestamp for received PTP event frame. */
@@ -1240,11 +1247,7 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
                 {
                     break;
                 }
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+
                 memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[0]);
                 offset += handle->rxBuffSizeAlign[0];
 
@@ -1254,13 +1257,13 @@ status_t ENET_ReadFrame(ENET_Type *base, enet_handle_t *handle, uint8_t *data, u
 
             /* Get the current buffer descriptor. */
             curBuffDescrip = handle->rxBdCurrent[0];
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
             /* Add the cache invalidate maintain. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
             address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
 #else
             address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */            
+#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */                
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL        
             DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[0]);
 #endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
         }
@@ -1345,8 +1348,10 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-        
         memcpy((void *)address, data, length);
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+        DCACHE_CleanByRange(address, length);
+#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
         /* Set data length. */
         curBuffDescrip->length = length;
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -1372,15 +1377,6 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
         {
             handle->txBdCurrent[0]++;
         }
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-        /* Add the cache clean maintain. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-        address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-        DCACHE_CleanByRange(address, length);
-#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
         /* Active the transmit buffer descriptor. */
         ENET_ActiveSend(base, 0);
 
@@ -1414,15 +1410,19 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
             }
             /* update the size left to be transmit. */
             sizeleft = length - len;
+#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
+            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+#else
+            address = (uint32_t)curBuffDescrip->buffer;
+#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */            
             if (sizeleft > handle->txBuffSizeAlign[0])
             {
                 /* Data copy. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
                 memcpy((void *)address, data + len, handle->txBuffSizeAlign[0]);
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+                /* Add the cache clean maintain. */
+                DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
+#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
                 /* Data length update. */
                 curBuffDescrip->length = handle->txBuffSizeAlign[0];
                 len += handle->txBuffSizeAlign[0];
@@ -1434,24 +1434,15 @@ status_t ENET_SendFrame(ENET_Type *base, enet_handle_t *handle, const uint8_t *d
             }
             else
             {
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+
                 memcpy((void *)address, data + len, sizeleft);
-                curBuffDescrip->length = sizeleft;
-                /* Set Last buffer wrap flag. */
-                curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 /* Add the cache clean maintain. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-                DCACHE_CleanByRange(address, handle->txBuffSizeAlign[0]);
-#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */                 
+                DCACHE_CleanByRange(address, sizeleft);
+#endif  /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */ 
+                curBuffDescrip->length = sizeleft;
+                /* Set Last buffer wrap flag. */
+                curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;                
                 /* Active the transmit buffer descriptor. */
                 ENET_ActiveSend(base, 0);
 
@@ -1638,25 +1629,19 @@ status_t ENET_ReadFrameMultiRing(
     else
     {
         /* A frame on one buffer or several receive buffers are both considered. */
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-        /* Add the cache invalidate maintain. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
         address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
 #else
         address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+        /* Add the cache invalidate maintain. */
         DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]);
 #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
         enet_ptp_time_data_t ptpTimestamp;
         bool isPtpEventMessage = false;
-
         /* Parse the PTP message according to the header message. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-        address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
         isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimestamp, false);
 #endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
@@ -1671,11 +1656,6 @@ status_t ENET_ReadFrameMultiRing(
                 {
                     /* Copy the frame to user's buffer without FCS. */
                     len = curBuffDescrip->length - offset;
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                    address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                    address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
                     memcpy(data + offset, (void *)address, len);
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
                     /* Store the PTP 1588 timestamp for received PTP event frame. */
@@ -1706,11 +1686,6 @@ status_t ENET_ReadFrameMultiRing(
                 {
                     break;
                 }
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
                 memcpy(data + offset, (void *)address, handle->rxBuffSizeAlign[ringId]);
                 offset += handle->rxBuffSizeAlign[ringId];
 
@@ -1722,13 +1697,13 @@ status_t ENET_ReadFrameMultiRing(
             /* Get the current buffer descriptor. */
 
             curBuffDescrip = handle->rxBdCurrent[ringId];
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-            /* Add the cache invalidate maintain. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
             address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
 #else
             address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+            /* Add the cache invalidate maintain. */
             DCACHE_InvalidateByRange(address, handle->rxBuffSizeAlign[ringId]);
 #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
         }
@@ -1778,6 +1753,11 @@ status_t ENET_SendFrameMultiRing(
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
         memcpy((void *)address, data, length);
 
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+        /* Add the cache clean maintain. */
+        DCACHE_CleanByRange(address, length);
+#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
+
         /* Set data length. */
         curBuffDescrip->length = length;
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
@@ -1803,15 +1783,7 @@ status_t ENET_SendFrameMultiRing(
         {
             handle->txBdCurrent[ringId]++;
         }
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-        /* Add the cache clean maintain. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-        address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-        address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-        DCACHE_CleanByRange(address, length);
-#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
+
         /* Active the transmit buffer descriptor. */
         ENET_ActiveSend(base, ringId);
 
@@ -1845,53 +1817,41 @@ status_t ENET_SendFrameMultiRing(
             }
             /* update the size left to be transmit. */
             sizeleft = length - len;
-            if (sizeleft > handle->txBuffSizeAlign[ringId])
-            {
-                /* Data copy. */
 #if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
+            address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
 #else
-                address = (uint32_t)curBuffDescrip->buffer;
+            address = (uint32_t)curBuffDescrip->buffer;
 #endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+            if (sizeleft > handle->txBuffSizeAlign[ringId])
+            {
+                /* Data copy. */
                 memcpy((void*)address, data + len, handle->txBuffSizeAlign[ringId]);
+#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+                /* Add the cache clean maintain. */
+                DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]);
+#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
                 /* Data length update. */
                 curBuffDescrip->length = handle->txBuffSizeAlign[ringId];
                 len += handle->txBuffSizeAlign[ringId];
                 /* Sets the control flag. */
                 curBuffDescrip->control &= ~ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
                 curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK;
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-                /* Add the cache clean maintain. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
-                DCACHE_CleanByRange(address, handle->txBuffSizeAlign[ringId]);
-#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
+
                 /* Active the transmit buffer descriptor*/
                 ENET_ActiveSend(base, ringId);
             }
             else
             {
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
+
                 memcpy((void *)address, data + len, sizeleft);
-                curBuffDescrip->length = sizeleft;
-                /* Set Last buffer wrap flag. */
-                curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
 #if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
                 /* Add the cache clean maintain. */
-#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
-                address = MEMORY_ConvertMemoryMapAddress((uint32_t)curBuffDescrip->buffer,kMEMORY_DMA2Local);
-#else
-                address = (uint32_t)curBuffDescrip->buffer;
-#endif /* FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET */
                 DCACHE_CleanByRange(address, sizeleft);
 #endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
+                curBuffDescrip->length = sizeleft;
+                /* Set Last buffer wrap flag. */
+                curBuffDescrip->control |= ENET_BUFFDESCRIPTOR_TX_READY_MASK | ENET_BUFFDESCRIPTOR_TX_LAST_MASK;
+
                 /* Active the transmit buffer descriptor. */
                 ENET_ActiveSend(base, ringId);
 
@@ -1900,9 +1860,6 @@ status_t ENET_SendFrameMultiRing(
 
             /* Get the current buffer descriptor address. */
             curBuffDescrip = handle->txBdCurrent[ringId];
-#if defined(FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL) && FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
-/* Add the cache invalidate maintain. */
-#endif /* FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL */
         } while (!(curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK));
 
         return kStatus_ENET_TxFrameBusy;
@@ -2155,7 +2112,7 @@ static bool ENET_Ptp1588ParseFrame(const uint8_t *data, enet_ptp_time_data_t *pt
     switch (ENET_HTONS(ptpType))
     { /* Ethernet layer 2. */
         case ENET_ETHERNETL2:
-            if (*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) <= kENET_PtpEventMsgType)
+            if ((*(uint8_t *)(buffer + ENET_PTP1588_ETHL2_MSGTYPE_OFFSET) & 0x0F) <= kENET_PtpEventMsgType)
             {
                 isPtpMsg = true;
                 if (!isFastEnabled)
@@ -2488,6 +2445,7 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
     isPtpEventMessage = ENET_Ptp1588ParseFrame((uint8_t *)address, &ptpTimeData, false);
     if (isPtpEventMessage)
     {
+         /* Only store tx timestamp for ptp event message. */  
         do
         {
             /* Increase current buffer descriptor to the next one. */
@@ -2523,6 +2481,9 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
                     ptpTimeData.timeStamp.second = handle->msTimerSecond - 1;
                 }
 
+                /* Save transmit time stamp nanosecond. */
+                ptpTimeData.timeStamp.nanosecond = curBuffDescrip->timestamp;
+
                 /* Enable the interrupt. */
                 EnableGlobalIRQ(primask);
 
@@ -2533,7 +2494,6 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
             /* Get the current transmit buffer descriptor. */
             curBuffDescrip = handle->txBdDirtyTime[ringId];
 
-
             /* Get the control status data, If the buffer descriptor has not been processed break out. */
             if (curBuffDescrip->control & ENET_BUFFDESCRIPTOR_TX_READY_MASK)
             {
@@ -2542,6 +2502,18 @@ static status_t ENET_StoreTxFrameTime(ENET_Type *base, enet_handle_t *handle, ui
         } while (handle->txBdDirtyTime[ringId] != handle->txBdCurrent[ringId]);
         return kStatus_ENET_TxFrameFail;
     }
+    else
+    {
+        /* Only increase current buffer descriptor to the next one. */
+        if (handle->txBdDirtyTime[ringId]->control & ENET_BUFFDESCRIPTOR_TX_WRAP_MASK)
+        {
+            handle->txBdDirtyTime[ringId] = handle->txBdBase[ringId];
+        }
+        else
+        {
+            handle->txBdDirtyTime[ringId]++;
+        } 
+    }
     return kStatus_Success;
 }
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_enet.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,7 +50,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief Defines the driver version. */
-#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
+#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 2, 3)) /*!< Version 2.2.3. */
 /*@}*/
 
 /*! @name ENET DESCRIPTOR QUEUE */
@@ -194,7 +198,7 @@ typedef enum _enet_mii_mode
  *
  * Notice: "kENET_MiiSpeed1000M" only supported when mii mode is "kENET_RgmiiMode".
  */
-typedef enum _enet_mii_speed 
+typedef enum _enet_mii_speed
 {
     kENET_MiiSpeed10M = 0U,  /*!< Speed 10 Mbps. */
     kENET_MiiSpeed100M = 1U, /*!< Speed 100 Mbps. */
@@ -204,21 +208,21 @@ typedef enum _enet_mii_speed
 } enet_mii_speed_t;
 
 /*! @brief Defines the half or full duplex for the MII data interface. */
-typedef enum _enet_mii_duplex 
+typedef enum _enet_mii_duplex
 {
     kENET_MiiHalfDuplex = 0U, /*!< Half duplex mode. */
     kENET_MiiFullDuplex       /*!< Full duplex mode. */
 } enet_mii_duplex_t;
 
 /*! @brief Define the MII opcode for normal MDIO_CLAUSES_22 Frame. */
-typedef enum _enet_mii_write 
+typedef enum _enet_mii_write
 {
     kENET_MiiWriteNoCompliant = 0U, /*!< Write frame operation, but not MII-compliant. */
     kENET_MiiWriteValidFrame        /*!< Write frame operation for a valid MII management frame. */
 } enet_mii_write_t;
 
 /*! @brief Defines the read operation for the MII management frame. */
-typedef enum _enet_mii_read 
+typedef enum _enet_mii_read
 {
     kENET_MiiReadValidFrame = 2U, /*!< Read frame operation for a valid MII management frame. */
     kENET_MiiReadNoCompliant = 3U /*!< Read frame operation, but not MII-compliant. */
@@ -226,7 +230,8 @@ typedef enum _enet_mii_read
 
 #if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
 /*! @brief Define the MII opcode for extended MDIO_CLAUSES_45 Frame. */
-typedef enum _enet_mii_extend_opcode {
+typedef enum _enet_mii_extend_opcode
+{
     kENET_MiiAddrWrite_C45 = 0U,  /*!< Address Write operation. */
     kENET_MiiWriteFrame_C45 = 1U, /*!< Write frame operation for a valid MII management frame. */
     kENET_MiiReadFrame_C45 = 3U   /*!< Read frame operation for a valid MII management frame. */
@@ -245,7 +250,7 @@ typedef enum _enet_mii_extend_opcode {
  * configure rxFifoFullThreshold and txFifoWatermark
  * in the enet_config_t.
  */
-typedef enum _enet_special_control_flag 
+typedef enum _enet_special_control_flag
 {
     kENET_ControlFlowControlEnable = 0x0001U,       /*!< Enable ENET flow control: pause frame. */
     kENET_ControlRxPayloadCheckEnable = 0x0002U,    /*!< Enable ENET receive payload length check. */
@@ -268,7 +273,7 @@ typedef enum _enet_special_control_flag
  * members. Members usually map to interrupt enable bits in one or more
  * peripheral registers.
  */
-typedef enum _enet_interrupt_enable 
+typedef enum _enet_interrupt_enable
 {
     kENET_BabrInterrupt = ENET_EIR_BABR_MASK,        /*!< Babbling receive error interrupt source */
     kENET_BabtInterrupt = ENET_EIR_BABT_MASK,        /*!< Babbling transmit error interrupt source */
@@ -302,7 +307,7 @@ typedef enum _enet_interrupt_enable
 } enet_interrupt_enable_t;
 
 /*! @brief Defines the common interrupt event for callback use. */
-typedef enum _enet_event 
+typedef enum _enet_event
 {
     kENET_RxEvent,            /*!< Receive event. */
     kENET_TxEvent,            /*!< Transmit event. */
@@ -314,7 +319,7 @@ typedef enum _enet_event
 
 #if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
 /*! @brief Defines certain idle slope for bandwidth fraction. */
-typedef enum _enet_idle_slope 
+typedef enum _enet_idle_slope
 {
     kENET_IdleSlope1 = 1U,       /*!< The bandwidth fraction is about 0.002. */
     kENET_IdleSlope2 = 2U,       /*!< The bandwidth fraction is about 0.003. */
@@ -339,7 +344,7 @@ typedef enum _enet_idle_slope
 #endif /* FSL_FEATURE_ENET_HAS_AVB */
 
 /*! @brief Defines the transmit accelerator configuration. */
-typedef enum _enet_tx_accelerator 
+typedef enum _enet_tx_accelerator
 {
     kENET_TxAccelIsShift16Enabled = ENET_TACC_SHIFT16_MASK, /*!< Transmit FIFO shift-16. */
     kENET_TxAccelIpCheckEnabled = ENET_TACC_IPCHK_MASK,     /*!< Insert IP header checksum. */
@@ -347,7 +352,7 @@ typedef enum _enet_tx_accelerator
 } enet_tx_accelerator_t;
 
 /*! @brief Defines the receive accelerator configuration. */
-typedef enum _enet_rx_accelerator 
+typedef enum _enet_rx_accelerator
 {
     kENET_RxAccelPadRemoveEnabled = ENET_RACC_PADREM_MASK,  /*!< Padding removal for short IP frames. */
     kENET_RxAccelIpCheckEnabled = ENET_RACC_IPDIS_MASK,     /*!< Discard with wrong IP header checksum. */
@@ -358,7 +363,7 @@ typedef enum _enet_rx_accelerator
 
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
 /*! @brief Defines the ENET PTP message related constant. */
-typedef enum _enet_ptp_event_type 
+typedef enum _enet_ptp_event_type
 {
     kENET_PtpEventMsgType = 3U,  /*!< PTP event message type. */
     kENET_PtpSrcPortIdLen = 10U, /*!< PTP message sequence id length. */
@@ -367,7 +372,7 @@ typedef enum _enet_ptp_event_type
 } enet_ptp_event_type_t;
 
 /*! @brief Defines the IEEE 1588 PTP timer channel numbers. */
-typedef enum _enet_ptp_timer_channel 
+typedef enum _enet_ptp_timer_channel
 {
     kENET_PtpTimerChannel1 = 0U, /*!< IEEE 1588 PTP timer Channel 1. */
     kENET_PtpTimerChannel2,      /*!< IEEE 1588 PTP timer Channel 2. */
@@ -481,14 +486,16 @@ typedef struct _enet_data_error_stats
  */
 typedef struct _enet_buffer_config
 {
-    uint16_t rxBdNumber;                              /*!< Receive buffer descriptor number. */
-    uint16_t txBdNumber;                              /*!< Transmit buffer descriptor number. */
-    uint32_t rxBuffSizeAlign;                         /*!< Aligned receive data buffer size. */
-    uint32_t txBuffSizeAlign;                         /*!< Aligned transmit data buffer size. */
-    volatile enet_rx_bd_struct_t *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */
-    volatile enet_tx_bd_struct_t *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */
-    uint8_t *rxBufferAlign;                           /*!< Receive data buffer start address. */
-    uint8_t *txBufferAlign;                           /*!< Transmit data buffer start address. */
+    uint16_t rxBdNumber;      /*!< Receive buffer descriptor number. */
+    uint16_t txBdNumber;      /*!< Transmit buffer descriptor number. */
+    uint32_t rxBuffSizeAlign; /*!< Aligned receive data buffer size. */
+    uint32_t txBuffSizeAlign; /*!< Aligned transmit data buffer size. */
+    volatile enet_rx_bd_struct_t
+        *rxBdStartAddrAlign; /*!< Aligned receive buffer descriptor start address: should be non-cacheable. */
+    volatile enet_tx_bd_struct_t
+        *txBdStartAddrAlign; /*!< Aligned transmit buffer descriptor start address: should be non-cacheable. */
+    uint8_t *rxBufferAlign;  /*!< Receive data buffer start address. */
+    uint8_t *txBufferAlign;  /*!< Transmit data buffer start address. */
 } enet_buffer_config_t;
 
 #ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE

bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_ewm.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.ewm"
+#endif
+
+
 /*******************************************************************************
  * Code
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_ewm.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -31,10 +35,14 @@
 #include "fsl_flexcan.h"
 
 /*******************************************************************************
- * Definitons
+ * Definitions
  ******************************************************************************/
 
-#define FLEXCAN_TIME_QUANTA_NUM (10)
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcan"
+#endif
+
 
 /*! @brief FlexCAN Internal State. */
 enum _flexcan_state
@@ -80,14 +88,6 @@ typedef void (*flexcan_isr_t)(CAN_Type *base, flexcan_handle_t *handle);
  * Prototypes
  ******************************************************************************/
 
-/*!
- * @brief Get the FlexCAN instance from peripheral base address.
- *
- * @param base FlexCAN peripheral base address.
- * @return FlexCAN instance.
- */
-uint32_t FLEXCAN_GetInstance(CAN_Type *base);
-
 /*!
  * @brief Enter FlexCAN Freeze Mode.
  *
@@ -159,8 +159,12 @@ static void FLEXCAN_Reset(CAN_Type *base);
  * @param base FlexCAN peripheral base address.
  * @param sourceClock_Hz Source Clock in Hz.
  * @param baudRate_Bps Baud Rate in Bps.
+ * @param timingConfig FlexCAN timingConfig.
  */
-static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps);
+static void FLEXCAN_SetBaudRate(CAN_Type *base,
+                                uint32_t sourceClock_Hz,
+                                uint32_t baudRate_Bps,
+                                flexcan_timing_config_t timingConfig);
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
 /*!
@@ -171,8 +175,24 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_
  * @param base FlexCAN peripheral base address.
  * @param sourceClock_Hz Source Clock in Hz.
  * @param baudRateFD_Bps FD frame Baud Rate in Bps.
+ * @param timingConfig FlexCAN timingConfig.
  */
-static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps);
+static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps, flexcan_timing_config_t timingConfig);
+
+/*!
+ * @brief Get Mailbox offset number by dword.
+ *
+ * This function gets the offset number of the specified mailbox.
+ * Mailbox is not consecutive between memory regions when payload is not 8 bytes
+ * so need to calculate the specified mailbox address.
+ * For example, in the first memory region, MB[0].CS address is 0x4002_4080. For 32 bytes
+ * payload frame, the second mailbox is ((1/12)*512 + 1%12*40)/4 = 10, meaning 10 dword
+ * after the 0x4002_4080, which is actually the address of mailbox MB[1].CS.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @param mbIdx Mailbox index.
+ */
+static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx);
 #endif
 
 /*******************************************************************************
@@ -230,6 +250,7 @@ uint32_t FLEXCAN_GetInstance(CAN_Type *base)
 static void FLEXCAN_EnterFreezeMode(CAN_Type *base)
 {
     /* Set Freeze, Halt bits. */
+    base->MCR |= CAN_MCR_FRZ_MASK;
     base->MCR |= CAN_MCR_HALT_MASK;
 
     /* Wait until the FlexCAN Module enter freeze mode. */
@@ -242,6 +263,7 @@ static void FLEXCAN_ExitFreezeMode(CAN_Type *base)
 {
     /* Clear Freeze, Halt bits. */
     base->MCR &= ~CAN_MCR_HALT_MASK;
+    base->MCR &= ~CAN_MCR_FRZ_MASK;
 
     /* Wait until the FlexCAN Module exit freeze mode. */
     while (base->MCR & CAN_MCR_FRZACK_MASK)
@@ -405,14 +427,20 @@ static void FLEXCAN_Reset(CAN_Type *base)
     }
 }
 
-static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRate_Bps)
+static void FLEXCAN_SetBaudRate(CAN_Type *base,
+                                uint32_t sourceClock_Hz,
+                                uint32_t baudRate_Bps,
+                                flexcan_timing_config_t timingConfig)
 {
-    flexcan_timing_config_t timingConfig;
-    uint32_t priDiv = baudRate_Bps * FLEXCAN_TIME_QUANTA_NUM;
+    /* FlexCAN timing setting formula:
+     * quantum = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1);
+     */
+    uint32_t quantum = 1 + (timingConfig.phaseSeg1 + 1) + (timingConfig.phaseSeg2 + 1) + (timingConfig.propSeg + 1);
+    uint32_t priDiv = baudRate_Bps * quantum;
 
     /* Assertion: Desired baud rate is too high. */
     assert(baudRate_Bps <= 1000000U);
-    /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */
+    /* Assertion: Source clock should greater than baud rate * quantum. */
     assert(priDiv <= sourceClock_Hz);
 
     if (0 == priDiv)
@@ -428,27 +456,26 @@ static void FLEXCAN_SetBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_
         priDiv = 0xFF;
     }
 
-    /* FlexCAN timing setting formula:
-     * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1);
-     */
     timingConfig.preDivider = priDiv;
-    timingConfig.phaseSeg1 = 3;
-    timingConfig.phaseSeg2 = 2;
-    timingConfig.propSeg = 1;
-    timingConfig.rJumpwidth = 1;
 
     /* Update actual timing characteristic. */
     FLEXCAN_SetTimingConfig(base, &timingConfig);
 }
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint32_t baudRateFD_Bps)
+static void FLEXCAN_SetFDBaudRate(CAN_Type *base,
+                                  uint32_t sourceClock_Hz,
+                                  uint32_t baudRateFD_Bps,
+                                  flexcan_timing_config_t timingConfig)
 {
-    flexcan_timing_config_t timingConfig;
-    uint32_t priDiv = baudRateFD_Bps * FLEXCAN_TIME_QUANTA_NUM;
+    /* FlexCAN FD timing setting formula:
+     * quantum = 1 + (FPSEG1 + 1) + (FPSEG2 + 1) + FPROPSEG;
+     */
+    uint32_t quantum = 1 + (timingConfig.fphaseSeg1 + 1) + (timingConfig.fphaseSeg2 + 1) + timingConfig.fpropSeg;
+    uint32_t priDiv = baudRateFD_Bps * quantum;
 
     /* Assertion: Desired baud rate is too high. */
-    assert(baudRateFD_Bps <= 1000000U);
+    assert(baudRateFD_Bps <= 8000000U);
     /* Assertion: Source clock should greater than baud rate * FLEXCAN_TIME_QUANTA_NUM. */
     assert(priDiv <= sourceClock_Hz);
 
@@ -465,14 +492,7 @@ static void FLEXCAN_SetFDBaudRate(CAN_Type *base, uint32_t sourceClock_Hz, uint3
         priDiv = 0xFF;
     }
 
-    /* FlexCAN timing setting formula:
-     * FLEXCAN_TIME_QUANTA_NUM = 1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1);
-     */
-    timingConfig.preDivider = priDiv;
-    timingConfig.phaseSeg1 = 3;
-    timingConfig.phaseSeg2 = 2;
-    timingConfig.propSeg = 1;
-    timingConfig.rJumpwidth = 1;
+    timingConfig.fpreDivider = priDiv;
 
     /* Update actual timing characteristic. */
     FLEXCAN_SetFDTimingConfig(base, &timingConfig);
@@ -541,9 +561,9 @@ void FLEXCAN_Init(CAN_Type *base, const flexcan_config_t *config, uint32_t sourc
     base->MCR = mcrTemp;
 
     /* Baud Rate Configuration.*/
-    FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate);
+    FLEXCAN_SetBaudRate(base, sourceClock_Hz, config->baudRate, config->timingConfig);
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
-    FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD);
+    FLEXCAN_SetFDBaudRate(base, sourceClock_Hz, config->baudRateFD, config->timingConfig);
 #endif
 }
 
@@ -588,6 +608,17 @@ void FLEXCAN_GetDefaultConfig(flexcan_config_t *config)
     config->enableIndividMask = false;
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
     config->enableDoze = false;
+#endif
+    /* Default protocol timing configuration, time quantum is 10. */
+    config->timingConfig.phaseSeg1 = 3;
+    config->timingConfig.phaseSeg2 = 2;
+    config->timingConfig.propSeg = 1;
+    config->timingConfig.rJumpwidth = 1;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+    config->timingConfig.fphaseSeg1 = 3;
+    config->timingConfig.fphaseSeg2 = 3;
+    config->timingConfig.fpropSeg = 1;
+    config->timingConfig.frJumpwidth = 1;
 #endif
 }
 
@@ -606,6 +637,15 @@ void FLEXCAN_FDEnable(CAN_Type *base, flexcan_mb_size_t dataSize, bool brs)
     FLEXCAN_EnterFreezeMode(base);
     base->MCR |= CAN_MCR_FDEN_MASK;
     base->FDCTRL |= CAN_FDCTRL_MBDSR0(dataSize);
+#if defined(CAN_FDCTRL_MBDSR1_MASK)
+    base->FDCTRL |= CAN_FDCTRL_MBDSR1(dataSize);
+#endif
+#if defined(CAN_FDCTRL_MBDSR2_MASK)
+    base->FDCTRL |= CAN_FDCTRL_MBDSR2(dataSize);
+#endif
+#if defined(CAN_FDCTRL_MBDSR3_MASK)
+    base->FDCTRL |= CAN_FDCTRL_MBDSR3(dataSize);
+#endif
     /* Exit Freeze Mode. */
     FLEXCAN_ExitFreezeMode(base);
 }
@@ -652,14 +692,15 @@ void FLEXCAN_SetFDTimingConfig(CAN_Type *base, const flexcan_timing_config_t *co
     /* Enter Freeze Mode. */
     FLEXCAN_EnterFreezeMode(base);
 
+    base->CBT |= CAN_CBT_BTF(1);
     /* Cleaning previous Timing Setting. */
     base->FDCBT &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FRJW_MASK | CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK |
                      CAN_FDCBT_FPROPSEG_MASK);
 
     /* Updating Timing Setting according to configuration structure. */
-    base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->preDivider) | CAN_FDCBT_FRJW(config->rJumpwidth) |
-                    CAN_FDCBT_FPSEG1(config->phaseSeg1) | CAN_FDCBT_FPSEG2(config->phaseSeg2) |
-                    CAN_FDCBT_FPROPSEG(config->propSeg));
+    base->FDCBT |= (CAN_FDCBT_FPRESDIV(config->fpreDivider) | CAN_FDCBT_FRJW(config->frJumpwidth) |
+                    CAN_FDCBT_FPSEG1(config->fphaseSeg1) | CAN_FDCBT_FPSEG2(config->fphaseSeg2) |
+                    CAN_FDCBT_FPROPSEG(config->fpropSeg));
 
     /* Exit Freeze Mode. */
     FLEXCAN_ExitFreezeMode(base);
@@ -728,6 +769,35 @@ void FLEXCAN_SetTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
     base->MB[mbIdx].WORD1 = 0x0;
 }
 
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+static uint32_t FLEXCAN_GetFDMailboxOffset(CAN_Type *base, uint8_t mbIdx)
+{
+    uint32_t dataSize;
+    uint32_t offset = 0;
+    dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+    switch (dataSize)
+    {
+        case kFLEXCAN_8BperMB:
+            offset = (mbIdx / 32) * 512 + mbIdx % 32 * 16;
+            break;
+        case kFLEXCAN_16BperMB:
+            offset = (mbIdx / 21) * 512 + mbIdx % 21 * 24;
+            break;
+        case kFLEXCAN_32BperMB:
+            offset = (mbIdx / 12) * 512 + mbIdx % 12 * 40;
+            break;
+        case kFLEXCAN_64BperMB:
+            offset = (mbIdx / 7) * 512 + mbIdx % 7 * 72;
+            break;
+        default:
+            break;
+    }
+    /* To get the dword aligned offset, need to divide by 4. */
+    offset = offset / 4;
+    return offset;
+}
+#endif
+
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
 void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
 {
@@ -735,85 +805,44 @@ void FLEXCAN_SetFDTxMbConfig(CAN_Type *base, uint8_t mbIdx, bool enable)
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
     uint8_t cnt = 0;
+    uint8_t payload_dword = 1;
     uint32_t dataSize;
     dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+    volatile uint32_t *mbAddr = &(base->MB[0].CS);
+    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+    uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base));
+#endif
 
     /* Inactivate Message Buffer. */
     if (enable)
     {
-        switch (dataSize)
-        {
-            case kFLEXCAN_8BperMB:
-                base->MB_8B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                break;
-            case kFLEXCAN_16BperMB:
-                base->MB_16B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                break;
-            case kFLEXCAN_32BperMB:
-                base->MB_32B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                break;
-            case kFLEXCAN_64BperMB:
-                base->MB_64B[mbIdx].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                break;
-            default:
-                break;
-        }
+        /* Inactivate by writing CS. */
+        mbAddr[offset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
     }
     else
     {
-        switch (dataSize)
-        {
-            case kFLEXCAN_8BperMB:
-                base->MB_8B[mbIdx].CS = 0;
-                break;
-            case kFLEXCAN_16BperMB:
-                base->MB_16B[mbIdx].CS = 0;
-                break;
-            case kFLEXCAN_32BperMB:
-                base->MB_32B[mbIdx].CS = 0;
-                break;
-            case kFLEXCAN_64BperMB:
-                base->MB_64B[mbIdx].CS = 0;
-                break;
-            default:
-                break;
-        }
+        mbAddr[offset] = 0x0;
     }
 
-    /* Clean ID and Message Buffer content. */
-    switch (dataSize)
+    /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
+       Bytes payload. */
+    for (cnt = 0; cnt < dataSize + 1; cnt++)
     {
-        case kFLEXCAN_8BperMB:
-            base->MB_8B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 2; cnt++)
-            {
-                base->MB_8B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        case kFLEXCAN_16BperMB:
-            base->MB_16B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 4; cnt++)
-            {
-                base->MB_16B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        case kFLEXCAN_32BperMB:
-            base->MB_32B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 8; cnt++)
-            {
-                base->MB_32B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        case kFLEXCAN_64BperMB:
-            base->MB_64B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 16; cnt++)
-            {
-                base->MB_64B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        default:
-            break;
+        payload_dword *= 2;
+    }
+
+    /* Clean ID. */
+    mbAddr[offset + 1] = 0x0;
+    /* Clean Message Buffer content, DWORD by DWORD. */
+    for (cnt = 0; cnt < payload_dword; cnt++)
+    {
+        mbAddr[offset + 2 + cnt] = 0x0;
     }
+
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+    mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+#endif
 }
 #endif
 
@@ -867,68 +896,22 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_
 
     uint32_t cs_temp = 0;
     uint8_t cnt = 0;
-    uint32_t dataSize;
-    dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+    volatile uint32_t *mbAddr = &(base->MB[0].CS);
+    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
 
-    /* Inactivate Message Buffer and clean ID, Message Buffer content. */
-    switch (dataSize)
+    /* Inactivate all mailboxes first, clean ID and Message Buffer content. */
+    for (cnt = 0; cnt < FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(base); cnt++)
     {
-        case kFLEXCAN_8BperMB:
-            base->MB_8B[mbIdx].CS = 0;
-            base->MB_8B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 2; cnt++)
-            {
-                base->MB_8B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        case kFLEXCAN_16BperMB:
-            base->MB_16B[mbIdx].CS = 0;
-            base->MB_16B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 4; cnt++)
-            {
-                base->MB_16B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        case kFLEXCAN_32BperMB:
-            base->MB_32B[mbIdx].CS = 0;
-            base->MB_32B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 8; cnt++)
-            {
-                base->MB_32B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        case kFLEXCAN_64BperMB:
-            base->MB_64B[mbIdx].CS = 0;
-            base->MB_64B[mbIdx].ID = 0x0;
-            for (cnt = 0; cnt < 16; cnt++)
-            {
-                base->MB_64B[mbIdx].WORD[cnt] = 0x0;
-            }
-            break;
-        default:
-            break;
+       base->MB[cnt].CS = 0;
+       base->MB[cnt].ID = 0;
+       base->MB[cnt].WORD0 = 0;
+       base->MB[cnt].WORD1 = 0;
     }
 
     if (enable)
     {
         /* Setup Message Buffer ID. */
-        switch (dataSize)
-        {
-            case kFLEXCAN_8BperMB:
-                base->MB_8B[mbIdx].ID = config->id;
-                break;
-            case kFLEXCAN_16BperMB:
-                base->MB_16B[mbIdx].ID = config->id;
-                break;
-            case kFLEXCAN_32BperMB:
-                base->MB_32B[mbIdx].ID = config->id;
-                break;
-            case kFLEXCAN_64BperMB:
-                base->MB_64B[mbIdx].ID = config->id;
-                break;
-            default:
-                break;
-        }
+        mbAddr[offset + 1] = config->id;
 
         /* Setup Message Buffer format. */
         if (kFLEXCAN_FrameFormatExtend == config->format)
@@ -938,23 +921,7 @@ void FLEXCAN_SetFDRxMbConfig(CAN_Type *base, uint8_t mbIdx, const flexcan_rx_mb_
 
         /* Activate Rx Message Buffer. */
         cs_temp |= CAN_CS_CODE(kFLEXCAN_RxMbEmpty);
-        switch (dataSize)
-        {
-            case kFLEXCAN_8BperMB:
-                base->MB_8B[mbIdx].CS = cs_temp;
-                break;
-            case kFLEXCAN_16BperMB:
-                base->MB_16B[mbIdx].CS = cs_temp;
-                break;
-            case kFLEXCAN_32BperMB:
-                base->MB_32B[mbIdx].CS = cs_temp;
-                break;
-            case kFLEXCAN_64BperMB:
-                base->MB_64B[mbIdx].CS = cs_temp;
-                break;
-            default:
-                break;
-        }
+        mbAddr[offset] = cs_temp;
     }
 }
 #endif
@@ -1152,57 +1119,27 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra
     /* Assertion. */
     assert(mbIdx <= (base->MCR & CAN_MCR_MAXMB_MASK));
     assert(txFrame);
-    assert(txFrame->length <= 15);
     assert(!FLEXCAN_IsMbOccupied(base, mbIdx));
 
     uint32_t cs_temp = 0;
     uint8_t cnt = 0;
     uint32_t can_cs = 0;
+    uint8_t payload_dword = 1;
     uint32_t dataSize;
     dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
+    uint32_t availoffset = FLEXCAN_GetFDMailboxOffset(base, FLEXCAN_GetFirstValidMb(base));
+#endif
+    volatile uint32_t *mbAddr = &(base->MB[0].CS);
+    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
 
-    switch (dataSize)
-    {
-        case kFLEXCAN_8BperMB:
-            can_cs = base->MB_8B[mbIdx].CS;
-            break;
-        case kFLEXCAN_16BperMB:
-            can_cs = base->MB_16B[mbIdx].CS;
-            break;
-        case kFLEXCAN_32BperMB:
-            can_cs = base->MB_32B[mbIdx].CS;
-            break;
-        case kFLEXCAN_64BperMB:
-            can_cs = base->MB_64B[mbIdx].CS;
-            break;
-        default:
-            break;
-    }
+    can_cs = mbAddr[0];
     /* Check if Message Buffer is available. */
     if (CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) != (can_cs & CAN_CS_CODE_MASK))
     {
         /* Inactive Tx Message Buffer and Fill Message ID field. */
-        switch (dataSize)
-        {
-            case kFLEXCAN_8BperMB:
-                base->MB_8B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                base->MB_8B[mbIdx].ID = txFrame->id;
-                break;
-            case kFLEXCAN_16BperMB:
-                base->MB_16B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                base->MB_16B[mbIdx].ID = txFrame->id;
-                break;
-            case kFLEXCAN_32BperMB:
-                base->MB_32B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                base->MB_32B[mbIdx].ID = txFrame->id;
-                break;
-            case kFLEXCAN_64BperMB:
-                base->MB_64B[mbIdx].CS = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-                base->MB_64B[mbIdx].ID = txFrame->id;
-                break;
-            default:
-                break;
-        }
+        mbAddr[offset] = (can_cs & ~CAN_CS_CODE_MASK) | CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+        mbAddr[offset + 1] = txFrame->id;
 
         /* Fill Message Format field. */
         if (kFLEXCAN_FrameFormatExtend == txFrame->format)
@@ -1212,44 +1149,23 @@ status_t FLEXCAN_WriteFDTxMb(CAN_Type *base, uint8_t mbIdx, const flexcan_fd_fra
 
         cs_temp |= CAN_CS_CODE(kFLEXCAN_TxMbDataOrRemote) | CAN_CS_DLC(txFrame->length) | CAN_CS_EDL(1);
 
+        /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
+           Bytes payload. */
+        for (cnt = 0; cnt < dataSize + 1; cnt++)
+        {
+            payload_dword *= 2;
+        }
+
         /* Load Message Payload and Activate Tx Message Buffer. */
-        switch (dataSize)
+        for (cnt = 0; cnt < payload_dword; cnt++)
         {
-            case kFLEXCAN_8BperMB:
-                for (cnt = 0; cnt < 2; cnt++)
-                {
-                    base->MB_8B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt];
-                }
-                base->MB_8B[mbIdx].CS = cs_temp;
-                break;
-            case kFLEXCAN_16BperMB:
-                for (cnt = 0; cnt < 4; cnt++)
-                {
-                    base->MB_16B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt];
-                }
-                base->MB_16B[mbIdx].CS = cs_temp;
-                break;
-            case kFLEXCAN_32BperMB:
-                for (cnt = 0; cnt < 8; cnt++)
-                {
-                    base->MB_32B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt];
-                }
-                base->MB_32B[mbIdx].CS = cs_temp;
-                break;
-            case kFLEXCAN_64BperMB:
-                for (cnt = 0; cnt < 16; cnt++)
-                {
-                    base->MB_64B[mbIdx].WORD[cnt] = txFrame->dataWord[cnt];
-                }
-                base->MB_64B[mbIdx].CS = cs_temp;
-                break;
-            default:
-                break;
+            mbAddr[offset + 2 + cnt] = txFrame->dataWord[cnt];
         }
+        mbAddr[offset] = cs_temp;
 
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641) && FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641)
-        base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
-        base->MB[FLEXCAN_GetFirstValidMb(base)].CS = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+        mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
+        mbAddr[availoffset] = CAN_CS_CODE(kFLEXCAN_TxMbInactive);
 #endif
 
         return kStatus_Success;
@@ -1331,30 +1247,14 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r
     uint32_t can_id = 0;
     uint32_t dataSize;
     dataSize = (base->FDCTRL & CAN_FDCTRL_MBDSR0_MASK) >> CAN_FDCTRL_MBDSR0_SHIFT;
-    cs_temp = base->MB[mbIdx].CS;
+    uint8_t payload_dword = 1;
+    volatile uint32_t *mbAddr = &(base->MB[0].CS);
+    uint32_t offset = FLEXCAN_GetFDMailboxOffset(base, mbIdx);
 
     /* Read CS field of Rx Message Buffer to lock Message Buffer. */
-    switch (dataSize)
-    {
-        case kFLEXCAN_8BperMB:
-            cs_temp = base->MB_8B[mbIdx].CS;
-            can_id = base->MB_8B[mbIdx].ID;
-            break;
-        case kFLEXCAN_16BperMB:
-            cs_temp = base->MB_16B[mbIdx].CS;
-            can_id = base->MB_16B[mbIdx].ID;
-            break;
-        case kFLEXCAN_32BperMB:
-            cs_temp = base->MB_32B[mbIdx].CS;
-            can_id = base->MB_32B[mbIdx].ID;
-            break;
-        case kFLEXCAN_64BperMB:
-            cs_temp = base->MB_64B[mbIdx].CS;
-            can_id = base->MB_64B[mbIdx].ID;
-            break;
-        default:
-            break;
-    }
+    cs_temp = mbAddr[offset];
+    can_id = mbAddr[offset + 1];
+
     /* Get Rx Message Buffer Code field. */
     rx_code = (cs_temp & CAN_CS_CODE_MASK) >> CAN_CS_CODE_SHIFT;
 
@@ -1373,35 +1273,17 @@ status_t FLEXCAN_ReadFDRxMb(CAN_Type *base, uint8_t mbIdx, flexcan_fd_frame_t *r
         /* Get the message length. */
         rxFrame->length = (cs_temp & CAN_CS_DLC_MASK) >> CAN_CS_DLC_SHIFT;
 
+        /* Calculate the DWORD number, dataSize 0/1/2/3 corresponds to 8/16/32/64
+           Bytes payload. */
+        for (cnt = 0; cnt < dataSize + 1; cnt++)
+        {
+            payload_dword *= 2;
+        }
+
         /* Store Message Payload. */
-        switch (dataSize)
+        for (cnt = 0; cnt < payload_dword; cnt++)
         {
-            case kFLEXCAN_8BperMB:
-                for (cnt = 0; cnt < 2; cnt++)
-                {
-                    rxFrame->dataWord[cnt] = base->MB_8B[mbIdx].WORD[cnt];
-                }
-                break;
-            case kFLEXCAN_16BperMB:
-                for (cnt = 0; cnt < 4; cnt++)
-                {
-                    rxFrame->dataWord[cnt] = base->MB_16B[mbIdx].WORD[cnt];
-                }
-                break;
-            case kFLEXCAN_32BperMB:
-                for (cnt = 0; cnt < 8; cnt++)
-                {
-                    rxFrame->dataWord[cnt] = base->MB_32B[mbIdx].WORD[cnt];
-                }
-                break;
-            case kFLEXCAN_64BperMB:
-                for (cnt = 0; cnt < 16; cnt++)
-                {
-                    rxFrame->dataWord[cnt] = base->MB_64B[mbIdx].WORD[cnt];
-                }
-                break;
-            default:
-                break;
+            rxFrame->dataWord[cnt] = mbAddr[offset + 2 + cnt];
         }
 
         /* Read free-running timer to unlock Rx Message Buffer. */
@@ -2201,3 +2083,45 @@ void DMA_FLEXCAN2_INT_DriverIRQHandler(void)
 #endif
 }
 #endif
+
+#if defined(ADMA__CAN0)
+void ADMA_FLEXCAN0_INT_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]);
+
+    s_flexcanIsr(ADMA__CAN0, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN0)]);
+    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+      exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(ADMA__CAN1)
+void ADMA_FLEXCAN1_INT_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]);
+
+    s_flexcanIsr(ADMA__CAN1, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN1)]);
+    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+      exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(ADMA__CAN2)
+void ADMA_FLEXCAN2_INT_DriverIRQHandler(void)
+{
+    assert(s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]);
+
+    s_flexcanIsr(ADMA__CAN2, s_flexcanHandle[FLEXCAN_GetInstance(ADMA__CAN2)]);
+    /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+      exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexcan.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,7 +48,7 @@
 /*! @name Driver version */
 /*@{*/
 /*! @brief FlexCAN driver version 2.2.0. */
-#define FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+#define FSL_FLEXCAN_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
 /*! @brief FlexCAN Frame ID helper macro. */
@@ -68,24 +72,26 @@
      (FLEXCAN_ID_STD(id) << 1)) /*!< Standard Rx FIFO Mask helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_HIGH(id, rtr, ide)                     \
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
-     (((uint32_t)(id) & 0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
+     (((uint32_t)(id)&0x7FF) << 19)) /*!< Standard Rx FIFO Mask helper macro Type B upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_B_LOW(id, rtr, ide)                      \
     (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
-     (((uint32_t)(id) & 0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
+     (((uint32_t)(id)&0x7FF) << 3)) /*!< Standard Rx FIFO Mask helper macro Type B lower part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_HIGH(id) \
-    (((uint32_t)(id) & 0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
+    (((uint32_t)(id)&0x7F8) << 21) /*!< Standard Rx FIFO Mask helper macro Type C upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_HIGH(id) \
-    (((uint32_t)(id) & 0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
+    (((uint32_t)(id)&0x7F8) << 13) /*!< Standard Rx FIFO Mask helper macro Type C mid-upper part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(id) \
-    (((uint32_t)(id) & 0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
+    (((uint32_t)(id)&0x7F8) << 5) /*!< Standard Rx FIFO Mask helper macro Type C mid-lower part helper macro. */
 #define FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) \
-    (((uint32_t)(id) & 0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
+    (((uint32_t)(id)&0x7F8) >> 3) /*!< Standard Rx FIFO Mask helper macro Type C lower part helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide)                          \
     (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
      (FLEXCAN_ID_EXT(id) << 1)) /*!< Extend Rx FIFO Mask helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_HIGH(id, rtr, ide)                        \
-    (((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
-     ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
+    (                                                                             \
+        ((uint32_t)((uint32_t)(rtr) << 31) | (uint32_t)((uint32_t)(ide) << 30)) | \
+        ((FLEXCAN_ID_EXT(id) & 0x1FFF8000)                                        \
+         << 1)) /*!< Extend Rx FIFO Mask helper macro Type B upper part helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(id, rtr, ide)                      \
     (((uint32_t)((uint32_t)(rtr) << 15) | (uint32_t)((uint32_t)(ide) << 14)) | \
      ((FLEXCAN_ID_EXT(id) & 0x1FFF8000) >>                                     \
@@ -119,9 +125,10 @@
 #define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_MID_LOW(id) \
     FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_MID_LOW(          \
         id) /*!< Standard Rx FIFO Filter helper macro Type C mid-lower part helper macro. */
-#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)                                                                     \
-    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \
-                                               */
+#define FLEXCAN_RX_FIFO_STD_FILTER_TYPE_C_LOW(id)                                               \
+    FLEXCAN_RX_FIFO_STD_MASK_TYPE_C_LOW(                                                        \
+        id) /*!< Standard Rx FIFO Filter helper macro Type C lower part helper macro. \ \ \ \ \ \
+               */
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(id, rtr, ide) \
     FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type A helper macro. */
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_HIGH(id, rtr, ide) \
@@ -130,9 +137,10 @@
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_B_LOW(id, rtr, ide) \
     FLEXCAN_RX_FIFO_EXT_MASK_TYPE_B_LOW(                    \
         id, rtr, ide) /*!< Extend Rx FIFO Filter helper macro Type B lower part helper macro. */
-#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)                                                                   \
-    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \
-                                                */
+#define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_HIGH(id)                                            \
+    FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_HIGH(                                                     \
+        id) /*!< Extend Rx FIFO Filter helper macro Type C upper part helper macro. \ \ \ \ \ \
+               */
 #define FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_C_MID_HIGH(id) \
     FLEXCAN_RX_FIFO_EXT_MASK_TYPE_C_MID_HIGH(          \
         id) /*!< Extend Rx FIFO Filter helper macro Type C mid-upper part helper macro. */
@@ -363,11 +371,11 @@ typedef struct _flexcan_fd_frame
         uint32_t format : 1;     /*!< CAN Frame Identifier(STD or EXT format). */
         uint32_t srr : 1;        /*!< Substitute Remote request. */
         uint32_t : 1;
-        uint32_t code : 4;       /*!< Message Buffer Code. */
+        uint32_t code : 4; /*!< Message Buffer Code. */
         uint32_t : 1;
-        uint32_t esi : 1;        /*!< Error State Indicator. */
-        uint32_t brs : 1;        /*!< Bit Rate Switch. */
-        uint32_t edl : 1;        /*!< Extended Data Length. */
+        uint32_t esi : 1; /*!< Error State Indicator. */
+        uint32_t brs : 1; /*!< Bit Rate Switch. */
+        uint32_t edl : 1; /*!< Extended Data Length. */
     };
     struct
     {
@@ -395,6 +403,23 @@ typedef struct _flexcan_fd_frame
 } flexcan_fd_frame_t;
 #endif
 
+/*! @brief FlexCAN protocol timing characteristic configuration structure. */
+typedef struct _flexcan_timing_config
+{
+    uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
+    uint8_t rJumpwidth;  /*!< Re-sync Jump Width. */
+    uint8_t phaseSeg1;   /*!< Phase Segment 1. */
+    uint8_t phaseSeg2;   /*!< Phase Segment 2. */
+    uint8_t propSeg;     /*!< Propagation Segment. */
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE) && FSL_FEATURE_FLEXCAN_HAS_FLEXIBLE_DATA_RATE)
+    uint16_t fpreDivider; /*!< Fast Clock Pre-scaler Division Factor. */
+    uint8_t frJumpwidth;  /*!< Fast Re-sync Jump Width. */
+    uint8_t fphaseSeg1;   /*!< Fast Phase Segment 1. */
+    uint8_t fphaseSeg2;   /*!< Fast Phase Segment 2. */
+    uint8_t fpropSeg;     /*!< Fast Propagation Segment. */
+#endif
+} flexcan_timing_config_t;
+
 /*! @brief FlexCAN module configuration structure. */
 typedef struct _flexcan_config
 {
@@ -412,18 +437,9 @@ typedef struct _flexcan_config
 #if (defined(FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT) && FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT)
     bool enableDoze; /*!< Enable or Disable Doze Mode. */
 #endif
+    flexcan_timing_config_t timingConfig; /* Protocol timing . */
 } flexcan_config_t;
 
-/*! @brief FlexCAN protocol timing characteristic configuration structure. */
-typedef struct _flexcan_timing_config
-{
-    uint16_t preDivider; /*!< Clock Pre-scaler Division Factor. */
-    uint8_t rJumpwidth;  /*!< Re-sync Jump Width. */
-    uint8_t phaseSeg1;   /*!< Phase Segment 1. */
-    uint8_t phaseSeg2;   /*!< Phase Segment 2. */
-    uint8_t propSeg;     /*!< Propagation Segment. */
-} flexcan_timing_config_t;
-
 /*!
  * @brief FlexCAN Receive Message Buffer configuration structure
  *
@@ -510,6 +526,14 @@ extern "C" {
  * @{
  */
 
+/*!
+ * @brief Get the FlexCAN instance from peripheral base address.
+ *
+ * @param base FlexCAN peripheral base address.
+ * @return FlexCAN instance.
+ */
+uint32_t FLEXCAN_GetInstance(CAN_Type *base);
+
 /*!
  * @brief Initializes a FlexCAN instance.
  *
@@ -525,6 +549,7 @@ extern "C" {
  *   flexcanConfig.enableSelfWakeup  = false;
  *   flexcanConfig.enableIndividMask = false;
  *   flexcanConfig.enableDoze        = false;
+ *   flexcanConfig.timingConfig      = timingConfig;
  *   FLEXCAN_Init(CAN0, &flexcanConfig, 8000000UL);
  *   @endcode
  *
@@ -556,6 +581,7 @@ void FLEXCAN_Deinit(CAN_Type *base);
  *   flexcanConfig->enableSelfWakeup  = false;
  *   flexcanConfig->enableIndividMask = false;
  *   flexcanConfig->enableDoze        = false;
+ *   flexcanConfig.timingConfig       = timingConfig;
  *
  * @param config Pointer to the FlexCAN configuration structure.
  */

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,12 +38,25 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio"
+#endif
+
+
 /*< @brief user configurable flexio handle count. */
 #define FLEXIO_HANDLE_COUNT 2
 
 /*******************************************************************************
  * Variables
  ******************************************************************************/
+/*! @brief Pointers to flexio bases for each instance. */
+FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to flexio clocks for each instance. */
+const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*< @brief pointer to array of FLEXIO handle. */
 static void *s_flexioHandle[FLEXIO_HANDLE_COUNT];
@@ -50,14 +67,6 @@ static void *s_flexioType[FLEXIO_HANDLE_COUNT];
 /*< @brief pointer to array of FLEXIO Isr. */
 static flexio_isr_t s_flexioIsr[FLEXIO_HANDLE_COUNT];
 
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-/*! @brief Pointers to flexio clocks for each instance. */
-const clock_ip_name_t s_flexioClocks[] = FLEXIO_CLOCKS;
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-/*! @brief Pointers to flexio bases for each instance. */
-FLEXIO_Type *const s_flexioBases[] = FLEXIO_BASE_PTRS;
-
 /*******************************************************************************
  * Codes
  ******************************************************************************/
@@ -178,7 +187,7 @@ uint32_t FLEXIO_GetShifterBufferAddress(FLEXIO_Type *base, flexio_shifter_buffer
 void FLEXIO_SetShifterConfig(FLEXIO_Type *base, uint8_t index, const flexio_shifter_config_t *shifterConfig)
 {
     base->SHIFTCFG[index] = FLEXIO_SHIFTCFG_INSRC(shifterConfig->inputSource)
-#if defined(FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH) && FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
+#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
                             | FLEXIO_SHIFTCFG_PWIDTH(shifterConfig->parallelWidth)
 #endif /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
                             | FLEXIO_SHIFTCFG_SSTOP(shifterConfig->shifterStop) |

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -43,8 +47,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO driver version 2.0.1. */
-#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief FlexIO driver version 2.0.2. */
+#define FSL_FLEXIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 /*! @brief Calculate FlexIO timer trigger.*/
@@ -185,11 +189,11 @@ typedef enum _flexio_shifter_mode
     kFLEXIO_ShifterModeTransmit = 0x2U,        /*!< Transmit mode. */
     kFLEXIO_ShifterModeMatchStore = 0x4U,      /*!< Match store mode. */
     kFLEXIO_ShifterModeMatchContinuous = 0x5U, /*!< Match continuous mode. */
-#if defined(FSL_FEATURE_FLEXIO_HAS_STATE_MODE) && FSL_FEATURE_FLEXIO_HAS_STATE_MODE
+#if FSL_FEATURE_FLEXIO_HAS_STATE_MODE
     kFLEXIO_ShifterModeState = 0x6U, /*!< SHIFTBUF contents are used for storing
                                       programmable state attributes. */
 #endif                               /* FSL_FEATURE_FLEXIO_HAS_STATE_MODE */
-#if defined(FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE) && FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE
+#if FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE
     kFLEXIO_ShifterModeLogic = 0x7U, /*!< SHIFTBUF contents are used for implementing
                                      programmable logic look up table. */
 #endif                               /* FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE */
@@ -290,7 +294,7 @@ typedef struct _flexio_shifter_config
     flexio_pin_polarity_t pinPolarity; /*!< Shifter Pin Polarity. */
     /* Shifter. */
     flexio_shifter_mode_t shifterMode; /*!< Configures the mode of the Shifter. */
-#if defined(FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH) && FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
+#if FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH
     uint32_t parallelWidth;                    /*!< Configures the parallel width when using parallel mode.*/
 #endif                                         /* FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH */
     flexio_shifter_input_source_t inputSource; /*!< Selects the input source for the shifter. */
@@ -301,6 +305,16 @@ typedef struct _flexio_shifter_config
 /*! @brief typedef for FlexIO simulated driver interrupt handler.*/
 typedef void (*flexio_isr_t)(void *base, void *handle);
 
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/*! @brief Pointers to flexio bases for each instance. */
+extern FLEXIO_Type *const s_flexioBases[];
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to flexio clocks for each instance. */
+extern const clock_ip_name_t s_flexioClocks[];
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -357,6 +371,13 @@ void FLEXIO_Init(FLEXIO_Type *base, const flexio_config_t *userConfig);
 */
 void FLEXIO_Deinit(FLEXIO_Type *base);
 
+/*!
+ * @brief Get instance number for FLEXIO module.
+ *
+ * @param base FLEXIO peripheral base address.
+ */
+uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
+
 /* @} */
 
 /*!

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_i2c_master"
+#endif
+
+
 /*! @brief  FLEXIO I2C transfer state */
 enum _flexio_i2c_master_transfer_states
 {
@@ -45,18 +55,10 @@ enum _flexio_i2c_master_transfer_states
     kFLEXIO_I2C_ReceiveData = 0x5U,      /*!< Receive data transfer phase*/
 };
 
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-extern const clock_ip_name_t s_flexioClocks[];
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-extern FLEXIO_Type *const s_flexioBases[];
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
 
-extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
-
 /*!
  * @brief Set up master transfer, send slave address and decide the initial
  * transfer state.
@@ -97,7 +99,7 @@ static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
  * Codes
  ******************************************************************************/
 
-uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
+static uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
 {
     return FLEXIO_GetInstance(base->flexioBase);
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2c_master.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,8 +48,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO I2C master driver version 2.1.2. */
-#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @brief FlexIO I2C master driver version 2.1.5. */
+#define FSL_FLEXIO_I2C_MASTER_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
 /*@}*/
 
 /*! @brief  FlexIO I2C transfer status*/

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_flexio_i2s.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s"
+#endif
+
+
 /*******************************************************************************
 * Definitations
 ******************************************************************************/
@@ -43,8 +53,6 @@ enum _sai_transfer_state
  * Prototypes
  ******************************************************************************/
 
-extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
-
 /*!
  * @brief Receive a piece of data in non-blocking way.
  *
@@ -68,17 +76,11 @@ static void FLEXIO_I2S_WriteNonBlocking(FLEXIO_I2S_Type *base, uint8_t bitWidth,
  * Variables
  ******************************************************************************/
 
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-extern const clock_ip_name_t s_flexioClocks[];
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-extern FLEXIO_Type *const s_flexioBases[];
-
 /*******************************************************************************
  * Code
  ******************************************************************************/
 
-uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
+static uint32_t FLEXIO_I2S_GetInstance(FLEXIO_I2S_Type *base)
 {
     return FLEXIO_GetInstance(base->flexioBase);
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,8 +48,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO I2S driver version 2.1.1. */
-#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @brief FlexIO I2S driver version 2.1.4. */
+#define FSL_FLEXIO_I2S_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
 /*@}*/
 
 /*! @brief FlexIO I2S transfer status */

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,11 +34,17 @@
 
 #include "fsl_flexio_i2s_edma.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_i2s_edma"
+#endif
+
+
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
 /* Used for 32byte aligned */
-#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU)
+#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU)
 
 /*<! Structure definition for flexio_i2s_edma_private_handle_t. The structure is private. */
 typedef struct _flexio_i2s_edma_private_handle

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_i2s_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -42,6 +46,12 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO I2S EDMA driver version 2.1.4. */
+#define FSL_FLEXIO_I2S_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*@}*/
+
 typedef struct _flexio_i2s_edma_handle flexio_i2s_edma_handle_t;
 
 /*! @brief FlexIO I2S eDMA transfer callback function for finish and error */
@@ -155,7 +165,8 @@ status_t FLEXIO_I2S_TransferSendEDMA(FLEXIO_I2S_Type *base,
  * @brief Performs a non-blocking FlexIO I2S receive using eDMA.
  *
  * @note This interface returned immediately after transfer initiates. Users should call
- * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is finished.
+ * FLEXIO_I2S_GetReceiveRemainingBytes to poll the transfer status and check whether the FlexIO I2S transfer is
+ * finished.
  *
  * @param base FlexIO I2S peripheral base address.
  * @param handle FlexIO I2S DMA handle pointer.

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_spi"
+#endif
+
+
 /*! @brief FLEXIO SPI transfer state, which is used for SPI transactiaonl APIs' internal state. */
 enum _flexio_spi_transfer_states
 {
@@ -41,18 +51,10 @@ enum _flexio_spi_transfer_states
     kFLEXIO_SPI_Busy,        /*!< Transmiter/Receive's queue is not finished. */
 };
 
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-extern const clock_ip_name_t s_flexioClocks[];
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-extern FLEXIO_Type *const s_flexioBases[];
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
 
-extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
-
 /*!
  * @brief Send a piece of data for SPI.
  *
@@ -85,7 +87,7 @@ static void FLEXIO_SPI_TransferReceiveTransaction(FLEXIO_SPI_Type *base, flexio_
  * Codes
  ******************************************************************************/
 
-uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
+static uint32_t FLEXIO_SPI_GetInstance(FLEXIO_SPI_Type *base)
 {
     return FLEXIO_GetInstance(base->flexioBase);
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,8 +49,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO SPI driver version 2.1.1. */
-#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief FlexIO SPI driver version 2.1.3. */
+#define FSL_FLEXIO_SPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
 /*@}*/
 
 #ifndef FLEXIO_SPI_DUMMYDATA

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -31,8 +35,14 @@
 #include "fsl_flexio_spi_edma.h"
 
 /*******************************************************************************
- * Definitons
+ * Definitions
  ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_spi_edma"
+#endif
+
 /*<! Structure definition for spi_edma_private_handle_t. The structure is private. */
 typedef struct _flexio_spi_master_edma_private_handle
 {

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_spi_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -42,6 +46,12 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO SPI EDMA driver version 2.1.3. */
+#define FSL_FLEXIO_SPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*@}*/
+
 /*! @brief  typedef for flexio_spi_master_edma_handle_t in advance. */
 typedef struct _flexio_spi_master_edma_handle flexio_spi_master_edma_handle_t;
 
@@ -88,7 +98,8 @@ extern "C" {
 /*!
  * @brief Initializes the FlexIO SPI master eDMA handle.
  *
- * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master transactional
+ * This function initializes the FlexIO SPI master eDMA handle which can be used for other FlexIO SPI master
+ * transactional
  * APIs.
  * For a specified FlexIO SPI instance, call this API once to get the initialized handle.
  *

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_uart"
+#endif
+
+
 /*<! @brief uart transfer state. */
 enum _flexio_uart_transfer_states
 {
@@ -43,18 +53,10 @@ enum _flexio_uart_transfer_states
     kFLEXIO_UART_RxBusy  /* RX busy. */
 };
 
-#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
-extern const clock_ip_name_t s_flexioClocks[];
-#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
-
-extern FLEXIO_Type *const s_flexioBases[];
-
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
 
-extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
-
 /*!
  * @brief Get the length of received data in RX ring buffer.
  *
@@ -76,7 +78,7 @@ static bool FLEXIO_UART_TransferIsRxRingBufferFull(flexio_uart_handle_t *handle)
  * Codes
  ******************************************************************************/
 
-uint32_t FLEXIO_UART_GetInstance(FLEXIO_UART_Type *base)
+static uint32_t FLEXIO_UART_GetInstance(FLEXIO_UART_Type *base)
 {
     return FLEXIO_GetInstance(base->flexioBase);
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,8 +49,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FlexIO UART driver version 2.1.2. */
-#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
+/*! @brief FlexIO UART driver version 2.1.4. */
+#define FSL_FLEXIO_UART_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
 /*@}*/
 
 /*! @brief Error codes for the UART driver. */

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexio_uart_edma"
+#endif
+
+
 /*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
 typedef struct _flexio_uart_edma_private_handle
 {
@@ -51,8 +61,9 @@ enum _flexio_uart_edma_tansfer_states
 };
 
 /*******************************************************************************
- * Definitions
+ * Variables
  ******************************************************************************/
+
 /*< @brief user configurable flexio uart handle count. */
 #define FLEXIO_UART_HANDLE_COUNT 2
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexio_uart_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -42,6 +46,12 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexIO UART EDMA driver version 2.1.4. */
+#define FSL_FLEXIO_UART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
+/*@}*/
+
 /* Forward declaration of the handle typedef. */
 typedef struct _flexio_uart_edma_handle flexio_uart_edma_handle_t;
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,11 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexram"
+#endif
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -156,8 +165,8 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
     /* dtcm configuration */
     if (dtcmBankNum != 0U)
     {
-        IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ_MASK;
-        IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_MX6RT_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum));
+        IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ_MASK;
+        IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGDTCMSZ(FLEXRAM_MapTcmSizeToRegister(dtcmBankNum));
         IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_DTCM_EN_MASK;
     }
     else
@@ -167,8 +176,8 @@ static status_t FLEXRAM_SetTCMSize(uint8_t itcmBankNum, uint8_t dtcmBankNum)
     /* itcm configuration */
     if (itcmBankNum != 0U)
     {
-        IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ_MASK;
-        IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_MX6RT_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum));
+        IOMUXC_GPR->GPR14 &= ~IOMUXC_GPR_GPR14_CM7_CFGITCMSZ_MASK;
+        IOMUXC_GPR->GPR14 |= IOMUXC_GPR_GPR14_CM7_CFGITCMSZ(FLEXRAM_MapTcmSizeToRegister(itcmBankNum));
         IOMUXC_GPR->GPR16 |= IOMUXC_GPR_GPR16_INIT_ITCM_EN_MASK;
     }
     else

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexram.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,8 +48,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief Driver version 2.0.1. */
-#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*! @brief Driver version 2.0.2. */
+#define FSL_FLEXRAM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 2U))
 /*@}*/
 
 /*! @brief flexram write read sel */

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_flexspi.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexspi"
+#endif
+
+
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
@@ -97,8 +107,10 @@ status_t FLEXSPI_CheckAndClearError(FLEXSPI_Type *base, uint32_t status);
  * Variables
  ******************************************************************************/
 
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
 /*! @brief Pointers to flexspi handles for each instance. */
 static void *s_flexspiHandle[FSL_FEATURE_SOC_FLEXSPI_COUNT];
+#endif
 
 /*! @brief Pointers to flexspi bases for each instance. */
 static FLEXSPI_Type *const s_flexspiBases[] = FLEXSPI_BASE_PTRS;
@@ -247,7 +259,7 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
                   FLEXSPI_MCR0_HSEN(config->enableHalfSpeedAccess) |
                   FLEXSPI_MCR0_COMBINATIONEN(config->enableCombination) |
                   FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpTxFifo) |
-                  FLEXSPI_MCR0_ATDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK;
+                  FLEXSPI_MCR0_ARDFEN(config->ahbConfig.enableAHBWriteIpRxFifo) | FLEXSPI_MCR0_MDIS_MASK;
     base->MCR0 = configValue;
 
     /* Configure MCR1 configurations. */
@@ -256,28 +268,45 @@ void FLEXSPI_Init(FLEXSPI_Type *base, const flexspi_config_t *config)
     base->MCR1 = configValue;
 
     /* Configure MCR2 configurations. */
-    configValue = FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
-                  FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
-                  FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
-                  FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
+    configValue = base->MCR2;
+    configValue &= ~(FLEXSPI_MCR2_RESUMEWAIT_MASK | FLEXSPI_MCR2_SCKBDIFFOPT_MASK | FLEXSPI_MCR2_SAMEDEVICEEN_MASK |
+                     FLEXSPI_MCR2_CLRAHBBUFOPT_MASK);
+    configValue |= FLEXSPI_MCR2_RESUMEWAIT(config->ahbConfig.resumeWaitCycle) |
+                   FLEXSPI_MCR2_SCKBDIFFOPT(config->enableSckBDiffOpt) |
+                   FLEXSPI_MCR2_SAMEDEVICEEN(config->enableSameConfigForAll) |
+                   FLEXSPI_MCR2_CLRAHBBUFOPT(config->ahbConfig.enableClearAHBBufferOpt);
+
     base->MCR2 = configValue;
 
     /* Configure AHB control items. */
-    base->AHBCR = FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) |
-                  FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) |
-                  FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable);
+    configValue = base->AHBCR;
+    configValue &= ~(FLEXSPI_AHBCR_READADDROPT_MASK | FLEXSPI_AHBCR_PREFETCHEN_MASK | FLEXSPI_AHBCR_BUFFERABLEEN_MASK |
+                     FLEXSPI_AHBCR_CACHABLEEN_MASK);
+    configValue |= FLEXSPI_AHBCR_READADDROPT(config->ahbConfig.enableReadAddressOpt) |
+                   FLEXSPI_AHBCR_PREFETCHEN(config->ahbConfig.enableAHBPrefetch) |
+                   FLEXSPI_AHBCR_BUFFERABLEEN(config->ahbConfig.enableAHBBufferable) |
+                   FLEXSPI_AHBCR_CACHABLEEN(config->ahbConfig.enableAHBCachable);
+    base->AHBCR = configValue;
 
     /* Configure AHB rx buffers. */
-    for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
+    for (i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
     {
-        base->AHBRXBUFCR0[i] = FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) |
-                               FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) |
-                               FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize / 8);
+        configValue = base->AHBRXBUFCR0[i];
+
+        configValue &= ~(FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK |
+                         FLEXSPI_AHBRXBUFCR0_MSTRID_MASK | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK);
+        configValue |= FLEXSPI_AHBRXBUFCR0_PREFETCHEN(config->ahbConfig.buffer[i].enablePrefetch) |
+                       FLEXSPI_AHBRXBUFCR0_PRIORITY(config->ahbConfig.buffer[i].priority) |
+                       FLEXSPI_AHBRXBUFCR0_MSTRID(config->ahbConfig.buffer[i].masterIndex) |
+                       FLEXSPI_AHBRXBUFCR0_BUFSZ(config->ahbConfig.buffer[i].bufferSize * 8);
+        base->AHBRXBUFCR0[i] = configValue;
     }
 
     /* Configure IP Fifo watermarks. */
+    base->IPRXFCR &= ~FLEXSPI_IPRXFCR_RXWMRK_MASK;
     base->IPRXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->rxWatermark / 8 - 1);
-    base->IPTXFCR |= FLEXSPI_IPRXFCR_RXWMRK(config->txWatermark / 8 - 1);
+    base->IPTXFCR &= ~FLEXSPI_IPTXFCR_TXWMRK_MASK;
+    base->IPTXFCR |= FLEXSPI_IPTXFCR_TXWMRK(config->txWatermark / 8 - 1);
 }
 
 void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
@@ -299,7 +328,12 @@ void FLEXSPI_GetDefaultConfig(flexspi_config_t *config)
     config->ahbConfig.ahbBusTimeoutCycle = 0xFFFFU;
     config->ahbConfig.resumeWaitCycle = 0x20U;
     memset(config->ahbConfig.buffer, 0, sizeof(config->ahbConfig.buffer));
+    for (uint8_t i = 0; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT; i++)
+    {
+        config->ahbConfig.buffer[i].bufferSize = 256; /* Default buffer size 256 bytes*/
+    }
     config->ahbConfig.enableClearAHBBufferOpt = false;
+    config->ahbConfig.enableReadAddressOpt = false;
     config->ahbConfig.enableAHBPrefetch = false;
     config->ahbConfig.enableAHBBufferable = false;
     config->ahbConfig.enableAHBCachable = false;
@@ -358,6 +392,15 @@ void FLEXSPI_SetFlashConfig(FLEXSPI_Type *base, flexspi_device_config_t *config,
     base->DLLCR[index] = FLEXSPI_ConfigureDll(base, config);
 
     /* Configure write mask. */
+    if (config->enableWriteMask)
+    {
+        base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMOPT1_MASK;
+    }
+    else
+    {
+        base->FLSHCR4 |= FLEXSPI_FLSHCR4_WMOPT1_MASK;
+    }
+
     if (index == 0) /*PortA*/
     {
         base->FLSHCR4 &= ~FLEXSPI_FLSHCR4_WMENA_MASK;
@@ -591,8 +634,10 @@ void FLEXSPI_TransferCreateHandle(FLEXSPI_Type *base,
     handle->completionCallback = callback;
     handle->userData = userData;
 
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
     /* Save the context in global variables to support the double weak mechanism. */
     s_flexspiHandle[instance] = handle;
+#endif
 
     /* Enable NVIC interrupt. */
     EnableIRQ(s_flexspiIrqs[instance]);
@@ -785,6 +830,7 @@ void FLEXSPI_TransferHandleIRQ(FLEXSPI_Type *base, flexspi_handle_t *handle)
     }
 }
 
+#if defined(FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ) && FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
 #if defined(FLEXSPI)
 void FLEXSPI_DriverIRQHandler(void)
 {
@@ -819,3 +865,4 @@ void FLEXSPI1_DriverIRQHandler(void)
 #endif
 }
 #endif
+#endif

bsp/imxrt1052-evk/Libraries/drivers/fsl_flexspi.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,8 +50,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief FLEXSPI driver version 2.0.1. */
-#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*! @brief FLEXSPI driver version 2.0.2. */
+#define FSL_FLEXSPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
 /*@}*/
 
 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(0)
@@ -231,9 +235,11 @@ typedef enum _flexspi_command_type
 
 typedef struct _flexspi_ahbBuffer_config
 {
-    uint8_t priority;
-    uint8_t masterIndex;
-    uint16_t bufferSize;
+    uint8_t priority;    /*!< This priority for AHB Master Read which this AHB RX Buffer is assigned. */
+    uint8_t masterIndex; /*!< AHB Master ID the AHB RX Buffer is assigned. */
+    uint16_t bufferSize; /*!< AHB buffer size in byte. */
+    bool enablePrefetch; /*!< AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master, allows
+                          prefetch disable/enable seperately for each master. */
 } flexspi_ahbBuffer_config_t;
 
 /*! @brief FLEXSPI configuration structure. */
@@ -269,6 +275,8 @@ typedef struct _flexspi_config
         flexspi_ahbBuffer_config_t buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT]; /*!< AHB buffer size. */
         bool enableClearAHBBufferOpt; /*!< Enable/disable automatically clean AHB RX Buffer and TX Buffer
                                        when FLEXSPI returns STOP mode ACK. */
+        bool enableReadAddressOpt;    /*!< Enable/disable remove AHB read burst start address alignment limitation.
+                                       when eanble, there is no AHB read burst start address alignment limitation. */
         bool enableAHBPrefetch;       /*!< Enable/disable AHB read prefetch feature, when enabled, FLEXSPI
                                        will fetch more data than current AHB burst. */
         bool enableAHBBufferable;     /*!< Enable/disable AHB bufferable write access support, when enabled,

bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.c

@@ -1,10 +1,13 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -31,6 +35,12 @@
 
 #include "fsl_gpc.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gpc_1"
+#endif
+
+
 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
 {
     uint32_t irqRegNum = irqId / 32U;

bsp/imxrt1052-evk/Libraries/drivers/fsl_gpc.h

@@ -1,10 +1,13 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016 NXP
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_gpio.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.igpio"
+#endif
+
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -76,7 +86,7 @@ static uint32_t GPIO_GetInstance(GPIO_Type *base)
     return instance;
 }
 
-void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config)
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config)
 {
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Enable GPIO clock. */
@@ -93,7 +103,7 @@ void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config
     }
     else
     {
-        GPIO_WritePinOutput(base, pin, Config->outputLogic);
+        GPIO_PinWrite(base, pin, Config->outputLogic);
         base->GDIR |= (1U << pin);
     }
 
@@ -101,20 +111,20 @@ void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config
     GPIO_SetPinInterruptConfig(base, pin, Config->interruptMode);
 }
 
-void GPIO_PinWrite(GPIO_Type* base, uint32_t pin, uint8_t output)
+void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output)
 {
     assert(pin < 32);
     if (output == 0U)
     {
-        base->DR &= ~(1U << pin);  /* Set pin output to low level.*/
+        base->DR &= ~(1U << pin); /* Set pin output to low level.*/
     }
     else
     {
-        base->DR |= (1U << pin);  /* Set pin output to high level.*/
+        base->DR |= (1U << pin); /* Set pin output to high level.*/
     }
 }
 
-void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
+void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
 {
     volatile uint32_t *icr;
     uint32_t icrShift;
@@ -124,7 +134,7 @@ void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mo
     /* Register reset to default value */
     base->EDGE_SEL &= ~(1U << pin);
 
-    if(pin < 16)
+    if (pin < 16)
     {
         icr = &(base->ICR1);
     }
@@ -133,21 +143,21 @@ void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mo
         icr = &(base->ICR2);
         icrShift -= 16;
     }
-    switch(pinInterruptMode)
+    switch (pinInterruptMode)
     {
-        case(kGPIO_IntLowLevel):
+        case (kGPIO_IntLowLevel):
             *icr &= ~(3U << (2 * icrShift));
             break;
-        case(kGPIO_IntHighLevel):
+        case (kGPIO_IntHighLevel):
             *icr = (*icr & (~(3U << (2 * icrShift)))) | (1U << (2 * icrShift));
             break;
-        case(kGPIO_IntRisingEdge):
+        case (kGPIO_IntRisingEdge):
             *icr = (*icr & (~(3U << (2 * icrShift)))) | (2U << (2 * icrShift));
             break;
-        case(kGPIO_IntFallingEdge):
+        case (kGPIO_IntFallingEdge):
             *icr |= (3U << (2 * icrShift));
             break;
-        case(kGPIO_IntRisingOrFallingEdge):
+        case (kGPIO_IntRisingOrFallingEdge):
             base->EDGE_SEL |= (1U << pin);
             break;
         default:

bsp/imxrt1052-evk/Libraries/drivers/fsl_gpio.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -51,27 +55,28 @@
 /*! @brief GPIO direction definition. */
 typedef enum _gpio_pin_direction
 {
-    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input.*/
+    kGPIO_DigitalInput = 0U,  /*!< Set current pin as digital input.*/
     kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output.*/
 } gpio_pin_direction_t;
 
 /*! @brief GPIO interrupt mode definition. */
 typedef enum _gpio_interrupt_mode
 {
-    kGPIO_NoIntmode = 0U, /*!< Set current pin general IO functionality.*/
-    kGPIO_IntLowLevel = 1U, /*!< Set current pin interrupt is low-level sensitive.*/
-    kGPIO_IntHighLevel = 2U, /*!< Set current pin interrupt is high-level sensitive.*/
-    kGPIO_IntRisingEdge = 3U, /*!< Set current pin interrupt is rising-edge sensitive.*/
-    kGPIO_IntFallingEdge = 4U, /*!< Set current pin interrupt is falling-edge sensitive.*/
+    kGPIO_NoIntmode = 0U,              /*!< Set current pin general IO functionality.*/
+    kGPIO_IntLowLevel = 1U,            /*!< Set current pin interrupt is low-level sensitive.*/
+    kGPIO_IntHighLevel = 2U,           /*!< Set current pin interrupt is high-level sensitive.*/
+    kGPIO_IntRisingEdge = 3U,          /*!< Set current pin interrupt is rising-edge sensitive.*/
+    kGPIO_IntFallingEdge = 4U,         /*!< Set current pin interrupt is falling-edge sensitive.*/
     kGPIO_IntRisingOrFallingEdge = 5U, /*!< Enable the edge select bit to override the ICR register's configuration.*/
 } gpio_interrupt_mode_t;
 
 /*! @brief GPIO Init structure definition. */
 typedef struct _gpio_pin_config
 {
-    gpio_pin_direction_t  direction;     /*!< Specifies the pin direction. */
-    uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
-    gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */
+    gpio_pin_direction_t direction; /*!< Specifies the pin direction. */
+    uint8_t outputLogic;            /*!< Set a default output logic, which has no use in input */
+    gpio_interrupt_mode_t
+        interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */
 } gpio_pin_config_t;
 
 /*******************************************************************************
@@ -96,7 +101,7 @@ extern "C" {
  * @param initConfig pointer to a @ref gpio_pin_config_t structure that
  *        contains the configuration information.
  */
-void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config);
+void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *Config);
 /*@}*/
 
 /*!
@@ -113,13 +118,13 @@ void GPIO_PinInit(GPIO_Type* base, uint32_t pin, const gpio_pin_config_t* Config
  *        - 0: corresponding pin output low-logic level.
  *        - 1: corresponding pin output high-logic level.
  */
-void GPIO_PinWrite(GPIO_Type* base, uint32_t pin, uint8_t output);
+void GPIO_PinWrite(GPIO_Type *base, uint32_t pin, uint8_t output);
 
 /*!
  * @brief Sets the output level of the individual GPIO pin to logic 1 or 0.
  * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinWrite.
  */
-static inline void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t output)
+static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
 {
     GPIO_PinWrite(base, pin, output);
 }
@@ -130,16 +135,20 @@ static inline void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, uint8_t ou
  * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
  * @param mask GPIO pin number macro
  */
-static inline void GPIO_PortSet(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t mask)
 {
+#if (defined(FSL_FEATURE_IGPIO_HAS_DR_SET) && (FSL_FEATURE_IGPIO_HAS_DR_SET == 1))
+    base->DR_SET = mask;
+#else
     base->DR |= mask;
+#endif /* FSL_FEATURE_IGPIO_HAS_DR_SET */
 }
 
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1.
  * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PortSet.
  */
-static inline void GPIO_SetPinsOutput(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
 {
     GPIO_PortSet(base, mask);
 }
@@ -150,20 +159,37 @@ static inline void GPIO_SetPinsOutput(GPIO_Type* base, uint32_t mask)
  * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
  * @param mask GPIO pin number macro
  */
-static inline void GPIO_PortClear(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t mask)
 {
+#if (defined(FSL_FEATURE_IGPIO_HAS_DR_CLEAR) && (FSL_FEATURE_IGPIO_HAS_DR_CLEAR == 1))
+    base->DR_CLEAR = mask;
+#else
     base->DR &= ~mask;
+#endif /* FSL_FEATURE_IGPIO_HAS_DR_CLEAR */
 }
 
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 0.
  * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PortClear.
  */
-static inline void GPIO_ClearPinsOutput(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
 {
     GPIO_PortClear(base, mask);
 }
 
+/*!
+ * @brief Reverses the current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer (GPIO1, GPIO2, GPIO3, and so on.)
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
+{
+#if (defined(FSL_FEATURE_IGPIO_HAS_DR_TOGGLE) && (FSL_FEATURE_IGPIO_HAS_DR_TOGGLE == 1))
+    base->DR_TOGGLE = mask;
+#endif /* FSL_FEATURE_IGPIO_HAS_DR_TOGGLE */
+}
+
 /*!
  * @brief Reads the current input value of the GPIO port.
  *
@@ -171,7 +197,7 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type* base, uint32_t mask)
  * @param pin GPIO port pin number.
  * @retval GPIO port input value.
  */
-static inline uint32_t GPIO_PinRead(GPIO_Type* base, uint32_t pin)
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
 {
     assert(pin < 32);
 
@@ -182,7 +208,7 @@ static inline uint32_t GPIO_PinRead(GPIO_Type* base, uint32_t pin)
  * @brief Reads the current input value of the GPIO port.
  * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinRead.
  */
-static inline uint32_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin)
+static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
 {
     return GPIO_PinRead(base, pin);
 }
@@ -193,28 +219,29 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin)
  * @{
  */
 
- /*!
- * @brief Reads the current GPIO pin pad status.
- *
- * @param base GPIO base pointer.
- * @param pin GPIO port pin number.
- * @retval GPIO pin pad status value.
- */
-static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type* base, uint32_t pin)
+/*!
+* @brief Reads the current GPIO pin pad status.
+*
+* @param base GPIO base pointer.
+* @param pin GPIO port pin number.
+* @retval GPIO pin pad status value.
+*/
+static inline uint8_t GPIO_PinReadPadStatus(GPIO_Type *base, uint32_t pin)
 {
     assert(pin < 32);
 
     return (uint8_t)(((base->PSR) >> pin) & 0x1U);
 }
 
- /*!
- * @brief Reads the current GPIO pin pad status.
- * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinReadPadStatus.
- */
-static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin)
+/*!
+* @brief Reads the current GPIO pin pad status.
+* @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinReadPadStatus.
+*/
+static inline uint8_t GPIO_ReadPadStatus(GPIO_Type *base, uint32_t pin)
 {
     return GPIO_PinReadPadStatus(base, pin);
 }
+
 /*@}*/
 
 /*!
@@ -230,13 +257,13 @@ static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin)
  * @param pininterruptMode pointer to a @ref gpio_interrupt_mode_t structure
  *        that contains the interrupt mode information.
  */
-void GPIO_PinSetInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode);
+void GPIO_PinSetInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode);
 
 /*!
  * @brief Sets the current pin interrupt mode.
  * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PinSetInterruptConfig.
  */
-static inline void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
+static inline void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t pin, gpio_interrupt_mode_t pinInterruptMode)
 {
     GPIO_PinSetInterruptConfig(base, pin, pinInterruptMode);
 }
@@ -247,7 +274,7 @@ static inline void GPIO_SetPinInterruptConfig(GPIO_Type* base, uint32_t pin, gpi
  * @param base GPIO base pointer.
  * @param mask GPIO pin number macro.
  */
-static inline void GPIO_PortEnableInterrupts(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t mask)
 {
     base->IMR |= mask;
 }
@@ -258,7 +285,7 @@ static inline void GPIO_PortEnableInterrupts(GPIO_Type* base, uint32_t mask)
  * @param base GPIO base pointer.
  * @param mask GPIO pin number macro.
  */
-static inline void GPIO_EnableInterrupts(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_EnableInterrupts(GPIO_Type *base, uint32_t mask)
 {
     GPIO_PortEnableInterrupts(base, mask);
 }
@@ -269,7 +296,7 @@ static inline void GPIO_EnableInterrupts(GPIO_Type* base, uint32_t mask)
  * @param base GPIO base pointer.
  * @param mask GPIO pin number macro.
  */
-static inline void GPIO_PortDisableInterrupts(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t mask)
 {
     base->IMR &= ~mask;
 }
@@ -278,7 +305,7 @@ static inline void GPIO_PortDisableInterrupts(GPIO_Type* base, uint32_t mask)
  * @brief Disables the specific pin interrupt.
  * @deprecated Do not use this function.  It has been superceded by @ref GPIO_PortDisableInterrupts.
  */
-static inline void GPIO_DisableInterrupts(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_DisableInterrupts(GPIO_Type *base, uint32_t mask)
 {
     GPIO_PortDisableInterrupts(base, mask);
 }
@@ -289,7 +316,7 @@ static inline void GPIO_DisableInterrupts(GPIO_Type* base, uint32_t mask)
  * @param base GPIO base pointer.
  * @retval current pin interrupt status flag.
  */
-static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type* base)
+static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type *base)
 {
     return base->ISR;
 }
@@ -300,7 +327,7 @@ static inline uint32_t GPIO_PortGetInterruptFlags(GPIO_Type* base)
  * @param base GPIO base pointer.
  * @retval current pin interrupt status flag.
  */
-static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type* base)
+static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base)
 {
     return GPIO_PortGetInterruptFlags(base);
 }
@@ -312,7 +339,7 @@ static inline uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type* base)
  * @param base GPIO base pointer.
  * @param mask GPIO pin number macro.
  */
-static inline void GPIO_PortClearInterruptFlags(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t mask)
 {
     base->ISR = mask;
 }
@@ -324,7 +351,7 @@ static inline void GPIO_PortClearInterruptFlags(GPIO_Type* base, uint32_t mask)
  * @param base GPIO base pointer.
  * @param mask GPIO pin number macro.
  */
-static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type* base, uint32_t mask)
+static inline void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask)
 {
     GPIO_PortClearInterruptFlags(base, mask);
 }

bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_gpt.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.gpt"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_gpt.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_iomuxc.h

@@ -1,31 +1,37 @@
 /*
- * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * The Clear BSD License
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
  * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted (subject to the limitations in the
+ * disclaimer below) provided that the following conditions are met:
+ * 
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * 
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * 
+ * * Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from
+ *   this software without specific prior written permission.
+ * 
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+ * GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+ * HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
 #ifndef _FSL_IOMUXC_H_
@@ -43,6 +49,10 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
+#endif
 
 /*! @name Driver version */
 /*@{*/
@@ -54,7 +64,7 @@
 /*@{*/
 /*! @brief The pin function ID is a tuple of <muxRegister muxMode inputRegister inputDaisy configRegister> */
 #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U
-#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0, 0, 0x400A8018U
+#define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U
 
 #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU
 #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU
@@ -74,7 +84,6 @@
 #define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U
 #define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U
 #define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U
-#define IOMUXC_GPIO_EMC_00_JTAG_DONE 0x401F8014U, 0x7U, 0, 0, 0x401F8204U
 
 #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U
 #define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U
@@ -82,7 +91,6 @@
 #define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U
 #define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U
 #define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U
-#define IOMUXC_GPIO_EMC_01_JTAG_DE_B 0x401F8018U, 0x7U, 0, 0, 0x401F8208U
 
 #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU
 #define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU
@@ -90,7 +98,6 @@
 #define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU
 #define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU
 #define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU
-#define IOMUXC_GPIO_EMC_02_JTAG_FAIL 0x401F801CU, 0x7U, 0, 0, 0x401F820CU
 
 #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U
 #define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U
@@ -98,7 +105,6 @@
 #define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U
 #define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U
 #define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U
-#define IOMUXC_GPIO_EMC_03_JTAG_ACTIVE 0x401F8020U, 0x7U, 0, 0, 0x401F8210U
 
 #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U
 #define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U
@@ -490,6 +496,7 @@
 #define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU
 #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU
 #define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU
+#define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU
 
 #define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U
 #define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0, 0, 0x401F82E0U
@@ -696,6 +703,7 @@
 #define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU
 #define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU
 #define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU
+#define IOMUXC_GPIO_B0_04_ARM_CM7_TRACE00 0x401F814CU, 0x3U, 0, 0, 0x401F833CU
 #define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU
 #define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU
 #define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU
@@ -703,6 +711,7 @@
 #define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U
 #define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U
 #define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U
+#define IOMUXC_GPIO_B0_05_ARM_CM7_TRACE01 0x401F8150U, 0x3U, 0, 0, 0x401F8340U
 #define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U
 #define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U
 #define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U
@@ -710,6 +719,7 @@
 #define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U
 #define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U
 #define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U
+#define IOMUXC_GPIO_B0_06_ARM_CM7_TRACE02 0x401F8154U, 0x3U, 0, 0, 0x401F8344U
 #define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U
 #define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U
 #define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U
@@ -717,6 +727,7 @@
 #define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U
 #define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U
 #define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U
+#define IOMUXC_GPIO_B0_07_ARM_CM7_TRACE03 0x401F8158U, 0x3U, 0, 0, 0x401F8348U
 #define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U
 #define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U
 #define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U
@@ -755,6 +766,7 @@
 
 #define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU
 #define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU
+#define IOMUXC_GPIO_B0_12_ARM_CM7_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU
 #define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU
 #define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU
 #define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU
@@ -762,6 +774,7 @@
 
 #define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U
 #define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U
+#define IOMUXC_GPIO_B0_13_ARM_CM7_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U
 #define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U
 #define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U
 #define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U
@@ -821,7 +834,6 @@
 #define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU
 #define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU
 #define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU
-#define IOMUXC_GPIO_B1_04_CSU_CSU_ALARM_AUT02 0x401F818CU, 0x6U, 0, 0, 0x401F837CU
 
 #define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U
 #define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U
@@ -829,7 +841,6 @@
 #define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U
 #define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U
 #define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U
-#define IOMUXC_GPIO_B1_05_CSU_CSU_ALARM_AUT01 0x401F8190U, 0x6U, 0, 0, 0x401F8380U
 
 #define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U
 #define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U
@@ -837,7 +848,6 @@
 #define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U
 #define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U
 #define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U
-#define IOMUXC_GPIO_B1_06_CSU_CSU_ALARM_AUT00 0x401F8194U, 0x6U, 0, 0, 0x401F8384U
 
 #define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U
 #define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U
@@ -845,7 +855,6 @@
 #define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U
 #define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U
 #define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U
-#define IOMUXC_GPIO_B1_07_CSU_CSU_INT_DEB 0x401F8198U, 0x6U, 0, 0, 0x401F8388U
 
 #define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU
 #define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU
@@ -969,7 +978,6 @@
 #define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U
 #define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U
 #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U
-#define IOMUXC_GPIO_SD_B1_01_CCM_DI0_EXT_CLK 0x401F81D8U, 0x6U, 0, 0, 0x401F83C8U
 
 #define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU
 #define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU
@@ -1015,7 +1023,6 @@
 #define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U
 #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U
 #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U
-#define IOMUXC_GPIO_SD_B1_07_CCM_REF_EN_B 0x401F81F0U, 0x6U, 0, 0, 0x401F83E0U
 
 #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U
 #define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U
@@ -1038,7 +1045,6 @@
 #define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU
 #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU
 #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU
-#define IOMUXC_GPIO_SD_B1_10_SRC_SYSTEM_RESET 0x401F81FCU, 0x6U, 0, 0, 0x401F83ECU
 
 #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U
 #define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U
@@ -1046,7 +1052,6 @@
 #define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U
 #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U
 #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U
-#define IOMUXC_GPIO_SD_B1_11_SRC_EARLY_RESET 0x401F8200U, 0x6U, 0, 0, 0x401F83F0U
 
 #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U)
 #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U)
@@ -1164,11 +1169,15 @@ static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
  */
 static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable)
 {
-    uint32_t gpr = base->GPR1 & 0xFFF;
+    mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK
+            | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK
+            | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK
+            | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK
+            | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK);
 
     if (enable)
     {
-        base->GPR1 = mode | gpr;
+        base->GPR1 |= mode;
     }
     else
     {

bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.c

@@ -1,8 +1,11 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -32,6 +36,12 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.kpp"
+#endif
+
 #define KPP_KEYPAD_SCAN_TIMES (3U)
 /*******************************************************************************
  * Prototypes

bsp/imxrt1052-evk/Libraries/drivers/fsl_kpp.h

@@ -1,8 +1,11 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -36,6 +40,11 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpi2c"
+#endif
+
 /*! @brief Common sets of flags used by the driver. */
 enum _lpi2c_flag_constants
 {
@@ -115,14 +124,8 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz,
                                         uint32_t maxCycles,
                                         uint32_t prescaler);
 
-/* Not static so it can be used from fsl_lpi2c_edma.c. */
-status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status);
-
 static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base);
 
-/* Not static so it can be used from fsl_lpi2c_edma.c. */
-status_t LPI2C_CheckForBusyBus(LPI2C_Type *base);
-
 static status_t LPI2C_RunTransferStateMachine(LPI2C_Type *base, lpi2c_master_handle_t *handle, bool *isDone);
 
 static void LPI2C_InitTransferStateMachine(lpi2c_master_handle_t *handle);
@@ -156,13 +159,13 @@ static const clock_ip_name_t kLpi2cPeriphClocks[] = LPI2C_PERIPH_CLOCKS;
 static lpi2c_master_isr_t s_lpi2cMasterIsr;
 
 /*! @brief Pointers to master handles for each instance. */
-static lpi2c_master_handle_t *s_lpi2cMasterHandle[FSL_FEATURE_SOC_LPI2C_COUNT];
+static lpi2c_master_handle_t *s_lpi2cMasterHandle[ARRAY_SIZE(kLpi2cBases)];
 
 /*! @brief Pointer to slave IRQ handler for each instance. */
 static lpi2c_slave_isr_t s_lpi2cSlaveIsr;
 
 /*! @brief Pointers to slave handles for each instance. */
-static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[FSL_FEATURE_SOC_LPI2C_COUNT];
+static lpi2c_slave_handle_t *s_lpi2cSlaveHandle[ARRAY_SIZE(kLpi2cBases)];
 
 /*******************************************************************************
  * Code
@@ -204,6 +207,9 @@ static uint32_t LPI2C_GetCyclesForWidth(uint32_t sourceClock_Hz,
                                         uint32_t maxCycles,
                                         uint32_t prescaler)
 {
+    assert(sourceClock_Hz > 0);
+    assert(prescaler > 0);
+
     uint32_t busCycle_ns = 1000000 / (sourceClock_Hz / prescaler / 1000);
     uint32_t cycles = 0;
 
@@ -692,7 +698,7 @@ status_t LPI2C_MasterReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize)
 
 status_t LPI2C_MasterSend(LPI2C_Type *base, const void *txBuff, size_t txSize)
 {
-    uint8_t *buf = (uint8_t *)((void *)txBuff);
+    const uint8_t *buf = (const uint8_t *)((const void *)txBuff);
 
     assert(txBuff);
 
@@ -834,6 +840,10 @@ void LPI2C_MasterTransferCreateHandle(LPI2C_Type *base,
 
     /* Clear internal IRQ enables and enable NVIC IRQ. */
     LPI2C_MasterDisableInterrupts(base, kMasterIrqFlags);
+
+    /* Enable NVIC IRQ, this only enables the IRQ directly connected to the NVIC.
+     In some cases the LPI2C IRQ is configured through INTMUX, user needs to enable
+     INTMUX IRQ in application code. */
     EnableIRQ(kLpi2cIrqs[instance]);
 }
 
@@ -1352,7 +1362,7 @@ static status_t LPI2C_SlaveCheckAndClearError(LPI2C_Type *base, uint32_t flags)
 
 status_t LPI2C_SlaveSend(LPI2C_Type *base, const void *txBuff, size_t txSize, size_t *actualTxSize)
 {
-    uint8_t *buf = (uint8_t *)((void *)txBuff);
+    const uint8_t *buf = (const uint8_t *)((const void *)txBuff);
     size_t remaining = txSize;
 
     assert(txBuff);
@@ -1804,6 +1814,14 @@ void LPI2C3_DriverIRQHandler(void)
 }
 #endif
 
+#if defined(LPI2C4)
+/* Implementation of LPI2C4 handler named in startup code. */
+void LPI2C4_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(LPI2C4, 4);
+}
+#endif
+
 #if defined(CM4_0__LPI2C)
 /* Implementation of CM4_0__LPI2C handler named in startup code. */
 void M4_0_LPI2C_DriverIRQHandler(void)
@@ -1812,6 +1830,14 @@ void M4_0_LPI2C_DriverIRQHandler(void)
 }
 #endif
 
+#if defined(CM4__LPI2C)
+/* Implementation of CM4__LPI2C handler named in startup code. */
+void M4_LPI2C_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(CM4__LPI2C, LPI2C_GetInstance(CM4__LPI2C));
+}
+#endif
+
 #if defined(CM4_1__LPI2C)
 /* Implementation of CM4_1__LPI2C handler named in startup code. */
 void M4_1_LPI2C_DriverIRQHandler(void)
@@ -1859,3 +1885,43 @@ void DMA_I2C4_INT_DriverIRQHandler(void)
     LPI2C_CommonIRQHandler(DMA__LPI2C4, LPI2C_GetInstance(DMA__LPI2C4));
 }
 #endif
+
+#if defined(ADMA__LPI2C0)
+/* Implementation of DMA__LPI2C0 handler named in startup code. */
+void ADMA_I2C0_INT_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(ADMA__LPI2C0, LPI2C_GetInstance(ADMA__LPI2C0));
+}
+#endif
+
+#if defined(ADMA__LPI2C1)
+/* Implementation of DMA__LPI2C1 handler named in startup code. */
+void ADMA_I2C1_INT_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(ADMA__LPI2C1, LPI2C_GetInstance(ADMA__LPI2C1));
+}
+#endif
+
+#if defined(ADMA__LPI2C2)
+/* Implementation of DMA__LPI2C2 handler named in startup code. */
+void ADMA_I2C2_INT_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(ADMA__LPI2C2, LPI2C_GetInstance(ADMA__LPI2C2));
+}
+#endif
+
+#if defined(ADMA__LPI2C3)
+/* Implementation of DMA__LPI2C3 handler named in startup code. */
+void ADMA_I2C3_INT_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(ADMA__LPI2C3, LPI2C_GetInstance(ADMA__LPI2C3));
+}
+#endif
+
+#if defined(ADMA__LPI2C4)
+/* Implementation of DMA__LPI2C3 handler named in startup code. */
+void ADMA_I2C4_INT_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(ADMA__LPI2C4, LPI2C_GetInstance(ADMA__LPI2C4));
+}
+#endif

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,8 +49,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPI2C driver version 2.1.3. */
-#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @brief LPI2C driver version 2.1.5. */
+#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
 /*@}*/
 
 /*! @brief Timeout times for waiting flag. */
@@ -498,6 +502,12 @@ void LPI2C_MasterDeinit(LPI2C_Type *base);
  */
 void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *config);
 
+/* Not static so it can be used from fsl_lpi2c_edma.c. */
+status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status);
+
+/* Not static so it can be used from fsl_lpi2c_edma.c. */
+status_t LPI2C_CheckForBusyBus(LPI2C_Type *base);
+
 /*!
  * @brief Performs a software reset.
  *
@@ -708,6 +718,10 @@ static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount,
  * The LPI2C master is automatically disabled and re-enabled as necessary to configure the baud
  * rate. Do not call this function during a transfer, or the transfer is aborted.
  *
+ * @note Please note that the second parameter is the clock frequency of LPI2C module, the third
+ * parameter means user configured bus baudrate, this implementation is different from other I2C drivers
+ * which use baudrate configuration as second parameter and source clock frequency as third parameter.
+ *
  * @param base The LPI2C peripheral base address.
  * @param sourceClock_Hz LPI2C functional clock frequency in Hertz.
  * @param baudRate_Hz Requested bus frequency in Hertz.
@@ -844,6 +858,11 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
  * is created, there is not a corresponding destroy handle. If the user wants to
  * terminate a transfer, the LPI2C_MasterTransferAbort() API shall be called.
  *
+ *
+ * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice
+ * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to
+ * enable the associated INTMUX IRQ in application.
+ *
  * @param base The LPI2C peripheral base address.
  * @param[out] handle Pointer to the LPI2C master driver handle.
  * @param callback User provided pointer to the asynchronous callback function.
@@ -935,7 +954,7 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, lpi2c_master_handle_t *hand
  *  slaveConfig->sclStall.enableAddress    = true;
  *  slaveConfig->ignoreAck                 = false;
  *  slaveConfig->enableReceivedAddressRead = false;
- *  slaveConfig->sdaGlitchFilterWidth_ns   = 0; // TODO determine default width values
+ *  slaveConfig->sdaGlitchFilterWidth_ns   = 0;
  *  slaveConfig->sclGlitchFilterWidth_ns   = 0;
  *  slaveConfig->dataValidDelay_ns         = 0;
  *  slaveConfig->clockHoldTime_ns          = 0;
@@ -1188,6 +1207,10 @@ status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_
  * is created, there is not a corresponding destroy handle. If the user wants to
  * terminate a transfer, the LPI2C_SlaveTransferAbort() API shall be called.
  *
+ * @note The function also enables the NVIC IRQ for the input LPI2C. Need to notice
+ * that on some SoCs the LPI2C IRQ is connected to INTMUX, in this case user needs to
+ * enable the associated INTMUX IRQ in application.
+
  * @param base The LPI2C peripheral base address.
  * @param[out] handle Pointer to the LPI2C slave driver handle.
  * @param callback User provided pointer to the asynchronous callback function.

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -36,6 +40,11 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma"
+#endif
+
 /* @brief Mask to align an address to 32 bytes. */
 #define ALIGN_32_MASK (0x1fU)
 
@@ -96,12 +105,6 @@ typedef void (*lpi2c_isr_t)(LPI2C_Type *base, void *handle);
  * Prototypes
  ******************************************************************************/
 
-/* Defined in fsl_lpi2c.c. */
-extern status_t LPI2C_CheckForBusyBus(LPI2C_Type *base);
-
-/* Defined in fsl_lpi2c.c. */
-extern status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status);
-
 static uint32_t LPI2C_GenerateCommands(lpi2c_master_edma_handle_t *handle);
 
 static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds);
@@ -446,7 +449,15 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl
 static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, bool isTransferDone, uint32_t tcds)
 {
     lpi2c_master_edma_handle_t *handle = (lpi2c_master_edma_handle_t *)userData;
-    bool hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize);
+    bool hasReceiveData;
+
+    if (!handle)
+    {
+        return;
+    }
+
+    hasReceiveData = (handle->transfer.direction == kLPI2C_Read) && (handle->transfer.dataSize);
+
     if (hasReceiveData && !FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(base))
     {
         if (EDMA_GetNextTCDAddress(handle->tx) != 0)
@@ -455,11 +466,6 @@ static void LPI2C_MasterEDMACallback(edma_handle_t *dmaHandle, void *userData, b
         }
     }
 
-    if (!handle)
-    {
-        return;
-    }
-
     /* Check for errors. */
     status_t result = LPI2C_MasterCheckAndClearError(handle->base, LPI2C_MasterGetStatusFlags(handle->base));
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpi2c_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -37,6 +41,12 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPI2C EDMA driver version 2.1.5. */
+#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+/*@}*/
+
 /*!
  * @addtogroup lpi2c_master_edma_driver
  * @{

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,6 +37,12 @@
 /*******************************************************************************
 * Definitions
 ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpspi"
+#endif
+
 /*!
  * @brief Default watermark values.
  *
@@ -53,12 +63,6 @@ typedef void (*lpspi_slave_isr_t)(LPSPI_Type *base, lpspi_slave_handle_t *handle
 /*******************************************************************************
 * Prototypes
 ******************************************************************************/
-/*!
-* @brief Get instance number for LPSPI module.
-*
-* @param base LPSPI peripheral base address.
-*/
-uint32_t LPSPI_GetInstance(LPSPI_Type *base);
 
 /*!
 * @brief Configures the LPSPI peripheral chip select polarity.
@@ -114,12 +118,6 @@ static void LPSPI_SlaveTransferFillUpTxFifo(LPSPI_Type *base, lpspi_slave_handle
 */
 static void LPSPI_SlaveTransferComplete(LPSPI_Type *base, lpspi_slave_handle_t *handle);
 
-/*!
-* @brief Check the argument for transfer .
-* This is not a public API. Not static because lpspi_edma.c will use this API.
-*/
-bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame);
-
 /*!
 * @brief LPSPI common interrupt handler.
 *
@@ -158,7 +156,7 @@ static lpspi_master_isr_t s_lpspiMasterIsr;
 /*! @brief Pointer to slave IRQ handler for each instance. */
 static lpspi_slave_isr_t s_lpspiSlaveIsr;
 /* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
-volatile uint8_t s_dummyData[ARRAY_SIZE(s_lpspiBases)] = {0};
+volatile uint8_t g_lpspiDummyData[ARRAY_SIZE(s_lpspiBases)] = {0};
 /**********************************************************************************************************************
 * Code
 *********************************************************************************************************************/
@@ -183,7 +181,7 @@ uint32_t LPSPI_GetInstance(LPSPI_Type *base)
 void LPSPI_SetDummyData(LPSPI_Type *base, uint8_t dummyData)
 {
     uint32_t instance = LPSPI_GetInstance(base);
-    s_dummyData[instance] = dummyData;
+    g_lpspiDummyData[instance] = dummyData;
 }
 
 void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
@@ -634,7 +632,7 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
     uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
     uint32_t temp = 0U;
-    uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)];
+    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {
@@ -799,7 +797,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
     uint32_t bitsPerFrame = ((base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT) + 1;
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
     uint32_t temp = 0U;
-    uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)];
+    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {
@@ -1820,3 +1818,34 @@ void DMA_SPI3_INT_DriverIRQHandler(void)
     LPSPI_CommonIRQHandler(DMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(DMA__LPSPI3)]);
 }
 #endif
+
+#if defined(ADMA__LPSPI0)
+void ADMA_SPI0_INT_DriverIRQHandler(void)
+{
+    assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]);
+    LPSPI_CommonIRQHandler(ADMA__LPSPI0, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI0)]);
+}
+#endif
+
+#if defined(ADMA__LPSPI1)
+void ADMA_SPI1_INT_DriverIRQHandler(void)
+{
+    assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]);
+    LPSPI_CommonIRQHandler(ADMA__LPSPI1, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI1)]);
+}
+#endif
+#if defined(ADMA__LPSPI2)
+void ADMA_SPI2_INT_DriverIRQHandler(void)
+{
+    assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]);
+    LPSPI_CommonIRQHandler(ADMA__LPSPI2, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI2)]);
+}
+#endif
+
+#if defined(ADMA__LPSPI3)
+void ADMA_SPI3_INT_DriverIRQHandler(void)
+{
+    assert(s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]);
+    LPSPI_CommonIRQHandler(ADMA__LPSPI3, s_lpspiHandle[LPSPI_GetInstance(ADMA__LPSPI3)]);
+}
+#endif

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -52,6 +56,9 @@
 #define LPSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for tx if there is not txData. */
 #endif
 
+/*! @brief Global variable for dummy data value setting. */
+extern volatile uint8_t g_lpspiDummyData[];
+
 /*! @brief Status for the LPSPI driver.*/
 enum _lpspi_status
 {
@@ -223,17 +230,17 @@ enum _lpspi_transfer_config_flag_for_master
 
     kLPSPI_MasterByteSwap =
         1U << 22 /*!< Is master swap the byte.
-                 * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
-                 * lpspi_shift_direction_t to MSB).
-                 * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
-                 * or not, the waveform is 1 2 3 4 5 6 7 8.
-                 * 2. If you set bitPerFrame = 16 :
-                 * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
-                 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
-                 * 3. If you set bitPerFrame = 32 :
-                 * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
-                 * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
-                 */
+                     * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
+                     * lpspi_shift_direction_t to MSB).
+                     * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_MasterByteSwapyou flag is used
+                     * or not, the waveform is 1 2 3 4 5 6 7 8.
+                     * 2. If you set bitPerFrame = 16 :
+                     * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_MasterByteSwap flag.
+                     * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
+                     * 3. If you set bitPerFrame = 32 :
+                     * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_MasterByteSwap flag.
+                     * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_MasterByteSwap flag.
+                     */
 };
 
 #define LPSPI_SLAVE_PCS_SHIFT (4U)   /*!< LPSPI slave PCS shift macro , internal used. */
@@ -249,17 +256,17 @@ enum _lpspi_transfer_config_flag_for_slave
 
     kLPSPI_SlaveByteSwap =
         1U << 22 /*!< Is slave swap the byte.
-                  * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
-                  * lpspi_shift_direction_t to MSB).
-                  * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
-                  * or not, the waveform is 1 2 3 4 5 6 7 8.
-                  * 2. If you set bitPerFrame = 16 :
-                  * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
-                  * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
-                  * 3. If you set bitPerFrame = 32 :
-                  * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
-                  * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
-                  */
+                      * For example, when want to send data 1 2 3 4 5 6 7 8 (suppose you set
+                      * lpspi_shift_direction_t to MSB).
+                      * 1. If you set bitPerFrame = 8 , no matter the kLPSPI_SlaveByteSwap flag is used
+                      * or not, the waveform is 1 2 3 4 5 6 7 8.
+                      * 2. If you set bitPerFrame = 16 :
+                      * (1) the waveform is 2 1 4 3 6 5 8 7 if you do not use the kLPSPI_SlaveByteSwap flag.
+                      * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
+                      * 3. If you set bitPerFrame = 32 :
+                      * (1) the waveform is 4 3 2 1 8 7 6 5 if you do not use the kLPSPI_SlaveByteSwap flag.
+                      * (2) the waveform is 1 2 3 4 5 6 7 8 if you use the kLPSPI_SlaveByteSwap flag.
+                      */
 };
 
 /*! @brief LPSPI transfer state, which is used for LPSPI transactional API state machine. */
@@ -376,16 +383,16 @@ struct _lpspi_master_handle
 
     volatile uint8_t rxWatermark; /*!< Rx watermark. */
 
-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR . */
+    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
     uint8_t *volatile txData;             /*!< Send buffer. */
     uint8_t *volatile rxData;             /*!< Receive buffer. */
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
 
-    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */
-    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times . */
+    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
+    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */
 
     uint32_t totalByteCount; /*!< Number of transfer bytes*/
 
@@ -406,8 +413,8 @@ struct _lpspi_slave_handle
 
     volatile uint8_t rxWatermark; /*!< Rx watermark. */
 
-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR . */
+    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
     uint8_t *volatile txData; /*!< Send buffer. */
     uint8_t *volatile rxData; /*!< Receive buffer. */
@@ -415,8 +422,8 @@ struct _lpspi_slave_handle
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
 
-    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */
-    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times . */
+    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
+    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */
 
     uint32_t totalByteCount; /*!< Number of transfer bytes*/
 
@@ -718,6 +725,24 @@ static inline uint32_t LPSPI_GetRxRegisterAddress(LPSPI_Type *base)
  * @{
  */
 
+/*!
+* @brief Get instance number for LPSPI module.
+*
+* @param base LPSPI peripheral base address.
+* @return Return the value of LPSPI instance.
+*/
+uint32_t LPSPI_GetInstance(LPSPI_Type *base);
+
+/*!
+* @brief Check the argument for transfer .
+*
+* @param transfer the transfer struct to be used.
+* @param bitPerFrame The bit size of one frame.
+* @param bytePerFrame The byte size of one frame.
+* @return Return true for right and false for wrong.
+*/
+bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame);
+
 /*!
  * @brief Configures the LPSPI for either master or slave.
  *
@@ -797,12 +822,12 @@ static inline void LPSPI_SetAllPcsPolarity(LPSPI_Type *base, uint32_t mask)
  * size is 32-bits for each word except the last (the last word contains the remainder bits if the frame size is not
  * divisible by 32). The minimum word size is 2-bits. A frame size of 33-bits (or similar) is not supported.
  *
- * Note 1 : The transmit command register should be initialized before enabling the LPSPI in slave mode, although
+ * Note 1: The transmit command register should be initialized before enabling the LPSPI in slave mode, although
  * the command register does not update until after the LPSPI is enabled. After it is enabled, the transmit command
  * register
  * should only be changed if the LPSPI is idle.
  *
- * Note 2 : The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That
+ * Note 2: The transmit and command FIFO is a combined FIFO that includes both transmit data and command words. That
  * means the TCR register should be written to when the Tx FIFO is not full.
  *
  * @param base LPSPI peripheral address.

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -31,8 +35,14 @@
 #include "fsl_lpspi_edma.h"
 
 /***********************************************************************************************************************
-* Definitons
+* Definitions
 ***********************************************************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpspi_edma"
+#endif
+
 /*!
 * @brief Structure definition for dspi_master_edma_private_handle_t. The structure is private.
 */
@@ -71,18 +81,6 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
                                     void *g_lpspiEdmaPrivateHandle,
                                     bool transferDone,
                                     uint32_t tcds);
-/*!
-* @brief Get instance number for LPSPI module.
-* This is not a public API and it's extern from fsl_lpspi.c.
-* @param base LPSPI peripheral base address
-*/
-extern uint32_t LPSPI_GetInstance(LPSPI_Type *base);
-
-/*!
-* @brief Check the argument for transfer .
-* This is not a public API. It's extern from fsl_lpspi.c.
-*/
-extern bool LPSPI_CheckTransferArgument(lpspi_transfer_t *transfer, uint32_t bitsPerFrame, uint32_t bytesPerFrame);
 
 static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint32_t bytesEachRead, bool isByteSwap);
 
@@ -94,8 +92,6 @@ static void LPSPI_SeparateEdmaReadData(uint8_t *rxData, uint32_t readData, uint3
 static lpspi_master_edma_private_handle_t s_lpspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT];
 static lpspi_slave_edma_private_handle_t s_lpspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_LPSPI_COUNT];
 
-/*! @brief Global variable for dummy data value setting. */
-extern volatile uint8_t s_dummyData[];
 /***********************************************************************************************************************
 * Code
 ***********************************************************************************************************************/
@@ -225,7 +221,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 
     bool isThereExtraTxBytes = false;
 
-    uint8_t dummyData = s_dummyData[instance];
+    uint8_t dummyData = g_lpspiDummyData[instance];
 
     edma_transfer_config_t transferConfigRx;
     edma_transfer_config_t transferConfigTx;
@@ -657,7 +653,7 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     uint32_t bytesPerFrame = (bitsPerFrame + 7) / 8;
     uint32_t temp = 0U;
 
-    uint8_t dummyData = s_dummyData[LPSPI_GetInstance(base)];
+    uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
 
     if (!LPSPI_CheckTransferArgument(transfer, bitsPerFrame, bytesPerFrame))
     {

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpspi_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -41,6 +45,11 @@
 /***********************************************************************************************************************
  * Definitions
  **********************************************************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPSPI EDMA driver version 2.0.2. */
+#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
 
 /*!
 * @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
@@ -88,10 +97,10 @@ struct _lpspi_master_edma_handle
 
     volatile uint8_t rxWatermark; /*!< Rx watermark. */
 
-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR . */
+    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
-    volatile uint8_t bytesLastRead;       /*!< Bytes for last read RDR . */
+    volatile uint8_t bytesLastRead;       /*!< Bytes for last read RDR. */
     volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */
 
     uint8_t *volatile txData;             /*!< Send buffer. */
@@ -119,7 +128,7 @@ struct _lpspi_master_edma_handle
     edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
     edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg buff*/
 
-    edma_tcd_t lpspiSoftwareTCD[3]; /*!<SoftwareTCD , internal used*/
+    edma_tcd_t lpspiSoftwareTCD[3]; /*!<SoftwareTCD, internal used*/
 };
 
 /*! @brief LPSPI slave eDMA transfer handle structure used for transactional API.*/
@@ -131,10 +140,10 @@ struct _lpspi_slave_edma_handle
 
     volatile uint8_t rxWatermark; /*!< Rx watermark. */
 
-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR . */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR . */
+    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
-    volatile uint8_t bytesLastRead;       /*!< Bytes for last read RDR . */
+    volatile uint8_t bytesLastRead;       /*!< Bytes for last read RDR. */
     volatile uint8_t isThereExtraRxBytes; /*!< Is there extra RX byte. */
 
     uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
@@ -144,8 +153,8 @@ struct _lpspi_slave_edma_handle
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
 
-    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times . */
-    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times . */
+    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
+    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */
 
     uint32_t totalByteCount; /*!< Number of transfer bytes*/
 
@@ -162,7 +171,7 @@ struct _lpspi_slave_edma_handle
     edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
     edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg*/
 
-    edma_tcd_t lpspiSoftwareTCD[2]; /*!<SoftwareTCD , internal used*/
+    edma_tcd_t lpspiSoftwareTCD[2]; /*!<SoftwareTCD, internal used*/
 };
 
 /***********************************************************************************************************************

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,6 +37,12 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpuart"
+#endif
+
 /* LPUART transfer state. */
 enum _lpuart_transfer_states
 {
@@ -48,14 +58,6 @@ typedef void (*lpuart_isr_t)(LPUART_Type *base, lpuart_handle_t *handle);
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
-/*!
- * @brief Get the LPUART instance from peripheral base address.
- *
- * @param base LPUART peripheral base address.
- * @return LPUART instance.
- */
-uint32_t LPUART_GetInstance(LPUART_Type *base);
-
 /*!
  * @brief Check whether the RX ring buffer is full.
  *
@@ -199,8 +201,7 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     uint32_t ctrl = base->CTRL;
     bool isSevenDataBits =
-        ((ctrl & LPUART_CTRL_M7_MASK) ||
-         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+        ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
 #endif
 
     /* The Non Blocking read data API assume user have ensured there is enough space in
@@ -698,8 +699,7 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     uint32_t ctrl = base->CTRL;
     bool isSevenDataBits =
-        ((ctrl & LPUART_CTRL_M7_MASK) ||
-         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+        ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
 #endif
 
     while (length--)
@@ -764,8 +764,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     uint32_t ctrl = base->CTRL;
     bool isSevenDataBits =
-        ((ctrl & LPUART_CTRL_M7_MASK) ||
-         ((!(ctrl & LPUART_CTRL_M7_MASK)) && (!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
+        ((ctrl & LPUART_CTRL_M7_MASK) || ((!(ctrl & LPUART_CTRL_M_MASK)) && (ctrl & LPUART_CTRL_PE_MASK)));
 #endif
 
     /* Zero the handle. */
@@ -1651,8 +1650,20 @@ void M4_1_LPUART_DriverIRQHandler(void)
 }
 #endif
 
+#if defined(CM4__LPUART)
+void M4_LPUART_DriverIRQHandler(void)
+{
+    s_lpuartIsr(CM4__LPUART, s_lpuartHandle[LPUART_GetInstance(CM4__LPUART)]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
 #if defined(DMA__LPUART0)
-void DMA_UART0_INT_IRQHandler(void)
+void DMA_UART0_INT_DriverIRQHandler(void)
 {
     s_lpuartIsr(DMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART0)]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -1664,7 +1675,7 @@ void DMA_UART0_INT_IRQHandler(void)
 #endif
 
 #if defined(DMA__LPUART1)
-void DMA_UART1_INT_IRQHandler(void)
+void DMA_UART1_INT_DriverIRQHandler(void)
 {
     s_lpuartIsr(DMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART1)]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -1676,7 +1687,7 @@ void DMA_UART1_INT_IRQHandler(void)
 #endif
 
 #if defined(DMA__LPUART2)
-void DMA_UART2_INT_IRQHandler(void)
+void DMA_UART2_INT_DriverIRQHandler(void)
 {
     s_lpuartIsr(DMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART2)]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -1688,7 +1699,7 @@ void DMA_UART2_INT_IRQHandler(void)
 #endif
 
 #if defined(DMA__LPUART3)
-void DMA_UART3_INT_IRQHandler(void)
+void DMA_UART3_INT_DriverIRQHandler(void)
 {
     s_lpuartIsr(DMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART3)]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -1700,7 +1711,7 @@ void DMA_UART3_INT_IRQHandler(void)
 #endif
 
 #if defined(DMA__LPUART4)
-void DMA_UART4_INT_IRQHandler(void)
+void DMA_UART4_INT_DriverIRQHandler(void)
 {
     s_lpuartIsr(DMA__LPUART4, s_lpuartHandle[LPUART_GetInstance(DMA__LPUART4)]);
 /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
@@ -1710,3 +1721,51 @@ void DMA_UART4_INT_IRQHandler(void)
 #endif
 }
 #endif
+
+#if defined(ADMA__LPUART0)
+void ADMA_UART0_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr(ADMA__LPUART0, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART0)]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(ADMA__LPUART1)
+void ADMA_UART1_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr(ADMA__LPUART1, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART1)]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(ADMA__LPUART2)
+void ADMA_UART2_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr(ADMA__LPUART2, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART2)]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(ADMA__LPUART3)
+void ADMA_UART3_INT_DriverIRQHandler(void)
+{
+    s_lpuartIsr(ADMA__LPUART3, s_lpuartHandle[LPUART_GetInstance(ADMA__LPUART3)]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -548,6 +552,14 @@ static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
  * @{
  */
 
+/*!
+ * @brief Get the LPUART instance from peripheral base address.
+ *
+ * @param base LPUART peripheral base address.
+ * @return LPUART instance.
+ */
+uint32_t LPUART_GetInstance(LPUART_Type *base);
+
 /*!
  * @brief Enables or disables the LPUART transmitter.
  *

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -34,6 +38,11 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpuart_edma"
+#endif
+
 /*<! Structure definition for lpuart_edma_private_handle_t. The structure is private. */
 typedef struct _lpuart_edma_private_handle
 {
@@ -51,7 +60,7 @@ enum _lpuart_edma_tansfer_states
 };
 
 /*******************************************************************************
- * Definitions
+ * Variables
  ******************************************************************************/
 
 /* Array of LPUART handle. */
@@ -122,14 +131,6 @@ static void LPUART_SendEDMACallback(edma_handle_t *handle, void *param, bool tra
  */
 static void LPUART_ReceiveEDMACallback(edma_handle_t *handle, void *param, bool transferDone, uint32_t tcds);
 
-/*!
- * @brief Get the LPUART instance from peripheral base address.
- *
- * @param base LPUART peripheral base address.
- * @return LPUART instance.
- */
-extern uint32_t LPUART_GetInstance(LPUART_Type *base);
-
 /*******************************************************************************
  * Code
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_lpuart_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -42,6 +46,12 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPUART EDMA driver version 2.2.5. */
+#define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 5))
+/*@}*/
+
 /* Forward declaration of the handle typedef. */
 typedef struct _lpuart_edma_handle lpuart_edma_handle_t;
 

bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_pit.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pit"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_pit.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -29,6 +33,12 @@
  */
 #include "fsl_pmu.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pmu"
+#endif
+
+
 uint32_t PMU_GetStatusFlags(PMU_Type *base)
 {
     uint32_t ret = 0U;

bsp/imxrt1052-evk/Libraries/drivers/fsl_pmu.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_pwm.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pwm"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_pwm.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,6 +37,12 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.pxp"
+#endif
+
 /* The CSC2 coefficient is ###.####_#### */
 #define PXP_CSC2_COEF_INT_WIDTH 2
 #define PXP_CSC2_COEF_FRAC_WIDTH 8

bsp/imxrt1052-evk/Libraries/drivers/fsl_pxp.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2017, NXP Semiconductors, Inc.
  * All rights reserved.
  *
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.c

@@ -1,8 +1,11 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -29,6 +33,12 @@
 
 #include "fsl_qtmr.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.qtmr"
+#endif
+
+
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_qtmr.h

@@ -1,8 +1,11 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,12 @@
 
 #include "fsl_rtwdog.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.rtwdog"
+#endif
+
+
 /*******************************************************************************
  * Code
  ******************************************************************************/

bsp/imxrt1052-evk/Libraries/drivers/fsl_rtwdog.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
- *
+ * All rights reserved.
+ * 
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,6 +34,11 @@
 
 #include "fsl_sai.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.sai"
+#endif
+
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
@@ -69,7 +78,7 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t
  *
  * @param base SAI base pointer.
  */
-uint32_t SAI_GetInstance(I2S_Type *base);
+static uint32_t SAI_GetInstance(I2S_Type *base);
 
 /*!
  * @brief sends a piece of data in non-blocking way.
@@ -98,7 +107,7 @@ static void SAI_ReadNonBlocking(I2S_Type *base, uint32_t channel, uint32_t bitWi
 /* Base pointer array */
 static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
 /*!@brief SAI handle pointer */
-sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2];
+static sai_handle_t *s_saiHandle[ARRAY_SIZE(s_saiBases)][2];
 /* IRQ number array */
 static const IRQn_Type s_saiTxIRQ[] = I2S_TX_IRQS;
 static const IRQn_Type s_saiRxIRQ[] = I2S_RX_IRQS;
@@ -178,7 +187,7 @@ static void SAI_SetMasterClockDivider(I2S_Type *base, uint32_t mclk_Hz, uint32_t
 }
 #endif /* FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER */
 
-uint32_t SAI_GetInstance(I2S_Type *base)
+static uint32_t SAI_GetInstance(I2S_Type *base)
 {
     uint32_t instance;
 
@@ -254,6 +263,8 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
     base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
+    SAI_TxReset(base);
+
     /* Configure audio protocol */
     switch (config->protocol)
     {
@@ -337,6 +348,10 @@ void SAI_TxInit(I2S_Type *base, const sai_config_t *config)
         default:
             break;
     }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    SAI_TxSetFIFOErrorContinue(base, true);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */
 }
 
 void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
@@ -358,6 +373,8 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
     base->MCR = (val | I2S_MCR_MOE(config->mclkOutputEnable));
 #endif /* FSL_FEATURE_SAI_HAS_MCR */
 
+    SAI_RxReset(base);
+
     /* Configure audio protocol */
     switch (config->protocol)
     {
@@ -441,6 +458,10 @@ void SAI_RxInit(I2S_Type *base, const sai_config_t *config)
         default:
             break;
     }
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+    SAI_RxSetFIFOErrorContinue(base, true);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR */
 }
 
 void SAI_Deinit(I2S_Type *base)
@@ -457,7 +478,7 @@ void SAI_TxGetDefaultConfig(sai_config_t *config)
     config->bclkSource = kSAI_BclkSourceMclkDiv;
     config->masterSlave = kSAI_Master;
     config->mclkSource = kSAI_MclkSourceSysclk;
-    config->protocol = kSAI_BusLeftJustified;
+    config->protocol = kSAI_BusI2S;
     config->syncMode = kSAI_ModeAsync;
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     config->mclkOutputEnable = true;
@@ -469,7 +490,7 @@ void SAI_RxGetDefaultConfig(sai_config_t *config)
     config->bclkSource = kSAI_BclkSourceMclkDiv;
     config->masterSlave = kSAI_Master;
     config->mclkSource = kSAI_MclkSourceSysclk;
-    config->protocol = kSAI_BusLeftJustified;
+    config->protocol = kSAI_BusI2S;
     config->syncMode = kSAI_ModeSync;
 #if defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)
     config->mclkOutputEnable = true;
@@ -583,6 +604,74 @@ void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask)
     base->RCR3 |= I2S_RCR3_RCE(mask);
 }
 
+void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order)
+{
+    uint32_t val = (base->TCR4) & (~I2S_TCR4_MF_MASK);
+
+    val |= I2S_TCR4_MF(order);
+    base->TCR4 = val;
+}
+
+void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order)
+{
+    uint32_t val = (base->RCR4) & (~I2S_RCR4_MF_MASK);
+
+    val |= I2S_RCR4_MF(order);
+    base->RCR4 = val;
+}
+
+void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->TCR2) & (~I2S_TCR2_BCP_MASK);
+
+    val |= I2S_TCR2_BCP(polarity);
+    base->TCR2 = val;
+}
+
+void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->RCR2) & (~I2S_RCR2_BCP_MASK);
+
+    val |= I2S_RCR2_BCP(polarity);
+    base->RCR2 = val;
+}
+
+void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->TCR4) & (~I2S_TCR4_FSP_MASK);
+
+    val |= I2S_TCR4_FSP(polarity);
+    base->TCR4 = val;
+}
+
+void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity)
+{
+    uint32_t val = (base->RCR4) & (~I2S_RCR4_FSP_MASK);
+
+    val |= I2S_RCR4_FSP(polarity);
+    base->RCR4 = val;
+}
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
+{
+    uint32_t val = base->TCR4;
+
+    val &= ~I2S_TCR4_FPACK_MASK;
+    val |= I2S_TCR4_FPACK(pack);
+    base->TCR4 = val;
+}
+
+void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack)
+{
+    uint32_t val = base->RCR4;
+
+    val &= ~I2S_RCR4_FPACK_MASK;
+    val |= I2S_RCR4_FPACK(pack);
+    base->RCR4 = val;
+}
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
+
 void SAI_TxSetFormat(I2S_Type *base,
                      sai_transfer_format_t *format,
                      uint32_t mclkSourceClockHz,
@@ -633,7 +722,14 @@ void SAI_TxSetFormat(I2S_Type *base,
     }
     else
     {
-        base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1);
+        if (base->TCR4 & I2S_TCR4_MF_MASK)
+        {
+            base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(format->bitWidth - 1);
+        }
+        else
+        {
+            base->TCR5 = I2S_TCR5_WNW(val) | I2S_TCR5_W0W(val) | I2S_TCR5_FBT(0);
+        }
     }
 
     /* Set mono or stereo */
@@ -699,7 +795,14 @@ void SAI_RxSetFormat(I2S_Type *base,
     }
     else
     {
-        base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1);
+        if (base->RCR4 & I2S_RCR4_MF_MASK)
+        {
+            base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(format->bitWidth - 1);
+        }
+        else
+        {
+            base->RCR5 = I2S_RCR5_WNW(val) | I2S_RCR5_W0W(val) | I2S_RCR5_FBT(0);
+        }
     }
 
     /* Set mono or stereo */
@@ -1575,6 +1678,192 @@ void AUDIO_SAI7_INT_DriverIRQHandler(void)
 }
 #endif /* AUDIO__SAI7 */
 
+#if defined(ADMA__SAI0)
+void ADMA_SAI0_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI0->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI0->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI0->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI0, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI0->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI0->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI0->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI0->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI0, s_saiHandle[1][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif /* ADMA__SAI0 */
+
+#if defined(ADMA__SAI1)
+void ADMA_SAI1_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI1->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI1->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI1->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI1, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI1->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI1->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI1->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI1->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI1, s_saiHandle[1][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif /* ADMA__SAI1 */
+
+#if defined(ADMA__SAI2)
+void ADMA_SAI2_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI2->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI2->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI2->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI2, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI2->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI2->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI2->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI2->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI2, s_saiHandle[1][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif /* ADMA__SAI2 */
+
+#if defined(ADMA__SAI3)
+void ADMA_SAI3_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI3->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI3->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI3->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI3, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI3->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI3->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI3->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI3->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI3, s_saiHandle[1][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif /* ADMA__SAI3 */
+
+#if defined(ADMA__SAI4)
+void ADMA_SAI4_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI4->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI4->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI4->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI4, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI4->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI4->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI4->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI4->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI4, s_saiHandle[1][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif /* ADMA__SAI4 */
+
+#if defined(ADMA__SAI5)
+void ADMA_SAI5_INT_DriverIRQHandler(void)
+{
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI5->RCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][1]) && ((ADMA__SAI5->RCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI5->RCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->RCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiRxIsr(ADMA__SAI5, s_saiHandle[1][1]);
+    }
+#if defined(FSL_FEATURE_SAI_FIFO_COUNT) && (FSL_FEATURE_SAI_FIFO_COUNT > 1)
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFORequestFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI5->TCSR & kSAI_FIFORequestInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#else
+    if ((s_saiHandle[1][0]) && ((ADMA__SAI5->TCSR & kSAI_FIFOWarningFlag) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorFlag)) &&
+        ((ADMA__SAI5->TCSR & kSAI_FIFOWarningInterruptEnable) || (ADMA__SAI5->TCSR & kSAI_FIFOErrorInterruptEnable)))
+#endif
+    {
+        s_saiTxIsr(ADMA__SAI5, s_saiHandle[1][0]);
+    }
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif /* ADMA__SAI5 */
+
 #if defined(SAI0)
 void SAI0_DriverIRQHandler(void)
 {
@@ -1697,6 +1986,28 @@ void SAI3_DriverIRQHandler(void)
     __DSB();
 #endif
 }
+
+void SAI3_Tx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][0]);
+    s_saiTxIsr(SAI3, s_saiHandle[3][0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+void SAI3_Rx_DriverIRQHandler(void)
+{
+    assert(s_saiHandle[3][1]);
+    s_saiRxIsr(SAI3, s_saiHandle[3][1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
 #endif /* SAI3 */
 
 #if defined(SAI4)

bsp/imxrt1052-evk/Libraries/drivers/fsl_sai.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -44,7 +48,7 @@
 
 /*! @name Driver version */
 /*@{*/
-#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3)) /*!< Version 2.1.3 */
+#define FSL_SAI_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */
 /*@}*/
 
 /*! @brief SAI return status*/
@@ -84,6 +88,20 @@ typedef enum _sai_mono_stereo
     kSAI_MonoLeft       /*!< Only left channel have sound. */
 } sai_mono_stereo_t;
 
+/*! @brief SAI data order, MSB or LSB */
+typedef enum _sai_data_order
+{
+    kSAI_DataLSB = 0x0U, /*!< LSB bit transferred first */
+    kSAI_DataMSB         /*!< MSB bit transferred first */
+} sai_data_order_t;
+
+/*! @brief SAI clock polarity, active high or low */
+typedef enum _sai_clock_polarity
+{
+    kSAI_PolarityActiveHigh = 0x0U, /*!< Clock active high */
+    kSAI_PolarityActiveLow          /*!< Clock active low */
+} sai_clock_polarity_t;
+
 /*! @brief Synchronous or asynchronous mode */
 typedef enum _sai_sync_mode
 {
@@ -281,7 +299,7 @@ extern "C" {
 void SAI_TxInit(I2S_Type *base, const sai_config_t *config);
 
 /*!
- * @brief Initializes the the SAI Rx peripheral.
+ * @brief Initializes the SAI Rx peripheral.
  *
  * Ungates the SAI clock, resets the module, and configures the SAI Rx with a configuration structure.
  * The configuration structure can be custom filled or set with default values by
@@ -473,6 +491,115 @@ void SAI_TxSetChannelFIFOMask(I2S_Type *base, uint8_t mask);
  */
 void SAI_RxSetChannelFIFOMask(I2S_Type *base, uint8_t mask);
 
+/*!
+ * @brief Set the Tx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_TxSetDataOrder(I2S_Type *base, sai_data_order_t order);
+
+/*!
+ * @brief Set the Rx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_RxSetDataOrder(I2S_Type *base, sai_data_order_t order);
+
+/*!
+ * @brief Set the Tx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_TxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+/*!
+ * @brief Set the Rx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_RxSetBitClockPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+/*!
+ * @brief Set the Tx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_TxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+/*!
+ * @brief Set the Rx data order.
+ *
+ * @param base SAI base pointer
+ * @param order Data order MSB or LSB
+ */
+void SAI_RxSetFrameSyncPolarity(I2S_Type *base, sai_clock_polarity_t polarity);
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_PACKING) && FSL_FEATURE_SAI_HAS_FIFO_PACKING
+/*!
+ * @brief Set Tx FIFO packing feature.
+ *
+ * @param base SAI base pointer.
+ * @param pack FIFO pack type. It is element of sai_fifo_packing_t.
+ */
+void SAI_TxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
+
+/*!
+* @brief Set Rx FIFO packing feature.
+*
+* @param base SAI base pointer.
+* @param pack FIFO pack type. It is element of sai_fifo_packing_t.
+*/
+void SAI_RxSetFIFOPacking(I2S_Type *base, sai_fifo_packing_t pack);
+#endif /* FSL_FEATURE_SAI_HAS_FIFO_PACKING */
+
+#if defined(FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR) && FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR
+/*!
+* @brief Set Tx FIFO error continue.
+*
+* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature
+* not enabled, SAI will hang and users need to clear FEF flag in TCSR register.
+*
+* @param base SAI base pointer.
+* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
+*/
+static inline void SAI_TxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
+{
+    if (isEnabled)
+    {
+        base->TCR4 |= I2S_TCR4_FCONT_MASK;
+    }
+    else
+    {
+        base->TCR4 &= ~I2S_TCR4_FCONT_MASK;
+    }
+}
+
+/*!
+* @brief Set Rx FIFO error continue.
+*
+* FIFO error continue mode means SAI will keep running while FIFO error occured. If this feature
+* not enabled, SAI will hang and users need to clear FEF flag in RCSR register.
+*
+* @param base SAI base pointer.
+* @param isEnabled Is FIFO error continue enabled, true means enable, false means disable.
+*/
+static inline void SAI_RxSetFIFOErrorContinue(I2S_Type *base, bool isEnabled)
+{
+    if (isEnabled)
+    {
+        base->RCR4 |= I2S_RCR4_FCONT_MASK;
+    }
+    else
+    {
+        base->RCR4 &= ~I2S_RCR4_FCONT_MASK;
+    }
+}
+#endif
 /*! @} */
 
 /*!
@@ -857,7 +984,7 @@ status_t SAI_TransferGetReceiveCount(I2S_Type *base, sai_handle_t *handle, size_
 void SAI_TransferAbortSend(I2S_Type *base, sai_handle_t *handle);
 
 /*!
- * @brief Aborts the the current IRQ receive.
+ * @brief Aborts the current IRQ receive.
  *
  * @note This API can be called when an interrupt non-blocking transfer initiates
  * to abort the transfer early.

bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.c

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -30,11 +34,18 @@
 
 #include "fsl_sai_edma.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.sai_edma"
+#endif
+
 /*******************************************************************************
  * Definitations
  ******************************************************************************/
 /* Used for 32byte aligned */
-#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)address + 32) & ~0x1FU)
+#define STCD_ADDR(address) (edma_tcd_t *)(((uint32_t)(address) + 32) & ~0x1FU)
+
+static I2S_Type *const s_saiBases[] = I2S_BASE_PTRS;
 
 /*<! Structure definition for uart_edma_private_handle_t. The structure is private. */
 typedef struct _sai_edma_private_handle
@@ -50,7 +61,7 @@ enum _sai_edma_transfer_state
 };
 
 /*<! Private handle only used for internally. */
-static sai_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT][2];
+static sai_edma_private_handle_t s_edmaPrivateHandle[ARRAY_SIZE(s_saiBases)][2];
 
 /*******************************************************************************
  * Prototypes
@@ -60,7 +71,7 @@ static sai_edma_private_handle_t s_edmaPrivateHandle[FSL_FEATURE_SOC_I2S_COUNT][
  *
  * @param base SAI base pointer.
  */
-extern uint32_t SAI_GetInstance(I2S_Type *base);
+static uint32_t SAI_GetInstance(I2S_Type *base);
 
 /*!
  * @brief SAI EDMA callback for send.
@@ -85,6 +96,24 @@ static void SAI_RxEDMACallback(edma_handle_t *handle, void *userData, bool done,
 /*******************************************************************************
 * Code
 ******************************************************************************/
+static uint32_t SAI_GetInstance(I2S_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_saiBases); instance++)
+    {
+        if (s_saiBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_saiBases));
+
+    return instance;
+}
+
 static void SAI_TxEDMACallback(edma_handle_t *handle, void *userData, bool done, uint32_t tcds)
 {
     sai_edma_private_handle_t *privHandle = (sai_edma_private_handle_t *)userData;

bsp/imxrt1052-evk/Libraries/drivers/fsl_sai_edma.h

@@ -1,9 +1,12 @@
 /*
+ * The Clear BSD License
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
  * Copyright 2016-2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -42,6 +46,11 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+#define FSL_SAI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 4)) /*!< Version 2.1.4 */
+/*@}*/
+
 typedef struct _sai_edma_handle sai_edma_handle_t;
 
 /*! @brief SAI eDMA transfer callback function for finish and error */
@@ -50,19 +59,19 @@ typedef void (*sai_edma_callback_t)(I2S_Type *base, sai_edma_handle_t *handle, s
 /*! @brief SAI DMA transfer handle, users should not touch the content of the handle.*/
 struct _sai_edma_handle
 {
-    edma_handle_t *dmaHandle;                     /*!< DMA handler for SAI send */
-    uint8_t nbytes;                               /*!< eDMA minor byte transfer count initially configured. */
-    uint8_t bytesPerFrame;                        /*!< Bytes in a frame */
-    uint8_t channel;                              /*!< Which data channel */
-    uint8_t count;                                /*!< The transfer data count in a DMA request */
-    uint32_t state;                               /*!< Internal state for SAI eDMA transfer */
-    sai_edma_callback_t callback;                 /*!< Callback for users while transfer finish or error occurs */
-    void *userData;                               /*!< User callback parameter */
-    edma_tcd_t tcd[SAI_XFER_QUEUE_SIZE + 1U];     /*!< TCD pool for eDMA transfer. */
-    sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE]; /*!< Transfer queue storing queued transfer. */
-    size_t transferSize[SAI_XFER_QUEUE_SIZE];     /*!< Data bytes need to transfer */
-    volatile uint8_t queueUser;                   /*!< Index for user to queue transfer. */
-    volatile uint8_t queueDriver;                 /*!< Index for driver to get the transfer data and size */
+    edma_handle_t *dmaHandle;     /*!< DMA handler for SAI send */
+    uint8_t nbytes;               /*!< eDMA minor byte transfer count initially configured. */
+    uint8_t bytesPerFrame;        /*!< Bytes in a frame */
+    uint8_t channel;              /*!< Which data channel */
+    uint8_t count;                /*!< The transfer data count in a DMA request */
+    uint32_t state;               /*!< Internal state for SAI eDMA transfer */
+    sai_edma_callback_t callback; /*!< Callback for users while transfer finish or error occurs */
+    void *userData;               /*!< User callback parameter */
+    uint8_t tcd[(SAI_XFER_QUEUE_SIZE + 1U) * sizeof(edma_tcd_t)]; /*!< TCD pool for eDMA transfer. */
+    sai_transfer_t saiQueue[SAI_XFER_QUEUE_SIZE];                 /*!< Transfer queue storing queued transfer. */
+    size_t transferSize[SAI_XFER_QUEUE_SIZE];                     /*!< Data bytes need to transfer */
+    volatile uint8_t queueUser;                                   /*!< Index for user to queue transfer. */
+    volatile uint8_t queueDriver; /*!< Index for driver to get the transfer data and size */
 };
 
 /*******************************************************************************

bsp/imxrt1052-evk/Libraries/drivers/fsl_semc.c

@@ -1,8 +1,11 @@
 /*
+ * The Clear BSD License
  * Copyright 2017 NXP
+ * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ *  that the following conditions are met:
  *
  * o Redistributions of source code must retain the above copyright notice, this list
  *   of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,6 +37,12 @@
  * Definitions
  ******************************************************************************/
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.semc"
+#endif
+
+
 /*! @brief Define macros for SEMC driver. */
 #define SEMC_IPCOMMANDDATASIZEBYTEMAX (4U)
 #define SEMC_IPCOMMANDMAGICKEY (0xA55A)
@@ -62,7 +72,7 @@
 #define SEMC_BR_MEMSIZE_MAX (4 * 1024 * 1024)
 #define SEMC_SDRAM_MODESETCAL_OFFSET (4)
 #define SEMC_BR_REG_NUM (9)
-#define SEMC_BYTE_NUMBIT (4)
+#define SEMC_BYTE_NUMBIT (8)
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
@@ -116,6 +126,7 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base);
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
 /*! @brief Pointers to SEMC clocks for each instance. */
 static const clock_ip_name_t s_semcClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_CLOCKS;
+static const clock_ip_name_t s_semcExtClock[FSL_FEATURE_SOC_SEMC_COUNT] = SEMC_EXSC_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to SEMC bases for each instance. */
@@ -193,6 +204,9 @@ static status_t SEMC_ConfigureIPCommand(SEMC_Type *base, uint8_t size_bytes)
      *    then the 4-byte data transfer will be split into two 2-byte transfer, the slave address
      *    will be switched automatically according to connected device type*/
     base->IPCR1 = SEMC_IPCR1_DATSZ(size_bytes);
+    /* Clear data size. */
+    base->IPCR2 = 0;
+    /* Set data size. */
     if (size_bytes < 4)
     {
         base->IPCR2 |= SEMC_IPCR2_BM3_MASK;
@@ -212,7 +226,8 @@ static status_t SEMC_IsIPCommandDone(SEMC_Type *base)
 {
     /* Poll status bit till command is done*/
     while (!(base->INTR & SEMC_INTR_IPCMDDONE_MASK))
-    {};
+    {
+    };
 
     /* Clear status bit */
     base->INTR |= SEMC_INTR_IPCMDDONE_MASK;
@@ -266,6 +281,7 @@ void SEMC_Init(SEMC_Type *base, semc_config_t *configure)
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Un-gate sdram controller clock. */
     CLOCK_EnableClock(s_semcClock[SEMC_GetInstance(base)]);
+    CLOCK_EnableClock(s_semcExtClock[SEMC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
     /* Initialize all BR to zero due to the default base address set. */
@@ -310,6 +326,7 @@ void SEMC_Deinit(SEMC_Type *base)
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Disable SDRAM clock. */
     CLOCK_DisableClock(s_semcClock[SEMC_GetInstance(base)]);
+    CLOCK_DisableClock(s_semcExtClock[SEMC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 }
 
@@ -367,16 +384,18 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
     base->IOCR &= ~SEMC_IOCR_MUX_A8_MASK;
 
     /* Timing setting. */
-    base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrtie_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz));
-    base->SDRAMCR2 = SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR2_REF2REF(SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) |
-                     SEMC_SDRAMCR2_ITO(idle);
+    base->SDRAMCR1 = SEMC_SDRAMCR1_PRE2ACT(SEMC_ConvertTiming(config->tPrecharge2Act_Ns, clkSrc_Hz) - 1) |
+                     SEMC_SDRAMCR1_ACT2RW(SEMC_ConvertTiming(config->tAct2ReadWrite_Ns, clkSrc_Hz) - 1) |
+                     SEMC_SDRAMCR1_RFRC(SEMC_ConvertTiming(config->tRefreshRecovery_Ns, clkSrc_Hz) - 1) |
+                     SEMC_SDRAMCR1_WRC(SEMC_ConvertTiming(config->tWriteRecovery_Ns, clkSrc_Hz) - 1) |
+                     SEMC_SDRAMCR1_CKEOFF(SEMC_ConvertTiming(config->tCkeOff_Ns, clkSrc_Hz) - 1) |
+                     SEMC_SDRAMCR1_ACT2PRE(SEMC_ConvertTiming(config->tAct2Prechage_Ns, clkSrc_Hz) - 1);
+    base->SDRAMCR2 =
+        SEMC_SDRAMCR2_SRRC(SEMC_ConvertTiming(config->tSelfRefRecovery_Ns, clkSrc_Hz) - 1) |
+        SEMC_SDRAMCR2_REF2REF(
+            SEMC_ConvertTiming(config->tRefresh2Refresh_Ns, clkSrc_Hz)) |           /* No Minus one to keep with RM */
+        SEMC_SDRAMCR2_ACT2ACT(SEMC_ConvertTiming(config->tAct2Act_Ns, clkSrc_Hz)) | /* No Minus one to keep with RM */
+        SEMC_SDRAMCR2_ITO(idle);
     base->SDRAMCR3 = SEMC_SDRAMCR3_REBL(config->refreshBurstLen - 1) |
                      /* N * 16 * 1s / clkSrc_Hz = config->tPrescalePeriod_Ns */
                      SEMC_SDRAMCR3_PRESCALE(prescale) | SEMC_SDRAMCR3_RT(refresh) | SEMC_SDRAMCR3_UT(urgentRef);
@@ -399,11 +418,6 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
     {
         return result;
     }
-    result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_AutoRefresh, 0, NULL);
-    if (result != kStatus_Success)
-    {
-        return result;
-    }
     /* Mode setting value. */
     mode = (uint16_t)config->burstLen | (uint16_t)(config->casLatency << SEMC_SDRAM_MODESETCAL_OFFSET);
     result = SEMC_SendIPCommand(base, kSEMC_MemType_SDRAM, config->address, kSEMC_SDRAMCM_Modeset, mode, NULL);
@@ -411,6 +425,8 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
     {
         return result;
     }
+    /* Enables refresh */
+    base->SDRAMCR3 |= SEMC_SDRAMCR3_REN_MASK;
 
     return kStatus_Success;
 }
@@ -418,6 +434,7 @@ status_t SEMC_ConfigureSDRAM(SEMC_Type *base, semc_sdram_cs_t cs, semc_sdram_con
 status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_t clkSrc_Hz)
 {
     assert(config);
+    assert(config->timingConfig);
 
     uint8_t memsize;
     status_t result;
@@ -471,21 +488,21 @@ status_t SEMC_ConfigureNAND(SEMC_Type *base, semc_nand_config_t *config, uint32_
                     SEMC_NANDCR0_EDO(config->edoModeEnabled) | SEMC_NANDCR0_COL(config->columnAddrBitNum);
 
     /* Timing setting. */
-    base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->tCeSetup_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->tCeHold_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->tWeLow_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->tWeHigh_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->tReLow_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->tReHigh_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->tTurnAround_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->tCeInterval_Ns, clkSrc_Hz));
-    base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->tWehigh2Relow_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->tRehigh2Welow_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->tAle2WriteStart_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->tReady2Relow_Ns, clkSrc_Hz)) |
-                    SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->tWehigh2Busy_Ns, clkSrc_Hz));
+    base->NANDCR1 = SEMC_NANDCR1_CES(SEMC_ConvertTiming(config->timingConfig->tCeSetup_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_CEH(SEMC_ConvertTiming(config->timingConfig->tCeHold_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_WEL(SEMC_ConvertTiming(config->timingConfig->tWeLow_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_WEH(SEMC_ConvertTiming(config->timingConfig->tWeHigh_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_REL(SEMC_ConvertTiming(config->timingConfig->tReLow_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_REH(SEMC_ConvertTiming(config->timingConfig->tReHigh_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_TA(SEMC_ConvertTiming(config->timingConfig->tTurnAround_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR1_CEITV(SEMC_ConvertTiming(config->timingConfig->tCeInterval_Ns, clkSrc_Hz) - 1);
+    base->NANDCR2 = SEMC_NANDCR2_TWHR(SEMC_ConvertTiming(config->timingConfig->tWehigh2Relow_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR2_TRHW(SEMC_ConvertTiming(config->timingConfig->tRehigh2Welow_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR2_TADL(SEMC_ConvertTiming(config->timingConfig->tAle2WriteStart_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR2_TRR(SEMC_ConvertTiming(config->timingConfig->tReady2Relow_Ns, clkSrc_Hz) - 1) |
+                    SEMC_NANDCR2_TWB(SEMC_ConvertTiming(config->timingConfig->tWehigh2Busy_Ns, clkSrc_Hz) - 1);
     base->NANDCR3 = config->arrayAddrOption;
-    return SEMC_ConfigureIPCommand(base, (config->portSize + 1));
+    return kStatus_Success;
 }
 
 status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t clkSrc_Hz)
@@ -502,8 +519,8 @@ status_t SEMC_ConfigureNOR(SEMC_Type *base, semc_nor_config_t *config, uint32_t
 
     uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux);
     uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
-                        SEMC_IOCR_NOR_CE - 1 :
-                        ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE);
+                         SEMC_IOCR_NOR_CE - 1 :
+                         ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_NOR_CE_A8 : SEMC_IOCR_NOR_CE);
 
     /* IOMUX setting. */
     base->IOCR = iocReg | (muxCe << config->cePinMux);
@@ -615,8 +632,8 @@ status_t SEMC_ConfigureSRAM(SEMC_Type *base, semc_sram_config_t *config, uint32_
 
     uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->cePinMux);
     uint32_t muxCe = (config->cePinMux == kSEMC_MUXRDY) ?
-                        SEMC_IOCR_PSRAM_CE - 1 :
-                        ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE);
+                         SEMC_IOCR_PSRAM_CE - 1 :
+                         ((config->cePinMux == kSEMC_MUXA8) ? SEMC_IOCR_PSRAM_CE_A8 : SEMC_IOCR_PSRAM_CE);
 
     /* IOMUX setting. */
     base->IOCR = iocReg | (muxCe << config->cePinMux);
@@ -721,8 +738,8 @@ status_t SEMC_ConfigureDBI(SEMC_Type *base, semc_dbi_config_t *config, uint32_t
 
     uint32_t iocReg = base->IOCR & ~(SEMC_IOCR_PINMUXBITWIDTH << config->csxPinMux);
     uint32_t muxCsx = (config->csxPinMux == kSEMC_MUXRDY) ?
-                         SEMC_IOCR_DBI_CSX - 1 :
-                         ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX);
+                          SEMC_IOCR_DBI_CSX - 1 :
+                          ((config->csxPinMux == kSEMC_MUXA8) ? SEMC_IOCR_DBI_CSX_A8 : SEMC_IOCR_DBI_CSX);
 
     /* IOMUX setting. */
     base->IOCR = iocReg | (muxCsx << config->csxPinMux);
@@ -751,8 +768,8 @@ status_t SEMC_SendIPCommand(
     SEMC_Type *base, semc_mem_type_t type, uint32_t address, uint16_t command, uint32_t write, uint32_t *read)
 {
     uint32_t cmdMode;
-    bool readCmd = false;
-    bool writeCmd = false;
+    bool readCmd = 0;
+    bool writeCmd = 0;
     status_t result;
 
     /* Clear status bit */
@@ -765,9 +782,9 @@ status_t SEMC_SendIPCommand(
     switch (type)
     {
         case kSEMC_MemType_NAND:
-            readCmd = (cmdMode == kSEMC_NANDCM_AXICmdAddrRead) || (cmdMode == kSEMC_NANDCM_CommandAddressRead) ||
+            readCmd = (cmdMode == kSEMC_NANDCM_CommandAddressRead) ||
                       (cmdMode == kSEMC_NANDCM_CommandRead) || (cmdMode == kSEMC_NANDCM_Read);
-            writeCmd = (cmdMode == kSEMC_NANDCM_AXICmdAddrWrite) || (cmdMode == kSEMC_NANDCM_CommandAddressWrite) ||
+            writeCmd = (cmdMode == kSEMC_NANDCM_CommandAddressWrite) ||
                        (cmdMode == kSEMC_NANDCM_CommandWrite) || (cmdMode == kSEMC_NANDCM_Write);
             break;
         case kSEMC_MemType_NOR:
@@ -817,7 +834,6 @@ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *dat
 
     status_t result = kStatus_Success;
     uint16_t ipCmd;
-    uint8_t dataSize = base->NANDCR0 & SEMC_NANDCR0_PS_MASK;
     uint32_t tempData = 0;
 
     /* Write command built */
@@ -842,13 +858,12 @@ status_t SEMC_IPCommandNandWrite(SEMC_Type *base, uint32_t address, uint8_t *dat
 
         while (size_bytes)
         {
-            tempData |= ((uint32_t)*(data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT));
+            tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT));
             size_bytes--;
         }
 
         result = SEMC_SendIPCommand(base, kSEMC_MemType_NAND, address, ipCmd, tempData, NULL);
     }
-    SEMC_ConfigureIPCommand(base, dataSize);
 
     return result;
 }
@@ -858,7 +873,6 @@ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data
     assert(data);
 
     status_t result = kStatus_Success;
-    uint8_t dataSize = base->NANDCR0 & SEMC_NANDCR0_PS_MASK;
     uint16_t ipCmd;
     uint32_t tempData = 0;
 
@@ -886,12 +900,11 @@ status_t SEMC_IPCommandNandRead(SEMC_Type *base, uint32_t address, uint8_t *data
 
         while (size_bytes)
         {
-            *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * (size_bytes - 1))) & 0xFFU;
             size_bytes--;
+            *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU;
         }
     }
 
-    SEMC_ConfigureIPCommand(base, dataSize);
     return result;
 }
 
@@ -924,8 +937,8 @@ status_t SEMC_IPCommandNorRead(SEMC_Type *base, uint32_t address, uint8_t *data,
         result = SEMC_SendIPCommand(base, kSEMC_MemType_NOR, address, kSEMC_NORDBICM_Read, 0, &tempData);
         while (size_bytes)
         {
-            *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * (size_bytes - 1))) & 0xFFU;
             size_bytes--;
+            *(data + size_bytes) = (tempData >> (SEMC_BYTE_NUMBIT * size_bytes)) & 0xFFU;
         }
     }
 
@@ -961,7 +974,7 @@ status_t SEMC_IPCommandNorWrite(SEMC_Type *base, uint32_t address, uint8_t *data
 
         while (size_bytes)
         {
-            tempData |= ((uint32_t)*(data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT));
+            tempData |= ((uint32_t) * (data + size_bytes - 1) << ((size_bytes - 1) * SEMC_BYTE_NUMBIT));
             size_bytes--;
         }