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@@ -436,13 +436,11 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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if(rt1052_pin_map[pin].gpio != GPIO5)
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{
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CLOCK_EnableClock(kCLOCK_Iomuxc);
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-
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IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 1);
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}
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else
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{
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CLOCK_EnableClock(kCLOCK_IomuxcSnvs);
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-
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IOMUXC_SetPinMux(0x400A8000U + (pin-125)*4, 0x5U, 0, 0, 0, 1);
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}
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@@ -566,6 +564,7 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
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{
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gpio_pin_config_t gpio;
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IRQn_Type irq_num;
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+ rt_uint32_t config_value = 0x1b0a0;
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struct rt1052_pin* pin_map = RT_NULL;
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struct rt1052_irq* irq_map = RT_NULL;
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@@ -639,6 +638,15 @@ static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, r
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break;
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}
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+ if(rt1052_pin_map[pin].gpio != GPIO5)
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+ {
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+ IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value);
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+ }
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+ else
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+ {
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+ IOMUXC_SetPinConfig(0, 0, 0, 0, 0x400A8018U + (pin-125)*4, config_value);
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+ }
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+
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irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin);
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NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
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@@ -675,7 +683,7 @@ int rt_hw_pin_init(void)
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rt1052_pin_ops.pin_read = rt1052_pin_read;
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rt1052_pin_ops.pin_write = rt1052_pin_write;
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rt1052_pin_ops.pin_attach_irq = rt1052_pin_attach_irq;
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- rt1052_pin_ops.pin_detach_irq = rt1052_pin_detach_irq;
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+ rt1052_pin_ops.pin_detach_irq = rt1052_pin_detach_irq;
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rt1052_pin_ops.pin_irq_enable = rt1052_pin_irq_enable;
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ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL);
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