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@@ -8,6 +8,7 @@
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* 2020-12-27 iysheng first version
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* 2021-01-01 iysheng support exti interrupt
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* 2021-09-07 FuC Suit for Vango V85xx
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+ * 2021-09-09 ZhuXW Fixing GPIO interrupt ...
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*/
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#include <board.h>
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@@ -15,50 +16,24 @@
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#ifdef RT_USING_PIN
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-#if defined(GPIOG)
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-#define __GD32_PORT_MAX 7u
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-#elif defined(GPIOF)
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-#define __GD32_PORT_MAX 6u
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+#if defined(GPIOF)
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+#define __V85XX_PORT_MAX 6u
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#elif defined(GPIOE)
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-#define __GD32_PORT_MAX 5u
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+#define __V85XX_PORT_MAX 5u
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#elif defined(GPIOD)
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-#define __GD32_PORT_MAX 4u
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+#define __V85XX_PORT_MAX 4u
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#elif defined(GPIOC)
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-#define __GD32_PORT_MAX 3u
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+#define __V85XX_PORT_MAX 3u
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#elif defined(GPIOB)
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-#define __GD32_PORT_MAX 2u
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+#define __V85XX_PORT_MAX 2u
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#elif defined(GPIOA)
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-#define __GD32_PORT_MAX 1u
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+#define __V85XX_PORT_MAX 1u
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#else
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-#define __GD32_PORT_MAX 0u
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-#error Unsupported GD32 GPIO peripheral.
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+#define __V85XX_PORT_MAX 0u
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+#error Unsupported V85XX GPIO peripheral.
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#endif
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-#define PIN_GDPORT_MAX __GD32_PORT_MAX
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-
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-// static const struct pin_irq_map pin_irq_map[] =
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-// {
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-// #if defined(SOC_SERIES_GD32F1)
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-// {GPIO_Pin_0, EXTI0_IRQn},
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-// {GPIO_Pin_1, EXTI1_IRQn},
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-// {GPIO_Pin_2, EXTI2_IRQn},
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-// {GPIO_Pin_3, EXTI3_IRQn},
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-// {GPIO_Pin_4, EXTI4_IRQn},
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-// {GPIO_Pin_5, EXTI9_5_IRQn},
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-// {GPIO_Pin_6, EXTI9_5_IRQn},
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-// {GPIO_Pin_7, EXTI9_5_IRQn},
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-// {GPIO_Pin_8, EXTI9_5_IRQn},
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-// {GPIO_Pin_9, EXTI9_5_IRQn},
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-// {GPIO_Pin_10, EXTI15_10_IRQn},
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-// {GPIO_Pin_11, EXTI15_10_IRQn},
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-// {GPIO_Pin_12, EXTI15_10_IRQn},
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-// {GPIO_Pin_13, EXTI15_10_IRQn},
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-// {GPIO_Pin_14, EXTI15_10_IRQn},
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-// {GPIO_Pin_15, EXTI15_10_IRQn},
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-// #else
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-// #error "Unsupported soc series"
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-// #endif
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-// };
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+#define PIN_GDPORT_MAX __V85XX_PORT_MAX
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
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{
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@@ -100,7 +75,7 @@ static rt_base_t v85xx_pin_get(const char *name)
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return -RT_EINVAL;
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}
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- if ((name[1] >= 'A') && (name[1] <= 'Z'))
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+ if ((name[1] >= 'A') && (name[1] <= 'F'))
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{
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hw_port_num = (int)(name[1] - 'A');
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}
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@@ -161,7 +136,6 @@ static void v85xx_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
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/* Configure GPIO_InitStructure */
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GPIO_InitStruct.GPIO_Pin = PIN_GDPIN(pin);
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- // GPIO_InitStruct.GPIO_Speed = GPIO_SPEED_2MHZ;
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
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switch (mode)
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@@ -201,12 +175,64 @@ rt_inline rt_int32_t bit2bitno(rt_uint32_t bit)
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return -1;
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}
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+
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+static rt_err_t v85xx_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
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+ rt_uint32_t mode, void (*hdr)(void *args), void *args)
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+{
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+ rt_base_t level;
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+ rt_int32_t irqindex = -1;
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+
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+ if (PIN_PORT(pin) >= PIN_GDPORT_MAX)
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+ {
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+ return -RT_ENOSYS;
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+ }
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+
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+ irqindex = bit2bitno(PIN_GDPIN(pin));
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+
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+ level = rt_hw_interrupt_disable();
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+ if (pin_irq_hdr_tab[irqindex].pin == pin &&
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+ pin_irq_hdr_tab[irqindex].hdr == hdr &&
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+ pin_irq_hdr_tab[irqindex].mode == mode &&
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+ pin_irq_hdr_tab[irqindex].args == args)
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+ {
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+ rt_hw_interrupt_enable(level);
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+ return RT_EOK;
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+ }
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+ if (pin_irq_hdr_tab[irqindex].pin != -1)
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+ {
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+ rt_hw_interrupt_enable(level);
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+ return RT_EBUSY;
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+ }
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+ pin_irq_hdr_tab[irqindex].pin = pin;
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+ pin_irq_hdr_tab[irqindex].hdr = hdr;
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+ pin_irq_hdr_tab[irqindex].mode = mode;
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+ pin_irq_hdr_tab[irqindex].args = args;
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+ rt_hw_interrupt_enable(level);
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+
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+ return RT_EOK;
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+}
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+static rt_err_t v85xx_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
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+{
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+
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+ return RT_EOK;
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+}
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+static rt_err_t v85xx_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
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+{
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+
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+ return RT_EOK;
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+}
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+
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+
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+
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const static struct rt_pin_ops _v85xx_pin_ops =
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{
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v85xx_pin_mode,
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v85xx_pin_write,
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v85xx_pin_read,
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- // v85xx_pin_get,
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+ v85xx_pin_attach_irq,
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+ v85xx_pin_detach_irq,
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+ v85xx_pin_irq_enable,
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+ v85xx_pin_get,
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};
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rt_inline void pin_irq_hdr(int irqno)
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@@ -217,86 +243,12 @@ rt_inline void pin_irq_hdr(int irqno)
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}
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}
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-// /**
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-// * @brief This function handles EXTI interrupt request.
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-// * @param gpio_pin: Specifies the pins connected EXTI line
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-// * @retval none
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-// */
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-// void v85xx_pin_exti_irqhandler(uint16_t gpio_pin)
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-// {
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-// if (SET == EXTI_GetIntBitState(gpio_pin))
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-// {
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-// EXTI_ClearIntBitState(gpio_pin);
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-// pin_irq_hdr(bit2bitno(gpio_pin));
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-// }
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-// }
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-
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-// void EXTI0_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_0);
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-// rt_interrupt_leave();
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-// }
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-
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-// void EXTI1_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_1);
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-// rt_interrupt_leave();
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-// }
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-
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-// void EXTI2_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_2);
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-// rt_interrupt_leave();
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-// }
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-
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-// void EXTI3_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_3);
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-// rt_interrupt_leave();
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-// }
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-
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-// void EXTI4_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_4);
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-// rt_interrupt_leave();
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-// }
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-
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-// void EXTI5_9_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_5);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_6);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_7);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_8);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_9);
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-// rt_interrupt_leave();
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-// }
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-
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-// void EXTI10_15_IRQHandler(void)
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-// {
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-// rt_interrupt_enter();
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_10);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_11);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_12);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_13);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_14);
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-// v85xx_pin_exti_irqhandler(GPIO_Pin_15);
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-// rt_interrupt_leave();
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-// }
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-
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int rt_hw_pin_init(void)
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{
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GPIO_InitType GPIO_InitStruct;
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GPIO_InitStruct.GPIO_Mode = GPIO_Mode_INPUT;
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GPIO_InitStruct.GPIO_Pin = GPIO_Pin_All;
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-#if defined(GPIOG)
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- GPIOBToF_Init(GPIOG, &GPIO_InitStruct);
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-#endif
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+
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#if defined(GPIOF)
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GPIOBToF_Init(GPIOF, &GPIO_InitStruct);
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#endif
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@@ -315,7 +267,7 @@ int rt_hw_pin_init(void)
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#if defined(GPIOA)
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GPIOA_Init(GPIOA, &GPIO_InitStruct);
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#endif
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- GPIOBToF_Init(GPIOB, &GPIO_InitStruct);
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+
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return rt_device_pin_register("pin", &_v85xx_pin_ops, RT_NULL);
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}
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INIT_BOARD_EXPORT(rt_hw_pin_init);
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