2011.08.07 Magicoe Added PK40X256VLQ100

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1666 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/PK40X256VLQ100/application.c

@@ -0,0 +1,98 @@
+/*
+ * File      : app.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-06     Magicoe      first release
+ *
+ */
+
+/**
+ * @addtogroup PK40X256LVQ100
+ */
+/*@{*/
+#include <rtthread.h>
+#include "tc_comm.h"
+#include "SLCD_Driver.h"
+
+/*
+ * This is an example for delay thread
+ */
+static struct rt_thread thread;
+static char thread_stack[THREAD_STACK_SIZE];
+static void thread_entry(void* parameter)
+{
+	rt_tick_t tick;
+	rt_uint8_t *dispchar[4] = {"INITED",
+							   "TICK10",
+							   "TICK15",
+							   " EXIT "};
+
+	rt_kprintf("thread inited ok\n");
+	SLCD_PrintString(dispchar[0], 0);
+
+	tick = rt_tick_get();
+	rt_kprintf("thread tick %d\n", tick);
+	rt_kprintf("thread delay 10 tick\n");
+	
+
+	rt_thread_delay(1000);	
+	if (rt_tick_get() - tick > 1000)
+	{
+		tc_done(TC_STAT_FAILED);
+		return;
+	}
+	SLCD_PrintString(dispchar[1], 0);
+
+	tick = rt_tick_get();
+	rt_kprintf("thread delay 15 tick\n");
+ 
+	rt_thread_delay(1500);
+	if (rt_tick_get() - tick > 1500)
+	{
+		tc_done(TC_STAT_FAILED);
+		return;
+	}
+	
+	SLCD_PrintString(dispchar[2], 0);
+
+	rt_thread_delay(1000);
+
+	rt_kprintf("thread exit\n");
+	SLCD_PrintString(dispchar[3], 0);
+
+	tc_done(TC_STAT_PASSED);
+}
+
+rt_err_t thread_delay_init()
+{
+	rt_err_t result;
+
+	result = rt_thread_init(&thread,
+		"test",
+		thread_entry, RT_NULL,
+		&thread_stack[0], sizeof(thread_stack),
+		THREAD_PRIORITY, 10);
+
+	if (result == RT_EOK)
+		rt_thread_startup(&thread);
+	else
+		tc_stat(TC_STAT_END | TC_STAT_FAILED);
+
+	return result;
+}
+
+int rt_application_init()
+{
+	thread_delay_init();
+
+	return 0;
+}
+
+/*@}*/

bsp/PK40X256VLQ100/board.c

@@ -0,0 +1,73 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ * 2011-08-06     Magicoe      PK40X256VLQ100 version
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "board.h"
+#include "uart.h"
+
+#include "PK40X256VLQ100.h"
+#include "core_cm4.h"
+
+#include "SLCD_Driver.h"
+
+/**
+ * @addtogroup PK40X256VLQ100
+ */
+/*@{*/
+
+/**
+ * This is the timer interrupt service routine.
+ */
+void rt_hw_timer_handler()
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+/**
+ * This function will initial sam7s64 board.
+ */
+void rt_hw_board_init()
+{
+	rt_uint8_t *dispchar = {"RTINIT"};
+	/* Get Core Clock Frequency */
+	SystemCoreClockUpdate();                      /* Get Core Clock Frequency */
+	/* init systick */
+	SysTick_Config( SystemCoreClock/1000 );       /* Generate interrupt each 1 ms    */
+	
+	SLCD_Configuration();
+	SLCD_SegmentsAllOff ();
+	SLCD_PrintString(dispchar, 0);
+
+	/* set pend exception priority */
+//	NVIC_SetPriority(PendSV_IRQn, (1<<__NVIC_PRIO_BITS) - 1);
+#ifdef RT_USING_UART
+	/* init hardware UART device */
+	rt_hw_uart_init();
+#endif
+#ifdef RT_USING_CONSOLE
+	/* set console device */
+	rt_console_set_device("uart0");
+#endif
+	SLCD_PrintString(dispchar, 0);
+}
+/*@}*/

bsp/PK40X256VLQ100/board.h

@@ -0,0 +1,20 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+void rt_hw_board_init(void);
+
+#endif

bsp/PK40X256VLQ100/bsp/Font_35x8.h

@@ -0,0 +1,475 @@
+const int8_t Font_35x8[] = {
+  /* Space ' ' */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '!' */
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,1,0,0,  
+  /* '"' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '#' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '$' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '%' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '&' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* ''' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '(' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* ')' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '*' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '+' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* ',' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '-' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '.' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '/' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '0' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,1,1,
+  1,0,1,0,1,
+  1,1,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,  
+  /* '1' */
+  0,0,1,0,0,
+  0,1,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,1,1,1,0,
+  /* '2' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  0,0,0,0,1,
+  0,0,0,1,0,
+  0,0,1,0,0,
+  0,1,0,0,0,
+  1,1,1,1,1,
+  /* '3' */
+  1,1,1,1,1,
+  0,0,0,1,0,
+  0,0,1,0,0,
+  0,0,0,1,0,
+  0,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,
+  /* '4' */
+  0,0,0,1,0,
+  0,0,1,1,0,
+  0,1,0,1,0,
+  1,0,0,1,0,
+  1,1,1,1,1,
+  0,0,0,1,0,
+  0,0,0,1,0,
+  /* '5' */
+  1,1,1,1,1,
+  1,0,0,0,0,
+  1,1,1,1,0,
+  0,0,0,0,1,
+  0,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,    
+  /* '6' */
+  0,0,1,1,0,
+  0,1,0,0,0,
+  1,0,0,0,0,
+  1,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,
+  /* '7' */
+  1,1,1,1,1,
+  0,0,0,0,1,
+  0,0,0,1,0,
+  0,0,1,0,0,
+  0,1,0,0,0,
+  0,1,0,0,0,
+  0,1,0,0,0,
+  /* '8' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,
+  /* '9' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,1,
+  0,0,0,0,1,
+  0,0,0,1,0,
+  0,1,1,0,0,
+  /* ':' */
+  0,0,0,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,0,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,0,0,0,  
+  /* ';' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '<' */
+  0,0,0,0,1,
+  0,0,0,1,0,
+  0,0,1,0,0,
+  0,1,0,0,0,
+  0,0,1,0,0,
+  0,0,0,1,0,
+  0,0,0,0,1,  
+  /* '=' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,1,1,1,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '>' */
+  0,1,0,0,0,
+  0,0,1,0,0,
+  0,0,0,1,0,
+  0,0,0,0,1,
+  0,0,0,1,0,
+  0,0,1,0,0,
+  0,1,0,0,0,  
+  /* '?'not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* '@' not defined */
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,
+  0,0,0,0,0,  
+  /* 'A' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,1,1,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  /* 'B' */
+  1,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,1,1,0,
+  /* 'C' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,1,
+  0,1,1,1,0,
+  /* 'D' */
+  1,1,1,0,0,
+  1,0,0,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,1,0,
+  1,1,1,0,0,  
+  /* 'E' */
+  1,1,1,1,1,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,1,1,1,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,1,1,1,1,
+  /* 'F' */
+  1,1,1,1,1,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,1,1,1,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  /* 'G' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,0,
+  1,0,1,1,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,1,
+  /* 'H' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,1,1,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  /* 'I' */
+  0,1,1,1,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,1,1,1,0,  
+  /* 'J' */
+  0,0,1,1,1,
+  0,0,0,1,0,
+  0,0,0,1,0,
+  0,0,0,1,0,
+  0,0,0,1,0,
+  1,0,0,1,0,
+  0,1,1,0,0,
+  /* 'K' */
+  1,0,0,0,1,
+  1,0,0,1,0,
+  1,0,1,0,0,
+  1,1,0,0,0,
+  1,0,1,0,0,
+  1,0,0,1,0,
+  1,0,0,0,1,    
+  /* 'L' */
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,1,1,1,1,
+  /* 'M' */
+  1,0,0,0,1,
+  1,1,0,1,1,
+  1,0,1,0,1,
+  1,0,1,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  /* 'N' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,0,0,1,
+  1,0,1,0,1,
+  1,0,0,1,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  /* 'O' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,  
+  /* 'P' */
+  1,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,1,1,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  /* 'Q' */
+  0,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,1,0,1,
+  1,0,0,1,0,
+  0,1,1,0,1,
+  /* 'R' */
+  1,1,1,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,1,1,1,0,
+  1,0,1,0,0,
+  1,0,0,1,0,
+  1,0,0,0,1,  
+  /* 'S' */
+  0,1,1,1,1,
+  1,0,0,0,0,
+  1,0,0,0,0,
+  0,1,1,1,0,
+  0,0,0,0,1,
+  0,0,0,0,1,
+  1,1,1,1,0,
+  /* 'T' */
+  1,1,1,1,1,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  /* 'U' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,1,1,0,
+  /* 'V' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,0,1,0,
+  0,0,1,0,0,
+  /* 'W' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,1,0,1,
+  1,0,1,0,1,
+  1,0,1,0,1,
+  0,1,0,1,0,
+  /* 'X' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,0,1,0,
+  0,0,1,0,0,
+  0,1,0,1,0,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  /* 'Y' */
+  1,0,0,0,1,
+  1,0,0,0,1,
+  1,0,0,0,1,
+  0,1,0,1,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  0,0,1,0,0,
+  /* 'Z' */
+  1,1,1,1,1,
+  0,0,0,0,1,
+  0,0,0,1,0,
+  0,0,1,0,0,
+  0,1,0,0,0,
+  1,0,0,0,0,
+  1,1,1,1,1,
+};
+

bsp/PK40X256VLQ100/bsp/SLCD_Driver.c

@@ -0,0 +1,367 @@
+/**************************************************************************//**
+ * @file     SLCD_Driver.c
+ * @brief    MK40X256VMD100 Segment LCD Low Level Driver (306 Segments) 
+ * @version  V0.01
+ * @date     13. May 2011
+ *
+ * @note
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#include <PK40X256VLQ100.H>
+#include <string.h>
+#include "rtdef.h"
+#include "Font_35x8.h"
+#include "SLCD_Driver.h"
+
+const uint8_t WFShiftTable[] =  /*Front Plane 0 - 38*/ 
+{
+   0,
+   8,
+  16,
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,               
+  24,               
+   0,                
+   8,                
+  16,             
+};
+
+/*******************************************************************************
+* SLCD controller Initialization                                             *
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+
+
+void SLCD_Configuration (void)
+{
+  MCG->C1     |=   MCG_C1_IRCLKEN_MASK;      /* Enable IRCLK            */
+
+  SIM->SCGC5  |=  (SIM_SCGC5_PORTB_MASK      /* Enable Port B,C,D Clock */
+              |    SIM_SCGC5_PORTC_MASK 
+              |    SIM_SCGC5_PORTD_MASK );
+
+  SIM->SCGC3  |= SIM_SCGC3_SLCD_MASK;        /* Enable SLCD Clock      */
+  
+  LCD->GCR     = 0;                          /* Disable SLCD module    */
+
+  LCD->PEN[0]  = 0xFFFFFFFE;                 /* Enable SLCD pins  1-31 */ 
+  LCD->PEN[1]  = 0x0000FFFF;                 /* Enable SLCD pins 32-47 */
+
+  
+  LCD->BPEN[1] = 0x0000FF00;                 /* SLCD Backplane Assignment: Pin 38 - 46 */
+  LCD->BPEN[0] = 0;
+
+  LCD->WF[0]   = 0;                          /* Clear SLCD */ 
+  LCD->WF[1]   = 0;
+  LCD->WF[2]   = 0;
+  LCD->WF[3]   = 0;
+  LCD->WF[4]   = 0;
+  LCD->WF[5]   = 0;
+  LCD->WF[6]   = 0;
+  LCD->WF[7]   = 0;
+  LCD->WF[8]   = 0;
+  LCD->WF[9]   = 0;
+  
+  LCD->WF[10]  = 0x08040201;                 /* SLCD Backplane Phase Assignment */ 
+  LCD->WF[11]  = 0x80402010;
+
+  LCD->GCR    |=  LCD_GCR_VSUPPLY(1);        /* Drive VLL3 from VDD                  */
+  LCD->GCR    |=  LCD_GCR_CPSEL_MASK;        /* LCD charge pump is selected          */
+  LCD->GCR    |=  LCD_GCR_DUTY(7);           /* Use 8 BP                             */
+  LCD->GCR    |=  LCD_GCR_SOURCE_MASK;       /* LCD clock source   : alternate clock */      
+  LCD->GCR    |=  LCD_GCR_LCLK(4);           /* LCD clock prescaler: 4               */
+  
+  LCD->GCR    |= LCD_GCR_LCDEN_MASK;         /* Enable LCD module                    */
+}
+/*******************************************************************************
+* SLCD All Segments Off
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_SegmentsAllOff (void)
+{
+  LCD->WF[0]   = 0;
+  LCD->WF[1]   = 0;
+  LCD->WF[2]   = 0;
+  LCD->WF[3]   = 0;
+  LCD->WF[4]   = 0;
+  LCD->WF[5]   = 0;
+  LCD->WF[6]   = 0;
+  LCD->WF[7]   = 0;
+  LCD->WF[8]   = 0;
+  LCD->WF[9]   = 0;
+}
+
+/*******************************************************************************
+* SLCD All Segments On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_SegmentsAllOn(void) 
+{
+  LCD->WF[0] = 0xFFFFFF00;
+  LCD->WF[1] = 0xFFFFFFFF;
+  LCD->WF[2] = 0xFFFFFFFF;
+  LCD->WF[3] = 0xFFFFFFFF;
+  LCD->WF[4] = 0xFFFFFFFF;
+  LCD->WF[5] = 0xFFFFFFFF;
+  LCD->WF[6] = 0xFFFFFFFF;
+  LCD->WF[7] = 0xFFFFFFFF;
+  LCD->WF[8] = 0xFFFFFFFF;
+  LCD->WF[9] = 0xFFFFFFFF;
+}
+
+/*******************************************************************************
+* SLCD Draw One ASCII character
+*   Parameter:    in (ASCII character), fploc (Front Plane Location)
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_DrawChar(uint8_t in, uint8_t fploc)
+{
+  int nCol, nRow;
+  uint8_t bploc = 0;
+  uint8_t value = 0;  
+
+  in -= 0x20;
+
+  for (nRow = 0; nRow < (CHAR_SIZE_ROW); nRow++) {
+    for (nCol = 0; nCol < CHAR_SIZE_COLUMN; nCol++) {
+      value = Font_35x8[in*CHAR_SIZE + nRow*CHAR_SIZE_COLUMN + nCol];           
+      if (value == 0) {
+        LCD->WF[(fploc + 2)/4] &= ~(1 << (bploc + WFShiftTable[fploc + 2]));      
+      }
+      else {
+        LCD->WF[(fploc + 2)/4] |= (1 << (bploc + WFShiftTable[fploc + 2]));   
+      }
+      fploc++;
+    }
+    bploc++;
+    fploc -= CHAR_SIZE_COLUMN;
+  }
+}
+
+/*******************************************************************************
+* SLCD Print String
+*   Parameter:    srcStr (Source String) , sPos (Front Plane Location)
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_PrintString (uint8_t *  srcStr, uint8_t sPos)
+{
+  uint8_t offset = sPos;  
+
+  while (*srcStr)
+  {
+    SLCD_DrawChar(*srcStr++,offset);        
+    offset += CHAR_SIZE_SEGMENT;  
+  }
+}
+
+/*******************************************************************************
+* SLCD Print String2
+*   Parameter:    srcStr (Source String) , sPos (Front Plane Location)
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_PrintString2 (uint8_t *  srcStr, uint8_t sPos)
+{
+  uint8_t offset = sPos;  
+
+  while (*srcStr)
+  {
+    SLCD_DrawChar(*srcStr++,offset);        
+    offset += CHAR_SIZE_SEGMENT;  
+  }
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_RadioSighOn (void)
+{
+  LCD->WF[0]  |= (1 << (BP_0 + 8));  /*FrontPlane: LCD_P1. BackPlane: 0*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_USBSighOn (void)
+{
+  LCD->WF[0]  |= (1 << (BP_1 + 8));  /*FrontPlane: LCD_P1. BackPlane: 1*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_ClockSighOn (void)
+{
+  LCD->WF[0]  |= (1 << (BP_3 + 8));  /*FrontPlane: LCD_P1. BackPlane: 3*/
+}
+
+/*******************************************************************************
+* Freescale Logo Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_FreescaleLogoOn (void)
+{
+  LCD->WF[0]  |= (1 << (BP_4 + 8));	 /*FrontPlane: LCD_P1. BackPlane: 4*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_JLinkSignOn (void)
+{
+  LCD->WF[0]  |= (1 << (BP_5 + 8));  /*FrontPlane: LCD_P1. BackPlane: 5*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_BatterySignOn (int level)
+{
+  LCD->WF[0]  |= (1 << (BP_6 + 8));  /*FrontPlane: LCD_P1. BackPlane: 6*/
+  if(level == 0)
+  {
+	LCD->WF[0]  &= ~(1 << (BP_7 + 8 )); /*FrontPlane: LCD_P1. BackPlane: 0*/
+    LCD->WF[9]  &= ~(1 << (BP_6 + 24)); /*BackPlane:*/
+	LCD->WF[9]  &= ~(1 << (BP_7 + 24));/*BackPlane:*/ 
+  }
+  if(level == 1)
+  {
+    LCD->WF[0]  &= ~(1 << (BP_7 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
+    LCD->WF[9]  &= ~(1 << (BP_6 + 24)); /*BackPlane:*/
+	LCD->WF[9]  |=  (1 << (BP_7 + 24)); /*BackPlane:*/ 
+  }
+  if(level == 2)
+  {
+    LCD->WF[0]  &= ~(1 << (BP_7 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
+    LCD->WF[9]  |=  (1 << (BP_6 + 24)); /*BackPlane:*/
+	LCD->WF[9]  |=  (1 << (BP_7 + 24)); /*BackPlane:*/ 
+  }
+  if(level == 3)
+  {
+    LCD->WF[0]  |=  (1 << (BP_7 + 8));  /*FrontPlane: LCD_P1. BackPlane: 6*/
+    LCD->WF[9]  |=  (1 << (BP_6 + 24)); /*BackPlane:*/
+	LCD->WF[9]  |=  (1 << (BP_7 + 24)); /*BackPlane:*/ 
+  }
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_RadioSighOff (void)
+{
+  LCD->WF[0]  &= ~(1 << (BP_0 + 8)); /*FrontPlane: LCD_P1. BackPlane: 0*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_USBSighOff (void)
+{
+  LCD->WF[0]  &= ~(1 << (BP_1 + 8)); /*FrontPlane: LCD_P1. BackPlane: 1*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment On
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_ClockSighOff (void)
+{
+  LCD->WF[0]  &= ~(1 << (BP_3 + 8)); /*FrontPlane: LCD_P1. BackPlane: 3*/
+}
+
+/*******************************************************************************
+* Freescale Logo Segment Off
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_FreescaleLogoOff (void)
+{
+  LCD->WF[0]  &= ~(1 << (BP_4 + 8)); /*FrontPlane: LCD_P1. BackPlane: 4*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment Off
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_JLinkSignOff (void)
+{
+  LCD->WF[0]  &= ~(1 << (BP_5 + 8)); /*FrontPlane: LCD_P1. BackPlane: 5*/
+}
+
+/*******************************************************************************
+* JLink Sign Segment Off
+*   Parameter:    None
+*   Return:                                                                    *
+*******************************************************************************/
+void SLCD_BatterySignOff (void)
+{
+  LCD->WF[0]  &= ~(1 << (BP_6 + 8));  /*FrontPlane: LCD_P1. BackPlane: 5*/
+  LCD->WF[0]  &= ~(1 << (BP_7 + 8));  /*FrontPlane: LCD_P1. BackPlane: 7*/
+  LCD->WF[9]  &= ~(1 << (BP_6 + 24)); /*BackPlane:*/
+  LCD->WF[9]  &= ~(1 << (BP_7 + 24)); /*BackPlane:*/ 
+}
+
+// end file ----------------------------------------------------------------------------

bsp/PK40X256VLQ100/bsp/SLCD_Driver.h

@@ -0,0 +1,69 @@
+/**************************************************************************//**
+ * @file     SLCD_Driver.h
+ * @brief    SLCD Low Level Driver function prototypes and defines
+ * @version  V0.01
+ * @date     13. May 2011
+ *
+ * @note
+ * Copyright (C) 2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+#ifndef _SLCD_DRIVER_H
+#define _SLCD_DRIVER_H
+
+
+#define CHAR_SIZE_COLUMN       5
+#define CHAR_SIZE_ROW          7
+#define CHAR_SIZE_SEGMENT      6
+
+#define CHAR_SIZE             35 
+
+
+typedef enum
+{
+  BP_0 = 0,
+  BP_1,
+  BP_2,
+  BP_3,
+  BP_4,
+  BP_5,
+  BP_6,
+  BP_7  
+} BackPlaneNumber;
+
+
+extern void SLCD_Configuration (void);
+extern void SLCD_SegmentsAllOff(void); 
+extern void SLCD_SegmentsAllOn(void); 
+extern void SLCD_DrawChar(rt_uint8_t in, rt_uint8_t fploc);
+extern void SLCD_PrintString (rt_uint8_t *  srcStr, rt_uint8_t sPos);
+
+extern void SLCD_RadioSighOn(void);
+extern void SLCD_USBSighOn(void);
+extern void SLCD_FreescaleLogoOn(void);
+extern void SLCD_JLinkSignOn(void);
+extern void SLCD_ClockSighOn(void);
+extern void SLCD_BatterySignOn(int level);
+
+extern void SLCD_RadioSighOff(void); 
+extern void SLCD_USBSighOff(void); 
+extern void SLCD_FreescaleLogoOff(void);
+extern void SLCD_JLinkSignOff(void);
+extern void SLCD_ClockSighOff(void); 
+extern void SLCD_BatterySignOff(void); 
+
+#endif /* _SLCD_DRIVER_H */

bsp/PK40X256VLQ100/rtconfig.h

@@ -0,0 +1,67 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	4
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX*/
+#define RT_THREAD_PRIORITY_MAX	8
+
+/* Tick per Second*/
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug*/
+/* #define RT_THREAD_DEBUG */
+
+/* Using Hook*/
+/* #define RT_USING_HOOK */
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex*/
+/* #define RT_USING_MUTEX */
+
+/* Using Event*/
+/* #define RT_USING_EVENT */
+
+/* Using MailBox*/
+#define RT_USING_MAILBOX
+
+/* Using Message Queue*/
+/* #define RT_USING_MESSAGEQUEUE */
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+/* #define RT_USING_MEMPOOL */
+
+/* Using Dynamic Heap Management*/
+/* #define RT_USING_HEAP */
+
+/* Using Small MM*/
+#define RT_USING_SMALL_MEM
+#define RT_USING_TINY_SIZE
+
+/* SECTION: Device System */
+/* Using Device System */
+//#define RT_USING_DEVICE
+
+/* buffer size for UART reception */
+//#define RT_UART_RX_BUFFER_SIZE	64
+
+/* Using UART */
+//#define RT_USING_UART
+
+/* SECTION: Console options */
+/* use console for rt_kprintf */
+//#define RT_USING_CONSOLE
+/* the buffer size of console */
+//#define RT_CONSOLEBUF_SIZE	80
+
+#endif

bsp/PK40X256VLQ100/startup.c

@@ -0,0 +1,116 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-01-25     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#ifdef RT_USING_UART
+#include "uart.h"
+#endif
+
+/**
+ * @addtogroup sam7s
+ */
+
+/*@{*/
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#endif
+
+#ifdef __GNUC__
+extern unsigned char __bss_start;
+extern unsigned char __bss_end;
+#endif
+
+extern void rt_hw_interrupt_init(void);
+extern int  rt_application_init(void);
+#ifdef RT_USING_DEVICE
+extern rt_err_t rt_hw_serial_init(void);
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init kernel object */
+	rt_system_object_init();
+
+	/* init board */
+	rt_hw_board_init();
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+#ifdef __CC_ARM
+	rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)0x204000);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void*)0x204000);
+#else
+	rt_system_heap_init((void*)&__bss_end, (void*)0x204000);
+#endif
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+#ifdef RT_USING_HOOK /* if the hook is used */
+	/* set idle thread hook */
+	rt_thread_idle_sethook(rt_hw_led_flash);
+#endif
+
+#ifdef RT_USING_DEVICE
+	/* init all device */
+	rt_device_init_all();
+#endif
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device("uart1");
+#endif
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main (void)
+{
+	rt_uint32_t UNUSED level;
+
+	/* disable interrupt first */
+	level = rt_hw_interrupt_disable();
+
+	/* invoke rtthread_startup */
+	rtthread_startup();
+	while(1);	
+	return 0;
+}
+
+/*@}*/

bsp/PK40X256VLQ100/uart.c

@@ -0,0 +1,295 @@
+/****************************************************************************
+ *   $Id:: uart.c 3736 2010-06-24 02:07:03Z usb00423                        $
+ *   Project: NXP LPC122x UART example
+ *
+ *   Description:
+ *     This file contains UART code example which include UART 
+ *     initialization, UART interrupt handler, and related APIs for 
+ *     UART access.
+ *
+ ****************************************************************************
+ * Software that is described herein is for illustrative purposes only
+ * which provides customers with programming information regarding the
+ * products. This software is supplied "AS IS" without any warranties.
+ * NXP Semiconductors assumes no responsibility or liability for the
+ * use of the software, conveys no license or title under any patent,
+ * copyright, or mask work right to the product. NXP Semiconductors
+ * reserves the right to make changes in the software without
+ * notification. NXP Semiconductors also make no representation or
+ * warranty that such application will be suitable for the specified
+ * use without further testing or modification.
+****************************************************************************/
+#include <rthw.h>
+#include <rtthread.h>
+#include <CMSIS/LPC122x.h>
+
+#include "uart.h"
+
+#define IER_RBR		0x01
+#define IER_THRE	0x02
+#define IER_RLS		0x04
+
+#define IIR_PEND	0x01
+#define IIR_RLS		0x03
+#define IIR_RDA		0x02
+#define IIR_CTI		0x06
+#define IIR_THRE	0x01
+
+#define LSR_RDR		0x01
+#define LSR_OE		0x02
+#define LSR_PE		0x04
+#define LSR_FE		0x08
+#define LSR_BI		0x10
+#define LSR_THRE	0x20
+#define LSR_TEMT	0x40
+#define LSR_RXFE	0x80
+
+/**
+ * @addtogroup LPC11xx
+ */
+
+/*@{*/
+#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
+
+#define UART_BAUDRATE   115200
+
+struct rt_uart_lpc
+{
+	struct rt_device parent;
+
+	/* buffer for reception */
+	rt_uint8_t read_index, save_index;
+	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+}uart_device;
+
+void UART0_IRQHandler(void)
+{
+	rt_ubase_t level, iir;
+	struct rt_uart_lpc* uart = &uart_device;
+
+	/* read IIR and clear it */
+	iir = LPC_UART0->IIR;
+
+	iir >>= 0x01;		/* skip pending bit in IIR */
+	iir  &= 0x07;		/* check bit 1~3, interrupt identification */
+
+	if (iir == IIR_RDA)	/* Receive Line Status */
+	{
+		/* If no error on RLS, normal ready, save into the data buffer. */
+		/* Note: read RBR will clear the interrupt */
+		uart->rx_buffer[uart->save_index] = LPC_UART0->RBR;
+		level = rt_hw_interrupt_disable();
+		uart->save_index ++;
+		if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+	   		uart->save_index = 0;
+		rt_hw_interrupt_enable(level);
+		/* invoke callback */
+		if(uart->parent.rx_indicate != RT_NULL)
+		{
+		    rt_size_t length;
+		    if (uart->read_index > uart->save_index)
+	            length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+	        else
+	            length = uart->save_index - uart->read_index;
+	
+	        uart->parent.rx_indicate(&uart->parent, length);
+		}
+	}
+	return;
+}
+
+/*****************************************************************************
+** Function name:		rt_uart_init
+** Descriptions:		
+** parameters:			dev
+** Returned value:		None
+*****************************************************************************/
+static rt_err_t rt_uart_init(rt_device_t dev)
+{
+	rt_uint32_t Fdiv;
+	rt_uint32_t regVal;
+
+	NVIC_DisableIRQ(UART0_IRQn);
+	
+	/* Init UART Hardware */
+	LPC_IOCON->PIO0_1  &= ~0x07;		/* UART I/O config */
+	LPC_IOCON->PIO0_1  |=  0x02;		/* UART RXD */
+	LPC_IOCON->PIO0_2  &= ~0x07;	
+	LPC_IOCON->PIO0_2  |=  0x02;		/* UART TXD */
+	
+	/* Enable UART clock */
+	LPC_SYSCON->PRESETCTRL    |= (0x1<<2);
+	LPC_SYSCON->SYSAHBCLKCTRL |= (0x1<<12);
+	LPC_SYSCON->UART0CLKDIV    =  0x1;	/* divided by 1 */
+	
+	LPC_UART0->LCR = 0x83;				/* 8 bits, no Parity, 1 Stop bit */
+	regVal = LPC_SYSCON->UART0CLKDIV;
+	Fdiv = ((SystemAHBFrequency/regVal)/16)/UART_BAUDRATE ;	/*baud rate */
+	
+	LPC_UART0->DLM = Fdiv / 256;							
+	LPC_UART0->DLL = Fdiv % 256;
+	LPC_UART0->LCR = 0x03;				/* DLAB = 0 */
+	LPC_UART0->FCR = 0x07;				/* Enable and reset TX and RX FIFO. */
+	
+	/* Read to clear the line status. */
+	regVal = LPC_UART0->LSR;
+	
+	/* Ensure a clean start, no data in either TX or RX FIFO. */
+	while ( LPC_UART0->LSR & (LSR_THRE|LSR_TEMT) != (LSR_THRE|LSR_TEMT) );
+	while ( LPC_UART0->LSR & LSR_RDR )
+	{
+		regVal = LPC_UART0->RBR;		/* Dump data from RX FIFO */
+	}
+ 
+	/* Enable the UART Interrupt */
+	NVIC_EnableIRQ(UART0_IRQn);
+	
+	LPC_UART0->IER = IER_RBR | IER_THRE | IER_RLS;	/* Enable UART interrupt */
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	RT_ASSERT(dev != RT_NULL);
+	if(dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* Enable the UART Interrupt */
+		NVIC_EnableIRQ(UART0_IRQn);
+	}
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_close(rt_device_t dev)
+{
+	RT_ASSERT(dev != RT_NULL);
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* Disable the UART Interrupt */
+		NVIC_DisableIRQ(UART0_IRQn);
+	}
+
+	return RT_EOK;
+}
+static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+	RT_ASSERT(uart != RT_NULL);
+
+	/* point to buffer */
+	ptr = (rt_uint8_t*) buffer;
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		while (size)
+		{
+			/* interrupt receive */
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+			if (uart->read_index != uart->save_index)
+			{
+				*ptr = uart->rx_buffer[uart->read_index];
+
+				uart->read_index ++;
+				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+					uart->read_index = 0;
+			}
+			else
+			{
+				/* no data in rx buffer */
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+
+			ptr ++;
+			size --;
+		}
+
+		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+	}
+
+	return 0;
+}
+
+static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	char *ptr;
+	ptr = (char*)buffer;
+
+	if (dev->flag & RT_DEVICE_FLAG_STREAM)
+	{
+		/* stream mode */
+		while (size)
+		{
+			if (*ptr == '\n')
+			{
+				/* THRE status, contain valid data */
+				while ( !(LPC_UART0->LSR & LSR_THRE) );
+				/* write data */
+				LPC_UART0->THR = '\r';
+			}
+
+			/* THRE status, contain valid data */
+			while ( !(LPC_UART0->LSR & LSR_THRE) );	
+			/* write data */
+			LPC_UART0->THR = *ptr;
+			
+			ptr ++;
+			size --;
+		}
+	}
+	else
+	{
+	while ( size != 0 )
+	{
+		/* THRE status, contain valid data */
+		while ( !(LPC_UART0->LSR & LSR_THRE) );
+
+		/* write data */
+		LPC_UART0->THR = *ptr;
+
+		ptr++;
+		size--;
+	}
+	}
+
+	return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+void rt_hw_uart_init(void)
+{
+	struct rt_uart_lpc* uart;
+
+	/* get uart device */
+	uart = &uart_device;
+
+	/* device initialization */
+	uart->parent.type = RT_Device_Class_Char;
+	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+	uart->read_index = uart->save_index = 0;
+
+	/* device interface */
+	uart->parent.init 	    = rt_uart_init;
+	uart->parent.open 	    = rt_uart_open;
+	uart->parent.close      = rt_uart_close;
+	uart->parent.read 	    = rt_uart_read;
+	uart->parent.write      = rt_uart_write;
+	uart->parent.control    = RT_NULL;
+	uart->parent.user_data  = RT_NULL;
+
+	rt_device_register(&uart->parent,
+		"uart", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+}
+
+#endif
+
+/******************************************************************************
+**                            End Of File
+******************************************************************************/

bsp/PK40X256VLQ100/uart.h

@@ -0,0 +1,6 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+void rt_hw_uart_init(void);
+
+#endif

libcpu/arm/PK40X25VLQ100/PK40X256VLQ100.h

@@ -0,0 +1,9329 @@
+/*
+** ###################################################################
+**     Processor:           PK40X256VLQ100
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU ARM C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    K40P144M100SF2RM, Rev. 3, 4 Nov 2010
+**     Version:             rev. 1.6, 2011-01-14
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK40N512MD100
+**
+**     Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 0.1 (2010-09-29)
+**         Initial version
+**     - rev. 1.0 (2010-10-15)
+**         First public version
+**     - rev. 1.1 (2010-10-27)
+**         Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
+**         ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
+**         CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
+**         CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
+**         CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE.
+**         CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx.
+**         DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE.
+**         DMA - Peripheral base pointer macro renamed from eDMA to DMA.
+**         GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
+**         LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE.
+**         LCD - Peripheral base pointer macro renamed from SLCD to LCD.
+**         PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
+**         RFSYS - System regfile registers have been added (#MTWX43999)
+**         RFVBAT - VBAT  regfile registers have been added (#MTWX43999)
+**         RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
+**         TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
+**         USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE.
+**         USB - Peripheral base pointer macro renamed from USBOTG0 to USB0.
+**         VREF - Peripheral register TRM removed.
+**     - rev. 1.2 (2010-11-11)
+**         Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
+**         CAN - Individual Matching Element Update (IMEU) feature has been removed.
+**         CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
+**         CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
+**         CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
+**         NV - Fixed offset address of BACKKEYx, FPROTx registers.
+**         TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
+**     - rev. 1.3 (2010-11-19)
+**         CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed.
+**         CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed.
+**     - rev. 1.4 (2010-11-30)
+**         EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
+**     - rev. 1.5 (2010-12-17)
+**         AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
+**     - rev. 1.6 (2011-01-14)
+**         Added BITBAND_REG() macro to provide access to register bits using bit band region.
+**
+** ###################################################################
+*/
+
+/*! \file PK40X256VLQ100.h */
+/*! \version 1.6 */
+/*! \date 2011-01-14 */
+/*! \brief CMSIS Peripheral Access Layer for PK40X256VLQ100 */
+/*! \detailed CMSIS Peripheral Access Layer for PK40X256VLQ100 */
+
+#if !defined(PK40X256VLQ100)
+#define PK40X256VLQ100_H_                         /*!< Symbol preventing repeated inclusion */
+
+/*! Memory map version 1.6 */
+#define MCU_MEM_MAP_VERSION 0x0106u
+
+/*!
+ * \def BITBAND_REG(reg,bit)
+ * \brief Macro to access a single bit of a peripheral register (bit band region 0x40000000 to 0x400FFFFF) using the bit-band alias region access.
+ * \param Reg Register to access
+ * \param Bit Bit number to access
+ * \return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG(Reg,Bit) (*((uint32_t volatile*)(0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup Interrupt_vector_numbers Interrupt vector numbers */
+/*! \{ */
+
+/*! Interrupt Number Definitions */
+typedef enum IRQn {
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /*!< Non Maskable Interrupt */
+  MemoryManagement_IRQn        = -12,              /*!< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /*!< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /*!< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /*!< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /*!< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /*!< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /*!< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /*!< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /*!< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /*!< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /*!< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /*!< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /*!< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /*!< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /*!< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /*!< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /*!< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /*!< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /*!< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /*!< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /*!< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /*!< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /*!< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /*!< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /*!< Normal Interrupt */
+  FTFL_IRQn                    = 18,               /*!< FTFL Interrupt */
+  Read_Collision_IRQn          = 19,               /*!< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /*!< Low Voltage Detect, Low Voltage Warning */
+  LLW_IRQn                     = 21,               /*!< Low Leakage Wakeup */
+  Watchdog_IRQn                = 22,               /*!< WDOG Interrupt */
+  Reserved39_IRQn              = 23,               /*!< Reserved interrupt 39 */
+  I2C0_IRQn                    = 24,               /*!< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /*!< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /*!< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /*!< SPI1 Interrupt */
+  SPI2_IRQn                    = 28,               /*!< SPI2 Interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 29,              /*!< CAN0 OR'd Message Buffers Interrupt */
+  CAN0_Bus_Off_IRQn            = 30,               /*!< CAN0 Bus Off Interrupt */
+  CAN0_Error_IRQn              = 31,               /*!< CAN0 Error Interrupt */
+  CAN0_Tx_Warning_IRQn         = 32,               /*!< CAN0 Tx Warning Interrupt */
+  CAN0_Rx_Warning_IRQn         = 33,               /*!< CAN0 Rx Warning Interrupt */
+  CAN0_Wake_Up_IRQn            = 34,               /*!< CAN0 Wake Up Interrupt */
+  Reserved51_IRQn              = 35,               /*!< Reserved interrupt 51 */
+  Reserved52_IRQn              = 36,               /*!< Reserved interrupt 52 */
+  CAN1_ORed_Message_buffer_IRQn = 37,              /*!< CAN1 OR'd Message Buffers Interrupt */
+  CAN1_Bus_Off_IRQn            = 38,               /*!< CAN1 Bus Off Interrupt */
+  CAN1_Error_IRQn              = 39,               /*!< CAN1 Error Interrupt */
+  CAN1_Tx_Warning_IRQn         = 40,               /*!< CAN1 Tx Warning Interrupt */
+  CAN1_Rx_Warning_IRQn         = 41,               /*!< CAN1 Rx Warning Interrupt */
+  CAN1_Wake_Up_IRQn            = 42,               /*!< CAN1 Wake Up Interrupt */
+  Reserved59_IRQn              = 43,               /*!< Reserved interrupt 59 */
+  Reserved60_IRQn              = 44,               /*!< Reserved interrupt 60 */
+  UART0_RX_TX_IRQn             = 45,               /*!< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 46,               /*!< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 47,               /*!< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 48,               /*!< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 49,               /*!< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 50,               /*!< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 51,               /*!< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 52,               /*!< UART3 Error interrupt */
+  UART4_RX_TX_IRQn             = 53,               /*!< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 54,               /*!< UART4 Error interrupt */
+  UART5_RX_TX_IRQn             = 55,               /*!< UART5 Receive/Transmit interrupt */
+  UART5_ERR_IRQn               = 56,               /*!< UART5 Error interrupt */
+  ADC0_IRQn                    = 57,               /*!< ADC0 interrupt */
+  ADC1_IRQn                    = 58,               /*!< ADC1 interrupt */
+  CMP0_IRQn                    = 59,               /*!< CMP0 interrupt */
+  CMP1_IRQn                    = 60,               /*!< CMP1 interrupt */
+  CMP2_IRQn                    = 61,               /*!< CMP2 interrupt */
+  FTM0_IRQn                    = 62,               /*!< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 63,               /*!< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 64,               /*!< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 65,               /*!< CMT interrupt */
+  RTC_IRQn                     = 66,               /*!< RTC interrupt */
+  Reserved83_IRQn              = 67,               /*!< Reserved interrupt 83 */
+  PIT0_IRQn                    = 68,               /*!< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 69,               /*!< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 70,               /*!< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 71,               /*!< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 72,               /*!< PDB0 Interrupt */
+  USB0_IRQn                    = 73,               /*!< USB0 interrupt */
+  USBDCD_IRQn                  = 74,               /*!< USBDCD Interrupt */
+  Reserved91_IRQn              = 75,               /*!< Reserved interrupt 91 */
+  Reserved92_IRQn              = 76,               /*!< Reserved interrupt 92 */
+  Reserved93_IRQn              = 77,               /*!< Reserved interrupt 93 */
+  Reserved94_IRQn              = 78,               /*!< Reserved interrupt 94 */
+  I2S0_IRQn                    = 79,               /*!< I2S0 Interrupt */
+  SDHC_IRQn                    = 80,               /*!< SDHC Interrupt */
+  DAC0_IRQn                    = 81,               /*!< DAC0 interrupt */
+  DAC1_IRQn                    = 82,               /*!< DAC1 interrupt */
+  TSI0_IRQn                    = 83,               /*!< TSI0 Interrupt */
+  MCG_IRQn                     = 84,               /*!< MCG Interrupt */
+  LPTimer_IRQn                 = 85,               /*!< LPTimer interrupt */
+  LCD_IRQn                     = 86,               /*!< Segment LCD Interrupt */
+  PORTA_IRQn                   = 87,               /*!< Port A interrupt */
+  PORTB_IRQn                   = 88,               /*!< Port B interrupt */
+  PORTC_IRQn                   = 89,               /*!< Port C interrupt */
+  PORTD_IRQn                   = 90,               /*!< Port D interrupt */
+  PORTE_IRQn                   = 91,               /*!< Port E interrupt */
+  Reserved108_IRQn             = 92,               /*!< Reserved interrupt 108 */
+  Reserved109_IRQn             = 93,               /*!< Reserved interrupt 109 */
+  Reserved110_IRQn             = 94,               /*!< Reserved interrupt 110 */
+  Reserved111_IRQn             = 95,               /*!< Reserved interrupt 111 */
+  Reserved112_IRQn             = 96,               /*!< Reserved interrupt 112 */
+  Reserved113_IRQn             = 97,               /*!< Reserved interrupt 113 */
+  Reserved114_IRQn             = 98,               /*!< Reserved interrupt 114 */
+  Reserved115_IRQn             = 99,               /*!< Reserved interrupt 115 */
+  Reserved116_IRQn             = 100,              /*!< Reserved interrupt 116 */
+  Reserved117_IRQn             = 101,              /*!< Reserved interrupt 117 */
+  Reserved118_IRQn             = 102,              /*!< Reserved interrupt 118 */
+  Reserved119_IRQn             = 103               /*!< Reserved interrupt 119 */
+} IRQn_Type;
+
+/*! \} */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration */
+/*! \{ */
+
+#define __MPU_PRESENT                  0         /*!< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /*!< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /*!< Vendor specific implementation of SysTickConfig is defined */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_PK40X256VLQ100.h"     /* Device specific configuration file */
+
+/*! \} */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup Peripheral_access_layer Device Peripheral Access Layer */
+/*! \{ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer */
+/*! \{ */
+
+/*! ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /*!< ADC status and control registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /*!< ADC configuration register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /*!< Configuration register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /*!< ADC data result register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /*!< Compare value registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /*!< Compare value registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /*!< Status and control register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /*!< Status and control register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /*!< ADC offset correction register, offset: 0x28 */
+  __IO uint32_t PG;                                /*!< ADC plus-side gain register, offset: 0x2C */
+  __IO uint32_t MG;                                /*!< ADC minus-side gain register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /*!< ADC plus-side general calibration value register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /*!< ADC plus-side general calibration value register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /*!< ADC plus-side general calibration value register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /*!< ADC plus-side general calibration value register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /*!< ADC plus-side general calibration value register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /*!< ADC plus-side general calibration value register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /*!< ADC plus-side general calibration value register, offset: 0x4C */
+  __IO uint32_t PGA;                               /*!< ADC PGA register, offset: 0x50 */
+  __IO uint32_t CLMD;                              /*!< ADC minus-side general calibration value register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /*!< ADC minus-side general calibration value register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /*!< ADC minus-side general calibration value register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /*!< ADC minus-side general calibration value register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /*!< ADC minus-side general calibration value register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /*!< ADC minus-side general calibration value register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /*!< ADC minus-side general calibration value register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup ADC_Register_Masks ADC Register Masks */
+/*! \{ */
+
+/* SC1 Bit Fields */
+#define ADC_SC1_ADCH_MASK                        0x1Fu
+#define ADC_SC1_ADCH_SHIFT                       0
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        0x20u
+#define ADC_SC1_DIFF_SHIFT                       5
+#define ADC_SC1_AIEN_MASK                        0x40u
+#define ADC_SC1_AIEN_SHIFT                       6
+#define ADC_SC1_COCO_MASK                        0x80u
+#define ADC_SC1_COCO_SHIFT                       7
+/* CFG1 Bit Fields */
+#define ADC_CFG1_ADICLK_MASK                     0x3u
+#define ADC_CFG1_ADICLK_SHIFT                    0
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       0xCu
+#define ADC_CFG1_MODE_SHIFT                      2
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     0x10u
+#define ADC_CFG1_ADLSMP_SHIFT                    4
+#define ADC_CFG1_ADIV_MASK                       0x60u
+#define ADC_CFG1_ADIV_SHIFT                      5
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      0x80u
+#define ADC_CFG1_ADLPC_SHIFT                     7
+/* CFG2 Bit Fields */
+#define ADC_CFG2_ADLSTS_MASK                     0x3u
+#define ADC_CFG2_ADLSTS_SHIFT                    0
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      0x4u
+#define ADC_CFG2_ADHSC_SHIFT                     2
+#define ADC_CFG2_ADACKEN_MASK                    0x8u
+#define ADC_CFG2_ADACKEN_SHIFT                   3
+#define ADC_CFG2_MUXSEL_MASK                     0x10u
+#define ADC_CFG2_MUXSEL_SHIFT                    4
+/* R Bit Fields */
+#define ADC_R_D_MASK                             0xFFFFu
+#define ADC_R_D_SHIFT                            0
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
+/* CV1 Bit Fields */
+#define ADC_CV1_CV_MASK                          0xFFFFu
+#define ADC_CV1_CV_SHIFT                         0
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
+/* CV2 Bit Fields */
+#define ADC_CV2_CV_MASK                          0xFFFFu
+#define ADC_CV2_CV_SHIFT                         0
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
+/* SC2 Bit Fields */
+#define ADC_SC2_REFSEL_MASK                      0x3u
+#define ADC_SC2_REFSEL_SHIFT                     0
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       0x4u
+#define ADC_SC2_DMAEN_SHIFT                      2
+#define ADC_SC2_ACREN_MASK                       0x8u
+#define ADC_SC2_ACREN_SHIFT                      3
+#define ADC_SC2_ACFGT_MASK                       0x10u
+#define ADC_SC2_ACFGT_SHIFT                      4
+#define ADC_SC2_ACFE_MASK                        0x20u
+#define ADC_SC2_ACFE_SHIFT                       5
+#define ADC_SC2_ADTRG_MASK                       0x40u
+#define ADC_SC2_ADTRG_SHIFT                      6
+#define ADC_SC2_ADACT_MASK                       0x80u
+#define ADC_SC2_ADACT_SHIFT                      7
+/* SC3 Bit Fields */
+#define ADC_SC3_AVGS_MASK                        0x3u
+#define ADC_SC3_AVGS_SHIFT                       0
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        0x4u
+#define ADC_SC3_AVGE_SHIFT                       2
+#define ADC_SC3_ADCO_MASK                        0x8u
+#define ADC_SC3_ADCO_SHIFT                       3
+#define ADC_SC3_CALF_MASK                        0x40u
+#define ADC_SC3_CALF_SHIFT                       6
+#define ADC_SC3_CAL_MASK                         0x80u
+#define ADC_SC3_CAL_SHIFT                        7
+/* OFS Bit Fields */
+#define ADC_OFS_OFS_MASK                         0xFFFFu
+#define ADC_OFS_OFS_SHIFT                        0
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
+/* PG Bit Fields */
+#define ADC_PG_PG_MASK                           0xFFFFu
+#define ADC_PG_PG_SHIFT                          0
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
+/* MG Bit Fields */
+#define ADC_MG_MG_MASK                           0xFFFFu
+#define ADC_MG_MG_SHIFT                          0
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
+/* CLPD Bit Fields */
+#define ADC_CLPD_CLPD_MASK                       0x3Fu
+#define ADC_CLPD_CLPD_SHIFT                      0
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
+/* CLPS Bit Fields */
+#define ADC_CLPS_CLPS_MASK                       0x3Fu
+#define ADC_CLPS_CLPS_SHIFT                      0
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
+/* CLP4 Bit Fields */
+#define ADC_CLP4_CLP4_MASK                       0x3FFu
+#define ADC_CLP4_CLP4_SHIFT                      0
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
+/* CLP3 Bit Fields */
+#define ADC_CLP3_CLP3_MASK                       0x1FFu
+#define ADC_CLP3_CLP3_SHIFT                      0
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
+/* CLP2 Bit Fields */
+#define ADC_CLP2_CLP2_MASK                       0xFFu
+#define ADC_CLP2_CLP2_SHIFT                      0
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
+/* CLP1 Bit Fields */
+#define ADC_CLP1_CLP1_MASK                       0x7Fu
+#define ADC_CLP1_CLP1_SHIFT                      0
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
+/* CLP0 Bit Fields */
+#define ADC_CLP0_CLP0_MASK                       0x3Fu
+#define ADC_CLP0_CLP0_SHIFT                      0
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
+/* PGA Bit Fields */
+#define ADC_PGA_PGAG_MASK                        0xF0000u
+#define ADC_PGA_PGAG_SHIFT                       16
+#define ADC_PGA_PGAG(x)                          (((uint32_t)(((uint32_t)(x))<<ADC_PGA_PGAG_SHIFT))&ADC_PGA_PGAG_MASK)
+#define ADC_PGA_PGAEN_MASK                       0x800000u
+#define ADC_PGA_PGAEN_SHIFT                      23
+/* CLMD Bit Fields */
+#define ADC_CLMD_CLMD_MASK                       0x3Fu
+#define ADC_CLMD_CLMD_SHIFT                      0
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
+/* CLMS Bit Fields */
+#define ADC_CLMS_CLMS_MASK                       0x3Fu
+#define ADC_CLMS_CLMS_SHIFT                      0
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
+/* CLM4 Bit Fields */
+#define ADC_CLM4_CLM4_MASK                       0x3FFu
+#define ADC_CLM4_CLM4_SHIFT                      0
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
+/* CLM3 Bit Fields */
+#define ADC_CLM3_CLM3_MASK                       0x1FFu
+#define ADC_CLM3_CLM3_SHIFT                      0
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
+/* CLM2 Bit Fields */
+#define ADC_CLM2_CLM2_MASK                       0xFFu
+#define ADC_CLM2_CLM2_SHIFT                      0
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
+/* CLM1 Bit Fields */
+#define ADC_CLM1_CLM1_MASK                       0x7Fu
+#define ADC_CLM1_CLM1_SHIFT                      0
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
+/* CLM0 Bit Fields */
+#define ADC_CLM0_CLM0_MASK                       0x3Fu
+#define ADC_CLM0_CLM0_SHIFT                      0
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
+
+/*! \} */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/*! Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/*! Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/*! Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/*! Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+
+/*! \} */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer */
+/*! \{ */
+
+/*! AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /*!< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /*!< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /*!< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /*!< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /*!< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /*!< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /*!< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /*!< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /*!< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /*!< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /*!< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /*!< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /*!< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /*!< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /*!< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /*!< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /*!< Peripheral Access Control Register, offset: 0x6C */
+} AIPS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup AIPS_Register_Masks AIPS Register Masks */
+/*! \{ */
+
+/* MPRA Bit Fields */
+#define AIPS_MPRA_MPL5_MASK                      0x100u
+#define AIPS_MPRA_MPL5_SHIFT                     8
+#define AIPS_MPRA_MTW5_MASK                      0x200u
+#define AIPS_MPRA_MTW5_SHIFT                     9
+#define AIPS_MPRA_MTR5_MASK                      0x400u
+#define AIPS_MPRA_MTR5_SHIFT                     10
+#define AIPS_MPRA_MPL4_MASK                      0x1000u
+#define AIPS_MPRA_MPL4_SHIFT                     12
+#define AIPS_MPRA_MTW4_MASK                      0x2000u
+#define AIPS_MPRA_MTW4_SHIFT                     13
+#define AIPS_MPRA_MTR4_MASK                      0x4000u
+#define AIPS_MPRA_MTR4_SHIFT                     14
+#define AIPS_MPRA_MPL2_MASK                      0x100000u
+#define AIPS_MPRA_MPL2_SHIFT                     20
+#define AIPS_MPRA_MTW2_MASK                      0x200000u
+#define AIPS_MPRA_MTW2_SHIFT                     21
+#define AIPS_MPRA_MTR2_MASK                      0x400000u
+#define AIPS_MPRA_MTR2_SHIFT                     22
+#define AIPS_MPRA_MPL1_MASK                      0x1000000u
+#define AIPS_MPRA_MPL1_SHIFT                     24
+#define AIPS_MPRA_MTW1_MASK                      0x2000000u
+#define AIPS_MPRA_MTW1_SHIFT                     25
+#define AIPS_MPRA_MTR1_MASK                      0x4000000u
+#define AIPS_MPRA_MTR1_SHIFT                     26
+#define AIPS_MPRA_MPL0_MASK                      0x10000000u
+#define AIPS_MPRA_MPL0_SHIFT                     28
+#define AIPS_MPRA_MTW0_MASK                      0x20000000u
+#define AIPS_MPRA_MTW0_SHIFT                     29
+#define AIPS_MPRA_MTR0_MASK                      0x40000000u
+#define AIPS_MPRA_MTR0_SHIFT                     30
+/* PACRA Bit Fields */
+#define AIPS_PACRA_TP7_MASK                      0x1u
+#define AIPS_PACRA_TP7_SHIFT                     0
+#define AIPS_PACRA_WP7_MASK                      0x2u
+#define AIPS_PACRA_WP7_SHIFT                     1
+#define AIPS_PACRA_SP7_MASK                      0x4u
+#define AIPS_PACRA_SP7_SHIFT                     2
+#define AIPS_PACRA_TP6_MASK                      0x10u
+#define AIPS_PACRA_TP6_SHIFT                     4
+#define AIPS_PACRA_WP6_MASK                      0x20u
+#define AIPS_PACRA_WP6_SHIFT                     5
+#define AIPS_PACRA_SP6_MASK                      0x40u
+#define AIPS_PACRA_SP6_SHIFT                     6
+#define AIPS_PACRA_TP5_MASK                      0x100u
+#define AIPS_PACRA_TP5_SHIFT                     8
+#define AIPS_PACRA_WP5_MASK                      0x200u
+#define AIPS_PACRA_WP5_SHIFT                     9
+#define AIPS_PACRA_SP5_MASK                      0x400u
+#define AIPS_PACRA_SP5_SHIFT                     10
+#define AIPS_PACRA_TP4_MASK                      0x1000u
+#define AIPS_PACRA_TP4_SHIFT                     12
+#define AIPS_PACRA_WP4_MASK                      0x2000u
+#define AIPS_PACRA_WP4_SHIFT                     13
+#define AIPS_PACRA_SP4_MASK                      0x4000u
+#define AIPS_PACRA_SP4_SHIFT                     14
+#define AIPS_PACRA_TP3_MASK                      0x10000u
+#define AIPS_PACRA_TP3_SHIFT                     16
+#define AIPS_PACRA_WP3_MASK                      0x20000u
+#define AIPS_PACRA_WP3_SHIFT                     17
+#define AIPS_PACRA_SP3_MASK                      0x40000u
+#define AIPS_PACRA_SP3_SHIFT                     18
+#define AIPS_PACRA_TP2_MASK                      0x100000u
+#define AIPS_PACRA_TP2_SHIFT                     20
+#define AIPS_PACRA_WP2_MASK                      0x200000u
+#define AIPS_PACRA_WP2_SHIFT                     21
+#define AIPS_PACRA_SP2_MASK                      0x400000u
+#define AIPS_PACRA_SP2_SHIFT                     22
+#define AIPS_PACRA_TP1_MASK                      0x1000000u
+#define AIPS_PACRA_TP1_SHIFT                     24
+#define AIPS_PACRA_WP1_MASK                      0x2000000u
+#define AIPS_PACRA_WP1_SHIFT                     25
+#define AIPS_PACRA_SP1_MASK                      0x4000000u
+#define AIPS_PACRA_SP1_SHIFT                     26
+#define AIPS_PACRA_TP0_MASK                      0x10000000u
+#define AIPS_PACRA_TP0_SHIFT                     28
+#define AIPS_PACRA_WP0_MASK                      0x20000000u
+#define AIPS_PACRA_WP0_SHIFT                     29
+#define AIPS_PACRA_SP0_MASK                      0x40000000u
+#define AIPS_PACRA_SP0_SHIFT                     30
+/* PACRB Bit Fields */
+#define AIPS_PACRB_TP7_MASK                      0x1u
+#define AIPS_PACRB_TP7_SHIFT                     0
+#define AIPS_PACRB_WP7_MASK                      0x2u
+#define AIPS_PACRB_WP7_SHIFT                     1
+#define AIPS_PACRB_SP7_MASK                      0x4u
+#define AIPS_PACRB_SP7_SHIFT                     2
+#define AIPS_PACRB_TP6_MASK                      0x10u
+#define AIPS_PACRB_TP6_SHIFT                     4
+#define AIPS_PACRB_WP6_MASK                      0x20u
+#define AIPS_PACRB_WP6_SHIFT                     5
+#define AIPS_PACRB_SP6_MASK                      0x40u
+#define AIPS_PACRB_SP6_SHIFT                     6
+#define AIPS_PACRB_TP5_MASK                      0x100u
+#define AIPS_PACRB_TP5_SHIFT                     8
+#define AIPS_PACRB_WP5_MASK                      0x200u
+#define AIPS_PACRB_WP5_SHIFT                     9
+#define AIPS_PACRB_SP5_MASK                      0x400u
+#define AIPS_PACRB_SP5_SHIFT                     10
+#define AIPS_PACRB_TP4_MASK                      0x1000u
+#define AIPS_PACRB_TP4_SHIFT                     12
+#define AIPS_PACRB_WP4_MASK                      0x2000u
+#define AIPS_PACRB_WP4_SHIFT                     13
+#define AIPS_PACRB_SP4_MASK                      0x4000u
+#define AIPS_PACRB_SP4_SHIFT                     14
+#define AIPS_PACRB_TP3_MASK                      0x10000u
+#define AIPS_PACRB_TP3_SHIFT                     16
+#define AIPS_PACRB_WP3_MASK                      0x20000u
+#define AIPS_PACRB_WP3_SHIFT                     17
+#define AIPS_PACRB_SP3_MASK                      0x40000u
+#define AIPS_PACRB_SP3_SHIFT                     18
+#define AIPS_PACRB_TP2_MASK                      0x100000u
+#define AIPS_PACRB_TP2_SHIFT                     20
+#define AIPS_PACRB_WP2_MASK                      0x200000u
+#define AIPS_PACRB_WP2_SHIFT                     21
+#define AIPS_PACRB_SP2_MASK                      0x400000u
+#define AIPS_PACRB_SP2_SHIFT                     22
+#define AIPS_PACRB_TP1_MASK                      0x1000000u
+#define AIPS_PACRB_TP1_SHIFT                     24
+#define AIPS_PACRB_WP1_MASK                      0x2000000u
+#define AIPS_PACRB_WP1_SHIFT                     25
+#define AIPS_PACRB_SP1_MASK                      0x4000000u
+#define AIPS_PACRB_SP1_SHIFT                     26
+#define AIPS_PACRB_TP0_MASK                      0x10000000u
+#define AIPS_PACRB_TP0_SHIFT                     28
+#define AIPS_PACRB_WP0_MASK                      0x20000000u
+#define AIPS_PACRB_WP0_SHIFT                     29
+#define AIPS_PACRB_SP0_MASK                      0x40000000u
+#define AIPS_PACRB_SP0_SHIFT                     30
+/* PACRC Bit Fields */
+#define AIPS_PACRC_TP7_MASK                      0x1u
+#define AIPS_PACRC_TP7_SHIFT                     0
+#define AIPS_PACRC_WP7_MASK                      0x2u
+#define AIPS_PACRC_WP7_SHIFT                     1
+#define AIPS_PACRC_SP7_MASK                      0x4u
+#define AIPS_PACRC_SP7_SHIFT                     2
+#define AIPS_PACRC_TP6_MASK                      0x10u
+#define AIPS_PACRC_TP6_SHIFT                     4
+#define AIPS_PACRC_WP6_MASK                      0x20u
+#define AIPS_PACRC_WP6_SHIFT                     5
+#define AIPS_PACRC_SP6_MASK                      0x40u
+#define AIPS_PACRC_SP6_SHIFT                     6
+#define AIPS_PACRC_TP5_MASK                      0x100u
+#define AIPS_PACRC_TP5_SHIFT                     8
+#define AIPS_PACRC_WP5_MASK                      0x200u
+#define AIPS_PACRC_WP5_SHIFT                     9
+#define AIPS_PACRC_SP5_MASK                      0x400u
+#define AIPS_PACRC_SP5_SHIFT                     10
+#define AIPS_PACRC_TP4_MASK                      0x1000u
+#define AIPS_PACRC_TP4_SHIFT                     12
+#define AIPS_PACRC_WP4_MASK                      0x2000u
+#define AIPS_PACRC_WP4_SHIFT                     13
+#define AIPS_PACRC_SP4_MASK                      0x4000u
+#define AIPS_PACRC_SP4_SHIFT                     14
+#define AIPS_PACRC_TP3_MASK                      0x10000u
+#define AIPS_PACRC_TP3_SHIFT                     16
+#define AIPS_PACRC_WP3_MASK                      0x20000u
+#define AIPS_PACRC_WP3_SHIFT                     17
+#define AIPS_PACRC_SP3_MASK                      0x40000u
+#define AIPS_PACRC_SP3_SHIFT                     18
+#define AIPS_PACRC_TP2_MASK                      0x100000u
+#define AIPS_PACRC_TP2_SHIFT                     20
+#define AIPS_PACRC_WP2_MASK                      0x200000u
+#define AIPS_PACRC_WP2_SHIFT                     21
+#define AIPS_PACRC_SP2_MASK                      0x400000u
+#define AIPS_PACRC_SP2_SHIFT                     22
+#define AIPS_PACRC_TP1_MASK                      0x1000000u
+#define AIPS_PACRC_TP1_SHIFT                     24
+#define AIPS_PACRC_WP1_MASK                      0x2000000u
+#define AIPS_PACRC_WP1_SHIFT                     25
+#define AIPS_PACRC_SP1_MASK                      0x4000000u
+#define AIPS_PACRC_SP1_SHIFT                     26
+#define AIPS_PACRC_TP0_MASK                      0x10000000u
+#define AIPS_PACRC_TP0_SHIFT                     28
+#define AIPS_PACRC_WP0_MASK                      0x20000000u
+#define AIPS_PACRC_WP0_SHIFT                     29
+#define AIPS_PACRC_SP0_MASK                      0x40000000u
+#define AIPS_PACRC_SP0_SHIFT                     30
+/* PACRD Bit Fields */
+#define AIPS_PACRD_TP7_MASK                      0x1u
+#define AIPS_PACRD_TP7_SHIFT                     0
+#define AIPS_PACRD_WP7_MASK                      0x2u
+#define AIPS_PACRD_WP7_SHIFT                     1
+#define AIPS_PACRD_SP7_MASK                      0x4u
+#define AIPS_PACRD_SP7_SHIFT                     2
+#define AIPS_PACRD_TP6_MASK                      0x10u
+#define AIPS_PACRD_TP6_SHIFT                     4
+#define AIPS_PACRD_WP6_MASK                      0x20u
+#define AIPS_PACRD_WP6_SHIFT                     5
+#define AIPS_PACRD_SP6_MASK                      0x40u
+#define AIPS_PACRD_SP6_SHIFT                     6
+#define AIPS_PACRD_TP5_MASK                      0x100u
+#define AIPS_PACRD_TP5_SHIFT                     8
+#define AIPS_PACRD_WP5_MASK                      0x200u
+#define AIPS_PACRD_WP5_SHIFT                     9
+#define AIPS_PACRD_SP5_MASK                      0x400u
+#define AIPS_PACRD_SP5_SHIFT                     10
+#define AIPS_PACRD_TP4_MASK                      0x1000u
+#define AIPS_PACRD_TP4_SHIFT                     12
+#define AIPS_PACRD_WP4_MASK                      0x2000u
+#define AIPS_PACRD_WP4_SHIFT                     13
+#define AIPS_PACRD_SP4_MASK                      0x4000u
+#define AIPS_PACRD_SP4_SHIFT                     14
+#define AIPS_PACRD_TP3_MASK                      0x10000u
+#define AIPS_PACRD_TP3_SHIFT                     16
+#define AIPS_PACRD_WP3_MASK                      0x20000u
+#define AIPS_PACRD_WP3_SHIFT                     17
+#define AIPS_PACRD_SP3_MASK                      0x40000u
+#define AIPS_PACRD_SP3_SHIFT                     18
+#define AIPS_PACRD_TP2_MASK                      0x100000u
+#define AIPS_PACRD_TP2_SHIFT                     20
+#define AIPS_PACRD_WP2_MASK                      0x200000u
+#define AIPS_PACRD_WP2_SHIFT                     21
+#define AIPS_PACRD_SP2_MASK                      0x400000u
+#define AIPS_PACRD_SP2_SHIFT                     22
+#define AIPS_PACRD_TP1_MASK                      0x1000000u
+#define AIPS_PACRD_TP1_SHIFT                     24
+#define AIPS_PACRD_WP1_MASK                      0x2000000u
+#define AIPS_PACRD_WP1_SHIFT                     25
+#define AIPS_PACRD_SP1_MASK                      0x4000000u
+#define AIPS_PACRD_SP1_SHIFT                     26
+#define AIPS_PACRD_TP0_MASK                      0x10000000u
+#define AIPS_PACRD_TP0_SHIFT                     28
+#define AIPS_PACRD_WP0_MASK                      0x20000000u
+#define AIPS_PACRD_WP0_SHIFT                     29
+#define AIPS_PACRD_SP0_MASK                      0x40000000u
+#define AIPS_PACRD_SP0_SHIFT                     30
+/* PACRE Bit Fields */
+#define AIPS_PACRE_TP7_MASK                      0x1u
+#define AIPS_PACRE_TP7_SHIFT                     0
+#define AIPS_PACRE_WP7_MASK                      0x2u
+#define AIPS_PACRE_WP7_SHIFT                     1
+#define AIPS_PACRE_SP7_MASK                      0x4u
+#define AIPS_PACRE_SP7_SHIFT                     2
+#define AIPS_PACRE_TP6_MASK                      0x10u
+#define AIPS_PACRE_TP6_SHIFT                     4
+#define AIPS_PACRE_WP6_MASK                      0x20u
+#define AIPS_PACRE_WP6_SHIFT                     5
+#define AIPS_PACRE_SP6_MASK                      0x40u
+#define AIPS_PACRE_SP6_SHIFT                     6
+#define AIPS_PACRE_TP5_MASK                      0x100u
+#define AIPS_PACRE_TP5_SHIFT                     8
+#define AIPS_PACRE_WP5_MASK                      0x200u
+#define AIPS_PACRE_WP5_SHIFT                     9
+#define AIPS_PACRE_SP5_MASK                      0x400u
+#define AIPS_PACRE_SP5_SHIFT                     10
+#define AIPS_PACRE_TP4_MASK                      0x1000u
+#define AIPS_PACRE_TP4_SHIFT                     12
+#define AIPS_PACRE_WP4_MASK                      0x2000u
+#define AIPS_PACRE_WP4_SHIFT                     13
+#define AIPS_PACRE_SP4_MASK                      0x4000u
+#define AIPS_PACRE_SP4_SHIFT                     14
+#define AIPS_PACRE_TP3_MASK                      0x10000u
+#define AIPS_PACRE_TP3_SHIFT                     16
+#define AIPS_PACRE_WP3_MASK                      0x20000u
+#define AIPS_PACRE_WP3_SHIFT                     17
+#define AIPS_PACRE_SP3_MASK                      0x40000u
+#define AIPS_PACRE_SP3_SHIFT                     18
+#define AIPS_PACRE_TP2_MASK                      0x100000u
+#define AIPS_PACRE_TP2_SHIFT                     20
+#define AIPS_PACRE_WP2_MASK                      0x200000u
+#define AIPS_PACRE_WP2_SHIFT                     21
+#define AIPS_PACRE_SP2_MASK                      0x400000u
+#define AIPS_PACRE_SP2_SHIFT                     22
+#define AIPS_PACRE_TP1_MASK                      0x1000000u
+#define AIPS_PACRE_TP1_SHIFT                     24
+#define AIPS_PACRE_WP1_MASK                      0x2000000u
+#define AIPS_PACRE_WP1_SHIFT                     25
+#define AIPS_PACRE_SP1_MASK                      0x4000000u
+#define AIPS_PACRE_SP1_SHIFT                     26
+#define AIPS_PACRE_TP0_MASK                      0x10000000u
+#define AIPS_PACRE_TP0_SHIFT                     28
+#define AIPS_PACRE_WP0_MASK                      0x20000000u
+#define AIPS_PACRE_WP0_SHIFT                     29
+#define AIPS_PACRE_SP0_MASK                      0x40000000u
+#define AIPS_PACRE_SP0_SHIFT                     30
+/* PACRF Bit Fields */
+#define AIPS_PACRF_TP7_MASK                      0x1u
+#define AIPS_PACRF_TP7_SHIFT                     0
+#define AIPS_PACRF_WP7_MASK                      0x2u
+#define AIPS_PACRF_WP7_SHIFT                     1
+#define AIPS_PACRF_SP7_MASK                      0x4u
+#define AIPS_PACRF_SP7_SHIFT                     2
+#define AIPS_PACRF_TP6_MASK                      0x10u
+#define AIPS_PACRF_TP6_SHIFT                     4
+#define AIPS_PACRF_WP6_MASK                      0x20u
+#define AIPS_PACRF_WP6_SHIFT                     5
+#define AIPS_PACRF_SP6_MASK                      0x40u
+#define AIPS_PACRF_SP6_SHIFT                     6
+#define AIPS_PACRF_TP5_MASK                      0x100u
+#define AIPS_PACRF_TP5_SHIFT                     8
+#define AIPS_PACRF_WP5_MASK                      0x200u
+#define AIPS_PACRF_WP5_SHIFT                     9
+#define AIPS_PACRF_SP5_MASK                      0x400u
+#define AIPS_PACRF_SP5_SHIFT                     10
+#define AIPS_PACRF_TP4_MASK                      0x1000u
+#define AIPS_PACRF_TP4_SHIFT                     12
+#define AIPS_PACRF_WP4_MASK                      0x2000u
+#define AIPS_PACRF_WP4_SHIFT                     13
+#define AIPS_PACRF_SP4_MASK                      0x4000u
+#define AIPS_PACRF_SP4_SHIFT                     14
+#define AIPS_PACRF_TP3_MASK                      0x10000u
+#define AIPS_PACRF_TP3_SHIFT                     16
+#define AIPS_PACRF_WP3_MASK                      0x20000u
+#define AIPS_PACRF_WP3_SHIFT                     17
+#define AIPS_PACRF_SP3_MASK                      0x40000u
+#define AIPS_PACRF_SP3_SHIFT                     18
+#define AIPS_PACRF_TP2_MASK                      0x100000u
+#define AIPS_PACRF_TP2_SHIFT                     20
+#define AIPS_PACRF_WP2_MASK                      0x200000u
+#define AIPS_PACRF_WP2_SHIFT                     21
+#define AIPS_PACRF_SP2_MASK                      0x400000u
+#define AIPS_PACRF_SP2_SHIFT                     22
+#define AIPS_PACRF_TP1_MASK                      0x1000000u
+#define AIPS_PACRF_TP1_SHIFT                     24
+#define AIPS_PACRF_WP1_MASK                      0x2000000u
+#define AIPS_PACRF_WP1_SHIFT                     25
+#define AIPS_PACRF_SP1_MASK                      0x4000000u
+#define AIPS_PACRF_SP1_SHIFT                     26
+#define AIPS_PACRF_TP0_MASK                      0x10000000u
+#define AIPS_PACRF_TP0_SHIFT                     28
+#define AIPS_PACRF_WP0_MASK                      0x20000000u
+#define AIPS_PACRF_WP0_SHIFT                     29
+#define AIPS_PACRF_SP0_MASK                      0x40000000u
+#define AIPS_PACRF_SP0_SHIFT                     30
+/* PACRG Bit Fields */
+#define AIPS_PACRG_TP7_MASK                      0x1u
+#define AIPS_PACRG_TP7_SHIFT                     0
+#define AIPS_PACRG_WP7_MASK                      0x2u
+#define AIPS_PACRG_WP7_SHIFT                     1
+#define AIPS_PACRG_SP7_MASK                      0x4u
+#define AIPS_PACRG_SP7_SHIFT                     2
+#define AIPS_PACRG_TP6_MASK                      0x10u
+#define AIPS_PACRG_TP6_SHIFT                     4
+#define AIPS_PACRG_WP6_MASK                      0x20u
+#define AIPS_PACRG_WP6_SHIFT                     5
+#define AIPS_PACRG_SP6_MASK                      0x40u
+#define AIPS_PACRG_SP6_SHIFT                     6
+#define AIPS_PACRG_TP5_MASK                      0x100u
+#define AIPS_PACRG_TP5_SHIFT                     8
+#define AIPS_PACRG_WP5_MASK                      0x200u
+#define AIPS_PACRG_WP5_SHIFT                     9
+#define AIPS_PACRG_SP5_MASK                      0x400u
+#define AIPS_PACRG_SP5_SHIFT                     10
+#define AIPS_PACRG_TP4_MASK                      0x1000u
+#define AIPS_PACRG_TP4_SHIFT                     12
+#define AIPS_PACRG_WP4_MASK                      0x2000u
+#define AIPS_PACRG_WP4_SHIFT                     13
+#define AIPS_PACRG_SP4_MASK                      0x4000u
+#define AIPS_PACRG_SP4_SHIFT                     14
+#define AIPS_PACRG_TP3_MASK                      0x10000u
+#define AIPS_PACRG_TP3_SHIFT                     16
+#define AIPS_PACRG_WP3_MASK                      0x20000u
+#define AIPS_PACRG_WP3_SHIFT                     17
+#define AIPS_PACRG_SP3_MASK                      0x40000u
+#define AIPS_PACRG_SP3_SHIFT                     18
+#define AIPS_PACRG_TP2_MASK                      0x100000u
+#define AIPS_PACRG_TP2_SHIFT                     20
+#define AIPS_PACRG_WP2_MASK                      0x200000u
+#define AIPS_PACRG_WP2_SHIFT                     21
+#define AIPS_PACRG_SP2_MASK                      0x400000u
+#define AIPS_PACRG_SP2_SHIFT                     22
+#define AIPS_PACRG_TP1_MASK                      0x1000000u
+#define AIPS_PACRG_TP1_SHIFT                     24
+#define AIPS_PACRG_WP1_MASK                      0x2000000u
+#define AIPS_PACRG_WP1_SHIFT                     25
+#define AIPS_PACRG_SP1_MASK                      0x4000000u
+#define AIPS_PACRG_SP1_SHIFT                     26
+#define AIPS_PACRG_TP0_MASK                      0x10000000u
+#define AIPS_PACRG_TP0_SHIFT                     28
+#define AIPS_PACRG_WP0_MASK                      0x20000000u
+#define AIPS_PACRG_WP0_SHIFT                     29
+#define AIPS_PACRG_SP0_MASK                      0x40000000u
+#define AIPS_PACRG_SP0_SHIFT                     30
+/* PACRH Bit Fields */
+#define AIPS_PACRH_TP7_MASK                      0x1u
+#define AIPS_PACRH_TP7_SHIFT                     0
+#define AIPS_PACRH_WP7_MASK                      0x2u
+#define AIPS_PACRH_WP7_SHIFT                     1
+#define AIPS_PACRH_SP7_MASK                      0x4u
+#define AIPS_PACRH_SP7_SHIFT                     2
+#define AIPS_PACRH_TP6_MASK                      0x10u
+#define AIPS_PACRH_TP6_SHIFT                     4
+#define AIPS_PACRH_WP6_MASK                      0x20u
+#define AIPS_PACRH_WP6_SHIFT                     5
+#define AIPS_PACRH_SP6_MASK                      0x40u
+#define AIPS_PACRH_SP6_SHIFT                     6
+#define AIPS_PACRH_TP5_MASK                      0x100u
+#define AIPS_PACRH_TP5_SHIFT                     8
+#define AIPS_PACRH_WP5_MASK                      0x200u
+#define AIPS_PACRH_WP5_SHIFT                     9
+#define AIPS_PACRH_SP5_MASK                      0x400u
+#define AIPS_PACRH_SP5_SHIFT                     10
+#define AIPS_PACRH_TP4_MASK                      0x1000u
+#define AIPS_PACRH_TP4_SHIFT                     12
+#define AIPS_PACRH_WP4_MASK                      0x2000u
+#define AIPS_PACRH_WP4_SHIFT                     13
+#define AIPS_PACRH_SP4_MASK                      0x4000u
+#define AIPS_PACRH_SP4_SHIFT                     14
+#define AIPS_PACRH_TP3_MASK                      0x10000u
+#define AIPS_PACRH_TP3_SHIFT                     16
+#define AIPS_PACRH_WP3_MASK                      0x20000u
+#define AIPS_PACRH_WP3_SHIFT                     17
+#define AIPS_PACRH_SP3_MASK                      0x40000u
+#define AIPS_PACRH_SP3_SHIFT                     18
+#define AIPS_PACRH_TP2_MASK                      0x100000u
+#define AIPS_PACRH_TP2_SHIFT                     20
+#define AIPS_PACRH_WP2_MASK                      0x200000u
+#define AIPS_PACRH_WP2_SHIFT                     21
+#define AIPS_PACRH_SP2_MASK                      0x400000u
+#define AIPS_PACRH_SP2_SHIFT                     22
+#define AIPS_PACRH_TP1_MASK                      0x1000000u
+#define AIPS_PACRH_TP1_SHIFT                     24
+#define AIPS_PACRH_WP1_MASK                      0x2000000u
+#define AIPS_PACRH_WP1_SHIFT                     25
+#define AIPS_PACRH_SP1_MASK                      0x4000000u
+#define AIPS_PACRH_SP1_SHIFT                     26
+#define AIPS_PACRH_TP0_MASK                      0x10000000u
+#define AIPS_PACRH_TP0_SHIFT                     28
+#define AIPS_PACRH_WP0_MASK                      0x20000000u
+#define AIPS_PACRH_WP0_SHIFT                     29
+#define AIPS_PACRH_SP0_MASK                      0x40000000u
+#define AIPS_PACRH_SP0_SHIFT                     30
+/* PACRI Bit Fields */
+#define AIPS_PACRI_TP7_MASK                      0x1u
+#define AIPS_PACRI_TP7_SHIFT                     0
+#define AIPS_PACRI_WP7_MASK                      0x2u
+#define AIPS_PACRI_WP7_SHIFT                     1
+#define AIPS_PACRI_SP7_MASK                      0x4u
+#define AIPS_PACRI_SP7_SHIFT                     2
+#define AIPS_PACRI_TP6_MASK                      0x10u
+#define AIPS_PACRI_TP6_SHIFT                     4
+#define AIPS_PACRI_WP6_MASK                      0x20u
+#define AIPS_PACRI_WP6_SHIFT                     5
+#define AIPS_PACRI_SP6_MASK                      0x40u
+#define AIPS_PACRI_SP6_SHIFT                     6
+#define AIPS_PACRI_TP5_MASK                      0x100u
+#define AIPS_PACRI_TP5_SHIFT                     8
+#define AIPS_PACRI_WP5_MASK                      0x200u
+#define AIPS_PACRI_WP5_SHIFT                     9
+#define AIPS_PACRI_SP5_MASK                      0x400u
+#define AIPS_PACRI_SP5_SHIFT                     10
+#define AIPS_PACRI_TP4_MASK                      0x1000u
+#define AIPS_PACRI_TP4_SHIFT                     12
+#define AIPS_PACRI_WP4_MASK                      0x2000u
+#define AIPS_PACRI_WP4_SHIFT                     13
+#define AIPS_PACRI_SP4_MASK                      0x4000u
+#define AIPS_PACRI_SP4_SHIFT                     14
+#define AIPS_PACRI_TP3_MASK                      0x10000u
+#define AIPS_PACRI_TP3_SHIFT                     16
+#define AIPS_PACRI_WP3_MASK                      0x20000u
+#define AIPS_PACRI_WP3_SHIFT                     17
+#define AIPS_PACRI_SP3_MASK                      0x40000u
+#define AIPS_PACRI_SP3_SHIFT                     18
+#define AIPS_PACRI_TP2_MASK                      0x100000u
+#define AIPS_PACRI_TP2_SHIFT                     20
+#define AIPS_PACRI_WP2_MASK                      0x200000u
+#define AIPS_PACRI_WP2_SHIFT                     21
+#define AIPS_PACRI_SP2_MASK                      0x400000u
+#define AIPS_PACRI_SP2_SHIFT                     22
+#define AIPS_PACRI_TP1_MASK                      0x1000000u
+#define AIPS_PACRI_TP1_SHIFT                     24
+#define AIPS_PACRI_WP1_MASK                      0x2000000u
+#define AIPS_PACRI_WP1_SHIFT                     25
+#define AIPS_PACRI_SP1_MASK                      0x4000000u
+#define AIPS_PACRI_SP1_SHIFT                     26
+#define AIPS_PACRI_TP0_MASK                      0x10000000u
+#define AIPS_PACRI_TP0_SHIFT                     28
+#define AIPS_PACRI_WP0_MASK                      0x20000000u
+#define AIPS_PACRI_WP0_SHIFT                     29
+#define AIPS_PACRI_SP0_MASK                      0x40000000u
+#define AIPS_PACRI_SP0_SHIFT                     30
+/* PACRJ Bit Fields */
+#define AIPS_PACRJ_TP7_MASK                      0x1u
+#define AIPS_PACRJ_TP7_SHIFT                     0
+#define AIPS_PACRJ_WP7_MASK                      0x2u
+#define AIPS_PACRJ_WP7_SHIFT                     1
+#define AIPS_PACRJ_SP7_MASK                      0x4u
+#define AIPS_PACRJ_SP7_SHIFT                     2
+#define AIPS_PACRJ_TP6_MASK                      0x10u
+#define AIPS_PACRJ_TP6_SHIFT                     4
+#define AIPS_PACRJ_WP6_MASK                      0x20u
+#define AIPS_PACRJ_WP6_SHIFT                     5
+#define AIPS_PACRJ_SP6_MASK                      0x40u
+#define AIPS_PACRJ_SP6_SHIFT                     6
+#define AIPS_PACRJ_TP5_MASK                      0x100u
+#define AIPS_PACRJ_TP5_SHIFT                     8
+#define AIPS_PACRJ_WP5_MASK                      0x200u
+#define AIPS_PACRJ_WP5_SHIFT                     9
+#define AIPS_PACRJ_SP5_MASK                      0x400u
+#define AIPS_PACRJ_SP5_SHIFT                     10
+#define AIPS_PACRJ_TP4_MASK                      0x1000u
+#define AIPS_PACRJ_TP4_SHIFT                     12
+#define AIPS_PACRJ_WP4_MASK                      0x2000u
+#define AIPS_PACRJ_WP4_SHIFT                     13
+#define AIPS_PACRJ_SP4_MASK                      0x4000u
+#define AIPS_PACRJ_SP4_SHIFT                     14
+#define AIPS_PACRJ_TP3_MASK                      0x10000u
+#define AIPS_PACRJ_TP3_SHIFT                     16
+#define AIPS_PACRJ_WP3_MASK                      0x20000u
+#define AIPS_PACRJ_WP3_SHIFT                     17
+#define AIPS_PACRJ_SP3_MASK                      0x40000u
+#define AIPS_PACRJ_SP3_SHIFT                     18
+#define AIPS_PACRJ_TP2_MASK                      0x100000u
+#define AIPS_PACRJ_TP2_SHIFT                     20
+#define AIPS_PACRJ_WP2_MASK                      0x200000u
+#define AIPS_PACRJ_WP2_SHIFT                     21
+#define AIPS_PACRJ_SP2_MASK                      0x400000u
+#define AIPS_PACRJ_SP2_SHIFT                     22
+#define AIPS_PACRJ_TP1_MASK                      0x1000000u
+#define AIPS_PACRJ_TP1_SHIFT                     24
+#define AIPS_PACRJ_WP1_MASK                      0x2000000u
+#define AIPS_PACRJ_WP1_SHIFT                     25
+#define AIPS_PACRJ_SP1_MASK                      0x4000000u
+#define AIPS_PACRJ_SP1_SHIFT                     26
+#define AIPS_PACRJ_TP0_MASK                      0x10000000u
+#define AIPS_PACRJ_TP0_SHIFT                     28
+#define AIPS_PACRJ_WP0_MASK                      0x20000000u
+#define AIPS_PACRJ_WP0_SHIFT                     29
+#define AIPS_PACRJ_SP0_MASK                      0x40000000u
+#define AIPS_PACRJ_SP0_SHIFT                     30
+/* PACRK Bit Fields */
+#define AIPS_PACRK_TP7_MASK                      0x1u
+#define AIPS_PACRK_TP7_SHIFT                     0
+#define AIPS_PACRK_WP7_MASK                      0x2u
+#define AIPS_PACRK_WP7_SHIFT                     1
+#define AIPS_PACRK_SP7_MASK                      0x4u
+#define AIPS_PACRK_SP7_SHIFT                     2
+#define AIPS_PACRK_TP6_MASK                      0x10u
+#define AIPS_PACRK_TP6_SHIFT                     4
+#define AIPS_PACRK_WP6_MASK                      0x20u
+#define AIPS_PACRK_WP6_SHIFT                     5
+#define AIPS_PACRK_SP6_MASK                      0x40u
+#define AIPS_PACRK_SP6_SHIFT                     6
+#define AIPS_PACRK_TP5_MASK                      0x100u
+#define AIPS_PACRK_TP5_SHIFT                     8
+#define AIPS_PACRK_WP5_MASK                      0x200u
+#define AIPS_PACRK_WP5_SHIFT                     9
+#define AIPS_PACRK_SP5_MASK                      0x400u
+#define AIPS_PACRK_SP5_SHIFT                     10
+#define AIPS_PACRK_TP4_MASK                      0x1000u
+#define AIPS_PACRK_TP4_SHIFT                     12
+#define AIPS_PACRK_WP4_MASK                      0x2000u
+#define AIPS_PACRK_WP4_SHIFT                     13
+#define AIPS_PACRK_SP4_MASK                      0x4000u
+#define AIPS_PACRK_SP4_SHIFT                     14
+#define AIPS_PACRK_TP3_MASK                      0x10000u
+#define AIPS_PACRK_TP3_SHIFT                     16
+#define AIPS_PACRK_WP3_MASK                      0x20000u
+#define AIPS_PACRK_WP3_SHIFT                     17
+#define AIPS_PACRK_SP3_MASK                      0x40000u
+#define AIPS_PACRK_SP3_SHIFT                     18
+#define AIPS_PACRK_TP2_MASK                      0x100000u
+#define AIPS_PACRK_TP2_SHIFT                     20
+#define AIPS_PACRK_WP2_MASK                      0x200000u
+#define AIPS_PACRK_WP2_SHIFT                     21
+#define AIPS_PACRK_SP2_MASK                      0x400000u
+#define AIPS_PACRK_SP2_SHIFT                     22
+#define AIPS_PACRK_TP1_MASK                      0x1000000u
+#define AIPS_PACRK_TP1_SHIFT                     24
+#define AIPS_PACRK_WP1_MASK                      0x2000000u
+#define AIPS_PACRK_WP1_SHIFT                     25
+#define AIPS_PACRK_SP1_MASK                      0x4000000u
+#define AIPS_PACRK_SP1_SHIFT                     26
+#define AIPS_PACRK_TP0_MASK                      0x10000000u
+#define AIPS_PACRK_TP0_SHIFT                     28
+#define AIPS_PACRK_WP0_MASK                      0x20000000u
+#define AIPS_PACRK_WP0_SHIFT                     29
+#define AIPS_PACRK_SP0_MASK                      0x40000000u
+#define AIPS_PACRK_SP0_SHIFT                     30
+/* PACRL Bit Fields */
+#define AIPS_PACRL_TP7_MASK                      0x1u
+#define AIPS_PACRL_TP7_SHIFT                     0
+#define AIPS_PACRL_WP7_MASK                      0x2u
+#define AIPS_PACRL_WP7_SHIFT                     1
+#define AIPS_PACRL_SP7_MASK                      0x4u
+#define AIPS_PACRL_SP7_SHIFT                     2
+#define AIPS_PACRL_TP6_MASK                      0x10u
+#define AIPS_PACRL_TP6_SHIFT                     4
+#define AIPS_PACRL_WP6_MASK                      0x20u
+#define AIPS_PACRL_WP6_SHIFT                     5
+#define AIPS_PACRL_SP6_MASK                      0x40u
+#define AIPS_PACRL_SP6_SHIFT                     6
+#define AIPS_PACRL_TP5_MASK                      0x100u
+#define AIPS_PACRL_TP5_SHIFT                     8
+#define AIPS_PACRL_WP5_MASK                      0x200u
+#define AIPS_PACRL_WP5_SHIFT                     9
+#define AIPS_PACRL_SP5_MASK                      0x400u
+#define AIPS_PACRL_SP5_SHIFT                     10
+#define AIPS_PACRL_TP4_MASK                      0x1000u
+#define AIPS_PACRL_TP4_SHIFT                     12
+#define AIPS_PACRL_WP4_MASK                      0x2000u
+#define AIPS_PACRL_WP4_SHIFT                     13
+#define AIPS_PACRL_SP4_MASK                      0x4000u
+#define AIPS_PACRL_SP4_SHIFT                     14
+#define AIPS_PACRL_TP3_MASK                      0x10000u
+#define AIPS_PACRL_TP3_SHIFT                     16
+#define AIPS_PACRL_WP3_MASK                      0x20000u
+#define AIPS_PACRL_WP3_SHIFT                     17
+#define AIPS_PACRL_SP3_MASK                      0x40000u
+#define AIPS_PACRL_SP3_SHIFT                     18
+#define AIPS_PACRL_TP2_MASK                      0x100000u
+#define AIPS_PACRL_TP2_SHIFT                     20
+#define AIPS_PACRL_WP2_MASK                      0x200000u
+#define AIPS_PACRL_WP2_SHIFT                     21
+#define AIPS_PACRL_SP2_MASK                      0x400000u
+#define AIPS_PACRL_SP2_SHIFT                     22
+#define AIPS_PACRL_TP1_MASK                      0x1000000u
+#define AIPS_PACRL_TP1_SHIFT                     24
+#define AIPS_PACRL_WP1_MASK                      0x2000000u
+#define AIPS_PACRL_WP1_SHIFT                     25
+#define AIPS_PACRL_SP1_MASK                      0x4000000u
+#define AIPS_PACRL_SP1_SHIFT                     26
+#define AIPS_PACRL_TP0_MASK                      0x10000000u
+#define AIPS_PACRL_TP0_SHIFT                     28
+#define AIPS_PACRL_WP0_MASK                      0x20000000u
+#define AIPS_PACRL_WP0_SHIFT                     29
+#define AIPS_PACRL_SP0_MASK                      0x40000000u
+#define AIPS_PACRL_SP0_SHIFT                     30
+/* PACRM Bit Fields */
+#define AIPS_PACRM_TP7_MASK                      0x1u
+#define AIPS_PACRM_TP7_SHIFT                     0
+#define AIPS_PACRM_WP7_MASK                      0x2u
+#define AIPS_PACRM_WP7_SHIFT                     1
+#define AIPS_PACRM_SP7_MASK                      0x4u
+#define AIPS_PACRM_SP7_SHIFT                     2
+#define AIPS_PACRM_TP6_MASK                      0x10u
+#define AIPS_PACRM_TP6_SHIFT                     4
+#define AIPS_PACRM_WP6_MASK                      0x20u
+#define AIPS_PACRM_WP6_SHIFT                     5
+#define AIPS_PACRM_SP6_MASK                      0x40u
+#define AIPS_PACRM_SP6_SHIFT                     6
+#define AIPS_PACRM_TP5_MASK                      0x100u
+#define AIPS_PACRM_TP5_SHIFT                     8
+#define AIPS_PACRM_WP5_MASK                      0x200u
+#define AIPS_PACRM_WP5_SHIFT                     9
+#define AIPS_PACRM_SP5_MASK                      0x400u
+#define AIPS_PACRM_SP5_SHIFT                     10
+#define AIPS_PACRM_TP4_MASK                      0x1000u
+#define AIPS_PACRM_TP4_SHIFT                     12
+#define AIPS_PACRM_WP4_MASK                      0x2000u
+#define AIPS_PACRM_WP4_SHIFT                     13
+#define AIPS_PACRM_SP4_MASK                      0x4000u
+#define AIPS_PACRM_SP4_SHIFT                     14
+#define AIPS_PACRM_TP3_MASK                      0x10000u
+#define AIPS_PACRM_TP3_SHIFT                     16
+#define AIPS_PACRM_WP3_MASK                      0x20000u
+#define AIPS_PACRM_WP3_SHIFT                     17
+#define AIPS_PACRM_SP3_MASK                      0x40000u
+#define AIPS_PACRM_SP3_SHIFT                     18
+#define AIPS_PACRM_TP2_MASK                      0x100000u
+#define AIPS_PACRM_TP2_SHIFT                     20
+#define AIPS_PACRM_WP2_MASK                      0x200000u
+#define AIPS_PACRM_WP2_SHIFT                     21
+#define AIPS_PACRM_SP2_MASK                      0x400000u
+#define AIPS_PACRM_SP2_SHIFT                     22
+#define AIPS_PACRM_TP1_MASK                      0x1000000u
+#define AIPS_PACRM_TP1_SHIFT                     24
+#define AIPS_PACRM_WP1_MASK                      0x2000000u
+#define AIPS_PACRM_WP1_SHIFT                     25
+#define AIPS_PACRM_SP1_MASK                      0x4000000u
+#define AIPS_PACRM_SP1_SHIFT                     26
+#define AIPS_PACRM_TP0_MASK                      0x10000000u
+#define AIPS_PACRM_TP0_SHIFT                     28
+#define AIPS_PACRM_WP0_MASK                      0x20000000u
+#define AIPS_PACRM_WP0_SHIFT                     29
+#define AIPS_PACRM_SP0_MASK                      0x40000000u
+#define AIPS_PACRM_SP0_SHIFT                     30
+/* PACRN Bit Fields */
+#define AIPS_PACRN_TP7_MASK                      0x1u
+#define AIPS_PACRN_TP7_SHIFT                     0
+#define AIPS_PACRN_WP7_MASK                      0x2u
+#define AIPS_PACRN_WP7_SHIFT                     1
+#define AIPS_PACRN_SP7_MASK                      0x4u
+#define AIPS_PACRN_SP7_SHIFT                     2
+#define AIPS_PACRN_TP6_MASK                      0x10u
+#define AIPS_PACRN_TP6_SHIFT                     4
+#define AIPS_PACRN_WP6_MASK                      0x20u
+#define AIPS_PACRN_WP6_SHIFT                     5
+#define AIPS_PACRN_SP6_MASK                      0x40u
+#define AIPS_PACRN_SP6_SHIFT                     6
+#define AIPS_PACRN_TP5_MASK                      0x100u
+#define AIPS_PACRN_TP5_SHIFT                     8
+#define AIPS_PACRN_WP5_MASK                      0x200u
+#define AIPS_PACRN_WP5_SHIFT                     9
+#define AIPS_PACRN_SP5_MASK                      0x400u
+#define AIPS_PACRN_SP5_SHIFT                     10
+#define AIPS_PACRN_TP4_MASK                      0x1000u
+#define AIPS_PACRN_TP4_SHIFT                     12
+#define AIPS_PACRN_WP4_MASK                      0x2000u
+#define AIPS_PACRN_WP4_SHIFT                     13
+#define AIPS_PACRN_SP4_MASK                      0x4000u
+#define AIPS_PACRN_SP4_SHIFT                     14
+#define AIPS_PACRN_TP3_MASK                      0x10000u
+#define AIPS_PACRN_TP3_SHIFT                     16
+#define AIPS_PACRN_WP3_MASK                      0x20000u
+#define AIPS_PACRN_WP3_SHIFT                     17
+#define AIPS_PACRN_SP3_MASK                      0x40000u
+#define AIPS_PACRN_SP3_SHIFT                     18
+#define AIPS_PACRN_TP2_MASK                      0x100000u
+#define AIPS_PACRN_TP2_SHIFT                     20
+#define AIPS_PACRN_WP2_MASK                      0x200000u
+#define AIPS_PACRN_WP2_SHIFT                     21
+#define AIPS_PACRN_SP2_MASK                      0x400000u
+#define AIPS_PACRN_SP2_SHIFT                     22
+#define AIPS_PACRN_TP1_MASK                      0x1000000u
+#define AIPS_PACRN_TP1_SHIFT                     24
+#define AIPS_PACRN_WP1_MASK                      0x2000000u
+#define AIPS_PACRN_WP1_SHIFT                     25
+#define AIPS_PACRN_SP1_MASK                      0x4000000u
+#define AIPS_PACRN_SP1_SHIFT                     26
+#define AIPS_PACRN_TP0_MASK                      0x10000000u
+#define AIPS_PACRN_TP0_SHIFT                     28
+#define AIPS_PACRN_WP0_MASK                      0x20000000u
+#define AIPS_PACRN_WP0_SHIFT                     29
+#define AIPS_PACRN_SP0_MASK                      0x40000000u
+#define AIPS_PACRN_SP0_SHIFT                     30
+/* PACRO Bit Fields */
+#define AIPS_PACRO_TP7_MASK                      0x1u
+#define AIPS_PACRO_TP7_SHIFT                     0
+#define AIPS_PACRO_WP7_MASK                      0x2u
+#define AIPS_PACRO_WP7_SHIFT                     1
+#define AIPS_PACRO_SP7_MASK                      0x4u
+#define AIPS_PACRO_SP7_SHIFT                     2
+#define AIPS_PACRO_TP6_MASK                      0x10u
+#define AIPS_PACRO_TP6_SHIFT                     4
+#define AIPS_PACRO_WP6_MASK                      0x20u
+#define AIPS_PACRO_WP6_SHIFT                     5
+#define AIPS_PACRO_SP6_MASK                      0x40u
+#define AIPS_PACRO_SP6_SHIFT                     6
+#define AIPS_PACRO_TP5_MASK                      0x100u
+#define AIPS_PACRO_TP5_SHIFT                     8
+#define AIPS_PACRO_WP5_MASK                      0x200u
+#define AIPS_PACRO_WP5_SHIFT                     9
+#define AIPS_PACRO_SP5_MASK                      0x400u
+#define AIPS_PACRO_SP5_SHIFT                     10
+#define AIPS_PACRO_TP4_MASK                      0x1000u
+#define AIPS_PACRO_TP4_SHIFT                     12
+#define AIPS_PACRO_WP4_MASK                      0x2000u
+#define AIPS_PACRO_WP4_SHIFT                     13
+#define AIPS_PACRO_SP4_MASK                      0x4000u
+#define AIPS_PACRO_SP4_SHIFT                     14
+#define AIPS_PACRO_TP3_MASK                      0x10000u
+#define AIPS_PACRO_TP3_SHIFT                     16
+#define AIPS_PACRO_WP3_MASK                      0x20000u
+#define AIPS_PACRO_WP3_SHIFT                     17
+#define AIPS_PACRO_SP3_MASK                      0x40000u
+#define AIPS_PACRO_SP3_SHIFT                     18
+#define AIPS_PACRO_TP2_MASK                      0x100000u
+#define AIPS_PACRO_TP2_SHIFT                     20
+#define AIPS_PACRO_WP2_MASK                      0x200000u
+#define AIPS_PACRO_WP2_SHIFT                     21
+#define AIPS_PACRO_SP2_MASK                      0x400000u
+#define AIPS_PACRO_SP2_SHIFT                     22
+#define AIPS_PACRO_TP1_MASK                      0x1000000u
+#define AIPS_PACRO_TP1_SHIFT                     24
+#define AIPS_PACRO_WP1_MASK                      0x2000000u
+#define AIPS_PACRO_WP1_SHIFT                     25
+#define AIPS_PACRO_SP1_MASK                      0x4000000u
+#define AIPS_PACRO_SP1_SHIFT                     26
+#define AIPS_PACRO_TP0_MASK                      0x10000000u
+#define AIPS_PACRO_TP0_SHIFT                     28
+#define AIPS_PACRO_WP0_MASK                      0x20000000u
+#define AIPS_PACRO_WP0_SHIFT                     29
+#define AIPS_PACRO_SP0_MASK                      0x40000000u
+#define AIPS_PACRO_SP0_SHIFT                     30
+/* PACRP Bit Fields */
+#define AIPS_PACRP_TP7_MASK                      0x1u
+#define AIPS_PACRP_TP7_SHIFT                     0
+#define AIPS_PACRP_WP7_MASK                      0x2u
+#define AIPS_PACRP_WP7_SHIFT                     1
+#define AIPS_PACRP_SP7_MASK                      0x4u
+#define AIPS_PACRP_SP7_SHIFT                     2
+#define AIPS_PACRP_TP6_MASK                      0x10u
+#define AIPS_PACRP_TP6_SHIFT                     4
+#define AIPS_PACRP_WP6_MASK                      0x20u
+#define AIPS_PACRP_WP6_SHIFT                     5
+#define AIPS_PACRP_SP6_MASK                      0x40u
+#define AIPS_PACRP_SP6_SHIFT                     6
+#define AIPS_PACRP_TP5_MASK                      0x100u
+#define AIPS_PACRP_TP5_SHIFT                     8
+#define AIPS_PACRP_WP5_MASK                      0x200u
+#define AIPS_PACRP_WP5_SHIFT                     9
+#define AIPS_PACRP_SP5_MASK                      0x400u
+#define AIPS_PACRP_SP5_SHIFT                     10
+#define AIPS_PACRP_TP4_MASK                      0x1000u
+#define AIPS_PACRP_TP4_SHIFT                     12
+#define AIPS_PACRP_WP4_MASK                      0x2000u
+#define AIPS_PACRP_WP4_SHIFT                     13
+#define AIPS_PACRP_SP4_MASK                      0x4000u
+#define AIPS_PACRP_SP4_SHIFT                     14
+#define AIPS_PACRP_TP3_MASK                      0x10000u
+#define AIPS_PACRP_TP3_SHIFT                     16
+#define AIPS_PACRP_WP3_MASK                      0x20000u
+#define AIPS_PACRP_WP3_SHIFT                     17
+#define AIPS_PACRP_SP3_MASK                      0x40000u
+#define AIPS_PACRP_SP3_SHIFT                     18
+#define AIPS_PACRP_TP2_MASK                      0x100000u
+#define AIPS_PACRP_TP2_SHIFT                     20
+#define AIPS_PACRP_WP2_MASK                      0x200000u
+#define AIPS_PACRP_WP2_SHIFT                     21
+#define AIPS_PACRP_SP2_MASK                      0x400000u
+#define AIPS_PACRP_SP2_SHIFT                     22
+#define AIPS_PACRP_TP1_MASK                      0x1000000u
+#define AIPS_PACRP_TP1_SHIFT                     24
+#define AIPS_PACRP_WP1_MASK                      0x2000000u
+#define AIPS_PACRP_WP1_SHIFT                     25
+#define AIPS_PACRP_SP1_MASK                      0x4000000u
+#define AIPS_PACRP_SP1_SHIFT                     26
+#define AIPS_PACRP_TP0_MASK                      0x10000000u
+#define AIPS_PACRP_TP0_SHIFT                     28
+#define AIPS_PACRP_WP0_MASK                      0x20000000u
+#define AIPS_PACRP_WP0_SHIFT                     29
+#define AIPS_PACRP_SP0_MASK                      0x40000000u
+#define AIPS_PACRP_SP0_SHIFT                     30
+
+/*! \} */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/*! Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/*! Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+/*! Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/*! Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+
+/*! \} */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer */
+/*! \{ */
+
+/*! AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /*!< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /*!< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /*!< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /*!< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /*!< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[508];
+  __IO uint32_t MGPCR4;                            /*!< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR5;                            /*!< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup AXBS_Register_Masks AXBS Register Masks */
+/*! \{ */
+
+/* PRS Bit Fields */
+#define AXBS_PRS_M0_MASK                         0x7u
+#define AXBS_PRS_M0_SHIFT                        0
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         0x70u
+#define AXBS_PRS_M1_SHIFT                        4
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         0x700u
+#define AXBS_PRS_M2_SHIFT                        8
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         0x7000u
+#define AXBS_PRS_M3_SHIFT                        12
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         0x70000u
+#define AXBS_PRS_M4_SHIFT                        16
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         0x700000u
+#define AXBS_PRS_M5_SHIFT                        20
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
+/* CRS Bit Fields */
+#define AXBS_CRS_PARK_MASK                       0x7u
+#define AXBS_CRS_PARK_SHIFT                      0
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       0x30u
+#define AXBS_CRS_PCTL_SHIFT                      4
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        0x300u
+#define AXBS_CRS_ARB_SHIFT                       8
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        0x40000000u
+#define AXBS_CRS_HLP_SHIFT                       30
+#define AXBS_CRS_RO_MASK                         0x80000000u
+#define AXBS_CRS_RO_SHIFT                        31
+/* MGPCR0 Bit Fields */
+#define AXBS_MGPCR0_AULB_MASK                    0x7u
+#define AXBS_MGPCR0_AULB_SHIFT                   0
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
+/* MGPCR1 Bit Fields */
+#define AXBS_MGPCR1_AULB_MASK                    0x7u
+#define AXBS_MGPCR1_AULB_SHIFT                   0
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
+/* MGPCR2 Bit Fields */
+#define AXBS_MGPCR2_AULB_MASK                    0x7u
+#define AXBS_MGPCR2_AULB_SHIFT                   0
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
+/* MGPCR4 Bit Fields */
+#define AXBS_MGPCR4_AULB_MASK                    0x7u
+#define AXBS_MGPCR4_AULB_SHIFT                   0
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
+/* MGPCR5 Bit Fields */
+#define AXBS_MGPCR5_AULB_MASK                    0x7u
+#define AXBS_MGPCR5_AULB_SHIFT                   0
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
+
+/*! \} */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/*! Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/*! Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+
+/*! \} */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer */
+/*! \{ */
+
+/*! CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /*!< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /*!< Control 1 Register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /*!< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /*!< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /*!< Rx 14 Mask Register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /*!< Rx 15 Mask Register, offset: 0x18 */
+  __IO uint32_t ECR;                               /*!< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /*!< Error and Status 1 Register, offset: 0x20 */
+  __IO uint32_t IMASK2;                            /*!< Interrupt Masks 2 Register, offset: 0x24 */
+  __IO uint32_t IMASK1;                            /*!< Interrupt Masks 1 Register, offset: 0x28 */
+  __IO uint32_t IFLAG2;                            /*!< Interrupt Flags 2 Register, offset: 0x2C */
+  __IO uint32_t IFLAG1;                            /*!< Interrupt Flags 1 Register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /*!< Control 2 Register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /*!< Error and Status 2 Register, offset: 0x38 */
+       uint8_t RESERVED_1[8];
+  __I  uint32_t CRCR;                              /*!< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /*!< Rx FIFO Global Mask Register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /*!< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_2[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /*!< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /*!< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /*!< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /*!< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_3[1792];
+  __IO uint32_t RXIMR[16];                         /*!< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CAN_Register_Masks CAN Register Masks */
+/*! \{ */
+
+/* MCR Bit Fields */
+#define CAN_MCR_MAXMB_MASK                       0x7Fu
+#define CAN_MCR_MAXMB_SHIFT                      0
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        0x300u
+#define CAN_MCR_IDAM_SHIFT                       8
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         0x1000u
+#define CAN_MCR_AEN_SHIFT                        12
+#define CAN_MCR_LPRIOEN_MASK                     0x2000u
+#define CAN_MCR_LPRIOEN_SHIFT                    13
+#define CAN_MCR_IRMQ_MASK                        0x10000u
+#define CAN_MCR_IRMQ_SHIFT                       16
+#define CAN_MCR_SRXDIS_MASK                      0x20000u
+#define CAN_MCR_SRXDIS_SHIFT                     17
+#define CAN_MCR_DOZE_MASK                        0x40000u
+#define CAN_MCR_DOZE_SHIFT                       18
+#define CAN_MCR_LPMACK_MASK                      0x100000u
+#define CAN_MCR_LPMACK_SHIFT                     20
+#define CAN_MCR_WRNEN_MASK                       0x200000u
+#define CAN_MCR_WRNEN_SHIFT                      21
+#define CAN_MCR_SLFWAK_MASK                      0x400000u
+#define CAN_MCR_SLFWAK_SHIFT                     22
+#define CAN_MCR_SUPV_MASK                        0x800000u
+#define CAN_MCR_SUPV_SHIFT                       23
+#define CAN_MCR_FRZACK_MASK                      0x1000000u
+#define CAN_MCR_FRZACK_SHIFT                     24
+#define CAN_MCR_SOFTRST_MASK                     0x2000000u
+#define CAN_MCR_SOFTRST_SHIFT                    25
+#define CAN_MCR_WAKMSK_MASK                      0x4000000u
+#define CAN_MCR_WAKMSK_SHIFT                     26
+#define CAN_MCR_NOTRDY_MASK                      0x8000000u
+#define CAN_MCR_NOTRDY_SHIFT                     27
+#define CAN_MCR_HALT_MASK                        0x10000000u
+#define CAN_MCR_HALT_SHIFT                       28
+#define CAN_MCR_RFEN_MASK                        0x20000000u
+#define CAN_MCR_RFEN_SHIFT                       29
+#define CAN_MCR_FRZ_MASK                         0x40000000u
+#define CAN_MCR_FRZ_SHIFT                        30
+#define CAN_MCR_MDIS_MASK                        0x80000000u
+#define CAN_MCR_MDIS_SHIFT                       31
+/* CTRL1 Bit Fields */
+#define CAN_CTRL1_PROPSEG_MASK                   0x7u
+#define CAN_CTRL1_PROPSEG_SHIFT                  0
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       0x8u
+#define CAN_CTRL1_LOM_SHIFT                      3
+#define CAN_CTRL1_LBUF_MASK                      0x10u
+#define CAN_CTRL1_LBUF_SHIFT                     4
+#define CAN_CTRL1_TSYN_MASK                      0x20u
+#define CAN_CTRL1_TSYN_SHIFT                     5
+#define CAN_CTRL1_BOFFREC_MASK                   0x40u
+#define CAN_CTRL1_BOFFREC_SHIFT                  6
+#define CAN_CTRL1_SMP_MASK                       0x80u
+#define CAN_CTRL1_SMP_SHIFT                      7
+#define CAN_CTRL1_RWRNMSK_MASK                   0x400u
+#define CAN_CTRL1_RWRNMSK_SHIFT                  10
+#define CAN_CTRL1_TWRNMSK_MASK                   0x800u
+#define CAN_CTRL1_TWRNMSK_SHIFT                  11
+#define CAN_CTRL1_LPB_MASK                       0x1000u
+#define CAN_CTRL1_LPB_SHIFT                      12
+#define CAN_CTRL1_CLKSRC_MASK                    0x2000u
+#define CAN_CTRL1_CLKSRC_SHIFT                   13
+#define CAN_CTRL1_ERRMSK_MASK                    0x4000u
+#define CAN_CTRL1_ERRMSK_SHIFT                   14
+#define CAN_CTRL1_BOFFMSK_MASK                   0x8000u
+#define CAN_CTRL1_BOFFMSK_SHIFT                  15
+#define CAN_CTRL1_PSEG2_MASK                     0x70000u
+#define CAN_CTRL1_PSEG2_SHIFT                    16
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     0x380000u
+#define CAN_CTRL1_PSEG1_SHIFT                    19
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       0xC00000u
+#define CAN_CTRL1_RJW_SHIFT                      22
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   0xFF000000u
+#define CAN_CTRL1_PRESDIV_SHIFT                  24
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
+/* TIMER Bit Fields */
+#define CAN_TIMER_TIMER_MASK                     0xFFFFu
+#define CAN_TIMER_TIMER_SHIFT                    0
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
+/* RXMGMASK Bit Fields */
+#define CAN_RXMGMASK_MG_MASK                     0xFFFFFFFFu
+#define CAN_RXMGMASK_MG_SHIFT                    0
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
+/* RX14MASK Bit Fields */
+#define CAN_RX14MASK_RX14M_MASK                  0xFFFFFFFFu
+#define CAN_RX14MASK_RX14M_SHIFT                 0
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
+/* RX15MASK Bit Fields */
+#define CAN_RX15MASK_RX15M_MASK                  0xFFFFFFFFu
+#define CAN_RX15MASK_RX15M_SHIFT                 0
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
+/* ECR Bit Fields */
+#define CAN_ECR_TXERRCNT_MASK                    0xFFu
+#define CAN_ECR_TXERRCNT_SHIFT                   0
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    0xFF00u
+#define CAN_ECR_RXERRCNT_SHIFT                   8
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
+/* ESR1 Bit Fields */
+#define CAN_ESR1_WAKINT_MASK                     0x1u
+#define CAN_ESR1_WAKINT_SHIFT                    0
+#define CAN_ESR1_ERRINT_MASK                     0x2u
+#define CAN_ESR1_ERRINT_SHIFT                    1
+#define CAN_ESR1_BOFFINT_MASK                    0x4u
+#define CAN_ESR1_BOFFINT_SHIFT                   2
+#define CAN_ESR1_RX_MASK                         0x8u
+#define CAN_ESR1_RX_SHIFT                        3
+#define CAN_ESR1_FLTCONF_MASK                    0x30u
+#define CAN_ESR1_FLTCONF_SHIFT                   4
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         0x40u
+#define CAN_ESR1_TX_SHIFT                        6
+#define CAN_ESR1_IDLE_MASK                       0x80u
+#define CAN_ESR1_IDLE_SHIFT                      7
+#define CAN_ESR1_RXWRN_MASK                      0x100u
+#define CAN_ESR1_RXWRN_SHIFT                     8
+#define CAN_ESR1_TXWRN_MASK                      0x200u
+#define CAN_ESR1_TXWRN_SHIFT                     9
+#define CAN_ESR1_STFERR_MASK                     0x400u
+#define CAN_ESR1_STFERR_SHIFT                    10
+#define CAN_ESR1_FRMERR_MASK                     0x800u
+#define CAN_ESR1_FRMERR_SHIFT                    11
+#define CAN_ESR1_CRCERR_MASK                     0x1000u
+#define CAN_ESR1_CRCERR_SHIFT                    12
+#define CAN_ESR1_ACKERR_MASK                     0x2000u
+#define CAN_ESR1_ACKERR_SHIFT                    13
+#define CAN_ESR1_BIT0ERR_MASK                    0x4000u
+#define CAN_ESR1_BIT0ERR_SHIFT                   14
+#define CAN_ESR1_BIT1ERR_MASK                    0x8000u
+#define CAN_ESR1_BIT1ERR_SHIFT                   15
+#define CAN_ESR1_RWRNINT_MASK                    0x10000u
+#define CAN_ESR1_RWRNINT_SHIFT                   16
+#define CAN_ESR1_TWRNINT_MASK                    0x20000u
+#define CAN_ESR1_TWRNINT_SHIFT                   17
+#define CAN_ESR1_SYNCH_MASK                      0x40000u
+#define CAN_ESR1_SYNCH_SHIFT                     18
+/* IMASK2 Bit Fields */
+#define CAN_IMASK2_BUFHM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK2_BUFHM_SHIFT                   0
+#define CAN_IMASK2_BUFHM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK2_BUFHM_SHIFT))&CAN_IMASK2_BUFHM_MASK)
+/* IMASK1 Bit Fields */
+#define CAN_IMASK1_BUFLM_MASK                    0xFFFFFFFFu
+#define CAN_IMASK1_BUFLM_SHIFT                   0
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
+/* IFLAG2 Bit Fields */
+#define CAN_IFLAG2_BUFHI_MASK                    0xFFFFFFFFu
+#define CAN_IFLAG2_BUFHI_SHIFT                   0
+#define CAN_IFLAG2_BUFHI(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG2_BUFHI_SHIFT))&CAN_IFLAG2_BUFHI_MASK)
+/* IFLAG1 Bit Fields */
+#define CAN_IFLAG1_BUF4TO0I_MASK                 0x1Fu
+#define CAN_IFLAG1_BUF4TO0I_SHIFT                0
+#define CAN_IFLAG1_BUF4TO0I(x)                   (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO0I_SHIFT))&CAN_IFLAG1_BUF4TO0I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    0x20u
+#define CAN_IFLAG1_BUF5I_SHIFT                   5
+#define CAN_IFLAG1_BUF6I_MASK                    0x40u
+#define CAN_IFLAG1_BUF6I_SHIFT                   6
+#define CAN_IFLAG1_BUF7I_MASK                    0x80u
+#define CAN_IFLAG1_BUF7I_SHIFT                   7
+#define CAN_IFLAG1_BUF31TO8I_MASK                0xFFFFFF00u
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               8
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
+/* CTRL2 Bit Fields */
+#define CAN_CTRL2_EACEN_MASK                     0x10000u
+#define CAN_CTRL2_EACEN_SHIFT                    16
+#define CAN_CTRL2_RRS_MASK                       0x20000u
+#define CAN_CTRL2_RRS_SHIFT                      17
+#define CAN_CTRL2_MRP_MASK                       0x40000u
+#define CAN_CTRL2_MRP_SHIFT                      18
+#define CAN_CTRL2_TASD_MASK                      0xF80000u
+#define CAN_CTRL2_TASD_SHIFT                     19
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      0xF000000u
+#define CAN_CTRL2_RFFN_SHIFT                     24
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    0x10000000u
+#define CAN_CTRL2_WRMFRZ_SHIFT                   28
+/* ESR2 Bit Fields */
+#define CAN_ESR2_IMB_MASK                        0x2000u
+#define CAN_ESR2_IMB_SHIFT                       13
+#define CAN_ESR2_VPS_MASK                        0x4000u
+#define CAN_ESR2_VPS_SHIFT                       14
+#define CAN_ESR2_LPTM_MASK                       0x7F0000u
+#define CAN_ESR2_LPTM_SHIFT                      16
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
+/* CRCR Bit Fields */
+#define CAN_CRCR_TXCRC_MASK                      0x7FFFu
+#define CAN_CRCR_TXCRC_SHIFT                     0
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      0x7F0000u
+#define CAN_CRCR_MBCRC_SHIFT                     16
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
+/* RXFGMASK Bit Fields */
+#define CAN_RXFGMASK_FGM_MASK                    0xFFFFFFFFu
+#define CAN_RXFGMASK_FGM_SHIFT                   0
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
+/* RXFIR Bit Fields */
+#define CAN_RXFIR_IDHIT_MASK                     0x1FFu
+#define CAN_RXFIR_IDHIT_SHIFT                    0
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
+/* CS Bit Fields */
+#define CAN_CS_TIME_STAMP_MASK                   0xFFFFu
+#define CAN_CS_TIME_STAMP_SHIFT                  0
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          0xF0000u
+#define CAN_CS_DLC_SHIFT                         16
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          0x100000u
+#define CAN_CS_RTR_SHIFT                         20
+#define CAN_CS_IDE_MASK                          0x200000u
+#define CAN_CS_IDE_SHIFT                         21
+#define CAN_CS_SRR_MASK                          0x400000u
+#define CAN_CS_SRR_SHIFT                         22
+#define CAN_CS_CODE_MASK                         0xF000000u
+#define CAN_CS_CODE_SHIFT                        24
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
+/* ID Bit Fields */
+#define CAN_ID_EXT_MASK                          0x3FFFFu
+#define CAN_ID_EXT_SHIFT                         0
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          0x1FFC0000u
+#define CAN_ID_STD_SHIFT                         18
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         0xE0000000u
+#define CAN_ID_PRIO_SHIFT                        29
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
+/* WORD0 Bit Fields */
+#define CAN_WORD0_DATA_BYTE_3_MASK               0xFFu
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              0
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               0xFF00u
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              8
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               0xFF0000u
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              16
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               0xFF000000u
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              24
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
+/* WORD1 Bit Fields */
+#define CAN_WORD1_DATA_BYTE_7_MASK               0xFFu
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              0
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               0xFF00u
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              8
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               0xFF0000u
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              16
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               0xFF000000u
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              24
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
+/* RXIMR Bit Fields */
+#define CAN_RXIMR_MI_MASK                        0xFFFFFFFFu
+#define CAN_RXIMR_MI_SHIFT                       0
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
+
+/*! \} */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/*! Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/*! Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/*! Peripheral CAN1 base address */
+#define CAN1_BASE                                (0x400A4000u)
+/*! Peripheral CAN1 base pointer */
+#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+
+/*! \} */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer */
+/*! \{ */
+
+/*! CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /*!< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /*!< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /*!< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /*!< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /*!< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /*!< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CMP_Register_Masks CMP Register Masks */
+/*! \{ */
+
+/* CR0 Bit Fields */
+#define CMP_CR0_HYSTCTR_MASK                     0x3u
+#define CMP_CR0_HYSTCTR_SHIFT                    0
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  0x70u
+#define CMP_CR0_FILTER_CNT_SHIFT                 4
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
+/* CR1 Bit Fields */
+#define CMP_CR1_EN_MASK                          0x1u
+#define CMP_CR1_EN_SHIFT                         0
+#define CMP_CR1_OPE_MASK                         0x2u
+#define CMP_CR1_OPE_SHIFT                        1
+#define CMP_CR1_COS_MASK                         0x4u
+#define CMP_CR1_COS_SHIFT                        2
+#define CMP_CR1_INV_MASK                         0x8u
+#define CMP_CR1_INV_SHIFT                        3
+#define CMP_CR1_PMODE_MASK                       0x10u
+#define CMP_CR1_PMODE_SHIFT                      4
+#define CMP_CR1_WE_MASK                          0x40u
+#define CMP_CR1_WE_SHIFT                         6
+#define CMP_CR1_SE_MASK                          0x80u
+#define CMP_CR1_SE_SHIFT                         7
+/* FPR Bit Fields */
+#define CMP_FPR_FILT_PER_MASK                    0xFFu
+#define CMP_FPR_FILT_PER_SHIFT                   0
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
+/* SCR Bit Fields */
+#define CMP_SCR_COUT_MASK                        0x1u
+#define CMP_SCR_COUT_SHIFT                       0
+#define CMP_SCR_CFF_MASK                         0x2u
+#define CMP_SCR_CFF_SHIFT                        1
+#define CMP_SCR_CFR_MASK                         0x4u
+#define CMP_SCR_CFR_SHIFT                        2
+#define CMP_SCR_IEF_MASK                         0x8u
+#define CMP_SCR_IEF_SHIFT                        3
+#define CMP_SCR_IER_MASK                         0x10u
+#define CMP_SCR_IER_SHIFT                        4
+#define CMP_SCR_SMELB_MASK                       0x20u
+#define CMP_SCR_SMELB_SHIFT                      5
+#define CMP_SCR_DMAEN_MASK                       0x40u
+#define CMP_SCR_DMAEN_SHIFT                      6
+/* DACCR Bit Fields */
+#define CMP_DACCR_VOSEL_MASK                     0x3Fu
+#define CMP_DACCR_VOSEL_SHIFT                    0
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     0x40u
+#define CMP_DACCR_VRSEL_SHIFT                    6
+#define CMP_DACCR_DACEN_MASK                     0x80u
+#define CMP_DACCR_DACEN_SHIFT                    7
+/* MUXCR Bit Fields */
+#define CMP_MUXCR_MSEL_MASK                      0x7u
+#define CMP_MUXCR_MSEL_SHIFT                     0
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      0x38u
+#define CMP_MUXCR_PSEL_SHIFT                     3
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_MEN_MASK                       0x40u
+#define CMP_MUXCR_MEN_SHIFT                      6
+#define CMP_MUXCR_PEN_MASK                       0x80u
+#define CMP_MUXCR_PEN_SHIFT                      7
+
+/*! \} */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/*! Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/*! Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+/*! Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/*! Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+/*! Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/*! Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+
+/*! \} */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer */
+/*! \{ */
+
+/*! CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /*!< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /*!< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /*!< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /*!< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /*!< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /*!< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /*!< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /*!< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /*!< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /*!< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /*!< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /*!< CMT Direct Memory Access, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CMT_Register_Masks CMT Register Masks */
+/*! \{ */
+
+/* CGH1 Bit Fields */
+#define CMT_CGH1_PH_MASK                         0xFFu
+#define CMT_CGH1_PH_SHIFT                        0
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
+/* CGL1 Bit Fields */
+#define CMT_CGL1_PL_MASK                         0xFFu
+#define CMT_CGL1_PL_SHIFT                        0
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
+/* CGH2 Bit Fields */
+#define CMT_CGH2_SH_MASK                         0xFFu
+#define CMT_CGH2_SH_SHIFT                        0
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
+/* CGL2 Bit Fields */
+#define CMT_CGL2_SL_MASK                         0xFFu
+#define CMT_CGL2_SL_SHIFT                        0
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
+/* OC Bit Fields */
+#define CMT_OC_IROPEN_MASK                       0x20u
+#define CMT_OC_IROPEN_SHIFT                      5
+#define CMT_OC_CMTPOL_MASK                       0x40u
+#define CMT_OC_CMTPOL_SHIFT                      6
+#define CMT_OC_IROL_MASK                         0x80u
+#define CMT_OC_IROL_SHIFT                        7
+/* MSC Bit Fields */
+#define CMT_MSC_MCGEN_MASK                       0x1u
+#define CMT_MSC_MCGEN_SHIFT                      0
+#define CMT_MSC_EOCIE_MASK                       0x2u
+#define CMT_MSC_EOCIE_SHIFT                      1
+#define CMT_MSC_FSK_MASK                         0x4u
+#define CMT_MSC_FSK_SHIFT                        2
+#define CMT_MSC_BASE_MASK                        0x8u
+#define CMT_MSC_BASE_SHIFT                       3
+#define CMT_MSC_EXSPC_MASK                       0x10u
+#define CMT_MSC_EXSPC_SHIFT                      4
+#define CMT_MSC_CMTDIV_MASK                      0x60u
+#define CMT_MSC_CMTDIV_SHIFT                     5
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        0x80u
+#define CMT_MSC_EOCF_SHIFT                       7
+/* CMD1 Bit Fields */
+#define CMT_CMD1_MB_MASK                         0xFFu
+#define CMT_CMD1_MB_SHIFT                        0
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
+/* CMD2 Bit Fields */
+#define CMT_CMD2_MB_MASK                         0xFFu
+#define CMT_CMD2_MB_SHIFT                        0
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
+/* CMD3 Bit Fields */
+#define CMT_CMD3_SB_MASK                         0xFFu
+#define CMT_CMD3_SB_SHIFT                        0
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
+/* CMD4 Bit Fields */
+#define CMT_CMD4_SB_MASK                         0xFFu
+#define CMT_CMD4_SB_SHIFT                        0
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
+/* PPS Bit Fields */
+#define CMT_PPS_PPSDIV_MASK                      0xFu
+#define CMT_PPS_PPSDIV_SHIFT                     0
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
+/* DMA Bit Fields */
+#define CMT_DMA_DMA_MASK                         0x1u
+#define CMT_DMA_DMA_SHIFT                        0
+
+/*! \} */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/*! Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/*! Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+
+/*! \} */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer */
+/*! \{ */
+
+/*! CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    __IO uint32_t CRC;                               /*!< CRC Data Register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t CRCL;                              /*!< CRC_CRCL register., offset: 0x0 */
+      __IO uint16_t CRCH;                              /*!< CRC_CRCH register., offset: 0x2 */
+    } ACCESS16BIT;
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t CRCLL;                              /*!< CRC_CRCLL register., offset: 0x0 */
+      __IO uint8_t CRCLU;                              /*!< CRC_CRCLU register., offset: 0x1 */
+      __IO uint8_t CRCHL;                              /*!< CRC_CRCHL register., offset: 0x2 */
+      __IO uint8_t CRCHU;                              /*!< CRC_CRCHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    __IO uint32_t GPOLY;                             /*!< CRC Polynomial Register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /*!< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /*!< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /*!< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /*!< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /*!< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /*!< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  __IO uint32_t CTRL;                              /*!< CRC Control Register, offset: 0x8 */
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup CRC_Register_Masks CRC Register Masks */
+/*! \{ */
+
+/* CRC Bit Fields */
+#define CRC_CRC_LL_MASK                          0xFFu
+#define CRC_CRC_LL_SHIFT                         0
+#define CRC_CRC_LL(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LL_SHIFT))&CRC_CRC_LL_MASK)
+#define CRC_CRC_LU_MASK                          0xFF00u
+#define CRC_CRC_LU_SHIFT                         8
+#define CRC_CRC_LU(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_LU_SHIFT))&CRC_CRC_LU_MASK)
+#define CRC_CRC_HL_MASK                          0xFF0000u
+#define CRC_CRC_HL_SHIFT                         16
+#define CRC_CRC_HL(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HL_SHIFT))&CRC_CRC_HL_MASK)
+#define CRC_CRC_HU_MASK                          0xFF000000u
+#define CRC_CRC_HU_SHIFT                         24
+#define CRC_CRC_HU(x)                            (((uint32_t)(((uint32_t)(x))<<CRC_CRC_HU_SHIFT))&CRC_CRC_HU_MASK)
+/* CRCL Bit Fields */
+#define CRC_CRCL_CRCL_MASK                       0xFFFFu
+#define CRC_CRCL_CRCL_SHIFT                      0
+#define CRC_CRCL_CRCL(x)                         (((uint16_t)(((uint16_t)(x))<<CRC_CRCL_CRCL_SHIFT))&CRC_CRCL_CRCL_MASK)
+/* CRCH Bit Fields */
+#define CRC_CRCH_CRCH_MASK                       0xFFFFu
+#define CRC_CRCH_CRCH_SHIFT                      0
+#define CRC_CRCH_CRCH(x)                         (((uint16_t)(((uint16_t)(x))<<CRC_CRCH_CRCH_SHIFT))&CRC_CRCH_CRCH_MASK)
+/* CRCLL Bit Fields */
+#define CRC_CRCLL_CRCLL_MASK                     0xFFu
+#define CRC_CRCLL_CRCLL_SHIFT                    0
+#define CRC_CRCLL_CRCLL(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCLL_CRCLL_SHIFT))&CRC_CRCLL_CRCLL_MASK)
+/* CRCLU Bit Fields */
+#define CRC_CRCLU_CRCLU_MASK                     0xFFu
+#define CRC_CRCLU_CRCLU_SHIFT                    0
+#define CRC_CRCLU_CRCLU(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCLU_CRCLU_SHIFT))&CRC_CRCLU_CRCLU_MASK)
+/* CRCHL Bit Fields */
+#define CRC_CRCHL_CRCHL_MASK                     0xFFu
+#define CRC_CRCHL_CRCHL_SHIFT                    0
+#define CRC_CRCHL_CRCHL(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCHL_CRCHL_SHIFT))&CRC_CRCHL_CRCHL_MASK)
+/* CRCHU Bit Fields */
+#define CRC_CRCHU_CRCHU_MASK                     0xFFu
+#define CRC_CRCHU_CRCHU_SHIFT                    0
+#define CRC_CRCHU_CRCHU(x)                       (((uint8_t)(((uint8_t)(x))<<CRC_CRCHU_CRCHU_SHIFT))&CRC_CRCHU_CRCHU_MASK)
+/* GPOLY Bit Fields */
+#define CRC_GPOLY_LOW_MASK                       0xFFFFu
+#define CRC_GPOLY_LOW_SHIFT                      0
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      0xFFFF0000u
+#define CRC_GPOLY_HIGH_SHIFT                     16
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
+/* GPOLYL Bit Fields */
+#define CRC_GPOLYL_GPOLYL_MASK                   0xFFFFu
+#define CRC_GPOLYL_GPOLYL_SHIFT                  0
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
+/* GPOLYH Bit Fields */
+#define CRC_GPOLYH_GPOLYH_MASK                   0xFFFFu
+#define CRC_GPOLYH_GPOLYH_SHIFT                  0
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
+/* GPOLYLL Bit Fields */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 0xFFu
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                0
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
+/* GPOLYLU Bit Fields */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 0xFFu
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                0
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
+/* GPOLYHL Bit Fields */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 0xFFu
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                0
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
+/* GPOLYHU Bit Fields */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 0xFFu
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                0
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
+/* CTRL Bit Fields */
+#define CRC_CTRL_TCRC_MASK                       0x1000000u
+#define CRC_CTRL_TCRC_SHIFT                      24
+#define CRC_CTRL_WAS_MASK                        0x2000000u
+#define CRC_CTRL_WAS_SHIFT                       25
+#define CRC_CTRL_FXOR_MASK                       0x4000000u
+#define CRC_CTRL_FXOR_SHIFT                      26
+#define CRC_CTRL_TOTR_MASK                       0x30000000u
+#define CRC_CTRL_TOTR_SHIFT                      28
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        0xC0000000u
+#define CRC_CTRL_TOT_SHIFT                       30
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
+
+/*! \} */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/*! Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/*! Peripheral CRC base pointer */
+#define CRC                                      ((CRC_Type *)CRC_BASE)
+
+/*! \} */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer */
+/*! \{ */
+
+/*! DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /*!< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /*!< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /*!< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /*!< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /*!< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /*!< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup DAC_Register_Masks DAC Register Masks */
+/*! \{ */
+
+/* DATL Bit Fields */
+#define DAC_DATL_DATA_MASK                       0xFFu
+#define DAC_DATL_DATA_SHIFT                      0
+#define DAC_DATL_DATA(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA_SHIFT))&DAC_DATL_DATA_MASK)
+/* DATH Bit Fields */
+#define DAC_DATH_DATA_MASK                       0xFu
+#define DAC_DATH_DATA_SHIFT                      0
+#define DAC_DATH_DATA(x)                         (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA_SHIFT))&DAC_DATH_DATA_MASK)
+/* SR Bit Fields */
+#define DAC_SR_DACBFRPBF_MASK                    0x1u
+#define DAC_SR_DACBFRPBF_SHIFT                   0
+#define DAC_SR_DACBFRPTF_MASK                    0x2u
+#define DAC_SR_DACBFRPTF_SHIFT                   1
+#define DAC_SR_DACBFWMF_MASK                     0x4u
+#define DAC_SR_DACBFWMF_SHIFT                    2
+/* C0 Bit Fields */
+#define DAC_C0_DACBBIEN_MASK                     0x1u
+#define DAC_C0_DACBBIEN_SHIFT                    0
+#define DAC_C0_DACBTIEN_MASK                     0x2u
+#define DAC_C0_DACBTIEN_SHIFT                    1
+#define DAC_C0_DACBWIEN_MASK                     0x4u
+#define DAC_C0_DACBWIEN_SHIFT                    2
+#define DAC_C0_LPEN_MASK                         0x8u
+#define DAC_C0_LPEN_SHIFT                        3
+#define DAC_C0_DACSWTRG_MASK                     0x10u
+#define DAC_C0_DACSWTRG_SHIFT                    4
+#define DAC_C0_DACTRGSEL_MASK                    0x20u
+#define DAC_C0_DACTRGSEL_SHIFT                   5
+#define DAC_C0_DACRFS_MASK                       0x40u
+#define DAC_C0_DACRFS_SHIFT                      6
+#define DAC_C0_DACEN_MASK                        0x80u
+#define DAC_C0_DACEN_SHIFT                       7
+/* C1 Bit Fields */
+#define DAC_C1_DACBFEN_MASK                      0x1u
+#define DAC_C1_DACBFEN_SHIFT                     0
+#define DAC_C1_DACBFMD_MASK                      0x6u
+#define DAC_C1_DACBFMD_SHIFT                     1
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      0x18u
+#define DAC_C1_DACBFWM_SHIFT                     3
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        0x80u
+#define DAC_C1_DMAEN_SHIFT                       7
+/* C2 Bit Fields */
+#define DAC_C2_DACBFUP_MASK                      0xFu
+#define DAC_C2_DACBFUP_SHIFT                     0
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      0xF0u
+#define DAC_C2_DACBFRP_SHIFT                     4
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
+
+/*! \} */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/*! Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/*! Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+/*! Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/*! Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+
+/*! \} */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer */
+/*! \{ */
+
+/*! DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /*!< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /*!< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /*!< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /*!< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /*!< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /*!< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /*!< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /*!< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /*!< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /*!< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /*!< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /*!< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /*!< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /*!< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t HRS;                               /*!< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /*!< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /*!< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /*!< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /*!< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /*!< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /*!< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /*!< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /*!< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /*!< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /*!< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /*!< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /*!< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /*!< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /*!< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /*!< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /*!< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /*!< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /*!< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /*!< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /*!< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /*!< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /*!< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /*!< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /*!< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /*!< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /*!< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /*!< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /*!< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /*!< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /*!< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /*!< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup DMA_Register_Masks DMA Register Masks */
+/*! \{ */
+
+/* CR Bit Fields */
+#define DMA_CR_EDBG_MASK                         0x2u
+#define DMA_CR_EDBG_SHIFT                        1
+#define DMA_CR_ERCA_MASK                         0x4u
+#define DMA_CR_ERCA_SHIFT                        2
+#define DMA_CR_HOE_MASK                          0x10u
+#define DMA_CR_HOE_SHIFT                         4
+#define DMA_CR_HALT_MASK                         0x20u
+#define DMA_CR_HALT_SHIFT                        5
+#define DMA_CR_CLM_MASK                          0x40u
+#define DMA_CR_CLM_SHIFT                         6
+#define DMA_CR_EMLM_MASK                         0x80u
+#define DMA_CR_EMLM_SHIFT                        7
+#define DMA_CR_ECX_MASK                          0x10000u
+#define DMA_CR_ECX_SHIFT                         16
+#define DMA_CR_CX_MASK                           0x20000u
+#define DMA_CR_CX_SHIFT                          17
+/* ES Bit Fields */
+#define DMA_ES_DBE_MASK                          0x1u
+#define DMA_ES_DBE_SHIFT                         0
+#define DMA_ES_SBE_MASK                          0x2u
+#define DMA_ES_SBE_SHIFT                         1
+#define DMA_ES_SGE_MASK                          0x4u
+#define DMA_ES_SGE_SHIFT                         2
+#define DMA_ES_NCE_MASK                          0x8u
+#define DMA_ES_NCE_SHIFT                         3
+#define DMA_ES_DOE_MASK                          0x10u
+#define DMA_ES_DOE_SHIFT                         4
+#define DMA_ES_DAE_MASK                          0x20u
+#define DMA_ES_DAE_SHIFT                         5
+#define DMA_ES_SOE_MASK                          0x40u
+#define DMA_ES_SOE_SHIFT                         6
+#define DMA_ES_SAE_MASK                          0x80u
+#define DMA_ES_SAE_SHIFT                         7
+#define DMA_ES_ERRCHN_MASK                       0xF00u
+#define DMA_ES_ERRCHN_SHIFT                      8
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          0x4000u
+#define DMA_ES_CPE_SHIFT                         14
+#define DMA_ES_ECX_MASK                          0x10000u
+#define DMA_ES_ECX_SHIFT                         16
+#define DMA_ES_VLD_MASK                          0x80000000u
+#define DMA_ES_VLD_SHIFT                         31
+/* ERQ Bit Fields */
+#define DMA_ERQ_ERQ0_MASK                        0x1u
+#define DMA_ERQ_ERQ0_SHIFT                       0
+#define DMA_ERQ_ERQ1_MASK                        0x2u
+#define DMA_ERQ_ERQ1_SHIFT                       1
+#define DMA_ERQ_ERQ2_MASK                        0x4u
+#define DMA_ERQ_ERQ2_SHIFT                       2
+#define DMA_ERQ_ERQ3_MASK                        0x8u
+#define DMA_ERQ_ERQ3_SHIFT                       3
+#define DMA_ERQ_ERQ4_MASK                        0x10u
+#define DMA_ERQ_ERQ4_SHIFT                       4
+#define DMA_ERQ_ERQ5_MASK                        0x20u
+#define DMA_ERQ_ERQ5_SHIFT                       5
+#define DMA_ERQ_ERQ6_MASK                        0x40u
+#define DMA_ERQ_ERQ6_SHIFT                       6
+#define DMA_ERQ_ERQ7_MASK                        0x80u
+#define DMA_ERQ_ERQ7_SHIFT                       7
+#define DMA_ERQ_ERQ8_MASK                        0x100u
+#define DMA_ERQ_ERQ8_SHIFT                       8
+#define DMA_ERQ_ERQ9_MASK                        0x200u
+#define DMA_ERQ_ERQ9_SHIFT                       9
+#define DMA_ERQ_ERQ10_MASK                       0x400u
+#define DMA_ERQ_ERQ10_SHIFT                      10
+#define DMA_ERQ_ERQ11_MASK                       0x800u
+#define DMA_ERQ_ERQ11_SHIFT                      11
+#define DMA_ERQ_ERQ12_MASK                       0x1000u
+#define DMA_ERQ_ERQ12_SHIFT                      12
+#define DMA_ERQ_ERQ13_MASK                       0x2000u
+#define DMA_ERQ_ERQ13_SHIFT                      13
+#define DMA_ERQ_ERQ14_MASK                       0x4000u
+#define DMA_ERQ_ERQ14_SHIFT                      14
+#define DMA_ERQ_ERQ15_MASK                       0x8000u
+#define DMA_ERQ_ERQ15_SHIFT                      15
+/* EEI Bit Fields */
+#define DMA_EEI_EEI0_MASK                        0x1u
+#define DMA_EEI_EEI0_SHIFT                       0
+#define DMA_EEI_EEI1_MASK                        0x2u
+#define DMA_EEI_EEI1_SHIFT                       1
+#define DMA_EEI_EEI2_MASK                        0x4u
+#define DMA_EEI_EEI2_SHIFT                       2
+#define DMA_EEI_EEI3_MASK                        0x8u
+#define DMA_EEI_EEI3_SHIFT                       3
+#define DMA_EEI_EEI4_MASK                        0x10u
+#define DMA_EEI_EEI4_SHIFT                       4
+#define DMA_EEI_EEI5_MASK                        0x20u
+#define DMA_EEI_EEI5_SHIFT                       5
+#define DMA_EEI_EEI6_MASK                        0x40u
+#define DMA_EEI_EEI6_SHIFT                       6
+#define DMA_EEI_EEI7_MASK                        0x80u
+#define DMA_EEI_EEI7_SHIFT                       7
+#define DMA_EEI_EEI8_MASK                        0x100u
+#define DMA_EEI_EEI8_SHIFT                       8
+#define DMA_EEI_EEI9_MASK                        0x200u
+#define DMA_EEI_EEI9_SHIFT                       9
+#define DMA_EEI_EEI10_MASK                       0x400u
+#define DMA_EEI_EEI10_SHIFT                      10
+#define DMA_EEI_EEI11_MASK                       0x800u
+#define DMA_EEI_EEI11_SHIFT                      11
+#define DMA_EEI_EEI12_MASK                       0x1000u
+#define DMA_EEI_EEI12_SHIFT                      12
+#define DMA_EEI_EEI13_MASK                       0x2000u
+#define DMA_EEI_EEI13_SHIFT                      13
+#define DMA_EEI_EEI14_MASK                       0x4000u
+#define DMA_EEI_EEI14_SHIFT                      14
+#define DMA_EEI_EEI15_MASK                       0x8000u
+#define DMA_EEI_EEI15_SHIFT                      15
+/* CEEI Bit Fields */
+#define DMA_CEEI_CEEI_MASK                       0xFu
+#define DMA_CEEI_CEEI_SHIFT                      0
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       0x40u
+#define DMA_CEEI_CAEE_SHIFT                      6
+#define DMA_CEEI_NOP_MASK                        0x80u
+#define DMA_CEEI_NOP_SHIFT                       7
+/* SEEI Bit Fields */
+#define DMA_SEEI_SEEI_MASK                       0xFu
+#define DMA_SEEI_SEEI_SHIFT                      0
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       0x40u
+#define DMA_SEEI_SAEE_SHIFT                      6
+#define DMA_SEEI_NOP_MASK                        0x80u
+#define DMA_SEEI_NOP_SHIFT                       7
+/* CERQ Bit Fields */
+#define DMA_CERQ_CERQ_MASK                       0xFu
+#define DMA_CERQ_CERQ_SHIFT                      0
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       0x40u
+#define DMA_CERQ_CAER_SHIFT                      6
+#define DMA_CERQ_NOP_MASK                        0x80u
+#define DMA_CERQ_NOP_SHIFT                       7
+/* SERQ Bit Fields */
+#define DMA_SERQ_SERQ_MASK                       0xFu
+#define DMA_SERQ_SERQ_SHIFT                      0
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       0x40u
+#define DMA_SERQ_SAER_SHIFT                      6
+#define DMA_SERQ_NOP_MASK                        0x80u
+#define DMA_SERQ_NOP_SHIFT                       7
+/* CDNE Bit Fields */
+#define DMA_CDNE_CDNE_MASK                       0xFu
+#define DMA_CDNE_CDNE_SHIFT                      0
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       0x40u
+#define DMA_CDNE_CADN_SHIFT                      6
+#define DMA_CDNE_NOP_MASK                        0x80u
+#define DMA_CDNE_NOP_SHIFT                       7
+/* SSRT Bit Fields */
+#define DMA_SSRT_SSRT_MASK                       0xFu
+#define DMA_SSRT_SSRT_SHIFT                      0
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       0x40u
+#define DMA_SSRT_SAST_SHIFT                      6
+#define DMA_SSRT_NOP_MASK                        0x80u
+#define DMA_SSRT_NOP_SHIFT                       7
+/* CERR Bit Fields */
+#define DMA_CERR_CERR_MASK                       0xFu
+#define DMA_CERR_CERR_SHIFT                      0
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       0x40u
+#define DMA_CERR_CAEI_SHIFT                      6
+#define DMA_CERR_NOP_MASK                        0x80u
+#define DMA_CERR_NOP_SHIFT                       7
+/* CINT Bit Fields */
+#define DMA_CINT_CINT_MASK                       0xFu
+#define DMA_CINT_CINT_SHIFT                      0
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       0x40u
+#define DMA_CINT_CAIR_SHIFT                      6
+#define DMA_CINT_NOP_MASK                        0x80u
+#define DMA_CINT_NOP_SHIFT                       7
+/* INT Bit Fields */
+#define DMA_INT_INT0_MASK                        0x1u
+#define DMA_INT_INT0_SHIFT                       0
+#define DMA_INT_INT1_MASK                        0x2u
+#define DMA_INT_INT1_SHIFT                       1
+#define DMA_INT_INT2_MASK                        0x4u
+#define DMA_INT_INT2_SHIFT                       2
+#define DMA_INT_INT3_MASK                        0x8u
+#define DMA_INT_INT3_SHIFT                       3
+#define DMA_INT_INT4_MASK                        0x10u
+#define DMA_INT_INT4_SHIFT                       4
+#define DMA_INT_INT5_MASK                        0x20u
+#define DMA_INT_INT5_SHIFT                       5
+#define DMA_INT_INT6_MASK                        0x40u
+#define DMA_INT_INT6_SHIFT                       6
+#define DMA_INT_INT7_MASK                        0x80u
+#define DMA_INT_INT7_SHIFT                       7
+#define DMA_INT_INT8_MASK                        0x100u
+#define DMA_INT_INT8_SHIFT                       8
+#define DMA_INT_INT9_MASK                        0x200u
+#define DMA_INT_INT9_SHIFT                       9
+#define DMA_INT_INT10_MASK                       0x400u
+#define DMA_INT_INT10_SHIFT                      10
+#define DMA_INT_INT11_MASK                       0x800u
+#define DMA_INT_INT11_SHIFT                      11
+#define DMA_INT_INT12_MASK                       0x1000u
+#define DMA_INT_INT12_SHIFT                      12
+#define DMA_INT_INT13_MASK                       0x2000u
+#define DMA_INT_INT13_SHIFT                      13
+#define DMA_INT_INT14_MASK                       0x4000u
+#define DMA_INT_INT14_SHIFT                      14
+#define DMA_INT_INT15_MASK                       0x8000u
+#define DMA_INT_INT15_SHIFT                      15
+/* ERR Bit Fields */
+#define DMA_ERR_ERR0_MASK                        0x1u
+#define DMA_ERR_ERR0_SHIFT                       0
+#define DMA_ERR_ERR1_MASK                        0x2u
+#define DMA_ERR_ERR1_SHIFT                       1
+#define DMA_ERR_ERR2_MASK                        0x4u
+#define DMA_ERR_ERR2_SHIFT                       2
+#define DMA_ERR_ERR3_MASK                        0x8u
+#define DMA_ERR_ERR3_SHIFT                       3
+#define DMA_ERR_ERR4_MASK                        0x10u
+#define DMA_ERR_ERR4_SHIFT                       4
+#define DMA_ERR_ERR5_MASK                        0x20u
+#define DMA_ERR_ERR5_SHIFT                       5
+#define DMA_ERR_ERR6_MASK                        0x40u
+#define DMA_ERR_ERR6_SHIFT                       6
+#define DMA_ERR_ERR7_MASK                        0x80u
+#define DMA_ERR_ERR7_SHIFT                       7
+#define DMA_ERR_ERR8_MASK                        0x100u
+#define DMA_ERR_ERR8_SHIFT                       8
+#define DMA_ERR_ERR9_MASK                        0x200u
+#define DMA_ERR_ERR9_SHIFT                       9
+#define DMA_ERR_ERR10_MASK                       0x400u
+#define DMA_ERR_ERR10_SHIFT                      10
+#define DMA_ERR_ERR11_MASK                       0x800u
+#define DMA_ERR_ERR11_SHIFT                      11
+#define DMA_ERR_ERR12_MASK                       0x1000u
+#define DMA_ERR_ERR12_SHIFT                      12
+#define DMA_ERR_ERR13_MASK                       0x2000u
+#define DMA_ERR_ERR13_SHIFT                      13
+#define DMA_ERR_ERR14_MASK                       0x4000u
+#define DMA_ERR_ERR14_SHIFT                      14
+#define DMA_ERR_ERR15_MASK                       0x8000u
+#define DMA_ERR_ERR15_SHIFT                      15
+/* HRS Bit Fields */
+#define DMA_HRS_HRS0_MASK                        0x1u
+#define DMA_HRS_HRS0_SHIFT                       0
+#define DMA_HRS_HRS1_MASK                        0x2u
+#define DMA_HRS_HRS1_SHIFT                       1
+#define DMA_HRS_HRS2_MASK                        0x4u
+#define DMA_HRS_HRS2_SHIFT                       2
+#define DMA_HRS_HRS3_MASK                        0x8u
+#define DMA_HRS_HRS3_SHIFT                       3
+#define DMA_HRS_HRS4_MASK                        0x10u
+#define DMA_HRS_HRS4_SHIFT                       4
+#define DMA_HRS_HRS5_MASK                        0x20u
+#define DMA_HRS_HRS5_SHIFT                       5
+#define DMA_HRS_HRS6_MASK                        0x40u
+#define DMA_HRS_HRS6_SHIFT                       6
+#define DMA_HRS_HRS7_MASK                        0x80u
+#define DMA_HRS_HRS7_SHIFT                       7
+#define DMA_HRS_HRS8_MASK                        0x100u
+#define DMA_HRS_HRS8_SHIFT                       8
+#define DMA_HRS_HRS9_MASK                        0x200u
+#define DMA_HRS_HRS9_SHIFT                       9
+#define DMA_HRS_HRS10_MASK                       0x400u
+#define DMA_HRS_HRS10_SHIFT                      10
+#define DMA_HRS_HRS11_MASK                       0x800u
+#define DMA_HRS_HRS11_SHIFT                      11
+#define DMA_HRS_HRS12_MASK                       0x1000u
+#define DMA_HRS_HRS12_SHIFT                      12
+#define DMA_HRS_HRS13_MASK                       0x2000u
+#define DMA_HRS_HRS13_SHIFT                      13
+#define DMA_HRS_HRS14_MASK                       0x4000u
+#define DMA_HRS_HRS14_SHIFT                      14
+#define DMA_HRS_HRS15_MASK                       0x8000u
+#define DMA_HRS_HRS15_SHIFT                      15
+/* DCHPRI3 Bit Fields */
+#define DMA_DCHPRI3_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI3_CHPRI_SHIFT                  0
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     0x40u
+#define DMA_DCHPRI3_DPA_SHIFT                    6
+#define DMA_DCHPRI3_ECP_MASK                     0x80u
+#define DMA_DCHPRI3_ECP_SHIFT                    7
+/* DCHPRI2 Bit Fields */
+#define DMA_DCHPRI2_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI2_CHPRI_SHIFT                  0
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     0x40u
+#define DMA_DCHPRI2_DPA_SHIFT                    6
+#define DMA_DCHPRI2_ECP_MASK                     0x80u
+#define DMA_DCHPRI2_ECP_SHIFT                    7
+/* DCHPRI1 Bit Fields */
+#define DMA_DCHPRI1_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI1_CHPRI_SHIFT                  0
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     0x40u
+#define DMA_DCHPRI1_DPA_SHIFT                    6
+#define DMA_DCHPRI1_ECP_MASK                     0x80u
+#define DMA_DCHPRI1_ECP_SHIFT                    7
+/* DCHPRI0 Bit Fields */
+#define DMA_DCHPRI0_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI0_CHPRI_SHIFT                  0
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     0x40u
+#define DMA_DCHPRI0_DPA_SHIFT                    6
+#define DMA_DCHPRI0_ECP_MASK                     0x80u
+#define DMA_DCHPRI0_ECP_SHIFT                    7
+/* DCHPRI7 Bit Fields */
+#define DMA_DCHPRI7_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI7_CHPRI_SHIFT                  0
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     0x40u
+#define DMA_DCHPRI7_DPA_SHIFT                    6
+#define DMA_DCHPRI7_ECP_MASK                     0x80u
+#define DMA_DCHPRI7_ECP_SHIFT                    7
+/* DCHPRI6 Bit Fields */
+#define DMA_DCHPRI6_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI6_CHPRI_SHIFT                  0
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     0x40u
+#define DMA_DCHPRI6_DPA_SHIFT                    6
+#define DMA_DCHPRI6_ECP_MASK                     0x80u
+#define DMA_DCHPRI6_ECP_SHIFT                    7
+/* DCHPRI5 Bit Fields */
+#define DMA_DCHPRI5_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI5_CHPRI_SHIFT                  0
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     0x40u
+#define DMA_DCHPRI5_DPA_SHIFT                    6
+#define DMA_DCHPRI5_ECP_MASK                     0x80u
+#define DMA_DCHPRI5_ECP_SHIFT                    7
+/* DCHPRI4 Bit Fields */
+#define DMA_DCHPRI4_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI4_CHPRI_SHIFT                  0
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     0x40u
+#define DMA_DCHPRI4_DPA_SHIFT                    6
+#define DMA_DCHPRI4_ECP_MASK                     0x80u
+#define DMA_DCHPRI4_ECP_SHIFT                    7
+/* DCHPRI11 Bit Fields */
+#define DMA_DCHPRI11_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI11_CHPRI_SHIFT                 0
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    0x40u
+#define DMA_DCHPRI11_DPA_SHIFT                   6
+#define DMA_DCHPRI11_ECP_MASK                    0x80u
+#define DMA_DCHPRI11_ECP_SHIFT                   7
+/* DCHPRI10 Bit Fields */
+#define DMA_DCHPRI10_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI10_CHPRI_SHIFT                 0
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    0x40u
+#define DMA_DCHPRI10_DPA_SHIFT                   6
+#define DMA_DCHPRI10_ECP_MASK                    0x80u
+#define DMA_DCHPRI10_ECP_SHIFT                   7
+/* DCHPRI9 Bit Fields */
+#define DMA_DCHPRI9_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI9_CHPRI_SHIFT                  0
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     0x40u
+#define DMA_DCHPRI9_DPA_SHIFT                    6
+#define DMA_DCHPRI9_ECP_MASK                     0x80u
+#define DMA_DCHPRI9_ECP_SHIFT                    7
+/* DCHPRI8 Bit Fields */
+#define DMA_DCHPRI8_CHPRI_MASK                   0xFu
+#define DMA_DCHPRI8_CHPRI_SHIFT                  0
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     0x40u
+#define DMA_DCHPRI8_DPA_SHIFT                    6
+#define DMA_DCHPRI8_ECP_MASK                     0x80u
+#define DMA_DCHPRI8_ECP_SHIFT                    7
+/* DCHPRI15 Bit Fields */
+#define DMA_DCHPRI15_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI15_CHPRI_SHIFT                 0
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    0x40u
+#define DMA_DCHPRI15_DPA_SHIFT                   6
+#define DMA_DCHPRI15_ECP_MASK                    0x80u
+#define DMA_DCHPRI15_ECP_SHIFT                   7
+/* DCHPRI14 Bit Fields */
+#define DMA_DCHPRI14_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI14_CHPRI_SHIFT                 0
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    0x40u
+#define DMA_DCHPRI14_DPA_SHIFT                   6
+#define DMA_DCHPRI14_ECP_MASK                    0x80u
+#define DMA_DCHPRI14_ECP_SHIFT                   7
+/* DCHPRI13 Bit Fields */
+#define DMA_DCHPRI13_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI13_CHPRI_SHIFT                 0
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    0x40u
+#define DMA_DCHPRI13_DPA_SHIFT                   6
+#define DMA_DCHPRI13_ECP_MASK                    0x80u
+#define DMA_DCHPRI13_ECP_SHIFT                   7
+/* DCHPRI12 Bit Fields */
+#define DMA_DCHPRI12_CHPRI_MASK                  0xFu
+#define DMA_DCHPRI12_CHPRI_SHIFT                 0
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    0x40u
+#define DMA_DCHPRI12_DPA_SHIFT                   6
+#define DMA_DCHPRI12_ECP_MASK                    0x80u
+#define DMA_DCHPRI12_ECP_SHIFT                   7
+/* SADDR Bit Fields */
+#define DMA_SADDR_SADDR_MASK                     0xFFFFFFFFu
+#define DMA_SADDR_SADDR_SHIFT                    0
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
+/* SOFF Bit Fields */
+#define DMA_SOFF_SOFF_MASK                       0xFFFFu
+#define DMA_SOFF_SOFF_SHIFT                      0
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
+/* ATTR Bit Fields */
+#define DMA_ATTR_DSIZE_MASK                      0x7u
+#define DMA_ATTR_DSIZE_SHIFT                     0
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       0xF8u
+#define DMA_ATTR_DMOD_SHIFT                      3
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      0x700u
+#define DMA_ATTR_SSIZE_SHIFT                     8
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       0xF800u
+#define DMA_ATTR_SMOD_SHIFT                      11
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
+/* NBYTES_MLNO Bit Fields */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              0xFFFFFFFFu
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             0
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
+/* NBYTES_MLOFFNO Bit Fields */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           0x3FFFFFFFu
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          0
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            0x40000000u
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           30
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            0x80000000u
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           31
+/* NBYTES_MLOFFYES Bit Fields */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          0x3FFu
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         0
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           0x3FFFFC00u
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          10
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           0x40000000u
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          30
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           0x80000000u
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          31
+/* SLAST Bit Fields */
+#define DMA_SLAST_SLAST_MASK                     0xFFFFFFFFu
+#define DMA_SLAST_SLAST_SHIFT                    0
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
+/* DADDR Bit Fields */
+#define DMA_DADDR_DADDR_MASK                     0xFFFFFFFFu
+#define DMA_DADDR_DADDR_SHIFT                    0
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
+/* DOFF Bit Fields */
+#define DMA_DOFF_DOFF_MASK                       0xFFFFu
+#define DMA_DOFF_DOFF_SHIFT                      0
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
+/* CITER_ELINKYES Bit Fields */
+#define DMA_CITER_ELINKYES_CITER_MASK            0x1FFu
+#define DMA_CITER_ELINKYES_CITER_SHIFT           0
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           15
+/* CITER_ELINKNO Bit Fields */
+#define DMA_CITER_ELINKNO_CITER_MASK             0x7FFFu
+#define DMA_CITER_ELINKNO_CITER_SHIFT            0
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            15
+/* DLAST_SGA Bit Fields */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              0xFFFFFFFFu
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             0
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
+/* CSR Bit Fields */
+#define DMA_CSR_START_MASK                       0x1u
+#define DMA_CSR_START_SHIFT                      0
+#define DMA_CSR_INTMAJOR_MASK                    0x2u
+#define DMA_CSR_INTMAJOR_SHIFT                   1
+#define DMA_CSR_INTHALF_MASK                     0x4u
+#define DMA_CSR_INTHALF_SHIFT                    2
+#define DMA_CSR_DREQ_MASK                        0x8u
+#define DMA_CSR_DREQ_SHIFT                       3
+#define DMA_CSR_ESG_MASK                         0x10u
+#define DMA_CSR_ESG_SHIFT                        4
+#define DMA_CSR_MAJORELINK_MASK                  0x20u
+#define DMA_CSR_MAJORELINK_SHIFT                 5
+#define DMA_CSR_ACTIVE_MASK                      0x40u
+#define DMA_CSR_ACTIVE_SHIFT                     6
+#define DMA_CSR_DONE_MASK                        0x80u
+#define DMA_CSR_DONE_SHIFT                       7
+#define DMA_CSR_MAJORLINKCH_MASK                 0xF00u
+#define DMA_CSR_MAJORLINKCH_SHIFT                8
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         0xC000u
+#define DMA_CSR_BWC_SHIFT                        14
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
+/* BITER_ELINKNO Bit Fields */
+#define DMA_BITER_ELINKNO_BITER_MASK             0x7FFFu
+#define DMA_BITER_ELINKNO_BITER_SHIFT            0
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             0x8000u
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            15
+/* BITER_ELINKYES Bit Fields */
+#define DMA_BITER_ELINKYES_BITER_MASK            0x1FFu
+#define DMA_BITER_ELINKYES_BITER_SHIFT           0
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           0x1E00u
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          9
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            0x8000u
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           15
+
+/*! \} */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/*! Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/*! Peripheral DMA base pointer */
+#define DMA                                      ((DMA_Type *)DMA_BASE)
+
+/*! \} */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer */
+/*! \{ */
+
+/*! DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /*!< Channel Configuration Register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup DMAMUX_Register_Masks DMAMUX Register Masks */
+/*! \{ */
+
+/* CHCFG Bit Fields */
+#define DMAMUX_CHCFG_SOURCE_MASK                 0x3Fu
+#define DMAMUX_CHCFG_SOURCE_SHIFT                0
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   0x40u
+#define DMAMUX_CHCFG_TRIG_SHIFT                  6
+#define DMAMUX_CHCFG_ENBL_MASK                   0x80u
+#define DMAMUX_CHCFG_ENBL_SHIFT                  7
+
+/*! \} */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/*! Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/*! Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+
+/*! \} */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer */
+/*! \{ */
+
+/*! EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /*!< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /*!< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /*!< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /*!< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup EWM_Register_Masks EWM Register Masks */
+/*! \{ */
+
+/* CTRL Bit Fields */
+#define EWM_CTRL_EWMEN_MASK                      0x1u
+#define EWM_CTRL_EWMEN_SHIFT                     0
+#define EWM_CTRL_ASSIN_MASK                      0x2u
+#define EWM_CTRL_ASSIN_SHIFT                     1
+#define EWM_CTRL_INEN_MASK                       0x4u
+#define EWM_CTRL_INEN_SHIFT                      2
+/* SERV Bit Fields */
+#define EWM_SERV_SERVICE_MASK                    0xFFu
+#define EWM_SERV_SERVICE_SHIFT                   0
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
+/* CMPL Bit Fields */
+#define EWM_CMPL_COMPAREL_MASK                   0xFFu
+#define EWM_CMPL_COMPAREL_SHIFT                  0
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
+/* CMPH Bit Fields */
+#define EWM_CMPH_COMPAREH_MASK                   0xFFu
+#define EWM_CMPH_COMPAREH_SHIFT                  0
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
+
+/*! \} */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/*! Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/*! Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+
+/*! \} */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer */
+/*! \{ */
+
+/*! FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /*!< Chip select address register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /*!< Chip select mask register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /*!< Chip select control register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /*!< Chip select port multiplexing control register, offset: 0x60 */
+} FB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FB_Register_Masks FB Register Masks */
+/*! \{ */
+
+/* CSAR Bit Fields */
+#define FB_CSAR_BA_MASK                          0xFFFF0000u
+#define FB_CSAR_BA_SHIFT                         16
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
+/* CSMR Bit Fields */
+#define FB_CSMR_V_MASK                           0x1u
+#define FB_CSMR_V_SHIFT                          0
+#define FB_CSMR_WP_MASK                          0x100u
+#define FB_CSMR_WP_SHIFT                         8
+#define FB_CSMR_BAM_MASK                         0xFFFF0000u
+#define FB_CSMR_BAM_SHIFT                        16
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
+/* CSCR Bit Fields */
+#define FB_CSCR_BSTW_MASK                        0x8u
+#define FB_CSCR_BSTW_SHIFT                       3
+#define FB_CSCR_BSTR_MASK                        0x10u
+#define FB_CSCR_BSTR_SHIFT                       4
+#define FB_CSCR_BEM_MASK                         0x20u
+#define FB_CSCR_BEM_SHIFT                        5
+#define FB_CSCR_PS_MASK                          0xC0u
+#define FB_CSCR_PS_SHIFT                         6
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          0x100u
+#define FB_CSCR_AA_SHIFT                         8
+#define FB_CSCR_BLS_MASK                         0x200u
+#define FB_CSCR_BLS_SHIFT                        9
+#define FB_CSCR_WS_MASK                          0xFC00u
+#define FB_CSCR_WS_SHIFT                         10
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        0x30000u
+#define FB_CSCR_WRAH_SHIFT                       16
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        0xC0000u
+#define FB_CSCR_RDAH_SHIFT                       18
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        0x300000u
+#define FB_CSCR_ASET_SHIFT                       20
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXALE_MASK                       0x400000u
+#define FB_CSCR_EXALE_SHIFT                      22
+#define FB_CSCR_SWSEN_MASK                       0x800000u
+#define FB_CSCR_SWSEN_SHIFT                      23
+#define FB_CSCR_SWS_MASK                         0xFC000000u
+#define FB_CSCR_SWS_SHIFT                        26
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
+/* CSPMCR Bit Fields */
+#define FB_CSPMCR_GROUP5_MASK                    0xF000u
+#define FB_CSPMCR_GROUP5_SHIFT                   12
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    0xF0000u
+#define FB_CSPMCR_GROUP4_SHIFT                   16
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    0xF00000u
+#define FB_CSPMCR_GROUP3_SHIFT                   20
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    0xF000000u
+#define FB_CSPMCR_GROUP2_SHIFT                   24
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    0xF0000000u
+#define FB_CSPMCR_GROUP1_SHIFT                   28
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
+
+/*! \} */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/*! Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/*! Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+
+/*! \} */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer */
+/*! \{ */
+
+/*! FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /*!< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /*!< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /*!< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVD[4][8];                       /*!< Cache Directory Storage, array offset: 0x100, array step: index*0x20, index2*0x4 */
+       uint8_t RESERVED_1[128];
+  struct {                                         /* offset: 0x200, array step: index*0x40, index2*0x8 */
+    __IO uint32_t DATA_U;                            /*!< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
+    __IO uint32_t DATA_L;                            /*!< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
+  } SET[4][8];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FMC_Register_Masks FMC Register Masks */
+/*! \{ */
+
+/* PFAPR Bit Fields */
+#define FMC_PFAPR_M0AP_MASK                      0x3u
+#define FMC_PFAPR_M0AP_SHIFT                     0
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      0xCu
+#define FMC_PFAPR_M1AP_SHIFT                     2
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      0x30u
+#define FMC_PFAPR_M2AP_SHIFT                     4
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      0xC0u
+#define FMC_PFAPR_M3AP_SHIFT                     6
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      0x300u
+#define FMC_PFAPR_M4AP_SHIFT                     8
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      0xC00u
+#define FMC_PFAPR_M5AP_SHIFT                     10
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      0x3000u
+#define FMC_PFAPR_M6AP_SHIFT                     12
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      0xC000u
+#define FMC_PFAPR_M7AP_SHIFT                     14
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     0x10000u
+#define FMC_PFAPR_M0PFD_SHIFT                    16
+#define FMC_PFAPR_M1PFD_MASK                     0x20000u
+#define FMC_PFAPR_M1PFD_SHIFT                    17
+#define FMC_PFAPR_M2PFD_MASK                     0x40000u
+#define FMC_PFAPR_M2PFD_SHIFT                    18
+#define FMC_PFAPR_M3PFD_MASK                     0x80000u
+#define FMC_PFAPR_M3PFD_SHIFT                    19
+#define FMC_PFAPR_M4PFD_MASK                     0x100000u
+#define FMC_PFAPR_M4PFD_SHIFT                    20
+#define FMC_PFAPR_M5PFD_MASK                     0x200000u
+#define FMC_PFAPR_M5PFD_SHIFT                    21
+#define FMC_PFAPR_M6PFD_MASK                     0x400000u
+#define FMC_PFAPR_M6PFD_SHIFT                    22
+#define FMC_PFAPR_M7PFD_MASK                     0x800000u
+#define FMC_PFAPR_M7PFD_SHIFT                    23
+/* PFB0CR Bit Fields */
+#define FMC_PFB0CR_B0SEBE_MASK                   0x1u
+#define FMC_PFB0CR_B0SEBE_SHIFT                  0
+#define FMC_PFB0CR_B0IPE_MASK                    0x2u
+#define FMC_PFB0CR_B0IPE_SHIFT                   1
+#define FMC_PFB0CR_B0DPE_MASK                    0x4u
+#define FMC_PFB0CR_B0DPE_SHIFT                   2
+#define FMC_PFB0CR_B0ICE_MASK                    0x8u
+#define FMC_PFB0CR_B0ICE_SHIFT                   3
+#define FMC_PFB0CR_B0DCE_MASK                    0x10u
+#define FMC_PFB0CR_B0DCE_SHIFT                   4
+#define FMC_PFB0CR_CRC_MASK                      0xE0u
+#define FMC_PFB0CR_CRC_SHIFT                     5
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     0x60000u
+#define FMC_PFB0CR_B0MW_SHIFT                    17
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV_MASK                  0x80000u
+#define FMC_PFB0CR_S_B_INV_SHIFT                 19
+#define FMC_PFB0CR_CINV_WAY_MASK                 0xF00000u
+#define FMC_PFB0CR_CINV_WAY_SHIFT                20
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 0xF000000u
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                24
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   0xF0000000u
+#define FMC_PFB0CR_B0RWSC_SHIFT                  28
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
+/* PFB1CR Bit Fields */
+#define FMC_PFB1CR_B1SEBE_MASK                   0x1u
+#define FMC_PFB1CR_B1SEBE_SHIFT                  0
+#define FMC_PFB1CR_B1IPE_MASK                    0x2u
+#define FMC_PFB1CR_B1IPE_SHIFT                   1
+#define FMC_PFB1CR_B1DPE_MASK                    0x4u
+#define FMC_PFB1CR_B1DPE_SHIFT                   2
+#define FMC_PFB1CR_B1ICE_MASK                    0x8u
+#define FMC_PFB1CR_B1ICE_SHIFT                   3
+#define FMC_PFB1CR_B1DCE_MASK                    0x10u
+#define FMC_PFB1CR_B1DCE_SHIFT                   4
+#define FMC_PFB1CR_B1MW_MASK                     0x60000u
+#define FMC_PFB1CR_B1MW_SHIFT                    17
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   0xF0000000u
+#define FMC_PFB1CR_B1RWSC_SHIFT                  28
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
+/* TAGVD Bit Fields */
+#define FMC_TAGVD_valid_MASK                     0x1u
+#define FMC_TAGVD_valid_SHIFT                    0
+#define FMC_TAGVD_tag_MASK                       0x7FFC0u
+#define FMC_TAGVD_tag_SHIFT                      6
+#define FMC_TAGVD_tag(x)                         (((uint32_t)(((uint32_t)(x))<<FMC_TAGVD_tag_SHIFT))&FMC_TAGVD_tag_MASK)
+/* DATA_U Bit Fields */
+#define FMC_DATA_U_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_U_data_SHIFT                    0
+#define FMC_DATA_U_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
+/* DATA_L Bit Fields */
+#define FMC_DATA_L_data_MASK                     0xFFFFFFFFu
+#define FMC_DATA_L_data_SHIFT                    0
+#define FMC_DATA_L_data(x)                       (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
+
+/*! \} */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/*! Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/*! Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+
+/*! \} */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFL Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FTFL_Peripheral_Access_Layer FTFL Peripheral Access Layer */
+/*! \{ */
+
+/*! FTFL - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /*!< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /*!< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /*!< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /*!< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /*!< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /*!< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /*!< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /*!< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /*!< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /*!< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /*!< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /*!< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /*!< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /*!< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /*!< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /*!< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /*!< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /*!< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /*!< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /*!< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /*!< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /*!< Data Flash Protection Register, offset: 0x17 */
+} FTFL_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFL Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FTFL_Register_Masks FTFL Register Masks */
+/*! \{ */
+
+/* FSTAT Bit Fields */
+#define FTFL_FSTAT_MGSTAT0_MASK                  0x1u
+#define FTFL_FSTAT_MGSTAT0_SHIFT                 0
+#define FTFL_FSTAT_FPVIOL_MASK                   0x10u
+#define FTFL_FSTAT_FPVIOL_SHIFT                  4
+#define FTFL_FSTAT_ACCERR_MASK                   0x20u
+#define FTFL_FSTAT_ACCERR_SHIFT                  5
+#define FTFL_FSTAT_RDCOLERR_MASK                 0x40u
+#define FTFL_FSTAT_RDCOLERR_SHIFT                6
+#define FTFL_FSTAT_CCIF_MASK                     0x80u
+#define FTFL_FSTAT_CCIF_SHIFT                    7
+/* FCNFG Bit Fields */
+#define FTFL_FCNFG_EEERDY_MASK                   0x1u
+#define FTFL_FCNFG_EEERDY_SHIFT                  0
+#define FTFL_FCNFG_RAMRDY_MASK                   0x2u
+#define FTFL_FCNFG_RAMRDY_SHIFT                  1
+#define FTFL_FCNFG_PFLSH_MASK                    0x4u
+#define FTFL_FCNFG_PFLSH_SHIFT                   2
+#define FTFL_FCNFG_SWAP_MASK                     0x8u
+#define FTFL_FCNFG_SWAP_SHIFT                    3
+#define FTFL_FCNFG_ERSSUSP_MASK                  0x10u
+#define FTFL_FCNFG_ERSSUSP_SHIFT                 4
+#define FTFL_FCNFG_ERSAREQ_MASK                  0x20u
+#define FTFL_FCNFG_ERSAREQ_SHIFT                 5
+#define FTFL_FCNFG_RDCOLLIE_MASK                 0x40u
+#define FTFL_FCNFG_RDCOLLIE_SHIFT                6
+#define FTFL_FCNFG_CCIE_MASK                     0x80u
+#define FTFL_FCNFG_CCIE_SHIFT                    7
+/* FSEC Bit Fields */
+#define FTFL_FSEC_SEC_MASK                       0x3u
+#define FTFL_FSEC_SEC_SHIFT                      0
+#define FTFL_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_SEC_SHIFT))&FTFL_FSEC_SEC_MASK)
+#define FTFL_FSEC_FSLACC_MASK                    0xCu
+#define FTFL_FSEC_FSLACC_SHIFT                   2
+#define FTFL_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_FSLACC_SHIFT))&FTFL_FSEC_FSLACC_MASK)
+#define FTFL_FSEC_MEEN_MASK                      0x30u
+#define FTFL_FSEC_MEEN_SHIFT                     4
+#define FTFL_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_MEEN_SHIFT))&FTFL_FSEC_MEEN_MASK)
+#define FTFL_FSEC_KEYEN_MASK                     0xC0u
+#define FTFL_FSEC_KEYEN_SHIFT                    6
+#define FTFL_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x))<<FTFL_FSEC_KEYEN_SHIFT))&FTFL_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define FTFL_FOPT_OPT_MASK                       0xFFu
+#define FTFL_FOPT_OPT_SHIFT                      0
+#define FTFL_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x))<<FTFL_FOPT_OPT_SHIFT))&FTFL_FOPT_OPT_MASK)
+/* FCCOB3 Bit Fields */
+#define FTFL_FCCOB3_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB3_CCOBn_SHIFT                  0
+#define FTFL_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB3_CCOBn_SHIFT))&FTFL_FCCOB3_CCOBn_MASK)
+/* FCCOB2 Bit Fields */
+#define FTFL_FCCOB2_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB2_CCOBn_SHIFT                  0
+#define FTFL_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB2_CCOBn_SHIFT))&FTFL_FCCOB2_CCOBn_MASK)
+/* FCCOB1 Bit Fields */
+#define FTFL_FCCOB1_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB1_CCOBn_SHIFT                  0
+#define FTFL_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB1_CCOBn_SHIFT))&FTFL_FCCOB1_CCOBn_MASK)
+/* FCCOB0 Bit Fields */
+#define FTFL_FCCOB0_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB0_CCOBn_SHIFT                  0
+#define FTFL_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB0_CCOBn_SHIFT))&FTFL_FCCOB0_CCOBn_MASK)
+/* FCCOB7 Bit Fields */
+#define FTFL_FCCOB7_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB7_CCOBn_SHIFT                  0
+#define FTFL_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB7_CCOBn_SHIFT))&FTFL_FCCOB7_CCOBn_MASK)
+/* FCCOB6 Bit Fields */
+#define FTFL_FCCOB6_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB6_CCOBn_SHIFT                  0
+#define FTFL_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB6_CCOBn_SHIFT))&FTFL_FCCOB6_CCOBn_MASK)
+/* FCCOB5 Bit Fields */
+#define FTFL_FCCOB5_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB5_CCOBn_SHIFT                  0
+#define FTFL_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB5_CCOBn_SHIFT))&FTFL_FCCOB5_CCOBn_MASK)
+/* FCCOB4 Bit Fields */
+#define FTFL_FCCOB4_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB4_CCOBn_SHIFT                  0
+#define FTFL_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB4_CCOBn_SHIFT))&FTFL_FCCOB4_CCOBn_MASK)
+/* FCCOBB Bit Fields */
+#define FTFL_FCCOBB_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOBB_CCOBn_SHIFT                  0
+#define FTFL_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBB_CCOBn_SHIFT))&FTFL_FCCOBB_CCOBn_MASK)
+/* FCCOBA Bit Fields */
+#define FTFL_FCCOBA_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOBA_CCOBn_SHIFT                  0
+#define FTFL_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOBA_CCOBn_SHIFT))&FTFL_FCCOBA_CCOBn_MASK)
+/* FCCOB9 Bit Fields */
+#define FTFL_FCCOB9_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB9_CCOBn_SHIFT                  0
+#define FTFL_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB9_CCOBn_SHIFT))&FTFL_FCCOB9_CCOBn_MASK)
+/* FCCOB8 Bit Fields */
+#define FTFL_FCCOB8_CCOBn_MASK                   0xFFu
+#define FTFL_FCCOB8_CCOBn_SHIFT                  0
+#define FTFL_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FCCOB8_CCOBn_SHIFT))&FTFL_FCCOB8_CCOBn_MASK)
+/* FPROT3 Bit Fields */
+#define FTFL_FPROT3_PROT_MASK                    0xFFu
+#define FTFL_FPROT3_PROT_SHIFT                   0
+#define FTFL_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT3_PROT_SHIFT))&FTFL_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define FTFL_FPROT2_PROT_MASK                    0xFFu
+#define FTFL_FPROT2_PROT_SHIFT                   0
+#define FTFL_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT2_PROT_SHIFT))&FTFL_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define FTFL_FPROT1_PROT_MASK                    0xFFu
+#define FTFL_FPROT1_PROT_SHIFT                   0
+#define FTFL_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT1_PROT_SHIFT))&FTFL_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define FTFL_FPROT0_PROT_MASK                    0xFFu
+#define FTFL_FPROT0_PROT_SHIFT                   0
+#define FTFL_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x))<<FTFL_FPROT0_PROT_SHIFT))&FTFL_FPROT0_PROT_MASK)
+/* FEPROT Bit Fields */
+#define FTFL_FEPROT_EPROT_MASK                   0xFFu
+#define FTFL_FEPROT_EPROT_SHIFT                  0
+#define FTFL_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FEPROT_EPROT_SHIFT))&FTFL_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define FTFL_FDPROT_DPROT_MASK                   0xFFu
+#define FTFL_FDPROT_DPROT_SHIFT                  0
+#define FTFL_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x))<<FTFL_FDPROT_DPROT_SHIFT))&FTFL_FDPROT_DPROT_MASK)
+
+/*! \} */ /* end of group FTFL_Register_Masks */
+
+
+/* FTFL - Peripheral instance base addresses */
+/*! Peripheral FTFL base address */
+#define FTFL_BASE                                (0x40020000u)
+/*! Peripheral FTFL base pointer */
+#define FTFL                                     ((FTFL_Type *)FTFL_BASE)
+
+/*! \} */ /* end of group FTFL_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer */
+/*! \{ */
+
+/*! NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /*!< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /*!< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /*!< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /*!< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /*!< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /*!< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /*!< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /*!< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /*!< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /*!< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /*!< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /*!< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /*!< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /*!< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /*!< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /*!< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup NV_Register_Masks NV Register Masks */
+/*! \{ */
+
+/* BACKKEY3 Bit Fields */
+#define NV_BACKKEY3_KEY_MASK                     0xFFu
+#define NV_BACKKEY3_KEY_SHIFT                    0
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
+/* BACKKEY2 Bit Fields */
+#define NV_BACKKEY2_KEY_MASK                     0xFFu
+#define NV_BACKKEY2_KEY_SHIFT                    0
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
+/* BACKKEY1 Bit Fields */
+#define NV_BACKKEY1_KEY_MASK                     0xFFu
+#define NV_BACKKEY1_KEY_SHIFT                    0
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
+/* BACKKEY0 Bit Fields */
+#define NV_BACKKEY0_KEY_MASK                     0xFFu
+#define NV_BACKKEY0_KEY_SHIFT                    0
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
+/* BACKKEY7 Bit Fields */
+#define NV_BACKKEY7_KEY_MASK                     0xFFu
+#define NV_BACKKEY7_KEY_SHIFT                    0
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
+/* BACKKEY6 Bit Fields */
+#define NV_BACKKEY6_KEY_MASK                     0xFFu
+#define NV_BACKKEY6_KEY_SHIFT                    0
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
+/* BACKKEY5 Bit Fields */
+#define NV_BACKKEY5_KEY_MASK                     0xFFu
+#define NV_BACKKEY5_KEY_SHIFT                    0
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
+/* BACKKEY4 Bit Fields */
+#define NV_BACKKEY4_KEY_MASK                     0xFFu
+#define NV_BACKKEY4_KEY_SHIFT                    0
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
+/* FPROT3 Bit Fields */
+#define NV_FPROT3_PROT_MASK                      0xFFu
+#define NV_FPROT3_PROT_SHIFT                     0
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
+/* FPROT2 Bit Fields */
+#define NV_FPROT2_PROT_MASK                      0xFFu
+#define NV_FPROT2_PROT_SHIFT                     0
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
+/* FPROT1 Bit Fields */
+#define NV_FPROT1_PROT_MASK                      0xFFu
+#define NV_FPROT1_PROT_SHIFT                     0
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
+/* FPROT0 Bit Fields */
+#define NV_FPROT0_PROT_MASK                      0xFFu
+#define NV_FPROT0_PROT_SHIFT                     0
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
+/* FSEC Bit Fields */
+#define NV_FSEC_SEC_MASK                         0x3u
+#define NV_FSEC_SEC_SHIFT                        0
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      0xCu
+#define NV_FSEC_FSLACC_SHIFT                     2
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        0x30u
+#define NV_FSEC_MEEN_SHIFT                       4
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       0xC0u
+#define NV_FSEC_KEYEN_SHIFT                      6
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
+/* FOPT Bit Fields */
+#define NV_FOPT_LPBOOT_MASK                      0x1u
+#define NV_FOPT_LPBOOT_SHIFT                     0
+#define NV_FOPT_EZPORT_DIS_MASK                  0x2u
+#define NV_FOPT_EZPORT_DIS_SHIFT                 1
+/* FEPROT Bit Fields */
+#define NV_FEPROT_EPROT_MASK                     0xFFu
+#define NV_FEPROT_EPROT_SHIFT                    0
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
+/* FDPROT Bit Fields */
+#define NV_FDPROT_DPROT_MASK                     0xFFu
+#define NV_FDPROT_DPROT_SHIFT                    0
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
+
+/*! \} */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/*! Peripheral FTFL_FlashConfig base address */
+#define FTFL_FlashConfig_BASE                    (0x400u)
+/*! Peripheral FTFL_FlashConfig base pointer */
+#define FTFL_FlashConfig                         ((NV_Type *)FTFL_FlashConfig_BASE)
+
+/*! \} */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer */
+/*! \{ */
+
+/*! FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /*!< Status and Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /*!< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /*!< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /*!< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /*!< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /*!< Counter Initial Value, offset: 0x4C */
+  __I  uint32_t STATUS;                            /*!< Capture and Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /*!< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /*!< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /*!< Initial State for Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /*!< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /*!< Function for Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /*!< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /*!< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /*!< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /*!< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /*!< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /*!< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /*!< Quadrature Decoder Control and Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /*!< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /*!< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /*!< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /*!< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /*!< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /*!< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup FTM_Register_Masks FTM Register Masks */
+/*! \{ */
+
+/* SC Bit Fields */
+#define FTM_SC_PS_MASK                           0x7u
+#define FTM_SC_PS_SHIFT                          0
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         0x18u
+#define FTM_SC_CLKS_SHIFT                        3
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        0x20u
+#define FTM_SC_CPWMS_SHIFT                       5
+#define FTM_SC_TOIE_MASK                         0x40u
+#define FTM_SC_TOIE_SHIFT                        6
+#define FTM_SC_TOF_MASK                          0x80u
+#define FTM_SC_TOF_SHIFT                         7
+/* CNT Bit Fields */
+#define FTM_CNT_COUNT_MASK                       0xFFFFu
+#define FTM_CNT_COUNT_SHIFT                      0
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
+/* MOD Bit Fields */
+#define FTM_MOD_MOD_MASK                         0xFFFFu
+#define FTM_MOD_MOD_SHIFT                        0
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
+/* CnSC Bit Fields */
+#define FTM_CnSC_DMA_MASK                        0x1u
+#define FTM_CnSC_DMA_SHIFT                       0
+#define FTM_CnSC_ELSA_MASK                       0x4u
+#define FTM_CnSC_ELSA_SHIFT                      2
+#define FTM_CnSC_ELSB_MASK                       0x8u
+#define FTM_CnSC_ELSB_SHIFT                      3
+#define FTM_CnSC_MSA_MASK                        0x10u
+#define FTM_CnSC_MSA_SHIFT                       4
+#define FTM_CnSC_MSB_MASK                        0x20u
+#define FTM_CnSC_MSB_SHIFT                       5
+#define FTM_CnSC_CHIE_MASK                       0x40u
+#define FTM_CnSC_CHIE_SHIFT                      6
+#define FTM_CnSC_CHF_MASK                        0x80u
+#define FTM_CnSC_CHF_SHIFT                       7
+/* CnV Bit Fields */
+#define FTM_CnV_VAL_MASK                         0xFFFFu
+#define FTM_CnV_VAL_SHIFT                        0
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
+/* CNTIN Bit Fields */
+#define FTM_CNTIN_INIT_MASK                      0xFFFFu
+#define FTM_CNTIN_INIT_SHIFT                     0
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
+/* STATUS Bit Fields */
+#define FTM_STATUS_CH0F_MASK                     0x1u
+#define FTM_STATUS_CH0F_SHIFT                    0
+#define FTM_STATUS_CH1F_MASK                     0x2u
+#define FTM_STATUS_CH1F_SHIFT                    1
+#define FTM_STATUS_CH2F_MASK                     0x4u
+#define FTM_STATUS_CH2F_SHIFT                    2
+#define FTM_STATUS_CH3F_MASK                     0x8u
+#define FTM_STATUS_CH3F_SHIFT                    3
+#define FTM_STATUS_CH4F_MASK                     0x10u
+#define FTM_STATUS_CH4F_SHIFT                    4
+#define FTM_STATUS_CH5F_MASK                     0x20u
+#define FTM_STATUS_CH5F_SHIFT                    5
+#define FTM_STATUS_CH6F_MASK                     0x40u
+#define FTM_STATUS_CH6F_SHIFT                    6
+#define FTM_STATUS_CH7F_MASK                     0x80u
+#define FTM_STATUS_CH7F_SHIFT                    7
+/* MODE Bit Fields */
+#define FTM_MODE_FTMEN_MASK                      0x1u
+#define FTM_MODE_FTMEN_SHIFT                     0
+#define FTM_MODE_INIT_MASK                       0x2u
+#define FTM_MODE_INIT_SHIFT                      1
+#define FTM_MODE_WPDIS_MASK                      0x4u
+#define FTM_MODE_WPDIS_SHIFT                     2
+#define FTM_MODE_PWMSYNC_MASK                    0x8u
+#define FTM_MODE_PWMSYNC_SHIFT                   3
+#define FTM_MODE_CAPTEST_MASK                    0x10u
+#define FTM_MODE_CAPTEST_SHIFT                   4
+#define FTM_MODE_FAULTM_MASK                     0x60u
+#define FTM_MODE_FAULTM_SHIFT                    5
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    0x80u
+#define FTM_MODE_FAULTIE_SHIFT                   7
+/* SYNC Bit Fields */
+#define FTM_SYNC_CNTMIN_MASK                     0x1u
+#define FTM_SYNC_CNTMIN_SHIFT                    0
+#define FTM_SYNC_CNTMAX_MASK                     0x2u
+#define FTM_SYNC_CNTMAX_SHIFT                    1
+#define FTM_SYNC_REINIT_MASK                     0x4u
+#define FTM_SYNC_REINIT_SHIFT                    2
+#define FTM_SYNC_SYNCHOM_MASK                    0x8u
+#define FTM_SYNC_SYNCHOM_SHIFT                   3
+#define FTM_SYNC_TRIG0_MASK                      0x10u
+#define FTM_SYNC_TRIG0_SHIFT                     4
+#define FTM_SYNC_TRIG1_MASK                      0x20u
+#define FTM_SYNC_TRIG1_SHIFT                     5
+#define FTM_SYNC_TRIG2_MASK                      0x40u
+#define FTM_SYNC_TRIG2_SHIFT                     6
+#define FTM_SYNC_SWSYNC_MASK                     0x80u
+#define FTM_SYNC_SWSYNC_SHIFT                    7
+/* OUTINIT Bit Fields */
+#define FTM_OUTINIT_CH0OI_MASK                   0x1u
+#define FTM_OUTINIT_CH0OI_SHIFT                  0
+#define FTM_OUTINIT_CH1OI_MASK                   0x2u
+#define FTM_OUTINIT_CH1OI_SHIFT                  1
+#define FTM_OUTINIT_CH2OI_MASK                   0x4u
+#define FTM_OUTINIT_CH2OI_SHIFT                  2
+#define FTM_OUTINIT_CH3OI_MASK                   0x8u
+#define FTM_OUTINIT_CH3OI_SHIFT                  3
+#define FTM_OUTINIT_CH4OI_MASK                   0x10u
+#define FTM_OUTINIT_CH4OI_SHIFT                  4
+#define FTM_OUTINIT_CH5OI_MASK                   0x20u
+#define FTM_OUTINIT_CH5OI_SHIFT                  5
+#define FTM_OUTINIT_CH6OI_MASK                   0x40u
+#define FTM_OUTINIT_CH6OI_SHIFT                  6
+#define FTM_OUTINIT_CH7OI_MASK                   0x80u
+#define FTM_OUTINIT_CH7OI_SHIFT                  7
+/* OUTMASK Bit Fields */
+#define FTM_OUTMASK_CH0OM_MASK                   0x1u
+#define FTM_OUTMASK_CH0OM_SHIFT                  0
+#define FTM_OUTMASK_CH1OM_MASK                   0x2u
+#define FTM_OUTMASK_CH1OM_SHIFT                  1
+#define FTM_OUTMASK_CH2OM_MASK                   0x4u
+#define FTM_OUTMASK_CH2OM_SHIFT                  2
+#define FTM_OUTMASK_CH3OM_MASK                   0x8u
+#define FTM_OUTMASK_CH3OM_SHIFT                  3
+#define FTM_OUTMASK_CH4OM_MASK                   0x10u
+#define FTM_OUTMASK_CH4OM_SHIFT                  4
+#define FTM_OUTMASK_CH5OM_MASK                   0x20u
+#define FTM_OUTMASK_CH5OM_SHIFT                  5
+#define FTM_OUTMASK_CH6OM_MASK                   0x40u
+#define FTM_OUTMASK_CH6OM_SHIFT                  6
+#define FTM_OUTMASK_CH7OM_MASK                   0x80u
+#define FTM_OUTMASK_CH7OM_SHIFT                  7
+/* COMBINE Bit Fields */
+#define FTM_COMBINE_COMBINE0_MASK                0x1u
+#define FTM_COMBINE_COMBINE0_SHIFT               0
+#define FTM_COMBINE_COMP0_MASK                   0x2u
+#define FTM_COMBINE_COMP0_SHIFT                  1
+#define FTM_COMBINE_DECAPEN0_MASK                0x4u
+#define FTM_COMBINE_DECAPEN0_SHIFT               2
+#define FTM_COMBINE_DECAP0_MASK                  0x8u
+#define FTM_COMBINE_DECAP0_SHIFT                 3
+#define FTM_COMBINE_DTEN0_MASK                   0x10u
+#define FTM_COMBINE_DTEN0_SHIFT                  4
+#define FTM_COMBINE_SYNCEN0_MASK                 0x20u
+#define FTM_COMBINE_SYNCEN0_SHIFT                5
+#define FTM_COMBINE_FAULTEN0_MASK                0x40u
+#define FTM_COMBINE_FAULTEN0_SHIFT               6
+#define FTM_COMBINE_COMBINE1_MASK                0x100u
+#define FTM_COMBINE_COMBINE1_SHIFT               8
+#define FTM_COMBINE_COMP1_MASK                   0x200u
+#define FTM_COMBINE_COMP1_SHIFT                  9
+#define FTM_COMBINE_DECAPEN1_MASK                0x400u
+#define FTM_COMBINE_DECAPEN1_SHIFT               10
+#define FTM_COMBINE_DECAP1_MASK                  0x800u
+#define FTM_COMBINE_DECAP1_SHIFT                 11
+#define FTM_COMBINE_DTEN1_MASK                   0x1000u
+#define FTM_COMBINE_DTEN1_SHIFT                  12
+#define FTM_COMBINE_SYNCEN1_MASK                 0x2000u
+#define FTM_COMBINE_SYNCEN1_SHIFT                13
+#define FTM_COMBINE_FAULTEN1_MASK                0x4000u
+#define FTM_COMBINE_FAULTEN1_SHIFT               14
+#define FTM_COMBINE_COMBINE2_MASK                0x10000u
+#define FTM_COMBINE_COMBINE2_SHIFT               16
+#define FTM_COMBINE_COMP2_MASK                   0x20000u
+#define FTM_COMBINE_COMP2_SHIFT                  17
+#define FTM_COMBINE_DECAPEN2_MASK                0x40000u
+#define FTM_COMBINE_DECAPEN2_SHIFT               18
+#define FTM_COMBINE_DECAP2_MASK                  0x80000u
+#define FTM_COMBINE_DECAP2_SHIFT                 19
+#define FTM_COMBINE_DTEN2_MASK                   0x100000u
+#define FTM_COMBINE_DTEN2_SHIFT                  20
+#define FTM_COMBINE_SYNCEN2_MASK                 0x200000u
+#define FTM_COMBINE_SYNCEN2_SHIFT                21
+#define FTM_COMBINE_FAULTEN2_MASK                0x400000u
+#define FTM_COMBINE_FAULTEN2_SHIFT               22
+#define FTM_COMBINE_COMBINE3_MASK                0x1000000u
+#define FTM_COMBINE_COMBINE3_SHIFT               24
+#define FTM_COMBINE_COMP3_MASK                   0x2000000u
+#define FTM_COMBINE_COMP3_SHIFT                  25
+#define FTM_COMBINE_DECAPEN3_MASK                0x4000000u
+#define FTM_COMBINE_DECAPEN3_SHIFT               26
+#define FTM_COMBINE_DECAP3_MASK                  0x8000000u
+#define FTM_COMBINE_DECAP3_SHIFT                 27
+#define FTM_COMBINE_DTEN3_MASK                   0x10000000u
+#define FTM_COMBINE_DTEN3_SHIFT                  28
+#define FTM_COMBINE_SYNCEN3_MASK                 0x20000000u
+#define FTM_COMBINE_SYNCEN3_SHIFT                29
+#define FTM_COMBINE_FAULTEN3_MASK                0x40000000u
+#define FTM_COMBINE_FAULTEN3_SHIFT               30
+/* DEADTIME Bit Fields */
+#define FTM_DEADTIME_DTVAL_MASK                  0x3Fu
+#define FTM_DEADTIME_DTVAL_SHIFT                 0
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   0xC0u
+#define FTM_DEADTIME_DTPS_SHIFT                  6
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
+/* EXTTRIG Bit Fields */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 0x1u
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                0
+#define FTM_EXTTRIG_CH3TRIG_MASK                 0x2u
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                1
+#define FTM_EXTTRIG_CH4TRIG_MASK                 0x4u
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                2
+#define FTM_EXTTRIG_CH5TRIG_MASK                 0x8u
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                3
+#define FTM_EXTTRIG_CH0TRIG_MASK                 0x10u
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                4
+#define FTM_EXTTRIG_CH1TRIG_MASK                 0x20u
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                5
+#define FTM_EXTTRIG_INITTRIGEN_MASK              0x40u
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             6
+#define FTM_EXTTRIG_TRIGF_MASK                   0x80u
+#define FTM_EXTTRIG_TRIGF_SHIFT                  7
+/* POL Bit Fields */
+#define FTM_POL_POL0_MASK                        0x1u
+#define FTM_POL_POL0_SHIFT                       0
+#define FTM_POL_POL1_MASK                        0x2u
+#define FTM_POL_POL1_SHIFT                       1
+#define FTM_POL_POL2_MASK                        0x4u
+#define FTM_POL_POL2_SHIFT                       2
+#define FTM_POL_POL3_MASK                        0x8u
+#define FTM_POL_POL3_SHIFT                       3
+#define FTM_POL_POL4_MASK                        0x10u
+#define FTM_POL_POL4_SHIFT                       4
+#define FTM_POL_POL5_MASK                        0x20u
+#define FTM_POL_POL5_SHIFT                       5
+#define FTM_POL_POL6_MASK                        0x40u
+#define FTM_POL_POL6_SHIFT                       6
+#define FTM_POL_POL7_MASK                        0x80u
+#define FTM_POL_POL7_SHIFT                       7
+/* FMS Bit Fields */
+#define FTM_FMS_FAULTF0_MASK                     0x1u
+#define FTM_FMS_FAULTF0_SHIFT                    0
+#define FTM_FMS_FAULTF1_MASK                     0x2u
+#define FTM_FMS_FAULTF1_SHIFT                    1
+#define FTM_FMS_FAULTF2_MASK                     0x4u
+#define FTM_FMS_FAULTF2_SHIFT                    2
+#define FTM_FMS_FAULTF3_MASK                     0x8u
+#define FTM_FMS_FAULTF3_SHIFT                    3
+#define FTM_FMS_FAULTIN_MASK                     0x20u
+#define FTM_FMS_FAULTIN_SHIFT                    5
+#define FTM_FMS_WPEN_MASK                        0x40u
+#define FTM_FMS_WPEN_SHIFT                       6
+#define FTM_FMS_FAULTF_MASK                      0x80u
+#define FTM_FMS_FAULTF_SHIFT                     7
+/* FILTER Bit Fields */
+#define FTM_FILTER_CH0FVAL_MASK                  0xFu
+#define FTM_FILTER_CH0FVAL_SHIFT                 0
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  0xF0u
+#define FTM_FILTER_CH1FVAL_SHIFT                 4
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  0xF00u
+#define FTM_FILTER_CH2FVAL_SHIFT                 8
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  0xF000u
+#define FTM_FILTER_CH3FVAL_SHIFT                 12
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
+/* FLTCTRL Bit Fields */
+#define FTM_FLTCTRL_FAULT0EN_MASK                0x1u
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               0
+#define FTM_FLTCTRL_FAULT1EN_MASK                0x2u
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               1
+#define FTM_FLTCTRL_FAULT2EN_MASK                0x4u
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               2
+#define FTM_FLTCTRL_FAULT3EN_MASK                0x8u
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               3
+#define FTM_FLTCTRL_FFLTR0EN_MASK                0x10u
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               4
+#define FTM_FLTCTRL_FFLTR1EN_MASK                0x20u
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               5
+#define FTM_FLTCTRL_FFLTR2EN_MASK                0x40u
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               6
+#define FTM_FLTCTRL_FFLTR3EN_MASK                0x80u
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               7
+#define FTM_FLTCTRL_FFVAL_MASK                   0xF00u
+#define FTM_FLTCTRL_FFVAL_SHIFT                  8
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
+/* QDCTRL Bit Fields */
+#define FTM_QDCTRL_QUADEN_MASK                   0x1u
+#define FTM_QDCTRL_QUADEN_SHIFT                  0
+#define FTM_QDCTRL_TOFDIR_MASK                   0x2u
+#define FTM_QDCTRL_TOFDIR_SHIFT                  1
+#define FTM_QDCTRL_QUADIR_MASK                   0x4u
+#define FTM_QDCTRL_QUADIR_SHIFT                  2
+#define FTM_QDCTRL_QUADMODE_MASK                 0x8u
+#define FTM_QDCTRL_QUADMODE_SHIFT                3
+#define FTM_QDCTRL_PHBPOL_MASK                   0x10u
+#define FTM_QDCTRL_PHBPOL_SHIFT                  4
+#define FTM_QDCTRL_PHAPOL_MASK                   0x20u
+#define FTM_QDCTRL_PHAPOL_SHIFT                  5
+#define FTM_QDCTRL_PHBFLTREN_MASK                0x40u
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               6
+#define FTM_QDCTRL_PHAFLTREN_MASK                0x80u
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               7
+/* CONF Bit Fields */
+#define FTM_CONF_NUMTOF_MASK                     0x1Fu
+#define FTM_CONF_NUMTOF_SHIFT                    0
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    0xC0u
+#define FTM_CONF_BDMMODE_SHIFT                   6
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     0x200u
+#define FTM_CONF_GTBEEN_SHIFT                    9
+#define FTM_CONF_GTBEOUT_MASK                    0x400u
+#define FTM_CONF_GTBEOUT_SHIFT                   10
+/* FLTPOL Bit Fields */
+#define FTM_FLTPOL_FLT0POL_MASK                  0x1u
+#define FTM_FLTPOL_FLT0POL_SHIFT                 0
+#define FTM_FLTPOL_FLT1POL_MASK                  0x2u
+#define FTM_FLTPOL_FLT1POL_SHIFT                 1
+#define FTM_FLTPOL_FLT2POL_MASK                  0x4u
+#define FTM_FLTPOL_FLT2POL_SHIFT                 2
+#define FTM_FLTPOL_FLT3POL_MASK                  0x8u
+#define FTM_FLTPOL_FLT3POL_SHIFT                 3
+/* SYNCONF Bit Fields */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              0x1u
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             0
+#define FTM_SYNCONF_CNTINC_MASK                  0x4u
+#define FTM_SYNCONF_CNTINC_SHIFT                 2
+#define FTM_SYNCONF_INVC_MASK                    0x10u
+#define FTM_SYNCONF_INVC_SHIFT                   4
+#define FTM_SYNCONF_SWOC_MASK                    0x20u
+#define FTM_SYNCONF_SWOC_SHIFT                   5
+#define FTM_SYNCONF_SYNCMODE_MASK                0x80u
+#define FTM_SYNCONF_SYNCMODE_SHIFT               7
+#define FTM_SYNCONF_SWRSTCNT_MASK                0x100u
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               8
+#define FTM_SYNCONF_SWWRBUF_MASK                 0x200u
+#define FTM_SYNCONF_SWWRBUF_SHIFT                9
+#define FTM_SYNCONF_SWOM_MASK                    0x400u
+#define FTM_SYNCONF_SWOM_SHIFT                   10
+#define FTM_SYNCONF_SWINVC_MASK                  0x800u
+#define FTM_SYNCONF_SWINVC_SHIFT                 11
+#define FTM_SYNCONF_SWSOC_MASK                   0x1000u
+#define FTM_SYNCONF_SWSOC_SHIFT                  12
+#define FTM_SYNCONF_HWRSTCNT_MASK                0x10000u
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               16
+#define FTM_SYNCONF_HWWRBUF_MASK                 0x20000u
+#define FTM_SYNCONF_HWWRBUF_SHIFT                17
+#define FTM_SYNCONF_HWOM_MASK                    0x40000u
+#define FTM_SYNCONF_HWOM_SHIFT                   18
+#define FTM_SYNCONF_HWINVC_MASK                  0x80000u
+#define FTM_SYNCONF_HWINVC_SHIFT                 19
+#define FTM_SYNCONF_HWSOC_MASK                   0x100000u
+#define FTM_SYNCONF_HWSOC_SHIFT                  20
+/* INVCTRL Bit Fields */
+#define FTM_INVCTRL_INV0EN_MASK                  0x1u
+#define FTM_INVCTRL_INV0EN_SHIFT                 0
+#define FTM_INVCTRL_INV1EN_MASK                  0x2u
+#define FTM_INVCTRL_INV1EN_SHIFT                 1
+#define FTM_INVCTRL_INV2EN_MASK                  0x4u
+#define FTM_INVCTRL_INV2EN_SHIFT                 2
+#define FTM_INVCTRL_INV3EN_MASK                  0x8u
+#define FTM_INVCTRL_INV3EN_SHIFT                 3
+/* SWOCTRL Bit Fields */
+#define FTM_SWOCTRL_CH0OC_MASK                   0x1u
+#define FTM_SWOCTRL_CH0OC_SHIFT                  0
+#define FTM_SWOCTRL_CH1OC_MASK                   0x2u
+#define FTM_SWOCTRL_CH1OC_SHIFT                  1
+#define FTM_SWOCTRL_CH2OC_MASK                   0x4u
+#define FTM_SWOCTRL_CH2OC_SHIFT                  2
+#define FTM_SWOCTRL_CH3OC_MASK                   0x8u
+#define FTM_SWOCTRL_CH3OC_SHIFT                  3
+#define FTM_SWOCTRL_CH4OC_MASK                   0x10u
+#define FTM_SWOCTRL_CH4OC_SHIFT                  4
+#define FTM_SWOCTRL_CH5OC_MASK                   0x20u
+#define FTM_SWOCTRL_CH5OC_SHIFT                  5
+#define FTM_SWOCTRL_CH6OC_MASK                   0x40u
+#define FTM_SWOCTRL_CH6OC_SHIFT                  6
+#define FTM_SWOCTRL_CH7OC_MASK                   0x80u
+#define FTM_SWOCTRL_CH7OC_SHIFT                  7
+#define FTM_SWOCTRL_CH0OCV_MASK                  0x100u
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 8
+#define FTM_SWOCTRL_CH1OCV_MASK                  0x200u
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 9
+#define FTM_SWOCTRL_CH2OCV_MASK                  0x400u
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 10
+#define FTM_SWOCTRL_CH3OCV_MASK                  0x800u
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 11
+#define FTM_SWOCTRL_CH4OCV_MASK                  0x1000u
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 12
+#define FTM_SWOCTRL_CH5OCV_MASK                  0x2000u
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 13
+#define FTM_SWOCTRL_CH6OCV_MASK                  0x4000u
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 14
+#define FTM_SWOCTRL_CH7OCV_MASK                  0x8000u
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 15
+/* PWMLOAD Bit Fields */
+#define FTM_PWMLOAD_CH0SEL_MASK                  0x1u
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 0
+#define FTM_PWMLOAD_CH1SEL_MASK                  0x2u
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 1
+#define FTM_PWMLOAD_CH2SEL_MASK                  0x4u
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 2
+#define FTM_PWMLOAD_CH3SEL_MASK                  0x8u
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 3
+#define FTM_PWMLOAD_CH4SEL_MASK                  0x10u
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 4
+#define FTM_PWMLOAD_CH5SEL_MASK                  0x20u
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 5
+#define FTM_PWMLOAD_CH6SEL_MASK                  0x40u
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 6
+#define FTM_PWMLOAD_CH7SEL_MASK                  0x80u
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 7
+#define FTM_PWMLOAD_LDOK_MASK                    0x200u
+#define FTM_PWMLOAD_LDOK_SHIFT                   9
+
+/*! \} */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/*! Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/*! Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+/*! Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/*! Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+/*! Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x400B8000u)
+/*! Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+
+/*! \} */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer */
+/*! \{ */
+
+/*! I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /*!< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /*!< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /*!< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /*!< I2C Status Register, offset: 0x3 */
+  __IO uint8_t D;                                  /*!< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /*!< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /*!< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /*!< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /*!< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /*!< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /*!< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /*!< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup I2C_Register_Masks I2C Register Masks */
+/*! \{ */
+
+/* A1 Bit Fields */
+#define I2C_A1_AD_MASK                           0xFEu
+#define I2C_A1_AD_SHIFT                          1
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
+/* F Bit Fields */
+#define I2C_F_ICR_MASK                           0x3Fu
+#define I2C_F_ICR_SHIFT                          0
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          0xC0u
+#define I2C_F_MULT_SHIFT                         6
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
+/* C1 Bit Fields */
+#define I2C_C1_DMAEN_MASK                        0x1u
+#define I2C_C1_DMAEN_SHIFT                       0
+#define I2C_C1_WUEN_MASK                         0x2u
+#define I2C_C1_WUEN_SHIFT                        1
+#define I2C_C1_RSTA_MASK                         0x4u
+#define I2C_C1_RSTA_SHIFT                        2
+#define I2C_C1_TXAK_MASK                         0x8u
+#define I2C_C1_TXAK_SHIFT                        3
+#define I2C_C1_TX_MASK                           0x10u
+#define I2C_C1_TX_SHIFT                          4
+#define I2C_C1_MST_MASK                          0x20u
+#define I2C_C1_MST_SHIFT                         5
+#define I2C_C1_IICIE_MASK                        0x40u
+#define I2C_C1_IICIE_SHIFT                       6
+#define I2C_C1_IICEN_MASK                        0x80u
+#define I2C_C1_IICEN_SHIFT                       7
+/* S Bit Fields */
+#define I2C_S_RXAK_MASK                          0x1u
+#define I2C_S_RXAK_SHIFT                         0
+#define I2C_S_IICIF_MASK                         0x2u
+#define I2C_S_IICIF_SHIFT                        1
+#define I2C_S_SRW_MASK                           0x4u
+#define I2C_S_SRW_SHIFT                          2
+#define I2C_S_RAM_MASK                           0x8u
+#define I2C_S_RAM_SHIFT                          3
+#define I2C_S_ARBL_MASK                          0x10u
+#define I2C_S_ARBL_SHIFT                         4
+#define I2C_S_BUSY_MASK                          0x20u
+#define I2C_S_BUSY_SHIFT                         5
+#define I2C_S_IAAS_MASK                          0x40u
+#define I2C_S_IAAS_SHIFT                         6
+#define I2C_S_TCF_MASK                           0x80u
+#define I2C_S_TCF_SHIFT                          7
+/* D Bit Fields */
+#define I2C_D_DATA_MASK                          0xFFu
+#define I2C_D_DATA_SHIFT                         0
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
+/* C2 Bit Fields */
+#define I2C_C2_AD_MASK                           0x7u
+#define I2C_C2_AD_SHIFT                          0
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         0x8u
+#define I2C_C2_RMEN_SHIFT                        3
+#define I2C_C2_SBRC_MASK                         0x10u
+#define I2C_C2_SBRC_SHIFT                        4
+#define I2C_C2_HDRS_MASK                         0x20u
+#define I2C_C2_HDRS_SHIFT                        5
+#define I2C_C2_ADEXT_MASK                        0x40u
+#define I2C_C2_ADEXT_SHIFT                       6
+#define I2C_C2_GCAEN_MASK                        0x80u
+#define I2C_C2_GCAEN_SHIFT                       7
+/* FLT Bit Fields */
+#define I2C_FLT_FLT_MASK                         0x1Fu
+#define I2C_FLT_FLT_SHIFT                        0
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
+/* RA Bit Fields */
+#define I2C_RA_RAD_MASK                          0xFEu
+#define I2C_RA_RAD_SHIFT                         1
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
+/* SMB Bit Fields */
+#define I2C_SMB_SHTF2IE_MASK                     0x1u
+#define I2C_SMB_SHTF2IE_SHIFT                    0
+#define I2C_SMB_SHTF2_MASK                       0x2u
+#define I2C_SMB_SHTF2_SHIFT                      1
+#define I2C_SMB_SHTF1_MASK                       0x4u
+#define I2C_SMB_SHTF1_SHIFT                      2
+#define I2C_SMB_SLTF_MASK                        0x8u
+#define I2C_SMB_SLTF_SHIFT                       3
+#define I2C_SMB_TCKSEL_MASK                      0x10u
+#define I2C_SMB_TCKSEL_SHIFT                     4
+#define I2C_SMB_SIICAEN_MASK                     0x20u
+#define I2C_SMB_SIICAEN_SHIFT                    5
+#define I2C_SMB_ALERTEN_MASK                     0x40u
+#define I2C_SMB_ALERTEN_SHIFT                    6
+#define I2C_SMB_FACK_MASK                        0x80u
+#define I2C_SMB_FACK_SHIFT                       7
+/* A2 Bit Fields */
+#define I2C_A2_SAD_MASK                          0xFEu
+#define I2C_A2_SAD_SHIFT                         1
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
+/* SLTH Bit Fields */
+#define I2C_SLTH_SSLT_MASK                       0xFFu
+#define I2C_SLTH_SSLT_SHIFT                      0
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
+/* SLTL Bit Fields */
+#define I2C_SLTL_SSLT_MASK                       0xFFu
+#define I2C_SLTL_SSLT_SHIFT                      0
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
+
+/*! \} */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/*! Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/*! Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/*! Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/*! Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+
+/*! \} */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer */
+/*! \{ */
+
+/*! I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TX0;                               /*!< I2S Transmit Data Registers 0, offset: 0x0 */
+  __IO uint32_t TX1;                               /*!< I2S Transmit Data Registers 1, offset: 0x4 */
+  __IO uint32_t RX0;                               /*!< I2S Receive Data Registers 0, offset: 0x8 */
+  __IO uint32_t RX1;                               /*!< I2S Receive Data Registers 1, offset: 0xC */
+  __IO uint32_t CR;                                /*!< I2S Control Register, offset: 0x10 */
+  __IO uint32_t ISR;                               /*!< I2S Interrupt Status Register, offset: 0x14 */
+  __IO uint32_t IER;                               /*!< I2S Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t TCR;                               /*!< I2S Transmit Configuration Register, offset: 0x1C */
+  __IO uint32_t RCR;                               /*!< I2S Receive Configuration Register, offset: 0x20 */
+  __IO uint32_t TCCR;                              /*!< I2S Transmit Clock Control Registers, offset: 0x24 */
+  __IO uint32_t RCCR;                              /*!< I2S Receive Clock Control Registers, offset: 0x28 */
+  __IO uint32_t FCSR;                              /*!< I2S FIFO Control/Status Register, offset: 0x2C */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t ACNT;                              /*!< I2S AC97 Control Register, offset: 0x38 */
+  __IO uint32_t ACADD;                             /*!< I2S AC97 Command Address Register, offset: 0x3C */
+  __IO uint32_t ACDAT;                             /*!< I2S AC97 Command Data Register, offset: 0x40 */
+  __IO uint32_t ATAG;                              /*!< I2S AC97 Tag Register, offset: 0x44 */
+  __IO uint32_t TMSK;                              /*!< I2S Transmit Time Slot Mask Register, offset: 0x48 */
+  __IO uint32_t RMSK;                              /*!< I2S Receive Time Slot Mask Register, offset: 0x4C */
+  __I  uint32_t ACCST;                             /*!< I2S AC97 Channel Status Register, offset: 0x50 */
+  __IO uint32_t ACCEN;                             /*!< I2S AC97 Channel Enable Register, offset: 0x54 */
+  __IO uint32_t ACCDIS;                            /*!< I2S AC97 Channel Disable Register, offset: 0x58 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup I2S_Register_Masks I2S Register Masks */
+/*! \{ */
+
+/* TX0 Bit Fields */
+#define I2S_TX0_TX0_MASK                         0xFFFFFFFFu
+#define I2S_TX0_TX0_SHIFT                        0
+#define I2S_TX0_TX0(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TX0_TX0_SHIFT))&I2S_TX0_TX0_MASK)
+/* TX1 Bit Fields */
+#define I2S_TX1_TX1_MASK                         0xFFFFFFFFu
+#define I2S_TX1_TX1_SHIFT                        0
+#define I2S_TX1_TX1(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TX1_TX1_SHIFT))&I2S_TX1_TX1_MASK)
+/* RX0 Bit Fields */
+#define I2S_RX0_RX0_MASK                         0xFFFFFFFFu
+#define I2S_RX0_RX0_SHIFT                        0
+#define I2S_RX0_RX0(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RX0_RX0_SHIFT))&I2S_RX0_RX0_MASK)
+/* RX1 Bit Fields */
+#define I2S_RX1_RX1_MASK                         0xFFFFFFFFu
+#define I2S_RX1_RX1_SHIFT                        0
+#define I2S_RX1_RX1(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RX1_RX1_SHIFT))&I2S_RX1_RX1_MASK)
+/* CR Bit Fields */
+#define I2S_CR_SSIEN_MASK                        0x1u
+#define I2S_CR_SSIEN_SHIFT                       0
+#define I2S_CR_TE_MASK                           0x2u
+#define I2S_CR_TE_SHIFT                          1
+#define I2S_CR_RE_MASK                           0x4u
+#define I2S_CR_RE_SHIFT                          2
+#define I2S_CR_NET_MASK                          0x8u
+#define I2S_CR_NET_SHIFT                         3
+#define I2S_CR_SYN_MASK                          0x10u
+#define I2S_CR_SYN_SHIFT                         4
+#define I2S_CR_I2SMODE_MASK                      0x60u
+#define I2S_CR_I2SMODE_SHIFT                     5
+#define I2S_CR_I2SMODE(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_CR_I2SMODE_SHIFT))&I2S_CR_I2SMODE_MASK)
+#define I2S_CR_SYSCLKEN_MASK                     0x80u
+#define I2S_CR_SYSCLKEN_SHIFT                    7
+#define I2S_CR_TCHEN_MASK                        0x100u
+#define I2S_CR_TCHEN_SHIFT                       8
+#define I2S_CR_CLKIST_MASK                       0x200u
+#define I2S_CR_CLKIST_SHIFT                      9
+#define I2S_CR_TFRCLKDIS_MASK                    0x400u
+#define I2S_CR_TFRCLKDIS_SHIFT                   10
+#define I2S_CR_RFRCLKDIS_MASK                    0x800u
+#define I2S_CR_RFRCLKDIS_SHIFT                   11
+#define I2S_CR_SYNCTXFS_MASK                     0x1000u
+#define I2S_CR_SYNCTXFS_SHIFT                    12
+/* ISR Bit Fields */
+#define I2S_ISR_TFE0_MASK                        0x1u
+#define I2S_ISR_TFE0_SHIFT                       0
+#define I2S_ISR_TFE1_MASK                        0x2u
+#define I2S_ISR_TFE1_SHIFT                       1
+#define I2S_ISR_RFF0_MASK                        0x4u
+#define I2S_ISR_RFF0_SHIFT                       2
+#define I2S_ISR_RFF1_MASK                        0x8u
+#define I2S_ISR_RFF1_SHIFT                       3
+#define I2S_ISR_RLS_MASK                         0x10u
+#define I2S_ISR_RLS_SHIFT                        4
+#define I2S_ISR_TLS_MASK                         0x20u
+#define I2S_ISR_TLS_SHIFT                        5
+#define I2S_ISR_RFS_MASK                         0x40u
+#define I2S_ISR_RFS_SHIFT                        6
+#define I2S_ISR_TFS_MASK                         0x80u
+#define I2S_ISR_TFS_SHIFT                        7
+#define I2S_ISR_TUE0_MASK                        0x100u
+#define I2S_ISR_TUE0_SHIFT                       8
+#define I2S_ISR_TUE1_MASK                        0x200u
+#define I2S_ISR_TUE1_SHIFT                       9
+#define I2S_ISR_ROE0_MASK                        0x400u
+#define I2S_ISR_ROE0_SHIFT                       10
+#define I2S_ISR_ROE1_MASK                        0x800u
+#define I2S_ISR_ROE1_SHIFT                       11
+#define I2S_ISR_TDE0_MASK                        0x1000u
+#define I2S_ISR_TDE0_SHIFT                       12
+#define I2S_ISR_TDE1_MASK                        0x2000u
+#define I2S_ISR_TDE1_SHIFT                       13
+#define I2S_ISR_RDR0_MASK                        0x4000u
+#define I2S_ISR_RDR0_SHIFT                       14
+#define I2S_ISR_RDR1_MASK                        0x8000u
+#define I2S_ISR_RDR1_SHIFT                       15
+#define I2S_ISR_RXT_MASK                         0x10000u
+#define I2S_ISR_RXT_SHIFT                        16
+#define I2S_ISR_CMDDU_MASK                       0x20000u
+#define I2S_ISR_CMDDU_SHIFT                      17
+#define I2S_ISR_CMDAU_MASK                       0x40000u
+#define I2S_ISR_CMDAU_SHIFT                      18
+#define I2S_ISR_TRFC_MASK                        0x800000u
+#define I2S_ISR_TRFC_SHIFT                       23
+#define I2S_ISR_RFRC_MASK                        0x1000000u
+#define I2S_ISR_RFRC_SHIFT                       24
+/* IER Bit Fields */
+#define I2S_IER_TFE0EN_MASK                      0x1u
+#define I2S_IER_TFE0EN_SHIFT                     0
+#define I2S_IER_TFE1EN_MASK                      0x2u
+#define I2S_IER_TFE1EN_SHIFT                     1
+#define I2S_IER_RFF0EN_MASK                      0x4u
+#define I2S_IER_RFF0EN_SHIFT                     2
+#define I2S_IER_RFF1EN_MASK                      0x8u
+#define I2S_IER_RFF1EN_SHIFT                     3
+#define I2S_IER_RLSEN_MASK                       0x10u
+#define I2S_IER_RLSEN_SHIFT                      4
+#define I2S_IER_TLSEN_MASK                       0x20u
+#define I2S_IER_TLSEN_SHIFT                      5
+#define I2S_IER_RFSEN_MASK                       0x40u
+#define I2S_IER_RFSEN_SHIFT                      6
+#define I2S_IER_TFSEN_MASK                       0x80u
+#define I2S_IER_TFSEN_SHIFT                      7
+#define I2S_IER_TUE0EN_MASK                      0x100u
+#define I2S_IER_TUE0EN_SHIFT                     8
+#define I2S_IER_TUE1EN_MASK                      0x200u
+#define I2S_IER_TUE1EN_SHIFT                     9
+#define I2S_IER_ROE0EN_MASK                      0x400u
+#define I2S_IER_ROE0EN_SHIFT                     10
+#define I2S_IER_ROE1EN_MASK                      0x800u
+#define I2S_IER_ROE1EN_SHIFT                     11
+#define I2S_IER_TDE0EN_MASK                      0x1000u
+#define I2S_IER_TDE0EN_SHIFT                     12
+#define I2S_IER_TDE1EN_MASK                      0x2000u
+#define I2S_IER_TDE1EN_SHIFT                     13
+#define I2S_IER_RDR0EN_MASK                      0x4000u
+#define I2S_IER_RDR0EN_SHIFT                     14
+#define I2S_IER_RDR1EN_MASK                      0x8000u
+#define I2S_IER_RDR1EN_SHIFT                     15
+#define I2S_IER_RXTEN_MASK                       0x10000u
+#define I2S_IER_RXTEN_SHIFT                      16
+#define I2S_IER_CMDDUEN_MASK                     0x20000u
+#define I2S_IER_CMDDUEN_SHIFT                    17
+#define I2S_IER_CMDAUEN_MASK                     0x40000u
+#define I2S_IER_CMDAUEN_SHIFT                    18
+#define I2S_IER_TIE_MASK                         0x80000u
+#define I2S_IER_TIE_SHIFT                        19
+#define I2S_IER_TDMAE_MASK                       0x100000u
+#define I2S_IER_TDMAE_SHIFT                      20
+#define I2S_IER_RIE_MASK                         0x200000u
+#define I2S_IER_RIE_SHIFT                        21
+#define I2S_IER_RDMAE_MASK                       0x400000u
+#define I2S_IER_RDMAE_SHIFT                      22
+#define I2S_IER_TFRC_EN_MASK                     0x800000u
+#define I2S_IER_TFRC_EN_SHIFT                    23
+#define I2S_IER_RFRC_EN_MASK                     0x1000000u
+#define I2S_IER_RFRC_EN_SHIFT                    24
+/* TCR Bit Fields */
+#define I2S_TCR_TEFS_MASK                        0x1u
+#define I2S_TCR_TEFS_SHIFT                       0
+#define I2S_TCR_TFSL_MASK                        0x2u
+#define I2S_TCR_TFSL_SHIFT                       1
+#define I2S_TCR_TFSI_MASK                        0x4u
+#define I2S_TCR_TFSI_SHIFT                       2
+#define I2S_TCR_TSCKP_MASK                       0x8u
+#define I2S_TCR_TSCKP_SHIFT                      3
+#define I2S_TCR_TSHFD_MASK                       0x10u
+#define I2S_TCR_TSHFD_SHIFT                      4
+#define I2S_TCR_TXDIR_MASK                       0x20u
+#define I2S_TCR_TXDIR_SHIFT                      5
+#define I2S_TCR_TFDIR_MASK                       0x40u
+#define I2S_TCR_TFDIR_SHIFT                      6
+#define I2S_TCR_TFEN0_MASK                       0x80u
+#define I2S_TCR_TFEN0_SHIFT                      7
+#define I2S_TCR_TFEN1_MASK                       0x100u
+#define I2S_TCR_TFEN1_SHIFT                      8
+#define I2S_TCR_TXBIT0_MASK                      0x200u
+#define I2S_TCR_TXBIT0_SHIFT                     9
+/* RCR Bit Fields */
+#define I2S_RCR_REFS_MASK                        0x1u
+#define I2S_RCR_REFS_SHIFT                       0
+#define I2S_RCR_RFSL_MASK                        0x2u
+#define I2S_RCR_RFSL_SHIFT                       1
+#define I2S_RCR_RFSI_MASK                        0x4u
+#define I2S_RCR_RFSI_SHIFT                       2
+#define I2S_RCR_RSCKP_MASK                       0x8u
+#define I2S_RCR_RSCKP_SHIFT                      3
+#define I2S_RCR_RSHFD_MASK                       0x10u
+#define I2S_RCR_RSHFD_SHIFT                      4
+#define I2S_RCR_RXDIR_MASK                       0x20u
+#define I2S_RCR_RXDIR_SHIFT                      5
+#define I2S_RCR_RFDIR_MASK                       0x40u
+#define I2S_RCR_RFDIR_SHIFT                      6
+#define I2S_RCR_RFEN0_MASK                       0x80u
+#define I2S_RCR_RFEN0_SHIFT                      7
+#define I2S_RCR_RFEN1_MASK                       0x100u
+#define I2S_RCR_RFEN1_SHIFT                      8
+#define I2S_RCR_RXBIT0_MASK                      0x200u
+#define I2S_RCR_RXBIT0_SHIFT                     9
+#define I2S_RCR_RXEXT_MASK                       0x400u
+#define I2S_RCR_RXEXT_SHIFT                      10
+/* TCCR Bit Fields */
+#define I2S_TCCR_PM_MASK                         0xFFu
+#define I2S_TCCR_PM_SHIFT                        0
+#define I2S_TCCR_PM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_PM_SHIFT))&I2S_TCCR_PM_MASK)
+#define I2S_TCCR_DC_MASK                         0x1F00u
+#define I2S_TCCR_DC_SHIFT                        8
+#define I2S_TCCR_DC(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_DC_SHIFT))&I2S_TCCR_DC_MASK)
+#define I2S_TCCR_WL_MASK                         0x1E000u
+#define I2S_TCCR_WL_SHIFT                        13
+#define I2S_TCCR_WL(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_TCCR_WL_SHIFT))&I2S_TCCR_WL_MASK)
+#define I2S_TCCR_PSR_MASK                        0x20000u
+#define I2S_TCCR_PSR_SHIFT                       17
+#define I2S_TCCR_DIV2_MASK                       0x40000u
+#define I2S_TCCR_DIV2_SHIFT                      18
+/* RCCR Bit Fields */
+#define I2S_RCCR_PM_MASK                         0xFFu
+#define I2S_RCCR_PM_SHIFT                        0
+#define I2S_RCCR_PM(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_PM_SHIFT))&I2S_RCCR_PM_MASK)
+#define I2S_RCCR_DC_MASK                         0x1F00u
+#define I2S_RCCR_DC_SHIFT                        8
+#define I2S_RCCR_DC(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_DC_SHIFT))&I2S_RCCR_DC_MASK)
+#define I2S_RCCR_WL_MASK                         0x1E000u
+#define I2S_RCCR_WL_SHIFT                        13
+#define I2S_RCCR_WL(x)                           (((uint32_t)(((uint32_t)(x))<<I2S_RCCR_WL_SHIFT))&I2S_RCCR_WL_MASK)
+#define I2S_RCCR_PSR_MASK                        0x20000u
+#define I2S_RCCR_PSR_SHIFT                       17
+#define I2S_RCCR_DIV2_MASK                       0x40000u
+#define I2S_RCCR_DIV2_SHIFT                      18
+/* FCSR Bit Fields */
+#define I2S_FCSR_TFWM0_MASK                      0xFu
+#define I2S_FCSR_TFWM0_SHIFT                     0
+#define I2S_FCSR_TFWM0(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM0_SHIFT))&I2S_FCSR_TFWM0_MASK)
+#define I2S_FCSR_RFWM0_MASK                      0xF0u
+#define I2S_FCSR_RFWM0_SHIFT                     4
+#define I2S_FCSR_RFWM0(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM0_SHIFT))&I2S_FCSR_RFWM0_MASK)
+#define I2S_FCSR_TFCNT0_MASK                     0xF00u
+#define I2S_FCSR_TFCNT0_SHIFT                    8
+#define I2S_FCSR_TFCNT0(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT0_SHIFT))&I2S_FCSR_TFCNT0_MASK)
+#define I2S_FCSR_RFCNT0_MASK                     0xF000u
+#define I2S_FCSR_RFCNT0_SHIFT                    12
+#define I2S_FCSR_RFCNT0(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT0_SHIFT))&I2S_FCSR_RFCNT0_MASK)
+#define I2S_FCSR_TFWM1_MASK                      0xF0000u
+#define I2S_FCSR_TFWM1_SHIFT                     16
+#define I2S_FCSR_TFWM1(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFWM1_SHIFT))&I2S_FCSR_TFWM1_MASK)
+#define I2S_FCSR_RFWM1_MASK                      0xF00000u
+#define I2S_FCSR_RFWM1_SHIFT                     20
+#define I2S_FCSR_RFWM1(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFWM1_SHIFT))&I2S_FCSR_RFWM1_MASK)
+#define I2S_FCSR_TFCNT1_MASK                     0xF000000u
+#define I2S_FCSR_TFCNT1_SHIFT                    24
+#define I2S_FCSR_TFCNT1(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_TFCNT1_SHIFT))&I2S_FCSR_TFCNT1_MASK)
+#define I2S_FCSR_RFCNT1_MASK                     0xF0000000u
+#define I2S_FCSR_RFCNT1_SHIFT                    28
+#define I2S_FCSR_RFCNT1(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_FCSR_RFCNT1_SHIFT))&I2S_FCSR_RFCNT1_MASK)
+/* ACNT Bit Fields */
+#define I2S_ACNT_AC97EN_MASK                     0x1u
+#define I2S_ACNT_AC97EN_SHIFT                    0
+#define I2S_ACNT_FV_MASK                         0x2u
+#define I2S_ACNT_FV_SHIFT                        1
+#define I2S_ACNT_TIF_MASK                        0x4u
+#define I2S_ACNT_TIF_SHIFT                       2
+#define I2S_ACNT_RD_MASK                         0x8u
+#define I2S_ACNT_RD_SHIFT                        3
+#define I2S_ACNT_WR_MASK                         0x10u
+#define I2S_ACNT_WR_SHIFT                        4
+#define I2S_ACNT_FRDIV_MASK                      0x7E0u
+#define I2S_ACNT_FRDIV_SHIFT                     5
+#define I2S_ACNT_FRDIV(x)                        (((uint32_t)(((uint32_t)(x))<<I2S_ACNT_FRDIV_SHIFT))&I2S_ACNT_FRDIV_MASK)
+/* ACADD Bit Fields */
+#define I2S_ACADD_ACADD_MASK                     0x7FFFFu
+#define I2S_ACADD_ACADD_SHIFT                    0
+#define I2S_ACADD_ACADD(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_ACADD_ACADD_SHIFT))&I2S_ACADD_ACADD_MASK)
+/* ACDAT Bit Fields */
+#define I2S_ACDAT_ACDAT_MASK                     0xFFFFFu
+#define I2S_ACDAT_ACDAT_SHIFT                    0
+#define I2S_ACDAT_ACDAT(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_ACDAT_ACDAT_SHIFT))&I2S_ACDAT_ACDAT_MASK)
+/* ATAG Bit Fields */
+#define I2S_ATAG_ATAG_MASK                       0xFFFFu
+#define I2S_ATAG_ATAG_SHIFT                      0
+#define I2S_ATAG_ATAG(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_ATAG_ATAG_SHIFT))&I2S_ATAG_ATAG_MASK)
+/* TMSK Bit Fields */
+#define I2S_TMSK_TMSK_MASK                       0xFFFFFFFFu
+#define I2S_TMSK_TMSK_SHIFT                      0
+#define I2S_TMSK_TMSK(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_TMSK_TMSK_SHIFT))&I2S_TMSK_TMSK_MASK)
+/* RMSK Bit Fields */
+#define I2S_RMSK_RMSK_MASK                       0xFFFFFFFFu
+#define I2S_RMSK_RMSK_SHIFT                      0
+#define I2S_RMSK_RMSK(x)                         (((uint32_t)(((uint32_t)(x))<<I2S_RMSK_RMSK_SHIFT))&I2S_RMSK_RMSK_MASK)
+/* ACCST Bit Fields */
+#define I2S_ACCST_ACCST_MASK                     0x3FFu
+#define I2S_ACCST_ACCST_SHIFT                    0
+#define I2S_ACCST_ACCST(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_ACCST_ACCST_SHIFT))&I2S_ACCST_ACCST_MASK)
+/* ACCEN Bit Fields */
+#define I2S_ACCEN_ACCEN_MASK                     0x3FFu
+#define I2S_ACCEN_ACCEN_SHIFT                    0
+#define I2S_ACCEN_ACCEN(x)                       (((uint32_t)(((uint32_t)(x))<<I2S_ACCEN_ACCEN_SHIFT))&I2S_ACCEN_ACCEN_MASK)
+/* ACCDIS Bit Fields */
+#define I2S_ACCDIS_ACCDIS_MASK                   0x3FFu
+#define I2S_ACCDIS_ACCDIS_SHIFT                  0
+#define I2S_ACCDIS_ACCDIS(x)                     (((uint32_t)(((uint32_t)(x))<<I2S_ACCDIS_ACCDIS_SHIFT))&I2S_ACCDIS_ACCDIS_MASK)
+
+/*! \} */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/*! Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/*! Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+
+/*! \} */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer */
+/*! \{ */
+
+/*! LCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GCR;                               /*!< LCD general control register, offset: 0x0 */
+  __IO uint32_t AR;                                /*!< LCD auxiliary register, offset: 0x4 */
+  __IO uint32_t FDCR;                              /*!< LCD fault detect control register, offset: 0x8 */
+  __IO uint32_t FDSR;                              /*!< LCD fault detect status register, offset: 0xC */
+  __IO uint32_t PEN[2];                            /*!< LCD pin enable register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t BPEN[2];                           /*!< LCD backplane enable register, array offset: 0x18, array step: 0x4 */
+  union {                                          /* offset: 0x20 */
+    __IO uint32_t WF[16];                            /*!< LCD waveform register, array offset: 0x20, array step: 0x4 */
+    __IO uint8_t WF8B[64];                           /*!< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
+  };
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup LCD_Register_Masks LCD Register Masks */
+/*! \{ */
+
+/* GCR Bit Fields */
+#define LCD_GCR_DUTY_MASK                        0x7u
+#define LCD_GCR_DUTY_SHIFT                       0
+#define LCD_GCR_DUTY(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
+#define LCD_GCR_LCLK_MASK                        0x38u
+#define LCD_GCR_LCLK_SHIFT                       3
+#define LCD_GCR_LCLK(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
+#define LCD_GCR_SOURCE_MASK                      0x40u
+#define LCD_GCR_SOURCE_SHIFT                     6
+#define LCD_GCR_LCDEN_MASK                       0x80u
+#define LCD_GCR_LCDEN_SHIFT                      7
+#define LCD_GCR_LCDSTP_MASK                      0x100u
+#define LCD_GCR_LCDSTP_SHIFT                     8
+#define LCD_GCR_LCDWAIT_MASK                     0x200u
+#define LCD_GCR_LCDWAIT_SHIFT                    9
+#define LCD_GCR_ALTDIV_MASK                      0x3000u
+#define LCD_GCR_ALTDIV_SHIFT                     12
+#define LCD_GCR_ALTDIV(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
+#define LCD_GCR_FDCIEN_MASK                      0x4000u
+#define LCD_GCR_FDCIEN_SHIFT                     14
+#define LCD_GCR_LCDIEN_MASK                      0x8000u
+#define LCD_GCR_LCDIEN_SHIFT                     15
+#define LCD_GCR_VSUPPLY_MASK                     0x30000u
+#define LCD_GCR_VSUPPLY_SHIFT                    16
+#define LCD_GCR_VSUPPLY(x)                       (((uint32_t)(((uint32_t)(x))<<LCD_GCR_VSUPPLY_SHIFT))&LCD_GCR_VSUPPLY_MASK)
+#define LCD_GCR_LADJ_MASK                        0x300000u
+#define LCD_GCR_LADJ_SHIFT                       20
+#define LCD_GCR_LADJ(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
+#define LCD_GCR_HREFSEL_MASK                     0x400000u
+#define LCD_GCR_HREFSEL_SHIFT                    22
+#define LCD_GCR_CPSEL_MASK                       0x800000u
+#define LCD_GCR_CPSEL_SHIFT                      23
+#define LCD_GCR_RVTRIM_MASK                      0xF000000u
+#define LCD_GCR_RVTRIM_SHIFT                     24
+#define LCD_GCR_RVTRIM(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
+#define LCD_GCR_RVEN_MASK                        0x80000000u
+#define LCD_GCR_RVEN_SHIFT                       31
+/* AR Bit Fields */
+#define LCD_AR_BRATE_MASK                        0x7u
+#define LCD_AR_BRATE_SHIFT                       0
+#define LCD_AR_BRATE(x)                          (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
+#define LCD_AR_BMODE_MASK                        0x8u
+#define LCD_AR_BMODE_SHIFT                       3
+#define LCD_AR_BLANK_MASK                        0x20u
+#define LCD_AR_BLANK_SHIFT                       5
+#define LCD_AR_ALT_MASK                          0x40u
+#define LCD_AR_ALT_SHIFT                         6
+#define LCD_AR_BLINK_MASK                        0x80u
+#define LCD_AR_BLINK_SHIFT                       7
+#define LCD_AR_LCDIF_MASK                        0x8000u
+#define LCD_AR_LCDIF_SHIFT                       15
+/* FDCR Bit Fields */
+#define LCD_FDCR_FDPINID_MASK                    0x3Fu
+#define LCD_FDCR_FDPINID_SHIFT                   0
+#define LCD_FDCR_FDPINID(x)                      (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
+#define LCD_FDCR_FDBPEN_MASK                     0x40u
+#define LCD_FDCR_FDBPEN_SHIFT                    6
+#define LCD_FDCR_FDEN_MASK                       0x80u
+#define LCD_FDCR_FDEN_SHIFT                      7
+#define LCD_FDCR_FDSWW_MASK                      0xE00u
+#define LCD_FDCR_FDSWW_SHIFT                     9
+#define LCD_FDCR_FDSWW(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
+#define LCD_FDCR_FDPRS_MASK                      0x7000u
+#define LCD_FDCR_FDPRS_SHIFT                     12
+#define LCD_FDCR_FDPRS(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
+/* FDSR Bit Fields */
+#define LCD_FDSR_FDCNT_MASK                      0xFFu
+#define LCD_FDSR_FDCNT_SHIFT                     0
+#define LCD_FDSR_FDCNT(x)                        (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
+#define LCD_FDSR_FDCF_MASK                       0x8000u
+#define LCD_FDSR_FDCF_SHIFT                      15
+/* PEN Bit Fields */
+#define LCD_PEN_PEN_MASK                         0xFFFFFFFFu
+#define LCD_PEN_PEN_SHIFT                        0
+#define LCD_PEN_PEN(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
+/* BPEN Bit Fields */
+#define LCD_BPEN_BPEN_MASK                       0xFFFFFFFFu
+#define LCD_BPEN_BPEN_SHIFT                      0
+#define LCD_BPEN_BPEN(x)                         (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
+/* WF Bit Fields */
+#define LCD_WF_WF0_MASK                          0xFFu
+#define LCD_WF_WF0_SHIFT                         0
+#define LCD_WF_WF0(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
+#define LCD_WF_WF60_MASK                         0xFFu
+#define LCD_WF_WF60_SHIFT                        0
+#define LCD_WF_WF60(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
+#define LCD_WF_WF56_MASK                         0xFFu
+#define LCD_WF_WF56_SHIFT                        0
+#define LCD_WF_WF56(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
+#define LCD_WF_WF52_MASK                         0xFFu
+#define LCD_WF_WF52_SHIFT                        0
+#define LCD_WF_WF52(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
+#define LCD_WF_WF4_MASK                          0xFFu
+#define LCD_WF_WF4_SHIFT                         0
+#define LCD_WF_WF4(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
+#define LCD_WF_WF48_MASK                         0xFFu
+#define LCD_WF_WF48_SHIFT                        0
+#define LCD_WF_WF48(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
+#define LCD_WF_WF44_MASK                         0xFFu
+#define LCD_WF_WF44_SHIFT                        0
+#define LCD_WF_WF44(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
+#define LCD_WF_WF40_MASK                         0xFFu
+#define LCD_WF_WF40_SHIFT                        0
+#define LCD_WF_WF40(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
+#define LCD_WF_WF8_MASK                          0xFFu
+#define LCD_WF_WF8_SHIFT                         0
+#define LCD_WF_WF8(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
+#define LCD_WF_WF36_MASK                         0xFFu
+#define LCD_WF_WF36_SHIFT                        0
+#define LCD_WF_WF36(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
+#define LCD_WF_WF32_MASK                         0xFFu
+#define LCD_WF_WF32_SHIFT                        0
+#define LCD_WF_WF32(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
+#define LCD_WF_WF28_MASK                         0xFFu
+#define LCD_WF_WF28_SHIFT                        0
+#define LCD_WF_WF28(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
+#define LCD_WF_WF12_MASK                         0xFFu
+#define LCD_WF_WF12_SHIFT                        0
+#define LCD_WF_WF12(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
+#define LCD_WF_WF24_MASK                         0xFFu
+#define LCD_WF_WF24_SHIFT                        0
+#define LCD_WF_WF24(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
+#define LCD_WF_WF20_MASK                         0xFFu
+#define LCD_WF_WF20_SHIFT                        0
+#define LCD_WF_WF20(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
+#define LCD_WF_WF16_MASK                         0xFFu
+#define LCD_WF_WF16_SHIFT                        0
+#define LCD_WF_WF16(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
+#define LCD_WF_WF5_MASK                          0xFF00u
+#define LCD_WF_WF5_SHIFT                         8
+#define LCD_WF_WF5(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
+#define LCD_WF_WF49_MASK                         0xFF00u
+#define LCD_WF_WF49_SHIFT                        8
+#define LCD_WF_WF49(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
+#define LCD_WF_WF45_MASK                         0xFF00u
+#define LCD_WF_WF45_SHIFT                        8
+#define LCD_WF_WF45(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
+#define LCD_WF_WF61_MASK                         0xFF00u
+#define LCD_WF_WF61_SHIFT                        8
+#define LCD_WF_WF61(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
+#define LCD_WF_WF25_MASK                         0xFF00u
+#define LCD_WF_WF25_SHIFT                        8
+#define LCD_WF_WF25(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
+#define LCD_WF_WF17_MASK                         0xFF00u
+#define LCD_WF_WF17_SHIFT                        8
+#define LCD_WF_WF17(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
+#define LCD_WF_WF41_MASK                         0xFF00u
+#define LCD_WF_WF41_SHIFT                        8
+#define LCD_WF_WF41(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
+#define LCD_WF_WF13_MASK                         0xFF00u
+#define LCD_WF_WF13_SHIFT                        8
+#define LCD_WF_WF13(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
+#define LCD_WF_WF57_MASK                         0xFF00u
+#define LCD_WF_WF57_SHIFT                        8
+#define LCD_WF_WF57(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
+#define LCD_WF_WF53_MASK                         0xFF00u
+#define LCD_WF_WF53_SHIFT                        8
+#define LCD_WF_WF53(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
+#define LCD_WF_WF37_MASK                         0xFF00u
+#define LCD_WF_WF37_SHIFT                        8
+#define LCD_WF_WF37(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
+#define LCD_WF_WF9_MASK                          0xFF00u
+#define LCD_WF_WF9_SHIFT                         8
+#define LCD_WF_WF9(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
+#define LCD_WF_WF1_MASK                          0xFF00u
+#define LCD_WF_WF1_SHIFT                         8
+#define LCD_WF_WF1(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
+#define LCD_WF_WF29_MASK                         0xFF00u
+#define LCD_WF_WF29_SHIFT                        8
+#define LCD_WF_WF29(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
+#define LCD_WF_WF33_MASK                         0xFF00u
+#define LCD_WF_WF33_SHIFT                        8
+#define LCD_WF_WF33(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
+#define LCD_WF_WF21_MASK                         0xFF00u
+#define LCD_WF_WF21_SHIFT                        8
+#define LCD_WF_WF21(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
+#define LCD_WF_WF26_MASK                         0xFF0000u
+#define LCD_WF_WF26_SHIFT                        16
+#define LCD_WF_WF26(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
+#define LCD_WF_WF46_MASK                         0xFF0000u
+#define LCD_WF_WF46_SHIFT                        16
+#define LCD_WF_WF46(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
+#define LCD_WF_WF6_MASK                          0xFF0000u
+#define LCD_WF_WF6_SHIFT                         16
+#define LCD_WF_WF6(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
+#define LCD_WF_WF42_MASK                         0xFF0000u
+#define LCD_WF_WF42_SHIFT                        16
+#define LCD_WF_WF42(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
+#define LCD_WF_WF18_MASK                         0xFF0000u
+#define LCD_WF_WF18_SHIFT                        16
+#define LCD_WF_WF18(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
+#define LCD_WF_WF38_MASK                         0xFF0000u
+#define LCD_WF_WF38_SHIFT                        16
+#define LCD_WF_WF38(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
+#define LCD_WF_WF22_MASK                         0xFF0000u
+#define LCD_WF_WF22_SHIFT                        16
+#define LCD_WF_WF22(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
+#define LCD_WF_WF34_MASK                         0xFF0000u
+#define LCD_WF_WF34_SHIFT                        16
+#define LCD_WF_WF34(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
+#define LCD_WF_WF50_MASK                         0xFF0000u
+#define LCD_WF_WF50_SHIFT                        16
+#define LCD_WF_WF50(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
+#define LCD_WF_WF14_MASK                         0xFF0000u
+#define LCD_WF_WF14_SHIFT                        16
+#define LCD_WF_WF14(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
+#define LCD_WF_WF54_MASK                         0xFF0000u
+#define LCD_WF_WF54_SHIFT                        16
+#define LCD_WF_WF54(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
+#define LCD_WF_WF2_MASK                          0xFF0000u
+#define LCD_WF_WF2_SHIFT                         16
+#define LCD_WF_WF2(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
+#define LCD_WF_WF58_MASK                         0xFF0000u
+#define LCD_WF_WF58_SHIFT                        16
+#define LCD_WF_WF58(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
+#define LCD_WF_WF30_MASK                         0xFF0000u
+#define LCD_WF_WF30_SHIFT                        16
+#define LCD_WF_WF30(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
+#define LCD_WF_WF62_MASK                         0xFF0000u
+#define LCD_WF_WF62_SHIFT                        16
+#define LCD_WF_WF62(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
+#define LCD_WF_WF10_MASK                         0xFF0000u
+#define LCD_WF_WF10_SHIFT                        16
+#define LCD_WF_WF10(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
+#define LCD_WF_WF63_MASK                         0xFF000000u
+#define LCD_WF_WF63_SHIFT                        24
+#define LCD_WF_WF63(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
+#define LCD_WF_WF59_MASK                         0xFF000000u
+#define LCD_WF_WF59_SHIFT                        24
+#define LCD_WF_WF59(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
+#define LCD_WF_WF55_MASK                         0xFF000000u
+#define LCD_WF_WF55_SHIFT                        24
+#define LCD_WF_WF55(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
+#define LCD_WF_WF3_MASK                          0xFF000000u
+#define LCD_WF_WF3_SHIFT                         24
+#define LCD_WF_WF3(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
+#define LCD_WF_WF51_MASK                         0xFF000000u
+#define LCD_WF_WF51_SHIFT                        24
+#define LCD_WF_WF51(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
+#define LCD_WF_WF47_MASK                         0xFF000000u
+#define LCD_WF_WF47_SHIFT                        24
+#define LCD_WF_WF47(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
+#define LCD_WF_WF43_MASK                         0xFF000000u
+#define LCD_WF_WF43_SHIFT                        24
+#define LCD_WF_WF43(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
+#define LCD_WF_WF7_MASK                          0xFF000000u
+#define LCD_WF_WF7_SHIFT                         24
+#define LCD_WF_WF7(x)                            (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
+#define LCD_WF_WF39_MASK                         0xFF000000u
+#define LCD_WF_WF39_SHIFT                        24
+#define LCD_WF_WF39(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
+#define LCD_WF_WF35_MASK                         0xFF000000u
+#define LCD_WF_WF35_SHIFT                        24
+#define LCD_WF_WF35(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
+#define LCD_WF_WF31_MASK                         0xFF000000u
+#define LCD_WF_WF31_SHIFT                        24
+#define LCD_WF_WF31(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
+#define LCD_WF_WF11_MASK                         0xFF000000u
+#define LCD_WF_WF11_SHIFT                        24
+#define LCD_WF_WF11(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
+#define LCD_WF_WF27_MASK                         0xFF000000u
+#define LCD_WF_WF27_SHIFT                        24
+#define LCD_WF_WF27(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
+#define LCD_WF_WF23_MASK                         0xFF000000u
+#define LCD_WF_WF23_SHIFT                        24
+#define LCD_WF_WF23(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
+#define LCD_WF_WF19_MASK                         0xFF000000u
+#define LCD_WF_WF19_SHIFT                        24
+#define LCD_WF_WF19(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
+#define LCD_WF_WF15_MASK                         0xFF000000u
+#define LCD_WF_WF15_SHIFT                        24
+#define LCD_WF_WF15(x)                           (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
+/* WF8B Bit Fields */
+#define LCD_WF8B_BPALCD0_MASK                    0x1u
+#define LCD_WF8B_BPALCD0_SHIFT                   0
+#define LCD_WF8B_BPALCD63_MASK                   0x1u
+#define LCD_WF8B_BPALCD63_SHIFT                  0
+#define LCD_WF8B_BPALCD62_MASK                   0x1u
+#define LCD_WF8B_BPALCD62_SHIFT                  0
+#define LCD_WF8B_BPALCD61_MASK                   0x1u
+#define LCD_WF8B_BPALCD61_SHIFT                  0
+#define LCD_WF8B_BPALCD60_MASK                   0x1u
+#define LCD_WF8B_BPALCD60_SHIFT                  0
+#define LCD_WF8B_BPALCD59_MASK                   0x1u
+#define LCD_WF8B_BPALCD59_SHIFT                  0
+#define LCD_WF8B_BPALCD58_MASK                   0x1u
+#define LCD_WF8B_BPALCD58_SHIFT                  0
+#define LCD_WF8B_BPALCD57_MASK                   0x1u
+#define LCD_WF8B_BPALCD57_SHIFT                  0
+#define LCD_WF8B_BPALCD1_MASK                    0x1u
+#define LCD_WF8B_BPALCD1_SHIFT                   0
+#define LCD_WF8B_BPALCD56_MASK                   0x1u
+#define LCD_WF8B_BPALCD56_SHIFT                  0
+#define LCD_WF8B_BPALCD55_MASK                   0x1u
+#define LCD_WF8B_BPALCD55_SHIFT                  0
+#define LCD_WF8B_BPALCD54_MASK                   0x1u
+#define LCD_WF8B_BPALCD54_SHIFT                  0
+#define LCD_WF8B_BPALCD53_MASK                   0x1u
+#define LCD_WF8B_BPALCD53_SHIFT                  0
+#define LCD_WF8B_BPALCD52_MASK                   0x1u
+#define LCD_WF8B_BPALCD52_SHIFT                  0
+#define LCD_WF8B_BPALCD51_MASK                   0x1u
+#define LCD_WF8B_BPALCD51_SHIFT                  0
+#define LCD_WF8B_BPALCD50_MASK                   0x1u
+#define LCD_WF8B_BPALCD50_SHIFT                  0
+#define LCD_WF8B_BPALCD2_MASK                    0x1u
+#define LCD_WF8B_BPALCD2_SHIFT                   0
+#define LCD_WF8B_BPALCD49_MASK                   0x1u
+#define LCD_WF8B_BPALCD49_SHIFT                  0
+#define LCD_WF8B_BPALCD48_MASK                   0x1u
+#define LCD_WF8B_BPALCD48_SHIFT                  0
+#define LCD_WF8B_BPALCD47_MASK                   0x1u
+#define LCD_WF8B_BPALCD47_SHIFT                  0
+#define LCD_WF8B_BPALCD46_MASK                   0x1u
+#define LCD_WF8B_BPALCD46_SHIFT                  0
+#define LCD_WF8B_BPALCD45_MASK                   0x1u
+#define LCD_WF8B_BPALCD45_SHIFT                  0
+#define LCD_WF8B_BPALCD44_MASK                   0x1u
+#define LCD_WF8B_BPALCD44_SHIFT                  0
+#define LCD_WF8B_BPALCD43_MASK                   0x1u
+#define LCD_WF8B_BPALCD43_SHIFT                  0
+#define LCD_WF8B_BPALCD3_MASK                    0x1u
+#define LCD_WF8B_BPALCD3_SHIFT                   0
+#define LCD_WF8B_BPALCD42_MASK                   0x1u
+#define LCD_WF8B_BPALCD42_SHIFT                  0
+#define LCD_WF8B_BPALCD41_MASK                   0x1u
+#define LCD_WF8B_BPALCD41_SHIFT                  0
+#define LCD_WF8B_BPALCD40_MASK                   0x1u
+#define LCD_WF8B_BPALCD40_SHIFT                  0
+#define LCD_WF8B_BPALCD39_MASK                   0x1u
+#define LCD_WF8B_BPALCD39_SHIFT                  0
+#define LCD_WF8B_BPALCD38_MASK                   0x1u
+#define LCD_WF8B_BPALCD38_SHIFT                  0
+#define LCD_WF8B_BPALCD37_MASK                   0x1u
+#define LCD_WF8B_BPALCD37_SHIFT                  0
+#define LCD_WF8B_BPALCD36_MASK                   0x1u
+#define LCD_WF8B_BPALCD36_SHIFT                  0
+#define LCD_WF8B_BPALCD4_MASK                    0x1u
+#define LCD_WF8B_BPALCD4_SHIFT                   0
+#define LCD_WF8B_BPALCD35_MASK                   0x1u
+#define LCD_WF8B_BPALCD35_SHIFT                  0
+#define LCD_WF8B_BPALCD34_MASK                   0x1u
+#define LCD_WF8B_BPALCD34_SHIFT                  0
+#define LCD_WF8B_BPALCD33_MASK                   0x1u
+#define LCD_WF8B_BPALCD33_SHIFT                  0
+#define LCD_WF8B_BPALCD32_MASK                   0x1u
+#define LCD_WF8B_BPALCD32_SHIFT                  0
+#define LCD_WF8B_BPALCD31_MASK                   0x1u
+#define LCD_WF8B_BPALCD31_SHIFT                  0
+#define LCD_WF8B_BPALCD30_MASK                   0x1u
+#define LCD_WF8B_BPALCD30_SHIFT                  0
+#define LCD_WF8B_BPALCD29_MASK                   0x1u
+#define LCD_WF8B_BPALCD29_SHIFT                  0
+#define LCD_WF8B_BPALCD5_MASK                    0x1u
+#define LCD_WF8B_BPALCD5_SHIFT                   0
+#define LCD_WF8B_BPALCD28_MASK                   0x1u
+#define LCD_WF8B_BPALCD28_SHIFT                  0
+#define LCD_WF8B_BPALCD27_MASK                   0x1u
+#define LCD_WF8B_BPALCD27_SHIFT                  0
+#define LCD_WF8B_BPALCD26_MASK                   0x1u
+#define LCD_WF8B_BPALCD26_SHIFT                  0
+#define LCD_WF8B_BPALCD25_MASK                   0x1u
+#define LCD_WF8B_BPALCD25_SHIFT                  0
+#define LCD_WF8B_BPALCD24_MASK                   0x1u
+#define LCD_WF8B_BPALCD24_SHIFT                  0
+#define LCD_WF8B_BPALCD23_MASK                   0x1u
+#define LCD_WF8B_BPALCD23_SHIFT                  0
+#define LCD_WF8B_BPALCD22_MASK                   0x1u
+#define LCD_WF8B_BPALCD22_SHIFT                  0
+#define LCD_WF8B_BPALCD6_MASK                    0x1u
+#define LCD_WF8B_BPALCD6_SHIFT                   0
+#define LCD_WF8B_BPALCD21_MASK                   0x1u
+#define LCD_WF8B_BPALCD21_SHIFT                  0
+#define LCD_WF8B_BPALCD20_MASK                   0x1u
+#define LCD_WF8B_BPALCD20_SHIFT                  0
+#define LCD_WF8B_BPALCD19_MASK                   0x1u
+#define LCD_WF8B_BPALCD19_SHIFT                  0
+#define LCD_WF8B_BPALCD18_MASK                   0x1u
+#define LCD_WF8B_BPALCD18_SHIFT                  0
+#define LCD_WF8B_BPALCD17_MASK                   0x1u
+#define LCD_WF8B_BPALCD17_SHIFT                  0
+#define LCD_WF8B_BPALCD16_MASK                   0x1u
+#define LCD_WF8B_BPALCD16_SHIFT                  0
+#define LCD_WF8B_BPALCD15_MASK                   0x1u
+#define LCD_WF8B_BPALCD15_SHIFT                  0
+#define LCD_WF8B_BPALCD7_MASK                    0x1u
+#define LCD_WF8B_BPALCD7_SHIFT                   0
+#define LCD_WF8B_BPALCD14_MASK                   0x1u
+#define LCD_WF8B_BPALCD14_SHIFT                  0
+#define LCD_WF8B_BPALCD13_MASK                   0x1u
+#define LCD_WF8B_BPALCD13_SHIFT                  0
+#define LCD_WF8B_BPALCD12_MASK                   0x1u
+#define LCD_WF8B_BPALCD12_SHIFT                  0
+#define LCD_WF8B_BPALCD11_MASK                   0x1u
+#define LCD_WF8B_BPALCD11_SHIFT                  0
+#define LCD_WF8B_BPALCD10_MASK                   0x1u
+#define LCD_WF8B_BPALCD10_SHIFT                  0
+#define LCD_WF8B_BPALCD9_MASK                    0x1u
+#define LCD_WF8B_BPALCD9_SHIFT                   0
+#define LCD_WF8B_BPALCD8_MASK                    0x1u
+#define LCD_WF8B_BPALCD8_SHIFT                   0
+#define LCD_WF8B_BPBLCD1_MASK                    0x2u
+#define LCD_WF8B_BPBLCD1_SHIFT                   1
+#define LCD_WF8B_BPBLCD32_MASK                   0x2u
+#define LCD_WF8B_BPBLCD32_SHIFT                  1
+#define LCD_WF8B_BPBLCD30_MASK                   0x2u
+#define LCD_WF8B_BPBLCD30_SHIFT                  1
+#define LCD_WF8B_BPBLCD60_MASK                   0x2u
+#define LCD_WF8B_BPBLCD60_SHIFT                  1
+#define LCD_WF8B_BPBLCD24_MASK                   0x2u
+#define LCD_WF8B_BPBLCD24_SHIFT                  1
+#define LCD_WF8B_BPBLCD28_MASK                   0x2u
+#define LCD_WF8B_BPBLCD28_SHIFT                  1
+#define LCD_WF8B_BPBLCD23_MASK                   0x2u
+#define LCD_WF8B_BPBLCD23_SHIFT                  1
+#define LCD_WF8B_BPBLCD48_MASK                   0x2u
+#define LCD_WF8B_BPBLCD48_SHIFT                  1
+#define LCD_WF8B_BPBLCD10_MASK                   0x2u
+#define LCD_WF8B_BPBLCD10_SHIFT                  1
+#define LCD_WF8B_BPBLCD15_MASK                   0x2u
+#define LCD_WF8B_BPBLCD15_SHIFT                  1
+#define LCD_WF8B_BPBLCD36_MASK                   0x2u
+#define LCD_WF8B_BPBLCD36_SHIFT                  1
+#define LCD_WF8B_BPBLCD44_MASK                   0x2u
+#define LCD_WF8B_BPBLCD44_SHIFT                  1
+#define LCD_WF8B_BPBLCD62_MASK                   0x2u
+#define LCD_WF8B_BPBLCD62_SHIFT                  1
+#define LCD_WF8B_BPBLCD53_MASK                   0x2u
+#define LCD_WF8B_BPBLCD53_SHIFT                  1
+#define LCD_WF8B_BPBLCD22_MASK                   0x2u
+#define LCD_WF8B_BPBLCD22_SHIFT                  1
+#define LCD_WF8B_BPBLCD47_MASK                   0x2u
+#define LCD_WF8B_BPBLCD47_SHIFT                  1
+#define LCD_WF8B_BPBLCD33_MASK                   0x2u
+#define LCD_WF8B_BPBLCD33_SHIFT                  1
+#define LCD_WF8B_BPBLCD2_MASK                    0x2u
+#define LCD_WF8B_BPBLCD2_SHIFT                   1
+#define LCD_WF8B_BPBLCD49_MASK                   0x2u
+#define LCD_WF8B_BPBLCD49_SHIFT                  1
+#define LCD_WF8B_BPBLCD0_MASK                    0x2u
+#define LCD_WF8B_BPBLCD0_SHIFT                   1
+#define LCD_WF8B_BPBLCD55_MASK                   0x2u
+#define LCD_WF8B_BPBLCD55_SHIFT                  1
+#define LCD_WF8B_BPBLCD56_MASK                   0x2u
+#define LCD_WF8B_BPBLCD56_SHIFT                  1
+#define LCD_WF8B_BPBLCD21_MASK                   0x2u
+#define LCD_WF8B_BPBLCD21_SHIFT                  1
+#define LCD_WF8B_BPBLCD6_MASK                    0x2u
+#define LCD_WF8B_BPBLCD6_SHIFT                   1
+#define LCD_WF8B_BPBLCD29_MASK                   0x2u
+#define LCD_WF8B_BPBLCD29_SHIFT                  1
+#define LCD_WF8B_BPBLCD25_MASK                   0x2u
+#define LCD_WF8B_BPBLCD25_SHIFT                  1
+#define LCD_WF8B_BPBLCD8_MASK                    0x2u
+#define LCD_WF8B_BPBLCD8_SHIFT                   1
+#define LCD_WF8B_BPBLCD54_MASK                   0x2u
+#define LCD_WF8B_BPBLCD54_SHIFT                  1
+#define LCD_WF8B_BPBLCD38_MASK                   0x2u
+#define LCD_WF8B_BPBLCD38_SHIFT                  1
+#define LCD_WF8B_BPBLCD43_MASK                   0x2u
+#define LCD_WF8B_BPBLCD43_SHIFT                  1
+#define LCD_WF8B_BPBLCD20_MASK                   0x2u
+#define LCD_WF8B_BPBLCD20_SHIFT                  1
+#define LCD_WF8B_BPBLCD9_MASK                    0x2u
+#define LCD_WF8B_BPBLCD9_SHIFT                   1
+#define LCD_WF8B_BPBLCD7_MASK                    0x2u
+#define LCD_WF8B_BPBLCD7_SHIFT                   1
+#define LCD_WF8B_BPBLCD50_MASK                   0x2u
+#define LCD_WF8B_BPBLCD50_SHIFT                  1
+#define LCD_WF8B_BPBLCD40_MASK                   0x2u
+#define LCD_WF8B_BPBLCD40_SHIFT                  1
+#define LCD_WF8B_BPBLCD63_MASK                   0x2u
+#define LCD_WF8B_BPBLCD63_SHIFT                  1
+#define LCD_WF8B_BPBLCD26_MASK                   0x2u
+#define LCD_WF8B_BPBLCD26_SHIFT                  1
+#define LCD_WF8B_BPBLCD12_MASK                   0x2u
+#define LCD_WF8B_BPBLCD12_SHIFT                  1
+#define LCD_WF8B_BPBLCD19_MASK                   0x2u
+#define LCD_WF8B_BPBLCD19_SHIFT                  1
+#define LCD_WF8B_BPBLCD34_MASK                   0x2u
+#define LCD_WF8B_BPBLCD34_SHIFT                  1
+#define LCD_WF8B_BPBLCD39_MASK                   0x2u
+#define LCD_WF8B_BPBLCD39_SHIFT                  1
+#define LCD_WF8B_BPBLCD59_MASK                   0x2u
+#define LCD_WF8B_BPBLCD59_SHIFT                  1
+#define LCD_WF8B_BPBLCD61_MASK                   0x2u
+#define LCD_WF8B_BPBLCD61_SHIFT                  1
+#define LCD_WF8B_BPBLCD37_MASK                   0x2u
+#define LCD_WF8B_BPBLCD37_SHIFT                  1
+#define LCD_WF8B_BPBLCD31_MASK                   0x2u
+#define LCD_WF8B_BPBLCD31_SHIFT                  1
+#define LCD_WF8B_BPBLCD58_MASK                   0x2u
+#define LCD_WF8B_BPBLCD58_SHIFT                  1
+#define LCD_WF8B_BPBLCD18_MASK                   0x2u
+#define LCD_WF8B_BPBLCD18_SHIFT                  1
+#define LCD_WF8B_BPBLCD45_MASK                   0x2u
+#define LCD_WF8B_BPBLCD45_SHIFT                  1
+#define LCD_WF8B_BPBLCD27_MASK                   0x2u
+#define LCD_WF8B_BPBLCD27_SHIFT                  1
+#define LCD_WF8B_BPBLCD14_MASK                   0x2u
+#define LCD_WF8B_BPBLCD14_SHIFT                  1
+#define LCD_WF8B_BPBLCD51_MASK                   0x2u
+#define LCD_WF8B_BPBLCD51_SHIFT                  1
+#define LCD_WF8B_BPBLCD52_MASK                   0x2u
+#define LCD_WF8B_BPBLCD52_SHIFT                  1
+#define LCD_WF8B_BPBLCD4_MASK                    0x2u
+#define LCD_WF8B_BPBLCD4_SHIFT                   1
+#define LCD_WF8B_BPBLCD35_MASK                   0x2u
+#define LCD_WF8B_BPBLCD35_SHIFT                  1
+#define LCD_WF8B_BPBLCD17_MASK                   0x2u
+#define LCD_WF8B_BPBLCD17_SHIFT                  1
+#define LCD_WF8B_BPBLCD41_MASK                   0x2u
+#define LCD_WF8B_BPBLCD41_SHIFT                  1
+#define LCD_WF8B_BPBLCD11_MASK                   0x2u
+#define LCD_WF8B_BPBLCD11_SHIFT                  1
+#define LCD_WF8B_BPBLCD46_MASK                   0x2u
+#define LCD_WF8B_BPBLCD46_SHIFT                  1
+#define LCD_WF8B_BPBLCD57_MASK                   0x2u
+#define LCD_WF8B_BPBLCD57_SHIFT                  1
+#define LCD_WF8B_BPBLCD42_MASK                   0x2u
+#define LCD_WF8B_BPBLCD42_SHIFT                  1
+#define LCD_WF8B_BPBLCD5_MASK                    0x2u
+#define LCD_WF8B_BPBLCD5_SHIFT                   1
+#define LCD_WF8B_BPBLCD3_MASK                    0x2u
+#define LCD_WF8B_BPBLCD3_SHIFT                   1
+#define LCD_WF8B_BPBLCD16_MASK                   0x2u
+#define LCD_WF8B_BPBLCD16_SHIFT                  1
+#define LCD_WF8B_BPBLCD13_MASK                   0x2u
+#define LCD_WF8B_BPBLCD13_SHIFT                  1
+#define LCD_WF8B_BPCLCD10_MASK                   0x4u
+#define LCD_WF8B_BPCLCD10_SHIFT                  2
+#define LCD_WF8B_BPCLCD55_MASK                   0x4u
+#define LCD_WF8B_BPCLCD55_SHIFT                  2
+#define LCD_WF8B_BPCLCD2_MASK                    0x4u
+#define LCD_WF8B_BPCLCD2_SHIFT                   2
+#define LCD_WF8B_BPCLCD23_MASK                   0x4u
+#define LCD_WF8B_BPCLCD23_SHIFT                  2
+#define LCD_WF8B_BPCLCD48_MASK                   0x4u
+#define LCD_WF8B_BPCLCD48_SHIFT                  2
+#define LCD_WF8B_BPCLCD24_MASK                   0x4u
+#define LCD_WF8B_BPCLCD24_SHIFT                  2
+#define LCD_WF8B_BPCLCD60_MASK                   0x4u
+#define LCD_WF8B_BPCLCD60_SHIFT                  2
+#define LCD_WF8B_BPCLCD47_MASK                   0x4u
+#define LCD_WF8B_BPCLCD47_SHIFT                  2
+#define LCD_WF8B_BPCLCD22_MASK                   0x4u
+#define LCD_WF8B_BPCLCD22_SHIFT                  2
+#define LCD_WF8B_BPCLCD8_MASK                    0x4u
+#define LCD_WF8B_BPCLCD8_SHIFT                   2
+#define LCD_WF8B_BPCLCD21_MASK                   0x4u
+#define LCD_WF8B_BPCLCD21_SHIFT                  2
+#define LCD_WF8B_BPCLCD49_MASK                   0x4u
+#define LCD_WF8B_BPCLCD49_SHIFT                  2
+#define LCD_WF8B_BPCLCD25_MASK                   0x4u
+#define LCD_WF8B_BPCLCD25_SHIFT                  2
+#define LCD_WF8B_BPCLCD1_MASK                    0x4u
+#define LCD_WF8B_BPCLCD1_SHIFT                   2
+#define LCD_WF8B_BPCLCD20_MASK                   0x4u
+#define LCD_WF8B_BPCLCD20_SHIFT                  2
+#define LCD_WF8B_BPCLCD50_MASK                   0x4u
+#define LCD_WF8B_BPCLCD50_SHIFT                  2
+#define LCD_WF8B_BPCLCD19_MASK                   0x4u
+#define LCD_WF8B_BPCLCD19_SHIFT                  2
+#define LCD_WF8B_BPCLCD26_MASK                   0x4u
+#define LCD_WF8B_BPCLCD26_SHIFT                  2
+#define LCD_WF8B_BPCLCD59_MASK                   0x4u
+#define LCD_WF8B_BPCLCD59_SHIFT                  2
+#define LCD_WF8B_BPCLCD61_MASK                   0x4u
+#define LCD_WF8B_BPCLCD61_SHIFT                  2
+#define LCD_WF8B_BPCLCD46_MASK                   0x4u
+#define LCD_WF8B_BPCLCD46_SHIFT                  2
+#define LCD_WF8B_BPCLCD18_MASK                   0x4u
+#define LCD_WF8B_BPCLCD18_SHIFT                  2
+#define LCD_WF8B_BPCLCD5_MASK                    0x4u
+#define LCD_WF8B_BPCLCD5_SHIFT                   2
+#define LCD_WF8B_BPCLCD63_MASK                   0x4u
+#define LCD_WF8B_BPCLCD63_SHIFT                  2
+#define LCD_WF8B_BPCLCD27_MASK                   0x4u
+#define LCD_WF8B_BPCLCD27_SHIFT                  2
+#define LCD_WF8B_BPCLCD17_MASK                   0x4u
+#define LCD_WF8B_BPCLCD17_SHIFT                  2
+#define LCD_WF8B_BPCLCD51_MASK                   0x4u
+#define LCD_WF8B_BPCLCD51_SHIFT                  2
+#define LCD_WF8B_BPCLCD9_MASK                    0x4u
+#define LCD_WF8B_BPCLCD9_SHIFT                   2
+#define LCD_WF8B_BPCLCD54_MASK                   0x4u
+#define LCD_WF8B_BPCLCD54_SHIFT                  2
+#define LCD_WF8B_BPCLCD15_MASK                   0x4u
+#define LCD_WF8B_BPCLCD15_SHIFT                  2
+#define LCD_WF8B_BPCLCD16_MASK                   0x4u
+#define LCD_WF8B_BPCLCD16_SHIFT                  2
+#define LCD_WF8B_BPCLCD14_MASK                   0x4u
+#define LCD_WF8B_BPCLCD14_SHIFT                  2
+#define LCD_WF8B_BPCLCD32_MASK                   0x4u
+#define LCD_WF8B_BPCLCD32_SHIFT                  2
+#define LCD_WF8B_BPCLCD28_MASK                   0x4u
+#define LCD_WF8B_BPCLCD28_SHIFT                  2
+#define LCD_WF8B_BPCLCD53_MASK                   0x4u
+#define LCD_WF8B_BPCLCD53_SHIFT                  2
+#define LCD_WF8B_BPCLCD33_MASK                   0x4u
+#define LCD_WF8B_BPCLCD33_SHIFT                  2
+#define LCD_WF8B_BPCLCD0_MASK                    0x4u
+#define LCD_WF8B_BPCLCD0_SHIFT                   2
+#define LCD_WF8B_BPCLCD43_MASK                   0x4u
+#define LCD_WF8B_BPCLCD43_SHIFT                  2
+#define LCD_WF8B_BPCLCD7_MASK                    0x4u
+#define LCD_WF8B_BPCLCD7_SHIFT                   2
+#define LCD_WF8B_BPCLCD4_MASK                    0x4u
+#define LCD_WF8B_BPCLCD4_SHIFT                   2
+#define LCD_WF8B_BPCLCD34_MASK                   0x4u
+#define LCD_WF8B_BPCLCD34_SHIFT                  2
+#define LCD_WF8B_BPCLCD29_MASK                   0x4u
+#define LCD_WF8B_BPCLCD29_SHIFT                  2
+#define LCD_WF8B_BPCLCD45_MASK                   0x4u
+#define LCD_WF8B_BPCLCD45_SHIFT                  2
+#define LCD_WF8B_BPCLCD57_MASK                   0x4u
+#define LCD_WF8B_BPCLCD57_SHIFT                  2
+#define LCD_WF8B_BPCLCD42_MASK                   0x4u
+#define LCD_WF8B_BPCLCD42_SHIFT                  2
+#define LCD_WF8B_BPCLCD35_MASK                   0x4u
+#define LCD_WF8B_BPCLCD35_SHIFT                  2
+#define LCD_WF8B_BPCLCD13_MASK                   0x4u
+#define LCD_WF8B_BPCLCD13_SHIFT                  2
+#define LCD_WF8B_BPCLCD36_MASK                   0x4u
+#define LCD_WF8B_BPCLCD36_SHIFT                  2
+#define LCD_WF8B_BPCLCD30_MASK                   0x4u
+#define LCD_WF8B_BPCLCD30_SHIFT                  2
+#define LCD_WF8B_BPCLCD52_MASK                   0x4u
+#define LCD_WF8B_BPCLCD52_SHIFT                  2
+#define LCD_WF8B_BPCLCD58_MASK                   0x4u
+#define LCD_WF8B_BPCLCD58_SHIFT                  2
+#define LCD_WF8B_BPCLCD41_MASK                   0x4u
+#define LCD_WF8B_BPCLCD41_SHIFT                  2
+#define LCD_WF8B_BPCLCD37_MASK                   0x4u
+#define LCD_WF8B_BPCLCD37_SHIFT                  2
+#define LCD_WF8B_BPCLCD3_MASK                    0x4u
+#define LCD_WF8B_BPCLCD3_SHIFT                   2
+#define LCD_WF8B_BPCLCD12_MASK                   0x4u
+#define LCD_WF8B_BPCLCD12_SHIFT                  2
+#define LCD_WF8B_BPCLCD11_MASK                   0x4u
+#define LCD_WF8B_BPCLCD11_SHIFT                  2
+#define LCD_WF8B_BPCLCD38_MASK                   0x4u
+#define LCD_WF8B_BPCLCD38_SHIFT                  2
+#define LCD_WF8B_BPCLCD44_MASK                   0x4u
+#define LCD_WF8B_BPCLCD44_SHIFT                  2
+#define LCD_WF8B_BPCLCD31_MASK                   0x4u
+#define LCD_WF8B_BPCLCD31_SHIFT                  2
+#define LCD_WF8B_BPCLCD40_MASK                   0x4u
+#define LCD_WF8B_BPCLCD40_SHIFT                  2
+#define LCD_WF8B_BPCLCD62_MASK                   0x4u
+#define LCD_WF8B_BPCLCD62_SHIFT                  2
+#define LCD_WF8B_BPCLCD56_MASK                   0x4u
+#define LCD_WF8B_BPCLCD56_SHIFT                  2
+#define LCD_WF8B_BPCLCD39_MASK                   0x4u
+#define LCD_WF8B_BPCLCD39_SHIFT                  2
+#define LCD_WF8B_BPCLCD6_MASK                    0x4u
+#define LCD_WF8B_BPCLCD6_SHIFT                   2
+#define LCD_WF8B_BPDLCD47_MASK                   0x8u
+#define LCD_WF8B_BPDLCD47_SHIFT                  3
+#define LCD_WF8B_BPDLCD23_MASK                   0x8u
+#define LCD_WF8B_BPDLCD23_SHIFT                  3
+#define LCD_WF8B_BPDLCD48_MASK                   0x8u
+#define LCD_WF8B_BPDLCD48_SHIFT                  3
+#define LCD_WF8B_BPDLCD24_MASK                   0x8u
+#define LCD_WF8B_BPDLCD24_SHIFT                  3
+#define LCD_WF8B_BPDLCD15_MASK                   0x8u
+#define LCD_WF8B_BPDLCD15_SHIFT                  3
+#define LCD_WF8B_BPDLCD22_MASK                   0x8u
+#define LCD_WF8B_BPDLCD22_SHIFT                  3
+#define LCD_WF8B_BPDLCD60_MASK                   0x8u
+#define LCD_WF8B_BPDLCD60_SHIFT                  3
+#define LCD_WF8B_BPDLCD10_MASK                   0x8u
+#define LCD_WF8B_BPDLCD10_SHIFT                  3
+#define LCD_WF8B_BPDLCD21_MASK                   0x8u
+#define LCD_WF8B_BPDLCD21_SHIFT                  3
+#define LCD_WF8B_BPDLCD49_MASK                   0x8u
+#define LCD_WF8B_BPDLCD49_SHIFT                  3
+#define LCD_WF8B_BPDLCD1_MASK                    0x8u
+#define LCD_WF8B_BPDLCD1_SHIFT                   3
+#define LCD_WF8B_BPDLCD25_MASK                   0x8u
+#define LCD_WF8B_BPDLCD25_SHIFT                  3
+#define LCD_WF8B_BPDLCD20_MASK                   0x8u
+#define LCD_WF8B_BPDLCD20_SHIFT                  3
+#define LCD_WF8B_BPDLCD2_MASK                    0x8u
+#define LCD_WF8B_BPDLCD2_SHIFT                   3
+#define LCD_WF8B_BPDLCD55_MASK                   0x8u
+#define LCD_WF8B_BPDLCD55_SHIFT                  3
+#define LCD_WF8B_BPDLCD59_MASK                   0x8u
+#define LCD_WF8B_BPDLCD59_SHIFT                  3
+#define LCD_WF8B_BPDLCD5_MASK                    0x8u
+#define LCD_WF8B_BPDLCD5_SHIFT                   3
+#define LCD_WF8B_BPDLCD19_MASK                   0x8u
+#define LCD_WF8B_BPDLCD19_SHIFT                  3
+#define LCD_WF8B_BPDLCD6_MASK                    0x8u
+#define LCD_WF8B_BPDLCD6_SHIFT                   3
+#define LCD_WF8B_BPDLCD26_MASK                   0x8u
+#define LCD_WF8B_BPDLCD26_SHIFT                  3
+#define LCD_WF8B_BPDLCD0_MASK                    0x8u
+#define LCD_WF8B_BPDLCD0_SHIFT                   3
+#define LCD_WF8B_BPDLCD50_MASK                   0x8u
+#define LCD_WF8B_BPDLCD50_SHIFT                  3
+#define LCD_WF8B_BPDLCD46_MASK                   0x8u
+#define LCD_WF8B_BPDLCD46_SHIFT                  3
+#define LCD_WF8B_BPDLCD18_MASK                   0x8u
+#define LCD_WF8B_BPDLCD18_SHIFT                  3
+#define LCD_WF8B_BPDLCD61_MASK                   0x8u
+#define LCD_WF8B_BPDLCD61_SHIFT                  3
+#define LCD_WF8B_BPDLCD9_MASK                    0x8u
+#define LCD_WF8B_BPDLCD9_SHIFT                   3
+#define LCD_WF8B_BPDLCD17_MASK                   0x8u
+#define LCD_WF8B_BPDLCD17_SHIFT                  3
+#define LCD_WF8B_BPDLCD27_MASK                   0x8u
+#define LCD_WF8B_BPDLCD27_SHIFT                  3
+#define LCD_WF8B_BPDLCD53_MASK                   0x8u
+#define LCD_WF8B_BPDLCD53_SHIFT                  3
+#define LCD_WF8B_BPDLCD51_MASK                   0x8u
+#define LCD_WF8B_BPDLCD51_SHIFT                  3
+#define LCD_WF8B_BPDLCD54_MASK                   0x8u
+#define LCD_WF8B_BPDLCD54_SHIFT                  3
+#define LCD_WF8B_BPDLCD13_MASK                   0x8u
+#define LCD_WF8B_BPDLCD13_SHIFT                  3
+#define LCD_WF8B_BPDLCD16_MASK                   0x8u
+#define LCD_WF8B_BPDLCD16_SHIFT                  3
+#define LCD_WF8B_BPDLCD32_MASK                   0x8u
+#define LCD_WF8B_BPDLCD32_SHIFT                  3
+#define LCD_WF8B_BPDLCD14_MASK                   0x8u
+#define LCD_WF8B_BPDLCD14_SHIFT                  3
+#define LCD_WF8B_BPDLCD28_MASK                   0x8u
+#define LCD_WF8B_BPDLCD28_SHIFT                  3
+#define LCD_WF8B_BPDLCD43_MASK                   0x8u
+#define LCD_WF8B_BPDLCD43_SHIFT                  3
+#define LCD_WF8B_BPDLCD4_MASK                    0x8u
+#define LCD_WF8B_BPDLCD4_SHIFT                   3
+#define LCD_WF8B_BPDLCD45_MASK                   0x8u
+#define LCD_WF8B_BPDLCD45_SHIFT                  3
+#define LCD_WF8B_BPDLCD8_MASK                    0x8u
+#define LCD_WF8B_BPDLCD8_SHIFT                   3
+#define LCD_WF8B_BPDLCD62_MASK                   0x8u
+#define LCD_WF8B_BPDLCD62_SHIFT                  3
+#define LCD_WF8B_BPDLCD33_MASK                   0x8u
+#define LCD_WF8B_BPDLCD33_SHIFT                  3
+#define LCD_WF8B_BPDLCD34_MASK                   0x8u
+#define LCD_WF8B_BPDLCD34_SHIFT                  3
+#define LCD_WF8B_BPDLCD29_MASK                   0x8u
+#define LCD_WF8B_BPDLCD29_SHIFT                  3
+#define LCD_WF8B_BPDLCD58_MASK                   0x8u
+#define LCD_WF8B_BPDLCD58_SHIFT                  3
+#define LCD_WF8B_BPDLCD57_MASK                   0x8u
+#define LCD_WF8B_BPDLCD57_SHIFT                  3
+#define LCD_WF8B_BPDLCD42_MASK                   0x8u
+#define LCD_WF8B_BPDLCD42_SHIFT                  3
+#define LCD_WF8B_BPDLCD35_MASK                   0x8u
+#define LCD_WF8B_BPDLCD35_SHIFT                  3
+#define LCD_WF8B_BPDLCD52_MASK                   0x8u
+#define LCD_WF8B_BPDLCD52_SHIFT                  3
+#define LCD_WF8B_BPDLCD7_MASK                    0x8u
+#define LCD_WF8B_BPDLCD7_SHIFT                   3
+#define LCD_WF8B_BPDLCD36_MASK                   0x8u
+#define LCD_WF8B_BPDLCD36_SHIFT                  3
+#define LCD_WF8B_BPDLCD30_MASK                   0x8u
+#define LCD_WF8B_BPDLCD30_SHIFT                  3
+#define LCD_WF8B_BPDLCD41_MASK                   0x8u
+#define LCD_WF8B_BPDLCD41_SHIFT                  3
+#define LCD_WF8B_BPDLCD37_MASK                   0x8u
+#define LCD_WF8B_BPDLCD37_SHIFT                  3
+#define LCD_WF8B_BPDLCD44_MASK                   0x8u
+#define LCD_WF8B_BPDLCD44_SHIFT                  3
+#define LCD_WF8B_BPDLCD63_MASK                   0x8u
+#define LCD_WF8B_BPDLCD63_SHIFT                  3
+#define LCD_WF8B_BPDLCD38_MASK                   0x8u
+#define LCD_WF8B_BPDLCD38_SHIFT                  3
+#define LCD_WF8B_BPDLCD56_MASK                   0x8u
+#define LCD_WF8B_BPDLCD56_SHIFT                  3
+#define LCD_WF8B_BPDLCD40_MASK                   0x8u
+#define LCD_WF8B_BPDLCD40_SHIFT                  3
+#define LCD_WF8B_BPDLCD31_MASK                   0x8u
+#define LCD_WF8B_BPDLCD31_SHIFT                  3
+#define LCD_WF8B_BPDLCD12_MASK                   0x8u
+#define LCD_WF8B_BPDLCD12_SHIFT                  3
+#define LCD_WF8B_BPDLCD39_MASK                   0x8u
+#define LCD_WF8B_BPDLCD39_SHIFT                  3
+#define LCD_WF8B_BPDLCD3_MASK                    0x8u
+#define LCD_WF8B_BPDLCD3_SHIFT                   3
+#define LCD_WF8B_BPDLCD11_MASK                   0x8u
+#define LCD_WF8B_BPDLCD11_SHIFT                  3
+#define LCD_WF8B_BPELCD12_MASK                   0x10u
+#define LCD_WF8B_BPELCD12_SHIFT                  4
+#define LCD_WF8B_BPELCD39_MASK                   0x10u
+#define LCD_WF8B_BPELCD39_SHIFT                  4
+#define LCD_WF8B_BPELCD3_MASK                    0x10u
+#define LCD_WF8B_BPELCD3_SHIFT                   4
+#define LCD_WF8B_BPELCD38_MASK                   0x10u
+#define LCD_WF8B_BPELCD38_SHIFT                  4
+#define LCD_WF8B_BPELCD40_MASK                   0x10u
+#define LCD_WF8B_BPELCD40_SHIFT                  4
+#define LCD_WF8B_BPELCD37_MASK                   0x10u
+#define LCD_WF8B_BPELCD37_SHIFT                  4
+#define LCD_WF8B_BPELCD41_MASK                   0x10u
+#define LCD_WF8B_BPELCD41_SHIFT                  4
+#define LCD_WF8B_BPELCD36_MASK                   0x10u
+#define LCD_WF8B_BPELCD36_SHIFT                  4
+#define LCD_WF8B_BPELCD8_MASK                    0x10u
+#define LCD_WF8B_BPELCD8_SHIFT                   4
+#define LCD_WF8B_BPELCD35_MASK                   0x10u
+#define LCD_WF8B_BPELCD35_SHIFT                  4
+#define LCD_WF8B_BPELCD42_MASK                   0x10u
+#define LCD_WF8B_BPELCD42_SHIFT                  4
+#define LCD_WF8B_BPELCD34_MASK                   0x10u
+#define LCD_WF8B_BPELCD34_SHIFT                  4
+#define LCD_WF8B_BPELCD33_MASK                   0x10u
+#define LCD_WF8B_BPELCD33_SHIFT                  4
+#define LCD_WF8B_BPELCD11_MASK                   0x10u
+#define LCD_WF8B_BPELCD11_SHIFT                  4
+#define LCD_WF8B_BPELCD43_MASK                   0x10u
+#define LCD_WF8B_BPELCD43_SHIFT                  4
+#define LCD_WF8B_BPELCD32_MASK                   0x10u
+#define LCD_WF8B_BPELCD32_SHIFT                  4
+#define LCD_WF8B_BPELCD31_MASK                   0x10u
+#define LCD_WF8B_BPELCD31_SHIFT                  4
+#define LCD_WF8B_BPELCD44_MASK                   0x10u
+#define LCD_WF8B_BPELCD44_SHIFT                  4
+#define LCD_WF8B_BPELCD30_MASK                   0x10u
+#define LCD_WF8B_BPELCD30_SHIFT                  4
+#define LCD_WF8B_BPELCD29_MASK                   0x10u
+#define LCD_WF8B_BPELCD29_SHIFT                  4
+#define LCD_WF8B_BPELCD7_MASK                    0x10u
+#define LCD_WF8B_BPELCD7_SHIFT                   4
+#define LCD_WF8B_BPELCD45_MASK                   0x10u
+#define LCD_WF8B_BPELCD45_SHIFT                  4
+#define LCD_WF8B_BPELCD28_MASK                   0x10u
+#define LCD_WF8B_BPELCD28_SHIFT                  4
+#define LCD_WF8B_BPELCD2_MASK                    0x10u
+#define LCD_WF8B_BPELCD2_SHIFT                   4
+#define LCD_WF8B_BPELCD27_MASK                   0x10u
+#define LCD_WF8B_BPELCD27_SHIFT                  4
+#define LCD_WF8B_BPELCD46_MASK                   0x10u
+#define LCD_WF8B_BPELCD46_SHIFT                  4
+#define LCD_WF8B_BPELCD26_MASK                   0x10u
+#define LCD_WF8B_BPELCD26_SHIFT                  4
+#define LCD_WF8B_BPELCD10_MASK                   0x10u
+#define LCD_WF8B_BPELCD10_SHIFT                  4
+#define LCD_WF8B_BPELCD13_MASK                   0x10u
+#define LCD_WF8B_BPELCD13_SHIFT                  4
+#define LCD_WF8B_BPELCD25_MASK                   0x10u
+#define LCD_WF8B_BPELCD25_SHIFT                  4
+#define LCD_WF8B_BPELCD5_MASK                    0x10u
+#define LCD_WF8B_BPELCD5_SHIFT                   4
+#define LCD_WF8B_BPELCD24_MASK                   0x10u
+#define LCD_WF8B_BPELCD24_SHIFT                  4
+#define LCD_WF8B_BPELCD47_MASK                   0x10u
+#define LCD_WF8B_BPELCD47_SHIFT                  4
+#define LCD_WF8B_BPELCD23_MASK                   0x10u
+#define LCD_WF8B_BPELCD23_SHIFT                  4
+#define LCD_WF8B_BPELCD22_MASK                   0x10u
+#define LCD_WF8B_BPELCD22_SHIFT                  4
+#define LCD_WF8B_BPELCD48_MASK                   0x10u
+#define LCD_WF8B_BPELCD48_SHIFT                  4
+#define LCD_WF8B_BPELCD21_MASK                   0x10u
+#define LCD_WF8B_BPELCD21_SHIFT                  4
+#define LCD_WF8B_BPELCD49_MASK                   0x10u
+#define LCD_WF8B_BPELCD49_SHIFT                  4
+#define LCD_WF8B_BPELCD20_MASK                   0x10u
+#define LCD_WF8B_BPELCD20_SHIFT                  4
+#define LCD_WF8B_BPELCD19_MASK                   0x10u
+#define LCD_WF8B_BPELCD19_SHIFT                  4
+#define LCD_WF8B_BPELCD9_MASK                    0x10u
+#define LCD_WF8B_BPELCD9_SHIFT                   4
+#define LCD_WF8B_BPELCD50_MASK                   0x10u
+#define LCD_WF8B_BPELCD50_SHIFT                  4
+#define LCD_WF8B_BPELCD18_MASK                   0x10u
+#define LCD_WF8B_BPELCD18_SHIFT                  4
+#define LCD_WF8B_BPELCD6_MASK                    0x10u
+#define LCD_WF8B_BPELCD6_SHIFT                   4
+#define LCD_WF8B_BPELCD17_MASK                   0x10u
+#define LCD_WF8B_BPELCD17_SHIFT                  4
+#define LCD_WF8B_BPELCD51_MASK                   0x10u
+#define LCD_WF8B_BPELCD51_SHIFT                  4
+#define LCD_WF8B_BPELCD16_MASK                   0x10u
+#define LCD_WF8B_BPELCD16_SHIFT                  4
+#define LCD_WF8B_BPELCD56_MASK                   0x10u
+#define LCD_WF8B_BPELCD56_SHIFT                  4
+#define LCD_WF8B_BPELCD57_MASK                   0x10u
+#define LCD_WF8B_BPELCD57_SHIFT                  4
+#define LCD_WF8B_BPELCD52_MASK                   0x10u
+#define LCD_WF8B_BPELCD52_SHIFT                  4
+#define LCD_WF8B_BPELCD1_MASK                    0x10u
+#define LCD_WF8B_BPELCD1_SHIFT                   4
+#define LCD_WF8B_BPELCD58_MASK                   0x10u
+#define LCD_WF8B_BPELCD58_SHIFT                  4
+#define LCD_WF8B_BPELCD59_MASK                   0x10u
+#define LCD_WF8B_BPELCD59_SHIFT                  4
+#define LCD_WF8B_BPELCD53_MASK                   0x10u
+#define LCD_WF8B_BPELCD53_SHIFT                  4
+#define LCD_WF8B_BPELCD14_MASK                   0x10u
+#define LCD_WF8B_BPELCD14_SHIFT                  4
+#define LCD_WF8B_BPELCD0_MASK                    0x10u
+#define LCD_WF8B_BPELCD0_SHIFT                   4
+#define LCD_WF8B_BPELCD60_MASK                   0x10u
+#define LCD_WF8B_BPELCD60_SHIFT                  4
+#define LCD_WF8B_BPELCD15_MASK                   0x10u
+#define LCD_WF8B_BPELCD15_SHIFT                  4
+#define LCD_WF8B_BPELCD61_MASK                   0x10u
+#define LCD_WF8B_BPELCD61_SHIFT                  4
+#define LCD_WF8B_BPELCD54_MASK                   0x10u
+#define LCD_WF8B_BPELCD54_SHIFT                  4
+#define LCD_WF8B_BPELCD62_MASK                   0x10u
+#define LCD_WF8B_BPELCD62_SHIFT                  4
+#define LCD_WF8B_BPELCD63_MASK                   0x10u
+#define LCD_WF8B_BPELCD63_SHIFT                  4
+#define LCD_WF8B_BPELCD55_MASK                   0x10u
+#define LCD_WF8B_BPELCD55_SHIFT                  4
+#define LCD_WF8B_BPELCD4_MASK                    0x10u
+#define LCD_WF8B_BPELCD4_SHIFT                   4
+#define LCD_WF8B_BPFLCD13_MASK                   0x20u
+#define LCD_WF8B_BPFLCD13_SHIFT                  5
+#define LCD_WF8B_BPFLCD39_MASK                   0x20u
+#define LCD_WF8B_BPFLCD39_SHIFT                  5
+#define LCD_WF8B_BPFLCD55_MASK                   0x20u
+#define LCD_WF8B_BPFLCD55_SHIFT                  5
+#define LCD_WF8B_BPFLCD47_MASK                   0x20u
+#define LCD_WF8B_BPFLCD47_SHIFT                  5
+#define LCD_WF8B_BPFLCD63_MASK                   0x20u
+#define LCD_WF8B_BPFLCD63_SHIFT                  5
+#define LCD_WF8B_BPFLCD43_MASK                   0x20u
+#define LCD_WF8B_BPFLCD43_SHIFT                  5
+#define LCD_WF8B_BPFLCD5_MASK                    0x20u
+#define LCD_WF8B_BPFLCD5_SHIFT                   5
+#define LCD_WF8B_BPFLCD62_MASK                   0x20u
+#define LCD_WF8B_BPFLCD62_SHIFT                  5
+#define LCD_WF8B_BPFLCD14_MASK                   0x20u
+#define LCD_WF8B_BPFLCD14_SHIFT                  5
+#define LCD_WF8B_BPFLCD24_MASK                   0x20u
+#define LCD_WF8B_BPFLCD24_SHIFT                  5
+#define LCD_WF8B_BPFLCD54_MASK                   0x20u
+#define LCD_WF8B_BPFLCD54_SHIFT                  5
+#define LCD_WF8B_BPFLCD15_MASK                   0x20u
+#define LCD_WF8B_BPFLCD15_SHIFT                  5
+#define LCD_WF8B_BPFLCD32_MASK                   0x20u
+#define LCD_WF8B_BPFLCD32_SHIFT                  5
+#define LCD_WF8B_BPFLCD61_MASK                   0x20u
+#define LCD_WF8B_BPFLCD61_SHIFT                  5
+#define LCD_WF8B_BPFLCD25_MASK                   0x20u
+#define LCD_WF8B_BPFLCD25_SHIFT                  5
+#define LCD_WF8B_BPFLCD60_MASK                   0x20u
+#define LCD_WF8B_BPFLCD60_SHIFT                  5
+#define LCD_WF8B_BPFLCD41_MASK                   0x20u
+#define LCD_WF8B_BPFLCD41_SHIFT                  5
+#define LCD_WF8B_BPFLCD33_MASK                   0x20u
+#define LCD_WF8B_BPFLCD33_SHIFT                  5
+#define LCD_WF8B_BPFLCD53_MASK                   0x20u
+#define LCD_WF8B_BPFLCD53_SHIFT                  5
+#define LCD_WF8B_BPFLCD59_MASK                   0x20u
+#define LCD_WF8B_BPFLCD59_SHIFT                  5
+#define LCD_WF8B_BPFLCD0_MASK                    0x20u
+#define LCD_WF8B_BPFLCD0_SHIFT                   5
+#define LCD_WF8B_BPFLCD46_MASK                   0x20u
+#define LCD_WF8B_BPFLCD46_SHIFT                  5
+#define LCD_WF8B_BPFLCD58_MASK                   0x20u
+#define LCD_WF8B_BPFLCD58_SHIFT                  5
+#define LCD_WF8B_BPFLCD26_MASK                   0x20u
+#define LCD_WF8B_BPFLCD26_SHIFT                  5
+#define LCD_WF8B_BPFLCD36_MASK                   0x20u
+#define LCD_WF8B_BPFLCD36_SHIFT                  5
+#define LCD_WF8B_BPFLCD10_MASK                   0x20u
+#define LCD_WF8B_BPFLCD10_SHIFT                  5
+#define LCD_WF8B_BPFLCD52_MASK                   0x20u
+#define LCD_WF8B_BPFLCD52_SHIFT                  5
+#define LCD_WF8B_BPFLCD57_MASK                   0x20u
+#define LCD_WF8B_BPFLCD57_SHIFT                  5
+#define LCD_WF8B_BPFLCD27_MASK                   0x20u
+#define LCD_WF8B_BPFLCD27_SHIFT                  5
+#define LCD_WF8B_BPFLCD11_MASK                   0x20u
+#define LCD_WF8B_BPFLCD11_SHIFT                  5
+#define LCD_WF8B_BPFLCD56_MASK                   0x20u
+#define LCD_WF8B_BPFLCD56_SHIFT                  5
+#define LCD_WF8B_BPFLCD1_MASK                    0x20u
+#define LCD_WF8B_BPFLCD1_SHIFT                   5
+#define LCD_WF8B_BPFLCD8_MASK                    0x20u
+#define LCD_WF8B_BPFLCD8_SHIFT                   5
+#define LCD_WF8B_BPFLCD40_MASK                   0x20u
+#define LCD_WF8B_BPFLCD40_SHIFT                  5
+#define LCD_WF8B_BPFLCD51_MASK                   0x20u
+#define LCD_WF8B_BPFLCD51_SHIFT                  5
+#define LCD_WF8B_BPFLCD16_MASK                   0x20u
+#define LCD_WF8B_BPFLCD16_SHIFT                  5
+#define LCD_WF8B_BPFLCD45_MASK                   0x20u
+#define LCD_WF8B_BPFLCD45_SHIFT                  5
+#define LCD_WF8B_BPFLCD6_MASK                    0x20u
+#define LCD_WF8B_BPFLCD6_SHIFT                   5
+#define LCD_WF8B_BPFLCD17_MASK                   0x20u
+#define LCD_WF8B_BPFLCD17_SHIFT                  5
+#define LCD_WF8B_BPFLCD28_MASK                   0x20u
+#define LCD_WF8B_BPFLCD28_SHIFT                  5
+#define LCD_WF8B_BPFLCD42_MASK                   0x20u
+#define LCD_WF8B_BPFLCD42_SHIFT                  5
+#define LCD_WF8B_BPFLCD29_MASK                   0x20u
+#define LCD_WF8B_BPFLCD29_SHIFT                  5
+#define LCD_WF8B_BPFLCD50_MASK                   0x20u
+#define LCD_WF8B_BPFLCD50_SHIFT                  5
+#define LCD_WF8B_BPFLCD18_MASK                   0x20u
+#define LCD_WF8B_BPFLCD18_SHIFT                  5
+#define LCD_WF8B_BPFLCD34_MASK                   0x20u
+#define LCD_WF8B_BPFLCD34_SHIFT                  5
+#define LCD_WF8B_BPFLCD19_MASK                   0x20u
+#define LCD_WF8B_BPFLCD19_SHIFT                  5
+#define LCD_WF8B_BPFLCD2_MASK                    0x20u
+#define LCD_WF8B_BPFLCD2_SHIFT                   5
+#define LCD_WF8B_BPFLCD9_MASK                    0x20u
+#define LCD_WF8B_BPFLCD9_SHIFT                   5
+#define LCD_WF8B_BPFLCD3_MASK                    0x20u
+#define LCD_WF8B_BPFLCD3_SHIFT                   5
+#define LCD_WF8B_BPFLCD37_MASK                   0x20u
+#define LCD_WF8B_BPFLCD37_SHIFT                  5
+#define LCD_WF8B_BPFLCD49_MASK                   0x20u
+#define LCD_WF8B_BPFLCD49_SHIFT                  5
+#define LCD_WF8B_BPFLCD20_MASK                   0x20u
+#define LCD_WF8B_BPFLCD20_SHIFT                  5
+#define LCD_WF8B_BPFLCD44_MASK                   0x20u
+#define LCD_WF8B_BPFLCD44_SHIFT                  5
+#define LCD_WF8B_BPFLCD30_MASK                   0x20u
+#define LCD_WF8B_BPFLCD30_SHIFT                  5
+#define LCD_WF8B_BPFLCD21_MASK                   0x20u
+#define LCD_WF8B_BPFLCD21_SHIFT                  5
+#define LCD_WF8B_BPFLCD35_MASK                   0x20u
+#define LCD_WF8B_BPFLCD35_SHIFT                  5
+#define LCD_WF8B_BPFLCD4_MASK                    0x20u
+#define LCD_WF8B_BPFLCD4_SHIFT                   5
+#define LCD_WF8B_BPFLCD31_MASK                   0x20u
+#define LCD_WF8B_BPFLCD31_SHIFT                  5
+#define LCD_WF8B_BPFLCD48_MASK                   0x20u
+#define LCD_WF8B_BPFLCD48_SHIFT                  5
+#define LCD_WF8B_BPFLCD7_MASK                    0x20u
+#define LCD_WF8B_BPFLCD7_SHIFT                   5
+#define LCD_WF8B_BPFLCD22_MASK                   0x20u
+#define LCD_WF8B_BPFLCD22_SHIFT                  5
+#define LCD_WF8B_BPFLCD38_MASK                   0x20u
+#define LCD_WF8B_BPFLCD38_SHIFT                  5
+#define LCD_WF8B_BPFLCD12_MASK                   0x20u
+#define LCD_WF8B_BPFLCD12_SHIFT                  5
+#define LCD_WF8B_BPFLCD23_MASK                   0x20u
+#define LCD_WF8B_BPFLCD23_SHIFT                  5
+#define LCD_WF8B_BPGLCD14_MASK                   0x40u
+#define LCD_WF8B_BPGLCD14_SHIFT                  6
+#define LCD_WF8B_BPGLCD55_MASK                   0x40u
+#define LCD_WF8B_BPGLCD55_SHIFT                  6
+#define LCD_WF8B_BPGLCD63_MASK                   0x40u
+#define LCD_WF8B_BPGLCD63_SHIFT                  6
+#define LCD_WF8B_BPGLCD15_MASK                   0x40u
+#define LCD_WF8B_BPGLCD15_SHIFT                  6
+#define LCD_WF8B_BPGLCD62_MASK                   0x40u
+#define LCD_WF8B_BPGLCD62_SHIFT                  6
+#define LCD_WF8B_BPGLCD54_MASK                   0x40u
+#define LCD_WF8B_BPGLCD54_SHIFT                  6
+#define LCD_WF8B_BPGLCD61_MASK                   0x40u
+#define LCD_WF8B_BPGLCD61_SHIFT                  6
+#define LCD_WF8B_BPGLCD60_MASK                   0x40u
+#define LCD_WF8B_BPGLCD60_SHIFT                  6
+#define LCD_WF8B_BPGLCD59_MASK                   0x40u
+#define LCD_WF8B_BPGLCD59_SHIFT                  6
+#define LCD_WF8B_BPGLCD53_MASK                   0x40u
+#define LCD_WF8B_BPGLCD53_SHIFT                  6
+#define LCD_WF8B_BPGLCD58_MASK                   0x40u
+#define LCD_WF8B_BPGLCD58_SHIFT                  6
+#define LCD_WF8B_BPGLCD0_MASK                    0x40u
+#define LCD_WF8B_BPGLCD0_SHIFT                   6
+#define LCD_WF8B_BPGLCD57_MASK                   0x40u
+#define LCD_WF8B_BPGLCD57_SHIFT                  6
+#define LCD_WF8B_BPGLCD52_MASK                   0x40u
+#define LCD_WF8B_BPGLCD52_SHIFT                  6
+#define LCD_WF8B_BPGLCD7_MASK                    0x40u
+#define LCD_WF8B_BPGLCD7_SHIFT                   6
+#define LCD_WF8B_BPGLCD56_MASK                   0x40u
+#define LCD_WF8B_BPGLCD56_SHIFT                  6
+#define LCD_WF8B_BPGLCD6_MASK                    0x40u
+#define LCD_WF8B_BPGLCD6_SHIFT                   6
+#define LCD_WF8B_BPGLCD51_MASK                   0x40u
+#define LCD_WF8B_BPGLCD51_SHIFT                  6
+#define LCD_WF8B_BPGLCD16_MASK                   0x40u
+#define LCD_WF8B_BPGLCD16_SHIFT                  6
+#define LCD_WF8B_BPGLCD1_MASK                    0x40u
+#define LCD_WF8B_BPGLCD1_SHIFT                   6
+#define LCD_WF8B_BPGLCD17_MASK                   0x40u
+#define LCD_WF8B_BPGLCD17_SHIFT                  6
+#define LCD_WF8B_BPGLCD50_MASK                   0x40u
+#define LCD_WF8B_BPGLCD50_SHIFT                  6
+#define LCD_WF8B_BPGLCD18_MASK                   0x40u
+#define LCD_WF8B_BPGLCD18_SHIFT                  6
+#define LCD_WF8B_BPGLCD19_MASK                   0x40u
+#define LCD_WF8B_BPGLCD19_SHIFT                  6
+#define LCD_WF8B_BPGLCD8_MASK                    0x40u
+#define LCD_WF8B_BPGLCD8_SHIFT                   6
+#define LCD_WF8B_BPGLCD49_MASK                   0x40u
+#define LCD_WF8B_BPGLCD49_SHIFT                  6
+#define LCD_WF8B_BPGLCD20_MASK                   0x40u
+#define LCD_WF8B_BPGLCD20_SHIFT                  6
+#define LCD_WF8B_BPGLCD9_MASK                    0x40u
+#define LCD_WF8B_BPGLCD9_SHIFT                   6
+#define LCD_WF8B_BPGLCD21_MASK                   0x40u
+#define LCD_WF8B_BPGLCD21_SHIFT                  6
+#define LCD_WF8B_BPGLCD13_MASK                   0x40u
+#define LCD_WF8B_BPGLCD13_SHIFT                  6
+#define LCD_WF8B_BPGLCD48_MASK                   0x40u
+#define LCD_WF8B_BPGLCD48_SHIFT                  6
+#define LCD_WF8B_BPGLCD22_MASK                   0x40u
+#define LCD_WF8B_BPGLCD22_SHIFT                  6
+#define LCD_WF8B_BPGLCD5_MASK                    0x40u
+#define LCD_WF8B_BPGLCD5_SHIFT                   6
+#define LCD_WF8B_BPGLCD47_MASK                   0x40u
+#define LCD_WF8B_BPGLCD47_SHIFT                  6
+#define LCD_WF8B_BPGLCD23_MASK                   0x40u
+#define LCD_WF8B_BPGLCD23_SHIFT                  6
+#define LCD_WF8B_BPGLCD24_MASK                   0x40u
+#define LCD_WF8B_BPGLCD24_SHIFT                  6
+#define LCD_WF8B_BPGLCD25_MASK                   0x40u
+#define LCD_WF8B_BPGLCD25_SHIFT                  6
+#define LCD_WF8B_BPGLCD46_MASK                   0x40u
+#define LCD_WF8B_BPGLCD46_SHIFT                  6
+#define LCD_WF8B_BPGLCD26_MASK                   0x40u
+#define LCD_WF8B_BPGLCD26_SHIFT                  6
+#define LCD_WF8B_BPGLCD27_MASK                   0x40u
+#define LCD_WF8B_BPGLCD27_SHIFT                  6
+#define LCD_WF8B_BPGLCD10_MASK                   0x40u
+#define LCD_WF8B_BPGLCD10_SHIFT                  6
+#define LCD_WF8B_BPGLCD45_MASK                   0x40u
+#define LCD_WF8B_BPGLCD45_SHIFT                  6
+#define LCD_WF8B_BPGLCD28_MASK                   0x40u
+#define LCD_WF8B_BPGLCD28_SHIFT                  6
+#define LCD_WF8B_BPGLCD29_MASK                   0x40u
+#define LCD_WF8B_BPGLCD29_SHIFT                  6
+#define LCD_WF8B_BPGLCD4_MASK                    0x40u
+#define LCD_WF8B_BPGLCD4_SHIFT                   6
+#define LCD_WF8B_BPGLCD44_MASK                   0x40u
+#define LCD_WF8B_BPGLCD44_SHIFT                  6
+#define LCD_WF8B_BPGLCD30_MASK                   0x40u
+#define LCD_WF8B_BPGLCD30_SHIFT                  6
+#define LCD_WF8B_BPGLCD2_MASK                    0x40u
+#define LCD_WF8B_BPGLCD2_SHIFT                   6
+#define LCD_WF8B_BPGLCD31_MASK                   0x40u
+#define LCD_WF8B_BPGLCD31_SHIFT                  6
+#define LCD_WF8B_BPGLCD43_MASK                   0x40u
+#define LCD_WF8B_BPGLCD43_SHIFT                  6
+#define LCD_WF8B_BPGLCD32_MASK                   0x40u
+#define LCD_WF8B_BPGLCD32_SHIFT                  6
+#define LCD_WF8B_BPGLCD33_MASK                   0x40u
+#define LCD_WF8B_BPGLCD33_SHIFT                  6
+#define LCD_WF8B_BPGLCD42_MASK                   0x40u
+#define LCD_WF8B_BPGLCD42_SHIFT                  6
+#define LCD_WF8B_BPGLCD34_MASK                   0x40u
+#define LCD_WF8B_BPGLCD34_SHIFT                  6
+#define LCD_WF8B_BPGLCD11_MASK                   0x40u
+#define LCD_WF8B_BPGLCD11_SHIFT                  6
+#define LCD_WF8B_BPGLCD35_MASK                   0x40u
+#define LCD_WF8B_BPGLCD35_SHIFT                  6
+#define LCD_WF8B_BPGLCD12_MASK                   0x40u
+#define LCD_WF8B_BPGLCD12_SHIFT                  6
+#define LCD_WF8B_BPGLCD41_MASK                   0x40u
+#define LCD_WF8B_BPGLCD41_SHIFT                  6
+#define LCD_WF8B_BPGLCD36_MASK                   0x40u
+#define LCD_WF8B_BPGLCD36_SHIFT                  6
+#define LCD_WF8B_BPGLCD3_MASK                    0x40u
+#define LCD_WF8B_BPGLCD3_SHIFT                   6
+#define LCD_WF8B_BPGLCD37_MASK                   0x40u
+#define LCD_WF8B_BPGLCD37_SHIFT                  6
+#define LCD_WF8B_BPGLCD40_MASK                   0x40u
+#define LCD_WF8B_BPGLCD40_SHIFT                  6
+#define LCD_WF8B_BPGLCD38_MASK                   0x40u
+#define LCD_WF8B_BPGLCD38_SHIFT                  6
+#define LCD_WF8B_BPGLCD39_MASK                   0x40u
+#define LCD_WF8B_BPGLCD39_SHIFT                  6
+#define LCD_WF8B_BPHLCD63_MASK                   0x80u
+#define LCD_WF8B_BPHLCD63_SHIFT                  7
+#define LCD_WF8B_BPHLCD62_MASK                   0x80u
+#define LCD_WF8B_BPHLCD62_SHIFT                  7
+#define LCD_WF8B_BPHLCD61_MASK                   0x80u
+#define LCD_WF8B_BPHLCD61_SHIFT                  7
+#define LCD_WF8B_BPHLCD60_MASK                   0x80u
+#define LCD_WF8B_BPHLCD60_SHIFT                  7
+#define LCD_WF8B_BPHLCD59_MASK                   0x80u
+#define LCD_WF8B_BPHLCD59_SHIFT                  7
+#define LCD_WF8B_BPHLCD58_MASK                   0x80u
+#define LCD_WF8B_BPHLCD58_SHIFT                  7
+#define LCD_WF8B_BPHLCD57_MASK                   0x80u
+#define LCD_WF8B_BPHLCD57_SHIFT                  7
+#define LCD_WF8B_BPHLCD0_MASK                    0x80u
+#define LCD_WF8B_BPHLCD0_SHIFT                   7
+#define LCD_WF8B_BPHLCD56_MASK                   0x80u
+#define LCD_WF8B_BPHLCD56_SHIFT                  7
+#define LCD_WF8B_BPHLCD55_MASK                   0x80u
+#define LCD_WF8B_BPHLCD55_SHIFT                  7
+#define LCD_WF8B_BPHLCD54_MASK                   0x80u
+#define LCD_WF8B_BPHLCD54_SHIFT                  7
+#define LCD_WF8B_BPHLCD53_MASK                   0x80u
+#define LCD_WF8B_BPHLCD53_SHIFT                  7
+#define LCD_WF8B_BPHLCD52_MASK                   0x80u
+#define LCD_WF8B_BPHLCD52_SHIFT                  7
+#define LCD_WF8B_BPHLCD51_MASK                   0x80u
+#define LCD_WF8B_BPHLCD51_SHIFT                  7
+#define LCD_WF8B_BPHLCD50_MASK                   0x80u
+#define LCD_WF8B_BPHLCD50_SHIFT                  7
+#define LCD_WF8B_BPHLCD1_MASK                    0x80u
+#define LCD_WF8B_BPHLCD1_SHIFT                   7
+#define LCD_WF8B_BPHLCD49_MASK                   0x80u
+#define LCD_WF8B_BPHLCD49_SHIFT                  7
+#define LCD_WF8B_BPHLCD48_MASK                   0x80u
+#define LCD_WF8B_BPHLCD48_SHIFT                  7
+#define LCD_WF8B_BPHLCD47_MASK                   0x80u
+#define LCD_WF8B_BPHLCD47_SHIFT                  7
+#define LCD_WF8B_BPHLCD46_MASK                   0x80u
+#define LCD_WF8B_BPHLCD46_SHIFT                  7
+#define LCD_WF8B_BPHLCD45_MASK                   0x80u
+#define LCD_WF8B_BPHLCD45_SHIFT                  7
+#define LCD_WF8B_BPHLCD44_MASK                   0x80u
+#define LCD_WF8B_BPHLCD44_SHIFT                  7
+#define LCD_WF8B_BPHLCD43_MASK                   0x80u
+#define LCD_WF8B_BPHLCD43_SHIFT                  7
+#define LCD_WF8B_BPHLCD2_MASK                    0x80u
+#define LCD_WF8B_BPHLCD2_SHIFT                   7
+#define LCD_WF8B_BPHLCD42_MASK                   0x80u
+#define LCD_WF8B_BPHLCD42_SHIFT                  7
+#define LCD_WF8B_BPHLCD41_MASK                   0x80u
+#define LCD_WF8B_BPHLCD41_SHIFT                  7
+#define LCD_WF8B_BPHLCD40_MASK                   0x80u
+#define LCD_WF8B_BPHLCD40_SHIFT                  7
+#define LCD_WF8B_BPHLCD39_MASK                   0x80u
+#define LCD_WF8B_BPHLCD39_SHIFT                  7
+#define LCD_WF8B_BPHLCD38_MASK                   0x80u
+#define LCD_WF8B_BPHLCD38_SHIFT                  7
+#define LCD_WF8B_BPHLCD37_MASK                   0x80u
+#define LCD_WF8B_BPHLCD37_SHIFT                  7
+#define LCD_WF8B_BPHLCD36_MASK                   0x80u
+#define LCD_WF8B_BPHLCD36_SHIFT                  7
+#define LCD_WF8B_BPHLCD3_MASK                    0x80u
+#define LCD_WF8B_BPHLCD3_SHIFT                   7
+#define LCD_WF8B_BPHLCD35_MASK                   0x80u
+#define LCD_WF8B_BPHLCD35_SHIFT                  7
+#define LCD_WF8B_BPHLCD34_MASK                   0x80u
+#define LCD_WF8B_BPHLCD34_SHIFT                  7
+#define LCD_WF8B_BPHLCD33_MASK                   0x80u
+#define LCD_WF8B_BPHLCD33_SHIFT                  7
+#define LCD_WF8B_BPHLCD32_MASK                   0x80u
+#define LCD_WF8B_BPHLCD32_SHIFT                  7
+#define LCD_WF8B_BPHLCD31_MASK                   0x80u
+#define LCD_WF8B_BPHLCD31_SHIFT                  7
+#define LCD_WF8B_BPHLCD30_MASK                   0x80u
+#define LCD_WF8B_BPHLCD30_SHIFT                  7
+#define LCD_WF8B_BPHLCD29_MASK                   0x80u
+#define LCD_WF8B_BPHLCD29_SHIFT                  7
+#define LCD_WF8B_BPHLCD4_MASK                    0x80u
+#define LCD_WF8B_BPHLCD4_SHIFT                   7
+#define LCD_WF8B_BPHLCD28_MASK                   0x80u
+#define LCD_WF8B_BPHLCD28_SHIFT                  7
+#define LCD_WF8B_BPHLCD27_MASK                   0x80u
+#define LCD_WF8B_BPHLCD27_SHIFT                  7
+#define LCD_WF8B_BPHLCD26_MASK                   0x80u
+#define LCD_WF8B_BPHLCD26_SHIFT                  7
+#define LCD_WF8B_BPHLCD25_MASK                   0x80u
+#define LCD_WF8B_BPHLCD25_SHIFT                  7
+#define LCD_WF8B_BPHLCD24_MASK                   0x80u
+#define LCD_WF8B_BPHLCD24_SHIFT                  7
+#define LCD_WF8B_BPHLCD23_MASK                   0x80u
+#define LCD_WF8B_BPHLCD23_SHIFT                  7
+#define LCD_WF8B_BPHLCD22_MASK                   0x80u
+#define LCD_WF8B_BPHLCD22_SHIFT                  7
+#define LCD_WF8B_BPHLCD5_MASK                    0x80u
+#define LCD_WF8B_BPHLCD5_SHIFT                   7
+#define LCD_WF8B_BPHLCD21_MASK                   0x80u
+#define LCD_WF8B_BPHLCD21_SHIFT                  7
+#define LCD_WF8B_BPHLCD20_MASK                   0x80u
+#define LCD_WF8B_BPHLCD20_SHIFT                  7
+#define LCD_WF8B_BPHLCD19_MASK                   0x80u
+#define LCD_WF8B_BPHLCD19_SHIFT                  7
+#define LCD_WF8B_BPHLCD18_MASK                   0x80u
+#define LCD_WF8B_BPHLCD18_SHIFT                  7
+#define LCD_WF8B_BPHLCD17_MASK                   0x80u
+#define LCD_WF8B_BPHLCD17_SHIFT                  7
+#define LCD_WF8B_BPHLCD16_MASK                   0x80u
+#define LCD_WF8B_BPHLCD16_SHIFT                  7
+#define LCD_WF8B_BPHLCD15_MASK                   0x80u
+#define LCD_WF8B_BPHLCD15_SHIFT                  7
+#define LCD_WF8B_BPHLCD6_MASK                    0x80u
+#define LCD_WF8B_BPHLCD6_SHIFT                   7
+#define LCD_WF8B_BPHLCD14_MASK                   0x80u
+#define LCD_WF8B_BPHLCD14_SHIFT                  7
+#define LCD_WF8B_BPHLCD13_MASK                   0x80u
+#define LCD_WF8B_BPHLCD13_SHIFT                  7
+#define LCD_WF8B_BPHLCD12_MASK                   0x80u
+#define LCD_WF8B_BPHLCD12_SHIFT                  7
+#define LCD_WF8B_BPHLCD11_MASK                   0x80u
+#define LCD_WF8B_BPHLCD11_SHIFT                  7
+#define LCD_WF8B_BPHLCD10_MASK                   0x80u
+#define LCD_WF8B_BPHLCD10_SHIFT                  7
+#define LCD_WF8B_BPHLCD9_MASK                    0x80u
+#define LCD_WF8B_BPHLCD9_SHIFT                   7
+#define LCD_WF8B_BPHLCD8_MASK                    0x80u
+#define LCD_WF8B_BPHLCD8_SHIFT                   7
+#define LCD_WF8B_BPHLCD7_MASK                    0x80u
+#define LCD_WF8B_BPHLCD7_SHIFT                   7
+
+/*! \} */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/*! Peripheral LCD base address */
+#define LCD_BASE                                 (0x400BE000u)
+/*! Peripheral LCD base pointer */
+#define LCD                                      ((LCD_Type *)LCD_BASE)
+
+/*! \} */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer */
+/*! \{ */
+
+/*! LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /*!< LLWU Pin Enable 1 Register, offset: 0x0 */
+  __IO uint8_t PE2;                                /*!< LLWU Pin Enable 2 Register, offset: 0x1 */
+  __IO uint8_t PE3;                                /*!< LLWU Pin Enable 3 Register, offset: 0x2 */
+  __IO uint8_t PE4;                                /*!< LLWU Pin Enable 4 Register, offset: 0x3 */
+  __IO uint8_t ME;                                 /*!< LLWU Module Enable Register, offset: 0x4 */
+  __IO uint8_t F1;                                 /*!< LLWU Flag 1 Register, offset: 0x5 */
+  __IO uint8_t F2;                                 /*!< LLWU Flag 2 Register, offset: 0x6 */
+  __IO uint8_t F3;                                 /*!< LLWU Flag 3 Register, offset: 0x7 */
+  __IO uint8_t CS;                                 /*!< LLWU Control and Status Register, offset: 0x8 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup LLWU_Register_Masks LLWU Register Masks */
+/*! \{ */
+
+/* PE1 Bit Fields */
+#define LLWU_PE1_WUPE0_MASK                      0x3u
+#define LLWU_PE1_WUPE0_SHIFT                     0
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      0xCu
+#define LLWU_PE1_WUPE1_SHIFT                     2
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      0x30u
+#define LLWU_PE1_WUPE2_SHIFT                     4
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      0xC0u
+#define LLWU_PE1_WUPE3_SHIFT                     6
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
+/* PE2 Bit Fields */
+#define LLWU_PE2_WUPE4_MASK                      0x3u
+#define LLWU_PE2_WUPE4_SHIFT                     0
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      0xCu
+#define LLWU_PE2_WUPE5_SHIFT                     2
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      0x30u
+#define LLWU_PE2_WUPE6_SHIFT                     4
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      0xC0u
+#define LLWU_PE2_WUPE7_SHIFT                     6
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
+/* PE3 Bit Fields */
+#define LLWU_PE3_WUPE8_MASK                      0x3u
+#define LLWU_PE3_WUPE8_SHIFT                     0
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      0xCu
+#define LLWU_PE3_WUPE9_SHIFT                     2
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     0x30u
+#define LLWU_PE3_WUPE10_SHIFT                    4
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     0xC0u
+#define LLWU_PE3_WUPE11_SHIFT                    6
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
+/* PE4 Bit Fields */
+#define LLWU_PE4_WUPE12_MASK                     0x3u
+#define LLWU_PE4_WUPE12_SHIFT                    0
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     0xCu
+#define LLWU_PE4_WUPE13_SHIFT                    2
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     0x30u
+#define LLWU_PE4_WUPE14_SHIFT                    4
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     0xC0u
+#define LLWU_PE4_WUPE15_SHIFT                    6
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
+/* ME Bit Fields */
+#define LLWU_ME_WUME0_MASK                       0x1u
+#define LLWU_ME_WUME0_SHIFT                      0
+#define LLWU_ME_WUME1_MASK                       0x2u
+#define LLWU_ME_WUME1_SHIFT                      1
+#define LLWU_ME_WUME2_MASK                       0x4u
+#define LLWU_ME_WUME2_SHIFT                      2
+#define LLWU_ME_WUME3_MASK                       0x8u
+#define LLWU_ME_WUME3_SHIFT                      3
+#define LLWU_ME_WUME4_MASK                       0x10u
+#define LLWU_ME_WUME4_SHIFT                      4
+#define LLWU_ME_WUME5_MASK                       0x20u
+#define LLWU_ME_WUME5_SHIFT                      5
+#define LLWU_ME_WUME6_MASK                       0x40u
+#define LLWU_ME_WUME6_SHIFT                      6
+#define LLWU_ME_WUME7_MASK                       0x80u
+#define LLWU_ME_WUME7_SHIFT                      7
+/* F1 Bit Fields */
+#define LLWU_F1_WUF0_MASK                        0x1u
+#define LLWU_F1_WUF0_SHIFT                       0
+#define LLWU_F1_WUF1_MASK                        0x2u
+#define LLWU_F1_WUF1_SHIFT                       1
+#define LLWU_F1_WUF2_MASK                        0x4u
+#define LLWU_F1_WUF2_SHIFT                       2
+#define LLWU_F1_WUF3_MASK                        0x8u
+#define LLWU_F1_WUF3_SHIFT                       3
+#define LLWU_F1_WUF4_MASK                        0x10u
+#define LLWU_F1_WUF4_SHIFT                       4
+#define LLWU_F1_WUF5_MASK                        0x20u
+#define LLWU_F1_WUF5_SHIFT                       5
+#define LLWU_F1_WUF6_MASK                        0x40u
+#define LLWU_F1_WUF6_SHIFT                       6
+#define LLWU_F1_WUF7_MASK                        0x80u
+#define LLWU_F1_WUF7_SHIFT                       7
+/* F2 Bit Fields */
+#define LLWU_F2_WUF8_MASK                        0x1u
+#define LLWU_F2_WUF8_SHIFT                       0
+#define LLWU_F2_WUF9_MASK                        0x2u
+#define LLWU_F2_WUF9_SHIFT                       1
+#define LLWU_F2_WUF10_MASK                       0x4u
+#define LLWU_F2_WUF10_SHIFT                      2
+#define LLWU_F2_WUF11_MASK                       0x8u
+#define LLWU_F2_WUF11_SHIFT                      3
+#define LLWU_F2_WUF12_MASK                       0x10u
+#define LLWU_F2_WUF12_SHIFT                      4
+#define LLWU_F2_WUF13_MASK                       0x20u
+#define LLWU_F2_WUF13_SHIFT                      5
+#define LLWU_F2_WUF14_MASK                       0x40u
+#define LLWU_F2_WUF14_SHIFT                      6
+#define LLWU_F2_WUF15_MASK                       0x80u
+#define LLWU_F2_WUF15_SHIFT                      7
+/* F3 Bit Fields */
+#define LLWU_F3_MWUF0_MASK                       0x1u
+#define LLWU_F3_MWUF0_SHIFT                      0
+#define LLWU_F3_MWUF1_MASK                       0x2u
+#define LLWU_F3_MWUF1_SHIFT                      1
+#define LLWU_F3_MWUF2_MASK                       0x4u
+#define LLWU_F3_MWUF2_SHIFT                      2
+#define LLWU_F3_MWUF3_MASK                       0x8u
+#define LLWU_F3_MWUF3_SHIFT                      3
+#define LLWU_F3_MWUF4_MASK                       0x10u
+#define LLWU_F3_MWUF4_SHIFT                      4
+#define LLWU_F3_MWUF5_MASK                       0x20u
+#define LLWU_F3_MWUF5_SHIFT                      5
+#define LLWU_F3_MWUF6_MASK                       0x40u
+#define LLWU_F3_MWUF6_SHIFT                      6
+#define LLWU_F3_MWUF7_MASK                       0x80u
+#define LLWU_F3_MWUF7_SHIFT                      7
+/* CS Bit Fields */
+#define LLWU_CS_FLTR_MASK                        0x1u
+#define LLWU_CS_FLTR_SHIFT                       0
+#define LLWU_CS_FLTEP_MASK                       0x2u
+#define LLWU_CS_FLTEP_SHIFT                      1
+#define LLWU_CS_ACKISO_MASK                      0x80u
+#define LLWU_CS_ACKISO_SHIFT                     7
+
+/*! \} */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/*! Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/*! Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+
+/*! \} */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer */
+/*! \{ */
+
+/*! LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /*!< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /*!< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /*!< Low Power Timer Compare Register, offset: 0x8 */
+  __I  uint32_t CNR;                               /*!< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup LPTMR_Register_Masks LPTMR Register Masks */
+/*! \{ */
+
+/* CSR Bit Fields */
+#define LPTMR_CSR_TEN_MASK                       0x1u
+#define LPTMR_CSR_TEN_SHIFT                      0
+#define LPTMR_CSR_TMS_MASK                       0x2u
+#define LPTMR_CSR_TMS_SHIFT                      1
+#define LPTMR_CSR_TFC_MASK                       0x4u
+#define LPTMR_CSR_TFC_SHIFT                      2
+#define LPTMR_CSR_TPP_MASK                       0x8u
+#define LPTMR_CSR_TPP_SHIFT                      3
+#define LPTMR_CSR_TPS_MASK                       0x30u
+#define LPTMR_CSR_TPS_SHIFT                      4
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       0x40u
+#define LPTMR_CSR_TIE_SHIFT                      6
+#define LPTMR_CSR_TCF_MASK                       0x80u
+#define LPTMR_CSR_TCF_SHIFT                      7
+/* PSR Bit Fields */
+#define LPTMR_PSR_PCS_MASK                       0x3u
+#define LPTMR_PSR_PCS_SHIFT                      0
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      0x4u
+#define LPTMR_PSR_PBYP_SHIFT                     2
+#define LPTMR_PSR_PRESCALE_MASK                  0x78u
+#define LPTMR_PSR_PRESCALE_SHIFT                 3
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
+/* CMR Bit Fields */
+#define LPTMR_CMR_COMPARE_MASK                   0xFFFFu
+#define LPTMR_CMR_COMPARE_SHIFT                  0
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
+/* CNR Bit Fields */
+#define LPTMR_CNR_COUNTER_MASK                   0xFFFFu
+#define LPTMR_CNR_COUNTER_SHIFT                  0
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
+
+/*! \} */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/*! Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/*! Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+
+/*! \} */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MC_Peripheral_Access_Layer MC Peripheral Access Layer */
+/*! \{ */
+
+/*! MC - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRSH;                               /*!< System Reset Status Register High, offset: 0x0 */
+  __I  uint8_t SRSL;                               /*!< System Reset Status Register Low, offset: 0x1 */
+  __IO uint8_t PMPROT;                             /*!< Power Mode Protection Register, offset: 0x2 */
+  __IO uint8_t PMCTRL;                             /*!< Power Mode Control Register, offset: 0x3 */
+} MC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MC_Register_Masks MC Register Masks */
+/*! \{ */
+
+/* SRSH Bit Fields */
+#define MC_SRSH_JTAG_MASK                        0x1u
+#define MC_SRSH_JTAG_SHIFT                       0
+#define MC_SRSH_LOCKUP_MASK                      0x2u
+#define MC_SRSH_LOCKUP_SHIFT                     1
+#define MC_SRSH_SW_MASK                          0x4u
+#define MC_SRSH_SW_SHIFT                         2
+/* SRSL Bit Fields */
+#define MC_SRSL_WAKEUP_MASK                      0x1u
+#define MC_SRSL_WAKEUP_SHIFT                     0
+#define MC_SRSL_LVD_MASK                         0x2u
+#define MC_SRSL_LVD_SHIFT                        1
+#define MC_SRSL_LOC_MASK                         0x4u
+#define MC_SRSL_LOC_SHIFT                        2
+#define MC_SRSL_COP_MASK                         0x20u
+#define MC_SRSL_COP_SHIFT                        5
+#define MC_SRSL_PIN_MASK                         0x40u
+#define MC_SRSL_PIN_SHIFT                        6
+#define MC_SRSL_POR_MASK                         0x80u
+#define MC_SRSL_POR_SHIFT                        7
+/* PMPROT Bit Fields */
+#define MC_PMPROT_AVLLS1_MASK                    0x1u
+#define MC_PMPROT_AVLLS1_SHIFT                   0
+#define MC_PMPROT_AVLLS2_MASK                    0x2u
+#define MC_PMPROT_AVLLS2_SHIFT                   1
+#define MC_PMPROT_AVLLS3_MASK                    0x4u
+#define MC_PMPROT_AVLLS3_SHIFT                   2
+#define MC_PMPROT_ALLS_MASK                      0x10u
+#define MC_PMPROT_ALLS_SHIFT                     4
+#define MC_PMPROT_AVLP_MASK                      0x20u
+#define MC_PMPROT_AVLP_SHIFT                     5
+/* PMCTRL Bit Fields */
+#define MC_PMCTRL_LPLLSM_MASK                    0x7u
+#define MC_PMCTRL_LPLLSM_SHIFT                   0
+#define MC_PMCTRL_LPLLSM(x)                      (((uint8_t)(((uint8_t)(x))<<MC_PMCTRL_LPLLSM_SHIFT))&MC_PMCTRL_LPLLSM_MASK)
+#define MC_PMCTRL_RUNM_MASK                      0x60u
+#define MC_PMCTRL_RUNM_SHIFT                     5
+#define MC_PMCTRL_RUNM(x)                        (((uint8_t)(((uint8_t)(x))<<MC_PMCTRL_RUNM_SHIFT))&MC_PMCTRL_RUNM_MASK)
+#define MC_PMCTRL_LPWUI_MASK                     0x80u
+#define MC_PMCTRL_LPWUI_SHIFT                    7
+
+/*! \} */ /* end of group MC_Register_Masks */
+
+
+/* MC - Peripheral instance base addresses */
+/*! Peripheral MC base address */
+#define MC_BASE                                  (0x4007E000u)
+/*! Peripheral MC base pointer */
+#define MC                                       ((MC_Type *)MC_BASE)
+
+/*! \} */ /* end of group MC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer */
+/*! \{ */
+
+/*! MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /*!< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /*!< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /*!< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /*!< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /*!< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /*!< MCG Control 6 Register, offset: 0x5 */
+  __I  uint8_t S;                                  /*!< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t ATC;                                /*!< MCG Auto Trim Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /*!< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /*!< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MCG_Register_Masks MCG Register Masks */
+/*! \{ */
+
+/* C1 Bit Fields */
+#define MCG_C1_IREFSTEN_MASK                     0x1u
+#define MCG_C1_IREFSTEN_SHIFT                    0
+#define MCG_C1_IRCLKEN_MASK                      0x2u
+#define MCG_C1_IRCLKEN_SHIFT                     1
+#define MCG_C1_IREFS_MASK                        0x4u
+#define MCG_C1_IREFS_SHIFT                       2
+#define MCG_C1_FRDIV_MASK                        0x38u
+#define MCG_C1_FRDIV_SHIFT                       3
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         0xC0u
+#define MCG_C1_CLKS_SHIFT                        6
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
+/* C2 Bit Fields */
+#define MCG_C2_IRCS_MASK                         0x1u
+#define MCG_C2_IRCS_SHIFT                        0
+#define MCG_C2_LP_MASK                           0x2u
+#define MCG_C2_LP_SHIFT                          1
+#define MCG_C2_EREFS_MASK                        0x4u
+#define MCG_C2_EREFS_SHIFT                       2
+#define MCG_C2_HGO_MASK                          0x8u
+#define MCG_C2_HGO_SHIFT                         3
+#define MCG_C2_RANGE_MASK                        0x30u
+#define MCG_C2_RANGE_SHIFT                       4
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
+/* C3 Bit Fields */
+#define MCG_C3_SCTRIM_MASK                       0xFFu
+#define MCG_C3_SCTRIM_SHIFT                      0
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
+/* C4 Bit Fields */
+#define MCG_C4_SCFTRIM_MASK                      0x1u
+#define MCG_C4_SCFTRIM_SHIFT                     0
+#define MCG_C4_FCTRIM_MASK                       0x1Eu
+#define MCG_C4_FCTRIM_SHIFT                      1
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     0x60u
+#define MCG_C4_DRST_DRS_SHIFT                    5
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        0x80u
+#define MCG_C4_DMX32_SHIFT                       7
+/* C5 Bit Fields */
+#define MCG_C5_PRDIV_MASK                        0x1Fu
+#define MCG_C5_PRDIV_SHIFT                       0
+#define MCG_C5_PRDIV(x)                          (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV_SHIFT))&MCG_C5_PRDIV_MASK)
+#define MCG_C5_PLLSTEN_MASK                      0x20u
+#define MCG_C5_PLLSTEN_SHIFT                     5
+#define MCG_C5_PLLCLKEN_MASK                     0x40u
+#define MCG_C5_PLLCLKEN_SHIFT                    6
+/* C6 Bit Fields */
+#define MCG_C6_VDIV_MASK                         0x1Fu
+#define MCG_C6_VDIV_SHIFT                        0
+#define MCG_C6_VDIV(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV_SHIFT))&MCG_C6_VDIV_MASK)
+#define MCG_C6_CME_MASK                          0x20u
+#define MCG_C6_CME_SHIFT                         5
+#define MCG_C6_PLLS_MASK                         0x40u
+#define MCG_C6_PLLS_SHIFT                        6
+#define MCG_C6_LOLIE_MASK                        0x80u
+#define MCG_C6_LOLIE_SHIFT                       7
+/* S Bit Fields */
+#define MCG_S_IRCST_MASK                         0x1u
+#define MCG_S_IRCST_SHIFT                        0
+#define MCG_S_OSCINIT_MASK                       0x2u
+#define MCG_S_OSCINIT_SHIFT                      1
+#define MCG_S_CLKST_MASK                         0xCu
+#define MCG_S_CLKST_SHIFT                        2
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
+#define MCG_S_IREFST_MASK                        0x10u
+#define MCG_S_IREFST_SHIFT                       4
+#define MCG_S_PLLST_MASK                         0x20u
+#define MCG_S_PLLST_SHIFT                        5
+#define MCG_S_LOCK_MASK                          0x40u
+#define MCG_S_LOCK_SHIFT                         6
+#define MCG_S_LOLS_MASK                          0x80u
+#define MCG_S_LOLS_SHIFT                         7
+/* ATC Bit Fields */
+#define MCG_ATC_ATMF_MASK                        0x20u
+#define MCG_ATC_ATMF_SHIFT                       5
+#define MCG_ATC_ATMS_MASK                        0x40u
+#define MCG_ATC_ATMS_SHIFT                       6
+#define MCG_ATC_ATME_MASK                        0x80u
+#define MCG_ATC_ATME_SHIFT                       7
+/* ATCVH Bit Fields */
+#define MCG_ATCVH_ATCVH_MASK                     0xFFu
+#define MCG_ATCVH_ATCVH_SHIFT                    0
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
+/* ATCVL Bit Fields */
+#define MCG_ATCVL_ATCVL_MASK                     0xFFu
+#define MCG_ATCVL_ATCVL_SHIFT                    0
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
+
+/*! \} */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/*! Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/*! Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+
+/*! \} */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer */
+/*! \{ */
+
+/*! MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /*!< Crossbar switch (AXBS) slave configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /*!< Crossbar switch (AXBS) master configuration, offset: 0xA */
+  __IO uint32_t SRAMAP;                            /*!< SRAM arbitration and protection, offset: 0xC */
+  __IO uint32_t ISR;                               /*!< Interrupt status register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /*!< ETB counter control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /*!< ETB reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /*!< ETB counter value register, offset: 0x1C */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MCM_Register_Masks MCM Register Masks */
+/*! \{ */
+
+/* PLASC Bit Fields */
+#define MCM_PLASC_ASC_MASK                       0xFFu
+#define MCM_PLASC_ASC_SHIFT                      0
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
+/* PLAMC Bit Fields */
+#define MCM_PLAMC_AMC_MASK                       0xFFu
+#define MCM_PLAMC_AMC_SHIFT                      0
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
+/* SRAMAP Bit Fields */
+#define MCM_SRAMAP_SRAMUAP_MASK                  0x3000000u
+#define MCM_SRAMAP_SRAMUAP_SHIFT                 24
+#define MCM_SRAMAP_SRAMUAP(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMUAP_SHIFT))&MCM_SRAMAP_SRAMUAP_MASK)
+#define MCM_SRAMAP_SRAMUWP_MASK                  0x4000000u
+#define MCM_SRAMAP_SRAMUWP_SHIFT                 26
+#define MCM_SRAMAP_SRAMLAP_MASK                  0x30000000u
+#define MCM_SRAMAP_SRAMLAP_SHIFT                 28
+#define MCM_SRAMAP_SRAMLAP(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_SRAMAP_SRAMLAP_SHIFT))&MCM_SRAMAP_SRAMLAP_MASK)
+#define MCM_SRAMAP_SRAMLWP_MASK                  0x40000000u
+#define MCM_SRAMAP_SRAMLWP_SHIFT                 30
+/* ISR Bit Fields */
+#define MCM_ISR_IRQ_MASK                         0x2u
+#define MCM_ISR_IRQ_SHIFT                        1
+#define MCM_ISR_NMI_MASK                         0x4u
+#define MCM_ISR_NMI_SHIFT                        2
+/* ETBCC Bit Fields */
+#define MCM_ETBCC_CNTEN_MASK                     0x1u
+#define MCM_ETBCC_CNTEN_SHIFT                    0
+#define MCM_ETBCC_RSPT_MASK                      0x6u
+#define MCM_ETBCC_RSPT_SHIFT                     1
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      0x8u
+#define MCM_ETBCC_RLRQ_SHIFT                     3
+#define MCM_ETBCC_ETDIS_MASK                     0x10u
+#define MCM_ETBCC_ETDIS_SHIFT                    4
+#define MCM_ETBCC_ITDIS_MASK                     0x20u
+#define MCM_ETBCC_ITDIS_SHIFT                    5
+/* ETBRL Bit Fields */
+#define MCM_ETBRL_RELOAD_MASK                    0x7FFu
+#define MCM_ETBRL_RELOAD_SHIFT                   0
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
+/* ETBCNT Bit Fields */
+#define MCM_ETBCNT_COUNTER_MASK                  0x7FFu
+#define MCM_ETBCNT_COUNTER_SHIFT                 0
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
+
+/*! \} */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/*! Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/*! Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+
+/*! \} */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer */
+/*! \{ */
+
+/*! MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /*!< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /*!< Error Address Register, Slave Port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /*!< Error Detail Register, Slave Port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /*!< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /*!< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup MPU_Register_Masks MPU Register Masks */
+/*! \{ */
+
+/* CESR Bit Fields */
+#define MPU_CESR_VLD_MASK                        0x1u
+#define MPU_CESR_VLD_SHIFT                       0
+#define MPU_CESR_NRGD_MASK                       0xF00u
+#define MPU_CESR_NRGD_SHIFT                      8
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        0xF000u
+#define MPU_CESR_NSP_SHIFT                       12
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        0xF0000u
+#define MPU_CESR_HRL_SHIFT                       16
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      0xF8000000u
+#define MPU_CESR_SPERR_SHIFT                     27
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
+/* EAR Bit Fields */
+#define MPU_EAR_EADDR_MASK                       0xFFFFFFFFu
+#define MPU_EAR_EADDR_SHIFT                      0
+#define MPU_EAR_EADDR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
+/* EDR Bit Fields */
+#define MPU_EDR_ERW_MASK                         0x1u
+#define MPU_EDR_ERW_SHIFT                        0
+#define MPU_EDR_EATTR_MASK                       0xEu
+#define MPU_EDR_EATTR_SHIFT                      1
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         0xF0u
+#define MPU_EDR_EMN_SHIFT                        4
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
+#define MPU_EDR_EACD_MASK                        0xFFFF0000u
+#define MPU_EDR_EACD_SHIFT                       16
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
+/* WORD Bit Fields */
+#define MPU_WORD_M0UM_MASK                       0x7u
+#define MPU_WORD_M0UM_SHIFT                      0
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
+#define MPU_WORD_VLD_MASK                        0x1u
+#define MPU_WORD_VLD_SHIFT                       0
+#define MPU_WORD_M0SM_MASK                       0x18u
+#define MPU_WORD_M0SM_SHIFT                      3
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
+#define MPU_WORD_ENDADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_ENDADDR_SHIFT                   5
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    0xFFFFFFE0u
+#define MPU_WORD_SRTADDR_SHIFT                   5
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       0x1C0u
+#define MPU_WORD_M1UM_SHIFT                      6
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       0x600u
+#define MPU_WORD_M1SM_SHIFT                      9
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M2UM_MASK                       0x7000u
+#define MPU_WORD_M2UM_SHIFT                      12
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       0x18000u
+#define MPU_WORD_M2SM_SHIFT                      15
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
+#define MPU_WORD_M3UM_MASK                       0x1C0000u
+#define MPU_WORD_M3UM_SHIFT                      18
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       0x600000u
+#define MPU_WORD_M3SM_SHIFT                      21
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M4WE_MASK                       0x1000000u
+#define MPU_WORD_M4WE_SHIFT                      24
+#define MPU_WORD_M4RE_MASK                       0x2000000u
+#define MPU_WORD_M4RE_SHIFT                      25
+#define MPU_WORD_M5WE_MASK                       0x4000000u
+#define MPU_WORD_M5WE_SHIFT                      26
+#define MPU_WORD_M5RE_MASK                       0x8000000u
+#define MPU_WORD_M5RE_SHIFT                      27
+#define MPU_WORD_M6WE_MASK                       0x10000000u
+#define MPU_WORD_M6WE_SHIFT                      28
+#define MPU_WORD_M6RE_MASK                       0x20000000u
+#define MPU_WORD_M6RE_SHIFT                      29
+#define MPU_WORD_M7WE_MASK                       0x40000000u
+#define MPU_WORD_M7WE_SHIFT                      30
+#define MPU_WORD_M7RE_MASK                       0x80000000u
+#define MPU_WORD_M7RE_SHIFT                      31
+/* RGDAAC Bit Fields */
+#define MPU_RGDAAC_M0UM_MASK                     0x7u
+#define MPU_RGDAAC_M0UM_SHIFT                    0
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     0x18u
+#define MPU_RGDAAC_M0SM_SHIFT                    3
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M1UM_MASK                     0x1C0u
+#define MPU_RGDAAC_M1UM_SHIFT                    6
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     0x600u
+#define MPU_RGDAAC_M1SM_SHIFT                    9
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M2UM_MASK                     0x7000u
+#define MPU_RGDAAC_M2UM_SHIFT                    12
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     0x18000u
+#define MPU_RGDAAC_M2SM_SHIFT                    15
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M3UM_MASK                     0x1C0000u
+#define MPU_RGDAAC_M3UM_SHIFT                    18
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     0x600000u
+#define MPU_RGDAAC_M3SM_SHIFT                    21
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M4WE_MASK                     0x1000000u
+#define MPU_RGDAAC_M4WE_SHIFT                    24
+#define MPU_RGDAAC_M4RE_MASK                     0x2000000u
+#define MPU_RGDAAC_M4RE_SHIFT                    25
+#define MPU_RGDAAC_M5WE_MASK                     0x4000000u
+#define MPU_RGDAAC_M5WE_SHIFT                    26
+#define MPU_RGDAAC_M5RE_MASK                     0x8000000u
+#define MPU_RGDAAC_M5RE_SHIFT                    27
+#define MPU_RGDAAC_M6WE_MASK                     0x10000000u
+#define MPU_RGDAAC_M6WE_SHIFT                    28
+#define MPU_RGDAAC_M6RE_MASK                     0x20000000u
+#define MPU_RGDAAC_M6RE_SHIFT                    29
+#define MPU_RGDAAC_M7WE_MASK                     0x40000000u
+#define MPU_RGDAAC_M7WE_SHIFT                    30
+#define MPU_RGDAAC_M7RE_MASK                     0x80000000u
+#define MPU_RGDAAC_M7RE_SHIFT                    31
+
+/*! \} */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/*! Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/*! Peripheral MPU base pointer */
+#define MPU                                      ((MPU_Type *)MPU_BASE)
+
+/*! \} */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer */
+/*! \{ */
+
+/*! OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /*!< OSC Control Register, offset: 0x0 */
+} OSC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup OSC_Register_Masks OSC Register Masks */
+/*! \{ */
+
+/* CR Bit Fields */
+#define OSC_CR_SC16P_MASK                        0x1u
+#define OSC_CR_SC16P_SHIFT                       0
+#define OSC_CR_SC8P_MASK                         0x2u
+#define OSC_CR_SC8P_SHIFT                        1
+#define OSC_CR_SC4P_MASK                         0x4u
+#define OSC_CR_SC4P_SHIFT                        2
+#define OSC_CR_SC2P_MASK                         0x8u
+#define OSC_CR_SC2P_SHIFT                        3
+#define OSC_CR_EREFSTEN_MASK                     0x20u
+#define OSC_CR_EREFSTEN_SHIFT                    5
+#define OSC_CR_ERCLKEN_MASK                      0x80u
+#define OSC_CR_ERCLKEN_SHIFT                     7
+
+/*! \} */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/*! Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+/*! Peripheral OSC base pointer */
+#define OSC                                      ((OSC_Type *)OSC_BASE)
+
+/*! \} */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer */
+/*! \{ */
+
+/*! PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /*!< Status and Control Register, offset: 0x0 */
+  __IO uint32_t MOD;                               /*!< Modulus Register, offset: 0x4 */
+  __I  uint32_t CNT;                               /*!< Counter Register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /*!< Interrupt Delay Register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /*!< Channel n Control Register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /*!< Channel n Status Register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /*!< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /*!< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /*!< DAC Interval n Register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /*!< Pulse-Out n Enable Register, offset: 0x190 */
+  __IO uint32_t PODLY;                             /*!< Pulse-Out n Delay Register, offset: 0x194 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PDB_Register_Masks PDB Register Masks */
+/*! \{ */
+
+/* SC Bit Fields */
+#define PDB_SC_LDOK_MASK                         0x1u
+#define PDB_SC_LDOK_SHIFT                        0
+#define PDB_SC_CONT_MASK                         0x2u
+#define PDB_SC_CONT_SHIFT                        1
+#define PDB_SC_MULT_MASK                         0xCu
+#define PDB_SC_MULT_SHIFT                        2
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        0x20u
+#define PDB_SC_PDBIE_SHIFT                       5
+#define PDB_SC_PDBIF_MASK                        0x40u
+#define PDB_SC_PDBIF_SHIFT                       6
+#define PDB_SC_PDBEN_MASK                        0x80u
+#define PDB_SC_PDBEN_SHIFT                       7
+#define PDB_SC_TRGSEL_MASK                       0xF00u
+#define PDB_SC_TRGSEL_SHIFT                      8
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    0x7000u
+#define PDB_SC_PRESCALER_SHIFT                   12
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        0x8000u
+#define PDB_SC_DMAEN_SHIFT                       15
+#define PDB_SC_SWTRIG_MASK                       0x10000u
+#define PDB_SC_SWTRIG_SHIFT                      16
+#define PDB_SC_PDBEIE_MASK                       0x20000u
+#define PDB_SC_PDBEIE_SHIFT                      17
+#define PDB_SC_LDMOD_MASK                        0xC0000u
+#define PDB_SC_LDMOD_SHIFT                       18
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
+/* MOD Bit Fields */
+#define PDB_MOD_MOD_MASK                         0xFFFFu
+#define PDB_MOD_MOD_SHIFT                        0
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
+/* CNT Bit Fields */
+#define PDB_CNT_CNT_MASK                         0xFFFFu
+#define PDB_CNT_CNT_SHIFT                        0
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
+/* IDLY Bit Fields */
+#define PDB_IDLY_IDLY_MASK                       0xFFFFu
+#define PDB_IDLY_IDLY_SHIFT                      0
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
+/* C1 Bit Fields */
+#define PDB_C1_EN_MASK                           0xFFu
+#define PDB_C1_EN_SHIFT                          0
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          0xFF00u
+#define PDB_C1_TOS_SHIFT                         8
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           0xFF0000u
+#define PDB_C1_BB_SHIFT                          16
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
+/* S Bit Fields */
+#define PDB_S_ERR_MASK                           0xFFu
+#define PDB_S_ERR_SHIFT                          0
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            0xFF0000u
+#define PDB_S_CF_SHIFT                           16
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
+/* DLY Bit Fields */
+#define PDB_DLY_DLY_MASK                         0xFFFFu
+#define PDB_DLY_DLY_SHIFT                        0
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
+/* INTC Bit Fields */
+#define PDB_INTC_TOE_MASK                        0x1u
+#define PDB_INTC_TOE_SHIFT                       0
+#define PDB_INTC_EXT_MASK                        0x2u
+#define PDB_INTC_EXT_SHIFT                       1
+/* INT Bit Fields */
+#define PDB_INT_INT_MASK                         0xFFFFu
+#define PDB_INT_INT_SHIFT                        0
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
+/* POEN Bit Fields */
+#define PDB_POEN_POEN_MASK                       0xFFu
+#define PDB_POEN_POEN_SHIFT                      0
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
+/* PODLY Bit Fields */
+#define PDB_PODLY_DLY2_MASK                      0xFFFFu
+#define PDB_PODLY_DLY2_SHIFT                     0
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      0xFFFF0000u
+#define PDB_PODLY_DLY1_SHIFT                     16
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
+
+/*! \} */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/*! Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/*! Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+
+/*! \} */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer */
+/*! \{ */
+
+/*! PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /*!< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /*!< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /*!< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /*!< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /*!< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PIT_Register_Masks PIT Register Masks */
+/*! \{ */
+
+/* MCR Bit Fields */
+#define PIT_MCR_FRZ_MASK                         0x1u
+#define PIT_MCR_FRZ_SHIFT                        0
+#define PIT_MCR_MDIS_MASK                        0x2u
+#define PIT_MCR_MDIS_SHIFT                       1
+/* LDVAL Bit Fields */
+#define PIT_LDVAL_TSV_MASK                       0xFFFFFFFFu
+#define PIT_LDVAL_TSV_SHIFT                      0
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
+/* CVAL Bit Fields */
+#define PIT_CVAL_TVL_MASK                        0xFFFFFFFFu
+#define PIT_CVAL_TVL_SHIFT                       0
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
+/* TCTRL Bit Fields */
+#define PIT_TCTRL_TEN_MASK                       0x1u
+#define PIT_TCTRL_TEN_SHIFT                      0
+#define PIT_TCTRL_TIE_MASK                       0x2u
+#define PIT_TCTRL_TIE_SHIFT                      1
+/* TFLG Bit Fields */
+#define PIT_TFLG_TIF_MASK                        0x1u
+#define PIT_TFLG_TIF_SHIFT                       0
+
+/*! \} */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/*! Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/*! Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+
+/*! \} */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer */
+/*! \{ */
+
+/*! PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /*!< Low Voltage Detect Status and Control 1 Register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /*!< Low Voltage Detect Status and Control 2 Register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /*!< Regulator Status and Control Register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PMC_Register_Masks PMC Register Masks */
+/*! \{ */
+
+/* LVDSC1 Bit Fields */
+#define PMC_LVDSC1_LVDV_MASK                     0x3u
+#define PMC_LVDSC1_LVDV_SHIFT                    0
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    0x10u
+#define PMC_LVDSC1_LVDRE_SHIFT                   4
+#define PMC_LVDSC1_LVDIE_MASK                    0x20u
+#define PMC_LVDSC1_LVDIE_SHIFT                   5
+#define PMC_LVDSC1_LVDACK_MASK                   0x40u
+#define PMC_LVDSC1_LVDACK_SHIFT                  6
+#define PMC_LVDSC1_LVDF_MASK                     0x80u
+#define PMC_LVDSC1_LVDF_SHIFT                    7
+/* LVDSC2 Bit Fields */
+#define PMC_LVDSC2_LVWV_MASK                     0x3u
+#define PMC_LVDSC2_LVWV_SHIFT                    0
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    0x20u
+#define PMC_LVDSC2_LVWIE_SHIFT                   5
+#define PMC_LVDSC2_LVWACK_MASK                   0x40u
+#define PMC_LVDSC2_LVWACK_SHIFT                  6
+#define PMC_LVDSC2_LVWF_MASK                     0x80u
+#define PMC_LVDSC2_LVWF_SHIFT                    7
+/* REGSC Bit Fields */
+#define PMC_REGSC_BGBE_MASK                      0x1u
+#define PMC_REGSC_BGBE_SHIFT                     0
+#define PMC_REGSC_REGONS_MASK                    0x4u
+#define PMC_REGSC_REGONS_SHIFT                   2
+#define PMC_REGSC_VLPRS_MASK                     0x8u
+#define PMC_REGSC_VLPRS_SHIFT                    3
+#define PMC_REGSC_TRAMPO_MASK                    0x10u
+#define PMC_REGSC_TRAMPO_SHIFT                   4
+
+/*! \} */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/*! Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/*! Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+
+/*! \} */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer */
+/*! \{ */
+
+/*! PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /*!< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /*!< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /*!< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /*!< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /*!< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /*!< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /*!< Digital Filter Width Register, offset: 0xC8 */
+} PORT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup PORT_Register_Masks PORT Register Masks */
+/*! \{ */
+
+/* PCR Bit Fields */
+#define PORT_PCR_PS_MASK                         0x1u
+#define PORT_PCR_PS_SHIFT                        0
+#define PORT_PCR_PE_MASK                         0x2u
+#define PORT_PCR_PE_SHIFT                        1
+#define PORT_PCR_SRE_MASK                        0x4u
+#define PORT_PCR_SRE_SHIFT                       2
+#define PORT_PCR_PFE_MASK                        0x10u
+#define PORT_PCR_PFE_SHIFT                       4
+#define PORT_PCR_ODE_MASK                        0x20u
+#define PORT_PCR_ODE_SHIFT                       5
+#define PORT_PCR_DSE_MASK                        0x40u
+#define PORT_PCR_DSE_SHIFT                       6
+#define PORT_PCR_MUX_MASK                        0x700u
+#define PORT_PCR_MUX_SHIFT                       8
+#define PORT_PCR_MUX(x)                          (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
+#define PORT_PCR_LK_MASK                         0x8000u
+#define PORT_PCR_LK_SHIFT                        15
+#define PORT_PCR_IRQC_MASK                       0xF0000u
+#define PORT_PCR_IRQC_SHIFT                      16
+#define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
+#define PORT_PCR_ISF_MASK                        0x1000000u
+#define PORT_PCR_ISF_SHIFT                       24
+/* GPCLR Bit Fields */
+#define PORT_GPCLR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCLR_GPWD_SHIFT                    0
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCLR_GPWE_SHIFT                    16
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
+/* GPCHR Bit Fields */
+#define PORT_GPCHR_GPWD_MASK                     0xFFFFu
+#define PORT_GPCHR_GPWD_SHIFT                    0
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     0xFFFF0000u
+#define PORT_GPCHR_GPWE_SHIFT                    16
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
+/* ISFR Bit Fields */
+#define PORT_ISFR_ISF_MASK                       0xFFFFFFFFu
+#define PORT_ISFR_ISF_SHIFT                      0
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
+/* DFER Bit Fields */
+#define PORT_DFER_DFE_MASK                       0xFFFFFFFFu
+#define PORT_DFER_DFE_SHIFT                      0
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
+/* DFCR Bit Fields */
+#define PORT_DFCR_CS_MASK                        0x1u
+#define PORT_DFCR_CS_SHIFT                       0
+/* DFWR Bit Fields */
+#define PORT_DFWR_FILT_MASK                      0x1Fu
+#define PORT_DFWR_FILT_SHIFT                     0
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
+
+/*! \} */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/*! Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/*! Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_Type *)PORTA_BASE)
+/*! Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/*! Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_Type *)PORTB_BASE)
+/*! Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/*! Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_Type *)PORTC_BASE)
+/*! Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/*! Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_Type *)PORTD_BASE)
+/*! Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/*! Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_Type *)PORTE_BASE)
+
+/*! \} */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer */
+/*! \{ */
+
+/*! GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /*!< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /*!< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /*!< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /*!< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /*!< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /*!< Port Data Direction Register, offset: 0x14 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup GPIO_Register_Masks GPIO Register Masks */
+/*! \{ */
+
+/* PDOR Bit Fields */
+#define GPIO_PDOR_PDO_MASK                       0xFFFFFFFFu
+#define GPIO_PDOR_PDO_SHIFT                      0
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
+/* PSOR Bit Fields */
+#define GPIO_PSOR_PTSO_MASK                      0xFFFFFFFFu
+#define GPIO_PSOR_PTSO_SHIFT                     0
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
+/* PCOR Bit Fields */
+#define GPIO_PCOR_PTCO_MASK                      0xFFFFFFFFu
+#define GPIO_PCOR_PTCO_SHIFT                     0
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
+/* PTOR Bit Fields */
+#define GPIO_PTOR_PTTO_MASK                      0xFFFFFFFFu
+#define GPIO_PTOR_PTTO_SHIFT                     0
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
+/* PDIR Bit Fields */
+#define GPIO_PDIR_PDI_MASK                       0xFFFFFFFFu
+#define GPIO_PDIR_PDI_SHIFT                      0
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
+/* PDDR Bit Fields */
+#define GPIO_PDDR_PDD_MASK                       0xFFFFFFFFu
+#define GPIO_PDDR_PDD_SHIFT                      0
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
+
+/*! \} */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/*! Peripheral PTA base address */
+#define PTA_BASE                                 (0x400FF000u)
+/*! Peripheral PTA base pointer */
+#define PTA                                      ((GPIO_Type *)PTA_BASE)
+/*! Peripheral PTB base address */
+#define PTB_BASE                                 (0x400FF040u)
+/*! Peripheral PTB base pointer */
+#define PTB                                      ((GPIO_Type *)PTB_BASE)
+/*! Peripheral PTC base address */
+#define PTC_BASE                                 (0x400FF080u)
+/*! Peripheral PTC base pointer */
+#define PTC                                      ((GPIO_Type *)PTC_BASE)
+/*! Peripheral PTD base address */
+#define PTD_BASE                                 (0x400FF0C0u)
+/*! Peripheral PTD base pointer */
+#define PTD                                      ((GPIO_Type *)PTD_BASE)
+/*! Peripheral PTE base address */
+#define PTE_BASE                                 (0x400FF100u)
+/*! Peripheral PTE base pointer */
+#define PTE                                      ((GPIO_Type *)PTE_BASE)
+
+/*! \} */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer */
+/*! \{ */
+
+/*! RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /*!< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup RFSYS_Register_Masks RFSYS Register Masks */
+/*! \{ */
+
+/* REG Bit Fields */
+#define RFSYS_REG_LL_MASK                        0xFFu
+#define RFSYS_REG_LL_SHIFT                       0
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        0xFF00u
+#define RFSYS_REG_LH_SHIFT                       8
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        0xFF0000u
+#define RFSYS_REG_HL_SHIFT                       16
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        0xFF000000u
+#define RFSYS_REG_HH_SHIFT                       24
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
+
+/*! \} */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/*! Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/*! Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+
+/*! \} */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer */
+/*! \{ */
+
+/*! RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /*!< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup RFVBAT_Register_Masks RFVBAT Register Masks */
+/*! \{ */
+
+/* REG Bit Fields */
+#define RFVBAT_REG_LL_MASK                       0xFFu
+#define RFVBAT_REG_LL_SHIFT                      0
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       0xFF00u
+#define RFVBAT_REG_LH_SHIFT                      8
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       0xFF0000u
+#define RFVBAT_REG_HL_SHIFT                      16
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       0xFF000000u
+#define RFVBAT_REG_HH_SHIFT                      24
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
+
+/*! \} */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/*! Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/*! Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+
+/*! \} */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer */
+/*! \{ */
+
+/*! RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /*!< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /*!< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /*!< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /*!< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /*!< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /*!< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /*!< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t CCR;                               /*!< RTC Chip Configuration Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /*!< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /*!< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup RTC_Register_Masks RTC Register Masks */
+/*! \{ */
+
+/* TSR Bit Fields */
+#define RTC_TSR_TSR_MASK                         0xFFFFFFFFu
+#define RTC_TSR_TSR_SHIFT                        0
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
+/* TPR Bit Fields */
+#define RTC_TPR_TPR_MASK                         0xFFFFu
+#define RTC_TPR_TPR_SHIFT                        0
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
+/* TAR Bit Fields */
+#define RTC_TAR_TAR_MASK                         0xFFFFFFFFu
+#define RTC_TAR_TAR_SHIFT                        0
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
+/* TCR Bit Fields */
+#define RTC_TCR_TCR_MASK                         0xFFu
+#define RTC_TCR_TCR_SHIFT                        0
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         0xFF00u
+#define RTC_TCR_CIR_SHIFT                        8
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         0xFF0000u
+#define RTC_TCR_TCV_SHIFT                        16
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         0xFF000000u
+#define RTC_TCR_CIC_SHIFT                        24
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
+/* CR Bit Fields */
+#define RTC_CR_SWR_MASK                          0x1u
+#define RTC_CR_SWR_SHIFT                         0
+#define RTC_CR_WPE_MASK                          0x2u
+#define RTC_CR_WPE_SHIFT                         1
+#define RTC_CR_SUP_MASK                          0x4u
+#define RTC_CR_SUP_SHIFT                         2
+#define RTC_CR_UM_MASK                           0x8u
+#define RTC_CR_UM_SHIFT                          3
+#define RTC_CR_OSCE_MASK                         0x100u
+#define RTC_CR_OSCE_SHIFT                        8
+#define RTC_CR_CLKO_MASK                         0x200u
+#define RTC_CR_CLKO_SHIFT                        9
+#define RTC_CR_SC16P_MASK                        0x400u
+#define RTC_CR_SC16P_SHIFT                       10
+#define RTC_CR_SC8P_MASK                         0x800u
+#define RTC_CR_SC8P_SHIFT                        11
+#define RTC_CR_SC4P_MASK                         0x1000u
+#define RTC_CR_SC4P_SHIFT                        12
+#define RTC_CR_SC2P_MASK                         0x2000u
+#define RTC_CR_SC2P_SHIFT                        13
+/* SR Bit Fields */
+#define RTC_SR_TIF_MASK                          0x1u
+#define RTC_SR_TIF_SHIFT                         0
+#define RTC_SR_TOF_MASK                          0x2u
+#define RTC_SR_TOF_SHIFT                         1
+#define RTC_SR_TAF_MASK                          0x4u
+#define RTC_SR_TAF_SHIFT                         2
+#define RTC_SR_TCE_MASK                          0x10u
+#define RTC_SR_TCE_SHIFT                         4
+/* LR Bit Fields */
+#define RTC_LR_TCL_MASK                          0x8u
+#define RTC_LR_TCL_SHIFT                         3
+#define RTC_LR_CRL_MASK                          0x10u
+#define RTC_LR_CRL_SHIFT                         4
+#define RTC_LR_SRL_MASK                          0x20u
+#define RTC_LR_SRL_SHIFT                         5
+/* CCR Bit Fields */
+#define RTC_CCR_CONFIG_MASK                      0xFFu
+#define RTC_CCR_CONFIG_SHIFT                     0
+#define RTC_CCR_CONFIG(x)                        (((uint32_t)(((uint32_t)(x))<<RTC_CCR_CONFIG_SHIFT))&RTC_CCR_CONFIG_MASK)
+/* WAR Bit Fields */
+#define RTC_WAR_TSRW_MASK                        0x1u
+#define RTC_WAR_TSRW_SHIFT                       0
+#define RTC_WAR_TPRW_MASK                        0x2u
+#define RTC_WAR_TPRW_SHIFT                       1
+#define RTC_WAR_TARW_MASK                        0x4u
+#define RTC_WAR_TARW_SHIFT                       2
+#define RTC_WAR_TCRW_MASK                        0x8u
+#define RTC_WAR_TCRW_SHIFT                       3
+#define RTC_WAR_CRW_MASK                         0x10u
+#define RTC_WAR_CRW_SHIFT                        4
+#define RTC_WAR_SRW_MASK                         0x20u
+#define RTC_WAR_SRW_SHIFT                        5
+#define RTC_WAR_LRW_MASK                         0x40u
+#define RTC_WAR_LRW_SHIFT                        6
+#define RTC_WAR_CCRW_MASK                        0x80u
+#define RTC_WAR_CCRW_SHIFT                       7
+/* RAR Bit Fields */
+#define RTC_RAR_TSRR_MASK                        0x1u
+#define RTC_RAR_TSRR_SHIFT                       0
+#define RTC_RAR_TPRR_MASK                        0x2u
+#define RTC_RAR_TPRR_SHIFT                       1
+#define RTC_RAR_TARR_MASK                        0x4u
+#define RTC_RAR_TARR_SHIFT                       2
+#define RTC_RAR_TCRR_MASK                        0x8u
+#define RTC_RAR_TCRR_SHIFT                       3
+#define RTC_RAR_CRR_MASK                         0x10u
+#define RTC_RAR_CRR_SHIFT                        4
+#define RTC_RAR_SRR_MASK                         0x20u
+#define RTC_RAR_SRR_SHIFT                        5
+#define RTC_RAR_LRR_MASK                         0x40u
+#define RTC_RAR_LRR_SHIFT                        6
+#define RTC_RAR_CCRR_MASK                        0x80u
+#define RTC_RAR_CCRR_SHIFT                       7
+
+/*! \} */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/*! Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/*! Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+
+/*! \} */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer */
+/*! \{ */
+
+/*! SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /*!< DMA System Address Register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /*!< Block Attributes Register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /*!< Command Argument Register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /*!< Transfer Type Register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /*!< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /*!< Buffer Data Port Register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /*!< Present State Register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /*!< Protocol Control Register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /*!< System Control Register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /*!< Interrupt Status Register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /*!< Interrupt Status Enable Register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /*!< Interrupt Signal Enable Register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /*!< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /*!< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /*!< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /*!< Force Event Register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /*!< ADMA Error Status Register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /*!< ADMA System Address Register, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /*!< Vendor Specific Register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /*!< MMC Boot Register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /*!< Host Controller Version, offset: 0xFC */
+} SDHC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup SDHC_Register_Masks SDHC Register Masks */
+/*! \{ */
+
+/* DSADDR Bit Fields */
+#define SDHC_DSADDR_DSADDR_MASK                  0xFFFFFFFCu
+#define SDHC_DSADDR_DSADDR_SHIFT                 2
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
+/* BLKATTR Bit Fields */
+#define SDHC_BLKATTR_BLKSIZE_MASK                0x1FFFu
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               0
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 0xFFFF0000u
+#define SDHC_BLKATTR_BLKCNT_SHIFT                16
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
+/* CMDARG Bit Fields */
+#define SDHC_CMDARG_CMDARG_MASK                  0xFFFFFFFFu
+#define SDHC_CMDARG_CMDARG_SHIFT                 0
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
+/* XFERTYP Bit Fields */
+#define SDHC_XFERTYP_DMAEN_MASK                  0x1u
+#define SDHC_XFERTYP_DMAEN_SHIFT                 0
+#define SDHC_XFERTYP_BCEN_MASK                   0x2u
+#define SDHC_XFERTYP_BCEN_SHIFT                  1
+#define SDHC_XFERTYP_AC12EN_MASK                 0x4u
+#define SDHC_XFERTYP_AC12EN_SHIFT                2
+#define SDHC_XFERTYP_DTDSEL_MASK                 0x10u
+#define SDHC_XFERTYP_DTDSEL_SHIFT                4
+#define SDHC_XFERTYP_MSBSEL_MASK                 0x20u
+#define SDHC_XFERTYP_MSBSEL_SHIFT                5
+#define SDHC_XFERTYP_RSPTYP_MASK                 0x30000u
+#define SDHC_XFERTYP_RSPTYP_SHIFT                16
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  0x80000u
+#define SDHC_XFERTYP_CCCEN_SHIFT                 19
+#define SDHC_XFERTYP_CICEN_MASK                  0x100000u
+#define SDHC_XFERTYP_CICEN_SHIFT                 20
+#define SDHC_XFERTYP_DPSEL_MASK                  0x200000u
+#define SDHC_XFERTYP_DPSEL_SHIFT                 21
+#define SDHC_XFERTYP_CMDTYP_MASK                 0xC00000u
+#define SDHC_XFERTYP_CMDTYP_SHIFT                22
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 0x3F000000u
+#define SDHC_XFERTYP_CMDINX_SHIFT                24
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
+/* CMDRSP Bit Fields */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 0xFFFFFFFFu
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                0
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
+/* DATPORT Bit Fields */
+#define SDHC_DATPORT_DATCONT_MASK                0xFFFFFFFFu
+#define SDHC_DATPORT_DATCONT_SHIFT               0
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
+/* PRSSTAT Bit Fields */
+#define SDHC_PRSSTAT_CIHB_MASK                   0x1u
+#define SDHC_PRSSTAT_CIHB_SHIFT                  0
+#define SDHC_PRSSTAT_CDIHB_MASK                  0x2u
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 1
+#define SDHC_PRSSTAT_DLA_MASK                    0x4u
+#define SDHC_PRSSTAT_DLA_SHIFT                   2
+#define SDHC_PRSSTAT_SDSTB_MASK                  0x8u
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 3
+#define SDHC_PRSSTAT_IPGOFF_MASK                 0x10u
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                4
+#define SDHC_PRSSTAT_HCKOFF_MASK                 0x20u
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                5
+#define SDHC_PRSSTAT_PEROFF_MASK                 0x40u
+#define SDHC_PRSSTAT_PEROFF_SHIFT                6
+#define SDHC_PRSSTAT_SDOFF_MASK                  0x80u
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 7
+#define SDHC_PRSSTAT_WTA_MASK                    0x100u
+#define SDHC_PRSSTAT_WTA_SHIFT                   8
+#define SDHC_PRSSTAT_RTA_MASK                    0x200u
+#define SDHC_PRSSTAT_RTA_SHIFT                   9
+#define SDHC_PRSSTAT_BWEN_MASK                   0x400u
+#define SDHC_PRSSTAT_BWEN_SHIFT                  10
+#define SDHC_PRSSTAT_BREN_MASK                   0x800u
+#define SDHC_PRSSTAT_BREN_SHIFT                  11
+#define SDHC_PRSSTAT_CINS_MASK                   0x10000u
+#define SDHC_PRSSTAT_CINS_SHIFT                  16
+#define SDHC_PRSSTAT_CLSL_MASK                   0x800000u
+#define SDHC_PRSSTAT_CLSL_SHIFT                  23
+#define SDHC_PRSSTAT_DLSL_MASK                   0xFF000000u
+#define SDHC_PRSSTAT_DLSL_SHIFT                  24
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
+/* PROCTL Bit Fields */
+#define SDHC_PROCTL_LCTL_MASK                    0x1u
+#define SDHC_PROCTL_LCTL_SHIFT                   0
+#define SDHC_PROCTL_DTW_MASK                     0x6u
+#define SDHC_PROCTL_DTW_SHIFT                    1
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    0x8u
+#define SDHC_PROCTL_D3CD_SHIFT                   3
+#define SDHC_PROCTL_EMODE_MASK                   0x30u
+#define SDHC_PROCTL_EMODE_SHIFT                  4
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    0x40u
+#define SDHC_PROCTL_CDTL_SHIFT                   6
+#define SDHC_PROCTL_CDSS_MASK                    0x80u
+#define SDHC_PROCTL_CDSS_SHIFT                   7
+#define SDHC_PROCTL_DMAS_MASK                    0x300u
+#define SDHC_PROCTL_DMAS_SHIFT                   8
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 0x10000u
+#define SDHC_PROCTL_SABGREQ_SHIFT                16
+#define SDHC_PROCTL_CREQ_MASK                    0x20000u
+#define SDHC_PROCTL_CREQ_SHIFT                   17
+#define SDHC_PROCTL_RWCTL_MASK                   0x40000u
+#define SDHC_PROCTL_RWCTL_SHIFT                  18
+#define SDHC_PROCTL_IABG_MASK                    0x80000u
+#define SDHC_PROCTL_IABG_SHIFT                   19
+#define SDHC_PROCTL_WECINT_MASK                  0x1000000u
+#define SDHC_PROCTL_WECINT_SHIFT                 24
+#define SDHC_PROCTL_WECINS_MASK                  0x2000000u
+#define SDHC_PROCTL_WECINS_SHIFT                 25
+#define SDHC_PROCTL_WECRM_MASK                   0x4000000u
+#define SDHC_PROCTL_WECRM_SHIFT                  26
+/* SYSCTL Bit Fields */
+#define SDHC_SYSCTL_IPGEN_MASK                   0x1u
+#define SDHC_SYSCTL_IPGEN_SHIFT                  0
+#define SDHC_SYSCTL_HCKEN_MASK                   0x2u
+#define SDHC_SYSCTL_HCKEN_SHIFT                  1
+#define SDHC_SYSCTL_PEREN_MASK                   0x4u
+#define SDHC_SYSCTL_PEREN_SHIFT                  2
+#define SDHC_SYSCTL_SDCLKEN_MASK                 0x8u
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                3
+#define SDHC_SYSCTL_DVS_MASK                     0xF0u
+#define SDHC_SYSCTL_DVS_SHIFT                    4
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 0xFF00u
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                8
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   0xF0000u
+#define SDHC_SYSCTL_DTOCV_SHIFT                  16
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    0x1000000u
+#define SDHC_SYSCTL_RSTA_SHIFT                   24
+#define SDHC_SYSCTL_RSTC_MASK                    0x2000000u
+#define SDHC_SYSCTL_RSTC_SHIFT                   25
+#define SDHC_SYSCTL_RSTD_MASK                    0x4000000u
+#define SDHC_SYSCTL_RSTD_SHIFT                   26
+#define SDHC_SYSCTL_INITA_MASK                   0x8000000u
+#define SDHC_SYSCTL_INITA_SHIFT                  27
+/* IRQSTAT Bit Fields */
+#define SDHC_IRQSTAT_CC_MASK                     0x1u
+#define SDHC_IRQSTAT_CC_SHIFT                    0
+#define SDHC_IRQSTAT_TC_MASK                     0x2u
+#define SDHC_IRQSTAT_TC_SHIFT                    1
+#define SDHC_IRQSTAT_BGE_MASK                    0x4u
+#define SDHC_IRQSTAT_BGE_SHIFT                   2
+#define SDHC_IRQSTAT_DINT_MASK                   0x8u
+#define SDHC_IRQSTAT_DINT_SHIFT                  3
+#define SDHC_IRQSTAT_BWR_MASK                    0x10u
+#define SDHC_IRQSTAT_BWR_SHIFT                   4
+#define SDHC_IRQSTAT_BRR_MASK                    0x20u
+#define SDHC_IRQSTAT_BRR_SHIFT                   5
+#define SDHC_IRQSTAT_CINS_MASK                   0x40u
+#define SDHC_IRQSTAT_CINS_SHIFT                  6
+#define SDHC_IRQSTAT_CRM_MASK                    0x80u
+#define SDHC_IRQSTAT_CRM_SHIFT                   7
+#define SDHC_IRQSTAT_CINT_MASK                   0x100u
+#define SDHC_IRQSTAT_CINT_SHIFT                  8
+#define SDHC_IRQSTAT_CTOE_MASK                   0x10000u
+#define SDHC_IRQSTAT_CTOE_SHIFT                  16
+#define SDHC_IRQSTAT_CCE_MASK                    0x20000u
+#define SDHC_IRQSTAT_CCE_SHIFT                   17
+#define SDHC_IRQSTAT_CEBE_MASK                   0x40000u
+#define SDHC_IRQSTAT_CEBE_SHIFT                  18
+#define SDHC_IRQSTAT_CIE_MASK                    0x80000u
+#define SDHC_IRQSTAT_CIE_SHIFT                   19
+#define SDHC_IRQSTAT_DTOE_MASK                   0x100000u
+#define SDHC_IRQSTAT_DTOE_SHIFT                  20
+#define SDHC_IRQSTAT_DCE_MASK                    0x200000u
+#define SDHC_IRQSTAT_DCE_SHIFT                   21
+#define SDHC_IRQSTAT_DEBE_MASK                   0x400000u
+#define SDHC_IRQSTAT_DEBE_SHIFT                  22
+#define SDHC_IRQSTAT_AC12E_MASK                  0x1000000u
+#define SDHC_IRQSTAT_AC12E_SHIFT                 24
+#define SDHC_IRQSTAT_DMAE_MASK                   0x10000000u
+#define SDHC_IRQSTAT_DMAE_SHIFT                  28
+/* IRQSTATEN Bit Fields */
+#define SDHC_IRQSTATEN_CCSEN_MASK                0x1u
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               0
+#define SDHC_IRQSTATEN_TCSEN_MASK                0x2u
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               1
+#define SDHC_IRQSTATEN_BGESEN_MASK               0x4u
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              2
+#define SDHC_IRQSTATEN_DINTSEN_MASK              0x8u
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             3
+#define SDHC_IRQSTATEN_BWRSEN_MASK               0x10u
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              4
+#define SDHC_IRQSTATEN_BRRSEN_MASK               0x20u
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              5
+#define SDHC_IRQSTATEN_CINSEN_MASK               0x40u
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              6
+#define SDHC_IRQSTATEN_CRMSEN_MASK               0x80u
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              7
+#define SDHC_IRQSTATEN_CINTSEN_MASK              0x100u
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             8
+#define SDHC_IRQSTATEN_CTOESEN_MASK              0x10000u
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             16
+#define SDHC_IRQSTATEN_CCESEN_MASK               0x20000u
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              17
+#define SDHC_IRQSTATEN_CEBESEN_MASK              0x40000u
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             18
+#define SDHC_IRQSTATEN_CIESEN_MASK               0x80000u
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              19
+#define SDHC_IRQSTATEN_DTOESEN_MASK              0x100000u
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             20
+#define SDHC_IRQSTATEN_DCESEN_MASK               0x200000u
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              21
+#define SDHC_IRQSTATEN_DEBESEN_MASK              0x400000u
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             22
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             0x1000000u
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            24
+#define SDHC_IRQSTATEN_DMAESEN_MASK              0x10000000u
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             28
+/* IRQSIGEN Bit Fields */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 0x1u
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                0
+#define SDHC_IRQSIGEN_TCIEN_MASK                 0x2u
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                1
+#define SDHC_IRQSIGEN_BGEIEN_MASK                0x4u
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               2
+#define SDHC_IRQSIGEN_DINTIEN_MASK               0x8u
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              3
+#define SDHC_IRQSIGEN_BWRIEN_MASK                0x10u
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               4
+#define SDHC_IRQSIGEN_BRRIEN_MASK                0x20u
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               5
+#define SDHC_IRQSIGEN_CINSIEN_MASK               0x40u
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              6
+#define SDHC_IRQSIGEN_CRMIEN_MASK                0x80u
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               7
+#define SDHC_IRQSIGEN_CINTIEN_MASK               0x100u
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              8
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               0x10000u
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              16
+#define SDHC_IRQSIGEN_CCEIEN_MASK                0x20000u
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               17
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               0x40000u
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              18
+#define SDHC_IRQSIGEN_CIEIEN_MASK                0x80000u
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               19
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               0x100000u
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              20
+#define SDHC_IRQSIGEN_DCEIEN_MASK                0x200000u
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               21
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               0x400000u
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              22
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              0x1000000u
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             24
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               0x10000000u
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              28
+/* AC12ERR Bit Fields */
+#define SDHC_AC12ERR_AC12NE_MASK                 0x1u
+#define SDHC_AC12ERR_AC12NE_SHIFT                0
+#define SDHC_AC12ERR_AC12TOE_MASK                0x2u
+#define SDHC_AC12ERR_AC12TOE_SHIFT               1
+#define SDHC_AC12ERR_AC12EBE_MASK                0x4u
+#define SDHC_AC12ERR_AC12EBE_SHIFT               2
+#define SDHC_AC12ERR_AC12CE_MASK                 0x8u
+#define SDHC_AC12ERR_AC12CE_SHIFT                3
+#define SDHC_AC12ERR_AC12IE_MASK                 0x10u
+#define SDHC_AC12ERR_AC12IE_SHIFT                4
+#define SDHC_AC12ERR_CNIBAC12E_MASK              0x80u
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             7
+/* HTCAPBLT Bit Fields */
+#define SDHC_HTCAPBLT_MBL_MASK                   0x70000u
+#define SDHC_HTCAPBLT_MBL_SHIFT                  16
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 0x100000u
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                20
+#define SDHC_HTCAPBLT_HSS_MASK                   0x200000u
+#define SDHC_HTCAPBLT_HSS_SHIFT                  21
+#define SDHC_HTCAPBLT_DMAS_MASK                  0x400000u
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 22
+#define SDHC_HTCAPBLT_SRS_MASK                   0x800000u
+#define SDHC_HTCAPBLT_SRS_SHIFT                  23
+#define SDHC_HTCAPBLT_VS33_MASK                  0x1000000u
+#define SDHC_HTCAPBLT_VS33_SHIFT                 24
+#define SDHC_HTCAPBLT_VS30_MASK                  0x2000000u
+#define SDHC_HTCAPBLT_VS30_SHIFT                 25
+#define SDHC_HTCAPBLT_VS18_MASK                  0x4000000u
+#define SDHC_HTCAPBLT_VS18_SHIFT                 26
+/* WML Bit Fields */
+#define SDHC_WML_RDWML_MASK                      0xFFu
+#define SDHC_WML_RDWML_SHIFT                     0
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      0xFF0000u
+#define SDHC_WML_WRWML_SHIFT                     16
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
+#define SDHC_WML_WRBRSTLEN_MASK                  0x1F000000u
+#define SDHC_WML_WRBRSTLEN_SHIFT                 24
+#define SDHC_WML_WRBRSTLEN(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRBRSTLEN_SHIFT))&SDHC_WML_WRBRSTLEN_MASK)
+/* FEVT Bit Fields */
+#define SDHC_FEVT_AC12NE_MASK                    0x1u
+#define SDHC_FEVT_AC12NE_SHIFT                   0
+#define SDHC_FEVT_AC12TOE_MASK                   0x2u
+#define SDHC_FEVT_AC12TOE_SHIFT                  1
+#define SDHC_FEVT_AC12CE_MASK                    0x4u
+#define SDHC_FEVT_AC12CE_SHIFT                   2
+#define SDHC_FEVT_AC12EBE_MASK                   0x8u
+#define SDHC_FEVT_AC12EBE_SHIFT                  3
+#define SDHC_FEVT_AC12IE_MASK                    0x10u
+#define SDHC_FEVT_AC12IE_SHIFT                   4
+#define SDHC_FEVT_CNIBAC12E_MASK                 0x80u
+#define SDHC_FEVT_CNIBAC12E_SHIFT                7
+#define SDHC_FEVT_CTOE_MASK                      0x10000u
+#define SDHC_FEVT_CTOE_SHIFT                     16
+#define SDHC_FEVT_CCE_MASK                       0x20000u
+#define SDHC_FEVT_CCE_SHIFT                      17
+#define SDHC_FEVT_CEBE_MASK                      0x40000u
+#define SDHC_FEVT_CEBE_SHIFT                     18
+#define SDHC_FEVT_CIE_MASK                       0x80000u
+#define SDHC_FEVT_CIE_SHIFT                      19
+#define SDHC_FEVT_DTOE_MASK                      0x100000u
+#define SDHC_FEVT_DTOE_SHIFT                     20
+#define SDHC_FEVT_DCE_MASK                       0x200000u
+#define SDHC_FEVT_DCE_SHIFT                      21
+#define SDHC_FEVT_DEBE_MASK                      0x400000u
+#define SDHC_FEVT_DEBE_SHIFT                     22
+#define SDHC_FEVT_AC12E_MASK                     0x1000000u
+#define SDHC_FEVT_AC12E_SHIFT                    24
+#define SDHC_FEVT_DMAE_MASK                      0x10000000u
+#define SDHC_FEVT_DMAE_SHIFT                     28
+#define SDHC_FEVT_CINT_MASK                      0x80000000u
+#define SDHC_FEVT_CINT_SHIFT                     31
+/* ADMAES Bit Fields */
+#define SDHC_ADMAES_ADMAES_MASK                  0x3u
+#define SDHC_ADMAES_ADMAES_SHIFT                 0
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 0x4u
+#define SDHC_ADMAES_ADMALME_SHIFT                2
+#define SDHC_ADMAES_ADMADCE_MASK                 0x8u
+#define SDHC_ADMAES_ADMADCE_SHIFT                3
+/* ADSADDR Bit Fields */
+#define SDHC_ADSADDR_ADSADDR_MASK                0xFFFFFFFCu
+#define SDHC_ADSADDR_ADSADDR_SHIFT               2
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
+/* VENDOR Bit Fields */
+#define SDHC_VENDOR_EXTDMAEN_MASK                0x1u
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               0
+#define SDHC_VENDOR_VOLTSEL_MASK                 0x2u
+#define SDHC_VENDOR_VOLTSEL_SHIFT                1
+#define SDHC_VENDOR_INTSTVAL_MASK                0xFF0000u
+#define SDHC_VENDOR_INTSTVAL_SHIFT               16
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
+/* MMCBOOT Bit Fields */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               0xFu
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              0
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                0x10u
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               4
+#define SDHC_MMCBOOT_BOOTMODE_MASK               0x20u
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              5
+#define SDHC_MMCBOOT_BOOTEN_MASK                 0x40u
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                6
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             0x80u
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            7
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             0xFFFF0000u
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            16
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+/* HOSTVER Bit Fields */
+#define SDHC_HOSTVER_SVN_MASK                    0xFFu
+#define SDHC_HOSTVER_SVN_SHIFT                   0
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    0xFF00u
+#define SDHC_HOSTVER_VVN_SHIFT                   8
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
+
+/*! \} */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/*! Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/*! Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+
+/*! \} */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer */
+/*! \{ */
+
+/*! SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /*!< System Options Register 1, offset: 0x0 */
+       uint8_t RESERVED_0[4096];
+  __IO uint32_t SOPT2;                             /*!< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /*!< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /*!< System Options Register 5, offset: 0x1010 */
+  __IO uint32_t SOPT6;                             /*!< System Options Register 6, offset: 0x1014 */
+  __IO uint32_t SOPT7;                             /*!< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_2[8];
+  __I  uint32_t SDID;                              /*!< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /*!< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /*!< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /*!< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /*!< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /*!< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /*!< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /*!< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /*!< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /*!< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /*!< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /*!< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /*!< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /*!< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /*!< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /*!< Unique Identification Register Low, offset: 0x1060 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup SIM_Register_Masks SIM Register Masks */
+/*! \{ */
+
+/* SOPT1 Bit Fields */
+#define SIM_SOPT1_RAMSIZE_MASK                   0xF000u
+#define SIM_SOPT1_RAMSIZE_SHIFT                  12
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 0x80000u
+#define SIM_SOPT1_OSC32KSEL_SHIFT                19
+#define SIM_SOPT1_MS_MASK                        0x800000u
+#define SIM_SOPT1_MS_SHIFT                       23
+#define SIM_SOPT1_USBSTBY_MASK                   0x40000000u
+#define SIM_SOPT1_USBSTBY_SHIFT                  30
+#define SIM_SOPT1_USBREGEN_MASK                  0x80000000u
+#define SIM_SOPT1_USBREGEN_SHIFT                 31
+/* SOPT2 Bit Fields */
+#define SIM_SOPT2_MCGCLKSEL_MASK                 0x1u
+#define SIM_SOPT2_MCGCLKSEL_SHIFT                0
+#define SIM_SOPT2_FBSL_MASK                      0x300u
+#define SIM_SOPT2_FBSL_SHIFT                     8
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_CMTUARTPAD_MASK                0x800u
+#define SIM_SOPT2_CMTUARTPAD_SHIFT               11
+#define SIM_SOPT2_TRACECLKSEL_MASK               0x1000u
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              12
+#define SIM_SOPT2_PLLFLLSEL_MASK                 0x10000u
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                16
+#define SIM_SOPT2_USBSRC_MASK                    0x40000u
+#define SIM_SOPT2_USBSRC_SHIFT                   18
+#define SIM_SOPT2_I2SSRC_MASK                    0x3000000u
+#define SIM_SOPT2_I2SSRC_SHIFT                   24
+#define SIM_SOPT2_I2SSRC(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_I2SSRC_SHIFT))&SIM_SOPT2_I2SSRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   0x30000000u
+#define SIM_SOPT2_SDHCSRC_SHIFT                  28
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
+/* SOPT4 Bit Fields */
+#define SIM_SOPT4_FTM0FLT0_MASK                  0x1u
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 0
+#define SIM_SOPT4_FTM0FLT1_MASK                  0x2u
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 1
+#define SIM_SOPT4_FTM0FLT2_MASK                  0x4u
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 2
+#define SIM_SOPT4_FTM1FLT0_MASK                  0x10u
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 4
+#define SIM_SOPT4_FTM2FLT0_MASK                  0x100u
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 8
+#define SIM_SOPT4_FTM1CH0SRC_MASK                0xC0000u
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               18
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                0x300000u
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               20
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                0x1000000u
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               24
+#define SIM_SOPT4_FTM1CLKSEL_MASK                0x2000000u
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               25
+#define SIM_SOPT4_FTM2CLKSEL_MASK                0x4000000u
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               26
+/* SOPT5 Bit Fields */
+#define SIM_SOPT5_UART0TXSRC_MASK                0x3u
+#define SIM_SOPT5_UART0TXSRC_SHIFT               0
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                0xCu
+#define SIM_SOPT5_UART0RXSRC_SHIFT               2
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UARTTXSRC_MASK                 0x30u
+#define SIM_SOPT5_UARTTXSRC_SHIFT                4
+#define SIM_SOPT5_UARTTXSRC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UARTTXSRC_SHIFT))&SIM_SOPT5_UARTTXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                0xC0u
+#define SIM_SOPT5_UART1RXSRC_SHIFT               6
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
+/* SOPT6 Bit Fields */
+#define SIM_SOPT6_RSTFLTSEL_MASK                 0x1F000000u
+#define SIM_SOPT6_RSTFLTSEL_SHIFT                24
+#define SIM_SOPT6_RSTFLTSEL(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTSEL_SHIFT))&SIM_SOPT6_RSTFLTSEL_MASK)
+#define SIM_SOPT6_RSTFLTEN_MASK                  0xE0000000u
+#define SIM_SOPT6_RSTFLTEN_SHIFT                 29
+#define SIM_SOPT6_RSTFLTEN(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_SOPT6_RSTFLTEN_SHIFT))&SIM_SOPT6_RSTFLTEN_MASK)
+/* SOPT7 Bit Fields */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                0xFu
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               0
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             0x10u
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            4
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              0x80u
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             7
+#define SIM_SOPT7_ADC1TRGSEL_MASK                0xF00u
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               8
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             0x1000u
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            12
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              0x8000u
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             15
+/* SDID Bit Fields */
+#define SIM_SDID_PINID_MASK                      0xFu
+#define SIM_SDID_PINID_SHIFT                     0
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      0x70u
+#define SIM_SDID_FAMID_SHIFT                     4
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
+#define SIM_SDID_REVID_MASK                      0xF000u
+#define SIM_SDID_REVID_SHIFT                     12
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
+/* SCGC1 Bit Fields */
+#define SIM_SCGC1_UART4_MASK                     0x400u
+#define SIM_SCGC1_UART4_SHIFT                    10
+#define SIM_SCGC1_UART5_MASK                     0x800u
+#define SIM_SCGC1_UART5_SHIFT                    11
+/* SCGC2 Bit Fields */
+#define SIM_SCGC2_DAC0_MASK                      0x1000u
+#define SIM_SCGC2_DAC0_SHIFT                     12
+#define SIM_SCGC2_DAC1_MASK                      0x2000u
+#define SIM_SCGC2_DAC1_SHIFT                     13
+/* SCGC3 Bit Fields */
+#define SIM_SCGC3_FLEXCAN1_MASK                  0x10u
+#define SIM_SCGC3_FLEXCAN1_SHIFT                 4
+#define SIM_SCGC3_SPI2_MASK                      0x1000u
+#define SIM_SCGC3_SPI2_SHIFT                     12
+#define SIM_SCGC3_SDHC_MASK                      0x20000u
+#define SIM_SCGC3_SDHC_SHIFT                     17
+#define SIM_SCGC3_FTM2_MASK                      0x1000000u
+#define SIM_SCGC3_FTM2_SHIFT                     24
+#define SIM_SCGC3_ADC1_MASK                      0x8000000u
+#define SIM_SCGC3_ADC1_SHIFT                     27
+#define SIM_SCGC3_SLCD_MASK                      0x40000000u
+#define SIM_SCGC3_SLCD_SHIFT                     30
+/* SCGC4 Bit Fields */
+#define SIM_SCGC4_EWM_MASK                       0x2u
+#define SIM_SCGC4_EWM_SHIFT                      1
+#define SIM_SCGC4_CMT_MASK                       0x4u
+#define SIM_SCGC4_CMT_SHIFT                      2
+#define SIM_SCGC4_I2C0_MASK                      0x40u
+#define SIM_SCGC4_I2C0_SHIFT                     6
+#define SIM_SCGC4_I2C1_MASK                      0x80u
+#define SIM_SCGC4_I2C1_SHIFT                     7
+#define SIM_SCGC4_UART0_MASK                     0x400u
+#define SIM_SCGC4_UART0_SHIFT                    10
+#define SIM_SCGC4_UART1_MASK                     0x800u
+#define SIM_SCGC4_UART1_SHIFT                    11
+#define SIM_SCGC4_UART2_MASK                     0x1000u
+#define SIM_SCGC4_UART2_SHIFT                    12
+#define SIM_SCGC4_UART3_MASK                     0x2000u
+#define SIM_SCGC4_UART3_SHIFT                    13
+#define SIM_SCGC4_USBOTG_MASK                    0x40000u
+#define SIM_SCGC4_USBOTG_SHIFT                   18
+#define SIM_SCGC4_CMP_MASK                       0x80000u
+#define SIM_SCGC4_CMP_SHIFT                      19
+#define SIM_SCGC4_VREF_MASK                      0x100000u
+#define SIM_SCGC4_VREF_SHIFT                     20
+#define SIM_SCGC4_LLWU_MASK                      0x10000000u
+#define SIM_SCGC4_LLWU_SHIFT                     28
+/* SCGC5 Bit Fields */
+#define SIM_SCGC5_LPTIMER_MASK                   0x1u
+#define SIM_SCGC5_LPTIMER_SHIFT                  0
+#define SIM_SCGC5_REGFILE_MASK                   0x2u
+#define SIM_SCGC5_REGFILE_SHIFT                  1
+#define SIM_SCGC5_TSI_MASK                       0x20u
+#define SIM_SCGC5_TSI_SHIFT                      5
+#define SIM_SCGC5_PORTA_MASK                     0x200u
+#define SIM_SCGC5_PORTA_SHIFT                    9
+#define SIM_SCGC5_PORTB_MASK                     0x400u
+#define SIM_SCGC5_PORTB_SHIFT                    10
+#define SIM_SCGC5_PORTC_MASK                     0x800u
+#define SIM_SCGC5_PORTC_SHIFT                    11
+#define SIM_SCGC5_PORTD_MASK                     0x1000u
+#define SIM_SCGC5_PORTD_SHIFT                    12
+#define SIM_SCGC5_PORTE_MASK                     0x2000u
+#define SIM_SCGC5_PORTE_SHIFT                    13
+/* SCGC6 Bit Fields */
+#define SIM_SCGC6_FTFL_MASK                      0x1u
+#define SIM_SCGC6_FTFL_SHIFT                     0
+#define SIM_SCGC6_DMAMUX_MASK                    0x2u
+#define SIM_SCGC6_DMAMUX_SHIFT                   1
+#define SIM_SCGC6_FLEXCAN0_MASK                  0x10u
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 4
+#define SIM_SCGC6_DSPI0_MASK                     0x1000u
+#define SIM_SCGC6_DSPI0_SHIFT                    12
+#define SIM_SCGC6_SPI1_MASK                      0x2000u
+#define SIM_SCGC6_SPI1_SHIFT                     13
+#define SIM_SCGC6_I2S_MASK                       0x8000u
+#define SIM_SCGC6_I2S_SHIFT                      15
+#define SIM_SCGC6_CRC_MASK                       0x40000u
+#define SIM_SCGC6_CRC_SHIFT                      18
+#define SIM_SCGC6_USBDCD_MASK                    0x200000u
+#define SIM_SCGC6_USBDCD_SHIFT                   21
+#define SIM_SCGC6_PDB_MASK                       0x400000u
+#define SIM_SCGC6_PDB_SHIFT                      22
+#define SIM_SCGC6_PIT_MASK                       0x800000u
+#define SIM_SCGC6_PIT_SHIFT                      23
+#define SIM_SCGC6_FTM0_MASK                      0x1000000u
+#define SIM_SCGC6_FTM0_SHIFT                     24
+#define SIM_SCGC6_FTM1_MASK                      0x2000000u
+#define SIM_SCGC6_FTM1_SHIFT                     25
+#define SIM_SCGC6_ADC0_MASK                      0x8000000u
+#define SIM_SCGC6_ADC0_SHIFT                     27
+#define SIM_SCGC6_RTC_MASK                       0x20000000u
+#define SIM_SCGC6_RTC_SHIFT                      29
+/* SCGC7 Bit Fields */
+#define SIM_SCGC7_FLEXBUS_MASK                   0x1u
+#define SIM_SCGC7_FLEXBUS_SHIFT                  0
+#define SIM_SCGC7_DMA_MASK                       0x2u
+#define SIM_SCGC7_DMA_SHIFT                      1
+#define SIM_SCGC7_MPU_MASK                       0x4u
+#define SIM_SCGC7_MPU_SHIFT                      2
+/* CLKDIV1 Bit Fields */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 0xF0000u
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                16
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 0xF00000u
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                20
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 0xF000000u
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                24
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 0xF0000000u
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                28
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
+/* CLKDIV2 Bit Fields */
+#define SIM_CLKDIV2_USBFRAC_MASK                 0x1u
+#define SIM_CLKDIV2_USBFRAC_SHIFT                0
+#define SIM_CLKDIV2_USBDIV_MASK                  0xEu
+#define SIM_CLKDIV2_USBDIV_SHIFT                 1
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
+#define SIM_CLKDIV2_I2SFRAC_MASK                 0xFF00u
+#define SIM_CLKDIV2_I2SFRAC_SHIFT                8
+#define SIM_CLKDIV2_I2SFRAC(x)                   (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SFRAC_SHIFT))&SIM_CLKDIV2_I2SFRAC_MASK)
+#define SIM_CLKDIV2_I2SDIV_MASK                  0xFFF00000u
+#define SIM_CLKDIV2_I2SDIV_SHIFT                 20
+#define SIM_CLKDIV2_I2SDIV(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_I2SDIV_SHIFT))&SIM_CLKDIV2_I2SDIV_MASK)
+/* FCFG1 Bit Fields */
+#define SIM_FCFG1_DEPART_MASK                    0xF00u
+#define SIM_FCFG1_DEPART_SHIFT                   8
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    0xF0000u
+#define SIM_FCFG1_EESIZE_SHIFT                   16
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_FSIZE_MASK                     0xFF000000u
+#define SIM_FCFG1_FSIZE_SHIFT                    24
+#define SIM_FCFG1_FSIZE(x)                       (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_FSIZE_SHIFT))&SIM_FCFG1_FSIZE_MASK)
+/* FCFG2 Bit Fields */
+#define SIM_FCFG2_MAXADDR1_MASK                  0x3F0000u
+#define SIM_FCFG2_MAXADDR1_SHIFT                 16
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     0x800000u
+#define SIM_FCFG2_PFLSH_SHIFT                    23
+#define SIM_FCFG2_MAXADDR0_MASK                  0x3F000000u
+#define SIM_FCFG2_MAXADDR0_SHIFT                 24
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_SWAPPFLSH_MASK                 0x80000000u
+#define SIM_FCFG2_SWAPPFLSH_SHIFT                31
+/* UIDH Bit Fields */
+#define SIM_UIDH_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDH_UID_SHIFT                       0
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
+/* UIDMH Bit Fields */
+#define SIM_UIDMH_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDMH_UID_SHIFT                      0
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
+/* UIDML Bit Fields */
+#define SIM_UIDML_UID_MASK                       0xFFFFFFFFu
+#define SIM_UIDML_UID_SHIFT                      0
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
+/* UIDL Bit Fields */
+#define SIM_UIDL_UID_MASK                        0xFFFFFFFFu
+#define SIM_UIDL_UID_SHIFT                       0
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
+
+/*! \} */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/*! Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/*! Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+
+/*! \} */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer */
+/*! \{ */
+
+/*! SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /*!< DSPI Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /*!< DSPI Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /*!< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /*!< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /*!< DSPI Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /*!< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /*!< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /*!< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /*!< DSPI POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /*!< DSPI Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /*!< DSPI Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /*!< DSPI Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /*!< DSPI Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /*!< DSPI Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /*!< DSPI Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /*!< DSPI Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /*!< DSPI Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup SPI_Register_Masks SPI Register Masks */
+/*! \{ */
+
+/* MCR Bit Fields */
+#define SPI_MCR_HALT_MASK                        0x1u
+#define SPI_MCR_HALT_SHIFT                       0
+#define SPI_MCR_SMPL_PT_MASK                     0x300u
+#define SPI_MCR_SMPL_PT_SHIFT                    8
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     0x400u
+#define SPI_MCR_CLR_RXF_SHIFT                    10
+#define SPI_MCR_CLR_TXF_MASK                     0x800u
+#define SPI_MCR_CLR_TXF_SHIFT                    11
+#define SPI_MCR_DIS_RXF_MASK                     0x1000u
+#define SPI_MCR_DIS_RXF_SHIFT                    12
+#define SPI_MCR_DIS_TXF_MASK                     0x2000u
+#define SPI_MCR_DIS_TXF_SHIFT                    13
+#define SPI_MCR_MDIS_MASK                        0x4000u
+#define SPI_MCR_MDIS_SHIFT                       14
+#define SPI_MCR_DOZE_MASK                        0x8000u
+#define SPI_MCR_DOZE_SHIFT                       15
+#define SPI_MCR_PCSIS_MASK                       0x3F0000u
+#define SPI_MCR_PCSIS_SHIFT                      16
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        0x1000000u
+#define SPI_MCR_ROOE_SHIFT                       24
+#define SPI_MCR_PCSSE_MASK                       0x2000000u
+#define SPI_MCR_PCSSE_SHIFT                      25
+#define SPI_MCR_MTFE_MASK                        0x4000000u
+#define SPI_MCR_MTFE_SHIFT                       26
+#define SPI_MCR_FRZ_MASK                         0x8000000u
+#define SPI_MCR_FRZ_SHIFT                        27
+#define SPI_MCR_DCONF_MASK                       0x30000000u
+#define SPI_MCR_DCONF_SHIFT                      28
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   0x40000000u
+#define SPI_MCR_CONT_SCKE_SHIFT                  30
+#define SPI_MCR_MSTR_MASK                        0x80000000u
+#define SPI_MCR_MSTR_SHIFT                       31
+/* TCR Bit Fields */
+#define SPI_TCR_SPI_TCNT_MASK                    0xFFFF0000u
+#define SPI_TCR_SPI_TCNT_SHIFT                   16
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
+/* CTAR Bit Fields */
+#define SPI_CTAR_BR_MASK                         0xFu
+#define SPI_CTAR_BR_SHIFT                        0
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         0xF0u
+#define SPI_CTAR_DT_SHIFT                        4
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        0xF00u
+#define SPI_CTAR_ASC_SHIFT                       8
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      0xF000u
+#define SPI_CTAR_CSSCK_SHIFT                     12
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        0x30000u
+#define SPI_CTAR_PBR_SHIFT                       16
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        0xC0000u
+#define SPI_CTAR_PDT_SHIFT                       18
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       0x300000u
+#define SPI_CTAR_PASC_SHIFT                      20
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     0xC00000u
+#define SPI_CTAR_PCSSCK_SHIFT                    22
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      0x1000000u
+#define SPI_CTAR_LSBFE_SHIFT                     24
+#define SPI_CTAR_CPHA_MASK                       0x2000000u
+#define SPI_CTAR_CPHA_SHIFT                      25
+#define SPI_CTAR_CPOL_MASK                       0x4000000u
+#define SPI_CTAR_CPOL_SHIFT                      26
+#define SPI_CTAR_FMSZ_MASK                       0x78000000u
+#define SPI_CTAR_FMSZ_SHIFT                      27
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        0x80000000u
+#define SPI_CTAR_DBR_SHIFT                       31
+/* CTAR_SLAVE Bit Fields */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 0x2000000u
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                25
+#define SPI_CTAR_SLAVE_CPOL_MASK                 0x4000000u
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                26
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 0xF8000000u
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                27
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
+/* SR Bit Fields */
+#define SPI_SR_POPNXTPTR_MASK                    0xFu
+#define SPI_SR_POPNXTPTR_SHIFT                   0
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        0xF0u
+#define SPI_SR_RXCTR_SHIFT                       4
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     0xF00u
+#define SPI_SR_TXNXTPTR_SHIFT                    8
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        0xF000u
+#define SPI_SR_TXCTR_SHIFT                       12
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         0x20000u
+#define SPI_SR_RFDF_SHIFT                        17
+#define SPI_SR_RFOF_MASK                         0x80000u
+#define SPI_SR_RFOF_SHIFT                        19
+#define SPI_SR_TFFF_MASK                         0x2000000u
+#define SPI_SR_TFFF_SHIFT                        25
+#define SPI_SR_TFUF_MASK                         0x8000000u
+#define SPI_SR_TFUF_SHIFT                        27
+#define SPI_SR_EOQF_MASK                         0x10000000u
+#define SPI_SR_EOQF_SHIFT                        28
+#define SPI_SR_TXRXS_MASK                        0x40000000u
+#define SPI_SR_TXRXS_SHIFT                       30
+#define SPI_SR_TCF_MASK                          0x80000000u
+#define SPI_SR_TCF_SHIFT                         31
+/* RSER Bit Fields */
+#define SPI_RSER_RFDF_DIRS_MASK                  0x10000u
+#define SPI_RSER_RFDF_DIRS_SHIFT                 16
+#define SPI_RSER_RFDF_RE_MASK                    0x20000u
+#define SPI_RSER_RFDF_RE_SHIFT                   17
+#define SPI_RSER_RFOF_RE_MASK                    0x80000u
+#define SPI_RSER_RFOF_RE_SHIFT                   19
+#define SPI_RSER_TFFF_DIRS_MASK                  0x1000000u
+#define SPI_RSER_TFFF_DIRS_SHIFT                 24
+#define SPI_RSER_TFFF_RE_MASK                    0x2000000u
+#define SPI_RSER_TFFF_RE_SHIFT                   25
+#define SPI_RSER_TFUF_RE_MASK                    0x8000000u
+#define SPI_RSER_TFUF_RE_SHIFT                   27
+#define SPI_RSER_EOQF_RE_MASK                    0x10000000u
+#define SPI_RSER_EOQF_RE_SHIFT                   28
+#define SPI_RSER_TCF_RE_MASK                     0x80000000u
+#define SPI_RSER_TCF_RE_SHIFT                    31
+/* PUSHR Bit Fields */
+#define SPI_PUSHR_TXDATA_MASK                    0xFFFFu
+#define SPI_PUSHR_TXDATA_SHIFT                   0
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       0x3F0000u
+#define SPI_PUSHR_PCS_SHIFT                      16
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     0x4000000u
+#define SPI_PUSHR_CTCNT_SHIFT                    26
+#define SPI_PUSHR_EOQ_MASK                       0x8000000u
+#define SPI_PUSHR_EOQ_SHIFT                      27
+#define SPI_PUSHR_CTAS_MASK                      0x70000000u
+#define SPI_PUSHR_CTAS_SHIFT                     28
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      0x80000000u
+#define SPI_PUSHR_CONT_SHIFT                     31
+/* PUSHR_SLAVE Bit Fields */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              0xFFFFFFFFu
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             0
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
+/* POPR Bit Fields */
+#define SPI_POPR_RXDATA_MASK                     0xFFFFFFFFu
+#define SPI_POPR_RXDATA_SHIFT                    0
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
+/* TXFR0 Bit Fields */
+#define SPI_TXFR0_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR0_TXDATA_SHIFT                   0
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
+/* TXFR1 Bit Fields */
+#define SPI_TXFR1_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR1_TXDATA_SHIFT                   0
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
+/* TXFR2 Bit Fields */
+#define SPI_TXFR2_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR2_TXDATA_SHIFT                   0
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
+/* TXFR3 Bit Fields */
+#define SPI_TXFR3_TXDATA_MASK                    0xFFFFu
+#define SPI_TXFR3_TXDATA_SHIFT                   0
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              0xFFFF0000u
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             16
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
+/* RXFR0 Bit Fields */
+#define SPI_RXFR0_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR0_RXDATA_SHIFT                   0
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
+/* RXFR1 Bit Fields */
+#define SPI_RXFR1_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR1_RXDATA_SHIFT                   0
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
+/* RXFR2 Bit Fields */
+#define SPI_RXFR2_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR2_RXDATA_SHIFT                   0
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
+/* RXFR3 Bit Fields */
+#define SPI_RXFR3_RXDATA_MASK                    0xFFFFFFFFu
+#define SPI_RXFR3_RXDATA_SHIFT                   0
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
+
+/*! \} */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/*! Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/*! Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/*! Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/*! Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/*! Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/*! Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+
+/*! \} */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TSI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer */
+/*! \{ */
+
+/*! TSI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GENCS;                             /*!< General Control and Status Register, offset: 0x0 */
+  __IO uint32_t SCANC;                             /*!< SCAN control register, offset: 0x4 */
+  __IO uint32_t PEN;                               /*!< Pin enable register, offset: 0x8 */
+  __IO uint32_t STATUS;                            /*!< Status Register, offset: 0xC */
+       uint8_t RESERVED_0[240];
+  __I  uint32_t CNTR1;                             /*!< Counter Register, offset: 0x100 */
+  __I  uint32_t CNTR3;                             /*!< Counter Register, offset: 0x104 */
+  __I  uint32_t CNTR5;                             /*!< Counter Register, offset: 0x108 */
+  __I  uint32_t CNTR7;                             /*!< Counter Register, offset: 0x10C */
+  __I  uint32_t CNTR9;                             /*!< Counter Register, offset: 0x110 */
+  __I  uint32_t CNTR11;                            /*!< Counter Register, offset: 0x114 */
+  __I  uint32_t CNTR13;                            /*!< Counter Register, offset: 0x118 */
+  __I  uint32_t CNTR15;                            /*!< Counter Register, offset: 0x11C */
+  __IO uint32_t THRESHLD[16];                      /*!< Channel n threshold register, array offset: 0x120, array step: 0x4 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TSI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup TSI_Register_Masks TSI Register Masks */
+/*! \{ */
+
+/* GENCS Bit Fields */
+#define TSI_GENCS_STPE_MASK                      0x1u
+#define TSI_GENCS_STPE_SHIFT                     0
+#define TSI_GENCS_STM_MASK                       0x2u
+#define TSI_GENCS_STM_SHIFT                      1
+#define TSI_GENCS_ESOR_MASK                      0x10u
+#define TSI_GENCS_ESOR_SHIFT                     4
+#define TSI_GENCS_ERIE_MASK                      0x20u
+#define TSI_GENCS_ERIE_SHIFT                     5
+#define TSI_GENCS_TSIIE_MASK                     0x40u
+#define TSI_GENCS_TSIIE_SHIFT                    6
+#define TSI_GENCS_TSIEN_MASK                     0x80u
+#define TSI_GENCS_TSIEN_SHIFT                    7
+#define TSI_GENCS_SWTS_MASK                      0x100u
+#define TSI_GENCS_SWTS_SHIFT                     8
+#define TSI_GENCS_SCNIP_MASK                     0x200u
+#define TSI_GENCS_SCNIP_SHIFT                    9
+#define TSI_GENCS_OVRF_MASK                      0x1000u
+#define TSI_GENCS_OVRF_SHIFT                     12
+#define TSI_GENCS_EXTERF_MASK                    0x2000u
+#define TSI_GENCS_EXTERF_SHIFT                   13
+#define TSI_GENCS_OUTRGF_MASK                    0x4000u
+#define TSI_GENCS_OUTRGF_SHIFT                   14
+#define TSI_GENCS_EOSF_MASK                      0x8000u
+#define TSI_GENCS_EOSF_SHIFT                     15
+#define TSI_GENCS_PS_MASK                        0x70000u
+#define TSI_GENCS_PS_SHIFT                       16
+#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
+#define TSI_GENCS_NSCN_MASK                      0xF80000u
+#define TSI_GENCS_NSCN_SHIFT                     19
+#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_LPSCNITV_MASK                  0xF000000u
+#define TSI_GENCS_LPSCNITV_SHIFT                 24
+#define TSI_GENCS_LPSCNITV(x)                    (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_LPSCNITV_SHIFT))&TSI_GENCS_LPSCNITV_MASK)
+#define TSI_GENCS_LPCLKS_MASK                    0x10000000u
+#define TSI_GENCS_LPCLKS_SHIFT                   28
+/* SCANC Bit Fields */
+#define TSI_SCANC_AMPSC_MASK                     0x7u
+#define TSI_SCANC_AMPSC_SHIFT                    0
+#define TSI_SCANC_AMPSC(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMPSC_SHIFT))&TSI_SCANC_AMPSC_MASK)
+#define TSI_SCANC_AMCLKS_MASK                    0x18u
+#define TSI_SCANC_AMCLKS_SHIFT                   3
+#define TSI_SCANC_AMCLKS(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_AMCLKS_SHIFT))&TSI_SCANC_AMCLKS_MASK)
+#define TSI_SCANC_AMCLKDIV_MASK                  0x20u
+#define TSI_SCANC_AMCLKDIV_SHIFT                 5
+#define TSI_SCANC_SMOD_MASK                      0xFF00u
+#define TSI_SCANC_SMOD_SHIFT                     8
+#define TSI_SCANC_SMOD(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_SMOD_SHIFT))&TSI_SCANC_SMOD_MASK)
+#define TSI_SCANC_DELVOL_MASK                    0x70000u
+#define TSI_SCANC_DELVOL_SHIFT                   16
+#define TSI_SCANC_DELVOL(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_DELVOL_SHIFT))&TSI_SCANC_DELVOL_MASK)
+#define TSI_SCANC_EXTCHRG_MASK                   0xF80000u
+#define TSI_SCANC_EXTCHRG_SHIFT                  19
+#define TSI_SCANC_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_EXTCHRG_SHIFT))&TSI_SCANC_EXTCHRG_MASK)
+#define TSI_SCANC_CAPTRM_MASK                    0x7000000u
+#define TSI_SCANC_CAPTRM_SHIFT                   24
+#define TSI_SCANC_CAPTRM(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_CAPTRM_SHIFT))&TSI_SCANC_CAPTRM_MASK)
+#define TSI_SCANC_REFCHRG_MASK                   0xF8000000u
+#define TSI_SCANC_REFCHRG_SHIFT                  27
+#define TSI_SCANC_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_SCANC_REFCHRG_SHIFT))&TSI_SCANC_REFCHRG_MASK)
+/* PEN Bit Fields */
+#define TSI_PEN_PEN0_MASK                        0x1u
+#define TSI_PEN_PEN0_SHIFT                       0
+#define TSI_PEN_PEN1_MASK                        0x2u
+#define TSI_PEN_PEN1_SHIFT                       1
+#define TSI_PEN_PEN2_MASK                        0x4u
+#define TSI_PEN_PEN2_SHIFT                       2
+#define TSI_PEN_PEN3_MASK                        0x8u
+#define TSI_PEN_PEN3_SHIFT                       3
+#define TSI_PEN_PEN4_MASK                        0x10u
+#define TSI_PEN_PEN4_SHIFT                       4
+#define TSI_PEN_PEN5_MASK                        0x20u
+#define TSI_PEN_PEN5_SHIFT                       5
+#define TSI_PEN_PEN6_MASK                        0x40u
+#define TSI_PEN_PEN6_SHIFT                       6
+#define TSI_PEN_PEN7_MASK                        0x80u
+#define TSI_PEN_PEN7_SHIFT                       7
+#define TSI_PEN_PEN8_MASK                        0x100u
+#define TSI_PEN_PEN8_SHIFT                       8
+#define TSI_PEN_PEN9_MASK                        0x200u
+#define TSI_PEN_PEN9_SHIFT                       9
+#define TSI_PEN_PEN10_MASK                       0x400u
+#define TSI_PEN_PEN10_SHIFT                      10
+#define TSI_PEN_PEN11_MASK                       0x800u
+#define TSI_PEN_PEN11_SHIFT                      11
+#define TSI_PEN_PEN12_MASK                       0x1000u
+#define TSI_PEN_PEN12_SHIFT                      12
+#define TSI_PEN_PEN13_MASK                       0x2000u
+#define TSI_PEN_PEN13_SHIFT                      13
+#define TSI_PEN_PEN14_MASK                       0x4000u
+#define TSI_PEN_PEN14_SHIFT                      14
+#define TSI_PEN_PEN15_MASK                       0x8000u
+#define TSI_PEN_PEN15_SHIFT                      15
+#define TSI_PEN_LPSP_MASK                        0xF0000u
+#define TSI_PEN_LPSP_SHIFT                       16
+#define TSI_PEN_LPSP(x)                          (((uint32_t)(((uint32_t)(x))<<TSI_PEN_LPSP_SHIFT))&TSI_PEN_LPSP_MASK)
+/* STATUS Bit Fields */
+#define TSI_STATUS_ORNGF0_MASK                   0x1u
+#define TSI_STATUS_ORNGF0_SHIFT                  0
+#define TSI_STATUS_ORNGF1_MASK                   0x2u
+#define TSI_STATUS_ORNGF1_SHIFT                  1
+#define TSI_STATUS_ORNGF2_MASK                   0x4u
+#define TSI_STATUS_ORNGF2_SHIFT                  2
+#define TSI_STATUS_ORNGF3_MASK                   0x8u
+#define TSI_STATUS_ORNGF3_SHIFT                  3
+#define TSI_STATUS_ORNGF4_MASK                   0x10u
+#define TSI_STATUS_ORNGF4_SHIFT                  4
+#define TSI_STATUS_ORNGF5_MASK                   0x20u
+#define TSI_STATUS_ORNGF5_SHIFT                  5
+#define TSI_STATUS_ORNGF6_MASK                   0x40u
+#define TSI_STATUS_ORNGF6_SHIFT                  6
+#define TSI_STATUS_ORNGF7_MASK                   0x80u
+#define TSI_STATUS_ORNGF7_SHIFT                  7
+#define TSI_STATUS_ORNGF8_MASK                   0x100u
+#define TSI_STATUS_ORNGF8_SHIFT                  8
+#define TSI_STATUS_ORNGF9_MASK                   0x200u
+#define TSI_STATUS_ORNGF9_SHIFT                  9
+#define TSI_STATUS_ORNGF10_MASK                  0x400u
+#define TSI_STATUS_ORNGF10_SHIFT                 10
+#define TSI_STATUS_ORNGF11_MASK                  0x800u
+#define TSI_STATUS_ORNGF11_SHIFT                 11
+#define TSI_STATUS_ORNGF12_MASK                  0x1000u
+#define TSI_STATUS_ORNGF12_SHIFT                 12
+#define TSI_STATUS_ORNGF13_MASK                  0x2000u
+#define TSI_STATUS_ORNGF13_SHIFT                 13
+#define TSI_STATUS_ORNGF14_MASK                  0x4000u
+#define TSI_STATUS_ORNGF14_SHIFT                 14
+#define TSI_STATUS_ORNGF15_MASK                  0x8000u
+#define TSI_STATUS_ORNGF15_SHIFT                 15
+#define TSI_STATUS_ERROF0_MASK                   0x10000u
+#define TSI_STATUS_ERROF0_SHIFT                  16
+#define TSI_STATUS_ERROF1_MASK                   0x20000u
+#define TSI_STATUS_ERROF1_SHIFT                  17
+#define TSI_STATUS_ERROF2_MASK                   0x40000u
+#define TSI_STATUS_ERROF2_SHIFT                  18
+#define TSI_STATUS_ERROF3_MASK                   0x80000u
+#define TSI_STATUS_ERROF3_SHIFT                  19
+#define TSI_STATUS_ERROF4_MASK                   0x100000u
+#define TSI_STATUS_ERROF4_SHIFT                  20
+#define TSI_STATUS_ERROF5_MASK                   0x200000u
+#define TSI_STATUS_ERROF5_SHIFT                  21
+#define TSI_STATUS_ERROF6_MASK                   0x400000u
+#define TSI_STATUS_ERROF6_SHIFT                  22
+#define TSI_STATUS_ERROF7_MASK                   0x800000u
+#define TSI_STATUS_ERROF7_SHIFT                  23
+#define TSI_STATUS_ERROF8_MASK                   0x1000000u
+#define TSI_STATUS_ERROF8_SHIFT                  24
+#define TSI_STATUS_ERROF9_MASK                   0x2000000u
+#define TSI_STATUS_ERROF9_SHIFT                  25
+#define TSI_STATUS_ERROF10_MASK                  0x4000000u
+#define TSI_STATUS_ERROF10_SHIFT                 26
+#define TSI_STATUS_ERROF11_MASK                  0x8000000u
+#define TSI_STATUS_ERROF11_SHIFT                 27
+#define TSI_STATUS_ERROF12_MASK                  0x10000000u
+#define TSI_STATUS_ERROF12_SHIFT                 28
+#define TSI_STATUS_ERROF13_MASK                  0x20000000u
+#define TSI_STATUS_ERROF13_SHIFT                 29
+#define TSI_STATUS_ERROF14_MASK                  0x40000000u
+#define TSI_STATUS_ERROF14_SHIFT                 30
+#define TSI_STATUS_ERROF15_MASK                  0x80000000u
+#define TSI_STATUS_ERROF15_SHIFT                 31
+/* CNTR1 Bit Fields */
+#define TSI_CNTR1_CNTN_MASK                      0xFFFFu
+#define TSI_CNTR1_CNTN_SHIFT                     0
+#define TSI_CNTR1_CNTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CNTN_SHIFT))&TSI_CNTR1_CNTN_MASK)
+#define TSI_CNTR1_CNTN1_MASK                     0xFFFF0000u
+#define TSI_CNTR1_CNTN1_SHIFT                    16
+#define TSI_CNTR1_CNTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR1_CNTN1_SHIFT))&TSI_CNTR1_CNTN1_MASK)
+/* CNTR3 Bit Fields */
+#define TSI_CNTR3_CNTN_MASK                      0xFFFFu
+#define TSI_CNTR3_CNTN_SHIFT                     0
+#define TSI_CNTR3_CNTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CNTN_SHIFT))&TSI_CNTR3_CNTN_MASK)
+#define TSI_CNTR3_CNTN1_MASK                     0xFFFF0000u
+#define TSI_CNTR3_CNTN1_SHIFT                    16
+#define TSI_CNTR3_CNTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR3_CNTN1_SHIFT))&TSI_CNTR3_CNTN1_MASK)
+/* CNTR5 Bit Fields */
+#define TSI_CNTR5_CNTN_MASK                      0xFFFFu
+#define TSI_CNTR5_CNTN_SHIFT                     0
+#define TSI_CNTR5_CNTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CNTN_SHIFT))&TSI_CNTR5_CNTN_MASK)
+#define TSI_CNTR5_CNTN1_MASK                     0xFFFF0000u
+#define TSI_CNTR5_CNTN1_SHIFT                    16
+#define TSI_CNTR5_CNTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR5_CNTN1_SHIFT))&TSI_CNTR5_CNTN1_MASK)
+/* CNTR7 Bit Fields */
+#define TSI_CNTR7_CNTN_MASK                      0xFFFFu
+#define TSI_CNTR7_CNTN_SHIFT                     0
+#define TSI_CNTR7_CNTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CNTN_SHIFT))&TSI_CNTR7_CNTN_MASK)
+#define TSI_CNTR7_CNTN1_MASK                     0xFFFF0000u
+#define TSI_CNTR7_CNTN1_SHIFT                    16
+#define TSI_CNTR7_CNTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR7_CNTN1_SHIFT))&TSI_CNTR7_CNTN1_MASK)
+/* CNTR9 Bit Fields */
+#define TSI_CNTR9_CNTN_MASK                      0xFFFFu
+#define TSI_CNTR9_CNTN_SHIFT                     0
+#define TSI_CNTR9_CNTN(x)                        (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CNTN_SHIFT))&TSI_CNTR9_CNTN_MASK)
+#define TSI_CNTR9_CNTN1_MASK                     0xFFFF0000u
+#define TSI_CNTR9_CNTN1_SHIFT                    16
+#define TSI_CNTR9_CNTN1(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR9_CNTN1_SHIFT))&TSI_CNTR9_CNTN1_MASK)
+/* CNTR11 Bit Fields */
+#define TSI_CNTR11_CNTN_MASK                     0xFFFFu
+#define TSI_CNTR11_CNTN_SHIFT                    0
+#define TSI_CNTR11_CNTN(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CNTN_SHIFT))&TSI_CNTR11_CNTN_MASK)
+#define TSI_CNTR11_CNTN1_MASK                    0xFFFF0000u
+#define TSI_CNTR11_CNTN1_SHIFT                   16
+#define TSI_CNTR11_CNTN1(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_CNTR11_CNTN1_SHIFT))&TSI_CNTR11_CNTN1_MASK)
+/* CNTR13 Bit Fields */
+#define TSI_CNTR13_CNTN_MASK                     0xFFFFu
+#define TSI_CNTR13_CNTN_SHIFT                    0
+#define TSI_CNTR13_CNTN(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CNTN_SHIFT))&TSI_CNTR13_CNTN_MASK)
+#define TSI_CNTR13_CNTN1_MASK                    0xFFFF0000u
+#define TSI_CNTR13_CNTN1_SHIFT                   16
+#define TSI_CNTR13_CNTN1(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_CNTR13_CNTN1_SHIFT))&TSI_CNTR13_CNTN1_MASK)
+/* CNTR15 Bit Fields */
+#define TSI_CNTR15_CNTN_MASK                     0xFFFFu
+#define TSI_CNTR15_CNTN_SHIFT                    0
+#define TSI_CNTR15_CNTN(x)                       (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CNTN_SHIFT))&TSI_CNTR15_CNTN_MASK)
+#define TSI_CNTR15_CNTN1_MASK                    0xFFFF0000u
+#define TSI_CNTR15_CNTN1_SHIFT                   16
+#define TSI_CNTR15_CNTN1(x)                      (((uint32_t)(((uint32_t)(x))<<TSI_CNTR15_CNTN1_SHIFT))&TSI_CNTR15_CNTN1_MASK)
+/* THRESHLD Bit Fields */
+#define TSI_THRESHLD_HTHH_MASK                   0xFFFFu
+#define TSI_THRESHLD_HTHH_SHIFT                  0
+#define TSI_THRESHLD_HTHH(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_HTHH_SHIFT))&TSI_THRESHLD_HTHH_MASK)
+#define TSI_THRESHLD_LTHH_MASK                   0xFFFF0000u
+#define TSI_THRESHLD_LTHH_SHIFT                  16
+#define TSI_THRESHLD_LTHH(x)                     (((uint32_t)(((uint32_t)(x))<<TSI_THRESHLD_LTHH_SHIFT))&TSI_THRESHLD_LTHH_MASK)
+
+/*! \} */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/*! Peripheral TSI0 base address */
+#define TSI0_BASE                                (0x40045000u)
+/*! Peripheral TSI0 base pointer */
+#define TSI0                                     ((TSI_Type *)TSI0_BASE)
+
+/*! \} */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer */
+/*! \{ */
+
+/*! UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /*!< UART Baud Rate Registers:High, offset: 0x0 */
+  __IO uint8_t BDL;                                /*!< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /*!< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /*!< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /*!< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /*!< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /*!< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /*!< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /*!< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /*!< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /*!< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /*!< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /*!< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /*!< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /*!< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /*!< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /*!< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /*!< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /*!< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /*!< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /*!< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /*!< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /*!< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /*!< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /*!< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816_T_TYPE0;                     /*!< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816_T_TYPE1;                     /*!< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /*!< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /*!< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /*!< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /*!< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup UART_Register_Masks UART Register Masks */
+/*! \{ */
+
+/* BDH Bit Fields */
+#define UART_BDH_SBR_MASK                        0x1Fu
+#define UART_BDH_SBR_SHIFT                       0
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
+#define UART_BDH_RXEDGIE_MASK                    0x40u
+#define UART_BDH_RXEDGIE_SHIFT                   6
+#define UART_BDH_LBKDIE_MASK                     0x80u
+#define UART_BDH_LBKDIE_SHIFT                    7
+/* BDL Bit Fields */
+#define UART_BDL_SBR_MASK                        0xFFu
+#define UART_BDL_SBR_SHIFT                       0
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
+/* C1 Bit Fields */
+#define UART_C1_PT_MASK                          0x1u
+#define UART_C1_PT_SHIFT                         0
+#define UART_C1_PE_MASK                          0x2u
+#define UART_C1_PE_SHIFT                         1
+#define UART_C1_ILT_MASK                         0x4u
+#define UART_C1_ILT_SHIFT                        2
+#define UART_C1_WAKE_MASK                        0x8u
+#define UART_C1_WAKE_SHIFT                       3
+#define UART_C1_M_MASK                           0x10u
+#define UART_C1_M_SHIFT                          4
+#define UART_C1_RSRC_MASK                        0x20u
+#define UART_C1_RSRC_SHIFT                       5
+#define UART_C1_UARTSWAI_MASK                    0x40u
+#define UART_C1_UARTSWAI_SHIFT                   6
+#define UART_C1_LOOPS_MASK                       0x80u
+#define UART_C1_LOOPS_SHIFT                      7
+/* C2 Bit Fields */
+#define UART_C2_SBK_MASK                         0x1u
+#define UART_C2_SBK_SHIFT                        0
+#define UART_C2_RWU_MASK                         0x2u
+#define UART_C2_RWU_SHIFT                        1
+#define UART_C2_RE_MASK                          0x4u
+#define UART_C2_RE_SHIFT                         2
+#define UART_C2_TE_MASK                          0x8u
+#define UART_C2_TE_SHIFT                         3
+#define UART_C2_ILIE_MASK                        0x10u
+#define UART_C2_ILIE_SHIFT                       4
+#define UART_C2_RIE_MASK                         0x20u
+#define UART_C2_RIE_SHIFT                        5
+#define UART_C2_TCIE_MASK                        0x40u
+#define UART_C2_TCIE_SHIFT                       6
+#define UART_C2_TIE_MASK                         0x80u
+#define UART_C2_TIE_SHIFT                        7
+/* S1 Bit Fields */
+#define UART_S1_PF_MASK                          0x1u
+#define UART_S1_PF_SHIFT                         0
+#define UART_S1_FE_MASK                          0x2u
+#define UART_S1_FE_SHIFT                         1
+#define UART_S1_NF_MASK                          0x4u
+#define UART_S1_NF_SHIFT                         2
+#define UART_S1_OR_MASK                          0x8u
+#define UART_S1_OR_SHIFT                         3
+#define UART_S1_IDLE_MASK                        0x10u
+#define UART_S1_IDLE_SHIFT                       4
+#define UART_S1_RDRF_MASK                        0x20u
+#define UART_S1_RDRF_SHIFT                       5
+#define UART_S1_TC_MASK                          0x40u
+#define UART_S1_TC_SHIFT                         6
+#define UART_S1_TDRE_MASK                        0x80u
+#define UART_S1_TDRE_SHIFT                       7
+/* S2 Bit Fields */
+#define UART_S2_RAF_MASK                         0x1u
+#define UART_S2_RAF_SHIFT                        0
+#define UART_S2_LBKDE_MASK                       0x2u
+#define UART_S2_LBKDE_SHIFT                      1
+#define UART_S2_BRK13_MASK                       0x4u
+#define UART_S2_BRK13_SHIFT                      2
+#define UART_S2_RWUID_MASK                       0x8u
+#define UART_S2_RWUID_SHIFT                      3
+#define UART_S2_RXINV_MASK                       0x10u
+#define UART_S2_RXINV_SHIFT                      4
+#define UART_S2_MSBF_MASK                        0x20u
+#define UART_S2_MSBF_SHIFT                       5
+#define UART_S2_RXEDGIF_MASK                     0x40u
+#define UART_S2_RXEDGIF_SHIFT                    6
+#define UART_S2_LBKDIF_MASK                      0x80u
+#define UART_S2_LBKDIF_SHIFT                     7
+/* C3 Bit Fields */
+#define UART_C3_PEIE_MASK                        0x1u
+#define UART_C3_PEIE_SHIFT                       0
+#define UART_C3_FEIE_MASK                        0x2u
+#define UART_C3_FEIE_SHIFT                       1
+#define UART_C3_NEIE_MASK                        0x4u
+#define UART_C3_NEIE_SHIFT                       2
+#define UART_C3_ORIE_MASK                        0x8u
+#define UART_C3_ORIE_SHIFT                       3
+#define UART_C3_TXINV_MASK                       0x10u
+#define UART_C3_TXINV_SHIFT                      4
+#define UART_C3_TXDIR_MASK                       0x20u
+#define UART_C3_TXDIR_SHIFT                      5
+#define UART_C3_T8_MASK                          0x40u
+#define UART_C3_T8_SHIFT                         6
+#define UART_C3_R8_MASK                          0x80u
+#define UART_C3_R8_SHIFT                         7
+/* D Bit Fields */
+#define UART_D_RT_MASK                           0xFFu
+#define UART_D_RT_SHIFT                          0
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
+/* MA1 Bit Fields */
+#define UART_MA1_MA_MASK                         0xFFu
+#define UART_MA1_MA_SHIFT                        0
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
+/* MA2 Bit Fields */
+#define UART_MA2_MA_MASK                         0xFFu
+#define UART_MA2_MA_SHIFT                        0
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
+/* C4 Bit Fields */
+#define UART_C4_BRFA_MASK                        0x1Fu
+#define UART_C4_BRFA_SHIFT                       0
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         0x20u
+#define UART_C4_M10_SHIFT                        5
+#define UART_C4_MAEN2_MASK                       0x40u
+#define UART_C4_MAEN2_SHIFT                      6
+#define UART_C4_MAEN1_MASK                       0x80u
+#define UART_C4_MAEN1_SHIFT                      7
+/* C5 Bit Fields */
+#define UART_C5_RDMAS_MASK                       0x20u
+#define UART_C5_RDMAS_SHIFT                      5
+#define UART_C5_TDMAS_MASK                       0x80u
+#define UART_C5_TDMAS_SHIFT                      7
+/* ED Bit Fields */
+#define UART_ED_PARITYE_MASK                     0x40u
+#define UART_ED_PARITYE_SHIFT                    6
+#define UART_ED_NOISY_MASK                       0x80u
+#define UART_ED_NOISY_SHIFT                      7
+/* MODEM Bit Fields */
+#define UART_MODEM_TXCTSE_MASK                   0x1u
+#define UART_MODEM_TXCTSE_SHIFT                  0
+#define UART_MODEM_TXRTSE_MASK                   0x2u
+#define UART_MODEM_TXRTSE_SHIFT                  1
+#define UART_MODEM_TXRTSPOL_MASK                 0x4u
+#define UART_MODEM_TXRTSPOL_SHIFT                2
+#define UART_MODEM_RXRTSE_MASK                   0x8u
+#define UART_MODEM_RXRTSE_SHIFT                  3
+/* IR Bit Fields */
+#define UART_IR_TNP_MASK                         0x3u
+#define UART_IR_TNP_SHIFT                        0
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        0x4u
+#define UART_IR_IREN_SHIFT                       2
+/* PFIFO Bit Fields */
+#define UART_PFIFO_RXFIFOSIZE_MASK               0x7u
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              0
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     0x8u
+#define UART_PFIFO_RXFE_SHIFT                    3
+#define UART_PFIFO_TXFIFOSIZE_MASK               0x70u
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              4
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     0x80u
+#define UART_PFIFO_TXFE_SHIFT                    7
+/* CFIFO Bit Fields */
+#define UART_CFIFO_RXUFE_MASK                    0x1u
+#define UART_CFIFO_RXUFE_SHIFT                   0
+#define UART_CFIFO_TXOFE_MASK                    0x2u
+#define UART_CFIFO_TXOFE_SHIFT                   1
+#define UART_CFIFO_RXFLUSH_MASK                  0x40u
+#define UART_CFIFO_RXFLUSH_SHIFT                 6
+#define UART_CFIFO_TXFLUSH_MASK                  0x80u
+#define UART_CFIFO_TXFLUSH_SHIFT                 7
+/* SFIFO Bit Fields */
+#define UART_SFIFO_RXUF_MASK                     0x1u
+#define UART_SFIFO_RXUF_SHIFT                    0
+#define UART_SFIFO_TXOF_MASK                     0x2u
+#define UART_SFIFO_TXOF_SHIFT                    1
+#define UART_SFIFO_RXEMPT_MASK                   0x40u
+#define UART_SFIFO_RXEMPT_SHIFT                  6
+#define UART_SFIFO_TXEMPT_MASK                   0x80u
+#define UART_SFIFO_TXEMPT_SHIFT                  7
+/* TWFIFO Bit Fields */
+#define UART_TWFIFO_TXWATER_MASK                 0xFFu
+#define UART_TWFIFO_TXWATER_SHIFT                0
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
+/* TCFIFO Bit Fields */
+#define UART_TCFIFO_TXCOUNT_MASK                 0xFFu
+#define UART_TCFIFO_TXCOUNT_SHIFT                0
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
+/* RWFIFO Bit Fields */
+#define UART_RWFIFO_RXWATER_MASK                 0xFFu
+#define UART_RWFIFO_RXWATER_SHIFT                0
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
+/* RCFIFO Bit Fields */
+#define UART_RCFIFO_RXCOUNT_MASK                 0xFFu
+#define UART_RCFIFO_RXCOUNT_SHIFT                0
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
+/* C7816 Bit Fields */
+#define UART_C7816_ISO_7816E_MASK                0x1u
+#define UART_C7816_ISO_7816E_SHIFT               0
+#define UART_C7816_TTYPE_MASK                    0x2u
+#define UART_C7816_TTYPE_SHIFT                   1
+#define UART_C7816_INIT_MASK                     0x4u
+#define UART_C7816_INIT_SHIFT                    2
+#define UART_C7816_ANACK_MASK                    0x8u
+#define UART_C7816_ANACK_SHIFT                   3
+#define UART_C7816_ONACK_MASK                    0x10u
+#define UART_C7816_ONACK_SHIFT                   4
+/* IE7816 Bit Fields */
+#define UART_IE7816_RXTE_MASK                    0x1u
+#define UART_IE7816_RXTE_SHIFT                   0
+#define UART_IE7816_TXTE_MASK                    0x2u
+#define UART_IE7816_TXTE_SHIFT                   1
+#define UART_IE7816_GTVE_MASK                    0x4u
+#define UART_IE7816_GTVE_SHIFT                   2
+#define UART_IE7816_INITDE_MASK                  0x10u
+#define UART_IE7816_INITDE_SHIFT                 4
+#define UART_IE7816_BWTE_MASK                    0x20u
+#define UART_IE7816_BWTE_SHIFT                   5
+#define UART_IE7816_CWTE_MASK                    0x40u
+#define UART_IE7816_CWTE_SHIFT                   6
+#define UART_IE7816_WTE_MASK                     0x80u
+#define UART_IE7816_WTE_SHIFT                    7
+/* IS7816 Bit Fields */
+#define UART_IS7816_RXT_MASK                     0x1u
+#define UART_IS7816_RXT_SHIFT                    0
+#define UART_IS7816_TXT_MASK                     0x2u
+#define UART_IS7816_TXT_SHIFT                    1
+#define UART_IS7816_GTV_MASK                     0x4u
+#define UART_IS7816_GTV_SHIFT                    2
+#define UART_IS7816_INITD_MASK                   0x10u
+#define UART_IS7816_INITD_SHIFT                  4
+#define UART_IS7816_BWT_MASK                     0x20u
+#define UART_IS7816_BWT_SHIFT                    5
+#define UART_IS7816_CWT_MASK                     0x40u
+#define UART_IS7816_CWT_SHIFT                    6
+#define UART_IS7816_WT_MASK                      0x80u
+#define UART_IS7816_WT_SHIFT                     7
+/* WP7816_T_TYPE0 Bit Fields */
+#define UART_WP7816_T_TYPE0_WI_MASK              0xFFu
+#define UART_WP7816_T_TYPE0_WI_SHIFT             0
+#define UART_WP7816_T_TYPE0_WI(x)                (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE0_WI_SHIFT))&UART_WP7816_T_TYPE0_WI_MASK)
+/* WP7816_T_TYPE1 Bit Fields */
+#define UART_WP7816_T_TYPE1_BWI_MASK             0xFu
+#define UART_WP7816_T_TYPE1_BWI_SHIFT            0
+#define UART_WP7816_T_TYPE1_BWI(x)               (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_BWI_SHIFT))&UART_WP7816_T_TYPE1_BWI_MASK)
+#define UART_WP7816_T_TYPE1_CWI_MASK             0xF0u
+#define UART_WP7816_T_TYPE1_CWI_SHIFT            4
+#define UART_WP7816_T_TYPE1_CWI(x)               (((uint8_t)(((uint8_t)(x))<<UART_WP7816_T_TYPE1_CWI_SHIFT))&UART_WP7816_T_TYPE1_CWI_MASK)
+/* WN7816 Bit Fields */
+#define UART_WN7816_GTN_MASK                     0xFFu
+#define UART_WN7816_GTN_SHIFT                    0
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
+/* WF7816 Bit Fields */
+#define UART_WF7816_GTFD_MASK                    0xFFu
+#define UART_WF7816_GTFD_SHIFT                   0
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
+/* ET7816 Bit Fields */
+#define UART_ET7816_RXTHRESHOLD_MASK             0xFu
+#define UART_ET7816_RXTHRESHOLD_SHIFT            0
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             0xF0u
+#define UART_ET7816_TXTHRESHOLD_SHIFT            4
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
+/* TL7816 Bit Fields */
+#define UART_TL7816_TLEN_MASK                    0xFFu
+#define UART_TL7816_TLEN_SHIFT                   0
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
+
+/*! \} */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/*! Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/*! Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+/*! Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/*! Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+/*! Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/*! Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+/*! Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/*! Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+/*! Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/*! Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+/*! Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/*! Peripheral UART5 base pointer */
+#define UART5                                    ((UART_Type *)UART5_BASE)
+
+/*! \} */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer */
+/*! \{ */
+
+/*! USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /*!< Peripheral ID Register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /*!< Peripheral ID Complement Register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /*!< Peripheral Revision Register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /*!< Peripheral Additional Info Register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /*!< OTG Interrupt Status Register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /*!< OTG Interrupt Control Register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /*!< OTG Status Register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /*!< OTG Control Register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /*!< Interrupt Status Register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /*!< Interrupt Enable Register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /*!< Error Interrupt Status Register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /*!< Error Interrupt Enable Register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /*!< Status Register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /*!< Control Register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /*!< Address Register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /*!< BDT Page Register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /*!< Frame Number Register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /*!< Frame Number Register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /*!< Token Register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /*!< SOF Threshold Register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /*!< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /*!< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /*!< Endpoint Control Register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /*!< USB Control Register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /*!< USB OTG Observe Register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /*!< USB OTG Control Register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /*!< USB Transceiver Control Register 0, offset: 0x10C */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup USB_Register_Masks USB Register Masks */
+/*! \{ */
+
+/* PERID Bit Fields */
+#define USB_PERID_ID_MASK                        0x3Fu
+#define USB_PERID_ID_SHIFT                       0
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
+/* IDCOMP Bit Fields */
+#define USB_IDCOMP_NID_MASK                      0x3Fu
+#define USB_IDCOMP_NID_SHIFT                     0
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
+/* REV Bit Fields */
+#define USB_REV_REV_MASK                         0xFFu
+#define USB_REV_REV_SHIFT                        0
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
+/* ADDINFO Bit Fields */
+#define USB_ADDINFO_IEHOST_MASK                  0x1u
+#define USB_ADDINFO_IEHOST_SHIFT                 0
+#define USB_ADDINFO_IRQNUM_MASK                  0xF8u
+#define USB_ADDINFO_IRQNUM_SHIFT                 3
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
+/* OTGISTAT Bit Fields */
+#define USB_OTGISTAT_AVBUSCHG_MASK               0x1u
+#define USB_OTGISTAT_AVBUSCHG_SHIFT              0
+#define USB_OTGISTAT_B_SESS_CHG_MASK             0x4u
+#define USB_OTGISTAT_B_SESS_CHG_SHIFT            2
+#define USB_OTGISTAT_SESSVLDCHG_MASK             0x8u
+#define USB_OTGISTAT_SESSVLDCHG_SHIFT            3
+#define USB_OTGISTAT_LINE_STATE_CHG_MASK         0x20u
+#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT        5
+#define USB_OTGISTAT_ONEMSEC_MASK                0x40u
+#define USB_OTGISTAT_ONEMSEC_SHIFT               6
+#define USB_OTGISTAT_IDCHG_MASK                  0x80u
+#define USB_OTGISTAT_IDCHG_SHIFT                 7
+/* OTGICR Bit Fields */
+#define USB_OTGICR_AVBUSEN_MASK                  0x1u
+#define USB_OTGICR_AVBUSEN_SHIFT                 0
+#define USB_OTGICR_BSESSEN_MASK                  0x4u
+#define USB_OTGICR_BSESSEN_SHIFT                 2
+#define USB_OTGICR_SESSVLDEN_MASK                0x8u
+#define USB_OTGICR_SESSVLDEN_SHIFT               3
+#define USB_OTGICR_LINESTATEEN_MASK              0x20u
+#define USB_OTGICR_LINESTATEEN_SHIFT             5
+#define USB_OTGICR_ONEMSECEN_MASK                0x40u
+#define USB_OTGICR_ONEMSECEN_SHIFT               6
+#define USB_OTGICR_IDEN_MASK                     0x80u
+#define USB_OTGICR_IDEN_SHIFT                    7
+/* OTGSTAT Bit Fields */
+#define USB_OTGSTAT_AVBUSVLD_MASK                0x1u
+#define USB_OTGSTAT_AVBUSVLD_SHIFT               0
+#define USB_OTGSTAT_BSESSEND_MASK                0x4u
+#define USB_OTGSTAT_BSESSEND_SHIFT               2
+#define USB_OTGSTAT_SESS_VLD_MASK                0x8u
+#define USB_OTGSTAT_SESS_VLD_SHIFT               3
+#define USB_OTGSTAT_LINESTATESTABLE_MASK         0x20u
+#define USB_OTGSTAT_LINESTATESTABLE_SHIFT        5
+#define USB_OTGSTAT_ONEMSECEN_MASK               0x40u
+#define USB_OTGSTAT_ONEMSECEN_SHIFT              6
+#define USB_OTGSTAT_ID_MASK                      0x80u
+#define USB_OTGSTAT_ID_SHIFT                     7
+/* OTGCTL Bit Fields */
+#define USB_OTGCTL_OTGEN_MASK                    0x4u
+#define USB_OTGCTL_OTGEN_SHIFT                   2
+#define USB_OTGCTL_DMLOW_MASK                    0x10u
+#define USB_OTGCTL_DMLOW_SHIFT                   4
+#define USB_OTGCTL_DPLOW_MASK                    0x20u
+#define USB_OTGCTL_DPLOW_SHIFT                   5
+#define USB_OTGCTL_DPHIGH_MASK                   0x80u
+#define USB_OTGCTL_DPHIGH_SHIFT                  7
+/* ISTAT Bit Fields */
+#define USB_ISTAT_USBRST_MASK                    0x1u
+#define USB_ISTAT_USBRST_SHIFT                   0
+#define USB_ISTAT_ERROR_MASK                     0x2u
+#define USB_ISTAT_ERROR_SHIFT                    1
+#define USB_ISTAT_SOFTOK_MASK                    0x4u
+#define USB_ISTAT_SOFTOK_SHIFT                   2
+#define USB_ISTAT_TOKDNE_MASK                    0x8u
+#define USB_ISTAT_TOKDNE_SHIFT                   3
+#define USB_ISTAT_SLEEP_MASK                     0x10u
+#define USB_ISTAT_SLEEP_SHIFT                    4
+#define USB_ISTAT_RESUME_MASK                    0x20u
+#define USB_ISTAT_RESUME_SHIFT                   5
+#define USB_ISTAT_ATTACH_MASK                    0x40u
+#define USB_ISTAT_ATTACH_SHIFT                   6
+#define USB_ISTAT_STALL_MASK                     0x80u
+#define USB_ISTAT_STALL_SHIFT                    7
+/* INTEN Bit Fields */
+#define USB_INTEN_USBRSTEN_MASK                  0x1u
+#define USB_INTEN_USBRSTEN_SHIFT                 0
+#define USB_INTEN_ERROREN_MASK                   0x2u
+#define USB_INTEN_ERROREN_SHIFT                  1
+#define USB_INTEN_SOFTOKEN_MASK                  0x4u
+#define USB_INTEN_SOFTOKEN_SHIFT                 2
+#define USB_INTEN_TOKDNEEN_MASK                  0x8u
+#define USB_INTEN_TOKDNEEN_SHIFT                 3
+#define USB_INTEN_SLEEPEN_MASK                   0x10u
+#define USB_INTEN_SLEEPEN_SHIFT                  4
+#define USB_INTEN_RESUMEEN_MASK                  0x20u
+#define USB_INTEN_RESUMEEN_SHIFT                 5
+#define USB_INTEN_ATTACHEN_MASK                  0x40u
+#define USB_INTEN_ATTACHEN_SHIFT                 6
+#define USB_INTEN_STALLEN_MASK                   0x80u
+#define USB_INTEN_STALLEN_SHIFT                  7
+/* ERRSTAT Bit Fields */
+#define USB_ERRSTAT_PIDERR_MASK                  0x1u
+#define USB_ERRSTAT_PIDERR_SHIFT                 0
+#define USB_ERRSTAT_CRC5EOF_MASK                 0x2u
+#define USB_ERRSTAT_CRC5EOF_SHIFT                1
+#define USB_ERRSTAT_CRC16_MASK                   0x4u
+#define USB_ERRSTAT_CRC16_SHIFT                  2
+#define USB_ERRSTAT_DFN8_MASK                    0x8u
+#define USB_ERRSTAT_DFN8_SHIFT                   3
+#define USB_ERRSTAT_BTOERR_MASK                  0x10u
+#define USB_ERRSTAT_BTOERR_SHIFT                 4
+#define USB_ERRSTAT_DMAERR_MASK                  0x20u
+#define USB_ERRSTAT_DMAERR_SHIFT                 5
+#define USB_ERRSTAT_BTSERR_MASK                  0x80u
+#define USB_ERRSTAT_BTSERR_SHIFT                 7
+/* ERREN Bit Fields */
+#define USB_ERREN_PIDERREN_MASK                  0x1u
+#define USB_ERREN_PIDERREN_SHIFT                 0
+#define USB_ERREN_CRC5EOFEN_MASK                 0x2u
+#define USB_ERREN_CRC5EOFEN_SHIFT                1
+#define USB_ERREN_CRC16EN_MASK                   0x4u
+#define USB_ERREN_CRC16EN_SHIFT                  2
+#define USB_ERREN_DFN8EN_MASK                    0x8u
+#define USB_ERREN_DFN8EN_SHIFT                   3
+#define USB_ERREN_BTOERREN_MASK                  0x10u
+#define USB_ERREN_BTOERREN_SHIFT                 4
+#define USB_ERREN_DMAERREN_MASK                  0x20u
+#define USB_ERREN_DMAERREN_SHIFT                 5
+#define USB_ERREN_BTSERREN_MASK                  0x80u
+#define USB_ERREN_BTSERREN_SHIFT                 7
+/* STAT Bit Fields */
+#define USB_STAT_ODD_MASK                        0x4u
+#define USB_STAT_ODD_SHIFT                       2
+#define USB_STAT_TX_MASK                         0x8u
+#define USB_STAT_TX_SHIFT                        3
+#define USB_STAT_ENDP_MASK                       0xF0u
+#define USB_STAT_ENDP_SHIFT                      4
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
+/* CTL Bit Fields */
+#define USB_CTL_USBENSOFEN_MASK                  0x1u
+#define USB_CTL_USBENSOFEN_SHIFT                 0
+#define USB_CTL_ODDRST_MASK                      0x2u
+#define USB_CTL_ODDRST_SHIFT                     1
+#define USB_CTL_RESUME_MASK                      0x4u
+#define USB_CTL_RESUME_SHIFT                     2
+#define USB_CTL_HOSTMODEEN_MASK                  0x8u
+#define USB_CTL_HOSTMODEEN_SHIFT                 3
+#define USB_CTL_RESET_MASK                       0x10u
+#define USB_CTL_RESET_SHIFT                      4
+#define USB_CTL_TXSUSPENDTOKENBUSY_MASK          0x20u
+#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT         5
+#define USB_CTL_SE0_MASK                         0x40u
+#define USB_CTL_SE0_SHIFT                        6
+#define USB_CTL_JSTATE_MASK                      0x80u
+#define USB_CTL_JSTATE_SHIFT                     7
+/* ADDR Bit Fields */
+#define USB_ADDR_ADDR_MASK                       0x7Fu
+#define USB_ADDR_ADDR_SHIFT                      0
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN_MASK                       0x80u
+#define USB_ADDR_LSEN_SHIFT                      7
+/* BDTPAGE1 Bit Fields */
+#define USB_BDTPAGE1_BDTBA_MASK                  0xFEu
+#define USB_BDTPAGE1_BDTBA_SHIFT                 1
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
+/* FRMNUML Bit Fields */
+#define USB_FRMNUML_FRM_MASK                     0xFFu
+#define USB_FRMNUML_FRM_SHIFT                    0
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
+/* FRMNUMH Bit Fields */
+#define USB_FRMNUMH_FRM_MASK                     0x7u
+#define USB_FRMNUMH_FRM_SHIFT                    0
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
+/* TOKEN Bit Fields */
+#define USB_TOKEN_TOKENENDPT_MASK                0xFu
+#define USB_TOKEN_TOKENENDPT_SHIFT               0
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  0xF0u
+#define USB_TOKEN_TOKENPID_SHIFT                 4
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
+/* SOFTHLD Bit Fields */
+#define USB_SOFTHLD_CNT_MASK                     0xFFu
+#define USB_SOFTHLD_CNT_SHIFT                    0
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
+/* BDTPAGE2 Bit Fields */
+#define USB_BDTPAGE2_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE2_BDTBA_SHIFT                 0
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
+/* BDTPAGE3 Bit Fields */
+#define USB_BDTPAGE3_BDTBA_MASK                  0xFFu
+#define USB_BDTPAGE3_BDTBA_SHIFT                 0
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
+/* ENDPT Bit Fields */
+#define USB_ENDPT_EPHSHK_MASK                    0x1u
+#define USB_ENDPT_EPHSHK_SHIFT                   0
+#define USB_ENDPT_EPSTALL_MASK                   0x2u
+#define USB_ENDPT_EPSTALL_SHIFT                  1
+#define USB_ENDPT_EPTXEN_MASK                    0x4u
+#define USB_ENDPT_EPTXEN_SHIFT                   2
+#define USB_ENDPT_EPRXEN_MASK                    0x8u
+#define USB_ENDPT_EPRXEN_SHIFT                   3
+#define USB_ENDPT_EPCTLDIS_MASK                  0x10u
+#define USB_ENDPT_EPCTLDIS_SHIFT                 4
+#define USB_ENDPT_RETRYDIS_MASK                  0x40u
+#define USB_ENDPT_RETRYDIS_SHIFT                 6
+#define USB_ENDPT_HOSTWOHUB_MASK                 0x80u
+#define USB_ENDPT_HOSTWOHUB_SHIFT                7
+/* USBCTRL Bit Fields */
+#define USB_USBCTRL_PDE_MASK                     0x40u
+#define USB_USBCTRL_PDE_SHIFT                    6
+#define USB_USBCTRL_SUSP_MASK                    0x80u
+#define USB_USBCTRL_SUSP_SHIFT                   7
+/* OBSERVE Bit Fields */
+#define USB_OBSERVE_DMPD_MASK                    0x10u
+#define USB_OBSERVE_DMPD_SHIFT                   4
+#define USB_OBSERVE_DPPD_MASK                    0x40u
+#define USB_OBSERVE_DPPD_SHIFT                   6
+#define USB_OBSERVE_DPPU_MASK                    0x80u
+#define USB_OBSERVE_DPPU_SHIFT                   7
+/* CONTROL Bit Fields */
+#define USB_CONTROL_DPPULLUPNONOTG_MASK          0x10u
+#define USB_CONTROL_DPPULLUPNONOTG_SHIFT         4
+/* USBTRC0 Bit Fields */
+#define USB_USBTRC0_USB_RESUME_INT_MASK          0x1u
+#define USB_USBTRC0_USB_RESUME_INT_SHIFT         0
+#define USB_USBTRC0_SYNC_DET_MASK                0x2u
+#define USB_USBTRC0_SYNC_DET_SHIFT               1
+#define USB_USBTRC0_USBRESMEN_MASK               0x20u
+#define USB_USBTRC0_USBRESMEN_SHIFT              5
+#define USB_USBTRC0_USBRESET_MASK                0x80u
+#define USB_USBTRC0_USBRESET_SHIFT               7
+
+/*! \} */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/*! Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/*! Peripheral USB0 base pointer */
+#define USB0                                     ((USB_Type *)USB0_BASE)
+
+/*! \} */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer */
+/*! \{ */
+
+/*! USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /*!< Control Register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /*!< Clock Register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /*!< Status Register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /*!< TIMER0 Register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /*!< , offset: 0x14 */
+  __IO uint32_t TIMER2;                            /*!< , offset: 0x18 */
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup USBDCD_Register_Masks USBDCD Register Masks */
+/*! \{ */
+
+/* CONTROL Bit Fields */
+#define USBDCD_CONTROL_IACK_MASK                 0x1u
+#define USBDCD_CONTROL_IACK_SHIFT                0
+#define USBDCD_CONTROL_IF_MASK                   0x100u
+#define USBDCD_CONTROL_IF_SHIFT                  8
+#define USBDCD_CONTROL_IE_MASK                   0x10000u
+#define USBDCD_CONTROL_IE_SHIFT                  16
+#define USBDCD_CONTROL_START_MASK                0x1000000u
+#define USBDCD_CONTROL_START_SHIFT               24
+#define USBDCD_CONTROL_SR_MASK                   0x2000000u
+#define USBDCD_CONTROL_SR_SHIFT                  25
+/* CLOCK Bit Fields */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             0x1u
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            0
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            0xFFCu
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           2
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
+/* STATUS Bit Fields */
+#define USBDCD_STATUS_SEQ_RES_MASK               0x30000u
+#define USBDCD_STATUS_SEQ_RES_SHIFT              16
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              0xC0000u
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             18
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   0x100000u
+#define USBDCD_STATUS_ERR_SHIFT                  20
+#define USBDCD_STATUS_TO_MASK                    0x200000u
+#define USBDCD_STATUS_TO_SHIFT                   21
+#define USBDCD_STATUS_ACTIVE_MASK                0x400000u
+#define USBDCD_STATUS_ACTIVE_SHIFT               22
+/* TIMER0 Bit Fields */
+#define USBDCD_TIMER0_TUNITCON_MASK              0xFFFu
+#define USBDCD_TIMER0_TUNITCON_SHIFT             0
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             0x3FF0000u
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            16
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
+/* TIMER1 Bit Fields */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            0x3FFu
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           0
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             0x3FF0000u
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            16
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
+/* TIMER2 Bit Fields */
+#define USBDCD_TIMER2_CHECK_DM_MASK              0xFu
+#define USBDCD_TIMER2_CHECK_DM_SHIFT             0
+#define USBDCD_TIMER2_CHECK_DM(x)                (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_CHECK_DM_SHIFT))&USBDCD_TIMER2_CHECK_DM_MASK)
+#define USBDCD_TIMER2_TVDPSRC_CON_MASK           0x3FF0000u
+#define USBDCD_TIMER2_TVDPSRC_CON_SHIFT          16
+#define USBDCD_TIMER2_TVDPSRC_CON(x)             (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_TVDPSRC_CON_MASK)
+
+/*! \} */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/*! Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/*! Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+
+/*! \} */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer */
+/*! \{ */
+
+/*! VREF - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /*!< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup VREF_Register_Masks VREF Register Masks */
+/*! \{ */
+
+/* SC Bit Fields */
+#define VREF_SC_MODE_LV_MASK                     0x3u
+#define VREF_SC_MODE_LV_SHIFT                    0
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      0x4u
+#define VREF_SC_VREFST_SHIFT                     2
+#define VREF_SC_REGEN_MASK                       0x40u
+#define VREF_SC_REGEN_SHIFT                      6
+#define VREF_SC_VREFEN_MASK                      0x80u
+#define VREF_SC_VREFEN_SHIFT                     7
+
+/*! \} */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/*! Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/*! Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+
+/*! \} */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer */
+/*! \{ */
+
+/*! WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /*!< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /*!< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /*!< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /*!< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /*!< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /*!< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /*!< Watchdog Refresh Register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /*!< Watchdog Unlock Register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /*!< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /*!< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /*!< Watchdog Reset Count Register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /*!< Watchdog Prescaler Register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*! \addtogroup WDOG_Register_Masks WDOG Register Masks */
+/*! \{ */
+
+/* STCTRLH Bit Fields */
+#define WDOG_STCTRLH_WDOGEN_MASK                 0x1u
+#define WDOG_STCTRLH_WDOGEN_SHIFT                0
+#define WDOG_STCTRLH_CLKSRC_MASK                 0x2u
+#define WDOG_STCTRLH_CLKSRC_SHIFT                1
+#define WDOG_STCTRLH_IRQRSTEN_MASK               0x4u
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              2
+#define WDOG_STCTRLH_WINEN_MASK                  0x8u
+#define WDOG_STCTRLH_WINEN_SHIFT                 3
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            0x10u
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           4
+#define WDOG_STCTRLH_DBGEN_MASK                  0x20u
+#define WDOG_STCTRLH_DBGEN_SHIFT                 5
+#define WDOG_STCTRLH_STOPEN_MASK                 0x40u
+#define WDOG_STCTRLH_STOPEN_SHIFT                6
+#define WDOG_STCTRLH_WAITEN_MASK                 0x80u
+#define WDOG_STCTRLH_WAITEN_SHIFT                7
+#define WDOG_STCTRLH_STNDBYEN_MASK               0x100u
+#define WDOG_STCTRLH_STNDBYEN_SHIFT              8
+#define WDOG_STCTRLH_TESTWDOG_MASK               0x400u
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              10
+#define WDOG_STCTRLH_TESTSEL_MASK                0x800u
+#define WDOG_STCTRLH_TESTSEL_SHIFT               11
+#define WDOG_STCTRLH_BYTESEL_MASK                0x3000u
+#define WDOG_STCTRLH_BYTESEL_SHIFT               12
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            0x4000u
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           14
+/* STCTRLL Bit Fields */
+#define WDOG_STCTRLL_INTFLG_MASK                 0x8000u
+#define WDOG_STCTRLL_INTFLG_SHIFT                15
+/* TOVALH Bit Fields */
+#define WDOG_TOVALH_TOVALHIGH_MASK               0xFFFFu
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              0
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
+/* TOVALL Bit Fields */
+#define WDOG_TOVALL_TOVALLOW_MASK                0xFFFFu
+#define WDOG_TOVALL_TOVALLOW_SHIFT               0
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
+/* WINH Bit Fields */
+#define WDOG_WINH_WINHIGH_MASK                   0xFFFFu
+#define WDOG_WINH_WINHIGH_SHIFT                  0
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
+/* WINL Bit Fields */
+#define WDOG_WINL_WINLOW_MASK                    0xFFFFu
+#define WDOG_WINL_WINLOW_SHIFT                   0
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
+/* REFRESH Bit Fields */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            0xFFFFu
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           0
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
+/* UNLOCK Bit Fields */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              0xFFFFu
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             0
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
+/* TMROUTH Bit Fields */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           0xFFFFu
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          0
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+/* TMROUTL Bit Fields */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            0xFFFFu
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           0
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
+/* RSTCNT Bit Fields */
+#define WDOG_RSTCNT_RSTCNT_MASK                  0xFFFFu
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 0
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
+/* PRESC Bit Fields */
+#define WDOG_PRESC_PRESCVAL_MASK                 0x700u
+#define WDOG_PRESC_PRESCVAL_SHIFT                8
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
+
+/*! \} */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/*! Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/*! Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+
+/*! \} */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*! \} */ /* end of group Peripheral_access_layer */
+
+
+#endif  /* #if !defined(PK40X256VLQ100) */
+
+/* PK40X256VLQ100.h, eof. */

libcpu/arm/PK40X25VLQ100/context_rvds.S

@@ -0,0 +1,176 @@
+;/*
+; * File      : context_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; * 2010-02-04     Magicoe      Edit for LPC17xx Series 
+; * 2010-08-06     Magicoe      Amended for PK40X256VLQ100
+; */
+
+;/**
+; * @addtogroup PK40X256VLQ100
+; */
+;/*@{*/
+
+NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
+NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (3) 
+NVIC_PENDSV_PRI EQU     0x00FF0000               ; PendSV priority value (lowest)
+NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
+
+	AREA |.text|, CODE, READONLY, ALIGN=2
+	THUMB
+	REQUIRE8
+	PRESERVE8
+
+	IMPORT rt_thread_switch_interrput_flag
+	IMPORT rt_interrupt_from_thread
+	IMPORT rt_interrupt_to_thread
+
+;/*
+; * rt_base_t rt_hw_interrupt_disable();
+; */
+rt_hw_interrupt_disable    PROC
+	EXPORT  rt_hw_interrupt_disable
+	MRS		r0, PRIMASK
+	CPSID   I
+	BX		LR
+	ENDP
+
+;/*
+; * void rt_hw_interrupt_enable(rt_base_t level);
+; */
+rt_hw_interrupt_enable    PROC
+	EXPORT  rt_hw_interrupt_enable
+	MSR		PRIMASK, r0
+	BX      LR
+	ENDP
+
+;/*
+; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+; * r0 --> from
+; * r1 --> to
+; */
+rt_hw_context_switch_interrupt
+	EXPORT rt_hw_context_switch_interrupt
+rt_hw_context_switch    PROC
+	EXPORT rt_hw_context_switch
+
+	; set rt_thread_switch_interrput_flag to 1
+	LDR 	r2, =rt_thread_switch_interrput_flag
+	LDR 	r3, [r2]
+	CMP 	r3, #1
+	BEQ 	_reswitch
+	MOV 	r3, #1
+	STR 	r3, [r2]
+
+	LDR 	r2, =rt_interrupt_from_thread	; set rt_interrupt_from_thread
+	STR 	r0, [r2]
+
+_reswitch
+	LDR 	r2, =rt_interrupt_to_thread		; set rt_interrupt_to_thread
+	STR 	r1, [r2]
+
+    LDR     r0, =NVIC_INT_CTRL      		; trigger the PendSV exception (causes context switch)
+    LDR     r1, =NVIC_PENDSVSET
+	STR     r1, [r0]
+	BX      LR
+	ENDP
+
+; r0 --> swith from thread stack
+; r1 --> swith to thread stack
+; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
+rt_hw_pend_sv	PROC
+	EXPORT rt_hw_pend_sv
+
+	; disable interrupt to protect context switch
+	MRS		r2, PRIMASK
+	CPSID   I
+
+	; get rt_thread_switch_interrupt_flag
+	LDR		r0, =rt_thread_switch_interrput_flag
+	LDR		r1, [r0]
+	CBZ		r1, pendsv_exit			; pendsv already handled
+
+	; clear rt_thread_switch_interrput_flag to 0
+	MOV		r1, #0x00
+	STR		r1, [r0]
+
+	LDR		r0, =rt_interrupt_from_thread
+	LDR		r1, [r0]
+	CBZ		r1, swtich_to_thread    ; skip register save at the first time
+
+	MRS     r1, psp                 ; get from thread stack pointer
+	STMFD	r1!, {r4 - r11}			; push r4 - r11 register
+	LDR		r0, [r0]
+	STR		r1, [r0]				; update from thread stack pointer
+
+swtich_to_thread
+	LDR		r1, =rt_interrupt_to_thread
+	LDR		r1, [r1]
+	LDR		r1, [r1]				; load thread stack pointer
+
+	LDMFD	r1!, {r4 - r11}			; pop r4 - r11 register
+	MSR		psp, r1					; update stack pointer
+
+pendsv_exit
+	; restore interrupt
+	MSR		PRIMASK, r2
+
+	ORR     lr, lr, #0x04
+	BX		lr
+	ENDP
+
+;/*
+; * void rt_hw_context_switch_to(rt_uint32 to);
+; * r0 --> to
+; * this fucntion is used to perform the first thread switch
+; */
+rt_hw_context_switch_to    PROC
+	EXPORT rt_hw_context_switch_to
+	; set to thread
+	LDR		r1, =rt_interrupt_to_thread
+	STR		r0, [r1]
+
+	; set from thread to 0
+	LDR		r1, =rt_interrupt_from_thread
+	MOV		r0, #0x0
+	STR		r0, [r1]
+
+	; set interrupt flag to 1
+	LDR 	r1, =rt_thread_switch_interrput_flag
+	MOV 	r0, #1
+	STR 	r0, [r1]
+
+	; set the PendSV exception priority
+    LDR     r0, =NVIC_SYSPRI2
+    LDR     r1, =NVIC_PENDSV_PRI
+	LDR.W   R2, [r0,#0x00]          ; read
+	ORR     r1,r1,r2                ; modify
+    STR     r1, [r0]                ; write-bak
+
+	; trigger the PendSV exception (causes context switch)
+    LDR     r0, =NVIC_INT_CTRL
+    LDR     r1, =NVIC_PENDSVSET
+    STR     r1, [r0]
+
+	; enable interrupts at processor level
+    CPSIE   I
+
+	; never reach here!
+	ENDP
+
+; compatible with old version
+rt_hw_interrupt_thread_switch PROC
+	EXPORT rt_hw_interrupt_thread_switch
+	BX		lr
+	NOP
+	ENDP
+
+	END

libcpu/arm/PK40X25VLQ100/core_cm4.h

@@ -0,0 +1,1265 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V2.02
+ * @date     24. March 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )                   
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M4
+   
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+ 
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+     - Cortex-M SIMD instructions
+ 
+  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease 
+  access to the Cortex-M Core
+ */ 
+
+/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
+  List of Lint messages which will be suppressed and not shown:
+    - not yet checked
+  .
+  Note:  To re-enable a Message, insert a space before 'lint' *
+ 
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core 
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (0x00)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */
+
+
+#if defined ( __CC_ARM   )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined   (  __TASKING__  )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+#include <stdint.h>                      /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+#include "core_cm4_simd.h"               /*!< Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define     __I     volatile           /*!< defines 'read only' permissions                 */
+#else
+  #define     __I     volatile const     /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+*/
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */ 
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];                                   
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];                                    
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];                                   
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];                                   
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];                                   
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];                                  
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;                                               
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x880 (R/W)  Coprocessor access register                           */
+} SCB_Type;                                                
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_VTOR_TBLBASE_Pos               29                                             /*!< SCB VTOR: TBLBASE Position */
+#define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)                  /*!< SCB VTOR: TBLBASE Mask */
+
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)            /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+                                     
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union  
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];                                 
+  __IO uint32_t TER;                     /*!< Offset:       (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];                                  
+  __IO uint32_t TPR;                     /*!< Offset:       (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];                                  
+  __IO uint32_t TCR;                     /*!< Offset:       (R/W)  ITM Trace Control Register                */
+       uint32_t RESERVED3[29];                                  
+  __IO uint32_t IWR;                     /*!< Offset:       (R/W)  ITM Integration Write Register            */
+  __IO uint32_t IRR;                     /*!< Offset:       (R/W)  ITM Integration Read Register             */
+  __IO uint32_t IMCR;                    /*!< Offset:       (R/W)  ITM Integration Mode Control Register     */
+       uint32_t RESERVED4[43];                                  
+  __IO uint32_t LAR;                     /*!< Offset:       (R/W)  ITM Lock Access Register                  */
+  __IO uint32_t LSR;                     /*!< Offset:       (R/W)  ITM Lock Status Register                  */
+       uint32_t RESERVED5[6];                                   
+  __I  uint32_t PID4;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #4 */
+  __I  uint32_t PID5;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #5 */
+  __I  uint32_t PID6;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #6 */
+  __I  uint32_t PID7;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #7 */
+  __I  uint32_t PID0;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #0 */
+  __I  uint32_t PID1;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #1 */
+  __I  uint32_t PID2;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #2 */
+  __I  uint32_t PID3;                    /*!< Offset:       (R/ )  ITM Peripheral Identification Register #3 */
+  __I  uint32_t CID0;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #0 */
+  __I  uint32_t CID1;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #1 */
+  __I  uint32_t CID2;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #2 */
+  __I  uint32_t CID3;                    /*!< Offset:       (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;                                                
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                             /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)                /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                             /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_ATBID_Pos                  16                                             /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_ATBID_Msk                  (0x7FUL << ITM_TCR_ATBID_Pos)                  /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                             /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                             /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3                                             /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                             /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                             /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                             /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                    /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0                                             /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL << ITM_IWR_ATVALIDM_Pos)                  /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0                                             /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL << ITM_IRR_ATREADYM_Pos)                  /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0                                             /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL << ITM_IMCR_INTEGRATION_Pos)              /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2                                             /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1                                             /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0                                             /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL << ITM_LSR_Present_Pos)                   /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_InterruptType CMSIS Interrupt Type
+  Type definitions for the Cortex-M Interrupt Type Register
+  @{
+ */
+
+/** \brief  Structure type to access the Interrupt Type Register.
+ */
+typedef struct
+{
+       uint32_t RESERVED0;
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Control Type Register */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+} InterruptType_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define IntType_ICTR_INTLINESNUM_Pos  0                                                   /*!< InterruptType ICTR: INTLINESNUM Position */
+#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos)             /*!< InterruptType ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define IntType_ACTLR_DISFOLD_Pos     2                                                   /*!< InterruptType ACTLR: DISFOLD Position */
+#define IntType_ACTLR_DISFOLD_Msk    (1UL << IntType_ACTLR_DISFOLD_Pos)                   /*!< InterruptType ACTLR: DISFOLD Mask */
+
+#define IntType_ACTLR_DISDEFWBUF_Pos  1                                                   /*!< InterruptType ACTLR: DISDEFWBUF Position */
+#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos)                /*!< InterruptType ACTLR: DISDEFWBUF Mask */
+
+#define IntType_ACTLR_DISMCYCINT_Pos  0                                                   /*!< InterruptType ACTLR: DISMCYCINT Position */
+#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos)                /*!< InterruptType ACTLR: DISMCYCINT Mask */
+
+/*@}*/ /* end of group CMSIS_InterruptType */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;                                                
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_XN_Pos                    28                                             /*!< MPU RASR: XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: XN Mask */
+
+#define MPU_RASR_AP_Pos                    24                                             /*!< MPU RASR: AP Position */
+#define MPU_RASR_AP_Msk                    (7UL << MPU_RASR_AP_Pos)                       /*!< MPU RASR: AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19                                             /*!< MPU RASR: TEX Position */
+#define MPU_RASR_TEX_Msk                   (7UL << MPU_RASR_TEX_Pos)                      /*!< MPU RASR: TEX Mask */
+
+#define MPU_RASR_S_Pos                     18                                             /*!< MPU RASR: Shareable bit Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: Shareable bit Mask */
+
+#define MPU_RASR_C_Pos                     17                                             /*!< MPU RASR: Cacheable bit Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: Cacheable bit Mask */
+
+#define MPU_RASR_B_Pos                     16                                             /*!< MPU RASR: Bufferable bit Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: Bufferable bit Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENA_Pos                     0                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENA_Msk                    (0x1UL << MPU_RASR_ENA_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_FPU CMSIS FPU
+  Type definitions for the Cortex-M Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];                                 
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating point context control register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating point context address register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating point default status control register        */
+  __IO uint32_t MVFR0;                   /*!< Offset: 0x010 (R/W)  Media and VFP feature register 0                      */
+  __IO uint32_t MVFR1;                   /*!< Offset: 0x014 (R/W)  Media and VFP feature register 1                      */
+} FPU_Type;                                                
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register   
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register   
+  @{
+ */
+ 
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                  */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define InterruptType       ((InterruptType_Type *) SCS_BASE)         /*!< Interrupt Type Register           */
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
+#define SysTick             ((SysTick_Type *)       SysTick_BASE)     /*!< SysTick configuration struct      */
+#define NVIC                ((NVIC_Type *)          NVIC_BASE)        /*!< NVIC configuration struct         */
+#define ITM                 ((ITM_Type *)           ITM_BASE)         /*!< ITM configuration struct          */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct   */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit            */
+  #define MPU               ((MPU_Type*)            MPU_BASE)         /*!< Memory Protection Unit            */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit               */
+  #define FPU               ((FPU_Type*)            FPU_BASE)         /*!< Floating Point Unit               */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);                         /* only values 0..7 are used          */
+  
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                       |
+                (0x5FA << SCB_AIRCR_VECTKEY_Pos) | 
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value. 
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value. 
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt. 
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt. 
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt. 
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit. 
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt 
+    number can be positive to specify an external (device specific) 
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt 
+    number can be positive to specify an external (device specific) 
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ 
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+ 
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to 
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+ 
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+ 
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+  
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */              
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      | 
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */              
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{ 
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+                                                               
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk | 
+                   SysTick_CTRL_TICKINT_Msk   | 
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0. 
+    It just returns when no debugger is connected that has booked the output.  
+    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }  
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer. 
+    It just returns when no debugger is connected that has booked the output.  
+    It is blocking when a debugger is connected, but the previous character send is not transmitted. 
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+  
+  return (ch); 
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not. 
+    It returns '1' if a character is available and '0' if no character is available. 
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
+
+/*lint -restore */

libcpu/arm/PK40X25VLQ100/core_cm4_simd.h

@@ -0,0 +1,706 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V2.01
+ * @date     06. December 2010
+ *
+ * @note
+ * Copyright (C) 2010 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CM4_SIMD_H__
+#define __CORE_CM4_SIMD_H__
+
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include <intrinsics.h>                     /* IAR Intrinsics   */
+
+#pragma diag_suppress=Pe940
+
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
+/* intrinsic __SADD8      see intrinsics.h */
+/* intrinsic __QADD8      see intrinsics.h */
+/* intrinsic __SHADD8     see intrinsics.h */
+/* intrinsic __UADD8      see intrinsics.h */
+/* intrinsic __UQADD8     see intrinsics.h */
+/* intrinsic __UHADD8     see intrinsics.h */
+/* intrinsic __SSUB8      see intrinsics.h */
+/* intrinsic __QSUB8      see intrinsics.h */
+/* intrinsic __SHSUB8     see intrinsics.h */
+/* intrinsic __USUB8      see intrinsics.h */
+/* intrinsic __UQSUB8     see intrinsics.h */
+/* intrinsic __UHSUB8     see intrinsics.h */
+/* intrinsic __SADD16     see intrinsics.h */
+/* intrinsic __QADD16     see intrinsics.h */
+/* intrinsic __SHADD16    see intrinsics.h */
+/* intrinsic __UADD16     see intrinsics.h */
+/* intrinsic __UQADD16    see intrinsics.h */
+/* intrinsic __UHADD16    see intrinsics.h */
+/* intrinsic __SSUB16     see intrinsics.h */
+/* intrinsic __QSUB16     see intrinsics.h */
+/* intrinsic __SHSUB16    see intrinsics.h */
+/* intrinsic __USUB16     see intrinsics.h */
+/* intrinsic __UQSUB16    see intrinsics.h */
+/* intrinsic __UHSUB16    see intrinsics.h */
+/* intrinsic __SASX       see intrinsics.h */
+/* intrinsic __QASX       see intrinsics.h */
+/* intrinsic __SHASX      see intrinsics.h */
+/* intrinsic __UASX       see intrinsics.h */
+/* intrinsic __UQASX      see intrinsics.h */
+/* intrinsic __UHASX      see intrinsics.h */
+/* intrinsic __SSAX       see intrinsics.h */
+/* intrinsic __QSAX       see intrinsics.h */
+/* intrinsic __SHSAX      see intrinsics.h */
+/* intrinsic __USAX       see intrinsics.h */
+/* intrinsic __UQSAX      see intrinsics.h */
+/* intrinsic __UHSAX      see intrinsics.h */
+/* intrinsic __USAD8      see intrinsics.h */
+/* intrinsic __USADA8     see intrinsics.h */
+/* intrinsic __SSAT16     see intrinsics.h */
+/* intrinsic __USAT16     see intrinsics.h */
+/* intrinsic __UXTB16     see intrinsics.h */
+/* intrinsic __SXTB16     see intrinsics.h */
+/* intrinsic __UXTAB16    see intrinsics.h */
+/* intrinsic __SXTAB16    see intrinsics.h */
+/* intrinsic __SMUAD      see intrinsics.h */
+/* intrinsic __SMUADX     see intrinsics.h */
+/* intrinsic __SMLAD      see intrinsics.h */
+/* intrinsic __SMLADX     see intrinsics.h */
+/* intrinsic __SMLALD     see intrinsics.h */
+/* intrinsic __SMLALDX    see intrinsics.h */
+/* intrinsic __SMUSD      see intrinsics.h */
+/* intrinsic __SMUSDX     see intrinsics.h */
+/* intrinsic __SMLSD      see intrinsics.h */
+/* intrinsic __SMLSDX     see intrinsics.h */
+/* intrinsic __SMLSLD     see intrinsics.h */
+/* intrinsic __SMLSLDX    see intrinsics.h */
+/* intrinsic __SEL        see intrinsics.h */
+/* intrinsic __QADD       see intrinsics.h */
+/* intrinsic __QSUB       see intrinsics.h */
+/* intrinsic __PKHBT      see intrinsics.h */
+/* intrinsic __PKHTB      see intrinsics.h */
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+#pragma diag_default=Pe940
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+  
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else	\
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif (defined (__TASKING__)) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_SIMD_H__ */

libcpu/arm/PK40X25VLQ100/core_cmFunc.h

@@ -0,0 +1,664 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.03
+ * @date     07. April 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H__
+#define __CORE_CMFUNC_H__
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_CONTROL(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_CONTROL(uint32_t control);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_IPSR(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_APSR(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_xPSR(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_PSP(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_PSP(uint32_t topOfProcStack);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_MSP(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_MSP(uint32_t topOfMainStack);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_PRIMASK(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_PRIMASK(uint32_t priMask);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_BASEPRI(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_BASEPRI(uint32_t basePri);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+#endif /*  __ARMCC_VERSION  */ 
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          uint32_t __get_FAULTMASK(void);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+#if       (__ARMCC_VERSION <  400000)
+extern          void __set_FAULTMASK(uint32_t faultMask);
+#else  /* (__ARMCC_VERSION >= 400000) */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & 1);
+}
+#endif /*  __ARMCC_VERSION  */ 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+ #elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1)
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1)
+  __ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H__ */

libcpu/arm/PK40X25VLQ100/core_cmInstr.h

@@ -0,0 +1,592 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.03
+ * @date     07. April 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H__
+#define __CORE_CMINSTR_H__
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if defined ( __CC_ARM   ) /*------------------ RealView Compiler ----------------*/
+/* ARM armcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern uint32_t __REV16(uint32_t value);
+#else  /* (__ARMCC_VERSION >= 400677)  */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#if (__ARMCC_VERSION < 400677)
+extern int32_t __REVSH(int32_t value);
+#else  /* (__ARMCC_VERSION >= 400677)  */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif /* __ARMCC_VERSION  */ 
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#if (__ARMCC_VERSION < 400000)
+extern void __CLREX(void);
+#else  /* (__ARMCC_VERSION >= 400000)  */
+#define __CLREX                           __clrex
+#endif /* __ARMCC_VERSION  */ 
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
+/* IAR iccarm specific functions */
+
+#include <cmsis_iar.h>
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H__ */

libcpu/arm/PK40X25VLQ100/cpu.c

@@ -0,0 +1,44 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ * 2010-02-04     Magicoe      Edit for LPC17xx Series
+ * 2011-08-06     Magicoe      Manded for PK40X256VLQ100
+ */
+
+#include <rtthread.h>
+
+/**
+ * @addtogroup PK40X256VLQ100
+ */
+/*@{*/
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+	/*NOTREACHED*/
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+	rt_kprintf("shutdown...\n");
+
+	RT_ASSERT(0);
+}
+
+/*@}*/

libcpu/arm/PK40X25VLQ100/fault.c

@@ -0,0 +1,47 @@
+/*
+ * File      : fault.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ */
+#include <rtthread.h>
+
+struct stack_contex
+{
+	rt_uint32_t r0;
+	rt_uint32_t r1;
+	rt_uint32_t r2;
+	rt_uint32_t r3;
+	rt_uint32_t r12;
+	rt_uint32_t lr;
+	rt_uint32_t pc;
+	rt_uint32_t psr;
+};
+
+extern void rt_hw_interrupt_thread_switch(void);
+extern void list_thread(void);
+extern rt_thread_t rt_current_thread;
+void rt_hw_hard_fault_exception(struct stack_contex* contex)
+{
+	rt_kprintf("psr: 0x%08x\n", contex->psr);
+	rt_kprintf(" pc: 0x%08x\n", contex->pc);
+	rt_kprintf(" lr: 0x%08x\n", contex->lr);
+	rt_kprintf("r12: 0x%08x\n", contex->r12);
+	rt_kprintf("r03: 0x%08x\n", contex->r3);
+	rt_kprintf("r02: 0x%08x\n", contex->r2);
+	rt_kprintf("r01: 0x%08x\n", contex->r1);
+	rt_kprintf("r00: 0x%08x\n", contex->r0);
+
+	rt_kprintf("hard fault on thread: %s\n", rt_current_thread->name);
+#ifdef RT_USING_FINSH
+	list_thread();
+#endif
+	while (1);
+}

libcpu/arm/PK40X25VLQ100/fault_rvds.S

@@ -0,0 +1,35 @@
+;/*
+; * File      : fault_rvds.S
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2006, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-01-17     Bernard      first version
+; */
+
+    AREA |.text|, CODE, READONLY, ALIGN=2
+    THUMB
+    REQUIRE8
+    PRESERVE8
+
+    IMPORT rt_hw_hard_fault_exception
+
+rt_hw_hard_fault    PROC
+    EXPORT rt_hw_hard_fault
+
+    ; get current context
+    MRS     r0, psp                 ; get fault thread stack pointer
+    PUSH    {lr}
+    BL      rt_hw_hard_fault_exception
+    POP     {lr}
+
+    ORR     lr, lr, #0x04
+    BX      lr
+    ENDP
+
+    END

libcpu/arm/PK40X25VLQ100/interrupt.c

@@ -0,0 +1,21 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ */
+
+#include <rtthread.h>
+
+/* exception and interrupt handler table */
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrput_flag;
+
+/*@}*/

libcpu/arm/PK40X25VLQ100/stack.c

@@ -0,0 +1,61 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-23     Bernard      the first version
+ * 2010-02-04     Magicoe      Edit for LPC17xx Series
+ * 2011-08-06     Magicoe      Manded for PK40X256VLQ100
+ */
+#include <rtthread.h>
+
+/**
+ * @addtogroup PK40X256VLQ100
+ */
+/*@{*/
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+	rt_uint8_t *stack_addr, void *texit)
+{
+	unsigned long *stk;
+
+	stk 	 = (unsigned long *)stack_addr;
+	*(stk)   = 0x01000000L;					/* PSR */
+	*(--stk) = (unsigned long)tentry;		/* entry point, pc */
+	*(--stk) = (unsigned long)texit;		/* lr */
+	*(--stk) = 0;							/* r12 */
+	*(--stk) = 0;							/* r3 */
+	*(--stk) = 0;							/* r2 */
+	*(--stk) = 0;							/* r1 */
+	*(--stk) = (unsigned long)parameter;	/* r0 : argument */
+
+	*(--stk) = 0;							/* r11 */
+	*(--stk) = 0;							/* r10 */
+	*(--stk) = 0;							/* r9 */
+	*(--stk) = 0;							/* r8 */
+	*(--stk) = 0;							/* r7 */
+	*(--stk) = 0;							/* r6 */
+	*(--stk) = 0;							/* r5 */
+	*(--stk) = 0;							/* r4 */
+
+	/* return task's current stack address */
+	return (rt_uint8_t *)stk;
+}
+
+/*@}*/

libcpu/arm/PK40X25VLQ100/start_rvds.S

@@ -0,0 +1,652 @@
+; /*
+; * File      : start_rvds.s
+; * This file is part of RT-Thread RTOS
+; * COPYRIGHT (C) 2009, RT-Thread Development Team
+; *
+; * The license and distribution terms for this file may be
+; * found in the file LICENSE in this distribution or at
+; * http://www.rt-thread.org/license/LICENSE
+; *
+; * Change Logs:
+; * Date           Author       Notes
+; * 2009-09-23     Bernard      first implementation
+; * 2010-02-04     Magicoe      Edit for LPC17xx Series
+; * 2011-08-06     Magicoe      Edit for PK40X256VLQ100
+; */
+
+;/*****************************************************************************
+; * @file:         startup_MK40N512MD100.s
+; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the
+; *                  MK40N512MD100
+; * @version:  1.6
+; * @date:      2011-1-14
+; *
+; * Copyright: 1997 - 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+;*
+; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
+; *
+; *****************************************************************************/
+
+
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00001000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00001000
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+
+                PRESERVE8
+                THUMB
+
+				IMPORT rt_hw_hard_fault
+				IMPORT rt_hw_pend_sv
+				IMPORT rt_hw_timer_handler
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp  ; Top of Stack
+                DCD     Reset_Handler  ; Reset Handler
+                DCD     NMI_Handler  ; NMI Handler
+                DCD     rt_hw_hard_fault  ; Hard Fault Handler
+                DCD     MemManage_Handler  ; MPU Fault Handler
+                DCD     BusFault_Handler  ; Bus Fault Handler
+                DCD     UsageFault_Handler  ; Usage Fault Handler
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     0  ; Reserved
+                DCD     SVC_Handler  ; SVCall Handler
+                DCD     DebugMon_Handler  ; Debug Monitor Handler
+                DCD     0  ; Reserved
+                DCD     rt_hw_pend_sv  ; PendSV Handler
+                DCD     rt_hw_timer_handler  ; SysTick Handler
+
+                ; External Interrupts
+                DCD     DMA0_IRQHandler  ; DMA Channel 0 Transfer Complete
+                DCD     DMA1_IRQHandler  ; DMA Channel 1 Transfer Complete
+                DCD     DMA2_IRQHandler  ; DMA Channel 2 Transfer Complete
+                DCD     DMA3_IRQHandler  ; DMA Channel 3 Transfer Complete
+                DCD     DMA4_IRQHandler  ; DMA Channel 4 Transfer Complete
+                DCD     DMA5_IRQHandler  ; DMA Channel 5 Transfer Complete
+                DCD     DMA6_IRQHandler  ; DMA Channel 6 Transfer Complete
+                DCD     DMA7_IRQHandler  ; DMA Channel 7 Transfer Complete
+                DCD     DMA8_IRQHandler  ; DMA Channel 8 Transfer Complete
+                DCD     DMA9_IRQHandler  ; DMA Channel 9 Transfer Complete
+                DCD     DMA10_IRQHandler  ; DMA Channel 10 Transfer Complete
+                DCD     DMA11_IRQHandler  ; DMA Channel 11 Transfer Complete
+                DCD     DMA12_IRQHandler  ; DMA Channel 12 Transfer Complete
+                DCD     DMA13_IRQHandler  ; DMA Channel 13 Transfer Complete
+                DCD     DMA14_IRQHandler  ; DMA Channel 14 Transfer Complete
+                DCD     DMA15_IRQHandler  ; DMA Channel 15 Transfer Complete
+                DCD     DMA_Error_IRQHandler  ; DMA Error Interrupt
+                DCD     MCM_IRQHandler  ; Normal Interrupt
+                DCD     FTFL_IRQHandler  ; FTFL Interrupt
+                DCD     Read_Collision_IRQHandler  ; Read Collision Interrupt
+                DCD     LVD_LVW_IRQHandler  ; Low Voltage Detect, Low Voltage Warning
+                DCD     LLW_IRQHandler  ; Low Leakage Wakeup
+                DCD     Watchdog_IRQHandler  ; WDOG Interrupt
+                DCD     Reserved39_IRQHandler  ; Reserved interrupt 39
+                DCD     I2C0_IRQHandler  ; I2C0 interrupt
+                DCD     I2C1_IRQHandler  ; I2C1 interrupt
+                DCD     SPI0_IRQHandler  ; SPI0 Interrupt
+                DCD     SPI1_IRQHandler  ; SPI1 Interrupt
+                DCD     SPI2_IRQHandler  ; SPI2 Interrupt
+                DCD     CAN0_ORed_Message_buffer_IRQHandler  ; CAN0 OR'd Message Buffers Interrupt
+                DCD     CAN0_Bus_Off_IRQHandler  ; CAN0 Bus Off Interrupt
+                DCD     CAN0_Error_IRQHandler  ; CAN0 Error Interrupt
+                DCD     CAN0_Tx_Warning_IRQHandler  ; CAN0 Tx Warning Interrupt
+                DCD     CAN0_Rx_Warning_IRQHandler  ; CAN0 Rx Warning Interrupt
+                DCD     CAN0_Wake_Up_IRQHandler  ; CAN0 Wake Up Interrupt
+                DCD     Reserved51_IRQHandler  ; Reserved interrupt 51
+                DCD     Reserved52_IRQHandler  ; Reserved interrupt 52
+                DCD     CAN1_ORed_Message_buffer_IRQHandler  ; CAN1 OR'd Message Buffers Interrupt
+                DCD     CAN1_Bus_Off_IRQHandler  ; CAN1 Bus Off Interrupt
+                DCD     CAN1_Error_IRQHandler  ; CAN1 Error Interrupt
+                DCD     CAN1_Tx_Warning_IRQHandler  ; CAN1 Tx Warning Interrupt
+                DCD     CAN1_Rx_Warning_IRQHandler  ; CAN1 Rx Warning Interrupt
+                DCD     CAN1_Wake_Up_IRQHandler  ; CAN1 Wake Up Interrupt
+                DCD     Reserved59_IRQHandler  ; Reserved interrupt 59
+                DCD     Reserved60_IRQHandler  ; Reserved interrupt 60
+                DCD     UART0_RX_TX_IRQHandler  ; UART0 Receive/Transmit interrupt
+                DCD     UART0_ERR_IRQHandler  ; UART0 Error interrupt
+                DCD     UART1_RX_TX_IRQHandler  ; UART1 Receive/Transmit interrupt
+                DCD     UART1_ERR_IRQHandler  ; UART1 Error interrupt
+                DCD     UART2_RX_TX_IRQHandler  ; UART2 Receive/Transmit interrupt
+                DCD     UART2_ERR_IRQHandler  ; UART2 Error interrupt
+                DCD     UART3_RX_TX_IRQHandler  ; UART3 Receive/Transmit interrupt
+                DCD     UART3_ERR_IRQHandler  ; UART3 Error interrupt
+                DCD     UART4_RX_TX_IRQHandler  ; UART4 Receive/Transmit interrupt
+                DCD     UART4_ERR_IRQHandler  ; UART4 Error interrupt
+                DCD     UART5_RX_TX_IRQHandler  ; UART5 Receive/Transmit interrupt
+                DCD     UART5_ERR_IRQHandler  ; UART5 Error interrupt
+                DCD     ADC0_IRQHandler  ; ADC0 interrupt
+                DCD     ADC1_IRQHandler  ; ADC1 interrupt
+                DCD     CMP0_IRQHandler  ; CMP0 interrupt
+                DCD     CMP1_IRQHandler  ; CMP1 interrupt
+                DCD     CMP2_IRQHandler  ; CMP2 interrupt
+                DCD     FTM0_IRQHandler  ; FTM0 fault, overflow and channels interrupt
+                DCD     FTM1_IRQHandler  ; FTM1 fault, overflow and channels interrupt
+                DCD     FTM2_IRQHandler  ; FTM2 fault, overflow and channels interrupt
+                DCD     CMT_IRQHandler  ; CMT interrupt
+                DCD     RTC_IRQHandler  ; RTC interrupt
+                DCD     Reserved83_IRQHandler  ; Reserved interrupt 83
+                DCD     PIT0_IRQHandler  ; PIT timer channel 0 interrupt
+                DCD     PIT1_IRQHandler  ; PIT timer channel 1 interrupt
+                DCD     PIT2_IRQHandler  ; PIT timer channel 2 interrupt
+                DCD     PIT3_IRQHandler  ; PIT timer channel 3 interrupt
+                DCD     PDB0_IRQHandler  ; PDB0 Interrupt
+                DCD     USB0_IRQHandler  ; USB0 interrupt
+                DCD     USBDCD_IRQHandler  ; USBDCD Interrupt
+                DCD     Reserved91_IRQHandler  ; Reserved interrupt 91
+                DCD     Reserved92_IRQHandler  ; Reserved interrupt 92
+                DCD     Reserved93_IRQHandler  ; Reserved interrupt 93
+                DCD     Reserved94_IRQHandler  ; Reserved interrupt 94
+                DCD     I2S0_IRQHandler  ; I2S0 Interrupt
+                DCD     SDHC_IRQHandler  ; SDHC Interrupt
+                DCD     DAC0_IRQHandler  ; DAC0 interrupt
+                DCD     DAC1_IRQHandler  ; DAC1 interrupt
+                DCD     TSI0_IRQHandler  ; TSI0 Interrupt
+                DCD     MCG_IRQHandler  ; MCG Interrupt
+                DCD     LPTimer_IRQHandler  ; LPTimer interrupt
+                DCD     LCD_IRQHandler  ; Segment LCD Interrupt
+                DCD     PORTA_IRQHandler  ; Port A interrupt
+                DCD     PORTB_IRQHandler  ; Port B interrupt
+                DCD     PORTC_IRQHandler  ; Port C interrupt
+                DCD     PORTD_IRQHandler  ; Port D interrupt
+                DCD     PORTE_IRQHandler  ; Port E interrupt
+                DCD     Reserved108_IRQHandler  ; Reserved interrupt 108
+                DCD     Reserved109_IRQHandler  ; Reserved interrupt 109
+                DCD     Reserved110_IRQHandler  ; Reserved interrupt 110
+                DCD     Reserved111_IRQHandler  ; Reserved interrupt 111
+                DCD     Reserved112_IRQHandler  ; Reserved interrupt 112
+                DCD     Reserved113_IRQHandler  ; Reserved interrupt 113
+                DCD     Reserved114_IRQHandler  ; Reserved interrupt 114
+                DCD     Reserved115_IRQHandler  ; Reserved interrupt 115
+                DCD     Reserved116_IRQHandler  ; Reserved interrupt 116
+                DCD     Reserved117_IRQHandler  ; Reserved interrupt 117
+                DCD     Reserved118_IRQHandler  ; Reserved interrupt 118
+                DCD     Reserved119_IRQHandler  ; Reserved interrupt 119
+__Vectors_End
+
+__Vectors_Size 	EQU 	__Vectors_End - __Vectors
+
+; <h> Flash Configuration
+;   <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
+;   <i> and security information that allows the MCU to restrict acces to the FTFL module.
+;   <h> Backdoor Comparison Key
+;     <o0>  Backdoor Key 0  <0x0-0xFF:2>
+;     <o1>  Backdoor Key 1  <0x0-0xFF:2>
+;     <o2>  Backdoor Key 2  <0x0-0xFF:2>
+;     <o3>  Backdoor Key 3  <0x0-0xFF:2>
+;     <o4>  Backdoor Key 4  <0x0-0xFF:2>
+;     <o5>  Backdoor Key 5  <0x0-0xFF:2>
+;     <o6>  Backdoor Key 6  <0x0-0xFF:2>
+;     <o7>  Backdoor Key 7  <0x0-0xFF:2>
+BackDoorK0      EQU     0xFF
+BackDoorK1      EQU     0xFF
+BackDoorK2      EQU     0xFF
+BackDoorK3      EQU     0xFF
+BackDoorK4      EQU     0xFF
+BackDoorK5      EQU     0xFF
+BackDoorK6      EQU     0xFF
+BackDoorK7      EQU     0xFF
+;   </h>
+;   <h> Program flash protection bytes (FPROT)
+;     <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
+;     <i> Each bit protects a 1/32 region of the program flash memory.
+;     <h> FPROT0
+;       <i> Program flash protection bytes
+;       <i> 1/32 - 8/32 region
+;       <o.0>   FPROT0.0
+;       <o.1>   FPROT0.1
+;       <o.2>   FPROT0.2
+;       <o.3>   FPROT0.3
+;       <o.4>   FPROT0.4
+;       <o.5>   FPROT0.5
+;       <o.6>   FPROT0.6
+;       <o.7>   FPROT0.7
+nFPROT0         EQU     0x00
+FPROT0          EQU     nFPROT0:EOR:0xFF
+;     </h>
+;     <h> FPROT1
+;       <i> Program Flash Region Protect Register 1
+;       <i> 9/32 - 16/32 region
+;       <o.0>   FPROT1.0
+;       <o.1>   FPROT1.1
+;       <o.2>   FPROT1.2
+;       <o.3>   FPROT1.3
+;       <o.4>   FPROT1.4
+;       <o.5>   FPROT1.5
+;       <o.6>   FPROT1.6
+;       <o.7>   FPROT1.7
+nFPROT1         EQU     0x00
+FPROT1          EQU     nFPROT1:EOR:0xFF
+;     </h>
+;     <h> FPROT2
+;       <i> Program Flash Region Protect Register 2
+;       <i> 17/32 - 24/32 region
+;       <o.0>   FPROT2.0
+;       <o.1>   FPROT2.1
+;       <o.2>   FPROT2.2
+;       <o.3>   FPROT2.3
+;       <o.4>   FPROT2.4
+;       <o.5>   FPROT2.5
+;       <o.6>   FPROT2.6
+;       <o.7>   FPROT2.7
+nFPROT2         EQU     0x00
+FPROT2          EQU     nFPROT2:EOR:0xFF
+;     </h>
+;     <h> FPROT3
+;       <i> Program Flash Region Protect Register 3
+;       <i> 25/32 - 32/32 region
+;       <o.0>   FPROT3.0
+;       <o.1>   FPROT3.1
+;       <o.2>   FPROT3.2
+;       <o.3>   FPROT3.3
+;       <o.4>   FPROT3.4
+;       <o.5>   FPROT3.5
+;       <o.6>   FPROT3.6
+;       <o.7>   FPROT3.7
+nFPROT3         EQU     0x00
+FPROT3          EQU     nFPROT3:EOR:0xFF
+;     </h>
+;   </h>
+;   <h> Data flash protection byte (FDPROT)
+;     <i> Each bit protects a 1/8 region of the data flash memory.
+;     <i> (Program flash only devices: Reserved)
+;     <o.0>   FDPROT.0
+;     <o.1>   FDPROT.1
+;     <o.2>   FDPROT.2
+;     <o.3>   FDPROT.3
+;     <o.4>   FDPROT.4
+;     <o.5>   FDPROT.5
+;     <o.6>   FDPROT.6
+;     <o.7>   FDPROT.7
+nFDPROT         EQU     0x00
+FDPROT          EQU     nFDPROT:EOR:0xFF
+;   </h>
+;   <h> EEPROM protection byte (FEPROT)
+;     <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM.
+;     <i> (Program flash only devices: Reserved)
+;     <o.0>   FEPROT.0
+;     <o.1>   FEPROT.1
+;     <o.2>   FEPROT.2
+;     <o.3>   FEPROT.3
+;     <o.4>   FEPROT.4
+;     <o.5>   FEPROT.5
+;     <o.6>   FEPROT.6
+;     <o.7>   FEPROT.7
+nFEPROT         EQU     0x00
+FEPROT          EQU     nFEPROT:EOR:0xFF
+;   </h>
+;   <h> Flash nonvolatile option byte (FOPT)
+;     <i> Allows the user to customize the operation of the MCU at boot time.
+;     <o.0>  LPBOOT
+;       <0=> Low-power boot
+;       <1=> normal boot
+;     <o.1>  EZPORT_DIS
+;       <0=> EzPort operation is enabled
+;       <1=> EzPort operation is disabled
+FOPT            EQU     0xFF
+;   </h>
+;   <h> Flash security byte (FSEC)
+;     <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
+;     <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
+;     <o.0..1> SEC
+;       <2=> MCU security status is unsecure
+;       <3=> MCU security status is secure
+;         <i> Flash Security
+;         <i> This bits define the security state of the MCU.
+;     <o.2..3> FSLACC
+;       <2=> Freescale factory access denied
+;       <3=> Freescale factory access granted
+;         <i> Freescale Failure Analysis Access Code
+;         <i> This bits define the security state of the MCU.
+;     <o.4..5> MEEN
+;       <2=> Mass erase is disabled
+;       <3=> Mass erase is enabled
+;         <i> Mass Erase Enable Bits
+;         <i> Enables and disables mass erase capability of the FTFL module
+;     <o.6..7> KEYEN
+;       <2=> Backdoor key access enabled
+;       <3=> Backdoor key access disabled
+;         <i> Backdoor key Security Enable
+;         <i> These bits enable and disable backdoor key access to the FTFL module.
+FSEC            EQU     0xFE
+;   </h>
+; </h>
+                IF      :LNOT::DEF:RAM_TARGET
+                AREA    |.ARM.__at_0x400|, CODE, READONLY
+                DCB     BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
+                DCB     BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
+                DCB     FPROT0,     FPROT1,     FPROT2,     FPROT3
+                DCB     FSEC,       FOPT,       FEPROT,     FDPROT
+                ENDIF
+
+                AREA    |.text|, CODE, READONLY
+
+
+; Reset Handler
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler         [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler          [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  DMA0_IRQHandler     [WEAK]
+                EXPORT  DMA1_IRQHandler     [WEAK]
+                EXPORT  DMA2_IRQHandler     [WEAK]
+                EXPORT  DMA3_IRQHandler     [WEAK]
+                EXPORT  DMA4_IRQHandler     [WEAK]
+                EXPORT  DMA5_IRQHandler     [WEAK]
+                EXPORT  DMA6_IRQHandler     [WEAK]
+                EXPORT  DMA7_IRQHandler     [WEAK]
+                EXPORT  DMA8_IRQHandler     [WEAK]
+                EXPORT  DMA9_IRQHandler     [WEAK]
+                EXPORT  DMA10_IRQHandler     [WEAK]
+                EXPORT  DMA11_IRQHandler     [WEAK]
+                EXPORT  DMA12_IRQHandler     [WEAK]
+                EXPORT  DMA13_IRQHandler     [WEAK]
+                EXPORT  DMA14_IRQHandler     [WEAK]
+                EXPORT  DMA15_IRQHandler     [WEAK]
+                EXPORT  DMA_Error_IRQHandler     [WEAK]
+                EXPORT  MCM_IRQHandler     [WEAK]
+                EXPORT  FTFL_IRQHandler     [WEAK]
+                EXPORT  Read_Collision_IRQHandler     [WEAK]
+                EXPORT  LVD_LVW_IRQHandler     [WEAK]
+                EXPORT  LLW_IRQHandler     [WEAK]
+                EXPORT  Watchdog_IRQHandler     [WEAK]
+                EXPORT  Reserved39_IRQHandler     [WEAK]
+                EXPORT  I2C0_IRQHandler     [WEAK]
+                EXPORT  I2C1_IRQHandler     [WEAK]
+                EXPORT  SPI0_IRQHandler     [WEAK]
+                EXPORT  SPI1_IRQHandler     [WEAK]
+                EXPORT  SPI2_IRQHandler     [WEAK]
+                EXPORT  CAN0_ORed_Message_buffer_IRQHandler     [WEAK]
+                EXPORT  CAN0_Bus_Off_IRQHandler     [WEAK]
+                EXPORT  CAN0_Error_IRQHandler     [WEAK]
+                EXPORT  CAN0_Tx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN0_Rx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN0_Wake_Up_IRQHandler     [WEAK]
+                EXPORT  Reserved51_IRQHandler     [WEAK]
+                EXPORT  Reserved52_IRQHandler     [WEAK]
+                EXPORT  CAN1_ORed_Message_buffer_IRQHandler     [WEAK]
+                EXPORT  CAN1_Bus_Off_IRQHandler     [WEAK]
+                EXPORT  CAN1_Error_IRQHandler     [WEAK]
+                EXPORT  CAN1_Tx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN1_Rx_Warning_IRQHandler     [WEAK]
+                EXPORT  CAN1_Wake_Up_IRQHandler     [WEAK]
+                EXPORT  Reserved59_IRQHandler     [WEAK]
+                EXPORT  Reserved60_IRQHandler     [WEAK]
+                EXPORT  UART0_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART0_ERR_IRQHandler     [WEAK]
+                EXPORT  UART1_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART1_ERR_IRQHandler     [WEAK]
+                EXPORT  UART2_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART2_ERR_IRQHandler     [WEAK]
+                EXPORT  UART3_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART3_ERR_IRQHandler     [WEAK]
+                EXPORT  UART4_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART4_ERR_IRQHandler     [WEAK]
+                EXPORT  UART5_RX_TX_IRQHandler     [WEAK]
+                EXPORT  UART5_ERR_IRQHandler     [WEAK]
+                EXPORT  ADC0_IRQHandler     [WEAK]
+                EXPORT  ADC1_IRQHandler     [WEAK]
+                EXPORT  CMP0_IRQHandler     [WEAK]
+                EXPORT  CMP1_IRQHandler     [WEAK]
+                EXPORT  CMP2_IRQHandler     [WEAK]
+                EXPORT  FTM0_IRQHandler     [WEAK]
+                EXPORT  FTM1_IRQHandler     [WEAK]
+                EXPORT  FTM2_IRQHandler     [WEAK]
+                EXPORT  CMT_IRQHandler     [WEAK]
+                EXPORT  RTC_IRQHandler     [WEAK]
+                EXPORT  Reserved83_IRQHandler     [WEAK]
+                EXPORT  PIT0_IRQHandler     [WEAK]
+                EXPORT  PIT1_IRQHandler     [WEAK]
+                EXPORT  PIT2_IRQHandler     [WEAK]
+                EXPORT  PIT3_IRQHandler     [WEAK]
+                EXPORT  PDB0_IRQHandler     [WEAK]
+                EXPORT  USB0_IRQHandler     [WEAK]
+                EXPORT  USBDCD_IRQHandler     [WEAK]
+                EXPORT  Reserved91_IRQHandler     [WEAK]
+                EXPORT  Reserved92_IRQHandler     [WEAK]
+                EXPORT  Reserved93_IRQHandler     [WEAK]
+                EXPORT  Reserved94_IRQHandler     [WEAK]
+                EXPORT  I2S0_IRQHandler     [WEAK]
+                EXPORT  SDHC_IRQHandler     [WEAK]
+                EXPORT  DAC0_IRQHandler     [WEAK]
+                EXPORT  DAC1_IRQHandler     [WEAK]
+                EXPORT  TSI0_IRQHandler     [WEAK]
+                EXPORT  MCG_IRQHandler     [WEAK]
+                EXPORT  LPTimer_IRQHandler     [WEAK]
+                EXPORT  LCD_IRQHandler     [WEAK]
+                EXPORT  PORTA_IRQHandler     [WEAK]
+                EXPORT  PORTB_IRQHandler     [WEAK]
+                EXPORT  PORTC_IRQHandler     [WEAK]
+                EXPORT  PORTD_IRQHandler     [WEAK]
+                EXPORT  PORTE_IRQHandler     [WEAK]
+                EXPORT  Reserved108_IRQHandler     [WEAK]
+                EXPORT  Reserved109_IRQHandler     [WEAK]
+                EXPORT  Reserved110_IRQHandler     [WEAK]
+                EXPORT  Reserved111_IRQHandler     [WEAK]
+                EXPORT  Reserved112_IRQHandler     [WEAK]
+                EXPORT  Reserved113_IRQHandler     [WEAK]
+                EXPORT  Reserved114_IRQHandler     [WEAK]
+                EXPORT  Reserved115_IRQHandler     [WEAK]
+                EXPORT  Reserved116_IRQHandler     [WEAK]
+                EXPORT  Reserved117_IRQHandler     [WEAK]
+                EXPORT  Reserved118_IRQHandler     [WEAK]
+                EXPORT  Reserved119_IRQHandler     [WEAK]
+
+DMA0_IRQHandler
+DMA1_IRQHandler
+DMA2_IRQHandler
+DMA3_IRQHandler
+DMA4_IRQHandler
+DMA5_IRQHandler
+DMA6_IRQHandler
+DMA7_IRQHandler
+DMA8_IRQHandler
+DMA9_IRQHandler
+DMA10_IRQHandler
+DMA11_IRQHandler
+DMA12_IRQHandler
+DMA13_IRQHandler
+DMA14_IRQHandler
+DMA15_IRQHandler
+DMA_Error_IRQHandler
+MCM_IRQHandler
+FTFL_IRQHandler
+Read_Collision_IRQHandler
+LVD_LVW_IRQHandler
+LLW_IRQHandler
+Watchdog_IRQHandler
+Reserved39_IRQHandler
+I2C0_IRQHandler
+I2C1_IRQHandler
+SPI0_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+CAN0_ORed_Message_buffer_IRQHandler
+CAN0_Bus_Off_IRQHandler
+CAN0_Error_IRQHandler
+CAN0_Tx_Warning_IRQHandler
+CAN0_Rx_Warning_IRQHandler
+CAN0_Wake_Up_IRQHandler
+Reserved51_IRQHandler
+Reserved52_IRQHandler
+CAN1_ORed_Message_buffer_IRQHandler
+CAN1_Bus_Off_IRQHandler
+CAN1_Error_IRQHandler
+CAN1_Tx_Warning_IRQHandler
+CAN1_Rx_Warning_IRQHandler
+CAN1_Wake_Up_IRQHandler
+Reserved59_IRQHandler
+Reserved60_IRQHandler
+UART0_RX_TX_IRQHandler
+UART0_ERR_IRQHandler
+UART1_RX_TX_IRQHandler
+UART1_ERR_IRQHandler
+UART2_RX_TX_IRQHandler
+UART2_ERR_IRQHandler
+UART3_RX_TX_IRQHandler
+UART3_ERR_IRQHandler
+UART4_RX_TX_IRQHandler
+UART4_ERR_IRQHandler
+UART5_RX_TX_IRQHandler
+UART5_ERR_IRQHandler
+ADC0_IRQHandler
+ADC1_IRQHandler
+CMP0_IRQHandler
+CMP1_IRQHandler
+CMP2_IRQHandler
+FTM0_IRQHandler
+FTM1_IRQHandler
+FTM2_IRQHandler
+CMT_IRQHandler
+RTC_IRQHandler
+Reserved83_IRQHandler
+PIT0_IRQHandler
+PIT1_IRQHandler
+PIT2_IRQHandler
+PIT3_IRQHandler
+PDB0_IRQHandler
+USB0_IRQHandler
+USBDCD_IRQHandler
+Reserved91_IRQHandler
+Reserved92_IRQHandler
+Reserved93_IRQHandler
+Reserved94_IRQHandler
+I2S0_IRQHandler
+SDHC_IRQHandler
+DAC0_IRQHandler
+DAC1_IRQHandler
+TSI0_IRQHandler
+MCG_IRQHandler
+LPTimer_IRQHandler
+LCD_IRQHandler
+PORTA_IRQHandler
+PORTB_IRQHandler
+PORTC_IRQHandler
+PORTD_IRQHandler
+PORTE_IRQHandler
+Reserved108_IRQHandler
+Reserved109_IRQHandler
+Reserved110_IRQHandler
+Reserved111_IRQHandler
+Reserved112_IRQHandler
+Reserved113_IRQHandler
+Reserved114_IRQHandler
+Reserved115_IRQHandler
+Reserved116_IRQHandler
+Reserved117_IRQHandler
+Reserved118_IRQHandler
+Reserved119_IRQHandler
+                B       .
+
+                ENDP
+
+
+                ALIGN
+
+
+; User Initial Stack & Heap
+
+                IF      :DEF:__MICROLIB
+
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+
+                ELSE
+
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+
+                END
+

libcpu/arm/PK40X25VLQ100/system_pk40x256vlq100.c

@@ -0,0 +1,309 @@
+/*
+** ###################################################################
+**     Processor:           PK40X256VLQ100
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU ARM C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    K40P144M100SF2RM, Rev. 3, 4 Nov 2010
+**     Version:             rev. 1.6, 2011-01-14
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that contains the system frequency.
+**         It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 0.1 (2010-09-29)
+**         Initial version
+**     - rev. 1.0 (2010-10-15)
+**         First public version
+**     - rev. 1.1 (2010-10-27)
+**         Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
+**         ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
+**         CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
+**         CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
+**         CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE.
+**         CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx.
+**         DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE.
+**         DMA - Peripheral base pointer macro renamed from eDMA to DMA.
+**         GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
+**         LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE.
+**         LCD - Peripheral base pointer macro renamed from SLCD to LCD.
+**         PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
+**         RFSYS - System regfile registers have been added (#MTWX43999)
+**         RFVBAT - VBAT  regfile registers have been added (#MTWX43999)
+**         RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
+**         TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
+**         USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE.
+**         USB - Peripheral base pointer macro renamed from USBOTG0 to USB0.
+**         VREF - Peripheral register TRM removed.
+**     - rev. 1.2 (2010-11-11)
+**         Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
+**         CAN - Individual Matching Element Update (IMEU) feature has been removed.
+**         CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
+**         CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
+**         CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
+**         NV - Fixed offset address of BACKKEYx, FPROTx registers.
+**         TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
+**     - rev. 1.3 (2010-11-19)
+**         CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed.
+**         CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed.
+**     - rev. 1.4 (2010-11-30)
+**         EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
+**     - rev. 1.5 (2010-12-17)
+**         AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
+**     - rev. 1.6 (2011-01-14)
+**         Added BITBAND_REG() macro to provide access to register bits using bit band region.
+**
+** ###################################################################
+*/
+
+/*! \file MK40N512MD100 */
+/*! \version 1.6 */
+/*! \date 2011-01-14 */
+/*! \brief Device specific configuration file for MK40N512MD100 (implementation file) */
+/*! \detailed Provides a system configuration function and a global variable that contains the system frequency.
+      It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device. */
+
+#include <stdint.h>
+#include "PK40X256VLQ100.h"
+
+#define DISABLE_WDOG    1
+
+#define CLOCK_SETUP     1
+/* Predefined clock setups
+   0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
+         Core clock/Bus clock derived from an internal clock source 32.768kHz
+         Core clock = 47.97MHz, BusClock = 47.97MHz
+   1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE} mode
+         Clock derived from and external crystal 8MHz
+         Core clock = 24MHz, BusClock = 24MHz
+   2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
+         Core clock/Bus clock derived directly from external crystal with no multiplication
+         Core clock = 4MHz, BusClock = 4MHz
+*/
+
+/*----------------------------------------------------------------------------
+  Define clock source values
+ *----------------------------------------------------------------------------*/
+#if (CLOCK_SETUP == 0)
+  #define CPU_XTAL_CLK_HZ                 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+  #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+  #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+  #define DEFAULT_SYSTEM_CLOCK            47972352u /* Default System clock value */
+#elif (CLOCK_SETUP == 1)
+  #define CPU_XTAL_CLK_HZ                 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+  #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+  #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+  #define DEFAULT_SYSTEM_CLOCK            24000000u /* Default System clock value */
+#elif (CLOCK_SETUP == 2)
+  #define CPU_XTAL_CLK_HZ                 4000000u /* Value of the external crystal or oscillator clock frequency in Hz */
+  #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
+  #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
+  #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
+  #define DEFAULT_SYSTEM_CLOCK            4000000u /* Default System clock value */
+#endif /* (CLOCK_SETUP == 2) */
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if (DISABLE_WDOG)
+  /* Disable the WDOG module */
+  /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
+  WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */
+  /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
+  WDOG->UNLOCK  = (uint16_t)0xD928u;    /* Key 2 */
+  /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
+  WDOG->STCTRLH = (uint16_t)0x01D2u;
+#endif /* (DISABLE_WDOG) */
+
+  /* System clock initialization */
+#if (CLOCK_SETUP == 0)
+  /* Switch to FEI Mode */
+  /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x06u;
+  /* MCG->C2: ??=0,??=0,RANGE=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x00u;
+  /* MCG_C4: DMX32=1,DRST_DRS=1 */
+  MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0x40u) | (uint8_t)0xA0u);
+  /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+  MCG->C5 = (uint8_t)0x00u;
+  /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
+  MCG->C6 = (uint8_t)0x00u;
+  while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
+  }
+  while((MCG->S & 0x0Cu) != 0x00u) {    /* Wait until output of the FLL is selected */
+  }
+  /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+#elif (CLOCK_SETUP == 1)
+  /* Switch to FBE Mode */
+  /* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC->CR = (uint8_t)0x00u;
+  /* SIM->SOPT2: MCGCLKSEL=0 */
+  SIM->SOPT2 &= (uint8_t)~(uint8_t)0x01u;
+  /* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x24u;
+  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x9Au;
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+  /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
+  MCG->C5 = (uint8_t)0x03u;
+  /* MCG->C5: PLLCLKEN=1 */
+  MCG->C5 |= (uint8_t)0x40u;            /* Enable the PLL */
+  /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
+  MCG->C6 = (uint8_t)0x00u;
+  while((MCG->S & MCG_S_OSCINIT_MASK) == 0u) { /* Check that the oscillator is running */
+  }
+  while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0Cu) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to PBE Mode */
+  /* MCG->C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x82u;
+  /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
+  MCG->C6 = (uint8_t)0x40u;
+  /* Switch to PEE Mode */
+  /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x02u;
+  /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=3 */
+  MCG->C5 = (uint8_t)0x03u;
+  /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV=0 */
+  MCG->C6 = (uint8_t)0x40u;
+  while((MCG->S & 0x0Cu) != 0x0Cu) {    /* Wait until output of the PLL is selected */
+  }
+  while((MCG->S & MCG_S_LOCK_MASK) == 0u) { /* Wait until locked */
+  }
+  /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+#elif (CLOCK_SETUP == 2)
+  /* Switch to FBE Mode */
+  /* OSC->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
+  OSC->CR = (uint8_t)0x00u;
+  /* SIM->SOPT2: MCGCLKSEL=0 */
+  SIM->SOPT2 &= (uint8_t)~(uint8_t)0x01u;
+  /* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x24u;
+  /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
+  MCG->C1 = (uint8_t)0x9Au;
+  /* MCG->C4: DMX32=0,DRST_DRS=0 */
+  MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
+  /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV=0 */
+  MCG->C5 = (uint8_t)0x00u;
+  /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV=0 */
+  MCG->C6 = (uint8_t)0x00u;
+  while((MCG->S & MCG_S_OSCINIT_MASK) == 0u) { /* Check that the oscillator is running */
+  }
+  while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
+  }
+  while((MCG->S & 0x0CU) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
+  }
+  /* Switch to BLPE Mode */
+  /* MCG->C2: ??=0,??=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
+  MCG->C2 = (uint8_t)0x24u;
+  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
+  SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
+#endif /* (CLOCK_SETUP == 2) */
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+  uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
+  uint8_t Divider;
+
+  if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
+    /* Output of FLL or PLL is selected */
+    if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
+      /* FLL is selected */
+      if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
+        /* External reference clock is selected */
+        if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
+          MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
+        } else { /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
+          MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
+        } /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
+        Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
+        MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
+        if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) {
+          MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
+        } /* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0u) */
+      } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+        MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
+      } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
+      /* Select correct multiplier to calculate the MCG output clock  */
+      switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
+        case 0x0u:
+          MCGOUTClock *= 640u;
+          break;
+        case 0x20u:
+          MCGOUTClock *= 1280u;
+          break;
+        case 0x40u:
+          MCGOUTClock *= 1920u;
+          break;
+        case 0x60u:
+          MCGOUTClock *= 2560u;
+          break;
+        case 0x80u:
+          MCGOUTClock *= 732u;
+          break;
+        case 0xA0u:
+          MCGOUTClock *= 1464u;
+          break;
+        case 0xC0u:
+          MCGOUTClock *= 2197u;
+          break;
+        case 0xE0u:
+          MCGOUTClock *= 2929u;
+          break;
+        default:
+          break;
+      }
+    } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+      /* PLL is selected */
+      Divider = (1u + (MCG->C5 & MCG_C5_PRDIV_MASK));
+      MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);    /* Calculate the PLL reference clock */
+      Divider = ((MCG->C6 & MCG_C6_VDIV_MASK) + 24u);
+      MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
+    } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
+    /* Internal reference clock is selected */
+    if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
+      MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
+    } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_INT_FAST_CLK_HZ;                                       /* Fast internal reference clock selected */
+    } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
+  } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
+    /* External reference clock is selected */
+    if ((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u) {
+      MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
+    } else { /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
+      MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
+    } /* (!((SIM->SOPT2 & SIM_SOPT2_MCGCLKSEL_MASK) == 0x0u)) */
+  } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+    /* Reserved value */
+    return;
+  } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
+  SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
+}

libcpu/arm/PK40X25VLQ100/system_pk40x256vlq100.h

@@ -0,0 +1,104 @@
+/*
+** ###################################################################
+**     Processor:           PK40X256VLQ100
+**     Compilers:           ARM Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU ARM C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**     Reference manual:    K40P144M100SF2RM, Rev. 3, 4 Nov 2010
+**     Version:             rev. 1.6, 2011-01-14
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that contains the system frequency.
+**         It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 0.1 (2010-09-29)
+**         Initial version
+**     - rev. 1.0 (2010-10-15)
+**         First public version
+**     - rev. 1.1 (2010-10-27)
+**         Registers updated according to the new reference manual revision - Rev. 2, 15 Oct 2010
+**         ADC - Peripheral register PGA bit definition has been fixed, bits PGALP, PGACHP removed.
+**         CAN - Peripheral register MCR bit definition has been fixed, bit WAKSRC removed.
+**         CRC - Peripheral register layout structure has been extended with 8/16-bit access to shadow registers.
+**         CMP - Peripheral base address macro renamed from HSCMPx_BASE to CMPx_BASE.
+**         CMP - Peripheral base pointer macro renamed from HSCMPx to CMPx.
+**         DMA - Peripheral base address macro renamed from eDMA_BASE to DMA_BASE.
+**         DMA - Peripheral base pointer macro renamed from eDMA to DMA.
+**         GPIO - Port Output Enable Register (POER) has been renamed to Port Data Direction Register (PDDR), all POER related macros fixed to PDDR.
+**         LCD - Peripheral base address macro renamed from SLCD_BASE to LCD_BASE.
+**         LCD - Peripheral base pointer macro renamed from SLCD to LCD.
+**         PDB - Peripheral register layout structure has been extended for Channel n and DAC n register array access (#MTWX44115).
+**         RFSYS - System regfile registers have been added (#MTWX43999)
+**         RFVBAT - VBAT  regfile registers have been added (#MTWX43999)
+**         RTC - Peripheral register CR bit definition has been fixed, bit OTE removed.
+**         TSI - Peripheral registers STATUS, SCANC bit definition have been fixed, bit groups CAPTRM, DELVOL and AMCLKDIV added.
+**         USB - Peripheral base address macro renamed from USBOTG0_BASE to USB0_BASE.
+**         USB - Peripheral base pointer macro renamed from USBOTG0 to USB0.
+**         VREF - Peripheral register TRM removed.
+**     - rev. 1.2 (2010-11-11)
+**         Registers updated according to the new reference manual revision - Rev. 3, 4 Nov 2010
+**         CAN - Individual Matching Element Update (IMEU) feature has been removed.
+**         CAN - Peripheral register layout structure has been fixed, registers IMEUR, LRFR have been removed.
+**         CAN - Peripheral register CTRL2 bit definition has been fixed, bits IMEUMASK, LOSTRMMSK, LOSTRLMSK, IMEUEN have been removed.
+**         CAN - Peripheral register ESR2 bit definition has been fixed, bits IMEUF, LOSTRMF, LOSTRLF have been removed.
+**         NV - Fixed offset address of BACKKEYx, FPROTx registers.
+**         TSI - Peripheral register layout structure has been fixed, register WUCNTR has been removed.
+**     - rev. 1.3 (2010-11-19)
+**         CAN - Support for CAN0_IMEU_IRQn, CAN0_Lost_Rx_IRQn interrupts has been removed.
+**         CAN - Support for CAN1_IMEU_IRQn, CAN1_Lost_Rx_IRQn interrupts has been removed.
+**     - rev. 1.4 (2010-11-30)
+**         EWM - Peripheral base address EWM_BASE definition has been fixed from 0x4005F000u to 0x40061000u (#MTWX44776).
+**     - rev. 1.5 (2010-12-17)
+**         AIPS0, AIPS1 - Fixed offset of PACRE-PACRP registers (#MTWX45259).
+**     - rev. 1.6 (2011-01-14)
+**         Added BITBAND_REG() macro to provide access to register bits using bit band region.
+**
+** ###################################################################
+*/
+
+/*! \file PK40X256VLQ100 */
+/*! \version 1.6 */
+/*! \date 2011-01-14 */
+/*! \brief Device specific configuration file for PK40X256VLQ100 (header file) */
+/*! \detailed Provides a system configuration function and a global variable that contains the system frequency.
+      It configures the device and initializes the oscillator (PLL) that is part of the microcontroller device. */
+
+#ifndef SYSTEM_PK40X256VLQ100_H_
+#define SYSTEM_PK40X256VLQ100_H_                  /*!< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*! \brief System clock frequency (core clock)
+    \detailed The system clock frequency supplied to the SysTick timer and the processor core clock.
+      This variable can be used by the user application to setup the SysTick timer or configure other parameters.
+      It may also be used by debugger to query the frequency of the debug timer or configure the trace clock speed.
+      SystemCoreClock is initialized with a correct predefined value. */
+extern uint32_t SystemCoreClock;
+
+/*! \brief Setup the microcontroller system.
+    \detailed Typically this function configures the oscillator (PLL) that is part of the microcontroller device.
+      For systems with variable clock speed it also updates the variable SystemCoreClock.
+      SystemInit is called from startup_device file. */
+void SystemInit (void);
+
+/*! \brief Updates the SystemCoreClock variable.
+    \detailed It must be called whenever the core clock is changed during program execution.
+      SystemCoreClockUpdate() evaluates the clock register settings and calculates the current core clock. */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* #if !defined(SYSTEM_PK40X256VLQ100_H_) */