[bsp] add bl808 lp core (#7069)

* Add riscv_32e support

* add bl808 lp core

* update README.md

bsp/README.md

@@ -146,7 +146,7 @@ RT-THREAD bsp company list
 - 紫芯
   - [asm9260t](asm9260t)
 - 博流
-  - [bl808](bl808)
+  - [bouffalo_lab](bouffalo_lab) series
 - 航顺
   - [hk32](hk32) series
 - 辉芒微

bsp/bouffalo_lab/README.md

@@ -116,7 +116,7 @@ Windows下推荐使用[env工具][1]，在console下进入bsp/bouffalo_lab/bl61x
 
 ### 3.1. GUI方式下载
 
-当前bsp必须使用`bouffalo_flash_cube-1.0.4](https://pan.baidu.com/s/1eG9pkxf3riAqQAu9aXiOjw?pwd=miv1)工具进行烧录，否则无法正常运行。
+当前bsp必须使用[bouffalo_flash_cube-1.0.4](https://pan.baidu.com/s/1eG9pkxf3riAqQAu9aXiOjw?pwd=miv1)工具进行烧录，否则无法正常运行。
 
 1. 连接好串口并在工具上选择对应的串口号
 

bsp/bouffalo_lab/bl808/flash_prog_cfg.ini

@@ -9,3 +9,7 @@ boot2_isp_mode = 0
 [FW1]
 filedir = ./m0/rtthread_m0.bin
 address = 0x000000
+
+[FW2]
+filedir = ./lp/rtthread_lp.bin
+address = 0xC0000

bsp/bouffalo_lab/bl808/lp/.config

@@ -0,0 +1,977 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+# CONFIG_RT_USING_MEMPOOL is not set
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=512
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+# CONFIG_RT_USING_MSH is not set
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL808=y
+CONFIG_BL808_CORE_LP=y
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+# CONFIG_BSP_USING_UART0 is not set
+CONFIG_BSP_USING_UART1=y
+# CONFIG_UART1_TX_USING_GPIO4 is not set
+# CONFIG_UART1_TX_USING_GPIO16 is not set
+CONFIG_UART1_TX_USING_GPIO18=y
+# CONFIG_UART1_TX_USING_GPIO26 is not set
+# CONFIG_UART1_RX_USING_GPIO3 is not set
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+# CONFIG_UART1_RX_USING_GPIO17 is not set
+CONFIG_UART1_RX_USING_GPIO19=y
+# CONFIG_UART1_RX_USING_GPIO27 is not set

bsp/bouffalo_lab/bl808/lp/Kconfig

@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"

bsp/bouffalo_lab/bl808/lp/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/bouffalo_lab/bl808/lp/SConstruct

@@ -0,0 +1,45 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/../libraries'):
+    libraries_path_prefix = SDK_ROOT + '/../libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/../libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/bouffalo_lab/bl808/lp/applications/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/bouffalo_lab/bl808/lp/applications/main.c

@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ */
+
+#include <rtthread.h>
+#include <stdio.h>
+
+int main(void)
+{
+    while(1)
+    {
+        rt_kprintf("Hello, RISC-V!\n");
+        rt_thread_delay(5000);
+    }
+
+    return 0;
+}

bsp/bouffalo_lab/bl808/lp/board/Kconfig

@@ -0,0 +1,11 @@
+config BSP_USING_BL808
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select BL808_CORE_LP
+    default y
+
+config BL808_CORE_LP
+    bool
+    default y

bsp/bouffalo_lab/bl808/lp/board/SConscript

@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/bouffalo_lab/bl808/lp/board/board.c

@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+#include "drv_uart.h"
+
+#define RT_HEAP_SIZE 1024
+static uint32_t user_heap[RT_HEAP_SIZE];     // heap default size: 4K(1024 * 4)
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_irq_initialize();
+
+    CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+    bflb_mtimer_config(HW_MTIMER_CLOCK * 2 / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_system_heap_init((void *)user_heap, (void *)user_heap + RT_HEAP_SIZE);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);

bsp/bouffalo_lab/bl808/lp/board/board.h

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include <rtconfig.h>
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl808_glb.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_ef_cfg.h"
+#include "bl808_uhs_phy.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif

bsp/bouffalo_lab/bl808/lp/board/fw_header.c

@@ -0,0 +1,208 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x07, /*!<  0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.mcu_clk = 0x04,   /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
+    .clk_cfg.cfg.mcu_clk_div = 0x00,
+    .clk_cfg.cfg.mcu_bclk_div = 0x00,
+
+    .clk_cfg.cfg.mcu_pbclk_div = 0x03,
+    .clk_cfg.cfg.lp_div = 0x01,
+    .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
+    .clk_cfg.cfg.dsp_clk_div = 0x00,
+
+    .clk_cfg.cfg.dsp_bclk_div = 0x01,
+    .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
+    .clk_cfg.cfg.dsp_pbclk_div = 0x00,
+    .clk_cfg.cfg.emi_clk = 0x02, /*!<  0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+
+    .clk_cfg.cfg.emi_clk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.cfg.wifipll_pu = 0x01,
+
+    .clk_cfg.cfg.aupll_pu = 0x01,
+    .clk_cfg.cfg.cpupll_pu = 0x01,
+    .clk_cfg.cfg.mipipll_pu = 0x01,
+    .clk_cfg.cfg.uhspll_pu = 0x01,
+
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* basic cfg */
+    .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
+    .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
+    .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
+    .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
+    .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
+    .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
+    .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
+    .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
+    .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
+    .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
+    .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
+    .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
+    .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
+    .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
+    .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+    .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+    .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
+    .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+    .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+    .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
+
+#ifdef BFLB_BOOT2
+    .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
+#else
+    .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+#endif
+    .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
+
+    .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+    .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
+
+    /* cpu cfg */
+    .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
+    .cpu_cfg[0].halt_cpu = 0x0,       /* halt this cpu */
+    .cpu_cfg[0].cache_enable = 0x0,   /* cache setting :only for BL Cache */
+    .cpu_cfg[0].cache_wa = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wb = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wt = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].rsvd = 0x0,
+
+    .cpu_cfg[0].cache_range_h = 0x00000000,
+    .cpu_cfg[0].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[0].image_address_offset = 0x0,
+    .cpu_cfg[0].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[0].msp_val = 0x00000000, /* msp value */
+
+    /* cpu cfg */
+    .cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
+    .cpu_cfg[1].halt_cpu = 0x0,      /* halt this cpu */
+    .cpu_cfg[1].cache_enable = 0x0,  /* cache setting :only for BL Cache */
+    .cpu_cfg[1].cache_wa = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wb = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wt = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].rsvd = 0x0,
+
+    .cpu_cfg[1].cache_range_h = 0x00000000,
+    .cpu_cfg[1].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[1].image_address_offset = 0x0,
+    .cpu_cfg[1].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[1].msp_val = 0x00000000, /* msp value */
+
+    /* address of partition table 0 */ /* 4 */
+    .boot2_pt_table_0_rsvd = 0x00000000,
+    /* address of partition table 1 */ /* 4 */
+    .boot2_pt_table_1_rsvd = 0x00000000,
+
+    /* address of flashcfg table list */ /* 4 */
+    .flash_cfg_table_addr = 0x00000000,
+    /* flashcfg table list len */ /* 4 */
+    .flash_cfg_table_len = 0x00000000,
+
+    .rsvd1[0] = 0x20000320,
+    .rsvd1[1] = 0x00000000,
+    .rsvd1[2] = 0x2000F038,
+    .rsvd1[3] = 0x18000000,
+
+    .crc32 = 0xdeadbeef /* 4 */
+};

bsp/bouffalo_lab/bl808/lp/board/fw_header.h

@@ -0,0 +1,213 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t mcu_clk;
+    uint8_t mcu_clk_div;
+    uint8_t mcu_bclk_div;
+
+    uint8_t mcu_pbclk_div;
+    uint8_t lp_div;
+    uint8_t dsp_clk;
+    uint8_t dsp_clk_div;
+
+    uint8_t dsp_bclk_div;
+    uint8_t dsp_pbclk;
+    uint8_t dsp_pbclk_div;
+    uint8_t emi_clk;
+
+    uint8_t emi_clk_div;
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t wifipll_pu;
+
+    uint8_t aupll_pu;
+    uint8_t cpupll_pu;
+    uint8_t mipipll_pu;
+    uint8_t uhspll_pu;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t rsvd_0             : 1; /* [9]      boot2 enable(rsvd_0) */
+    uint32_t rsvd_1             : 1; /* [10]     boot2 rollback(rsvd_1) */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t rsvd_3             : 1; /* [31] rsvd_3 */
+
+    uint32_t group_image_offset; /* flash controller offset */
+    uint32_t aes_region_len;     /* aes region length */
+
+    uint32_t img_len_cnt;  /* image length or segment count */
+    uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+    uint8_t config_enable;     /* coinfig this cpu */
+    uint8_t halt_cpu;          /* halt this cpu */
+    uint8_t cache_enable  : 1; /* cache setting */
+    uint8_t cache_wa      : 1; /* cache setting */
+    uint8_t cache_wb      : 1; /* cache setting */
+    uint8_t cache_wt      : 1; /* cache setting */
+    uint8_t cache_way_dis : 4; /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t cache_range_h; /* cache range high */
+    uint32_t cache_range_l; /* cache range low */
+
+    uint32_t image_address_offset; /* image_address_offset */
+    uint32_t rsvd0;                /* rsvd0 */
+    uint32_t msp_val;              /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /* 4 */
+    uint32_t rivison;   /* 4 */
+
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 20 + 4 */
+
+    struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+    struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
+
+    uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+    uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+    uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+    uint32_t flash_cfg_table_len; /* flashcfg table list len */         /* 4 */
+
+    uint32_t rsvd0[8]; /* rsvd */
+    uint32_t rsvd1[8]; /* rsvd */
+
+    uint32_t rsvd3[5]; /* 20 */
+
+    uint32_t crc32; /* 4 */
+};
+
+#define BFLB_FW_LENGTH_OFFSET 140
+#define BFLB_FW_HASH_OFFSET   144
+
+#endif

bsp/bouffalo_lab/bl808/lp/board/linker_scripts/bl808_flash_lp.ld

@@ -0,0 +1,267 @@
+/****************************************************************************************
+* @file flash.ld
+*
+* @brief This file is the link script file (gnuarm or armgcc).
+*
+* Copyright (C) BouffaloLab 2021
+*
+****************************************************************************************
+*/
+
+/* configure the CPU type */
+OUTPUT_ARCH( "riscv" )
+/* link with the standard c library */
+INPUT(-lc)
+/* link with the standard GCC library */
+INPUT(-lgcc)
+/* configure the entry point */
+ENTRY(__start)
+
+StackSize    = 0x0400; /*  1KB */
+HeapMinSize  = 0x1000; /*  4KB */
+
+MEMORY
+{
+    fw_header_memory  (rx)  : ORIGIN = 0x580C0000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0x580C0000, LENGTH = 1M
+    itcm_memory (rx)  : ORIGIN = 0x2202C000, LENGTH = 16K
+    dtcm_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 16K
+    nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
+    ram_memory  (!rx) : ORIGIN = 0x22034000, LENGTH = 16K
+    xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
+}
+
+SECTIONS
+{
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
+
+    .text :
+    {
+        . = ALIGN(4);
+        __text_code_start__ = .;
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
+
+        *(.text)
+        *(.text.*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        
+        /* section information for usb usbh_class_info */
+        . = ALIGN(4);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        . = ALIGN(4);
+        __usbh_class_info_end__ = .;
+
+        /*put .rodata**/
+        *(EXCLUDE_FILE( *bl808_glb*.o* \
+                        *bl808_glb_gpio*.o* \
+                        *bl808_pds*.o* \
+                        *bl808_aon*.o* \
+                        *bl808_hbn*.o* \
+                        *bl808_l1c*.o* \
+                        *bl808_common*.o* \
+                        *bl808_clock*.o* \
+                        *bl808_ef_ctrl*.o* \
+                        *bl808_sf_cfg*.o* \
+                        *bl808_sf_ctrl*.o* \
+                        *bl808_sflash*.o* \
+                        *bl808_xip_sflash*.o* \
+                        *bl808_romapi_patch*.o* ) .rodata*)
+        *(.srodata)
+        *(.srodata.*)
+
+        . = ALIGN(4);
+        __text_code_end__ = .;
+    } > xip_memory
+
+    . = ALIGN(4);
+    __itcm_load_addr = .;
+
+    .itcm_region : AT (__itcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_code_start__ = .;
+
+        *(.tcm_code.*)
+        *(.tcm_const.*)
+        *(.sclock_rlt_code.*)
+        *(.sclock_rlt_const.*)
+
+        *bl808_glb*.o*(.rodata*)
+        *bl808_glb_gpio*.o*(.rodata*)
+        *bl808_pds*.o*(.rodata*)
+        *bl808_aon*.o*(.rodata*)
+        *bl808_hbn*.o*(.rodata*)
+        *bl808_l1c*.o*(.rodata*)
+        *bl808_common*.o*(.rodata*)
+        *bl808_clock*.o*(.rodata*)
+        *bl808_ef_ctrl*.o*(.rodata*)
+        *bl808_sf_cfg*.o*(.rodata*)
+        *bl808_sf_ctrl*.o*(.rodata*)
+        *bl808_sflash*.o*(.rodata*)
+        *bl808_xip_sflash*.o*(.rodata*)
+        *bl808_romapi_patch*.o*(.rodata*)
+
+        . = ALIGN(4);
+        __tcm_code_end__ = .;
+    } > itcm_memory
+
+    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .dtcm_region : AT (__dtcm_load_addr)
+    {
+        . = ALIGN(4);
+        __tcm_data_start__ = .;
+
+        *(.tcm_data)
+        /* *finger_print.o(.data*) */
+
+        . = ALIGN(4);
+        __tcm_data_end__ = .;
+    } > dtcm_memory
+
+    /*************************************************************************/
+    /* .stack_dummy section doesn't contains any symbols. It is only
+     * used for linker to calculate size of stack sections, and assign
+     * values to stack symbols later */
+    .stack_dummy (NOLOAD):
+    {
+        . = ALIGN(0x4);
+        . = . + StackSize;
+        . = ALIGN(0x4);
+    } > dtcm_memory
+
+    /* Set stack top to end of RAM, and stack limit move down by
+     * size of stack_dummy section */
+    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
+    PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
+    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
+
+    /* Check if data + heap + stack exceeds RAM limit */
+    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+
+    /*************************************************************************/
+
+    __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
+    .nocache_ram_region  : AT (__nocache_ram_load_addr)
+    {
+        . = ALIGN(4);
+        __nocache_ram_data_start__ = .;
+
+        *(.nocache_ram)
+
+        . = ALIGN(4);
+        __nocache_ram_data_end__ = .;
+    } > nocache_ram_memory
+
+    __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
+
+    /* Data section */
+    RAM_DATA : AT (__ram_load_addr)
+    {
+        . = ALIGN(4);
+        __ram_data_start__ = .;
+
+        PROVIDE( __global_pointer$ = . + 0x800 );
+
+        *(.data)
+        *(.data.*)
+        *(.sdata)
+        *(.sdata.*)
+        *(.sdata2)
+        *(.sdata2.*)
+
+        . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
+        __ram_data_end__ = .;
+    } > ram_memory
+
+    __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
+    ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
+
+    .bss (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+
+        *(.bss*)
+        *(.sbss*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > ram_memory
+
+    .noinit_data (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __noinit_data_start__ = .;
+
+        *(.noinit_data*)
+
+        . = ALIGN(4);
+        __noinit_data_end__ = .;
+    } > ram_memory
+
+    .nocache_noinit_ram_region (NOLOAD) :
+    {
+        . = ALIGN(4);
+        __nocache_noinit_ram_data_start__ = .;
+
+        *(.nocache_noinit_ram)
+        *(.noncacheable)
+
+        . = ALIGN(4);
+        __nocache_noinit_ram_data_end__ = .;
+    } > nocache_ram_memory
+
+    .heap (NOLOAD):
+    {
+        . = ALIGN(4);
+        __HeapBase = .;
+
+        /*__end__ = .;*/
+        /*end = __end__;*/
+        KEEP(*(.heap*))
+
+        . = ALIGN(4);
+        __HeapLimit = .;
+    } > ram_memory
+
+    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
+    ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
+
+}
+

bsp/bouffalo_lab/bl808/lp/board/trap_gcc.S

@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret

bsp/bouffalo_lab/bl808/lp/combine.sh

@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=../config
+TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE

bsp/bouffalo_lab/bl808/lp/rtconfig.h

@@ -0,0 +1,225 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 512
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL808
+#define BL808_CORE_LP
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO18
+#define UART1_RX_USING_GPIO19
+
+#endif

bsp/bouffalo_lab/bl808/lp/rtconfig.py

@@ -0,0 +1,63 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+VENDOR      ='t-head'
+CPU         ='e9xx'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32emcxtheadse -mabi=ilp32e -mtune=e902'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl808_flash_lp.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_lp.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl808 ./rtthread_lp.bin\n'

libcpu/risc-v/common/context_gcc.S

@@ -9,6 +9,7 @@
  * 2018/12/27     Jesven       Add SMP support
  * 2020/11/20     BalanceTWK   Add FPU support
  * 2022/12/28     WangShun     Add macro to distinguish whether FPU is supported
+ * 2023/03/19     Flyingcys    Add riscv_32e support
  */
 
 #define __ASSEMBLY__
@@ -115,7 +116,12 @@ rt_hw_context_switch:
     FSTORE  f31, 31 * FREGBYTES(sp)
 
 #endif
+#ifndef __riscv_32e
     addi  sp,  sp, -32 * REGBYTES
+#else
+    addi  sp,  sp, -16 * REGBYTES
+#endif
+
     STORE sp,  (a0)
 
     STORE x1,   0 * REGBYTES(sp)
@@ -140,6 +146,7 @@ save_mpie:
     STORE x13, 13 * REGBYTES(sp)
     STORE x14, 14 * REGBYTES(sp)
     STORE x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     STORE x16, 16 * REGBYTES(sp)
     STORE x17, 17 * REGBYTES(sp)
     STORE x18, 18 * REGBYTES(sp)
@@ -156,7 +163,7 @@ save_mpie:
     STORE x29, 29 * REGBYTES(sp)
     STORE x30, 30 * REGBYTES(sp)
     STORE x31, 31 * REGBYTES(sp)
-
+#endif
     /* restore to thread context
      * sp(0) -> epc;
      * sp(1) -> ra;
@@ -237,6 +244,7 @@ rt_hw_context_switch_exit:
     LOAD x13, 13 * REGBYTES(sp)
     LOAD x14, 14 * REGBYTES(sp)
     LOAD x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     LOAD x16, 16 * REGBYTES(sp)
     LOAD x17, 17 * REGBYTES(sp)
     LOAD x18, 18 * REGBYTES(sp)
@@ -255,6 +263,9 @@ rt_hw_context_switch_exit:
     LOAD x31, 31 * REGBYTES(sp)
 
     addi sp,  sp, 32 * REGBYTES
+#else
+    addi sp,  sp, 16 * REGBYTES
+#endif
 
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)

libcpu/risc-v/common/interrupt_gcc.S

@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2023/01/17     WangShun    The first version
+ * 2023/03/19     Flyingcys    Add riscv_32e support
  */
 #define __ASSEMBLY__
 #include "cpuport.h"
@@ -58,7 +59,11 @@ SW_handler:
     FSTORE  f31, 31 * FREGBYTES(sp)
 #endif
     /* save all from thread context */
+#ifndef __riscv_32e
     addi sp, sp, -32 * REGBYTES
+#else
+    addi sp, sp, -16 * REGBYTES
+#endif
     STORE x5,   5 * REGBYTES(sp)
     STORE x1,   1 * REGBYTES(sp)
     /* Mandatory set the MPIE of mstatus */
@@ -75,6 +80,7 @@ SW_handler:
     STORE x13, 13 * REGBYTES(sp)
     STORE x14, 14 * REGBYTES(sp)
     STORE x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     STORE x16, 16 * REGBYTES(sp)
     STORE x17, 17 * REGBYTES(sp)
     STORE x18, 18 * REGBYTES(sp)
@@ -91,7 +97,7 @@ SW_handler:
     STORE x29, 29 * REGBYTES(sp)
     STORE x30, 30 * REGBYTES(sp)
     STORE x31, 31 * REGBYTES(sp)
-
+#endif
     /* switch to interrupt stack */
     csrrw sp,mscratch,sp
     /* interrupt handle */
@@ -104,22 +110,22 @@ SW_handler:
     csrrw sp,mscratch,sp
 
     /* Determine whether to trigger scheduling at the interrupt function */
-    la    s0, rt_thread_switch_interrupt_flag
-    lw    s2, 0(s0)
-    beqz  s2, 1f
+    la    t0, rt_thread_switch_interrupt_flag
+    lw    t2, 0(t0)
+    beqz  t2, 1f
     /* clear the flag of rt_thread_switch_interrupt_flag */
-    sw    zero, 0(s0)
+    sw    zero, 0(t0)
 
     csrr  a0, mepc
     STORE a0, 0 * REGBYTES(sp)
 
-    la    s0, rt_interrupt_from_thread
-    LOAD  s1, 0(s0)
-    STORE sp, 0(s1)
+    la    t0, rt_interrupt_from_thread
+    LOAD  t1, 0(t0)
+    STORE sp, 0(t1)
 
-    la    s0, rt_interrupt_to_thread
-    LOAD  s1, 0(s0)
-    LOAD  sp, 0(s1)
+    la    t0, rt_interrupt_to_thread
+    LOAD  t1, 0(t0)
+    LOAD  sp, 0(t1)
 
     LOAD  a0,  0 * REGBYTES(sp)
     csrw  mepc, a0
@@ -145,6 +151,7 @@ SW_handler:
     LOAD  x13, 13 * REGBYTES(sp)
     LOAD  x14, 14 * REGBYTES(sp)
     LOAD  x15, 15 * REGBYTES(sp)
+#ifndef __riscv_32e
     LOAD  x16, 16 * REGBYTES(sp)
     LOAD  x17, 17 * REGBYTES(sp)
     LOAD  x18, 18 * REGBYTES(sp)
@@ -163,6 +170,10 @@ SW_handler:
     LOAD  x31, 31 * REGBYTES(sp)
 
     addi  sp, sp, 32 * REGBYTES
+#else
+    addi  sp, sp, 16 * REGBYTES
+#endif
+
 #ifdef ARCH_RISCV_FPU
     FLOAD   f0, 0 * FREGBYTES(sp)
     FLOAD   f1, 1 * FREGBYTES(sp)

libcpu/risc-v/common/rt_hw_stack_frame.h

@@ -31,6 +31,7 @@ typedef struct rt_hw_stack_frame
     rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
     rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
     rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
+#ifndef __riscv_32e
     rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
     rt_ubase_t a7;         /* x17 - a7     - function argument 7                 */
     rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
@@ -47,6 +48,7 @@ typedef struct rt_hw_stack_frame
     rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
     rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
     rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
+#endif
 #ifdef ARCH_RISCV_FPU
     rv_floatreg_t f0;      /* f0  */
     rv_floatreg_t f1;      /* f1  */

libcpu/risc-v/common/trap_common.c

@@ -96,10 +96,12 @@ rt_weak void rt_show_stack_frame(void)
     rt_kprintf("a3      : 0x%08x\r\n", s_stack_frame->a3);
     rt_kprintf("a4      : 0x%08x\r\n", s_stack_frame->a4);
     rt_kprintf("a5      : 0x%08x\r\n", s_stack_frame->a5);
+#ifndef __riscv_32e
     rt_kprintf("a6      : 0x%08x\r\n", s_stack_frame->a6);
     rt_kprintf("a7      : 0x%08x\r\n", s_stack_frame->a7);
     rt_kprintf("t3      : 0x%08x\r\n", s_stack_frame->t3);
     rt_kprintf("t4      : 0x%08x\r\n", s_stack_frame->t4);
     rt_kprintf("t5      : 0x%08x\r\n", s_stack_frame->t5);
     rt_kprintf("t6      : 0x%08x\r\n", s_stack_frame->t6);
+#endif
 }