code format

bsp/ls2kdev/drivers/board.h

@@ -15,7 +15,7 @@
 
 extern unsigned char __bss_end;
 
-#define CPU_HZ	(1000 * 1000 * 1000) //QEMU 200*1000*1000
+#define CPU_HZ              (1000 * 1000 * 1000) //QEMU 200*1000*1000
 #define RT_HW_HEAP_BEGIN    (void*)&__bss_end
 #define RT_HW_HEAP_END      (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
 

bsp/ls2kdev/drivers/clk.c

@@ -14,7 +14,6 @@
 #include <rtthread.h>
 #include "ls2k1000.h"
 
-
 struct loongson_pll {
     rt_uint64_t PLL_SYS_0;
     rt_uint64_t PLL_SYS_1;

bsp/ls2kdev/drivers/drv_gpio.c

@@ -5,8 +5,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2015-01-20     Bernard      the first version
- * 2017-10-20      ZYH          add mode open drain and input pull down
- * 2020-06-01     Du Huanpeng   GPIO driver based on <components/drivers/include/drivers/pin.h>
+ * 2017-10-20      ZYH         add mode open drain and input pull down
+ * 2020-06-01     Du Huanpeng  GPIO driver based on <components/drivers/include/drivers/pin.h>
  */
 #include <rtthread.h>
 #include <drivers/pin.h>

bsp/ls2kdev/drivers/drv_gpio.h

@@ -6,7 +6,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2017-11-24     勤为本          first version
+ * 2017-11-24     勤为本        first version
  * 2018-05-11     zhuangwei    add gpio interrupt ops
  */
 
@@ -36,6 +36,5 @@ struct loongson_gpio {
 
 int loongson_pin_init(void);
 
-
 #endif
 

bsp/ls2kdev/drivers/drv_uart.h

@@ -15,100 +15,99 @@
 #include <rthw.h>
 
 /* UART registers */
-#define UART_DAT(base)		HWREG8(base + 0x00)
-#define UART_IER(base)		HWREG8(base + 0x01)
-#define UART_IIR(base)		HWREG8(base + 0x02)
-#define UART_FCR(base)		HWREG8(base + 0x02)
-#define UART_LCR(base)		HWREG8(base + 0x03)
-#define UART_MCR(base)		HWREG8(base + 0x04)
-#define UART_LSR(base)		HWREG8(base + 0x05)
-#define UART_MSR(base)		HWREG8(base + 0x06)
+#define UART_DAT(base)        HWREG8(base + 0x00)
+#define UART_IER(base)        HWREG8(base + 0x01)
+#define UART_IIR(base)        HWREG8(base + 0x02)
+#define UART_FCR(base)        HWREG8(base + 0x02)
+#define UART_LCR(base)        HWREG8(base + 0x03)
+#define UART_MCR(base)        HWREG8(base + 0x04)
+#define UART_LSR(base)        HWREG8(base + 0x05)
+#define UART_MSR(base)        HWREG8(base + 0x06)
 
-#define UART_LSB(base)		HWREG8(base + 0x00)
-#define UART_MSB(base)		HWREG8(base + 0x01)
+#define UART_LSB(base)        HWREG8(base + 0x00)
+#define UART_MSB(base)        HWREG8(base + 0x01)
 
 /* interrupt enable register */
-#define	IER_IRxE	0x1
-#define	IER_ITxE	0x2
-#define	IER_ILE	    0x4
-#define	IER_IME	    0x8
+#define    IER_IRxE         0x1
+#define    IER_ITxE         0x2
+#define    IER_ILE          0x4
+#define    IER_IME          0x8
 
 /* interrupt identification register */
-#define	IIR_IMASK	0xf	/* mask */
-#define	IIR_RXTOUT	0xc	/* receive timeout */
-#define	IIR_RLS		0x6	/* receive line status */
-#define	IIR_RXRDY	0x4	/* receive ready */
-#define	IIR_TXRDY	0x2	/* transmit ready */
-#define	IIR_NOPEND	0x1	/* nothing */
-#define	IIR_MLSC	0x0	/* modem status */
-#define	IIR_FIFO_MASK	0xc0	/* set if FIFOs are enabled */
+#define    IIR_IMASK        0xf    /* mask */
+#define    IIR_RXTOUT       0xc    /* receive timeout */
+#define    IIR_RLS          0x6    /* receive line status */
+#define    IIR_RXRDY        0x4    /* receive ready */
+#define    IIR_TXRDY        0x2    /* transmit ready */
+#define    IIR_NOPEND       0x1    /* nothing */
+#define    IIR_MLSC         0x0    /* modem status */
+#define    IIR_FIFO_MASK    0xc0    /* set if FIFOs are enabled */
 
 /* fifo control register */
-#define	FIFO_ENABLE	    0x01	/* enable fifo */
-#define	FIFO_RCV_RST	0x02	/* reset receive fifo */
-#define	FIFO_XMT_RST	0x04	/* reset transmit fifo */
-#define	FIFO_DMA_MODE	0x08	/* enable dma mode */
-#define	FIFO_TRIGGER_1	0x00	/* trigger at 1 char */
-#define	FIFO_TRIGGER_4	0x40	/* trigger at 4 chars */
-#define	FIFO_TRIGGER_8	0x80	/* trigger at 8 chars */
-#define	FIFO_TRIGGER_14	0xc0	/* trigger at 14 chars */
+#define    FIFO_ENABLE      0x01    /* enable fifo */
+#define    FIFO_RCV_RST     0x02    /* reset receive fifo */
+#define    FIFO_XMT_RST     0x04    /* reset transmit fifo */
+#define    FIFO_DMA_MODE    0x08    /* enable dma mode */
+#define    FIFO_TRIGGER_1   0x00    /* trigger at 1 char */
+#define    FIFO_TRIGGER_4   0x40    /* trigger at 4 chars */
+#define    FIFO_TRIGGER_8   0x80    /* trigger at 8 chars */
+#define    FIFO_TRIGGER_14  0xc0    /* trigger at 14 chars */
 
-// 线路控制寄存器
 /* character format control register */
-#define	CFCR_DLAB	0x80	/* divisor latch */
-#define	CFCR_SBREAK	0x40	/* send break */
-#define	CFCR_PZERO	0x30	/* zero parity */
-#define	CFCR_PONE	0x20	/* one parity */
-#define	CFCR_PEVEN	0x10	/* even parity */
-#define	CFCR_PODD	0x00	/* odd parity */
-#define	CFCR_PENAB	0x08	/* parity enable */
-#define	CFCR_STOPB	0x04	/* 2 stop bits */
-#define	CFCR_8BITS	0x03	/* 8 data bits */
-#define	CFCR_7BITS	0x02	/* 7 data bits */
-#define	CFCR_6BITS	0x01	/* 6 data bits */
-#define	CFCR_5BITS	0x00	/* 5 data bits */
+#define    CFCR_DLAB        0x80    /* divisor latch */
+#define    CFCR_SBREAK      0x40    /* send break */
+#define    CFCR_PZERO       0x30    /* zero parity */
+#define    CFCR_PONE        0x20    /* one parity */
+#define    CFCR_PEVEN       0x10    /* even parity */
+#define    CFCR_PODD        0x00    /* odd parity */
+#define    CFCR_PENAB       0x08    /* parity enable */
+#define    CFCR_STOPB       0x04    /* 2 stop bits */
+#define    CFCR_8BITS       0x03    /* 8 data bits */
+#define    CFCR_7BITS       0x02    /* 7 data bits */
+#define    CFCR_6BITS       0x01    /* 6 data bits */
+#define    CFCR_5BITS       0x00    /* 5 data bits */
 
 /* modem control register */
-#define	MCR_LOOPBACK	0x10	/* loopback */
-#define	MCR_IENABLE	0x08	/* output 2 = int enable */
-#define	MCR_DRS		0x04	/* output 1 = xxx */
-#define	MCR_RTS		0x02	/* enable RTS */
-#define	MCR_DTR		0x01	/* enable DTR */
+#define    MCR_LOOPBACK     0x10    /* loopback */
+#define    MCR_IENABLE      0x08    /* output 2 = int enable */
+#define    MCR_DRS          0x04    /* output 1 = xxx */
+#define    MCR_RTS          0x02    /* enable RTS */
+#define    MCR_DTR          0x01    /* enable DTR */
 
 /* line status register */
-#define	LSR_RCV_FIFO	0x80	/* error in receive fifo */
-#define	LSR_TSRE	0x40	/* transmitter empty */
-#define	LSR_TXRDY	0x20	/* transmitter ready */
-#define	LSR_BI		0x10	/* break detected */
-#define	LSR_FE		0x08	/* framing error */
-#define	LSR_PE		0x04	/* parity error */
-#define	LSR_OE		0x02	/* overrun error */
-#define	LSR_RXRDY	0x01	/* receiver ready */
-#define	LSR_RCV_MASK	0x1f
+#define    LSR_RCV_FIFO     0x80    /* error in receive fifo */
+#define    LSR_TSRE         0x40    /* transmitter empty */
+#define    LSR_TXRDY        0x20    /* transmitter ready */
+#define    LSR_BI           0x10    /* break detected */
+#define    LSR_FE           0x08    /* framing error */
+#define    LSR_PE           0x04    /* parity error */
+#define    LSR_OE           0x02    /* overrun error */
+#define    LSR_RXRDY        0x01    /* receiver ready */
+#define    LSR_RCV_MASK     0x1f
 
 
 /* UART interrupt enable register value */
-#define UARTIER_IME		(1 << 3)
-#define UARTIER_ILE		(1 << 2)
-#define UARTIER_ITXE	(1 << 1)
-#define UARTIER_IRXE	(1 << 0)
+#define UARTIER_IME       (1 << 3)
+#define UARTIER_ILE       (1 << 2)
+#define UARTIER_ITXE      (1 << 1)
+#define UARTIER_IRXE      (1 << 0)
 
 /* UART line control register value */
-#define UARTLCR_DLAB	(1 << 7)
-#define UARTLCR_BCB		(1 << 6)
-#define UARTLCR_SPB		(1 << 5)
-#define UARTLCR_EPS		(1 << 4)
-#define UARTLCR_PE		(1 << 3)
-#define UARTLCR_SB		(1 << 2)
+#define UARTLCR_DLAB      (1 << 7)
+#define UARTLCR_BCB       (1 << 6)
+#define UARTLCR_SPB       (1 << 5)
+#define UARTLCR_EPS       (1 << 4)
+#define UARTLCR_PE        (1 << 3)
+#define UARTLCR_SB        (1 << 2)
 
 /* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
+#define UARTLSR_ERROR     (1 << 7)
+#define UARTLSR_TE        (1 << 6)
+#define UARTLSR_TFE       (1 << 5)
+#define UARTLSR_BI        (1 << 4)
+#define UARTLSR_FE        (1 << 3)
+#define UARTLSR_PE        (1 << 2)
+#define UARTLSR_OE        (1 << 1)
+#define UARTLSR_DR        (1 << 0)
 
 #endif

bsp/ls2kdev/drivers/interrupt.h

@@ -64,22 +64,22 @@
 #define LS2K_GPIO2_INT_IRQ          (62)
 #define LS2K_GPIO3_INT_IRQ          (63)
 
-#define MAX_INTR 64
-#define LIOINTC0_IRQBASE 0
-#define LIOINTC1_IRQBASE 32
+#define MAX_INTR                    (64)
+#define LIOINTC0_IRQBASE            (0)
+#define LIOINTC1_IRQBASE            (32)
 
-#define LIOINTC_SHIFT_INTx 4
-#define LIOINTC_COREx_INTy(x, y)   ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
+#define LIOINTC_SHIFT_INTx          (4)
+#define LIOINTC_COREx_INTy(x, y)    ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
 
-#define LIOINTC_INTC_CHIP_START	    0x20
+#define LIOINTC_INTC_CHIP_START      0x20
 
-#define LIOINTC_REG_INTC_STATUS	    (LIOINTC_INTC_CHIP_START + 0x00)
-#define LIOINTC_REG_INTC_EN_STATUS	(LIOINTC_INTC_CHIP_START + 0x04)
-#define LIOINTC_REG_INTC_ENABLE	    (LIOINTC_INTC_CHIP_START + 0x08)
-#define LIOINTC_REG_INTC_DISABLE	(LIOINTC_INTC_CHIP_START + 0x0c)
-#define LIOINTC_REG_INTC_POL	    (LIOINTC_INTC_CHIP_START + 0x10)
-#define LIOINTC_REG_INTC_EDGE	    (LIOINTC_INTC_CHIP_START + 0x14)
+#define LIOINTC_REG_INTC_STATUS      (LIOINTC_INTC_CHIP_START + 0x00)
+#define LIOINTC_REG_INTC_EN_STATUS   (LIOINTC_INTC_CHIP_START + 0x04)
+#define LIOINTC_REG_INTC_ENABLE      (LIOINTC_INTC_CHIP_START + 0x08)
+#define LIOINTC_REG_INTC_DISABLE     (LIOINTC_INTC_CHIP_START + 0x0c)
+#define LIOINTC_REG_INTC_POL         (LIOINTC_INTC_CHIP_START + 0x10)
+#define LIOINTC_REG_INTC_EDGE        (LIOINTC_INTC_CHIP_START + 0x14)
 
 void liointc_set_irq_mode(int irq, int mode);
 
-#endif
+#endif

bsp/ls2kdev/drivers/ls2k1000.h

@@ -6,11 +6,11 @@
 
 #define APB_BASE         CKSEG1ADDR(0xbfe00000)
 
-#define UART0_BASE_ADDR 0xbfe00000
-#define UART0_OFF   0x0
-#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
+#define UART0_BASE_ADDR  (0xbfe00000)
+#define UART0_OFF        (0x0)
+#define UART0_BASE       CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
 
-#define UARTx_BASE(x)   ((APB_BASE | (0x0 << 12) | (x << 8)))
+#define UARTx_BASE(x)    ((APB_BASE | (0x0 << 12) | (x << 8)))
 
 #define LIOINTC0_BASE    CKSEG1ADDR(0x1fe11400)
 #define CORE0_INTISR0    CKSEG1ADDR(0x1fe11040)
@@ -18,11 +18,11 @@
 #define LIOINTC1_BASE    CKSEG1ADDR(0x1fe11440)
 #define CORE0_INTISR1    CKSEG1ADDR(0x1fe11048)
 
-#define GPIO_BASE    0xFFFFFFFFBFE10500
-#define PLL_SYS_BASE 0xFFFFFFFFBFE10480
-#define RTC_BASE 0xFFFFFFFFBFE07820
+#define GPIO_BASE        (0xFFFFFFFFBFE10500)
+#define PLL_SYS_BASE     (0xFFFFFFFFBFE10480)
+#define RTC_BASE         (0xFFFFFFFFBFE07820)
 
-#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420
+#define GEN_CONFIG0_REG  (0xFFFFFFFFBfe10420)
 
 void rt_hw_timer_handler(void);
 void rt_hw_uart_init(void);

bsp/ls2kdev/drivers/net/mii.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/ls2kdev/drivers/net/mii.h

@@ -37,7 +37,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000        0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -135,8 +135,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL    0x2000    /* Can do 1000BT Full */
-#define ESTATUS_1000_THALF    0x1000    /* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL      0x2000    /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF      0x1000    /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -170,11 +170,11 @@
 
 
 /* Which connector port. */
-#define PORT_TP         0x00
-#define PORT_AUI        0x01
-#define PORT_MII        0x02 
-#define PORT_FIBRE      0x03
-#define PORT_BNC        0x04
+#define PORT_TP             0x00
+#define PORT_AUI            0x01
+#define PORT_MII            0x02 
+#define PORT_FIBRE          0x03
+#define PORT_BNC            0x04
 
 /* Which transceiver to use. */
 #define XCVR_INTERNAL       0x00
@@ -183,18 +183,18 @@
 #define XCVR_DUMMY2         0x03 
 #define XCVR_DUMMY3         0x04
 
-#define AUTONEG_DISABLE        0x00
-#define AUTONEG_ENABLE         0x01
+#define AUTONEG_DISABLE     0x00
+#define AUTONEG_ENABLE      0x01
 
 
-#define SPEED_10          10
-#define SPEED_100         100
-#define SPEED_1000        1000
-#define SPEED_2500        2500
-#define SPEED_10000       10000
+#define SPEED_10            10
+#define SPEED_100           100
+#define SPEED_1000          1000
+#define SPEED_2500          2500
+#define SPEED_10000         10000
 
-#define DUPLEX_HALF        0x00
-#define DUPLEX_FULL        0x01
+#define DUPLEX_HALF         0x00
+#define DUPLEX_FULL         0x01
 
 struct ethtool_cmd {
     u32    cmd;

bsp/ls2kdev/drivers/net/synopGMAC.c

@@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter)
     return gmacdev->Speed | (gmacdev->DuplexMode << 4);
 }
 
-
 static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
 {
     int i;
@@ -894,7 +893,6 @@ int rt_hw_eth_init(void)
     struct synopGMACNetworkAdapter *synopGMACadapter;
     static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
     int index;
-    //rt_kprintf("rt_hw_eth_init 1\n");
     rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
     rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
@@ -958,8 +956,6 @@ int rt_hw_eth_init(void)
     
     eth_device_init(&(eth_dev.parent), "e0");
     eth_device_linkchange(&eth_dev.parent, RT_TRUE);   //linkup the e0 for lwip to check
-    //rt_kprintf("rt_hw_eth_init 2\n");
     return 0;
 }
-
 INIT_COMPONENT_EXPORT(rt_hw_eth_init);

bsp/ls2kdev/drivers/net/synopGMAC_Dev.c

@@ -860,7 +860,6 @@ void synopGMAC_promisc_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Enables unicast hash filtering.
   * When enabled GMAC performs the destination address filtering of unicast frames according to the hash table.
@@ -1032,7 +1031,6 @@ void synopGMAC_pause_control(synopGMACdevice *gmacdev)
     synopGMACWriteReg(gmacdev -> MacBase,GmacFlowControl,mac_flow_control_reg);
 
     return;
-
 }
 
 /**
@@ -1352,10 +1350,9 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
     desc -> length = 0; 
     #else
     desc -> length = last_ring_desc ? TxDescEndOfRing : 0;
-  desc -> status = 0;
+    desc -> status = 0;
     #endif
 //sw    
-
     desc -> buffer1 = 0;
     desc -> buffer2 = 0;
     desc -> data1 = 0;
@@ -1365,8 +1362,6 @@ void synopGMAC_tx_desc_init_ring(DmaDesc *desc, bool last_ring_desc)
     return;
 }
 
-
-
 /**
   * Initialize the rx descriptors for chain mode of operation.
   *     - Status field is initialized to 0.
@@ -1409,7 +1404,6 @@ void synopGMAC_tx_desc_init_chain(DmaDesc * desc)
     return;
 }
 
-
 s32 synopGMAC_init_tx_rx_desc_queue(synopGMACdevice *gmacdev)
 {
     s32 i;
@@ -1817,7 +1811,6 @@ void synopGMAC_get_desc_data(DmaDesc *desc,u32 *Status,u32 *Buffer1,u32 *Length1
     }
     
     return;
-
 }
 
 #ifdef ENH_DESC_8W
@@ -1912,10 +1905,7 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
     u32  txover      = gmacdev->TxBusy;
     DmaDesc * txdesc = gmacdev->TxBusyDesc;
     int i;
-    
 //sw: dbg
-    
-
     //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_R);
     //pci_sync_cache(0, (vm_offset_t)txdesc, 64, SYNC_W);
 #if SYNOP_TX_DEBUG
@@ -1954,12 +1944,12 @@ s32 synopGMAC_get_tx_qptr(synopGMACdevice * gmacdev, u32 * Status, u32 * Buffer1
     gmacdev->TxBusy     = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txover + 1;
 
     if(synopGMAC_is_tx_desc_chained(txdesc))
-  {
-           gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
+    {
+        gmacdev->TxBusyDesc = (DmaDesc *)txdesc->data2;
         synopGMAC_tx_desc_init_chain(txdesc);
     }
     else
-  {
+    {
         gmacdev->TxBusyDesc = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? gmacdev->TxDesc : (txdesc + 1);
         synopGMAC_tx_desc_init_ring(txdesc, synopGMAC_is_last_tx_desc(gmacdev,txdesc));
     }
@@ -2008,37 +1998,40 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
 
     (gmacdev->BusyTxDesc)++; //busy tx descriptor is reduced by one as it will be handed over to Processor now
     
-    if(synopGMAC_is_tx_desc_chained(txdesc)){
-        txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
-        #ifdef ENH_DESC
-        txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
-        #else
-        txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
-        #endif
-
-         txdesc->buffer1 = Buffer1;
-        txdesc->data1 = Data1;
-
-    if(offload_needed){
-        /*
-         Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
-         before calling any of the functions given below.         
-         */
-        synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc);
-        synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc);
+    if(synopGMAC_is_tx_desc_chained(txdesc))
+    {
+      txdesc->length |= ((Length1 <<DescSize1Shift) & DescSize1Mask);
+      #ifdef ENH_DESC
+      txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
+      #else
+      txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
+      #endif
+
+      txdesc->buffer1 = Buffer1;
+      txdesc->data1 = Data1;
+
+      if(offload_needed)
+      {
+          /*
+           Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
+           before calling any of the functions given below.         
+           */
+          synopGMAC_tx_checksum_offload_ipv4hdr(gmacdev, txdesc);
+          synopGMAC_tx_checksum_offload_tcponly(gmacdev, txdesc);
 //        synopGMAC_tx_checksum_offload_tcp_pseudo(gmacdev, txdesc);
+      }
+      #ifdef ENH_DESC
+      txdesc->status |= DescOwnByDma;//ENH_DESC
+      #else
+      txdesc->status = DescOwnByDma;
+      #endif
+
+      gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
+          gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
     }
-        #ifdef ENH_DESC
-        txdesc->status |= DescOwnByDma;//ENH_DESC
-        #else
-        txdesc->status = DescOwnByDma;
-        #endif
-
-        gmacdev->TxNext = synopGMAC_is_last_tx_desc(gmacdev,txdesc) ? 0 : txnext + 1;
-           gmacdev->TxNextDesc = (DmaDesc *)txdesc->data2;
-    }
-    else{
-//        printf("synopGMAC_set_tx_qptr:in ring mode\n");
+    else
+    {
+//      printf("synopGMAC_set_tx_qptr:in ring mode\n");
         txdesc->length |= (((Length1 <<DescSize1Shift) & DescSize1Mask) | ((Length2 <<DescSize2Shift) & DescSize2Mask));
         #ifdef ENH_DESC
         txdesc->status |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //ENH_DESC
@@ -2046,13 +2039,14 @@ s32 synopGMAC_set_tx_qptr(synopGMACdevice * gmacdev, u32 Buffer1, u32 Length1, u
         txdesc->length |=  (DescTxFirst | DescTxLast | DescTxIntEnable); //Its always assumed that complete data will fit in to one descriptor
         #endif
 
-         txdesc->buffer1 = Buffer1;
+        txdesc->buffer1 = Buffer1;
         txdesc->data1 = Data1;
 
-         txdesc->buffer2 = Buffer2;
+        txdesc->buffer2 = Buffer2;
         txdesc->data2 = Data2;
 
-        if(offload_needed){
+        if(offload_needed)
+        {
         /*
          Make sure that the OS you are running supports the IP and TCP checkusm offloaidng,
          before calling any of the functions given below.         
@@ -2638,8 +2632,7 @@ void synopGMAC_take_desc_ownership_tx(synopGMACdevice * gmacdev)
         else{
             synopGMAC_take_desc_ownership(desc + i);
         }
-    }
-    
+    }  
 }
 
 /**
@@ -2668,15 +2661,8 @@ void synopGMAC_disable_dma_rx(synopGMACdevice * gmacdev)
     data = synopGMACReadReg(gmacdev->DmaBase, DmaControl);
       data &= (~DmaRxStart); 
     synopGMACWriteReg(gmacdev->DmaBase, DmaControl ,data);
-}
-
-
-    
+}   
 /*******************PMT APIs***************************************/
-
-
-
-
 /**
   * Enables the assertion of PMT interrupt.
   * This enables the assertion of PMT interrupt due to Magic Pkt or Wakeup frame
@@ -2835,9 +2821,9 @@ void synopGMAC_write_wakeup_frame_register(synopGMACdevice *gmacdev, u32 * filte
 
 }
 #endif
+
 /*******************PMT APIs***************************************/
 /*******************MMC APIs***************************************/
-
 /**
   * Freezes the MMC counters.
   * This function call freezes the MMC counters. None of the MMC counters are updated
@@ -3081,7 +3067,6 @@ void synopGMAC_rx_tcpip_chksum_drop_disable(synopGMACdevice *gmacdev)
   * \return returns TRUE or FALSE
   */
 #ifdef ENH_DESC_8W
-
 /**
   * This function indicates whether extended status is available in the RDES0.
   * Any function which accesses the fields of extended status register must ensure a check on this has been made
@@ -3132,8 +3117,6 @@ bool synopGMAC_ES_is_IP_payload_error(synopGMACdevice *gmacdev,u32 ext_status)
 }
 #endif
 
-
-
 /**
   * Decodes the Rx Descriptor status to various checksum error conditions.
   * @param[in] pointer to synopGMACdevice.
@@ -3172,7 +3155,6 @@ bool synopGMAC_is_tx_ipv4header_checksum_error(synopGMACdevice *gmacdev, u32 sta
     return((status & DescTxIpv4ChkError) == DescTxIpv4ChkError);
 }
 
-
 /**
   * Checks if any payload checksum error in the frame just transmitted.
   * This serves as indication that error occureed in the payload checksum insertion.
@@ -3199,7 +3181,6 @@ void synopGMAC_tx_checksum_offload_bypass(synopGMACdevice *gmacdev, DmaDesc *des
     #else
     desc->length = (desc->length & (~DescTxCisMask));
     #endif
-
 }
 /**
   * The check summ offload engine is enabled to do only IPV4 header checksum.
@@ -3215,7 +3196,6 @@ void synopGMAC_tx_checksum_offload_ipv4hdr(synopGMACdevice *gmacdev, DmaDesc *de
     #else
     desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisIpv4HdrCs);
     #endif
-
 }
 
 /**
@@ -3233,7 +3213,6 @@ void synopGMAC_tx_checksum_offload_tcponly(synopGMACdevice *gmacdev, DmaDesc *de
     #else
     desc->length = ((desc->length & (~DescTxCisMask)) | DescTxCisTcpOnlyCs);
     #endif
-
 }
 /**
   * The check summ offload engine is enabled to do complete checksum computation.
@@ -3254,14 +3233,7 @@ void synopGMAC_tx_checksum_offload_tcp_pseudo(synopGMACdevice *gmacdev, DmaDesc
 
 }
 /*******************Ip checksum offloading APIs***************************************/
-
-
-
-
-
 /*******************IEEE 1588 Timestamping API***************************************/
-
-
 /*
  * At this time the driver supports the IEEE time stamping feature when the Enhanced Descriptors are enabled.
  * For normal descriptor and the IEEE time stamp (version 1), driver support is not proviced
@@ -3295,7 +3267,6 @@ void synopGMAC_TS_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Enable the interrupt to get timestamping interrupt. 
   * This enables the host to get the interrupt when (1) system time is greater or equal to the 
@@ -3344,7 +3315,6 @@ void synopGMAC_TS_mac_addr_filt_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Selet the type of clock mode for PTP. 
   * Please note to use one of the follwoing as the clk_type argument.
@@ -3493,7 +3463,6 @@ void synopGMAC_TS_ptp_over_ethernet_disable(synopGMACdevice *gmacdev)
     return;
 }
 
-
 /**
   * Snoop PTP packet for version 2 format 
   * When set the PTP packets are snooped using the version 2 format.
@@ -3584,11 +3553,10 @@ s32 synopGMAC_TS_addend_update(synopGMACdevice *gmacdev, u32 addend_value)
         if(loop_variable < DEFAULT_LOOP_VARIABLE)
                synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSADDREG);
         else{
-        TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
-    return -ESYNOPGMACPHYERR;
+          TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
+          return -ESYNOPGMACPHYERR;
         }
-return -ESYNOPGMACNOERR;
-
+    return -ESYNOPGMACNOERR;
 }
 /**
   * time stamp Update 
@@ -3602,21 +3570,21 @@ return -ESYNOPGMACNOERR;
 s32 synopGMAC_TS_timestamp_update(synopGMACdevice *gmacdev, u32 high_value, u32 low_value)
 {
     u32 loop_variable;
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
-        for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
+    for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
         if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSUPDT)){ // if it is cleared then break
-        break;
+            break;
         } 
         plat_delay(DEFAULT_DELAY_VARIABLE);
-        }
-        if(loop_variable < DEFAULT_LOOP_VARIABLE)
-               synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT);
-        else{
+    }
+    if(loop_variable < DEFAULT_LOOP_VARIABLE)
+        synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSUPDT);
+    else{
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
-    return -ESYNOPGMACPHYERR;
-        }
-return -ESYNOPGMACNOERR;
+        return -ESYNOPGMACPHYERR;
+    }
+    return -ESYNOPGMACNOERR;
 }
 
 /**
@@ -3631,21 +3599,21 @@ return -ESYNOPGMACNOERR;
 s32 synopGMAC_TS_timestamp_init(synopGMACdevice *gmacdev, u32 high_value, u32 low_value)
 {
     u32 loop_variable;
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
-        synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
-        for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSHighUpdate,high_value);// Load the high value to Timestamp High register
+    synopGMACWriteReg(gmacdev->MacBase,GmacTSLowUpdate,low_value);// Load the high value to Timestamp High register
+    for(loop_variable = 0; loop_variable < DEFAULT_LOOP_VARIABLE; loop_variable++){ //Wait till the busy bit gets cleared with in a certain amount of time
         if(!((synopGMACReadReg(gmacdev->MacBase,GmacTSControl)) & GmacTSINT)){ // if it is cleared then break
-        break;
+            break;
         } 
         plat_delay(DEFAULT_DELAY_VARIABLE);
-        }
-        if(loop_variable < DEFAULT_LOOP_VARIABLE)
-               synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT);
-        else{
+    }
+    if(loop_variable < DEFAULT_LOOP_VARIABLE)
+        synopGMACSetBits(gmacdev->MacBase,GmacTSControl,GmacTSINT);
+    else{
         TR("Error::: The TSADDREG bit is not getting cleared !!!!!!\n");
-    return -ESYNOPGMACPHYERR;
-        }
-return -ESYNOPGMACNOERR;
+        return -ESYNOPGMACPHYERR;
+    }
+    return -ESYNOPGMACNOERR;
 }
 
 /**
@@ -3696,8 +3664,8 @@ void synopGMAC_TS_subsecond_init(synopGMACdevice *gmacdev, u32 sub_sec_inc_value
 void synopGMAC_TS_read_timestamp(synopGMACdevice *gmacdev, u16 * higher_sec_val, u32 * sec_val, u32 *  sub_sec_val)
 {
     * higher_sec_val = (u16)(synopGMACReadReg(gmacdev->MacBase,GmacTSHighWord) & GmacTSHighWordMask);
-        * sec_val        = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh);
-        * sub_sec_val    = synopGMACReadReg(gmacdev->MacBase,GmacTSLow);
+    * sec_val        = synopGMACReadReg(gmacdev->MacBase,GmacTSHigh);
+    * sub_sec_val    = synopGMACReadReg(gmacdev->MacBase,GmacTSLow);
     return;
 }
 /**

bsp/ls2kdev/drivers/net/synopGMAC_plat.h

@@ -239,4 +239,4 @@ static bool  synopGMACCheckBits(u64 RegBase, u32 RegOffset, u32 BitPos)
     }
 }
 
-#endif
+#endif

libcpu/mips/gs264/cache.c

@@ -67,4 +67,4 @@ rt_base_t rt_hw_cpu_icache_status(void)
 rt_base_t rt_hw_cpu_dcache_status(void)
 {
     return 0;
-}
+}

libcpu/mips/gs264/cpuinit_gcc.S

@@ -19,8 +19,8 @@
 
     .globl  rt_cpu_early_init
 rt_cpu_early_init:
-     mfc0	t0, CP0_CONFIG
-     ori	t0, 3
-     mtc0	t0, CP0_CONFIG
+     mfc0    t0, CP0_CONFIG
+     ori     t0, 3
+     mtc0    t0, CP0_CONFIG
      ehb
-     jr	ra
+     jr      ra

libcpu/mips/gs264/mips_mmu.c

@@ -5,7 +5,7 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2020-07-26 	  lizhirui 	   the first version
+ * 2020-07-26     lizhirui     the first version
  */
 
 #include <string.h>
@@ -205,18 +205,18 @@ uint64_t mmu_tlb_get_bad_vaddr()
 
 void tlb_dump()
 {
-	uint32_t max_index = mmu_get_max_tlb_index();
-	//uint32_t max_index = 10;
-	uint32_t entry;
-	tlb_item_t tlb_item;
-
-	for(entry = 0;entry <= max_index;entry++)
-	{
-		mmu_tlb_read(entry,&tlb_item);
-		//mmu_tlb_write_indexed(entry,&tlb_item);
-		//mmu_tlb_read(entry,&tlb_item);
-		rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12);
-		rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c);
-		rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c);
-	}
-}
+    uint32_t max_index = mmu_get_max_tlb_index();
+    //uint32_t max_index = 10;
+    uint32_t entry;
+    tlb_item_t tlb_item;
+
+    for(entry = 0;entry <= max_index;entry++)
+    {
+        mmu_tlb_read(entry,&tlb_item);
+        //mmu_tlb_write_indexed(entry,&tlb_item);
+        //mmu_tlb_read(entry,&tlb_item);
+        rt_kprintf("vpn = 0x%p,ppn0 = 0x%p,ppn1 = 0x%p\n",(uint64_t)tlb_item.entry_hi.vpn2 << 13 | (uint64_t)tlb_item.entry_hi.asid << 62,(uint64_t)tlb_item.entry_lo[0].pfn << 12,(uint64_t)tlb_item.entry_lo[1].pfn << 12);
+        rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[0].v,tlb_item.entry_lo[0].d,tlb_item.entry_lo[0].g,tlb_item.entry_lo[0].ri,tlb_item.entry_lo[0].xi,tlb_item.entry_lo[0].c);
+        rt_kprintf("v = %d,d = %d,g = %d,ri = %d,xi = %d,c = %d\n",tlb_item.entry_lo[1].v,tlb_item.entry_lo[1].d,tlb_item.entry_lo[1].g,tlb_item.entry_lo[1].ri,tlb_item.entry_lo[1].xi,tlb_item.entry_lo[1].c);
+    }
+}

libcpu/mips/gs264/mips_mmu.h

@@ -5,96 +5,95 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2020-07-26 	  lizhirui 	   the first version
+ * 2020-07-26     lizhirui     the first version
  */
-
 #ifndef __MIPS_MMU_H__
 #define __MIPS_MMU_H__
 
-    typedef enum cpu_mode_t
-    {
-        CPU_MODE_KERNEL = 0x00,
-        CPU_MODE_SUPERVISOR = 0x01,
-        CPU_MODE_USER = 0x02
-    }cpu_mode_t;
+typedef enum cpu_mode_t
+{
+    CPU_MODE_KERNEL = 0x00,
+    CPU_MODE_SUPERVISOR = 0x01,
+    CPU_MODE_USER = 0x02
+}cpu_mode_t;
 
-    typedef enum page_mask_enum_t
-    {
-        PAGE_MASK_4KB = 0x00,
-        PAGE_MASK_16KB = 0x03,
-        PAGE_MASK_64KB = 0x0F,
-        PAGE_MASK_256KB = 0x3F,
-        PAGE_MASK_1MB = 0xFF,
-        PAGE_MASK_4MB = 0x3FF,
-        PAGE_MASK_16MB = 0xFFF,
-        PAGE_MASK_64MB = 0x3FFF,
-        PAGE_MASK_256MB = 0xFFFF,
-        PAGE_MASK_1GB = 0x3FFFF
-    }page_mask_enum_t;
+typedef enum page_mask_enum_t
+{
+    PAGE_MASK_4KB = 0x00,
+    PAGE_MASK_16KB = 0x03,
+    PAGE_MASK_64KB = 0x0F,
+    PAGE_MASK_256KB = 0x3F,
+    PAGE_MASK_1MB = 0xFF,
+    PAGE_MASK_4MB = 0x3FF,
+    PAGE_MASK_16MB = 0xFFF,
+    PAGE_MASK_64MB = 0x3FFF,
+    PAGE_MASK_256MB = 0xFFFF,
+    PAGE_MASK_1GB = 0x3FFFF
+}page_mask_enum_t;
 
-    typedef struct page_mask_t
-    {
-        uint64_t : 11;
-        uint64_t : 2;
-        uint64_t mask : 18;
-        uint64_t : 33;
-    }page_mask_t;
+typedef struct page_mask_t
+{
+    uint64_t : 11;
+    uint64_t : 2;
+    uint64_t mask : 18;
+    uint64_t : 33;
+}page_mask_t;
 
-    typedef struct entry_lo_t
-    {
-        uint64_t g : 1;
-        uint64_t v : 1;
-        uint64_t d : 1;
-        uint64_t c : 3;
-        uint64_t pfn : 24;
-        uint64_t pfnx : 3;
-        uint64_t : 29;
-        uint64_t xi : 1;
-        uint64_t ri : 1;
-    }entry_lo_t;
+typedef struct entry_lo_t
+{
+    uint64_t g : 1;
+    uint64_t v : 1;
+    uint64_t d : 1;
+    uint64_t c : 3;
+    uint64_t pfn : 24;
+    uint64_t pfnx : 3;
+    uint64_t : 29;
+    uint64_t xi : 1;
+    uint64_t ri : 1;
+}entry_lo_t;
 
-    typedef struct entry_hi_t
-    {
-        uint64_t asid : 8;
-        uint64_t : 5;
-        uint64_t vpn2 : 27;
-        uint64_t : 22;
-        uint64_t r : 2;
-    }entry_hi_t;
+typedef struct entry_hi_t
+{
+    uint64_t asid : 8;
+    uint64_t : 5;
+    uint64_t vpn2 : 27;
+    uint64_t : 22;
+    uint64_t r : 2;
+}entry_hi_t;
 
-    typedef struct tlb_item_t
-    {
-        entry_lo_t entry_lo[2];
-        entry_hi_t entry_hi;
-        page_mask_t page_mask;
-    }tlb_item_t;
+typedef struct tlb_item_t
+{
+    entry_lo_t entry_lo[2];
+    entry_hi_t entry_hi;
+    page_mask_t page_mask;
+}tlb_item_t;
 
-    #define read_c0_diag()		__read_32bit_c0_register($22, 0)
-    #define write_c0_diag(val)	__write_32bit_c0_register($22, 0, val)
-    #define read_c0_badvaddr()  __read_64bit_c0_register($8, 0)
-    #define read_c0_random()  __read_32bit_c0_register($1, 0)
+#define read_c0_diag()        __read_32bit_c0_register($22, 0)
+#define write_c0_diag(val)    __write_32bit_c0_register($22, 0, val)
+#define read_c0_badvaddr()    __read_64bit_c0_register($8, 0)
+#define read_c0_random()      __read_32bit_c0_register($1, 0)
 
-    #define reg_type_convert(variable,new_type) *((new_type *)(&variable))
-    #define lowbit(x) ((x) & (-(x)))
+#define reg_type_convert(variable,new_type) *((new_type *)(&variable))
+#define lowbit(x) ((x) & (-(x)))
 
-    void mmu_init();
-    void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
-    cpu_mode_t mmu_get_cpu_mode();
-    void mmu_clear_tlb();
-    void mmu_clear_itlb();
-    uint32_t mmu_get_max_tlb_index();
-    void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
-    void mmu_tlb_write_random(tlb_item_t *tlb_item);
-    void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
-    uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
-    void mmu_tlb_item_init(tlb_item_t *tlb_item);
-    void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
-    uint32_t mmu_tlb_get_random();
-    uint32_t mmu_tlb_get_index();
-    void mmu_tlb_set_index(uint32_t index);
-    uint32_t mmu_tlb_is_matched();
-    uint64_t mmu_tlb_get_bad_vaddr();
+void mmu_init();
+void mmu_set_cpu_mode(cpu_mode_t cpu_mode);
+cpu_mode_t mmu_get_cpu_mode();
+void mmu_clear_tlb();
+void mmu_clear_itlb();
+uint32_t mmu_get_max_tlb_index();
+void mmu_tlb_write_indexed(uint32_t index,tlb_item_t *tlb_item);
+void mmu_tlb_write_random(tlb_item_t *tlb_item);
+void mmu_tlb_read(uint32_t index,tlb_item_t *tlb_item);
+uint32_t mmu_tlb_find(uint64_t vpn,uint32_t asid,uint32_t *index);
+void mmu_tlb_item_init(tlb_item_t *tlb_item);
+void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t asid,uint32_t global);
+uint32_t mmu_tlb_get_random();
+uint32_t mmu_tlb_get_index();
+void mmu_tlb_set_index(uint32_t index);
+uint32_t mmu_tlb_is_matched();
+uint64_t mmu_tlb_get_bad_vaddr();
 
-    void tlb_dump();
+void tlb_dump();
 
 #endif

libcpu/mips/gs264/mipscfg.c

@@ -12,15 +12,15 @@
 
 mips32_core_cfg_t g_mips_core =
 {
-    64,		/* icache_line_size */
-    128,	/* icache_lines_per_way */
-    4,		/* icache_ways */
+    64,        /* icache_line_size */
+    128,       /* icache_lines_per_way */
+    4,         /* icache_ways */
     32768,
-    64,		/* dcache_line_size */
-    128,	/* dcache_lines_per_way */
-    4,		/* dcache_ways */
+    64,        /* dcache_line_size */
+    128,       /* dcache_lines_per_way */
+    4,         /* dcache_ways */
     32768,
-    64,		/* max_tlb_entries */
+    64,        /* max_tlb_entries */
 };
 
 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)

libcpu/mips/gs264/mmu.c

@@ -21,15 +21,15 @@ void *current_mmu_table = RT_NULL;
 
 void *mmu_table_get()
 {
-	return current_mmu_table;
+    return current_mmu_table;
 }
 
 void switch_mmu(void *mmu_table)
 {
-	current_mmu_table = mmu_table;
+    current_mmu_table = mmu_table;
 
     mmu_clear_tlb();
-	mmu_clear_itlb();
+    mmu_clear_itlb();
 }
 
 /* dump 2nd level page table */
@@ -476,7 +476,7 @@ static int __rt_hw_mmu_map(rt_mmu_info *mmu_info, void* v_addr, void* p_addr, si
 static void rt_hw_cpu_tlb_invalidate(void)
 {
     mmu_clear_tlb();
-	mmu_clear_itlb();
+    mmu_clear_itlb();
 }
 
 #ifdef RT_USING_USERSPACE

libcpu/mips/gs264/mmu.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2020, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,21 +14,21 @@
 #include <rtthread.h>
 
 #define DESC_SEC       (0x2)
-#define MEMWBWA        ((1<<12)|(3<<2))     /* write back, write allocate */
-#define MEMWB          (3<<2)  /* write back, no write allocate */
-#define MEMWT          (2<<2)  /* write through, no write allocate */
-#define SHAREDEVICE    (1<<2)  /* shared device */
-#define STRONGORDER    (0<<2)  /* strong ordered */
-#define XN             (1<<4)  /* eXecute Never */
+#define MEMWBWA        ((1<<12)|(3<<2))      /* write back, write allocate */
+#define MEMWB          (3<<2)                /* write back, no write allocate */
+#define MEMWT          (2<<2)                /* write through, no write allocate */
+#define SHAREDEVICE    (1<<2)                /* shared device */
+#define STRONGORDER    (0<<2)                /* strong ordered */
+#define XN             (1<<4)                /* execute Never */
 #ifdef RT_USING_USERSPACE
-#define AP_RW          (1<<10) /* supervisor=RW, user=No */
-#define AP_RO          ((1<<10) |(1 << 15)) /* supervisor=RW, user=No */
+#define AP_RW          (1<<10)               /* supervisor=RW, user=No */
+#define AP_RO          ((1<<10) |(1 << 15))  /* supervisor=RW, user=No */
 #else
-#define AP_RW          (3<<10) /* supervisor=RW, user=RW */
-#define AP_RO          ((2<<10) /* supervisor=RW, user=RO */
+#define AP_RW          (3<<10)               /* supervisor=RW, user=RW */
+#define AP_RO          ((2<<10)              /* supervisor=RW, user=RO */
 #endif
 
-#define SHARED         (1<<16) /* shareable */
+#define SHARED         (1<<16)               /* shareable */
 
 #define DOMAIN_FAULT   (0x0)
 #define DOMAIN_CHK     (0x1)