更新MCXA153-SDK-V2.16.000

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/MCXA153_features.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b231012
+**     Build:               b240428
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -156,6 +156,16 @@
 #define FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI (1)
 /* @brief Indicate LPADC CFG register TPRICTRL bitfield width. */
 #define FSL_FEATURE_LPADC_CFG_TPRICTRL_BITFIELD_WIDTH (2)
+/* @brief Has internal temperature sensor. */
+#define FSL_FEATURE_LPADC_HAS_INTERNAL_TEMP_SENSOR (1)
+/* @brief Temperature sensor parameter A (slope). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_A (738.0f)
+/* @brief Temperature sensor parameter B (offset). */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_B (287.5f)
+/* @brief Temperature sensor parameter Alpha. */
+#define FSL_FEATURE_LPADC_TEMP_PARAMETER_ALPHA (10.06f)
+/* @brief The buffer size of temperature sensor. */
+#define FSL_FEATURE_LPADC_TEMP_SENS_BUFFER_SIZE (2U)
 
 /* AOI module features */
 
@@ -166,7 +176,8 @@
 
 /* CDOG module features */
 
-/* No feature definitions */
+/* @brief CDOG Has No Reset */
+#define FSL_FEATURE_CDOG_HAS_NO_RESET (1)
 
 /* CMC module features */
 
@@ -177,7 +188,7 @@
 /* @brief Has RSTCNT register */
 #define FSL_FEATURE_MCX_CMC_HAS_RSTCNT_REG (1)
 /* @brief Has BLR register */
-#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (1)
+#define FSL_FEATURE_MCX_CMC_HAS_BLR_REG (0)
 
 /* LPCMP module features */
 
@@ -191,6 +202,8 @@
 #define FSL_FEATURE_LPCMP_HAS_ROUNDROBIN_MODE (1)
 /* @brief Has window mode (related to existence of CCR1.WINDOW_CLS). */
 #define FSL_FEATURE_LPCMP_HAS_WINDOW_CONTROL (1)
+/* @brief Has no CCR0 CMP_STOP_EN bitfield. */
+#define FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN (0)
 
 /* CTIMER module features */
 
@@ -221,40 +234,44 @@
 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
 /* @brief If 64 bytes transfer supported. */
 #define FSL_FEATURE_EDMA_SUPPORT_64_BYTES_TRANSFER (1)
-/* @brief If channel clock controlled independently */
-#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
+/* @brief whether has prot register */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(x) (0)
 /* @brief If 128 bytes transfer supported. */
 #define FSL_FEATURE_EDMA_SUPPORT_128_BYTES_TRANSFER (1)
-/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
-#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (4)
+/* @brief whether has MP channel mux */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(x) (0)
 /* @brief If 128 bytes transfer supported. */
 #define FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn(x) (1)
-/* @brief Has no register bit fields MP_CSR[EBW]. */
-#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
+/* @brief If channel clock controlled independently */
+#define FSL_FEATURE_EDMA_CHANNEL_HAS_OWN_CLOCK_GATE (1)
 /* @brief Has register CH_CSR. */
 #define FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG (1)
-/* @brief If dma has common clock gate */
-#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
+/* @brief Number of channel for each EDMA instance, (only defined for soc with different channel numbers for difference instance) */
+#define FSL_FEATURE_EDMA_INSTANCE_CHANNELn(x) (4)
 /* @brief Has channel mux */
 #define FSL_FEATURE_EDMA_HAS_CHANNEL_MUX (1)
-/* @brief If dma channel IRQ support parameter */
-#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
+/* @brief Has no register bit fields MP_CSR[EBW]. */
+#define FSL_FEATURE_EDMA_HAS_NO_MP_CSR_EBW (1)
 /* @brief Instance has channel mux */
 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(x) (1)
-/* @brief NBYTES must be multiple of 8 when using scatter gather. */
-#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
+/* @brief If dma has common clock gate */
+#define FSL_FEATURE_EDMA_HAS_COMMON_CLOCK_GATE (0)
 /* @brief Has register CH_SBR. */
 #define FSL_FEATURE_EDMA_HAS_SBR (1)
-/* @brief NBYTES must be multiple of 8 when using scatter gather. */
-#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
+/* @brief If dma channel IRQ support parameter */
+#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SUPPORT_PARAMETER (0)
 /* @brief Has no register bit fields CH_SBR[ATTR]. */
 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_ATTR (1)
-/* @brief Has register bit fields MP_CSR[GMRC]. */
-#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_HAS_ERRATA_51327 (0)
 /* @brief Has register bit field CH_CSR[SWAP]. */
 #define FSL_FEATURE_EDMA_HAS_CHANNEL_SWAP_SIZE (0)
+/* @brief NBYTES must be multiple of 8 when using scatter gather. */
+#define FSL_FEATURE_EDMA_INSTANCE_HAS_ERRATA_51327n(x) (0)
 /* @brief Instance has register bit field CH_CSR[SWAP]. */
 #define FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_SWAP_SIZEn(x) (0)
+/* @brief Has register bit fields MP_CSR[GMRC]. */
+#define FSL_FEATURE_EDMA_HAS_GLOBAL_MASTER_ID_REPLICATION (1)
 /* @brief Has register bit field CH_SBR[INSTR]. */
 #define FSL_FEATURE_EDMA_HAS_CHANNEL_ACCESS_TYPE (0)
 /* @brief Instance has register bit field CH_SBR[INSTR]. */
@@ -277,6 +294,8 @@
 #define FSL_FEATURE_EDMA_INSTANCE_HAS_TRANSFER_MODEn(x) (0)
 /* @brief Has no register bit fields CH_SBR[SEC]. */
 #define FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC (1)
+/* @brief edma5 has different tcd type. */
+#define FSL_FEATURE_EDMA_TCD_TYPEn(x) (0)
 
 /* PWM module features */
 
@@ -307,6 +326,11 @@
 /* @brief If (e)FlexPWM has module capture functionality on X channels (inputs). */
 #define FSL_FEATURE_PWM_HAS_CAPTURE_ON_CHANNELX (1)
 
+/* GLIKEY module features */
+
+/* @brief GLIKEY has 8 step FSM configuration */
+#define FSL_FEATURE_GLIKEY_HAS_EIGHT_STEPS (1)
+
 /* GPIO module features */
 
 /* @brief Has GPIO attribute checker register (GACR). */
@@ -332,8 +356,12 @@
 #define FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND (1)
 /* @brief Register SCONFIG has HDROK bitfield. */
 #define FSL_FEATURE_I3C_HAS_HDROK (1)
+/* @brief SOC doesn't support slave IBI/MR/HJ. */
+#define FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ (0)
 /* @brief Has IBI bytes. */
 #define FSL_FEATURE_I3C_HAS_IBI_PAYLOAD_SIZE_OPTIONAL_BYTE (1)
+/* @brief Has SCL delay after START. */
+#define FSL_FEATURE_I3C_HAS_START_SCL_DELAY (1)
 
 /* LPI2C module features */
 
@@ -350,6 +378,10 @@
 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
 /* @brief Has CCR1 (related to existence of registers CCR1). */
 #define FSL_FEATURE_LPSPI_HAS_CCR1 (1)
+/* @brief Has no PCSCFG bit in CFGR1 register */
+#define FSL_FEATURE_LPSPI_HAS_NO_PCSCFG (0)
+/* @brief Has no WIDTH bits in TCR register */
+#define FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH (0)
 
 /* LPTMR module features */
 
@@ -359,8 +391,12 @@
 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (1)
 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1)
+/* @brief Do not has prescaler clock source 0. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT (0)
 /* @brief Do not has prescaler clock source 1. */
 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT (0)
+/* @brief Do not has prescaler clock source 2. */
+#define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT (0)
 /* @brief Do not has prescaler clock source 3. */
 #define FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT (0)
 
@@ -437,6 +473,25 @@
 /* @brief Has register Timeout. */
 #define FSL_FEATURE_LPUART_HAS_TIMEOUT (0)
 
+/* TRDC module features */
+
+/* @brief Process master count. */
+#define FSL_FEATURE_TRDC_PROCESSOR_MASTER_COUNT (2)
+/* @brief TRDC instance has PID configuration or not. */
+#define FSL_FEATURE_TRDC_INSTANCE_HAS_PID_CONFIGURATIONn(x) (0)
+/* @brief TRDC instance has MBC. */
+#define FSL_FEATURE_TRDC_HAS_MBC (1)
+/* @brief TRDC instance has MRC. */
+#define FSL_FEATURE_TRDC_HAS_MRC (0)
+/* @brief TRDC instance has TRDC_CR. */
+#define FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG (0)
+/* @brief TRDC instance has MDA_Wx_y_DFMT. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT (0)
+/* @brief TRDC instance has TRDC_FDID. */
+#define FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR (0)
+/* @brief TRDC instance has TRDC_FLW_CTL. */
+#define FSL_FEATURE_TRDC_HAS_FLW (0)
+
 /* PORT module features */
 
 /* @brief Has control lock (register bit PCR[LK]). */
@@ -467,6 +522,8 @@
 #define FSL_FEATURE_PORT_SUPPORT_DIFFERENT_VOLTAGE_RANGE (1)
 /* @brief Has EFT detect (registers EDFR, EDIER and EDCR). */
 #define FSL_FEATURE_PORT_SUPPORT_EFT (0)
+/* @brief Function 0 is GPIO. */
+#define FSL_FEATURE_PORT_PCR_MUX_GPIO (0)
 /* @brief Has drive strength control (register bit PCR[DSE]). */
 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
 /* @brief Defines width of PCR[MUX] field. */
@@ -519,6 +576,10 @@
 #define FSL_FEATURE_MCX_SPC_HAS_CNTRL_REG (0)
 /* @brief Has DPDOWN_PULLDOWN_DISABLE */
 #define FSL_FEATURE_MCX_SPC_HAS_DPDOWN_PULLDOWN_DISABLE_BIT (0)
+/* @brief Not have glitch detect */
+#define FSL_FEATURE_MCX_SPC_HAS_NO_GLITCH_DETECT (1)
+/* @brief Has BLEED_EN */
+#define FSL_FEATURE_MCX_SPC_HAS_DCDC_CFG_BLEED_EN (0)
 
 /* SYSCON module features */
 

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/arm/startup_MCXA153.S

@@ -4,11 +4,11 @@
 /*            MCXA153                                                        */
 /*  @version: 1.0                                                            */
 /*  @date:    2022-3-29                                                      */
-/*  @build:   b230804                                                        */
+/*  @build:   b240401                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2023 NXP                                                   */
+/* Copyright 2016-2024 NXP                                                   */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_aoi.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_AOI_H_
-#define _FSL_AOI_H_
+#ifndef FSL_AOI_H_
+#define FSL_AOI_H_
 
 #include "fsl_common.h"
 
@@ -23,9 +23,9 @@
 #endif
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_AOI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
-/*@}*/
+/*! @} */
 
 /*!
  * @brief AOI input configurations.
@@ -109,7 +109,7 @@ void AOI_Init(AOI_Type *base);
  */
 void AOI_Deinit(AOI_Type *base);
 
-/*@}*/
+/*! @} */
 
 /*!
  * @name  AOI Get Set Operation
@@ -179,8 +179,8 @@ void AOI_SetEventLogicConfig(AOI_Type *base, aoi_event_t event, const aoi_event_
 }
 #endif /* __cplusplus*/
 
-/*@}*/
+/*! @} */
 
 /*!* @} */
 
-#endif /* _FSL_AOI_H_*/
+#endif /* FSL_AOI_H_*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_cdog.c

@@ -0,0 +1,378 @@
+/*
+ * Copyright 2020-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_cdog.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.cdog"
+#endif
+
+/* Reset CONTROL mask */
+#define RESERVED_CTRL_MASK 0x800u
+
+#if defined(CDOG_IRQS)
+/* Array of IRQs */
+static const IRQn_Type s_CdogIrqs[] = CDOG_IRQS;
+#endif /* CDOG_IRQS */
+
+#ifdef CDOG_CLOCKS
+static const clock_ip_name_t s_CdogClocks[] = CDOG_CLOCKS;
+#endif /* CDOG_CLOCKS */
+
+#ifdef CDOG_BASE_PTRS
+static const CDOG_Type* s_cdogBases[] = CDOG_BASE_PTRS;
+#endif /* CDOG_BASE_PTRS */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t CDOG_GetInstance(CDOG_Type *base)
+{
+    uint32_t instance;
+ 
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_cdogBases); instance++)
+    {
+        if (s_cdogBases[instance] == base)
+        {
+            break;
+        }
+    }
+ 
+    assert(instance < ARRAY_SIZE(s_cdogBases));
+ 
+    return instance;
+} 
+
+/*!
+ * brief Sets the default configuration of CDOG
+ *
+ * This function initialize CDOG config structure to default values.
+ *
+ * param conf CDOG configuration structure
+ */
+void CDOG_GetDefaultConfig(cdog_config_t *conf)
+{
+    /* Default configuration after reset */
+    conf->lock       = (uint8_t)kCDOG_LockCtrl_Unlock;    /* Lock control */
+    conf->timeout    = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Timeout control */
+    conf->miscompare = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Miscompare control */
+    conf->sequence   = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Sequence control */
+    conf->state      = (uint8_t)kCDOG_FaultCtrl_NoAction; /* State control */
+    conf->address    = (uint8_t)kCDOG_FaultCtrl_NoAction; /* Address control */
+    conf->irq_pause  = (uint8_t)kCDOG_IrqPauseCtrl_Run;   /* IRQ pause control */
+    conf->debug_halt = (uint8_t)kCDOG_DebugHaltCtrl_Run;  /* Debug halt control */
+    return;
+}
+
+/*!
+ * brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in RELOAD and START registers for instruction timer.
+ *
+ * param base CDOG peripheral base address
+ * param reload reload value
+ * param start start value
+ */
+void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start)
+{
+    base->RELOAD = reload;
+    base->START  = start;
+}
+
+/*!
+ * brief Stops secure counter and instruction timer
+ *
+ * This function stops instruction timer and secure counter.
+ * This also change state of CDOG to IDLE.
+ *
+ * param base CDOG peripheral base address
+ * param stop expected value which will be compared with value of secure counter
+ */
+void CDOG_Stop(CDOG_Type *base, uint32_t stop)
+{
+    base->STOP = stop;
+}
+
+/*!
+ * brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in STOP, RELOAD and START registers
+ * for instruction timer and secure counter.
+ *
+ * param base CDOG peripheral base address
+ * param stop expected value which will be compared with value of secure counter
+ * param reload reload value for instruction timer
+ * param start start value for secure timer
+ */
+void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start)
+{
+    base->STOP   = stop;
+    base->RELOAD = reload;
+    base->START  = start;
+}
+
+/*!
+ * brief Add value to secure counter
+ *
+ * This function add specified value to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add(CDOG_Type *base, uint32_t add)
+{
+    base->ADD = (secure_counter_t)add;
+}
+
+/*!
+ * brief Add 1 to secure counter
+ *
+ * This function add 1 to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add1(CDOG_Type *base)
+{
+    base->ADD1 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Add 16 to secure counter
+ *
+ * This function add 16 to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add16(CDOG_Type *base)
+{
+    base->ADD16 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Add 256 to secure counter
+ *
+ * This function add 256 to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param add Value to be added.
+ */
+void CDOG_Add256(CDOG_Type *base)
+{
+    base->ADD256 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Substract value to secure counter
+ *
+ * This function substract specified value to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param sub Value to be substracted.
+ */
+void CDOG_Sub(CDOG_Type *base, uint32_t sub)
+{
+    base->SUB = (secure_counter_t)sub;
+}
+
+/*!
+ * brief Substract 1 from secure counter
+ *
+ * This function substract specified 1 from secure counter.
+ *
+ * param base CDOG peripheral base address.
+ */
+void CDOG_Sub1(CDOG_Type *base)
+{
+    base->SUB1 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Substract 16 from secure counter
+ *
+ * This function substract specified 16 from secure counter.
+ *
+ * param base CDOG peripheral base address.
+ */
+void CDOG_Sub16(CDOG_Type *base)
+{
+    base->SUB16 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Substract 256 from secure counter
+ *
+ * This function substract specified 256 from secure counter.
+ *
+ * param base CDOG peripheral base address.
+ */
+void CDOG_Sub256(CDOG_Type *base)
+{
+    base->SUB256 = (secure_counter_t)0x1U;
+}
+
+/*!
+ * brief Checks secure counter.
+ *
+ * This function compares stop value with secure counter value
+ * by writting to RELOAD refister.
+ *
+ * param base CDOG peripheral base address
+ * param check expected (stop) value.
+ */
+void CDOG_Check(CDOG_Type *base, uint32_t check)
+{
+#if defined(FLS_FEATURE_CDOG_USE_RESTART)
+    base->RESTART = check;
+#else
+    base->STOP = check;
+    base->RELOAD = base->RELOAD;
+    base->START= check;
+#endif
+}
+
+/*!
+ * brief Set the CDOG persistent word.
+ *
+ * param base CDOG peripheral base address.
+ * param value The value to be written.
+ */
+void CDOG_WritePersistent(CDOG_Type *base, uint32_t value)
+{
+    base->PERSISTENT = value;
+}
+
+/*!
+ * brief Get the CDOG persistent word.
+ *
+ * param base CDOG peripheral base address.
+ * return The persistent word.
+ */
+uint32_t CDOG_ReadPersistent(CDOG_Type *base)
+{
+    return base->PERSISTENT;
+}
+
+/*!
+ * brief Initialize CDOG
+ *
+ * This function initializes CDOG setting and enable all interrupts.
+ *
+ * param base CDOG peripheral base address
+ * param conf CDOG configuration structure
+ * return Status of the init operation
+ */
+status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf)
+{
+    /* Ungate clock to CDOG engine and reset it */
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#ifdef CDOG_CLOCKS
+    CLOCK_EnableClock(s_CdogClocks[CDOG_GetInstance(base)]);
+#endif /* CDOG_CLOCKS */
+#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
+    RESET_PeripheralReset(kCDOG_RST_SHIFT_RSTn);
+#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
+
+    if (base->CONTROL == 0x0U)
+    {
+        /* CDOG is not in IDLE mode, which may be cause after SW reset. */
+        /* Writing to CONTROL register will trigger fault. */
+        return kStatus_Fail;
+    }
+
+    /* Clear pending errors, otherwise the device will reset */
+    /* itself immediately after enable Code Watchdog */
+    if ((uint32_t)kCDOG_LockCtrl_Lock ==
+        ((base->CONTROL & CDOG_CONTROL_LOCK_CTRL_MASK) >> CDOG_CONTROL_LOCK_CTRL_SHIFT))
+
+    {
+        base->FLAGS = CDOG_FLAGS_TO_FLAG(1U) | CDOG_FLAGS_MISCOM_FLAG(1U) | CDOG_FLAGS_SEQ_FLAG(1U) |
+                      CDOG_FLAGS_CNT_FLAG(1U) | CDOG_FLAGS_STATE_FLAG(1U) | CDOG_FLAGS_ADDR_FLAG(1U) |
+                      CDOG_FLAGS_POR_FLAG(1U);
+    }
+    else
+    {
+/* load default values for CDOG->CONTROL before flags clear */
+#if defined(FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF) && (FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF > 0)
+        cdog_config_t default_conf;
+
+        /* Initialize CDOG */
+        CDOG_GetDefaultConfig(&default_conf);
+
+        /* Write default value to CDOG->CONTROL*/
+        base->CONTROL = 
+            CDOG_CONTROL_TIMEOUT_CTRL(default_conf.timeout) |       /* Action if the timeout event is triggered  */
+            CDOG_CONTROL_MISCOMPARE_CTRL(default_conf.miscompare) | /* Action if the miscompare error event is triggered  */
+            CDOG_CONTROL_SEQUENCE_CTRL(default_conf.sequence) |     /* Action if the sequence error event is triggered  */
+            CDOG_CONTROL_STATE_CTRL(default_conf.state) |           /* Action if the state error event is triggered  */
+            CDOG_CONTROL_ADDRESS_CTRL(default_conf.address) |       /* Action if the address error event is triggered */
+            CDOG_CONTROL_IRQ_PAUSE(default_conf.irq_pause) |        /* Pause running during interrupts setup */
+            CDOG_CONTROL_DEBUG_HALT_CTRL(default_conf.debug_halt) | /* Halt CDOG timer during debug */
+            CDOG_CONTROL_LOCK_CTRL(default_conf.lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
+#endif /* FSL_FEATURE_CDOG_NEED_LOAD_DEFAULT_CONF */
+
+        base->FLAGS = CDOG_FLAGS_TO_FLAG(0U) | CDOG_FLAGS_MISCOM_FLAG(0U) | CDOG_FLAGS_SEQ_FLAG(0U) |
+                      CDOG_FLAGS_CNT_FLAG(0U) | CDOG_FLAGS_STATE_FLAG(0U) | CDOG_FLAGS_ADDR_FLAG(0U) |
+                      CDOG_FLAGS_POR_FLAG(0U);
+    }
+
+    base->CONTROL =
+        CDOG_CONTROL_TIMEOUT_CTRL(conf->timeout) |       /* Action if the timeout event is triggered  */
+        CDOG_CONTROL_MISCOMPARE_CTRL(conf->miscompare) | /* Action if the miscompare error event is triggered  */
+        CDOG_CONTROL_SEQUENCE_CTRL(conf->sequence) |     /* Action if the sequence error event is triggered  */
+        CDOG_CONTROL_STATE_CTRL(conf->state) |           /* Action if the state error event is triggered  */
+        CDOG_CONTROL_ADDRESS_CTRL(conf->address) |       /* Action if the address error event is triggered */
+        CDOG_CONTROL_IRQ_PAUSE(conf->irq_pause) |        /* Pause running during interrupts setup */
+        CDOG_CONTROL_DEBUG_HALT_CTRL(conf->debug_halt) | /* Halt CDOG timer during debug */
+        CDOG_CONTROL_LOCK_CTRL(conf->lock) | RESERVED_CTRL_MASK; /* Lock control register, RESERVED */
+
+#if defined(CDOG_IRQS)
+    /* Enable peripheral IRQ */
+    NVIC_EnableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
+#endif /* CDOG_IRQS */
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitialize CDOG
+ *
+ * This function stops CDOG secure counter.
+ *
+ * param base CDOG peripheral base address
+ */
+void CDOG_Deinit(CDOG_Type *base)
+{
+#if defined(CDOG_IRQS)
+    /* Disable peripheral IRQ */
+    NVIC_DisableIRQ(s_CdogIrqs[CDOG_GetInstance(base)]);
+#endif /* CDOG_IRQS */
+
+#if !(defined(FSL_FEATURE_CDOG_HAS_NO_RESET) && FSL_FEATURE_CDOG_HAS_NO_RESET)
+    RESET_SetPeripheralReset(kCDOG_RST_SHIFT_RSTn);
+#endif /* !FSL_FEATURE_CDOG_HAS_NO_RESET */
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#ifdef CDOG_CLOCKS
+    CLOCK_DisableClock(s_CdogClocks[CDOG_GetInstance(base)]);
+#endif /* CDOG_CLOCKS */
+#endif /* !FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_cdog.h

@@ -0,0 +1,329 @@
+/*
+ * Copyright 2020-2022 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_CDOG_H_
+#define FSL_CDOG_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup CDOG
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*! @{ */
+/*! @brief Defines CDOG driver version 2.1.3.
+ *
+ * Change log:
+ * - Version 2.1.3
+ *   - Re-design multiple instance IRQs and Clocks
+ *   - Add fix for RESTART command errata
+ * - Version 2.1.2
+ *   - Support multiple IRQs
+ *   - Fix default CONTROL values
+ * - Version 2.1.1
+ *   - Remove bit CONTROL[CONTROL_CTRL]
+ * - Version 2.1.0
+ *   - Rename CWT to CDOG
+ * - Version 2.0.2
+ *   - Fix MISRA-2012 issues
+ * - Version 2.0.1
+ *   - Fix doxygen issues
+ * - Version 2.0.0
+ *   - initial version
+ */
+#define FSL_CDOG_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @} */
+
+typedef struct
+{
+    uint8_t lock : 2;
+    uint8_t timeout : 3;
+    uint8_t miscompare : 3;
+    uint8_t sequence : 3;
+    uint8_t state : 3;
+    uint8_t address : 3;
+    uint8_t reserved : 8;
+    uint8_t irq_pause : 2;
+    uint8_t debug_halt : 2;
+} cdog_config_t;
+
+enum __cdog_debug_Action_ctrl_enum
+{
+    kCDOG_DebugHaltCtrl_Run   = 0x1,
+    kCDOG_DebugHaltCtrl_Pause = 0x2,
+};
+
+enum __cdog_irq_pause_ctrl_enum
+{
+    kCDOG_IrqPauseCtrl_Run   = 0x1,
+    kCDOG_IrqPauseCtrl_Pause = 0x2,
+};
+
+enum __cdog_fault_ctrl_enum
+{
+    kCDOG_FaultCtrl_EnableReset     = 0x1U,
+    kCDOG_FaultCtrl_EnableInterrupt = 0x2U,
+    kCDOG_FaultCtrl_NoAction        = 0x4U,
+};
+
+enum __code_lock_ctrl_enum
+{
+    kCDOG_LockCtrl_Lock   = 0x1,
+    kCDOG_LockCtrl_Unlock = 0x2,
+};
+
+typedef uint32_t secure_counter_t;
+
+#define SC_ADD(add)                          \
+    do                                       \
+    {                                        \
+        CDOG->ADD = (secure_counter_t)(add); \
+    } while (0)
+
+#define SC_ADD1                              \
+    do                                       \
+    {                                        \
+        CDOG->ADD1 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_ADD16                              \
+    do                                        \
+    {                                         \
+        CDOG->ADD16 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_ADD256                              \
+    do                                         \
+    {                                          \
+        CDOG->ADD256 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_SUB(sub)                          \
+    do                                       \
+    {                                        \
+        CDOG->SUB = (secure_counter_t)(sub); \
+    } while (0)
+
+#define SC_SUB1                              \
+    do                                       \
+    {                                        \
+        CDOG->SUB1 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_SUB16                              \
+    do                                        \
+    {                                         \
+        CDOG->SUB16 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_SUB256                              \
+    do                                         \
+    {                                          \
+        CDOG->SUB256 = (secure_counter_t)0x1U; \
+    } while (0)
+
+#define SC_CHECK(val)                          \
+    do                                         \
+    {                                          \
+        CDOG->RESTART = (secure_counter_t)val; \
+    } while (0)
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name CDOG Functional Operation
+ * @{
+ */
+
+/*!
+ * @brief Initialize CDOG
+ *
+ * This function initializes CDOG block and setting.
+ *
+ * @param base CDOG peripheral base address
+ * @param conf CDOG configuration structure
+ * @return Status of the init operation
+ */
+status_t CDOG_Init(CDOG_Type *base, cdog_config_t *conf);
+
+/*!
+ * @brief Deinitialize CDOG
+ *
+ * This function deinitializes CDOG secure counter.
+ *
+ * @param base CDOG peripheral base address
+ */
+void CDOG_Deinit(CDOG_Type *base);
+
+/*!
+ * @brief Sets the default configuration of CDOG
+ *
+ * This function initialize CDOG config structure to default values.
+ *
+ * @param conf CDOG configuration structure
+ */
+void CDOG_GetDefaultConfig(cdog_config_t *conf);
+
+/*!
+ * @brief Stops secure counter and instruction timer
+ *
+ * This function stops instruction timer and secure counter.
+ * This also change state od CDOG to IDLE.
+ *
+ * @param base CDOG peripheral base address
+ * @param stop expected value which will be compared with value of secure counter
+ */
+void CDOG_Stop(CDOG_Type *base, uint32_t stop);
+
+/*!
+ * @brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in RELOAD and START registers
+ * for instruction timer and secure counter
+ *
+ * @param base CDOG peripheral base address
+ * @param reload reload value
+ * @param start start value
+ */
+void CDOG_Start(CDOG_Type *base, uint32_t reload, uint32_t start);
+
+/*!
+ * @brief Checks secure counter.
+ *
+ * This function compares stop value in handler with secure counter value
+ * by writting to RELOAD refister.
+ *
+ * @param base CDOG peripheral base address
+ * @param check expected (stop) value
+ */
+void CDOG_Check(CDOG_Type *base, uint32_t check);
+
+/*!
+ * @brief Sets secure counter and instruction timer values
+ *
+ * This function sets value in STOP, RELOAD and START registers
+ * for instruction timer and secure counter.
+ *
+ * @param base CDOG peripheral base address
+ * @param stop expected value which will be compared with value of secure counter
+ * @param reload reload value for instruction timer
+ * @param start start value for secure timer
+ */
+void CDOG_Set(CDOG_Type *base, uint32_t stop, uint32_t reload, uint32_t start);
+
+/*!
+ * @brief Add value to secure counter
+ *
+ * This function add specified value to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ * @param add Value to be added.
+ */
+void CDOG_Add(CDOG_Type *base, uint32_t add);
+
+/*!
+ * @brief Add 1 to secure counter
+ *
+ * This function add 1 to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Add1(CDOG_Type *base);
+
+/*!
+ * @brief Add 16 to secure counter
+ *
+ * This function add 16 to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Add16(CDOG_Type *base);
+
+/*!
+ * @brief Add 256 to secure counter
+ *
+ * This function add 256 to secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Add256(CDOG_Type *base);
+
+/*!
+ * brief Substract value to secure counter
+ *
+ * This function substract specified value to secure counter.
+ *
+ * param base CDOG peripheral base address.
+ * param sub Value to be substracted.
+ */
+void CDOG_Sub(CDOG_Type *base, uint32_t sub);
+
+/*!
+ * @brief Substract 1 from secure counter
+ *
+ * This function substract specified 1 from secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Sub1(CDOG_Type *base);
+
+/*!
+ * @brief Substract 16 from secure counter
+ *
+ * This function substract specified 16 from secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Sub16(CDOG_Type *base);
+
+/*!
+ * @brief Substract 256 from secure counter
+ *
+ * This function substract specified 256 from secure counter.
+ *
+ * @param base CDOG peripheral base address.
+ */
+void CDOG_Sub256(CDOG_Type *base);
+
+/*!
+ * @brief Set the CDOG persistent word.
+ *
+ * @param base CDOG peripheral base address.
+ * @param value The value to be written.
+ */
+void CDOG_WritePersistent(CDOG_Type *base, uint32_t value);
+
+/*!
+ * @brief Get the CDOG persistent word.
+ *
+ * @param base CDOG peripheral base address.
+ * @return The persistent word.
+ */
+uint32_t CDOG_ReadPersistent(CDOG_Type *base);
+
+/*! @}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/ /* end of group cdog */
+
+#endif /* FSL_CDOG_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_clock.c

@@ -283,8 +283,8 @@ status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask)
     VBAT0->FROCTLA |= VBAT_FROCTLA_FRO_EN_MASK;
     VBAT0->FROLCKA |= VBAT_FROLCKA_LOCK_MASK;
 
-    /* enable clk_16k0 and clk_16k1. */
-    VBAT0->FROCLKE = VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask) & VBAT_FROCLKE_CLKE_MASK);
+    /* enable clk_16k output clock to corresponding modules according to the enable_mask. */
+    VBAT0->FROCLKE |= VBAT_FROCLKE_CLKE(((uint32_t)clk_16k_enable_mask));
 
     return kStatus_Success;
 }
@@ -347,6 +347,47 @@ status_t CLOCK_SetupExtClocking(uint32_t iFreq)
     return kStatus_Success;
 }
 
+/*!
+ * @brief   Initialize the external reference clock to given frequency.
+ * param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq)
+{
+    
+    if (iFreq > 50000000U)
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If configure register is locked, return error. */
+    if ((SCG0->SOSCCSR & SCG_SOSCCSR_LK_MASK) != 0U)
+    {
+        return kStatus_ReadOnly;
+    }
+
+    /* De-initializes the SCG SOSC */
+    SCG0->SOSCCSR = SCG_SOSCCSR_SOSCERR_MASK;
+
+    /* Select SOSC source (external reference clock)*/
+    SCG0->SOSCCFG &= ~SCG_SOSCCFG_EREFS_MASK;
+
+    /* Unlock SOSCCSR */
+    SCG0->SOSCCSR &= ~SCG_SOSCCSR_LK_MASK;
+
+    /* Enable SOSC clock monitor and Enable SOSC */
+    SCG0->SOSCCSR |= (SCG_SOSCCSR_SOSCCM_MASK | SCG_SOSCCSR_SOSCEN_MASK);
+
+    /* Wait for SOSC clock to be valid. */
+    while ((SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) == 0U)
+    {
+    }
+
+    s_Ext_Clk_Freq = iFreq;
+
+    return kStatus_Success;
+}
+
 /* Get IP Clk */
 /*! brief  Return Frequency of selected clock
  *  return Frequency of selected clock
@@ -550,9 +591,9 @@ uint32_t CLOCK_GetCoreSysClkFreq(void)
     return CLOCK_GetMainClk() / ((SYSCON->AHBCLKDIV & 0xFFU) + 1U);
 }
 
-/* Get LPI2C Clk */
-/*! brief  Return Frequency of CTimer functional Clock
- *  return Frequency of CTimer functional Clock
+/* Get I3C Clk */
+/*! brief  Return Frequency of I3C Clock
+ *  return Frequency of I3C Clock
  */
 uint32_t CLOCK_GetI3CFClkFreq(void)
 {
@@ -630,8 +671,8 @@ uint32_t CLOCK_GetCTimerClkFreq(uint32_t id)
 }
 
 /* Get LPI2C Clk */
-/*! brief  Return Frequency of CTimer functional Clock
- *  return Frequency of CTimer functional Clock
+/*! brief  Return Frequency of LPI2C functional Clock
+ *  return Frequency of LPI2C functional Clock
  */
 uint32_t CLOCK_GetLpi2cClkFreq(void)
 {

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_clock.h

@@ -696,6 +696,13 @@ status_t CLOCK_SetupFRO16KClocking(uint8_t clk_16k_enable_mask);
  */
 status_t CLOCK_SetupExtClocking(uint32_t iFreq);
 
+/**
+ * @brief   Initialize the external reference clock to given frequency.
+ * @param   iFreq   : Desired frequency (must be equal to exact rate in Hz)
+ * @return  returns success or fail status.
+ */
+status_t CLOCK_SetupExtRefClocking(uint32_t iFreq);
+
 /*! @brief  Return Frequency of selected clock
  *  @return Frequency of selected clock
  */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_cmc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 ~ 2023 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -18,14 +18,7 @@
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
-#if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
-#define CMC_SRAMDIS_RESERVED_MASK                                                                                   \
-    (~(kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 | kCMC_RAMD1 |       \
-       kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 | kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | \
-       kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ | kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI))
 
-#define CMC_SRAMRET_RESERVED_MASK (CMC_SRAMDIS_RESERVED_MASK)
-#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 /*******************************************************************************
  * Variables
  ******************************************************************************/
@@ -127,10 +120,11 @@ void CMC_ConfigResetPin(CMC_Type *base, const cmc_reset_pin_config_t *config)
  */
 void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
 {
-    uint32_t reg = base->SRAMDIS[0];
+    uint32_t reg       = base->SRAMDIS[0];
+    uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
 
-    reg &= ~(CMC_SRAMDIS_DIS_MASK | CMC_SRAMDIS_RESERVED_MASK);
-    reg |= CMC_SRAMDIS_DIS(mask);
+    reg &= ~((uint32_t)kCMC_AllSramArrays);
+    reg |= CMC_SRAMDIS_DIS(maskToSet);
     base->SRAMDIS[0] = reg;
 }
 
@@ -145,14 +139,36 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask)
  */
 void CMC_PowerOffSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
 {
-    uint32_t reg = base->SRAMRET[0];
+    uint32_t reg       = base->SRAMRET[0];
+    uint32_t maskToSet = mask & ((uint32_t)kCMC_AllSramArrays);
 
-    reg &= ~(CMC_SRAMRET_RET_MASK | CMC_SRAMRET_RESERVED_MASK);
-    reg |= CMC_SRAMRET_RET(mask);
+    reg &= ~((uint32_t)kCMC_AllSramArrays);
+    reg |= CMC_SRAMRET_RET(maskToSet);
     base->SRAMRET[0] = reg;
 }
 #endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
+/*!
+ * brief Configs the low power mode of the on-chip flash memory.
+ *
+ * This function configs the low power mode of the on-chip flash memory.
+ *
+ * param base CMC peripheral base address.
+ * param doze true: Flash is disabled while core is sleeping
+ *             false: No effect.
+ * param disable true: Flash memory is placed in low power state.
+ *                false: No effect.
+ */
+void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable)
+{
+    uint32_t reg = 0UL;
+
+    reg |= (disable ? CMC_FLASHCR_FLASHDIS(1U) : CMC_FLASHCR_FLASHDIS(0U)) |
+           (doze ? CMC_FLASHCR_FLASHDOZE(1U) : CMC_FLASHCR_FLASHDOZE(0U));
+    base->FLASHCR = reg;
+}
+#else
 /*!
  * brief Configs the low power mode of the on-chip flash memory.
  *
@@ -178,6 +194,7 @@ void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable)
            (wake ? CMC_FLASHCR_FLASHWAKE(1U) : CMC_FLASHCR_FLASHWAKE(0U));
     base->FLASHCR = reg;
 }
+#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
 
 /*!
  * brief Prepares to enter stop modes.
@@ -274,7 +291,7 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
         CMC_SetMAINPowerMode(base, config->main_domain);
 #if (CMC_PMCTRL_COUNT > 1U)
         CMC_SetWAKEPowerMode(base, config->wake_domain);
-#endif /* (CMC_PMCTRL_COUNT > 1U) */
+#endif  /* (CMC_PMCTRL_COUNT > 1U) */
 
         /* Before execute WFI instruction read back the last register to
          * ensure all registers writes have completed. */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_cmc.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2022 ~ 2023 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_CMC_H_
-#define _FSL_CMC_H_
+#ifndef FSL_CMC_H_
+#define FSL_CMC_H_
 #include "fsl_common.h"
 
 /*!
@@ -17,8 +17,8 @@
  ******************************************************************************/
 /*! @name Driver version */
 /*@{*/
-/*! @brief CMC driver version 2.1.0. */
-#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
+/*! @brief CMC driver version 2.2.2. */
+#define FSL_CMC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
 /* @} */
 
 /*!
@@ -61,22 +61,25 @@ enum _cmc_system_reset_interrupt_enable
                                                                                     Reset interrupt enable. */
     kCMC_WindowedWatchdog0ResetInterruptEnable = CMC_SRIE_WWDT0_MASK,          /*!< Windowed Watchdog 0 reset
                                                                                  interrupt enable. */
-    kCMC_SoftwareResetInterruptEnable          = CMC_SRIE_SW_MASK,             /*!< Software Reset interrupt enable. */
-    kCMC_LockupResetInterruptEnable            = CMC_SRIE_LOCKUP_MASK,         /*!< Lockup Reset interrupt enable. */
+    kCMC_SoftwareResetInterruptEnable = CMC_SRIE_SW_MASK,                      /*!< Software Reset interrupt enable. */
+    kCMC_LockupResetInterruptEnable   = CMC_SRIE_LOCKUP_MASK,                  /*!< Lockup Reset interrupt enable. */
 #if defined(CMC_SRIE_CPU1_MASK)
-    kCMC_Cpu1ResetInterruptEnable              = CMC_SRIE_CPU1_MASK,           /*!< CPU1 Reset interrupt enable. */
-#endif /* CMC_SRIE_CPU1_MASK */
+    kCMC_Cpu1ResetInterruptEnable = CMC_SRIE_CPU1_MASK,                        /*!< CPU1 Reset interrupt enable. */
+#endif                                                                         /* CMC_SRIE_CPU1_MASK */
+#if defined(CMC_SRIE_ADVC_MASK)
+    kCMC_AdvcResetInterruptEnable = CMC_SRIE_ADVC_MASK,                        /*!< ADVC Reset interrupt enable. */
+#endif                                                                         /* CMC_SRIE_ADVC_MASK */
 #if defined(CMC_SRIE_VBAT_MASK)
-    kCMC_VBATResetInterruptEnable              = CMC_SRIE_VBAT_MASK,           /*!< VBAT reset interrupt enable. */
-#endif /* CMC_SRIE_VBAT_MASK */
+    kCMC_VBATResetInterruptEnable = CMC_SRIE_VBAT_MASK,                        /*!< VBAT reset interrupt enable. */
+#endif                                                                         /* CMC_SRIE_VBAT_MASK */
 #if defined(CMC_SRIE_WWDT1_MASK)
     kCMC_WindowedWatchdog1ResetInterruptEnable = CMC_SRIE_WWDT1_MASK,          /*!< Windowed Watchdog 1 reset
                                                                                      interrupt enable. */
-#endif /* CMC_SRIE_WWDT1_MASK */
+#endif                                                                         /* CMC_SRIE_WWDT1_MASK */
     kCMC_CodeWatchDog0ResetInterruptEnable = CMC_SRIE_CDOG0_MASK, /*!< Code watchdog 0 reset interrupt enable. */
 #if defined(CMC_SRIE_CDOG1_MASK)
     kCMC_CodeWatchDog1ResetInterruptEnable = CMC_SRIE_CDOG1_MASK, /*!< Code watchdog 1 reset interrupt enable. */
-#endif /* CMC_SRIE_CDOG1_MASK */
+#endif                                                            /* CMC_SRIE_CDOG1_MASK */
 };
 
 /*!
@@ -92,18 +95,21 @@ enum _cmc_system_reset_interrupt_flag
     kCMC_SoftwareResetInterruptFlag          = CMC_SRIF_SW_MASK,     /*!< Software Reset interrupt flag. */
     kCMC_LockupResetInterruptFlag            = CMC_SRIF_LOCKUP_MASK, /*!< Lock up Reset interrupt flag. */
 #if defined(CMC_SRIF_CPU1_MASK)
-    kCMC_Cpu1ResetInterruptFlag              = CMC_SRIF_CPU1_MASK,   /*!< CPU1 Reset interrupt flag. */
-#endif /* CMC_SRIF_CPU1_MASK */
+    kCMC_Cpu1ResetInterruptFlag = CMC_SRIF_CPU1_MASK,                /*!< CPU1 Reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_CPU1_MASK */
+#if defined(CMC_SRIF_ADVC_MASK)
+    kCMC_AdvcResetInterruptFlag = CMC_SRIF_ADVC_MASK,                /*!< ADVC Reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_ADVC_MASK */
 #if defined(CMC_SRIF_VBAT_MASK)
-    kCMC_VbatResetInterruptFlag              = CMC_SRIF_VBAT_MASK,   /*!< VBAT system reset interrupt flag. */
-#endif /* CMC_SRIF_VBAT_MASK */
+    kCMC_VbatResetInterruptFlag = CMC_SRIF_VBAT_MASK,                /*!< VBAT system reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_VBAT_MASK */
 #if defined(CMC_SRIF_WWDT1_MASK)
     kCMC_WindowedWatchdog1ResetInterruptFlag = CMC_SRIF_WWDT1_MASK,  /*!< Windowned Watchdog 1 Reset interrupt flag. */
-#endif /* CMC_SRIF_WWDT1_MASK */
-    kCMC_CodeWatchdog0ResetInterruptFlag     = CMC_SRIF_CDOG0_MASK,  /*!< Code watchdog0 reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_WWDT1_MASK */
+    kCMC_CodeWatchdog0ResetInterruptFlag = CMC_SRIF_CDOG0_MASK,      /*!< Code watchdog0 reset interrupt flag. */
 #if defined(CMC_SRIF_CDOG1_MASK)
-    kCMC_CodeWatchdog1ResetInterruptFlag     = CMC_SRIF_CDOG1_MASK,  /*!< Code watchdog1 reset interrupt flag. */
-#endif /* CMC_SRIF_CDOG1_MASK */
+    kCMC_CodeWatchdog1ResetInterruptFlag = CMC_SRIF_CDOG1_MASK,      /*!< Code watchdog1 reset interrupt flag. */
+#endif                                                               /* CMC_SRIF_CDOG1_MASK */
 };
 
 #if (defined(FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG) && FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG)
@@ -133,8 +139,13 @@ enum _cmc_system_sram_arrays
     kCMC_PQ                  = 1UL << 27UL, /*!< Used to control PQ. */
     kCMC_CAN0_CAN1_ENET_USB1 = 1UL << 28UL, /*!< Used to control CAN0, CAN1, ENET, USB1. */
     kCMC_FlexSPI             = 1UL << 29UL, /*!< Used to control FlexSPI. */
+
+    kCMC_AllSramArrays = (kCMC_RAMX0 | kCMC_RAMX1 | kCMC_RAMX2 | kCMC_RAMB | kCMC_RAMC0 | kCMC_RAMC1 | kCMC_RAMD0 |
+                          kCMC_RAMD1 | kCMC_RAME0 | kCMC_RAME1 | kCMC_RAMF0 | kCMC_RAMF1 | kCMC_RAMG0_RAMG1 |
+                          kCMC_RAMG2_RAMG3 | kCMC_RAMH0_RAMH1 | kCMC_LPCAC | kCMC_DMA0_DMA1_PKC | kCMC_USB0 | kCMC_PQ |
+                          kCMC_CAN0_CAN1_ENET_USB1 | kCMC_FlexSPI), /*!< Mask of all System SRAM arrays. */
 };
-#endif /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
+#endif                                                              /* FSL_FEATURE_MCX_CMC_HAS_SRAM_DIS_REG */
 
 /*!
  * @brief System reset sources enumeration.
@@ -158,25 +169,28 @@ enum _cmc_system_reset_sources
     kCMC_SoftwareReset          = CMC_SRS_SW_MASK,    /*!< The reset caused by a software reset request. */
     kCMC_LockUoReset = CMC_SRS_LOCKUP_MASK, /*!< The reset caused by the ARM core indication of a LOCKUP event. */
 #if defined(CMC_SRS_CPU1_MASK)
-    kCMC_Cpu1Reset   = CMC_SRS_CPU1_MASK,   /*!< The reset caused by a CPU1 system reset. */
-#endif /* CMC_SRS_CPU1_MASK */
+    kCMC_Cpu1Reset = CMC_SRS_CPU1_MASK,     /*!< The reset caused by a CPU1 system reset. */
+#endif                                      /* CMC_SRS_CPU1_MASK */
+#if defined(CMC_SRS_ADVC_MASK)
+    kCMC_AdvcReset = CMC_SRS_ADVC_MASK,     /*!< The reset caused by ADVC critical reset.  */
+#endif                                      /* CMC_SRS_ADVC_MASK */
 #if defined(CMC_SRS_VBAT_MASK)
-    kCMC_VbatReset   = CMC_SRS_VBAT_MASK,   /*!< The reset caused by a VBAT POR. */
-#endif /* CMC_SRS_VBAT_MASK */
+    kCMC_VbatReset = CMC_SRS_VBAT_MASK,     /*!< The reset caused by a VBAT POR. */
+#endif                                      /* CMC_SRS_VBAT_MASK */
 #if defined(CMC_SRS_WWDT1_MASK)
     kCMC_WindowedWatchdog1Reset = CMC_SRS_WWDT1_MASK,  /*!< The reset caused by the Windowed WatchDog 1 timeout. */
-#endif /* CMC_SRS_WWDT1_MASK */
-    kCMC_CodeWatchDog0Reset     = CMC_SRS_CDOG0_MASK,  /*!< The reset caused by the code watchdog0 fault. */
+#endif                                                 /* CMC_SRS_WWDT1_MASK */
+    kCMC_CodeWatchDog0Reset = CMC_SRS_CDOG0_MASK,      /*!< The reset caused by the code watchdog0 fault. */
 #if defined(CMC_SRS_CDOG1_MASK)
-    kCMC_CodeWatchDog1Reset     = CMC_SRS_CDOG1_MASK,  /*!< The reset caused by the code watchdog1 fault. */
-#endif /* CMC_SRS_CDOG1_MASK */
-    kCMC_JTAGSystemReset        = CMC_SRS_JTAG_MASK,   /*!< The reset caused by a JTAG system reset request. */
+    kCMC_CodeWatchDog1Reset = CMC_SRS_CDOG1_MASK,      /*!< The reset caused by the code watchdog1 fault. */
+#endif                                                 /* CMC_SRS_CDOG1_MASK */
+    kCMC_JTAGSystemReset = CMC_SRS_JTAG_MASK,          /*!< The reset caused by a JTAG system reset request. */
 #if defined(CMC_SRS_SECVIO_MASK)
     kCMC_SecurityViolationReset = CMC_SRS_SECVIO_MASK, /*!< The reset caused by a Security Violation logic. */
-#endif /* CMC_SRS_SECVIO_MASK */
+#endif                                                 /* CMC_SRS_SECVIO_MASK */
 #if defined(CMC_SRS_TAMPER_MASK)
-    kCMC_TapmerReset            = CMC_SRS_TAMPER_MASK, /*!< The reset caused by the tamper detection logic. */
-#endif /* CMC_SRS_TAMPER_MASK */
+    kCMC_TapmerReset = CMC_SRS_TAMPER_MASK,            /*!< The reset caused by the tamper detection logic. */
+#endif                                                 /* CMC_SRS_TAMPER_MASK */
 };
 
 /*!
@@ -231,7 +245,7 @@ typedef struct _cmc_power_domain_config
     cmc_low_power_mode_t main_domain; /*!< The low power mode of the MAIN power domain. */
 #if (CMC_PMCTRL_COUNT > 1U)
     cmc_low_power_mode_t wake_domain; /*!< The low power mode of the WAKE power domain. */
-#endif /* (CMC_PMCTRL_COUNT > 1U) */
+#endif                                /* (CMC_PMCTRL_COUNT > 1U) */
 } cmc_power_domain_config_t;
 
 /*******************************************************************************
@@ -736,10 +750,12 @@ static inline void CMC_UnlockBootRomStatusWritten(CMC_Type *base)
 /*!
  * @brief Power off the selected system SRAM always.
  *
- * This function power off the selected system SRAM always. The SRAM arrays should
+ * @note This function power off the selected system SRAM always. The SRAM arrays should
  * not be accessed while they are shut down. SRAM array contents are not retained
  * if they are powered off.
  *
+ * @note Once invoked, the previous settings will be overwritten.
+ *
  * @param base CMC peripheral base address.
  * @param mask Bitmap of the SRAM arrays to be powered off all modes.
  *             See @ref _cmc_system_sram_arrays for details.
@@ -750,6 +766,8 @@ void CMC_PowerOffSRAMAllMode(CMC_Type *base, uint32_t mask);
 /*!
  * @brief Power on SRAM during all mode.
  *
+ * @note Once invoked, the previous settings will be overwritten.
+ *
  * @param base CMC peripheral base address.
  * @param mask Bitmap of the SRAM arrays to be powered on all modes.
  *             See @ref _cmc_system_sram_arrays for details.
@@ -796,6 +814,21 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
  * @name Flash Low Power Mode configuration.
  * @{
  */
+
+#if (defined(FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE) && FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE)
+/*!
+ * @brief Configs the low power mode of the on-chip flash memory.
+ *
+ * This function configs the low power mode of the on-chip flash memory.
+ *
+ * @param base CMC peripheral base address.
+ * @param doze true: Flash is disabled while core is sleeping
+ *             false: No effect.
+ * @param disable true: Flash memory is placed in low power state.
+ *                false: No effect.
+ */
+void CMC_ConfigFlashMode(CMC_Type *base, bool doze, bool disable);
+#else
 /*!
  * @brief Configs the low power mode of the on-chip flash memory.
  *
@@ -810,7 +843,7 @@ static inline void CMC_PowerOnSRAMLowPowerOnly(CMC_Type *base, uint32_t mask)
  *                false: No effect.
  */
 void CMC_ConfigFlashMode(CMC_Type *base, bool wake, bool doze, bool disable);
-
+#endif /* FSL_FEATURE_MCX_CMC_HAS_NO_FLASHCR_WAKE */
 /* @} */
 
 /*!
@@ -893,4 +926,4 @@ void CMC_EnterLowPowerMode(CMC_Type *base, const cmc_power_domain_config_t *conf
 #endif /* __cplusplus */
 
 /*! @}*/
-#endif /* _FSL_CMC_H_ */
+#endif /* FSL_CMC_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_common.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_COMMON_H_
-#define _FSL_COMMON_H_
+#ifndef FSL_COMMON_H_
+#define FSL_COMMON_H_
 
 #include <assert.h>
 #include <stdbool.h>
@@ -57,12 +57,13 @@
 #define MAKE_VERSION(major, minor, bugfix) (((major)*65536L) + ((minor)*256L) + (bugfix))
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief common driver version. */
-#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
-/*@}*/
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
+/*! @} */
 
-/* Debug console type definition. */
+/*! @name Debug console type definition. */
+/*! @{ */
 #define DEBUG_CONSOLE_DEVICE_TYPE_NONE       0U  /*!< No debug console.             */
 #define DEBUG_CONSOLE_DEVICE_TYPE_UART       1U  /*!< Debug console based on UART.   */
 #define DEBUG_CONSOLE_DEVICE_TYPE_LPUART     2U  /*!< Debug console based on LPUART. */
@@ -74,6 +75,7 @@
 #define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART 8U  /*!< Debug console based on LPC_USART. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_SWO        9U  /*!< Debug console based on SWO. */
 #define DEBUG_CONSOLE_DEVICE_TYPE_QSCI       10U /*!< Debug console based on QSCI. */
+/*! @} */
 
 /*! @brief Status group numbers. */
 enum _status_groups
@@ -156,6 +158,9 @@ enum _status_groups
     kStatusGroup_PUF                   = 105, /*!< Group number for PUF status codes. */
     kStatusGroup_TOUCH_PANEL           = 106, /*!< Group number for touch panel status codes */
     kStatusGroup_VBAT                  = 107, /*!< Group number for VBAT status codes */
+    kStatusGroup_XSPI                  = 108, /*!< Group number for XSPI status codes */
+    kStatusGroup_PNGDEC                = 109, /*!< Group number for PNGDEC status codes */
+    kStatusGroup_JPEGDEC               = 110, /*!< Group number for JPEGDEC status codes */
 
     kStatusGroup_HAL_GPIO       = 121, /*!< Group number for HAL GPIO status codes. */
     kStatusGroup_HAL_UART       = 122, /*!< Group number for HAL UART status codes. */
@@ -189,7 +194,7 @@ enum _status_groups
     kStatusGroup_LOG            = 154, /*!< Group number for LOG status codes. */
     kStatusGroup_I3CBUS         = 155, /*!< Group number for I3CBUS status codes. */
     kStatusGroup_QSCI           = 156, /*!< Group number for QSCI status codes. */
-    kStatusGroup_SNT            = 157, /*!< Group number for SNT status codes. */
+    kStatusGroup_ELEMU          = 157, /*!< Group number for ELEMU status codes. */
     kStatusGroup_QUEUEDSPI      = 158, /*!< Group number for QSPI status codes. */
     kStatusGroup_POWER_MANAGER  = 159, /*!< Group number for POWER_MANAGER status codes. */
     kStatusGroup_IPED           = 160, /*!< Group number for IPED status codes. */
@@ -224,48 +229,66 @@ enum
 /*! @brief Type used for all status and error return values. */
 typedef int32_t status_t;
 
+#ifdef __ZEPHYR__
+#include <zephyr/sys/util.h>
+#else
 /*!
  * @name Min/max macros
  * @{
  */
 #if !defined(MIN)
+/*! Computes the minimum of \a a and \a b. */
 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
 #endif
 
 #if !defined(MAX)
+/*! Computes the maximum of \a a and \a b. */
 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
 #endif
-/* @} */
+/*! @} */
 
 /*! @brief Computes the number of elements in an array. */
 #if !defined(ARRAY_SIZE)
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
 #endif
+#endif /* __ZEPHYR__ */
 
 /*! @name UINT16_MAX/UINT32_MAX value */
-/* @{ */
+/*! @{ */
 #if !defined(UINT16_MAX)
+/*! Max value of uint16_t type. */
 #define UINT16_MAX ((uint16_t)-1)
 #endif
 
 #if !defined(UINT32_MAX)
+/*! Max value of uint32_t type. */
 #define UINT32_MAX ((uint32_t)-1)
 #endif
-/* @} */
+/*! @} */
 
-/*! @name Suppress fallthrough warning macro */
-/* For switch case code block, if case section ends without "break;" statement, there wil be
- fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
- To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
- case section which misses "break;"statement.
+/*! Macro to get upper 32 bits of a 64-bit value */
+#if !defined(UINT64_H)
+#define UINT64_H(X)        ((uint32_t)((((uint64_t) (X)) >> 32U) & 0x0FFFFFFFFULL))
+#endif
+
+/*! Macro to get lower 32 bits of a 64-bit value */
+#if !defined(UINT64_L)
+#define UINT64_L(X)        ((uint32_t)(((uint64_t) (X)) & 0x0FFFFFFFFULL))
+#endif
+
+/*!
+ * @def SUPPRESS_FALL_THROUGH_WARNING()
+ *
+ * For switch case code block, if case section ends without "break;" statement, there wil be
+ * fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ * To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ * case section which misses "break;"statement.
  */
-/* @{ */
 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
 #define SUPPRESS_FALL_THROUGH_WARNING() __attribute__((fallthrough))
 #else
 #define SUPPRESS_FALL_THROUGH_WARNING()
 #endif
-/* @} */
 
 /*******************************************************************************
  * API
@@ -319,4 +342,4 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz);
 #include "fsl_common_arm.h"
 #endif
 
-#endif /* _FSL_COMMON_H_ */
+#endif /* FSL_COMMON_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_common_arm.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2021 NXP
+ * Copyright 2016-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -25,11 +25,11 @@ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
 #if defined(__CC_ARM) || defined(__ARMCC_VERSION)
     extern uint32_t Image$$VECTOR_ROM$$Base[];
     extern uint32_t Image$$VECTOR_RAM$$Base[];
-    extern uint32_t Image$$RW_m_data$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$ZI$$Limit[];
 
 #define __VECTOR_TABLE          Image$$VECTOR_ROM$$Base
 #define __VECTOR_RAM            Image$$VECTOR_RAM$$Base
-#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$VECTOR_RAM$$ZI$$Limit - (uint32_t)Image$$VECTOR_RAM$$Base))
 #elif defined(__ICCARM__)
     extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
     extern uint32_t __VECTOR_TABLE[];
@@ -159,11 +159,11 @@ static void DelayLoop(uint32_t count)
 {
     __ASM volatile("    MOV    X0, %0" : : "r"(count));
     __ASM volatile(
-        "loop:                          \n"
+        "loop%=:                        \n"
         "    SUB    X0, X0, #1          \n"
         "    CMP    X0, #0              \n"
 
-        "    BNE    loop                \n"
+        "    BNE    loop%=              \n"
         :
         :
         : "r0");
@@ -176,7 +176,7 @@ static void DelayLoop(uint32_t count)
 {
     __ASM volatile("    MOV    R0, %0" : : "r"(count));
     __ASM volatile(
-        "loop:                          \n"
+        "loop%=:                        \n"
 #if defined(__GNUC__) && !defined(__ARMCC_VERSION)
         "    SUB    R0, R0, #1          \n"
 #else
@@ -184,7 +184,7 @@ static void DelayLoop(uint32_t count)
 #endif
         "    CMP    R0, #0              \n"
 
-        "    BNE    loop                \n"
+        "    BNE    loop%=              \n"
         :
         :
         : "r0");
@@ -232,13 +232,21 @@ void SDK_DelayAtLeastUs(uint32_t delayTime_us, uint32_t coreClock_Hz)
         {
         }
 #else
+#if defined(__CORTEX_Axx) && ((__CORTEX_Axx == 53) || (__CORTEX_Axx == 55))
+        /*
+         * Cortex-A53/A55 execution throughput:
+         *  - SUB/CMP: 2 instructions per cycle
+         *  - BNE:     1 instruction per cycle
+         * So, each loop takes 2 CPU cycles.
+         */
+        count = count / 2U;
+#elif (__CORTEX_M == 7)
         /* Divide value may be different in various environment to ensure delay is precise.
          * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
          * two instructions in one period, through test here set divide 1.5. Other M cores use
          * divide 4. By the way, divide 1.5 or 4 could let the count lose precision, but it does
          * not matter because other instructions outside while loop is enough to fill the time.
          */
-#if (__CORTEX_M == 7)
         count = count / 3U * 2U;
 #else
         count = count / 4U;

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_common_arm.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_COMMON_ARM_H_
-#define _FSL_COMMON_ARM_H_
+#ifndef FSL_COMMON_ARM_H_
+#define FSL_COMMON_ARM_H_
 
 /*
  * For CMSIS pack RTE.
@@ -28,13 +28,7 @@
  * These macros are used for atomic access, such as read-modify-write
  * to the peripheral registers.
  *
- * - SDK_ATOMIC_LOCAL_ADD
- * - SDK_ATOMIC_LOCAL_SET
- * - SDK_ATOMIC_LOCAL_CLEAR
- * - SDK_ATOMIC_LOCAL_TOGGLE
- * - SDK_ATOMIC_LOCAL_CLEAR_AND_SET
- *
- * Take SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
+ * Take @ref SDK_ATOMIC_LOCAL_CLEAR_AND_SET as an example: the parameter @c addr
  * means the address of the peripheral register or variable you want to modify
  * atomically, the parameter @c clearBits is the bits to clear, the parameter
  * @c setBits it the bits to set.
@@ -59,6 +53,27 @@
  * @{
  */
 
+/*!
+ * @def SDK_ATOMIC_LOCAL_ADD(addr, val)
+ * Add value \a val from the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SUB(addr, val)
+ * Subtract value \a val to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_SET(addr, bits)
+ * Set the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR(addr, bits)
+ * Clear the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)
+ * Toggle the bits specifiled by \a bits to the variable at address \a address.
+ *
+ * @def SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits)
+ * For the variable at address \a address, clear the bits specifiled by \a clearBits
+ * and set the bits specifiled by \a setBits.
+ */
+
 /* clang-format off */
 #if ((defined(__ARM_ARCH_7M__     ) && (__ARM_ARCH_7M__      == 1)) || \
      (defined(__ARM_ARCH_7EM__    ) && (__ARM_ARCH_7EM__     == 1)) || \
@@ -261,7 +276,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) += (val);                    \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_SUB(addr, val)      \
     do                                       \
@@ -270,7 +285,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) -= (val);                    \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_SET(addr, bits)     \
     do                                       \
@@ -279,7 +294,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) |= (bits);                   \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_CLEAR(addr, bits)   \
     do                                       \
@@ -288,7 +303,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) &= ~(bits);                  \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_TOGGLE(addr, bits)  \
     do                                       \
@@ -297,7 +312,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ(); \
         *(addr) ^= (bits);                   \
         EnableGlobalIRQ(s_atomicOldInt);     \
-    } while (0)
+    } while (false)
 
 #define SDK_ATOMIC_LOCAL_CLEAR_AND_SET(addr, clearBits, setBits) \
     do                                                           \
@@ -306,13 +321,13 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
         s_atomicOldInt = DisableGlobalIRQ();                     \
         *(addr)        = (*(addr) & ~(clearBits)) | (setBits);   \
         EnableGlobalIRQ(s_atomicOldInt);                         \
-    } while (0)
+    } while (false)
 
 #endif
-/* @} */
+/*! @} */
 
 /*! @name Timer utilities */
-/* @{ */
+/*! @{ */
 /*! Macro to convert a microsecond period to raw count value */
 #define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
 /*! Macro to convert a raw count value to microsecond */
@@ -322,7 +337,7 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
 #define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)(ms) * (clockFreqInHz) / 1000U)
 /*! Macro to convert a raw count value to millisecond */
 #define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)(count)*1000U / (clockFreqInHz))
-/* @} */
+/*! @} */
 
 /*! @name ISR exit barrier
  * @{
@@ -339,10 +354,10 @@ static inline void _SDK_AtomicLocalClearAndSet4Byte(volatile uint32_t *addr, uin
 #define SDK_ISR_EXIT_BARRIER
 #endif
 
-/* @} */
+/*! @} */
 
 /*! @name Alignment variable definition macros */
-/* @{ */
+/*! @{ */
 #if (defined(__ICCARM__))
 /*
  * Workaround to disable MISRA C message suppress warnings for IAR compiler.
@@ -356,7 +371,7 @@ _Pragma("diag_suppress=Pm120")
 #elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
 /*! Macro to define a variable with alignbytes alignment */
 #define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
-#elif defined(__GNUC__)
+#elif defined(__GNUC__) || defined(DOXYGEN_OUTPUT)
 /*! Macro to define a variable with alignbytes alignment */
 #define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
 #else
@@ -375,15 +390,37 @@ _Pragma("diag_suppress=Pm120")
 /*! Macro to change a value to a given size aligned value */
 #define SDK_SIZEALIGN(var, alignbytes) \
     ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
-/* @} */
+/*! @} */
 
-/*! @name Non-cacheable region definition macros */
-/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
- * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable
- * variables, please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
+/*!
+ * @name Non-cacheable region definition macros
+ *
+ * For initialized non-zero non-cacheable variables, please use "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them. For zero-inited non-cacheable
+ * variables, please use "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them,
  * these zero-inited variables will be initialized to zero in system startup.
+ *
+ * @note For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ *
+ * @{
+ */
+
+/*!
+ * @def AT_NONCACHEABLE_SECTION(var)
+ * Define a variable \a var, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes)
+ * Define a variable \a var, and place it in non-cacheable section, the start address
+ * of the variable is aligned to \a alignbytes.
+ *
+ * @def AT_NONCACHEABLE_SECTION_INIT(var)
+ * Define a variable \a var with initial value, and place it in non-cacheable section.
+ *
+ * @def AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes)
+ * Define a variable \a var with initial value, and place it in non-cacheable section,
+ * the start address of the variable is aligned to \a alignbytes.
  */
-/* @{ */
 
 #if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && \
      defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
@@ -409,7 +446,7 @@ _Pragma("diag_suppress=Pm120")
     __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
 #endif
 
-#elif (defined(__GNUC__))
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
 /* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
  * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
  */
@@ -432,12 +469,24 @@ _Pragma("diag_suppress=Pm120")
 
 #endif
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Time sensitive region
  * @{
  */
+
+/*!
+ * @def AT_QUICKACCESS_SECTION_CODE(func)
+ * Place function in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA(var)
+ * Place data in a section which can be accessed quickly by core.
+ *
+ * @def AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes)
+ * Place data in a section which can be accessed quickly by core, and the variable
+ * address is set to align with \a alignbytes.
+ */
 #if (defined(__ICCARM__))
 #define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
 #define AT_QUICKACCESS_SECTION_DATA(var)  var @"DataQuickAccess"
@@ -448,7 +497,7 @@ _Pragma("diag_suppress=Pm120")
 #define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
 #define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
     __attribute__((section("DataQuickAccess"))) __attribute__((aligned(alignbytes))) var
-#elif (defined(__GNUC__))
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
 #define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
 #define AT_QUICKACCESS_SECTION_DATA(var)  __attribute__((section("DataQuickAccess"))) var
 #define AT_QUICKACCESS_SECTION_DATA_ALIGN(var, alignbytes) \
@@ -456,18 +505,25 @@ _Pragma("diag_suppress=Pm120")
 #else
 #error Toolchain not supported.
 #endif /* defined(__ICCARM__) */
+/*! @} */
 
-/*! @name Ram Function */
+/*!
+ * @name Ram Function
+ * @{
+ *
+ * @def RAMFUNCTION_SECTION_CODE(func)
+ * Place function in ram.
+ */
 #if (defined(__ICCARM__))
 #define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
 #elif (defined(__CC_ARM) || defined(__ARMCC_VERSION))
 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
-#elif (defined(__GNUC__))
+#elif (defined(__GNUC__)) || defined(DOXYGEN_OUTPUT)
 #define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
 #else
 #error Toolchain not supported.
 #endif /* defined(__ICCARM__) */
-/* @} */
+/*! @} */
 
 #if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
         void DefaultISR(void);
@@ -839,4 +895,4 @@ uint32_t MSDK_GetCpuCycleCount(void);
 
 /*! @} */
 
-#endif /* _FSL_COMMON_ARM_H_ */
+#endif /* FSL_COMMON_ARM_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_crc.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_CRC_H_
-#define _FSL_CRC_H_
+#ifndef FSL_CRC_H_
+#define FSL_CRC_H_
 
 #include "fsl_common.h"
 
@@ -21,7 +21,7 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief CRC driver version. Version 2.0.4.
  *
  * Current version: 2.0.4
@@ -30,7 +30,7 @@
  *
  * - Version 2.0.4
  *   - Release peripheral from reset if necessary in init function.
- *
+ * 
  * - Version 2.0.3
  *   - Fix MISRA issues
  *
@@ -41,7 +41,7 @@
  *   - move DATA and DATALL macro definition from header file to source file
  */
 #define FSL_CRC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
-/*@}*/
+/*! @} */
 
 #ifndef CRC_DRIVER_CUSTOM_DEFAULTS
 /*! @brief Default configuration structure filled by CRC_GetDefaultConfig(). Use CRC16-CCIT-FALSE as defeault. */
@@ -178,4 +178,4 @@ uint16_t CRC_Get16bitResult(CRC_Type *base);
  *@}
  */
 
-#endif /* _FSL_CRC_H_ */
+#endif /* FSL_CRC_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_ctimer.c

@@ -575,3 +575,30 @@ void CTIMER4_DriverIRQHandler(void)
     SDK_ISR_EXIT_BARRIER;
 }
 #endif
+
+#if defined(CTIMER5)
+void CTIMER5_DriverIRQHandler(void);
+void CTIMER5_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(5);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CTIMER6)
+void CTIMER6_DriverIRQHandler(void);
+void CTIMER6_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(6);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif
+
+#if defined(CTIMER7)
+void CTIMER7_DriverIRQHandler(void);
+void CTIMER7_DriverIRQHandler(void)
+{
+    CTIMER_GenericIRQHandler(7);
+    SDK_ISR_EXIT_BARRIER;
+}
+#endif

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_ctimer.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_CTIMER_H_
-#define _FSL_CTIMER_H_
+#ifndef FSL_CTIMER_H_
+#define FSL_CTIMER_H_
 
 #include "fsl_common.h"
 
@@ -22,9 +22,9 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 #define FSL_CTIMER_DRIVER_VERSION (MAKE_VERSION(2, 3, 1)) /*!< Version 2.3.1 */
-/*@}*/
+/*! @} */
 
 /*! @brief List of Timer capture channels */
 typedef enum _ctimer_capture_channel
@@ -679,4 +679,4 @@ static inline void CTIMER_SetShadowValue(CTIMER_Type *base, ctimer_match_t match
 
 /*! @}*/
 
-#endif /* _FSL_CTIMER_H_ */
+#endif /* FSL_CTIMER_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_edma.h

@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_EDMA_H_
-#define _FSL_EDMA_H_
+#ifndef FSL_EDMA_H_
+#define FSL_EDMA_H_
 
 #include "fsl_common.h"
 #include "fsl_edma_core.h"
@@ -20,14 +20,18 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief eDMA driver version */
-#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 8, 1)) /*!< Version 2.8.1. */
-/*@}*/
+#define FSL_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 10, 0)) /*!< Version 2.10.0. */
+/*! @} */
+
+/*! @brief eDMA driver name */
+#ifndef FSL_EDMA_DRIVER_EDMA4
+#define FSL_EDMA_DRIVER_EDMA4 (1)
+#endif
 
-/*!@brief Macro used for allocate edma descriptior */
-#define EDMA_ALLOCATE_TCD(name, number) \
-    AT_NONCACHEABLE_SECTION_ALIGN(dma_descriptor_t name[number], EDMA_TCD_ALIGN_SIZE)
+/*!@brief Macro used for allocate edma TCD */
+#define EDMA_ALLOCATE_TCD(name, number) AT_NONCACHEABLE_SECTION_ALIGN(edma_tcd_t name[number], EDMA_TCD_ALIGN_SIZE)
 
 /*! @brief _edma_transfer_status eDMA transfer status */
 enum
@@ -137,13 +141,13 @@ enum
     kEDMA_SourceAddressErrorFlag      = DMA_ERR_SAE_FLAG, /*!< Source address not aligned with source size*/
     kEDMA_ErrorChannelFlag = DMA_ERR_ERRCHAN_FLAG,        /*!< Error channel number of the cancelled channel number */
 #if defined(FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR) && (FSL_FEATURE_EDMA_HAS_PRIORITY_ERROR > 1)
-    kEDMA_ChannelPriorityErrorFlag = DMA_ERR_CPE_FLAG, /*!< Channel priority is not unique. */
+    kEDMA_ChannelPriorityErrorFlag = DMA_ERR_CPE_FLAG,    /*!< Channel priority is not unique. */
 #endif
-    kEDMA_TransferCanceledFlag = DMA_ERR_ECX_FLAG, /*!< Transfer cancelled */
+    kEDMA_TransferCanceledFlag = DMA_ERR_ECX_FLAG,        /*!< Transfer cancelled */
 #if defined(FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT) && (FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT > 1)
-    kEDMA_GroupPriorityErrorFlag = DMA_ERR_GPE_FLAG, /*!< Group priority is not unique. */
+    kEDMA_GroupPriorityErrorFlag = DMA_ERR_GPE_FLAG,      /*!< Group priority is not unique. */
 #endif
-    kEDMA_ValidFlag = (int)DMA_ERR_FLAG, /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
+    kEDMA_ValidFlag = (int)DMA_ERR_FLAG,                  /*!< No error occurred, this bit is 0. Otherwise, it is 1. */
 };
 
 /*! @brief _edma_interrupt_enable eDMA interrupt source */
@@ -242,6 +246,7 @@ typedef enum _edma_channel_access_type
 } edma_channel_access_type_t;
 #endif
 
+/*! @brief eDMA4 channel protection level */
 typedef enum _edma_channel_protection_level
 {
     kEDMA_ChannelProtectionLevelUser       = 0x0U, /*!< user protection level for eDMA transfers. */
@@ -249,6 +254,8 @@ typedef enum _edma_channel_protection_level
 } edma_channel_protection_level_t;
 
 #if !(defined(FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC) && FSL_FEATURE_EDMA_HAS_NO_CH_SBR_SEC)
+
+/*! @brief eDMA4 channel security level */
 typedef enum _edma_channel_security_level
 {
     kEDMA_ChannelSecurityLevelNonSecure = 0x0U, /*!< non secure  level for eDMA transfers. */
@@ -276,7 +283,7 @@ typedef struct _edma_channel_config
 
     uint8_t channelDataSignExtensionBitPosition; /*!< channel data sign extension bit psition configuration */
 
-#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
+#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX)
     int channelRequestSource; /*!< hardware service request source for the channel */
 #endif
 
@@ -339,33 +346,32 @@ typedef struct _edma_transfer_config
     edma_transfer_size_t destTransferSize; /*!< Destination data transfer size. */
     int16_t srcOffset;                     /*!< Sign-extended offset value in byte unit applied to the current source
                                                 address to form the next-state   value as each source read is completed */
-    int16_t destOffset;       /*!< Sign-extended offset value in byte unit applied to the current destination
-                  address to form the next-state value as each destination write is completed. */
-    uint32_t minorLoopBytes;  /*!< bytes in each minor loop or each request
-                               * range: 1 - (2^30 -1) when minor loop mapping is enabled
-                               * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor
-                               * loop offset is enabled
-                               * range: 1 - (2^32 - 1) when minor loop mapping is disabled
-                               */
-    uint32_t majorLoopCounts; /*!< minor loop counts in each major loop, should be 1 at least for each
-                               * transfer range: (0 - (2^15 - 1)) when minor loop channel link is
-                               * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled
-                               * total bytes in a transfer = minorLoopCountsEachMajorLoop *
-                               * bytesEachMinorLoop
-                               */
-
-    uint16_t enabledInterruptMask; /*!< channel interrupt to enable, can be OR'ed value of @ref
-                                         _edma_channel_interrupt_enable */
-
-    edma_modulo_t srcAddrModulo; /*!< source circular data queue range */
-    int32_t srcMajorLoopOffset;  /*!< source major loop offset */
-
-    edma_modulo_t dstAddrModulo; /*!< destination circular data queue range */
-    int32_t dstMajorLoopOffset;  /*!< destination major loop offset */
-
-    bool enableSrcMinorLoopOffset; /*!< enable source minor loop offset */
-    bool enableDstMinorLoopOffset; /*!< enable dest minor loop offset */
-    int32_t minorLoopOffset;       /*!< burst offset, the offset will be applied after minor loop update */
+    int16_t destOffset;              /*!< Sign-extended offset value in byte unit applied to the current destination
+                         address to form the next-state value as each destination write is completed. */
+    uint32_t minorLoopBytes;         /*!< bytes in each minor loop or each request
+                                      * range: 1 - (2^30 -1) when minor loop mapping is enabled
+                                      * range: 1 - (2^10 - 1) when minor loop mapping is enabled and source or dest minor
+                                      * loop offset is enabled
+                                      * range: 1 - (2^32 - 1) when minor loop mapping is disabled
+                                      */
+    uint32_t majorLoopCounts;        /*!< minor loop counts in each major loop, should be 1 at least for each
+                                      * transfer range: (0 - (2^15 - 1)) when minor loop channel link is
+                                      * disabled range: (0 - (2^9 - 1)) when minor loop channel link is enabled
+                                      * total bytes in a transfer = minorLoopCountsEachMajorLoop *
+                                      * bytesEachMinorLoop
+                                      */
+
+    uint16_t enabledInterruptMask;   /*!< channel interrupt to enable, can be OR'ed value of _edma_interrupt_enable */
+
+    edma_modulo_t srcAddrModulo;     /*!< source circular data queue range */
+    int32_t srcMajorLoopOffset;      /*!< source major loop offset */
+
+    edma_modulo_t dstAddrModulo;     /*!< destination circular data queue range */
+    int32_t dstMajorLoopOffset;      /*!< destination major loop offset */
+
+    bool enableSrcMinorLoopOffset;   /*!< enable source minor loop offset */
+    bool enableDstMinorLoopOffset;   /*!< enable dest minor loop offset */
+    int32_t minorLoopOffset;         /*!< burst offset, the offset will be applied after minor loop update */
 
     bool enableChannelMajorLoopLink; /*!< channel link when major loop complete */
     uint32_t majorLoopLinkChannel;   /*!< major loop link channel number */
@@ -373,7 +379,7 @@ typedef struct _edma_transfer_config
     bool enableChannelMinorLoopLink; /*!< channel link when minor loop complete */
     uint32_t minorLoopLinkChannel;   /*!< minor loop link channel number */
 
-    edma_tcd_t *linkTCD; /*!< pointer to the link transfer control descriptor */
+    edma_tcd_t *linkTCD;             /*!< pointer to the link transfer control descriptor */
 } edma_transfer_config_t;
 
 /*! @brief eDMA global configuration structure.*/
@@ -393,11 +399,11 @@ typedef struct _edma_config
     bool enableGlobalChannelLink; /*!< Enable(true) channel linking is available and controlled by each channel's link
                                      settings. */
 
-    bool enableHaltOnError; /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
-                          Subsequently, all service requests are ignored until the HALT bit is cleared.*/
+    bool enableHaltOnError;       /*!< Enable (true) transfer halt on error. Any error causes the HALT bit to set.
+                                Subsequently, all service requests are ignored until the HALT bit is cleared.*/
 
-    bool enableDebugMode; /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of
-                               a new channel. Executing channels are allowed to complete. */
+    bool enableDebugMode;         /*!< Enable(true) eDMA4 debug mode. When in debug mode, the eDMA4 stalls the start of
+                                       a new channel. Executing channels are allowed to complete. */
 
     bool enableRoundRobinArbitration; /*!< Enable(true) channel linking is available and controlled by each channel's
                                      link settings. */
@@ -438,11 +444,11 @@ typedef struct _edma_handle
 #if defined FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG && FSL_FEATURE_EDMA_HAS_CHANNEL_CONFIG
     EDMA_ChannelType *channelBase; /*!< eDMA peripheral channel base address. */
 #endif
-    EDMA_Type *base;       /*!< eDMA peripheral base address*/
-    EDMA_TCDType *tcdBase; /*!< eDMA peripheral tcd base address. */
+    EDMA_Type *base;               /*!< eDMA peripheral base address*/
+    EDMA_TCDType *tcdBase;         /*!< eDMA peripheral tcd base address. */
 
-    edma_tcd_t *tcdPool; /*!< Pointer to memory stored TCDs. */
-    uint32_t channel;    /*!< eDMA channel number. */
+    edma_tcd_t *tcdPool;           /*!< Pointer to memory stored TCDs. */
+    uint32_t channel;              /*!< eDMA channel number. */
 
     volatile int8_t header; /*!< The first TCD index. Should point to the next TCD to be loaded into the eDMA engine. */
     volatile int8_t tail;   /*!< The last TCD index. Should point to the next TCD to be stored into the memory pool. */
@@ -490,7 +496,7 @@ void EDMA_Deinit(EDMA_Type *base);
  * @param channel EDMA channel number.
  * @param tcd Point to TCD structure.
  */
-void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, const edma_tcd_t *tcd);
+void EDMA_InstallTCD(EDMA_Type *base, uint32_t channel, edma_tcd_t *tcd);
 
 /*!
  * @brief Gets the eDMA default configuration structure.
@@ -556,7 +562,7 @@ static inline void EDMA_EnableMinorLoopMapping(EDMA_Type *base, bool enable)
 }
 #endif
 
-/* @} */
+/*! @} */
 /*!
  * @name eDMA Channel Operation
  * @{
@@ -590,8 +596,18 @@ static inline void EDMA_SetChannelMemoryAttribute(EDMA_Type *base,
 
     if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MEMORY_ATTRIBUTEn(base))
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_MATTR =
-            DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute);
+#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX
+        if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(base) == 1U)
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA5_REG.CH_MATTR =
+                DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute);
+        }
+        else
+#endif
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MATTR =
+                DMA_CH_MATTR_WCACHE(writeAttribute) | DMA_CH_MATTR_RCACHE(readAttribute);
+        }
     }
 }
 #endif
@@ -656,14 +672,26 @@ static inline void EDMA_SetChannelAccessType(EDMA_Type *base,
 
     if (0U != (uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_ACCESS_TYPEn(base))
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR =
-            (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) |
-            ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT);
+#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER
+        if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1)
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] =
+                (EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] & (~DMA_CH_SBR_INSTR_MASK)) |
+                ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT);
+        }
+        else
+#endif
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR =
+                (EDMA_CHANNEL_BASE(base, channel)->CH_SBR & (~DMA_CH_SBR_INSTR_MASK)) |
+                ((uint32_t)channelAccessType << DMA_CH_SBR_INSTR_SHIFT);
+        }
     }
 }
 #endif
 
-#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
+#if (defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX) || \
+    (defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX)
 /*!
  * @brief Set channel request source.
  *
@@ -680,7 +708,21 @@ static inline void EDMA_SetChannelMux(EDMA_Type *base, uint32_t channel, int32_t
 
     if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_CHANNEL_MUXn(base) == 1U)
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource);
+        /* Reset channel mux */
+#if defined FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_MP_CHANNEL_MUX
+        if ((uint32_t)FSL_FEATURE_EDMA_INSTANCE_HAS_MP_CHANNEL_MUXn(base) == 1U)
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_MUX[channel] = DMA_CH_MUX_SOURCE(0);
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_MUX[channel] = DMA_CH_MUX_SOURCE(channelRequestSource);
+        }
+        else
+#endif
+        {
+#if defined FSL_FEATURE_EDMA_HAS_CHANNEL_MUX && FSL_FEATURE_EDMA_HAS_CHANNEL_MUX
+            EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MUX = DMA_CH_MUX_SOURCE(0);
+            EDMA_CHANNEL_BASE(base, channel)->CH_REGS.EDMA4_REG.CH_MUX = DMA_CH_MUX_SOURCE(channelRequestSource);
+#endif
+        }
     }
 }
 #endif
@@ -711,13 +753,29 @@ static inline void EDMA_EnableChannelMasterIDReplication(EDMA_Type *base, uint32
 {
     assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base));
 
-    if (enable)
+#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER
+    if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1)
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK;
+        if (enable)
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_EMI_MASK;
+        }
+        else
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_EMI_MASK;
+        }
     }
     else
+#endif
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK;
+        if (enable)
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_EMI_MASK;
+        }
+        else
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_EMI_MASK;
+        }
     }
 }
 
@@ -733,13 +791,29 @@ static inline void EDMA_SetChannelSecurityLevel(EDMA_Type *base, uint32_t channe
 {
     assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base));
 
-    if (level == kEDMA_ChannelSecurityLevelSecure)
+#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER
+    if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1)
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK;
+        if (level == kEDMA_ChannelSecurityLevelSecure)
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_SEC_MASK;
+        }
+        else
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_SEC_MASK;
+        }
     }
     else
+#endif
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK;
+        if (level == kEDMA_ChannelSecurityLevelSecure)
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_SEC_MASK;
+        }
+        else
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_SEC_MASK;
+        }
     }
 }
 #endif
@@ -757,13 +831,29 @@ static inline void EDMA_SetChannelProtectionLevel(EDMA_Type *base,
 {
     assert(channel < (uint32_t)FSL_FEATURE_EDMA_INSTANCE_CHANNELn(base));
 
-    if (level == kEDMA_ChannelProtectionLevelPrivileged)
+#if defined FSL_FEATURE_EDMA_HAS_PROT_REGISTER && FSL_FEATURE_EDMA_HAS_PROT_REGISTER
+    if (FSL_FEATURE_EDMA_INSTANCE_HAS_PROT_REGISTERn(base) == 1)
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK;
+        if (level == kEDMA_ChannelProtectionLevelPrivileged)
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] |= DMA_CH_SBR_PAL_MASK;
+        }
+        else
+        {
+            EDMA_MP_BASE(base)->MP_REGS.EDMA5_REG.CH_PROT[channel] &= ~DMA_CH_SBR_PAL_MASK;
+        }
     }
     else
+#endif
     {
-        EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK;
+        if (level == kEDMA_ChannelProtectionLevelPrivileged)
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR |= DMA_CH_SBR_PAL_MASK;
+        }
+        else
+        {
+            EDMA_CHANNEL_BASE(base, channel)->CH_SBR &= ~DMA_CH_SBR_PAL_MASK;
+        }
     }
 }
 
@@ -927,11 +1017,11 @@ static inline void EDMA_EnableAutoStopRequest(EDMA_Type *base, uint32_t channel,
 
     if (enable)
     {
-        EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_DREQ_MASK;
+        EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_DREQ_MASK;
     }
     else
     {
-        EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_DREQ_MASK;
+        EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_DREQ_MASK;
     }
 }
 
@@ -967,14 +1057,17 @@ void EDMA_DisableChannelInterrupts(EDMA_Type *base, uint32_t channel, uint32_t m
  */
 void EDMA_SetMajorOffsetConfig(EDMA_Type *base, uint32_t channel, int32_t sourceOffset, int32_t destOffset);
 
-/* @} */
+/*! @} */
 /*!
  * @name eDMA TCD Operation
  * @{
  */
 /*!
  * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref
- * edma4_channel_transfer_config_t.
+ * edma_transfer_config_t.
+ *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_ConfigChannelSoftwareTCDExt
  *
  * Application should be careful about the TCD pool buffer storage class,
  * - For the platform has cache, the software TCD should be put in non cache section
@@ -990,6 +1083,9 @@ void EDMA_ConfigChannelSoftwareTCD(edma_tcd_t *tcd, const edma_transfer_config_t
 /*!
  * @brief Sets all fields to default values for the TCD structure.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdResetExt
+ *
  * This function sets all fields for this TCD structure to default value.
  *
  * @param tcd Pointer to the TCD structure.
@@ -1000,6 +1096,9 @@ void EDMA_TcdReset(edma_tcd_t *tcd);
 /*!
  * @brief Configures the eDMA TCD transfer attribute.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdSetTransferConfigExt
+ *
  * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
  * The TCD is used in the scatter-gather mode.
  * This function configures the TCD transfer attribute, including source address, destination address,
@@ -1029,6 +1128,9 @@ void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *co
 /*!
  * @brief Configures the eDMA TCD minor offset feature.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdSetMinorOffsetConfigExt
+ *
  * A minor offset is a signed-extended value added to the source address or a destination
  * address after each minor loop.
  *
@@ -1040,6 +1142,9 @@ void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_confi
 /*!
  * @brief Sets the channel link for the eDMA TCD.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdSetChannelLinkExt
+ *
  * This function configures either a minor link or a major link. The minor link means the channel link is
  * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
  * exhausted.
@@ -1058,6 +1163,9 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
 /*!
  * @brief Sets the bandwidth for the eDMA TCD.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdSetBandWidthExt
+ *
  * Because the eDMA processes the minor loop, it continuously generates read/write sequences
  * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
  * each read/write access to control the bus request bandwidth seen by the crossbar switch.
@@ -1070,15 +1178,18 @@ void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint
 static inline void EDMA_TcdSetBandWidth(edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
-    tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth));
+    EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) =
+        (uint16_t)((EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth));
 }
 #endif
 
 /*!
  * @brief Sets the source modulo and the destination modulo for the eDMA TCD.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdSetModuloExt
+ *
  * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
  * calculation is performed or the original register value. It provides the ability to implement a circular data
  * queue easily.
@@ -1092,6 +1203,9 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d
 /*!
  * @brief Sets the auto stop request for the eDMA TCD.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdEnableAutoStopRequestExt
+ *
  * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
  *
  * @param tcd A pointer to the TCD structure.
@@ -1100,14 +1214,17 @@ void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t d
 static inline void EDMA_TcdEnableAutoStopRequest(edma_tcd_t *tcd, bool enable)
 {
     assert(tcd != NULL);
-    assert(((uint32_t)tcd & 0x1FU) == 0U);
 
-    tcd->CSR = (uint16_t)((tcd->CSR & (~DMA_CSR_DREQ_MASK)) | DMA_CSR_DREQ((true == enable ? 1U : 0U)));
+    EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) = (uint16_t)((EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) & (~DMA_CSR_DREQ_MASK)) |
+                                                    DMA_CSR_DREQ((true == enable ? 1U : 0U)));
 }
 
 /*!
  * @brief Enables the interrupt source for the eDMA TCD.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdEnableInterruptsExt
+ *
  * @param tcd Point to the TCD structure.
  * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
@@ -1117,6 +1234,9 @@ void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask);
 /*!
  * @brief Disables the interrupt source for the eDMA TCD.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdDisableInterruptsExt
+ *
  * @param tcd Point to the TCD structure.
  * @param mask The mask of interrupt source to be set. Users need to use
  *             the defined edma_interrupt_enable_t type.
@@ -1126,6 +1246,9 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
 /*!
  * @brief Configures the eDMA TCD major offset feature.
  *
+ * @Note This API only supports EDMA4 TCD type. It can be used to support all types with extension API @ref
+ * EDMA_TcdSetMajorOffsetConfigExt
+ *
  * Adjustment value added to the source address at the completion of the major iteration count
  *
  * @param tcd A point to the TCD structure.
@@ -1134,6 +1257,184 @@ void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask);
  */
 void EDMA_TcdSetMajorOffsetConfig(edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset);
 
+/*!
+ * @brief Sets TCD fields according to the user's channel transfer configuration structure, @ref
+ * edma_transfer_config_t.
+ *
+ * Application should be careful about the TCD pool buffer storage class,
+ * - For the platform has cache, the software TCD should be put in non cache section
+ * - The TCD pool buffer should have a consistent storage class.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd Pointer to the TCD structure.
+ * @param transfer channel transfer configuration pointer.
+ *
+ * @note This function enables the auto stop request feature.
+ */
+void EDMA_ConfigChannelSoftwareTCDExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_transfer_config_t *transfer);
+
+/*!
+ * @brief Sets all fields to default values for the TCD structure.
+ *
+ * This function sets all fields for this TCD structure to default value.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd Pointer to the TCD structure.
+ * @note This function enables the auto stop request feature.
+ */
+void EDMA_TcdResetExt(EDMA_Type *base, edma_tcd_t *tcd);
+
+/*!
+ * @brief Configures the eDMA TCD transfer attribute.
+ *
+ * The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
+ * The TCD is used in the scatter-gather mode.
+ * This function configures the TCD transfer attribute, including source address, destination address,
+ * transfer size, address offset, and so on. It also configures the scatter gather feature if the
+ * user supplies the next TCD address.
+ * Example:
+ * @code
+ *   edma_transfer_t config = {
+ *   ...
+ *   }
+ *   edma_tcd_t tcd __aligned(32);
+ *   edma_tcd_t nextTcd __aligned(32);
+ *   EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
+ * @endcode
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd Pointer to the TCD structure.
+ * @param config Pointer to eDMA transfer configuration structure.
+ * @param nextTcd Pointer to the next TCD structure. It can be NULL if users
+ *                do not want to enable scatter/gather feature.
+ * @note TCD address should be 32 bytes aligned or it causes an eDMA error.
+ * @note If the nextTcd is not NULL, the scatter gather feature is enabled
+ *       and DREQ bit is cleared in the previous transfer configuration, which
+ *       is set in the EDMA_TcdReset.
+ */
+void EDMA_TcdSetTransferConfigExt(EDMA_Type *base,
+                                  edma_tcd_t *tcd,
+                                  const edma_transfer_config_t *config,
+                                  edma_tcd_t *nextTcd);
+
+/*!
+ * @brief Configures the eDMA TCD minor offset feature.
+ *
+ * A minor offset is a signed-extended value added to the source address or a destination
+ * address after each minor loop.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd A point to the TCD structure.
+ * @param config A pointer to the minor offset configuration structure.
+ */
+void EDMA_TcdSetMinorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, const edma_minor_offset_config_t *config);
+
+/*!
+ * @brief Sets the channel link for the eDMA TCD.
+ *
+ * This function configures either a minor link or a major link. The minor link means the channel link is
+ * triggered every time CITER decreases by 1. The major link means that the channel link  is triggered when the CITER is
+ * exhausted.
+ *
+ * @note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
+ * @param base eDMA peripheral base address.
+ * @param tcd Point to the TCD structure.
+ * @param type Channel link type, it can be one of:
+ *   @arg kEDMA_LinkNone
+ *   @arg kEDMA_MinorLink
+ *   @arg kEDMA_MajorLink
+ * @param linkedChannel The linked channel number.
+ */
+void EDMA_TcdSetChannelLinkExt(EDMA_Type *base, edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel);
+
+#if defined FSL_FEATURE_EDMA_HAS_BANDWIDTH && FSL_FEATURE_EDMA_HAS_BANDWIDTH
+/*!
+ * @brief Sets the bandwidth for the eDMA TCD.
+ *
+ * Because the eDMA processes the minor loop, it continuously generates read/write sequences
+ * until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
+ * each read/write access to control the bus request bandwidth seen by the crossbar switch.
+ * @param base eDMA peripheral base address.
+ * @param tcd A pointer to the TCD structure.
+ * @param bandWidth A bandwidth setting, which can be one of the following:
+ *     @arg kEDMABandwidthStallNone
+ *     @arg kEDMABandwidthStall4Cycle
+ *     @arg kEDMABandwidthStall8Cycle
+ */
+static inline void EDMA_TcdSetBandWidthExt(EDMA_Type *base, edma_tcd_t *tcd, edma_bandwidth_t bandWidth)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
+
+    EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) =
+        (uint16_t)((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth));
+}
+#endif
+
+/*!
+ * @brief Sets the source modulo and the destination modulo for the eDMA TCD.
+ *
+ * This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
+ * calculation is performed or the original register value. It provides the ability to implement a circular data
+ * queue easily.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd A pointer to the TCD structure.
+ * @param srcModulo A source modulo value.
+ * @param destModulo A destination modulo value.
+ */
+void EDMA_TcdSetModuloExt(EDMA_Type *base, edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo);
+
+/*!
+ * @brief Sets the auto stop request for the eDMA TCD.
+ *
+ * If enabling the auto stop request, the eDMA hardware automatically disables the hardware channel request.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd A pointer to the TCD structure.
+ * @param enable The command to enable (true) or disable (false).
+ */
+static inline void EDMA_TcdEnableAutoStopRequestExt(EDMA_Type *base, edma_tcd_t *tcd, bool enable)
+{
+    assert(tcd != NULL);
+    assert(((uint32_t)tcd & 0x1FU) == 0U);
+
+    EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) = (uint16_t)((EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) & (~DMA_CSR_DREQ_MASK)) |
+                                                       DMA_CSR_DREQ((true == enable ? 1U : 0U)));
+}
+
+/*!
+ * @brief Enables the interrupt source for the eDMA TCD.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd Point to the TCD structure.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdEnableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask);
+
+/*!
+ * @brief Disables the interrupt source for the eDMA TCD.
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd Point to the TCD structure.
+ * @param mask The mask of interrupt source to be set. Users need to use
+ *             the defined edma_interrupt_enable_t type.
+ */
+void EDMA_TcdDisableInterruptsExt(EDMA_Type *base, edma_tcd_t *tcd, uint32_t mask);
+
+/*!
+ * @brief Configures the eDMA TCD major offset feature.
+ *
+ * Adjustment value added to the source address at the completion of the major iteration count
+ *
+ * @param base eDMA peripheral base address.
+ * @param tcd A point to the TCD structure.
+ * @param sourceOffset source address offset wiil be applied to source address after major loop done.
+ * @param destOffset destination address offset will be applied to source address after major loop done.
+ */
+void EDMA_TcdSetMajorOffsetConfigExt(EDMA_Type *base, edma_tcd_t *tcd, int32_t sourceOffset, int32_t destOffset);
+
 /*! @} */
 /*!
  * @name eDMA Channel Transfer Operation
@@ -1193,7 +1494,7 @@ static inline void EDMA_TriggerChannelStart(EDMA_Type *base, uint32_t channel)
 #if defined FSL_EDMA_SOC_IP_EDMA && FSL_EDMA_SOC_IP_EDMA
     EDMA_BASE(base)->SSRT = DMA_SSRT_SSRT(channel);
 #else
-    EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_START_MASK;
+    EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_START_MASK;
 #endif
 }
 
@@ -1323,6 +1624,8 @@ void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userD
  * @note The data address and the data width must be consistent. For example, if the SRC
  *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
  *       source address error (SAE).
+ *       User can check if 128 bytes support is available for specific instance by
+ *       FSL_FEATURE_EDMA_INSTANCE_SUPPORT_128_BYTES_TRANSFERn.
  */
 void EDMA_PrepareTransferConfig(edma_transfer_config_t *config,
                                 void *srcAddr,
@@ -1363,10 +1666,10 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
 /*!
  * @brief Prepares the eDMA transfer content descriptor.
  *
- * @This function prepares the transfer content descriptor structure according to the user input.
+ * This function prepares the transfer content descriptor structure according to the user input.
  *
  * @param handle eDMA handle pointer.
- * @param config The user configuration structure of type edma_transfer_t.
+ * @param tcd Pointer to eDMA transfer content descriptor structure.
  * @param srcAddr eDMA transfer source address.
  * @param srcWidth eDMA transfer source address width(bytes).
  * @param srcOffset source address offset.
@@ -1376,7 +1679,6 @@ void EDMA_PrepareTransfer(edma_transfer_config_t *config,
  * @param bytesEachRequest eDMA transfer bytes per channel request.
  * @param transferBytes eDMA transfer bytes to be transferred.
  * @param nextTcd eDMA transfer linked TCD address.
- * @param type eDMA transfer type.
  *
  * @note The data address and the data width must be consistent. For example, if the SRC
  *       is 4 bytes, the source address must be 4 bytes aligned, or it results in
@@ -1447,7 +1749,7 @@ void EDMA_PrepareTransferTCD(edma_handle_t *handle,
  * @retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
  * @retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
  */
-status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, const edma_tcd_t *tcd);
+status_t EDMA_SubmitTransferTCD(edma_handle_t *handle, edma_tcd_t *tcd);
 
 /*!
  * @brief Submits the eDMA transfer request.
@@ -1487,8 +1789,8 @@ status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t
  * itself.
  *
  * @retval #kStatus_Success It means submit transfer request succeed
- * @retval #kStatus_EDMA_ChannelBusy channel is in busy status
- * @retval #kStatus_EDMA_ChannelQueueFull It means TCD pool is not len enough for the ring transfer request
+ * @retval #kStatus_EDMA_Busy channel is in busy status
+ * @retval #kStatus_InvalidArgument Invalid Argument
  */
 status_t EDMA_SubmitLoopTransfer(edma_handle_t *handle, edma_transfer_config_t *transfer, uint32_t transferLoopCount);
 
@@ -1547,7 +1849,7 @@ static inline uint32_t EDMA_GetUnusedTCDNumber(edma_handle_t *handle)
  */
 static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)
 {
-    return (uint32_t)(handle->tcdBase->DLAST_SGA);
+    return (uint32_t)(EDMA_TCD_DLAST_SGA(handle->tcdBase, EDMA_TCD_TYPE(handle->base)));
 }
 
 /*!
@@ -1580,12 +1882,12 @@ static inline uint32_t EDMA_GetNextTCDAddress(edma_handle_t *handle)
  */
 void EDMA_HandleIRQ(edma_handle_t *handle);
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
 #endif /* __cplusplus */
 
-/* @} */
+/*! @} */
 
-#endif /*_FSL_EDMA_H_*/
+#endif /*FSL_EDMA_H_*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_edma_core.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_EDMA_CORE_H_
-#define _FSL_EDMA_CORE_H_
+#ifndef FSL_EDMA_CORE_H_
+#define FSL_EDMA_CORE_H_
 
 #include "fsl_edma_soc.h"
 
@@ -17,147 +17,53 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#if defined(FSL_EDMA_SOC_IP_DMA3) && defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA3 && FSL_EDMA_SOC_IP_DMA4
-#define DMA_CSR_INTMAJOR_MASK          DMA_TCD_CSR_INTMAJOR_MASK
-#define DMA_CSR_INTHALF_MASK           DMA_TCD_CSR_INTHALF_MASK
-#define DMA_CSR_DREQ_MASK              DMA_TCD_CSR_DREQ_MASK
-#define DMA_CSR_ESG_MASK               DMA_TCD_CSR_ESG_MASK
-#define DMA_CSR_BWC_MASK               DMA_TCD_CSR_BWC_MASK
-#define DMA_CSR_BWC(x)                 DMA_TCD_CSR_BWC(x)
-#define DMA_CSR_START_MASK             DMA_TCD_CSR_START_MASK
-#define DMA_CITER_ELINKNO_CITER_MASK   DMA_TCD_CITER_ELINKNO_CITER_MASK
-#define DMA_BITER_ELINKNO_BITER_MASK   DMA_TCD_BITER_ELINKNO_BITER_MASK
-#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA_TCD_CITER_ELINKNO_CITER_SHIFT
-#define DMA_CITER_ELINKYES_CITER_MASK  DMA_TCD_CITER_ELINKYES_CITER_MASK
-#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
-#define DMA_ATTR_SMOD_MASK             DMA_TCD_ATTR_SMOD_MASK
-#define DMA_ATTR_DMOD_MASK             DMA_TCD_ATTR_DMOD_MASK
-#define DMA_CITER_ELINKNO_ELINK_MASK   DMA_TCD_CITER_ELINKNO_ELINK_MASK
-#define DMA_CSR_MAJORELINK_MASK        DMA_TCD_CSR_MAJORELINK_MASK
-#define DMA_BITER_ELINKYES_ELINK_MASK  DMA_TCD_BITER_ELINKYES_ELINK_MASK
-#define DMA_CITER_ELINKYES_ELINK_MASK  DMA_TCD_CITER_ELINKYES_ELINK_MASK
-#define DMA_CSR_MAJORLINKCH_MASK       DMA_TCD_CSR_MAJORLINKCH_MASK
-#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
-#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
-#define DMA_NBYTES_MLOFFNO_NBYTES_MASK DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK
-#define DMA_ATTR_DMOD(x)               DMA_TCD_ATTR_DMOD(x)
-#define DMA_ATTR_SMOD(X)               DMA_TCD_ATTR_SMOD(X)
-#define DMA_BITER_ELINKYES_LINKCH(x)   DMA_TCD_BITER_ELINKYES_LINKCH(x)
-#define DMA_CITER_ELINKYES_LINKCH(x)   DMA_TCD_CITER_ELINKYES_LINKCH(x)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
-#define DMA_ATTR_DSIZE(x)              DMA_TCD_ATTR_DSIZE(x)
-#define DMA_ATTR_SSIZE(x)              DMA_TCD_ATTR_SSIZE(x)
-#define DMA_CSR_DREQ(x)                DMA_TCD_CSR_DREQ(x)
-#define DMA_CSR_MAJORLINKCH(x)         DMA_TCD_CSR_MAJORLINKCH(x)
-#define DMA_CH_MATTR_WCACHE(x)         DMA4_CH_MATTR_WCACHE(x)
-#define DMA_CH_MATTR_RCACHE(x)         DMA4_CH_MATTR_RCACHE(x)
-#define DMA_CH_CSR_SIGNEXT_MASK        DMA4_CH_CSR_SIGNEXT_MASK
-#define DMA_CH_CSR_SIGNEXT_SHIFT       DMA4_CH_CSR_SIGNEXT_SHIFT
-#define DMA_CH_CSR_SWAP_MASK           DMA4_CH_CSR_SWAP_MASK
-#define DMA_CH_CSR_SWAP_SHIFT          DMA4_CH_CSR_SWAP_SHIFT
-#define DMA_CH_SBR_INSTR_MASK          DMA4_CH_SBR_INSTR_MASK
-#define DMA_CH_SBR_INSTR_SHIFT         DMA4_CH_SBR_INSTR_SHIFT
-#define DMA_CH_MUX_SOURCE(x)           DMA4_CH_MUX_SRC(x)
-#elif defined(FSL_EDMA_SOC_IP_DMA3) && FSL_EDMA_SOC_IP_DMA3 && \
-    (!defined(FSL_EDMA_SOC_IP_DMA4) || (defined(FSL_EDMA_SOC_IP_DMA4) && !FSL_EDMA_SOC_IP_DMA4))
-#define DMA_CSR_INTMAJOR_MASK          DMA_TCD_CSR_INTMAJOR_MASK
-#define DMA_CSR_INTHALF_MASK           DMA_TCD_CSR_INTHALF_MASK
-#define DMA_CSR_DREQ_MASK              DMA_TCD_CSR_DREQ_MASK
-#define DMA_CSR_ESG_MASK               DMA_TCD_CSR_ESG_MASK
-#define DMA_CSR_BWC_MASK               DMA_TCD_CSR_BWC_MASK
-#define DMA_CSR_BWC(x)                 DMA_TCD_CSR_BWC(x)
-#define DMA_CSR_START_MASK             DMA_TCD_CSR_START_MASK
-#define DMA_CITER_ELINKNO_CITER_MASK   DMA_TCD_CITER_ELINKNO_CITER_MASK
-#define DMA_BITER_ELINKNO_BITER_MASK   DMA_TCD_BITER_ELINKNO_BITER_MASK
-#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA_TCD_CITER_ELINKNO_CITER_SHIFT
-#define DMA_CITER_ELINKYES_CITER_MASK  DMA_TCD_CITER_ELINKYES_CITER_MASK
-#define DMA_CITER_ELINKYES_CITER_SHIFT DMA_TCD_CITER_ELINKYES_CITER_SHIFT
-#define DMA_ATTR_SMOD_MASK             DMA_TCD_ATTR_SMOD_MASK
-#define DMA_ATTR_DMOD_MASK             DMA_TCD_ATTR_DMOD_MASK
-#define DMA_CITER_ELINKNO_ELINK_MASK   DMA_TCD_CITER_ELINKNO_ELINK_MASK
-#define DMA_CSR_MAJORELINK_MASK        DMA_TCD_CSR_MAJORELINK_MASK
-#define DMA_BITER_ELINKYES_ELINK_MASK  DMA_TCD_BITER_ELINKYES_ELINK_MASK
-#define DMA_CITER_ELINKYES_ELINK_MASK  DMA_TCD_CITER_ELINKYES_ELINK_MASK
-#define DMA_CSR_MAJORLINKCH_MASK       DMA_TCD_CSR_MAJORLINKCH_MASK
-#define DMA_BITER_ELINKYES_LINKCH_MASK DMA_TCD_BITER_ELINKYES_LINKCH_MASK
-#define DMA_CITER_ELINKYES_LINKCH_MASK DMA_TCD_CITER_ELINKYES_LINKCH_MASK
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK
-#define DMA_ATTR_DMOD(x)               DMA_TCD_ATTR_DMOD(x)
-#define DMA_ATTR_SMOD(X)               DMA_TCD_ATTR_SMOD(X)
-#define DMA_BITER_ELINKYES_LINKCH(x)   DMA_TCD_BITER_ELINKYES_LINKCH(x)
-#define DMA_CITER_ELINKYES_LINKCH(x)   DMA_TCD_CITER_ELINKYES_LINKCH(x)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA_TCD_NBYTES_MLOFFYES_MLOFF(x)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_DMLOE(x)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA_TCD_NBYTES_MLOFFYES_SMLOE(x)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA_TCD_NBYTES_MLOFFNO_NBYTES(x)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA_TCD_NBYTES_MLOFFYES_NBYTES(x)
-#define DMA_ATTR_DSIZE(x)              DMA_TCD_ATTR_DSIZE(x)
-#define DMA_ATTR_SSIZE(x)              DMA_TCD_ATTR_SSIZE(x)
-#define DMA_CSR_DREQ(x)                DMA_TCD_CSR_DREQ(x)
-#define DMA_CSR_MAJORLINKCH(x)         DMA_TCD_CSR_MAJORLINKCH(x)
-#define DMA_CH_MUX_SOURCE(x)           DMA_CH_MUX_SRC(x)
-#elif defined(FSL_EDMA_SOC_IP_DMA4) && FSL_EDMA_SOC_IP_DMA4 && \
-    (!defined(FSL_EDMA_SOC_IP_DMA3) || (defined(FSL_EDMA_SOC_IP_DMA3) && !FSL_EDMA_SOC_IP_DMA3))
-#define DMA_CSR_INTMAJOR_MASK          DMA4_CSR_INTMAJOR_MASK
-#define DMA_CSR_INTHALF_MASK           DMA4_CSR_INTHALF_MASK
-#define DMA_CSR_DREQ_MASK              DMA4_CSR_DREQ_MASK
-#define DMA_CSR_ESG_MASK               DMA4_CSR_ESG_MASK
-#define DMA_CSR_BWC_MASK               DMA4_CSR_BWC_MASK
-#define DMA_CSR_BWC(x)                 DMA4_CSR_BWC(x)
-#define DMA_CSR_START_MASK             DMA4_CSR_START_MASK
-#define DMA_CITER_ELINKNO_CITER_MASK   DMA4_CITER_ELINKNO_CITER_MASK
-#define DMA_BITER_ELINKNO_BITER_MASK   DMA4_BITER_ELINKNO_BITER_MASK
-#define DMA_CITER_ELINKNO_CITER_SHIFT  DMA4_CITER_ELINKNO_CITER_SHIFT
-#define DMA_CITER_ELINKYES_CITER_MASK  DMA4_CITER_ELINKYES_CITER_MASK
-#define DMA_CITER_ELINKYES_CITER_SHIFT DMA4_CITER_ELINKYES_CITER_SHIFT
-#define DMA_ATTR_SMOD_MASK             DMA4_ATTR_SMOD_MASK
-#define DMA_ATTR_DMOD_MASK             DMA4_ATTR_DMOD_MASK
-#define DMA_CITER_ELINKNO_ELINK_MASK   DMA4_CITER_ELINKNO_ELINK_MASK
-#define DMA_CSR_MAJORELINK_MASK        DMA4_CSR_MAJORELINK_MASK
-#define DMA_BITER_ELINKYES_ELINK_MASK  DMA4_BITER_ELINKYES_ELINK_MASK
-#define DMA_CITER_ELINKYES_ELINK_MASK  DMA4_CITER_ELINKYES_ELINK_MASK
-#define DMA_CSR_MAJORLINKCH_MASK       DMA4_CSR_MAJORLINKCH_MASK
-#define DMA_BITER_ELINKYES_LINKCH_MASK DMA4_BITER_ELINKYES_LINKCH_MASK
-#define DMA_CITER_ELINKYES_LINKCH_MASK DMA4_CITER_ELINKYES_LINKCH_MASK
-#define DMA_NBYTES_MLOFFYES_MLOFF_MASK DMA4_NBYTES_MLOFFYES_MLOFF_MASK
-#define DMA_NBYTES_MLOFFYES_DMLOE_MASK DMA4_NBYTES_MLOFFYES_DMLOE_MASK
-#define DMA_NBYTES_MLOFFYES_SMLOE_MASK DMA4_NBYTES_MLOFFYES_SMLOE_MASK
-#define DMA_ATTR_DMOD(x)               DMA4_ATTR_DMOD(x)
-#define DMA_ATTR_SMOD(X)               DMA4_ATTR_SMOD(X)
-#define DMA_BITER_ELINKYES_LINKCH(x)   DMA4_BITER_ELINKYES_LINKCH(x)
-#define DMA_CITER_ELINKYES_LINKCH(x)   DMA4_CITER_ELINKYES_LINKCH(x)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)   DMA4_NBYTES_MLOFFYES_MLOFF(x)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)   DMA4_NBYTES_MLOFFYES_DMLOE(x)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)   DMA4_NBYTES_MLOFFYES_SMLOE(x)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)   DMA4_NBYTES_MLOFFNO_NBYTES(x)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)  DMA4_NBYTES_MLOFFYES_NBYTES(x)
-#define DMA_ATTR_DSIZE(x)              DMA4_ATTR_DSIZE(x)
-#define DMA_ATTR_SSIZE(x)              DMA4_ATTR_SSIZE(x)
-#define DMA_CSR_DREQ(x)                DMA4_CSR_DREQ(x)
-#define DMA_CSR_MAJORLINKCH(x)         DMA4_CSR_MAJORLINKCH(x)
-#define DMA_CH_MATTR_WCACHE(x)         DMA4_CH_MATTR_WCACHE(x)
-#define DMA_CH_MATTR_RCACHE(x)         DMA4_CH_MATTR_RCACHE(x)
-#define DMA_CH_CSR_SIGNEXT_MASK        DMA4_CH_CSR_SIGNEXT_MASK
-#define DMA_CH_CSR_SIGNEXT_SHIFT       DMA4_CH_CSR_SIGNEXT_SHIFT
-#define DMA_CH_CSR_SWAP_MASK           DMA4_CH_CSR_SWAP_MASK
-#define DMA_CH_CSR_SWAP_SHIFT          DMA4_CH_CSR_SWAP_SHIFT
-#define DMA_CH_SBR_INSTR_MASK          DMA4_CH_SBR_INSTR_MASK
-#define DMA_CH_SBR_INSTR_SHIFT         DMA4_CH_SBR_INSTR_SHIFT
-#define DMA_CH_MUX_SOURCE(x)           DMA4_CH_MUX_SRC(x)
-#define DMA_CH_CSR_DONE_MASK           DMA4_CH_CSR_DONE_MASK
-#define DMA_CH_CSR_ERQ_MASK            DMA4_CH_CSR_ERQ_MASK
-#elif defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
-/*! intentional empty */
-#endif
+#define DMA_CSR_INTMAJOR_MASK          (0x2U)
+#define DMA_CSR_INTHALF_MASK           (0x4U)
+#define DMA_CSR_DREQ_MASK              (0x8U)
+#define DMA_CSR_ESG_MASK               (0x10U)
+#define DMA_CSR_BWC_MASK               (0xC000U)
+#define DMA_CSR_BWC(x)                 (((uint16_t)(((uint16_t)(x)) << (14U))) & (0xC000U))
+#define DMA_CSR_START_MASK             (0x1U)
+#define DMA_CITER_ELINKNO_CITER_MASK   (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_MASK   (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT  (0U)
+#define DMA_CITER_ELINKYES_CITER_MASK  (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
+#define DMA_ATTR_SMOD_MASK             (0xF800U)
+#define DMA_ATTR_DMOD_MASK             (0xF8U)
+#define DMA_CITER_ELINKNO_ELINK_MASK   (0x8000U)
+#define DMA_CSR_MAJORELINK_MASK        (0x20U)
+#define DMA_BITER_ELINKYES_ELINK_MASK  (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_MASK  (0x8000U)
+#define DMA_CSR_MAJORLINKCH_MASK       (0x1F00U)
+#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
+#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
+#define DMA_ATTR_DMOD(x)               (((uint16_t)(((uint16_t)(x)) << (3U))) & (0xF8U))
+#define DMA_ATTR_SMOD(x)               (((uint16_t)(((uint16_t)(x)) << (11U))) & (0xF800U))
+#define DMA_BITER_ELINKYES_LINKCH(x)   (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U))
+#define DMA_CITER_ELINKYES_LINKCH(x)   (((uint16_t)(((uint16_t)(x)) << (9U))) & (0x3E00U))
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)   (((uint32_t)(((uint32_t)(x)) << (10U))) & (0x3FFFFC00U))
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)   (((uint32_t)(((uint32_t)(x)) << (30U))) & (0x40000000U))
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)   (((uint32_t)(((uint32_t)(x)) << (31U))) & (0x80000000U))
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)   (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFFFFFFU))
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)  (((uint32_t)(((uint32_t)(x)) << (0U))) & (0x3FFU))
+#define DMA_ATTR_DSIZE(x)              (((uint16_t)(((uint16_t)(x)) << (0U))) & (0x7U))
+#define DMA_ATTR_SSIZE(x)              (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x700U))
+#define DMA_CSR_DREQ(x)                (((uint16_t)(((uint16_t)(x)) << (3U))) & (0x8U))
+#define DMA_CSR_MAJORLINKCH(x)         (((uint16_t)(((uint16_t)(x)) << (8U))) & (0x1F00U))
+#define DMA_CH_MATTR_WCACHE(x)         (((uint16_t)(((uint16_t)(x)) << (4U))) & (0xF0U))
+#define DMA_CH_MATTR_RCACHE(x)         (((uint16_t)(((uint16_t)(x)) << (0U))) & (0xFU))
+#define DMA_CH_CSR_SIGNEXT_MASK        (0x3F0000U)
+#define DMA_CH_CSR_SIGNEXT_SHIFT       (16U)
+#define DMA_CH_CSR_SWAP_MASK           (0xF000U)
+#define DMA_CH_CSR_SWAP_SHIFT          (12U)
+#define DMA_CH_SBR_INSTR_MASK          (0x2000U)
+#define DMA_CH_SBR_INSTR_SHIFT         (13U)
+#define DMA_CH_MUX_SOURCE(x)           (((uint32_t)(((uint32_t)(x)) << (0U))) & (0xFFU))
 
 /*! @brief DMA error flag */
 #if defined(FSL_EDMA_SOC_IP_EDMA) && FSL_EDMA_SOC_IP_EDMA
@@ -222,10 +128,14 @@
 #endif /*FSL_EDMA_SOC_IP_EDMA*/
 
 /*! @brief enable/dsiable MAJOR/HALF INT*/
-#define DMA_ENABLE_MAJOR_INT(base, channel)  (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTMAJOR_MASK)
-#define DMA_ENABLE_HALF_INT(base, channel)   (EDMA_TCD_BASE(base, channel)->CSR |= DMA_CSR_INTHALF_MASK)
-#define DMA_DISABLE_MAJOR_INT(base, channel) (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK)
-#define DMA_DISABLE_HALF_INT(base, channel)  (EDMA_TCD_BASE(base, channel)->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
+#define DMA_ENABLE_MAJOR_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTMAJOR_MASK)
+#define DMA_ENABLE_HALF_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK)
+#define DMA_DISABLE_MAJOR_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTMAJOR_MASK)
+#define DMA_DISABLE_HALF_INT(base, channel) \
+    (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
 
 /*!@brief EDMA tcd align size */
 #define EDMA_TCD_ALIGN_SIZE (32U)
@@ -235,22 +145,81 @@ typedef struct _edma_core_mp
 {
     __IO uint32_t MP_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
     __IO uint32_t MP_ES;  /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
+    union
+    {
+        struct
+        {
+            __IO uint32_t MP_INT_LOW;   /**< Channel Control and Status, array offset: 0x10008, array step: 0x10000 */
+            __I uint32_t MP_INT_HIGH;   /**< Channel Control and Status, array offset: 0x1000C, array step: 0x10000 */
+            __I uint32_t MP_HRS_LOW;    /**< Channel Control and Status, array offset: 0x10010, array step: 0x10000 */
+            __I uint32_t MP_HRS_HIGH;   /**< Channel Control and Status, array offset: 0x10014, array step: 0x10000 */
+            uint8_t RESERVED_0[8];
+            __IO uint32_t MP_STOPCH;    /**< Channel Control and Status, array offset: 0x10020, array step: 0x10000 */
+            uint8_t RESERVED_1[12];
+            __I uint32_t MP_SSR_LOW;    /**< Channel Control and Status, array offset: 0x10030, array step: 0x10000 */
+            __I uint32_t MP_SSR_HIGH;   /**< Channel Control and Status, array offset: 0x10034, array step: 0x10000 */
+            uint8_t RESERVED_2[200];
+            __IO uint32_t CH_GRPRI[64]; /**< Channel Control and Status, array offset: 0x10100, array step: 0x10000 */
+            __IO uint32_t CH_MUX[64];   /**< Channel Control and Status, array offset: 0x10200, array step: 0x10000 */
+            uint8_t RESERVED_3[256];
+            __IO uint32_t CH_PROT[64];  /**< Channel Control and Status, array offset: 0x10400, array step: 0x10000 */
+        } EDMA5_REG;
+    } MP_REGS;
 } edma_core_mp_t;
 
 /*!@brief edma core channel struture definition */
 typedef struct _edma_core_channel
 {
-    __IO uint32_t CH_CSR;   /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
-    __IO uint32_t CH_ES;    /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
-    __IO uint32_t CH_INT;   /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
-    __IO uint32_t CH_SBR;   /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
-    __IO uint32_t CH_PRI;   /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
-    __IO uint32_t CH_MUX;   /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
-    __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+    __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x10000, array step: 0x10000 */
+    __IO uint32_t CH_ES;  /**< Channel Error Status, array offset: 0x10004, array step: 0x10000 */
+    __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x10008, array step: 0x10000 */
+    __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0x1000C, array step: 0x10000 */
+    __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10010, array step: 0x10000 */
+    union
+    {
+        struct
+        {
+            __IO uint8_t RESERVED_1[4];
+            __IO uint32_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+        } EDMA5_REG;
+        struct
+        {
+            __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
+            __IO uint16_t CH_MATTR; /**< Memory Attributes Register, array offset: 0x10018, array step: 0x8000 */
+        } EDMA4_REG;
+    } CH_REGS;
 } edma_core_channel_t;
 
-/*!@brief edma core TCD struture definition */
-typedef struct _edma_core_tcd
+/*! @brief eDMA tcd flag type */
+typedef enum _edma_tcd_type
+{
+    kEDMA_EDMA4Flag = 0x0U, /*!< Data access for eDMA4 transfers. */
+    kEDMA_EDMA5Flag = 0x1U, /*!< Instruction access for eDMA4 transfers. */
+} edma_tcd_type_t;
+
+/*!@brief edma5 core TCD struture definition */
+typedef struct _edma5_core_tcd
+{
+    __IO uint32_t SADDR;          /*!< SADDR register, used to save source address */
+    __IO uint32_t SADDR_HIGH;     /*!< SADDR HIGH register, used to save source address */
+    __IO uint16_t SOFF;           /*!< SOFF register, save offset bytes every transfer */
+    __IO uint16_t ATTR;           /*!< ATTR register, source/destination transfer size and modulo */
+    __IO uint32_t NBYTES;         /*!< Nbytes register, minor loop length in bytes */
+    __IO uint32_t SLAST;          /*!< SLAST register */
+    __IO uint32_t SLAST_SDA_HIGH; /*!< SLAST SDA HIGH register */
+    __IO uint32_t DADDR;          /*!< DADDR register, used for destination address */
+    __IO uint32_t DADDR_HIGH;     /*!< DADDR HIGH register, used for destination address */
+    __IO uint32_t DLAST_SGA;      /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
+    __IO uint32_t DLAST_SGA_HIGH; /*!< DLASTSGA HIGH register, next tcd address used in scatter-gather mode */
+    __IO uint16_t DOFF;           /*!< DOFF register, used for destination offset */
+    __IO uint16_t CITER;          /*!< CITER register, current minor loop numbers, for unfinished minor loop.*/
+    __IO uint16_t CSR;            /*!< CSR register, for TCD control status */
+    __IO uint16_t BITER;          /*!< BITER register, begin minor loop count. */
+    uint8_t RESERVED[16];         /*!< Aligned 64 bytes */
+} edma5_core_tcd_t;
+
+/*!@brief edma4 core TCD struture definition */
+typedef struct _edma4_core_tcd
 {
     __IO uint32_t SADDR;     /*!< SADDR register, used to save source address */
     __IO uint16_t SOFF;      /*!< SOFF register, save offset bytes every transfer */
@@ -263,6 +232,18 @@ typedef struct _edma_core_tcd
     __IO uint32_t DLAST_SGA; /*!< DLASTSGA register, next tcd address used in scatter-gather mode */
     __IO uint16_t CSR;       /*!< CSR register, for TCD control status */
     __IO uint16_t BITER;     /*!< BITER register, begin minor loop count. */
+} edma4_core_tcd_t;
+
+/*!@brief edma core TCD struture definition */
+typedef struct _edma_core_tcd
+{
+    union
+    {
+        edma4_core_tcd_t edma4_tcd;
+#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5
+        edma5_core_tcd_t edma5_tcd;
+#endif /* FSL_EDMA_SOC_IP_DMA5 */
+    } TCD_REGS;
 } edma_core_tcd_t;
 
 /*!@brief EDMA typedef */
@@ -280,6 +261,83 @@ typedef void EDMA_Type;
                          (channel)*EDMA_CHANNEL_ARRAY_STEP(base) + 0x20U))
 #define EDMA_MP_BASE(base) ((edma_core_mp_t *)((uint32_t)(uint32_t *)(base)))
 
+/*!@brief EDMA TCD type macro */
+#if defined FSL_FEATURE_EDMA_TCD_TYPEn
+#define EDMA_TCD_TYPE(x) FSL_FEATURE_EDMA_TCD_TYPEn(x)
+#else
+#define EDMA_TCD_TYPE(x) (0)
+#endif
+
+#if defined FSL_EDMA_SOC_IP_DMA5 && FSL_EDMA_SOC_IP_DMA5
+/*!@brief EDMA TCD address convert macro */
+#define EDMA_TCD_SADDR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SADDR))))
+
+#define EDMA_TCD_SOFF(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SOFF))))
+
+#define EDMA_TCD_ATTR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->ATTR))))
+
+#define EDMA_TCD_NBYTES(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->NBYTES))))
+
+#define EDMA_TCD_SLAST(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->SLAST))))
+
+#define EDMA_TCD_DADDR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DADDR))))
+
+#define EDMA_TCD_DOFF(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DOFF))))
+
+#define EDMA_TCD_CITER(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CITER))))
+
+#define EDMA_TCD_DLAST_SGA(tcd, flag)                                         \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ?                         \
+           (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)) : \
+           (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->DLAST_SGA))))
+
+#define EDMA_TCD_CSR(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->CSR))))
+
+#define EDMA_TCD_BITER(tcd, flag)                                                                                    \
+    (*(((edma_tcd_type_t)(flag) == kEDMA_EDMA4Flag) ? (&(((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)) : \
+                                                      (&(((edma5_core_tcd_t *)(&(tcd)->TCD_REGS.edma5_tcd))->BITER))))
+#else
+/*!@brief EDMA TCD address convert macro */
+#define EDMA_TCD_SADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SADDR)
+
+#define EDMA_TCD_SOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SOFF)
+
+#define EDMA_TCD_ATTR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->ATTR)
+
+#define EDMA_TCD_NBYTES(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->NBYTES)
+
+#define EDMA_TCD_SLAST(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->SLAST)
+
+#define EDMA_TCD_DADDR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DADDR)
+
+#define EDMA_TCD_DOFF(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DOFF)
+
+#define EDMA_TCD_CITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CITER)
+
+#define EDMA_TCD_DLAST_SGA(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->DLAST_SGA)
+
+#define EDMA_TCD_CSR(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->CSR)
+
+#define EDMA_TCD_BITER(tcd, flag) (((edma4_core_tcd_t *)(&(tcd)->TCD_REGS.edma4_tcd))->BITER)
+#endif /* FSL_EDMA_SOC_IP_DMA5 */
 /*******************************************************************************
  * API
  ******************************************************************************/
@@ -296,4 +354,4 @@ extern "C" {
  * @}
  */
 
-#endif /* _FSL_EDMA_CORE_H_ */
+#endif /* FSL_EDMA_CORE_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_eim.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_EIM_H_
-#define _FSL_EIM_H_
+#ifndef FSL_EIM_H_
+#define FSL_EIM_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  *****************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Driver version. */
 #define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
-/*@}*/
+/*! @} */
 
 /*******************************************************************************
  * APIs
@@ -47,7 +47,7 @@ void EIM_Init(EIM_Type *base);
  */
 void EIM_Deinit(EIM_Type *base);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name functional

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_eqdc.c

@@ -93,7 +93,7 @@ void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)
     /* Initialize Double-set registers */
     EQDC_ClearBufferedRegisterLoadUpdateMode(base);
     EQDC_ClearEqdcLdok(base);
-
+    
     /* Counter value. */
     EQDC_SetPositionCounterValue(base, psConfig->positionCounterValue);
 
@@ -117,6 +117,9 @@ void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig)
     /* Watchdog. */
     EQDC_SetWatchdogTimeout(base, psConfig->watchdogTimeoutValue);
 
+    /* Clear EQDC_REV */
+    base->REV = 0U;
+
     /* EQDC_IMR. */
     base->IMR = EQDC_IMR_FPHA(psConfig->filterPhaseA) | EQDC_IMR_FPHB(psConfig->filterPhaseB) |
                 EQDC_IMR_FIND_PRE(psConfig->filterIndPre) | EQDC_IMR_FHOM_ENA(psConfig->filterHomEna);
@@ -200,7 +203,7 @@ void EQDC_Deinit(EQDC_Type *base)
  *    psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
  *    psConfig->filterSamplePeriod                  = 0U;
  *    psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
- *    psConfig->positionCompareValue[0]         = 0xFFFFFFFFU;
+ *    psConfig->positionCompareValue[0]  	    = 0xFFFFFFFFU;
  *    psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
  *    psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
  *    psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
@@ -295,4 +298,4 @@ void EQDC_SetOperateMode(EQDC_Type *base, eqdc_operate_mode_t operateMode)
             assert(false);
             break;
     }
-}
+}

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_eqdc.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_EQDC_H_
-#define _FSL_EQDC_H_
+#ifndef FSL_EQDC_H_
+#define FSL_EQDC_H_
 
 #include "fsl_common.h"
 
@@ -17,7 +17,7 @@
 /*******************************************************************************
  * Definitions
  ******************************************************************************/
-#define FSL_EQDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+#define FSL_EQDC_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
 
 /*! @brief W1C bits in EQDC CTRL registers. */
 #define EQDC_CTRL_W1C_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK)
@@ -31,9 +31,14 @@
 #define EQDC_CTRL_INT_EN (EQDC_CTRL_HIE_MASK | EQDC_CTRL_XIE_MASK | EQDC_CTRL_WDIE_MASK)
 
 /*! @brief Interrupt enable bits in EQDC INTCTRL registers. */
+#if (defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
+#define EQDC_INTCTRL_INT_EN                                                                                \
+    (EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK)
+#else
 #define EQDC_INTCTRL_INT_EN                                                                                \
     (EQDC_INTCTRL_SABIE_MASK | EQDC_INTCTRL_DIRIE_MASK | EQDC_INTCTRL_RUIE_MASK | EQDC_INTCTRL_ROIE_MASK | \
      EQDC_INTCTRL_CMP0IE_MASK | EQDC_INTCTRL_CMP1IE_MASK | EQDC_INTCTRL_CMP2IE_MASK | EQDC_INTCTRL_CMP3IE_MASK)
+#endif
 
 /*! @brief Interrupt flag bits in EQDC CTRL registers. */
 #define EQDC_CTRL_INT_FLAGS (EQDC_CTRL_HIRQ_MASK | EQDC_CTRL_XIRQ_MASK | EQDC_CTRL_WDIRQ_MASK)
@@ -43,10 +48,12 @@
     (EQDC_INTCTRL_SABIRQ_MASK | EQDC_INTCTRL_DIRIRQ_MASK | EQDC_INTCTRL_RUIRQ_MASK | EQDC_INTCTRL_ROIRQ_MASK | \
      EQDC_INTCTRL_CMP0IRQ_MASK | EQDC_INTCTRL_CMP1IRQ_MASK | EQDC_INTCTRL_CMP2IRQ_MASK | EQDC_INTCTRL_CMP3IRQ_MASK)
 
+#if !(defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
 #define kEQDC_PositionCompare0InerruptEnable kEQDC_PositionCompare0InterruptEnable
 #define kEQDC_PositionCompare1InerruptEnable kEQDC_PositionCompare1InterruptEnable
 #define kEQDC_PositionCompare2InerruptEnable kEQDC_PositionCompare2InterruptEnable
 #define kEQDC_PositionCompare3InerruptEnable kEQDC_PositionCompare3InterruptEnable
+#endif
 
 /*!
  * @brief EQDC status flags, these flags indicate the counter's events.
@@ -134,6 +141,7 @@ enum _eqdc_interrupt_enable
     kEQDC_PositionRollUnderInterruptEnable = (uint32_t)EQDC_INTCTRL_RUIE_MASK
                                              << 16U, /*!< Roll-under interrupt enable. */
 
+#if !(defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
     kEQDC_PositionCompare0InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP0IE_MASK
                                            << 16U, /*!< Position compare 0 interrupt enable. */
     kEQDC_PositionCompare1InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP1IE_MASK
@@ -142,13 +150,21 @@ enum _eqdc_interrupt_enable
                                            << 16U, /*!< Position compare 2 interrupt enable. */
     kEQDC_PositionCompare3InterruptEnable = (uint32_t)EQDC_INTCTRL_CMP3IE_MASK
                                            << 16U, /*!< Position compare 3 interrupt enable. */
+#endif
 
+#if (defined(FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT) && FSL_FEATURE_EQDC_HAS_NO_COMPARE_INTERRUPT)
+    kEQDC_AllInterruptEnable = kEQDC_HomeEnableTransitionInterruptEnable | kEQDC_IndexPresetPulseInterruptEnable |
+                               kEQDC_WatchdogTimeoutInterruptEnable | kEQDC_SimultPhaseChangeInterruptEnable |
+                               kEQDC_CountDirectionChangeInterruptEnable | kEQDC_PositionRollOverInterruptEnable |
+                               kEQDC_PositionRollUnderInterruptEnable
+#else
     kEQDC_AllInterruptEnable = kEQDC_HomeEnableTransitionInterruptEnable | kEQDC_IndexPresetPulseInterruptEnable |
                                kEQDC_WatchdogTimeoutInterruptEnable | kEQDC_SimultPhaseChangeInterruptEnable |
                                kEQDC_CountDirectionChangeInterruptEnable | kEQDC_PositionRollOverInterruptEnable |
                                kEQDC_PositionRollUnderInterruptEnable | kEQDC_PositionCompare0InterruptEnable |
                                kEQDC_PositionCompare1InterruptEnable | kEQDC_PositionCompare2InterruptEnable |
                                kEQDC_PositionCompare3InterruptEnable
+#endif
 };
 
 /*!
@@ -464,7 +480,7 @@ void EQDC_Init(EQDC_Type *base, const eqdc_config_t *psConfig);
     psConfig->filterSampleCount                   = kEQDC_Filter3Samples;
     psConfig->filterSamplePeriod                  = 0U;
     psConfig->outputPulseMode                     = kEQDC_OutputPulseOnCounterEqualCompare;
-    psConfig->positionCompareValue[0]             = 0xFFFFFFFFU;
+    psConfig->positionCompareValue[0]  	          = 0xFFFFFFFFU;
     psConfig->positionCompareValue[1]             = 0xFFFFFFFFU;
     psConfig->positionCompareValue[2]             = 0xFFFFFFFFU;
     psConfig->positionCompareValue[3]             = 0xFFFFFFFFU;
@@ -1192,4 +1208,4 @@ static inline uint16_t EQDC_GetHoldPositionDifferencePeriod(EQDC_Type *base)
 /*!
  * @}
  */
-#endif /* _FSL_EQDC_H_ */
+#endif /* FSL_EQDC_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_erm.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_ERM_H_
-#define _FSL_ERM_H_
+#ifndef FSL_ERM_H_
+#define FSL_ERM_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  *****************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Driver version. */
 #define FSL_ERM_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
-/*@}*/
+/*! @} */
 
 /*!
  * @brief ERM interrupt configuration structure, default settings all disabled, _erm_interrupt_enable.
@@ -78,7 +78,7 @@ void ERM_Init(ERM_Type *base);
  */
 void ERM_Deinit(ERM_Type *base);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupt
@@ -177,7 +177,7 @@ static inline void ERM_ClearInterruptStatus(ERM_Type *base, erm_memory_channel_t
 #endif
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name functional

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_freqme.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_FREQME_
-#define _FSL_FREQME_
+#ifndef FSL_FREQME_H_
+#define FSL_FREQME_H_
 
 #include "fsl_common.h"
 
@@ -19,10 +19,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief FREQME driver version 2.1.2. */
 #define FSL_FREQME_DRIVER_VERSION (MAKE_VERSION(2, 1, 2))
-/*@}*/
+/*! @} */
 
 /*!
  * @brief The enumeration of interrupt status flags.
@@ -438,4 +438,4 @@ static inline void FREQME_DisableInterrupts(FREQME_Type *base, uint32_t masks)
 /*!
  * @}
  */
-#endif /* __FSL_FREQME_H__ */
+#endif /* FSL_FREQME_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_glikey.c

@@ -46,9 +46,8 @@ static inline void Glikey_Internal_Set_WR_1(GLIKEY_Type *base, uint32_t value);
 
 __WEAK void GLIKEY0_DriverIRQHandler(void)
 {
-    // GLIKEY generates IRQ until corresponding bit in STATUS is cleared by calling
-    // GLIKEY_ClearStatusFlags();
-    //
+    GLIKEY generates IRQ until corresponding bit in STATUS is cleared by calling
+    GLIKEY_ClearStatusFlags();
 }
 */
 
@@ -81,7 +80,7 @@ uint32_t GLIKEY_GetStatus(GLIKEY_Type *base)
 
 status_t GLIKEY_IsLocked(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked == retCode)
     {
         return kStatus_GLIKEY_NotLocked;
@@ -104,16 +103,18 @@ status_t GLIKEY_CheckLock(GLIKEY_Type *base)
     return kStatus_GLIKEY_NotLocked;
 }
 
+#if defined(GLIKEY_VERSION_FSM_CONFIG)
 status_t GLIKEY_GetVersion(GLIKEY_Type *base, uint32_t *result)
 {
     *result = ((GLIKEY_Type *)base)->VERSION;
 
     return kStatus_Success;
 }
+#endif
 
 status_t GLIKEY_SyncReset(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -127,7 +128,7 @@ status_t GLIKEY_SyncReset(GLIKEY_Type *base)
 
 status_t GLIKEY_SetIntEnable(GLIKEY_Type *base, uint32_t value)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -147,7 +148,7 @@ status_t GLIKEY_GetIntEnable(GLIKEY_Type *base, uint32_t *value)
 
 status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -160,7 +161,7 @@ status_t GLIKEY_ClearIntStatus(GLIKEY_Type *base)
 
 status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)
 {
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -174,7 +175,7 @@ status_t GLIKEY_SetIntStatus(GLIKEY_Type *base)
 status_t GLIKEY_Lock(GLIKEY_Type *base)
 {
     /* Check if SFR_LOCK is locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode) /* Glikey is not locked -> lock */
     {
         uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
@@ -216,7 +217,7 @@ status_t GLIKEY_IsIndexLocked(GLIKEY_Type *base, uint32_t index)
 status_t GLIKEY_LockIndex(GLIKEY_Type *base)
 {
     /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -239,7 +240,7 @@ status_t GLIKEY_LockIndex(GLIKEY_Type *base)
 status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
 {
     /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -262,7 +263,7 @@ status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
     ctrl0 |= GLIKEY_CTRL_0_WRITE_INDEX(index);
 
     /* Start the enable process by writting 0x01 to CTRL0.WR_EN_0 */
-    ctrl0 = ctrl0 | (0x01u << GLIKEY_CTRL_0_WR_EN_0_SHIFT);
+    ctrl0 = ctrl0 | ((uint32_t)0x01u << GLIKEY_CTRL_0_WR_EN_0_SHIFT);
 
     /* Write to CTRL0 (new index and WR_EN_0 = 0x01) */
     ((GLIKEY_Type *)base)->CTRL_0 = ctrl0;
@@ -271,7 +272,7 @@ status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
     uint32_t ctrl1 = ((GLIKEY_Type *)base)->CTRL_1;
     /* Clear CTRL1.WR_EN_1 */
     ctrl1 &= ~GLIKEY_CTRL_1_WR_EN_1_MASK;
-    //((GLIKEY_Type*)base)->CTRL_1 = ctrl1;
+    ((GLIKEY_Type*)base)->CTRL_1 = ctrl1;
 
     return kStatus_Success;
 }
@@ -279,7 +280,7 @@ status_t GLIKEY_StartEnable(GLIKEY_Type *base, uint32_t index)
 status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)
 {
     /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -317,7 +318,7 @@ status_t GLIKEY_ContinueEnable(GLIKEY_Type *base, uint32_t codeword)
 status_t GLIKEY_EndOperation(GLIKEY_Type *base)
 {
     /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;
@@ -341,7 +342,8 @@ status_t GLIKEY_EndOperation(GLIKEY_Type *base)
                 return kStatus_GLIKEY_Locked;
             }
 
-            return kStatus_Success;
+            retCode = kStatus_Success;
+            break;
         }
 
         case GLIKEY_FSM_SSR_RESET:
@@ -352,19 +354,23 @@ status_t GLIKEY_EndOperation(GLIKEY_Type *base)
             Glikey_Internal_Set_WR_0(base, WR_0_INIT);
             Glikey_Internal_Set_WR_1(base, WR_1_INIT);
 
-            return kStatus_Success;
+            retCode = kStatus_Success;
+            break;
         }
 
         default:
             /* Disabled error */
-            return kStatus_GLIKEY_DisabledError;
+            retCode = kStatus_GLIKEY_DisabledError;
+            break;
     }
+
+    return retCode;
 }
 
 status_t GLIKEY_ResetIndex(GLIKEY_Type *base, uint32_t index)
 {
     /* Check if Glikey SFR locked */
-    uint32_t retCode = GLIKEY_CheckLock(base);
+    status_t retCode = GLIKEY_CheckLock(base);
     if (kStatus_GLIKEY_NotLocked != retCode)
     {
         return retCode;

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_glikey.h

@@ -73,7 +73,6 @@ enum
 /*******************************************************************************
  * API
  *******************************************************************************/
-extern void GLIKEY0_IRQHandler(void);
 
 #if defined(__cplusplus)
 extern "C" {

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_gpio.c

@@ -28,6 +28,10 @@
     defined(FSL_FEATURE_SOC_PORT_COUNT)
 static PORT_Type *const s_portBases[] = PORT_BASE_PTRS;
 static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#else
+#if defined(GPIO_RESETS_ARRAY)
+static GPIO_Type *const s_gpioBases[] = GPIO_BASE_PTRS;
+#endif
 #endif
 
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_gpio.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_GPIO_H_
-#define _FSL_GPIO_H_
+#ifndef FSL_GPIO_H_
+#define FSL_GPIO_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief GPIO driver version. */
 #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 7, 3))
-/*@}*/
+/*! @} */
 
 #if defined(FSL_FEATURE_GPIO_REGISTERS_WIDTH) && (FSL_FEATURE_GPIO_REGISTERS_WIDTH == 8U)
 #define GPIO_FIT_REG(value) \
@@ -147,7 +147,7 @@ extern "C" {
  */
 
 /*! @name GPIO Configuration */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Initializes a GPIO pin used by the board.
@@ -312,10 +312,10 @@ static inline void GPIO_PortInputDisable(GPIO_Type *base, uint32_t mask)
 }
 #endif /* FSL_FEATURE_GPIO_HAS_PORT_INPUT_CONTROL */
 
-/*@}*/
+/*! @} */
 
 /*! @name GPIO Output Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
@@ -394,10 +394,10 @@ static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t mask)
 #endif
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name GPIO Input Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reads the current input value of the GPIO port.
@@ -413,10 +413,10 @@ static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t pin)
     return (((uint32_t)(base->PDIR) >> pin) & 0x01UL);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name GPIO Interrupt */
-/*@{*/
+/*! @{ */
 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
     defined(FSL_FEATURE_SOC_PORT_COUNT)
 /*!
@@ -604,7 +604,7 @@ static inline void GPIO_SetMultipleInterruptPinsConfig(GPIO_Type *base, uint32_t
 void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
 #endif
 
-/*@}*/
+/*! @} */
 /*! @} */
 
 /*!
@@ -623,7 +623,7 @@ void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribut
 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
 
 /*! @name FGPIO Configuration */
-/*@{*/
+/*! @{ */
 
 #if defined(FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL) && FSL_FEATURE_PCC_HAS_FGPIO_CLOCK_GATE_CONTROL
 /*!
@@ -664,10 +664,10 @@ void FGPIO_PortInit(FGPIO_Type *base);
  */
 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
 
-/*@}*/
+/*! @} */
 
 /*! @name FGPIO Output Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
@@ -722,10 +722,10 @@ static inline void FGPIO_PortToggle(FGPIO_Type *base, uint32_t mask)
 {
     base->PTOR = mask;
 }
-/*@}*/
+/*! @} */
 
 /*! @name FGPIO Input Operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reads the current input value of the FGPIO port.
@@ -740,10 +740,10 @@ static inline uint32_t FGPIO_PinRead(FGPIO_Type *base, uint32_t pin)
 {
     return (((base->PDIR) >> pin) & 0x01U);
 }
-/*@}*/
+/*! @} */
 
 /*! @name FGPIO Interrupt */
-/*@{*/
+/*! @{ */
 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && \
     defined(FSL_FEATURE_SOC_PORT_COUNT)
 
@@ -784,7 +784,7 @@ void FGPIO_PortClearInterruptFlags(FGPIO_Type *base, uint32_t mask);
 void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
 #endif /* FSL_FEATURE_FGPIO_HAS_ATTRIBUTE_CHECKER */
 
-/*@}*/
+/*! @} */
 
 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
 
@@ -796,4 +796,4 @@ void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attrib
  * @}
  */
 
-#endif /* _FSL_GPIO_H_*/
+#endif /* FSL_GPIO_H_*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_i3c.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2023 NXP
+ * Copyright 2018-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -431,7 +431,7 @@ status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status)
     return result;
 }
 
-static status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)
+status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle)
 {
     status_t result = kStatus_Success;
     uint32_t status, errStatus;
@@ -767,8 +767,10 @@ void I3C_GetDefaultConfig(i3c_config_t *config)
     config->baudRate_Hz.i2cBaud          = 400000U;
     config->baudRate_Hz.i3cPushPullBaud  = 12500000U;
     config->baudRate_Hz.i3cOpenDrainBaud = 2500000U;
-    config->masterDynamicAddress         = 0x0AU;    /* Default master dynamic address. */
-    config->slowClock_Hz                 = 1000000U; /* Default slow timer clock 1MHz. */
+    config->masterDynamicAddress         = 0x0AU; /* Default master dynamic address. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    config->slowClock_Hz                 = 0; /* Not update the Soc default setting. */
+#endif
     config->enableSlave                  = true;
     config->vendorID                     = 0x11BU;
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_IDRAND)
@@ -795,7 +797,10 @@ void I3C_GetDefaultConfig(i3c_config_t *config)
  */
 void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_Hz)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \
+    !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET)
     uint32_t instance = I3C_GetInstance(base);
+#endif
     uint32_t configValue;
 
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
@@ -818,14 +823,30 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H
                     I3C_MCONFIG_HKEEP(config->hKeep) | I3C_MCONFIG_ODSTOP(config->enableOpenDrainStop) |
                     I3C_MCONFIG_ODHPP(config->enableOpenDrainHigh);
 
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(config->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(config->restartSclDelay);
+#endif
+
     I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true);
 
     I3C_MasterSetBaudRate(base, &config->baudRate_Hz, sourceClock_Hz);
 
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    assert((config->slowClock_Hz >= 1000000U) || (config->slowClock_Hz == 0U));
+
     uint8_t matchCount;
-    /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/
-    matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL);
+    /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle. Controller uses it to count 100us timeout. Target uses it as IBI request to drive SDA low.
+       Note: Use BAMATCH = 1 to generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */
+    if (config->slowClock_Hz != 0U)
+    {
+        matchCount = (uint8_t)(config->slowClock_Hz / 1000000UL) - 1U;
+        matchCount = (matchCount == 0U) ? 1U : matchCount;
+    }
+    else
+    {
+        /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */
+        matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT);
+    }
 #endif
 
     configValue = base->SCONFIG;
@@ -904,6 +925,8 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H
  */
 void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)
 {
+    (void)memset(masterConfig, 0, sizeof(*masterConfig));
+
     masterConfig->enableMaster                 = kI3C_MasterOn;
     masterConfig->disableTimeout               = false;
     masterConfig->hKeep                        = kI3C_MasterHighKeeperNone;
@@ -928,7 +951,11 @@ void I3C_MasterGetDefaultConfig(i3c_master_config_t *masterConfig)
  */
 void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uint32_t sourceClock_Hz)
 {
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \
+    !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET)
     uint32_t instance = I3C_GetInstance(base);
+#endif
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the clock. */
     CLOCK_EnableClock(kI3cClocks[instance]);
@@ -942,9 +969,33 @@ void I3C_MasterInit(I3C_Type *base, const i3c_master_config_t *masterConfig, uin
                     I3C_MCONFIG_HKEEP(masterConfig->hKeep) | I3C_MCONFIG_ODSTOP(masterConfig->enableOpenDrainStop) |
                     I3C_MCONFIG_ODHPP(masterConfig->enableOpenDrainHigh);
 
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    base->MCONFIG_EXT = I3C_MCONFIG_EXT_I3C_CAS_DEL(masterConfig->startSclDelay) | I3C_MCONFIG_EXT_I3C_CASR_DEL(masterConfig->restartSclDelay);
+#endif
+
     I3C_MasterSetWatermarks(base, kI3C_TxTriggerUntilOneLessThanFull, kI3C_RxTriggerOnNotEmpty, true, true);
 
     I3C_MasterSetBaudRate(base, &masterConfig->baudRate_Hz, sourceClock_Hz);
+
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    assert((masterConfig->slowClock_Hz >= 1000000U) || (masterConfig->slowClock_Hz == 0U));
+
+    uint32_t configValue;
+    uint8_t matchCount;
+
+    /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */
+    if (masterConfig->slowClock_Hz != 0U)
+    {
+        /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for 100us timeout. Note: Use BAMATCH = 1 to generate 1us clock cycle
+           if slow clock is 1MHz. The value of 0 would not give a correct match indication. */
+        matchCount = (uint8_t)(masterConfig->slowClock_Hz / 1000000UL) - 1U;
+        matchCount = (matchCount == 0U) ? 1U : matchCount;
+
+        configValue = base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK;
+        configValue |= I3C_SCONFIG_BAMATCH(matchCount);
+        base->SCONFIG = configValue;
+    }
+#endif
 }
 
 /*!
@@ -1391,6 +1442,7 @@ status_t I3C_MasterReceive(I3C_Type *base, void *rxBuff, size_t rxSize, uint32_t
                     if (I3C_MasterGetState(base) == kI3C_MasterStateDdr)
                     {
                         I3C_MasterEmitRequest(base, kI3C_RequestForceExit);
+                        result = I3C_MasterWaitForCtrlDone(base, false);
                     }
                     else
                     {
@@ -1509,6 +1561,7 @@ status_t I3C_MasterSend(I3C_Type *base, const void *txBuff, size_t txSize, uint3
         if (I3C_MasterGetState(base) == kI3C_MasterStateDdr)
         {
             I3C_MasterEmitRequest(base, kI3C_RequestForceExit);
+            result = I3C_MasterWaitForCtrlDone(base, false);
         }
         else
         {
@@ -1596,7 +1649,7 @@ status_t I3C_MasterProcessDAASpecifiedBaudrate(I3C_Type *base,
         {
             I3C_MasterGetFifoCounts(base, &rxCount, NULL);
 
-            if ((0UL != (status & (uint32_t)kI3C_MasterRxReadyFlag)) && (rxCount != 0U))
+            if (rxCount != 0U)
             {
                 rxBuffer[rxSize++] = (uint8_t)(base->MRDATAB & I3C_MRDATAB_VALUE_MASK);
             }
@@ -1786,6 +1839,32 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
         rxTermOps = kI3C_RxTermLastByte;
     }
 
+    if (0UL != (transfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr))
+    {
+        if (0UL != (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (0UL != (transfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Issue 0x7E as start. */
+        result = I3C_MasterStart(base, transfer->busType, 0x7E, kI3C_Write);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+
     if (0UL == (transfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
     {
         if ((direction == kI3C_Read) && (rxTermOps == kI3C_RxAutoTerm))
@@ -1797,6 +1876,16 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
         {
             result = I3C_MasterStart(base, transfer->busType, transfer->slaveAddress, direction);
         }
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
 
         if (true == I3C_MasterTransferNoStartFlag(base, transfer))
         {
@@ -1860,6 +1949,12 @@ status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *trans
                 I3C_MasterClearFlagsAndEnableIRQ(base);
                 return result;
             }
+
+            result = I3C_MasterWaitForCtrlDone(base, false);
+            if (result != kStatus_Success)
+            {
+                return result;
+            }
         }
     }
 
@@ -2029,14 +2124,21 @@ static void I3C_TransferStateMachineSendCommandState(I3C_Type *base,
         {
             base->MWDATABE = (uint8_t)((handle->transfer.subaddress) >> (8U * handle->transfer.subaddressSize));
 
-            if (0UL == handle->transfer.dataSize)
+            if (handle->transfer.busType != kI3C_TypeI3CDdr)
             {
-                handle->state = (uint8_t)kWaitForCompletionState;
+                if (0UL == handle->transfer.dataSize)
+                {
+                    handle->state = (uint8_t)kWaitForCompletionState;
+                }
+                else
+                {
+                    /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */
+                    handle->state = (uint8_t)kWaitRepeatedStartCompleteState;
+                }
             }
             else
             {
-                /* xfer->dataSize != 0U, xfer->direction = kI3C_Read */
-                handle->state = (uint8_t)kWaitRepeatedStartCompleteState;
+                handle->state = (uint8_t)kTransferDataState;
             }
         }
         else
@@ -2294,6 +2396,32 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t
         direction = (0UL != xfer->subaddressSize) ? kI3C_Write : xfer->direction;
     }
 
+    if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr))
+    {
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Issue 0x7E as start. */
+        result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+
     /* Handle no start option. */
     if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
     {
@@ -2332,10 +2460,14 @@ static status_t I3C_InitTransferStateMachine(I3C_Type *base, i3c_master_handle_t
     {
         handle->state = (uint8_t)kSendCommandState;
     }
-    else
+    else if (xfer->dataSize != 0U)
     {
         handle->state = (uint8_t)kTransferDataState;
     }
+    else
+    {
+        handle->state = (uint8_t)kStopState;
+    }
 
     if ((handle->remainingBytes < 256U) && (direction == kI3C_Read))
     {
@@ -2514,14 +2646,14 @@ void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle)
  * note This function does not need to be called unless you are reimplementing the
  *  nonblocking API's interrupt handler routines to add special functionality.
  * param base The I3C peripheral base address.
- * param handle Pointer to the I3C master driver handle.
+ * param intHandle Pointer to the I3C master driver handle.
  */
 void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle)
 {
-    bool isDone;
+    i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle;
     status_t result;
+    bool isDone;
 
-    i3c_master_handle_t *handle = (i3c_master_handle_t *)intHandle;
     /* Don't do anything if we don't have a valid handle. */
     if (NULL == handle)
     {
@@ -2620,14 +2752,19 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig)
  * param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of
  * defaults that you can override.
  * param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values.
+ * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
  */
 void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz)
 {
     assert(NULL != slaveConfig);
-    assert(0UL != slowClock_Hz);
+    assert((slowClock_Hz >= 1000000U) || (slowClock_Hz == 0U));
 
     uint32_t configValue;
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) || \
+    !(defined(FSL_FEATURE_I3C_HAS_NO_RESET) && FSL_FEATURE_I3C_HAS_NO_RESET)
     uint32_t instance = I3C_GetInstance(base);
+#endif
+
 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
     /* Ungate the clock. */
     CLOCK_EnableClock(kI3cClocks[instance]);
@@ -2640,8 +2777,18 @@ void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32
 
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
     uint8_t matchCount;
-    /* Caculate bus available condition match value for current slow clock, count value provides 1us.*/
-    matchCount = (uint8_t)(slowClock_Hz / 1000000UL);
+    /* Set as (slowClk(MHz) - 1) to generate 1us clock cycle for IBI request to drive SDA low. Note: Use BAMATCH = 1 to
+       generate 1us clock cycle if slow clock is 1MHz. The value of 0 would not give a correct match indication. */
+    if (slowClock_Hz != 0U)
+    {
+        matchCount = (uint8_t)(slowClock_Hz / 1000000UL) - 1U;
+        matchCount = (matchCount == 0U) ? 1U : matchCount;
+    }
+    else
+    {
+        /* BAMATCH has default value based on Soc default slow clock after reset, using this default value when slowClock_Hz is 0. */
+        matchCount = (uint8_t)((base->SCONFIG & I3C_SCONFIG_BAMATCH_MASK) >> I3C_SCONFIG_BAMATCH_SHIFT);
+    }
 #endif
 
     configValue = base->SCONFIG;
@@ -3172,7 +3319,7 @@ static void I3C_SlaveTransferHandleBusStop(I3C_Type *base,
     I3C_SlaveDisableInterrupts(base, (uint32_t)kI3C_SlaveTxReadyFlag);
     stateParams->pendingInts &= ~(uint32_t)kI3C_SlaveTxReadyFlag;
     base->SDATACTRL |= I3C_SDATACTRL_FLUSHTB_MASK | I3C_SDATACTRL_FLUSHFB_MASK;
-    if (handle->isBusy == true)
+    if (handle->isBusy)
     {
         handle->transfer.event            = (uint32_t)kI3C_SlaveCompletionEvent;
         handle->transfer.completionStatus = kStatus_Success;
@@ -3223,6 +3370,7 @@ static void I3C_SlaveTransferHandleTxReady(I3C_Type *base,
         if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag))
         {
             handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent;
+            handle->isBusy = true;
         }
         if (NULL != handle->callback)
         {
@@ -3269,6 +3417,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base,
         if (0UL != (stateParams->flags & (uint32_t)kI3C_SlaveBusHDRModeFlag))
         {
             handle->transfer.event |= (uint32_t)kI3C_SlaveHDRCommandMatchEvent;
+            handle->isBusy = true;
         }
         if (NULL != handle->callback)
         {
@@ -3291,7 +3440,7 @@ static void I3C_SlaveTransferHandleRxReady(I3C_Type *base,
  * note This function does not need to be called unless you are reimplementing the
  *  non blocking API's interrupt handler routines to add special functionality.
  * param base The I3C peripheral base address.
- * param handle Pointer to #i3c_slave_handle_t structure which stores the transfer state.
+ * param intHandle Pointer to #i3c_slave_handle_t structure which stores the transfer state.
  */
 void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle)
 {
@@ -3412,3 +3561,12 @@ void I3C2_DriverIRQHandler(void)
     I3C_CommonIRQHandler(I3C2, 2);
 }
 #endif
+
+#if defined(I3C3)
+/* Implementation of I3C3 handler named in startup code. */
+void I3C3_DriverIRQHandler(void);
+void I3C3_DriverIRQHandler(void)
+{
+    I3C_CommonIRQHandler(I3C3, 3);
+}
+#endif

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_i3c.h

@@ -1,10 +1,10 @@
 /*
- * Copyright 2018-2023 NXP
+ * Copyright 2018-2024 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_I3C_H_
-#define _FSL_I3C_H_
+#ifndef FSL_I3C_H_
+#define FSL_I3C_H_
 
 #include "fsl_common.h"
 
@@ -18,10 +18,10 @@
  */
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief I3C driver version */
-#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 10, 4))
-/*@}*/
+#define FSL_I3C_DRIVER_VERSION (MAKE_VERSION(2, 12, 0))
+/*! @} */
 
 /*! @brief Timeout times for waiting flag. */
 #ifndef I3C_RETRY_TIMES
@@ -262,6 +262,15 @@ typedef enum _i3c_rx_term_ops
     kI3C_RxTermLastByte = 2U,  /*!< Master terminates read at any time after START, no length limitation. */
 } i3c_rx_term_ops_t;
 
+/*! @brief I3C start SCL delay options. */
+typedef enum _i3c_start_scl_delay
+{
+    kI3C_NoDelay = 0U, /*!< No delay. */
+    kI3C_IncreaseSclHalfPeriod = 1U, /*!< Increases SCL clock period by 1/2. */
+    kI3C_IncreaseSclOnePeriod = 2U, /*!< Increases SCL clock period by 1. */
+    kI3C_IncreaseSclOneAndHalfPeriod = 3U, /*!< Increases SCL clock period by 1 1/2 */
+} i3c_start_scl_delay_t;
+
 /*! @brief Structure with setting master IBI rules and slave registry. */
 typedef struct _i3c_register_ibi_addr
 {
@@ -302,6 +311,13 @@ typedef struct _i3c_master_config
     bool enableOpenDrainStop;         /*!< Whether to emit open-drain speed STOP. */
     bool enableOpenDrainHigh;         /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
     i3c_baudrate_hz_t baudRate_Hz;    /*!< Desired baud rate settings. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
+    uint32_t slowClock_Hz;            /*!< Slow clock frequency. */
+#endif
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */
+    i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */
+#endif
 } i3c_master_config_t;
 
 /* Forward declaration of the transfer descriptor and handle typedefs. */
@@ -337,6 +353,7 @@ enum _i3c_master_transfer_flags
     kI3C_TransferDisableRxTermFlag = 0x10U, /*!< Disable Rx termination. Note: It's for I3C CCC transfer. */
     kI3C_TransferRxAutoTermFlag =
         0x20U, /*!< Set Rx auto-termination. Note: It's adaptive based on Rx size(<=255 bytes) except in I3C_MasterReceive. */
+    kI3C_TransferStartWithBroadcastAddr = 0x40U, /*!< Start transfer with 0x7E, then read/write data with device address. */
 };
 
 /*!
@@ -619,8 +636,14 @@ typedef struct _i3c_config
     bool enableOpenDrainStop;         /*!< Whether to emit open-drain speed STOP. */
     bool enableOpenDrainHigh;         /*!< Enable Open-Drain High to be 1 PPBAUD count for i3c messages, or 1 ODBAUD. */
     i3c_baudrate_hz_t baudRate_Hz;    /*!< Desired baud rate settings. */
+#if defined(FSL_FEATURE_I3C_HAS_START_SCL_DELAY) && FSL_FEATURE_I3C_HAS_START_SCL_DELAY
+    i3c_start_scl_delay_t startSclDelay; /*!< I3C SCL delay after START. */
+    i3c_start_scl_delay_t restartSclDelay; /*!< I3C SCL delay after Repeated START. */
+#endif
     uint8_t masterDynamicAddress;     /*!< Main master dynamic address configuration. */
+#if !(defined(FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH) && FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH)
     uint32_t slowClock_Hz;            /*!< Slow clock frequency for time control. */
+#endif
     uint32_t maxWriteLength;          /*!< Maximum write length. */
     uint32_t maxReadLength;           /*!< Maximum read length. */
     bool enableSlave;                 /*!< Whether to enable slave. */
@@ -735,7 +758,7 @@ void I3C_Init(I3C_Type *base, const i3c_config_t *config, uint32_t sourceClock_H
  */
 
 /*! @name Initialization and deinitialization */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Provides a default configuration for the I3C master peripheral.
@@ -785,6 +808,9 @@ void I3C_MasterDeinit(I3C_Type *base);
 /* Not static so it can be used from fsl_i3c_dma.c. */
 status_t I3C_MasterCheckAndClearError(I3C_Type *base, uint32_t status);
 
+/* Not static so it can be used from fsl_i3c_dma.c. */
+status_t I3C_MasterWaitForCtrlDone(I3C_Type *base, bool waitIdle);
+
 /* Not static so it can be used from fsl_i3c_dma.c. */
 status_t I3C_CheckForBusyBus(I3C_Type *base);
 
@@ -799,10 +825,10 @@ static inline void I3C_MasterEnable(I3C_Type *base, i3c_master_enable_t enable)
     base->MCONFIG = (base->MCONFIG & ~I3C_MCONFIG_MSTENA_MASK) | I3C_MCONFIG_MSTENA(enable);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Status */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Gets the I3C master status flags.
@@ -886,10 +912,10 @@ static inline void I3C_MasterClearErrorStatusFlags(I3C_Type *base, uint32_t stat
  */
 i3c_master_state_t I3C_MasterGetState(I3C_Type *base);
 
-/*@}*/
+/*! @} */
 
 /*! @name Interrupts */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables the I3C master interrupt requests.
@@ -945,10 +971,10 @@ static inline uint32_t I3C_MasterGetPendingInterrupts(I3C_Type *base)
     return base->MINTMASKED;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables I3C master DMA requests.
@@ -991,10 +1017,10 @@ static inline uint32_t I3C_MasterGetRxFifoAddress(I3C_Type *base, uint32_t width
     return (uint32_t)((width == 2U) ? &base->MRDATAH : &base->MRDATAB);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name FIFO control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the watermarks for I3C master FIFOs.
@@ -1035,10 +1061,10 @@ static inline void I3C_MasterGetFifoCounts(I3C_Type *base, size_t *rxCount, size
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Bus operations */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the I3C bus frequency for master transactions.
@@ -1331,10 +1357,10 @@ i3c_device_info_t *I3C_MasterGetDeviceListAfterDAA(I3C_Type *base, uint8_t *coun
  */
 status_t I3C_MasterTransferBlocking(I3C_Type *base, i3c_master_transfer_t *transfer);
 
-/*@}*/
+/*! @} */
 
 /*! @name Non-blocking */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Creates a new handle for the I3C master non-blocking APIs.
@@ -1393,21 +1419,21 @@ status_t I3C_MasterTransferGetCount(I3C_Type *base, i3c_master_handle_t *handle,
  */
 void I3C_MasterTransferAbort(I3C_Type *base, i3c_master_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @name IRQ handler */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reusable routine to handle master interrupts.
  * @note This function does not need to be called unless you are reimplementing the
  *  nonblocking API's interrupt handler routines to add special functionality.
  * @param base The I3C peripheral base address.
- * @param handle Pointer to the I3C master driver handle.
+ * @param intHandle Pointer to the I3C master driver handle.
  */
 void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle);
 
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -1417,7 +1443,7 @@ void I3C_MasterTransferHandleIRQ(I3C_Type *base, void *intHandle);
  */
 
 /*! @name Initialization and deinitialization */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Provides a default configuration for the I3C slave peripheral.
@@ -1444,6 +1470,7 @@ void I3C_SlaveGetDefaultConfig(i3c_slave_config_t *slaveConfig);
  * @param slaveConfig User provided peripheral configuration. Use I3C_SlaveGetDefaultConfig() to get a set of
  * defaults that you can override.
  * @param slowClock_Hz Frequency in Hertz of the I3C slow clock. Used to calculate the bus match condition values.
+ * If FSL_FEATURE_I3C_HAS_NO_SCONFIG_BAMATCH defines as 1, this parameter is useless.
  */
 void I3C_SlaveInit(I3C_Type *base, const i3c_slave_config_t *slaveConfig, uint32_t slowClock_Hz);
 
@@ -1467,10 +1494,10 @@ static inline void I3C_SlaveEnable(I3C_Type *base, bool isEnable)
     base->SCONFIG = (base->SCONFIG & ~I3C_SCONFIG_SLVENA_MASK) | I3C_SCONFIG_SLVENA(isEnable);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Status */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Gets the I3C slave status flags.
@@ -1551,10 +1578,10 @@ i3c_slave_activity_state_t I3C_SlaveGetActivityState(I3C_Type *base);
 
 /* Not static so it can be used from fsl_i3c_dma.c. */
 status_t I3C_SlaveCheckAndClearError(I3C_Type *base, uint32_t status);
-/*@}*/
+/*! @} */
 
 /*! @name Interrupts */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables the I3C slave interrupt requests.
@@ -1630,10 +1657,10 @@ static inline uint32_t I3C_SlaveGetPendingInterrupts(I3C_Type *base)
     return base->SINTMASKED;
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name DMA control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Enables or disables I3C slave DMA requests.
@@ -1676,10 +1703,10 @@ static inline uint32_t I3C_SlaveGetRxFifoAddress(I3C_Type *base, uint32_t width)
     return (uint32_t)((width == 2U) ? &base->SRDATAH : &base->SRDATAB);
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name FIFO control */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Sets the watermarks for I3C slave FIFOs.
@@ -1720,10 +1747,10 @@ static inline void I3C_SlaveGetFifoCounts(I3C_Type *base, size_t *rxCount, size_
     }
 }
 
-/*@}*/
+/*! @} */
 
 /*! @name Bus operations */
-/*@{*/
+/*! @{ */
 
 #if !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ)
 /*!
@@ -1755,10 +1782,10 @@ status_t I3C_SlaveSend(I3C_Type *base, const void *txBuff, size_t txSize);
  */
 status_t I3C_SlaveReceive(I3C_Type *base, void *rxBuff, size_t rxSize);
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave non-blocking */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Creates a new handle for the I3C slave non-blocking APIs.
@@ -1828,17 +1855,17 @@ status_t I3C_SlaveTransferGetCount(I3C_Type *base, i3c_slave_handle_t *handle, s
  */
 void I3C_SlaveTransferAbort(I3C_Type *base, i3c_slave_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @name Slave IRQ handler */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Reusable routine to handle slave interrupts.
  * @note This function does not need to be called unless you are reimplementing the
  *  non blocking API's interrupt handler routines to add special functionality.
  * @param base The I3C peripheral base address.
- * @param handle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
+ * @param intHandle Pointer to struct: _i3c_slave_handle structure which stores the transfer state.
  */
 void I3C_SlaveTransferHandleIRQ(I3C_Type *base, void *intHandle);
 
@@ -1863,10 +1890,10 @@ void I3C_SlaveRequestIBIWithData(I3C_Type *base, uint8_t *data, size_t dataSize)
 void I3C_SlaveRequestIBIWithSingleData(I3C_Type *base, uint8_t data, size_t dataSize);
 #endif /* !(defined(FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) && FSL_FEATURE_I3C_HAS_NO_SLAVE_IBI_MR_HJ) */
 
-/*@}*/
+/*! @} */
 /*! @} */
 #if defined(__cplusplus)
 }
 #endif
 
-#endif /* _FSL_I3C_H_ */
+#endif /* FSL_I3C_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_i3c_edma.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2023 NXP
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,12 +67,18 @@ enum _i3c_edma_flag_constants
 /*******************************************************************************
  * Variables
  ******************************************************************************/
+/*! @brief Array to map I3C instance number to base pointer. */
+static I3C_Type *const kI3cBases[] = I3C_BASE_PTRS;
+
+/*! @brief Array to store the END byte of I3C teransfer. */
+static uint8_t i3cEndByte[ARRAY_SIZE(kI3cBases)] = {0};
 
 /*******************************************************************************
  * Prototypes
  ******************************************************************************/
 static void I3C_MasterRunEDMATransfer(
     I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction);
+
 /*******************************************************************************
  * Code
  ******************************************************************************/
@@ -82,40 +88,47 @@ static void I3C_MasterTransferEDMACallbackRx(edma_handle_t *dmaHandle, void *par
 
     if (transferDone)
     {
-        /* Read last data byte */
+        /* Terminate following data if present. */
         i3cHandle->base->MCTRL |= I3C_MCTRL_RDTERM(1U);
-        size_t rxCount = 0U;
-        while (rxCount == 0U)
+
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+        if (i3cHandle->transfer.dataSize > 1U)
         {
-            I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL);
-        };
-        *(uint8_t *)((uint32_t)((uint32_t *)i3cHandle->transfer.data) + i3cHandle->transfer.dataSize - 1U) =
-            (uint8_t)i3cHandle->base->MRDATAB;
+            size_t rxCount;
+            /* Read out the last byte data. */
+            do
+            {
+                I3C_MasterGetFifoCounts(i3cHandle->base, &rxCount, NULL);
+            } while (rxCount == 0U);
+            *(uint8_t *)((uint32_t)(uint32_t *)i3cHandle->transfer.data + i3cHandle->transfer.dataSize - 1U) =
+                (uint8_t)i3cHandle->base->MRDATAB;
+        }
+#endif
 
-        /* Disable I3C Rx DMA */
+        /* Disable I3C Rx DMA. */
         i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMAFB_MASK;
-
-        i3cHandle->state = (uint8_t)kStopState;
-        I3C_MasterTransferEDMAHandleIRQ(i3cHandle->base, i3cHandle);
     }
 }
 
 static void I3C_MasterTransferEDMACallbackTx(edma_handle_t *dmaHandle, void *param, bool transferDone, uint32_t tcds)
 {
     i3c_master_edma_handle_t *i3cHandle = (i3c_master_edma_handle_t *)param;
+    uint32_t instance;
 
     if (transferDone)
     {
-        /* Disable I3C Tx DMA */
+        /* Disable I3C Tx DMA. */
         i3cHandle->base->MDATACTRL &= ~I3C_MDMACTRL_DMATB_MASK;
-        i3cHandle->state = (uint8_t)kStopState;
 
-        size_t txCount = 0U;
-        do
+        if (i3cHandle->transferCount != 1U)
         {
-            I3C_MasterGetFifoCounts(i3cHandle->base, NULL, &txCount);
-        } while (txCount != 0U);
-        I3C_MasterTransferEDMAHandleIRQ(i3cHandle->base, i3cHandle);
+            instance = I3C_GetInstance(i3cHandle->base);
+            /* Ensure there's space in the Tx FIFO. */
+            while ((i3cHandle->base->MDATACTRL & I3C_MDATACTRL_TXFULL_MASK) != 0U)
+            {
+            }
+            i3cHandle->base->MWDATABE = i3cEndByte[instance];
+        }
     }
 }
 /*!
@@ -144,6 +157,32 @@ static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_maste
         handle->state = (uint8_t)kStopState;
     }
 
+    if (0UL != (xfer->flags & (uint32_t)kI3C_TransferStartWithBroadcastAddr))
+    {
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        if (0UL != (xfer->flags & (uint32_t)kI3C_TransferRepeatedStartFlag))
+        {
+            return kStatus_InvalidArgument;
+        }
+
+        /* Issue 0x7E as start. */
+        result = I3C_MasterStart(base, xfer->busType, 0x7E, kI3C_Write);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+
+        result = I3C_MasterWaitForCtrlDone(base, false);
+        if (result != kStatus_Success)
+        {
+            return result;
+        }
+    }
+
     /* Handle no start option. */
     if (0U != (xfer->flags & (uint32_t)kI3C_TransferNoStartFlag))
     {
@@ -190,7 +229,7 @@ static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_maste
 
         if (handle->transfer.direction == kI3C_Read)
         {
-            I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize - 1U, kI3C_Read);
+            I3C_MasterRunEDMATransfer(base, handle, xfer->data, xfer->dataSize, kI3C_Read);
         }
 
         if (handle->state != (uint8_t)kStopState)
@@ -214,10 +253,11 @@ static status_t I3C_MasterInitTransferStateMachineEDMA(I3C_Type *base, i3c_maste
 static void I3C_MasterRunEDMATransfer(
     I3C_Type *base, i3c_master_edma_handle_t *handle, void *data, size_t dataSize, i3c_direction_t direction)
 {
-    edma_transfer_config_t xferConfig;
-    uint32_t address;
     bool isEnableTxDMA = false;
     bool isEnableRxDMA = false;
+    edma_transfer_config_t xferConfig;
+    uint32_t instance;
+    uint32_t address;
     uint32_t width;
 
     handle->transferCount = dataSize;
@@ -225,7 +265,18 @@ static void I3C_MasterRunEDMATransfer(
     switch (direction)
     {
         case kI3C_Write:
-            address = (uint32_t)&base->MWDATAB1;
+            if (dataSize != 1U)
+            {
+                address = (uint32_t)&base->MWDATAB1;
+                /* Cause controller sends command and data with same interface, need special buffer to store the END byte. */
+                instance = I3C_GetInstance(base);
+                i3cEndByte[instance] = *(uint8_t *)((uint32_t)(uint32_t *)data + dataSize - 1U);
+                dataSize--;
+            }
+            else
+            {
+                address = (uint32_t)&base->MWDATABE;
+            }
             EDMA_PrepareTransfer(&xferConfig, data, sizeof(uint8_t), (uint32_t *)address, sizeof(uint8_t), 1, dataSize,
                                  kEDMA_MemoryToPeripheral);
             (void)EDMA_SubmitTransfer(handle->txDmaHandle, &xferConfig);
@@ -235,6 +286,15 @@ static void I3C_MasterRunEDMATransfer(
             break;
 
         case kI3C_Read:
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+            /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the
+            last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA
+            interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */
+            if (dataSize > 1U)
+            {
+                dataSize--;
+            }
+#endif
             address = (uint32_t)&base->MRDATAB;
             EDMA_PrepareTransfer(&xferConfig, (uint32_t *)address, sizeof(uint8_t), data, sizeof(uint8_t), 1, dataSize,
                                  kEDMA_PeripheralToMemory);
@@ -246,7 +306,7 @@ static void I3C_MasterRunEDMATransfer(
 
         default:
             /* This should never happen */
-            assert(0);
+            assert(false);
             break;
     }
 
@@ -364,12 +424,6 @@ static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master
                 break;
 
             case (uint8_t)kSendCommandState:
-                /* Calculate command count and put into command buffer. */
-                if (xfer->dataSize == 0U)
-                {
-                    *isDone = true;
-                }
-
                 I3C_MasterRunEDMATransfer(base, handle, handle->subaddressBuffer, handle->subaddressCount, kI3C_Write);
 
                 if ((xfer->direction == kI3C_Read) || (0UL == xfer->dataSize))
@@ -442,6 +496,7 @@ static status_t I3C_MasterRunTransferStateMachineEDMA(I3C_Type *base, i3c_master
                     else
                     {
                         I3C_MasterEmitRequest(base, kI3C_RequestEmitStop);
+                        result = I3C_MasterWaitForCtrlDone(base, false);
                     }
                 }
                 *isDone        = true;
@@ -593,6 +648,7 @@ void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle)
         if ((result == kStatus_I3C_Nak) || (result == kStatus_I3C_IBIWon))
         {
             I3C_MasterEmitRequest(base, kI3C_RequestEmitStop);
+            (void)I3C_MasterWaitForCtrlDone(base, false);
         }
 
         /* Set handle to idle state. */
@@ -692,12 +748,29 @@ static void I3C_SlaveTransferEDMACallback(edma_handle_t *dmaHandle, void *param,
 
             if (i3cHandle->transfer.txDataSize > 1U)
             {
+                /* Ensure there's space in the Tx FIFO. */
+                while ((i3cHandle->base->SDATACTRL & I3C_SDATACTRL_TXFULL_MASK) != 0U)
+                {
+                }
                 /* Send the last byte. */
                 i3cHandle->base->SWDATABE = *(uint8_t *)((uintptr_t)i3cHandle->transfer.txData + i3cHandle->transfer.txDataSize - 1U);
             }
         }
         else
         {
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+            if (i3cHandle->transfer.rxDataSize > 1U)
+            {
+                size_t rxCount;
+                /* Read out the last byte data. */
+                do
+                {
+                    I3C_SlaveGetFifoCounts(i3cHandle->base, &rxCount, NULL);
+                } while (rxCount == 0U);
+                *(uint8_t *)((uintptr_t)i3cHandle->transfer.rxData + i3cHandle->transfer.rxDataSize - 1U) =
+                    (uint8_t)i3cHandle->base->SRDATAB;
+            }
+#endif
             i3cHandle->base->SDMACTRL &= ~I3C_SDMACTRL_DMAFB_MASK;
         }
     }
@@ -778,7 +851,7 @@ static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *hand
     }
     else
     {
-        txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB;
+        txFifoBase = (uint32_t *)(uintptr_t)&base->SWDATAB1;
         EDMA_PrepareTransfer(&txConfig, xfer->txData, 1, (void *)txFifoBase, 1, 1, xfer->txDataSize - 1U,
                              kEDMA_MemoryToPeripheral);
     }
@@ -789,11 +862,22 @@ static void I3C_SlavePrepareTxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *hand
 
 static void I3C_SlavePrepareRxEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
 {
-    edma_transfer_config_t rxConfig;
     uint32_t *rxFifoBase            = (uint32_t *)(uintptr_t)&base->SRDATAB;
     i3c_slave_edma_transfer_t *xfer = &handle->transfer;
+    size_t dataSize                 = xfer->rxDataSize;
+    edma_transfer_config_t rxConfig;
+
+#if defined(FSL_FEATURE_I3C_HAS_ERRATA_052086) && (FSL_FEATURE_I3C_HAS_ERRATA_052086)
+    /* ERRATA052086: Soc integration issue results in target misses the last DMA request to copy the
+    last one byte from controler when transmission data size is > 1 byte. Resolution: Triggering DMA
+    interrupt one byte in advance, then receive the last one byte data after DMA transmission finishes. */
+    if (dataSize > 1U)
+    {
+        dataSize--;
+    }
+#endif
 
-    EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, xfer->rxDataSize,
+    EDMA_PrepareTransfer(&rxConfig, (void *)rxFifoBase, 1, xfer->rxData, 1, 1, dataSize,
                          kEDMA_PeripheralToMemory);
     (void)EDMA_SubmitTransfer(handle->rxDmaHandle, &rxConfig);
     EDMA_StartTransfer(handle->rxDmaHandle);

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_i3c_edma.h

@@ -3,8 +3,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_I3C_EDMA_H_
-#define _FSL_I3C_EDMA_H_
+#ifndef FSL_I3C_EDMA_H_
+#define FSL_I3C_EDMA_H_
 
 #include "fsl_i3c.h"
 #include "fsl_edma.h"
@@ -14,10 +14,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief I3C EDMA driver version. */
-#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
-/*@}*/
+#define FSL_I3C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 9))
+/*! @} */
 
 /*!
  * @addtogroup i3c_master_edma_driver
@@ -125,7 +125,7 @@ extern "C" {
  */
 
 /*! @name Master DMA */
-/*@{*/
+/*! @{ */
 
 /*!
  * @brief Create a new handle for the I3C master DMA APIs.
@@ -193,10 +193,10 @@ void I3C_MasterTransferAbortEDMA(I3C_Type *base, i3c_master_edma_handle_t *handl
  * @note This function does not need to be called unless you are reimplementing the
  *  nonblocking API's interrupt handler routines to add special functionality.
  * @param base The I3C peripheral base address.
- * @param handle Pointer to the I3C master DMA driver handle.
+ * @param i3cHandle Pointer to the I3C master DMA driver handle.
  */
 void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -206,7 +206,7 @@ void I3C_MasterTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
  */
 
 /*! @name Slave DMA */
-/*@{*/
+/*! @{ */
 /*!
  * @brief Create a new handle for the I3C slave DMA APIs.
  *
@@ -266,14 +266,14 @@ void I3C_SlaveTransferAbortEDMA(I3C_Type *base, i3c_slave_edma_handle_t *handle)
  * @note This function does not need to be called unless you are reimplementing the
  *  nonblocking API's interrupt handler routines to add special functionality.
  * @param base The I3C peripheral base address.
- * @param handle Pointer to the I3C slave DMA driver handle.
+ * @param i3cHandle Pointer to the I3C slave DMA driver handle.
  */
 void I3C_SlaveTransferEDMAHandleIRQ(I3C_Type *base, void *i3cHandle);
-/*@}*/
+/*! @} */
 
 /*! @} */
 #if defined(__cplusplus)
 }
 #endif
 
-#endif /* _FSL_I3C_EDMA_H_ */
+#endif /* FSL_I3C_EDMA_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_inputmux.h

@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_INPUTMUX_H_
-#define _FSL_INPUTMUX_H_
+#ifndef FSL_INPUTMUX_H_
+#define FSL_INPUTMUX_H_
 
 #include "fsl_inputmux_connections.h"
 #include "fsl_common.h"
@@ -25,10 +25,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Group interrupt driver version for SDK */
 #define FSL_INPUTMUX_DRIVER_VERSION (MAKE_VERSION(2, 0, 7))
-/*@}*/
+/*! @} */
 
 /*******************************************************************************
  * API
@@ -98,6 +98,6 @@ void INPUTMUX_Deinit(INPUTMUX_Type *base);
 }
 #endif
 
-/*@}*/
+/*! @} */
 
-#endif /* _FSL_INPUTMUX_H_ */
+#endif /* FSL_INPUTMUX_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_inputmux_connections.h

@@ -62,6 +62,8 @@
 #define LPSPI0_TRIG_REG           0x5E0U
 #define LPSPI1_TRIG_REG           0x600U
 #define LPUART0_TRIG_REG          0x620U
+#define LPUART1_TRIG_REG          0x640U
+#define LPUART2_TRIG_REG          0x660U
 
 #define PMUX_SHIFT 20U
 
@@ -1300,6 +1302,74 @@ typedef enum _inputmux_connection_t
     kINPUTMUX_Gpio3PinEventTrig0ToLpuart0Trigger      = 32U + (LPUART0_TRIG_REG << PMUX_SHIFT),
     kINPUTMUX_WuuToLpuart0Trigger                     = 34U + (LPUART0_TRIG_REG << PMUX_SHIFT),
     kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart0Trigger = 35U + (LPUART0_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART1 trigger input connections. */
+    kINPUTMUX_ArmTxevToLpuart1Trigger                 = 1U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToLpuart1Trigger                = 2U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart1Trigger                = 3U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart1Trigger                = 4U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart1Trigger                = 5U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart1Trigger                 = 6U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart1Trigger                 = 7U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart1Trigger               = 9U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart1Trigger               = 10U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart1Trigger               = 11U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart1Trigger               = 12U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart1Trigger               = 13U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart1Trigger               = 14U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart1Trigger                  = 15U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart1Trigger                 = 17U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart1Trigger                 = 18U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart1Trigger                 = 19U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart1Trigger                 = 20U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart1Trigger                 = 21U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart1Trigger                 = 22U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart1Trigger                 = 23U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart1Trigger                 = 24U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart1Trigger                 = 25U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart1Trigger                 = 26U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart1Trigger                = 27U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart1Trigger                = 28U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart1Trigger      = 29U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart1Trigger      = 30U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart1Trigger      = 31U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart1Trigger      = 32U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart1Trigger                     = 34U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart1Trigger = 35U + (LPUART1_TRIG_REG << PMUX_SHIFT),
+
+    /*!< LPUART2 trigger input connections. */
+    kINPUTMUX_ArmTxevToLpuart2Trigger                 = 1U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out0ToLpuart2Trigger                = 2U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out1ToLpuart2Trigger                = 3U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out2ToLpuart2Trigger                = 4U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Aoi0Out3ToLpuart2Trigger                = 5U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp0OutToLpuart2Trigger                 = 6U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Cmp1OutToLpuart2Trigger                 = 7U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M2ToLpuart2Trigger               = 9U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer0M3ToLpuart2Trigger               = 10U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M2ToLpuart2Trigger               = 11U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer1M3ToLpuart2Trigger               = 12U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M2ToLpuart2Trigger               = 13U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Ctimer2M3ToLpuart2Trigger               = 14U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Lptmr0ToLpuart2Trigger                  = 15U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn0ToLpuart2Trigger                 = 17U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn1ToLpuart2Trigger                 = 18U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn2ToLpuart2Trigger                 = 19U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn3ToLpuart2Trigger                 = 20U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn4ToLpuart2Trigger                 = 21U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn5ToLpuart2Trigger                 = 22U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn6ToLpuart2Trigger                 = 23U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn7ToLpuart2Trigger                 = 24U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn8ToLpuart2Trigger                 = 25U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn9ToLpuart2Trigger                 = 26U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn10ToLpuart2Trigger                = 27U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_TrigIn11ToLpuart2Trigger                = 28U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio0PinEventTrig0ToLpuart2Trigger      = 29U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio1PinEventTrig0ToLpuart2Trigger      = 30U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio2PinEventTrig0ToLpuart2Trigger      = 31U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Gpio3PinEventTrig0ToLpuart2Trigger      = 32U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_WuuToLpuart2Trigger                     = 34U + (LPUART2_TRIG_REG << PMUX_SHIFT),
+    kINPUTMUX_Usb0IppIndUartRxdUsbmuxToLpuart2Trigger = 35U + (LPUART2_TRIG_REG << PMUX_SHIFT),
 } inputmux_connection_t;
 
 /*@}*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpadc.c

@@ -29,18 +29,18 @@
 #define ADC_CMDL_CHANNEL_MODE(x) \
     (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CHANNEL_MODE_SHIFT)) & ADC_CMDL_CHANNEL_MODE_MASK)
 
-#define GET_ADC_CFG_TPRICTRL_VALUE(val) (val & 0x3U)
+#define GET_ADC_CFG_TPRICTRL_VALUE(val) (((uint32_t)val) & 0x3U)
 
 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES
-#define GET_ADC_CFG_TRES_VALUE(val) ((val & 0x4U) >> 2U)
+#define GET_ADC_CFG_TRES_VALUE(val) ((((uint32_t)val) & 0x4U) >> 2U)
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */
 
 #if defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES
-#define GET_ADC_CFG_TCMDRES_VALUE(val) ((val & 0x8U) >> 3U)
+#define GET_ADC_CFG_TCMDRES_VALUE(val) ((((uint32_t)val) & 0x8U) >> 3U)
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */
 
 #if defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI
-#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((val & 0x10U) >> 4U)
+#define GET_ADC_CFG_HPT_EXDI_VALUE(val) ((((uint32_t)val) & 0x10U) >> 4U)
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */
 
 #if defined(LPADC_RSTS)
@@ -161,7 +161,6 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
     (void)CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-
 #if defined(LPADC_RESETS_ARRAY)
     RESET_ReleasePeripheralReset(s_lpadcResets[LPADC_GetInstance(base)]);
 #endif
@@ -220,15 +219,15 @@ void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
     tmp32 |= ADC_CFG_TPRICTRL(GET_ADC_CFG_TPRICTRL_VALUE(config->triggerPriorityPolicy));
 
 #if (defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES)
-    tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE((uint8_t)(config->triggerPriorityPolicy)));
+    tmp32 |= ADC_CFG_TRES(GET_ADC_CFG_TRES_VALUE(config->triggerPriorityPolicy));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TRES) && FSL_FEATURE_LPADC_HAS_CFG_TRES */
 
 #if (defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES)
-    tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE((uint8_t)(config->triggerPriorityPolicy)));
+    tmp32 |= ADC_CFG_TCMDRES(GET_ADC_CFG_TCMDRES_VALUE(config->triggerPriorityPolicy));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_TCMDRES) && FSL_FEATURE_LPADC_HAS_CFG_TCMDRES */
 
 #if (defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI)
-    tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE((uint8_t)(config->triggerPriorityPolicy)));
+    tmp32 |= ADC_CFG_HPT_EXDI(GET_ADC_CFG_HPT_EXDI_VALUE(config->triggerPriorityPolicy));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI) && FSL_FEATURE_LPADC_HAS_CFG_HPT_EXDI */
 
     base->CFG = tmp32;
@@ -342,10 +341,11 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in
 
     uint32_t tmp32 = 0U;
 
-    while (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
+    tmp32 = base->RESFIFO[index];
+
+    if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
     {
-        /* while loop until FIFO is not empty */
-        tmp32 = base->RESFIFO[index];
+        return false; /* FIFO is empty. Discard any read from RESFIFO. */
     }
 
     result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
@@ -355,6 +355,31 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t in
 
     return true;
 }
+/*!
+ * brief Get the result in conversion FIFOn using blocking method.
+ *
+ * param base LPADC peripheral base address.
+ * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * param index Result FIFO index.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index)
+{
+    assert(result != NULL); /* Check if the input pointer is available. */
+
+    uint32_t tmp32 = 0U;
+
+    tmp32 = base->RESFIFO[index];
+
+    while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
+    {
+        tmp32 = base->RESFIFO[index];
+    }
+
+    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+}
 #else
 /*!
  * brief Get the result in conversion FIFO.
@@ -370,10 +395,11 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
 
     uint32_t tmp32 = 0U;
 
-    while (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
+    tmp32 = base->RESFIFO;
+
+    if (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
     {
-        /* while loop until FIFO is not empty */
-        tmp32 = base->RESFIFO;
+        return false; /* FIFO is empty. Discard any read from RESFIFO. */
     }
 
     result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
@@ -383,6 +409,30 @@ bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
 
     return true;
 }
+/*!
+ * @brief Get the result in conversion FIFO using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result)
+{
+    assert(result != NULL); /* Check if the input pointer is available. */
+
+    uint32_t tmp32 = 0U;
+
+    tmp32 = base->RESFIFO;
+
+    while (ADC_RESFIFO_VALID_MASK != (tmp32 & ADC_RESFIFO_VALID_MASK))
+    {
+        tmp32 = base->RESFIFO;
+    }
+
+    result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
+    result->loopCountIndex  = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
+    result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
+    result->convValue       = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
+}
 #endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
 
 /*!
@@ -453,6 +503,9 @@ void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
 /*!
  * brief Configure conversion command.
  *
+ * note The number of compare value register on different chips is different, that is mean in some chips, some
+ * command buffers do not have the compare functionality.
+ *
  * param base LPADC peripheral base address.
  * param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
  * param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
@@ -483,7 +536,6 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
     assert(((config->sampleChannelMode >= kLPADC_SampleChannelDiffBothSideAB) &&
             (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) ||
            (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSideAB));
-    tmp32 |= ADC_CMDL_CHANNEL_MODE(config->sampleChannelMode);
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
 
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
@@ -491,8 +543,7 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
             (((base->VERID) & ADC_VERID_DIFFEN_MASK) != 0U)) ||
            ((config->sampleChannelMode == kLPADC_SampleChannelDualSingleEndBothSide) &&
             (((base->VERID) & ADC_VERID_NUM_SEC_MASK) != 0U)) ||
-           (config->sampleChannelMode < kLPADC_SampleChannelDiffBothSide));
-    tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode);
+           (config->sampleChannelMode < kLPADC_SampleChannelDualSingleEndBothSide));
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
 
@@ -533,13 +584,15 @@ void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_
 
     /* Hardware compare settings.
      * Not all Command Buffers have an associated Compare Value register. The compare function is only available on
-     * Command Buffers that have a corresponding Compare Value register.
+     * Command Buffers that have a corresponding Compare Value register. Therefore, assertion judgment needs to be
+     * made before setting the CV register.
      */
-    if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode)
+
+    if ((kLPADC_HardwareCompareDisabled != config->hardwareCompareMode) && (commandId < ADC_CV_COUNT))
     {
         /* Set CV register. */
-        base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh)   /* Compare value high. */
-                              | ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */
+        base->CV[commandId] = (ADC_CV_CVH(config->hardwareCompareValueHigh)    /* Compare value high. */
+                               | ADC_CV_CVL(config->hardwareCompareValueLow)); /* Compare value low. */
     }
 }
 
@@ -764,8 +817,8 @@ void LPADC_FinishAutoCalibration(ADC_Type *base)
     }
 
 #if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFSMODE
-    GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
-    GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
+    GCCa = (int32_t)(base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
+    GCCb = (int32_t)(base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
     if (0U != ((base->GCC[0]) & 0x8000U))
     {
         GCCa         = GCCa - 0x10000;

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpadc.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPADC_H_
-#define _FSL_LPADC_H_
+#ifndef FSL_LPADC_H_
+#define FSL_LPADC_H_
 
 #include "fsl_common.h"
 
@@ -22,10 +22,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief LPADC driver version 2.7.2. */
-#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 7, 2))
-/*@}*/
+/*! @{ */
+/*! @brief LPADC driver version 2.8.4. */
+#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 8, 4))
+/*! @} */
 
 #if (defined(FSL_FEATURE_LPADC_OFSTRIM_COUNT) && (FSL_FEATURE_LPADC_OFSTRIM_COUNT == 1))
 #define ADC_OFSTRIM_OFSTRIM_MAX  (ADC_OFSTRIM_OFSTRIM_MASK >> ADC_OFSTRIM_OFSTRIM_SHIFT)
@@ -290,8 +290,8 @@ typedef enum _lpadc_sample_channel_mode
     kLPADC_SampleChannelDiffBothSideBA = 0x3U, /*!< Differential mode, the ADC result is (CHnB-CHnA). */
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
 #if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
-    kLPADC_SampleChannelDualSingleEndBothSide = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */
-    kLPADC_SampleChannelDiffBothSide          = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side
+    kLPADC_SampleChannelDiffBothSide          = 0x02U, /*!< Differential mode, the ADC result is (CHnA-CHnB). */
+    kLPADC_SampleChannelDualSingleEndBothSide = 0x03U, /*!< Dual-Single-Ended Mode. Both A side and B side
                                                             channels are converted independently. */
 #endif /* defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
 #endif /* !(defined(FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS) && (FSL_FEATURE_LPADC_HAS_B_SIDE_CHANNELS == 0U)) */
@@ -816,7 +816,7 @@ static inline void LPADC_DoResetConfig(ADC_Type *base)
     base->CTRL &= ~ADC_CTRL_RST_MASK;
 }
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Status
@@ -876,7 +876,7 @@ static inline void LPADC_ClearTriggerStatusFlags(ADC_Type *base, uint32_t mask)
 }
 #endif /* (defined(FSL_FEATURE_LPADC_HAS_TSTAT) && FSL_FEATURE_LPADC_HAS_TSTAT) */
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -976,7 +976,7 @@ static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
     }
 }
 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */
-/* @} */
+/*! @} */
 
 /*!
  * @name Trigger and conversion with FIFO.
@@ -997,15 +997,24 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index)
 }
 
 /*!
- * brief Get the result in conversion FIFOn.
+ * @brief Get the result in conversion FIFOn.
  *
- * param base LPADC peripheral base address.
- * param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
- * param index Result FIFO index.
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * @param index Result FIFO index.
  *
- * return Status whether FIFOn entry is valid.
+ * @return Status whether FIFOn entry is valid.
  */
 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
+
+/*!
+ * @brief Get the result in conversion FIFOn using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
+ * @param index Result FIFO index.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
 #else  /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 1)) */
 /*!
  * @brief Get the count of result kept in conversion FIFO.
@@ -1027,6 +1036,14 @@ static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
  * @return Status whether FIFO entry is valid.
  */
 bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
+
+/*!
+ * @brief Get the result in conversion FIFO using blocking method.
+ *
+ * @param base LPADC peripheral base address.
+ * @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
+ */
+void LPADC_GetConvResultBlocking(ADC_Type *base, lpadc_conv_result_t *result);
 #endif /* (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2)) */
 
 /*!
@@ -1094,6 +1111,9 @@ static inline void LPADC_EnableHardwareTriggerCommandSelection(ADC_Type *base, u
 
 /*!
  * @brief Configure conversion command.
+
+ * @note The number of compare value register on different chips is different, that is mean in some chips, some
+ * command buffers do not have the compare functionality.
  *
  * @param base LPADC peripheral base address.
  * @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
@@ -1186,8 +1206,6 @@ void LPADC_DoAutoCalibration(ADC_Type *base);
  */
 static inline void LPADC_SetOffsetValue(ADC_Type *base, int16_t value)
 {
-    assert((value >= -512) && (value <= 511));
-
     base->OFSTRIM = ADC_OFSTRIM_OFSTRIM(value);
 }
 
@@ -1224,9 +1242,6 @@ static inline void LPADC_GetOffsetValue(ADC_Type *base, int16_t *pValue)
  */
 static inline void LPADC_SetOffsetValue(ADC_Type *base, int32_t valueA, int32_t valueB)
 {
-    assert((valueA >= -16) && (valueA <= 15));
-    assert((valueB >= -16) && (valueB <= 15));
-
     base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB);
 }
 
@@ -1503,7 +1518,7 @@ static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable)
 }
 #endif /* (defined(FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) && FSL_FEATURE_LPADC_HAS_CFG2_JLEFT) */
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -1511,4 +1526,4 @@ static inline void LPADC_EnableJustifiedLeft(ADC_Type *base, bool enable)
 /*!
  * @}
  */
-#endif /* _FSL_LPADC_H_ */
+#endif /* FSL_LPADC_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpcmp.c

@@ -116,15 +116,23 @@ void LPCMP_Init(LPCMP_Type *base, const lpcmp_config_t *config)
 
     /* Configure. */
     LPCMP_Enable(base, false);
+
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
     /* CCR0 register. */
-    if (config->enableStopMode)
+#if defined(FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn)
+    if (1U == FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn(base))
+#endif /* FSL_FEATURE_LPCMP_INSTANCE_SUPPORT_CCR0_CMP_STOP_ENn */
     {
-        base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK;
-    }
-    else
-    {
-        base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK;
+        if (config->enableStopMode)
+        {
+            base->CCR0 |= LPCMP_CCR0_CMP_STOP_EN_MASK;
+        }
+        else
+        {
+            base->CCR0 &= ~LPCMP_CCR0_CMP_STOP_EN_MASK;
+        }
     }
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
 
     /* CCR1 register. */
     tmp32 = (base->CCR1 & (~(LPCMP_CCR1_COUT_PEN_MASK | LPCMP_CCR1_COUT_SEL_MASK | LPCMP_CCR1_COUT_INV_MASK
@@ -202,8 +210,9 @@ void LPCMP_GetDefaultConfig(lpcmp_config_t *config)
 {
     /* Initializes the configure structure to zero. */
     (void)memset(config, 0, sizeof(*config));
-
-    config->enableStopMode      = false;
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
+    config->enableStopMode = false;
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
     config->enableOutputPin     = false;
     config->useUnfilteredOutput = false;
     config->enableInvertOutput  = false;

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpcmp.h

@@ -1,14 +1,14 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2020, 2023 NXP
+ * Copyright 2016-2020, 2023-2024 NXP
  * All rights reserved.
  *
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_LPCMP_H_
-#define _FSL_LPCMP_H_
+#ifndef FSL_LPCMP_H_
+#define FSL_LPCMP_H_
 
 #include "fsl_common.h"
 
@@ -22,8 +22,8 @@
  ******************************************************************************/
 /*! @name Driver version */
 /*! @{ */
-/*! @brief LPCMP driver version 2.1.1. */
-#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*! @brief LPCMP driver version 2.1.3. */
+#define FSL_LPCMP_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
 /*! @} */
 
 #define LPCMP_CCR1_COUTA_CFG_MASK  (LPCMP_CCR1_COUTA_OWEN_MASK | LPCMP_CCR1_COUTA_OW_MASK)
@@ -196,7 +196,10 @@ typedef struct _lpcmp_dac_config
  */
 typedef struct _lpcmp_config
 {
-    bool enableStopMode;      /*!< Decide whether to enable the comparator when in STOP modes. */
+#if !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN)
+    bool enableStopMode; /*!< Decide whether to enable the comparator when in STOP modes. */
+#endif /* !(defined(FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) && FSL_FEATURE_LPCMP_HAS_NO_CCR0_CMP_STOP_EN) */
+
     bool enableOutputPin;     /*!< Decide whether to enable the comparator is available in selected pin. */
     bool useUnfilteredOutput; /*!< Decide whether to use unfiltered output. */
     bool enableInvertOutput;  /*!< Decide whether to inverts the comparator output. */
@@ -235,9 +238,12 @@ typedef struct _lpcmp_roundrobin_config
     uint8_t sampleTimeThreshhold; /*!< Specify that for one channel, when (sampleTimeThreshhold + 1) sample results are
                                        "1",the final result is "1", otherwise the final result is "0", note that the
                                        sampleTimeThreshhold must not be larger than channelSampleNumbers. */
-    lpcmp_roundrobin_clock_source_t roundrobinClockSource;    /*!< Decide which clock source to choose in round robin mode. */
-    lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource;  /*!< Decide which trigger source to choose in round robin mode. */
-    lpcmp_roundrobin_fixedmuxport_t fixedMuxPort;           /*!< Decide which mux port to choose as fixed channel in round robin mode. */
+    lpcmp_roundrobin_clock_source_t roundrobinClockSource;     /*!< Decide which clock source to
+                                                        choose in round robin mode. */
+    lpcmp_roundrobin_trigger_source_t roundrobinTriggerSource; /*!< Decide which trigger source to
+                                                        choose in round robin mode. */
+    lpcmp_roundrobin_fixedmuxport_t fixedMuxPort;              /*!< Decide which mux port to choose as
+                                                        fixed channel in round robin mode. */
     uint8_t fixedChannel;       /*!< Indicate which channel of the fixed mux port is used in round robin mode. */
     uint8_t checkerChannelMask; /*!< Indicate which channel of the non-fixed mux port to check its voltage value in
                                      round robin mode, for example, if checkerChannelMask set to 0x11U means select
@@ -576,4 +582,4 @@ static inline uint8_t LPCMP_GetInputChangedFlags(LPCMP_Type *base)
 
 /*! @} */
 
-#endif /* _FSL_LPCMP_H_ */
+#endif /* FSL_LPCMP_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpi2c.c

@@ -39,7 +39,7 @@
 #define LPI2C_RESETS_ARRAY LPI2C_RSTS
 #endif
 
-/* ! @brief LPI2C master fifo commands. */
+/*! @brief LPI2C master fifo commands. */
 enum
 {
     kTxDataCmd = LPI2C_MTDR_CMD(0x0U), /*!< Transmit DATA[7:0] */
@@ -70,16 +70,16 @@ enum
     kWaitForCompletionState,
 };
 
-/*
- * <! Structure definition for variables that passed as parameters in LPI2C_RunTransferStateMachine.
+/*!
+ * @brief Structure definition for variables that passed as parameters in LPI2C_RunTransferStateMachine.
  * The structure is private.
  */
 typedef struct _lpi2c_state_machine_param
 {
-    bool state_complete;
-    size_t rxCount;
-    size_t txCount;
-    uint32_t status;
+    bool state_complete; /*!< status of complete */
+    size_t rxCount;      /*!< rx count */
+    size_t txCount;      /*!< tx count */
+    uint32_t status;     /*!< machine status */
 } lpi2c_state_machine_param_t;
 
 /*! @brief Typedef for slave interrupt handler. */
@@ -274,16 +274,15 @@ static uint32_t LPI2C_GetCyclesForWidth(
 }
 
 /*!
- * @brief Convert provided flags to status code, and clear any errors if present.
- * @param base The LPI2C peripheral base address.
- * @param status Current status flags value that will be checked.
- * @retval #kStatus_Success
- * @retval #kStatus_LPI2C_PinLowTimeout
- * @retval #kStatus_LPI2C_ArbitrationLost
- * @retval #kStatus_LPI2C_Nak
- * @retval #kStatus_LPI2C_FifoError
+ * brief Convert provided flags to status code, and clear any errors if present.
+ * param base The LPI2C peripheral base address.
+ * param status Current status flags value that will be checked.
+ * retval #kStatus_Success
+ * retval #kStatus_LPI2C_PinLowTimeout
+ * retval #kStatus_LPI2C_ArbitrationLost
+ * retval #kStatus_LPI2C_Nak
+ * retval #kStatus_LPI2C_FifoError
  */
-/* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
 {
     status_t result = kStatus_Success;
@@ -323,8 +322,16 @@ status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status)
         /* Clear the flags. */
         LPI2C_MasterClearStatusFlags(base, status);
 
-        /* Reset fifos. These flags clear automatically. */
-        base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
+        if (((base->MCFGR1 & LPI2C_MCFGR1_IGNACK_MASK) != 0x00U) && (result == kStatus_LPI2C_Nak))
+        {
+            /* ERR051119: If IGNACK was set and nak detect , we will ignore the Nak status */
+            result = kStatus_Success;
+        }
+        else
+        {
+            /* Reset fifos. These flags clear automatically.*/
+            base->MCR |= LPI2C_MCR_RRF_MASK | LPI2C_MCR_RTF_MASK;
+        }
     }
     else
     {
@@ -382,13 +389,13 @@ static status_t LPI2C_MasterWaitForTxReady(LPI2C_Type *base)
 }
 
 /*!
- * @brief Make sure the bus isn't already busy.
+ * brief Make sure the bus isn't already busy.
  *
  * A busy bus is allowed if we are the one driving it.
  *
- * @param base The LPI2C peripheral base address.
- * @retval #kStatus_Success
- * @retval #kStatus_LPI2C_Busy
+ * param base The LPI2C peripheral base address.
+ * retval #kStatus_Success
+ * retval #kStatus_LPI2C_Busy
  */
 /* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_CheckForBusyBus(LPI2C_Type *base)
@@ -547,7 +554,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
         /* Calculate bus idle timeout value. The value is equal to BUSIDLE cycles of functional clock divided by
            prescaler. And set BUSIDLE to 0 disables the fileter, so the min value is 1. */
         cycles       = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->busIdleTimeout_ns, 1U,
-                                         (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
+                                               (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
         base->MCFGR2 = (base->MCFGR2 & (~LPI2C_MCFGR2_BUSIDLE_MASK)) | LPI2C_MCFGR2_BUSIDLE(cycles);
     }
     if (0U != masterConfig->pinLowTimeout_ns)
@@ -555,7 +562,7 @@ void LPI2C_MasterInit(LPI2C_Type *base, const lpi2c_master_config_t *masterConfi
         /* Calculate bus pin low timeout value. The value is equal to PINLOW cycles of functional clock divided by
            prescaler. And set PINLOW to 0 disables the fileter, so the min value is 1. */
         cycles       = LPI2C_GetCyclesForWidth(sourceClock_Hz, masterConfig->pinLowTimeout_ns / 256U, 1U,
-                                         (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
+                                               (LPI2C_MCFGR2_BUSIDLE_MASK >> LPI2C_MCFGR2_BUSIDLE_SHIFT), prescaler);
         base->MCFGR3 = (base->MCFGR3 & ~LPI2C_MCFGR3_PINLOW_MASK) | LPI2C_MCFGR3_PINLOW(cycles);
     }
 
@@ -1115,6 +1122,15 @@ status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t
                 }
             }
         }
+
+        /* Transmit fail */
+        if (kStatus_Success != result)
+        {
+            if ((transfer->flags & (uint32_t)kLPI2C_TransferNoStopFlag) == 0U)
+            {
+                (void)LPI2C_MasterStop(base);
+            }
+        }
     }
 
     return result;
@@ -1665,8 +1681,6 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h
  *
  * param base The LPI2C peripheral base address.
  * param handle Pointer to the LPI2C master driver handle.
- * retval #kStatus_Success A transaction was successfully aborted.
- * retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress.
  */
 void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle)
 {
@@ -2296,8 +2310,6 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han
  * note This API could be called at any time to stop slave for handling the bus events.
  * param base The LPI2C peripheral base address.
  * param handle Pointer to #lpi2c_slave_handle_t structure which stores the transfer state.
- * retval #kStatus_Success
- * retval #kStatus_LPI2C_Idle
  */
 void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle)
 {
@@ -2355,9 +2367,9 @@ void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle
             if (0U !=
                 (flags & (((uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag) | ((uint32_t)kLPI2C_SlaveStopDetectFlag))))
             {
-                xfer->event = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ?
-                                  kLPI2C_SlaveRepeatedStartEvent :
-                                  kLPI2C_SlaveCompletionEvent;
+                xfer->event            = (0U != (flags & (uint32_t)kLPI2C_SlaveRepeatedStartDetectFlag)) ?
+                                             kLPI2C_SlaveRepeatedStartEvent :
+                                             kLPI2C_SlaveCompletionEvent;
                 xfer->receivedAddress  = 0U;
                 xfer->completionStatus = kStatus_Success;
                 xfer->transferredCount = handle->transferredCount;
@@ -2567,6 +2579,24 @@ void LPI2C6_DriverIRQHandler(void)
 }
 #endif
 
+#if defined(LPI2C7)
+/* Implementation of LPI2C7 handler named in startup code. */
+void LPI2C7_DriverIRQHandler(void);
+void LPI2C7_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(LPI2C7, 7U);
+}
+#endif
+
+#if defined(LPI2C8)
+/* Implementation of LPI2C8 handler named in startup code. */
+void LPI2C8_DriverIRQHandler(void);
+void LPI2C8_DriverIRQHandler(void)
+{
+    LPI2C_CommonIRQHandler(LPI2C8, 8U);
+}
+#endif
+
 #if defined(CM4_0__LPI2C)
 /* Implementation of CM4_0__LPI2C handler named in startup code. */
 void M4_0_LPI2C_DriverIRQHandler(void);

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpi2c.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPI2C_H_
-#define _FSL_LPI2C_H_
+#ifndef FSL_LPI2C_H_
+#define FSL_LPI2C_H_
 
 #include <stddef.h>
 #include "fsl_device_registers.h"
@@ -21,11 +21,13 @@
  * @{
  */
 
-/*! @name Driver version */
-/*@{*/
+/*!
+ * @name Driver version
+ * @{
+ */
 /*! @brief LPI2C driver version. */
-#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
-/*@}*/
+#define FSL_LPI2C_DRIVER_VERSION (MAKE_VERSION(2, 5, 4))
+/*! @} */
 
 /*! @brief Retry times for waiting flag. */
 #ifndef I2C_RETRY_TIMES
@@ -49,8 +51,6 @@ enum
     kStatus_LPI2C_Timeout        = MAKE_STATUS(kStatusGroup_LPI2C, 9), /*!< Timeout polling status flags. */
 };
 
-/*! @} */
-
 /*!
  * @addtogroup lpi2c_master_driver
  * @{
@@ -192,7 +192,9 @@ typedef struct _lpi2c_match_config
 } lpi2c_data_match_config_t;
 
 /* Forward declaration of the transfer descriptor and handle typedefs. */
+/*! @brief LPI2C master descriptor of the transfer. */
 typedef struct _lpi2c_master_transfer lpi2c_master_transfer_t;
+/*! @brief LPI2C master handle of the transfer. */
 typedef struct _lpi2c_master_handle lpi2c_master_handle_t;
 
 /*!
@@ -202,6 +204,7 @@ typedef struct _lpi2c_master_handle lpi2c_master_handle_t;
  * in the call to LPI2C_MasterTransferCreateHandle().
  *
  * @param base The LPI2C peripheral base address.
+ * @param handle Pointer to the LPI2C master driver handle.
  * @param completionStatus Either kStatus_Success or an error code describing how the transfer completed.
  * @param userData Arbitrary pointer-sized value passed from the application.
  */
@@ -347,7 +350,7 @@ typedef struct _lpi2c_slave_config
         bool enableRx;      /*!< Enables SCL clock stretching when receive data flag is set during
                                          a slave-receive transfer. */
         bool enableAddress; /*!< Enables SCL clock stretching when the address valid flag is asserted. */
-    } sclStall;
+    } sclStall;                       /*!< SCL stall enable options. */
     bool ignoreAck;                   /*!< Continue transfers after a NACK is detected. */
     bool enableReceivedAddressRead;   /*!< Enable reading the address received address as the first byte of data. */
     uint32_t sdaGlitchFilterWidth_ns; /*!< Width in nanoseconds of the digital filter on the SDA signal. Set to 0 to
@@ -397,6 +400,7 @@ typedef struct _lpi2c_slave_transfer
 } lpi2c_slave_transfer_t;
 
 /* Forward declaration. */
+/*! @brief LPI2C slave handle structure. */
 typedef struct _lpi2c_slave_handle lpi2c_slave_handle_t;
 
 /*!
@@ -467,8 +471,10 @@ uint32_t LPI2C_GetInstance(LPI2C_Type *base);
  * @{
  */
 
-/*! @name Initialization and deinitialization */
-/*@{*/
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
 
 /*!
  * @brief Provides a default configuration for the LPI2C master peripheral.
@@ -529,9 +535,28 @@ void LPI2C_MasterDeinit(LPI2C_Type *base);
  */
 void LPI2C_MasterConfigureDataMatch(LPI2C_Type *base, const lpi2c_data_match_config_t *matchConfig);
 
+/*!
+ * @brief Convert provided flags to status code, and clear any errors if present.
+ * @param base The LPI2C peripheral base address.
+ * @param status Current status flags value that will be checked.
+ * @retval #kStatus_Success
+ * @retval #kStatus_LPI2C_PinLowTimeout
+ * @retval #kStatus_LPI2C_ArbitrationLost
+ * @retval #kStatus_LPI2C_Nak
+ * @retval #kStatus_LPI2C_FifoError
+ */
 /* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_MasterCheckAndClearError(LPI2C_Type *base, uint32_t status);
 
+/*!
+ * @brief Make sure the bus isn't already busy.
+ *
+ * A busy bus is allowed if we are the one driving it.
+ *
+ * @param base The LPI2C peripheral base address.
+ * @retval #kStatus_Success
+ * @retval #kStatus_LPI2C_Busy
+ */
 /* Not static so it can be used from fsl_lpi2c_edma.c. */
 status_t LPI2C_CheckForBusyBus(LPI2C_Type *base);
 
@@ -559,10 +584,12 @@ static inline void LPI2C_MasterEnable(LPI2C_Type *base, bool enable)
     base->MCR = (base->MCR & ~LPI2C_MCR_MEN_MASK) | LPI2C_MCR_MEN(enable);
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name Status */
-/*@{*/
+/*!
+ * @name Status
+ * @{
+ */
 
 /*!
  * @brief Gets the LPI2C master status flags.
@@ -606,10 +633,12 @@ static inline void LPI2C_MasterClearStatusFlags(LPI2C_Type *base, uint32_t statu
     base->MSR = statusMask;
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name Interrupts */
-/*@{*/
+/*!
+ * @name Interrupts
+ * @{
+ */
 
 /*!
  * @brief Enables the LPI2C master interrupt requests.
@@ -653,10 +682,12 @@ static inline uint32_t LPI2C_MasterGetEnabledInterrupts(LPI2C_Type *base)
     return base->MIER;
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name DMA control */
-/*@{*/
+/*!
+ * @name DMA control
+ * @{
+ */
 
 /*!
  * @brief Enables or disables LPI2C master DMA requests.
@@ -692,10 +723,12 @@ static inline uint32_t LPI2C_MasterGetRxFifoAddress(LPI2C_Type *base)
     return (uint32_t)(uintptr_t)&base->MRDR;
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name FIFO control */
-/*@{*/
+/*!
+ * @name FIFO control
+ * @{
+ */
 
 /*!
  * @brief Sets the watermarks for LPI2C master FIFOs.
@@ -734,10 +767,12 @@ static inline void LPI2C_MasterGetFifoCounts(LPI2C_Type *base, size_t *rxCount,
     }
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name Bus operations */
-/*@{*/
+/*!
+ * @name Bus operations
+ * @{
+ */
 
 /*!
  * @brief Sets the I2C bus frequency for master transactions.
@@ -873,10 +908,12 @@ status_t LPI2C_MasterStop(LPI2C_Type *base);
  */
 status_t LPI2C_MasterTransferBlocking(LPI2C_Type *base, lpi2c_master_transfer_t *transfer);
 
-/*@}*/
+/*! @}*/
 
-/*! @name Non-blocking */
-/*@{*/
+/*!
+ * @name Non-blocking
+ * @{
+ */
 
 /*!
  * @brief Creates a new handle for the LPI2C master non-blocking APIs.
@@ -932,15 +969,15 @@ status_t LPI2C_MasterTransferGetCount(LPI2C_Type *base, lpi2c_master_handle_t *h
  *
  * @param base The LPI2C peripheral base address.
  * @param handle Pointer to the LPI2C master driver handle.
- * @retval kStatus_Success A transaction was successfully aborted.
- * @retval #kStatus_LPI2C_Idle There is not a non-blocking transaction currently in progress.
  */
 void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle);
 
-/*@}*/
+/*! @}*/
 
-/*! @name IRQ handler */
-/*@{*/
+/*!
+ * @name IRQ handler 
+ * @{
+ */
 
 /*!
  * @brief Reusable routine to handle master interrupts.
@@ -951,7 +988,7 @@ void LPI2C_MasterTransferAbort(LPI2C_Type *base, lpi2c_master_handle_t *handle);
  */
 void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle);
 
-/*@}*/
+/*! @}*/
 
 /*! @} */
 
@@ -960,8 +997,10 @@ void LPI2C_MasterTransferHandleIRQ(LPI2C_Type *base, void *lpi2cMasterHandle);
  * @{
  */
 
-/*! @name Slave initialization and deinitialization */
-/*@{*/
+/*!
+ * @name Slave initialization and deinitialization
+ * @{
+ */
 
 /*!
  * @brief Provides a default configuration for the LPI2C slave peripheral.
@@ -1042,10 +1081,12 @@ static inline void LPI2C_SlaveEnable(LPI2C_Type *base, bool enable)
     base->SCR = (base->SCR & ~LPI2C_SCR_SEN_MASK) | LPI2C_SCR_SEN(enable);
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name Slave status */
-/*@{*/
+/*!
+ * @name Slave status 
+ * @{
+ */
 
 /*!
  * @brief Gets the LPI2C slave status flags.
@@ -1085,11 +1126,12 @@ static inline void LPI2C_SlaveClearStatusFlags(LPI2C_Type *base, uint32_t status
 {
     base->SSR = statusMask;
 }
+/*! @}*/
 
-/*@}*/
-
-/*! @name Slave interrupts */
-/*@{*/
+/*!
+ * @name Slave interrupts 
+ * @{
+ */
 
 /*!
  * @brief Enables the LPI2C slave interrupt requests.
@@ -1132,10 +1174,12 @@ static inline uint32_t LPI2C_SlaveGetEnabledInterrupts(LPI2C_Type *base)
     return base->SIER;
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name Slave DMA control */
-/*@{*/
+/*!
+ * @name Slave DMA control
+ * @{
+ */
 
 /*!
  * @brief Enables or disables the LPI2C slave peripheral DMA requests.
@@ -1152,10 +1196,12 @@ static inline void LPI2C_SlaveEnableDMA(LPI2C_Type *base, bool enableAddressVali
                  LPI2C_SDER_AVDE(enableAddressValid) | LPI2C_SDER_RDDE(enableRx) | LPI2C_SDER_TDDE(enableTx);
 }
 
-/*@}*/
+/*! @}*/
 
-/*! @name Slave bus operations */
-/*@{*/
+/*!
+ * @name Slave bus operations
+ * @{
+ */
 
 /*!
  * @brief Returns whether the bus is idle.
@@ -1243,10 +1289,12 @@ status_t LPI2C_SlaveSend(LPI2C_Type *base, void *txBuff, size_t txSize, size_t *
  */
 status_t LPI2C_SlaveReceive(LPI2C_Type *base, void *rxBuff, size_t rxSize, size_t *actualRxSize);
 
-/*@}*/
+/*! @}*/
 
-/*! @name Slave non-blocking */
-/*@{*/
+/*!
+ * @name Slave non-blocking
+ * @{
+ */
 
 /*!
  * @brief Creates a new handle for the LPI2C slave non-blocking APIs.
@@ -1311,15 +1359,15 @@ status_t LPI2C_SlaveTransferGetCount(LPI2C_Type *base, lpi2c_slave_handle_t *han
  * @note This API could be called at any time to stop slave for handling the bus events.
  * @param base The LPI2C peripheral base address.
  * @param handle Pointer to lpi2c_slave_handle_t structure which stores the transfer state.
- * @retval kStatus_Success
- * @retval #kStatus_LPI2C_Idle
  */
 void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle);
 
-/*@}*/
+/*! @}*/
 
-/*! @name Slave IRQ handler */
-/*@{*/
+/*!
+ * @name Slave IRQ handler
+ * @{
+ */
 
 /*!
  * @brief Reusable routine to handle slave interrupts.
@@ -1330,12 +1378,12 @@ void LPI2C_SlaveTransferAbort(LPI2C_Type *base, lpi2c_slave_handle_t *handle);
  */
 void LPI2C_SlaveTransferHandleIRQ(LPI2C_Type *base, lpi2c_slave_handle_t *handle);
 
-/*@}*/
+/*! @}*/
 
 /*! @} */
 
 #if defined(__cplusplus)
 }
 #endif
-
-#endif /* _FSL_LPI2C_H_ */
+/*! @} */
+#endif /* FSL_LPI2C_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpi2c_edma.c

@@ -30,8 +30,8 @@
 #define FSL_COMPONENT_ID "platform.drivers.lpi2c_edma"
 #endif
 
-/* @brief Mask to align an address to 32 bytes. */
-#define ALIGN_32_MASK (0x1fU)
+/* @brief Mask to align an address to edma_tcd_t size. */
+#define ALIGN_TCD_SIZE_MASK (sizeof(edma_tcd_t) - 1U)
 
 /* ! @brief LPI2C master fifo commands. */
 enum _lpi2c_master_fifo_cmd
@@ -313,7 +313,7 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
     }
 
     /* Get a 32-byte aligned TCD pointer. */
-    edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_32_MASK));
+    edma_tcd_t *tcd = (edma_tcd_t *)((uint32_t)(&handle->tcds[1]) & (~ALIGN_TCD_SIZE_MASK));
 
     bool hasSendData    = (transfer->direction == kLPI2C_Write) && (transfer->dataSize != 0U);
     bool hasReceiveData = (transfer->direction == kLPI2C_Read) && (transfer->dataSize != 0U);
@@ -339,10 +339,17 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
 
         if (commandCount != 0U)
         {
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            /* Create a software TCD, which will be chained after the commands. */
+            EDMA_TcdResetExt(handle->tx->base, tcd);
+            EDMA_TcdSetTransferConfigExt(handle->tx->base, tcd, &transferConfig, NULL);
+            EDMA_TcdEnableInterruptsExt(handle->tx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#else
             /* Create a software TCD, which will be chained after the commands. */
             EDMA_TcdReset(tcd);
             EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
             EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#endif
             linkTcd = tcd;
         }
         else
@@ -380,9 +387,15 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
                enabling rx dma and disabling tx dma, which will be chained onto the commands transfer,
                and create another software TCD of transfering data and chain it onto the last TCD.
                Notice that in this situation assume tx/rx uses same channel */
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->rx->base, tcd);
+            EDMA_TcdSetTransferConfigExt(handle->rx->base, tcd, &transferConfig, NULL);
+            EDMA_TcdEnableInterruptsExt(handle->rx->base, tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#else
             EDMA_TcdReset(tcd);
             EDMA_TcdSetTransferConfig(tcd, &transferConfig, NULL);
             EDMA_TcdEnableInterrupts(tcd, (uint32_t)kEDMA_MajorInterruptEnable);
+#endif
 
             transferConfig.srcAddr          = (uint32_t)&lpi2c_edma_RecSetting;
             transferConfig.destAddr         = (uint32_t) & (base->MDER);
@@ -393,10 +406,14 @@ status_t LPI2C_MasterTransferEDMA(LPI2C_Type *base,
             transferConfig.minorLoopBytes   = sizeof(uint8_t);
             transferConfig.majorLoopCounts  = 1;
 
-            edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_32_MASK));
-
+            edma_tcd_t *tcdSetRxClearTxDMA = (edma_tcd_t *)((uint32_t)(&handle->tcds[2]) & (~ALIGN_TCD_SIZE_MASK));
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->rx->base, tcdSetRxClearTxDMA);
+            EDMA_TcdSetTransferConfigExt(handle->rx->base, tcdSetRxClearTxDMA, &transferConfig, tcd);
+#else
             EDMA_TcdReset(tcdSetRxClearTxDMA);
             EDMA_TcdSetTransferConfig(tcdSetRxClearTxDMA, &transferConfig, tcd);
+#endif
             linkTcd = tcdSetRxClearTxDMA;
         }
     }

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpi2c_edma.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPI2C_EDMA_H_
-#define _FSL_LPI2C_EDMA_H_
+#ifndef FSL_LPI2C_EDMA_H_
+#define FSL_LPI2C_EDMA_H_
 
 #include "fsl_lpi2c.h"
 #include "fsl_edma.h"
@@ -15,11 +15,13 @@
  * Definitions
  ******************************************************************************/
 
-/*! @name Driver version */
-/*@{*/
+/*!
+ * @name Driver version
+ * @{
+ */
 /*! @brief LPI2C EDMA driver version. */
-#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+#define FSL_LPI2C_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 2))
+/*! @} */
 
 /*!
  * @addtogroup lpi2c_master_edma_driver
@@ -27,6 +29,7 @@
  */
 
 /* Forward declaration of the transfer descriptor and handle typedefs. */
+/*! @brief LPI2C master EDMA handle of the transfer. */
 typedef struct _lpi2c_master_edma_handle lpi2c_master_edma_handle_t;
 
 /*!
@@ -79,8 +82,10 @@ extern "C" {
  * @{
  */
 
-/*! @name Master DMA */
-/*@{*/
+/*!
+ * @name Master DMA
+ * @{
+ */
 
 /*!
  * @brief Create a new handle for the LPI2C master DMA APIs.
@@ -147,7 +152,7 @@ status_t LPI2C_MasterTransferGetCountEDMA(LPI2C_Type *base, lpi2c_master_edma_ha
  */
 status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handle_t *handle);
 
-/*@}*/
+/*! @} */
 
 /*! @} */
 
@@ -155,4 +160,4 @@ status_t LPI2C_MasterTransferAbortEDMA(LPI2C_Type *base, lpi2c_master_edma_handl
 }
 #endif
 
-#endif /* _FSL_LPI2C_EDMA_H_ */
+#endif /* FSL_LPI2C_EDMA_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpspi.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2022, 2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -59,7 +59,7 @@ typedef struct _lpspi_transfer_blocking_param
     bool isPcsContinuous;
     uint8_t bytesEachWrite;
     uint8_t bytesEachRead;    
-    uint8_t *txData;
+    const uint8_t *txData;
     uint8_t *rxData;
     uint32_t rxRemainingByteCount;
 } lpspi_transfer_blocking_param_t;
@@ -94,7 +94,7 @@ static void LPSPI_SetOnePcsPolarity(LPSPI_Type *base,
  * @brief Combine the write data for 1 byte to 4 bytes.
  * This is not a public API.
  */
-static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap);
+static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap);
 
 /*!
  * @brief Separate the read data for 1 byte to 4 bytes.
@@ -294,9 +294,17 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
 
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
-#if defined(ZQ_RESETS_ARRAY)
+#if defined(LPSPI_RESETS_ARRAY)
     RESET_ReleasePeripheralReset(s_lpspiResets[LPSPI_GetInstance(base)]);
 #endif
+    /* if register exist,software manual reset the register to default and clear FIFO */
+    base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
+    base->IER = 0U;
+    base->CR  = 0U;
+    
+    /* Disable LPSPI first */
+    LPSPI_Enable(base, false);
+
     /* Set LPSPI to master */
     LPSPI_SetMasterSlaveMode(base, kLPSPI_Master);
 
@@ -307,7 +315,11 @@ void LPSPI_MasterInit(LPSPI_Type *base, const lpspi_master_config_t *masterConfi
     base->CFGR1 = (base->CFGR1 & ~(LPSPI_CFGR1_OUTCFG_MASK | LPSPI_CFGR1_PINCFG_MASK | LPSPI_CFGR1_NOSTALL_MASK |
                                    LPSPI_CFGR1_SAMPLE_MASK)) |
                   LPSPI_CFGR1_OUTCFG(masterConfig->dataOutConfig) | LPSPI_CFGR1_PINCFG(masterConfig->pinCfg) |
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+                  LPSPI_CFGR1_PCSCFG(masterConfig->pcsFunc) |
+#endif
                   LPSPI_CFGR1_NOSTALL(0) | LPSPI_CFGR1_SAMPLE((uint32_t)masterConfig->enableInputDelay);
+
     if ((masterConfig->pinCfg == kLPSPI_SdiInSdiOut) || (masterConfig->pinCfg == kLPSPI_SdoInSdoOut))
     {
         base->CFGR1 |= LPSPI_CFGR1_OUTCFG_MASK;
@@ -358,6 +370,9 @@ void LPSPI_MasterGetDefaultConfig(lpspi_master_config_t *masterConfig)
     masterConfig->cpol         = kLPSPI_ClockPolarityActiveHigh;
     masterConfig->cpha         = kLPSPI_ClockPhaseFirstEdge;
     masterConfig->direction    = kLPSPI_MsbFirst;
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+    masterConfig->pcsFunc            = kLPSPI_PcsAsCs; 
+#endif
 
     masterConfig->pcsToSckDelayInNanoSec        = (1000000000U / masterConfig->baudRate) / 2U;
     masterConfig->lastSckToPcsDelayInNanoSec    = (1000000000U / masterConfig->baudRate) / 2U;
@@ -953,7 +968,7 @@ static bool LPSPI_MasterTransferWriteAllTxData(LPSPI_Type *base,
         /*Wait until TX FIFO is not full*/
 #if SPI_RETRY_TIMES
         uint32_t waitTimes = SPI_RETRY_TIMES;
-        while (LPSPI_GetTxFifoCount(base) == fifo_size) && ((--waitTimes) != 0U))
+        while ((LPSPI_GetTxFifoCount(base) == fifo_size) && ((--waitTimes) != 0U))
 #else
         while (LPSPI_GetTxFifoCount(base) == fifo_size)
 #endif
@@ -1179,6 +1194,9 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
 
     /* Variables */
     uint32_t whichPcs = (transfer->configFlags & LPSPI_MASTER_PCS_MASK) >> LPSPI_MASTER_PCS_SHIFT;
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+    uint32_t width    = (transfer->configFlags & LPSPI_MASTER_WIDTH_MASK) >> LPSPI_MASTER_WIDTH_SHIFT;
+#endif
     uint32_t temp     = (base->CFGR1 & LPSPI_CFGR1_PINCFG_MASK);
     lpspi_transfer_blocking_param_t stateParams;
     (void)memset(&stateParams, 0, sizeof(stateParams));
@@ -1206,8 +1224,10 @@ status_t LPSPI_MasterTransferBlocking(LPSPI_Type *base, lpspi_transfer_t *transf
     /* Configure transfer control register. */
     base->TCR = (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_RXMSK_MASK |
                                LPSPI_TCR_TXMSK_MASK | LPSPI_TCR_PCS_MASK)) |
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+                LPSPI_TCR_WIDTH(width) |
+#endif
                 LPSPI_TCR_PCS(whichPcs);
-
     /*TCR is also shared the FIFO, so wait for TCR written.*/
     /*
      * $Branch Coverage Justification$
@@ -1337,6 +1357,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
 
     /* Variables */
     bool isRxMask = false;
+    handle->isTxMask = false;
     uint8_t txWatermark;
     uint8_t dummyData = g_lpspiDummyData[LPSPI_GetInstance(base)];
     uint32_t tmpTimes;
@@ -1457,7 +1478,7 @@ status_t LPSPI_MasterTransferNonBlocking(LPSPI_Type *base, lpspi_master_handle_t
         handle->txRemainingByteCount -= (uint32_t)handle->bytesPerFrame;
         if (!LPSPI_WaitTxFifoEmpty(base))
         {
-            return false;
+            return kStatus_LPSPI_Timeout;
         }
     }
     else
@@ -2214,6 +2235,8 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle
             handle->state = (uint8_t)kLPSPI_Error;
         }
         handle->errorCount++;
+        /* ERR051588: Clear FIFO after underrun occurs */   
+        LPSPI_FlushFifo(base, true, false);
     }
     /* Catch rx fifo overflow conditions, service only if rx over flow interrupt enabled */
     /*
@@ -2237,7 +2260,7 @@ void LPSPI_SlaveTransferHandleIRQ(LPSPI_Type *base, lpspi_slave_handle_t *handle
     }
 }
 
-static uint32_t LPSPI_CombineWriteData(uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap)
+static uint32_t LPSPI_CombineWriteData(const uint8_t *txData, uint8_t bytesEachWrite, bool isByteSwap)
 {
     assert(txData != NULL);
 
@@ -2501,6 +2524,15 @@ void LPSPI5_DriverIRQHandler(void)
 }
 #endif
 
+#if defined(LPSPI6)
+void LPSPI6_DriverIRQHandler(void);
+void LPSPI6_DriverIRQHandler(void)
+{
+    assert(s_lpspiHandle[6] != NULL);
+    LPSPI_CommonIRQHandler(LPSPI6, s_lpspiHandle[6]);
+}
+#endif
+
 #if defined(DMA__LPSPI0)
 void DMA_SPI0_INT_DriverIRQHandler(void);
 void DMA_SPI0_INT_DriverIRQHandler(void)

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpspi.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2023, 2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPSPI_H_
-#define _FSL_LPSPI_H_
+#ifndef FSL_LPSPI_H_
+#define FSL_LPSPI_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  *********************************************************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPSPI driver version. */
-#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
-/*@}*/
+#define FSL_LPSPI_DRIVER_VERSION (MAKE_VERSION(2, 6, 8))
+/*! @} */
 
 #ifndef LPSPI_DUMMY_DATA
 /*! @brief LPSPI dummy data if no Tx data.*/
@@ -179,6 +179,15 @@ typedef enum _lpspi_data_out_config
     kLpspiDataOutTristate = 1U  /*!< Data out is tristated when chip select is de-asserted */
 } lpspi_data_out_config_t;
 
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+/*! @brief LPSPI cs function configuration. */
+typedef enum _lpspi_pcs_function_config
+{
+    kLPSPI_PcsAsCs = 0U,        /*!< PCS pin select as cs function */
+    kLPSPI_PcsAsData = 1U,      /*!< PCS pin select as date function */
+} lpspi_pcs_function_config_t;
+#endif
+
 /*! @brief LPSPI transfer width configuration. */
 typedef enum _lpspi_transfer_width
 {
@@ -197,6 +206,10 @@ typedef enum _lpspi_delay_type
 
 #define LPSPI_MASTER_PCS_SHIFT (4U)    /*!< LPSPI master PCS shift macro , internal used. */
 #define LPSPI_MASTER_PCS_MASK  (0xF0U) /*!< LPSPI master PCS shift macro , internal used. */
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+#define LPSPI_MASTER_WIDTH_SHIFT (16U)      /*!< LPSPI master width shift macro, internal used */
+#define LPSPI_MASTER_WIDTH_MASK  (0x30000U) /*!< LPSPI master width shift mask, internal used */
+#endif
 
 /*! @brief Use this enumeration for LPSPI master transfer configFlags. */
 enum _lpspi_transfer_config_flag_for_master
@@ -205,6 +218,11 @@ enum _lpspi_transfer_config_flag_for_master
     kLPSPI_MasterPcs1 = 1U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS1 signal */
     kLPSPI_MasterPcs2 = 2U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS2 signal */
     kLPSPI_MasterPcs3 = 3U << LPSPI_MASTER_PCS_SHIFT, /*!< LPSPI master transfer use PCS3 signal */
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH) && FSL_FEATURE_LPSPI_HAS_NO_MULTI_WIDTH)
+    kLPSPI_MasterWidth1 = 0U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 1bit */
+    kLPSPI_MasterWidth2 = 1U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 2bit */
+    kLPSPI_MasterWidth4 = 2U << LPSPI_MASTER_WIDTH_SHIFT, /*!< LPSPI master transfer 4bit */
+#endif
 
     kLPSPI_MasterPcsContinuous = 1U << 20, /*!< Is PCS signal continuous */
 
@@ -278,7 +296,10 @@ typedef struct _lpspi_master_config
 
     lpspi_pin_config_t pinCfg; /*!< Configures which pins are used for input and output data
                                 *during single bit transfers.*/
-
+    
+#if !(defined(FSL_FEATURE_LPSPI_HAS_NO_PCSCFG) && FSL_FEATURE_LPSPI_HAS_NO_PCSCFG)
+    lpspi_pcs_function_config_t pcsFunc; /*!< Configures cs pins function.*/
+#endif
     lpspi_data_out_config_t dataOutConfig; /*!< Configures if the output data is tristated
                                             * between accesses (LPSPI_PCS is negated). */
     bool enableInputDelay; /*!< Enable master to sample the input data on a delayed SCK. This can help improve slave
@@ -342,7 +363,7 @@ typedef void (*lpspi_slave_transfer_callback_t)(LPSPI_Type *base,
 /*! @brief LPSPI master/slave transfer structure.*/
 typedef struct _lpspi_transfer
 {
-    uint8_t *txData;          /*!< Send buffer. */
+    const uint8_t *txData;    /*!< Send buffer. */
     uint8_t *rxData;          /*!< Receive buffer. */
     volatile size_t dataSize; /*!< Transfer bytes. */
 
@@ -368,7 +389,7 @@ struct _lpspi_master_handle
     volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
     volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
-    uint8_t *volatile txData;             /*!< Send buffer. */
+    const uint8_t *volatile txData;            /*!< Send buffer. */
     uint8_t *volatile rxData;             /*!< Receive buffer. */
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
     volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
@@ -398,7 +419,7 @@ struct _lpspi_slave_handle
     volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
     volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
 
-    uint8_t *volatile txData; /*!< Send buffer. */
+    const uint8_t *volatile txData;           /*!< Send buffer. */
     uint8_t *volatile rxData; /*!< Receive buffer. */
 
     volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
@@ -514,6 +535,7 @@ static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
     {
         base->CR &= ~LPSPI_CR_MEN_MASK;
     }
+#if defined(FSL_FEATURE_LPSPI_HAS_ERRATA_051472) && FSL_FEATURE_LPSPI_HAS_ERRATA_051472
     /* ERRATA051472: The SR[REF] would assert if software disables the LPSPI module 
        after receiving some data and then enabled the LPSPI again without performing a software reset.
        Clear SR[REF] flag after LPSPI module enabled*/
@@ -521,6 +543,7 @@ static inline void LPSPI_Enable(LPSPI_Type *base, bool enable)
     {
         base->SR = (uint32_t)kLPSPI_ReceiveErrorFlag;
     }
+#endif
 }
 
 /*!
@@ -1205,4 +1228,4 @@ bool LPSPI_WaitTxFifoEmpty(LPSPI_Type *base);
 
 /*! @}*/
 
-#endif /*_FSL_LPSPI_H_*/
+#endif /*FSL_LPSPI_H_*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpspi_edma.c

@@ -176,8 +176,9 @@ void LPSPI_MasterTransferCreateHandleEDMA(LPSPI_Type *base,
     s_lpspiMasterEdmaPrivateHandle[instance].base   = base;
     s_lpspiMasterEdmaPrivateHandle[instance].handle = handle;
 
-    handle->callback = callback;
-    handle->userData = userData;
+    handle->callback           = callback;
+    handle->userData           = userData;
+    handle->dataBytesEveryTime = DMA_MAX_TRANSFER_COUNT;
 
     handle->edmaRxRegToRxDataHandle = edmaRxRegToRxDataHandle;
     handle->edmaTxDataToTxRegHandle = edmaTxDataToTxRegHandle;
@@ -195,7 +196,7 @@ static void LPSPI_PrepareTransferEDMA(LPSPI_Type *base)
 /*!
  * brief LPSPI master config transfer parameter using eDMA.
  *
- * This function is preparing to transfers data using eDMA. 
+ * This function is preparing to transfer data using eDMA.
  *
  * param base LPSPI peripheral base address.
  * param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
@@ -272,7 +273,7 @@ status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma
  * is transferred, the callback function is called.
  *
  * Note:
- * This API is only for transfer through DMA without configuration. 
+ * This API is only for transfer through DMA without configuration.
  * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once.
  * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
  * For bytesPerFrame greater than 4:
@@ -305,9 +306,10 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
     }
 
     /* Variables */
-    bool isThereExtraTxBytes = false;
-    uint8_t bytesLastWrite   = 0;
-    uint32_t instance        = LPSPI_GetInstance(base);
+    uint32_t firstTimeDataSize = 0;
+    bool isThereExtraTxBytes   = false;
+    uint8_t bytesLastWrite     = 0;
+    uint32_t instance          = LPSPI_GetInstance(base);
     /*Used for byte swap*/
     uint32_t addrOffset    = 0;
     uint32_t rxAddr        = LPSPI_GetRxRegisterAddress(base);
@@ -318,13 +320,42 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
     edma_tcd_t *softwareTCD_pcsContinuous   = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[2]) & (~0x1FU));
     edma_tcd_t *softwareTCD_extraBytes      = (edma_tcd_t *)((uint32_t)(&handle->lpspiSoftwareTCD[1]) & (~0x1FU));
 
+    if (transfer->dataSize <= bytesPerFrame)
+    {
+        /* Once dma transfer*/
+        firstTimeDataSize          = transfer->dataSize;
+        handle->isMultiDMATransmit = false;
+    }
+    else if (transfer->dataSize > handle->dataBytesEveryTime)
+    {
+        /* More dma transfer*/
+        firstTimeDataSize          = handle->dataBytesEveryTime;
+        handle->isMultiDMATransmit = true;
+        if (transfer->dataSize % handle->dataBytesEveryTime != 0U)
+        {
+            handle->lastTimeDataBytes = transfer->dataSize % handle->dataBytesEveryTime;
+        }
+        else
+        {
+            handle->lastTimeDataBytes = handle->dataBytesEveryTime;
+        }
+
+        handle->dmaTransmitTime =
+            (uint8_t)((transfer->dataSize + handle->dataBytesEveryTime - 1U) / handle->dataBytesEveryTime);
+    }
+    else
+    {
+        /* Once dma transfer*/
+        firstTimeDataSize          = transfer->dataSize;
+        handle->isMultiDMATransmit = false;
+    }
     handle->state                  = (uint8_t)kLPSPI_Busy;
     handle->txData                 = transfer->txData;
     handle->rxData                 = transfer->rxData;
-    handle->txRemainingByteCount   = transfer->dataSize;
-    handle->rxRemainingByteCount   = transfer->dataSize;
-    handle->totalByteCount         = transfer->dataSize;
-    handle->writeRegRemainingTimes = (transfer->dataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U);
+    handle->txRemainingByteCount   = firstTimeDataSize;
+    handle->rxRemainingByteCount   = firstTimeDataSize;
+    handle->totalByteCount         = firstTimeDataSize;
+    handle->writeRegRemainingTimes = (firstTimeDataSize / bytesPerFrame) * ((bytesPerFrame + 3U) / 4U);
     handle->readRegRemainingTimes  = handle->writeRegRemainingTimes;
 
     handle->isThereExtraRxBytes = false;
@@ -469,8 +500,20 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
         transferConfigTx.destAddr        = (uint32_t)txAddr + addrOffset;
         transferConfigTx.majorLoopCounts = 1;
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+        EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes);
+        if (handle->isPcsContinuous)
+        {
+            EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes,
+                                         &transferConfigTx, softwareTCD_pcsContinuous);
+        }
+        else
+        {
+            EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes,
+                                         &transferConfigTx, NULL);
+        }
+#else
         EDMA_TcdReset(softwareTCD_extraBytes);
-
         if (handle->isPcsContinuous)
         {
             EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, softwareTCD_pcsContinuous);
@@ -479,12 +522,14 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
         {
             EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL);
         }
+#endif
     }
 
     if (handle->isPcsContinuous)
     {
-        handle->transmitCommand = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK);
-
+        /*  Set continue incase of twice call transfer. */
+        LPSPI_SetPCSContinous(base, true);
+        handle->transmitCommand    = base->TCR & ~(LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK);
         transferConfigTx.srcAddr   = (uint32_t) & (handle->transmitCommand);
         transferConfigTx.srcOffset = 0;
 
@@ -496,8 +541,14 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
         transferConfigTx.minorLoopBytes   = 4;
         transferConfigTx.majorLoopCounts  = 1;
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+        EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous);
+        EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_pcsContinuous,
+                                     &transferConfigTx, NULL);
+#else
         EDMA_TcdReset(softwareTCD_pcsContinuous);
         EDMA_TcdSetTransferConfig(softwareTCD_pcsContinuous, &transferConfigTx, NULL);
+#endif
     }
 
     if (handle->txData != NULL)
@@ -559,20 +610,39 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
 
     if (isThereExtraTxBytes)
     {
-        EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                               &transferConfigTx, softwareTCD_extraBytes);
+        handle->lastTimeTCD = softwareTCD_extraBytes;
     }
     else if (handle->isPcsContinuous)
     {
-        EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
-                               &transferConfigTx, softwareTCD_pcsContinuous);
+        handle->lastTimeTCD = softwareTCD_pcsContinuous;
     }
     else
     {
+        handle->lastTimeTCD = NULL;
+    }
+
+    if (handle->isMultiDMATransmit)
+    {
+        transferConfigTx.majorLoopCounts = handle->dataBytesEveryTime;
+        if (handle->isPcsContinuous)
+        {
+            /* Pcs-continue mode is not supported in Multi DMA.
+               Please use no-continue mode and use GPIO control CS pin*/
+            LPSPI_SetPCSContinous(base, false);
+            assert(false);
+        }
+
         EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
                                &transferConfigTx, NULL);
+        (void)memcpy(&handle->transferConfigTx, &transferConfigTx, sizeof(edma_transfer_config_t));
+        (void)memcpy(&handle->transferConfigRx, &transferConfigRx, sizeof(edma_transfer_config_t));
+    }
+    else
+    {
+        transferConfigTx.majorLoopCounts = handle->writeRegRemainingTimes;
+        EDMA_SetTransferConfig(handle->edmaTxDataToTxRegHandle->base, handle->edmaTxDataToTxRegHandle->channel,
+                               &transferConfigTx, handle->lastTimeTCD);
     }
-
     EDMA_StartTransfer(handle->edmaTxDataToTxRegHandle);
     EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
     LPSPI_EnableDMA(base, (uint32_t)kLPSPI_RxDmaEnable | (uint32_t)kLPSPI_TxDmaEnable);
@@ -600,12 +670,12 @@ status_t LPSPI_MasterTransferEDMALite(LPSPI_Type *base, lpspi_master_edma_handle
 status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, lpspi_transfer_t *transfer)
 {
     status_t status = kStatus_Fail;
-    status = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags);
-    if(kStatus_Success != status)
+    status          = LPSPI_MasterTransferPrepareEDMALite(base, handle, transfer->configFlags);
+    if (kStatus_Success != status)
     {
-       return status;
+        return status;
     }
-    return LPSPI_MasterTransferEDMALite(base,handle,transfer);
+    return LPSPI_MasterTransferEDMALite(base, handle, transfer);
 }
 
 static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
@@ -617,28 +687,99 @@ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
     assert(g_lpspiEdmaPrivateHandle != NULL);
 
     uint32_t readData;
-
+    status_t callbackStatus = kStatus_Success;
     lpspi_master_edma_private_handle_t *lpspiEdmaPrivateHandle;
-
+    lpspi_master_edma_handle_t *lpspiEdmaHandle;
     lpspiEdmaPrivateHandle = (lpspi_master_edma_private_handle_t *)g_lpspiEdmaPrivateHandle;
 
-    size_t rxRemainingByteCount = lpspiEdmaPrivateHandle->handle->rxRemainingByteCount;
-    uint8_t bytesLastRead       = lpspiEdmaPrivateHandle->handle->bytesLastRead;
-    bool isByteSwap             = lpspiEdmaPrivateHandle->handle->isByteSwap;
+    lpspiEdmaHandle             = lpspiEdmaPrivateHandle->handle;
+    size_t rxRemainingByteCount = lpspiEdmaHandle->rxRemainingByteCount;
+    uint8_t bytesLastRead       = lpspiEdmaHandle->bytesLastRead;
+    bool isByteSwap             = lpspiEdmaHandle->isByteSwap;
+
+    bool lpspitxDmaUpdate = false;
+    bool lpspirxDmaUpdate = false;
 
     LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable);
 
-    if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes)
+    if (!transferDone)
     {
-        while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U)
+        callbackStatus = kStatus_LPSPI_Error;
+    }
+    else
+    {
+        if (lpspiEdmaHandle->isMultiDMATransmit)
         {
-        }
-        readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base);
+            /* multi DMA transmit */
+            lpspiEdmaHandle->dmaTransmitTime--;
+            if (lpspiEdmaHandle->dmaTransmitTime >= 1U)
+            {
+                if (lpspiEdmaHandle->txData != NULL)
+                {
+                    lpspitxDmaUpdate = true;
+                    lpspiEdmaHandle->transferConfigTx.srcAddr += lpspiEdmaHandle->dataBytesEveryTime;
+                }
+                if (lpspiEdmaHandle->rxData != NULL)
+                {
+                    lpspirxDmaUpdate = true;
+                    lpspiEdmaHandle->transferConfigRx.destAddr += lpspiEdmaHandle->dataBytesEveryTime;
+                }
+                /* The last time - 1 time, need check the lastTime data bytes */
+                if (lpspiEdmaHandle->dmaTransmitTime == 1U)
+                {
+                    if (lpspiEdmaHandle->lastTimeDataBytes != lpspiEdmaHandle->dataBytesEveryTime)
+                    {
+                        /* Need update count if last time count is not dataBytesEveryTime*/
+                        lpspiEdmaHandle->transferConfigTx.majorLoopCounts = lpspiEdmaHandle->lastTimeDataBytes;
+                        lpspiEdmaHandle->transferConfigRx.majorLoopCounts = lpspiEdmaHandle->lastTimeDataBytes;
+                        lpspitxDmaUpdate                                  = true;
+                        lpspirxDmaUpdate                                  = true;
+                    }
+                }
+                /* Update RX channel first */
+                if (lpspirxDmaUpdate)
+                {
+                    EDMA_SetTransferConfig(lpspiEdmaHandle->edmaRxRegToRxDataHandle->base,
+                                           lpspiEdmaHandle->edmaRxRegToRxDataHandle->channel,
+                                           &lpspiEdmaHandle->transferConfigRx, NULL);
+                }
+                EDMA_StartTransfer(lpspiEdmaHandle->edmaRxRegToRxDataHandle);
+                /* Update TX channel */
+                if (lpspitxDmaUpdate)
+                {
+                    EDMA_SetTransferConfig(lpspiEdmaHandle->edmaTxDataToTxRegHandle->base,
+                                           lpspiEdmaHandle->edmaTxDataToTxRegHandle->channel,
+                                           &lpspiEdmaHandle->transferConfigTx, NULL);
+                }
+                EDMA_StartTransfer(lpspiEdmaHandle->edmaTxDataToTxRegHandle);
 
-        if (lpspiEdmaPrivateHandle->handle->rxData != NULL)
+                LPSPI_EnableDMA(lpspiEdmaPrivateHandle->base,
+                                (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable);
+                /* Continue DMA transmit*/
+                return;
+            }
+            else
+            {
+                /* Transmit complete */
+            }
+        }
+        else
         {
-            LPSPI_SeparateEdmaReadData(&(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]),
-                                       readData, bytesLastRead, isByteSwap);
+            /* Once DMA transfer */
+            if (lpspiEdmaPrivateHandle->handle->isThereExtraRxBytes)
+            {
+                while (LPSPI_GetRxFifoCount(lpspiEdmaPrivateHandle->base) == 0U)
+                {
+                }
+                readData = LPSPI_ReadData(lpspiEdmaPrivateHandle->base);
+                if (lpspiEdmaPrivateHandle->handle->rxData != NULL)
+                {
+                    LPSPI_SeparateEdmaReadData(
+                        &(lpspiEdmaPrivateHandle->handle->rxData[rxRemainingByteCount - bytesLastRead]), readData,
+                        bytesLastRead, isByteSwap);
+                }
+            }
+            /* Transmit complete */
         }
     }
 
@@ -647,7 +788,7 @@ static void EDMA_LpspiMasterCallback(edma_handle_t *edmaHandle,
     if (lpspiEdmaPrivateHandle->handle->callback != NULL)
     {
         lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle,
-                                                 kStatus_Success, lpspiEdmaPrivateHandle->handle->userData);
+                                                 callbackStatus, lpspiEdmaPrivateHandle->handle->userData);
     }
 }
 
@@ -839,15 +980,15 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
     base->TCR =
         (base->TCR & ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK | LPSPI_TCR_BYSW_MASK | LPSPI_TCR_TXMSK_MASK)) |
         LPSPI_TCR_TXMSK(transfer->txData == NULL) | LPSPI_TCR_BYSW(isByteSwap) | LPSPI_TCR_PCS(whichPcs);
-    
-    if(transfer->txData == NULL)
+
+    if (transfer->txData == NULL)
     {
         if (!LPSPI_WaitTxFifoEmpty(base))
         {
             return kStatus_LPSPI_Error;
         }
     }
-    
+
     /*Calculate the bytes for write/read the TX/RX register each time*/
     if (bytesPerFrame <= 4U)
     {
@@ -997,8 +1138,14 @@ status_t LPSPI_SlaveTransferEDMA(LPSPI_Type *base, lpspi_slave_edma_handle_t *ha
             transferConfigTx.destAddr        = (uint32_t)txAddr + addrOffset;
             transferConfigTx.majorLoopCounts = 1;
 
+#if defined FSL_EDMA_DRIVER_EDMA4 && FSL_EDMA_DRIVER_EDMA4
+            EDMA_TcdResetExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes);
+            EDMA_TcdSetTransferConfigExt(handle->edmaRxRegToRxDataHandle->base, softwareTCD_extraBytes,
+                                         &transferConfigTx, NULL);
+#else
             EDMA_TcdReset(softwareTCD_extraBytes);
             EDMA_TcdSetTransferConfig(softwareTCD_extraBytes, &transferConfigTx, NULL);
+#endif
         }
 
         transferConfigTx.srcAddr         = (uint32_t)(handle->txData);
@@ -1074,6 +1221,7 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
     assert(g_lpspiEdmaPrivateHandle != NULL);
 
     uint32_t readData;
+    status_t callbackStatus = kStatus_Success;
 
     lpspi_slave_edma_private_handle_t *lpspiEdmaPrivateHandle;
 
@@ -1085,6 +1233,11 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
 
     LPSPI_DisableDMA(lpspiEdmaPrivateHandle->base, (uint32_t)kLPSPI_TxDmaEnable | (uint32_t)kLPSPI_RxDmaEnable);
 
+    if (!transferDone)
+    {
+        callbackStatus = kStatus_LPSPI_Error;
+    }
+
     /*
      * $Branch Coverage Justification$
      * When there are extra bytes, the slave will not receive the extra bytes,The while here will not stop.(will
@@ -1109,7 +1262,7 @@ static void EDMA_LpspiSlaveCallback(edma_handle_t *edmaHandle,
     if (lpspiEdmaPrivateHandle->handle->callback != NULL)
     {
         lpspiEdmaPrivateHandle->handle->callback(lpspiEdmaPrivateHandle->base, lpspiEdmaPrivateHandle->handle,
-                                                 kStatus_Success, lpspiEdmaPrivateHandle->handle->userData);
+                                                 callbackStatus, lpspiEdmaPrivateHandle->handle->userData);
     }
 }
 

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpspi_edma.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPSPI_EDMA_H_
-#define _FSL_LPSPI_EDMA_H_
+#ifndef FSL_LPSPI_EDMA_H_
+#define FSL_LPSPI_EDMA_H_
 
 #include "fsl_lpspi.h"
 #include "fsl_edma.h"
@@ -20,10 +20,13 @@
  * Definitions
  **********************************************************************************************************************/
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPSPI EDMA driver version. */
-#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+#define FSL_LPSPI_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 4, 4))
+
+/*! @brief DMA max transfer size */
+#define DMA_MAX_TRANSFER_COUNT 0x7FFFU
+/*! @} */
 
 /*!
  * @brief Forward declaration of the _lpspi_master_edma_handle typedefs.
@@ -63,89 +66,98 @@ typedef void (*lpspi_slave_edma_transfer_callback_t)(LPSPI_Type *base,
 /*! @brief LPSPI master eDMA transfer handle structure used for transactional API. */
 struct _lpspi_master_edma_handle
 {
-    volatile bool isPcsContinuous; /*!< Is PCS continuous in transfer. */
+    volatile bool isPcsContinuous;            /*!< Is PCS continuous in transfer. */
 
-    volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
+    volatile bool isByteSwap;                 /*!< A flag that whether should byte swap. */
 
-    volatile uint8_t fifoSize; /*!< FIFO dataSize. */
+    volatile uint8_t fifoSize;                /*!< FIFO dataSize. */
 
-    volatile uint8_t rxWatermark; /*!< Rx watermark. */
+    volatile uint8_t rxWatermark;             /*!< Rx watermark. */
 
-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
+    volatile uint8_t bytesEachWrite;          /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;           /*!< Bytes for each read RDR. */
 
-    volatile uint8_t bytesLastRead;    /*!< Bytes for last read RDR. */
-    volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */
+    volatile uint8_t bytesLastRead;           /*!< Bytes for last read RDR. */
+    volatile bool isThereExtraRxBytes;        /*!< Is there extra RX byte. */
 
-    uint8_t *volatile txData;             /*!< Send buffer. */
-    uint8_t *volatile rxData;             /*!< Receive buffer. */
-    volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
-    volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
+    const uint8_t *volatile txData;           /*!< Send buffer. */
+    uint8_t *volatile rxData;                 /*!< Receive buffer. */
+    volatile size_t txRemainingByteCount;     /*!< Number of bytes remaining to send.*/
+    volatile size_t rxRemainingByteCount;     /*!< Number of bytes remaining to receive.*/
 
     volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
     volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */
 
-    uint32_t totalByteCount; /*!< Number of transfer bytes*/
+    uint32_t totalByteCount;                  /*!< Number of transfer bytes*/
+
+    edma_tcd_t *lastTimeTCD;                  /*!< Pointer to the lastTime TCD*/
+    bool isMultiDMATransmit;                  /*!< Is there multi DMA transmit*/
+    volatile uint8_t dmaTransmitTime;         /*!< DMA Transfer times. */
+    uint32_t lastTimeDataBytes;               /*!< DMA transmit last Time data Bytes */
+
+    uint32_t dataBytesEveryTime;             /*!< Bytes in a time for DMA transfer, default is DMA_MAX_TRANSFER_COUNT */
 
-    uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
-    uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
+    edma_transfer_config_t transferConfigRx; /*!< Config of DMA rx channel.*/
+    edma_transfer_config_t transferConfigTx; /*!< Config of DMA tx channel.*/
+    uint32_t txBuffIfNull;                   /*!< Used if there is not txData for DMA purpose.*/
+    uint32_t rxBuffIfNull;                   /*!< Used if there is not rxData for DMA purpose.*/
 
-    uint32_t transmitCommand; /*!< Used to write TCR for DMA purpose.*/
+    uint32_t transmitCommand;                /*!< Used to write TCR for DMA purpose.*/
 
-    volatile uint8_t state; /*!< LPSPI transfer state , _lpspi_transfer_state.*/
+    volatile uint8_t state;                  /*!< LPSPI transfer state , _lpspi_transfer_state.*/
 
-    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+    uint8_t nbytes;                          /*!< eDMA minor byte transfer count initially configured. */
 
     lpspi_master_edma_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                                 /*!< Callback user data. */
 
-    edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
-    edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg buff*/
+    edma_handle_t *edmaRxRegToRxDataHandle;         /*!<edma_handle_t handle point used for RxReg to RxData buff*/
+    edma_handle_t *edmaTxDataToTxRegHandle;         /*!<edma_handle_t handle point used for TxData to TxReg buff*/
 
-    edma_tcd_t lpspiSoftwareTCD[3]; /*!<SoftwareTCD, internal used*/
+    edma_tcd_t lpspiSoftwareTCD[3];                 /*!<SoftwareTCD, internal used*/
 };
 
 /*! @brief LPSPI slave eDMA transfer handle structure used for transactional API.*/
 struct _lpspi_slave_edma_handle
 {
-    volatile bool isByteSwap; /*!< A flag that whether should byte swap. */
+    volatile bool isByteSwap;                      /*!< A flag that whether should byte swap. */
 
-    volatile uint8_t fifoSize; /*!< FIFO dataSize. */
+    volatile uint8_t fifoSize;                     /*!< FIFO dataSize. */
 
-    volatile uint8_t rxWatermark; /*!< Rx watermark. */
+    volatile uint8_t rxWatermark;                  /*!< Rx watermark. */
 
-    volatile uint8_t bytesEachWrite; /*!< Bytes for each write TDR. */
-    volatile uint8_t bytesEachRead;  /*!< Bytes for each read RDR. */
+    volatile uint8_t bytesEachWrite;               /*!< Bytes for each write TDR. */
+    volatile uint8_t bytesEachRead;                /*!< Bytes for each read RDR. */
 
-    volatile uint8_t bytesLastRead;    /*!< Bytes for last read RDR. */
-    volatile bool isThereExtraRxBytes; /*!< Is there extra RX byte. */
+    volatile uint8_t bytesLastRead;                /*!< Bytes for last read RDR. */
+    volatile bool isThereExtraRxBytes;             /*!< Is there extra RX byte. */
 
-    uint8_t nbytes; /*!< eDMA minor byte transfer count initially configured. */
+    uint8_t nbytes;                                /*!< eDMA minor byte transfer count initially configured. */
 
-    uint8_t *volatile txData;             /*!< Send buffer. */
-    uint8_t *volatile rxData;             /*!< Receive buffer. */
-    volatile size_t txRemainingByteCount; /*!< Number of bytes remaining to send.*/
-    volatile size_t rxRemainingByteCount; /*!< Number of bytes remaining to receive.*/
+    const uint8_t *volatile txData;                /*!< Send buffer. */
+    uint8_t *volatile rxData;                      /*!< Receive buffer. */
+    volatile size_t txRemainingByteCount;          /*!< Number of bytes remaining to send.*/
+    volatile size_t rxRemainingByteCount;          /*!< Number of bytes remaining to receive.*/
 
-    volatile uint32_t writeRegRemainingTimes; /*!< Write TDR register remaining times. */
-    volatile uint32_t readRegRemainingTimes;  /*!< Read RDR register remaining times. */
+    volatile uint32_t writeRegRemainingTimes;      /*!< Write TDR register remaining times. */
+    volatile uint32_t readRegRemainingTimes;       /*!< Read RDR register remaining times. */
 
-    uint32_t totalByteCount; /*!< Number of transfer bytes*/
+    uint32_t totalByteCount;                       /*!< Number of transfer bytes*/
 
-    uint32_t txBuffIfNull; /*!< Used if there is not txData for DMA purpose.*/
-    uint32_t rxBuffIfNull; /*!< Used if there is not rxData for DMA purpose.*/
+    uint32_t txBuffIfNull;                         /*!< Used if there is not txData for DMA purpose.*/
+    uint32_t rxBuffIfNull;                         /*!< Used if there is not rxData for DMA purpose.*/
 
-    volatile uint8_t state; /*!< LPSPI transfer state.*/
+    volatile uint8_t state;                        /*!< LPSPI transfer state.*/
 
-    uint32_t errorCount; /*!< Error count for slave transfer.*/
+    uint32_t errorCount;                           /*!< Error count for slave transfer.*/
 
     lpspi_slave_edma_transfer_callback_t callback; /*!< Completion callback. */
     void *userData;                                /*!< Callback user data. */
 
-    edma_handle_t *edmaRxRegToRxDataHandle; /*!<edma_handle_t handle point used for RxReg to RxData buff*/
-    edma_handle_t *edmaTxDataToTxRegHandle; /*!<edma_handle_t handle point used for TxData to TxReg*/
+    edma_handle_t *edmaRxRegToRxDataHandle;        /*!<edma_handle_t handle point used for RxReg to RxData buff*/
+    edma_handle_t *edmaTxDataToTxRegHandle;        /*!<edma_handle_t handle point used for TxData to TxReg*/
 
-    edma_tcd_t lpspiSoftwareTCD[2]; /*!<SoftwareTCD, internal used*/
+    edma_tcd_t lpspiSoftwareTCD[2];                /*!<SoftwareTCD, internal used*/
 };
 
 /***********************************************************************************************************************
@@ -205,7 +217,7 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
 /*!
  * @brief LPSPI master config transfer parameter while using eDMA.
  *
- * This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite. 
+ * This function is preparing to transfer data using eDMA, work with LPSPI_MasterTransferEDMALite.
  *
  * @param base LPSPI peripheral base address.
  * @param handle pointer to lpspi_master_edma_handle_t structure which stores the transfer state.
@@ -214,7 +226,9 @@ status_t LPSPI_MasterTransferEDMA(LPSPI_Type *base, lpspi_master_edma_handle_t *
  * @retval kStatus_Success          Execution successfully.
  * @retval kStatus_LPSPI_Busy       The LPSPI device is busy.
  */
-status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma_handle_t *handle, uint32_t configFlags);
+status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base,
+                                             lpspi_master_edma_handle_t *handle,
+                                             uint32_t configFlags);
 
 /*!
  * @brief LPSPI master transfer data using eDMA without configs.
@@ -223,7 +237,7 @@ status_t LPSPI_MasterTransferPrepareEDMALite(LPSPI_Type *base, lpspi_master_edma
  * is transferred, the callback function is called.
  *
  * Note:
- * This API is only for transfer through DMA without configuration. 
+ * This API is only for transfer through DMA without configuration.
  * Before calling this API, you must call LPSPI_MasterTransferPrepareEDMALite to configure it once.
  * The transfer data size should be an integer multiple of bytesPerFrame if bytesPerFrame is less than or equal to 4.
  * For bytesPerFrame greater than 4:
@@ -336,4 +350,4 @@ status_t LPSPI_SlaveTransferGetCountEDMA(LPSPI_Type *base, lpspi_slave_edma_hand
 
 /*! @}*/
 
-#endif /*_FSL_LPSPI_EDMA_H_*/
+#endif /*FSL_LPSPI_EDMA_H_*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lptmr.c

@@ -165,9 +165,19 @@ void LPTMR_GetDefaultConfig(lptmr_config_t *config)
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
       FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
     config->prescalerClockSource = kLPTMR_PrescalerClock_1;
-#else
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
     config->prescalerClockSource = kLPTMR_PrescalerClock_0;
-#endif /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_2;
+#elif !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
+    config->prescalerClockSource = kLPTMR_PrescalerClock_3;
+#else
+#error No valid source
+#endif
+
     /* Divide the prescaler clock by 2 */
     config->value = kLPTMR_Prescale_Glitch_0;
 }

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lptmr.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2017, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPTMR_H_
-#define _FSL_LPTMR_H_
+#ifndef FSL_LPTMR_H_
+#define FSL_LPTMR_H_
 
 #include "fsl_common.h"
 
@@ -20,9 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 1, 1)) /*!< Version 2.1.1 */
-/*@}*/
+/*! @{ */
+/*! Driver Version */
+#define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @} */
 
 /*! @brief LPTMR pin selection used in pulse counter mode.*/
 typedef enum _lptmr_pin_select
@@ -74,12 +75,21 @@ typedef enum _lptmr_prescaler_glitch_value
  */
 typedef enum _lptmr_prescaler_clock_select
 {
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_0_SUPPORT)
     kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
+#endif
+
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT) && \
       FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT)
     kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
 #endif                              /* FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_1_SUPPORT */
+
+#if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT) && \
+      FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_2_SUPPORT)
     kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
+#endif
+
 #if !(defined(FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT) && \
       FSL_FEATURE_LPTMR_HAS_NO_PRESCALER_CLOCK_SOURCE_3_SUPPORT)
     kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
@@ -371,4 +381,4 @@ static inline void LPTMR_StopTimer(LPTMR_Type *base)
 
 /*! @}*/
 
-#endif /* _FSL_LPTMR_H_ */
+#endif /* FSL_LPTMR_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpuart.c

@@ -66,6 +66,19 @@ static bool LPUART_TransferIsRxRingBufferFull(LPUART_Type *base, lpuart_handle_t
  * @param length Size of the buffer to be sent.
  */
 static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
+/*!
+ * @brief Write to TX register using non-blocking method in 9bit or 10bit mode.
+ *
+ * The 10bit of data will be writen to TX register DATA.
+ * Please make sure data 10bit is valid and other bit is 0.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the buffer to be sent.
+ */
+static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length);
 
 /*!
  * @brief Read RX register using non-blocking method.
@@ -78,7 +91,18 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
  * @param length Size of the buffer.
  */
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length);
-
+/*!
+ * @brief Read RX register using non-blocking method in 9bit or 10bit mode.
+ *
+ * This function reads 10bit data from the RX register directly and stores to 16bit data.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ */
+static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length);
 /*!
  * @brief LPUART_TransferHandleIDLEIsReady handle function.
  * This function handles when IDLE is ready.
@@ -251,6 +275,19 @@ static void LPUART_WriteNonBlocking(LPUART_Type *base, const uint8_t *data, size
         base->DATA = data[i];
     }
 }
+static void LPUART_WriteNonBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+
+    /* The Non Blocking write data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        base->DATA = data[i];
+    }
+}
 
 static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 {
@@ -282,6 +319,19 @@ static void LPUART_ReadNonBlocking(LPUART_Type *base, uint8_t *data, size_t leng
     }
 }
 
+static void LPUART_ReadNonBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    size_t i;
+    /* The Non Blocking read data API assume user have ensured there is enough space in
+    peripheral to write. */
+    for (i = 0; i < length; i++)
+    {
+        data[i] = (uint16_t)(base->DATA & 0x03FFU);
+    }
+}
+
 /*!
  * brief Initializes an LPUART instance with the user configuration structure and the peripheral clock.
  *
@@ -333,13 +383,13 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
     for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
     {
         /* calculate the temporary sbr value   */
-        sbrTemp = (uint16_t)((srcClock_Hz * 10U / (config->baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U);
+        sbrTemp = (uint16_t)((srcClock_Hz * 2U / (config->baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U);
         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
         if (sbrTemp == 0U)
         {
             sbrTemp = 1U;
         }
-		else if (sbrTemp > LPUART_BAUD_SBR_MASK)
+        else if (sbrTemp > LPUART_BAUD_SBR_MASK)
         {
             sbrTemp = LPUART_BAUD_SBR_MASK;
         }
@@ -350,7 +400,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
         /* Calculate the baud rate based on the temporary OSR and SBR values */
         calculatedBaud = (srcClock_Hz / ((uint32_t)osrTemp * (uint32_t)sbrTemp));
         tempDiff       = calculatedBaud > config->baudRate_Bps ? (calculatedBaud - config->baudRate_Bps) :
-                                                           (config->baudRate_Bps - calculatedBaud);
+                                                                 (config->baudRate_Bps - calculatedBaud);
 
         if (tempDiff <= baudDiff)
         {
@@ -382,7 +432,7 @@ status_t LPUART_Init(LPUART_Type *base, const lpuart_config_t *config, uint32_t
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 #if defined(LPUART_RESETS_ARRAY)
-    RESET_ReleasePeripheralReset(s_lpuartResets[LPUART_GetInstance(base)]);
+        RESET_ReleasePeripheralReset(s_lpuartResets[LPUART_GetInstance(base)]);
 #endif
 
 #if defined(FSL_FEATURE_LPUART_HAS_GLOBAL) && FSL_FEATURE_LPUART_HAS_GLOBAL
@@ -665,7 +715,7 @@ status_t LPUART_SetBaudRate(LPUART_Type *base, uint32_t baudRate_Bps, uint32_t s
     for (osrTemp = 4U; osrTemp <= 32U; osrTemp++)
     {
         /* calculate the temporary sbr value   */
-        sbrTemp = (uint16_t)((srcClock_Hz * 10U / (baudRate_Bps * (uint32_t)osrTemp) + 5U) / 10U);
+        sbrTemp = (uint16_t)((srcClock_Hz * 2U / (baudRate_Bps * (uint32_t)osrTemp) + 1U) / 2U);
         /*set sbrTemp to 1 if the sourceClockInHz can not satisfy the desired baud rate*/
         if (sbrTemp == 0U)
         {
@@ -801,31 +851,41 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address)
  */
 void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
 {
+    uint32_t s_atomicOldInt;
     /* Only consider the real interrupt enable bits. */
     mask &= (uint32_t)kLPUART_AllInterruptEnable;
 
     /* Check int enable bits in base->BAUD */
-    uint32_t tempReg = base->BAUD;
+    uint32_t baudRegMask = 0UL;
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    tempReg |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
     /* Clear bit 7 from mask */
     mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
 #endif
-    tempReg |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
     /* Clear bit 6 from mask */
     mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
-    base->BAUD = tempReg;
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->BAUD |= baudRegMask;
+    EnableGlobalIRQ(s_atomicOldInt);
 
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     /* Check int enable bits in base->FIFO */
-    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->FIFO     = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) |
                  (mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    EnableGlobalIRQ(s_atomicOldInt);
+
     /* Clear bit 9 and bit 8 from mask */
     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
 #endif
 
     /* Set int enable bits in base->CTRL */
+    s_atomicOldInt = DisableGlobalIRQ();
     base->CTRL |= mask;
+    EnableGlobalIRQ(s_atomicOldInt);
 }
 
 /*!
@@ -843,30 +903,40 @@ void LPUART_EnableInterrupts(LPUART_Type *base, uint32_t mask)
  */
 void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask)
 {
+    uint32_t s_atomicOldInt;
     /* Only consider the real interrupt enable bits. */
     mask &= (uint32_t)kLPUART_AllInterruptEnable;
-    /* Check int enable bits in base->BAUD */
-    uint32_t tempReg = base->BAUD;
+
+    /* Clear int enable bits in base->BAUD */
+    uint32_t baudRegMask = 0UL;
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    tempReg &= ~((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_LBKDIE_MASK);
     /* Clear bit 7 from mask */
     mask &= ~(uint32_t)kLPUART_LinBreakInterruptEnable;
 #endif
-    tempReg &= ~((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
+    baudRegMask |= ((mask << 8U) & LPUART_BAUD_RXEDGIE_MASK);
     /* Clear bit 6 from mask */
     mask &= ~(uint32_t)kLPUART_RxActiveEdgeInterruptEnable;
-    base->BAUD = tempReg;
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->BAUD &= ~baudRegMask;
+    EnableGlobalIRQ(s_atomicOldInt);
 
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
-    /* Check int enable bits in base->FIFO */
-    base->FIFO = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
+    /* Clear int enable bits in base->FIFO */
+
+    s_atomicOldInt = DisableGlobalIRQ();
+    base->FIFO     = (base->FIFO & ~(LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK)) &
                  ~(mask & (LPUART_FIFO_TXOFE_MASK | LPUART_FIFO_RXUFE_MASK));
+    EnableGlobalIRQ(s_atomicOldInt);
     /* Clear bit 9 and bit 8 from mask */
     mask &= ~((uint32_t)kLPUART_TxFifoOverflowInterruptEnable | (uint32_t)kLPUART_RxFifoUnderflowInterruptEnable);
 #endif
 
-    /* Check int enable bits in base->CTRL */
+    /* Clear int enable bits in base->CTRL */
+    s_atomicOldInt = DisableGlobalIRQ();
     base->CTRL &= ~mask;
+    EnableGlobalIRQ(s_atomicOldInt);
 }
 
 /*!
@@ -974,8 +1044,8 @@ status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask)
         /* Get the FIFO register value and mask the rx/tx FIFO flush bits and the status bits that can be W1C in case
            they are written 1 accidentally. */
         temp = (uint32_t)base->FIFO;
-        temp &= (uint32_t)(
-            ~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK));
+        temp &= (uint32_t)(~(LPUART_FIFO_TXFLUSH_MASK | LPUART_FIFO_RXFLUSH_MASK | LPUART_FIFO_TXOF_MASK |
+                             LPUART_FIFO_RXUF_MASK));
         temp |= (mask << 16U) & (LPUART_FIFO_TXOF_MASK | LPUART_FIFO_RXUF_MASK);
         base->FIFO = temp;
     }
@@ -1017,6 +1087,66 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len
     const uint8_t *dataAddress = data;
     size_t transferSize        = length;
 
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != transferSize)
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+        while ((0U == (base->STAT & LPUART_STAT_TDRE_MASK)) && (0U != --waitTimes))
+#else
+        while (0U == (base->STAT & LPUART_STAT_TDRE_MASK))
+#endif
+        {
+        }
+#if UART_RETRY_TIMES
+        if (0U == waitTimes)
+        {
+            return kStatus_LPUART_Timeout;
+        }
+#endif
+        base->DATA = *(dataAddress);
+        dataAddress++;
+        transferSize--;
+    }
+    /* Ensure all the data in the transmit buffer are sent out to bus. */
+#if UART_RETRY_TIMES
+    waitTimes = UART_RETRY_TIMES;
+    while ((0U == (base->STAT & LPUART_STAT_TC_MASK)) && (0U != --waitTimes))
+#else
+    while (0U == (base->STAT & LPUART_STAT_TC_MASK))
+#endif
+    {
+    }
+#if UART_RETRY_TIMES
+    if (0U == waitTimes)
+    {
+        return kStatus_LPUART_Timeout;
+    }
+#endif
+    return kStatus_Success;
+}
+/*!
+ * brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
+ *
+ * note This function only support 9bit or 10bit transfer.
+ *       Please make sure only 10bit of data is valid and other bits are 0.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    const uint16_t *dataAddress = data;
+    size_t transferSize         = length;
+
 #if UART_RETRY_TIMES
     uint32_t waitTimes;
 #endif
@@ -1191,6 +1321,117 @@ status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length)
 
     return status;
 }
+/*!
+ * brief Reads the receiver data register in 9bit or 10bit mode.
+ *
+ * note This function only support 9bit or 10bit transfer.
+ *
+ * param base LPUART peripheral base address.
+ * param data Start address of the buffer to store the received data by 16bit, only 10bit is valid.
+ * param length Size of the buffer.
+ * retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length)
+{
+    assert(NULL != data);
+
+    status_t status = kStatus_Success;
+    uint32_t statusFlag;
+    uint16_t *dataAddress = data;
+
+#if UART_RETRY_TIMES
+    uint32_t waitTimes;
+#endif
+
+    while (0U != (length--))
+    {
+#if UART_RETRY_TIMES
+        waitTimes = UART_RETRY_TIMES;
+#endif
+#if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
+        while (0U == ((base->WATER & LPUART_WATER_RXCOUNT_MASK) >> LPUART_WATER_RXCOUNT_SHIFT))
+#else
+        while (0U == (base->STAT & LPUART_STAT_RDRF_MASK))
+#endif
+        {
+#if UART_RETRY_TIMES
+            if (0U == --waitTimes)
+            {
+                status = kStatus_LPUART_Timeout;
+                break;
+            }
+#endif
+            statusFlag = LPUART_GetStatusFlags(base);
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_RxOverrunFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_RxOverrunFlag)) ?
+                              (kStatus_LPUART_RxHardwareOverrun) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+                /* Other error flags(FE, NF, and PF) are prevented from setting once OR is set, no need to check other
+                 * error flags*/
+                break;
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_ParityErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_ParityErrorFlag)) ?
+                              (kStatus_LPUART_ParityError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_FramingErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_FramingErrorFlag)) ?
+                              (kStatus_LPUART_FramingError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+
+            if (0U != (statusFlag & (uint32_t)kLPUART_NoiseErrorFlag))
+            {
+                /*
+                 * $Branch Coverage Justification$
+                 * $ref fsl_lpuart_c_ref_2$.
+                 */
+                status = ((kStatus_Success == LPUART_ClearStatusFlags(base, (uint32_t)kLPUART_NoiseErrorFlag)) ?
+                              (kStatus_LPUART_NoiseError) :
+                              (kStatus_LPUART_FlagCannotClearManually));
+            }
+            if (kStatus_Success != status)
+            {
+                break;
+            }
+        }
+        if (kStatus_Success == status)
+        {
+            *(dataAddress) = (uint16_t)(base->DATA & 0x03FFU);
+            dataAddress++;
+        }
+        else
+        {
+            break;
+        }
+    }
+
+    return status;
+}
 
 /*!
  * brief Initializes the LPUART handle.
@@ -1240,6 +1481,7 @@ void LPUART_TransferCreateHandle(LPUART_Type *base,
     /* Initial seven data bits flag */
     handle->isSevenDataBits = isSevenDataBits;
 #endif
+    handle->is16bitData = false;
 
     /* Get instance from peripheral base address. */
     instance = LPUART_GetInstance(base);
@@ -1284,8 +1526,15 @@ void LPUART_TransferStartRingBuffer(LPUART_Type *base,
     assert(NULL != ringBuffer);
 
     /* Setup the ring buffer address */
-    handle->rxRingBuffer     = ringBuffer;
-    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBuffer = ringBuffer;
+    if (!handle->is16bitData)
+    {
+        handle->rxRingBufferSize = ringBufferSize;
+    }
+    else
+    {
+        handle->rxRingBufferSize = ringBufferSize / 2U;
+    }
     handle->rxRingBufferHead = 0U;
     handle->rxRingBufferTail = 0U;
 
@@ -1358,7 +1607,14 @@ status_t LPUART_TransferSendNonBlocking(LPUART_Type *base, lpuart_handle_t *hand
     }
     else
     {
-        handle->txData        = xfer->txData;
+        if (!handle->is16bitData)
+        {
+            handle->txData = xfer->txData;
+        }
+        else
+        {
+            handle->txData16 = xfer->txData16;
+        }
         handle->txDataSize    = xfer->dataSize;
         handle->txDataSizeAll = xfer->dataSize;
         handle->txState       = (uint8_t)kLPUART_TxBusy;
@@ -1529,7 +1785,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
                 /* Copy data from ring buffer to user memory. */
                 for (i = 0U; i < bytesToCopy; i++)
                 {
-                    xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    if (!handle->is16bitData)
+                    {
+                        xfer->rxData[bytesCurrentReceived] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    }
+                    else
+                    {
+                        xfer->rxData16[bytesCurrentReceived] = handle->rxRingBuffer16[handle->rxRingBufferTail];
+                    }
                     bytesCurrentReceived++;
 
                     /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
@@ -1548,7 +1811,15 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
             if (0U != bytesToReceive)
             {
                 /* No data in ring buffer, save the request to LPUART handle. */
-                handle->rxData        = &xfer->rxData[bytesCurrentReceived];
+
+                if (!handle->is16bitData)
+                {
+                    handle->rxData = &xfer->rxData[bytesCurrentReceived];
+                }
+                else
+                {
+                    handle->rxData16 = &xfer->rxData16[bytesCurrentReceived];
+                }
                 handle->rxDataSize    = bytesToReceive;
                 handle->rxDataSizeAll = xfer->dataSize;
                 handle->rxState       = (uint8_t)kLPUART_RxBusy;
@@ -1573,7 +1844,14 @@ status_t LPUART_TransferReceiveNonBlocking(LPUART_Type *base,
         /* Ring buffer not used. */
         else
         {
-            handle->rxData        = &xfer->rxData[bytesCurrentReceived];
+            if (!handle->is16bitData)
+            {
+                handle->rxData = &xfer->rxData[bytesCurrentReceived];
+            }
+            else
+            {
+                handle->rxData16 = &xfer->rxData16[bytesCurrentReceived];
+            }
             handle->rxDataSize    = bytesToReceive;
             handle->rxDataSizeAll = bytesToReceive;
             handle->rxState       = (uint8_t)kLPUART_RxBusy;
@@ -1669,10 +1947,17 @@ static void LPUART_TransferHandleIDLEReady(LPUART_Type *base, lpuart_handle_t *h
     while ((0U != handle->rxDataSize) && (0U != count))
     {
         tempCount = (uint8_t)MIN(handle->rxDataSize, count);
-
         /* Using non block API to read the data from the registers. */
-        LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
-        handle->rxData = &handle->rxData[tempCount];
+        if (!handle->is16bitData)
+        {
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData = &handle->rxData[tempCount];
+        }
+        else
+        {
+            LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount);
+            handle->rxData16 = &handle->rxData16[tempCount];
+        }
         handle->rxDataSize -= tempCount;
         count -= tempCount;
 
@@ -1736,8 +2021,16 @@ static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handl
 #endif
 
         /* Using non block API to read the data from the registers. */
-        LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
-        handle->rxData = &handle->rxData[tempCount];
+        if (!handle->is16bitData)
+        {
+            LPUART_ReadNonBlocking(base, handle->rxData, tempCount);
+            handle->rxData = &handle->rxData[tempCount];
+        }
+        else
+        {
+            LPUART_ReadNonBlocking16bit(base, handle->rxData16, tempCount);
+            handle->rxData16 = &handle->rxData16[tempCount];
+        }
         handle->rxDataSize -= tempCount;
         count -= tempCount;
 
@@ -1791,10 +2084,24 @@ static void LPUART_TransferHandleReceiveDataFull(LPUART_Type *base, lpuart_handl
             }
             else
             {
-                handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                if (!handle->is16bitData)
+                {
+                    handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+                }
+                else
+                {
+                    handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU);
+                }
             }
 #else
-            handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+            if (!handle->is16bitData)
+            {
+                handle->rxRingBuffer[tpmRxRingBufferHead] = (uint8_t)tpmData;
+            }
+            else
+            {
+                handle->rxRingBuffer16[tpmRxRingBufferHead] = (uint16_t)(tpmData & 0x3FFU);
+            }
 #endif
 
             /* Increase handle->rxRingBufferHead. */
@@ -1846,8 +2153,16 @@ static void LPUART_TransferHandleSendDataEmpty(LPUART_Type *base, lpuart_handle_
 #endif
 
         /* Using non block API to write the data to the registers. */
-        LPUART_WriteNonBlocking(base, handle->txData, tempCount);
-        handle->txData = &handle->txData[tempCount];
+        if (!handle->is16bitData)
+        {
+            LPUART_WriteNonBlocking(base, handle->txData, tempCount);
+            handle->txData = &handle->txData[tempCount];
+        }
+        else
+        {
+            LPUART_WriteNonBlocking16bit(base, handle->txData16, tempCount);
+            handle->txData16 = &handle->txData16[tempCount];
+        }
         handle->txDataSize -= tempCount;
         count -= tempCount;
 

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpuart.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPUART_H_
-#define _FSL_LPUART_H_
+#ifndef FSL_LPUART_H_
+#define FSL_LPUART_H_
 
 #include "fsl_common.h"
 
@@ -20,10 +20,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPUART driver version. */
-#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 7, 4))
-/*@}*/
+#define FSL_LPUART_DRIVER_VERSION (MAKE_VERSION(2, 8, 2))
+/*! @} */
 
 /*! @brief Retry times for waiting flag. */
 #ifndef UART_RETRY_TIMES
@@ -124,7 +124,7 @@ typedef enum _lpuart_idle_config
 enum _lpuart_interrupt_enable
 {
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U), /*!< LIN break detect. bit 7 */
+    kLPUART_LinBreakInterruptEnable = (LPUART_BAUD_LBKDIE_MASK >> 8U),              /*!< LIN break detect. bit 7 */
 #endif
     kLPUART_RxActiveEdgeInterruptEnable         = (LPUART_BAUD_RXEDGIE_MASK >> 8U), /*!< Receive Active Edge. bit 6 */
     kLPUART_TxDataRegEmptyInterruptEnable       = (LPUART_CTRL_TIE_MASK),  /*!< Transmit data register empty. bit 23 */
@@ -136,8 +136,8 @@ enum _lpuart_interrupt_enable
     kLPUART_FramingErrorInterruptEnable         = (LPUART_CTRL_FEIE_MASK), /*!< Framing error flag. bit 25 */
     kLPUART_ParityErrorInterruptEnable          = (LPUART_CTRL_PEIE_MASK), /*!< Parity error flag. bit 24 */
 #if defined(FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING) && FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING
-    kLPUART_Match1InterruptEnable = (LPUART_CTRL_MA1IE_MASK), /*!< Parity error flag. bit 15 */
-    kLPUART_Match2InterruptEnable = (LPUART_CTRL_MA2IE_MASK), /*!< Parity error flag. bit 14 */
+    kLPUART_Match1InterruptEnable = (LPUART_CTRL_MA1IE_MASK),              /*!< Parity error flag. bit 15 */
+    kLPUART_Match2InterruptEnable = (LPUART_CTRL_MA2IE_MASK),              /*!< Parity error flag. bit 14 */
 #endif
 #if defined(FSL_FEATURE_LPUART_HAS_FIFO) && FSL_FEATURE_LPUART_HAS_FIFO
     kLPUART_TxFifoOverflowInterruptEnable  = (LPUART_FIFO_TXOFE_MASK), /*!< Transmit FIFO Overflow. bit 9 */
@@ -171,7 +171,7 @@ enum _lpuart_flags
     kLPUART_TxDataRegEmptyFlag =
         (LPUART_STAT_TDRE_MASK), /*!< Transmit data register empty flag, sets when transmit buffer is empty. bit 23 */
     kLPUART_TransmissionCompleteFlag =
-        (LPUART_STAT_TC_MASK), /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */
+        (LPUART_STAT_TC_MASK),   /*!< Transmission complete flag, sets when transmission activity complete. bit 22 */
     kLPUART_RxDataRegFullFlag = (LPUART_STAT_RDRF_MASK), /*!< Receive data register full flag, sets when the receive
                                                             data buffer is full. bit 21 */
     kLPUART_IdleLineFlag  = (LPUART_STAT_IDLE_MASK), /*!< Idle line detect flag, sets when idle line detected. bit 20 */
@@ -183,8 +183,8 @@ enum _lpuart_flags
         (LPUART_STAT_FE_MASK), /*!< Frame error flag, sets if logic 0 was detected where stop bit expected. bit 17 */
     kLPUART_ParityErrorFlag = (LPUART_STAT_PF_MASK), /*!< If parity enabled, sets upon parity error detection. bit 16 */
 #if defined(FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT) && FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT
-    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK), /*!< LIN break detect interrupt flag, sets when LIN break
-                                                         char detected and LIN circuit enabled. bit 31 */
+    kLPUART_LinBreakFlag = (LPUART_STAT_LBKDIF_MASK),      /*!< LIN break detect interrupt flag, sets when LIN break
+                                                              char detected and LIN circuit enabled. bit 31 */
 #endif
     kLPUART_RxActiveEdgeFlag = (LPUART_STAT_RXEDGIF_MASK), /*!< Receive pin active edge interrupt flag, sets when active
                                                               edge detected. bit 30 */
@@ -202,9 +202,9 @@ enum _lpuart_flags
     kLPUART_RxFifoEmptyFlag =
         (LPUART_FIFO_RXEMPT_MASK >> 16), /*!< RXEMPT bit, sets if receive buffer is empty. bit 6 */
     kLPUART_TxFifoOverflowFlag =
-        (LPUART_FIFO_TXOF_MASK >> 16), /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */
+        (LPUART_FIFO_TXOF_MASK >> 16),   /*!< TXOF bit, sets if transmit buffer overflow occurred. bit 1 */
     kLPUART_RxFifoUnderflowFlag =
-        (LPUART_FIFO_RXUF_MASK >> 16), /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */
+        (LPUART_FIFO_RXUF_MASK >> 16),   /*!< RXUF bit, sets if receive buffer underflow occurred. bit 0 */
 #endif
 
     kLPUART_AllClearFlags = kLPUART_RxActiveEdgeFlag | kLPUART_IdleLineFlag | kLPUART_RxOverrunFlag |
@@ -239,10 +239,10 @@ enum _lpuart_flags
 /*! @brief LPUART configuration structure. */
 typedef struct _lpuart_config
 {
-    uint32_t baudRate_Bps;            /*!< LPUART baud rate  */
-    lpuart_parity_mode_t parityMode;  /*!< Parity mode, disabled (default), even, odd */
-    lpuart_data_bits_t dataBitsCount; /*!< Data bits count, eight (default), seven */
-    bool isMsb;                       /*!< Data bits order, LSB (default), MSB */
+    uint32_t baudRate_Bps;                /*!< LPUART baud rate  */
+    lpuart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    lpuart_data_bits_t dataBitsCount;     /*!< Data bits count, eight (default), seven */
+    bool isMsb;                           /*!< Data bits order, LSB (default), MSB */
 #if defined(FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT) && FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT
     lpuart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
 #endif
@@ -256,10 +256,10 @@ typedef struct _lpuart_config
     lpuart_transmit_cts_source_t txCtsSource; /*!< TX CTS source */
     lpuart_transmit_cts_config_t txCtsConfig; /*!< TX CTS configure */
 #endif
-    lpuart_idle_type_select_t rxIdleType; /*!< RX IDLE type. */
-    lpuart_idle_config_t rxIdleConfig;    /*!< RX IDLE configuration. */
-    bool enableTx;                        /*!< Enable TX */
-    bool enableRx;                        /*!< Enable RX */
+    lpuart_idle_type_select_t rxIdleType;     /*!< RX IDLE type. */
+    lpuart_idle_config_t rxIdleConfig;        /*!< RX IDLE configuration. */
+    bool enableTx;                            /*!< Enable TX */
+    bool enableRx;                            /*!< Enable RX */
 } lpuart_config_t;
 
 /*! @brief LPUART transfer structure. */
@@ -271,11 +271,13 @@ typedef struct _lpuart_transfer
      */
     union
     {
-        uint8_t *data;         /*!< The buffer of data to be transfer.*/
-        uint8_t *rxData;       /*!< The buffer to receive data. */
-        const uint8_t *txData; /*!< The buffer of data to be sent. */
+        uint8_t *data;            /*!< The buffer of data to be transfer.*/
+        uint8_t *rxData;          /*!< The buffer to receive data. */
+        uint16_t *rxData16;       /*!< The buffer to receive data. */
+        const uint8_t *txData;    /*!< The buffer of data to be sent. */
+        const uint16_t *txData16; /*!< The buffer of data to be sent. */
     };
-    size_t dataSize; /*!< The byte count to be transfer. */
+    size_t dataSize;              /*!< The byte count to be transfer. */
 } lpuart_transfer_t;
 
 /* Forward declaration of the handle typedef. */
@@ -287,27 +289,40 @@ typedef void (*lpuart_transfer_callback_t)(LPUART_Type *base, lpuart_handle_t *h
 /*! @brief LPUART handle structure. */
 struct _lpuart_handle
 {
-    const uint8_t *volatile txData; /*!< Address of remaining data to send. */
-    volatile size_t txDataSize;     /*!< Size of the remaining data to send. */
-    size_t txDataSizeAll;           /*!< Size of the data to send out. */
-    uint8_t *volatile rxData;       /*!< Address of remaining data to receive. */
-    volatile size_t rxDataSize;     /*!< Size of the remaining data to receive. */
-    size_t rxDataSizeAll;           /*!< Size of the data to receive. */
-
-    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
-    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
-    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
-    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+    union
+    {
+        const uint8_t *volatile txData;    /*!< Address of remaining data to send. */
+        const uint16_t *volatile txData16; /*!< Address of remaining data to send. */
+    };
+    volatile size_t txDataSize;            /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;                  /*!< Size of the data to send out. */
+    union
+    {
+        uint8_t *volatile rxData;    /*!< Address of remaining data to receive. */
+        uint16_t *volatile rxData16; /*!< Address of remaining data to receive. */
+    };
+    volatile size_t rxDataSize;      /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;            /*!< Size of the data to receive. */
+
+    union
+    {
+        uint8_t *rxRingBuffer;           /*!< Start address of the receiver ring buffer. */
+        uint16_t *rxRingBuffer16;        /*!< Start address of the receiver ring buffer. */
+    };
+    size_t rxRingBufferSize;             /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead;  /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail;  /*!< Index for the user to get data from the ring buffer. */
 
     lpuart_transfer_callback_t callback; /*!< Callback function. */
     void *userData;                      /*!< LPUART callback function parameter.*/
 
-    volatile uint8_t txState; /*!< TX transfer state. */
-    volatile uint8_t rxState; /*!< RX transfer state. */
+    volatile uint8_t txState;            /*!< TX transfer state. */
+    volatile uint8_t rxState;            /*!< RX transfer state. */
 
 #if defined(FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT) && FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT
     bool isSevenDataBits; /*!< Seven data bits flag. */
 #endif
+    bool is16bitData;     /*!< 16bit data bits flag, only used for 9bit or 10bit data */
 };
 
 /* Typedef for interrupt handler. */
@@ -357,7 +372,7 @@ static inline void LPUART_SoftwareReset(LPUART_Type *base)
     base->GLOBAL |= LPUART_GLOBAL_RST_MASK;
     base->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
 }
-/* @} */
+/*! @} */
 #endif /*FSL_FEATURE_LPUART_HAS_GLOBAL*/
 
 /*!
@@ -420,7 +435,7 @@ void LPUART_Deinit(LPUART_Type *base);
  * @param config Pointer to a configuration structure.
  */
 void LPUART_GetDefaultConfig(lpuart_config_t *config);
-/* @} */
+/*! @} */
 
 /*!
  * @name Module configuration
@@ -531,7 +546,20 @@ static inline void LPUART_SetTxFifoWatermark(LPUART_Type *base, uint8_t water)
     base->WATER = (base->WATER & ~LPUART_WATER_TXWATER_MASK) | LPUART_WATER_TXWATER(water);
 }
 #endif
-/* @} */
+
+/*!
+ * @brief Sets the LPUART using 16bit transmit, only for 9bit or 10bit mode.
+ *
+ * This function Enable 16bit Data transmit in lpuart_handle_t.
+ *
+ * @param handle LPUART handle pointer.
+ * @param enable true to enable, false to disable.
+ */
+static inline void LPUART_TransferEnable16Bit(lpuart_handle_t *handle, bool enable)
+{
+    handle->is16bitData = enable;
+}
+/*! @} */
 
 /*!
  * @name Status
@@ -577,7 +605,7 @@ uint32_t LPUART_GetStatusFlags(LPUART_Type *base);
  * @retval kStatus_Success Status in the mask are cleared.
  */
 status_t LPUART_ClearStatusFlags(LPUART_Type *base, uint32_t mask);
-/* @} */
+/*! @} */
 
 /*!
  * @name Interrupts
@@ -635,7 +663,7 @@ void LPUART_DisableInterrupts(LPUART_Type *base, uint32_t mask);
  * @return LPUART interrupt flags which are logical OR of the enumerators in @ref _lpuart_interrupt_enable.
  */
 uint32_t LPUART_GetEnabledInterrupts(LPUART_Type *base);
-/* @} */
+/*! @} */
 
 #if defined(FSL_FEATURE_LPUART_HAS_DMA_ENABLE) && FSL_FEATURE_LPUART_HAS_DMA_ENABLE
 /*!
@@ -694,7 +722,7 @@ static inline void LPUART_EnableRxDMA(LPUART_Type *base, bool enable)
         base->BAUD &= ~LPUART_BAUD_RDMAE_MASK;
     }
 }
-/* @} */
+/*! @} */
 #endif /* FSL_FEATURE_LPUART_HAS_DMA_ENABLE */
 
 /*!
@@ -848,6 +876,20 @@ void LPUART_SendAddress(LPUART_Type *base, uint8_t address);
  */
 status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t length);
 
+/*!
+ * @brief Writes to the transmitter register using a blocking method in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *       Please make sure only 10bit of data is valid and other bits are 0.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully wrote all data.
+ */
+status_t LPUART_WriteBlocking16bit(LPUART_Type *base, const uint16_t *data, size_t length);
+
 /*!
  * @brief Reads the receiver data register using a blocking method.
  *
@@ -866,7 +908,24 @@ status_t LPUART_WriteBlocking(LPUART_Type *base, const uint8_t *data, size_t len
  */
 status_t LPUART_ReadBlocking(LPUART_Type *base, uint8_t *data, size_t length);
 
-/* @} */
+/*!
+ * @brief Reads the receiver data register in 9bit or 10bit mode.
+ *
+ * @note This function only support 9bit or 10bit transfer.
+ *
+ * @param base LPUART peripheral base address.
+ * @param data Start address of the buffer to store the received data by 16bit, only 10bit is valid.
+ * @param length Size of the buffer.
+ * @retval kStatus_LPUART_RxHardwareOverrun Receiver overrun happened while receiving data.
+ * @retval kStatus_LPUART_NoiseError Noise error happened while receiving data.
+ * @retval kStatus_LPUART_FramingError Framing error happened while receiving data.
+ * @retval kStatus_LPUART_ParityError Parity error happened while receiving data.
+ * @retval kStatus_LPUART_Timeout Transmission timed out and was aborted.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t LPUART_ReadBlocking16bit(LPUART_Type *base, uint16_t *data, size_t length);
+
+/*! @} */
 
 /*!
  * @name Transactional
@@ -1058,7 +1117,7 @@ void LPUART_TransferHandleIRQ(LPUART_Type *base, void *irqHandle);
  */
 void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle);
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -1066,4 +1125,4 @@ void LPUART_TransferHandleErrorIRQ(LPUART_Type *base, void *irqHandle);
 
 /*! @}*/
 
-#endif /* _FSL_LPUART_H_ */
+#endif /* FSL_LPUART_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_lpuart_edma.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_LPUART_EDMA_H_
-#define _FSL_LPUART_EDMA_H_
+#ifndef FSL_LPUART_EDMA_H_
+#define FSL_LPUART_EDMA_H_
 
 #include "fsl_lpuart.h"
 #include "fsl_edma.h"
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief LPUART EDMA driver version. */
 #define FSL_LPUART_EDMA_DRIVER_VERSION (MAKE_VERSION(2, 6, 0))
-/*@}*/
+/*! @} */
 
 /* Forward declaration of the handle typedef. */
 typedef struct _lpuart_edma_handle lpuart_edma_handle_t;
@@ -178,7 +178,7 @@ status_t LPUART_TransferGetReceiveCountEDMA(LPUART_Type *base, lpuart_edma_handl
  */
 void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -186,4 +186,4 @@ void LPUART_TransferEdmaHandleIRQ(LPUART_Type *base, void *lpuartEdmaHandle);
 
 /*! @}*/
 
-#endif /* _FSL_LPUART_EDMA_H_ */
+#endif /* FSL_LPUART_EDMA_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_ostimer.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2018-2021 NXP
+ * Copyright 2018-2021, 2023 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -375,20 +375,10 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb)
     }
 }
 
-#if defined(OSTIMER0)
 void OS_EVENT_DriverIRQHandler(void);
 void OS_EVENT_DriverIRQHandler(void)
 {
-    s_ostimerIsr(OSTIMER0, s_ostimerHandle[0]);
+    s_ostimerIsr(s_ostimerBases[0], s_ostimerHandle[0]);
     SDK_ISR_EXIT_BARRIER;
 }
-#endif
 
-#if defined(OSTIMER)
-void OS_EVENT_DriverIRQHandler(void);
-void OS_EVENT_DriverIRQHandler(void)
-{
-    s_ostimerIsr(OSTIMER, s_ostimerHandle[0]);
-    SDK_ISR_EXIT_BARRIER;
-}
-#endif

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_ostimer.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_OSTIMER_H_
-#define _FSL_OSTIMER_H_
+#ifndef FSL_OSTIMER_H_
+#define FSL_OSTIMER_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief OSTIMER driver version. */
-#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
-/*@}*/
+#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*! @} */
 
 /*!
  * @brief OSTIMER status flags.
@@ -149,7 +149,7 @@ status_t OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callb
  * value to gray code.
  *
  * @param base   OSTIMER peripheral base address.
- * @param count  OSTIMER timer match value (Value is gray-code format).
+ * @param value  OSTIMER timer match value (Value is gray-code format).
  */
 static inline void OSTIMER_SetMatchRegister(OSTIMER_Type *base, uint64_t value)
 {
@@ -262,7 +262,7 @@ uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base);
  * @return       none
  */
 void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb);
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -270,4 +270,4 @@ void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb);
 
 /*! @}*/
 
-#endif /* _FSL_OSTIMER_H_ */
+#endif /* FSL_OSTIMER_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_port.h

@@ -1,12 +1,12 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * Copyright 2016-2022 NXP
+ * Copyright 2016-2022, 2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_PORT_H_
-#define _FSL_PORT_H_
+#ifndef FSL_PORT_H_
+#define FSL_PORT_H_
 
 #include "fsl_common.h"
 
@@ -25,10 +25,10 @@
 #endif
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief PORT driver version. */
-#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
-/*@}*/
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 5, 0))
+/*! @} */
 
 #if defined(FSL_FEATURE_PORT_HAS_PULL_ENABLE) && FSL_FEATURE_PORT_HAS_PULL_ENABLE
 /*! @brief Internal resistor pull feature selection */
@@ -125,8 +125,12 @@ enum _port_lock_register
 /*! @brief Pin mux selection */
 typedef enum _port_mux
 {
+#if defined(FSL_FEATURE_PORT_PCR_MUX_GPIO) && (FSL_FEATURE_PORT_PCR_MUX_GPIO == 0)
+    kPORT_MuxAsGpio           = 0U,  /*!< Corresponding pin is configured as GPIO. */
+#else
     kPORT_PinDisabledOrAnalog = 0U,  /*!< Corresponding pin is disabled, but is used as an analog pin. */
     kPORT_MuxAsGpio           = 1U,  /*!< Corresponding pin is configured as GPIO. */
+#endif
     kPORT_MuxAlt0             = 0U,  /*!< Chip-specific */
     kPORT_MuxAlt1             = 1U,  /*!< Chip-specific */
     kPORT_MuxAlt2             = 2U,  /*!< Chip-specific */
@@ -295,9 +299,10 @@ typedef enum _port_voltage_range
 extern "C" {
 #endif
 
-#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 /*! @name Configuration */
-/*@{*/
+/*! @{ */
+
+#if defined(FSL_FEATURE_PORT_PCR_MUX_WIDTH) && FSL_FEATURE_PORT_PCR_MUX_WIDTH
 
 #if defined(FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER) && FSL_FEATURE_PORT_HAS_VERSION_INFO_REGISTER
 /*!
@@ -497,10 +502,10 @@ static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digit
 }
 
 #endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
-/*@}*/
+/*! @} */
 
 /*! @name Interrupt */
-/*@{*/
+/*! @{ */
 
 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
 /*!
@@ -668,7 +673,7 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
 }
 #endif /* FSL_FEATURE_PORT_SUPPORT_EFT */
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -676,4 +681,4 @@ static inline void PORT_ClearAllHighEFTDetectors(PORT_Type *base)
 
 /*! @}*/
 
-#endif /* _FSL_PORT_H_ */
+#endif /* FSL_PORT_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_pwm.c

@@ -93,6 +93,165 @@ static uint32_t PWM_GetInstance(PWM_Type *base)
     return instance;
 }
 
+/*!
+ * brief Set register about period on one PWM submodule.
+ *
+ * param base        PWM peripheral base address
+ * param subModule   PWM submodule to configure
+ * param mode        PWM operation mode, options available in enumeration ::pwm_mode_t
+ * param pulseCnt    PWM period, value should be between 0 to 65535
+ */
+static void PWM_SetPeriodRegister(PWM_Type *base, pwm_submodule_t subModule, pwm_mode_t mode, uint16_t pulseCnt)
+{
+    uint16_t modulo = 0;
+
+    switch (mode)
+    {
+        case kPWM_SignedCenterAligned:
+            /* Setup the PWM period for a signed center aligned signal */
+            modulo = (pulseCnt >> 1U);
+            /* Indicates the start of the PWM period */
+            base->SM[subModule].INIT = PWM_GetComplementU16(modulo);
+            /* Indicates the center value */
+            base->SM[subModule].VAL0 = 0;
+            /* Indicates the end of the PWM period */
+            /* The change during the end to start of the PWM period requires a count time */
+            base->SM[subModule].VAL1 = modulo - 1U;
+            break;
+        case kPWM_CenterAligned:
+            /* Setup the PWM period for an unsigned center aligned signal */
+            /* Indicates the start of the PWM period */
+            base->SM[subModule].INIT = 0;
+            /* Indicates the center value */
+            base->SM[subModule].VAL0 = (pulseCnt / 2U);
+            /* Indicates the end of the PWM period */
+            /* The change during the end to start of the PWM period requires a count time */
+            base->SM[subModule].VAL1 = pulseCnt - 1U;
+            break;
+        case kPWM_SignedEdgeAligned:
+            /* Setup the PWM period for a signed edge aligned signal */
+            modulo = (pulseCnt >> 1U);
+            /* Indicates the start of the PWM period */
+            base->SM[subModule].INIT = PWM_GetComplementU16(modulo);
+            /* Indicates the center value */
+            base->SM[subModule].VAL0 = 0;
+            /* Indicates the end of the PWM period */
+            /* The change during the end to start of the PWM period requires a count time */
+            base->SM[subModule].VAL1 = modulo - 1U;
+            break;
+        case kPWM_EdgeAligned:
+            /* Setup the PWM period for a unsigned edge aligned signal */
+            /* Indicates the start of the PWM period */
+            base->SM[subModule].INIT = 0;
+            /* Indicates the center value */
+            base->SM[subModule].VAL0 = (pulseCnt / 2U);
+            /* Indicates the end of the PWM period */
+            /* The change during the end to start of the PWM period requires a count time */
+            base->SM[subModule].VAL1 = pulseCnt - 1U;
+            break;
+        default:
+            assert(false);
+            break;
+    }
+}
+
+/*!
+ * brief Set register about dutycycle on one PWM submodule.
+ *
+ * param base        PWM peripheral base address
+ * param subModule   PWM submodule to configure
+ * param pwmSignal   Signal (PWM A or PWM B) to update
+ * param mode        PWM operation mode, options available in enumeration ::pwm_mode_t
+ * param pulseCnt    PWM period, value should be between 0 to 65535
+ * param dutyCycle         New PWM pulse width, value should be between 0 to 65535
+ */
+static void PWM_SetDutycycleRegister(PWM_Type *base,
+                                     pwm_submodule_t subModule,
+                                     pwm_channels_t pwmSignal,
+                                     pwm_mode_t mode,
+                                     uint16_t pulseCnt,
+                                     uint16_t pwmHighPulse)
+{
+    uint16_t modulo = 0;
+
+    switch (mode)
+    {
+        case kPWM_SignedCenterAligned:
+            /* Setup the PWM dutycycle for a signed center aligned signal */
+            if (pwmSignal == kPWM_PwmA)
+            {
+                base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U);
+                base->SM[subModule].VAL3 = (pwmHighPulse / 2U);
+            }
+            else if (pwmSignal == kPWM_PwmB)
+            {
+                base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U);
+                base->SM[subModule].VAL5 = (pwmHighPulse / 2U);
+            }
+            else
+            {
+                ; /* Intentional empty */
+            }
+            break;
+        case kPWM_CenterAligned:
+            /* Setup the PWM dutycycle for an unsigned center aligned signal */
+            if (pwmSignal == kPWM_PwmA)
+            {
+                base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U);
+                base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U);
+            }
+            else if (pwmSignal == kPWM_PwmB)
+            {
+                base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U);
+                base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U);
+            }
+            else
+            {
+                ; /* Intentional empty */
+            }
+            break;
+        case kPWM_SignedEdgeAligned:
+            modulo = (pulseCnt >> 1U);
+
+            /* Setup the PWM dutycycle for a signed edge aligned signal */
+            if (pwmSignal == kPWM_PwmA)
+            {
+                base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo);
+                base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse;
+            }
+            else if (pwmSignal == kPWM_PwmB)
+            {
+                base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo);
+                base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse;
+            }
+            else
+            {
+                ; /* Intentional empty */
+            }
+            break;
+        case kPWM_EdgeAligned:
+            /* Setup the PWM dutycycle for a unsigned edge aligned signal */
+            if (pwmSignal == kPWM_PwmA)
+            {
+                base->SM[subModule].VAL2 = 0;
+                base->SM[subModule].VAL3 = pwmHighPulse;
+            }
+            else if (pwmSignal == kPWM_PwmB)
+            {
+                base->SM[subModule].VAL4 = 0;
+                base->SM[subModule].VAL5 = pwmHighPulse;
+            }
+            else
+            {
+                ; /* Intentional empty */
+            }
+            break;
+        default:
+            assert(false);
+            break;
+    }
+}
+
 /*!
  * brief Ungates the PWM submodule clock and configures the peripheral for basic operation.
  *
@@ -201,7 +360,12 @@ status_t PWM_Init(PWM_Type *base, pwm_submodule_t subModule, const pwm_config_t
     base->SM[subModule].CTRL = reg;
 
     /* Set PWM output normal */
+#if defined(PWM_MASK_UPDATE_MASK)
+    base->MASK &= (uint16_t)(~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK |
+                                         PWM_MASK_UPDATE_MASK_MASK));
+#else
     base->MASK &= ~(uint16_t)(PWM_MASK_MASKX_MASK | PWM_MASK_MASKA_MASK | PWM_MASK_MASKB_MASK);
+#endif
 
     base->DTSRCSEL = 0U;
 
@@ -297,7 +461,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config)
  *                    Array size should not be more than 2 as each submodule has 2 pins to output PWM
  * param mode        PWM operation mode, options available in enumeration ::pwm_mode_t
  * param pwmFreq_Hz  PWM signal frequency in Hz
- * param srcClock_Hz PWM main counter clock in Hz.
+ * param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from
+ *                   submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0
+ *                   prescaler value instead of submodule0 source clock.
  *
  * return Returns kStatusFail if there was error setting up the signal; kStatusSuccess otherwise
  */
@@ -316,7 +482,6 @@ status_t PWM_SetupPwm(PWM_Type *base,
 
     uint32_t pwmClock;
     uint16_t pulseCnt = 0, pwmHighPulse = 0;
-    uint16_t modulo = 0;
     uint8_t i, polarityShift = 0, outputEnableShift = 0;
 
     for (i = 0; i < numOfChnls; i++)
@@ -339,114 +504,15 @@ status_t PWM_SetupPwm(PWM_Type *base,
         pwmHighPulse = (pulseCnt * chnlParams->dutyCyclePercent) / 100U;
 
         /* Setup the different match registers to generate the PWM signal */
-        switch (mode)
+        if (i == 0U)
         {
-            case kPWM_SignedCenterAligned:
-                /* Setup the PWM period for a signed center aligned signal */
-                if (i == 0U)
-                {
-                    modulo = (pulseCnt >> 1U);
-                    /* Indicates the start of the PWM period */
-                    base->SM[subModule].INIT = PWM_GetComplementU16(modulo);
-                    /* Indicates the center value */
-                    base->SM[subModule].VAL0 = 0;
-                    /* Indicates the end of the PWM period */
-                    /* The change during the end to start of the PWM period requires a count time */
-                    base->SM[subModule].VAL1 = modulo - 1U;
-                }
-
-                /* Setup the PWM dutycycle */
-                if (chnlParams->pwmChannel == kPWM_PwmA)
-                {
-                    base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U);
-                    base->SM[subModule].VAL3 = (pwmHighPulse / 2U);
-                }
-                else
-                {
-                    base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U);
-                    base->SM[subModule].VAL5 = (pwmHighPulse / 2U);
-                }
-                break;
-            case kPWM_CenterAligned:
-                /* Setup the PWM period for an unsigned center aligned signal */
-                /* Indicates the start of the PWM period */
-                if (i == 0U)
-                {
-                    base->SM[subModule].INIT = 0;
-                    /* Indicates the center value */
-                    base->SM[subModule].VAL0 = (pulseCnt / 2U);
-                    /* Indicates the end of the PWM period */
-                    /* The change during the end to start of the PWM period requires a count time */
-                    base->SM[subModule].VAL1 = pulseCnt - 1U;
-                }
-
-                /* Setup the PWM dutycycle */
-                if (chnlParams->pwmChannel == kPWM_PwmA)
-                {
-                    base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U);
-                    base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U);
-                }
-                else
-                {
-                    base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U);
-                    base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U);
-                }
-                break;
-            case kPWM_SignedEdgeAligned:
-                /* Setup the PWM period for a signed edge aligned signal */
-                if (i == 0U)
-                {
-                    modulo = (pulseCnt >> 1U);
-                    /* Indicates the start of the PWM period */
-                    base->SM[subModule].INIT = PWM_GetComplementU16(modulo);
-                    /* Indicates the center value */
-                    base->SM[subModule].VAL0 = 0;
-                    /* Indicates the end of the PWM period */
-                    /* The change during the end to start of the PWM period requires a count time */
-                    base->SM[subModule].VAL1 = modulo - 1U;
-                }
-
-                /* Setup the PWM dutycycle */
-                if (chnlParams->pwmChannel == kPWM_PwmA)
-                {
-                    base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo);
-                    base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse;
-                }
-                else
-                {
-                    base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo);
-                    base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse;
-                }
-                break;
-            case kPWM_EdgeAligned:
-                /* Setup the PWM period for a unsigned edge aligned signal */
-                /* Indicates the start of the PWM period */
-                if (i == 0U)
-                {
-                    base->SM[subModule].INIT = 0;
-                    /* Indicates the center value */
-                    base->SM[subModule].VAL0 = (pulseCnt / 2U);
-                    /* Indicates the end of the PWM period */
-                    /* The change during the end to start of the PWM period requires a count time */
-                    base->SM[subModule].VAL1 = pulseCnt - 1U;
-                }
-
-                /* Setup the PWM dutycycle */
-                if (chnlParams->pwmChannel == kPWM_PwmA)
-                {
-                    base->SM[subModule].VAL2 = 0;
-                    base->SM[subModule].VAL3 = pwmHighPulse;
-                }
-                else
-                {
-                    base->SM[subModule].VAL4 = 0;
-                    base->SM[subModule].VAL5 = pwmHighPulse;
-                }
-                break;
-            default:
-                assert(false);
-                break;
+            /* Update register about period */
+            PWM_SetPeriodRegister(base, subModule, mode, pulseCnt);
         }
+
+        /* Update register about dutycycle */
+        PWM_SetDutycycleRegister(base, subModule, chnlParams->pwmChannel, mode, pulseCnt, pwmHighPulse);
+
         /* Setup register shift values based on the channel being configured.
          * Also setup the deadtime value
          */
@@ -653,98 +719,96 @@ void PWM_UpdatePwmDutycycleHighAccuracy(
             pulseCnt = modulo * 2U;
             /* Calculate pulse width */
             pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
-
-            /* Setup the PWM dutycycle */
-            if (pwmSignal == kPWM_PwmA)
-            {
-                base->SM[subModule].VAL2 = PWM_GetComplementU16(pwmHighPulse / 2U);
-                base->SM[subModule].VAL3 = (pwmHighPulse / 2U);
-            }
-            else if (pwmSignal == kPWM_PwmB)
-            {
-                base->SM[subModule].VAL4 = PWM_GetComplementU16(pwmHighPulse / 2U);
-                base->SM[subModule].VAL5 = (pwmHighPulse / 2U);
-            }
-            else
-            {
-                assert(false);
-            }
             break;
         case kPWM_CenterAligned:
             pulseCnt = base->SM[subModule].VAL1 + 1U;
             /* Calculate pulse width */
             pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
-
-            /* Setup the PWM dutycycle */
-            if (pwmSignal == kPWM_PwmA)
-            {
-                base->SM[subModule].VAL2 = ((pulseCnt - pwmHighPulse) / 2U);
-                base->SM[subModule].VAL3 = ((pulseCnt + pwmHighPulse) / 2U);
-            }
-            else if (pwmSignal == kPWM_PwmB)
-            {
-                base->SM[subModule].VAL4 = ((pulseCnt - pwmHighPulse) / 2U);
-                base->SM[subModule].VAL5 = ((pulseCnt + pwmHighPulse) / 2U);
-            }
-            else
-            {
-                assert(false);
-            }
             break;
         case kPWM_SignedEdgeAligned:
             modulo   = base->SM[subModule].VAL1 + 1U;
             pulseCnt = modulo * 2U;
             /* Calculate pulse width */
             pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
-
-            /* Setup the PWM dutycycle */
-            if (pwmSignal == kPWM_PwmA)
-            {
-                base->SM[subModule].VAL2 = PWM_GetComplementU16(modulo);
-                base->SM[subModule].VAL3 = PWM_GetComplementU16(modulo) + pwmHighPulse;
-            }
-            else if (pwmSignal == kPWM_PwmB)
-            {
-                base->SM[subModule].VAL4 = PWM_GetComplementU16(modulo);
-                base->SM[subModule].VAL5 = PWM_GetComplementU16(modulo) + pwmHighPulse;
-            }
-            else
-            {
-                assert(false);
-            }
             break;
         case kPWM_EdgeAligned:
             pulseCnt = base->SM[subModule].VAL1 + 1U;
             /* Calculate pulse width */
             pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
-
-            /* Setup the PWM dutycycle */
-            if (pwmSignal == kPWM_PwmA)
-            {
-                base->SM[subModule].VAL2 = 0;
-                base->SM[subModule].VAL3 = pwmHighPulse;
-            }
-            else if (pwmSignal == kPWM_PwmB)
-            {
-                base->SM[subModule].VAL4 = 0;
-                base->SM[subModule].VAL5 = pwmHighPulse;
-            }
-            else
-            {
-                assert(false);
-            }
             break;
         default:
             assert(false);
             break;
     }
+
+    /* Update register about dutycycle */
+    if (kPWM_PwmA == pwmSignal)
+    {
+        PWM_SetDutycycleRegister(base, subModule, kPWM_PwmA, currPwmMode, pulseCnt, pwmHighPulse);
+    }
+    else if (kPWM_PwmB == pwmSignal)
+    {
+        PWM_SetDutycycleRegister(base, subModule, kPWM_PwmB, currPwmMode, pulseCnt, pwmHighPulse);
+    }
+    else
+    {
+        ; /* Intentional empty */
+    }
+
     if (kPWM_PwmX != pwmSignal)
     {
         /* Get the pwm duty cycle */
-        s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle / 65535U);
+        s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)(dutyCycle * 100U / 65535U);
     }
 }
 
+/*!
+ * brief Update the PWM signal's period and dutycycle for a PWM submodule.
+ *
+ * The function updates PWM signal period generated by a specific submodule according to the parameters
+ * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle
+ * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by
+ * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function
+ * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register
+ * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time
+ * period specified by the user. PWM signal will not be generated if its period is less than dead time duration.
+ *
+ * param base        PWM peripheral base address
+ * param subModule   PWM submodule to configure
+ * param pwmSignal   Signal (PWM A or PWM B) to update
+ * param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t
+ * param pulseCnt    New PWM period, value should be between 0 to 65535
+ *                    0=minimum PWM period...
+ *                    65535=maximum PWM period
+ * param dutyCycle   New PWM pulse width of channel, value should be between 0 to 65535
+ *                    0=inactive signal(0% duty cycle)...
+ *                    65535=active signal (100% duty cycle)
+ *                    You can keep original dutycycle or update new dutycycle
+ */
+void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base,
+                                     pwm_submodule_t subModule,
+                                     pwm_channels_t pwmSignal,
+                                     pwm_mode_t currPwmMode,
+                                     uint16_t pulseCnt,
+                                     uint16_t dutyCycle)
+{
+    uint16_t pwmHighPulse = 0;
+
+    assert(pwmSignal != kPWM_PwmX);
+
+    /* Calculate pulse width */
+    pwmHighPulse = (pulseCnt * dutyCycle) / 65535U;
+
+    /* Update register about period */
+    PWM_SetPeriodRegister(base, subModule, currPwmMode, pulseCnt);
+
+    /* Update register about dutycycle */
+    PWM_SetDutycycleRegister(base, subModule, pwmSignal, currPwmMode, pulseCnt, pwmHighPulse);
+
+    /* Get the pwm duty cycle */
+    s_pwmGetPwmDutyCycle[subModule][pwmSignal] = (uint8_t)((dutyCycle * 100U) / 65535U);
+}
+
 /*!
  * brief Sets up the PWM input capture
  *
@@ -1236,7 +1300,9 @@ void PWM_SetClockMode(PWM_Type *base, pwm_submodule_t subModule, pwm_clock_presc
  */
 void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmChannel, bool forcetozero)
 {
+#if !defined(PWM_MASK_UPDATE_MASK)
     uint16_t reg = base->SM[subModule].CTRL2;
+#endif
     uint16_t mask;
 
     if (kPWM_PwmA == pwmChannel)
@@ -1263,12 +1329,17 @@ void PWM_SetPwmForceOutputToZero(PWM_Type *base, pwm_submodule_t subModule, pwm_
         base->MASK &= ~mask;
     }
 
+#if defined(PWM_MASK_UPDATE_MASK)
+    /* Update output mask bits immediately with UPDATE_MASK bit */
+    base->MASK |= PWM_MASK_UPDATE_MASK(0x01UL << (uint8_t)subModule);
+#else
     /* Select local force signal */
     base->SM[subModule].CTRL2 &= ~(uint16_t)PWM_CTRL2_FORCE_SEL_MASK;
     /* Issue a local Force trigger event */
     base->SM[subModule].CTRL2 |= PWM_CTRL2_FORCE_MASK;
     /* Restore the source of FORCE OUTPUT signal */
     base->SM[subModule].CTRL2 = reg;
+#endif
 }
 
 /*!
@@ -1366,24 +1437,49 @@ status_t PWM_SetPhaseDelay(PWM_Type *base, pwm_channels_t pwmChannel, pwm_submod
 {
     assert(subModule != kPWM_Module_0);
     uint16_t reg = base->SM[subModule].CTRL2;
-    
+
     /* Clear LDOK bit if it is set */
     if (0U != (base->MCTRL & PWM_MCTRL_LDOK(1UL << (uint8_t)subModule)))
     {
         base->MCTRL |= PWM_MCTRL_CLDOK(1UL << (uint8_t)subModule);
     }
-    
-    if(base->SM[kPWM_Module_0].VAL1 < delayCycles)
+
+    if (base->SM[kPWM_Module_0].VAL1 < delayCycles)
     {
         return kStatus_Fail;
     }
     else
     {
+        /*
+         * ERR051989: When the value of the phase delay register SMxPHASEDLY is reduced from a
+         * non-zero value to 0 and submodule x reload source is from submodule0, the submodule
+         * x may output an unexpected wide PWM pulse. The workaround is set SMxPHASEDLY=1,
+         * SMxINIT=SM0INIT-1, SMxVALy=SM0VALy-1 (x=1,2,3, y=0,1,2,3,4,5).
+         */
+#if defined(FSL_FEATURE_PWM_HAS_ERRATA_51989) && FSL_FEATURE_PWM_HAS_ERRATA_51989
+        if (delayCycles == 0 &&
+            ((base->SM[subModule].CTRL2 & PWM_CTRL2_RELOAD_SEL_MASK) >> PWM_CTRL2_RELOAD_SEL_SHIFT) == 1U)
+        {
+            base->SM[subModule].PHASEDLY = 1U;
+            base->SM[subModule].INIT     = base->SM[0].INIT - 1U;
+            base->SM[subModule].VAL0     = base->SM[0].VAL0 - 1U;
+            base->SM[subModule].VAL1     = base->SM[0].VAL1 - 1U;
+            base->SM[subModule].VAL2     = base->SM[0].VAL2 - 1U;
+            base->SM[subModule].VAL3     = base->SM[0].VAL3 - 1U;
+            base->SM[subModule].VAL4     = base->SM[0].VAL4 - 1U;
+            base->SM[subModule].VAL5     = base->SM[0].VAL5 - 1U;
+        }
+        else
+        {
+            base->SM[subModule].PHASEDLY = delayCycles;
+        }
+#else
         base->SM[subModule].PHASEDLY = delayCycles;
+#endif
     }
-    
+
     /* Select the master sync signal as the source for initialization */
-    reg = (reg & ~(uint16_t)PWM_CTRL2_INIT_SEL_MASK)| PWM_CTRL2_INIT_SEL(2);
+    reg = (reg & ~(uint16_t)PWM_CTRL2_INIT_SEL_MASK) | PWM_CTRL2_INIT_SEL(2);
     /* Set Load mode to make Buffered registers take effect immediately when LDOK bit set */
     base->SM[subModule].CTRL |= PWM_CTRL_LDMOD_MASK;
     /* Set LDOK bit to load buffer registers */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_pwm.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_PWM_H_
-#define _FSL_PWM_H_
+#ifndef FSL_PWM_H_
+#define FSL_PWM_H_
 
 #include "fsl_common.h"
 
@@ -19,9 +19,9 @@
  * Definitions
  ******************************************************************************/
 /*! @name Driver version */
-/*@{*/
-#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 7, 1)) /*!< Version 2.7.1 */
-/*@}*/
+/*! @{ */
+#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 8, 4)) /*!< Version 2.8.4 */
+/*! @} */
 
 /*! Number of bits per submodule for software output control */
 #define PWM_SUBMODULE_SWCONTROL_WIDTH 2
@@ -508,7 +508,9 @@ void PWM_GetDefaultConfig(pwm_config_t *config);
  *                    Array size should not be more than 2 as each submodule has 2 pins to output PWM
  * @param mode        PWM operation mode, options available in enumeration ::pwm_mode_t
  * @param pwmFreq_Hz  PWM signal frequency in Hz
- * @param srcClock_Hz PWM main counter clock in Hz.
+ * @param srcClock_Hz PWM source clock of correspond submodule in Hz. If source clock of submodule1,2,3 is from
+ *                    submodule0 AUX_CLK, its source clock is submodule0 source clock divided with submodule0
+ *                    prescaler value instead of submodule0 source clock.
  *
  * @return Returns kStatus_Fail if there was error setting up the signal; kStatus_Success otherwise
  */
@@ -521,14 +523,14 @@ status_t PWM_SetupPwm(PWM_Type *base,
                       uint32_t srcClock_Hz);
 
 /*!
- * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle..
+ * @brief Set PWM phase shift for PWM channel running on channel PWM_A, PWM_B which with 50% duty cycle.
  *
  * @param base        PWM peripheral base address
  * @param subModule   PWM submodule to configure
  * @param pwmChannel  PWM channel to configure
  * @param pwmFreq_Hz  PWM signal frequency in Hz
  * @param srcClock_Hz PWM main counter clock in Hz.
- * @param shiftvalue  Phase shift value
+ * @param shiftvalue  Phase shift value, range in 0 ~ 50
  * @param doSync      true: Set LDOK bit for the submodule list;
  *                    false: LDOK bit don't set, need to call PWM_SetPwmLdok to sync update.
  *
@@ -581,6 +583,36 @@ void PWM_UpdatePwmDutycycle(PWM_Type *base,
 void PWM_UpdatePwmDutycycleHighAccuracy(
     PWM_Type *base, pwm_submodule_t subModule, pwm_channels_t pwmSignal, pwm_mode_t currPwmMode, uint16_t dutyCycle);
 
+/*!
+ * @brief Update the PWM signal's period and dutycycle for a PWM submodule.
+ *
+ * The function updates PWM signal period generated by a specific submodule according to the parameters
+ * passed in by the user. This function can also set dutycycle weather you want to keep original dutycycle
+ * or update new dutycycle. Call this function in local sync control mode because PWM period is depended by  
+ * INIT and VAL1 register of each submodule. In master sync initialization control mode, call this function 
+ * to update INIT and VAL1 register of all submodule because PWM period is depended by INIT and VAL1 register
+ * in submodule0. If the dead time insertion logic is enabled, the pulse period is reduced by the dead time 
+ * period specified by the user. PWM signal will not be generated if its period is less than dead time duration.
+ *
+ * @param base        PWM peripheral base address
+ * @param subModule   PWM submodule to configure
+ * @param pwmSignal   Signal (PWM A or PWM B) to update
+ * @param currPwmMode The current PWM mode set during PWM setup, options available in enumeration ::pwm_mode_t
+ * @param pulseCnt    New PWM period, value should be between 0 to 65535
+ *                    0=minimum PWM period...
+ *                    65535=maximum PWM period
+ * @param dutyCycle   New PWM pulse width of channel, value should be between 0 to 65535
+ *                    0=inactive signal(0% duty cycle)...
+ *                    65535=active signal (100% duty cycle)
+ *                    You can keep original duty cycle or update new duty cycle
+ */
+void PWM_UpdatePwmPeriodAndDutycycle(PWM_Type *base,
+                                         pwm_submodule_t subModule,
+                                         pwm_channels_t pwmSignal,
+                                         pwm_mode_t currPwmMode,
+                                         uint16_t pulseCnt,
+                                         uint16_t dutyCycle);
+
 /*! @}*/
 
 /*!
@@ -1337,4 +1369,4 @@ static inline void PWM_SetFilterSamplePeriod(PWM_Type *base,
 
 /*! @}*/
 
-#endif /* _FSL_PWM_H_ */
+#endif /* FSL_PWM_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_reset.c

@@ -68,6 +68,10 @@ void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
         MRCC0->MRCC_GLB_RST1_SET = bitMask;
         pResetCtrl               = &(MRCC0->MRCC_GLB_RST1);
     }
+    else
+    {
+     /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */
+    } 
     /* wait until it reads 0b1 */
     while (0u == ((*pResetCtrl) & bitMask))
     {
@@ -109,6 +113,10 @@ void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
         MRCC0->MRCC_GLB_RST1_CLR = bitMask;
         pResetCtrl               = &(MRCC0->MRCC_GLB_RST1);
     }
+    else
+    {
+     /* Added comments to prevent the violation of MISRA C-2012 rule 15.7 */
+    } 
     /* wait until it reads 0b0 */
     while (bitMask == ((*pResetCtrl) & bitMask))
     {

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_reset.h

@@ -119,7 +119,7 @@ typedef enum _SYSCON_RSTn
     } /* Reset bits for LPUART peripheral */
 #define LPSPI_RSTS                                     \
     {                                                  \
-        kLPSPI0_RST_SHIFT_RSTn, kLPSPI0_RST_SHIFT_RSTn \
+        kLPSPI0_RST_SHIFT_RSTn, kLPSPI1_RST_SHIFT_RSTn \
     } /* Reset bits for LPSPI peripheral */
 #define LPI2C_RSTS             \
     {                          \

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_romapi.h

@@ -31,6 +31,49 @@
 #define FSL_ROMAPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
 /*@}*/
 
+/*!
+ * @name Flash status
+ * @{
+ */
+/*! @brief Flash driver status group. */
+#if defined(kStatusGroup_FlashDriver)
+#define kStatusGroupGeneric     kStatusGroup_Generic
+#define kStatusGroupFlashDriver kStatusGroup_FlashDriver
+#elif defined(kStatusGroup_FLASHIAP)
+#define kStatusGroupGeneric     kStatusGroup_Generic
+#define kStatusGroupFlashDriver kStatusGroup_FLASH
+#else
+#define kStatusGroupGeneric     0
+#define kStatusGroupFlashDriver 1
+#endif
+
+/*! @brief Constructs a status code value from a group and a code number. */
+#if !defined(MAKE_STATUS)
+#define MAKE_STATUS(group, code) ((((group) * 100) + (code)))
+#endif
+
+/*!
+ * @brief Flash driver status codes.
+ */
+enum
+{
+    kStatus_FLASH_Success         = MAKE_STATUS(kStatusGroupGeneric, 0),     /*!< API is executed successfully*/
+    kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4),     /*!< Invalid argument*/
+    kStatus_FLASH_SizeError       = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/
+    kStatus_FLASH_AlignmentError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/
+    kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
+    kStatus_FLASH_AccessError =
+        MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */
+    kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
+        kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
+    kStatus_FLASH_CommandFailure =
+        MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
+    kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/
+    kStatus_FLASH_EraseKeyError   = MAKE_STATUS(kStatusGroupFlashDriver, 7)  /*!< API erase key is invalid.*/
+};
+/*@}*/
+
 /*!
  * @brief Enumeration for various flash properties.
  */
@@ -167,6 +210,298 @@ typedef struct _bootloader_tree
 /** FLASH API base pointer */
 #define FLASH_API (ROM_API->flash_driver)
 
+/*!
+ * @name Flash API
+ * @{
+ */
+
+/*!
+ * @brief Initializes the global flash properties structure members
+ *
+ * This function checks and initializes the Flash module for the other Flash APIs.
+ *
+ * @param config Pointer to the storage for the driver runtime state.
+ *
+ */
+static inline status_t FLASH_Init(flash_config_t *config)
+{
+    return FLASH_API->flash_init(config);
+}
+
+/*!
+ * @brief Erases the flash sectors encompassed by parameters passed into function
+ *
+ * This function erases the appropriate number of flash sectors based on the
+ * desired start address and length.
+ *
+ * @param config The pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be erased.
+ *              NOTE: The start address need to be 4 Bytes-aligned.
+ *
+ * @param lengthInBytes The length, given in bytes need be 4 Bytes-aligned.
+ *
+ * @param key The value used to validate all flash erase APIs.
+ *
+ */
+static inline status_t FLASH_EraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
+{
+    return FLASH_API->flash_erase_sector(config, start, lengthInBytes, key);
+}
+
+/*!
+ * @brief Programs flash phrases with data at locations passed in through parameters
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ */
+static inline status_t FLASH_ProgramPhrase(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    return FLASH_API->flash_program_phrase(config, start, src, lengthInBytes);
+}
+
+/*!
+ * @brief Programs flash page with data at locations passed in through parameters
+ *
+ * This function programs the flash memory with the desired data for a given
+ * flash area as determined by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be programmed. Must be
+ *              word-aligned.
+ * @param src A pointer to the source buffer of data that is to be programmed
+ *            into the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be programmed. Must be word-aligned.
+ *
+ */
+static inline status_t FLASH_ProgramPage(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
+{
+    return FLASH_API->flash_program_page(config, start, src, lengthInBytes);
+}
+
+/*!
+ * @brief Verifies programming of the desired flash area
+ *
+ * This function verifies the data programed in the flash memory using the
+ * Flash Program Check Command and compares it to the expected data for a given
+ * flash area as determined by the start address and length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ * @param expectedData A pointer to the expected data that is to be
+ *        verified against.
+ * @param failedAddress A pointer to the returned failing address.
+ * @param failedData A pointer to the returned failing data.  Some derivatives do
+ *        not include failed data as part of the FCCOBx registers.  In this
+ *        case, zeros are returned upon failure.
+ *
+ */
+static inline status_t FLASH_VerifyProgram(flash_config_t *config,
+                                           uint32_t start,
+                                           uint32_t lengthInBytes,
+                                           const uint8_t *expectedData,
+                                           uint32_t *failedAddress,
+                                           uint32_t *failedData)
+{
+    return FLASH_API->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress, failedData);
+}
+
+/*!
+ * @brief Verify that the flash phrases are erased
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ *
+ */
+static inline status_t FLASH_VerifyErasePhrase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
+{
+    return FLASH_API->flash_verify_erase_phrase(config, start, lengthInBytes);
+}
+
+/*!
+ * @brief Verify that the flash pages are erased
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ *
+ */
+static inline status_t FLASH_VerifyErasePage(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
+{
+    return FLASH_API->flash_verify_erase_page(config, start, lengthInBytes);
+}
+
+/*!
+ * @brief Verify that the flash sectors are erased
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ *
+ */
+static inline status_t FLASH_VerifyEraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
+{
+    return FLASH_API->flash_verify_erase_sector(config, start, lengthInBytes);
+}
+
+/*!
+ * @brief Returns the desired flash property
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param whichProperty The desired property from the list of properties in
+ *        enum flash_property_tag_t
+ * @param value A pointer to the value returned for the desired flash property.
+ *
+ */
+static inline status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
+{
+    return FLASH_API->flash_get_property(config, whichProperty, value);
+}
+
+/*!
+ * @brief Verify that the IFR0 phrases are erased
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ *
+ */
+static inline status_t IFR_VerifyErasePhrase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
+{
+    return FLASH_API->ifr_verify_erase_phrase(config, start, lengthInBytes);
+}
+
+/*!
+ * @brief Verify that the IFR0 pages are erased
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ *
+ */
+static inline status_t IFR_VerifyErasePage(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
+{
+    return FLASH_API->ifr_verify_erase_page(config, start, lengthInBytes);
+}
+
+/*!
+ * @brief Verify that the IFR0 sectors are erased
+ *
+ * This function checks the appropriate number of flash sectors based on
+ * the desired start address and length to check whether the flash is erased
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be verified.
+ *        The start address does not need to be sector-aligned but must be word-aligned.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *        to be verified. Must be word-aligned.
+ *
+ */
+static inline status_t IFR_VerifyEraseSector(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
+{
+    return FLASH_API->ifr_verify_erase_sector(config, start, lengthInBytes);
+}
+
+/*!
+ * @brief Reads flash at locations passed in through parameters
+ *
+ * This function read the flash memory from a given flash area as determined
+ * by the start address and the length.
+ *
+ * @param config A pointer to the storage for the driver runtime state.
+ * @param start The start address of the desired flash memory to be read.
+ * @param dest A pointer to the dest buffer of data that is to be read
+ *            from the flash.
+ * @param lengthInBytes The length, given in bytes (not words or long-words),
+ *                      to be read.
+ *
+ */
+static inline status_t FLASH_Read(flash_config_t *config, uint32_t start, uint8_t *dest, uint32_t lengthInBytes)
+{
+    return FLASH_API->flash_read(config, start, dest, lengthInBytes);
+}
+
+/*!
+ * @brief Get ROM API version.
+ *
+ * This function read the ROM API version.
+ *
+ */
+static inline uint32_t ROMAPI_GetVersion(void)
+{
+    return FLASH_API->version;
+}
+
+/*!
+ * @brief Run the Bootloader API  to force into the ISP mode base on the user arg
+ *
+ * @param arg Indicates API prototype fields definition.
+ *          Refer to the above #user_app_boot_invoke_option_t structure
+ */
+static inline void ROMAPI_RunBootloader(void *arg)
+{
+    ROM_API->run_bootloader(arg);
+}
+
+/*!
+ * @brief Get the UUID
+ *
+ * @param uuid UUID data array
+ *
+ */
+static inline void ROMAPI_GetUUID(uint8_t *uuid)
+{
+#define MCXA_UUID_ADDR (0x01100800U)
+#define MCXA_UUID_SIZE (16U)
+
+    uint8_t *p = (uint8_t *)MCXA_UUID_ADDR;
+    for (uint8_t i = 0; i < MCXA_UUID_SIZE; i++)
+    {
+        *uuid = *p;
+        uuid++;
+        p++;
+    }
+}
+
+/* @} */
+
 /*! @} */
 
 #endif /* _FSL_RESET_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_trdc.c

@@ -0,0 +1,854 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_trdc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.trdc1"
+#endif
+
+/* The memory increment definition in byte of MBC and MRC configuration registers */
+#define TRDC_MRC_DOMAIN_INCREMENT 0x100UL
+#define TRDC_MBC_DOMAIN_INCREMENT 0x200UL
+/* In latest TRDC register definition this macro has been removed from device header file. Add this for backward
+ * compatability. */
+#ifndef TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL
+#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) ((uint32_t)(((uint32_t)(x)) << TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL0_SHIFT))
+#endif
+/* Get the memory increment in for each slave inside MBC */
+#define TRDC_MBC_SLAVE_INCREMENT(x) \
+    (((x) == 0U) ? (0U) : (((x) == 1U) ? (0x140UL) : (((x) == 2U) ? (0x168UL) : (0x190UL))))
+
+typedef union
+{
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT
+    trdc_processor_domain_assignment_t _processor_domain_assignment;
+    trdc_non_processor_domain_assignment_t _non_processor_domain_assignment;
+    trdc_pid_config_t _pid_config;
+#endif
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+    trdc_idau_config_t _idau_config;
+#endif
+#if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \
+    (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC)
+    trdc_memory_access_control_config_t _memory_access_control;
+#endif
+#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
+    trdc_mbc_memory_block_config_t _mbc_memory_blk;
+    trdc_mbc_nse_update_config_t _mbc_nse_update;
+#endif
+    uint32_t _u32;
+} trdc_reg32_convert_t;
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/*!
+ * brief Gets the TRDC hardware configuration.
+ *
+ * This function gets the TRDC hardware configurations, including number of bus
+ * masters, number of domains, number of MRCs and number of PACs.
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to the structure to get the configuration.
+ */
+void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config)
+{
+    assert(NULL != config);
+
+    config->masterNumber =
+        (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT);
+    config->domainNumber =
+        (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT);
+    config->mbcNumber =
+        (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> TRDC_TRDC_HWCFG0_NMBC_SHIFT);
+    config->mrcNumber =
+        (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMRC_MASK) >> TRDC_TRDC_HWCFG0_NMRC_SHIFT);
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
+/*!
+ * brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to the structure to get the configuration.
+ * param mbcIdx MBC number.
+ * param slvIdx Slave number.
+ */
+void TRDC_GetMbcHardwareConfig(TRDC_Type *base,
+                               trdc_slave_memory_hardware_config_t *config,
+                               uint8_t mbcIdx,
+                               uint8_t slvIdx)
+{
+    assert(NULL != config);
+#if defined(TRDC_MBC_COUNT) && TRDC_MBC_COUNT
+    assert(mbcIdx < (uint8_t)TRDC_MBC_COUNT);
+#else
+    assert(mbcIdx < (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >>
+                              TRDC_TRDC_HWCFG0_NMBC_SHIFT));
+#endif
+    assert(slvIdx < 4U);
+
+    config->blockNum  = TRDC_MBC_BASE(base, mbcIdx)->MBC_MEM_GLBCFG[slvIdx] & TRDC_MBC_MEM_GLBCFG_NBLKS_MASK;
+    config->blockSize = (TRDC_MBC_BASE(base, mbcIdx)->MBC_MEM_GLBCFG[slvIdx] & TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK) >>
+                        TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT;
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT
+/*!
+ * brief Gets the default master domain assignment for the processor bus master.
+ *
+ * This function gets the default master domain assignment for the processor bus master.
+ * It should only be used for the processor bus masters, such as CORE0. This function
+ * sets the assignment as follows:
+ *
+ * code
+ * assignment->domainId           = 0U;
+ * assignment->domainIdSelect     = kTRDC_DidMda;
+ * assignment->lock               = 0U;
+ * endcode
+ *
+ * param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment)
+{
+    assert(NULL != domainAssignment);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(domainAssignment, 0, sizeof(*domainAssignment));
+}
+
+/*!
+ * brief Gets the default master domain assignment for non-processor bus master.
+ *
+ * This function gets the default master domain assignment for non-processor bus master.
+ * It should only be used for the non-processor bus masters, such as DMA. This function
+ * sets the assignment as follows:
+ *
+ * code
+ * assignment->domainId            = 0U;
+ * assignment->privilegeAttr       = kTRDC_ForceUser;
+ * assignment->secureAttr       = kTRDC_ForceSecure;
+ * assignment->bypassDomainId      = 0U;
+ * assignment->lock                = 0U;
+ * endcode
+ *
+ * param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment)
+{
+    assert(NULL != domainAssignment);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(domainAssignment, 0, sizeof(*domainAssignment));
+}
+
+/*!
+ * brief Sets the processor bus master domain assignment.
+ *
+ * This function sets the processor master domain assignment as valid.
+ * One bus master might have multiple domain assignment registers. The parameter
+ * \p assignIndex specifies which assignment register to set.
+ *
+ * Example: Set domain assignment for core 0.
+ *
+ * code
+ * trdc_processor_domain_assignment_t processorAssignment;
+ *
+ * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);
+ *
+ * processorAssignment.domainId = 0;
+ * processorAssignment.xxx      = xxx;
+ * TRDC_SetMasterDomainAssignment(TRDC, 1, &processorAssignment);
+ * endcode
+ *
+ * param base TRDC peripheral base address.
+ * param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.
+ * param regNum Which register to configure, processor master can have more than one register for the MDAC
+ * configuration. param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_SetProcessorDomainAssignment(TRDC_Type *base,
+                                       uint8_t master,
+                                       uint8_t regNum,
+                                       const trdc_processor_domain_assignment_t *domainAssignment)
+{
+    /* Make sure the master number does not exceed the max master count. */
+    assert(master <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
+    /* Make sure the master is a processor master. */
+    assert(0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK));
+    assert(NULL != domainAssignment);
+    assert(domainAssignment->domainId <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT));
+
+    trdc_reg32_convert_t pid;
+    pid._processor_domain_assignment                                         = *domainAssignment;
+    TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] = pid._u32 | TRDC_MDA_W_DFMT0_VLD_MASK;
+}
+
+/*!
+ * brief Sets the non-processor bus master domain assignment.
+ *
+ * This function sets the non-processor master domain assignment as valid.
+ * One bus master might have multiple domain assignment registers. The parameter
+ * \p assignIndex specifies which assignment register to set.
+ *
+ * Example: Set domain assignment for DMA0.
+ * code
+ * trdc_non_processor_domain_assignment_t nonProcessorAssignment;
+ *
+ * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
+ * nonProcessorAssignment.domainId = 1;
+ * nonProcessorAssignment.xxx      = xxx;
+ *
+ * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);
+ * endcode
+ *
+ * param base TRDC peripheral base address.
+ * param master Which master to configure, refer to trdc_master_t in processor header file.
+ * param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base,
+                                          uint8_t master,
+                                          const trdc_non_processor_domain_assignment_t *domainAssignment)
+{
+    /* The master number should be less than the master count. */
+    assert(master <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
+    /* Make sure the master is a non-CPU/non-processor master */
+    assert(0U != (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK));
+    assert(NULL != domainAssignment);
+    assert(domainAssignment->domainId <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT));
+
+    trdc_reg32_convert_t pid;
+    pid._non_processor_domain_assignment = *domainAssignment;
+
+    TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] = pid._u32 | TRDC_MDA_W_DFMT1_VLD_MASK;
+}
+
+/*!
+ * brief Sets the current Process identifier(PID) for processor core.
+ *
+ * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains.
+ * Secure privileged software saves and restores the PID as part of any context switch.
+ * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register
+ * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3]
+ * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding
+ * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information
+ * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality.
+ *
+ * param base TRDC peripheral base address.
+ * param master Which processor master to configure, refer to trdc_master_t in processor header file.
+ * param pidConfig Pointer to the configuration structure.
+ */
+void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig)
+{
+    assert(pidConfig != NULL);
+    /* The master number should be less than the master count. */
+    assert(master <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
+    /* This master has to be a processor master. */
+    assert((TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK) == 0U);
+
+    trdc_reg32_convert_t pid;
+    pid._pid_config                                = *pidConfig;
+    TRDC_DOMAIN_ASSIGNMENT_BASE(base)->PID[master] = pid._u32;
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/*!
+ * brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.
+ *
+ * code
+ * config->lockSecureVTOR    = false;
+ * config->lockNonsecureVTOR = false;
+ * config->lockSecureMPU     = false;
+ * config->lockNonsecureMPU  = false;
+ * config->lockSAU           = false;
+ * endcode
+ *
+ * param domainAssignment Pointer to the configuration structure.
+ */
+void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration)
+{
+    assert(NULL != idauConfiguration);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(idauConfiguration, 0, sizeof(*idauConfiguration));
+}
+
+/*!
+ * brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.
+ *
+ * Example: Lock the secure and non-secure MPU registers.
+ *
+ * code
+ * trdc_idau_config_t idauConfiguration;
+ *
+ * TRDC_GetDefaultIDAUConfig(&idauConfiguration);
+ *
+ * idauConfiguration.lockSecureMPU = true;
+ * idauConfiguration.lockNonsecureMPU      = true;
+ * TRDC_SetIDAU(TRDC, &idauConfiguration);
+ * endcode
+ *
+ * param base TRDC peripheral base address.
+ * param domainAssignment Pointer to the configuration structure.
+ */
+void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration)
+{
+    assert(NULL != idauConfiguration);
+
+    trdc_reg32_convert_t pid;
+    pid._idau_config = *idauConfiguration;
+
+    TRDC_GENERAL_BASE(base)->TRDC_IDAU_CR = pid._u32 | TRDC_TRDC_IDAU_CR_VLD_MASK;
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW
+/*!
+ * brief Gets the default FLW(Flsh Logical Window) configuration.
+ *
+ * code
+ * config->blockCount    = false;
+ * config->arrayBaseAddr = false;
+ * config->lock     = false;
+ * config->enable  = false;
+ * endcode
+ *
+ * param flwConfiguration Pointer to the configuration structure.
+ */
+void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration)
+{
+    assert(NULL != flwConfiguration);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(flwConfiguration, 0, sizeof(*flwConfiguration));
+
+    flwConfiguration->enable = 0x1UL;
+}
+
+/*!
+ * brief Sets the FLW function's configuration.
+ *
+ * code
+ * trdc_flw_config_t flwConfiguration;
+ *
+ * TRDC_GetDefaultIDAUConfig(&flwConfiguration);
+ *
+ * flwConfiguration.blockCount = 32U;
+ * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
+ * TRDC_SetIDAU(TRDC, &flwConfiguration);
+ * endcode
+ *
+ * param base TRDC peripheral base address.
+ * param flwConfiguration Pointer to the configuration structure.
+ */
+void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration)
+{
+    assert(NULL != flwConfiguration);
+
+    TRDC_FLW_BASE(base)->TRDC_FLW_ABASE = flwConfiguration->arrayBaseAddr;
+    TRDC_FLW_BASE(base)->TRDC_FLW_BCNT  = flwConfiguration->blockCount;
+    TRDC_FLW_BASE(base)->TRDC_FLW_CTL =
+        TRDC_TRDC_FLW_CTL_V(flwConfiguration->enable) | TRDC_TRDC_FLW_CTL_LK(flwConfiguration->lock);
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR
+#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__)))
+/*!
+ * @brief Count the leading zeros.
+ *
+ * Count the leading zeros of an 32-bit data. This function is only defined
+ * for CM0 and CM0+ for IAR, because other cortex series have the clz instruction,
+ * KEIL and ARMGCC have toolchain build in function for this purpose.
+ *
+ * @param data The data to process.
+ * @return Count of the leading zeros.
+ */
+static uint8_t TRDC_CountLeadingZeros(uint32_t data)
+{
+    uint8_t count = 0U;
+    uint32_t mask = 0x80000000U;
+
+    while ((data & mask) == 0U)
+    {
+        count++;
+        mask >>= 1U;
+    }
+
+    return count;
+}
+#endif
+#endif
+
+/*!
+ * brief Initializes the TRDC module.
+ *
+ * This function enables the TRDC clock.
+ *
+ * param base TRDC peripheral base address.
+ */
+void TRDC_Init(TRDC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+/*!
+ * brief De-initializes the TRDC module.
+ *
+ * This function disables the TRDC clock.
+ *
+ * param base TRDC peripheral base address.
+ */
+void TRDC_Deinit(TRDC_Type *base)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR
+/*!
+ * brief Gets and clears the first domain error of the current domain.
+ *
+ * This function gets the first access violation information for the current domain
+ * and clears the pending flag. There might be multiple access violations pending
+ * for the current domain. This function only processes the first error.
+ *
+ * param base TRDC peripheral base address.
+ * param error Pointer to the error information.
+ * return If the access violation is captured, this function returns the kStatus_Success.
+ *         The error information can be obtained from the parameter error. If no
+ *         access violation is captured, this function returns the kStatus_NoData.
+ */
+status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error)
+{
+    return TRDC_GetAndClearFirstSpecificDomainError(base, error, TRDC_GetCurrentMasterDomainId(base));
+}
+
+/*!
+ * brief Gets and clears the first domain error of the specific domain.
+ *
+ * This function gets the first access violation information for the specific domain
+ * and clears the pending flag. There might be multiple access violations pending
+ * for the current domain. This function only processes the first error.
+ *
+ * param base TRDC peripheral base address.
+ * param error Pointer to the error information.
+ * param domainId The error of which domain to get and clear.
+ * return If the access violation is captured, this function returns the kStatus_Success.
+ *         The error information can be obtained from the parameter error. If no
+ *         access violation is captured, this function returns the kStatus_NoData.
+ */
+status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId)
+{
+    assert(NULL != error);
+
+    status_t status;
+    uint8_t errorIndex;   /* The index of first domain error. */
+    uint32_t errorBitMap; /* Domain error location bit map.   */
+    uint32_t regW1;       /* To save TRDC_DERR_W1.            */
+
+    /* Get the error bitmap. */
+    errorBitMap = TRDC_DOMAIN_ERROR_BASE(base)->TRDC_DERRLOC[domainId];
+
+    if (0U == errorBitMap) /* No error captured. */
+    {
+        status = kStatus_NoData;
+    }
+    else
+    {
+        /* Get the first error controller index. */
+#if (((__CORTEX_M == 0U) && (defined(__ICCARM__))) || (defined(__XTENSA__)))
+        errorIndex = 31U - TRDC_CountLeadingZeros(errorBitMap);
+#else
+        errorIndex = 31U - __CLZ(errorBitMap);
+#endif
+
+        /* Must write TRDC_FDID[TRDC_FDID] with the domain ID before reading the Domain Error registers. */
+        TRDC_DOMAIN_ERROR_BASE(base)->TRDC_FDID = TRDC_TRDC_FDID_FDID(domainId);
+
+        /* Initializes the error structure to zero. */
+        (void)memset(error, 0, sizeof(*error));
+
+        if (errorIndex > 15U)
+        {
+            /* Error in Memory Region Checker (MRC) */
+            errorIndex -= 12U;
+            error->controller = (trdc_controller_t)errorIndex;
+            errorIndex -= 4U;
+
+            /* Get the error information. */
+            regW1          = TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W1;
+            error->address = TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W0;
+            /* Clear error pending. */
+            TRDC_DOMAIN_ERROR_BASE(base)->MRC_DERR[errorIndex].W3 = TRDC_W3_RECR(0x01U);
+        }
+        else
+        {
+            /* Error in Memory Block Controller (MBC) */
+            error->slaveMemoryIdx = errorIndex % 4U;
+            errorIndex /= 4U;
+            error->controller = (trdc_controller_t)errorIndex;
+
+            /* Check if the MBC error index exceeds the module's max MBC index to avoid overrun access. */
+            if (errorIndex >=
+                ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMBC_MASK) >> TRDC_TRDC_HWCFG0_NMBC_SHIFT))
+            {
+                return kStatus_Fail;
+            }
+
+            error->controller = (trdc_controller_t)errorIndex;
+
+            /* Get the error information. */
+            regW1          = TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W1;
+            error->address = TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W0;
+            /* Clear error pending. */
+            TRDC_DOMAIN_ERROR_BASE(base)->MBC_DERR[errorIndex].W3 = TRDC_W3_RECR(0x01U);
+        }
+
+        uint8_t tempVal   = 0U;
+        error->domainId   = (uint8_t)((regW1 & TRDC_W1_EDID_MASK) >> TRDC_W1_EDID_MASK);
+        tempVal           = (uint8_t)((regW1 & TRDC_W1_EATR_MASK) >> TRDC_W1_EATR_SHIFT);
+        error->errorAttr  = (trdc_error_attr_t)tempVal;
+        tempVal           = (uint8_t)((regW1 & TRDC_W1_ERW_MASK) >> TRDC_W1_ERW_SHIFT);
+        error->errorType  = (trdc_error_type_t)tempVal;
+        error->errorPort  = (uint8_t)((regW1 & TRDC_W1_EPORT_MASK) >> TRDC_W1_EPORT_SHIFT);
+        tempVal           = (uint8_t)((regW1 & TRDC_W1_EST_MASK) >> TRDC_W1_EST_SHIFT);
+        error->errorState = (trdc_error_state_t)tempVal;
+
+        status = kStatus_Success;
+    }
+
+    return status;
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC
+/*!
+ * brief Sets the memory access configuration for one of the access control register of one MRC.
+ *
+ * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
+ *
+ * code
+ * trdc_memory_access_control_config_t config;
+ *
+ * config.securePrivX = true;
+ * config.securePrivW = true;
+ * config.securePrivR = true;
+ * config.lock = true;
+ * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);
+ * endcode
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to the configuration structure.
+ * param mrcIdx MRC index.
+ * param regIdx Register number.
+ */
+void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base,
+                                   const trdc_memory_access_control_config_t *config,
+                                   uint8_t mrcIdx,
+                                   uint8_t regIdx)
+{
+    assert(NULL != base);
+    assert(NULL != config);
+
+    trdc_reg32_convert_t pid;
+
+    pid._memory_access_control                     = *config;
+    TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBAC[regIdx] = pid._u32;
+}
+
+/*!
+ * brief Enables the update of the selected domians.
+ *
+ * After the domians' update are enabled, their regions' NSE bits can be set or clear.
+ *
+ * param base TRDC peripheral base address.
+ * param mrcIdx MRC index.
+ * param domianMask Bit mask of the domains to be enabled.
+ * param enable True to enable, false to disable.
+ */
+void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable)
+{
+    assert(NULL != base);
+
+    if (enable)
+    {
+        TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_INDIRECT |= ((uint32_t)domianMask << 16U);
+    }
+    else
+    {
+        TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_INDIRECT &= ~((uint32_t)domianMask << 16U);
+    }
+}
+
+/*!
+ * brief Sets the NSE bits of the selected regions for domains.
+ *
+ * This function sets the NSE bits for the selected regions for the domains whose update are enabled.
+ *
+ * param base TRDC peripheral base address.
+ * param mrcIdx MRC index.
+ * param regionMask Bit mask of the regions whose NSE bits to set.
+ */
+void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)
+{
+    assert(NULL != base);
+
+    TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_SET = ((uint32_t)regionMask);
+}
+
+/*!
+ * brief Clears the NSE bits of the selected regions for domains.
+ *
+ * This function clears the NSE bits for the selected regions for the domains whose update are enabled.
+ *
+ * param base TRDC peripheral base address.
+ * param mrcIdx MRC index.
+ * param regionMask Bit mask of the regions whose NSE bits to clear.
+ */
+void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask)
+{
+    assert(NULL != base);
+
+    TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_CLR = ((uint32_t)regionMask);
+}
+
+/*!
+ * brief Clears the NSE bits for all the regions of the selected domains.
+ *
+ * This function clears the NSE bits for all regions of selected domains whose update are enabled.
+ *
+ * param base TRDC peripheral base address.
+ * param mrcIdx MRC index.
+ * param domainMask Bit mask of the domians whose NSE bits to clear.
+ */
+void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask)
+{
+    assert(NULL != base);
+
+    uint8_t domainCount =
+        (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT);
+    uint8_t maxDomainId = 0U;
+    uint16_t tmpDomainMask = domainMask;
+
+    while (tmpDomainMask != 0U)
+    {
+        tmpDomainMask >>= 1U;
+        maxDomainId++;
+    }
+
+    /* Check whether the domain mask contains invalid domain. */
+    if (maxDomainId > domainCount)
+    {
+        assert(false);
+    }
+
+    TRDC_MRC_BASE(base, mrcIdx)->MRC_NSE_RGN_CLR_ALL = ((uint32_t)domainMask << 16U);
+}
+
+/*!
+ * brief Sets the configuration for one of the region descriptor per domain per MRC instnce.
+ *
+ * This function sets the configuration for one of the region descriptor, including the start
+ * and end address of the region, memory access control policy and valid.
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to region descriptor configuration structure.
+ */
+void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config)
+{
+    assert(NULL != base);
+
+    uint32_t regAddr = (uint32_t) & (TRDC_MRC_BASE(base, config->mrcIdx)->MRC_DOM0_RGD_W[config->regionIdx][0]);
+
+    regAddr += TRDC_MRC_DOMAIN_INCREMENT * config->domainIdx;
+
+    /* Set configuration for word 0 */
+    uint32_t data = TRDC_MRC_DOM0_RGD_W_MRACSEL(config->memoryAccessControlSelect) |
+                    ((config->startAddr) & ~(TRDC_MRC_DOM0_RGD_W_MRACSEL_MASK));
+    *(uint32_t *)regAddr = data;
+
+    /* Set configuration for word 1 */
+    regAddr += 4U;
+    data = TRDC_MRC_DOM0_RGD_W_VLD(config->valid) | TRDC_MRC_DOM0_RGD_W_NSE(config->nseEnable) |
+           ((config->endAddr) & ~(TRDC_MRC_DOM0_RGD_W_VLD_MASK | TRDC_MRC_DOM0_RGD_W_NSE_MASK));
+    *(uint32_t *)regAddr = data;
+}
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
+/*!
+ * brief Sets the NSR update configuration for one of the MBC instance.
+ *
+ * After set the NSE configuration, the configured memory area can be updateby NSE set/clear.
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to NSE update configuration structure.
+ * param mbcIdx MBC index.
+ */
+void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx)
+{
+    assert(base != NULL);
+
+    trdc_reg32_convert_t pid;
+
+    pid._mbc_nse_update                            = *config;
+    TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_INDEX = pid._u32;
+}
+
+/*!
+ * brief Sets the NSE bits of the selected configuration words according to NSE update configuration.
+ *
+ * This function sets the NSE bits of the word for the configured regio, memory.
+ *
+ * param base TRDC peripheral base address.
+ * param mbcIdx MBC index.
+ * param bitMask Mask of the bits whose NSE bits to set.
+ */
+void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)
+{
+    assert(NULL != base);
+
+    TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_SET = ((uint32_t)bitMask);
+}
+
+/*!
+ * brief Clears the NSE bits of the selected configuration words according to NSE update configuration.
+ *
+ * This function sets the NSE bits of the word for the configured regio, memory.
+ *
+ * param base TRDC peripheral base address.
+ * param mbcIdx MBC index.
+ * param bitMask Mask of the bits whose NSE bits to clear.
+ */
+void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask)
+{
+    assert(NULL != base);
+
+    TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_CLR = ((uint32_t)bitMask);
+}
+
+/*!
+ * brief Clears all configuration words' NSE bits of the selected domain and memory.
+ *
+ * param base TRDC peripheral base address.
+ * param mbcIdx MBC index.
+ * param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.
+ * param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits.
+ */
+void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave)
+{
+    assert(NULL != base);
+
+#if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && FSL_FEATURE_TRDC_DOMAIN_COUNT
+    uint8_t dmainCount = FSL_FEATURE_TRDC_DOMAIN_COUNT;
+#else
+    uint8_t dmainCount =
+        (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NDID_MASK) >> TRDC_TRDC_HWCFG0_NDID_SHIFT);
+#endif
+    uint8_t maxDomainId = 0U;
+    uint16_t tmpDomainMask = domainMask;
+
+    while (tmpDomainMask != 0U)
+    {
+        tmpDomainMask >>= 1U;
+        maxDomainId++;
+    }
+
+    if (maxDomainId > dmainCount)
+    {
+        assert(false);
+    }
+
+    TRDC_MBC_BASE(base, mbcIdx)->MBC_NSE_BLK_CLR_ALL =
+        TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(domainMask) | TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(slave);
+}
+
+/*!
+ * brief Sets the memory access configuration for one of the region descriptor of one MBC.
+ *
+ * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
+ *
+ * code
+ * trdc_memory_access_control_config_t config;
+ *
+ * config.securePrivX = true;
+ * config.securePrivW = true;
+ * config.securePrivR = true;
+ * config.lock = true;
+ * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);
+ * endcode
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to the configuration structure.
+ * param mbcIdx MBC index.
+ * param rgdIdx Region descriptor number.
+ */
+void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base,
+                                   const trdc_memory_access_control_config_t *config,
+                                   uint8_t mbcIdx,
+                                   uint8_t rgdIdx)
+{
+    assert(NULL != base);
+    assert(NULL != config);
+
+    trdc_reg32_convert_t pid;
+
+    pid._memory_access_control                          = *config;
+    TRDC_MBC_BASE(base, mbcIdx)->MBC_MEMN_GLBAC[rgdIdx] = pid._u32;
+}
+
+/*!
+ * brief Sets the configuration for one of the memory block per domain per MBC instnce.
+ *
+ * This function sets the configuration for one of the memory block, including the memory access
+ * control policy and nse enable.
+ *
+ * param base TRDC peripheral base address.
+ * param config Pointer to memory block configuration structure.
+ */
+void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config)
+{
+    assert(NULL != base);
+
+    uint32_t shift      = 4UL * (config->memoryBlockIdx % 8UL);
+    uint32_t regAddr    = (uint32_t) & (TRDC_MBC_BASE(base, config->mbcIdx)->MBC_DOM0_MEM0_BLK_CFG_W[0]);
+    uint32_t configWord = 0U;
+    trdc_reg32_convert_t pid;
+
+    pid._mbc_memory_blk = *config;
+    configWord          = (pid._u32 & 0xFU) << shift;
+
+    regAddr += (TRDC_MBC_DOMAIN_INCREMENT * config->domainIdx + TRDC_MBC_SLAVE_INCREMENT(config->slaveMemoryIdx)) +
+               ((uint32_t)config->memoryBlockIdx / 8U) * sizeof(uint32_t);
+    configWord           = configWord | (*(uint32_t *)regAddr & ~(0xFUL << shift));
+    *(uint32_t *)regAddr = configWord;
+}
+#endif

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_trdc.h

@@ -0,0 +1,1131 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef FSL_TRDC_H_
+#define FSL_TRDC_H_
+
+#include "fsl_common.h"
+#include "fsl_trdc_core.h"
+
+/*!
+ * @addtogroup trdc
+ * @{
+ */
+
+/******************************************************************************
+ * Definitions
+ *****************************************************************************/
+#define FSL_TRDC_DRIVER_VERSION (MAKE_VERSION(2, 2, 1))
+
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/* Hardware configuration definitions */
+/*!
+ * @brief TRDC hardware configuration.
+ */
+typedef struct _trdc_hardware_config
+{
+    uint8_t masterNumber; /*!< Number of bus masters. */
+    uint8_t domainNumber; /*!< Number of domains.     */
+    uint8_t mbcNumber;    /*!< Number of MBCs.        */
+    uint8_t mrcNumber;    /*!< Number of MRCs.        */
+} trdc_hardware_config_t;
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
+/*!
+ * @brief Hardware configuration of the two slave memories within each MBC(memory block checker).
+ */
+typedef struct _trdc_slave_memory_hardware_config
+{
+    uint32_t blockNum;  /*!< Number of blocks. */
+    uint32_t blockSize; /*!< Block size. */
+} trdc_slave_memory_hardware_config_t;
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT
+/* Master domain assignment definitions */
+/*!
+ * @brief TRDC domain ID select method, the register bit TRDC_MDA_W0_0_DFMT0[DIDS], used for
+ * domain hit evaluation.
+ */
+typedef enum _trdc_did_sel
+{
+    kTRDC_DidMda,         /*!< Use MDAn[2:0] as DID. */
+    kTRDC_DidInput,       /*!< Use the input DID (DID_in) as DID. */
+    kTRDC_DidMdaAndInput, /*!< Use MDAn[2] concatenated with DID_in[1:0] as DID. */
+    kTRDC_DidReserved     /*!< Reserved. */
+} trdc_did_sel_t;
+
+/*!
+ * @brief TRDC secure attribute, the register bit TRDC_MDA_W0_0_DFMT0[SA], used for
+ * bus master domain assignment.
+ */
+typedef enum _trdc_secure_attr
+{
+    kTRDC_ForceSecure,    /*!< Force the bus attribute for this master to secure.        */
+    kTRDC_ForceNonSecure, /*!< Force the bus attribute for this master to non-secure.    */
+    kTRDC_MasterSecure,   /*!< Use the bus master's secure/nonsecure attribute directly. */
+    kTRDC_MasterSecure1,  /*!< Use the bus master's secure/nonsecure attribute directly. */
+} trdc_secure_attr_t;
+
+/*!
+ * @brief The configuration of domain hit evaluation of PID.
+ */
+typedef enum _trdc_pid_domain_hit_config
+{
+    kTRDC_pidDomainHitNone0,     /*!< No PID is included in the domain hit evaluation. */
+    kTRDC_pidDomainHitNone1,     /*!< No PID is included in the domain hit evaluation. */
+    kTRDC_pidDomainHitInclusive, /*!< The PID is included in the domain hit evaluation when (PID & ~PIDM). */
+    kTRDC_pidDomainHitExclusive, /*!< The PID is included in the domain hit evaluation when ~(PID & ~PIDM). */
+} trdc_pid_domain_hit_config_t;
+
+/*!
+ * @brief Domain assignment for the processor bus master.
+ */
+typedef struct _trdc_processor_domain_assignment
+{
+    uint32_t domainId : 4U;           /*!< Domain ID. */
+    uint32_t domainIdSelect : 2U;     /*!< Domain ID select method, see @ref trdc_did_sel_t. */
+    uint32_t pidDomainHitConfig : 2U; /*!< The configuration of the domain hit evaluation for PID, see @ref
+                                         trdc_pid_domain_hit_config_t. */
+    uint32_t pidMask : 6U;    /*!< The mask combined with PID, so multiple PID can be included as part of the domain hit
+                                 determination. Set to 0 to disable. */
+    uint32_t secureAttr : 2U; /*!< Secure attribute, see @ref trdc_secure_attr_t. */
+    uint32_t pid : 6U;  /*!< The process identifier, combined with pidMask to form the domain hit determination. */
+    uint32_t : 8U;      /*!< Reserved. */
+    uint32_t lock : 1U; /*!< Lock the register. */
+    uint32_t : 1U;      /*!< Reserved. */
+} trdc_processor_domain_assignment_t;
+
+/*!
+ * @brief TRDC privileged attribute, the register bit TRDC_MDA_W0_x_DFMT1[PA], used for non-processor
+ * bus master domain assignment.
+ */
+typedef enum _trdc_privilege_attr
+{
+    kTRDC_ForceUser,        /*!< Force the bus attribute for this master to user. */
+    kTRDC_ForcePrivilege,   /*!< Force the bus attribute for this master to privileged. */
+    kTRDC_MasterPrivilege,  /*!< Use the bus master's attribute directly. */
+    kTRDC_MasterPrivilege1, /*!< Use the bus master's attribute directly. */
+} trdc_privilege_attr_t;
+
+/*!
+ * @brief Domain assignment for the non-processor bus master.
+ */
+typedef struct _trdc_non_processor_domain_assignment
+{
+    uint32_t domainId : 4U;       /*!< Domain ID. */
+    uint32_t privilegeAttr : 2U;  /*!< Privileged attribute, see @ref trdc_privilege_attr_t. */
+    uint32_t secureAttr : 2U;     /*!< Secure attribute, see @ref trdc_secure_attr_t. */
+    uint32_t bypassDomainId : 1U; /*!< Bypass domain ID. */
+    uint32_t : 21U;               /*!< Reserved. */
+    uint32_t lock : 1U;           /*!< Lock the register. */
+    uint32_t : 1U;                /*!< Reserved. */
+} trdc_non_processor_domain_assignment_t;
+
+/*!
+ * @brief PID lock configuration.
+ */
+typedef enum _trdc_pid_lock
+{
+    kTRDC_PidUnlocked0, /*!< The PID value can be updated by any secure priviledged write. */
+    kTRDC_PidUnlocked1, /*!< The PID value can be updated by any secure priviledged write. */
+    kTRDC_PidUnlocked2, /*!< The PID value can be updated by any secure priviledged write from the bus master that first
+                           configured this register. */
+    kTRDC_PidLocked,    /*!< The PID value is locked until next reset. */
+} trdc_pid_lock_t;
+
+/*!
+ * @brief Process identifier(PID) configuration for processor cores.
+ */
+typedef struct _trdc_pid_config
+{
+    uint32_t pid : 6U;  /*!< The process identifier of the executing task. The highest bit can be used to define
+                           secure/nonsecure attribute of the task. */
+    uint32_t : 23U;     /*!< Reserved. */
+    uint32_t lock : 2U; /*!< How to lock the register, see @ref trdc_pid_lock_t. */
+    uint32_t : 1U;      /*!< Reserved. */
+} trdc_pid_config_t;
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/* TZ-M congiguration definitions */
+/*!
+ * @brief IDAU(Implementation-Defined Attribution Unit) configuration for TZ-M function control.
+ */
+typedef struct _trdc_idau_config
+{
+    uint32_t : 8U;                   /*!< Reserved. */
+    uint32_t lockSecureVTOR : 1U;    /*!< Disable writes to secure VTOR(Vector Table Offset Register). */
+    uint32_t lockNonsecureVTOR : 1U; /*!< Disable writes to non-secure VTOR, Application interrupt and Reset Control
+                                        Registers. */
+    uint32_t lockSecureMPU : 1U; /*!< Disable writes to secure MPU(Memory Protection Unit) from software or from a debug
+                                    agent connected to the processor in Secure state. */
+    uint32_t lockNonsecureMPU : 1U; /*!< Disable writes to non-secure MPU(Memory Protection Unit) from software or from
+                                       a debug agent connected to the processor. */
+    uint32_t lockSAU : 1U;          /*!< Disable writes to SAU(Security Attribution Unit) registers. */
+    uint32_t : 19U;                 /*!< Reserved. */
+} trdc_idau_config_t;
+
+/* FLW(Flash Logical Window) configuration definitions */
+/*!
+ * @brief FLW(Flash Logical Window) configuration.
+ */
+typedef struct _trdc_flw_config
+{
+    uint16_t blockCount;    /*!< Block count of the Flash Logic Window in 32KByte blocks. */
+    uint32_t arrayBaseAddr; /*!< Flash array base address of the Flash Logical Window. */
+    bool lock;              /*!< Disable writes to FLW registers. */
+    bool enable;            /*!< Enable FLW function. */
+} trdc_flw_config_t;
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR
+/* Domain error check and clear definitions */
+/*!
+ * @brief TRDC controller definition for domain error check. Each TRDC instance may have different
+ * MRC or MBC count, call TRDC_GetHardwareConfig to get the actual count.
+ */
+typedef enum _trdc_controller
+{
+    kTRDC_MemBlockController0 = 0U,  /*!< Memory block checker 0. */
+    kTRDC_MemBlockController1 = 1U,  /*!< Memory block checker 1. */
+    kTRDC_MemBlockController2 = 2U,  /*!< Memory block checker 2. */
+    kTRDC_MemBlockController3 = 3U,  /*!< Memory block checker 3. */
+    kTRDC_MemRegionChecker0   = 4U,  /*!< Memory region checker 0.   */
+    kTRDC_MemRegionChecker1   = 5U,  /*!< Memory region checker 1.   */
+    kTRDC_MemRegionChecker2   = 6U,  /*!< Memory region checker 2.   */
+    kTRDC_MemRegionChecker3   = 7U,  /*!< Memory region checker 3.   */
+    kTRDC_MemRegionChecker4   = 8U,  /*!< Memory region checker 4.   */
+    kTRDC_MemRegionChecker5   = 9U,  /*!< Memory region checker 5.   */
+    kTRDC_MemRegionChecker6   = 10U, /*!< Memory region checker 6.   */
+} trdc_controller_t;
+
+/*!
+ * @brief TRDC domain error state definition TRDC_MBCn_DERR_W1[EST] or TRDC_MRCn_DERR_W1[EST].
+ */
+typedef enum _trdc_error_state
+{
+    kTRDC_ErrorStateNone   = 0x00U, /*!< No access violation detected.       */
+    kTRDC_ErrorStateNone1  = 0x01U, /*!< No access violation detected.       */
+    kTRDC_ErrorStateSingle = 0x02U, /*!< Single access violation detected.   */
+    kTRDC_ErrorStateMulti  = 0x03U  /*!< Multiple access violation detected. */
+} trdc_error_state_t;
+
+/*!
+ * @brief TRDC domain error attribute definition TRDC_MBCn_DERR_W1[EATR] or TRDC_MRCn_DERR_W1[EATR].
+ */
+typedef enum _trdc_error_attr
+{
+    kTRDC_ErrorSecureUserInst         = 0x00U, /*!< Secure user mode, instruction fetch access.           */
+    kTRDC_ErrorSecureUserData         = 0x01U, /*!< Secure user mode, data access.                        */
+    kTRDC_ErrorSecurePrivilegeInst    = 0x02U, /*!< Secure privileged mode, instruction fetch access.     */
+    kTRDC_ErrorSecurePrivilegeData    = 0x03U, /*!< Secure privileged mode, data access.                  */
+    kTRDC_ErrorNonSecureUserInst      = 0x04U, /*!< NonSecure user mode, instruction fetch access.        */
+    kTRDC_ErrorNonSecureUserData      = 0x05U, /*!< NonSecure user mode, data access.                     */
+    kTRDC_ErrorNonSecurePrivilegeInst = 0x06U, /*!< NonSecure privileged mode, instruction fetch access.  */
+    kTRDC_ErrorNonSecurePrivilegeData = 0x07U  /*!< NonSecure privileged mode, data access.               */
+} trdc_error_attr_t;
+
+/*!
+ * @brief TRDC domain error access type definition TRDC_DERR_W1_n[ERW].
+ */
+typedef enum _trdc_error_type
+{
+    kTRDC_ErrorTypeRead  = 0x00U, /*!< Error occurs on read reference.  */
+    kTRDC_ErrorTypeWrite = 0x01U  /*!< Error occurs on write reference. */
+} trdc_error_type_t;
+
+/*!
+ * @brief TRDC domain error definition.
+ */
+typedef struct _trdc_domain_error
+{
+    trdc_controller_t controller;  /*!< Which controller captured access violation.     */
+    uint32_t address;              /*!< Access address that generated access violation. */
+    trdc_error_state_t errorState; /*!< Error state.                                    */
+    trdc_error_attr_t errorAttr;   /*!< Error attribute.                                */
+    trdc_error_type_t errorType;   /*!< Error type.                                     */
+    uint8_t errorPort;             /*!< Error port.                                     */
+    uint8_t domainId;              /*!< Domain ID.                                      */
+    uint8_t slaveMemoryIdx;        /*!< The slave memory index. Only apply when violation in MBC. */
+} trdc_domain_error_t;
+#endif
+
+#if (defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC) || \
+    (defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC)
+/* Common definitions for MBC/MRC configuration */
+/*!
+ * @brief Memory access control configuration for MBC/MRC.
+ */
+typedef struct _trdc_memory_access_control_config
+{
+    uint32_t nonsecureUsrX : 1U;  /*!< Allow nonsecure user execute access. */
+    uint32_t nonsecureUsrW : 1U;  /*!< Allow nonsecure user write access. */
+    uint32_t nonsecureUsrR : 1U;  /*!< Allow nonsecure user read access. */
+    uint32_t : 1U;                /*!< Reserved. */
+    uint32_t nonsecurePrivX : 1U; /*!< Allow nonsecure privilege execute access. */
+    uint32_t nonsecurePrivW : 1U; /*!< Allow nonsecure privilege write access. */
+    uint32_t nonsecurePrivR : 1U; /*!< Allow nonsecure privilege read access. */
+    uint32_t : 1U;                /*!< Reserved. */
+    uint32_t secureUsrX : 1U;     /*!< Allow secure user execute access. */
+    uint32_t secureUsrW : 1U;     /*!< Allow secure user write access. */
+    uint32_t secureUsrR : 1U;     /*!< Allow secure user read access. */
+    uint32_t : 1U;                /*!< Reserved. */
+    uint32_t securePrivX : 1U;    /*!< Allownsecure privilege execute access. */
+    uint32_t securePrivW : 1U;    /*!< Allownsecure privilege write access. */
+    uint32_t securePrivR : 1U;    /*!< Allownsecure privilege read access. */
+    uint32_t : 16U;               /*!< Reserved. */
+    uint32_t lock : 1U; /*!< Lock the configuration until next reset, only apply to access control register 0. */
+} trdc_memory_access_control_config_t;
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC
+/*! @brief The region descriptor enumeration, used to form a mask to set/clear the NSE bits for one or several regions.
+ */
+enum _trdc_region_descriptor
+{
+    kTRDC_RegionDescriptor0  = (1U << 0U),  /*!< Region descriptor 0. */
+    kTRDC_RegionDescriptor1  = (1U << 1U),  /*!< Region descriptor 1. */
+    kTRDC_RegionDescriptor2  = (1U << 2U),  /*!< Region descriptor 2. */
+    kTRDC_RegionDescriptor3  = (1U << 3U),  /*!< Region descriptor 3. */
+    kTRDC_RegionDescriptor4  = (1U << 4U),  /*!< Region descriptor 4. */
+    kTRDC_RegionDescriptor5  = (1U << 5U),  /*!< Region descriptor 5. */
+    kTRDC_RegionDescriptor6  = (1U << 6U),  /*!< Region descriptor 6. */
+    kTRDC_RegionDescriptor7  = (1U << 7U),  /*!< Region descriptor 7. */
+    kTRDC_RegionDescriptor8  = (1U << 8U),  /*!< Region descriptor 8. */
+    kTRDC_RegionDescriptor9  = (1U << 9U),  /*!< Region descriptor 9. */
+    kTRDC_RegionDescriptor10 = (1U << 10U), /*!< Region descriptor 10. */
+    kTRDC_RegionDescriptor11 = (1U << 11U), /*!< Region descriptor 11. */
+    kTRDC_RegionDescriptor12 = (1U << 12U), /*!< Region descriptor 12. */
+    kTRDC_RegionDescriptor13 = (1U << 13U), /*!< Region descriptor 13. */
+    kTRDC_RegionDescriptor14 = (1U << 14U), /*!< Region descriptor 14. */
+    kTRDC_RegionDescriptor15 = (1U << 15U), /*!< Region descriptor 15. */
+};
+
+/* MRC configuration definitions */
+/*! @brief The MRC domain enumeration, used to form a mask to enable/disable the update or clear all NSE bits of one or
+ * several domains. */
+enum _trdc_MRC_domain
+{
+    kTRDC_MrcDomain0  = (1U << 0U),  /*!< Domain 0. */
+    kTRDC_MrcDomain1  = (1U << 1U),  /*!< Domain 1. */
+    kTRDC_MrcDomain2  = (1U << 2U),  /*!< Domain 2. */
+    kTRDC_MrcDomain3  = (1U << 3U),  /*!< Domain 3. */
+    kTRDC_MrcDomain4  = (1U << 4U),  /*!< Domain 4. */
+    kTRDC_MrcDomain5  = (1U << 5U),  /*!< Domain 5. */
+    kTRDC_MrcDomain6  = (1U << 6U),  /*!< Domain 6. */
+    kTRDC_MrcDomain7  = (1U << 7U),  /*!< Domain 7. */
+    kTRDC_MrcDomain8  = (1U << 8U),  /*!< Domain 8. */
+    kTRDC_MrcDomain9  = (1U << 9U),  /*!< Domain 9. */
+    kTRDC_MrcDomain10 = (1U << 10U), /*!< Domain 10. */
+    kTRDC_MrcDomain11 = (1U << 11U), /*!< Domain 11. */
+    kTRDC_MrcDomain12 = (1U << 12U), /*!< Domain 12. */
+    kTRDC_MrcDomain13 = (1U << 13U), /*!< Domain 13. */
+    kTRDC_MrcDomain14 = (1U << 14U), /*!< Domain 14. */
+    kTRDC_MrcDomain15 = (1U << 15U), /*!< Domain 15. */
+};
+
+/*!
+ * @brief The configuration of each region descriptor per domain per MRC instance.
+ */
+typedef struct _trdc_mrc_region_descriptor_config
+{
+    uint8_t memoryAccessControlSelect; /*!< Select one of the 8 access control policies for this region, for
+                                                access cotrol policies see @ref trdc_memory_access_control_config_t. */
+    uint32_t startAddr;                /*!< Physical start address. */
+    bool valid;                        /*!< Lock the register. */
+    bool nseEnable;                    /*!< Enable non-secure accesses and disable secure accesses. */
+    uint32_t endAddr;                  /*!< Physical start address. */
+    uint8_t mrcIdx;                    /*!< The index of the MRC for this configuration to take effect. */
+    uint8_t domainIdx;                 /*!< The index of the domain for this configuration to take effect. */
+    uint8_t regionIdx;                 /*!< The index of the region for this configuration to take effect. */
+} trdc_mrc_region_descriptor_config_t;
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
+/* MBC configuration definitions */
+/*!
+ * @brief The configuration of MBC NSE update.
+ */
+#if defined(FSL_FEATURE_TRDC_DOMAIN_COUNT) && (FSL_FEATURE_TRDC_DOMAIN_COUNT > 0x8U)
+typedef struct _trdc_mbc_nse_update_config
+{
+    uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this
+                                    configuration. */
+    uint32_t : 1U;               /*!< Reserved. */
+    uint32_t wordIdx : 4U;       /*!< MBC configuration word index to be updated. */
+    uint32_t : 2U;               /*!< Reserved. */
+    uint32_t memorySelect : 4U;  /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */
+    uint32_t : 4U;               /*!< Reserved. */
+    uint32_t domianSelect : 16U; /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */
+} trdc_mbc_nse_update_config_t;
+#else
+typedef struct _trdc_mbc_nse_update_config
+{
+    uint32_t : 2U;               /*!< Reserved. */
+    uint32_t wordIdx : 4U;       /*!< MBC configuration word index to be updated. */
+    uint32_t : 2U;               /*!< Reserved. */
+    uint32_t memorySelect : 4U;  /*!< Bit mask of the selected memory to be updated. @ref _trdc_MBC_memory. */
+    uint32_t : 4U;               /*!< Reserved. */
+    uint32_t domianSelect : 8U;  /*!< Bit mask of the selected domain to be updated. @ref _trdc_MBC_domain. */
+    uint32_t : 7U;               /*!< Reserved. */
+    uint32_t autoIncrement : 1U; /*!< Whether to increment the word index after current word is updated using this
+                                    configuration. */
+} trdc_mbc_nse_update_config_t;
+#endif
+
+/*! @brief The MBC domain enumeration, used to form a mask to enable/disable the update or clear NSE bits of one or
+ * several domains. */
+enum _trdc_MBC_domain
+{
+    kTRDC_MbcDomain0 = (1U << 0U), /*!< Domain 0. */
+    kTRDC_MbcDomain1 = (1U << 1U), /*!< Domain 1. */
+    kTRDC_MbcDomain2 = (1U << 2U), /*!< Domain 2. */
+    kTRDC_MbcDomain3 = (1U << 3U), /*!< Domain 3. */
+    kTRDC_MbcDomain4 = (1U << 4U), /*!< Domain 4. */
+    kTRDC_MbcDomain5 = (1U << 5U), /*!< Domain 5. */
+    kTRDC_MbcDomain6 = (1U << 6U), /*!< Domain 6. */
+    kTRDC_MbcDomain7 = (1U << 7U), /*!< Domain 7. */
+};
+
+/*! @brief The MBC slave memory enumeration, used to form a mask to enable/disable the update or clear NSE bits of one
+ * or several memory block. */
+enum _trdc_MBC_memory
+{
+    kTRDC_MbcSlaveMemory0 = (1U << 0U), /*!< Memory 0. */
+    kTRDC_MbcSlaveMemory1 = (1U << 1U), /*!< Memory 1. */
+    kTRDC_MbcSlaveMemory2 = (1U << 2U), /*!< Memory 2. */
+    kTRDC_MbcSlaveMemory3 = (1U << 3U), /*!< Memory 3. */
+};
+
+/*! @brief The MBC bit enumeration, used to form a mask to set/clear configured words' NSE. */
+enum _trdc_MBC_bit
+{
+    kTRDC_MbcBit0  = (1U << 0U),  /*!< Bit 0. */
+    kTRDC_MbcBit1  = (1U << 1U),  /*!< Bit 1. */
+    kTRDC_MbcBit2  = (1U << 2U),  /*!< Bit 2. */
+    kTRDC_MbcBit3  = (1U << 3U),  /*!< Bit 3. */
+    kTRDC_MbcBit4  = (1U << 4U),  /*!< Bit 4. */
+    kTRDC_MbcBit5  = (1U << 5U),  /*!< Bit 5. */
+    kTRDC_MbcBit6  = (1U << 6U),  /*!< Bit 6. */
+    kTRDC_MbcBit7  = (1U << 7U),  /*!< Bit 7. */
+    kTRDC_MbcBit8  = (1U << 8U),  /*!< Bit 8. */
+    kTRDC_MbcBit9  = (1U << 9U),  /*!< Bit 9. */
+    kTRDC_MbcBit10 = (1U << 10U), /*!< Bit 10. */
+    kTRDC_MbcBit11 = (1U << 11U), /*!< Bit 11. */
+    kTRDC_MbcBit12 = (1U << 12U), /*!< Bit 12. */
+    kTRDC_MbcBit13 = (1U << 13U), /*!< Bit 13. */
+    kTRDC_MbcBit14 = (1U << 14U), /*!< Bit 14. */
+    kTRDC_MbcBit15 = (1U << 15U), /*!< Bit 15. */
+    kTRDC_MbcBit16 = (1U << 16U), /*!< Bit 16. */
+    kTRDC_MbcBit17 = (1U << 17U), /*!< Bit 17. */
+    kTRDC_MbcBit18 = (1U << 18U), /*!< Bit 18. */
+    kTRDC_MbcBit19 = (1U << 19U), /*!< Bit 19. */
+    kTRDC_MbcBit20 = (1U << 20U), /*!< Bit 20. */
+    kTRDC_MbcBit21 = (1U << 21U), /*!< Bit 21. */
+    kTRDC_MbcBit22 = (1U << 22U), /*!< Bit 22. */
+    kTRDC_MbcBit23 = (1U << 23U), /*!< Bit 23. */
+    kTRDC_MbcBit24 = (1U << 24U), /*!< Bit 24. */
+    kTRDC_MbcBit25 = (1U << 25U), /*!< Bit 25. */
+    kTRDC_MbcBit26 = (1U << 26U), /*!< Bit 26. */
+    kTRDC_MbcBit27 = (1U << 27U), /*!< Bit 27. */
+    kTRDC_MbcBit28 = (1U << 28U), /*!< Bit 28. */
+    kTRDC_MbcBit29 = (1U << 29U), /*!< Bit 29. */
+    kTRDC_MbcBit30 = (1U << 30U), /*!< Bit 30. */
+    kTRDC_MbcBit31 = (1U << 31U), /*!< Bit 31. */
+};
+
+/*!
+ * @brief The configuration of each memory block per domain per MBC instance.
+ */
+typedef struct _trdc_mbc_memory_block_config
+{
+    uint32_t memoryAccessControlSelect : 3U; /*!< Select one of the 8 access control policies for this memory block, for
+                                                access cotrol policies see @ref trdc_memory_access_control_config_t. */
+    uint32_t nseEnable : 1U;                 /*!< Enable non-secure accesses and disable secure accesses. */
+    uint32_t mbcIdx : 4U;                    /*!< The index of the MBC for this configuration to take effect. */
+    uint32_t domainIdx : 8U;                 /*!< The index of the domain for this configuration to take effect. */
+    uint32_t slaveMemoryIdx : 8U; /*!< The index of the slave memory for this configuration to take effect. */
+    uint32_t memoryBlockIdx : 8U; /*!< The index of the memory block for this configuration to take effect. */
+} trdc_mbc_memory_block_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+/*!
+ * @brief Initializes the TRDC module.
+ *
+ * This function enables the TRDC clock.
+ *
+ * @param base TRDC peripheral base address.
+ */
+void TRDC_Init(TRDC_Type *base);
+
+/*!
+ * @brief De-initializes the TRDC module.
+ *
+ * This function disables the TRDC clock.
+ *
+ * @param base TRDC peripheral base address.
+ */
+void TRDC_Deinit(TRDC_Type *base);
+/*! @} */
+
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/*!
+ * @name Hardware configuration
+ * @{
+ */
+/*!
+ * @brief Gets the domain ID of the current bus master.
+ *
+ * @param base TRDC peripheral base address.
+ * @return Domain ID of current bus master.
+ */
+static inline uint8_t TRDC_GetCurrentMasterDomainId(TRDC_Type *base)
+{
+    return (uint8_t)((TRDC_GENERAL_BASE(base)->TRDC_HWCFG1 & TRDC_TRDC_HWCFG1_DID_MASK) >> TRDC_TRDC_HWCFG1_DID_SHIFT);
+}
+
+/*!
+ * @brief Gets the TRDC hardware configuration.
+ *
+ * This function gets the TRDC hardware configurations, including number of bus
+ * masters, number of domains, number of MRCs and number of PACs.
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to the structure to get the configuration.
+ */
+void TRDC_GetHardwareConfig(TRDC_Type *base, trdc_hardware_config_t *config);
+/*! @} */
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT) && FSL_FEATURE_TRDC_HAS_DOMAIN_ASSIGNMENT
+/*!
+ * @name Master domain assignment
+ * @{
+ */
+/*!
+ * @brief Sets the TRDC DAC(Domain Assignment Controllers) global valid.
+ *
+ * Once enabled, it will remain enabled until next reset.
+ *
+ * @param base TRDC peripheral base address.
+ */
+static inline void TRDC_SetDacGlobalValid(TRDC_Type *base)
+{
+    TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDM_MASK;
+}
+
+/*!
+ * @brief Locks the bus master domain assignment register.
+ *
+ * This function locks the master domain assignment. After it is locked, the register can't be changed
+ * until next reset.
+ *
+ * @param base TRDC peripheral base address.
+ * @param master Which master to configure, refer to trdcx_master_t in processor header file, x is trdc instance.
+ * @param regNum Which register to configure, processor master can have more than one register for the MDAC
+   configuration.
+ * @param assignIndex Which assignment register to lock.
+ */
+static inline void TRDC_LockMasterDomainAssignment(TRDC_Type *base, uint8_t master, uint8_t regNum)
+{
+    /* Make sure in the master range. */
+    assert((uint32_t)master <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
+    if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK))
+    {
+        TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_LK1_MASK;
+    }
+    else
+    {
+        TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_LK1_MASK;
+    }
+}
+
+/*!
+ * @brief Sets the master domain assignment as valid or invalid.
+ *
+ * This function sets the master domain assignment as valid or invalid.
+ *
+ * @param base TRDC peripheral base address.
+ * @param master Which master to configure.
+ * @param regNum Which register to configure, processor master can have more than one register for the MDAC
+ * configuration.
+ * @param assignIndex Index for the domain assignment register.
+ * @param valid True to set valid, false to set invalid.
+ */
+static inline void TRDC_SetMasterDomainAssignmentValid(TRDC_Type *base, uint8_t master, uint8_t regNum, bool valid)
+{
+    /* Make sure in the master range. */
+    assert((uint32_t)master <
+           ((TRDC_GENERAL_BASE(base)->TRDC_HWCFG0 & TRDC_TRDC_HWCFG0_NMSTR_MASK) >> TRDC_TRDC_HWCFG0_NMSTR_SHIFT));
+    if (valid)
+    {
+        if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK))
+        {
+            TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] |= TRDC_MDA_W_DFMT0_VLD_MASK;
+        }
+        else
+        {
+            TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] |= TRDC_MDA_W_DFMT1_VLD_MASK;
+        }
+    }
+    else
+    {
+        if (0U == (TRDC_GENERAL_BASE(base)->DACFG[master] & TRDC_DACFG_NCM_MASK))
+        {
+            TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT0[master].MDA_W_DFMT0[regNum] &= ~TRDC_MDA_W_DFMT0_VLD_MASK;
+        }
+        else
+        {
+            TRDC_DOMAIN_ASSIGNMENT_BASE(base)->MDA_DFMT1[master].MDA_W_DFMT1[0] &= ~TRDC_MDA_W_DFMT1_VLD_MASK;
+        }
+    }
+}
+
+/*!
+ * @brief Gets the default master domain assignment for the processor bus master.
+ *
+ * This function gets the default master domain assignment for the processor bus master.
+ * It should only be used for the processor bus masters, such as CORE0. This function
+ * sets the assignment as follows:
+ *
+ * @code
+ * assignment->domainId           = 0U;
+ * assignment->domainIdSelect     = kTRDC_DidMda;
+ * assignment->lock               = 0U;
+ * @endcode
+ *
+ * @param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_GetDefaultProcessorDomainAssignment(trdc_processor_domain_assignment_t *domainAssignment);
+
+/*!
+ * @brief Gets the default master domain assignment for non-processor bus master.
+ *
+ * This function gets the default master domain assignment for non-processor bus master.
+ * It should only be used for the non-processor bus masters, such as DMA. This function
+ * sets the assignment as follows:
+ *
+ * @code
+ * assignment->domainId            = 0U;
+ * assignment->privilegeAttr       = kTRDC_ForceUser;
+ * assignment->secureAttr       = kTRDC_ForceSecure;
+ * assignment->bypassDomainId      = 0U;
+ * assignment->lock                = 0U;
+ * @endcode
+ *
+ * @param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_GetDefaultNonProcessorDomainAssignment(trdc_non_processor_domain_assignment_t *domainAssignment);
+
+/*!
+ * @brief Sets the processor bus master domain assignment.
+ *
+ * This function sets the processor master domain assignment as valid.
+ * One bus master might have multiple domain assignment registers. The parameter
+ * \p assignIndex specifies which assignment register to set.
+ *
+ * Example: Set domain assignment for core 0.
+ *
+ * @code
+ * trdc_processor_domain_assignment_t processorAssignment;
+ *
+ * TRDC_GetDefaultProcessorDomainAssignment(&processorAssignment);
+ *
+ * processorAssignment.domainId = 0;
+ * processorAssignment.xxx      = xxx;
+ * TRDC_SetMasterDomainAssignment(TRDC, &processorAssignment);
+ * @endcode
+ *
+ * @param base TRDC peripheral base address.
+ * @param master Which master to configure, refer to trdc_master_t in processor header file.
+ * @param regNum Which register to configure, processor master can have more than one register for the MDAC
+ * configuration.
+ * @param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_SetProcessorDomainAssignment(TRDC_Type *base,
+                                       uint8_t master,
+                                       uint8_t regNum,
+                                       const trdc_processor_domain_assignment_t *domainAssignment);
+
+/*!
+ * @brief Sets the non-processor bus master domain assignment.
+ *
+ * This function sets the non-processor master domain assignment as valid.
+ * One bus master might have multiple domain assignment registers. The parameter
+ * \p assignIndex specifies which assignment register to set.
+ *
+ * Example: Set domain assignment for DMA0.
+ * @code
+ * trdc_non_processor_domain_assignment_t nonProcessorAssignment;
+ *
+ * TRDC_GetDefaultNonProcessorDomainAssignment(&nonProcessorAssignment);
+ * nonProcessorAssignment.domainId = 1;
+ * nonProcessorAssignment.xxx      = xxx;
+ *
+ * TRDC_SetMasterDomainAssignment(TRDC, kTrdcMasterDma0, 0U, &nonProcessorAssignment);
+ * @endcode
+ *
+ * @param base TRDC peripheral base address.
+ * @param master Which master to configure, refer to trdc_master_t in processor header file.
+ * @param domainAssignment Pointer to the assignment structure.
+ */
+void TRDC_SetNonProcessorDomainAssignment(TRDC_Type *base,
+                                          uint8_t master,
+                                          const trdc_non_processor_domain_assignment_t *domainAssignment);
+
+/*!
+ * @brief Gets the bit map of the bus master(s) that is(are) sourcing a PID register.
+ *
+ * This function sets the non-processor master domain assignment as valid.
+ *
+ * @param base TRDC peripheral base address.
+ * @return the bit map of the master(s). Bit 1 sets indicates bus master 1.
+ */
+static inline uint64_t TRDC_GetActiveMasterPidMap(TRDC_Type *base)
+{
+    return ((uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG3 << 32U) | (uint64_t)TRDC_GENERAL_BASE(base)->TRDC_HWCFG2;
+}
+
+/*!
+ * @brief Sets the current Process identifier(PID) for processor core.
+ *
+ * Each processor has a corresponding process identifier (PID) which can be used to group tasks into different domains.
+ * Secure privileged software saves and restores the PID as part of any context switch.
+ * This data structure defines an array of 32-bit values, one per MDA module, that define the PID. Since this register
+ * resource is only applicable to processor cores, the data structure is typically sparsely populated. The HWCFG[2-3]
+ * registers provide a bitmap of the implemented PIDn registers. This data structure is indexed using the corresponding
+ * MDA instance number. Depending on the operating clock domain of each DAC instance, there may be optional information
+ * stored in the corresponding PIDm register to properly implement the LK2 = 2 functionality.
+ *
+ * @param base TRDC peripheral base address.
+ * @param master Which processor master to configure, refer to trdc_master_t in processor header file.
+ * @param pidConfig Pointer to the configuration structure.
+ */
+void TRDC_SetPid(TRDC_Type *base, uint8_t master, const trdc_pid_config_t *pidConfig);
+/*! @} */
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/*!
+ * @name TZ-M congiguration
+ * @{
+ */
+/*!
+ * @brief Gets the default IDAU(Implementation-Defined Attribution Unit) configuration.
+ *
+ * @code
+ * config->lockSecureVTOR    = false;
+ * config->lockNonsecureVTOR = false;
+ * config->lockSecureMPU     = false;
+ * config->lockNonsecureMPU  = false;
+ * config->lockSAU           = false;
+ * @endcode
+ *
+ * @param domainAssignment Pointer to the configuration structure.
+ */
+void TRDC_GetDefaultIDAUConfig(trdc_idau_config_t *idauConfiguration);
+
+/*!
+ * @brief Sets the IDAU(Implementation-Defined Attribution Unit) control configuration.
+ *
+ * Example: Lock the secure and non-secure MPU registers.
+ *
+ * @code
+ * trdc_idau_config_t idauConfiguration;
+ *
+ * TRDC_GetDefaultIDAUConfig(&idauConfiguration);
+ *
+ * idauConfiguration.lockSecureMPU = true;
+ * idauConfiguration.lockNonsecureMPU      = true;
+ * TRDC_SetIDAU(TRDC, &idauConfiguration);
+ * @endcode
+ *
+ * @param base TRDC peripheral base address.
+ * @param domainAssignment Pointer to the configuration structure.
+ */
+void TRDC_SetIDAU(TRDC_Type *base, const trdc_idau_config_t *idauConfiguration);
+/*! @} */
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_FLW) && FSL_FEATURE_TRDC_HAS_FLW
+/*!
+ * @name FLW(Flash Logical Window) configuration
+ * @{
+ */
+/*!
+ * @brief Enables/disables the FLW(flash logical window) function.
+ *
+ * @param base TRDC peripheral base address.
+ * @param enable True to enable, false to disable.
+ */
+static inline void TRDC_EnableFlashLogicalWindow(TRDC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_V_MASK;
+    }
+    else
+    {
+        TRDC_FLW_BASE(base)->TRDC_FLW_CTL &= ~TRDC_TRDC_FLW_CTL_V_MASK;
+    }
+}
+
+/*!
+ * @brief Locks FLW registers. Once locked the registers can noy be updated until next reset.
+ *
+ * @param base TRDC peripheral base address.
+ */
+static inline void TRDC_LockFlashLogicalWindow(TRDC_Type *base)
+{
+    TRDC_FLW_BASE(base)->TRDC_FLW_CTL |= TRDC_TRDC_FLW_CTL_LK_MASK;
+}
+
+/*!
+ * @brief Gets the FLW physical base address.
+ *
+ * @param base TRDC peripheral base address.
+ * @return Physical address of the FLW function.
+ */
+static inline uint32_t TRDC_GetFlashLogicalWindowPbase(TRDC_Type *base)
+{
+    return TRDC_FLW_BASE(base)->TRDC_FLW_PBASE;
+}
+
+/*!
+ * @brief Sets the FLW size.
+ *
+ * @param base TRDC peripheral base address.
+ * @param size Size of the FLW in unit of 32k bytes.
+ */
+static inline void TRDC_GetSetFlashLogicalWindowSize(TRDC_Type *base, uint16_t size)
+{
+    TRDC_FLW_BASE(base)->TRDC_FLW_BCNT = size;
+}
+
+/*!
+ * @brief Gets the default FLW(Flsh Logical Window) configuration.
+ *
+ * @code
+ * config->blockCount    = false;
+ * config->arrayBaseAddr = false;
+ * config->lock     = false;
+ * config->enable  = false;
+ * @endcode
+ *
+ * @param flwConfiguration Pointer to the configuration structure.
+ */
+void TRDC_GetDefaultFlashLogicalWindowConfig(trdc_flw_config_t *flwConfiguration);
+
+/*!
+ * @brief Sets the FLW function's configuration.
+ *
+ * @code
+ * trdc_flw_config_t flwConfiguration;
+ *
+ * TRDC_GetDefaultIDAUConfig(&flwConfiguration);
+ *
+ * flwConfiguration.blockCount = 32U;
+ * flwConfiguration.arrayBaseAddr = 0xXXXXXXXX;
+ * TRDC_SetIDAU(TRDC, &flwConfiguration);
+ * @endcode
+ *
+ * @param base TRDC peripheral base address.
+ * @param flwConfiguration Pointer to the configuration structure.
+ */
+void TRDC_SetFlashLogicalWindow(TRDC_Type *base, const trdc_flw_config_t *flwConfiguration);
+/*! @} */
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR) && FSL_FEATURE_TRDC_HAS_DOMAIN_ERROR
+/*!
+ * @name Domain error check and clear
+ * @{
+ */
+/*!
+ * @brief Gets and clears the first domain error of the current domain.
+ *
+ * This function gets the first access violation information for the current domain
+ * and clears the pending flag. There might be multiple access violations pending
+ * for the current domain. This function only processes the first error.
+ *
+ * @param base TRDC peripheral base address.
+ * @param error Pointer to the error information.
+ * @return If the access violation is captured, this function returns the kStatus_Success.
+ *         The error information can be obtained from the parameter error. If no
+ *         access violation is captured, this function returns the kStatus_NoData.
+ */
+status_t TRDC_GetAndClearFirstDomainError(TRDC_Type *base, trdc_domain_error_t *error);
+
+/*!
+ * @brief Gets and clears the first domain error of the specific domain.
+ *
+ * This function gets the first access violation information for the specific domain
+ * and clears the pending flag. There might be multiple access violations pending
+ * for the current domain. This function only processes the first error.
+ *
+ * @param base TRDC peripheral base address.
+ * @param error Pointer to the error information.
+ * @param domainId The error of which domain to get and clear.
+ * @return If the access violation is captured, this function returns the kStatus_Success.
+ *         The error information can be obtained from the parameter error. If no
+ *         access violation is captured, this function returns the kStatus_NoData.
+ */
+status_t TRDC_GetAndClearFirstSpecificDomainError(TRDC_Type *base, trdc_domain_error_t *error, uint8_t domainId);
+/*! @} */
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MRC) && FSL_FEATURE_TRDC_HAS_MRC
+/*!
+ * @name MRC configuration
+ * @{
+ */
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/*!
+ * @brief Sets the TRDC MRC(Memory Region Checkers) global valid.
+ *
+ * Once enabled, it will remain enabled until next reset.
+ *
+ * @param base TRDC peripheral base address.
+ */
+static inline void TRDC_SetMrcGlobalValid(TRDC_Type *base)
+{
+    TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDR_MASK;
+}
+#endif
+
+/*!
+ * @brief Gets the TRDC MRC(Memory Region Checkers) region number valid.
+ *
+ * @param base TRDC peripheral base address.
+ * @return the region number of the given MRC instance
+ */
+static inline uint8_t TRDC_GetMrcRegionNumber(TRDC_Type *base, uint8_t mrcIdx)
+{
+    return (uint8_t)((TRDC_MRC_BASE(base, mrcIdx)->MRC_GLBCFG & TRDC_MRC_GLBCFG_NRGNS_MASK) >>
+                     TRDC_MRC_GLBCFG_NRGNS_SHIFT);
+}
+
+/*!
+ * @brief Sets the memory access configuration for one of the access control register of one MRC.
+ *
+ * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
+ *
+ * @code
+ * trdc_memory_access_control_config_t config;
+ *
+ * config.securePrivX = true;
+ * config.securePrivW = true;
+ * config.securePrivR = true;
+ * config.lock = true;
+ * TRDC_SetMrcMemoryAccess(TRDC, &config, 0, 1);
+ * @endcode
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to the configuration structure.
+ * @param mrcIdx MRC index.
+ * @param regIdx Register number.
+ */
+void TRDC_MrcSetMemoryAccessConfig(TRDC_Type *base,
+                                   const trdc_memory_access_control_config_t *config,
+                                   uint8_t mrcIdx,
+                                   uint8_t regIdx);
+
+/*!
+ * @brief Enables the update of the selected domians.
+ *
+ * After the domians' update are enabled, their regions' NSE bits can be set or clear.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mrcIdx MRC index.
+ * @param domianMask Bit mask of the domains to be enabled.
+ * @param enable True to enable, false to disable.
+ */
+void TRDC_MrcEnableDomainNseUpdate(TRDC_Type *base, uint8_t mrcIdx, uint16_t domianMask, bool enable);
+
+/*!
+ * @brief Sets the NSE bits of the selected regions for domains.
+ *
+ * This function sets the NSE bits for the selected regions for the domains whose update are enabled.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mrcIdx MRC index.
+ * @param regionMask Bit mask of the regions whose NSE bits to set.
+ */
+void TRDC_MrcRegionNseSet(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask);
+
+/*!
+ * @brief Clears the NSE bits of the selected regions for domains.
+ *
+ * This function clears the NSE bits for the selected regions for the domains whose update are enabled.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mrcIdx MRC index.
+ * @param regionMask Bit mask of the regions whose NSE bits to clear.
+ */
+void TRDC_MrcRegionNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t regionMask);
+
+/*!
+ * @brief Clears the NSE bits for all the regions of the selected domains.
+ *
+ * This function clears the NSE bits for all regions of selected domains whose update are enabled.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mrcIdx MRC index.
+ * @param domainMask Bit mask of the domians whose NSE bits to clear.
+ */
+void TRDC_MrcDomainNseClear(TRDC_Type *base, uint8_t mrcIdx, uint16_t domainMask);
+
+/*!
+ * @brief Sets the configuration for one of the region descriptor per domain per MRC instnce.
+ *
+ * This function sets the configuration for one of the region descriptor, including the start
+ * and end address of the region, memory access control policy and valid.
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to region descriptor configuration structure.
+ */
+void TRDC_MrcSetRegionDescriptorConfig(TRDC_Type *base, const trdc_mrc_region_descriptor_config_t *config);
+/*! @} */
+#endif
+
+#if defined(FSL_FEATURE_TRDC_HAS_MBC) && FSL_FEATURE_TRDC_HAS_MBC
+/*!
+ * @name MBC configuration
+ * @{
+ */
+#if defined(FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG) && FSL_FEATURE_TRDC_HAS_GENERAL_CONFIG
+/*!
+ * @brief Sets the TRDC MBC(Memory Block Checkers) global valid.
+ *
+ * Once enabled, it will remain enabled until next reset.
+ *
+ * @param base TRDC peripheral base address.
+ */
+static inline void TRDC_SetMbcGlobalValid(TRDC_Type *base)
+{
+    TRDC_GENERAL_BASE(base)->TRDC_CR |= TRDC_TRDC_CR_GVLDB_MASK;
+}
+#endif
+
+/*!
+ * @brief Gets the hardware configuration of the one of two slave memories within each MBC(memory block checker).
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to the structure to get the configuration.
+ * @param mbcIdx MBC number.
+ * @param slvIdx Slave number.
+ */
+void TRDC_GetMbcHardwareConfig(TRDC_Type *base,
+                               trdc_slave_memory_hardware_config_t *config,
+                               uint8_t mbcIdx,
+                               uint8_t slvIdx);
+
+/*!
+ * @brief Sets the NSR update configuration for one of the MBC instance.
+ *
+ * After set the NSE configuration, the configured memory area can be updateby NSE set/clear.
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to NSE update configuration structure.
+ * @param mbcIdx MBC index.
+ */
+void TRDC_MbcSetNseUpdateConfig(TRDC_Type *base, const trdc_mbc_nse_update_config_t *config, uint8_t mbcIdx);
+
+/*!
+ * @brief Sets the NSE bits of the selected configuration words according to NSE update configuration.
+ *
+ * This function sets the NSE bits of the word for the configured regio, memory.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mbcIdx MBC index.
+ * @param bitMask Mask of the bits whose NSE bits to set.
+ */
+void TRDC_MbcWordNseSet(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask);
+
+/*!
+ * @brief Clears the NSE bits of the selected configuration words according to NSE update configuration.
+ *
+ * This function sets the NSE bits of the word for the configured regio, memory.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mbcIdx MBC index.
+ * @param bitMask Mask of the bits whose NSE bits to clear.
+ */
+void TRDC_MbcWordNseClear(TRDC_Type *base, uint8_t mbcIdx, uint32_t bitMask);
+
+/*!
+ * @brief Clears all configuration words' NSE bits of the selected domain and memory.
+ *
+ * @param base TRDC peripheral base address.
+ * @param mbcIdx MBC index.
+ * @param domainMask Mask of the domains whose NSE bits to clear, 0b110 means clear domain 1&2.
+ * @param slaveMask Mask of the slaves whose NSE bits to clear, 0x11 means clear all slave 0&1's NSE bits.
+ */
+void TRDC_MbcNseClearAll(TRDC_Type *base, uint8_t mbcIdx, uint16_t domainMask, uint8_t slave);
+
+/*!
+ * @brief Sets the memory access configuration for one of the region descriptor of one MBC.
+ *
+ * Example: Enable the secure operations and lock the configuration for MRC0 region 1.
+ *
+ * @code
+ * trdc_memory_access_control_config_t config;
+ *
+ * config.securePrivX = true;
+ * config.securePrivW = true;
+ * config.securePrivR = true;
+ * config.lock = true;
+ * TRDC_SetMbcMemoryAccess(TRDC, &config, 0, 1);
+ * @endcode
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to the configuration structure.
+ * @param mbcIdx MBC index.
+ * @param rgdIdx Region descriptor number.
+ */
+void TRDC_MbcSetMemoryAccessConfig(TRDC_Type *base,
+                                   const trdc_memory_access_control_config_t *config,
+                                   uint8_t mbcIdx,
+                                   uint8_t rgdIdx);
+
+/*!
+ * @brief Sets the configuration for one of the memory block per domain per MBC instnce.
+ *
+ * This function sets the configuration for one of the memory block, including the memory access
+ * control policy and nse enable.
+ *
+ * @param base TRDC peripheral base address.
+ * @param config Pointer to memory block configuration structure.
+ */
+void TRDC_MbcSetMemoryBlockConfig(TRDC_Type *base, const trdc_mbc_memory_block_config_t *config);
+/*! @} */
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* FSL_TRDC_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_trdc_core.h

@@ -0,0 +1,489 @@
+/*
+ * Copyright 2022-2024 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef FSL_TRDC_CORE_H_
+#define FSL_TRDC_CORE_H_
+
+#include "fsl_trdc_soc.h"
+
+/*!
+ * @addtogroup trdc_core
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*!@brief TRDC general configuration register definition. */
+typedef struct _TRDC_General_Type
+{
+    __IO uint32_t TRDC_CR; /**< TRDC Register, offset: 0x0 */
+    uint8_t RESERVED_0[236];
+    __I uint32_t TRDC_HWCFG0; /**< TRDC Hardware Configuration Register 0, offset: 0xF0 */
+    __I uint32_t TRDC_HWCFG1; /**< TRDC Hardware Configuration Register 1, offset: 0xF4 */
+    __I uint32_t TRDC_HWCFG2; /**< TRDC Hardware Configuration Register 2, offset: 0xF8 */
+    __I uint32_t TRDC_HWCFG3; /**< TRDC Hardware Configuration Register 3, offset: 0xFC */
+    __I uint8_t DACFG[8];     /**< Domain Assignment Configuration Register, array offset: 0x100, array step: 0x1 */
+    uint8_t RESERVED_1[184];
+    __IO uint32_t TRDC_IDAU_CR; /**< TRDC IDAU Control Register, offset: 0x1C0 */
+} TRDC_General_Type;
+
+/*!@brief TRDC flash logical control register definition. */
+typedef struct _TRDC_FLW_Type
+{
+    __IO uint32_t TRDC_FLW_CTL;   /**< TRDC FLW Control, offset: 0x1E0 */
+    __I uint32_t TRDC_FLW_PBASE;  /**< TRDC FLW Physical Base, offset: 0x1E4 */
+    __IO uint32_t TRDC_FLW_ABASE; /**< TRDC FLW Array Base, offset: 0x1E8 */
+    __IO uint32_t TRDC_FLW_BCNT;  /**< TRDC FLW Block Count, offset: 0x1EC */
+} TRDC_FLW_Type;
+
+/*!@brief TRDC domain error register definition. */
+typedef struct _TRDC_DomainError_Type
+{
+    __IO uint32_t TRDC_FDID;       /**< TRDC Fault Domain ID, offset: 0x1FC */
+    __I uint32_t TRDC_DERRLOC[16]; /**< TRDC Domain Error Location Register, array offset: 0x200, array step: 0x4 */
+    uint8_t RESERVED_4[448];
+    struct
+    {                    /* offset: 0x400, array step: 0x10 */
+        __I uint32_t W0; /**< MBC Domain Error Word0 Register, array offset: 0x400, array step: 0x10 */
+        __I uint32_t W1; /**< MBC Domain Error Word1 Register, array offset: 0x404, array step: 0x10 */
+        uint8_t RESERVED_0[4];
+        __O uint32_t W3; /**< MBC Domain Error Word3 Register, array offset: 0x40C, array step: 0x10 */
+    } MBC_DERR[8];
+    struct
+    {                    /* offset: 0x480, array step: 0x10 */
+        __I uint32_t W0; /**< MRC Domain Error Word0 Register, array offset: 0x480, array step: 0x10 */
+        __I uint32_t W1; /**< MRC Domain Error Word1 Register, array offset: 0x484, array step: 0x10 */
+        uint8_t RESERVED_0[4];
+        __O uint32_t W3; /**< MRC Domain Error Word3 Register, array offset: 0x48C, array step: 0x10 */
+    } MRC_DERR[8];
+} TRDC_DomainError_Type;
+
+/*!@brief TRDC master domain assignment register definition. */
+typedef struct _TRDC_DomainAssignment_Type
+{
+    __IO uint32_t PID[8]; /**< Process Identifier, array offset: 0x700, array step: 0x4 */
+    uint8_t RESERVED_7[224];
+    union
+    {
+        struct
+        {                                 /* offset: 0x800, array step: 0x20 */
+            __IO uint32_t MDA_W_DFMT0[8]; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step:
+                                             index*0x20, index2*0x4 */
+        } MDA_DFMT0[8];
+        struct
+        {                                 /* offset: 0x800, array step: 0x20 */
+            __IO uint32_t MDA_W_DFMT1[1]; /**< DAC Master Domain Assignment Register, array offset: 0x800, array step:
+                                             index*0x20, index2*0x4 */
+            uint8_t RESERVED_0[28];
+        } MDA_DFMT1[8];
+    };
+} TRDC_DomainAssignment_Type;
+
+/*!@brief TRDC MBC control register definition. */
+typedef struct _TRDC_MBC_Type
+{
+    __I uint32_t MBC_MEM_GLBCFG[4];  /**< MBC Global Configuration Register, array offset: 0x10000, array step:
+                                        index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_NSE_BLK_INDEX; /**< MBC NonSecure Enable Block Index, array offset: 0x10010, array step: 0x2000 */
+    __O uint32_t MBC_NSE_BLK_SET;    /**< MBC NonSecure Enable Block Set, array offset: 0x10014, array step: 0x2000 */
+    __O uint32_t MBC_NSE_BLK_CLR;    /**< MBC NonSecure Enable Block Clear, array offset: 0x10018, array step: 0x2000 */
+    __O uint32_t
+        MBC_NSE_BLK_CLR_ALL; /**< MBC NonSecure Enable Block Clear All, array offset: 0x1001C, array step: 0x2000 */
+    __IO uint32_t MBC_MEMN_GLBAC[8]; /**< MBC Global Access Control, array offset: 0x10020, array step: index*0x2000,
+                                        index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10040, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10140, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10180, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x101A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x101D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM0_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x101F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_0[72];
+    __IO uint32_t MBC_DOM1_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10240, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10340, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10380, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x103A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x103D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM1_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x103F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_1[72];
+    __IO uint32_t MBC_DOM2_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10440, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10540, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10580, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x105A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x105D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM2_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x105F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_2[72];
+    __IO uint32_t MBC_DOM3_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10640, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10740, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10780, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x107A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x107D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM3_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x107F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_3[72];
+    __IO uint32_t MBC_DOM4_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10840, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10940, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10980, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x109A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x109D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM4_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x109F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_4[72];
+    __IO uint32_t MBC_DOM5_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10A40, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10B40, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10B80, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BA0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10BA8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BC8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10BD0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM5_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10BF0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_5[72];
+    __IO uint32_t MBC_DOM6_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10C40, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10D40, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10D80, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DA0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10DA8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DC8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10DD0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM6_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10DF0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_7[72];
+    __IO uint32_t MBC_DOM7_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x10E40, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10F40, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10F80, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FA0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10FA8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FC8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x10FD0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM7_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x10FF0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_8[72];
+    __IO uint32_t MBC_DOM8_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11040, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11140, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11180, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x111A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x111D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM8_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x111F0, array
+                                                  step: index*0x2000, index2*0x4 */
+
+    __IO uint32_t MBC_DOM9_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11240, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11340, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11380, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM1_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM2_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x113A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM2_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM3_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x113D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM9_MEM3_BLK_NSE_W[2];  /**< MBC Memory Block NonSecure Enable Word, array offset: 0x113F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_9[72];
+    __IO uint32_t MBC_DOM10_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11440, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11540,
+                                                   array step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11580, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x115A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x115D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM10_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x115F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_10[72];
+    __IO uint32_t MBC_DOM11_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11640, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11740,
+                                                   array step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11780, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x117A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x117D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM11_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x117F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_11[72];
+    __IO uint32_t MBC_DOM12_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11840, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11940,
+                                                   array step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11980, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119A0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x119A8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119C8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x119D0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM12_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x119F0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_12[72];
+    __IO uint32_t MBC_DOM13_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11A40, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11B40,
+                                                   array step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11B80, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BA0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11BA8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BC8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11BD0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM13_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11BF0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_13[72];
+    __IO uint32_t MBC_DOM14_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11C40, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11D40,
+                                                   array step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11D80, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DA0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11DA8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DC8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11DD0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM14_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11DF0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_14[72];
+    __IO uint32_t MBC_DOM15_MEM0_BLK_CFG_W[64]; /**< MBC Memory Block Configuration Word, array offset: 0x11E40, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM0_BLK_NSE_W[16]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11F40,
+                                                   array step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM1_BLK_CFG_W[8];  /**< MBC Memory Block Configuration Word, array offset: 0x11F80, array
+                                                   step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM1_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FA0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM2_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11FA8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM2_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FC8, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM3_BLK_CFG_W[8]; /**< MBC Memory Block Configuration Word, array offset: 0x11FD0, array
+                                                  step: index*0x2000, index2*0x4 */
+    __IO uint32_t MBC_DOM15_MEM3_BLK_NSE_W[2]; /**< MBC Memory Block NonSecure Enable Word, array offset: 0x11FF0, array
+                                                  step: index*0x2000, index2*0x4 */
+    uint8_t RESERVED_15[8];
+} TRDC_MBC_Type;
+
+/*!@brief TRDC MRC control register definition. MRC_DOM0_RGD_W[region][word] */
+typedef struct _TRDC_MRC_Type
+{
+    __I uint32_t MRC_GLBCFG; /**< MRC Global Configuration Register, array offset: 0x14000, array step: 0x1000 */
+    uint8_t RESERVED_0[12];
+    __IO uint32_t
+        MRC_NSE_RGN_INDIRECT; /**< MRC NonSecure Enable Region Indirect, array offset: 0x14010, array step: 0x1000 */
+    __O uint32_t MRC_NSE_RGN_SET; /**< MRC NonSecure Enable Region Set, array offset: 0x14014, array step: 0x1000 */
+    __O uint32_t MRC_NSE_RGN_CLR; /**< MRC NonSecure Enable Region Clear, array offset: 0x14018, array step: 0x1000 */
+    __O uint32_t
+        MRC_NSE_RGN_CLR_ALL; /**< MRC NonSecure Enable Region Clear All, array offset: 0x1401C, array step: 0x1000 */
+    __IO uint32_t
+        MRC_GLBAC[8]; /**< MRC Global Access Control, array offset: 0x14020, array step: index*0x1000, index2*0x4 */
+    __IO uint32_t MRC_DOM0_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14040, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM0_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x140C0, array step: 0x1000 */
+    uint8_t RESERVED_1[124];
+    __IO uint32_t MRC_DOM1_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14140, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM1_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x141C0, array step: 0x1000 */
+    uint8_t RESERVED_2[124];
+    __IO uint32_t MRC_DOM2_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14240, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM2_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x142C0, array step: 0x1000 */
+    uint8_t RESERVED_3[124];
+    __IO uint32_t MRC_DOM3_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14340, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM3_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x143C0, array step: 0x1000 */
+    uint8_t RESERVED_4[124];
+    __IO uint32_t MRC_DOM4_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14440, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM4_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x144C0, array step: 0x1000 */
+    uint8_t RESERVED_5[124];
+    __IO uint32_t MRC_DOM5_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14540, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM5_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x145C0, array step: 0x1000 */
+    uint8_t RESERVED_6[124];
+    __IO uint32_t MRC_DOM6_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14640, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM6_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x146C0, array step: 0x1000 */
+    uint8_t RESERVED_7[124];
+    __IO uint32_t MRC_DOM7_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14740, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM7_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x147C0, array step: 0x1000 */
+    uint8_t RESERVED_8[124];
+    __IO uint32_t MRC_DOM8_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14840, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM8_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x148C0, array step: 0x1000 */
+    uint8_t RESERVED_9[124];
+    __IO uint32_t MRC_DOM9_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                            0x14940, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM9_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x149C0, array step: 0x1000 */
+    uint8_t RESERVED_10[124];
+    __IO uint32_t MRC_DOM10_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                             0x14A40, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM10_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14AC0, array step: 0x1000 */
+    uint8_t RESERVED_11[124];
+    __IO uint32_t MRC_DOM11_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                             0x14B40, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM11_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14BC0, array step: 0x1000 */
+    uint8_t RESERVED_12[124];
+    __IO uint32_t MRC_DOM12_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                             0x14C40, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM12_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14CC0, array step: 0x1000 */
+    uint8_t RESERVED_13[124];
+    __IO uint32_t MRC_DOM13_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                             0x14D40, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM13_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14DC0, array step: 0x1000 */
+    uint8_t RESERVED_14[124];
+    __IO uint32_t MRC_DOM14_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                             0x14E40, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM14_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14EC0, array step: 0x1000 */
+    uint8_t RESERVED_15[124];
+    __IO uint32_t MRC_DOM15_RGD_W[16][2]; /**< MRC Region Descriptor Word 0..MRC Region Descriptor Word 1, array offset:
+                                             0x14F40, array step: index*0x1000, index2*0x8, index3*0x4 */
+    __IO uint32_t
+        MRC_DOM15_RGD_NSE; /**< MRC Region Descriptor NonSecure Enable, array offset: 0x14FC0, array step: 0x1000 */
+} TRDC_MRC_Type;
+
+/*!@brief TRDC base address convert macro */
+#define TRDC_GENERAL_BASE(base)      ((TRDC_General_Type *)((base)))
+#define TRDC_FLW_BASE(base)          ((TRDC_FLW_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_FLW_OFFSET)))
+#define TRDC_DOMAIN_ERROR_BASE(base) ((TRDC_DomainError_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_DOMAIN_ERROR_OFFSET)))
+#define TRDC_DOMAIN_ASSIGNMENT_BASE(base) \
+    ((TRDC_DomainAssignment_Type *)(((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_DOMAIN_ASSIGNMENT_OFFSET)))
+#define TRDC_MBC_BASE(base, instance) \
+    ((TRDC_MBC_Type *)((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_MBC_OFFSET(base) + (instance) * (uint32_t)TRDC_MBC_ARRAY_STEP))
+#define TRDC_MRC_BASE(base, instance) \
+    ((TRDC_MRC_Type *)((uint32_t)(uintptr_t)(base) + (uint32_t)TRDC_MRC_OFFSET(base) + (instance) * (uint32_t)TRDC_MRC_ARRAY_STEP))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* FSL_TRDC_CORE_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_trdc_soc.h

@@ -0,0 +1,60 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_TRDC_SOC_H_
+#define _FSL_TRDC_SOC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup trdc_soc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+ /* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.trdc_soc"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Driver version 2.0.0. */
+#define FSL_TRDC_SOC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define TRDC_MBC_MEM_GLBCFG_NBLKS_MASK      0x000003FFUL
+#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_MASK  0x001F0000UL
+#define TRDC_MBC_MEM_GLBCFG_SIZE_LOG2_SHIFT 16U
+#define TRDC_MBC_NSE_BLK_CLR_ALL_MEMSEL(x)  (((uint32_t)(x) & 0xFUL) << 8U)
+#define TRDC_MBC_NSE_BLK_CLR_ALL_DID_SEL(x) (((uint32_t)(x) & 0x1UL) << 16U)
+
+/*!@brief TRDC feature */
+#define FSL_FEATURE_TRDC_DOMAIN_COUNT 1
+
+/*!@brief TRDC base address convert macro */
+#define TRDC_MBC_COUNT 1
+#define TRDC_MBC_OFFSET(x)  0x0000 /* MBC register offset in TRDC_Type structure. */
+#define TRDC_MBC_ARRAY_STEP 0U     /* Offset between two MBC control block, useless if there is only one. */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _FSL_TRDC_SOC_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_utick.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_UTICK_H_
-#define _FSL_UTICK_H_
+#ifndef FSL_UTICK_H_
+#define FSL_UTICK_H_
 
 #include "fsl_common.h"
 /*!
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief UTICK driver version 2.0.5. */
 #define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 5))
-/*@}*/
+/*! @} */
 
 /*! @brief UTICK timer operational mode. */
 typedef enum _utick_mode
@@ -107,7 +107,7 @@ void UTICK_SetTick(UTICK_Type *base, utick_mode_t mode, uint32_t count, utick_ca
  */
 void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
 
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -115,4 +115,4 @@ void UTICK_HandleIRQ(UTICK_Type *base, utick_callback_t cb);
 
 /*! @}*/
 
-#endif /* _FSL_UTICK_H_ */
+#endif /* FSL_UTICK_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_vbat.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -78,7 +78,7 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,
 
     if (operateMode == kVBAT_Osc32kEnabledToLowPowerBackupMode)
     {
-        if ((extalCap & 0x1U) != 0U)
+        if (((uint8_t)extalCap & 0x1U) != 0U)
         {
             return kStatus_VBAT_WrongCapacitanceValue;
         }
@@ -91,11 +91,11 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,
         base->OSCCTLA = ((base->OSCCTLA & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) |
                          (VBAT_OSCCTLA_XTAL_CAP_SEL(xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(extalCap)));
         base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_EXTAL_CAP_SEL_MASK | VBAT_OSCCTLA_XTAL_CAP_SEL_MASK)) |
-                         VBAT_OSCCTLA_XTAL_CAP_SEL(~xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~extalCap));
+                         VBAT_OSCCTLA_XTAL_CAP_SEL(~(uint32_t)xtalCap) | VBAT_OSCCTLA_EXTAL_CAP_SEL(~(uint32_t)extalCap));
     }
 
     base->OSCCTLA = (((base->OSCCTLA & ~VBAT_OSCCTLA_MODE_EN_MASK)) | VBAT_OSCCTLA_MODE_EN(operateMode));
-    base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN((uint8_t)~operateMode));
+    base->OSCCTLB = ((base->OSCCTLB & ~VBAT_OSCCTLA_MODE_EN_MASK) | VBAT_OSCCTLA_MODE_EN(~(uint32_t)operateMode));
 
     return kStatus_Success;
 }

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_vbat.h

@@ -1,12 +1,12 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2024 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef _FSL_VBAT_H_
-#define _FSL_VBAT_H_
+#ifndef FSL_VBAT_H_
+#define FSL_VBAT_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,16 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief VBAT driver version 2.2.0. */
-#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
+/*! @brief VBAT driver version 2.3.1. */
+#define FSL_VBAT_DRIVER_VERSION (MAKE_VERSION(2, 3, 1))
 /*@}*/
 
+#if !defined(VBAT_LDORAMC_RET_MASK)
+#define VBAT_LDORAMC_RET_MASK   (0xF00U)
+#define VBAT_LDORAMC_RET_SHIFT  (8U) 
+#define VBAT_LDORAMC_RET(x)     (((uint32_t)(((uint32_t)(x)) << VBAT_LDORAMC_RET_SHIFT)) & VBAT_LDORAMC_RET_MASK)
+#endif 
+
 /*!
  * @brief The enumeration of VBAT module status.
  */
@@ -527,7 +533,7 @@ static inline void VBAT_EnableCrystalOsc32k(VBAT_Type *base, bool enable)
 
         /* Polling status register to check clock is ready. */
         while ((base->STATUSA & VBAT_STATUSA_OSC_RDY_MASK) == 0UL)
-            ;
+        {}
     }
     else
     {
@@ -561,6 +567,7 @@ static inline void VBAT_BypassCrystalOsc32k(VBAT_Type *base, bool enableBypass)
     }
 }
 
+#if (defined(FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) && FSL_FEATURE_MCX_VBAT_HAS_OSCCTLA_FINE_AMP_GAIN_BIT) 
 /*!
  * @brief Adjust 32k crystal oscillator amplifier gain.
  *
@@ -575,6 +582,20 @@ static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_
     base->OSCCTLB = ((base->OSCCTLB & ~(VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK | VBAT_OSCCTLA_FINE_AMP_GAIN_MASK)) |
                      (VBAT_OSCCTLA_COARSE_AMP_GAIN(~coarse) | VBAT_OSCCTLA_FINE_AMP_GAIN(~fine)));
 }
+#else
+/*!
+ * @brief Adjust 32k crystal oscillator amplifier gain.
+ *
+ * @param base VBAT peripheral base address.
+ * @param coarse Specify amplifier coarse trim value.
+ */
+static inline void VBAT_AdjustCrystalOsc32kAmplifierGain(VBAT_Type *base, uint8_t coarse)
+{
+    base->OSCCTLA = (base->OSCCTLA & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(coarse));
+    base->OSCCTLB = (base->OSCCTLB & ~VBAT_OSCCTLA_COARSE_AMP_GAIN_MASK) | (VBAT_OSCCTLA_COARSE_AMP_GAIN(~(uint32_t)coarse));        
+}
+
+#endif /*  */
 
 /*!
  * @brief Set 32k crystal oscillator mode and load capacitance for the XTAL/EXTAL pin.
@@ -602,7 +623,7 @@ status_t VBAT_SetCrystalOsc32kModeAndLoadCapacitance(VBAT_Type *base,
 static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32k_start_up_time_t startupTime)
 {
     base->OSCCFGA = ((base->OSCCFGA & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(startupTime));
-    base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~startupTime));
+    base->OSCCFGB = ((base->OSCCFGB & ~(VBAT_OSCCFGA_INIT_TRIM_MASK)) | VBAT_OSCCFGA_INIT_TRIM(~((uint32_t)startupTime)));
 }
 
 /*!
@@ -614,7 +635,7 @@ static inline void VBAT_TrimCrystalOsc32kStartupTime(VBAT_Type *base, vbat_osc32
 static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base, uint8_t comparatorTrimValue)
 {
     base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(comparatorTrimValue));
-    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~comparatorTrimValue));
+    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CMP_TRIM_MASK) | VBAT_OSCCFGA_CMP_TRIM(~((uint32_t)comparatorTrimValue)));
 }
 
 /*!
@@ -626,7 +647,7 @@ static inline void VBAT_SetOsc32kSwitchModeComparatorTrimValue(VBAT_Type *base,
 static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8_t delayTrimValue)
 {
     base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(delayTrimValue));
-    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~delayTrimValue));
+    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_DLY_TRIM_MASK) | VBAT_OSCCFGA_DLY_TRIM(~((uint32_t)delayTrimValue)));
 }
 
 /*!
@@ -638,7 +659,7 @@ static inline void VBAT_SetOsc32kSwitchModeDelayTrimValue(VBAT_Type *base, uint8
 static inline void VBAT_SetOsc32kSwitchModeCapacitorTrimValue(VBAT_Type *base, uint8_t capacitorTrimValue)
 {
     base->OSCCFGA = ((base->OSCCFGA & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(capacitorTrimValue));
-    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~capacitorTrimValue));
+    base->OSCCFGB = ((base->OSCCFGB & ~VBAT_OSCCFGA_CAP_TRIM_MASK) | VBAT_OSCCFGA_CAP_TRIM(~((uint32_t)capacitorTrimValue)));
 }
 
 /*!
@@ -835,7 +856,7 @@ static inline void VBAT_SwitchSRAMPowerBySocSupply(VBAT_Type *base)
  */
 static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)
 {
-    base->LDORAMC |= VBAT_LDORAMC_RET(sramMask);
+    base->LDORAMC |= (uint32_t)VBAT_LDORAMC_RET(sramMask);
 }
 
 /*!
@@ -846,7 +867,7 @@ static inline void VBAT_PowerOffSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sr
  */
 static inline void VBAT_RetainSRAMsInLowPowerModes(VBAT_Type *base, uint8_t sramMask)
 {
-    base->LDORAMC &= ~VBAT_LDORAMC_RET(sramMask);
+    base->LDORAMC &= ~(uint32_t)VBAT_LDORAMC_RET(sramMask);
 }
 
 /*!
@@ -951,7 +972,7 @@ static inline void VBAT_SwitchVBATModuleSupplyActiveMode(VBAT_Type *base, vbat_i
  */
 static inline vbat_internal_module_supply_t VBAT_GetVBATModuleSupply(VBAT_Type *base)
 {
-    return (base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK);
+    return (vbat_internal_module_supply_t)(uint8_t)(base->SWICTLA & VBAT_SWICTLA_SWI_EN_MASK);
 }
 
 /*!
@@ -1362,4 +1383,4 @@ static inline void VBAT_SetWakeupPinDefaultState(VBAT_Type *base, bool assert)
 /*!
  * @}
  */
-#endif /* __FSL_VBAT_H__ */
+#endif /* FSL_VBAT_H__ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_waketimer.h

@@ -4,8 +4,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_WAKETIMER_H_
-#define _FSL_WAKETIMER_H_
+#ifndef FSL_WAKETIMER_H_
+#define FSL_WAKETIMER_H_
 
 #include "fsl_common.h"
 
@@ -21,10 +21,10 @@
  ******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief WAKETIMER driver version. */
 #define FSL_WAKETIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
-/*@}*/
+/*! @} */
 
 /*!
  * @brief WAKETIMER status flags.
@@ -209,4 +209,4 @@ uint32_t WAKETIMER_GetCurrentTimerValue(WAKETIMER_Type *base);
 
 /*! @}*/
 
-#endif /* _FSL_WAKETIMER_H_ */
+#endif /* FSL_WAKETIMER_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_wuu.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2019-2023 NXP.
+ * Copyright 2019-2024 NXP.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -118,6 +118,26 @@ void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu
     }
 }
 
+/*!
+ * brief Disable and clear external wakeup pin settings.
+ * 
+ * param base MUU peripheral base address.
+ * param pinIndex The index of the external input pin.
+ */
+void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex)
+{
+    if (pinIndex <= 15U)
+    {
+        base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex));
+        base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)pinIndex));
+    }
+    else
+    {
+        base->PE1 &= ~(WUU_PE_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL)));
+        base->PDC1 &= ~(WUU_PDC_REG_BIT_FIELD_MASK << (2UL * (uint32_t)((uint32_t)pinIndex % 16UL)));
+    }
+}
+
 /*!
  * brief Config Internal modules' event as the wake up soures.
  *

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_wuu.h

@@ -1,11 +1,11 @@
 /*
- * Copyright 2019-2023 NXP.
+ * Copyright 2019-2024 NXP.
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_WUU_H_
-#define _FSL_WUU_H_
+#ifndef FSL_WUU_H_
+#define FSL_WUU_H_
 
 #include "fsl_common.h"
 
@@ -17,10 +17,10 @@
  *******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
-/*! @brief Defines WUU driver version 2.3.0. */
-#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
-/*@}*/
+/*! @{ */
+/*! @brief Defines WUU driver version 2.4.0. */
+#define FSL_WUU_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
+/*! @} */
 
 /*!
  * @brief External WakeUp pin edge detection enumeration.
@@ -135,6 +135,14 @@ extern "C" {
  */
 void WUU_SetExternalWakeUpPinsConfig(WUU_Type *base, uint8_t pinIndex, const wuu_external_wakeup_pin_config_t *config);
 
+/*!
+ * @brief Disable and clear external wakeup pin settings.
+ * 
+ * @param base MUU peripheral base address.
+ * @param pinIndex The index of the external input pin.
+ */
+void WUU_ClearExternalWakeupPinsConfig(WUU_Type *base, uint8_t pinIndex);
+
 /*!
  * @brief Gets External Wakeup pin flags.
  *
@@ -160,7 +168,7 @@ static inline void WUU_ClearExternalWakeUpPinsFlag(WUU_Type *base, uint32_t mask
 {
     base->PF = mask;
 }
-/* @} */
+/*! @} */
 
 /*!
  * @name Internal Wakeup Module control APIs.
@@ -215,7 +223,7 @@ static inline bool WUU_GetInternalWakeupModuleFlag(WUU_Type *base, uint32_t modu
 }
 #endif /* FSL_FEATURE_WUU_HAS_MF */
 
-/* @} */
+/*! @} */
 
 /*!
  * @name Pin Filter Control APIs
@@ -275,7 +283,7 @@ bool WUU_GetExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex);
  * param pinIndex A pin index, which starts from 0.
  */
 void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex);
-/* @} */
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -283,4 +291,4 @@ void WUU_ClearExternalWakeupPinFlag(WUU_Type *base, uint32_t pinIndex);
 
 /*! @} */
 
-#endif /*_FSL_WUU_H_*/
+#endif /*FSL_WUU_H_*/

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/drivers/fsl_wwdt.h

@@ -5,8 +5,8 @@
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
-#ifndef _FSL_WWDT_H_
-#define _FSL_WWDT_H_
+#ifndef FSL_WWDT_H_
+#define FSL_WWDT_H_
 
 #include "fsl_common.h"
 
@@ -22,16 +22,16 @@
  *******************************************************************************/
 
 /*! @name Driver version */
-/*@{*/
+/*! @{ */
 /*! @brief Defines WWDT driver version. */
 #define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 9))
-/*@}*/
+/*! @} */
 
 /*! @name Refresh sequence */
-/*@{*/
+/*! @{ */
 #define WWDT_FIRST_WORD_OF_REFRESH  (0xAAU) /*!< First word of refresh sequence */
 #define WWDT_SECOND_WORD_OF_REFRESH (0x55U) /*!< Second word of refresh sequence */
-/*@}*/
+/*! @} */
 
 /*! @brief Describes WWDT configuration structure. */
 typedef struct _wwdt_config
@@ -126,7 +126,7 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config);
  */
 void WWDT_Deinit(WWDT_Type *base);
 
-/* @} */
+/*! @} */
 
 /*!
  * @name WWDT Functional Operation
@@ -265,7 +265,7 @@ static inline void WWDT_SetWindowValue(WWDT_Type *base, uint32_t windowValue)
  */
 void WWDT_Refresh(WWDT_Type *base);
 
-/*@}*/
+/*! @} */
 
 #if defined(__cplusplus)
 }
@@ -273,4 +273,4 @@ void WWDT_Refresh(WWDT_Type *base);
 
 /*! @}*/
 
-#endif /* _FSL_WWDT_H_ */
+#endif /* FSL_WWDT_H_ */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/fsl_device_registers.h

@@ -1,6 +1,6 @@
 /*
  * Copyright 2014-2016 Freescale Semiconductor, Inc.
- * Copyright 2016-2023 NXP
+ * Copyright 2016-2024 NXP
  * SPDX-License-Identifier: BSD-3-Clause
  *
  */
@@ -13,7 +13,8 @@
  *
  * The CPU macro should be declared in the project or makefile.
  */
-#if (defined(CPU_MCXA153VFM) || defined(CPU_MCXA153VFT) || defined(CPU_MCXA153VLH))
+#if (defined(CPU_MCXA153VFM) || defined(CPU_MCXA153VFT) || defined(CPU_MCXA153VLF) || \
+    defined(CPU_MCXA153VLH))
 
 #define MCXA153_SERIES
 

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/gcc/MCXA153_flash.ld

@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            GNU C Compiler
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/gcc/MCXA153_ram.ld

@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            GNU C Compiler
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the GNU C Compiler
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/gcc/startup_MCXA153.S

@@ -4,11 +4,11 @@
 /*            MCXA153                                                        */
 /*  @version: 1.0                                                            */
 /*  @date:    2022-3-29                                                      */
-/*  @build:   b231018                                                        */
+/*  @build:   b240401                                                        */
 /* ------------------------------------------------------------------------- */
 /*                                                                           */
 /* Copyright 1997-2016 Freescale Semiconductor, Inc.                         */
-/* Copyright 2016-2023 NXP                                                   */
+/* Copyright 2016-2024 NXP                                                   */
 /* SPDX-License-Identifier: BSD-3-Clause                                     */
 /*****************************************************************************/
 /* Version: GCC for ARM Embedded Processors                                  */

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/iar/MCXA153_flash.icf

@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/iar/MCXA153_ram.icf

@@ -2,18 +2,19 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compiler:            IAR ANSI C/C++ Compiler for ARM
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230411
+**     Build:               b240403
 **
 **     Abstract:
 **         Linker file for the IAR ANSI C/C++ Compiler for ARM
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/iar/startup_MCXA153.s

@@ -4,11 +4,11 @@
 ;            MCXA153
 ;  @version: 1.0
 ;  @date:    2022-3-29
-;  @build:   b230804
+;  @build:   b240401
 ; -------------------------------------------------------------------------
 ;
 ; Copyright 1997-2016 Freescale Semiconductor, Inc.
-; Copyright 2016-2023 NXP
+; Copyright 2016-2024 NXP
 ; SPDX-License-Identifier: BSD-3-Clause
 ;
 ; The modules in this file are included in the libraries, and may be replaced

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/system_MCXA153.c

@@ -2,6 +2,7 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compilers:           GNU C Compiler
@@ -11,7 +12,7 @@
 **
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230725
+**     Build:               b240403
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
@@ -19,7 +20,7 @@
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com
@@ -79,8 +80,34 @@ __attribute__ ((weak)) void SystemInit (void) {
     /* Enable the LPCAC */
     SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_LPCAC_MEM_REQ_MASK;
     SYSCON->LPCAC_CTRL &= ~SYSCON_LPCAC_CTRL_DIS_LPCAC_MASK;
-    /* Disable AGDET RESET */
-    SPC0->GLITCH_DETECT_SC &= ~SPC_GLITCH_DETECT_SC_RE_MASK;
+
+    /* Enable flash RWX when FLASH_ACL in IFR0 is invalid */
+    if ((*((volatile const uint32_t *)(0x1000000)) == 0xFFFFFFFFU) ||
+        ((*((volatile const uint32_t *)(0x1000000)) == 0x59630000U) &&
+         (*((volatile const uint32_t *)(0x1000040)) == 0xFFFFFFFFU) &&
+         (*((volatile const uint32_t *)(0x1000044)) == 0xFFFFFFFFU)))
+    {
+        /* Enable MBC register written with GLIKEY index15 */
+        GLIKEY0->CTRL_0 = 0x00060000U;
+        GLIKEY0->CTRL_0 = 0x0002000FU;
+        GLIKEY0->CTRL_0 = 0x0001000FU;
+        GLIKEY0->CTRL_1 = 0x00290000U;
+        GLIKEY0->CTRL_0 = 0x0002000FU;
+        GLIKEY0->CTRL_1 = 0x00280000U;
+        GLIKEY0->CTRL_0 = 0x0000000FU;
+
+        /* Enable RWX for GLBAC0 */
+        MBC0->MBC_INDEX[0].MBC_MEMN_GLBAC[0] = 0x7700U;
+
+        /* Use GLBAC0 for all flash block */
+        for (uint8_t i = 0; i < 2U; i++)
+        {
+            MBC0->MBC_INDEX[0].MBC_DOM0_MEM0_BLK_CFG_W[i] = 0x00000000U;
+        }
+
+        /* Disable MBC register written */
+        GLIKEY0->CTRL_0 = 0x0002000FU;
+    }
   SystemInitHook();
 }
 

bsp/nxp/mcx/mcxa/Libraries/MCXA153/MCXA153/system_MCXA153.h

@@ -2,6 +2,7 @@
 ** ###################################################################
 **     Processors:          MCXA153VFM
 **                          MCXA153VFT
+**                          MCXA153VLF
 **                          MCXA153VLH
 **
 **     Compilers:           GNU C Compiler
@@ -11,7 +12,7 @@
 **
 **     Reference manual:    MCXA1 User manual
 **     Version:             rev. 1.0, 2022-03-29
-**     Build:               b230725
+**     Build:               b240403
 **
 **     Abstract:
 **         Provides a system configuration function and a global variable that
@@ -19,7 +20,7 @@
 **         the oscillator (PLL) that is part of the microcontroller device.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2023 NXP
+**     Copyright 2016-2024 NXP
 **     SPDX-License-Identifier: BSD-3-Clause
 **
 **     http:                 www.nxp.com