port rt-thread to NEC V850E

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@779 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/upd70f3454/Backup of upd70f3454.ewp

@@ -0,0 +1,1644 @@
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+				</option>
+				<option>
+					<name>xcOverrideProgramEntryLabel</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>xcProgramEntryLabelSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ListOutputFormat</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>BufferedTermOutput</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XlinkStackSize</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XcRTLibraryFile</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OXLibIOConfig</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XLibraryHeap</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XLinkMisraHandler</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OverlaySystemMap</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RawBinaryFile</name>
+					<state />
+				</option>
+				<option>
+					<name>RawBinarySymbol</name>
+					<state />
+				</option>
+				<option>
+					<name>RawBinarySegment</name>
+					<state />
+				</option>
+				<option>
+					<name>RawBinaryAlign</name>
+					<state />
+				</option>
+				<option>
+					<name>CrcAlign</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcInitialValue</name>
+					<state>0x0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>XAR</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<version>0</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>1</debug>
+				<option>
+					<name>XAROutOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XARInputs</name>
+					<state />
+				</option>
+				<option>
+					<name>OutputFile</name>
+					<state />
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>BILINK</name>
+			<archiveVersion>0</archiveVersion>
+			<data />
+		</settings>
+	</configuration>
+	<configuration>
+		<name>Release</name>
+		<toolchain>
+			<name>V850</name>
+		</toolchain>
+		<debug>0</debug>
+		<settings>
+			<name>General</name>
+			<archiveVersion>5</archiveVersion>
+			<data>
+				<version>5</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>0</debug>
+				<option>
+					<name>GMemoryModel</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>GUseShort</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCodeModel</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ExePath</name>
+					<state>Release\Exe</state>
+				</option>
+				<option>
+					<name>ObjPath</name>
+					<state>Release\Obj</state>
+				</option>
+				<option>
+					<name>ListPath</name>
+					<state>Release\List</state>
+				</option>
+				<option>
+					<name>GeneralStack</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>GOutputBinary</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>GRuntimeLibSelect</name>
+					<version>0</version>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RTDescription</name>
+					<state />
+				</option>
+				<option>
+					<name>RTConfigPath</name>
+					<state>xxx.h</state>
+				</option>
+				<option>
+					<name>RTLibraryPath</name>
+					<state>xxx.r85</state>
+				</option>
+				<option>
+					<name>GRuntimeLibSelectSlave</name>
+					<version>0</version>
+					<state>1</state>
+				</option>
+				<option>
+					<name>Input variant</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>Input description</name>
+					<state />
+				</option>
+				<option>
+					<name>Output variant</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>Output description</name>
+					<state />
+				</option>
+				<option>
+					<name>GHeapSize</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>GeneralEnableMisra</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>GeneralMisraVerbose</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>GDeviceSelect</name>
+					<state>70F3746	V850ES- uPD70F3746</state>
+				</option>
+				<option>
+          				<name>GeneralMisraVer</name>
+          				<state>0</state>
+        			</option>
+        			<option>
+          				<name>GeneralMisraRules04</name>
+          				<version>0</version>
+          				<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        			</option>
+        			<option>
+          				<name>GeneralMisraRules98</name>
+          				<version>0</version>
+          				<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        			</option>
+			</data>
+		</settings>
+		<settings>
+			<name>ICCV850</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<version>14</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>0</debug>
+				<option>
+					<name>CCDefines</name>
+					<state>NDEBUG</state>
+				</option>
+				<option>
+					<name>CCPreprocFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCPreprocComments</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCPreprocLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListCFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListCMnemonics</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListCMessages</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListAssFile</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCListAssSource</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCEnableRemarks</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCDiagSuppress</name>
+					<state />
+				</option>
+				<option>
+					<name>CCDiagRemark</name>
+					<state />
+				</option>
+				<option>
+					<name>CCDiagWarning</name>
+					<state />
+				</option>
+				<option>
+					<name>CCDiagError</name>
+					<state />
+				</option>
+				<option>
+					<name>IProcessor</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IMemory</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>ICode</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCObjPrefix</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCAllowList</name>
+					<version>1</version>
+					<state>11111</state>
+				</option>
+				<option>
+					<name>CCObjUseModuleName</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCObjModuleName</name>
+					<state />
+				</option>
+				<option>
+					<name>CCDebugInfo</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCLockedRegs</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IRegConstCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCDiagWarnAreErr</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCEnableMigration</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IRegConstCompCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCompilerRuntimeInfo</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCMultiByte</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCDisableSldSuppression</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OutputFile</name>
+					<state />
+				</option>
+				<option>
+					<name>CCLibConfigHeader</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCRequirePrototypes</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCCharIs</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CCExt</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCLangSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CompilerMisraOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>PreInclude</name>
+					<state />
+				</option>
+				<option>
+					<name>CCEnableMisalignedData</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCIncludePath2</name>
+					<state />
+				</option>
+				<option>
+					<name>CCStdIncCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCStdIncludePath</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>IccExtraOptionsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IccExtraOptions</name>
+					<state />
+				</option>
+				<option>
+					<name>CCOverrideModuleTypeDefault</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRadioModuleType</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CCRadioModuleTypeSlave</name>
+					<state>1</state>
+				</option>
+				<option>
+          				<name>CompilerMisraRules04</name>
+          				<version>0</version>
+          				<state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        			</option>
+        			<option>
+          				<name>CompilerMisraRules98</name>
+          				<version>0</version>
+          				<state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        			</option>
+  				<option>
+          				<name>CCOptLevel</name>
+          				<state>3</state>
+        			</option>
+        			<option>
+          				<name>CCOptStrategy</name>
+          				<version>0</version>
+          				<state>1</state>
+        			</option>
+        			<option>
+          				<name>CCOptLevelSlave</name>
+          				<state>3</state>
+        			</option>
+			</data>
+		</settings>
+		<settings>
+			<name>AV850</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<version>5</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>0</debug>
+				<option>
+					<name>AObjPrefix</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AProcessor</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>MacroChars</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ACaseSensitivity</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AList</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AListHeader</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AListing</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>Includes</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MacDefs</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MacExps</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>MacExec</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OnlyAssed</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>MultiLine</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>NoStrAsmList</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>PageLengthCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>PageLength</name>
+					<state>80</state>
+				</option>
+				<option>
+					<name>TabSpacing</name>
+					<state>8</state>
+				</option>
+				<option>
+					<name>AXRef</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AXRefDefines</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AXRefInternal</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AXRefDual</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ADefines</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>AWarnEnable</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnWhat</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AWarnOne</name>
+					<state />
+				</option>
+				<option>
+					<name>AWarnRange1</name>
+					<state />
+				</option>
+				<option>
+					<name>AWarnRange2</name>
+					<state />
+				</option>
+				<option>
+					<name>ADebugNew</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AMultiBytes</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OutputFile</name>
+					<state />
+				</option>
+				<option>
+					<name>Multibyte</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OAIncludePath2</name>
+					<state />
+				</option>
+				<option>
+					<name>OAStdIncCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OAStdIncludePath</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>AMaxErrChk</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AMaxNumErr</name>
+					<state>100</state>
+				</option>
+				<option>
+					<name>AsmExtraOptionsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>AsmExtraOptions</name>
+					<state />
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>CUSTOM</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<extensions />
+				<cmdline />
+			</data>
+		</settings>
+		<settings>
+			<name>BICOMP</name>
+			<archiveVersion>0</archiveVersion>
+			<data />
+		</settings>
+		<settings>
+			<name>BUILDACTION</name>
+			<archiveVersion>1</archiveVersion>
+			<data>
+				<prebuild />
+				<postbuild />
+			</data>
+		</settings>
+		<settings>
+			<name>XLINK</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<version>15</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>0</debug>
+				<option>
+					<name>XOutOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OutputFile</name>
+					<state />
+				</option>
+				<option>
+					<name>OutputFormat</name>
+					<version>11</version>
+					<state>23</state>
+				</option>
+				<option>
+					<name>FormatVariant</name>
+					<version>8</version>
+					<state>2</state>
+				</option>
+				<option>
+					<name>SecondaryOutputFile</name>
+					<state />
+				</option>
+				<option>
+					<name>XDefines</name>
+					<state />
+				</option>
+				<option>
+					<name>AlwaysOutput</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OverlapWarnings</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>NoGlobalCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XList</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>SegmentMap</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>ListSymbols</name>
+					<state>2</state>
+				</option>
+				<option>
+					<name>PageLengthCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>PageLength</name>
+					<state>80</state>
+				</option>
+				<option>
+					<name>XIncludes</name>
+					<state>###Uninitialized###</state>
+				</option>
+				<option>
+					<name>ModuleStatus</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XclOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XclFile</name>
+					<state>lnk0t.xcl</state>
+				</option>
+				<option>
+					<name>XclFileSlave</name>
+					<state />
+				</option>
+				<option>
+					<name>XExtraOptionsCheck</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XExtraOptions</name>
+					<state />
+				</option>
+				<option>
+					<name>DoFill</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>FillerByte</name>
+					<state>0xFF</state>
+				</option>
+				<option>
+					<name>DoCrc</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CrcSize</name>
+					<version>0</version>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcAlgo</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcPoly</name>
+					<state>0x11021</state>
+				</option>
+				<option>
+					<name>CrcCompl</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RangeCheckAlternatives</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>SuppressAllWarn</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>SuppressDiags</name>
+					<state />
+				</option>
+				<option>
+					<name>TreatAsWarn</name>
+					<state />
+				</option>
+				<option>
+					<name>TreatAsErr</name>
+					<state />
+				</option>
+				<option>
+					<name>ModuleLocalSym</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>CrcBitOrder</name>
+					<version>0</version>
+					<state>0</state>
+				</option>
+				<option>
+					<name>IncludeSuppressed</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ModuleSummary</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>xcProgramEntryLabel</name>
+					<state />
+				</option>
+				<option>
+					<name>DebugInformation</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>RuntimeControl</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>IoEmulation</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>AllowExtraOutput</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>GenerateExtraOutput</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XExtraOutOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ExtraOutputFile</name>
+					<state />
+				</option>
+				<option>
+					<name>ExtraOutputFormat</name>
+					<version>11</version>
+					<state>23</state>
+				</option>
+				<option>
+					<name>ExtraFormatVariant</name>
+					<version>8</version>
+					<state>2</state>
+				</option>
+				<option>
+					<name>xcOverrideProgramEntryLabel</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>xcProgramEntryLabelSelect</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>ListOutputFormat</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>BufferedTermOutput</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XlinkStackSize</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XcRTLibraryFile</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>OXLibIOConfig</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XLibraryHeap</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>XLinkMisraHandler</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>OverlaySystemMap</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>RawBinaryFile</name>
+					<state />
+				</option>
+				<option>
+					<name>RawBinarySymbol</name>
+					<state />
+				</option>
+				<option>
+					<name>RawBinarySegment</name>
+					<state />
+				</option>
+				<option>
+					<name>RawBinaryAlign</name>
+					<state />
+				</option>
+				<option>
+					<name>CrcAlign</name>
+					<state>1</state>
+				</option>
+				<option>
+					<name>CrcInitialValue</name>
+					<state>0x0</state>
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>XAR</name>
+			<archiveVersion>3</archiveVersion>
+			<data>
+				<version>0</version>
+				<wantNonLocal>1</wantNonLocal>
+				<debug>0</debug>
+				<option>
+					<name>XAROutOverride</name>
+					<state>0</state>
+				</option>
+				<option>
+					<name>XARInputs</name>
+					<state />
+				</option>
+				<option>
+					<name>OutputFile</name>
+					<state />
+				</option>
+			</data>
+		</settings>
+		<settings>
+			<name>BILINK</name>
+			<archiveVersion>0</archiveVersion>
+			<data />
+		</settings>
+	</configuration>
+	<file>
+	</file>
+<file><name>$PROJ_DIR$\applilet3_src\CG_main.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_systeminit.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_option.s85</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_system.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_system_user.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_port.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_port_user.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_serial.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_serial_user.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_timer.c</name></file><file><name>$PROJ_DIR$\applilet3_src\CG_timer_user.c</name></file></project>

bsp/upd70f3454/Debug/Obj/upd70f3454.pbd

@@ -0,0 +1,43 @@
+This is an internal working file generated by the Source Browser.
+10:24 01s
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_port.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_port_user.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_system.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_system_user.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_systeminit.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_timer.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\CG_timer_user.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\application.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\board.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\clock.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\cmd.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\device.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_compiler.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_error.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_heap.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_init.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_node.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_ops.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_parser.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_token.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_var.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\finsh_vm.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\idle.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\interrupt.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\ipc.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\irq.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\kservice.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\mem.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\mempool.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\module.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\object.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\rtm.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\scheduler.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\shell.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\slab.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\stack.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\startup.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\symbol.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\thread.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\timer.pbi
+E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\Debug\Obj\uart.pbi

bsp/upd70f3454/application.c

@@ -0,0 +1,62 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2010-06-29     lgnq         the first version
+ *
+ * For       : NEC V850E
+ * Toolchain : IAR Embedded Workbench for V850 v3.71
+*/
+
+#include <rtthread.h>
+#include "board.h"
+#include "CG_macrodriver.h"
+#include "CG_system.h"
+#include "CG_port.h"
+#include "CG_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+static struct rt_thread led;
+
+#if defined(__ICCM16C__) || defined(__ICCV850__)
+#pragma data_alignment=4
+#endif
+static rt_uint8_t led_stack[256];
+
+static void rt_thread_entry_led(void* parameter)
+{
+    while (1)
+    {
+        /* led off */
+        led_off();
+        rt_thread_delay(20); /* sleep 1 second and switch to other thread */
+        /* led on */
+        led_on();
+        rt_thread_delay(40);
+    }
+}
+
+int rt_application_init(void)
+{
+    /* create led thread */
+	rt_thread_init(&led,
+		"led",
+		rt_thread_entry_led, RT_NULL,
+		&led_stack[0], sizeof(led_stack),
+		5, 32);
+    
+    if (&led != RT_NULL)
+        rt_thread_startup(&led);
+        
+    return 0;
+}

bsp/upd70f3454/applilet3_src/CG_macrodriver.h

@@ -0,0 +1,110 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_macrodriver.h
+* Abstract:	This file implements general head file.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+#ifndef _MDSTATUS_
+#define _MDSTATUS_
+/*
+*******************************************************************************
+**  Include files
+*******************************************************************************
+*/
+#include <intrinsics.h>
+#include "io70f3454.h"
+/*
+*******************************************************************************
+**  Register bit define
+*******************************************************************************
+*/
+/*
+*******************************************************************************
+**  Macro define
+*******************************************************************************
+*/
+#define	DI	__disable_interrupt
+#define	EI	__enable_interrupt
+#define	NOP	__no_operation
+#define	HALT	__halt
+
+/* Data type defintion */
+typedef	unsigned long	ULONG;
+typedef	signed long	SLONG;
+
+typedef	unsigned int	UINT;
+typedef	signed int	SINT;
+
+typedef	unsigned short	USHORT;
+typedef	signed short	SHORT;
+
+typedef	unsigned char	UCHAR;
+typedef	signed char	SCHAR;
+
+typedef	unsigned char	BOOL;
+typedef	unsigned short	MD_STATUS;
+
+#define	MD_ON		1U
+#define	MD_OFF		0U
+
+#define	MD_TRUE		1U
+#define	MD_FALSE	0U
+
+#define MD_SET		1U
+#define MD_CLEAR	0U
+
+/* Status list definition */
+#define	MD_STATUSBASE		0x00U
+#define	MD_OK			(MD_STATUSBASE + 0x00U)	/* register setting OK */
+#define	MD_RESET		(MD_STATUSBASE + 0x01U)	/* reset input */
+#define	MD_SENDCOMPLETE		(MD_STATUSBASE + 0x02U)	/* send data complete */
+#define	MD_ADDRESSMATCH		(MD_STATUSBASE + 0x03U)	/* IIC slave address match */
+#define	MD_OVF			(MD_STATUSBASE + 0x04U)	/* timer count overflow */
+#define	MD_SPT			(MD_STATUSBASE + 0x07U)	/* IIC stop */
+#define	MD_NACK			(MD_STATUSBASE + 0x08U)	/* IIC no ACK */
+#define	MD_SLAVE_SEND_END	(MD_STATUSBASE + 0x09U)	/* IIC slave send end */
+#define	MD_SLAVE_RCV_END	(MD_STATUSBASE + 0x0AU)	/* IIC slave receive end */
+#define	MD_MASTER_SEND_END	(MD_STATUSBASE + 0x0BU)	/* IIC master send end */
+#define	MD_MASTER_RCV_END	(MD_STATUSBASE + 0x0CU)	/* IIC master receive end */
+#define	MD_UNDEREXEC		(MD_STATUSBASE + 0x0DU)	/* DMA transfer under execute */
+#define	MD_COMPLETED		(MD_STATUSBASE + 0x0EU)	/* DMA transfer completed */
+#define MD_BUSY1		(MD_STATUSBASE + 0x0FU)	/* busy 1 */
+#define MD_BUSY2		(MD_STATUSBASE + 0x10U)	/* busy 2 */
+
+/* Error list definition */
+#define	MD_ERRORBASE		0x80U
+#define	MD_ERROR		(MD_ERRORBASE + 0x00U)	/* error */
+#define	MD_RESOURCEERROR	(MD_ERRORBASE + 0x01U)	/* no resource available */
+#define	MD_PARITYERROR		(MD_ERRORBASE + 0x02U)	/* UARTn parity error n=0,1,2 */
+#define	MD_OVERRUNERROR		(MD_ERRORBASE + 0x03U)	/* UARTn overrun error n=0,1,2 */
+#define	MD_FRAMEERROR		(MD_ERRORBASE + 0x04U)	/* UARTn frame error n=0,1,2 */
+#define	MD_ARGERROR		(MD_ERRORBASE + 0x05U)	/* Error agrument input error */
+#define	MD_TIMINGERROR		(MD_ERRORBASE + 0x06U)	/* Error timing operation error */
+#define	MD_SETPROHIBITED	(MD_ERRORBASE + 0x07U)	/* setting prohibited */
+#define	MD_ODDBUF		(MD_ERRORBASE + 0x08U)	/* in 16bit transfer mode,buffer size should be even */
+#define	MD_DATAEXISTS		(MD_ERRORBASE + 0x09U)	/* Data to be transferred next exists in TXBn register */
+#define	MD_STSERROR		(MD_ERRORBASE + 0x0AU)	/* CAN status error */
+#define	MD_ALRDYSTART		(MD_ERRORBASE + 0x0BU)	/* CAN-controller is already started error */
+#define	MD_NOMSG		(MD_ERRORBASE + 0x0CU)	/* CAN message not received */
+#define	MD_ERROR1		(MD_ERRORBASE + 0x0DU)	/* error 1 */
+#define	MD_ERROR2		(MD_ERRORBASE + 0x0EU)	/* error 2 */
+/*
+*******************************************************************************
+**  Function define
+*******************************************************************************
+*/
+
+#endif

bsp/upd70f3454/applilet3_src/CG_port.c

@@ -0,0 +1,71 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_port.c
+* Abstract:	This file implements device driver for PORT module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_port.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function initializes setting for Port I/O.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void PORT_Init(void)
+{
+	PDLH = _10_Pn4_OUTPUT_1;
+	PMDLH = _01_PMn0_MODE_UNUSED | _02_PMn1_MODE_UNUSED | _04_PMn2_MODE_UNUSED | _08_PMn3_MODE_UNUSED | _00_PMn4_MODE_OUTPUT | _20_PMn5_MODE_UNUSED | _40_PMn6_MODE_UNUSED | _80_PMn7_MODE_UNUSED;
+	PMCDLH = _00_PMCn4_OPER_PORT;
+}
+
+void led_on(void)
+{
+    PDLH = _10_Pn4_OUTPUT_1;
+}
+
+void led_off(void)
+{
+    PDLH = _00_Pn4_OUTPUT_0;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_port.h

@@ -0,0 +1,130 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_port.h
+* Abstract:	This file implements device driver for PORT module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+#ifndef _MDPORT_
+#define _MDPORT_
+/*
+*******************************************************************************
+**  Register bit define
+*******************************************************************************
+*/
+/* Port mode control register (PMCn.7 - PMCn.0) */
+#define	_00_PMCn0_OPER_PORT		0x00U	/* Pn0 as port mode */
+#define	_00_PMCn1_OPER_PORT		0x00U	/* Pn1 as port mode */
+#define	_00_PMCn2_OPER_PORT		0x00U	/* Pn2 as port mode */
+#define	_00_PMCn3_OPER_PORT		0x00U	/* Pn3 as port mode */
+#define	_00_PMCn4_OPER_PORT		0x00U	/* Pn4 as port mode */
+#define	_00_PMCn5_OPER_PORT		0x00U	/* Pn5 as port mode */
+#define	_00_PMCn6_OPER_PORT		0x00U	/* Pn6 as port mode */
+#define	_00_PMCn7_OPER_PORT		0x00U	/* Pn7 as port mode */
+#define	_01_PMCn0_OPER_ALTER		0x01U	/* Pn0 as alternative mode */
+#define	_02_PMCn1_OPER_ALTER		0x02U	/* Pn1 as alternative mode */
+#define	_04_PMCn2_OPER_ALTER		0x04U	/* Pn2 as alternative mode */
+#define	_08_PMCn3_OPER_ALTER		0x08U	/* Pn3 as alternative mode */
+#define	_10_PMCn4_OPER_ALTER		0x10U	/* Pn4 as alternative mode */
+#define	_20_PMCn5_OPER_ALTER		0x20U	/* Pn5 as alternative mode */
+#define	_40_PMCn6_OPER_ALTER		0x40U	/* Pn6 as alternative mode */
+#define	_80_PMCn7_OPER_ALTER		0x80U	/* Pn7 as alternative mode */
+#define	_00_PMCn0_OPER_OCD		0x00U	/* PMC0 for MINI2 */
+
+/* Port mode register (PMn.7 - PMn.0) */
+#define	_01_PMn0_MODE_INPUT		0x01U	/* Pn0 as input mode */
+#define	_02_PMn1_MODE_INPUT		0x02U	/* Pn1 as input mode */
+#define	_04_PMn2_MODE_INPUT		0x04U	/* Pn2 as input mode */
+#define	_08_PMn3_MODE_INPUT		0x08U	/* Pn3 as input mode */
+#define	_10_PMn4_MODE_INPUT		0x10U	/* Pn4 as input mode */
+#define	_20_PMn5_MODE_INPUT		0x20U	/* Pn5 as input mode */
+#define	_40_PMn6_MODE_INPUT		0x40U	/* Pn6 as input mode */
+#define	_80_PMn7_MODE_INPUT		0x80U	/* Pn7 as input mode */
+#define	_00_PMn0_MODE_OUTPUT		0x00U	/* Pn0 as output mode */
+#define	_00_PMn1_MODE_OUTPUT		0x00U	/* Pn1 as output mode */
+#define	_00_PMn2_MODE_OUTPUT		0x00U	/* Pn2 as output mode */
+#define	_00_PMn3_MODE_OUTPUT		0x00U	/* Pn3 as output mode */
+#define	_00_PMn4_MODE_OUTPUT		0x00U	/* Pn4 as output mode */
+#define	_00_PMn5_MODE_OUTPUT		0x00U	/* Pn5 as output mode */
+#define	_00_PMn6_MODE_OUTPUT		0x00U	/* Pn6 as output mode */
+#define	_00_PMn7_MODE_OUTPUT		0x00U	/* Pn7 as output mode */
+#define	_01_PMn0_MODE_UNUSED		0x01U	/* Pn0 as default mode */
+#define	_02_PMn1_MODE_UNUSED		0x02U	/* Pn1 as default mode */
+#define	_04_PMn2_MODE_UNUSED		0x04U	/* Pn2 as default mode */
+#define	_08_PMn3_MODE_UNUSED		0x08U	/* Pn3 as default mode */
+#define	_10_PMn4_MODE_UNUSED		0x10U	/* Pn4 as default mode */
+#define	_20_PMn5_MODE_UNUSED		0x20U	/* Pn5 as default mode */
+#define	_40_PMn6_MODE_UNUSED		0x40U	/* Pn6 as default mode */
+#define	_80_PMn7_MODE_UNUSED		0x80U	/* Pn7 as default mode */
+#define	_00_PMn0_MODE_OCD		0x00U	/* PMC0 for MINI2 */
+
+/* Port register (Pn.7 - Pn.0) */
+#define	_00_Pn0_OUTPUT_0		0x00U	/* Pn0 output 0 */
+#define	_00_Pn1_OUTPUT_0		0x00U	/* Pn1 output 0 */
+#define	_00_Pn2_OUTPUT_0		0x00U	/* Pn2 output 0 */
+#define	_00_Pn3_OUTPUT_0		0x00U	/* Pn3 output 0 */
+#define	_00_Pn4_OUTPUT_0		0x00U	/* Pn4 output 0 */
+#define	_00_Pn5_OUTPUT_0		0x00U	/* Pn5 output 0 */
+#define	_00_Pn6_OUTPUT_0		0x00U	/* Pn6 output 0 */
+#define	_00_Pn7_OUTPUT_0		0x00U	/* Pn7 output 0 */
+#define	_01_Pn0_OUTPUT_1		0x01U	/* Pn0 output 1 */
+#define	_02_Pn1_OUTPUT_1		0x02U	/* Pn1 output 1 */
+#define	_04_Pn2_OUTPUT_1		0x04U	/* Pn2 output 1 */
+#define	_08_Pn3_OUTPUT_1		0x08U	/* Pn3 output 1 */
+#define	_10_Pn4_OUTPUT_1		0x10U	/* Pn4 output 1 */
+#define	_20_Pn5_OUTPUT_1		0x20U	/* Pn5 output 1 */
+#define	_40_Pn6_OUTPUT_1		0x40U	/* Pn6 output 1 */
+#define	_80_Pn7_OUTPUT_1		0x80U	/* Pn7 output 1 */
+
+/* Function register resistor (PFn.7 - PFn.0) */
+#define	_00_PFn0_FUN_NORMAL		0x00U	/* Pn0 normal output */
+#define	_00_PFn1_FUN_NORMAL		0x00U	/* Pn1 normal output */
+#define	_00_PFn2_FUN_NORMAL		0x00U	/* Pn2 normal output */
+#define	_00_PFn3_FUN_NORMAL		0x00U	/* Pn3 normal output */
+#define	_00_PFn4_FUN_NORMAL		0x00U	/* Pn4 normal output */
+#define	_00_PFn5_FUN_NORMAL		0x00U	/* Pn5 normal output */
+#define	_00_PFn6_FUN_NORMAL		0x00U	/* Pn6 normal output */
+#define	_00_PFn7_FUN_NORMAL		0x00U	/* Pn7 normal output */
+#define	_01_PFn0_FUN_OPEN		0x01U	/* Pn0 open-drain output */
+#define	_02_PFn1_FUN_OPEN		0x02U	/* Pn1 open-drain output */
+#define	_04_PFn2_FUN_OPEN		0x04U	/* Pn2 open-drain output */
+#define	_08_PFn3_FUN_OPEN		0x08U	/* Pn3 open-drain output */
+#define	_10_PFn4_FUN_OPEN		0x10U	/* Pn4 open-drain output */
+#define	_20_PFn5_FUN_OPEN		0x20U	/* Pn5 open-drain output */
+#define	_40_PFn6_FUN_OPEN		0x40U	/* Pn6 open-drain output */
+#define	_80_PFn7_FUN_OPEN		0x80U	/* Pn7 open-drain output */
+/*
+*******************************************************************************
+**  Macro define
+*******************************************************************************
+*/
+#define	_80_PM0_DEFAULT			0x80U	/* PM0 default value */
+#define	_FC_PM1_DEFAULT			0xFCU	/* PM1 default value */
+#define	_FC_PM3H_DEFAULT		0xFCU	/* PM3H default value */
+#define	_F8_PM4_DEFAULT			0xF8U	/* PM4 default value */
+#define	_C0_PM5_DEFAULT			0xC0U	/* PM5 default value */
+#define	_FC_PM8_DEFAULT			0xFCU	/* PM8 default value */
+#define	_F0_PMCD_DEFAULT		0xF0U	/* PMCD default value */
+/*
+*******************************************************************************
+**  Function define
+*******************************************************************************
+*/
+void PORT_Init(void);
+void led_on(void);
+void led_off(void);
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

bsp/upd70f3454/applilet3_src/CG_port_user.c

@@ -0,0 +1,41 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_port_user.c
+* Abstract:	This file implements device driver for PORT module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_port.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_system.c

@@ -0,0 +1,113 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_system.c
+* Abstract:	This file implements device driver for System module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_system.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+void clock_pll_mode(void)
+{
+	/* CPU operation clock selection */
+	/* Set PLL mode. */
+	PLLCTL = 0x03;						/* bit 1: CPU clock selection (PLL mode/clock-through mode selection) */
+										/* 1: PLL mode, 0: Clock-through mode */
+	
+	__asm("_loop:	set1	1,0xF82C[r0]");  //__IO_REG8_BIT(  PLLCTL, 0xFFFFF82C,  __READ_WRITE )
+	__asm("			tst1	1,0xF82C[r0]");  //__IO_REG8_BIT(  PLLCTL, 0xFFFFF82C,  __READ_WRITE )
+	__asm("			bz		_loop");
+	
+	return;
+}
+
+void clock_pcc_mode(void)
+{
+	/* DMA is forcibly terminated in this sample since DMA transfer must be terminated 
+	before data is set to a special register. */
+	
+	if(TC0 == 0 && E00 == 1){			/* DMA0 transfer judgment */
+		INIT0 = 1;						/* DMA0 forcible termination */
+	}
+	if(TC1 == 0 && E11 == 1){			/* DMA1 transfer judgment */
+		INIT1 = 1;						/* DMA1 forcible termination */
+	}
+	if(TC2 == 0 && E22 == 1){			/* DMA2 transfer judgment */
+		INIT2 = 1;						/* DMA2 forcible termination */
+	}
+	if(TC3 == 0 && E33 == 1){			/* DMA3 transfer judgment */
+		INIT3 = 1;						/* DMA3 forcible termination */
+	}
+	
+	/* The PCC register is a special register. Data can be written to this register only in a combination of specific sequences. */
+	/* bit 1, bit 0: Clock selection, 11: fxx/8, 10: fxx/4, 01: fxx/2, 00: fxx */
+	/* Clock selection: fxx */
+	__asm("mov 0x00, r10");				/* Set general-purpose register data to be set to special register. */
+	__asm("st.b r10, 0xF1FC[r0]");		/* Write to PRCMD register. */ //__IO_REG8(PRCMD, 0xFFFFF1FC, __WRITE)
+	__asm("st.b r10, 0xF828[r0]");		/* Set PCC register. */  //__IO_REG8_BIT(PCC, 0xFFFFF828, __READ_WRITE)
+	__asm("nop");						/* Insert five or more NOP instructions. */
+	__asm("nop");
+	__asm("nop");
+	__asm("nop");
+	__asm("nop");
+	
+	return;
+}
+
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function initializes the clock generator module.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void CLOCK_Init(void)
+{
+	DI();       						/* Maskable interrupt disabled */
+	
+	do{
+		clock_pll_mode();				/* PLL mode setting function */
+		
+		clock_pcc_mode();				/* PCC register setting function */
+		
+	}while(PRERR);						/* Written in correct sequence? */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_system.h

@@ -0,0 +1,172 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_system.h
+* Abstract:	This file implements device driver for System module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+#ifndef _MDSYSTEM_
+#define _MDSYSTEM_
+/*
+*******************************************************************************
+**  Register bit define
+*******************************************************************************
+*/
+/*
+	Processor clock control register (PCC)
+*/
+#define	_03_CG_PCC_INITIALVALUE		0x03U
+/* Use of subclock on-chip feedback resistor (FRC) */
+#define	_00_CG_SUBCLK_FEEDBACK_USE	0x00U	/* subclock on-chip feedback resistor connected */
+#define	_08_CG_SUBCLK_FEEDBACK_UNUSE	0x80U	/* subclock on-chip feedback resistor not connected */
+/* Main clock osillator control (MCK) */
+#define	_00_CG_MAINCLK_ENABLE		0x00U	/* main clock oscillation enabled */
+#define	_04_CG_MAINCLK_STOP		0x40U	/* main clock oscillation stopped */
+/* Use of main clock on-chip feedback resistor (MFRC) */
+#define	_00_CG_MAINCLK_FEEDBACK_USE	0x00U	/* main clock feedback resistor connected */
+#define	_20_CG_MAINCLK_FEEDBACK_UNUSE	0x20U	/* main clock feedback resistor not connected */
+/* Status of CPU clock fCPU (CLS) */
+#define	_00_CG_CPUCLK_MAINCLK		0x00U	/* main clock operation */
+#define	_10_CG_CPUCLK_SUBCLK		0x10U	/* subclock operation */
+/* Clock(fCLK/fCPU) selection (CK3 - CK0) */
+#define	_0F_CG_CPUCLK			0x0FU
+#define	_00_CG_CPUCLK_MAIN0		0x00U	/* fCPU = fXX */
+#define	_01_CG_CPUCLK_MAIN1		0x01U	/* fCPU = fXX/2 */
+#define	_02_CG_CPUCLK_MAIN2		0x02U	/* fCPU = fXX/2^2 */
+#define	_03_CG_CPUCLK_MAIN3		0x03U	/* fCPU = fXX/2^3 */
+#define	_04_CG_CPUCLK_MAIN4		0x04U	/* fCPU = fXX/2^4 */
+#define	_05_CG_CPUCLK_MAIN5		0x05U	/* fCPU = fXX/2^5 */
+#define	_0B_CG_CPUCLK_SUB		0x0BU	/* fXT */
+
+/*
+	Internal oscillator mode register (RCM)
+*/
+/* Oscillation/stop of internal oscillator (RSTOP) */
+#define	_00_CG_INTER_OSC_ON		0x00U	/* internal oscillator oscillation */
+#define	_01_CG_INTER_OSC_OFF		0x01U	/* internal oscillator stopped */
+
+/*
+	CPU operation clock status register (CCLS)
+*/
+/* CPU operation clock status (CCLSF) */
+#define	_00_CG_CPUCLK_STATUS_MAINORSUB	0x00U	/* operating on main clock(fX) or subclock(fXT) */
+#define	_01_CG_CPUCLK_STATUS_INTEROSC	0x01U	/* operating on internal oscillation clock(fR) */
+
+/*
+	Lock register (LOCKR)
+*/
+/* PLL lock status check (LOCK) */
+#define	_00_CG_PLLSTATUS_LOCK		0x00U	/* locked status */
+#define	_01_CG_PLLSTATUS_UNLOCK		0x01U	/* unlocked status */
+
+/*
+	PLL control register (PLLCTL)
+*/
+#define	_01_CG_PLLCTL_INITIALVALUE	0x01U
+/* CPU operation clock selection register (SELPLL) */
+#define	_00_CG_CPUCLK_CLKTHROUGH	0x00U	/* clock-through mode */
+#define	_02_CG_CPUCLK_PLL		0x02U	/* PLL mode */
+/* PLL operation stop register (PLLON) */
+#define	_00_CG_CPUCLK_PLLOFF		0x00U	/* PLL stopped */
+#define	_01_CG_CPUCLK_PLLON		0x01U	/* PLL operating */
+
+/*
+	Clock control register (CKC)
+*/
+#define	_0A_CG_CKC_INITIALVALUE		0x0AU
+/* Internal system clock(fXX) in PLL mode */
+#define	_00_CG_CPUCLK_4PLL		0x00U	/* fXX = 4* fX (fX = 2.5 to 5.0 MHz) */
+#define	_01_CG_CPUCLK_8PLL		0x01U	/* fXX = 8* fX (fX = 2.5 to 4.0 MHz) */
+
+/*
+	PLL lockup time specification register (PLLS)
+*/
+#define	_03_CG_PLLS_INITIALVALUE	0x03U
+/* PLL lockup time selection (PLLS2 - PLLS0) */
+#define	_00_CG_PLLLOCKUP_SEL0		0x00U	/* 2^10/fX */
+#define	_01_CG_PLLLOCKUP_SEL1		0x01U	/* 2^11/fX*/
+#define	_02_CG_PLLLOCKUP_SEL2		0x02U	/* 2^12/fX */
+#define	_03_CG_PLLLOCKUP_SEL3		0x03U	/* 2^13/fX (default value) */
+
+/*
+	Power save control register (PSC)
+*/
+/* Stand-by mode release control by occurrence of INTWDT2 signal (NMI1M) */
+#define	_00_CG_STANDBY_INTWDT2EN	0x00U	/* enable releasing stand-by mode by INTWDT2 signal */
+#define	_40_CG_STANDBY_INTWDT2DIS	0x40U	/* disable releasing stand-by mode by INTWDT2 signal */
+/* Stand-by mode release control by NMI pin input (NMI0M) */
+#define	_00_CG_STANDBY_NMIEN		0x00U	/* enable releasing stand-by mode by NMI pin input */
+#define	_20_CG_STANDBY_NMIDIS		0x20U	/* disable releasing stand-by mode by NMI pin input */
+/* Stand-by mode release control by maskable interrupt request signal (NMI0M) */
+#define	_00_CG_STANDBY_MASKIEN		0x00U	/* enable releasing stand-by mode by maskable interrupt request signal */
+#define	_10_CG_STANDBY_MASKIDIS		0x10U	/* disable releasing stand-by mode by maskable interrupt request signal */
+/* Setting of stand-by mode (STP) */
+#define	_00_CG_STANDBY_UNUSE		0x00U	/* normal mode */
+#define	_02_CG_STANDBY_USE		0x02U	/* stand-by mode */
+
+/*
+	Power save mode control register (PSMR)
+*/
+/* Specification of operation in software stand-by mode (PSM1,PSM0) */
+#define	_00_CG_POWERSAVE_IDLE1		0x00U	/* IDLE1, sub-IDLE modes */
+#define	_01_CG_POWERSAVE_STOP1		0x01U	/* STOP, sub-IDLE modes */
+#define	_02_CG_POWERSAVE_IDLE2		0x02U	/* IDLE2, sub-IDLE modes */
+#define	_03_CG_POWERSAVE_STOP2		0x03U	/* STOP mode */
+
+/*
+	Clock monitor mode register (CLM)
+*/
+/* Clock monitor operation enable or disable (CLME) */
+#define	_01_CG_MONITOR_ENABLE		0x01U	/* enable clock monitor operation */
+#define	_00_CG_MONITOR_DISABLE		0x00U	/* disable clock monitor operation */
+
+/*
+	Watchdog Timer 2 mode register (WDTM2)
+*/
+/* Selection of operation mode (WDM21, WDM20) */
+#define	_00_WDT2_OPERMODE_STOP		0x00U	/* stops operation */
+#define	_20_WDT2_OPERMODE_NONMASK	0x20U	/* non-maskable interrupt request mode (generation of INTWDT2) */
+#define	_40_WDT2_OPERMODE_RESET		0x40U	/* reset mode (generation of RESWDT2) */
+/* Selection of clock mode (WDCS24,WDCS23) */
+#define	_00_WDT2_CLKMODE_INTEROSC	0x00U	/* use internal oscillator */
+#define	_08_WDT2_CLKMODE_MAINCLK	0x08U	/* use Main clock */
+#define	_10_WDT2_CLKMODE_SUBCLK		0x10U	/* use subclock */
+/* Watchdog Timer 2 clock Selection (WDCS22 - WDCS20) */
+#define	_00_WDT2_CLOCK_SEL0		0x00U	/* 2^12/fR or 2^18/fXX or 2^9/fXT */
+#define	_01_WDT2_CLOCK_SEL1		0x01U	/* 2^13/fR or 2^19/fXX or 2^10/fXT */
+#define	_02_WDT2_CLOCK_SEL2		0x02U	/* 2^14/fR or 2^20/fXX or 2^11/fXT */
+#define	_03_WDT2_CLOCK_SEL3		0x03U	/* 2^15/fR or 2^21/fXX or 2^12/fXT */
+#define	_04_WDT2_CLOCK_SEL4		0x04U	/* 2^16/fR or 2^22/fXX or 2^13/fXT */
+#define	_05_WDT2_CLOCK_SEL5		0x05U	/* 2^17/fR or 2^23/fXX or 2^14/fXT */
+#define	_06_WDT2_CLOCK_SEL6		0x06U	/* 2^18/fR or 2^24/fXX or 2^15/fXT */
+#define	_07_WDT2_CLOCK_SEL7		0x07U	/* 2^19/fR or 2^25/fXX or 2^16/fXT */
+/*
+*******************************************************************************
+**  Macro define
+*******************************************************************************
+*/
+#define	_00_CG_VSWC_VALUE		0x00U
+/*
+*******************************************************************************
+**  Function define
+*******************************************************************************
+*/
+void CLOCK_Init(void);
+void WDT2_Restart(void);
+void CG_ReadResetSource(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

bsp/upd70f3454/applilet3_src/CG_system_user.c

@@ -0,0 +1,62 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_system_user.c
+* Abstract:	This file implements device driver for System module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_system.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function processes of Reset.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void CG_ReadResetSource( void )
+{
+	UCHAR resetflag = RESF;
+
+	/* Start user code. Do not edit comment generated here */
+	/* End user code. Do not edit comment generated here */
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_systeminit.c

@@ -0,0 +1,89 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_systeminit.c
+* Abstract:	This file implements system initializing function.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_system.h"
+#include "CG_port.h"
+#include "CG_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+UCHAR __low_level_init(void);
+void systeminit(void);
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function initializes each macro.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void systeminit(void)
+{
+	DI();	/* disable interrupt */
+	CG_ReadResetSource();
+	PORT_Init();
+	TAB0_Init();
+	EI();	/* enable interrupt */
+}
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function initializes hardware setting.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+UCHAR __low_level_init(void)
+{
+	VSWC = 0x13U;
+	CLOCK_Init();	/* call Clock_Init function */
+	systeminit();
+	
+	return MD_TRUE;
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_timer.c

@@ -0,0 +1,200 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_timer.c
+* Abstract:	This file implements device driver for Timer module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Count Clock (TABnCTL0) */
+#define	TAB_CNT_CLK				0x00	/* Count Clock fxx */
+#define	TAB_CNT_CLK_2			0x01	/* Count Clock fxx/2 */
+#define	TAB_CNT_CLK_4			0x02	/* Count Clock fxx/4 */
+#define	TAB_CNT_CLK_8			0x03	/* Count Clock fxx/8 */
+#define	TAB_CNT_CLK_16			0x04	/* Count Clock fxx/16 */
+#define	TAB_CNT_CLK_32			0x05	/* Count Clock fxx/32 */
+#define	TAB_CNT_CLK_64			0x06	/* Count Clock fxx/64 */
+#define	TAB_CNT_CLK_128			0x07	/* Count Clock fxx/128 */
+/* Mode (TABkMD2 + TABkMD1 + TABkMD0) */
+#define	TAB_INTERVAL_MODE		0x00	/* Interval Timer Mode */
+/* TAB0I/O Control Register (TABmIOC0) */
+#define	TAB_TOB00_DISABLE		0x00	/* TOB00 Output Disable */
+#define	TAB_TOB00_ENABLE		0x01	/* TOB00 Output Enable */
+#define	TAB_TOB00_HI_LEV_ST		0x00	/* TOB00 Output High Level Start */
+#define	TAB_TOB00_LO_LEV_ST		0x02	/* TOB00 Output Low Level Start */
+#define	TAB_TOB01_DISABLE		0x00	/* TOB01 Output Disable */
+#define	TAB_TOB01_ENABLE		0x04	/* TOB01 Output Enable */
+#define	TAB_TOB01_HI_LEV_ST		0x00	/* TOB01 Output High Level Start */
+#define	TAB_TOB01_LO_LEV_ST		0x08	/* TOB01 Output Low Level Start */
+#define	TAB_TOB02_DISABLE		0x00	/* TOB02 Output Disable */
+#define	TAB_TOB02_ENABLE		0x10	/* TOB02 Output Enable */
+#define	TAB_TOB02_HI_LEV_ST		0x00	/* TOB02 Output High Level Start */
+#define	TAB_TOB02_LO_LEV_ST		0x20	/* TOB02 Output Low Level Start */
+#define	TAB_TOB03_DISABLE		0x00	/* TOB03 Output Disable */
+#define	TAB_TOB03_ENABLE		0x40	/* TOB03 Output Enable */
+#define	TAB_TOB03_HI_LEV_ST		0x00	/* TOB03 Output High Level Start */
+#define	TAB_TOB03_LO_LEV_ST		0x80	/* TOB03 Output Low Level Start */
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+void timerab_interval(void)
+{
+	TAB0CTL0 = TAB_CNT_CLK_32;			/* TAB0CKS2 = 1 + TAB0CKS1 = 0 + TAB0CKS0 = 0 */
+										/*  : Clock Count = fxx/32 */
+	TAB0CTL1 = TAB_INTERVAL_MODE;		/* TAB0MD2 = 0 + TAB0MD1 = 0 + TAB0MD0 = 0 */
+										/*  : Interval Timer Mode */
+//	TAB0IOC2 = TAB_TOB03_LO_LEV_ST |	/* TAB0OL3 = 1 : TOB03 Low Level Start */
+//			   TAB_TOB03_DISABLE   |	/* TAB0OE3 = 0 : TOB03 Output Disable */
+//			   TAB_TOB02_LO_LEV_ST |	/* TAB0OL2 = 1 : TOB02 Low Level Start */
+//			   TAB_TOB02_DISABLE   |	/* TAB0OE2 = 0 : TOB02 Output Disable */
+//			   TAB_TOB01_HI_LEV_ST |	/* TAB0OL1 = 0 : TOB01 High Level Start */
+//			   TAB_TOB01_ENABLE    |	/* TAB0OE1 = 1 : TOB01 Output Enable */
+//			   TAB_TOB00_HI_LEV_ST |	/* TAB0OL0 = 0 : TOB00 High Level Start */
+//			   TAB_TOB00_ENABLE;		/* TAB0OE0 = 1 : TOB00 Output Enable */
+	TAB0CCR0	= 19999;				/* Compare Register */
+	TAB0CCR1 = 0xFFFF;					/* Compare Register */
+	TAB0CCR2 = 0xFFFF;					/* No Use */
+	TAB0CCR3 = 0xFFFF;					/* No Use */
+}
+
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function initializes the TAB0 module.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void TAB0_Init(void)
+{
+	TAB0CE = 0;							/* Stop TAB */
+
+	/* Port Definition */
+//	PFC1 = 0x00;						/* PFC17 = 0 : TOB00 Output */
+										/* PFC10 = 0 : TOB01 Output */
+//	PFCE1 = 0x01;						/* PFCE10 = 1 : TOB01 Output */
+//	PMC1 = 0x81;						/* PMC17 = 1 : TOB00 Output/INTP09 Input */
+										/* PMC10 = 1 : TOB0T1 Output/TIB01 Input/TOB01 Output */
+
+	/* Enable Interrupt */
+	TB0CCMK0 = 0;						/* TB0CCMK0 = 0 : INTTB0CC0 Enable */
+	TB0CCMK1 = 1;						/* TB0CCMK1 = 0 : INTTB0CC1 Enable */
+	TB0CCMK2 = 1;						/* TB0CCMK2 = 1 : INTTB0CC2 Disable */
+	TB0CCMK3 = 1;						/* TB0CCMK3 = 1 : INTTB0CC3 Disable */
+
+	timerab_interval();
+}
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function starts TMP0 counter.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void TAB0_Start(void)
+{
+	TB0CCIF0 = 0U;	/* clear INTTP0CC0 interrupt flag */
+	TB0CCMK0 = 0U;	/* enable INTTP0CC0 interrupt */
+	TAB0CE = 1U;	/* enable TMP0 operation */
+}
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function stops TMP0 counter.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+void TAB0_Stop(void)
+{
+	TAB0CE = 0U;	/* disable TMP0 operation */
+	TB0CCMK0 = 1U;	/* disable INTTP0CC0 interrupt */
+	TB0CCIF0 = 0U;	/* clear INTTP0CC0 interrupt flag */
+}
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function changes TMP0 register value.
+**
+**  Parameters:
+**	array_reg: register value buffer
+**	array_num: register index to be changed
+**
+**  Returns:
+**	MD_OK
+**	MD_ARGERROR
+**
+**-----------------------------------------------------------------------------
+*/
+MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num)
+{
+	MD_STATUS status = MD_OK;
+
+	switch (array_num)
+	{
+		case 1U:
+			TAB0CCR0 = array_reg[0U];
+			status = MD_OK;
+			break;
+		case 2U:
+			TAB0CCR0 = array_reg[0U];
+			TAB0CCR1 = array_reg[1U];
+			status = MD_OK;
+			break;
+		default:
+			status = MD_ARGERROR;
+			break;
+	}
+	
+	return (status);
+}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_timer.h

@@ -0,0 +1,278 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_timer.h
+* Abstract:	This file implements device driver for Timer module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+#ifndef _MDTIMER_
+#define _MDTIMER_
+/*
+*******************************************************************************
+**  Register bit define
+*******************************************************************************
+*/
+/* 
+	TMP control register 0 (TPnCTL0)
+*/
+/* TMP operation control (TPnCE) */
+#define	_00_TMP_OPERATION_DISABLE		0x00U	/* disable internal operating clock operation (asynchronously reset TMPn) */
+#define	_80_TMP_OPERATION_ENABLE		0x80U	/* enable internal operating clock operation */
+/* Internal count clock selection (TPnCKS2 - TPnCKS0) */
+#define	_00_TMP_INTERNAL_CLOCK0			0x00U	/* fXX */
+#define	_01_TMP_INTERNAL_CLOCK1			0x01U	/* fXX/2 */
+#define	_02_TMP_INTERNAL_CLOCK2			0x02U	/* fXX/2^2 */
+#define	_03_TMP_INTERNAL_CLOCK3			0x03U	/* fXX/2^3 */
+#define	_04_TMP_INTERNAL_CLOCK4			0x04U	/* fXX/2^4 */
+#define	_05_TMP_INTERNAL_CLOCK5			0x05U	/* fXX/2^5 */
+#define	_06_TMP_INTERNAL_CLOCK6			0x06U	/* fXX/2^6 or fXX/2^8 */
+#define	_07_TMP_INTERNAL_CLOCK7			0x07U	/* fXX/2^7 or fXX/2^9 */
+
+/* 
+	TMP control register 1 (TPnCTL1)
+*/
+/* Software trigger control (TPnEST) */
+#define	_00_TMP_SOFTTRIGGER_OFF			0x00U	/* no operation */
+#define	_40_TMP_SOFTTRIGGER_ON			0x40U	/* in one-shot pulse mode: One-shot pulse software trigger */
+											/* in external trigger pulse output mode: Pulse output software trigger */
+/* Count clock selection (TPnEEE) */
+#define	_00_TMP_INTERNAL_CLOCK			0x00U	/* use the internal clock (clock selected with bits TPnCKS2 to TPnCKS0) */
+#define	_20_TMP_EXTERNAL_CLOCK			0x20U	/* use the external clock from the TIPn0 input pin */ 
+/* Timer mode selection (TPnMD2 - TPnMD0) */
+#define	_00_TMP_MODE_INTERVAL			0x00U	/* interval timer mode */
+#define	_01_TMP_MODE_EXTERNALCOUNT		0x01U	/* external event counter mode */
+#define	_02_TMP_MODE_EXTERNALTRG		0x02U	/* external trigger pulse output mode */
+#define	_03_TMP_MODE_ONESHOT			0x03U	/* one-shot pulse mode */
+#define	_04_TMP_MODE_PWM			0x04U	/* PWM mode */
+#define	_05_TMP_MODE_FREERUNNING		0x05U	/* free-running mode */
+#define	_06_TMP_MODE_PULSEMEASURE		0x06U	/* pulse width measurement mode */
+
+/* 
+	TMP I/O control register 0 (TPnIOC0)
+*/
+/* TOPn0 pin output level setting (TPnOL0) */
+#define	_00_TMP_OUTPUT0_NORMAL			0x00U	/* normal output */
+#define	_02_TMP_OUTPUT0_INVERTED		0x02U	/* inverted output */
+/* TOPn0 pin output setting (TPnOE0) */
+#define	_00_TMP_OUTPUT0_DISABLE			0x00U	/* disable timer output */
+#define	_01_TMP_OUTPUT0_ENABLE			0x01U	/* enable timer output (TOPn0 pin outputs pulses) */
+/* TOPn1 pin output level setting (TPnOL1) */
+#define	_00_TMP_OUTPUT1_NORMAL			0x00U	/* normal output */
+#define	_08_TMP_OUTPUT1_INVERTED		0x08U	/* inverted output */
+/* TOPn1 pin output setting (TPnOE1) */
+#define	_00_TMP_OUTPUT1_DISABLE			0x00U	/* disable timer output */
+#define	_04_TMP_OUTPUT1_ENABLE			0x04U	/* enable timer output (TOPn1 pin outputs pulses) */
+
+/* 
+	TMP I/O control register 1 (TPnIOC1)
+*/
+/* Capture trigger input signal (TIPn1 pin) valid edge setting (TPnIS3,TPnIS2) */
+#define	_00_TMP_INPUT1_EDGE_NONE		0x00U	/* detect no edge (capture operation is invalid) */
+#define	_04_TMP_INPUT1_EDGE_RISING		0x04U	/* detection of rising edge */
+#define	_08_TMP_INPUT1_EDGE_FALLING		0x08U	/* detection of falling edge */
+#define	_0C_TMP_INPUT1_EDGE_BOTH		0x0CU	/* detection of both edges */
+/* Capture trigger input signal (TIPn0 pin) valid edge setting (TPnIS1,TPnIS0) */
+#define	_00_TMP_INPUT0_EDGE_NONE		0x00U	/* detect no edge (capture operation is invalid) */
+#define	_01_TMP_INPUT0_EDGE_RISING		0x01U	/* detection of rising edge */
+#define	_02_TMP_INPUT0_EDGE_FALLING		0x02U	/* detection of falling edge */
+#define	_03_TMP_INPUT0_EDGE_BOTH		0x03U	/* detection of both edges */
+
+/* 
+	TMP I/O control register 2 (TPnIOC2)
+*/
+/* External event count input signal (TIPn0 pin) valid edge setting (TPnEES1,TPnEES0) */
+#define	_00_TMP_EXTCOUNT_EDGE_NONE		0x00U	/* detect no edge (external event count is invalid) */
+#define	_04_TMP_EXTCOUNT_EDGE_RISING		0x04U	/* detection of rising edge */
+#define	_08_TMP_EXTCOUNT_EDGE_FALLING		0x08U	/* detection of falling edge */
+#define	_0C_TMP_EXTCOUNT_EDGE_BOTH		0x0CU	/* detection of both edges */
+/* External trigger input signal (TIPn0 pin) valid edge setting (TPnETS1,TPnETS0) */
+#define	_00_TMP_EXTTRIGGER_EDGE_NONE		0x00U	/* detect no edge (external trigger is invalid) */
+#define	_01_TMP_EXTTRIGGER_EDGE_RISING		0x01U	/* detection of rising edge */
+#define	_02_TMP_EXTTRIGGER_EDGE_FALLING		0x02U	/* detection of falling edge */
+#define	_03_TMP_EXTTRIGGER_EDGE_BOTH		0x03U	/* detection of both edges */
+
+/* 
+	TMP option register 0 (TPnOPT0)
+*/
+/* TPnCCR1 register capture/compare selection (TPnCCS1) */
+#define	_00_TMP_CCR1_COMPARE			0x00U	/* compare register */
+#define	_20_TMP_CCR1_CAPTURE			0x20U	/* capture register */
+/* TPnCCR0 register capture/compare selection (TPnCCS0) */
+#define	_00_TMP_CCR0_COMPARE			0x00U	/* compare register */
+#define	_10_TMP_CCR0_CAPTURE			0x10U	/* capture register */
+/* TMPn overflow detection flag (TPnOVF) */
+#define _01_TMP_OVERFLOW_OCCUR			0x01U	/* overflow occurred */
+#define _00_TMP_OVERFLOW_CLEAR			0x00U	/* clear overflow */
+
+/* 
+	TMQ0 control register 0 (TQ0CTL0)
+*/
+/* TMQ operation control (TQ0CE) */
+#define	_00_TMQ_OPERATION_DISABLE		0x00U	/* disable internal operating clock operation (asynchronously reset TMQ0) */
+#define	_80_TMQ_OPERATION_ENABLE		0x80U	/* enable internal operating clock operation */
+/* Internal count clock selection (TQ0CKS2 - TQ0CKS0) */
+#define	_00_TMQ_INTERNAL_CLOCK0			0x00U	/* fXX */
+#define	_01_TMQ_INTERNAL_CLOCK1			0x01U	/* fXX/2 */
+#define	_02_TMQ_INTERNAL_CLOCK2			0x02U	/* fXX/2^2 */
+#define	_03_TMQ_INTERNAL_CLOCK3			0x03U	/* fXX/2^3 */
+#define	_04_TMQ_INTERNAL_CLOCK4			0x04U	/* fXX/2^4 */
+#define	_05_TMQ_INTERNAL_CLOCK5			0x05U	/* fXX/2^5 */
+#define	_06_TMQ_INTERNAL_CLOCK6			0x06U	/* fXX/2^6 */
+#define	_07_TMQ_INTERNAL_CLOCK7			0x07U	/* fXX/2^7 */
+
+/* 
+	TMQ0 control register 1 (TQ0CTL1)
+*/
+/* Software trigger control (TQ0EST) */
+#define	_00_TMQ_SOFTTRIGGER_OFF			0x00U	/* no operation */
+#define	_40_TMQ_SOFTTRIGGER_ON			0x40U	/* in one-shot pulse mode: One-shot pulse software trigger */
+											/* in external trigger pulse output mode: Pulse output software trigger */
+/* Count clock selection (TQ0EEE) */
+#define	_00_TMQ_INTERNAL_CLOCK			0x00U	/* use the internal clock (clock selected with bits TQ0CKS2 to TQ0CKS0) */
+#define	_20_TMQ_EXTERNAL_CLOCK			0x20U	/* use the external clock from the TIQ00 input pin */ 
+/* Timer mode selection (TQ0MD2 - TQ0MD0) */
+#define	_00_TMQ_MODE_INTERVAL			0x00U	/* interval timer mode */
+#define	_01_TMQ_MODE_EXTERNALCOUNT		0x01U	/* external event counter mode */
+#define	_02_TMQ_MODE_EXTERNALTRG		0x02U	/* external trigger pulse output mode */
+#define	_03_TMQ_MODE_ONESHOT			0x03U	/* one-shot pulse mode */
+#define	_04_TMQ_MODE_PWM			0x04U	/* PWM mode */
+#define	_05_TMQ_MODE_FREERUNNING		0x05U	/* free-running mode */
+#define	_06_TMQ_MODE_PULSEMEASURE		0x06U	/* pulse width measurement mode */
+
+/* 
+	TMQ0 I/O control register 0 (TQ0IOC0)
+*/
+/* TOQ00 pin output level setting (TQ0OL0) */
+#define	_00_TMQ_OUTPUT0_NORMAL			0x00U	/* normal output */
+#define	_02_TMQ_OUTPUT0_INVERTED		0x02U	/* inverted output */
+/* TOQ00 pin output setting (TQ0OE0) */
+#define	_00_TMQ_OUTPUT0_DISABLE			0x00U	/* disable timer output */
+#define	_01_TMQ_OUTPUT0_ENABLE			0x01U	/* enable timer output (TOQ00 pin outputs pulses) */
+/* TOQ01 pin output level setting (TQ0OL1) */
+#define	_00_TMQ_OUTPUT1_NORMAL			0x00U	/* normal output */
+#define	_08_TMQ_OUTPUT1_INVERTED		0x08U	/* inverted output */
+/* TOQ01 pin output setting (TQ0OE1) */
+#define	_00_TMQ_OUTPUT1_DISABLE			0x00U	/* disable timer output */
+#define	_04_TMQ_OUTPUT1_ENABLE			0x04U	/* enable timer output (TOQ01 pin outputs pulses) */
+/* TOQ02 pin output level setting (TQ0OL2) */
+#define	_00_TMQ_OUTPUT2_NORMAL			0x00U	/* normal output */
+#define	_20_TMQ_OUTPUT2_INVERTED		0x20U	/* inverted output */
+/* TOQ02 pin output setting (TQ0OE2) */
+#define	_00_TMQ_OUTPUT2_DISABLE			0x00U	/* disable timer output */
+#define	_10_TMQ_OUTPUT2_ENABLE			0x10U	/* enable timer output (TOQ02 pin outputs pulses) */
+/* TOQ03 pin output level setting (TQ0OL3) */
+#define	_00_TMQ_OUTPUT3_NORMAL			0x00U	/* normal output */
+#define	_80_TMQ_OUTPUT3_INVERTED		0x80U	/* inverted output */
+/* TOQ03 pin output setting (TQ0OE3) */
+#define	_00_TMQ_OUTPUT3_DISABLE			0x00U	/* disable timer output */
+#define	_40_TMQ_OUTPUT3_ENABLE			0x40U	/* enable timer output (TOQ03 pin outputs pulses) */
+
+/* 
+	TMQ0 I/O control register 1 (TQ0IOC1)
+*/
+/* Capture trigger input signal (TIQ00 pin) valid edge setting (TQ0IS1,TQ0IS0) */
+#define	_00_TMQ_INPUT0_EDGE_NONE		0x00U	/* detect no edge (capture operation is invalid) */
+#define	_01_TMQ_INPUT0_EDGE_RISING		0x01U	/* detection of rising edge */
+#define	_02_TMQ_INPUT0_EDGE_FALLING		0x02U	/* detection of falling edge */
+#define	_03_TMQ_INPUT0_EDGE_BOTH		0x03U	/* detection of both edges */
+/* Capture trigger input signal (TIQ01 pin) valid edge setting (TQ0IS3,TQ0IS2) */
+#define	_00_TMQ_INPUT1_EDGE_NONE		0x00U	/* detect no edge (capture operation is invalid) */
+#define	_04_TMQ_INPUT1_EDGE_RISING		0x04U	/* detection of rising edge */
+#define	_08_TMQ_INPUT1_EDGE_FALLING		0x08U	/* detection of falling edge */
+#define	_0C_TMQ_INPUT1_EDGE_BOTH		0x0CU	/* detection of both edges */
+/* Capture trigger input signal (TIQ02 pin) valid edge setting (TQ0IS5,TQ0IS4) */
+#define	_00_TMQ_INPUT2_EDGE_NONE		0x00U	/* detect no edge (capture operation is invalid) */
+#define	_10_TMQ_INPUT2_EDGE_RISING		0x10U	/* detection of rising edge */
+#define	_20_TMQ_INPUT2_EDGE_FALLING		0x20U	/* detection of falling edge */
+#define	_30_TMQ_INPUT2_EDGE_BOTH		0x30U	/* detection of both edges */
+/* Capture trigger input signal (TIQ03 pin) valid edge setting (TQ0IS7,TQ0IS6) */
+#define	_00_TMQ_INPUT3_EDGE_NONE		0x00U	/* detect no edge (capture operation is invalid) */
+#define	_40_TMQ_INPUT3_EDGE_RISING		0x40U	/* detection of rising edge */
+#define	_80_TMQ_INPUT3_EDGE_FALLING		0x80U	/* detection of falling edge */
+#define	_C0_TMQ_INPUT3_EDGE_BOTH		0xC0U	/* detection of both edges */
+
+/* 
+	TMQ0 I/O control register 2 (TQ0IOC2)
+*/
+/* External event count input signal (TIQ00 pin) valid edge setting (TQ0EES1,TQ0EES0) */
+#define	_00_TMQ_EXTCOUNT_EDGE_NONE		0x00U	/* detect no edge (external event count is invalid) */
+#define	_04_TMQ_EXTCOUNT_EDGE_RISING		0x04U	/* detection of rising edge */
+#define	_08_TMQ_EXTCOUNT_EDGE_FALLING		0x08U	/* detection of falling edge */
+#define	_0C_TMQ_EXTCOUNT_EDGE_BOTH		0x0CU	/* detection of both edges */
+/* External trigger input signal (TIQ00 pin) valid edge setting (TQ0ETS1,TQ0ETS0) */
+#define	_00_TMQ_EXTTRIGGER_EDGE_NONE		0x00U	/* detect no edge (external trigger is invalid) */
+#define	_01_TMQ_EXTTRIGGER_EDGE_RISING		0x01U	/* detection of rising edge */
+#define	_02_TMQ_EXTTRIGGER_EDGE_FALLING		0x02U	/* detection of falling edge */
+#define	_03_TMQ_EXTTRIGGER_EDGE_BOTH		0x03U	/* detection of both edges */
+
+/* 
+	TMQ0 option register 0 (TQ0OPT0)
+*/
+/* TQ0CCR3 register capture/compare selection (TQ0CCS3) */
+#define	_00_TMQ_CCR3_COMPARE			0x00U	/* compare register */
+#define	_80_TMQ_CCR3_CAPTURE			0x80U	/* capture register */
+/* TQ0CCR2 register capture/compare selection (TQ0CCS2) */
+#define	_00_TMQ_CCR2_COMPARE			0x00U	/* compare register */
+#define	_40_TMQ_CCR2_CAPTURE			0x40U	/* capture register */
+/* TQ0CCR1 register capture/compare selection (TQ0CCS1) */
+#define	_00_TMQ_CCR1_COMPARE			0x00U	/* compare register */
+#define	_20_TMQ_CCR1_CAPTURE			0x20U	/* capture register */
+/* TQ0CCR0 register capture/compare selection (TQ0CCS0) */
+#define	_00_TMQ_CCR0_COMPARE			0x00U	/* compare register */
+#define	_10_TMQ_CCR0_CAPTURE			0x10U	/* capture register */
+/* TMQ0 overflow detection flag (TQ0OVF) */
+#define _01_TMQ_OVERFLOW_OCCUR			0x01U	/* overflow occurred */
+#define _00_TMQ_OVERFLOW_CLEAR			0x00U	/* clear overflow */
+
+/* 
+	TMM0 control register 0 (TM0CTL0)
+*/
+/* TMM0 operation control (TM0CE) */
+#define	_00_TMM_OPERATION_DISABLE		0x00U	/* disable internal operating clock operation (asynchronously reset TMM0) */
+#define	_80_TMM_OPERATION_ENABLE		0x80U	/* enable internal operating clock operation */
+/* Internal count clock selection (TM0CKS2 - TM0CKS0) */
+#define	_00_TMM_INTERNAL_CLOCK0			0x00U	/* fXX */
+#define	_01_TMM_INTERNAL_CLOCK1			0x01U	/* fXX/2 */
+#define	_02_TMM_INTERNAL_CLOCK2			0x02U	/* fXX/4 */
+#define	_03_TMM_INTERNAL_CLOCK3			0x03U	/* fXX/64 */
+#define	_04_TMM_INTERNAL_CLOCK4			0x04U	/* fXX/512 */
+#define	_05_TMM_INTERNAL_CLOCK5			0x05U	/* INTWT */
+#define	_06_TMM_INTERNAL_CLOCK6			0x06U	/* fR/8 */
+#define	_07_TMM_INTERNAL_CLOCK7			0x07U	/* fXT */
+/*
+*******************************************************************************
+**  Macro define
+*******************************************************************************
+*/
+/* TMP0 compare register 0 (TP0CCR0)*/
+#define _9C3F_TMP0_CCR0_VALUE			0x9C3FU
+enum TMChannel
+{
+	TMCHANNEL0, TMCHANNEL1, TMCHANNEL2, TMCHANNEL3
+};
+/*
+*******************************************************************************
+**  Function define
+*******************************************************************************
+*/
+void TAB0_Init(void);
+void TAB0_Start(void);
+void TAB0_Stop(void);
+MD_STATUS TAB0_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num);
+__interrupt void MD_INTTP0CC0(void);
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

bsp/upd70f3454/applilet3_src/CG_timer_user.c

@@ -0,0 +1,63 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_timer_user.c
+* Abstract:	This file implements device driver for Timer module.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+/*
+*******************************************************************************
+** Include files
+*******************************************************************************
+*/
+#include "CG_macrodriver.h"
+#include "CG_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+/*
+*******************************************************************************
+**  Global define
+*******************************************************************************
+*/
+/* Start user code for global. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+
+/*
+**-----------------------------------------------------------------------------
+**
+**  Abstract:
+**	This function is INTTP0CC0 interrupt service routine.
+**
+**  Parameters:
+**	None
+**
+**  Returns:
+**	None
+**
+**-----------------------------------------------------------------------------
+*/
+
+///#pragma vector = INTTB0CC0_vector
+///__interrupt void MD_INTTB0CC0(void)
+///{
+	/* Start user code. Do not edit comment generated here */
+///    PDLH = ~PDLH;
+	/* End user code. Do not edit comment generated here */
+///}
+
+/* Start user code for adding. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */

bsp/upd70f3454/applilet3_src/CG_userdefine.h

@@ -0,0 +1,30 @@
+/*
+*******************************************************************************
+* Copyright(C) NEC Electronics Corporation 2010
+* All rights reserved by NEC Electronics Corporation.
+* This program should be used on your own responsibility.
+* NEC Electronics Corporation assumes no responsibility for any losses
+* incurred by customers or third parties arising from the use of this file.
+*
+* This device driver was created by Applilet3 for V850ES/Jx3
+* 32-Bit Single-Chip Microcontrollers
+* Filename:	CG_userdefine.h
+* Abstract:	This file includes user definition.
+* APIlib:	Applilet3 for V850ES/Jx3 V2.01 [20 Apr 2010]
+* Device:	uPD70F3746
+* Compiler:	IAR Systems ICCV850
+* Creation date:	6/26/2010
+*******************************************************************************
+*/
+
+#ifndef _MD_USER_DEF_
+#define _MD_USER_DEF_
+/*
+*******************************************************************************
+**  User define
+*******************************************************************************
+*/
+
+/* Start user code for function. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#endif

bsp/upd70f3454/board.c

@@ -0,0 +1,33 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-06-29     lgnq         the first version
+ *
+ * For       : NEC V850E
+ * Toolchain : IAR Embedded Workbench for V850 v3.71
+*/
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "uart.h"
+#include "board.h"
+
+void rt_hw_board_init()
+{
+#ifdef RT_USING_UART0
+	rt_hw_uart_init();
+	rt_console_set_device("uart0");
+#endif
+
+    rt_kprintf("\r\n\r\nSystemInit......\r\n");
+}
+

bsp/upd70f3454/board.h

@@ -0,0 +1,38 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ * 2010-02-04     Magicoe      add board.h to LPC176x bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include "rtdef.h"
+
+#define LB900        1
+#define LM600        2
+#define LM201R       3
+#define LM201P       4
+#define LM101        5
+
+#define PLATFORM     LM201R
+
+#define ENTER_KEY    0x1d
+#define UP_KEY       0x1b
+#define DOWN_KEY     0x17
+#define LEFT_KEY     0x0f
+#define RIGHT_KEY    0x1e  
+
+void rt_hw_board_init(void);
+rt_uint8_t get_key(void);
+
+#endif

bsp/upd70f3454/cstartup.s85

@@ -0,0 +1,839 @@
+;-----------------------------------------------------------------------------
+;       This file contains the startup code used by the V850 C/C++ compiler.
+;
+;       Copyright (c) 1998-2009 IAR Systems AB.
+;
+;       $Revision: 5028 $
+;
+;-----------------------------------------------------------------------------
+
+;
+; Naming covention of labels in this file:
+;
+;  ?xxx   - External labels only accessed from assembler.
+;  __xxx  - External labels accessed from or defined in C.
+;  xxx    - Labels local to one module (note: this file contains
+;           several modules).
+;  main   - The starting point of the user program.
+;
+
+#include "lxx.h"
+#include "cfi.h"
+
+            CASEON
+
+#define A0  R1
+#define A1  R5
+#define A2  R6
+
+;---------------------------------------------------------------;
+; Call Frame Informatio                                         ;
+;---------------------------------------------------------------;
+
+            CFNAMES
+            CFCOMMON
+
+;---------------------------------------------------------------;
+; Reset Vector                                                  ;
+;---------------------------------------------------------------;
+
+            MODULE      ?RESET
+
+            PUBLIC      ?creset
+            EXTERN      __program_start
+
+            COMMON      INTVEC:CODE:ROOT(2)
+
+?creset:
+            MOV         __program_start, R1
+            JMP         [R1]
+
+            ENDMOD
+
+;---------------------------------------------------------------;
+; Module start.                                                 ;
+;---------------------------------------------------------------;
+
+            MODULE      __program_start
+
+            PUBLIC      __program_start
+            PUBLIC      ?cstartup
+            EXTERN      ?creset
+            REQUIRE     ?creset
+
+;---------------------------------------------------------------;
+; Forward declarations of segments used in this module.         ;
+;---------------------------------------------------------------;
+
+            RSEG        CODE:CODE:NOROOT(2)
+            RSEG        CSTACK:DATA(2)
+
+;---------------------------------------------------------------;
+; The startup code.                                             ;
+;---------------------------------------------------------------;
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            ;;
+            ;; The startup sequence contained in the final linked
+            ;; application will consist of a mosaic containing
+            ;; modules and segment parts defined in this file.
+            ;;
+            ;; The only part which is required is the call to
+            ;; the function "main".
+            ;;
+
+            EXTERN      ?cstart_call_main
+            REQUIRE     ?cstart_call_main
+
+            EXTERN      __cstart_low_level_init
+            REQUIRE     __cstart_low_level_init
+
+            PUBLIC      ?BTT_cstart_begin
+?BTT_cstart_begin:
+
+?cstartup:
+__program_start:
+
+;---------------------------------------------------------------;
+; Set up the stack and the global pointer.                      ;
+;---------------------------------------------------------------;
+
+#if __CORE__ == __CORE_V850__
+            ;; If an interrupt is issued beteween the MOVEA and
+            ;; MOVHI instructions the SP will point into
+            ;; nowhere.  To fix this problem we build the new SP
+            ;; value in R1 and moves it with an atomic operation
+            ;; to SP.
+            MOVE_M      SFE CSTACK, R1
+            MOV         R1, SP
+#else
+            MOVE_M      SFE CSTACK, SP
+#endif
+
+            EXTERN      ?BREL_BASE
+            MOVE_M      ?BREL_BASE + 0x8000, GP
+
+            EXTERN      ?BREL_CBASE
+            MOVE_M      ?BREL_CBASE + 0x8000, R25
+
+;---------------------------------------------------------------;
+; Setup constant registers.                                     ;
+;---------------------------------------------------------------;
+
+            RSEG        CSTART:CODE:NOROOT(1)
+            PUBLIC      ?INIT_REG
+
+?INIT_REG:  MOV         255, R18
+            ORI         65535, zero, R19
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; Initialize the saddr base pointers.                           ;
+;---------------------------------------------------------------;
+
+            MODULE      ?INIT_SADDR_BASE
+
+            RTMODEL     "__reg_ep", "saddr"
+
+            RSEG        CSTART:CODE:NOROOT(1)
+            PUBLIC      ?INIT_SADDR_BASE
+
+?INIT_SADDR_BASE:
+            EXTERN      ?SADDR_BASE
+            MOVE_M      ?SADDR_BASE, EP
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; If hardware must be initialized from C or if watch dog timer  ;
+; must be handled or if the segment init should not be          ;
+; performed it can now be done in `__low_level_init'.           ;
+;---------------------------------------------------------------;
+; Call the user function __low_level_init, if defined.          ;
+; It is the responsibility of __low_level_init to require       ;
+; __cstart_low_level_init in order to be called by cstartup.    ;
+;---------------------------------------------------------------;
+
+            MODULE      ?CSTART_LOW_LEVEL_INIT
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            PUBLIC      __cstart_low_level_init
+            EXTERN      __low_level_init
+            REQUIRE     __low_level_init
+            EXTERN      ?no_seg_init
+
+__cstart_low_level_init:
+            CALL_FUNC   __low_level_init, LP, R1
+            ANDI        0xFF, R1, R1
+            BZ          ?no_seg_init
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; Segment initialization code. Copy initialized ROMmed code to  ;
+; RAM and ?seg_clear uninitialized variables.                   ;
+;---------------------------------------------------------------;
+
+            MODULE      ?INIT_MEMORY
+
+;---------------------------------------------------------------;
+; Zero out NEAR_Z                                               ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_NEAR_Z
+
+            RSEG        NEAR_Z(2)
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_clear
+?INIT_NEAR_Z:
+
+            MOVE_M      SFB NEAR_Z, A0
+            MOVE_M      SFE NEAR_Z, A1
+            JARL        ?seg_clear, LP
+
+
+;---------------------------------------------------------------;
+; Zero out BREL_Z                                               ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_BREL_Z
+
+            RSEG        BREL_Z(2)
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_clear
+?INIT_BREL_Z:
+
+            MOVE_M      SFB BREL_Z, A0
+            MOVE_M      SFE BREL_Z, A1
+            JARL        ?seg_clear, LP
+
+;---------------------------------------------------------------;
+; Zero out SADDR7_Z                                             ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_SADDR7_Z
+
+            RSEG        SADDR7_Z(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_clear
+?INIT_SADDR7_Z:
+
+            MOVE_M      SFB SADDR7_Z, A0
+            MOVE_M      SFE SADDR7_Z, A1
+            JARL        ?seg_clear, LP
+
+
+;---------------------------------------------------------------;
+; Zero out SADDR8_Z                                             ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_SADDR8_Z
+
+            RSEG        SADDR8_Z(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_clear
+?INIT_SADDR8_Z:
+
+            MOVE_M      SFB SADDR8_Z, A0
+            MOVE_M      SFE SADDR8_Z, A1
+            JARL        ?seg_clear, LP
+
+
+;---------------------------------------------------------------;
+; Zero out BREL23_Z                                             ;
+;---------------------------------------------------------------;
+
+#if __CORE__ >= __CORE_V850E2M__
+
+            PUBLIC      ?INIT_BREL23_Z
+
+            RSEG        BREL23_Z(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_clear
+?INIT_BREL23_Z:
+
+            MOVE_M      SFB BREL23_Z, A0
+            MOVE_M      SFE BREL23_Z, A1
+            JARL        ?seg_clear, LP
+#endif
+
+;---------------------------------------------------------------;
+; Zero out HUGE_Z                                               ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_HUGE_Z
+
+            RSEG        HUGE_Z(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_clear
+?INIT_HUGE_Z:
+
+            MOVE_M      SFB HUGE_Z, A0
+            MOVE_M      SFE HUGE_Z, A1
+            JARL        ?seg_clear, LP
+
+;---------------------------------------------------------------;
+; Copy NEAR_ID into NEAR_I                                      ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_NEAR_I
+
+            RSEG        NEAR_I(2)
+            RSEG        NEAR_ID(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_copy
+?INIT_NEAR_I:
+
+            MOVE_M      SFB NEAR_ID, A0
+            MOVE_M      SFE NEAR_ID, A1
+            MOVE_M      SFB NEAR_I, A2
+            JARL        ?seg_copy, LP
+
+;---------------------------------------------------------------;
+; Copy BREL_ID into BREL_I                                      ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_BREL_I
+
+            RSEG        BREL_I(2)
+            RSEG        BREL_ID(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_copy
+?INIT_BREL_I:
+
+            MOVE_M      SFB BREL_ID, A0
+            MOVE_M      SFE BREL_ID, A1
+            MOVE_M      SFB BREL_I, A2
+            JARL        ?seg_copy, LP
+
+;---------------------------------------------------------------;
+; Copy SADDR7_ID into SADDR7_I                                  ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_SADDR7_I
+
+            RSEG        SADDR7_I(2)
+            RSEG        SADDR7_ID(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_copy
+?INIT_SADDR7_I:
+
+            MOVE_M      SFB SADDR7_ID, A0
+            MOVE_M      SFE SADDR7_ID, A1
+            MOVE_M      SFB SADDR7_I, A2
+            JARL        ?seg_copy, LP
+
+;---------------------------------------------------------------;
+; Copy SADDR8_ID into SADDR8_I                                  ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_SADDR8_I
+
+            RSEG        SADDR8_I(2)
+            RSEG        SADDR8_ID(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_copy
+?INIT_SADDR8_I:
+
+            MOVE_M      SFB SADDR8_ID, A0
+            MOVE_M      SFE SADDR8_ID, A1
+            MOVE_M      SFB SADDR8_I, A2
+            JARL        ?seg_copy, LP
+
+;---------------------------------------------------------------;
+; Copy BREL23_ID into BREL23_I                                  ;
+;---------------------------------------------------------------;
+
+#if __CORE__ >= __CORE_V850E2M__
+
+            PUBLIC      ?INIT_BREL23_I
+
+            RSEG        BREL23_I(1)
+            RSEG        BREL23_ID(1)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_copy
+
+?INIT_BREL23_I:
+
+            MOVE_M      SFB BREL23_ID, A0
+            MOVE_M      SFE BREL23_ID, A1
+            MOVE_M      SFB BREL23_I, A2
+            JARL        ?seg_copy, LP
+
+#endif
+
+;---------------------------------------------------------------;
+; Copy HUGE_ID into HUGE_I                                      ;
+;---------------------------------------------------------------;
+            PUBLIC      ?INIT_HUGE_I
+
+            RSEG        HUGE_I(1)
+            RSEG        HUGE_ID(1)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            EXTERN      ?seg_copy
+
+?INIT_HUGE_I:
+
+            MOVE_M      SFB HUGE_ID, A0
+            MOVE_M      SFE HUGE_ID, A1
+            MOVE_M      SFB HUGE_I, A2
+            JARL        ?seg_copy, LP
+
+
+;---------------------------------------------------------------;
+; Destination label when skipping data initialization.          ;
+;---------------------------------------------------------------;
+            PUBLIC      ?no_seg_init
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+?no_seg_init:
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; Calculate code distance (PIC only).                           ;
+;---------------------------------------------------------------;
+
+            MODULE      ?INIT_PIC
+            PUBLIC      ?INIT_PIC
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            RTMODEL     "__code_model", "pic"
+
+            EXTERN      ?CODE_DISTANCE
+            EXTERN_LS_M
+
+?INIT_PIC:
+            JARL        ref_point, A1
+ref_point:  MOVE_M      ref_point, A2
+            SUB         A2, A1
+            ;; Expands to correct store instruction/sequence.
+            STORE_M     A1, ?CODE_DISTANCE, A2
+            ;; Note: A1 (the value of ?CODE_DISTANCE) is used below!
+
+            ENDMOD
+
+
+#if __CORE__ >= __CORE_V850E2M__
+
+;---------------------------------------------------------------;
+; Initialize the BSEL system register bank selector.            ;
+;---------------------------------------------------------------;
+
+            MODULE      ?INIT_BSEL
+            RSEG        CSTART:CODE:NOROOT(1)
+            PUBLIC      ?INIT_BSEL
+
+?INIT_BSEL:
+            LDSR        R0, 31          ; BSEL
+
+            ENDMOD
+
+#endif
+
+
+#if __CORE__ >= __CORE_V850E__
+
+;---------------------------------------------------------------;
+; Initialize the CALLT base pointers.                           ;
+;---------------------------------------------------------------;
+
+
+            MODULE      ?INIT_CALLT
+            PUBLIC      ?INIT_CALLT
+            EXTERN      ?CALLT_BASE
+            COMMON      CLTVEC(2)
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            RTMODEL     "__cpu", "v850e"
+
+            REQUIRE     ?CALLT_BASE
+
+            ;; The Call table base pointer
+?INIT_CALLT:
+            MOVE_M      SFB CLTVEC, A2
+#ifdef CODE_MODEL_PIC
+            EXTERN      ?CODE_DISTANCE
+            REQUIRE     ?CODE_DISTANCE
+
+            ;; Add the value of ?CODE_DISTANCE calculated above
+            ADD         A1, A2
+#endif
+#if __CORE__ >= __CORE_V850E2M__
+            EXTERN      ?INIT_BSEL
+            REQUIRE     ?INIT_BSEL
+#endif
+            LDSR        A2, 20          ; CTBP
+
+            ENDMOD
+#endif
+
+
+#if __CORE__ >= __CORE_V850E2M__
+
+;---------------------------------------------------------------;
+; Initialize the SYSCALL base pointers.                         ;
+;---------------------------------------------------------------;
+
+            MODULE      ?INIT_SYSCALL
+            PUBLIC      ?INIT_SYSCALL
+            EXTERN      ?INIT_BSEL
+            EXTERN      ?SYSCALL_BASE
+            COMMON      SYSCALLVEC(2)
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+            REQUIRE     ?INIT_BSEL
+            REQUIRE     ?SYSCALL_BASE
+
+            ;; The syscall table base pointer
+?INIT_SYSCALL:
+            MOVE_M      SFB SYSCALLVEC, A2
+#ifdef CODE_MODEL_PIC
+            EXTERN      ?CODE_DISTANCE
+            REQUIRE     ?CODE_DISTANCE
+
+            ;; Add the value of ?CODE_DISTANCE calculated above
+            ADD         A1, A2
+#endif
+            LDSR        A2, 12          ; SCBP
+
+            MOVE_M      ((SFE SYSCALLVEC - SFB SYSCALLVEC)/4) - 1, A2
+            LDSR        A2, 11          ; SCCFG
+
+            ENDMOD
+
+#endif
+
+;---------------------------------------------------------------;
+; This segment part is required by the compiler when it is      ;
+; necessary to call constructors of global objects.             ;
+;---------------------------------------------------------------;
+
+            MODULE      ?CALL_MAIN
+            RSEG        DIFUNCT(2)
+            RSEG        CSTART:CODE:NOROOT(1)
+            PUBLIC      ?cstart_call_ctors
+
+            EXTERN      __call_ctors
+
+?cstart_call_ctors:
+            MOVE_M      SFB DIFUNCT, R1
+            MOVE_M      SFE DIFUNCT, R5
+
+            CALL_FUNC   __call_ctors, LP, R6
+
+
+;---------------------------------------------------------------;
+; Call C main() with no parameters.                             ;
+;---------------------------------------------------------------;
+
+            RSEG        CSTART:CODE:NOROOT(1)
+            PUBLIC      ?cstart_call_main
+
+            EXTERN      main
+            EXTERN      exit
+            EXTERN      __exit
+
+?cstart_call_main:
+            CALL_FUNC   main, LP, R6
+
+;---------------------------------------------------------------;
+; If we come here we have returned from main with a 'return'    ;
+; statement, not with a call to exit() or abort().              ;
+; In this case we must call exit() here for a nice ending.      ;
+; Note: The return value of main() is the argument to exit().   ;
+;---------------------------------------------------------------;
+            CALL_FUNC   exit, LP, R6
+
+;---------------------------------------------------------------;
+; We should never come here, but just in case.                  ;
+;---------------------------------------------------------------;
+
+            MOV         __exit, LP
+            JMP         [LP]
+
+            PUBLIC      ?BTT_cstart_end
+?BTT_cstart_end:
+
+
+;---------------------------------------------------------------;
+; Copy a chunk of memory.                                       ;
+;       A0 = Start of from block                                ;
+;       A1 = End of from block (+1)                             ;
+;       A2 = Start of to block                                  ;
+;---------------------------------------------------------------;
+
+            PUBLIC      ?seg_copy
+            PUBLIC      ?seg_clear
+
+            RSEG        CSTART:CODE:NOROOT(1)
+            REQUIRE     done
+
+cp_cont:    LD.B        0[A0], R7
+            ADD         1, A0
+            ST.B        R7, 0[A2]
+            ADD         1, A2
+
+            ;; Note: The entry point is here.
+?seg_copy:  CMP         A0, A1
+            BNE         cp_cont
+
+            RSEG        CSTART:CODE:NOROOT(1)
+
+done:       JMP         [LP]
+
+;---------------------------------------------------------------;
+; Clear a chunk of memory.                                      ;
+;       A0 = Start of block                                     ;
+;       A1 = End of block (+1)                                  ;
+;---------------------------------------------------------------;
+
+            RSEG        CSTART:CODE:NOROOT(1)
+            REQUIRE     done
+
+?seg_clear: CMP         A0, A1
+            BE          done
+cl_cont:    ST.B        zero, 0[A0]
+            ADD         1, A0
+            BR          ?seg_clear
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; _exit code                                                    ;
+;                                                               ;
+; Call destructors (if required), then fall through to __exit.  ;
+;---------------------------------------------------------------;
+
+            MODULE      ?_exit
+            PUBLIC      _exit
+            PUBLIC      ?BTT_exit_begin
+            EXTERN      ?exit_restore2
+            RSEG        RCODE:CODE:NOROOT(1)
+
+?BTT_exit_begin:
+_exit:
+            REQUIRE     ?exit_restore2
+            ;; If any of the two pieces of code "__cstart_call_dtors"
+            ;; or "__cstart_closeall" is called we need to save the
+            ;; argument to "_exit".  However, since we never will
+            ;; from this function we can use a permanent register
+            ;; rather than storing the value on the stack.
+
+            RSEG        RCODE:CODE:NOROOT(1)
+            EXTERN      ?exit_restore
+            PUBLIC      ?exit_save
+?exit_save:
+            REQUIRE     ?exit_restore
+
+            MOV         R1, R29
+
+            RSEG        RCODE:CODE:NOROOT(1)
+            PUBLIC      __cstart_call_dtors
+            EXTERN      __call_dtors
+            REQUIRE     ?exit_save
+
+            ;; This label is required by "__record_needed_destruction".
+
+__cstart_call_dtors:
+            CALL_FUNC   __call_dtors, LP, R1
+
+            ENDMOD
+
+            ;; A new module is needed so that a non-terminal-IO program
+            ;; doesn't include this, which requires __putchar.
+
+            MODULE      ?__cstart_closeall
+            RSEG        RCODE:CODE:NOROOT(1)
+
+            ;; When stdio is used, the following piece of code is
+            ;; required by the _Closreg macro.
+
+            PUBLIC      __cstart_closeall
+            EXTERN      ?exit_save
+            REQUIRE     ?exit_save
+
+            ;; This label is required by _Closreg
+
+__cstart_closeall:
+            EXTERN      _Close_all
+            CALL_FUNC   _Close_all, LP, R1
+
+            ENDMOD
+
+            ;; Restore the argument previously stored by the "save" section
+            ;; above.
+
+            MODULE      ?_exit_end
+            RSEG        RCODE:CODE:NOROOT(1)
+
+            PUBLIC      ?exit_restore
+            EXTERN      ?exit_restore2
+
+?exit_restore:
+            REQUIRE     ?exit_restore2
+            MOV         R29, R1
+
+            ENDMOD
+
+            MODULE      ?_exit_end2
+            PUBLIC      ?BTT_exit_end
+            RSEG        RCODE:CODE:NOROOT(1)
+
+            PUBLIC      ?exit_restore2
+            EXTERN      __exit
+?exit_restore2:
+
+            MOV         __exit, LP
+            JMP         [LP]
+
+?BTT_exit_end:
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; Define the base of the base relative (brel) data for RAM.     ;
+;                                                               ;
+; This empty segment should be places in front of the brel      ;
+; RAM data segments.                                            ;
+;---------------------------------------------------------------;
+
+            MODULE      ?BREL_BASE
+            PUBLIC      ?BREL_BASE
+
+            RSEG        BREL_BASE:DATA:NOROOT(2)
+
+?BREL_BASE:
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; Define the base of the base relative (brel) data for ROM.     ;
+;                                                               ;
+; This empty segment should be places in front of the brel      ;
+; ROM data segment.                                             ;
+;---------------------------------------------------------------;
+
+            MODULE      ?BREL_CBASE
+            PUBLIC      ?BREL_CBASE
+
+            RSEG        BREL_CBASE:CONST:NOROOT(2)
+
+?BREL_CBASE:
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; Define the base of the short addressing (saddr) data.         ;
+;                                                               ;
+; This empty segment should be places in front of the saddr     ;
+; data segments.                                                ;
+;---------------------------------------------------------------;
+
+            MODULE      ?SADDR_BASE
+
+            RTMODEL     "__reg_ep", "saddr"
+
+            PUBLIC      ?SADDR_BASE
+            RSEG        SADDR_BASE:CONST:NOROOT(2)
+
+            EXTERN      ?INIT_SADDR_BASE
+            REQUIRE     ?INIT_SADDR_BASE
+
+?SADDR_BASE:
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; The base of the CALLT vector.                                 ;
+;---------------------------------------------------------------;
+
+            MODULE      ?CALLT_BASE
+
+            PUBLIC      ?CALLT_BASE
+            COMMON      CLTVEC:CONST:NOROOT(2)
+            DATA
+?CALLT_BASE:
+
+            ENDMOD
+
+
+#if __CORE__ >= __CORE_V850E2M__
+
+;---------------------------------------------------------------;
+; The base of the SYSCALL vector.                               ;
+;---------------------------------------------------------------;
+
+            MODULE      ?SYSCALL_BASE
+
+            PUBLIC      ?SYSCALL_BASE
+            COMMON      SYSCALLVEC:CONST:NOROOT(2)
+            DATA
+?SYSCALL_BASE:
+
+            ENDMOD
+
+#endif
+
+;---------------------------------------------------------------;
+; The distance the code has been moved when using position      ;
+; independent code.                                             ;
+;---------------------------------------------------------------;
+
+            MODULE      ?CODE_DISTANCE
+
+            RTMODEL     "__code_model", "pic"
+
+            PUBLIC      ?CODE_DISTANCE
+            RSEG        LIBRARY_N:DATA:NOROOT(2)
+
+            EXTERN      ?INIT_PIC
+            REQUIRE     ?INIT_PIC
+
+?CODE_DISTANCE:
+            DS          4
+
+            ENDMOD
+
+
+;---------------------------------------------------------------;
+; A dummy "low level init" that will be used if the user        ;
+; hasn't defined this function.                                 ;
+;---------------------------------------------------------------;
+
+            MODULE      ?__low_level_init_stub
+            PUBLIC      __low_level_init
+            RSEG        RCODE:CODE:NOROOT
+__low_level_init:
+            MOV         1, R1
+            JMP         [LP]
+
+            ENDMOD
+
+            END

bsp/upd70f3454/io70f3454.h

@@ -0,0 +1,1587 @@
+/*-------------------------------------------------------------------------
+ *      Declarations of Peripheral I/O registers, I/O register bits,
+ *      Interrupt/Exeption vectors, Trap vectors and, V850E only, Callt
+ *      vectors for V850E microcontroller uPD70F3454.
+ *
+ *      This header file can be used by both the V850 assembler, AV850,
+ *      and the V850 C/C++ compiler, ICCV850.
+ *
+ *      This header file is generated from the device file:
+ *          DF3454.800
+ *          Format version 2.20, File version 1.00 
+ *
+ *-------------------------------------------------------------------------*/
+
+#ifndef __IO70F3454_H__
+#define __IO70F3454_H__
+
+#if ((__TID__ >> 8) & 0x7F) != 85
+#error "IO70F3454.H file for use with AV850 / ICCV850 only"
+#endif
+
+#if ((__TID__ >> 4) & 0x0F) != 1
+#error "IO70F3454.H file for use with AV850 / ICCV850 option -v1 only"
+#endif
+
+#pragma language=extended
+#pragma system_include
+
+/***********************************************
+ *       I/O register macros
+ ***********************************************/
+
+#include "io_macros.h"
+
+/***********************************************
+ *       Peripheral I/O register declarations
+ ***********************************************/
+
+
+__IO_REG16(     PDL,             0xFFFFF004,  __READ_WRITE )
+__IO_REG8_BIT(  PDLL,            0xFFFFF004,  __READ_WRITE )
+__IO_REG8_BIT(  PDLH,            0xFFFFF005,  __READ_WRITE )
+
+__IO_REG16(     PMDL,            0xFFFFF024,  __READ_WRITE )
+__IO_REG8_BIT(  PMDLL,           0xFFFFF024,  __READ_WRITE )
+__IO_REG8_BIT(  PMDLH,           0xFFFFF025,  __READ_WRITE )
+
+__IO_REG16(     PMCDL,           0xFFFFF044,  __READ_WRITE )
+__IO_REG8_BIT(  PMCDLL,          0xFFFFF044,  __READ_WRITE )
+__IO_REG8_BIT(  PMCDLH,          0xFFFFF045,  __READ_WRITE )
+
+__IO_REG16(     BSC,             0xFFFFF066,  __READ_WRITE )
+
+__IO_REG8(      VSWC,            0xFFFFF06E,  __READ_WRITE )
+
+__IO_REG16(     DSA0L,           0xFFFFF080,  __READ_WRITE )
+__IO_REG16(     DSA0H,           0xFFFFF082,  __READ_WRITE )
+__IO_REG16(     DDA0L,           0xFFFFF084,  __READ_WRITE )
+__IO_REG16(     DDA0H,           0xFFFFF086,  __READ_WRITE )
+__IO_REG16(     DSA1L,           0xFFFFF088,  __READ_WRITE )
+__IO_REG16(     DSA1H,           0xFFFFF08A,  __READ_WRITE )
+__IO_REG16(     DDA1L,           0xFFFFF08C,  __READ_WRITE )
+__IO_REG16(     DDA1H,           0xFFFFF08E,  __READ_WRITE )
+__IO_REG16(     DSA2L,           0xFFFFF090,  __READ_WRITE )
+__IO_REG16(     DSA2H,           0xFFFFF092,  __READ_WRITE )
+__IO_REG16(     DDA2L,           0xFFFFF094,  __READ_WRITE )
+__IO_REG16(     DDA2H,           0xFFFFF096,  __READ_WRITE )
+__IO_REG16(     DSA3L,           0xFFFFF098,  __READ_WRITE )
+__IO_REG16(     DSA3H,           0xFFFFF09A,  __READ_WRITE )
+__IO_REG16(     DDA3L,           0xFFFFF09C,  __READ_WRITE )
+__IO_REG16(     DDA3H,           0xFFFFF09E,  __READ_WRITE )
+
+__IO_REG16(     DBC0,            0xFFFFF0C0,  __READ_WRITE )
+__IO_REG16(     DBC1,            0xFFFFF0C2,  __READ_WRITE )
+__IO_REG16(     DBC2,            0xFFFFF0C4,  __READ_WRITE )
+__IO_REG16(     DBC3,            0xFFFFF0C6,  __READ_WRITE )
+
+__IO_REG16(     DADC0,           0xFFFFF0D0,  __READ_WRITE )
+__IO_REG16(     DADC1,           0xFFFFF0D2,  __READ_WRITE )
+__IO_REG16(     DADC2,           0xFFFFF0D4,  __READ_WRITE )
+__IO_REG16(     DADC3,           0xFFFFF0D6,  __READ_WRITE )
+
+__IO_REG8_BIT(  DCHC0,           0xFFFFF0E0,  __READ_WRITE )
+__IO_REG8_BIT(  DCHC1,           0xFFFFF0E2,  __READ_WRITE )
+__IO_REG8_BIT(  DCHC2,           0xFFFFF0E4,  __READ_WRITE )
+__IO_REG8_BIT(  DCHC3,           0xFFFFF0E6,  __READ_WRITE )
+
+__IO_REG16(     IMR0,            0xFFFFF100,  __READ_WRITE )
+__IO_REG8_BIT(  IMR0L,           0xFFFFF100,  __READ_WRITE )
+__IO_REG8_BIT(  IMR0H,           0xFFFFF101,  __READ_WRITE )
+__IO_REG16(     IMR1,            0xFFFFF102,  __READ_WRITE )
+__IO_REG8_BIT(  IMR1L,           0xFFFFF102,  __READ_WRITE )
+__IO_REG8_BIT(  IMR1H,           0xFFFFF103,  __READ_WRITE )
+__IO_REG16(     IMR2,            0xFFFFF104,  __READ_WRITE )
+__IO_REG8_BIT(  IMR2L,           0xFFFFF104,  __READ_WRITE )
+__IO_REG8_BIT(  IMR2H,           0xFFFFF105,  __READ_WRITE )
+__IO_REG16(     IMR3,            0xFFFFF106,  __READ_WRITE )
+__IO_REG8_BIT(  IMR3L,           0xFFFFF106,  __READ_WRITE )
+__IO_REG8_BIT(  IMR3H,           0xFFFFF107,  __READ_WRITE )
+__IO_REG16(     IMR4,            0xFFFFF108,  __READ_WRITE )
+__IO_REG8_BIT(  IMR4L,           0xFFFFF108,  __READ_WRITE )
+__IO_REG8_BIT(  IMR4H,           0xFFFFF109,  __READ_WRITE )
+__IO_REG16(     IMR5,            0xFFFFF10A,  __READ_WRITE )
+__IO_REG8_BIT(  IMR5L,           0xFFFFF10A,  __READ_WRITE )
+__IO_REG8_BIT(  IMR5H,           0xFFFFF10B,  __READ_WRITE )
+
+__IO_REG8_BIT(  LVILIC,          0xFFFFF110,  __READ_WRITE )
+__IO_REG8_BIT(  LVIHIC,          0xFFFFF112,  __READ_WRITE )
+__IO_REG8_BIT(  PIC00,           0xFFFFF114,  __READ_WRITE )
+__IO_REG8_BIT(  PIC01,           0xFFFFF116,  __READ_WRITE )
+__IO_REG8_BIT(  PIC02,           0xFFFFF118,  __READ_WRITE )
+__IO_REG8_BIT(  PIC03,           0xFFFFF11A,  __READ_WRITE )
+__IO_REG8_BIT(  PIC04,           0xFFFFF11C,  __READ_WRITE )
+__IO_REG8_BIT(  PIC05,           0xFFFFF11E,  __READ_WRITE )
+__IO_REG8_BIT(  PIC06,           0xFFFFF120,  __READ_WRITE )
+__IO_REG8_BIT(  PIC07,           0xFFFFF122,  __READ_WRITE )
+__IO_REG8_BIT(  PIC08,           0xFFFFF124,  __READ_WRITE )
+__IO_REG8_BIT(  PIC09,           0xFFFFF126,  __READ_WRITE )
+__IO_REG8_BIT(  PIC10,           0xFFFFF128,  __READ_WRITE )
+__IO_REG8_BIT(  PIC11,           0xFFFFF12A,  __READ_WRITE )
+__IO_REG8_BIT(  PIC12,           0xFFFFF12C,  __READ_WRITE )
+__IO_REG8_BIT(  PIC13,           0xFFFFF12E,  __READ_WRITE )
+__IO_REG8_BIT(  PIC14,           0xFFFFF130,  __READ_WRITE )
+__IO_REG8_BIT(  PIC15,           0xFFFFF132,  __READ_WRITE )
+__IO_REG8_BIT(  PIC16,           0xFFFFF134,  __READ_WRITE )
+__IO_REG8_BIT(  PIC17,           0xFFFFF136,  __READ_WRITE )
+__IO_REG8_BIT(  PIC18,           0xFFFFF138,  __READ_WRITE )
+__IO_REG8_BIT(  CMPIC0L,         0xFFFFF13A,  __READ_WRITE )
+__IO_REG8_BIT(  CMPIC0F,         0xFFFFF13C,  __READ_WRITE )
+__IO_REG8_BIT(  CMPIC1L,         0xFFFFF13E,  __READ_WRITE )
+__IO_REG8_BIT(  CMPIC1F,         0xFFFFF140,  __READ_WRITE )
+__IO_REG8_BIT(  TB0OVIC,         0xFFFFF142,  __READ_WRITE )
+__IO_REG8_BIT(  TB0CCIC0,        0xFFFFF144,  __READ_WRITE )
+__IO_REG8_BIT(  TB0CCIC1,        0xFFFFF146,  __READ_WRITE )
+__IO_REG8_BIT(  TB0CCIC2,        0xFFFFF148,  __READ_WRITE )
+__IO_REG8_BIT(  TB0CCIC3,        0xFFFFF14A,  __READ_WRITE )
+__IO_REG8_BIT(  TB1OVIC,         0xFFFFF14C,  __READ_WRITE )
+__IO_REG8_BIT(  TB1CCIC0,        0xFFFFF14E,  __READ_WRITE )
+__IO_REG8_BIT(  TB1CCIC1,        0xFFFFF150,  __READ_WRITE )
+__IO_REG8_BIT(  TB1CCIC2,        0xFFFFF152,  __READ_WRITE )
+__IO_REG8_BIT(  TB1CCIC3,        0xFFFFF154,  __READ_WRITE )
+__IO_REG8_BIT(  TT0OVIC,         0xFFFFF156,  __READ_WRITE )
+__IO_REG8_BIT(  TT0CCIC0,        0xFFFFF158,  __READ_WRITE )
+__IO_REG8_BIT(  TT0CCIC1,        0xFFFFF15A,  __READ_WRITE )
+__IO_REG8_BIT(  TT0IECIC,        0xFFFFF15C,  __READ_WRITE )
+__IO_REG8_BIT(  TT1OVIC,         0xFFFFF15E,  __READ_WRITE )
+__IO_REG8_BIT(  TT1CCIC0,        0xFFFFF160,  __READ_WRITE )
+__IO_REG8_BIT(  TT1CCIC1,        0xFFFFF162,  __READ_WRITE )
+__IO_REG8_BIT(  TT1IECIC,        0xFFFFF164,  __READ_WRITE )
+__IO_REG8_BIT(  TA0OVIC,         0xFFFFF166,  __READ_WRITE )
+__IO_REG8_BIT(  TA0CCIC0,        0xFFFFF168,  __READ_WRITE )
+__IO_REG8_BIT(  TA0CCIC1,        0xFFFFF16A,  __READ_WRITE )
+__IO_REG8_BIT(  TA1OVIC,         0xFFFFF16C,  __READ_WRITE )
+__IO_REG8_BIT(  TA1CCIC0,        0xFFFFF16E,  __READ_WRITE )
+__IO_REG8_BIT(  TA1CCIC1,        0xFFFFF170,  __READ_WRITE )
+__IO_REG8_BIT(  TA2OVIC,         0xFFFFF172,  __READ_WRITE )
+__IO_REG8_BIT(  TA2CCIC0,        0xFFFFF174,  __READ_WRITE )
+__IO_REG8_BIT(  TA2CCIC1,        0xFFFFF176,  __READ_WRITE )
+__IO_REG8_BIT(  TA3OVIC,         0xFFFFF178,  __READ_WRITE )
+__IO_REG8_BIT(  TA3CCIC0,        0xFFFFF17A,  __READ_WRITE )
+__IO_REG8_BIT(  TA3CCIC1,        0xFFFFF17C,  __READ_WRITE )
+__IO_REG8_BIT(  TA4OVIC,         0xFFFFF17E,  __READ_WRITE )
+__IO_REG8_BIT(  TA4CCIC0,        0xFFFFF180,  __READ_WRITE )
+__IO_REG8_BIT(  TA4CCIC1,        0xFFFFF182,  __READ_WRITE )
+__IO_REG8_BIT(  DMAIC0,          0xFFFFF184,  __READ_WRITE )
+__IO_REG8_BIT(  DMAIC1,          0xFFFFF186,  __READ_WRITE )
+__IO_REG8_BIT(  DMAIC2,          0xFFFFF188,  __READ_WRITE )
+__IO_REG8_BIT(  DMAIC3,          0xFFFFF18A,  __READ_WRITE )
+__IO_REG8_BIT(  UREIC,           0xFFFFF18C,  __READ_WRITE )
+__IO_REG8_BIT(  URIC,            0xFFFFF18E,  __READ_WRITE )
+__IO_REG8_BIT(  UTIC,            0xFFFFF190,  __READ_WRITE )
+__IO_REG8_BIT(  UIFIC,           0xFFFFF192,  __READ_WRITE )
+__IO_REG8_BIT(  UTOIC,           0xFFFFF194,  __READ_WRITE )
+__IO_REG8_BIT(  UA0REIC,         0xFFFFF196,  __READ_WRITE )
+__IO_REG8_BIT(  UA0RIC,          0xFFFFF198,  __READ_WRITE )
+__IO_REG8_BIT(  UA0TIC,          0xFFFFF19A,  __READ_WRITE )
+__IO_REG8_BIT(  CB0REIC,         0xFFFFF19C,  __READ_WRITE )
+__IO_REG8_BIT(  CB0RIC,          0xFFFFF19E,  __READ_WRITE )
+__IO_REG8_BIT(  CB0TIC,          0xFFFFF1A0,  __READ_WRITE )
+__IO_REG8_BIT(  UA1REIC,         0xFFFFF1A2,  __READ_WRITE )
+__IO_REG8_BIT(  UA1RIC,          0xFFFFF1A4,  __READ_WRITE )
+__IO_REG8_BIT(  UA1TIC,          0xFFFFF1A6,  __READ_WRITE )
+__IO_REG8_BIT(  CB1REIC,         0xFFFFF1A8,  __READ_WRITE )
+__IO_REG8_BIT(  CB1RIC,          0xFFFFF1AA,  __READ_WRITE )
+__IO_REG8_BIT(  CB1TIC,          0xFFFFF1AC,  __READ_WRITE )
+__IO_REG8_BIT(  UA2REIC,         0xFFFFF1AE,  __READ_WRITE )
+__IO_REG8_BIT(  UA2RIC,          0xFFFFF1B0,  __READ_WRITE )
+__IO_REG8_BIT(  UA2TIC,          0xFFFFF1B2,  __READ_WRITE )
+__IO_REG8_BIT(  CB2REIC,         0xFFFFF1B4,  __READ_WRITE )
+__IO_REG8_BIT(  CB2RIC,          0xFFFFF1B6,  __READ_WRITE )
+__IO_REG8_BIT(  CB2TIC,          0xFFFFF1B8,  __READ_WRITE )
+__IO_REG8_BIT(  IICIC,           0xFFFFF1BA,  __READ_WRITE )
+__IO_REG8_BIT(  AD0IC,           0xFFFFF1BC,  __READ_WRITE )
+__IO_REG8_BIT(  AD1IC,           0xFFFFF1BE,  __READ_WRITE )
+__IO_REG8_BIT(  AD2IC,           0xFFFFF1C0,  __READ_WRITE )
+__IO_REG8_BIT(  TM0EQIC0,        0xFFFFF1C2,  __READ_WRITE )
+__IO_REG8_BIT(  TM1EQIC0,        0xFFFFF1C4,  __READ_WRITE )
+__IO_REG8_BIT(  TM2EQIC0,        0xFFFFF1C6,  __READ_WRITE )
+__IO_REG8_BIT(  TM3EQIC0,        0xFFFFF1C8,  __READ_WRITE )
+__IO_REG8_BIT(  ADT0IC,          0xFFFFF1CA,  __READ_WRITE )
+__IO_REG8_BIT(  ADT1IC,          0xFFFFF1CC,  __READ_WRITE )
+
+__IO_REG8_BIT(  ISPR,            0xFFFFF1FA,  __READ       )
+__IO_REG8(      PRCMD,           0xFFFFF1FC,  __WRITE      )
+__IO_REG8_BIT(  PSC,             0xFFFFF1FE,  __READ_WRITE )
+__IO_REG16(     AD0CR0,          0xFFFFF200,  __READ       )
+__IO_REG8(      AD0CR0H,         0xFFFFF201,  __READ       )
+__IO_REG16(     AD0CR1,          0xFFFFF202,  __READ       )
+__IO_REG8(      AD0CR1H,         0xFFFFF203,  __READ       )
+__IO_REG16(     AD0CR2,          0xFFFFF204,  __READ       )
+__IO_REG8(      AD0CR2H,         0xFFFFF205,  __READ       )
+__IO_REG16(     AD0CR3,          0xFFFFF206,  __READ       )
+__IO_REG8(      AD0CR3H,         0xFFFFF207,  __READ       )
+__IO_REG16(     AD0CR4,          0xFFFFF208,  __READ       )
+__IO_REG8(      AD0CR4H,         0xFFFFF209,  __READ       )
+__IO_REG16(     AD0CR5,          0xFFFFF20A,  __READ       )
+__IO_REG8(      AD0CR5H,         0xFFFFF20B,  __READ       )
+__IO_REG16(     AD0CR6,          0xFFFFF20C,  __READ       )
+__IO_REG8(      AD0CR6H,         0xFFFFF20D,  __READ       )
+__IO_REG16(     AD0CR7,          0xFFFFF20E,  __READ       )
+__IO_REG8(      AD0CR7H,         0xFFFFF20F,  __READ       )
+__IO_REG16(     AD0CR8,          0xFFFFF210,  __READ       )
+__IO_REG8(      AD0CR8H,         0xFFFFF211,  __READ       )
+__IO_REG16(     AD0CR9,          0xFFFFF212,  __READ       )
+__IO_REG8(      AD0CR9H,         0xFFFFF213,  __READ       )
+__IO_REG16(     AD0CR10,         0xFFFFF214,  __READ       )
+__IO_REG8(      AD0CR10H,        0xFFFFF215,  __READ       )
+__IO_REG16(     AD0CR11,         0xFFFFF216,  __READ       )
+__IO_REG8(      AD0CR11H,        0xFFFFF217,  __READ       )
+__IO_REG16(     AD0CR12,         0xFFFFF218,  __READ       )
+__IO_REG8(      AD0CR12H,        0xFFFFF219,  __READ       )
+__IO_REG16(     AD0CR13,         0xFFFFF21A,  __READ       )
+__IO_REG8(      AD0CR13H,        0xFFFFF21B,  __READ       )
+__IO_REG16(     AD0CR14,         0xFFFFF21C,  __READ       )
+__IO_REG8(      AD0CR14H,        0xFFFFF21D,  __READ       )
+__IO_REG16(     AD0CR15,         0xFFFFF21E,  __READ       )
+__IO_REG8(      AD0CR15H,        0xFFFFF21F,  __READ       )
+__IO_REG16(     AD0SCM,          0xFFFFF220,  __READ_WRITE )
+__IO_REG8_BIT(  AD0SCML,         0xFFFFF220,  __READ_WRITE )
+__IO_REG8_BIT(  AD0SCMH,         0xFFFFF221,  __READ_WRITE )
+__IO_REG8_BIT(  AD0CTC,          0xFFFFF222,  __READ_WRITE )
+__IO_REG16(     AD0CHEN,         0xFFFFF224,  __READ_WRITE )
+__IO_REG8_BIT(  AD0CHENL,        0xFFFFF224,  __READ_WRITE )
+__IO_REG8_BIT(  AD0CHENH,        0xFFFFF225,  __READ_WRITE )
+
+__IO_REG8_BIT(  AD0CTL0,         0xFFFFF230,  __READ_WRITE )
+__IO_REG8_BIT(  AD0TSEL,         0xFFFFF231,  __READ_WRITE )
+__IO_REG8_BIT(  AD0CH1,          0xFFFFF232,  __READ_WRITE )
+__IO_REG8_BIT(  AD0CH2,          0xFFFFF233,  __READ_WRITE )
+
+__IO_REG16(     AD0ECR0,         0xFFFFF240,  __READ       )
+__IO_REG8(      AD0ECR0H,        0xFFFFF241,  __READ       )
+__IO_REG16(     AD0ECR1,         0xFFFFF242,  __READ       )
+__IO_REG8(      AD0ECR1H,        0xFFFFF243,  __READ       )
+__IO_REG16(     AD0ECR2,         0xFFFFF244,  __READ       )
+__IO_REG8(      AD0ECR2H,        0xFFFFF245,  __READ       )
+__IO_REG16(     AD0ECR3,         0xFFFFF246,  __READ       )
+__IO_REG8(      AD0ECR3H,        0xFFFFF247,  __READ       )
+__IO_REG16(     AD0ECR4,         0xFFFFF248,  __READ       )
+__IO_REG8(      AD0ECR4H,        0xFFFFF249,  __READ       )
+
+__IO_REG8(      AD0FLG,          0xFFFFF254,  __READ       )
+__IO_REG8(      AD0FLGB,         0xFFFFF255,  __READ       )
+
+__IO_REG8(      OP0CTL0,         0xFFFFF260,  __READ_WRITE )
+__IO_REG8(      CMP0CTL0,        0xFFFFF261,  __READ_WRITE )
+__IO_REG8(      CMP0CTL1,        0xFFFFF262,  __READ       )
+__IO_REG8(      CMP0CTL2,        0xFFFFF263,  __READ_WRITE )
+__IO_REG8(      CMP0CTL3,        0xFFFFF264,  __READ_WRITE )
+
+__IO_REG8(      AD0OCKS,         0xFFFFF270,  __READ_WRITE )
+
+__IO_REG8(      AD1OCKS,         0xFFFFF274,  __READ_WRITE )
+
+__IO_REG8(      CMPNFC0L,        0xFFFFF278,  __READ_WRITE )
+__IO_REG8(      CMPNFC0F,        0xFFFFF27A,  __READ_WRITE )
+__IO_REG8(      CMPNFC1L,        0xFFFFF27C,  __READ_WRITE )
+__IO_REG8(      CMPNFC1F,        0xFFFFF27E,  __READ_WRITE )
+__IO_REG16(     AD1CR0,          0xFFFFF280,  __READ       )
+__IO_REG8(      AD1CR0H,         0xFFFFF281,  __READ       )
+__IO_REG16(     AD1CR1,          0xFFFFF282,  __READ       )
+__IO_REG8(      AD1CR1H,         0xFFFFF283,  __READ       )
+__IO_REG16(     AD1CR2,          0xFFFFF284,  __READ       )
+__IO_REG8(      AD1CR2H,         0xFFFFF285,  __READ       )
+__IO_REG16(     AD1CR3,          0xFFFFF286,  __READ       )
+__IO_REG8(      AD1CR3H,         0xFFFFF287,  __READ       )
+__IO_REG16(     AD1CR4,          0xFFFFF288,  __READ       )
+__IO_REG8(      AD1CR4H,         0xFFFFF289,  __READ       )
+__IO_REG16(     AD1CR5,          0xFFFFF28A,  __READ       )
+__IO_REG8(      AD1CR5H,         0xFFFFF28B,  __READ       )
+__IO_REG16(     AD1CR6,          0xFFFFF28C,  __READ       )
+__IO_REG8(      AD1CR6H,         0xFFFFF28D,  __READ       )
+__IO_REG16(     AD1CR7,          0xFFFFF28E,  __READ       )
+__IO_REG8(      AD1CR7H,         0xFFFFF28F,  __READ       )
+__IO_REG16(     AD1CR8,          0xFFFFF290,  __READ       )
+__IO_REG8(      AD1CR8H,         0xFFFFF291,  __READ       )
+__IO_REG16(     AD1CR9,          0xFFFFF292,  __READ       )
+__IO_REG8(      AD1CR9H,         0xFFFFF293,  __READ       )
+__IO_REG16(     AD1CR10,         0xFFFFF294,  __READ       )
+__IO_REG8(      AD1CR10H,        0xFFFFF295,  __READ       )
+__IO_REG16(     AD1CR11,         0xFFFFF296,  __READ       )
+__IO_REG8(      AD1CR11H,        0xFFFFF297,  __READ       )
+__IO_REG16(     AD1CR12,         0xFFFFF298,  __READ       )
+__IO_REG8(      AD1CR12H,        0xFFFFF299,  __READ       )
+__IO_REG16(     AD1CR13,         0xFFFFF29A,  __READ       )
+__IO_REG8(      AD1CR13H,        0xFFFFF29B,  __READ       )
+__IO_REG16(     AD1CR14,         0xFFFFF29C,  __READ       )
+__IO_REG8(      AD1CR14H,        0xFFFFF29D,  __READ       )
+__IO_REG16(     AD1CR15,         0xFFFFF29E,  __READ       )
+__IO_REG8(      AD1CR15H,        0xFFFFF29F,  __READ       )
+__IO_REG16(     AD1SCM,          0xFFFFF2A0,  __READ_WRITE )
+__IO_REG8_BIT(  AD1SCML,         0xFFFFF2A0,  __READ_WRITE )
+__IO_REG8_BIT(  AD1SCMH,         0xFFFFF2A1,  __READ_WRITE )
+__IO_REG8_BIT(  AD1CTC,          0xFFFFF2A2,  __READ_WRITE )
+__IO_REG16(     AD1CHEN,         0xFFFFF2A4,  __READ_WRITE )
+__IO_REG8_BIT(  AD1CHENL,        0xFFFFF2A4,  __READ_WRITE )
+__IO_REG8_BIT(  AD1CHENH,        0xFFFFF2A5,  __READ_WRITE )
+
+__IO_REG8_BIT(  AD1CTL0,         0xFFFFF2B0,  __READ_WRITE )
+__IO_REG8_BIT(  AD1TSEL,         0xFFFFF2B1,  __READ_WRITE )
+__IO_REG8_BIT(  AD1CH1,          0xFFFFF2B2,  __READ_WRITE )
+__IO_REG8_BIT(  AD1CH2,          0xFFFFF2B3,  __READ_WRITE )
+
+__IO_REG16(     AD1ECR0,         0xFFFFF2C0,  __READ       )
+__IO_REG8(      AD1ECR0H,        0xFFFFF2C1,  __READ       )
+__IO_REG16(     AD1ECR1,         0xFFFFF2C2,  __READ       )
+__IO_REG8(      AD1ECR1H,        0xFFFFF2C3,  __READ       )
+__IO_REG16(     AD1ECR2,         0xFFFFF2C4,  __READ       )
+__IO_REG8(      AD1ECR2H,        0xFFFFF2C5,  __READ       )
+__IO_REG16(     AD1ECR3,         0xFFFFF2C6,  __READ       )
+__IO_REG8(      AD1ECR3H,        0xFFFFF2C7,  __READ       )
+__IO_REG16(     AD1ECR4,         0xFFFFF2C8,  __READ       )
+
+__IO_REG8(      AD1ECB4H,        0xFFFFF2D3,  __READ       )
+__IO_REG8(      AD1FLG,          0xFFFFF2D4,  __READ       )
+__IO_REG8(      AD1FLGB,         0xFFFFF2D5,  __READ       )
+
+__IO_REG8(      OP1CTL0,         0xFFFFF2E0,  __READ_WRITE )
+__IO_REG8(      CMP1CTL0,        0xFFFFF2E1,  __READ_WRITE )
+__IO_REG8(      CMP1CTL1,        0xFFFFF2E2,  __READ       )
+__IO_REG8(      CMP1CTL2,        0xFFFFF2E3,  __READ_WRITE )
+__IO_REG8(      CMP1CTL3,        0xFFFFF2E4,  __READ_WRITE )
+
+__IO_REG8_BIT(  ADTF,            0xFFFFF2F0,  __READ_WRITE )
+__IO_REG8_BIT(  ADTR,            0xFFFFF2F2,  __READ_WRITE )
+__IO_REG8_BIT(  CMPOF,           0xFFFFF2F4,  __READ_WRITE )
+__IO_REG8_BIT(  CMPOR,           0xFFFFF2F6,  __READ_WRITE )
+__IO_REG8(      ADLTS1,          0xFFFFF2F8,  __READ_WRITE )
+__IO_REG8(      ADLTS2,          0xFFFFF2FA,  __READ_WRITE )
+
+__IO_REG8(      INTNFC14,        0xFFFFF310,  __READ_WRITE )
+__IO_REG8(      INTNFC15,        0xFFFFF312,  __READ_WRITE )
+__IO_REG8(      INTNFC16,        0xFFFFF314,  __READ_WRITE )
+
+__IO_REG8_BIT(  P0,              0xFFFFF400,  __READ_WRITE )
+__IO_REG8_BIT(  P1,              0xFFFFF402,  __READ_WRITE )
+__IO_REG8_BIT(  P2,              0xFFFFF404,  __READ_WRITE )
+__IO_REG8_BIT(  P3,              0xFFFFF406,  __READ_WRITE )
+__IO_REG8_BIT(  P4,              0xFFFFF408,  __READ_WRITE )
+
+__IO_REG8_BIT(  PM0,             0xFFFFF420,  __READ_WRITE )
+__IO_REG8_BIT(  PM1,             0xFFFFF422,  __READ_WRITE )
+__IO_REG8_BIT(  PM2,             0xFFFFF424,  __READ_WRITE )
+__IO_REG8_BIT(  PM3,             0xFFFFF426,  __READ_WRITE )
+__IO_REG8_BIT(  PM4,             0xFFFFF428,  __READ_WRITE )
+
+__IO_REG8_BIT(  PMC0,            0xFFFFF440,  __READ_WRITE )
+__IO_REG8_BIT(  PMC1,            0xFFFFF442,  __READ_WRITE )
+__IO_REG8_BIT(  PMC2,            0xFFFFF444,  __READ_WRITE )
+__IO_REG8_BIT(  PMC3,            0xFFFFF446,  __READ_WRITE )
+__IO_REG8_BIT(  PMC4,            0xFFFFF448,  __READ_WRITE )
+
+__IO_REG8_BIT(  PFC0,            0xFFFFF460,  __READ_WRITE )
+__IO_REG8_BIT(  PFC1,            0xFFFFF462,  __READ_WRITE )
+__IO_REG8_BIT(  PFC2,            0xFFFFF464,  __READ_WRITE )
+__IO_REG8_BIT(  PFC3,            0xFFFFF466,  __READ_WRITE )
+__IO_REG8_BIT(  PFC4,            0xFFFFF468,  __READ_WRITE )
+
+__IO_REG16(     BCT0,            0xFFFFF480,  __READ_WRITE )
+
+__IO_REG16(     DWC0,            0xFFFFF484,  __READ_WRITE )
+
+__IO_REG16(     AWC,             0xFFFFF488,  __READ_WRITE )
+__IO_REG16(     BCC,             0xFFFFF48A,  __READ_WRITE )
+
+__IO_REG8(      DVC,             0xFFFFF48E,  __READ_WRITE )
+
+__IO_REG8_BIT(  TM0CTL0,         0xFFFFF540,  __READ_WRITE )
+
+__IO_REG16(     TM0CMP0,         0xFFFFF544,  __READ_WRITE )
+
+__IO_REG8_BIT(  TM1CTL0,         0xFFFFF550,  __READ_WRITE )
+
+__IO_REG16(     TM1CMP0,         0xFFFFF554,  __READ_WRITE )
+
+__IO_REG8_BIT(  TM2CTL0,         0xFFFFF560,  __READ_WRITE )
+
+__IO_REG16(     TM2CMP0,         0xFFFFF564,  __READ_WRITE )
+
+__IO_REG8_BIT(  TM3CTL0,         0xFFFFF570,  __READ_WRITE )
+
+__IO_REG16(     TM3CMP0,         0xFFFFF574,  __READ_WRITE )
+
+__IO_REG8_BIT(  TT0CTL0,         0xFFFFF580,  __READ_WRITE )
+__IO_REG8_BIT(  TT0CTL1,         0xFFFFF581,  __READ_WRITE )
+__IO_REG8_BIT(  TT0CTL2,         0xFFFFF582,  __READ_WRITE )
+__IO_REG8_BIT(  TT0IOC0,         0xFFFFF583,  __READ_WRITE )
+__IO_REG8_BIT(  TT0IOC1,         0xFFFFF584,  __READ_WRITE )
+__IO_REG8_BIT(  TT0IOC2,         0xFFFFF585,  __READ_WRITE )
+__IO_REG8_BIT(  TT0IOC3,         0xFFFFF586,  __READ_WRITE )
+__IO_REG8_BIT(  TT0OPT0,         0xFFFFF587,  __READ_WRITE )
+__IO_REG8_BIT(  TT0OPT1,         0xFFFFF588,  __READ_WRITE )
+__IO_REG16(     TT0CCR0,         0xFFFFF58A,  __READ_WRITE )
+__IO_REG16(     TT0CCR1,         0xFFFFF58C,  __READ_WRITE )
+__IO_REG16(     TT0CNT,          0xFFFFF58E,  __READ       )
+__IO_REG16(     TT0TCW,          0xFFFFF590,  __READ_WRITE )
+
+__IO_REG8(      TTNFC0,          0xFFFFF5A0,  __READ_WRITE )
+__IO_REG8(      TTNFC1,          0xFFFFF5A2,  __READ_WRITE )
+__IO_REG8(      TTISL0,          0xFFFFF5A4,  __READ_WRITE )
+__IO_REG8(      TTISL1,          0xFFFFF5A6,  __READ_WRITE )
+
+__IO_REG8_BIT(  TT1CTL0,         0xFFFFF5C0,  __READ_WRITE )
+__IO_REG8_BIT(  TT1CTL1,         0xFFFFF5C1,  __READ_WRITE )
+__IO_REG8_BIT(  TT1CTL2,         0xFFFFF5C2,  __READ_WRITE )
+__IO_REG8_BIT(  TT1IOC0,         0xFFFFF5C3,  __READ_WRITE )
+__IO_REG8_BIT(  TT1IOC1,         0xFFFFF5C4,  __READ_WRITE )
+__IO_REG8_BIT(  TT1IOC2,         0xFFFFF5C5,  __READ_WRITE )
+__IO_REG8_BIT(  TT1IOC3,         0xFFFFF5C6,  __READ_WRITE )
+__IO_REG8_BIT(  TT1OPT0,         0xFFFFF5C7,  __READ_WRITE )
+__IO_REG8_BIT(  TT1OPT1,         0xFFFFF5C8,  __READ_WRITE )
+__IO_REG16(     TT1CCR0,         0xFFFFF5CA,  __READ_WRITE )
+__IO_REG16(     TT1CCR1,         0xFFFFF5CC,  __READ_WRITE )
+__IO_REG16(     TT1CNT,          0xFFFFF5CE,  __READ       )
+__IO_REG16(     TT1TCW,          0xFFFFF5D0,  __READ_WRITE )
+
+__IO_REG8_BIT(  TAB0CTL0,        0xFFFFF5E0,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0CTL1,        0xFFFFF5E1,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0IOC0,        0xFFFFF5E2,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0IOC1,        0xFFFFF5E3,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0IOC2,        0xFFFFF5E4,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0OPT0,        0xFFFFF5E5,  __READ_WRITE )
+__IO_REG16(     TAB0CCR0,        0xFFFFF5E6,  __READ_WRITE )
+__IO_REG16(     TAB0CCR1,        0xFFFFF5E8,  __READ_WRITE )
+__IO_REG16(     TAB0CCR2,        0xFFFFF5EA,  __READ_WRITE )
+__IO_REG16(     TAB0CCR3,        0xFFFFF5EC,  __READ_WRITE )
+__IO_REG16(     TAB0CNT,         0xFFFFF5EE,  __READ       )
+
+__IO_REG8_BIT(  TAB0OPT1,        0xFFFFF600,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0OPT2,        0xFFFFF601,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0IOC3,        0xFFFFF602,  __READ_WRITE )
+__IO_REG8_BIT(  TAB0OPT3,        0xFFFFF603,  __READ_WRITE )
+__IO_REG16(     TAB0DTC,         0xFFFFF604,  __READ_WRITE )
+
+__IO_REG8_BIT(  HZA0CTL0,        0xFFFFF610,  __READ_WRITE )
+__IO_REG8_BIT(  HZA0CTL1,        0xFFFFF611,  __READ_WRITE )
+
+__IO_REG8_BIT(  HZA1CTL0,        0xFFFFF618,  __READ_WRITE )
+__IO_REG8_BIT(  HZA1CTL1,        0xFFFFF619,  __READ_WRITE )
+
+__IO_REG8_BIT(  TAB1CTL0,        0xFFFFF620,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1CTL1,        0xFFFFF621,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1IOC0,        0xFFFFF622,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1IOC1,        0xFFFFF623,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1IOC2,        0xFFFFF624,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1OPT0,        0xFFFFF625,  __READ_WRITE )
+__IO_REG16(     TAB1CCR0,        0xFFFFF626,  __READ_WRITE )
+__IO_REG16(     TAB1CCR1,        0xFFFFF628,  __READ_WRITE )
+__IO_REG16(     TAB1CCR2,        0xFFFFF62A,  __READ_WRITE )
+__IO_REG16(     TAB1CCR3,        0xFFFFF62C,  __READ_WRITE )
+__IO_REG16(     TAB1CNT,         0xFFFFF62E,  __READ       )
+
+__IO_REG8_BIT(  TAB1OPT1,        0xFFFFF640,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1OPT2,        0xFFFFF641,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1IOC3,        0xFFFFF642,  __READ_WRITE )
+__IO_REG8_BIT(  TAB1OPT3,        0xFFFFF643,  __READ_WRITE )
+__IO_REG16(     TAB1DTC,         0xFFFFF644,  __READ_WRITE )
+
+__IO_REG8_BIT(  HZA2CTL0,        0xFFFFF650,  __READ_WRITE )
+__IO_REG8_BIT(  HZA2CTL1,        0xFFFFF651,  __READ_WRITE )
+
+__IO_REG8_BIT(  HZA3CTL0,        0xFFFFF658,  __READ_WRITE )
+__IO_REG8_BIT(  HZA3CTL1,        0xFFFFF659,  __READ_WRITE )
+
+__IO_REG8_BIT(  TAA0CTL0,        0xFFFFF660,  __READ_WRITE )
+__IO_REG8_BIT(  TAA0CTL1,        0xFFFFF661,  __READ_WRITE )
+
+__IO_REG8_BIT(  TAA0OPT0,        0xFFFFF665,  __READ_WRITE )
+__IO_REG16(     TAA0CCR0,        0xFFFFF666,  __READ_WRITE )
+__IO_REG16(     TAA0CCR1,        0xFFFFF668,  __READ_WRITE )
+__IO_REG16(     TAA0CNT,         0xFFFFF66A,  __READ       )
+
+__IO_REG8_BIT(  TAA1CTL0,        0xFFFFF680,  __READ_WRITE )
+__IO_REG8_BIT(  TAA1CTL1,        0xFFFFF681,  __READ_WRITE )
+
+__IO_REG8_BIT(  TAA1OPT0,        0xFFFFF685,  __READ_WRITE )
+__IO_REG16(     TAA1CCR0,        0xFFFFF686,  __READ_WRITE )
+__IO_REG16(     TAA1CCR1,        0xFFFFF688,  __READ_WRITE )
+__IO_REG16(     TAA1CNT,         0xFFFFF68A,  __READ       )
+
+__IO_REG8_BIT(  TAA2CTL0,        0xFFFFF6A0,  __READ_WRITE )
+__IO_REG8_BIT(  TAA2CTL1,        0xFFFFF6A1,  __READ_WRITE )
+__IO_REG8_BIT(  TAA2IOC0,        0xFFFFF6A2,  __READ_WRITE )
+__IO_REG8_BIT(  TAA2IOC1,        0xFFFFF6A3,  __READ_WRITE )
+__IO_REG8_BIT(  TAA2IOC2,        0xFFFFF6A4,  __READ_WRITE )
+__IO_REG8_BIT(  TAA2OPT0,        0xFFFFF6A5,  __READ_WRITE )
+__IO_REG16(     TAA2CCR0,        0xFFFFF6A6,  __READ_WRITE )
+__IO_REG16(     TAA2CCR1,        0xFFFFF6A8,  __READ_WRITE )
+__IO_REG16(     TAA2CNT,         0xFFFFF6AA,  __READ       )
+
+__IO_REG8(      OSTS,            0xFFFFF6C0,  __READ_WRITE )
+
+__IO_REG8_BIT(  WDTM,            0xFFFFF6D0,  __READ_WRITE )
+__IO_REG8(      WDTE,            0xFFFFF6D1,  __READ_WRITE )
+
+__IO_REG8_BIT(  PFCE0,           0xFFFFF700,  __READ_WRITE )
+__IO_REG8_BIT(  PFCE1,           0xFFFFF702,  __READ_WRITE )
+__IO_REG8_BIT(  PFCE2,           0xFFFFF704,  __READ_WRITE )
+__IO_REG8_BIT(  PFCE3,           0xFFFFF706,  __READ_WRITE )
+__IO_REG8_BIT(  PFCE4,           0xFFFFF708,  __READ_WRITE )
+
+__IO_REG8_BIT(  SYS,             0xFFFFF802,  __READ_WRITE )
+
+__IO_REG8_BIT(  DTFR0,           0xFFFFF810,  __READ_WRITE )
+__IO_REG8_BIT(  DTFR1,           0xFFFFF812,  __READ_WRITE )
+__IO_REG8_BIT(  DTFR2,           0xFFFFF814,  __READ_WRITE )
+__IO_REG8_BIT(  DTFR3,           0xFFFFF816,  __READ_WRITE )
+
+__IO_REG8_BIT(  PSMR,            0xFFFFF820,  __READ_WRITE )
+
+__IO_REG8_BIT(  PCC,             0xFFFFF828,  __READ_WRITE )
+
+__IO_REG8_BIT(  PLLCTL,          0xFFFFF82C,  __READ_WRITE )
+
+__IO_REG8_BIT(  CLM,             0xFFFFF870,  __READ_WRITE )
+
+__IO_REG8_BIT(  RESF,            0xFFFFF888,  __READ_WRITE )
+
+__IO_REG8_BIT(  LVIM,            0xFFFFF890,  __READ_WRITE )
+__IO_REG8(      LVIS,            0xFFFFF891,  __READ_WRITE )
+
+__IO_REG8_BIT(  UA0CTL0,         0xFFFFFA00,  __READ_WRITE )
+__IO_REG8(      UA0CTL1,         0xFFFFFA01,  __READ_WRITE )
+__IO_REG8(      UA0CTL2,         0xFFFFFA02,  __READ_WRITE )
+__IO_REG8_BIT(  UA0OPT0,         0xFFFFFA03,  __READ_WRITE )
+__IO_REG8_BIT(  UA0STR,          0xFFFFFA04,  __READ_WRITE )
+__IO_REG8(      UA0RX,           0xFFFFFA06,  __READ       )
+__IO_REG8(      UA0TX,           0xFFFFFA07,  __READ_WRITE )
+
+__IO_REG8_BIT(  UA1CTL0,         0xFFFFFA10,  __READ_WRITE )
+__IO_REG8(      UA1CTL1,         0xFFFFFA11,  __READ_WRITE )
+__IO_REG8(      UA1CTL2,         0xFFFFFA12,  __READ_WRITE )
+__IO_REG8_BIT(  UA1OPT0,         0xFFFFFA13,  __READ_WRITE )
+__IO_REG8_BIT(  UA1STR,          0xFFFFFA14,  __READ_WRITE )
+__IO_REG8(      UA1RX,           0xFFFFFA16,  __READ       )
+__IO_REG8(      UA1TX,           0xFFFFFA17,  __READ_WRITE )
+
+__IO_REG8_BIT(  UA2CTL0,         0xFFFFFA20,  __READ_WRITE )
+__IO_REG8(      UA2CTL1,         0xFFFFFA21,  __READ_WRITE )
+__IO_REG8(      UA2CTL2,         0xFFFFFA22,  __READ_WRITE )
+__IO_REG8_BIT(  UA2OPT0,         0xFFFFFA23,  __READ_WRITE )
+__IO_REG8_BIT(  UA2STR,          0xFFFFFA24,  __READ_WRITE )
+__IO_REG8(      UA2RX,           0xFFFFFA26,  __READ       )
+__IO_REG8(      UA2TX,           0xFFFFFA27,  __READ_WRITE )
+
+__IO_REG8_BIT(  UBCTL0,          0xFFFFFA40,  __READ_WRITE )
+__IO_REG16(     UBCTL2,          0xFFFFFA42,  __READ_WRITE )
+__IO_REG8_BIT(  UBSTR,           0xFFFFFA44,  __READ_WRITE )
+__IO_REG16(     UBRXAP,          0xFFFFFA46,  __READ       )
+__IO_REG8(      UBRX,            0xFFFFFA46,  __READ       )
+__IO_REG8(      UBTX,            0xFFFFFA48,  __WRITE      )
+__IO_REG8_BIT(  UBFIC0,          0xFFFFFA4A,  __READ_WRITE )
+__IO_REG8_BIT(  UBFIC1,          0xFFFFFA4B,  __READ_WRITE )
+__IO_REG16(     UBFIC2,          0xFFFFFA4C,  __READ_WRITE )
+__IO_REG8(      UBFIC2L,         0xFFFFFA4C,  __READ_WRITE )
+__IO_REG8(      UBFIC2H,         0xFFFFFA4D,  __READ_WRITE )
+__IO_REG8(      UBFIS0,          0xFFFFFA4E,  __READ       )
+__IO_REG8(      UBFIS1,          0xFFFFFA4F,  __READ       )
+
+__IO_REG8_BIT(  TAA3CTL0,        0xFFFFFB00,  __READ_WRITE )
+__IO_REG8_BIT(  TAA3CTL1,        0xFFFFFB01,  __READ_WRITE )
+__IO_REG8_BIT(  TAA3IOC0,        0xFFFFFB02,  __READ_WRITE )
+__IO_REG8_BIT(  TAA3IOC1,        0xFFFFFB03,  __READ_WRITE )
+__IO_REG8_BIT(  TAA3IOC2,        0xFFFFFB04,  __READ_WRITE )
+__IO_REG8_BIT(  TAA3OPT0,        0xFFFFFB05,  __READ_WRITE )
+__IO_REG16(     TAA3CCR0,        0xFFFFFB06,  __READ_WRITE )
+__IO_REG16(     TAA3CCR1,        0xFFFFFB08,  __READ_WRITE )
+__IO_REG16(     TAA3CNT,         0xFFFFFB0A,  __READ       )
+
+__IO_REG8_BIT(  TAA4CTL0,        0xFFFFFB20,  __READ_WRITE )
+__IO_REG8_BIT(  TAA4CTL1,        0xFFFFFB21,  __READ_WRITE )
+__IO_REG8_BIT(  TAA4IOC0,        0xFFFFFB22,  __READ_WRITE )
+__IO_REG8_BIT(  TAA4IOC1,        0xFFFFFB23,  __READ_WRITE )
+__IO_REG8_BIT(  TAA4IOC2,        0xFFFFFB24,  __READ_WRITE )
+__IO_REG8_BIT(  TAA4OPT0,        0xFFFFFB25,  __READ_WRITE )
+__IO_REG16(     TAA4CCR0,        0xFFFFFB26,  __READ_WRITE )
+__IO_REG16(     TAA4CCR1,        0xFFFFFB28,  __READ_WRITE )
+__IO_REG16(     TAA4CNT,         0xFFFFFB2A,  __READ       )
+
+__IO_REG8(      TANFC2,          0xFFFFFB40,  __READ_WRITE )
+__IO_REG8(      TANFC3,          0xFFFFFB42,  __READ_WRITE )
+__IO_REG8(      TANFC4,          0xFFFFFB44,  __READ_WRITE )
+
+__IO_REG8_BIT(  AD2M0,           0xFFFFFB80,  __READ_WRITE )
+__IO_REG8_BIT(  AD2M1,           0xFFFFFB81,  __READ_WRITE )
+__IO_REG8_BIT(  AD2S,            0xFFFFFB82,  __READ_WRITE )
+
+__IO_REG16(     AD2CR0,          0xFFFFFB90,  __READ       )
+__IO_REG8(      AD2CR0H,         0xFFFFFB91,  __READ       )
+__IO_REG16(     AD2CR1,          0xFFFFFB92,  __READ       )
+__IO_REG8(      AD2CR1H,         0xFFFFFB93,  __READ       )
+__IO_REG16(     AD2CR2,          0xFFFFFB94,  __READ       )
+__IO_REG8(      AD2CR2H,         0xFFFFFB95,  __READ       )
+__IO_REG16(     AD2CR3,          0xFFFFFB96,  __READ       )
+__IO_REG8(      AD2CR3H,         0xFFFFFB97,  __READ       )
+__IO_REG16(     AD2CR4,          0xFFFFFB98,  __READ       )
+__IO_REG8(      AD2CR4H,         0xFFFFFB99,  __READ       )
+__IO_REG16(     AD2CR5,          0xFFFFFB9A,  __READ       )
+__IO_REG8(      AD2CR5H,         0xFFFFFB9B,  __READ       )
+__IO_REG16(     AD2CR6,          0xFFFFFB9C,  __READ       )
+__IO_REG8(      AD2CR6H,         0xFFFFFB9D,  __READ       )
+__IO_REG16(     AD2CR7,          0xFFFFFB9E,  __READ       )
+__IO_REG8(      AD2CR7H,         0xFFFFFB9F,  __READ       )
+
+__IO_REG8_BIT(  P7,              0xFFFFFBB0,  __READ_WRITE )
+
+__IO_REG8_BIT(  PMC7,            0xFFFFFBB8,  __READ_WRITE )
+
+__IO_REG8_BIT(  INTF0,           0xFFFFFC00,  __READ_WRITE )
+__IO_REG8_BIT(  INTF1,           0xFFFFFC02,  __READ_WRITE )
+__IO_REG8_BIT(  INTF2,           0xFFFFFC04,  __READ_WRITE )
+
+__IO_REG8_BIT(  INTR0,           0xFFFFFC20,  __READ_WRITE )
+__IO_REG8_BIT(  INTR1,           0xFFFFFC22,  __READ_WRITE )
+__IO_REG8_BIT(  INTR2,           0xFFFFFC24,  __READ_WRITE )
+
+__IO_REG8_BIT(  PU0,             0xFFFFFC40,  __READ_WRITE )
+__IO_REG8_BIT(  PU1,             0xFFFFFC42,  __READ_WRITE )
+__IO_REG8_BIT(  PU2,             0xFFFFFC44,  __READ_WRITE )
+__IO_REG8_BIT(  PU3,             0xFFFFFC46,  __READ_WRITE )
+__IO_REG8_BIT(  PU4,             0xFFFFFC48,  __READ_WRITE )
+
+__IO_REG8_BIT(  PF3,             0xFFFFFC66,  __READ_WRITE )
+
+__IO_REG8_BIT(  CB0CTL0,         0xFFFFFD00,  __READ_WRITE )
+__IO_REG8_BIT(  CB0CTL1,         0xFFFFFD01,  __READ_WRITE )
+__IO_REG8(      CB0CTL2,         0xFFFFFD02,  __READ_WRITE )
+__IO_REG8_BIT(  CB0STR,          0xFFFFFD03,  __READ_WRITE )
+__IO_REG16(     CB0RX,           0xFFFFFD04,  __READ       )
+__IO_REG8(      CB0RXL,          0xFFFFFD04,  __READ       )
+__IO_REG16(     CB0TX,           0xFFFFFD06,  __READ_WRITE )
+__IO_REG8(      CB0TXL,          0xFFFFFD06,  __READ_WRITE )
+
+__IO_REG8_BIT(  CB1CTL0,         0xFFFFFD10,  __READ_WRITE )
+__IO_REG8_BIT(  CB1CTL1,         0xFFFFFD11,  __READ_WRITE )
+__IO_REG8(      CB1CTL2,         0xFFFFFD12,  __READ_WRITE )
+__IO_REG8_BIT(  CB1STR,          0xFFFFFD13,  __READ_WRITE )
+__IO_REG16(     CB1RX,           0xFFFFFD14,  __READ       )
+__IO_REG8(      CB1RXL,          0xFFFFFD14,  __READ       )
+__IO_REG16(     CB1TX,           0xFFFFFD16,  __READ_WRITE )
+__IO_REG8(      CB1TXL,          0xFFFFFD16,  __READ_WRITE )
+
+__IO_REG8_BIT(  CB2CTL0,         0xFFFFFD20,  __READ_WRITE )
+__IO_REG8_BIT(  CB2CTL1,         0xFFFFFD21,  __READ_WRITE )
+__IO_REG8(      CB2CTL2,         0xFFFFFD22,  __READ_WRITE )
+__IO_REG8_BIT(  CB2STR,          0xFFFFFD23,  __READ_WRITE )
+__IO_REG16(     CB2RX,           0xFFFFFD24,  __READ       )
+__IO_REG8(      CB2RXL,          0xFFFFFD24,  __READ       )
+__IO_REG16(     CB2TX,           0xFFFFFD26,  __READ_WRITE )
+__IO_REG8(      CB2TXL,          0xFFFFFD26,  __READ_WRITE )
+
+__IO_REG8(      IIC0,            0xFFFFFD80,  __READ_WRITE )
+__IO_REG8_BIT(  IICC0,           0xFFFFFD82,  __READ_WRITE )
+__IO_REG8(      SVA0,            0xFFFFFD83,  __READ_WRITE )
+__IO_REG8_BIT(  IICCL0,          0xFFFFFD84,  __READ_WRITE )
+__IO_REG8_BIT(  IICX0,           0xFFFFFD85,  __READ_WRITE )
+__IO_REG8_BIT(  IICS0,           0xFFFFFD86,  __READ       )
+
+__IO_REG8_BIT(  IICF0,           0xFFFFFD8A,  __READ_WRITE )
+
+__IO_REG8(      IICOCKS,         0xFFFFFD90,  __READ_WRITE )
+
+__IO_REG16(     PUDL,            0xFFFFFF44,  __READ_WRITE )
+__IO_REG8_BIT(  PUDLL,           0xFFFFFF44,  __READ_WRITE )
+__IO_REG8_BIT(  PUDLH,           0xFFFFFF45,  __READ_WRITE )
+
+/***********************************************
+ *       Peripheral I/O bit declarations
+ ***********************************************/
+
+#ifdef __IAR_SYSTEMS_ICC__
+
+#define E00               DCHC0_bit.no0
+#define STG0              DCHC0_bit.no1
+#define INIT0             DCHC0_bit.no2
+#define MLE0              DCHC0_bit.no3
+#define TC0               DCHC0_bit.no7
+
+#define E11               DCHC1_bit.no0
+#define STG1              DCHC1_bit.no1
+#define INIT1             DCHC1_bit.no2
+#define MLE1              DCHC1_bit.no3
+#define TC1               DCHC1_bit.no7
+
+#define E22               DCHC2_bit.no0
+#define STG2              DCHC2_bit.no1
+#define INIT2             DCHC2_bit.no2
+#define MLE2              DCHC2_bit.no3
+#define TC2               DCHC2_bit.no7
+
+#define E33               DCHC3_bit.no0
+#define STG3              DCHC3_bit.no1
+#define INIT3             DCHC3_bit.no2
+#define MLE3              DCHC3_bit.no3
+#define TC3               DCHC3_bit.no7
+
+#define LVILMK            LVILIC_bit.no6
+#define LVILIF            LVILIC_bit.no7
+
+#define LVIHMK            LVIHIC_bit.no6
+#define LVIHIF            LVIHIC_bit.no7
+
+#define PMK00             PIC00_bit.no6
+#define PIF00             PIC00_bit.no7
+
+#define PMK01             PIC01_bit.no6
+#define PIF01             PIC01_bit.no7
+
+#define PMK02             PIC02_bit.no6
+#define PIF02             PIC02_bit.no7
+
+#define PMK03             PIC03_bit.no6
+#define PIF03             PIC03_bit.no7
+
+#define PMK04             PIC04_bit.no6
+#define PIF04             PIC04_bit.no7
+
+#define PMK05             PIC05_bit.no6
+#define PIF05             PIC05_bit.no7
+
+#define PMK06             PIC06_bit.no6
+#define PIF06             PIC06_bit.no7
+
+#define PMK07             PIC07_bit.no6
+#define PIF07             PIC07_bit.no7
+
+#define PMK08             PIC08_bit.no6
+#define PIF08             PIC08_bit.no7
+
+#define PMK09             PIC09_bit.no6
+#define PIF09             PIC09_bit.no7
+
+#define PMK10             PIC10_bit.no6
+#define PIF10             PIC10_bit.no7
+
+#define PMK11             PIC11_bit.no6
+#define PIF11             PIC11_bit.no7
+
+#define PMK12             PIC12_bit.no6
+#define PIF12             PIC12_bit.no7
+
+#define PMK13             PIC13_bit.no6
+#define PIF13             PIC13_bit.no7
+
+#define PMK14             PIC14_bit.no6
+#define PIF14             PIC14_bit.no7
+
+#define PMK15             PIC15_bit.no6
+#define PIF15             PIC15_bit.no7
+
+#define PMK16             PIC16_bit.no6
+#define PIF16             PIC16_bit.no7
+
+#define PMK17             PIC17_bit.no6
+#define PIF17             PIC17_bit.no7
+
+#define PMK18             PIC18_bit.no6
+#define PIF18             PIC18_bit.no7
+
+#define CMPMK0L           CMPIC0L_bit.no6
+#define CMPIF0L           CMPIC0L_bit.no7
+
+#define CMPMK0F           CMPIC0F_bit.no6
+#define CMPIF0F           CMPIC0F_bit.no7
+
+#define CMPMK1L           CMPIC1L_bit.no6
+#define CMPIF1L           CMPIC1L_bit.no7
+
+#define CMPMK1F           CMPIC1F_bit.no6
+#define CMPIF1F           CMPIC1F_bit.no7
+
+#define TB0OVMK           TB0OVIC_bit.no6
+#define TB0OVIF           TB0OVIC_bit.no7
+
+#define TB0CCMK0          TB0CCIC0_bit.no6
+#define TB0CCIF0          TB0CCIC0_bit.no7
+
+#define TB0CCMK1          TB0CCIC1_bit.no6
+#define TB0CCIF1          TB0CCIC1_bit.no7
+
+#define TB0CCMK2          TB0CCIC2_bit.no6
+#define TB0CCIF2          TB0CCIC2_bit.no7
+
+#define TB0CCMK3          TB0CCIC3_bit.no6
+#define TB0CCIF3          TB0CCIC3_bit.no7
+
+#define TB1OVMK           TB1OVIC_bit.no6
+#define TB1OVIF           TB1OVIC_bit.no7
+
+#define TB1CCMK0          TB1CCIC0_bit.no6
+#define TB1CCIF0          TB1CCIC0_bit.no7
+
+#define TB1CCMK1          TB1CCIC1_bit.no6
+#define TB1CCIF1          TB1CCIC1_bit.no7
+
+#define TB1CCMK2          TB1CCIC2_bit.no6
+#define TB1CCIF2          TB1CCIC2_bit.no7
+
+#define TB1CCMK3          TB1CCIC3_bit.no6
+#define TB1CCIF3          TB1CCIC3_bit.no7
+
+#define TT0OVMK           TT0OVIC_bit.no6
+#define TT0OVIF           TT0OVIC_bit.no7
+
+#define TT0CCMK0          TT0CCIC0_bit.no6
+#define TT0CCIF0          TT0CCIC0_bit.no7
+
+#define TT0CCMK1          TT0CCIC1_bit.no6
+#define TT0CCIF1          TT0CCIC1_bit.no7
+
+#define TT0IECMK          TT0IECIC_bit.no6
+#define TT0IECIF          TT0IECIC_bit.no7
+
+#define TT1OVMK           TT1OVIC_bit.no6
+#define TT1OVIF           TT1OVIC_bit.no7
+
+#define TT1CCMK0          TT1CCIC0_bit.no6
+#define TT1CCIF0          TT1CCIC0_bit.no7
+
+#define TT1CCMK1          TT1CCIC1_bit.no6
+#define TT1CCIF1          TT1CCIC1_bit.no7
+
+#define TT1IECMK          TT1IECIC_bit.no6
+#define TT1IECIF          TT1IECIC_bit.no7
+
+#define TA0OVMK           TA0OVIC_bit.no6
+#define TA0OVIF           TA0OVIC_bit.no7
+
+#define TA0CCMK0          TA0CCIC0_bit.no6
+#define TA0CCIF0          TA0CCIC0_bit.no7
+
+#define TA0CCMK1          TA0CCIC1_bit.no6
+#define TA0CCIF1          TA0CCIC1_bit.no7
+
+#define TA1OVMK           TA1OVIC_bit.no6
+#define TA1OVIF           TA1OVIC_bit.no7
+
+#define TA1CCMK0          TA1CCIC0_bit.no6
+#define TA1CCIF0          TA1CCIC0_bit.no7
+
+#define TA1CCMK1          TA1CCIC1_bit.no6
+#define TA1CCIF1          TA1CCIC1_bit.no7
+
+#define TA2OVMK           TA2OVIC_bit.no6
+#define TA2OVIF           TA2OVIC_bit.no7
+
+#define TA2CCMK0          TA2CCIC0_bit.no6
+#define TA2CCIF0          TA2CCIC0_bit.no7
+
+#define TA2CCMK1          TA2CCIC1_bit.no6
+#define TA2CCIF1          TA2CCIC1_bit.no7
+
+#define TA3OVMK           TA3OVIC_bit.no6
+#define TA3OVIF           TA3OVIC_bit.no7
+
+#define TA3CCMK0          TA3CCIC0_bit.no6
+#define TA3CCIF0          TA3CCIC0_bit.no7
+
+#define TA3CCMK1          TA3CCIC1_bit.no6
+#define TA3CCIF1          TA3CCIC1_bit.no7
+
+#define TA4OVMK           TA4OVIC_bit.no6
+#define TA4OVIF           TA4OVIC_bit.no7
+
+#define TA4CCMK0          TA4CCIC0_bit.no6
+#define TA4CCIF0          TA4CCIC0_bit.no7
+
+#define TA4CCMK1          TA4CCIC1_bit.no6
+#define TA4CCIF1          TA4CCIC1_bit.no7
+
+#define DMAMK0            DMAIC0_bit.no6
+#define DMAIF0            DMAIC0_bit.no7
+
+#define DMAMK1            DMAIC1_bit.no6
+#define DMAIF1            DMAIC1_bit.no7
+
+#define DMAMK2            DMAIC2_bit.no6
+#define DMAIF2            DMAIC2_bit.no7
+
+#define DMAMK3            DMAIC3_bit.no6
+#define DMAIF3            DMAIC3_bit.no7
+
+#define UREMK             UREIC_bit.no6
+#define UREIF             UREIC_bit.no7
+
+#define URMK              URIC_bit.no6
+#define URIF              URIC_bit.no7
+
+#define UTMK              UTIC_bit.no6
+#define UTIF              UTIC_bit.no7
+
+#define UIFMK             UIFIC_bit.no6
+#define UIFIF             UIFIC_bit.no7
+
+#define UTOMK             UTOIC_bit.no6
+#define UTOIF             UTOIC_bit.no7
+
+#define UA0REMK           UA0REIC_bit.no6
+#define UA0REIF           UA0REIC_bit.no7
+
+#define UA0RMK            UA0RIC_bit.no6
+#define UA0RIF            UA0RIC_bit.no7
+
+#define UA0TMK            UA0TIC_bit.no6
+#define UA0TIF            UA0TIC_bit.no7
+
+#define CB0REMK           CB0REIC_bit.no6
+#define CB0REIF           CB0REIC_bit.no7
+
+#define CB0RMK            CB0RIC_bit.no6
+#define CB0RIF            CB0RIC_bit.no7
+
+#define CB0TMK            CB0TIC_bit.no6
+#define CB0TIF            CB0TIC_bit.no7
+
+#define UA1REMK           UA1REIC_bit.no6
+#define UA1REIF           UA1REIC_bit.no7
+
+#define UA1RMK            UA1RIC_bit.no6
+#define UA1RIF            UA1RIC_bit.no7
+
+#define UA1TMK            UA1TIC_bit.no6
+#define UA1TIF            UA1TIC_bit.no7
+
+#define CB1REMK           CB1REIC_bit.no6
+#define CB1REIF           CB1REIC_bit.no7
+
+#define CB1RMK            CB1RIC_bit.no6
+#define CB1RIF            CB1RIC_bit.no7
+
+#define CB1TMK            CB1TIC_bit.no6
+#define CB1TIF            CB1TIC_bit.no7
+
+#define UA2REMK           UA2REIC_bit.no6
+#define UA2REIF           UA2REIC_bit.no7
+
+#define UA2RMK            UA2RIC_bit.no6
+#define UA2RIF            UA2RIC_bit.no7
+
+#define UA2TMK            UA2TIC_bit.no6
+#define UA2TIF            UA2TIC_bit.no7
+
+#define CB2REMK           CB2REIC_bit.no6
+#define CB2REIF           CB2REIC_bit.no7
+
+#define CB2RMK            CB2RIC_bit.no6
+#define CB2RIF            CB2RIC_bit.no7
+
+#define CB2TMK            CB2TIC_bit.no6
+#define CB2TIF            CB2TIC_bit.no7
+
+#define IICMK             IICIC_bit.no6
+#define IICIF             IICIC_bit.no7
+
+#define AD0MK             AD0IC_bit.no6
+#define AD0IF             AD0IC_bit.no7
+
+#define AD1MK             AD1IC_bit.no6
+#define AD1IF             AD1IC_bit.no7
+
+#define AD2MK             AD2IC_bit.no6
+#define AD2IF             AD2IC_bit.no7
+
+#define TM0EQMK0          TM0EQIC0_bit.no6
+#define TM0EQIF0          TM0EQIC0_bit.no7
+
+#define TM1EQMK0          TM1EQIC0_bit.no6
+#define TM1EQIF0          TM1EQIC0_bit.no7
+
+#define TM2EQMK0          TM2EQIC0_bit.no6
+#define TM2EQIF0          TM2EQIC0_bit.no7
+
+#define TM3EQMK0          TM3EQIC0_bit.no6
+#define TM3EQIF0          TM3EQIC0_bit.no7
+
+#define ADT0MK            ADT0IC_bit.no6
+#define ADT0IF            ADT0IC_bit.no7
+
+#define ADT1MK            ADT1IC_bit.no6
+#define ADT1IF            ADT1IC_bit.no7
+
+#define ISPR0             ISPR_bit.no0
+#define ISPR1             ISPR_bit.no1
+#define ISPR2             ISPR_bit.no2
+#define ISPR3             ISPR_bit.no3
+#define ISPR4             ISPR_bit.no4
+#define ISPR5             ISPR_bit.no5
+#define ISPR6             ISPR_bit.no6
+#define ISPR7             ISPR_bit.no7
+
+#define STB               PSC_bit.no1
+#define INTM              PSC_bit.no4
+#define NMI0M             PSC_bit.no5
+
+#define AD0CE             AD0SCMH_bit.no7
+
+#define AD1CE             AD1SCMH_bit.no7
+
+#define TM0CE             TM0CTL0_bit.no7
+
+#define TM1CE             TM1CTL0_bit.no7
+
+#define TM2CE             TM2CTL0_bit.no7
+
+#define TM3CE             TM3CTL0_bit.no7
+
+#define TT0CE             TT0CTL0_bit.no7
+
+#define TT0OE0            TT0IOC0_bit.no0
+#define TT0OE1            TT0IOC0_bit.no2
+
+#define TT0OVF            TT0OPT0_bit.no0
+
+#define TT0ESF            TT0OPT1_bit.no0
+#define TT0EOF            TT0OPT1_bit.no1
+#define TT0EUF            TT0OPT1_bit.no2
+
+#define TT1CE             TT1CTL0_bit.no7
+
+#define TT1OE0            TT1IOC0_bit.no0
+#define TT1OE1            TT1IOC0_bit.no2
+
+#define TT1OVF            TT1OPT0_bit.no0
+
+#define TT1ESF            TT1OPT1_bit.no0
+#define TT1EOF            TT1OPT1_bit.no1
+#define TT1EUF            TT1OPT1_bit.no2
+
+#define TAB0CE            TAB0CTL0_bit.no7
+
+#define TAB0OE0           TAB0IOC0_bit.no0
+#define TAB0OE1           TAB0IOC0_bit.no2
+#define TAB0OE2           TAB0IOC0_bit.no4
+#define TAB0OE3           TAB0IOC0_bit.no6
+
+#define TAB0OVF           TAB0OPT0_bit.no0
+#define TAB0CUF           TAB0OPT0_bit.no1
+#define TAB0CMS           TAB0OPT0_bit.no2
+#define TAB0CCS0          TAB0OPT0_bit.no4
+#define TAB0CCS1          TAB0OPT0_bit.no5
+#define TAB0CCS2          TAB0OPT0_bit.no6
+#define TAB0CCS3          TAB0OPT0_bit.no7
+
+#define TAB0IOE           TAB0OPT1_bit.no6
+#define TAB0ICE           TAB0OPT1_bit.no7
+
+#define TAB0AT0           TAB0OPT2_bit.no0
+#define TAB0AT1           TAB0OPT2_bit.no1
+#define TAB0AT2           TAB0OPT2_bit.no2
+#define TAB0AT3           TAB0OPT2_bit.no3
+#define TAB0ATM2          TAB0OPT2_bit.no4
+#define TAB0ATM3          TAB0OPT2_bit.no5
+#define TAB0DTM           TAB0OPT2_bit.no6
+#define TAB0RDE           TAB0OPT2_bit.no7
+
+#define TAB0OEB1          TAB0IOC3_bit.no2
+#define TAB0OLB1          TAB0IOC3_bit.no3
+#define TAB0OEB2          TAB0IOC3_bit.no4
+#define TAB0OLB2          TAB0IOC3_bit.no5
+#define TAB0OEB3          TAB0IOC3_bit.no6
+#define TAB0OLB3          TAB0IOC3_bit.no7
+
+#define TAB0AT4           TAB0OPT3_bit.no0
+#define TAB0AT5           TAB0OPT3_bit.no1
+#define TAB0AT6           TAB0OPT3_bit.no2
+#define TAB0AT7           TAB0OPT3_bit.no3
+#define TAB0ATM6          TAB0OPT3_bit.no4
+#define TAB0ATM7          TAB0OPT3_bit.no5
+
+#define HZA0DCF0          HZA0CTL0_bit.no0
+#define HZA0DCC0          HZA0CTL0_bit.no2
+#define HZA0DCT0          HZA0CTL0_bit.no3
+#define HZA0DCM0          HZA0CTL0_bit.no6
+#define HZA0DCE0          HZA0CTL0_bit.no7
+
+#define HZA0DCF1          HZA0CTL1_bit.no0
+#define HZA0DCC1          HZA0CTL1_bit.no2
+#define HZA0DCT1          HZA0CTL1_bit.no3
+#define HZA0DCM1          HZA0CTL1_bit.no6
+#define HZA0DCE1          HZA0CTL1_bit.no7
+
+#define HZA1DCF0          HZA1CTL0_bit.no0
+#define HZA1DCC0          HZA1CTL0_bit.no2
+#define HZA1DCT0          HZA1CTL0_bit.no3
+#define HZA1DCM0          HZA1CTL0_bit.no6
+#define HZA1DCE0          HZA1CTL0_bit.no7
+
+#define HZA1DCF1          HZA1CTL1_bit.no0
+#define HZA1DCC1          HZA1CTL1_bit.no2
+#define HZA1DCT1          HZA1CTL1_bit.no3
+#define HZA1DCM1          HZA1CTL1_bit.no6
+#define HZA1DCE1          HZA1CTL1_bit.no7
+
+#define TAB1CE            TAB1CTL0_bit.no7
+
+#define TAB1OE0           TAB1IOC0_bit.no0
+#define TAB1OE1           TAB1IOC0_bit.no2
+#define TAB1OE2           TAB1IOC0_bit.no4
+#define TAB1OE3           TAB1IOC0_bit.no6
+
+#define TAB1OVF           TAB1OPT0_bit.no0
+#define TAB1CUF           TAB1OPT0_bit.no1
+#define TAB1CMS           TAB1OPT0_bit.no2
+#define TAB1CCS0          TAB1OPT0_bit.no4
+#define TAB1CCS1          TAB1OPT0_bit.no5
+#define TAB1CCS2          TAB1OPT0_bit.no6
+#define TAB1CCS3          TAB1OPT0_bit.no7
+
+#define TAB1IOE           TAB1OPT1_bit.no6
+#define TAB1ICE           TAB1OPT1_bit.no7
+
+#define TAB1AT0           TAB1OPT2_bit.no0
+#define TAB1AT1           TAB1OPT2_bit.no1
+#define TAB1AT2           TAB1OPT2_bit.no2
+#define TAB1AT3           TAB1OPT2_bit.no3
+#define TAB1ATM2          TAB1OPT2_bit.no4
+#define TAB1ATM3          TAB1OPT2_bit.no5
+#define TAB1DTM           TAB1OPT2_bit.no6
+#define TAB1RDE           TAB1OPT2_bit.no7
+
+#define TAB1OEB1          TAB1IOC3_bit.no2
+#define TAB1OLB1          TAB1IOC3_bit.no3
+#define TAB1OEB2          TAB1IOC3_bit.no4
+#define TAB1OLB2          TAB1IOC3_bit.no5
+#define TAB1OEB3          TAB1IOC3_bit.no6
+#define TAB1OLB3          TAB1IOC3_bit.no7
+
+#define TAB1AT4           TAB1OPT3_bit.no0
+#define TAB1AT5           TAB1OPT3_bit.no1
+#define TAB1AT6           TAB1OPT3_bit.no2
+#define TAB1AT7           TAB1OPT3_bit.no3
+#define TAB1ATM6          TAB1OPT3_bit.no4
+#define TAB1ATM7          TAB1OPT3_bit.no5
+
+#define HZA2DCF0          HZA2CTL0_bit.no0
+#define HZA2DCC0          HZA2CTL0_bit.no2
+#define HZA2DCT0          HZA2CTL0_bit.no3
+#define HZA2DCM0          HZA2CTL0_bit.no6
+#define HZA2DCE0          HZA2CTL0_bit.no7
+
+#define HZA2DCF1          HZA2CTL1_bit.no0
+#define HZA2DCC1          HZA2CTL1_bit.no2
+#define HZA2DCT1          HZA2CTL1_bit.no3
+#define HZA2DCM1          HZA2CTL1_bit.no6
+#define HZA2DCE1          HZA2CTL1_bit.no7
+
+#define HZA3DCF0          HZA3CTL0_bit.no0
+#define HZA3DCC0          HZA3CTL0_bit.no2
+#define HZA3DCT0          HZA3CTL0_bit.no3
+#define HZA3DCM0          HZA3CTL0_bit.no6
+#define HZA3DCE0          HZA3CTL0_bit.no7
+
+#define HZA3DCF1          HZA3CTL1_bit.no0
+#define HZA3DCC1          HZA3CTL1_bit.no2
+#define HZA3DCT1          HZA3CTL1_bit.no3
+#define HZA3DCM1          HZA3CTL1_bit.no6
+#define HZA3DCE1          HZA3CTL1_bit.no7
+
+#define TAA0CE            TAA0CTL0_bit.no7
+
+#define TAA0OVF           TAA0OPT0_bit.no0
+
+#define TAA1CE            TAA1CTL0_bit.no7
+
+#define TAA1OVF           TAA1OPT0_bit.no0
+
+#define TAA2CE            TAA2CTL0_bit.no7
+
+#define TAA2OE0           TAA2IOC0_bit.no0
+#define TAA2OE1           TAA2IOC0_bit.no2
+
+#define TAA2OVF           TAA2OPT0_bit.no0
+
+#define PRERR             SYS_bit.no0
+
+#define DF0               DTFR0_bit.no7
+
+#define DF1               DTFR1_bit.no7
+
+#define DF2               DTFR2_bit.no7
+
+#define DF3               DTFR3_bit.no7
+
+#define PSM0              PSMR_bit.no0
+
+#define PLLON             PLLCTL_bit.no0
+#define SELPLL            PLLCTL_bit.no1
+
+#define LVIF              LVIM_bit.no0
+#define LVIMD             LVIM_bit.no1
+#define LVION             LVIM_bit.no7
+
+#define UA0DIR            UA0CTL0_bit.no4
+#define UA0RXE            UA0CTL0_bit.no5
+#define UA0TXE            UA0CTL0_bit.no6
+#define UA0PWR            UA0CTL0_bit.no7
+
+#define UA0OVE            UA0STR_bit.no0
+#define UA0FE             UA0STR_bit.no1
+#define UA0PE             UA0STR_bit.no2
+#define UA0TSF            UA0STR_bit.no7
+
+#define UA1DIR            UA1CTL0_bit.no4
+#define UA1RXE            UA1CTL0_bit.no5
+#define UA1TXE            UA1CTL0_bit.no6
+#define UA1PWR            UA1CTL0_bit.no7
+
+#define UA1OVE            UA1STR_bit.no0
+#define UA1FE             UA1STR_bit.no1
+#define UA1PE             UA1STR_bit.no2
+#define UA1TSF            UA1STR_bit.no7
+
+#define UA2DIR            UA2CTL0_bit.no4
+#define UA2RXE            UA2CTL0_bit.no5
+#define UA2TXE            UA2CTL0_bit.no6
+#define UA2PWR            UA2CTL0_bit.no7
+
+#define UA2OVE            UA2STR_bit.no0
+#define UA2FE             UA2STR_bit.no1
+#define UA2PE             UA2STR_bit.no2
+#define UA2TSF            UA2STR_bit.no7
+
+#define UBDIR             UBCTL0_bit.no4
+#define UBRXE             UBCTL0_bit.no5
+#define UBTXE             UBCTL0_bit.no6
+#define UBPWR             UBCTL0_bit.no7
+
+#define UBOVE             UBSTR_bit.no0
+#define UBFE              UBSTR_bit.no1
+#define UBPE              UBSTR_bit.no2
+#define UBTSF             UBSTR_bit.no7
+
+#define TAA3CE            TAA3CTL0_bit.no7
+
+#define TAA3OE0           TAA3IOC0_bit.no0
+#define TAA3OE1           TAA3IOC0_bit.no2
+
+#define TAA3OVF           TAA3OPT0_bit.no0
+
+#define TAA4CE            TAA4CTL0_bit.no7
+
+#define TAA4OE0           TAA4IOC0_bit.no0
+#define TAA4OE1           TAA4IOC0_bit.no2
+
+#define TAA4OVF           TAA4OPT0_bit.no0
+
+#define AD2CE             AD2M0_bit.no7
+
+#define INTF00            INTF0_bit.no0
+#define INTF01            INTF0_bit.no1
+#define INTF02            INTF0_bit.no2
+#define INTF03            INTF0_bit.no3
+#define INTF04            INTF0_bit.no4
+#define INTF05            INTF0_bit.no5
+#define INTF06            INTF0_bit.no6
+#define INTF07            INTF0_bit.no7
+
+#define INTF08            INTF1_bit.no0
+#define INTF09            INTF1_bit.no1
+#define INTF10            INTF1_bit.no2
+#define INTF11            INTF1_bit.no3
+#define INTF12            INTF1_bit.no4
+#define INTF13            INTF1_bit.no5
+#define INTF17            INTF1_bit.no6
+#define INTF18            INTF1_bit.no7
+
+#define INTF14            INTF2_bit.no0
+#define INTF15            INTF2_bit.no1
+#define INTF16            INTF2_bit.no2
+
+#define INTR00            INTR0_bit.no0
+#define INTR01            INTR0_bit.no1
+#define INTR02            INTR0_bit.no2
+#define INTR03            INTR0_bit.no3
+#define INTR04            INTR0_bit.no4
+#define INTR05            INTR0_bit.no5
+#define INTR06            INTR0_bit.no6
+#define INTR07            INTR0_bit.no7
+
+#define INTR08            INTR1_bit.no0
+#define INTR09            INTR1_bit.no1
+#define INTR10            INTR1_bit.no2
+#define INTR11            INTR1_bit.no3
+#define INTR12            INTR1_bit.no4
+#define INTR13            INTR1_bit.no5
+#define INTR17            INTR1_bit.no6
+#define INTR18            INTR1_bit.no7
+
+#define INTR14            INTR2_bit.no0
+#define INTR15            INTR2_bit.no1
+#define INTR16            INTR2_bit.no2
+
+#define CB0SCE            CB0CTL0_bit.no0
+#define CB0DIR            CB0CTL0_bit.no4
+#define CB0RXE            CB0CTL0_bit.no5
+#define CB0TXE            CB0CTL0_bit.no6
+#define CB0PWR            CB0CTL0_bit.no7
+
+#define CB0OVE            CB0STR_bit.no0
+#define CB0TSF            CB0STR_bit.no7
+
+#define CB1SCE            CB1CTL0_bit.no0
+#define CB1DIR            CB1CTL0_bit.no4
+#define CB1RXE            CB1CTL0_bit.no5
+#define CB1TXE            CB1CTL0_bit.no6
+#define CB1PWR            CB1CTL0_bit.no7
+
+#define CB1OVE            CB1STR_bit.no0
+#define CB1TSF            CB1STR_bit.no7
+
+#define CB2SCE            CB2CTL0_bit.no0
+#define CB2DIR            CB2CTL0_bit.no4
+#define CB2RXE            CB2CTL0_bit.no5
+#define CB2TXE            CB2CTL0_bit.no6
+#define CB2PWR            CB2CTL0_bit.no7
+
+#define CB2OVE            CB2STR_bit.no0
+#define CB2TSF            CB2STR_bit.no7
+
+#define SPT0              IICC0_bit.no0
+#define STT0              IICC0_bit.no1
+#define ACKE0             IICC0_bit.no2
+#define WTIM0             IICC0_bit.no3
+#define SPIE0             IICC0_bit.no4
+#define WREL0             IICC0_bit.no5
+#define LREL0             IICC0_bit.no6
+#define IICE0             IICC0_bit.no7
+
+#define DAD0              IICCL0_bit.no4
+#define CLD0              IICCL0_bit.no5
+
+#define CLX0              IICX0_bit.no0
+
+#define SPD0              IICS0_bit.no0
+#define STD0              IICS0_bit.no1
+#define ACKD0             IICS0_bit.no2
+#define TRC0              IICS0_bit.no3
+#define COI0              IICS0_bit.no4
+#define EXC0              IICS0_bit.no5
+#define ALD0              IICS0_bit.no6
+#define MSTS0             IICS0_bit.no7
+
+#define IICRSV0           IICF0_bit.no0
+#define STCEN0            IICF0_bit.no1
+#define IICBSY0           IICF0_bit.no6
+#define STCF0             IICF0_bit.no7
+
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+/***********************************************
+ *       Interrupt/Exeption table declarations
+ ***********************************************/
+
+#define RESET_vector             (0x0000)
+#define INTWDT_vector            (0x0010)
+#define DBG0_vector              (0x0060)
+#define ILGOP_vector             (0x0060)
+#define SECURITY_ID_vector       (0x0070)
+#define INTLVIL_vector           (0x0080)
+#define INTLVIH_vector           (0x0090)
+#define INTP00_vector            (0x00A0)
+#define INTP01_vector            (0x00B0)
+#define INTP02_vector            (0x00C0)
+#define INTP03_vector            (0x00D0)
+#define INTP04_vector            (0x00E0)
+#define INTP05_vector            (0x00F0)
+#define INTP06_vector            (0x0100)
+#define INTP07_vector            (0x0110)
+#define INTP08_vector            (0x0120)
+#define INTP09_vector            (0x0130)
+#define INTP10_vector            (0x0140)
+#define INTP11_vector            (0x0150)
+#define INTP12_vector            (0x0160)
+#define INTP13_vector            (0x0170)
+#define INTP14_vector            (0x0180)
+#define INTP15_vector            (0x0190)
+#define INTP16_vector            (0x01A0)
+#define INTP17_vector            (0x01B0)
+#define INTP18_vector            (0x01C0)
+#define INTCMP0L_vector          (0x01D0)
+#define INTCMP0F_vector          (0x01E0)
+#define INTCMP1L_vector          (0x01F0)
+#define INTCMP1F_vector          (0x0200)
+#define INTTB0OV_vector          (0x0210)
+#define INTTB0CC0_vector         (0x0220)
+#define INTTB0CC1_vector         (0x0230)
+#define INTTB0CC2_vector         (0x0240)
+#define INTTB0CC3_vector         (0x0250)
+#define INTTB1OV_vector          (0x0260)
+#define INTTB1CC0_vector         (0x0270)
+#define INTTB1CC1_vector         (0x0280)
+#define INTTB1CC2_vector         (0x0290)
+#define INTTB1CC3_vector         (0x02A0)
+#define INTTTIOV0_vector         (0x02B0)
+#define INTTTEQC00_vector        (0x02C0)
+#define INTTTEQC01_vector        (0x02D0)
+#define INTTIEC0_vector          (0x02E0)
+#define INTTTIOV1_vector         (0x02F0)
+#define INTTTEQC10_vector        (0x0300)
+#define INTTTEQC11_vector        (0x0310)
+#define INTTIEC1_vector          (0x0320)
+#define INTTA0OV_vector          (0x0330)
+#define INTTA0CC0_vector         (0x0340)
+#define INTTA0CC1_vector         (0x0350)
+#define INTTA1OV_vector          (0x0360)
+#define INTTA1CC0_vector         (0x0370)
+#define INTTA1CC1_vector         (0x0380)
+#define INTTA2OV_vector          (0x0390)
+#define INTTA2CC0_vector         (0x03A0)
+#define INTTA2CC1_vector         (0x03B0)
+#define INTTA3OV_vector          (0x03C0)
+#define INTTA3CC0_vector         (0x03D0)
+#define INTTA3CC1_vector         (0x03E0)
+#define INTTA4OV_vector          (0x03F0)
+#define INTTA4CC0_vector         (0x0400)
+#define INTTA4CC1_vector         (0x0410)
+#define INTDMA0_vector           (0x0420)
+#define INTDMA1_vector           (0x0430)
+#define INTDMA2_vector           (0x0440)
+#define INTDMA3_vector           (0x0450)
+#define INTUBTIRE_vector         (0x0460)
+#define INTUBTIR_vector          (0x0470)
+#define INTUBTIT_vector          (0x0480)
+#define INTUBTIF_vector          (0x0490)
+#define INTUBTITO_vector         (0x04A0)
+#define INTUA0RE_vector          (0x04B0)
+#define INTUA0R_vector           (0x04C0)
+#define INTUA0T_vector           (0x04D0)
+#define INTCB0RE_vector          (0x04E0)
+#define INTCB0R_vector           (0x04F0)
+#define INTCB0T_vector           (0x0500)
+#define INTUA1RE_vector          (0x0510)
+#define INTUA1R_vector           (0x0520)
+#define INTUA1T_vector           (0x0530)
+#define INTCB1RE_vector          (0x0540)
+#define INTCB1R_vector           (0x0550)
+#define INTCB1T_vector           (0x0560)
+#define INTUA2RE_vector          (0x0570)
+#define INTUA2R_vector           (0x0580)
+#define INTUA2T_vector           (0x0590)
+#define INTCB2RE_vector          (0x05A0)
+#define INTCB2R_vector           (0x05B0)
+#define INTCB2T_vector           (0x05C0)
+#define INTIIC_vector            (0x05D0)
+#define INTAD0_vector            (0x05E0)
+#define INTAD1_vector            (0x05F0)
+#define INTAD2_vector            (0x0600)
+#define INTTM0EQ0_vector         (0x0610)
+#define INTTM1EQ0_vector         (0x0620)
+#define INTTM2EQ0_vector         (0x0630)
+#define INTTM3EQ0_vector         (0x0640)
+#define INTADT0_vector           (0x0650)
+#define INTADT1_vector           (0x0660)
+#define INTWARE_vector           (0x0790)
+#define INTWAR_vector            (0x07A0)
+#define INTWAT_vector            (0x07B0)
+#define INTECCER_vector          (0x07C0)
+
+/***********************************************
+ *       Trap vectors
+ ***********************************************/
+
+#define TRAP00_vector      (0x00)
+#define TRAP01_vector      (0x01)
+#define TRAP02_vector      (0x02)
+#define TRAP03_vector      (0x03)
+#define TRAP04_vector      (0x04)
+#define TRAP05_vector      (0x05)
+#define TRAP06_vector      (0x06)
+#define TRAP07_vector      (0x07)
+#define TRAP08_vector      (0x08)
+#define TRAP09_vector      (0x09)
+#define TRAP0A_vector      (0x0A)
+#define TRAP0B_vector      (0x0B)
+#define TRAP0C_vector      (0x0C)
+#define TRAP0D_vector      (0x0D)
+#define TRAP0E_vector      (0x0E)
+#define TRAP0F_vector      (0x0F)
+#define TRAP10_vector      (0x10)
+#define TRAP11_vector      (0x11)
+#define TRAP12_vector      (0x12)
+#define TRAP13_vector      (0x13)
+#define TRAP14_vector      (0x14)
+#define TRAP15_vector      (0x15)
+#define TRAP16_vector      (0x16)
+#define TRAP17_vector      (0x17)
+#define TRAP18_vector      (0x18)
+#define TRAP19_vector      (0x19)
+#define TRAP1A_vector      (0x1A)
+#define TRAP1B_vector      (0x1B)
+#define TRAP1C_vector      (0x1C)
+#define TRAP1D_vector      (0x1D)
+#define TRAP1E_vector      (0x1E)
+#define TRAP1F_vector      (0x1F)
+
+/***********************************************
+ *       Callt vectors
+ ***********************************************/
+
+#define CALLT00_vector     (0x00)
+#define CALLT01_vector     (0x01)
+#define CALLT02_vector     (0x02)
+#define CALLT03_vector     (0x03)
+#define CALLT04_vector     (0x04)
+#define CALLT05_vector     (0x05)
+#define CALLT06_vector     (0x06)
+#define CALLT07_vector     (0x07)
+#define CALLT08_vector     (0x08)
+#define CALLT09_vector     (0x09)
+#define CALLT0A_vector     (0x0A)
+#define CALLT0B_vector     (0x0B)
+#define CALLT0C_vector     (0x0C)
+#define CALLT0D_vector     (0x0D)
+#define CALLT0E_vector     (0x0E)
+#define CALLT0F_vector     (0x0F)
+#define CALLT10_vector     (0x10)
+#define CALLT11_vector     (0x11)
+#define CALLT12_vector     (0x12)
+#define CALLT13_vector     (0x13)
+#define CALLT14_vector     (0x14)
+#define CALLT15_vector     (0x15)
+#define CALLT16_vector     (0x16)
+#define CALLT17_vector     (0x17)
+#define CALLT18_vector     (0x18)
+#define CALLT19_vector     (0x19)
+#define CALLT1A_vector     (0x1A)
+#define CALLT1B_vector     (0x1B)
+#define CALLT1C_vector     (0x1C)
+#define CALLT1D_vector     (0x1D)
+#define CALLT1E_vector     (0x1E)
+#define CALLT1F_vector     (0x1F)
+#define CALLT20_vector     (0x20)
+#define CALLT21_vector     (0x21)
+#define CALLT22_vector     (0x22)
+#define CALLT23_vector     (0x23)
+#define CALLT24_vector     (0x24)
+#define CALLT25_vector     (0x25)
+#define CALLT26_vector     (0x26)
+#define CALLT27_vector     (0x27)
+#define CALLT28_vector     (0x28)
+#define CALLT29_vector     (0x29)
+#define CALLT2A_vector     (0x2A)
+#define CALLT2B_vector     (0x2B)
+#define CALLT2C_vector     (0x2C)
+#define CALLT2D_vector     (0x2D)
+#define CALLT2E_vector     (0x2E)
+#define CALLT2F_vector     (0x2F)
+#define CALLT30_vector     (0x30)
+#define CALLT31_vector     (0x31)
+#define CALLT32_vector     (0x32)
+#define CALLT33_vector     (0x33)
+#define CALLT34_vector     (0x34)
+#define CALLT35_vector     (0x35)
+#define CALLT36_vector     (0x36)
+#define CALLT37_vector     (0x37)
+#define CALLT38_vector     (0x38)
+#define CALLT39_vector     (0x39)
+#define CALLT3A_vector     (0x3A)
+#define CALLT3B_vector     (0x3B)
+#define CALLT3C_vector     (0x3C)
+#define CALLT3D_vector     (0x3D)
+#define CALLT3E_vector     (0x3E)
+#define CALLT3F_vector     (0x3F)
+
+#pragma language=default
+
+#endif /* __IO70F3454_H__ */

bsp/upd70f3454/lnk70f3454.xcl

@@ -0,0 +1,157 @@
+//-------------------------------------------------------------------------
+//      XLINK command file template for V850E microcontroller uPD70F3454.
+//
+//      This file can be used to link object files from the V850E
+//      Assembler, AV850, and the C/C++ compiler ICCV850.
+//
+//          This file is generated from the device file:
+//          DF3454.800
+//          Copyright (C) NEC Corporation 2007
+//          Format version 2.20, File version 1.00 
+//-------------------------------------------------------------------------
+
+//-------------------------------------------------------------------------
+//      The following segments are defined in this template link file:
+//
+//      INTVEC      -- Interrupt vectors.
+//      TRAPVEC     -- Trap vector.
+//      CLTVEC      -- Calltable vectors.
+//      CSTART      -- The C/C++ startup code.
+//      RCODE       -- Code used by C/C++ run-time library.
+//      ICODE       -- Code used by interrupt functions.
+//      CLTCODE     -- Code of calltable functions.
+//      CODE        -- Program code.
+//      DIFUNCT     -- Dynamic initialization vector used by C++
+//      CSTACK      -- The stack used by C/C++ programs.
+//      HEAP        -- The heap used for malloc and free
+//      SADDR7_x    -- Variables used by __saddr (128 byte offset).
+//      SADDR8_x    -- Variables used by __saddr (256 byte offset).
+//      NEAR_x      -- Variables used by __near (must be +- 32KB from address 0).
+//      BREL_x      -- Variables used by __brel.
+//      HUGE_x      -- Variables used by __huge.
+//
+//      Where _x could be one of:
+//
+//      _BASE   -- An empty placeholder segment that should be placed
+//                 in front of the other segments (SADDR and BREL).
+//      _CBASE  -- An empty placeholder segment that should be placed
+//                 in front of the other segments (BREL_C).
+//      _Z      -- Initialized data (initvalue = 0 or without init value).
+//      _I      -- Initialized data (initvalue != 0).
+//      _ID     -- The inial values of _I.
+//      _N      -- Uninitialized data, used by __no_init.
+//      _C      -- Constants.
+//
+//      NOTE:   Be sure to use end values for the defined addresses.
+//-------------------------------------------------------------------------
+
+//-------------------------------------------------------------------------
+//      Define CPU
+//-------------------------------------------------------------------------
+-cv850
+
+//-------------------------------------------------------------------------
+//      Size of the stack.
+//      Remove comment and modify number if used from command line.
+//-------------------------------------------------------------------------
+//-D_CSTACK_SIZE=400
+
+//-------------------------------------------------------------------------
+//      Size of the heap.
+//      Remove comment and modify number if used from command line.
+//-------------------------------------------------------------------------
+//-D_HEAP_SIZE=400
+
+//-------------------------------------------------------------------------
+//      Define the format functions used by printf/scanf.
+//      Default is full formatting.
+//      Remove appropriate comment(s) to get reduced formatting
+//      if used from command line.
+//-------------------------------------------------------------------------
+//-e_PrintfTiny=_Printf
+//-e_PrintfSmall=_Printf
+//-e_PrintfLarge=_Printf
+
+//-e_ScanfSmall=_Scanf
+//-e_ScanfLarge=_Scanf
+
+//-------------------------------------------------------------------------
+//      Define if row buffering should be used by terminal output.
+//      Default is no buffering.
+//      Remove comment to get buffered terminal output if used from command line.
+//-------------------------------------------------------------------------
+//-e__write_buffered=__write
+
+///////////////////////////////////////////////////////////////////////////
+//      Allocate the read only segments that are mapped to ROM.
+///////////////////////////////////////////////////////////////////////////
+
+-Z(CODE)INTVEC=00000000-000007CF
+-Z(CONST)SECUID=00000070-00000079
+
+//-------------------------------------------------------------------------
+//      BREL_CBASE is an empty placeholer segment, it should be placed in
+//      front of the BREL_C segments holding constant data.
+//-------------------------------------------------------------------------
+-Z(CONST)NEAR_C=000007D0-00007FFF
+-Z(CONST)BREL_CBASE,BREL_C=000007D0-0000FFFF
+-Z(CONST)HUGE_C=000007D0-0003FFFB
+-Z(CODE)CSTART,RCODE,ICODE,TRAPVEC,DIFUNCT=000007D0-0003FFFB
+-Z(CONST)SADDR7_ID,SADDR8_ID,NEAR_ID,BREL_ID,HUGE_ID=000007D0-0003FFFB
+-Z(CONST)CLTVEC=000007D0-0003FFFB
+
+-Z(CODE)CLTCODE,CODE=000007D0-0003FFFB
+
+//-------------------------------------------------------------------------
+//      The CHECKSUM segment must be defined when ROM checksum should
+//      be generated.
+//-------------------------------------------------------------------------
+-Z(CONST)CHECKSUM=0003FFFC-0003FFFF
+
+///////////////////////////////////////////////////////////////////////////
+//      Allocate the read/write segments that are mapped to RAM.
+///////////////////////////////////////////////////////////////////////////
+
+//-------------------------------------------------------------------------
+//      Short loads relative from EP with 7 and 8 bit offset.
+//
+//      SADDR_BASE is an empty segment that mark the beginning of the saddr
+//      data segments.
+//-------------------------------------------------------------------------
+-Z(DATA)SADDR_BASE=FFFFC000
+-Z(DATA)SADDR7_I,SADDR7_Z,SADDR7_N=FFFFC000-FFFFC07F
+-Z(DATA)SADDR8_I,SADDR8_Z,SADDR8_N=FFFFC000-FFFFC0FF
+
+//-------------------------------------------------------------------------
+//      16-bit access from GP.
+//      BREL_BASE is an empty placeholer segment, it should be placed in
+//      front of the DATA (i.e. RAM) BREL segments.
+//-------------------------------------------------------------------------
+-Z(DATA)BREL_BASE,BREL_I,BREL_Z,BREL_N=FFFFC000-FFFFEFFF
+
+//-------------------------------------------------------------------------
+//      Global and 32-bit offset from GP.
+//      The rest of the external memory (all external memory not used
+//      by BREL segment variables) is addressed with HUGE memory model.
+//-------------------------------------------------------------------------
+-Z(DATA)HUGE_I,HUGE_Z,HUGE_N=FFFFBFFC-FFFFBFFC  // No memory availabale
+
+//-------------------------------------------------------------------------
+//      Data relative from zero with 16 bit offset.
+//      This segment is for TINY data model. All internal memory, SFR,
+//      and CONST variables in area 0000-7FFF may be accessed.
+//-------------------------------------------------------------------------
+-Z(DATA)NEAR_Z,NEAR_I,NEAR_N=FFFFC000-FFFFEFFF
+
+//-------------------------------------------------------------------------
+//      The stack and the heap.
+//-------------------------------------------------------------------------
+-Z(DATA)CSTACK+_CSTACK_SIZE,HEAP+_HEAP_SIZE=FFFFC000-FFFFEFFF
+
+// Set up near RT_HEAP 
+//fify 20100505 HEAP for RTT
+-Z(DATA)RT_HEAP+400=FFFFC000-FFFFEFFF
+
+//-------------------------------------------------------------------------
+//      End of File
+//-------------------------------------------------------------------------

bsp/upd70f3454/rtconfig.h

@@ -0,0 +1,151 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX	8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+///#define SCHEDULER_DEBUG
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+///#define RT_USING_HOOK
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore */
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+/* RT_USING_UART */
+#define RT_USING_UART0
+#define RT_UART_RX_BUFFER_SIZE	64
+
+/* SECTION: Console options */
+/* the buffer size of console */
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: finsh, a C-Express shell */
+/* Using FinSH as Shell*/
+#define RT_USING_FINSH
+/* Using symbol table */
+///#define FINSH_USING_SYMTAB
+///#define FINSH_USING_DESCRIPTION
+
+/* SECTION: device filesystem support */
+/* #define RT_USING_DFS */
+///#define RT_USING_DFS_ELMFAT
+
+/* the max number of mounted filesystem */
+///#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+///#define DFS_FD_MAX					4
+/* the max number of cached sector 		*/
+///#define DFS_CACHE_MAX_NUM   		4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+//#define RT_USING_LWIP
+
+/* Enable ICMP protocol*/
+///#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+///#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+///#define RT_LWIP_TCP
+/* Enable DNS */
+///#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+///#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+///#define RT_LWIP_IPADDR0	192
+///#define RT_LWIP_IPADDR1	168
+///#define RT_LWIP_IPADDR2	1
+///#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+/* SECTION: RT-Thread/GUI */
+/* #define RT_USING_RTGUI */
+
+/* name length of RTGUI object */
+#define RTGUI_NAME_MAX		12
+/* support 16 weight font */
+#define RTGUI_USING_FONT16
+/* support Chinese font */
+#define RTGUI_USING_FONTHZ
+/* use DFS as file interface */
+#define RTGUI_USING_DFS_FILERW
+/* use font file as Chinese font */
+#define RTGUI_USING_HZ_FILE
+/* use small size in RTGUI */
+#define RTGUI_USING_SMALL_SIZE
+/* use mouse cursor */
+/* #define RTGUI_USING_MOUSE_CURSOR */
+/* default font size in RTGUI */
+#define RTGUI_DEFAULT_FONT_SIZE	16
+
+#endif

bsp/upd70f3454/settings/upd70f3454.cspy.bat

@@ -0,0 +1,33 @@
+@REM This bat file has been generated by the IAR Embeddded Workbench
+@REM C-SPY interactive debugger,as an aid to preparing a command
+@REM line for running the cspybat command line utility with the
+@REM appropriate settings.
+@REM
+@REM After making some adjustments to this file, you can launch cspybat
+@REM by typing the name of this file followed by the name of the debug
+@REM file (usually an ubrof file). Note that this file is generated
+@REM every time a new debug session is initialized, so you may want to
+@REM move or rename the file before making changes.
+@REM
+@REM Note: some command line arguments cannot be properly generated
+@REM by this process. Specifically, the plugin which is responsible
+@REM for the Terminal I/O window (and other C runtime functionality)
+@REM comes in a special version for cspybat, and the name of that
+@REM plugin dll is not known when generating this file. It resides in
+@REM the $TOOLKIT_DIR$\bin folder and is usually called XXXbat.dll or
+@REM XXXlibsupportbat.dll, where XXX is the name of the corresponding
+@REM tool chain. Replace the '<libsupport_plugin>' parameter
+@REM below with the appropriate file name. Other plugins loaded by
+@REM C-SPY are usually not needed by, or will not work in, cspybat
+@REM but they are listed at the end of this file for reference.
+
+
+"C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\bin\cspybat" "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\bin\v850proc.dll" "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\bin\v850minicube2.dll"  %1 --plugin "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\bin\<libsupport_plugin>" --backend -B "-v10" "-p" "C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\v850\CONFIG\DDF\io70f3454.ddf" "-d" "minicube2" 
+
+
+@REM Loaded plugins:
+@REM    v850LibSupport.dll
+@REM    C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\CodeCoverage\CodeCoverage.dll
+@REM    C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\Profiling\Profiling.dll
+@REM    C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\stack\stack.dll
+@REM    C:\Program Files\IAR Systems\Embedded Workbench 5.4 Evaluation\common\plugins\SymList\SymList.dll

bsp/upd70f3454/settings/upd70f3454.dbgdt

@@ -0,0 +1,84 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Project>
+  <Desktop>
+    <Static>
+      <Debug-Log>
+        
+        
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>1381</ColumnWidth1></Debug-Log>
+      <Build>
+        <ColumnWidth0>20</ColumnWidth0>
+        <ColumnWidth1>1035</ColumnWidth1>
+        <ColumnWidth2>276</ColumnWidth2>
+        <ColumnWidth3>69</ColumnWidth3>
+      </Build>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
+          
+        <Column0>191</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+      </Workspace>
+      <Disassembly>
+        <MixedMode>1</MixedMode>
+        <CodeCovShow>0</CodeCovShow>
+        <InstrProfShow>0</InstrProfShow>
+        <PreferedWindows>
+          <Position>4</Position>
+          <ScreenPosX>254</ScreenPosX>
+          <ScreenPosY>143</ScreenPosY>
+          <Windows/>
+        </PreferedWindows>
+      </Disassembly>
+    <Register><PreferedWindows><Position>2</Position><ScreenPosX>0</ScreenPosX><ScreenPosY>0</ScreenPosY><Windows/></PreferedWindows></Register></Static>
+    <Windows>
+      
+      
+    <Wnd0>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-7492-12225</Identity>
+            <TabName>Debug Log</TabName>
+            <Factory>Debug-Log</Factory>
+            <Session/>
+          </Tab>
+          <Tab>
+            <Identity>TabID-6969-12235</Identity>
+            <TabName>Build</TabName>
+            <Factory>Build</Factory>
+            <Session/>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd0><Wnd1>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-18240-12229</Identity>
+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
+            <Session>
+              
+            <NodeDict><ExpandedNode>upd70f3454</ExpandedNode><ExpandedNode>upd70f3454/libcpu</ExpandedNode></NodeDict></Session>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd1></Windows>
+    <Editor>
+      
+      
+      
+      
+    <Pane><Tab><Factory>TextEditor</Factory><Filename>E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\applilet3_src\CG_systeminit.c</Filename><XPos>0</XPos><YPos>69</YPos><SelStart>2342</SelStart><SelEnd>2352</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\applilet3_src\CG_system.c</Filename><XPos>0</XPos><YPos>59</YPos><SelStart>2329</SelStart><SelEnd>2329</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\io70f3454.h</Filename><XPos>0</XPos><YPos>517</YPos><SelStart>27396</SelStart><SelEnd>27456</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\RTT\RTTV850\rt-thread\bsp\upd70f3454\cstartup.s85</Filename><XPos>0</XPos><YPos>97</YPos><SelStart>3377</SelStart><SelEnd>3377</SelEnd></Tab><ActiveTab>3</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+    <Positions>
+      
+      
+      
+      
+      
+    <Top><Row0><Sizes><Toolbar-0127ff80><key>iaridepm.enu1</key></Toolbar-0127ff80></Sizes></Row0><Row1><Sizes><Toolbar-067426c8><key>debuggergui.enu1</key></Toolbar-067426c8></Sizes></Row1><Row2><Sizes><Toolbar-04f91ae8><key>v850minicube21</key></Toolbar-04f91ae8></Sizes></Row2></Top><Left><Row0><Sizes><Wnd1><Rect><Top>-2</Top><Left>-2</Left><Bottom>472</Bottom><Right>265</Right><x>-2</x><y>-2</y><xscreen>27493</xscreen><yscreen>343</yscreen><sizeHorzCX>19092361</sizeHorzCX><sizeHorzCY>419315</sizeHorzCY><sizeVertCX>185417</sizeVertCX><sizeVertCY>579462</sizeVertCY></Rect></Wnd1></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd0><Rect><Top>-2</Top><Left>-2</Left><Bottom>253</Bottom><Right>1442</Right><x>-2</x><y>-2</y><xscreen>1444</xscreen><yscreen>255</yscreen><sizeHorzCX>1002778</sizeHorzCX><sizeHorzCY>311736</sizeHorzCY><sizeVertCX>19092361</sizeVertCX><sizeVertCY>419315</sizeVertCY></Rect></Wnd0></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+  </Desktop>
+</Project>
+
+

bsp/upd70f3454/settings/upd70f3454.dni

@@ -0,0 +1,124 @@
+[Interrupts]
+Enabled=1
+[MemoryMap]
+Enabled=0
+Base=0
+UseAuto=0
+TypeViolation=1
+UnspecRange=1
+ActionState=1
+[DataAlign]
+Action=1
+Notification=1
+[DebugChecksum]
+Checksum=576357238
+[DisAssemblyWindow]
+NumStates=_ 1
+State 1=_ 1
+[InstructionProfiling]
+Enabled=_ 0
+[CodeCoverage]
+Enabled=_ 0
+[Profiling]
+Enabled=0
+[StackPlugin]
+Enabled=1
+OverflowWarningsEnabled=1
+WarningThreshold=90
+SpWarningsEnabled=1
+WarnHow=0
+UseTrigger=1
+TriggerName=main
+LimitSize=0
+ByteLimit=50
+[MINICUBE2]
+Map0=0,0,262143,256,3
+Map1=1,268419072,268431359,12,3
+MapEntries=2
+HWsettings=1,33024,8155,0,160,0,0,1
+HWsettings2=0
+HWsettings3=124,1
+NWsettings=0,8000,0,0,FFFFFFFFFFFFFFFFFFFF
+NWsettings2=1
+AutoEventEntries=0
+EventEntries=0
+SeqName0=
+SeqData0=0,0,0
+SeqEnable10=0,0,0,0,0,0,0,0,0,0
+SeqEnable20=0,0,0,0,0,0,0,0,0,0
+SeqEnable30=0,0,0,0,0,0,0,0,0,0
+SeqEnable40=0,0,0,0,0,0,0,0,0,0
+SeqDisable0=0,0,0,0,0,0,0,0,0,0
+SeqName1=
+SeqData1=0,0,0
+SeqEnable11=0,0,0,0,0,0,0,0,0,0
+SeqEnable21=0,0,0,0,0,0,0,0,0,0
+SeqEnable31=0,0,0,0,0,0,0,0,0,0
+SeqEnable41=0,0,0,0,0,0,0,0,0,0
+SeqDisable1=0,0,0,0,0,0,0,0,0,0
+SeqName2=
+SeqData2=0,0,0
+SeqEnable12=0,0,0,0,0,0,0,0,0,0
+SeqEnable22=0,0,0,0,0,0,0,0,0,0
+SeqEnable32=0,0,0,0,0,0,0,0,0,0
+SeqEnable42=0,0,0,0,0,0,0,0,0,0
+SeqDisable2=0,0,0,0,0,0,0,0,0,0
+TraceSettings=-1,0,0,0,0,0,0,2298478591,12,11,0,1,1,1,8192,0,4
+DataFlashSettings=0,0,0,0,0,0,0,0,0,0,0,1,0,1,1
+SelfProgrammingSettings=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+TraceSave=1,v850trace.txt
+TriggerOutSettings=0,0,0,0,0,0,0,0,0,0
+TimerSettings=0,0,0
+Tim2Name1=
+Tim2Data1=0,0,0,0,0,0,0,0,0
+Tim2Start1=0,0,0,0,0,0,0,0,0,0
+Tim2Stop1=0,0,0,0,0,0,0,0,0,0
+Tim2Name2=
+Tim2Data2=0,0,0,0,0,0,0,0,0
+Tim2Start2=0,0,0,0,0,0,0,0,0,0
+Tim2Stop2=0,0,0,0,0,0,0,0,0,0
+Tim2Name3=
+Tim2Data3=0,0,0,0,0,0,0,0,0
+Tim2Start3=0,0,0,0,0,0,0,0,0,0
+Tim2Stop3=0,0,0,0,0,0,0,0,0,0
+Tim2Name4=
+Tim2Data4=0,0,0,0,0,0,0,0,0
+Tim2Start4=0,0,0,0,0,0,0,0,0,0
+Tim2Stop4=0,0,0,0,0,0,0,0,0,0
+Tim2Name5=
+Tim2Data5=0,0,0,0,0,0,0,0,0
+Tim2Start5=0,0,0,0,0,0,0,0,0,0
+Tim2Stop5=0,0,0,0,0,0,0,0,0,0
+Tim2Name6=
+Tim2Data6=0,0,0,0,0,0,0,0,0
+Tim2Start6=0,0,0,0,0,0,0,0,0,0
+Tim2Stop6=0,0,0,0,0,0,0,0,0,0
+Tim2Name7=
+Tim2Data7=0,0,0,0,0,0,0,0,0
+Tim2Start7=0,0,0,0,0,0,0,0,0,0
+Tim2Stop7=0,0,0,0,0,0,0,0,0,0
+Tim2Name8=
+Tim2Data8=0,0,0,0,0,0,0,0,0
+Tim2Start8=0,0,0,0,0,0,0,0,0,0
+Tim2Stop8=0,0,0,0,0,0,0,0,0,0
+Tim2Name9=
+Tim2Data9=0,0,0,0,0,0,0,0,0
+Tim2Start9=0,0,0,0,0,0,0,0,0,0
+Tim2Stop9=0,0,0,0,0,0,0,0,0,0
+CoverSettings=0,1048575,66060288,67108863,0,0,0
+CoverSettings2=0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
+Version=1
+LastDevFile=DF3454.800
+LastSetupFailed=0
+[Log file]
+LoggingEnabled=_ 0
+LogFile=_ ""
+Category=_ 0
+[TermIOLog]
+LoggingEnabled=_ 0
+LogFile=_ ""
+[Breakpoints]
+Count=0
+[TraceHelper]
+Enabled=0
+ShowSource=1

bsp/upd70f3454/settings/upd70f3454.wsdt

@@ -0,0 +1,66 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<Workspace>
+  <ConfigDictionary>
+    
+  <CurrentConfigs><Project>upd70f3454/Debug</Project></CurrentConfigs></ConfigDictionary>
+  <Desktop>
+    <Static>
+      <Workspace>
+        <ColumnWidths>
+          
+          
+          
+          
+        <Column0>198</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
+      </Workspace>
+      <Build>
+        
+        
+        
+        
+      <ColumnWidth0>20</ColumnWidth0><ColumnWidth1>615</ColumnWidth1><ColumnWidth2>164</ColumnWidth2><ColumnWidth3>41</ColumnWidth3></Build>
+    <TerminalIO/><Find-in-Files><ColumnWidth0>496</ColumnWidth0><ColumnWidth1>70</ColumnWidth1><ColumnWidth2>850</ColumnWidth2></Find-in-Files><Debug-Log><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>823</ColumnWidth1></Debug-Log></Static>
+    <Windows>
+      
+      
+    <Wnd2>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-10377-5417</Identity>
+            <TabName>Workspace</TabName>
+            <Factory>Workspace</Factory>
+            <Session>
+              
+            <NodeDict><ExpandedNode>upd70f3454</ExpandedNode><ExpandedNode>upd70f3454/Output</ExpandedNode></NodeDict></Session>
+          </Tab>
+        </Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd2><Wnd3>
+        <Tabs>
+          <Tab>
+            <Identity>TabID-17988-5479</Identity>
+            <TabName>Build</TabName>
+            <Factory>Build</Factory>
+            <Session/>
+          </Tab>
+        <Tab><Identity>TabID-19670-27945</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab><Tab><Identity>TabID-31574-29955</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab></Tabs>
+        
+      <SelectedTab>0</SelectedTab></Wnd3></Windows>
+    <Editor>
+      
+      
+      
+      
+    <Pane/><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
+    <Positions>
+      
+      
+      
+      
+      
+    <Top><Row0><Sizes><Toolbar-0127ff80><key>iaridepm.enu1</key></Toolbar-0127ff80></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>477</Bottom><Right>272</Right><x>-2</x><y>-2</y><xscreen>1</xscreen><yscreen>111</yscreen><sizeHorzCX>694</sizeHorzCX><sizeHorzCY>135697</sizeHorzCY><sizeVertCX>190278</sizeVertCX><sizeVertCY>585575</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>296</Bottom><Right>1442</Right><x>-2</x><y>-2</y><xscreen>1444</xscreen><yscreen>298</yscreen><sizeHorzCX>1002778</sizeHorzCX><sizeHorzCY>364303</sizeHorzCY><sizeVertCX>694</sizeVertCX><sizeVertCY>135697</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
+  </Desktop>
+</Workspace>
+
+

bsp/upd70f3454/startup.c

@@ -0,0 +1,110 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ * 2010-06-29     lgnq         for V850
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "board.h"
+
+#include "CG_macrodriver.h"
+#include "CG_system.h"
+#include "CG_port.h"
+#include "CG_timer.h"
+/* Start user code for include. Do not edit comment generated here */
+/* End user code. Do not edit comment generated here */
+#include "CG_userdefine.h"
+
+extern int  rt_application_init(void);
+
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef RT_USING_HEAP
+#ifdef __ICCV850__
+#pragma section="RT_HEAP"
+#endif
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+    
+	/* init kernel object */
+	rt_system_object_init();
+    
+	/* init timer system */
+	rt_system_timer_init();
+    
+#ifdef RT_USING_HEAP
+#ifdef __ICCV850__
+    rt_system_heap_init(__segment_begin("RT_HEAP"),__segment_end("RT_HEAP"));
+#endif
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+    
+#ifdef RT_USING_DEVICE
+	/* init all device */
+	rt_device_init_all();
+#endif
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device("uart0");
+#endif
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+    
+	/* init idle thread */
+	rt_thread_idle_init();
+    
+	/* start scheduler */
+	rt_system_scheduler_start();
+    
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* init system setting */
+    TAB0_Start();
+    
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}

bsp/upd70f3454/uart.c

@@ -0,0 +1,247 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author           Notes
+ * 2010-03-08     Bernard          The first version for LPC17xx
+ * 2010-06-29     lgnq             Modified for V850
+*/
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "io70f3454.h"
+#include "uart.h"
+
+#if defined(RT_USING_UART0) && defined(RT_USING_DEVICE)
+
+struct rt_uart_v850
+{
+	struct rt_device parent;
+
+	/* buffer for reception */
+	rt_uint8_t read_index, save_index;
+	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+}uart_device;
+
+void  uarta1_receive_handler(void)
+{
+	rt_ubase_t level;
+	rt_uint8_t	 c;
+
+    struct rt_uart_v850* uart = &uart_device;
+
+//	while(ri_u0c1 == 0)
+//		;
+	c = (char) UA1RX;
+
+	/* Receive Data Available */
+    uart->rx_buffer[uart->save_index] = c;
+
+    level = rt_hw_interrupt_disable();
+	uart->save_index ++;
+    if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+        uart->save_index = 0;
+    rt_hw_interrupt_enable(level);
+
+	/* invoke callback */
+	if(uart->parent.rx_indicate != RT_NULL)
+	{
+	    rt_size_t length;
+	    if (uart->read_index > uart->save_index)
+            length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+        else
+            length = uart->save_index - uart->read_index;
+
+        uart->parent.rx_indicate(&uart->parent, length);
+	}
+}
+
+static rt_err_t rt_uart_init (rt_device_t dev)
+{
+	UA1TXE = 0U;	/* disable UARTA1 transmission operation */
+	UA1RXE = 0U;	/* disable UARTA1 reception operation */
+	UA1PWR = 0U;	/* disable UARTA1 operation */
+	UA1TMK = 1U;	/* disable INTUA1T interrupt */
+	UA1TIF = 0U;	/* clear INTUA1T interrupt flag */
+	UA1RMK = 1U;	/* disable INTUA1R interrupt */
+	UA1RIF = 0U;	/* clear INTUA1R interrupt flag */
+	/* Set INTUA1T level low priority */
+	UA1TIC |= 0x07U;
+	/* Set INTUA1R level low priority */
+	UA1RIC |= 0x07U;
+    //BAUDRATE = 9600
+	UA1CTL1 = _03_UARTA_BASECLK_FXX_16;
+	UA1CTL2 = _11_UARTA1_BASECLK_DIVISION;
+	UA1CTL0 = _10_UARTA_TRANSFDIR_LSB | _00_UARTA_PARITY_NONE | _02_UARTA_DATALENGTH_8BIT | _00_UARTA_STOPLENGTH_1BIT;
+	UA1OPT0 = _14_UARTA_UAnOPT0_INITIALVALUE | _00_UARTA_TRAN_DATALEVEL_NORMAL | _00_UARTA_REC_DATALEVEL_NORMAL;
+	UA1PWR = 1U;	/* enable UARTA1 operation */
+	/* Set TXDA1 pin */
+	/* Set RXDA1 pin */
+	PFC3_bit.no0	= 0;
+	PFCE3_bit.no0	= 0;
+	PMC3_bit.no0	= 1;
+
+    PFC3_bit.no1	= 0;
+	PFCE3_bit.no1	= 0;
+	PMC3_bit.no1	= 1;
+    
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	RT_ASSERT(dev != RT_NULL);
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* Enable the UART Interrupt */
+	    UA1TIF = 0U;	/* clear INTUA1T interrupt flag */
+	    UA1TMK = 1U;	/* disable INTUA1T interrupt */
+	    UA1RIF = 0U;	/* clear INTUA1R interrupt flag */
+	    UA1RMK = 0U;	/* enable INTUA1R interrupt */
+	    UA1TXE = 1U;	/* enable UARTA1 transmission operation */
+	    UA1RXE = 1U;	/* enable UARTA1 reception operation */
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_uart_close(rt_device_t dev)
+{
+	RT_ASSERT(dev != RT_NULL);
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* Disable the UART Interrupt */
+	    UA1TXE = 0U;	/* disable UARTA1 transmission operation */
+	    UA1RXE = 0U;	/* disable UARTA1 reception operation */
+	    UA1TMK = 1U;	/* disable INTUA1T interrupt */
+	    UA1TIF = 0U;	/* clear INTUA1T interrupt flag */
+	    UA1RMK = 1U;	/* disable INTUA1R interrupt */
+	    UA1RIF = 0U;	/* clear INTUA1R interrupt flag */
+	}
+
+	return RT_EOK;
+}
+
+static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	struct rt_uart_v850 *uart = (struct rt_uart_v850*)dev;
+	RT_ASSERT(uart != RT_NULL);
+
+	/* point to buffer */
+	ptr = (rt_uint8_t*) buffer;
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		while (size)
+		{
+			/* interrupt receive */
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+			if (uart->read_index != uart->save_index)
+			{
+				*ptr = uart->rx_buffer[uart->read_index];
+
+				uart->read_index ++;
+				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+					uart->read_index = 0;
+			}
+			else
+			{
+				/* no data in rx buffer */
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+
+			ptr ++;
+			size --;
+		}
+
+		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+	}
+
+	return 0;
+}
+
+static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	char *ptr;
+	ptr = (char*)buffer;
+
+	if (dev->flag & RT_DEVICE_FLAG_STREAM)
+	{
+		/* stream mode */
+		while (size)
+		{
+			if (*ptr == '\n')
+			{
+                while(UA1TSF == 1U)
+                    ;
+                UA1TX = '\r';
+			}
+
+			/* THRE status, contain valid data */
+            while(UA1TSF == 1U)
+                ;
+            UA1TX = *ptr;
+  
+			ptr ++;
+			size --;
+		}
+	}
+	else
+	{
+		while ( size != 0 )
+		{
+			/* THRE status, contain valid data */
+            while(UA1TSF == 1U)
+                ;
+            UA1TX = *ptr;
+	
+			ptr++;
+			size--;
+		}
+	}
+
+	return (rt_size_t) ptr - (rt_size_t) buffer;
+}
+
+void rt_hw_uart_init(void)
+{
+	struct rt_uart_v850* uart;
+
+	/* get uart device */
+	uart = &uart_device;
+
+	/* device initialization */
+	uart->parent.type = RT_Device_Class_Char;
+	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+	uart->read_index = uart->save_index = 0;
+
+	/* device interface */
+	uart->parent.init 	    = rt_uart_init;
+	uart->parent.open 	    = rt_uart_open;
+	uart->parent.close      = rt_uart_close;
+	uart->parent.read 	    = rt_uart_read;
+	uart->parent.write      = rt_uart_write;
+	uart->parent.control    = RT_NULL;
+	uart->parent.private    = RT_NULL;
+
+	rt_device_register(&uart->parent,
+		"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+}
+#endif /* end of UART */
+
+/*@}*/

bsp/upd70f3454/uart.h

@@ -0,0 +1,296 @@
+#ifndef __UART_H__
+#define __UART_H__
+
+#define BAUD_RATE 9600
+
+/*
+	UARTAn control register 0 (UAnCTL0)
+*/
+#define	_10_UARTA_UAnCTL0_INITIALVALUE			0x10U
+/* UARTAn operation control (UAnPWR) */
+#define	_00_UARTA_OPERATION_DISABLE			0x00U	/* disable UARTAn operation (UARTAn reset asynchronously) */
+#define	_80_UARTA_OPERATION_ENABLE			0x80U	/* enable UARTAn operation */
+/* Transmission operation enable (UAnTXE) */
+#define	_00_UARTA_TRANSMISSION_DISABLE			0x00U	/* disable transmission operation */
+#define	_40_UARTA_TRANSMISSION_ENABLE			0x40U	/* enable transmission operation */
+/* Reception operation enable (UAnRXE) */
+#define	_00_UARTA_RECEPTION_DISABLE			0x00U	/* disable reception operation */
+#define	_20_UARTA_RECEPTION_ENABLE			0x20U	/* enable reception operation */
+/* Transfer direction selection (UAnDIR) */
+#define	_00_UARTA_TRANSFDIR_MSB				0x00U	/* MSB-first transfer */
+#define	_10_UARTA_TRANSFDIR_LSB				0x10U	/* LSB-first transfer */
+/* Parity selection during transmission/reception (UAnPS1,UAnPS0) */
+#define	_00_UARTA_PARITY_NONE				0x00U	/* no parity output/reception with no parity */
+#define	_04_UARTA_PARITY_ZREO				0x04U	/* 0 parity output/reception with 0 parity */
+#define	_08_UARTA_PARITY_ODD				0x08U	/* odd parity output/odd parity check */
+#define	_0C_UARTA_PARITY_EVEN				0x0CU	/* even parity output/even parity check */
+/* Specification of data character length of 1 frame of transmit/receive data (UAnCL) */
+#define	_00_UARTA_DATALENGTH_7BIT			0x00U	/* 7 bits */
+#define	_02_UARTA_DATALENGTH_8BIT			0x02U	/* 8 bits */
+/* Specification of length of stop bit for transmit data (UAnSL) */
+#define	_00_UARTA_STOPLENGTH_1BIT			0x00U	/* 1 bit */
+#define	_01_UARTA_STOPLENGTH_2BIT			0x01U	/* 2 bits */
+
+/*
+	UARTAn base clock selects register (UAnCTL1)
+*/
+/* UAnCTL1 register (UAnCKS3 - UAnCKS0) */
+#define	_00_UARTA_BASECLK_FXX_2				0x00U	/* fXX/2 */
+#define	_01_UARTA_BASECLK_FXX_4				0x01U	/* fXX/2^2 */
+#define	_02_UARTA_BASECLK_FXX_8				0x02U	/* fXX/2^3 */
+#define	_03_UARTA_BASECLK_FXX_16			0x03U	/* fXX/2^4 */
+#define	_04_UARTA_BASECLK_FXX_32			0x04U	/* fXX/2^5 */
+#define	_05_UARTA_BASECLK_FXX_64			0x05U	/* fXX/2^6 */
+#define	_06_UARTA_BASECLK_FXX_128			0x06U	/* fXX/2^7 */
+#define	_07_UARTA_BASECLK_FXX_256			0x07U	/* fXX/2^8 */
+#define	_08_UARTA_BASECLK_FXX_512			0x08U	/* fXX/2^9 */
+#define	_09_UARTA_BASECLK_FXX_1024			0x09U	/* fXX/2^10 */
+#define	_0A_UARTA_BASECLK_FXX_2048			0x0AU	/* fXX/2^11 */
+#define	_0B_UARTA_BASECLK_FXX_4096			0x0BU	/* fXX/2^12 */
+
+/*
+	UARTAn option control register 0 (UAnOPT0)
+*/
+#define	_14_UARTA_UAnOPT0_INITIALVALUE			0x14U
+/* Transmit data level bit(UAnTDL) */
+#define	_00_UARTA_TRAN_DATALEVEL_NORMAL			0x00U	/* normal output of transfer data */
+#define	_02_UARTA_TRAN_DATALEVEL_INVERTED		0x02U	/* inverted output of transfer data */
+/* Receive data level bit(UAnRDL) */
+#define	_00_UARTA_REC_DATALEVEL_NORMAL			0x00U	/* normal input of transfer data */
+#define	_01_UARTA_REC_DATALEVEL_INVERTED		0x01U	/* inverted input of transfer data */
+
+/*
+	CSIBn control register 0 (CBnCTL0)
+*/
+/* Specification of CSIBn operation disable/enable (CBnPWR)*/
+#define	_00_CSIB_OPERATION_DISABLE		0x00U	/* disable CSIBn operation and reset the CBnSTR register */
+#define	_80_CSIB_OPERATION_ENABLE		0x80U	/* enable CSIBn operation */
+/* Specification of transmit operation disable/enable (CBnTXE)*/
+#define	_00_CSIB_TRANSMIT_DISABLE		0x00U	/* disable transmit operation */
+#define	_40_CSIB_TRANSMIT_ENABLE		0x40U	/* enable transmit operation */
+/* Specification of receive operation disable/enable (CBnRXE)*/
+#define	_00_CSIB_RECEIVE_DISABLE		0x00U	/* disable receive operation */
+#define	_20_CSIB_RECEIVE_ENABLE			0x20U	/* enable receive operation */
+/* Specification of transfer direction mode (MSB/LSB) (CBnDIR) */
+#define	_00_CSIB_DATA_MSB			0x00U	/* MSB first */ 
+#define	_10_CSIB_DATA_LSB			0x10U	/* LSB first */
+/* Transfer mode specification (CBnTMS) */
+#define	_00_CSIB_MODE_SINGLE			0x00U	/* single transfer mode */
+#define	_02_CSIB_MODE_CONTINUOUS		0x02U	/* continuous transfer mode */
+/* Specification of start transfer disable/enable (CBnSCE) */
+#define	_00_CSIB_STARTTRG_INVALID		0x00U	/* communication start trigger invalid */
+#define	_01_CSIB_STARTTRG_VALID			0x01U	/* communication start trigger valid */
+
+/*
+	CSIBn control register 1 (CBnCTL1)
+*/
+/* Specification of data transmission/reception timing in relation to SCKBn (CBnCKP, CBnDAP) */
+#define	_00_CSIB_DATA_TIMING1			0x00U	/* communication type 1 */
+#define	_08_CSIB_DATA_TIMING2			0x08U	/* communication type 2 */
+#define	_10_CSIB_DATA_TIMING3			0x10U	/* communication type 3 */
+#define	_18_CSIB_DATA_TIMING4			0x18U	/* communication type 4 */
+/* Specification of input clock (CBnCKS2 - CBnCKS0) */
+#define	_00_CSIB_CLOCK_1			0x00U	/* fXX /2 */
+#define	_01_CSIB_CLOCK_2			0x01U	/* fXX/4 */
+#define	_02_CSIB_CLOCK_3			0x02U	/* fXX /8 */	
+#define	_03_CSIB_CLOCK_4			0x03U	/* fXX /16 */
+#define	_04_CSIB_CLOCK_5			0x04U	/* fXX /32 */
+#define	_05_CSIB_CLOCK_6			0x05U	/* fXX /64 */
+#define	_06_CSIB_CLOCK_7			0x06U	/* fBRGm */
+#define	_07_CSIB_CLOCK_EXT			0x07U	/* external clock SCKBn */
+
+/*
+	CSIBn control register 2 (CBnCTL2)
+*/
+/* Serial register bit length (CBnCL3,CBnCL2,CBnCL1,CBnCL0) */
+#define	_00_CSIB_DATA_LENGTH_8			0x00U	/* 8 bits */
+#define	_01_CSIB_DATA_LENGTH_9			0x01U	/* 9 bits */
+#define	_02_CSIB_DATA_LENGTH_10			0x02U	/* 10 bits */
+#define	_03_CSIB_DATA_LENGTH_11			0x03U	/* 11 bits */
+#define	_04_CSIB_DATA_LENGTH_12			0x04U	/* 12 bits */
+#define	_05_CSIB_DATA_LENGTH_13			0x05U	/* 13 bits */
+#define	_06_CSIB_DATA_LENGTH_14			0x06U	/* 14 bits */
+#define	_07_CSIB_DATA_LENGTH_15			0x07U	/* 15 bits */
+#define	_08_CSIB_DATA_LENGTH_16			0x08U	/* 16 bits */
+
+/*
+	CSIBn status register (CBnSTR)
+*/
+/* Communication status flag (CBnTSF) */
+#define	_00_CSIB_COMMUNICATION_STOP		0x00U	/* communication stopped */
+#define	_80_CSIB_COMMUNICATING			0x80U	/* communicating */
+/* Overrun error flag (CBnOVE) */
+#define	_00_CSIB_OVERRUN_NONE			0x00U	/* no overrun */
+#define	_01_CSIB_OVERRUN			0x01U	/* overrun */
+
+/*
+	BRGm prescaler mode registers (PRSMm)
+*/
+/* Baud rate output(BGCEm) */
+#define	_00_CSIB_FBRGM_DISABLE			0x00U	/* baudrate output disabled */
+#define	_10_CSIB_FBRGM_ENABLE			0x10U	/* baudrate output enabled */
+/* Input clock selection (BGCSm1,BGCSm0) */
+#define	_00_CSIB_FBGCS_0			0x00U	/* fXX */	
+#define	_01_CSIB_FBGCS_1			0x01U	/* fXX/2 */
+#define	_02_CSIB_FBGCS_2			0x02U	/* fXX/4 */
+#define	_03_CSIB_FBGCS_3			0x03U	/* fXX/8 */
+#define	CB4RIC		UA0RIC
+#define	CB4TIC		UA0TIC
+#define	CB0RIC		IICIC1
+
+/*
+	IIC control register (IICCn)
+*/
+/* IIC operation enable	(IICEn)	*/
+#define	_80_IIC_OPERATION			0x80U
+#define	_00_IIC_OPERATION_DISABLE		0x00U	/* stop operation */
+#define	_80_IIC_OPERATION_ENABLE		0x80U	/* enable operation */
+/* Exit	from communications (LRELn)	*/
+#define	_40_IIC_COMMUNICATION			0x40U
+#define	_00_IIC_COMMUNICATION_NORMAL		0x00U	/* normal operation	*/
+#define	_40_IIC_COMMUNICATION_EXIT		0x40U	/* exit	from current communication */
+/* Wait	cancellation (WRELn) */
+#define	_20_IIC_WAITCANCEL			0x20U
+#define	_00_IIC_WAIT_NOTCANCEL			0x00U	/* do not cancel wait */
+#define	_20_IIC_WAIT_CANCEL			0x20U	/* cancel wait */
+/* Generation of interrupt when	stop condition (SPIEn) */
+#define	_10_IIC_STOPINT				0x10U
+#define	_00_IIC_STOPINT_DISABLE			0x00U	/* disable */
+#define	_10_IIC_STOPINT_ENABLE			0x10U	/* enable */
+/* Wait	and interrupt generation (WTIMn) */
+#define	_08_IIC_WAITINT				0x08U
+#define	_00_IIC_WAITINT_CLK8FALLING		0x00U	/* generate at the eighth clock falling edge */
+#define	_08_IIC_WAITINT_CLK9FALLING		0x08U	/* generated at the ninth clock falling edge */
+/* Acknowledgement control (ACKEn) */
+#define	_04_IIC_ACK				0x04
+#define	_00_IIC_ACK_DISABLE			0x00U	/* disable acknowledgement */
+#define	_04_IIC_ACK_ENABLE			0x04U	/* enable acknowledgement */
+/* Start condition trigger (STTn) */
+#define	_02_IIC_STARTCONDITION			0x02U
+#define	_00_IIC_START_NOTGENERATE		0x00U	/* do not generate start condition */
+#define	_02_IIC_START_GENERATE			0x02U	/* generate start condition */
+/* Stop	condition trigger (SPTn) */
+#define	_01_IIC_STOPCONDITION			0x01U
+#define	_00_IIC_STOP_NOTGENERATE		0x00U	/* do not generate stop condition */
+#define	_01_IIC_STOP_GENERATE			0x01U	/* generate stop condition */
+
+/*
+	IIC Status Register (IICSn)
+*/
+/* Master device status (MSTSn) */
+#define	_80_IIC_MASTERSTATUS			0x80U
+#define	_00_IIC_STATUS_NOTMASTER		0x00U	/* slave device status or communication standby status */
+#define	_80_IIC_STATUS_MASTER			0x80U	/* master device communication status */
+/* Detection of arbitration loss (ALDn) */
+#define	_40_IIC_ARBITRATION			0x40U
+#define	_00_IIC_ARBITRATION_NO			0x00U	/* arbitration win or no arbitration */
+#define	_40_IIC_ARBITRATION_LOSS		0x40U	/* arbitration loss */
+/* Detection of extension code reception (EXCn) */
+#define	_20_IIC_EXTENSIONCODE			0x20U
+#define	_00_IIC_EXTCODE_NOT			0x00U	/* extension code not received */
+#define	_20_IIC_EXTCODE_RECEIVED		0x20U	/* extension code received */
+/* Detection of matching addresses (COIn) */
+#define	_10_IIC_ADDRESSMATCH			0x10U
+#define	_00_IIC_ADDRESS_NOTMATCH		0x00U	/* addresses do not match */
+#define	_10_IIC_ADDRESS_MATCH			0x10U	/* addresses match */
+/* Detection of transmit/receive status	(TRCn) */
+#define	_08_IIC_STATUS				0x08U
+#define	_00_IIC_STATUS_RECEIVE			0x00U	/* receive status */
+#define	_08_IIC_STATUS_TRANSMIT			0x08U	/* transmit status */
+/* Detection of acknowledge signal (ACKDn) */
+#define	_04_IIC_ACKDETECTION			0x04U
+#define	_00_IIC_ACK_NOTDETECTED			0x00U	/* ACK signal was not detected */
+#define	_04_IIC_ACK_DETECTED			0x04U	/* ACK signal was detected */
+/* Detection of start condition (STDn) */
+#define	_02_IIC_STARTDETECTION			0x02U
+#define	_00_IIC_START_NOTDETECTED		0x00U	/* start condition not detected */
+#define	_02_IIC_START_DETECTED			0x02U	/* start condition detected */
+/* Detection of stop condition (SPDn) */
+#define	_01_IIC_STOPDETECTION			0x01U
+#define	_00_IIC_STOP_NOTDETECTED		0x00U	/* stop	condition not detected */
+#define	_01_IIC_STOP_DETECTED			0x01U	/* stop	condition detected */
+
+/*
+	IIC	Flag Register (IICFn)
+*/
+/* STTn	clear flag (STCFn) */
+#define	_80_IIC_STARTFLAG			0x80U
+#define	_00_IIC_STARTFLAG_GENERATE		0x00U	/* generate start condition */
+#define	_80_IIC_STARTFLAG_UNSUCCESSFUL		0x80U	/* start condition generation unsuccessful */
+/* IIC bus status flag (IICBSYn)	*/
+#define	_40_IIC_BUSSTATUS			0x40U
+#define	_00_IIC_BUS_RELEASE			0x00U	/* bus release status */
+#define	_40_IIC_BUS_COMMUNICATION		0x40U	/* bus communication status */
+/* Initial start enable trigger (STCENn)	*/
+#define	_02_IIC_STARTWITHSTOP			0x02U
+#define	_00_IIC_START_WITHSTOP			0x00U	/* generation of a start condition upon detection of a stop condition */
+#define	_02_IIC_START_WITHOUTSTOP		0x02U	/* generation of a start condition without detecting a stop condition */
+/* Communication reservation function disable bit (IICRSVn) */
+#define	_01_IIC_RESERVATION			0x01U
+#define	_00_IIC_RESERVATION_ENABLE		0x00U	/* enable communication reservation */
+#define	_01_IIC_RESERVATION_DISABLE		0x01U	/* disable communication reservation */
+
+/*
+	IIC clock selection register (IICCLn)
+*/
+#define _00_IICCL_INITIALVALUE 				0x00U
+/* Detection of SCL0n pin level (CLDn) */
+#define	_20_IIC_SCLLEVEL				0x20U
+#define	_00_IIC_SCL_LOW					0x00U	/* clock line at low level */
+#define	_20_IIC_SCL_HIGH				0x20U	/* clock line at high level */
+/* Detection of SDA0 pin level (DADn) */
+#define	_10_IIC_SDALEVEL				0x10U
+#define	_00_IIC_SDA_LOW					0x00U	/* data	line at low level */
+#define	_10_IIC_SDA_HIGH				0x10U	/* data	line at high level */
+/* Operation mode switching (SMCn) */
+#define	_08_IIC_OPERATIONMODE				0x08U
+#define	_00_IIC_MODE_STANDARD				0x00U	/* operates in standard mode */
+#define	_08_IIC_MODE_HIGHSPEED				0x08U	/* operates in high-speed mode */
+/* Digital filter operation control (DFCn) */
+#define	_04_IIC_DIGITALFILTER				0x04U
+#define	_00_IIC_FILTER_OFF				0x00U	/* digital filter off */
+#define	_04_IIC_FILTER_ON				0x04U	/* digital filter on */
+/* Operation mode switching (CLn1, CLn0) */
+#define	_03_IIC_CLOCKSELECTION				0x03U
+/*	Combine of (CLn1, CLn0)*/
+#define	_00_IIC_CLOCK0					0x00U
+#define	_01_IIC_CLOCK1					0x01U
+#define	_02_IIC_CLOCK2					0x02U
+#define	_03_IIC_CLOCK3					0x03U
+
+/*
+	IIC division clock select register (OCKSn)
+*/
+#define	_10_IIC_SELECTED0				0x10U
+#define	_11_IIC_SELECTED1				0x11U
+#define	_12_IIC_SELECTED2				0x12U
+#define	_13_IIC_SELECTED3				0x13U
+#define	_18_IIC_SELECTED4				0x18U
+
+/*
+	IIC function expansion register	0 (IICXn)
+*/
+/* IIC clock expension (CLXn) */
+#define	_01_IIC_CLOCKEXPENSION				0x01U
+#define	_00_IIC_EXPENSION0				0x00U
+#define	_01_IIC_EXPENSION1				0x01U
+#define	_80_ADDRESS_COMPLETE				0x80U
+#define	_00_IIC_MASTER_FLAG_CLEAR			0x00U
+#define	IICIC2		UA1RIC
+#define	IICIC0		UA2RIC
+/*
+*******************************************************************************
+**  Macro define
+*******************************************************************************
+*/
+/* Selection of 8-bit counter output clock (UA1BRS7~UA1BRS0) */
+#define	_D0_UARTA1_BASECLK_DIVISION		0xD0U	/* 4 ~ 255 */ //9600
+#define	_11_UARTA1_BASECLK_DIVISION		0x11U	/* 4 ~ 255 */ //115200
+enum TransferMode 
+{
+	SEND, RECEIVE
+};
+
+void rt_hw_uart_init(void);
+
+#endif

bsp/upd70f3454/upd70f3454.cgp

@@ -0,0 +1,1575 @@
+<!-- edited with XMLSpy v2007 sp2 (http://www.altova.com) by luoy (NEC Electronics(China) Co.,Ltd) -->
+<V850ESJx3>
+  <VAR>
+    <ProjectName Name="PrjName" Text="upd70f3454" />
+    <ProjectPath Name="PrjPath" Text="E:\RTT\RTTV850\rt-thread\bsp\upd70f3454" />
+    <DeviceName Name="DeviceName" Fixed="" Text="V850ESJx3" />
+    <MCUName Name="MCUName" Text="V850ESJJ3" />
+    <ChipName Name="ChipName" Text="uPD70F3746" />
+    <ChipID Name="ChipID" Text="DF3746" />
+    <MCUType Name="MCUType" Fixed="" Text="V850ES" />
+    <Compiler Name="Compiler" Text="EW850" />
+    <fCLK Name="fCLK" Value="0.5" Comment="4M" Trigger="fCPU">
+      <Effect>
+        <LVI />
+      </Effect>
+    </fCLK>
+    <fXX Name="fXX" Value="4" Trigger="fXX" Comment="4M">
+      <Effect>
+        <AD />
+        <UARTA0 />
+        <UARTA1 />
+        <UARTA2 />
+        <UARTA3 />
+        <UARTA4 />
+        <UARTA5 />
+        <UARTC0 />
+        <CSIB0 />
+        <CSIB1 />
+        <CSIB2 />
+        <CSIB3 />
+        <CSIB4 />
+        <CSIB5 />
+        <IIC00 />
+        <IIC01 />
+        <IIC02 />
+        <TMP0 />
+        <TMP1 />
+        <TMP2 />
+        <TMP3 />
+        <TMP4 />
+        <TMP5 />
+        <TMP6 />
+        <TMP7 />
+        <TMP8 />
+        <TMQ0 />
+        <TMM0 />
+        <INTP />
+        <BUS />
+      </Effect>
+    </fXX>
+    <fXT Name="fXT" Value="0" Trigger="fXT" Comment="32.768kHz">
+      <Effect>
+        <INTP />
+        <TMM0 />
+        <RTC />
+        <WatchTimer />
+      </Effect>
+    </fXT>
+    <fR Name="fR" Value="220" Trigger="fR" Comment="220K">
+      <Effect>
+        <TMM0 />
+      </Effect>
+    </fR>
+    <fBRG Name="fBRG" Value="0" Trigger="fBRG" Comment="32.768kHz">
+      <Effect>
+        <RTC />
+        <WatchTimer />
+      </Effect>
+    </fBRG>
+    <INTWT Name="INTWT" Value="0" Trigger="INTWT" Comment="scale is interval, not frequency">
+      <Effect>
+        <TMM0 />
+      </Effect>
+    </INTWT>
+    <IIC00 Name="IIC00" Text="false" Comment="scale is interval, not frequency" Trigger="IIC00">
+      <Effect>
+        <PORT Forcible="" />
+      </Effect>
+    </IIC00>
+    <IIC01 Name="IIC01" Text="false" Comment="scale is interval, not frequency" Trigger="IIC01">
+      <Effect>
+        <PORT Forcible="" />
+      </Effect>
+    </IIC01>
+    <IIC02 Name="IIC02" Text="false" Comment="scale is interval, not frequency" Trigger="IIC02">
+      <Effect>
+        <PORT Forcible="" />
+      </Effect>
+    </IIC02>
+    <RompFile Name="RompFile" Text="1" />
+    <SecurityId Name="SecurityId" Text="FFFFFFFFFFFFFFFFFFFF" />
+    <MacroDef Name="MacroDef" Text="__nec__" />
+    <RAMStartAddress Chip="DF3741,DF3742,DF3745,DF3746" Fixed="" Name="RAMStartAddress" Text="03FF0000" />
+    <RAMEndAddress Fixed="" Name="RAMEndAddress" Text="03FFEFFF" />
+    <ROMStartAddress Fixed="" Name="ROMStartAddress" Text="00000000" />
+    <ROMEndAddress Chip="DF3746,DF3742" Fixed="" Name="ROMEndAddress" Text="000FFFFF" />
+    <BUSArea Name="BUSArea" Text="0,0,0,0" Comment="scale is interval, not frequency" Trigger="BUSArea">
+      <Effect>
+        <DMA0 />
+        <DMA1 />
+        <DMA2 />
+        <DMA3 />
+      </Effect>
+    </BUSArea>
+    <PrjKind Name="PrjKind" Text="ProjectV850" />
+    <CodePath Name="CodePath" Text=".\" />
+    <ReportType Name="ReportType" Text="Html" />
+    <GenerateType Name="GenerateType" Text="Merge" />
+    <PrjVersion Name="PrjVersion" Text="1.2.0.1" />
+    <UICultureNumberDecimalSeparator Name="UICultureNumberDecimalSeparator" Text="." />
+    <UICultureNumberGroupSeparator Name="UICultureNumberGroupSeparator" Text="," />
+  </VAR>
+  <DIR>
+    <PIN>
+      <System>
+        <FLMD0 AltFunc="" Point="I" />
+        <FLMD1 Port="PDL5" Point="I" UnConflict="AD5" />
+        <X1 AltFunc="" Point="I" />
+        <X2 AltFunc="" Point="-" />
+        <XT1 AltFunc="" Point="I" />
+        <XT2 AltFunc="" Point="-" />
+        <CLKOUT Port="PCM1" Point="O" />
+        <DRST Port="P05" RealName="_DRST" Point="I" />
+        <DDI Port="P52" Point="I" />
+        <DDO Port="P53" Point="O" />
+        <DCK Port="P54" Point="I" />
+        <DMS Port="P55" Point="I" />
+        <TXDA0_OCD Port="P30" RealName="TXDA0" Point="O" />
+        <RXDA0_OCD Port="P31" RealName="RXDA0" Point="I" Pset="" />
+        <SIB0_OCD Port="P40" RealName="SIB0" Point="I" Pset="" />
+        <SOB0_OCD Port="P41" RealName="SOB0" Point="O" Pset="" />
+        <SCKB0_OCD Port="P42" RealName="_SCKB0" Point="I/O" Pset="" />
+        <SIB3_OCD Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" RealName="SIB3" UnConflict="A10" Port="P910" Point="I" Pset="" />
+        <SOB3_OCD Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" RealName="SOB3" UnConflict="A11" Port="P911" Point="O" Pset="" />
+        <SCKB3_OCD Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" RealName="_SCKB3" UnConflict="A12" Port="P912" Point="I/O" Pset="" />
+        <PCM0_OCD Port="PCM0" RealName="PCM0" Point="I" Pset="" />
+      </System>
+      <BUS>
+        <WAIT Port="PCM0" RealName="_WAIT" Point="I" />
+        <HLDAK Port="PCM2" RealName="_HLDAK" Point="O" />
+        <HLDRQ Port="PCM3" RealName="_HLDRQ" Point="I" />
+        <CS0 Chip="V850ESJJ3" Port="PCS0" RealName="_CS0" Point="O" />
+        <CS1 Chip="V850ESJJ3" Port="PCS1" RealName="_CS1" Point="O" />
+        <CS2 Chip="V850ESJJ3" Port="PCS2" RealName="_CS2" Point="O" />
+        <CS3 Chip="V850ESJJ3" Port="PCS3" RealName="_CS3" Point="O" />
+        <WR0 Port="PCT0" RealName="_WR0" Point="O" />
+        <WR1 Port="PCT1" RealName="_WR1" Point="O" />
+        <RD Port="PCT4" RealName="_RD" Point="O" />
+        <ASTB Port="PCT6" Point="O" />
+        <AD0 Port="PDL0" Point="I/O" />
+        <AD1 Port="PDL1" Point="I/O" />
+        <AD2 Port="PDL2" Point="I/O" />
+        <AD3 Port="PDL3" Point="I/O" />
+        <AD4 Port="PDL4" Point="I/O" />
+        <AD5 Port="PDL5" Point="I/O" UnConflict="FLMD1" />
+        <AD6 Port="PDL6" Point="I/O" />
+        <AD7 Port="PDL7" Point="I/O" />
+        <AD8 Port="PDL8" Point="I/O" />
+        <AD9 Port="PDL9" Point="I/O" />
+        <AD10 Port="PDL10" Point="I/O" />
+        <AD11 Port="PDL11" Point="I/O" />
+        <AD12 Port="PDL12" Point="I/O" />
+        <AD13 Port="PDL13" Point="I/O" />
+        <AD14 Port="PDL14" Point="I/O" />
+        <AD15 Port="PDL15" Point="I/O" />
+        <A0 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P90" Point="O" />
+        <A1 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P91" Point="O" />
+        <A2 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P92" Point="O" />
+        <A3 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P93" Point="O" />
+        <A4 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P94" Point="O" />
+        <A5 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P95" Point="O" />
+        <A6 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P96" Point="O" />
+        <A7 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P97" Point="O" />
+        <A8 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P98" Point="O" />
+        <A9 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P99" Point="O" />
+        <A10 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" UnConflict="SIB3_OCD" Port="P910" Point="O" />
+        <A11 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" UnConflict="SOB3_OCD" Port="P911" Point="O" />
+        <A12 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" UnConflict="SCKB3_OCD" Port="P912" Point="O" />
+        <A13 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P913" Point="O" />
+        <A14 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P914" Point="O" />
+        <A15 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="P915" Point="O" />
+        <A16 Port="PDH0" Point="O" />
+        <A17 Port="PDH1" Point="O" />
+        <A18 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="PDH2" Point="O" />
+        <A19 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="PDH3" Point="O" />
+        <A20 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Port="PDH4" Point="O" />
+        <A21 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Port="PDH5" Point="O" />
+        <A22 Chip="V850ESJJ3" Port="PDH6" Point="O" />
+        <A23 Chip="V850ESJJ3" Port="PDH7" Point="O" />
+      </BUS>
+      <PORT>
+        <Port0 Nch="true">
+          <P00 Chip="V850ESJJ3" Name="P00/TIP61/TOP61" AltFunc="" Point="I/O" />
+          <P01 Chip="V850ESJJ3" Name="P01/TIP60/TOP60" AltFunc="" Point="I/O" />
+          <P02 Chip="V850ESJF3L,DF3737,DF3738,V850ESJG3,V850ESJJ3" Name="P02/NMI" AltFunc="" Point="I/O" />
+          <P03 Chip="V850ESJF3L,DF3737,DF3738,V850ESJG3,V850ESJJ3" Name="P03/INTP0/ADTRG" AltFunc="" Point="I/O" />
+          <P04 Chip="V850ESJF3L,DF3737,DF3738,V850ESJG3,V850ESJJ3" Name="P04/INTP1" AltFunc="" Point="I/O" />
+          <P05 Name="P05/INTP2/DRST" AltFunc="" Point="I/O" />
+          <P06 Name="P06/INTP3" AltFunc="" Point="I/O" />
+        </Port0>
+        <Port1 NoRegPMC="true">
+          <P10 Name="P10/ANO0" AltFunc="" Point="I/O" />
+          <P11 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P11/ANO1" AltFunc="" Point="I/O" />
+        </Port1>
+        <Port3 Nch="true">
+          <P30 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P30/TXDA0/SOB4" AltFunc="" Point="I/O" />
+          <P31 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P31/RXDA0/INTP7/SIB4" AltFunc="" Point="I/O" />
+          <P32 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P32/ASCKA0/SCKB4/TIP00/TOP00" AltFunc="" Point="I/O" />
+          <P33 Name="P33/TIP01/TOP01" AltFunc="" Point="I/O" />
+          <P34 Name="P34/TIP10/TOP10" AltFunc="" Point="I/O" />
+          <P35 Name="P35/TIP11/TOP11" AltFunc="" Point="I/O" />
+          <P36 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P36" AltFunc="" Point="I/O" />
+          <P37 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P37" AltFunc="" Point="I/O" />
+          <P38 Name="P38/TXDA2/SDA00" AltFunc="" Point="I/O" />
+          <P39 Name="P39/RXDA2/SCL00" AltFunc="" Point="I/O" />
+        </Port3>
+        <Port4 Nch="true">
+          <P40 Name="P40/SIB0/SDA01" AltFunc="" Point="I/O" />
+          <P41 Name="P41/SOB0/SCL01" AltFunc="" Point="I/O" />
+          <P42 Name="P42/SCKB0" AltFunc="" Point="I/O" />
+        </Port4>
+        <Port5 Nch="true">
+          <P50 Name="P50/TIQ01/KR0/TOQ01/RTP00" AltFunc="" Point="I/O" />
+          <P51 Name="P51/TIQ02/KR1/TOQ02/RTP01" AltFunc="" Point="I/O" />
+          <P52 Name="P52/TIQ03/KR2/TOQ03/RTP02/DDI" AltFunc="" Point="I/O" />
+          <P53 Name="P53/SIB2/TIQ00/KR3/TOQ00/RTP03/DDO" AltFunc="" Point="I/O" />
+          <P54 Name="P54/SOB2/KR4/RTP04/DCK" AltFunc="" Point="I/O" />
+          <P55 Name="P55/SCKB2/KR5/RTP05/DMS" AltFunc="" Point="I/O" />
+        </Port5>
+        <Port6 Chip="V850ESJJ3" Nch="true">
+          <P60 Name="P60/RTP10" AltFunc="" Point="I/O" />
+          <P61 Name="P61/RTP11" AltFunc="" Point="I/O" />
+          <P62 Name="P62/RTP12" AltFunc="" Point="I/O" />
+          <P63 Name="P63/RTP13" AltFunc="" Point="I/O" />
+          <P64 Name="P64/RTP14" AltFunc="" Point="I/O" />
+          <P65 Name="P65/RTP15" AltFunc="" Point="I/O" />
+          <P66 Name="P66/SIB5" AltFunc="" Point="I/O" />
+          <P67 Name="P67/SOB5" AltFunc="" Point="I/O" />
+          <P68 Name="P68/SCKB5" AltFunc="" Point="I/O" />
+          <P69 Name="P69/TIP70/TOP70" AltFunc="" Point="I/O" />
+          <P610 Name="P610/TIP71" AltFunc="" Point="I/O" />
+          <P611 Name="P611/TOP71" AltFunc="" Point="I/O" />
+          <P612 Name="P612/TIP80/TOP80" AltFunc="" Point="I/O" />
+          <P613 Name="P613/TIP81/TOP81" AltFunc="" Point="I/O" />
+          <P614 Name="P614" AltFunc="" Point="I/O" />
+          <P615 Name="P615" AltFunc="" Point="I/O" />
+        </Port6>
+        <Port7 NoRegPMC="true">
+          <P70 Name="P70/ANI0" AltFunc="" Point="I/O" />
+          <P71 Name="P71/ANI1" AltFunc="" Point="I/O" />
+          <P72 Name="P72/ANI2" AltFunc="" Point="I/O" />
+          <P73 Name="P73/ANI3" AltFunc="" Point="I/O" />
+          <P74 Name="P74/ANI4" AltFunc="" Point="I/O" />
+          <P75 Name="P75/ANI5" AltFunc="" Point="I/O" />
+          <P76 Name="P76/ANI6" AltFunc="" Point="I/O" />
+          <P77 Name="P77/ANI7" AltFunc="" Point="I/O" />
+          <P78 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P78/ANI8" AltFunc="" Point="I/O" />
+          <P79 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P79/ANI9" AltFunc="" Point="I/O" />
+          <P710 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P710/ANI10" AltFunc="" Point="I/O" />
+          <P711 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P711/ANI11" AltFunc="" Point="I/O" />
+          <P712 Chip="V850ESJJ3" Name="P712/ANI12" AltFunc="" Point="I/O" />
+          <P713 Chip="V850ESJJ3" Name="P713/ANI13" AltFunc="" Point="I/O" />
+          <P714 Chip="V850ESJJ3" Name="P714/ANI14" AltFunc="" Point="I/O" />
+          <P715 Chip="V850ESJJ3" Name="P715/ANI15" AltFunc="" Point="I/O" />
+        </Port7>
+        <Port8 Chip="V850ESJJ3" Nch="true">
+          <P80 Name="P80/RXDA3/INTP8" AltFunc="" Point="I/O" />
+          <P81 Name="P81/TXDA3" AltFunc="" Point="I/O" />
+        </Port8>
+        <Port9 Nch="true">
+          <P90 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P90/A0/KR6/TXDA1/SDA02" AltFunc="" Point="I/O" />
+          <P91 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P91/A1/KR7/RXDA1/SCL02" AltFunc="" Point="I/O" />
+          <P92 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P92/A2/TIP41/TOP41" AltFunc="" Point="I/O" />
+          <P93 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P93/A3/TIP40/TOP40" AltFunc="" Point="I/O" />
+          <P94 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P94/A4/TIP31/TOP31" AltFunc="" Point="I/O" />
+          <P95 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P95/A5/TIP30/TOP30" AltFunc="" Point="I/O" />
+          <P96 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P96/A6/TIP21/TOP21" AltFunc="" Point="I/O" />
+          <P97 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="P97/A7/SIB1/TIP20/TOP20" AltFunc="" Point="I/O" />
+          <P98 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P98/A8/SOB1" AltFunc="" Point="I/O" />
+          <P99 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P99//A9/SCKB1" AltFunc="" Point="I/O" />
+          <P910 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P910/A10/SIB3" AltFunc="" Point="I/O" />
+          <P911 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P911/A11/SOB3" AltFunc="" Point="I/O" />
+          <P912 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P912/A12/SCKB3" AltFunc="" Point="I/O" />
+          <P913 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P913/A13/INTP4" AltFunc="" Point="I/O" />
+          <P914 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P914/A14/INTP5/TIP51/TOP51" AltFunc="" Point="I/O" />
+          <P915 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="P915/A15/INTP6/TIP50/TOP50" AltFunc="" Point="I/O" />
+        </Port9>
+        <PortCD Chip="V850ESJJ3" PortOnly="true">
+          <PCD0 Name="PCD0" AltFunc="" Point="I/O" />
+          <PCD1 Name="PCD1" AltFunc="" Point="I/O" />
+          <PCD2 Name="PCD2" AltFunc="" Point="I/O" />
+          <PCD3 Name="PCD3" AltFunc="" Point="I/O" />
+        </PortCD>
+        <PortCM>
+          <PCM0 Name="PCM0/WAIT" AltFunc="" Point="I/O" />
+          <PCM1 Name="PCM1/CLKOUT" AltFunc="" Point="I/O" />
+          <PCM2 Name="PCM2/HLDAK" AltFunc="" Point="I/O" />
+          <PCM3 Name="PCM3/HLDRQ" AltFunc="" Point="I/O" />
+          <PCM4 Chip="V850ESJJ3" Name="PCM4" AltFunc="" Point="I/O" />
+          <PCM5 Chip="V850ESJJ3" Name="PCM5" AltFunc="" Point="I/O" />
+        </PortCM>
+        <PortCS Chip="V850ESJJ3">
+          <PCS0 Name="PCS0/CS0" AltFunc="" Point="I/O" />
+          <PCS1 Name="PCS1/CS1" AltFunc="" Point="I/O" />
+          <PCS2 Name="PCS2/CS2" AltFunc="" Point="I/O" />
+          <PCS3 Name="PCS3/CS3" AltFunc="" Point="I/O" />
+          <PCS4 Name="PCS4" AltFunc="" Point="I/O" />
+          <PCS5 Name="PCS5" AltFunc="" Point="I/O" />
+          <PCS6 Name="PCS6" AltFunc="" Point="I/O" />
+          <PCS7 Name="PCS7" AltFunc="" Point="I/O" />
+        </PortCS>
+        <PortCT>
+          <PCT0 Name="PCT0/WR0" AltFunc="" Point="I/O" />
+          <PCT1 Name="PCT1/WR1" AltFunc="" Point="I/O" />
+          <PCT2 Chip="V850ESJJ3" Name="PCT2" AltFunc="" Point="I/O" />
+          <PCT3 Chip="V850ESJJ3" Name="PCT3" AltFunc="" Point="I/O" />
+          <PCT4 Name="PCT4/RD" AltFunc="" Point="I/O" />
+          <PCT5 Chip="V850ESJJ3" Name="PCT5" AltFunc="" Point="I/O" />
+          <PCT6 Name="PCT6/ASTB" AltFunc="" Point="I/O" />
+          <PCT7 Chip="V850ESJJ3" Name="PCT7" AltFunc="" Point="I/O" />
+        </PortCT>
+        <PortDH>
+          <PDH0 Name="PDH0/A16" AltFunc="" Point="I/O" />
+          <PDH1 Name="PDH1/A17" AltFunc="" Point="I/O" />
+          <PDH2 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="PDH2/A18" AltFunc="" Point="I/O" />
+          <PDH3 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="PDH3/A19" AltFunc="" Point="I/O" />
+          <PDH4 Chip="V850ESJG3,V850ESJG3L,V850ESJJ3" Name="PDH4/A20" AltFunc="" Point="I/O" />
+          <PDH5 Chip="V850ESJG3,DF3737,DF3738,V850ESJJ3" Name="PDH5/A21" AltFunc="" Point="I/O" />
+          <PDH6 Chip="V850ESJJ3" Name="PDH6/A22" AltFunc="" Point="I/O" />
+          <PDH7 Chip="V850ESJJ3" Name="PDH7/A23" AltFunc="" Point="I/O" />
+        </PortDH>
+        <PortDL>
+          <PDL0 Name="PDL0/AD0" AltFunc="" Point="I/O" />
+          <PDL1 Name="PDL1/AD1" AltFunc="" Point="I/O" />
+          <PDL2 Name="PDL2/AD2" AltFunc="" Point="I/O" />
+          <PDL3 Name="PDL3/AD3" AltFunc="" Point="I/O" />
+          <PDL4 Name="PDL4/AD4" AltFunc="" Point="I/O" />
+          <PDL5 Name="PDL5/AD5/FLMD1" AltFunc="" Point="I/O" />
+          <PDL6 Name="PDL6/AD6" AltFunc="" Point="I/O" />
+          <PDL7 Name="PDL7/AD7" AltFunc="" Point="I/O" />
+          <PDL8 Name="PDL8/AD8" AltFunc="" Point="I/O" />
+          <PDL9 Name="PDL9/AD9" AltFunc="" Point="I/O" />
+          <PDL10 Name="PDL10/AD10" AltFunc="" Point="I/O" />
+          <PDL11 Name="PDL11/AD11" AltFunc="" Point="I/O" />
+          <PDL12 Name="PDL12/AD12" AltFunc="" Point="I/O" />
+          <PDL13 Name="PDL13/AD13" AltFunc="" Point="I/O" />
+          <PDL14 Name="PDL14/AD14" AltFunc="" Point="I/O" />
+          <PDL15 Name="PDL15/AD15" AltFunc="" Point="I/O" />
+        </PortDL>
+      </PORT>
+      <INT>
+        <INTP>
+          <NMI Port="P02" Point="I" />
+          <INTP0 Port="P03" Point="I" />
+          <INTP1 Port="P04" Point="I" />
+          <INTP2 Port="P05" Point="I" />
+          <INTP3 Port="P06" Point="I" />
+          <INTP4 Port="P913" Point="I" />
+          <INTP5 Port="P914" Point="I" />
+          <INTP6 Port="P915" Point="I" />
+          <INTP7 Port="P31" Point="I" />
+          <INTP8 Chip="V850ESJJ3" Port="P80" Point="I" />
+        </INTP>
+        <KEY>
+          <KR0 Port="P50" Point="I" />
+          <KR1 Port="P51" Point="I" />
+          <KR2 Port="P52" Point="I" />
+          <KR3 Port="P53" Point="I" />
+          <KR4 Port="P54" Point="I" />
+          <KR5 Port="P55" Point="I" />
+          <KR6 Port="P90" Point="I" />
+          <KR7 Port="P91" Point="I" />
+        </KEY>
+      </INT>
+      <Serial>
+        <UARTA0>
+          <ASCKA0 Port="P32" Point="I" />
+          <TXDA0 Port="P30" Point="O" />
+          <RXDA0 Port="P31" Point="I" />
+        </UARTA0>
+        <UARTA1>
+          <TXDA1 Port="P90" Point="O" />
+          <RXDA1 Port="P91" Point="I" />
+        </UARTA1>
+        <UARTA2>
+          <TXDA2 Port="P38" Point="O" />
+          <RXDA2 Port="P39" Point="I" />
+        </UARTA2>
+        <UARTA3 Chip="V850ESJJ3">
+          <TXDA3 Port="P81" Point="O" />
+          <RXDA3 Port="P80" Point="I" />
+        </UARTA3>
+        <CSIB0>
+          <SIB0 Port="P40" Point="I" />
+          <SOB0 Port="P41" Point="O" />
+          <SCKB0 Port="P42" RealName="_SCKB0" Point="I/O" />
+        </CSIB0>
+        <CSIB1>
+          <SIB1 Port="P97" Point="I" />
+          <SOB1 Port="P98" Point="O" />
+          <SCKB1 Port="P99" RealName="_SCKB1" Point="I/O" />
+        </CSIB1>
+        <CSIB2>
+          <SIB2 Port="P53" Point="I" />
+          <SOB2 Port="P54" Point="O" />
+          <SCKB2 Port="P55" RealName="_SCKB2" Point="I/O" />
+        </CSIB2>
+        <CSIB3 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L">
+          <SIB3 Port="P910" Point="I" />
+          <SOB3 Port="P911" Point="O" />
+          <SCKB3 Port="P912" RealName="_SCKB3" Point="I/O" />
+        </CSIB3>
+        <CSIB4 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L">
+          <SIB4 Port="P31" Point="I" />
+          <SOB4 Port="P30" Point="O" />
+          <SCKB4 Port="P32" RealName="_SCKB4" Point="I/O" />
+        </CSIB4>
+        <CSIB5 Chip="V850ESJJ3">
+          <SIB5 Port="P66" Point="I" />
+          <SOB5 Port="P67" Point="O" />
+          <SCKB5 Port="P68" RealName="_SCKB5" Point="I/O" />
+        </CSIB5>
+        <IIC00>
+          <SDA00 Port="P38" Point="I/O" CheckNch="true" />
+          <SCL00 Port="P39" Point="I/O" CheckNch="true" />
+        </IIC00>
+        <IIC01>
+          <SDA01 Port="P40" Point="I/O" CheckNch="true" />
+          <SCL01 Port="P41" Point="I/O" CheckNch="true" />
+        </IIC01>
+        <IIC02 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L">
+          <SDA02 Port="P90" Point="I/O" CheckNch="true" />
+          <SCL02 Port="P91" Point="I/O" CheckNch="true" />
+        </IIC02>
+      </Serial>
+      <AD>
+        <ADTRG Port="P03" Point="I" />
+        <ANI0 Port="P70" Point="I" />
+        <ANI1 Port="P71" Point="I" />
+        <ANI2 Port="P72" Point="I" />
+        <ANI3 Port="P73" Point="I" />
+        <ANI4 Port="P74" Point="I" />
+        <ANI5 Port="P75" Point="I" />
+        <ANI6 Port="P76" Point="I" />
+        <ANI7 Port="P77" Point="I" />
+        <ANI8 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" Port="P78" Point="I" />
+        <ANI9 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" Port="P79" Point="I" />
+        <ANI10 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" Port="P710" Point="I" />
+        <ANI11 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" Port="P711" Point="I" />
+        <ANI12 Chip="V850ESJJ3" Port="P712" Point="I" />
+        <ANI13 Chip="V850ESJJ3" Port="P713" Point="I" />
+        <ANI14 Chip="V850ESJJ3" Port="P714" Point="I" />
+        <ANI15 Chip="V850ESJJ3" Port="P715" Point="I" />
+      </AD>
+      <DA>
+        <DA0>
+          <ANO0 Port="P10" Point="O" />
+        </DA0>
+        <DA1 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3">
+          <ANO1 Port="P11" Point="O" />
+        </DA1>
+      </DA>
+      <Timer>
+        <TMP0>
+          <TIP00 Port="P32" Point="I" />
+          <TOP00 Port="P32" Point="O" />
+          <TIP01 Port="P33" Point="I" />
+          <TOP01 Port="P33" Point="O" />
+        </TMP0>
+        <TMP1>
+          <TIP10 Port="P34" Point="I" />
+          <TOP10 Port="P34" Point="O" />
+          <TIP11 Port="P35" Point="I" />
+          <TOP11 Port="P35" Point="O" />
+        </TMP1>
+        <TMP2>
+          <TIP20 Port="P97" Point="I" />
+          <TOP20 Port="P97" Point="O" />
+          <TIP21 Port="P96" Point="I" />
+          <TOP21 Port="P96" Point="O" />
+        </TMP2>
+        <TMP3 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3">
+          <TIP30 Port="P95" Point="I" />
+          <TOP30 Port="P95" Point="O" />
+          <TIP31 Port="P94" Point="I" />
+          <TOP31 Port="P94" Point="O" />
+        </TMP3>
+        <TMP4 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3">
+          <TIP40 Port="P93" Point="I" />
+          <TOP40 Port="P93" Point="O" />
+          <TIP41 Port="P92" Point="I" />
+          <TOP41 Port="P92" Point="O" />
+        </TMP4>
+        <TMP5>
+          <TIP50 Port="P915" Point="I" />
+          <TOP50 Port="P915" Point="O" />
+          <TIP51 Port="P914" Point="I" />
+          <TOP51 Port="P914" Point="O" />
+        </TMP5>
+        <TMP6 Chip="V850ESJJ3">
+          <TIP60 Port="P01" Point="I" />
+          <TOP60 Port="P01" Point="O" />
+          <TIP61 Port="P00" Point="I" />
+          <TOP61 Port="P00" Point="O" />
+        </TMP6>
+        <TMP7 Chip="V850ESJJ3">
+          <TIP70 Port="P69" Point="I" />
+          <TOP70 Port="P69" Point="O" />
+          <TIP71 Port="P610" Point="I" />
+          <TOP71 Port="P611" Point="O" />
+        </TMP7>
+        <TMP8 Chip="V850ESJJ3">
+          <TIP80 Port="P612" Point="I" />
+          <TOP80 Port="P612" Point="O" />
+          <TIP81 Port="P613" Point="I" />
+          <TOP81 Port="P613" Point="O" />
+        </TMP8>
+        <TMQ0>
+          <TIQ00 Port="P53" Point="I" />
+          <TIQ01 Port="P50" Point="I" />
+          <TIQ02 Port="P51" Point="I" />
+          <TIQ03 Port="P52" Point="I" />
+          <TOQ00 Port="P53" Point="O" />
+          <TOQ01 Port="P50" Point="O" />
+          <TOQ02 Port="P51" Point="O" />
+          <TOQ03 Port="P52" Point="O" />
+        </TMQ0>
+      </Timer>
+      <RTO>
+        <RTO0>
+          <RTP00 Port="P50" Point="O" />
+          <RTP01 Port="P51" Point="O" />
+          <RTP02 Port="P52" Point="O" />
+          <RTP03 Port="P53" Point="O" />
+          <RTP04 Port="P54" Point="O" />
+          <RTP05 Port="P55" Point="O" />
+        </RTO0>
+        <RTO1 Chip="V850ESJJ3">
+          <RTP10 Port="P60" Point="O" />
+          <RTP11 Port="P61" Point="O" />
+          <RTP12 Port="P62" Point="O" />
+          <RTP13 Port="P63" Point="O" />
+          <RTP14 Port="P64" Point="O" />
+          <RTP15 Port="P65" Point="O" />
+        </RTO1>
+      </RTO>
+      <Others>
+        <Power>
+          <AVREF0 AltFunc="AVREF0" Point="-" />
+          <AVSS AltFunc="AVSS" Point="-" />
+          <VDD AltFunc="VDD" Point="-" />
+          <VSS AltFunc="VSS" Point="-" />
+          <EVSS AltFunc="EVSS" Point="-" />
+          <EVDD AltFunc="EVDD" Point="-" />
+        </Power>
+        <Regular>
+          <REGC AltFunc="REGC" Point="-" />
+        </Regular>
+        <RESET AltFunc="RESET" RealName="_RESET" Point="I" />
+      </Others>
+    </PIN>
+    <INT>
+      <System>
+        <INTWDT2 InUse="0" ISR="MD_INTWDT2" />
+      </System>
+      <INT>
+        <INTP>
+          <NMI InUse="0" ISR="MD_INTNMI" />
+          <INTP0 InUse="0" ISR="MD_INTP0" />
+          <INTP1 InUse="0" ISR="MD_INTP1" />
+          <INTP2 InUse="0" ISR="MD_INTP2" />
+          <INTP3 InUse="0" ISR="MD_INTP3" />
+          <INTP4 InUse="0" ISR="MD_INTP4" />
+          <INTP5 InUse="0" ISR="MD_INTP5" />
+          <INTP6 InUse="0" ISR="MD_INTP6" />
+          <INTP7 InUse="0" ISR="MD_INTP7" />
+          <INTP8 Chip="V850ESJJ3" InUse="0" ISR="MD_INTP8" />
+        </INTP>
+        <KEY>
+          <INTKR InUse="0" ISR="MD_INTKR" />
+        </KEY>
+      </INT>
+      <Serial>
+        <UARTA0>
+          <INTUA0R InUse="0" ISR="MD_INTUA0R" />
+          <INTUA0T InUse="0" ISR="MD_INTUA0T" />
+        </UARTA0>
+        <UARTA1>
+          <INTUA1R InUse="0" ISR="MD_INTUA1R" />
+          <INTUA1T InUse="0" ISR="MD_INTUA1T" />
+        </UARTA1>
+        <UARTA2>
+          <INTUA2R InUse="0" ISR="MD_INTUA2R" IsDMATrigger="true" />
+          <INTUA2T InUse="0" ISR="MD_INTUA2T" IsDMATrigger="true" />
+        </UARTA2>
+        <UARTA3 Chip="DF3792,DF3793,V850ESJJ3">
+          <INTUA3R InUse="0" ISR="MD_INTUA3R" />
+          <INTUA3T InUse="0" ISR="MD_INTUA3T" />
+        </UARTA3>
+        <CSIB0>
+          <INTCB0R InUse="0" ISR="MD_INTCB0R" />
+          <INTCB0T InUse="0" ISR="MD_INTCB0T" />
+        </CSIB0>
+        <CSIB1>
+          <INTCB1R InUse="0" ISR="MD_INTCB1R" />
+          <INTCB1T InUse="0" ISR="MD_INTCB1T" />
+        </CSIB1>
+        <CSIB2>
+          <INTCB2R InUse="0" ISR="MD_INTCB2R" />
+          <INTCB2T InUse="0" ISR="MD_INTCB2T" />
+        </CSIB2>
+        <CSIB3 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L">
+          <INTCB3R InUse="0" ISR="MD_INTCB3R" />
+          <INTCB3T InUse="0" ISR="MD_INTCB3T" />
+        </CSIB3>
+        <CSIB4 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L">
+          <INTCB4R InUse="0" ISR="MD_INTCB4R" />
+          <INTCB4T InUse="0" ISR="MD_INTCB4T" />
+        </CSIB4>
+        <CSIB5 Chip="V850ESJJ3">
+          <INTCB5R InUse="0" ISR="MD_INTCB5R" />
+          <INTCB5T InUse="0" ISR="MD_INTCB5T" />
+        </CSIB5>
+        <IIC00>
+          <INTIIC0 InUse="0" ISR="MD_INTIIC0" />
+        </IIC00>
+        <IIC01>
+          <INTIIC1 InUse="0" ISR="MD_INTIIC1" />
+        </IIC01>
+        <IIC02 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L">
+          <INTIIC2 InUse="0" ISR="MD_INTIIC2" />
+        </IIC02>
+      </Serial>
+      <AD>
+        <INTAD InUse="0" ISR="MD_INTAD" />
+      </AD>
+      <Timer>
+        <TMP0>
+          <INTTP0OV InUse="0" ISR="MD_INTTP0OV" />
+          <INTTP0CC0 InUse="0" ISR="MD_INTTP0CC0" />
+          <INTTP0CC1 InUse="0" ISR="MD_INTTP0CC1" />
+        </TMP0>
+        <TMP1>
+          <INTTP1OV InUse="0" ISR="MD_INTTP1OV" />
+          <INTTP1CC0 InUse="0" ISR="MD_INTTP1CC0" />
+          <INTTP1CC1 InUse="0" ISR="MD_INTTP1CC1" />
+        </TMP1>
+        <TMP2>
+          <INTTP2OV InUse="0" ISR="MD_INTTP2OV" />
+          <INTTP2CC0 InUse="0" ISR="MD_INTTP2CC0" />
+          <INTTP2CC1 InUse="0" ISR="MD_INTTP2CC1" />
+        </TMP2>
+        <TMP3 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3">
+          <INTTP3OV InUse="0" ISR="MD_INTTP3OV" />
+          <INTTP3CC0 InUse="0" ISR="MD_INTTP3CC0" />
+          <INTTP3CC1 InUse="0" ISR="MD_INTTP3CC1" />
+        </TMP3>
+        <TMP4 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3">
+          <INTTP4OV InUse="0" ISR="MD_INTTP4OV" />
+          <INTTP4CC0 InUse="0" ISR="MD_INTTP4CC0" />
+          <INTTP4CC1 InUse="0" ISR="MD_INTTP4CC1" />
+        </TMP4>
+        <TMP5>
+          <INTTP5OV InUse="0" ISR="MD_INTTP5OV" />
+          <INTTP5CC0 InUse="0" ISR="MD_INTTP5CC0" />
+          <INTTP5CC1 InUse="0" ISR="MD_INTTP5CC1" />
+        </TMP5>
+        <TMP6 Chip="V850ESJJ3">
+          <INTTP6OV InUse="0" ISR="MD_INTTP6OV" />
+          <INTTP6CC0 InUse="0" ISR="MD_INTTP6CC0" />
+          <INTTP6CC1 InUse="0" ISR="MD_INTTP6CC1" />
+        </TMP6>
+        <TMP7 Chip="V850ESJJ3">
+          <INTTP7OV InUse="0" ISR="MD_INTTP7OV" />
+          <INTTP7CC0 InUse="0" ISR="MD_INTTP7CC0" />
+          <INTTP7CC1 InUse="0" ISR="MD_INTTP7CC1" />
+        </TMP7>
+        <TMP8 Chip="V850ESJJ3">
+          <INTTP8OV InUse="0" ISR="MD_INTTP8OV" />
+          <INTTP8CC0 InUse="0" ISR="MD_INTTP8CC0" />
+          <INTTP8CC1 InUse="0" ISR="MD_INTTP8CC1" />
+        </TMP8>
+        <TMQ0>
+          <INTTQ0OV InUse="0" ISR="MD_INTTQ0OV" />
+          <INTTQ0CC0 InUse="0" ISR="MD_INTTQ0CC0" />
+          <INTTQ0CC1 InUse="0" ISR="MD_INTTQ0CC1" />
+          <INTTQ0CC2 InUse="0" ISR="MD_INTTQ0CC2" />
+          <INTTQ0CC3 InUse="0" ISR="MD_INTTQ0CC3" />
+        </TMQ0>
+        <TMM0>
+          <INTTM0EQ0 InUse="0" ISR="MD_INTTM0EQ0" />
+        </TMM0>
+      </Timer>
+      <WatchTimer>
+        <INTWTI InUse="0" ISR="MD_INTWTI" />
+        <INTWT InUse="0" ISR="MD_INTWT" />
+      </WatchTimer>
+      <DMA>
+        <DMA0>
+          <INTDMA0 InUse="0" ISR="MD_INTDMA0" />
+        </DMA0>
+        <DMA1>
+          <INTDMA1 InUse="0" ISR="MD_INTDMA1" />
+        </DMA1>
+        <DMA2>
+          <INTDMA2 InUse="0" ISR="MD_INTDMA2" />
+        </DMA2>
+        <DMA3>
+          <INTDMA3 InUse="0" ISR="MD_INTDMA3" />
+        </DMA3>
+      </DMA>
+      <LVI>
+        <INTLVI InUse="0" ISR="MD_INTLVI" IsDMATrigger="true" />
+      </LVI>
+    </INT>
+    <FUNC>
+      <Common InUse="true">
+        <CG_main.c UserName="CG_main.c" LibName="main.c" InUse="2" IsLibrary="false">
+          <Type main="void main(void)" />
+          <main UserName="main" FixedName="" LibName="main" InUse="2" ForRTOS="false" />
+        </CG_main.c>
+        <CG_systeminit.c UserName="CG_systeminit.c" LibName="systeminit.c" InUse="1">
+          <Type systeminit="void systeminit(void)" />
+          <systeminit UserName="systeminit" LibName="systeminit" InUse="1" />
+        </CG_systeminit.c>
+        <CG_macrodriver.h UserName="CG_macrodriver.h" LibName="macrodriver.h" InUse="1" />
+        <CG_userdefine.h UserName="CG_userdefine.h" LibName="userdefine.h" InUse="1" />
+        <CG_lk.dir UserName="CG_lk.dir" LibName="lk.dir" IsLibrary="false" Compiler="CA850" InUse="1" />
+        <CG_start.s UserName="CG_start.s" LibName="start.s" IsLibrary="false" Compiler="CA850" InUse="1" />
+        <CG_inttab.s UserName="CG_inttab.s" LibName="inttab.s" Compiler="CA850,GHS850" InUse="1" />
+        <DF_ghs.head UserName="DF_ghs.head" CplName="" LibName="df_ghs.head" Compiler="GHS850" Visible="false" InUse="1" />
+        <io_macros.head UserName="io_macros.head" CplName="" LibName="io_macros.head" Compiler="GHS850" Visible="false" InUse="1" />
+        <CG_GHS850.lx UserName="CG_GHS850.lx" LibName="GHS850.lx" Visible="false" IsLibrary="false" Compiler="GHS850" InUse="1" />
+        <CG_mdt.prj UserName="CG_mdt.prj" Visible="false" IsLibrary="false" ForAP="true" LibName="mdt.prj" Compiler="CA850" InUse="1" />
+        <CG_mdt.prw UserName="CG_mdt.prw" Visible="false" IsLibrary="false" ForAP="true" LibName="mdt.prw" Compiler="CA850" InUse="1" />
+        <CG_startup.s UserName="CG_startup.s" LibName="startup.s" IsLibrary="false" Compiler="GHS850" InUse="1" />
+        <CG_mdt.eww UserName="CG_mdt.eww" Visible="false" IsLibrary="false" LibName="mdt.eww" Compiler="EW850" InUse="1" />
+        <CG_mdt.ewp UserName="CG_mdt.ewp" Visible="false" IsLibrary="false" LibName="mdt.ewp" Compiler="EW850" InUse="1" />
+        <CG_mdt.gpj UserName="CG_mdt.gpj" Visible="false" IsLibrary="false" LibName="mdt.gpj" Compiler="GHS850" InUse="1" />
+        <CG_mdt.gpw UserName="CG_mdt.gpw" Visible="false" IsLibrary="false" LibName="mdt.gpw" Compiler="GHS850" InUse="1" />
+        <CG_mdlnk.xcl UserName="CG_mdlnk.xcl" Visible="false" IsLibrary="false" LibName="md_lnk.xcl" Compiler="EW850" InUse="1" />
+        <CG_option.s85 UserName="CG_option.s85" LibName="option.s" Compiler="EW850" InUse="1" />
+      </Common>
+      <System InUse="1">
+        <CG_system.c UserName="CG_system.c" LibName=".c" InUse="1">
+          <Type CLOCK_Init="void CLOCK_Init(void)" CG_ChangeFrequency="MD_STATUS CG_ChangeFrequency(enum CPUClock clock)" CG_SelectPowerSaveMode="MD_STATUS CG_SelectPowerSaveMode(enum PSLevel level)" CG_ChangeClockMode="MD_STATUS CG_ChangeClockMode(enum ClockMode mode)" CG_SelectStabTime="MD_STATUS CG_SelectStabTime(enum StabTime waittime)" CG_SelectPllMode="MD_STATUS CG_SelectPllMode(enum PllMode pllmode)" WDT2_Restart="void WDT2_Restart(void)" CRC_Start="void CRC_Start(void)" CRC_SetData="void CRC_SetData(UCHAR data)" CRC_GetResult="void CRC_GetResult(USHORT *result)" />
+          <CLOCK_Init UserName="CLOCK_Init" LibName="CLOCK_Init" InUse="1" gInit="1" />
+          <CG_ChangeFrequency UserName="CG_ChangeFrequency" LibName="CG_ChangeFrequency" InUse="0" />
+          <CG_SelectPowerSaveMode UserName="CG_SelectPowerSaveMode" LibName="CG_SelectPowerSaveMode" InUse="0" />
+          <CG_ChangeClockMode UserName="CG_ChangeClockMode" LibName="CG_ChangeClockMode" InUse="0" />
+          <CG_SelectStabTime UserName="CG_SelectStabTime" LibName="CG_SelectStabTime" InUse="0" />
+          <CG_SelectPllMode UserName="CG_SelectPllMode" LibName="CG_SelectPllMode" InUse="0" />
+          <WDT2_Restart UserName="WDT2_Restart" LibName="WDT2_Restart" InUse="1" />
+          <CRC>
+            <CRC_Start NotSubMacro="" UserName="CRC_Start" LibName="CRC_Start" InUse="0" />
+            <CRC_SetData NotSubMacro="" UserName="CRC_SetData" LibName="CRC_SetData" InUse="0" />
+            <CRC_GetResult NotSubMacro="" UserName="CRC_GetResult" LibName="CRC_GetResult" InUse="0" />
+          </CRC>
+        </CG_system.c>
+        <CG_system_user.c UserName="CG_system_user.c" LibName="_user.c" InUse="1">
+          <Type Clock_UserInit="void CLOCK_UserInit(void)" CG_ReadResetSource="void CG_ReadResetSource(void)" MD_INTWDT2="__interrupt void MD_INTWDT2(void)" />
+          <CLOCK_UserInit UserName="CLOCK_UserInit" LibName="Clock_UserInit" InUse="0" />
+          <CG_ReadResetSource UserName="CG_ReadResetSource" LibName="CG_ReadResetSource" Init="0" InUse="1" />
+          <MD_INTWDT2 UserName="MD_INTWDT2" LibName="MD_INTWDT2" INTHandle="" InUse="0" />
+        </CG_system_user.c>
+        <CG_system.h UserName="CG_system.h" LibName=".h" InUse="1" />
+      </System>
+      <BUS InUse="">
+        <CG_bus.c UserName="CG_bus.c" LibName=".c" InUse="">
+          <Type BUS_Init="void BUS_Init(void)" />
+          <BUS_Init UserName="BUS_Init" LibName="BUS_Init" InUse="" Init="1" />
+        </CG_bus.c>
+        <CG_bus_user.c UserName="CG_bus_user.c" LibName="_user.c" InUse="">
+          <Type BUS_UserInit="void BUS_UserInit(void)" />
+          <BUS_UserInit UserName="BUS_UserInit" LibName="BUS_UserInit" InUse="" />
+        </CG_bus_user.c>
+        <CG_bus.h InUse="CG_bus.h" LibName=".h" UserName="CG_bus.h" />
+      </BUS>
+      <PORT InUse="">
+        <CG_port.c UserName="CG_port.c" LibName=".c" InUse="">
+          <Type PORT_Init="void PORT_Init(void)" PORT_ChangePmnInput3="void PORT_ChangePmnInput3(BOOL enablePU, BOOL enableTTL)" PORT_ChangePmnInput2="void PORT_ChangePmnInput2(BOOL enablePU)" PORT_ChangePmnInput1="void PORT_ChangePmnInput1(BOOL enableTTL)" PORT_ChangePmnInput0="void PORT_ChangePmnInput0(void)" PORT_ChangePmnOutput1="void PORT_ChangePmnOutput1(BOOL enableNch, BOOL initialValue)" PORT_ChangePmnOutput0="void PORT_ChangePmnOutput0(BOOL initialValue)" />
+          <PORT_Init UserName="PORT_Init" LibName="PORT_Init" InUse="" Init="0" />
+        </CG_port.c>
+        <CG_port_user.c UserName="CG_port_user.c" LibName="_user.c" InUse="">
+          <Type PORT_UserInit="void PORT_UserInit(void)" />
+          <PORT_UserInit UserName="PORT_UserInit" LibName="PORT_UserInit" InUse="" />
+        </CG_port_user.c>
+        <CG_port.h UserName="CG_port.h" LibName=".h" InUse="" />
+      </PORT>
+      <INT InUse="">
+        <CG_int.c UserName="CG_int.c" LibName=".c" InUse="">
+          <Type INTP_Init="void INTP_Init(void)" INTPn_Enable="void INTPn_Enable(void)" INTPn_Disable="void INTPn_Disable(void)" KEY_Init="void KEY_Init(void)" KEY_Enable="void KEY_Enable(void)" KEY_Disable="void KEY_Disable(void)" INT_MaskableInterruptEnable="void INT_MaskableInterruptEnable(enum MaskableSource name, BOOL enableflag)" />
+          <INTP>
+            <INTP_Init UserName="INTP_Init" LibName="INTP_Init" InUse="" Init="2" />
+            <INT_MaskableInterruptEnable UserName="INT_MaskableInterruptEnable" LibName="INT_MaskableInterruptEnable" InUse="" />
+            <INTP0>
+              <INTP0_Enable UserName="INTP0_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP0_Disable UserName="INTP0_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP0>
+            <INTP1>
+              <INTP1_Enable UserName="INTP1_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP1_Disable UserName="INTP1_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP1>
+            <INTP2>
+              <INTP2_Enable UserName="INTP2_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP2_Disable UserName="INTP2_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP2>
+            <INTP3>
+              <INTP3_Enable UserName="INTP3_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP3_Disable UserName="INTP3_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP3>
+            <INTP4>
+              <INTP4_Enable UserName="INTP4_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP4_Disable UserName="INTP4_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP4>
+            <INTP5>
+              <INTP5_Enable UserName="INTP5_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP5_Disable UserName="INTP5_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP5>
+            <INTP6>
+              <INTP6_Enable UserName="INTP6_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP6_Disable UserName="INTP6_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP6>
+            <INTP7>
+              <INTP7_Enable UserName="INTP7_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP7_Disable UserName="INTP7_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP7>
+            <INTP8 Chip="V850ESJJ3">
+              <INTP8_Enable UserName="INTP8_Enable" LibName="INTPn_Enable" InUse="" />
+              <INTP8_Disable UserName="INTP8_Disable" LibName="INTPn_Disable" InUse="" />
+            </INTP8>
+          </INTP>
+          <KEY>
+            <KEY_Init UserName="KEY_Init" LibName="KEY_Init" InUse="" Init="2" />
+            <KEY_Enable UserName="KEY_Enable" LibName="KEY_Enable" InUse="" />
+            <KEY_Disable UserName="KEY_Disable" LibName="KEY_Disable" InUse="" />
+          </KEY>
+        </CG_int.c>
+        <CG_int_user.c UserName="CG_int_user.c" LibName="_user.c" InUse="">
+          <Type INTP_UserInit="void INTP_UserInit(void)" KEY_UserInit="void KEY_UserInit(void)" MD_INTNMI="__interrupt void MD_INTNMI(void)" MD_INTPn="__interrupt void MD_INTPn(void)" MD_INTKR="__interrupt void MD_INTKR(void)" />
+          <INTP>
+            <INTP_UserInit UserName="INTP_UserInit" LibName="INTP_UserInit" InUse="" />
+            <NMI>
+              <MD_INTNMI UserName="MD_INTNMI" LibName="MD_INTNMI" INTHandle="" InUse="" />
+            </NMI>
+            <INTP0>
+              <MD_INTP0 UserName="MD_INTP0" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP0>
+            <INTP1>
+              <MD_INTP1 UserName="MD_INTP1" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP1>
+            <INTP2>
+              <MD_INTP2 UserName="MD_INTP2" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP2>
+            <INTP3>
+              <MD_INTP3 UserName="MD_INTP3" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP3>
+            <INTP4>
+              <MD_INTP4 UserName="MD_INTP4" INTHandle="" LibName="MD_INTPn" InUse="" />
+            </INTP4>
+            <INTP5>
+              <MD_INTP5 UserName="MD_INTP5" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP5>
+            <INTP6>
+              <MD_INTP6 UserName="MD_INTP6" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP6>
+            <INTP7>
+              <MD_INTP7 UserName="MD_INTP7" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP7>
+            <INTP8>
+              <MD_INTP8 Chip="V850ESJJ3" UserName="MD_INTP8" LibName="MD_INTPn" INTHandle="" InUse="" />
+            </INTP8>
+          </INTP>
+          <KEY>
+            <KEY_UserInit UserName="KEY_UserInit" LibName="KEY_UserInit" InUse="" />
+            <MD_INTKR UserName="MD_INTKR" LibName="MD_INTKR" INTHandle="" InUse="" />
+          </KEY>
+        </CG_int_user.c>
+        <CG_int.h UserName="CG_int.h" LibName=".h" InUse="" />
+      </INT>
+      <Serial InUse="">
+        <CG_serial.c Name="CG_serial.c" UserName="CG_serial.c" LibName=".c" InUse="">
+          <Type UARTAn_Init="void UARTAn_Init(void)" UARTAn_Start="void UARTAn_Start(void)" UARTAn_Stop="void UARTAn_Stop(void)" UARTAn_ReceiveData="MD_STATUS UARTAn_ReceiveData(UCHAR *rxbuf, USHORT rxnum)" UARTAn_SendData="MD_STATUS UARTAn_SendData(UCHAR *txbuf, USHORT txnum)" UARTCn_Init="void UARTCn_Init(void)" UARTCn_Start="void UARTCn_Start(void)" UARTCn_Stop="void UARTCn_Stop(void)" UARTCn_ReceiveData="MD_STATUS UARTCn_ReceiveData(UCHAR *rxbuf, USHORT rxnum)" UARTCn_SendData="MD_STATUS UARTCn_SendData(UCHAR *txbuf, USHORT txnum)" CSIBn_Init="void CSIBn_Init(void)" CSIBn_Start="void CSIBn_Start(void)" CSIBn_Stop="void CSIBn_Stop(void)" CSIBn_SendData="MD_STATUS CSIBn_SendData(UCHAR *txbuf, USHORT txnum)" CSIBn_ReceiveData="MD_STATUS CSIBn_ReceiveData(UCHAR *rxbuf, USHORT rxnum)" CSIBn_SendReceiveData="MD_STATUS CSIBn_SendReceiveData(UCHAR *txbuf, USHORT txnum, UCHAR *rxbuf)" IIC0n_Init="void IIC0n_Init(void)" IIC0n_Stop="void IIC0n_Stop(void)" IIC0n_StopCondition="void IIC0n_StopCondition(void)" IIC0n_MasterSendStart="MD_STATUS IIC0n_MasterSendStart(UCHAR adr, UCHAR *txbuf, USHORT txnum, UCHAR wait)" IIC0n_MasterReceiveStart="MD_STATUS IIC0n_MasterReceiveStart(UCHAR adr, UCHAR *rxbuf, USHORT rxnum, UCHAR wait)" IIC0n_SlaveSendStart="void IIC0n_SlaveSendStart(UCHAR *txbuf, USHORT txnum)" IIC0n_SlaveReceiveStart="void IIC0n_SlaveReceiveStart(UCHAR *rxbuf, USHORT rxnum)" />
+          <UARTA0 InUse="">
+            <UARTA0_Init UserName="UARTA0_Init" LibName="UARTAn_Init" InUse="" Init="2" />
+            <UARTA0_Start UserName="UARTA0_Start" LibName="UARTAn_Start" InUse="" />
+            <UARTA0_Stop UserName="UARTA0_Stop" LibName="UARTAn_Stop" InUse="" />
+            <UARTA0_SendData UserName="UARTA0_SendData" LibName="UARTAn_SendData" InUse="" />
+            <UARTA0_ReceiveData UserName="UARTA0_ReceiveData" LibName="UARTAn_ReceiveData" InUse="" />
+          </UARTA0>
+          <UARTA1 InUse="">
+            <UARTA1_Init UserName="UARTA1_Init" LibName="UARTAn_Init" InUse="" Init="2" />
+            <UARTA1_Start UserName="UARTA1_Start" LibName="UARTAn_Start" InUse="" />
+            <UARTA1_Stop UserName="UARTA1_Stop" LibName="UARTAn_Stop" InUse="" />
+            <UARTA1_SendData UserName="UARTA1_SendData" LibName="UARTAn_SendData" InUse="" />
+            <UARTA1_ReceiveData UserName="UARTA1_ReceiveData" LibName="UARTAn_ReceiveData" InUse="" />
+          </UARTA1>
+          <UARTA2 InUse="">
+            <UARTA2_Init UserName="UARTA2_Init" LibName="UARTAn_Init" InUse="" Init="2" />
+            <UARTA2_Start UserName="UARTA2_Start" LibName="UARTAn_Start" InUse="" />
+            <UARTA2_Stop UserName="UARTA2_Stop" LibName="UARTAn_Stop" InUse="" />
+            <UARTA2_SendData UserName="UARTA2_SendData" LibName="UARTAn_SendData" InUse="" />
+            <UARTA2_ReceiveData UserName="UARTA2_ReceiveData" LibName="UARTAn_ReceiveData" InUse="" />
+          </UARTA2>
+          <UARTA3 Chip="DF3792,DF3793,V850ESJJ3" InUse="">
+            <UARTA3_Init UserName="UARTA3_Init" LibName="UARTAn_Init" InUse="" Init="2" />
+            <UARTA3_Start UserName="UARTA3_Start" LibName="UARTAn_Start" InUse="" />
+            <UARTA3_Stop UserName="UARTA3_Stop" LibName="UARTAn_Stop" InUse="" />
+            <UARTA3_SendData UserName="UARTA3_SendData" LibName="UARTAn_SendData" InUse="" />
+            <UARTA3_ReceiveData UserName="UARTA3_ReceiveData" LibName="UARTAn_ReceiveData" InUse="" />
+          </UARTA3>
+          <CSIB0 InUse="">
+            <CSIB0_Init UserName="CSIB0_Init" LibName="CSIBn_Init" InUse="" Init="2" />
+            <CSIB0_Start UserName="CSIB0_Start" LibName="CSIBn_Start" InUse="" />
+            <CSIB0_Stop UserName="CSIB0_Stop" LibName="CSIBn_Stop" InUse="" />
+            <CSIB0_SendData UserName="CSIB0_SendData" LibName="CSIBn_SendData" InUse="" />
+            <CSIB0_ReceiveData UserName="CSIB0_ReceiveData" LibName="CSIBn_ReceiveData" InUse="" />
+            <CSIB0_SendReceiveData UserName="CSIB0_SendReceiveData" LibName="CSIBn_SendReceiveData" InUse="" />
+          </CSIB0>
+          <CSIB1 InUse="">
+            <CSIB1_Init UserName="CSIB1_Init" LibName="CSIBn_Init" InUse="" Init="2" />
+            <CSIB1_Start UserName="CSIB1_Start" LibName="CSIBn_Start" InUse="" />
+            <CSIB1_Stop UserName="CSIB1_Stop" LibName="CSIBn_Stop" InUse="" />
+            <CSIB1_SendData UserName="CSIB1_SendData" LibName="CSIBn_SendData" InUse="" />
+            <CSIB1_ReceiveData UserName="CSIB1_ReceiveData" LibName="CSIBn_ReceiveData" InUse="" />
+            <CSIB1_SendReceiveData UserName="CSIB1_SendReceiveData" LibName="CSIBn_SendReceiveData" InUse="" />
+          </CSIB1>
+          <CSIB2 InUse="">
+            <CSIB2_Init UserName="CSIB2_Init" LibName="CSIBn_Init" InUse="" Init="2" />
+            <CSIB2_Start UserName="CSIB2_Start" LibName="CSIBn_Start" InUse="" />
+            <CSIB2_Stop UserName="CSIB2_Stop" LibName="CSIBn_Stop" InUse="" />
+            <CSIB2_SendData UserName="CSIB2_SendData" LibName="CSIBn_SendData" InUse="" />
+            <CSIB2_ReceiveData UserName="CSIB2_ReceiveData" LibName="CSIBn_ReceiveData" InUse="" />
+            <CSIB2_SendReceiveData UserName="CSIB2_SendReceiveData" LibName="CSIBn_SendReceiveData" InUse="" />
+          </CSIB2>
+          <CSIB3 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" InUse="">
+            <CSIB3_Init UserName="CSIB3_Init" LibName="CSIBn_Init" InUse="" Init="2" />
+            <CSIB3_Start UserName="CSIB3_Start" LibName="CSIBn_Start" InUse="" />
+            <CSIB3_Stop UserName="CSIB3_Stop" LibName="CSIBn_Stop" InUse="" />
+            <CSIB3_SendData UserName="CSIB3_SendData" LibName="CSIBn_SendData" InUse="" />
+            <CSIB3_ReceiveData UserName="CSIB3_ReceiveData" LibName="CSIBn_ReceiveData" InUse="" />
+            <CSIB3_SendReceiveData UserName="CSIB3_SendReceiveData" LibName="CSIBn_SendReceiveData" InUse="" />
+          </CSIB3>
+          <CSIB4 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" InUse="">
+            <CSIB4_Init UserName="CSIB4_Init" LibName="CSIBn_Init" InUse="" Init="2" />
+            <CSIB4_Start UserName="CSIB4_Start" LibName="CSIBn_Start" InUse="" />
+            <CSIB4_Stop UserName="CSIB4_Stop" LibName="CSIBn_Stop" InUse="" />
+            <CSIB4_SendData UserName="CSIB4_SendData" LibName="CSIBn_SendData" InUse="" />
+            <CSIB4_ReceiveData UserName="CSIB4_ReceiveData" LibName="CSIBn_ReceiveData" InUse="" />
+            <CSIB4_SendReceiveData UserName="CSIB4_SendReceiveData" LibName="CSIBn_SendReceiveData" InUse="" />
+          </CSIB4>
+          <CSIB5 Chip="V850ESJJ3" InUse="">
+            <CSIB5_Init UserName="CSIB5_Init" LibName="CSIBn_Init" InUse="" Init="2" />
+            <CSIB5_Start UserName="CSIB5_Start" LibName="CSIBn_Start" InUse="" />
+            <CSIB5_Stop UserName="CSIB5_Stop" LibName="CSIBn_Stop" InUse="" />
+            <CSIB5_SendData UserName="CSIB5_SendData" LibName="CSIBn_SendData" InUse="" />
+            <CSIB5_ReceiveData UserName="CSIB5_ReceiveData" LibName="CSIBn_ReceiveData" InUse="" />
+            <CSIB5_SendReceiveData UserName="CSIB5_SendReceiveData" LibName="CSIBn_SendReceiveData" InUse="" />
+          </CSIB5>
+          <IIC00 InUse="">
+            <IIC00_Init UserName="IIC00_Init" LibName="IIC0n_Init" InUse="" Init="2" />
+            <IIC00_Stop UserName="IIC00_Stop" LibName="IIC0n_Stop" InUse="" />
+            <IIC00_StopCondition UserName="IIC00_StopCondition" LibName="IIC0n_StopCondition" InUse="" />
+            <IIC00_MasterSendStart UserName="IIC00_MasterSendStart" LibName="IIC0n_MasterSendStart" InUse="" />
+            <IIC00_MasterReceiveStart UserName="IIC00_MasterReceiveStart" LibName="IIC0n_MasterReceiveStart" InUse="" />
+            <IIC00_SlaveSendStart UserName="IIC00_SlaveSendStart" LibName="IIC0n_SlaveSendStart" InUse="" />
+            <IIC00_SlaveReceiveStart UserName="IIC00_SlaveReceiveStart" LibName="IIC0n_SlaveReceiveStart" InUse="" />
+          </IIC00>
+          <IIC01 InUse="">
+            <IIC01_Init UserName="IIC01_Init" LibName="IIC0n_Init" InUse="" Init="2" />
+            <IIC01_Stop UserName="IIC01_Stop" LibName="IIC0n_Stop" InUse="" />
+            <IIC01_StopCondition UserName="IIC01_StopCondition" LibName="IIC0n_StopCondition" InUse="" />
+            <IIC01_MasterSendStart UserName="IIC01_MasterSendStart" LibName="IIC0n_MasterSendStart" InUse="" />
+            <IIC01_MasterReceiveStart UserName="IIC01_MasterReceiveStart" LibName="IIC0n_MasterReceiveStart" InUse="" />
+            <IIC01_SlaveSendStart UserName="IIC01_SlaveSendStart" LibName="IIC0n_SlaveSendStart" InUse="" />
+            <IIC01_SlaveReceiveStart UserName="IIC01_SlaveReceiveStart" LibName="IIC0n_SlaveReceiveStart" InUse="" />
+          </IIC01>
+          <IIC02 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" InUse="">
+            <IIC02_Init UserName="IIC02_Init" LibName="IIC0n_Init" InUse="" Init="2" />
+            <IIC02_Stop UserName="IIC02_Stop" LibName="IIC0n_Stop" InUse="" />
+            <IIC02_StopCondition UserName="IIC02_StopCondition" LibName="IIC0n_StopCondition" InUse="" />
+            <IIC02_MasterSendStart UserName="IIC02_MasterSendStart" LibName="IIC0n_MasterSendStart" InUse="" />
+            <IIC02_MasterReceiveStart UserName="IIC02_MasterReceiveStart" LibName="IIC0n_MasterReceiveStart" InUse="" />
+            <IIC02_SlaveSendStart UserName="IIC02_SlaveSendStart" LibName="IIC0n_SlaveSendStart" InUse="" />
+            <IIC02_SlaveReceiveStart UserName="IIC02_SlaveReceiveStart" LibName="IIC0n_SlaveReceiveStart" InUse="" />
+          </IIC02>
+        </CG_serial.c>
+        <CG_serial_user.c UserName="CG_serial_user.c" LibName="_user.c" InUse="">
+          <Type UARTAn_UserInit="void UARTAn_UserInit(void)" UARTAn_ErrorCallback="void UARTAn_ErrorCallback(UCHAR err_type)" UARTAn_ReceiveEndCallback="void UARTAn_ReceiveEndCallback(void)" UARTAn_SendEndCallback="void UARTAn_SendEndCallback(void)" UARTAn_SoftOverRunCallback="void UARTAn_SoftOverRunCallback(UCHAR rx_data)" MD_INTUAnR="__interrupt void MD_INTUAnR(void)" MD_INTUAnT="__interrupt void MD_INTUAnT(void)" UARTCn_UserInit="void UARTCn_UserInit(void)" UARTCn_ErrorCallback="void UARTCn_ErrorCallback(UCHAR err_type)" UARTCn_ReceiveEndCallback="void UARTCn_ReceiveEndCallback(void)" UARTCn_SendEndCallback="void UARTCn_SendEndCallback(void)" UARTCn_SoftOverRunCallback="void UARTCn_SoftOverRunCallback(USHORT rx_data)" MD_INTUCnR="__interrupt void MD_INTUCnR(void)" MD_INTUCnT="__interrupt void MD_INTUCnT(void)" CSIBn_UserInit="void CSIBn_UserInit(void)" CSIBn_ErrorCallback="void CSIBn_ErrorCallback(void)" CSIBn_ReceiveEndCallback="void CSIBn_ReceiveEndCallback(void)" CSIBn_SendEndCallback="void CSIBn_SendEndCallback(void)" MD_INTCBnR="__interrupt void MD_INTCBnR(void)" MD_INTCBnT="__interrupt void MD_INTCBnT(void)" IIC0n_UserInit="void IIC0n_UserInit(void)" IIC0n_MasterReceiveEndCallback="void IIC0n_MasterReceiveEndCallback(void)" IIC0n_MasterSendEndCallback="void IIC0n_MasterSendEndCallback(void)" IIC0n_MasterErrorCallback="void IIC0n_MasterErrorCallback(MD_STATUS flag)" IIC0n_SlaveReceiveEndCallback="void IIC0n_SlaveReceiveEndCallback(void)" IIC0n_SlaveSendEndCallback="void IIC0n_SlaveSendEndCallback(void)" IIC0n_SlaveErrorCallback="void IIC0n_SlaveErrorCallback(MD_STATUS flag)" IIC0n_GetStopConditionCallback="void IIC0n_GetStopConditionCallback(void)" MD_INTIICn="__interrupt void MD_INTIICn(void)" />
+          <UARTA0 InUse="">
+            <UARTA0_UserInit UserName="UARTA0_UserInit" LibName="UARTAn_UserInit" InUse="" />
+            <UARTA0_ErrorCallback UserName="UARTA0_ErrorCallback" LibName="UARTAn_ErrorCallback" InUse="" />
+            <UARTA0_ReceiveEndCallback UserName="UARTA0_ReceiveEndCallback" LibName="UARTAn_ReceiveEndCallback" InUse="" />
+            <UARTA0_SendEndCallback UserName="UARTA0_SendEndCallback" LibName="UARTAn_SendEndCallback" InUse="" />
+            <UARTA0_SoftOverRunCallback UserName="UARTA0_SoftOverRunCallback" LibName="UARTAn_SoftOverRunCallback" InUse="" />
+            <MD_INTUA0R UserName="MD_INTUA0R" LibName="MD_INTUAnR" INTHandle="" InUse="" />
+            <MD_INTUA0T UserName="MD_INTUA0T" LibName="MD_INTUAnT" INTHandle="" InUse="" />
+          </UARTA0>
+          <UARTA1 InUse="">
+            <UARTA1_UserInit UserName="UARTA1_UserInit" LibName="UARTAn_UserInit" InUse="" />
+            <UARTA1_ErrorCallback UserName="UARTA1_ErrorCallback" LibName="UARTAn_ErrorCallback" InUse="" />
+            <UARTA1_ReceiveEndCallback UserName="UARTA1_ReceiveEndCallback" LibName="UARTAn_ReceiveEndCallback" InUse="" />
+            <UARTA1_SendEndCallback UserName="UARTA1_SendEndCallback" LibName="UARTAn_SendEndCallback" InUse="" />
+            <UARTA1_SoftOverRunCallback UserName="UARTA1_SoftOverRunCallback" LibName="UARTAn_SoftOverRunCallback" InUse="" />
+            <MD_INTUA1R UserName="MD_INTUA1R" LibName="MD_INTUAnR" INTHandle="" InUse="" />
+            <MD_INTUA1T UserName="MD_INTUA1T" LibName="MD_INTUAnT" INTHandle="" InUse="" />
+          </UARTA1>
+          <UARTA2 InUse="">
+            <UARTA2_UserInit UserName="UARTA2_UserInit" LibName="UARTAn_UserInit" InUse="" />
+            <UARTA2_ErrorCallback UserName="UARTA2_ErrorCallback" LibName="UARTAn_ErrorCallback" InUse="" />
+            <UARTA2_ReceiveEndCallback UserName="UARTA2_ReceiveEndCallback" LibName="UARTAn_ReceiveEndCallback" InUse="" />
+            <UARTA2_SendEndCallback UserName="UARTA2_SendEndCallback" LibName="UARTAn_SendEndCallback" InUse="" />
+            <UARTA2_SoftOverRunCallback UserName="UARTA2_SoftOverRunCallback" LibName="UARTAn_SoftOverRunCallback" InUse="" />
+            <MD_INTUA2R UserName="MD_INTUA2R" LibName="MD_INTUAnR" INTHandle="" InUse="" />
+            <MD_INTUA2T UserName="MD_INTUA2T" LibName="MD_INTUAnT" INTHandle="" InUse="" />
+          </UARTA2>
+          <UARTA3 Chip="DF3792,DF3793,V850ESJJ3" InUse="">
+            <UARTA3_UserInit UserName="UARTA3_UserInit" LibName="UARTAn_UserInit" InUse="" />
+            <UARTA3_ErrorCallback UserName="UARTA3_ErrorCallback" LibName="UARTAn_ErrorCallback" InUse="" />
+            <UARTA3_ReceiveEndCallback UserName="UARTA3_ReceiveEndCallback" LibName="UARTAn_ReceiveEndCallback" InUse="" />
+            <UARTA3_SendEndCallback UserName="UARTA3_SendEndCallback" LibName="UARTAn_SendEndCallback" InUse="" />
+            <UARTA3_SoftOverRunCallback UserName="UARTA3_SoftOverRunCallback" LibName="UARTAn_SoftOverRunCallback" InUse="" />
+            <MD_INTUA3R UserName="MD_INTUA3R" INTHandle="" LibName="MD_INTUAnR" InUse="" />
+            <MD_INTUA3T UserName="MD_INTUA3T" LibName="MD_INTUAnT" INTHandle="" InUse="" />
+          </UARTA3>
+          <CSIB0 InUse="">
+            <CSIB0_UserInit UserName="CSIB0_UserInit" LibName="CSIBn_UserInit" InUse="" />
+            <CSIB0_ErrorCallback UserName="CSIB0_ErrorCallback" LibName="CSIBn_ErrorCallback" InUse="" />
+            <CSIB0_ReceiveEndCallback UserName="CSIB0_ReceiveEndCallback" LibName="CSIBn_ReceiveEndCallback" InUse="" />
+            <CSIB0_SendEndCallback UserName="CSIB0_SendEndCallback" LibName="CSIBn_SendEndCallback" InUse="" />
+            <MD_INTCB0R UserName="MD_INTCB0R" LibName="MD_INTCBnR" INTHandle="" InUse="" />
+            <MD_INTCB0T UserName="MD_INTCB0T" LibName="MD_INTCBnT" INTHandle="" InUse="" />
+          </CSIB0>
+          <CSIB1 InUse="">
+            <CSIB1_UserInit UserName="CSIB1_UserInit" LibName="CSIBn_UserInit" InUse="" />
+            <CSIB1_ErrorCallback UserName="CSIB1_ErrorCallback" LibName="CSIBn_ErrorCallback" InUse="" />
+            <CSIB1_ReceiveEndCallback UserName="CSIB1_ReceiveEndCallback" LibName="CSIBn_ReceiveEndCallback" InUse="" />
+            <CSIB1_SendEndCallback UserName="CSIB1_SendEndCallback" LibName="CSIBn_SendEndCallback" InUse="" />
+            <MD_INTCB1R UserName="MD_INTCB1R" LibName="MD_INTCBnR" INTHandle="" InUse="" />
+            <MD_INTCB1T UserName="MD_INTCB1T" LibName="MD_INTCBnT" INTHandle="" InUse="" />
+          </CSIB1>
+          <CSIB2 InUse="">
+            <CSIB2_UserInit UserName="CSIB2_UserInit" LibName="CSIBn_UserInit" InUse="" />
+            <CSIB2_ErrorCallback UserName="CSIB2_ErrorCallback" LibName="CSIBn_ErrorCallback" InUse="" />
+            <CSIB2_ReceiveEndCallback UserName="CSIB2_ReceiveEndCallback" LibName="CSIBn_ReceiveEndCallback" InUse="" />
+            <CSIB2_SendEndCallback UserName="CSIB2_SendEndCallback" LibName="CSIBn_SendEndCallback" InUse="" />
+            <MD_INTCB2R UserName="MD_INTCB2R" LibName="MD_INTCBnR" INTHandle="" InUse="" />
+            <MD_INTCB2T UserName="MD_INTCB2T" LibName="MD_INTCBnT" INTHandle="" InUse="" />
+          </CSIB2>
+          <CSIB3 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" InUse="">
+            <CSIB3_UserInit UserName="CSIB3_UserInit" LibName="CSIBn_UserInit" InUse="" />
+            <CSIB3_ErrorCallback UserName="CSIB3_ErrorCallback" LibName="CSIBn_ErrorCallback" InUse="" />
+            <CSIB3_ReceiveEndCallback UserName="CSIB3_ReceiveEndCallback" LibName="CSIBn_ReceiveEndCallback" InUse="" />
+            <CSIB3_SendEndCallback UserName="CSIB3_SendEndCallback" LibName="CSIBn_SendEndCallback" InUse="" />
+            <MD_INTCB3R UserName="MD_INTCB3R" LibName="MD_INTCBnR" INTHandle="" InUse="" />
+            <MD_INTCB3T UserName="MD_INTCB3T" LibName="MD_INTCBnT" INTHandle="" InUse="" />
+          </CSIB3>
+          <CSIB4 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" InUse="">
+            <CSIB4_UserInit UserName="CSIB4_UserInit" LibName="CSIBn_UserInit" InUse="" />
+            <CSIB4_ErrorCallback UserName="CSIB4_ErrorCallback" LibName="CSIBn_ErrorCallback" InUse="" />
+            <CSIB4_ReceiveEndCallback UserName="CSIB4_ReceiveEndCallback" LibName="CSIBn_ReceiveEndCallback" InUse="" />
+            <CSIB4_SendEndCallback UserName="CSIB4_SendEndCallback" LibName="CSIBn_SendEndCallback" InUse="" />
+            <MD_INTCB4R UserName="MD_INTCB4R" LibName="MD_INTCBnR" INTHandle="" InUse="" />
+            <MD_INTCB4T UserName="MD_INTCB4T" LibName="MD_INTCBnT" INTHandle="" InUse="" />
+          </CSIB4>
+          <CSIB5 Chip="V850ESJJ3" InUse="">
+            <CSIB5_UserInit UserName="CSIB5_UserInit" LibName="CSIBn_UserInit" InUse="" />
+            <CSIB5_ErrorCallback UserName="CSIB5_ErrorCallback" LibName="CSIBn_ErrorCallback" InUse="" />
+            <CSIB5_ReceiveEndCallback UserName="CSIB5_ReceiveEndCallback" LibName="CSIBn_ReceiveEndCallback" InUse="" />
+            <CSIB5_SendEndCallback UserName="CSIB5_SendEndCallback" LibName="CSIBn_SendEndCallback" InUse="" />
+            <MD_INTCB5R UserName="MD_INTCB5R" LibName="MD_INTCBnR" INTHandle="" InUse="" />
+            <MD_INTCB5T UserName="MD_INTCB5T" LibName="MD_INTCBnT" INTHandle="" InUse="" />
+          </CSIB5>
+          <IIC00 InUse="">
+            <IIC00_UserInit UserName="IIC00_UserInit" LibName="IIC0n_UserInit" InUse="" />
+            <IIC00_MasterReceiveEndCallback UserName="IIC00_MasterReceiveEndCallback" LibName="IIC0n_MasterReceiveEndCallback" InUse="" />
+            <IIC00_MasterSendEndCallback UserName="IIC00_MasterSendEndCallback" LibName="IIC0n_MasterSendEndCallback" InUse="" />
+            <IIC00_MasterErrorCallback UserName="IIC00_MasterErrorCallback" LibName="IIC0n_MasterErrorCallback" InUse="" />
+            <IIC00_SlaveReceiveEndCallback UserName="IIC00_SlaveReceiveEndCallback" LibName="IIC0n_SlaveReceiveEndCallback" InUse="" />
+            <IIC00_SlaveSendEndCallback UserName="IIC00_SlaveSendEndCallback" LibName="IIC0n_SlaveSendEndCallback" InUse="" />
+            <IIC00_SlaveErrorCallback UserName="IIC00_SlaveErrorCallback" LibName="IIC0n_SlaveErrorCallback" InUse="" />
+            <IIC00_GetStopConditionCallback UserName="IIC00_GetStopConditionCallback" LibName="IIC0n_GetStopConditionCallback" InUse="" />
+            <MD_INTIIC0 UserName="MD_INTIIC0" LibName="MD_INTIICn" INTHandle="" InUse="" />
+          </IIC00>
+          <IIC01 InUse="">
+            <IIC01_UserInit UserName="IIC01_UserInit" LibName="IIC0n_UserInit" InUse="" />
+            <IIC01_MasterReceiveEndCallback UserName="IIC01_MasterReceiveEndCallback" LibName="IIC0n_MasterReceiveEndCallback" InUse="" />
+            <IIC01_MasterSendEndCallback UserName="IIC01_MasterSendEndCallback" LibName="IIC0n_MasterSendEndCallback" InUse="" />
+            <IIC01_MasterErrorCallback UserName="IIC01_MasterErrorCallback" LibName="IIC0n_MasterErrorCallback" InUse="" />
+            <IIC01_SlaveReceiveEndCallback UserName="IIC01_SlaveReceiveEndCallback" LibName="IIC0n_SlaveReceiveEndCallback" InUse="" />
+            <IIC01_SlaveSendEndCallback UserName="IIC01_SlaveSendEndCallback" LibName="IIC0n_SlaveSendEndCallback" InUse="" />
+            <IIC01_SlaveErrorCallback UserName="IIC01_SlaveErrorCallback" LibName="IIC0n_SlaveErrorCallback" InUse="" />
+            <IIC01_GetStopConditionCallback UserName="IIC01_GetStopConditionCallback" LibName="IIC0n_GetStopConditionCallback" InUse="" />
+            <MD_INTIIC1 UserName="MD_INTIIC1" LibName="MD_INTIICn" INTHandle="" InUse="" />
+          </IIC01>
+          <IIC02 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" InUse="">
+            <IIC02_UserInit UserName="IIC02_UserInit" LibName="IIC0n_UserInit" InUse="" />
+            <IIC02_MasterReceiveEndCallback UserName="IIC02_MasterReceiveEndCallback" LibName="IIC0n_MasterReceiveEndCallback" InUse="" />
+            <IIC02_MasterSendEndCallback UserName="IIC02_MasterSendEndCallback" LibName="IIC0n_MasterSendEndCallback" InUse="" />
+            <IIC02_MasterErrorCallback UserName="IIC02_MasterErrorCallback" LibName="IIC0n_MasterErrorCallback" InUse="" />
+            <IIC02_SlaveReceiveEndCallback UserName="IIC02_SlaveReceiveEndCallback" LibName="IIC0n_SlaveReceiveEndCallback" InUse="" />
+            <IIC02_SlaveSendEndCallback UserName="IIC02_SlaveSendEndCallback" LibName="IIC0n_SlaveSendEndCallback" InUse="" />
+            <IIC02_SlaveErrorCallback UserName="IIC02_SlaveErrorCallback" LibName="IIC0n_SlaveErrorCallback" InUse="" />
+            <IIC02_GetStopConditionCallback UserName="IIC02_GetStopConditionCallback" LibName="IIC0n_GetStopConditionCallback" InUse="" />
+            <MD_INTIIC2 UserName="MD_INTIIC2" LibName="MD_INTIICn" INTHandle="" InUse="" />
+          </IIC02>
+        </CG_serial_user.c>
+        <CG_serial.h UserName="CG_serial.h" LibName=".h" InUse="" />
+      </Serial>
+      <AD InUse="">
+        <CG_ad.c UserName="CG_ad.c" LibName=".c" InUse="">
+          <Type AD_Init="void AD_Init(void)" AD_Start="void AD_Start(void)" AD_Stop="void AD_Stop(void)" AD_Read="MD_STATUS AD_Read(USHORT *buffer)" AD_ReadByte="MD_STATUS AD_ReadByte(UCHAR *buffer)" AD_SelectADChannel="MD_STATUS AD_SelectADChannel(enum ADChannel channel)" AD_SetPFTCondition="MD_STATUS AD_SetPFTCondition(UCHAR pftvalue, enum ADPFTMode mode)" />
+          <AD_Init UserName="AD_Init" LibName="AD_Init" InUse="" Init="2" />
+          <AD_Start UserName="AD_Start" LibName="AD_Start" InUse="" />
+          <AD_Stop UserName="AD_Stop" LibName="AD_Stop" InUse="" />
+          <AD_Read UserName="AD_Read" LibName="AD_Read" InUse="" />
+          <AD_ReadByte UserName="AD_ReadByte" LibName="AD_ReadByte" InUse="" />
+          <AD_SelectADChannel UserName="AD_SelectADChannel" LibName="AD_SelectADChannel" InUse="" />
+          <AD_SetPFTCondition UserName="AD_SetPFTCondition" LibName="AD_SetPFTCondition" InUse="" />
+        </CG_ad.c>
+        <CG_ad_user.c UserName="CG_ad_user.c" LibName="_user.c" InUse="">
+          <Type AD_UserInit="void AD_UserInit(void)" MD_INTAD="__interrupt void MD_INTAD(void)" />
+          <AD_UserInit UserName="AD_UserInit" LibName="AD_UserInit" InUse="" />
+          <MD_INTAD UserName="MD_INTAD" LibName="MD_INTAD" INTHandle="" InUse="" />
+        </CG_ad_user.c>
+        <CG_ad.h UserName="CG_ad.h" LibName=".h" InUse="" />
+      </AD>
+      <DA InUse="">
+        <CG_da.c UserName="CG_da.c" LibName=".c" InUse="">
+          <Type DAn_Init="void DAn_Init(void)" DAn_Start="void DAn_Start(void)" DAn_Stop="void DAn_Stop(void)" DAn_SetValue="void DAn_SetValue(UCHAR value)" />
+          <DA0 InUse="">
+            <DA0_Init UserName="DA0_Init" LibName="DAn_Init" InUse="" Init="2" />
+            <DA0_Start UserName="DA0_Start" LibName="DAn_Start" InUse="" />
+            <DA0_Stop UserName="DA0_Stop" LibName="DAn_Stop" InUse="" />
+            <DA0_SetValue UserName="DA0_SetValue" LibName="DAn_SetValue" InUse="" />
+          </DA0>
+          <DA1 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" InUse="">
+            <DA1_Init UserName="DA1_Init" LibName="DAn_Init" InUse="" Init="2" />
+            <DA1_Start UserName="DA1_Start" LibName="DAn_Start" InUse="" />
+            <DA1_Stop UserName="DA1_Stop" LibName="DAn_Stop" InUse="" />
+            <DA1_SetValue UserName="DA1_SetValue" LibName="DAn_SetValue" InUse="" />
+          </DA1>
+        </CG_da.c>
+        <CG_da_user.c UserName="CG_da_user.c" LibName="_user.c" InUse="">
+          <Type DAn_UserInit="void DAn_UserInit(void)" />
+          <DA0 InUse="">
+            <DA0_UserInit UserName="DA0_UserInit" LibName="DAn_UserInit" InUse="" />
+          </DA0>
+          <DA1 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" InUse="">
+            <DA1_UserInit UserName="DA1_UserInit" LibName="DAn_UserInit" InUse="" />
+          </DA1>
+        </CG_da_user.c>
+        <CG_da.h UserName="CG_da.h" LibName=".h" InUse="" />
+      </DA>
+      <Timer InUse="">
+        <CG_timer.c UserName="CG_timer.c" LibName=".c" InUse="">
+          <Type TMPn_Init="void TMPn_Init(void)" TMPn_Start="void TMPn_Start(void)" TMPn_Stop="void TMPn_Stop(void)" TMPn_ChangeTimerCondition="MD_STATUS TMPn_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num)&#xD;&#xA;" TMPn_ChangeDuty="void TMPn_ChangeDuty(UCHAR array_duty)" TMPn_SoftwareTriggerOn="void TMPn_SoftwareTriggerOn(void)" TMPn_GetPulseWidth="void TMPn_GetPulseWidth(ULONG *activewidth, ULONG *inactivewidth)" TMPn_GetFreeRunningValue="MD_STATUS TMPn_GetFreeRunningValue(ULONG *count, enum TMChannel channel)" TMQn_Init="void TMQn_Init(void)" TMQn_Start="void TMQn_Start(void)" TMQn_Stop="void TMQn_Stop(void)" TMQn_ChangeTimerCondition="MD_STATUS TMQn_ChangeTimerCondition(USHORT *array_reg, UCHAR array_num)" TMQn_ChangeDuty="MD_STATUS TMQn_ChangeDuty(UCHAR *array_duty, UCHAR array_num)" TMQn_SoftwareTriggerOn="void TMQn_SoftwareTriggerOn(void)" TMQn_GetPulseWidth="void TMQn_GetPulseWidth(ULONG *activewidth, ULONG *inactivewidth)" TMQn_GetFreeRunningValue="MD_STATUS TMQn_GetFreeRunningValue(ULONG *count, enum TMChannel channel)" TMMn_Init="void TMMn_Init(void)" TMMn_Start="void TMMn_Start(void)" TMMn_Stop="void TMMn_Stop(void)" TMMn_ChangeTimerCondition="void TMMn_ChangeTimerCondition(USHORT regvalue)&#xD;&#xA;" />
+          <TMP0 InUse="">
+            <TMP0_Init UserName="TMP0_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP0_Start UserName="TMP0_Start" LibName="TMPn_Start" InUse="" />
+            <TMP0_Stop UserName="TMP0_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP0_ChangeTimerCondition UserName="TMP0_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP0_ChangeDuty UserName="TMP0_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP0_SoftwareTriggerOn UserName="TMP0_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP0_GetPulseWidth UserName="TMP0_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP0_GetFreeRunningValue UserName="TMP0_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP0>
+          <TMP1 InUse="">
+            <TMP1_Init UserName="TMP1_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP1_Start UserName="TMP1_Start" LibName="TMPn_Start" InUse="" />
+            <TMP1_Stop UserName="TMP1_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP1_ChangeTimerCondition UserName="TMP1_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP1_ChangeDuty UserName="TMP1_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP1_SoftwareTriggerOn UserName="TMP1_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP1_GetPulseWidth UserName="TMP1_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP1_GetFreeRunningValue UserName="TMP1_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP1>
+          <TMP2 InUse="">
+            <TMP2_Init UserName="TMP2_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP2_Start UserName="TMP2_Start" LibName="TMPn_Start" InUse="" />
+            <TMP2_Stop UserName="TMP2_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP2_ChangeTimerCondition UserName="TMP2_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP2_ChangeDuty UserName="TMP2_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP2_SoftwareTriggerOn UserName="TMP2_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP2_GetPulseWidth UserName="TMP2_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP2_GetFreeRunningValue UserName="TMP2_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP2>
+          <TMP3 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3" InUse="">
+            <TMP3_Init UserName="TMP3_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP3_Start UserName="TMP3_Start" LibName="TMPn_Start" InUse="" />
+            <TMP3_Stop UserName="TMP3_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP3_ChangeTimerCondition UserName="TMP3_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP3_ChangeDuty UserName="TMP3_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP3_SoftwareTriggerOn UserName="TMP3_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP3_GetPulseWidth UserName="TMP3_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP3_GetFreeRunningValue UserName="TMP3_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP3>
+          <TMP4 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3" InUse="">
+            <TMP4_Init UserName="TMP4_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP4_Start UserName="TMP4_Start" LibName="TMPn_Start" InUse="" />
+            <TMP4_Stop UserName="TMP4_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP4_ChangeTimerCondition UserName="TMP4_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP4_ChangeDuty UserName="TMP4_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP4_SoftwareTriggerOn UserName="TMP4_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP4_GetPulseWidth UserName="TMP4_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP4_GetFreeRunningValue UserName="TMP4_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP4>
+          <TMP5 InUse="">
+            <TMP5_Init UserName="TMP5_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP5_Start UserName="TMP5_Start" LibName="TMPn_Start" InUse="" />
+            <TMP5_Stop UserName="TMP5_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP5_ChangeTimerCondition UserName="TMP5_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP5_ChangeDuty UserName="TMP5_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP5_SoftwareTriggerOn UserName="TMP5_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP5_GetPulseWidth UserName="TMP5_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP5_GetFreeRunningValue UserName="TMP5_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP5>
+          <TMP6 Chip="V850ESJJ3" InUse="">
+            <TMP6_Init UserName="TMP6_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP6_Start UserName="TMP6_Start" LibName="TMPn_Start" InUse="" />
+            <TMP6_Stop UserName="TMP6_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP6_ChangeTimerCondition UserName="TMP6_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP6_ChangeDuty UserName="TMP6_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP6_SoftwareTriggerOn UserName="TMP6_SoftwareTriggerOn" LibName="Vn_SoftwareTriggerOn" InUse="" />
+            <TMP6_GetPulseWidth UserName="TMP6_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP6_GetFreeRunningValue UserName="TMP6_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP6>
+          <TMP7 Chip="V850ESJJ3" InUse="">
+            <TMP7_Init UserName="TMP7_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP7_Start UserName="TMP7_Start" LibName="TMPn_Start" InUse="" />
+            <TMP7_Stop UserName="TMP7_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP7_ChangeTimerCondition UserName="TMP7_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP7_ChangeDuty UserName="TMP7_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP7_SoftwareTriggerOn UserName="TMP7_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP7_GetPulseWidth UserName="TMP7_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP7_GetFreeRunningValue UserName="TMP7_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP7>
+          <TMP8 Chip="V850ESJJ3" InUse="">
+            <TMP8_Init UserName="TMP8_Init" LibName="TMPn_Init" InUse="" Init="2" />
+            <TMP8_Start UserName="TMP8_Start" LibName="TMPn_Start" InUse="" />
+            <TMP8_Stop UserName="TMP8_Stop" LibName="TMPn_Stop" InUse="" />
+            <TMP8_ChangeTimerCondition UserName="TMP8_ChangeTimerCondition" LibName="TMPn_ChangeTimerCondition" InUse="" />
+            <TMP8_ChangeDuty UserName="TMP8_ChangeDuty" LibName="TMPn_ChangeDuty" InUse="" />
+            <TMP8_SoftwareTriggerOn UserName="TMP8_SoftwareTriggerOn" LibName="TMPn_SoftwareTriggerOn" InUse="" />
+            <TMP8_GetPulseWidth UserName="TMP8_GetPulseWidth" LibName="TMPn_GetPulseWidth" InUse="" />
+            <TMP8_GetFreeRunningValue UserName="TMP8_GetFreeRunningValue" LibName="TMPn_GetFreeRunningValue" InUse="" />
+          </TMP8>
+          <TMQ0 InUse="">
+            <TMQ0_Init UserName="TMQ0_Init" LibName="TMQn_Init" InUse="" Init="2" />
+            <TMQ0_Start UserName="TMQ0_Start" LibName="TMQn_Start" InUse="" />
+            <TMQ0_Stop UserName="TMQ0_Stop" LibName="TMQn_Stop" InUse="" />
+            <TMQ0_ChangeTimerCondition UserName="TMQ0_ChangeTimerCondition" LibName="TMQn_ChangeTimerCondition" InUse="" />
+            <TMQ0_ChangeDuty UserName="TMQ0_ChangeDuty" LibName="TMQn_ChangeDuty" InUse="" />
+            <TMQ0_SoftwareTriggerOn UserName="TMQ0_SoftwareTriggerOn" LibName="TMQn_SoftwareTriggerOn" InUse="" />
+            <TMQ0_GetPulseWidth UserName="TMQ0_GetPulseWidth" LibName="TMQn_GetPulseWidth" InUse="" />
+            <TMQ0_GetFreeRunningValue UserName="TMQ0_GetFreeRunningValue" LibName="TMQn_GetFreeRunningValue" InUse="" />
+          </TMQ0>
+          <TMM0 InUse="">
+            <TMM0_Init UserName="TMM0_Init" LibName="TMMn_Init" InUse="" Init="2" />
+            <TMM0_Start UserName="TMM0_Start" LibName="TMMn_Start" InUse="" />
+            <TMM0_Stop UserName="TMM0_Stop" LibName="TMMn_Stop" InUse="" />
+            <TMM0_ChangeTimerCondition UserName="TMM0_ChangeTimerCondition" LibName="TMMn_ChangeTimerCondition" InUse="" />
+          </TMM0>
+        </CG_timer.c>
+        <CG_timer_user.c UserName="CG_timer_user.c" LibName="_user.c" InUse="">
+          <Type TMPn_UserInit="void TMPn_UserInit(void)" MD_INTTPnCC0="__interrupt void MD_INTTPnCC0(void)" MD_INTTPnCC1="__interrupt void MD_INTTPnCC1(void)" MD_INTTPnOV="__interrupt void MD_INTTPnOV(void)&#xD;&#xA;" TMQn_UserInit="void TMQn_UserInit(void)" MD_INTTQnCC0="__interrupt void MD_INTTQnCC0(void)" MD_INTTQnCC1="__interrupt void MD_INTTQnCC1(void)" MD_INTTQnCC2="__interrupt void MD_INTTQnCC2(void)" MD_INTTQnCC3="__interrupt void MD_INTTQnCC3(void)" MD_INTTQnOV="__interrupt void MD_INTTQnOV(void)" TMMn_UserInit="void TMMn_UserInit(void)" MD_INTTMnEQ0="__interrupt void MD_INTTMnEQ0(void)" />
+          <TMP0 InUse="">
+            <TMP0_UserInit UserName="TMP0_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP0CC0 UserName="MD_INTTP0CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP0CC1 UserName="MD_INTTP0CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP0OV UserName="MD_INTTP0OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP0>
+          <TMP1 InUse="">
+            <TMP1_UserInit UserName="TMP1_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP1CC0 UserName="MD_INTTP1CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP1CC1 UserName="MD_INTTP1CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP1OV UserName="MD_INTTP1OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP1>
+          <TMP2 InUse="">
+            <TMP2_UserInit UserName="TMP2_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP2CC0 UserName="MD_INTTP2CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP2CC1 UserName="MD_INTTP2CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP2OV UserName="MD_INTTP2OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP2>
+          <TMP3 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3" InUse="">
+            <TMP3_UserInit UserName="TMP3_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP3CC0 UserName="MD_INTTP3CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP3CC1 UserName="MD_INTTP3CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP3OV UserName="MD_INTTP3OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP3>
+          <TMP4 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3" InUse="">
+            <TMP4_UserInit UserName="TMP4_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP4CC0 UserName="MD_INTTP4CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP4CC1 UserName="MD_INTTP4CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP4OV UserName="MD_INTTP4OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP4>
+          <TMP5 InUse="">
+            <TMP5_UserInit UserName="TMP5_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP5CC0 UserName="MD_INTTP5CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP5CC1 UserName="MD_INTTP5CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP5OV UserName="MD_INTTP5OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP5>
+          <TMP6 Chip="V850ESJJ3" InUse="">
+            <TMP6_UserInit UserName="TMP6_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP6CC0 UserName="MD_INTTP6CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP6CC1 UserName="MD_INTTP6CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP6OV UserName="MD_INTTP6OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP6>
+          <TMP7 Chip="V850ESJJ3" InUse="">
+            <TMP7_UserInit UserName="TMP7_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP7CC0 UserName="MD_INTTP7CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP7CC1 UserName="MD_INTTP7CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP7OV UserName="MD_INTTP7OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP7>
+          <TMP8 Chip="V850ESJJ3" InUse="">
+            <TMP8_UserInit UserName="TMP8_UserInit" LibName="TMPn_UserInit" InUse="" />
+            <MD_INTTP8CC0 UserName="MD_INTTP8CC0" LibName="MD_INTTPnCC0" INTHandle="" InUse="" />
+            <MD_INTTP8CC1 UserName="MD_INTTP8CC1" LibName="MD_INTTPnCC1" INTHandle="" InUse="" />
+            <MD_INTTP8OV UserName="MD_INTTP8OV" LibName="MD_INTTPnOV" INTHandle="" InUse="" />
+          </TMP8>
+          <TMQ0 InUse="">
+            <TMQ0_UserInit UserName="TMQ0_UserInit" LibName="TMQn_UserInit" InUse="" />
+            <MD_INTTQ0CC0 UserName="MD_INTTQ0CC0" LibName="MD_INTTQnCC0" INTHandle="" InUse="" />
+            <MD_INTTQ0CC1 UserName="MD_INTTQ0CC1" LibName="MD_INTTQnCC1" INTHandle="" InUse="" />
+            <MD_INTTQ0CC2 UserName="MD_INTTQ0CC2" LibName="MD_INTTQnCC2" INTHandle="" InUse="" />
+            <MD_INTTQ0CC3 UserName="MD_INTTQ0CC3" LibName="MD_INTTQnCC3" INTHandle="" InUse="" />
+            <MD_INTTQ0OV UserName="MD_INTTQ0OV" LibName="MD_INTTQnOV" INTHandle="" InUse="" />
+          </TMQ0>
+          <TMM0 InUse="">
+            <TMM0_UserInit UserName="TMM0_UserInit" LibName="TMMn_UserInit" InUse="" />
+            <MD_INTTM0EQ0 UserName="MD_INTTM0EQ0" LibName="MD_INTTMnEQ0" INTHandle="" InUse="" />
+          </TMM0>
+        </CG_timer_user.c>
+        <CG_timer.h UserName="CG_timer.h" LibName=".h" InUse="" />
+      </Timer>
+      <WatchTimer InUse="">
+        <CG_wt.c UserName="CG_wt.c" LibName=".c" InUse="">
+          <Type WT_Init="void WT_Init(void)" WT_Start="void WT_Start(void)" WT_Stop="void WT_Stop(void)" />
+          <WT_Init UserName="WT_Init" LibName="WT_Init" InUse="" Init="2" />
+          <WT_Start UserName="WT_Start" LibName="WT_Start" InUse="" />
+          <WT_Stop UserName="WT_Stop" LibName="WT_Stop" InUse="" />
+        </CG_wt.c>
+        <CG_wt_user.c UserName="CG_wt_user.c" LibName="_user.c" InUse="">
+          <Type WT_UserInit="void WT_UserInit(void)" MD_INTWT="__interrupt void MD_INTWT(void)" MD_INTWTI="__interrupt void MD_INTWTI(void)" />
+          <WT_UserInit UserName="WT_UserInit" LibName="WT_UserInit" InUse="" />
+          <MD_INTWTI UserName="MD_INTWTI" LibName="MD_INTWTI" INTHandle="" InUse="" />
+          <MD_INTWT UserName="MD_INTWT" LibName="MD_INTWT" INTHandle="" InUse="" />
+        </CG_wt_user.c>
+        <CG_wt.h UserName="CG_wt.h" LibName=".h" InUse="" />
+      </WatchTimer>
+      <RTO InUse="">
+        <CG_rto.c UserName="CG_rto.c" LibName=".c" InUse="">
+          <Type RTOn_Init="void RTOn_Init(void)" RTOn_Enable="void RTOn_Enable(void)" RTOn_Disable="void RTOn_Disable(void)" RTOn_Set2BitsData="void RTOn_Set2BitsData(UCHAR data)" RTOn_Set4BitsData="void RTOn_Set4BitsData(UCHAR data)" RTOn_Set6BitsData="void RTOn_Set6BitsData(UCHAR data)" RTOn_GetValue="void RTOn_GetValue(UCHAR *value)" />
+          <RTO0 InUse="">
+            <RTO0_Init UserName="RTO0_Init" LibName="RTOn_Init" InUse="" Init="2" />
+            <RTO0_Enable UserName="RTO0_Enable" LibName="RTOn_Enable" InUse="" />
+            <RTO0_Disable UserName="RTO0_Disable" LibName="RTOn_Disable" InUse="" />
+            <RTO0_Set2BitsData UserName="RTO0_Set2BitsData" LibName="RTOn_Set2BitsData" InUse="" />
+            <RTO0_Set4BitsData UserName="RTO0_Set4BitsData" LibName="RTOn_Set4BitsData" InUse="" />
+            <RTO0_Set6BitsData UserName="RTO0_Set6BitsData" LibName="RTOn_Set6BitsData" InUse="" />
+            <RTO0_GetValue UserName="RTO0_GetValue" LibName="RTOn_GetValue" InUse="" />
+          </RTO0>
+          <RTO1 Chip="V850ESJJ3" InUse="">
+            <RTO1_Init UserName="RTO1_Init" LibName="RTOn_Init" InUse="" Init="2" />
+            <RTO1_Enable UserName="RTO1_Enable" LibName="RTOn_Enable" InUse="" />
+            <RTO1_Disable UserName="RTO1_Disable" LibName="RTOn_Disable" InUse="" />
+            <RTO1_Set2BitsData UserName="RTO1_Set2BitsData" LibName="RTOn_Set2BitsData" InUse="" />
+            <RTO1_Set4BitsData UserName="RTO1_Set4BitsData" LibName="RTOn_Set4BitsData" InUse="" />
+            <RTO1_Set6BitsData UserName="RTO1_Set6BitsData" LibName="RTOn_Set6BitsData" InUse="" />
+            <RTO1_GetValue UserName="RTO1_GetValue" LibName="RTOn_GetValue" InUse="" />
+          </RTO1>
+        </CG_rto.c>
+        <CG_rto_user.c UserName="CG_rto_user.c" LibName="_user.c" InUse="">
+          <Type RTOn_UserInit="void RTOn_UserInit(void)" />
+          <RTO0 InUse="">
+            <RTO0_UserInit UserName="RTO0_UserInit" LibName="RTOn_UserInit" InUse="" />
+          </RTO0>
+          <RTO1 Chip="V850ESJJ3" InUse="">
+            <RTO1_UserInit UserName="RTO1_UserInit" LibName="RTOn_UserInit" InUse="" />
+          </RTO1>
+        </CG_rto_user.c>
+        <CG_rto.h UserName="CG_rto.h" LibName=".h" InUse="" />
+      </RTO>
+      <DMA InUse="">
+        <CG_dma.c UserName="CG_dma.c" LibName=".c" InUse="">
+          <Type DMAn_Init="void DMAn_Init(void)	" DMAn_Enable="void DMAn_Enable(void)" DMAn_Disable="void DMAn_Disable(void)" DMAn_CheckStatus="MD_STATUS DMAn_CheckStatus(void)" DMAn_SoftwareTriggerOn="void DMAn_SoftwareTriggerOn(void)" DMAn_SetData="MD_STATUS DMAn_SetData(UINT srcaddr, UINT dstaddr, UINT count)" />
+          <DMA0 InUse="">
+            <DMA0_Init UserName="DMA0_Init" LibName="DMAn_Init" InUse="" Init="2" />
+            <DMA0_Enable UserName="DMA0_Enable" LibName="DMAn_Enable" InUse="" />
+            <DMA0_Disable UserName="DMA0_Disable" LibName="DMAn_Disable" InUse="" />
+            <DMA0_CheckStatus UserName="DMA0_CheckStatus" LibName="DMAn_CheckStatus" InUse="" />
+            <DMA0_SoftwareTriggerOn UserName="DMA0_SoftwareTriggerOn" LibName="DMAn_SoftwareTriggerOn" InUse="" />
+            <DMA0_SetData UserName="DMA0_SetData" LibName="DMAn_SetData" InUse="" />
+          </DMA0>
+          <DMA1 InUse="">
+            <DMA1_Init UserName="DMA1_Init" LibName="DMAn_Init" InUse="" Init="2" />
+            <DMA1_Enable UserName="DMA1_Enable" LibName="DMAn_Enable" InUse="" />
+            <DMA1_Disable UserName="DMA1_Disable" LibName="DMAn_Disable" InUse="" />
+            <DMA1_CheckStatus UserName="DMA1_CheckStatus" LibName="DMAn_CheckStatus" InUse="" />
+            <DMA1_SoftwareTriggerOn UserName="DMA1_SoftwareTriggerOn" LibName="DMAn_SoftwareTriggerOn" InUse="" />
+            <DMA1_SetData UserName="DMA1_SetData" LibName="DMAn_SetData" InUse="" />
+          </DMA1>
+          <DMA2 InUse="">
+            <DMA2_Init UserName="DMA2_Init" LibName="DMAn_Init" InUse="" Init="2" />
+            <DMA2_Enable UserName="DMA2_Enable" LibName="DMAn_Enable" InUse="" />
+            <DMA2_Disable UserName="DMA2_Disable" LibName="DMAn_Disable" InUse="" />
+            <DMA2_CheckStatus UserName="DMA2_CheckStatus" LibName="DMAn_CheckStatus" InUse="" />
+            <DMA2_SoftwareTriggerOn UserName="DMA2_SoftwareTriggerOn" LibName="DMAn_SoftwareTriggerOn" InUse="" />
+            <DMA2_SetData UserName="DMA2_SetData" LibName="DMAn_SetData" InUse="" />
+          </DMA2>
+          <DMA3 InUse="">
+            <DMA3_Init UserName="DMA3_Init" LibName="DMAn_Init" InUse="" Init="2" />
+            <DMA3_Enable UserName="DMA3_Enable" LibName="DMAn_Enable" InUse="" />
+            <DMA3_Disable UserName="DMA3_Disable" LibName="DMAn_Disable" InUse="" />
+            <DMA3_CheckStatus UserName="DMA3_CheckStatus" LibName="DMAn_CheckStatus" InUse="" />
+            <DMA3_SoftwareTriggerOn UserName="DMA3_SoftwareTriggerOn" LibName="DMAn_SoftwareTriggerOn" InUse="" />
+            <DMA3_SetData UserName="DMA3_SetData" LibName="DMAn_SetData" InUse="" />
+          </DMA3>
+        </CG_dma.c>
+        <CG_dma_user.c UserName="CG_dma_user.c" LibName="_user.c" InUse="">
+          <Type DMAn_UserInit="void DMAn_UserInit(void)" MD_INTDMAn="__interrupt void MD_INTDMAn(void)" />
+          <DMA0>
+            <DMA0_UserInit UserName="DMA0_UserInit" LibName="DMAn_UserInit" InUse="" />
+            <MD_INTDMA0 UserName="MD_INTDMA0" LibName="MD_INTDMAn" INTHandle="" InUse="" />
+          </DMA0>
+          <DMA1>
+            <DMA1_UserInit UserName="DMA1_UserInit" LibName="DMAn_UserInit" InUse="" />
+            <MD_INTDMA1 UserName="MD_INTDMA1" LibName="MD_INTDMAn" INTHandle="" InUse="" />
+          </DMA1>
+          <DMA2>
+            <DMA2_UserInit UserName="DMA2_UserInit" LibName="DMAn_UserInit" InUse="" />
+            <MD_INTDMA2 UserName="MD_INTDMA2" LibName="MD_INTDMAn" INTHandle="" InUse="" />
+          </DMA2>
+          <DMA3>
+            <DMA3_UserInit UserName="DMA3_UserInit" LibName="DMAn_UserInit" InUse="" />
+            <MD_INTDMA3 UserName="MD_INTDMA3" LibName="MD_INTDMAn" INTHandle="" InUse="" />
+          </DMA3>
+        </CG_dma_user.c>
+        <CG_dma.h UserName="CG_dma.h" LibName=".h" InUse="" />
+      </DMA>
+      <LVI InUse="">
+        <CG_lvi.c UserName="CG_lvi.c" LibName=".c" InUse="">
+          <Type LVI_Init="void LVI_Init(void)" LVI_InterruptModeStart="void LVI_INTModeStart(void)" LVI_ResetModeStart="MD_STATUS LVI_ResetModeStart(void)" LVI_Stop="void LVI_Stop(void)" LVI_SetLVILevel="MD_STATUS LVI_SetLVILevel(enum LVILevel level)" />
+          <LVI_Init UserName="LVI_Init" LibName="LVI_Init" InUse="" Init="2" />
+          <LVI_InterruptModeStart UserName="LVI_InterruptModeStart" LibName="LVI_InterruptModeStart" InUse="" />
+          <LVI_ResetModeStart UserName="LVI_ResetModeStart" LibName="LVI_ResetModeStart" InUse="" />
+          <LVI_Stop UserName="LVI_Stop" LibName="LVI_Stop" InUse="" />
+        </CG_lvi.c>
+        <CG_lvi_user.c UserName="CG_lvi_user.c" LibName="_user.c" InUse="">
+          <Type LVI_UserInit="void LVI_UserInit(void)" MD_INTLVI="__interrupt void MD_INTLVI(void)" />
+          <LVI_UserInit UserName="LVI_UserInit" LibName="LVI_UserInit" InUse="" />
+          <MD_INTLVI UserName="MD_INTLVI" LibName="MD_INTLVI" INTHandle="" InUse="" />
+        </CG_lvi_user.c>
+        <CG_lvi.h UserName="CG_lvi.h" LibName=".h" InUse="" />
+      </LVI>
+    </FUNC>
+    <TAG>
+      <GlobleUserTag>
+        <cg_vswc Name="cg_vswc" Value="00" />
+        <cg_security2 Name="cg_security2" Value="FF" />
+        <cg_security8 Name="cg_security8" Value="FF" />
+        <cg_security4 Name="cg_security4" Value="FF" />
+        <cg_security6 Name="cg_security6" Value="FF" />
+        <cg_security Name="cg_security" Value="FFFFFFFFFFFFFFFFFFFF" />
+        <cg_security3 Name="cg_security3" Value="FF" />
+        <cg_security0 Name="cg_security0" Value="FF" />
+        <cg_security9 Name="cg_security9" Value="FF" />
+        <cg_security5 Name="cg_security5" Value="FF" />
+        <cg_security7 Name="cg_security7" Value="FF" />
+        <cg_security1 Name="cg_security1" Value="FF" />
+        <use_cg_security Name="use_cg_security" Value="" />
+      </GlobleUserTag>
+    </TAG>
+  </DIR>
+  <MACRO>
+    <System SetFlag="True" Prepared="true" HelpID="system" NeedRefresh="False">
+      <System SetFlag="True" MacroName="System" />
+    </System>
+    <BUS SetFlag="" HelpID="externalbus" NeedRefresh="False">
+      <BUS SetFlag="" BusMode="15" />
+    </BUS>
+    <PORT HelpID="port" SetFlag="" NeedRefresh="False">
+      <PORT SetFlag="" MacroName="PORT" />
+    </PORT>
+    <INT HelpID="int" SetFlag="" NeedRefresh="False">
+      <INTP Chip="V850ESJJ3" SetFlag="" MacroName="INTP" NMIproperty="true" INTPproperty="9(3)" />
+      <KEY SetFlag="" MacroName="KEY" />
+    </INT>
+    <Serial HelpID="serial" SetFlag="" NeedRefresh="False">
+      <UARTA0 SetFlag="" MacroName="uarta" Channel="0" />
+      <UARTA1 SetFlag="" MacroName="uarta" Channel="1" />
+      <UARTA2 SetFlag="" MacroName="uarta" Channel="2" />
+      <UARTA3 Chip="DF3792,DF3793,V850ESJJ3" SetFlag="" MacroName="uarta" Channel="3" />
+      <CSIB0 SetFlag="" MacroName="csib" Channel="0" />
+      <CSIB1 SetFlag="" MacroName="csib" Channel="1" />
+      <CSIB2 SetFlag="" MacroName="csib" Channel="2" />
+      <CSIB3 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" SetFlag="" MacroName="csib" Channel="3" />
+      <CSIB4 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" SetFlag="" MacroName="csib" Channel="4" />
+      <CSIB5 Chip="V850ESJJ3" SetFlag="" MacroName="csib" Channel="5" />
+      <IIC00 SetFlag="" MacroName="iic0" Channel="0" />
+      <IIC01 SetFlag="" MacroName="iic0" Channel="1" />
+      <IIC02 Chip="V850ESJJ3,V850ESJG3,V850ESJG3L" SetFlag="" MacroName="iic0" Channel="2" />
+    </Serial>
+    <AD HelpID="ad" SetFlag="" NeedRefresh="False">
+      <AD Chip="V850ESJJ3" ANI="16" SetFlag="" />
+    </AD>
+    <DA HelpID="da" SetFlag="" NeedRefresh="False">
+      <DA0 SetFlag="" MacroName="DA" Channel="0" />
+      <DA1 Chip="V850ESJG3L,V850ESJG3,V850ESJJ3" SetFlag="" MacroName="DA" Channel="1" />
+    </DA>
+    <Timer HelpID="timer" SetFlag="" NeedRefresh="False">
+      <TMP0 SetFlag="" MacroName="TMP" Channel="0" />
+      <TMP1 SetFlag="" MacroName="TMP" Channel="1" />
+      <TMP2 SetFlag="" MacroName="TMP" Channel="2" />
+      <TMP3 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3" SetFlag="" MacroName="TMP" Channel="3" />
+      <TMP4 Chip="V850ESJJ3,V850ESJG3L,V850ESJG3" SetFlag="" MacroName="TMP" Channel="4" />
+      <TMP5 SetFlag="" MacroName="TMP" Channel="5" />
+      <TMP6 Chip="V850ESJJ3" SetFlag="" MacroName="TMP" Channel="6" />
+      <TMP7 Chip="V850ESJJ3" SetFlag="" MacroName="TMP" Channel="7" />
+      <TMP8 Chip="V850ESJJ3" SetFlag="" MacroName="TMP" Channel="8" />
+      <TMQ0 SetFlag="" MacroName="TMQ" Channel="0" />
+      <TMM0 SetFlag="" MacroName="TMM" Channel="0" />
+    </Timer>
+    <WatchTimer HelpID="watchtimer" SetFlag="" NeedRefresh="False">
+      <WatchTimer SetFlag="" MacroName="WatchTimer" />
+    </WatchTimer>
+    <RTO HelpID="realtimeoutput" SetFlag="" NeedRefresh="False">
+      <RTO0 SetFlag="" MacroName="RTO" Channel="0" />
+      <RTO1 Chip="V850ESJJ3" SetFlag="" MacroName="RTO" Channel="1" />
+    </RTO>
+    <DMA HelpID="dma" SetFlag="" NeedRefresh="False">
+      <DMA0 SetFlag="" MacroName="DMA" Channel="0" />
+      <DMA1 SetFlag="" MacroName="DMA" Channel="1" />
+      <DMA2 SetFlag="" MacroName="DMA" Channel="2" />
+      <DMA3 SetFlag="" MacroName="DMA" Channel="3" />
+    </DMA>
+    <LVI HelpID="lvi" SetFlag="" NeedRefresh="False">
+      <LVI SetFlag="" MacroName="LVI" />
+    </LVI>
+  </MACRO>
+  <SETTING>
+    <System>
+      <setting name="MainOSCFeedback" value="0" />
+      <setting name="MainOSCValue" value="4" />
+      <setting name="SubOSCValue" value="32.768" />
+      <setting name="SubclkFeedback" value="0" />
+      <setting name="InterOSCValue" value="220" />
+      <setting name="InterOSC" value="operation" />
+      <setting name="MainClock" value="0" />
+      <setting name="CPUClock" value="3" />
+      <setting name="PLLLockupTime" value="1" />
+      <setting name="fBRGValue" value="32.768" />
+      <setting name="fBRG" value="stop" />
+      <setting name="CLKOUT" value="off" />
+      <setting name="ClockMonitor" value="off" />
+      <setting name="StandbyReleaseNMI" value="Enable" />
+      <setting name="StandbyReleaseMask" value="Enable" />
+      <setting name="StandbyReleaseINTWDT2" value="Enable" />
+      <setting name="OCDMode" value="OCDUnused" />
+      <setting name="OCDMiniMode" value="MiniAndNWire" />
+      <setting name="OCDSecurityId" value="Used" />
+      <setting name="OCDSecurityIdValue" value="0xffffffffffffffffffff" />
+      <setting name="OCDRAMMode" value="Unused" />
+      <setting name="OCDMini2Interface" value="0" />
+      <setting name="WDT2Mode" value="ResetMode" />
+      <setting name="WDT2OPT" value="Off" />
+      <setting name="WDT2ClockMode" value="fR" />
+      <setting name="WDT2ClockSelection" value="7" />
+      <setting name="PowerOnClear" value="OutFunction" />
+      <setting name="Subclk" value="stop" />
+      <setting name="InterOSCOPT1" value="On" />
+      <setting name="InterOSC1" value="stop" />
+    </System>
+  </SETTING>
+</V850ESJx3>

bsp/upd70f3454/upd70f3454.dep

@@ -0,0 +1,1008 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
+  <fileVersion>2</fileVersion>
+  <fileChecksum>3094062322</fileChecksum>
+  <configuration>
+    <name>Debug</name>
+    <outputs>
+      <file>$PROJ_DIR$\Debug\Obj\CG_port_user.r85</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\cmd.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_error.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_heap.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_node.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_ops.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_parser.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\shell.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_token.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_var.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\finsh_vm.h</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\shell.c</file>
+      <file>$PROJ_DIR$\Debug\Obj\application.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\ipc.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\irq.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\stack.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\slab.r85</file>
+      <file>$TOOLKIT_DIR$\inc\xlocale.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_token.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\mem.r85</file>
+      <file>$TOOLKIT_DIR$\inc\DLib_Threads.h</file>
+      <file>$TOOLKIT_DIR$\inc\DLib_Defaults.h</file>
+      <file>$TOOLKIT_DIR$\inc\stdarg.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\board.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\device.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_vm.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\shell.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\interrupt.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\symbol.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_system.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\cstartup.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_port_user.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\object.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_init.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\module.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_system_user.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\object.pbi</file>
+      <file>$PROJ_DIR$\Debug\Exe\upd70f3454.d85</file>
+      <file>$PROJ_DIR$\Debug\Obj\mem.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\kservice.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\clock.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\io_macros.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\thread.r85</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_port.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\startup.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\interrupt.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\slab.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\xlocale_c.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_error.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\irq.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\ipc.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_init.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\application.r85</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_userdefine.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_system_user.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_timer.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\DLib_Product.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_heap.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\module.r85</file>
+      <file>$PROJ_DIR$\rtconfig.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_error.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\symbol.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_system.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\shell.r85</file>
+      <file>$TOOLKIT_DIR$\inc\ycheck.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_compiler.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_heap.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\mempool.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\cmd.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\stack.r85</file>
+      <file>$PROJ_DIR$\board.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_compiler.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\yvals.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_token.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_parser.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_timer_user.r85</file>
+      <file>$TOOLKIT_DIR$\inc\stdlib.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_ops.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\scheduler.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\idle.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_parser.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_vm.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_timer_user.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_port.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_var.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\ysizet.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_systeminit.r85</file>
+      <file>$TOOLKIT_DIR$\inc\ctype.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_port.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_node.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\startup.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\xmtx.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\timer.pbi</file>
+      <file>$PROJ_DIR$\io70f3454.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\thread.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\kservice.r85</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_timer.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\scheduler.r85</file>
+      <file>$PROJ_DIR$\uart.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\rtm.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\uart.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_ops.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_timer.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\uart.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\context.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\board.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\timer.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\mempool.r85</file>
+      <file>$TOOLKIT_DIR$\inc\string.h</file>
+      <file>$TOOLKIT_DIR$\inc\xlocaleuse.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\CG_systeminit.pbi</file>
+      <file>$PROJ_DIR$\Debug\Obj\idle.pbi</file>
+      <file>$PROJ_DIR$\..\..\components\finsh\symbol.c</file>
+      <file>$PROJ_DIR$\..\..\include\rtdef.h</file>
+      <file>$PROJ_DIR$\..\..\include\rthw.h</file>
+      <file>$PROJ_DIR$\..\..\include\rtm.h</file>
+      <file>$PROJ_DIR$\..\..\include\rtthread.h</file>
+      <file>$PROJ_DIR$\..\..\src\clock.c</file>
+      <file>$PROJ_DIR$\..\..\src\device.c</file>
+      <file>$PROJ_DIR$\..\..\src\idle.c</file>
+      <file>$PROJ_DIR$\..\..\src\ipc.c</file>
+      <file>$PROJ_DIR$\..\..\src\irq.c</file>
+      <file>$PROJ_DIR$\..\..\src\kservice.c</file>
+      <file>$PROJ_DIR$\..\..\src\kservice.h</file>
+      <file>$PROJ_DIR$\..\..\src\mem.c</file>
+      <file>$PROJ_DIR$\..\..\src\mempool.c</file>
+      <file>$PROJ_DIR$\..\..\src\module.c</file>
+      <file>$PROJ_DIR$\..\..\src\object.c</file>
+      <file>$PROJ_DIR$\..\..\src\rtm.c</file>
+      <file>$PROJ_DIR$\..\..\src\scheduler.c</file>
+      <file>$PROJ_DIR$\..\..\src\slab.c</file>
+      <file>$PROJ_DIR$\..\..\src\thread.c</file>
+      <file>$PROJ_DIR$\..\..\src\timer.c</file>
+      <file>$PROJ_DIR$\..\..\libcpu\v850\context.asm</file>
+      <file>$PROJ_DIR$\..\..\libcpu\v850\interrupt.c</file>
+      <file>$PROJ_DIR$\..\..\libcpu\v850\stack.c</file>
+      <file>$PROJ_DIR$\application.c</file>
+      <file>$PROJ_DIR$\board.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_system.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_port_user.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_port.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_system_user.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_systeminit.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_timer.c</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_timer_user.c</file>
+      <file>$PROJ_DIR$\cstartup.s85</file>
+      <file>$PROJ_DIR$\startup.c</file>
+      <file>$PROJ_DIR$\uart.c</file>
+      <file>$TOOLKIT_DIR$\inc\wchar.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\device.pbi</file>
+      <file>$TOOLKIT_DIR$\inc\intrinsics.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\upd70f3454.pbd</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_macrodriver.h</file>
+      <file>$TOOLKIT_DIR$\inc\xencoding_limits.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_node.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\clock.r85</file>
+      <file>$PROJ_DIR$\Debug\Obj\rtm.r85</file>
+      <file>$PROJ_DIR$\applilet3_src\CG_system.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\cmd.r85</file>
+      <file>$TOOLKIT_DIR$\inc\xtls.h</file>
+      <file>$PROJ_DIR$\Debug\Obj\finsh_var.r85</file>
+    </outputs>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 169</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 79</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 2 98 28 170 102 87 96 120 58 159 119</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 76</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 82</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 10 5 19 12 21</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 59</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 71</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 5 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 68</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 77</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 19</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 44</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 62</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 10 21 19 14 5 7</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 165</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 100</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 10 5 19 7</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 112</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 88</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 12 21 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 19</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 85</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 91</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 17 10 5 14 19</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 29</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 84</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 17 5</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 171</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 95</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 19</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 92</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 36</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119 21 19 12</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 74</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 37</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125 2 98 28 170 102 87 96 120 58 159 119 16</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>[ROOT_NODE]</name>
+      <outputs>
+        <tool>
+          <name>XLINK</name>
+          <file> 48</file>
+        </tool>
+      </outputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 72</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 39</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 2 127 124 70 33 75 83 32 67 164 31 98 28 170 102 87 96 120 58 159 119</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\clock.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 166</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 51</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\device.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 35</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 160</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\idle.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 90</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 122</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\ipc.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 61</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 24</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\irq.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 60</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 25</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\kservice.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 106</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 50</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\mem.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 30</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 49</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 2 98 28 170 102 87 96 120 58 159 119</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\mempool.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 118</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 78</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\module.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 69</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 45</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 126 124 70 33 75 83 32 67 164 31 127 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\object.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 43</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 47</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\rtm.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 167</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 110</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 126</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 108</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 89</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\slab.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 27</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 57</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\thread.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 53</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 105</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\timer.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 117</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 103</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 125 134</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\v850\context.asm</name>
+      <outputs>
+        <tool>
+          <name>AV850</name>
+          <file> 115</file>
+        </tool>
+      </outputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\v850\interrupt.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 38</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 56</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\v850\stack.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 80</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 26</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\application.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 63</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 23</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 127 124 70 33 75 83 32 67 164 31 81 163 161 104 52 168 54 107 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\board.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 34</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 116</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31 109 81</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_system.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 40</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 73</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 168 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_port_user.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 0</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 42</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 54 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_port.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 99</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 94</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 54 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_system_user.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 65</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 46</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 168 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_systeminit.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 97</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 121</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 168 54 107 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_timer.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 113</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 66</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 107 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\applilet3_src\CG_timer_user.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 86</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 93</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 163 161 104 52 107 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\cstartup.s85</name>
+      <outputs>
+        <tool>
+          <name>AV850</name>
+          <file> 41</file>
+        </tool>
+      </outputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\startup.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 55</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 101</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31 81 163 161 104 52 168 54 107 64</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\uart.c</name>
+      <outputs>
+        <tool>
+          <name>ICCV850</name>
+          <file> 111</file>
+        </tool>
+        <tool>
+          <name>BICOMP</name>
+          <file> 114</file>
+        </tool>
+      </outputs>
+      <inputs>
+        <tool>
+          <name>BICOMP</name>
+          <file> 125 127 124 70 33 75 83 32 67 164 31 104 52 109</file>
+        </tool>
+      </inputs>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\Debug\Obj\upd70f3454.pbd</name>
+      <inputs>
+        <tool>
+          <name>BILINK</name>
+          <file> 94 42 73 46 121 66 93 23 116 51 79 160 82 71 77 62 100 88 91 84 95 36 122 56 24 25 50 49 78 45 47 110 89 37 57 26 101 39 105 103 114</file>
+        </tool>
+      </inputs>
+    </file>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <outputs/>
+    <forcedrebuild>
+      <name>[MULTI_TOOL]</name>
+      <tool>XLINK</tool>
+    </forcedrebuild>
+  </configuration>
+</project>
+
+

bsp/upd70f3454/upd70f3454.ewd

@@ -0,0 +1,799 @@
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+
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+    <toolchain>
+      <name>V850</name>
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+          <name>CInput</name>
+          <state>1</state>
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+          <name>GoToName</name>
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+          <name>MemFile</name>
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+          <name>CMandatory</name>
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+        </option>
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+          <name>IecLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
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+        <option>
+          <name>IEC2E2RDoLogfile</name>
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+          <name>IEC2E2RLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
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+        <option>
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+          <name>MICMINICUBESpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MicDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MicLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
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+      <name>MIC2V850</name>
+      <archiveVersion>6</archiveVersion>
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+        <version>0</version>
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+          <name>MIC2Mandatory</name>
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+          <name>MIC2SuppressLoad</name>
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+          <name>MIC2VerifyLoad</name>
+          <state>0</state>
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+        <option>
+          <name>MIC2EraseFlash</name>
+          <state>0</state>
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+        <option>
+          <name>MIC2DoLogfile</name>
+          <state>0</state>
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+        <option>
+          <name>MIC2LogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
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+    </settings>
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+      <name>MICE2RV850</name>
+      <archiveVersion>6</archiveVersion>
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+          <name>MICE2RMandatory</name>
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+          <name>MICE2RSuppressLoad</name>
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+          <name>MICE2RVerifyLoad</name>
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+        </option>
+        <option>
+          <name>MICE2RDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MICE2RLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
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+      <name>NWIV850</name>
+      <archiveVersion>6</archiveVersion>
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+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
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+          <name>NWISuppressLoad</name>
+          <state>0</state>
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+        <option>
+          <name>NWIVerifyLoad</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NWIEraseFlash</name>
+          <state>0</state>
+        </option>
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+          <name>NWINWireSpeed</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>NwiDoLogfile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NwiLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
+        </option>
+      </data>
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+      <name>SIMV850</name>
+      <archiveVersion>6</archiveVersion>
+      <data>
+        <version>1</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
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+          <state>0</state>
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+      <name>TKSV850</name>
+      <archiveVersion>6</archiveVersion>
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+        <version>0</version>
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+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
+      </plugin>
+      <plugin>
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+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
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+    <toolchain>
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+          <name>TksDoLogfile</name>
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+          <name>TksLogFile</name>
+          <state>$PROJ_DIR$\cspycomm.log</state>
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+        <option>
+          <name>TksComPort</name>
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+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+        <loadFlag>0</loadFlag>
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+      <plugin>
+        <file>$TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin</file>
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+      <plugin>
+        <file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ENU.ewplugin</file>
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+      <plugin>
+        <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
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+      <plugin>
+        <file>$EW_DIR$\common\plugins\Profiling\Profiling.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
+      </plugin>
+      <plugin>
+        <file>$EW_DIR$\common\plugins\Stack\Stack.ENU.ewplugin</file>
+        <loadFlag>1</loadFlag>
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+      <plugin>
+        <file>$EW_DIR$\common\plugins\SymList\SymList.ENU.ewplugin</file>
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+    </debuggerPlugins>
+  </configuration>
+</project>
+
+

bsp/upd70f3454/upd70f3454.ewp

@@ -0,0 +1,1846 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<project>
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+          <name>CCCodeModel</name>
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+          <state>Debug\Exe</state>
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+          <state>Debug\Obj</state>
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+          <state></state>
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+          <name>CCLockedRegs</name>
+          <version>0</version>
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+          <name>CCDiagWarnAreErr</name>
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+          <state>0</state>
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+          <state>0</state>
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+          <name>PreInclude</name>
+          <state></state>
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+          <name>CCEnableMisalignedData</name>
+          <state>0</state>
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+          <name>CCIncludePath2</name>
+          <state>$PROJ_DIR$\</state>
+          <state>$PROJ_DIR$\applilet3_src\</state>
+          <state>$PROJ_DIR$\..\..\include\</state>
+          <state>$PROJ_DIR$\..\..\components\finsh</state>
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+          <name>CCStdIncCheck</name>
+          <state>0</state>
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+          <name>CCStdIncludePath</name>
+          <state>$TOOLKIT_DIR$\INC\</state>
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+          <state>0</state>
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+          <name>IccExtraOptions</name>
+          <state></state>
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+          <name>CCOverrideModuleTypeDefault</name>
+          <state>0</state>
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+          <name>CCRadioModuleType</name>
+          <state>0</state>
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+          <version>0</version>
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+          <state>1</state>
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+          <name>CCAggressiveInlining</name>
+          <state>0</state>
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+          <name>xcProgramEntryLabelSelect</name>
+          <state>0</state>
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+        <option>
+          <name>ListOutputFormat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>BufferedTermOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XlinkStackSize</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XcRTLibraryFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OXLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLibraryHeap</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OverlaySystemMap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XAR</name>
+      <archiveVersion>4</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>1</debug>
+        <option>
+          <name>XAROutOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XARInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <configuration>
+    <name>Release</name>
+    <toolchain>
+      <name>V850</name>
+    </toolchain>
+    <debug>0</debug>
+    <settings>
+      <name>General</name>
+      <archiveVersion>6</archiveVersion>
+      <data>
+        <version>7</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>GMemoryModel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GUseShort</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCodeModel</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ExePath</name>
+          <state>Release\Exe</state>
+        </option>
+        <option>
+          <name>ObjPath</name>
+          <state>Release\Obj</state>
+        </option>
+        <option>
+          <name>ListPath</name>
+          <state>Release\List</state>
+        </option>
+        <option>
+          <name>GeneralStack</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>GOutputBinary</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelect</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>RTDescription</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RTConfigPath</name>
+          <state>xxx.h</state>
+        </option>
+        <option>
+          <name>RTLibraryPath</name>
+          <state>xxx.r85</state>
+        </option>
+        <option>
+          <name>GRuntimeLibSelectSlave</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Input variant</name>
+          <version>0</version>
+          <state>0</state>
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+        <option>
+          <name>Input description</name>
+          <state></state>
+        </option>
+        <option>
+          <name>Output variant</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>Output description</name>
+          <state></state>
+        </option>
+        <option>
+          <name>GHeapSize</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>GeneralEnableMisra</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraVerbose</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GDeviceSelect</name>
+          <state>70F3746	V850ES- uPD70F3746</state>
+        </option>
+        <option>
+          <name>GeneralMisraVer</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>GeneralMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>GFloatingPointUnit</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>ICCV850</name>
+      <archiveVersion>4</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>CCDefines</name>
+          <state>NDEBUG</state>
+        </option>
+        <option>
+          <name>CCPreprocFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocComments</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCPreprocLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMnemonics</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListCMessages</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssFile</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCListAssSource</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableRemarks</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagSuppress</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagRemark</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagWarning</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDiagError</name>
+          <state></state>
+        </option>
+        <option>
+          <name>IProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IMemory</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ICode</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCAllowList</name>
+          <version>1</version>
+          <state>11111</state>
+        </option>
+        <option>
+          <name>CCObjUseModuleName</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCObjModuleName</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCDebugInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLockedRegs</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IRegConstCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDiagWarnAreErr</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCEnableMigration</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>IRegConstCompCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCompilerRuntimeInfo</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCMultiByte</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCDisableSldSuppression</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCLibConfigHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCRequirePrototypes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCCharIs</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCExt</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCLangSelect</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CompilerMisraOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PreInclude</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCEnableMisalignedData</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCIncludePath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCStdIncludePath</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>IccExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>IccExtraOptions</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CCOverrideModuleTypeDefault</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRadioModuleType</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>CCRadioModuleTypeSlave</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules04</name>
+          <version>0</version>
+          <state>111101110010111111111000110111111111111111111111111110010111101111010101111111111111111111111111101111111011111001111011111011111111111111111</state>
+        </option>
+        <option>
+          <name>CompilerMisraRules98</name>
+          <version>0</version>
+          <state>1000111110110101101110011100111111101110011011000101110111101101100111111111111100110011111001110111001111111111111111111111111</state>
+        </option>
+        <option>
+          <name>CCOptLevel</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCOptStrategy</name>
+          <version>0</version>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CCOptLevelSlave</name>
+          <state>3</state>
+        </option>
+        <option>
+          <name>CCAggressiveInlining</name>
+          <state>0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>AV850</name>
+      <archiveVersion>4</archiveVersion>
+      <data>
+        <version>6</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>AObjPrefix</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AProcessor</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacroChars</name>
+          <version>0</version>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ACaseSensitivity</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AListHeader</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>AListing</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>Includes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacDefs</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MacExps</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>MacExec</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OnlyAssed</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>MultiLine</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
+        </option>
+        <option>
+          <name>TabSpacing</name>
+          <state>8</state>
+        </option>
+        <option>
+          <name>AXRef</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDefines</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefInternal</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AXRefDual</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>ADefines</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>AWarnEnable</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnWhat</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AWarnOne</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange1</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AWarnRange2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>ADebugNew</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AMultiBytes</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>Multibyte</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OAIncludePath2</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OAStdIncCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OAStdIncludePath</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>AMaxErrChk</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AMaxNumErr</name>
+          <state>100</state>
+        </option>
+        <option>
+          <name>AsmExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>AsmExtraOptions</name>
+          <state></state>
+        </option>
+      </data>
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+      <archiveVersion>3</archiveVersion>
+      <data>
+        <extensions></extensions>
+        <cmdline></cmdline>
+      </data>
+    </settings>
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+      <name>BICOMP</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
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+    <settings>
+      <name>BUILDACTION</name>
+      <archiveVersion>1</archiveVersion>
+      <data>
+        <prebuild></prebuild>
+        <postbuild></postbuild>
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+      <name>XLINK</name>
+      <archiveVersion>4</archiveVersion>
+      <data>
+        <version>15</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>XOutOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OutputFormat</name>
+          <version>11</version>
+          <state>23</state>
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+        <option>
+          <name>FormatVariant</name>
+          <version>8</version>
+          <state>2</state>
+        </option>
+        <option>
+          <name>SecondaryOutputFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>XDefines</name>
+          <state></state>
+        </option>
+        <option>
+          <name>AlwaysOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OverlapWarnings</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>NoGlobalCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XList</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>SegmentMap</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>ListSymbols</name>
+          <state>2</state>
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+        <option>
+          <name>PageLengthCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>PageLength</name>
+          <state>80</state>
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+        <option>
+          <name>XIncludes</name>
+          <state>###Uninitialized###</state>
+        </option>
+        <option>
+          <name>ModuleStatus</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XclOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XclFile</name>
+          <state>lnk0t.xcl</state>
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+        <option>
+          <name>XclFileSlave</name>
+          <state></state>
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+        <option>
+          <name>XExtraOptionsCheck</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XExtraOptions</name>
+          <state></state>
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+          <name>DoFill</name>
+          <state>0</state>
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+        <option>
+          <name>FillerByte</name>
+          <state>0xFF</state>
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+          <name>DoCrc</name>
+          <state>0</state>
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+        <option>
+          <name>CrcSize</name>
+          <version>0</version>
+          <state>1</state>
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+          <name>CrcAlgo</name>
+          <state>1</state>
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+          <state>0x11021</state>
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+        <option>
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+          <state>0</state>
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+          <name>SuppressDiags</name>
+          <state></state>
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+        <option>
+          <name>TreatAsWarn</name>
+          <state></state>
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+        <option>
+          <name>TreatAsErr</name>
+          <state></state>
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+          <state>1</state>
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+          <name>RuntimeControl</name>
+          <state>1</state>
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+        <option>
+          <name>IoEmulation</name>
+          <state>1</state>
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+        <option>
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+        <option>
+          <name>GenerateExtraOutput</name>
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+          <state>0</state>
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+          <state></state>
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+          <version>11</version>
+          <state>23</state>
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+        <option>
+          <name>ExtraFormatVariant</name>
+          <version>8</version>
+          <state>2</state>
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+        <option>
+          <name>xcOverrideProgramEntryLabel</name>
+          <state>0</state>
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+        <option>
+          <name>xcProgramEntryLabelSelect</name>
+          <state>0</state>
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+        <option>
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+          <state>0</state>
+        </option>
+        <option>
+          <name>BufferedTermOutput</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XlinkStackSize</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XcRTLibraryFile</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>OXLibIOConfig</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLibraryHeap</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>XLinkMisraHandler</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>OverlaySystemMap</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>RawBinaryFile</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RawBinarySymbol</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RawBinarySegment</name>
+          <state></state>
+        </option>
+        <option>
+          <name>RawBinaryAlign</name>
+          <state></state>
+        </option>
+        <option>
+          <name>CrcAlign</name>
+          <state>1</state>
+        </option>
+        <option>
+          <name>CrcInitialValue</name>
+          <state>0x0</state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>XAR</name>
+      <archiveVersion>4</archiveVersion>
+      <data>
+        <version>0</version>
+        <wantNonLocal>1</wantNonLocal>
+        <debug>0</debug>
+        <option>
+          <name>XAROutOverride</name>
+          <state>0</state>
+        </option>
+        <option>
+          <name>XARInputs</name>
+          <state></state>
+        </option>
+        <option>
+          <name>OutputFile</name>
+          <state></state>
+        </option>
+      </data>
+    </settings>
+    <settings>
+      <name>BILINK</name>
+      <archiveVersion>0</archiveVersion>
+      <data/>
+    </settings>
+  </configuration>
+  <group>
+    <name>finsh</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\cmd.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_compiler.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_error.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_heap.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_init.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_node.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_ops.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_parser.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_token.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_var.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\finsh_vm.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\shell.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\shell.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\finsh\symbol.c</name>
+    </file>
+  </group>
+  <group>
+    <name>include</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\include\rtdef.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\include\rthw.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\include\rtm.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\include\rtthread.h</name>
+    </file>
+  </group>
+  <group>
+    <name>kernel</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\clock.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\device.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\idle.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\ipc.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\irq.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\kservice.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\kservice.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\mem.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\mempool.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\module.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\module.h</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\object.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\rtm.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\scheduler.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\slab.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\thread.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\src\timer.c</name>
+    </file>
+  </group>
+  <group>
+    <name>libcpu</name>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\v850\context.asm</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\v850\interrupt.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\libcpu\v850\stack.c</name>
+    </file>
+  </group>
+  <file>
+    <name>$PROJ_DIR$\application.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\board.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_port.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_port_user.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_system.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_system_user.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_systeminit.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_timer.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\applilet3_src\CG_timer_user.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\cstartup.s85</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\startup.c</name>
+  </file>
+  <file>
+    <name>$PROJ_DIR$\uart.c</name>
+  </file>
+</project>
+
+

bsp/upd70f3454/upd70f3454.eww

@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="iso-8859-1"?>
+
+<workspace>
+  <project>
+    <path>$WS_DIR$\upd70f3454.ewp</path>
+  </project>
+  <batchBuild />
+</workspace>

libcpu/v850/context.asm

@@ -0,0 +1,218 @@
+#include "macdefs.inc"
+
+    name OS_Core 
+
+    COMMON INTVEC:CODE 
+ 
+;******************************************************************** 
+; 
+;	function: 
+;	description:	Trap 0x10 vector used for context switch 
+;		Right now, all TRAPs to $1x are trated the same way 
+; 
+    org 50h 
+    jr OSCtxSW 
+ 
+ 
+;******************************************************************** 
+; 
+;	function: 
+;	description:    Timer 40 compare match interrupt used for system 
+;                   tick interrupt 
+; 
+    org 0x220
+    jr OSTickIntr 
+
+    org 0x0520
+    jr uarta1_int_r
+  
+    RSEG        CODE(1)
+
+    EXTERN    rt_thread_switch_interrput_flag
+    EXTERN    rt_interrupt_from_thread
+    EXTERN    rt_interrupt_to_thread
+
+    EXTERN    rt_interrupt_enter        
+    EXTERN    rt_interrupt_leave
+    EXTERN    rt_tick_increase
+    EXTERN    uarta1_receive_handler
+        
+    PUBLIC    rt_hw_interrupt_disable
+    PUBLIC    rt_hw_interrupt_enable 
+    PUBLIC    rt_hw_context_switch_to
+    PUBLIC    rt_hw_context_switch
+    PUBLIC    rt_hw_context_switch_interrupt
+    PUBLIC    OSCtxSW
+    PUBLIC    OS_Restore_CPU_Context    
+
+rt_hw_interrupt_disable:
+    stsr psw, r1    
+    di
+    jmp [lp]
+
+rt_hw_interrupt_enable:
+    ldsr r1, psw
+    jmp [lp]
+    
+OS_Restore_CPU_Context: 
+    mov sp, ep 
+    sld.w 4[ep], r2 
+	sld.w 8[ep], r5 
+	sld.w 12[ep],r6 
+	sld.w 16[ep],r7 
+	sld.w 20[ep],r8 
+	sld.w 24[ep],r9 
+	sld.w 28[ep],r10 
+	sld.w 32[ep],r11 
+	sld.w 36[ep],r12 
+	sld.w 40[ep],r13 
+	sld.w 44[ep],r14 
+	sld.w 48[ep],r15 
+	sld.w 52[ep],r16 
+ 
+    ;See what was the latest interruption (trap or interrupt) 
+    stsr ecr, r17                   ;Move ecr to r17 
+    mov 0x050,r1 
+    cmp r1, r17                     ;If latest break was due to TRAP, set EP 
+    be _SetEP 
+ 
+_ClrEP: 
+    mov 0x20, r17                   ;Set only ID 
+	ldsr r17, psw 
+ 
+	;Restore caller address 
+	sld.w 56[ep], r1 
+	ldsr r1, EIPC 
+	;Restore PSW 
+	sld.w 60[ep], r1 
+    andi 0xffdf,r1,r1 
+	ldsr r1, EIPSW 
+    sld.w 0[ep], r1 
+	dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} 
+ 
+	;Return from interrupt starts new task! 
+    reti 
+ 
+_SetEP: 
+    mov 0x60, r17                   ;Set both EIPC and ID bits 
+	ldsr r17, psw 
+ 
+	;Restore caller address 
+	sld.w 56[ep], r1 
+	ldsr r1, EIPC 
+	;Restore PSW 
+	sld.w 60[ep], r1 
+    andi 0xffdf,r1,r1 
+    ldsr r1, EIPSW 
+    sld.w 0[ep], r1 
+	dispose (8+(4*14)),{r23,r24,r25,r26,r27,r28,r29,r30,r31} 
+ 
+	;Return from interrupt starts new task! 
+	reti 
+    
+//rseg CODE:CODE
+//public rt_hw_context_switch_to
+rt_hw_context_switch_to:
+	;Load stack pointer of the task to run 
+    ld.w 0[r1], sp					;load sp from struct 
+ 
+	;Restore all Processor registers from stack and return from interrupt 
+    jr OS_Restore_CPU_Context
+
+OSCtxSW:
+    SAVE_CPU_CTX                    ;Save all CPU registers 
+        
+    mov rt_thread_switch_interrput_flag, r1
+    ld.w 0[r1],r5
+    cmp    0, r5
+    be      exit 
+
+    mov    0, r5
+    st.b r5, 0[r1]
+
+	mov rt_interrupt_from_thread, r21 
+	ld.w 0[r21], r21 
+	st.w sp, 0[r21] 
+    
+    mov    rt_interrupt_to_thread, r1
+    ld.w 0[r1], r1
+    ld.w 0[r1], sp 
+
+exit: 
+    ;Restore all Processor registers from stack and return from interrupt 
+	jr OS_Restore_CPU_Context 
+
+;R1 -> rt_interrupt_from_thread
+;R5 -> rt_interrupt_to_thread
+rt_hw_context_switch:
+    mov rt_thread_switch_interrput_flag, r8
+    ld.w 0[r8],r9
+    cmp    1, r9
+    be      jump1
+    ;mov rt_thread_switch_interrput_flag, r1
+    mov    1, r9
+    st.b r9, 0[r8]
+    mov rt_interrupt_from_thread, r10
+    st.w r1, 0[r10]
+jump1
+    mov rt_interrupt_to_thread, r11
+    st.w r5, 0[r11]
+    trap 0x10
+    jmp [lp]    
+  
+rt_hw_context_switch_interrupt:
+    mov rt_thread_switch_interrput_flag, r8
+    ld.w 0[r8],r9
+    cmp    1, r9
+    be      jump2
+    ;mov rt_thread_switch_interrput_flag, r1
+    mov    1, r9
+    st.b r9, 0[r8]
+    mov rt_interrupt_from_thread, r10
+    st.w r1, 0[r10]
+jump2
+    mov rt_interrupt_to_thread, r11
+    st.w r5, 0[r11]  
+    jmp [lp] 
+
+rt_hw_context_switch_interrupt_do
+    mov rt_thread_switch_interrput_flag, r8
+    mov    0, r9
+    st.b r9, 0[r8]
+    
+	mov rt_interrupt_from_thread, r21 
+	ld.w 0[r21], r21 
+	st.w sp, 0[r21]    
+    
+    mov    rt_interrupt_to_thread, r1
+    ld.w 0[r1], r1
+    ld.w 0[r1], sp 
+    jr OS_Restore_CPU_Context
+    
+OSTickIntr:
+    SAVE_CPU_CTX                    ;Save current task's registers
+    jarl    rt_interrupt_enter,lp
+    jarl    rt_tick_increase,lp
+    jarl    rt_interrupt_leave,lp
+
+    mov rt_thread_switch_interrput_flag, r8
+    ld.w 0[r8],r9
+    cmp    1, r9
+    be      rt_hw_context_switch_interrupt_do
+    
+    jr OS_Restore_CPU_Context
+    
+uarta1_int_r:
+    SAVE_CPU_CTX                    ;Save current task's registers
+    jarl    rt_interrupt_enter,lp
+    jarl    uarta1_receive_handler,lp
+    jarl    rt_interrupt_leave,lp
+
+    mov rt_thread_switch_interrput_flag, r8
+    ld.w   0[r8],r9
+    cmp    1, r9
+    be     rt_hw_context_switch_interrupt_do
+    
+    jr OS_Restore_CPU_Context
+    
+    END

libcpu/v850/interrupt.c

@@ -0,0 +1,22 @@
+/*
+ * File      : interrupt.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-06-29     lgnq         the first version
+ *
+ * For       : NEC V850E
+ * Toolchain : IAR Embedded Workbench for V850 v3.71
+*/
+
+#include <rtthread.h>
+
+rt_uint32_t rt_interrupt_from_thread;
+rt_uint32_t rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrput_flag;

libcpu/v850/macdefs.inc

@@ -0,0 +1,125 @@
+; 
+;       These are the macros used by the v850 port of the uCOS/II. 
+; 
+ 
+ 
+ 
+ 
+ 
+;******************************************************************** 
+;	function: 
+;	description: 
+;	--- Modifies ---------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;		   CPU: 
+;	--- Uses -------------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;	--- Input ------------------------------------------------- 
+;	--- Output ------------------------------------------------ 
+;	--- Notes ------------------------------------------------- 
+;==================================================================== 
+ 
+SAVE_CPU_CTX MACRO 
+	;Save all registers on entry (r3 is the stack pointer) 
+	prepare {r23,r24,r25,r26,r27,r28,r29,r30,r31},(8+(4*14))	 ;Add 8 bytes for 2 more registers 
+	mov sp, ep 
+        sst.w r1, 0[ep] 
+	sst.w r2, 4[ep] 
+	sst.w r5, 8[ep] 
+	sst.w r6, 12[ep] 
+	sst.w r7, 16[ep] 
+	sst.w r8, 20[ep] 
+	sst.w r9, 24[ep] 
+	sst.w r10, 28[ep] 
+	sst.w r11, 32[ep] 
+	sst.w r12, 36[ep] 
+	sst.w r13, 40[ep] 
+	sst.w r14, 44[ep] 
+	sst.w r15, 48[ep] 
+	sst.w r16, 52[ep] 
+	;Save caller's PC 
+	stsr EIPC, r1 
+	sst.w r1, 56[ep] 
+	;Save caller's PSW 
+	stsr EIPSW, r1 
+	sst.w r1, 60[ep] 
+ 
+        ENDMAC 
+ 
+ 
+ 
+ 
+ 
+;******************************************************************** 
+;	function: 
+;	description: 
+;	--- Modifies ---------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;		   CPU: 
+;	--- Uses -------------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;	--- Input ------------------------------------------------- 
+;	--- Output ------------------------------------------------ 
+;	--- Notes ------------------------------------------------- 
+;==================================================================== 
+SAVE_SP MACRO 
+	;Save stack pointer on OSTCBCur->OSTCBStkPtr (OSTCBStkPtr=0) 
+	mov OSTCBCur, r21 
+	ld.w 0[r21], r21 
+	st.w sp, 0[r21] 
+        ENDMAC 
+ 
+ 
+ 
+;******************************************************************** 
+;	function: 
+;	description: 
+;	--- Modifies ---------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;		   CPU: 
+;	--- Uses -------------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;	--- Input ------------------------------------------------- 
+;	--- Output ------------------------------------------------ 
+;	--- Notes ------------------------------------------------- 
+;==================================================================== 
+ISR_ENTRY  MACRO 
+        LOCAL _DontSaveSP 
+ 
+        ;Save all CPU registers according to the standard stack frame 
+        SAVE_CPU_CTX 
+ 
+	mov OSIntNesting, r1                   ;Increment OSNesting by one 
+	LD.BU	0[r1],r2 
+        add 1, r2 
+	ST.B  r2, 0[r1] 
+        cmp 1, r2                              ;If OSNesting==1 save SP in current TCB 
+        bne _DontSaveSP 
+        SAVE_SP 
+_DontSaveSP: 
+        ENDMAC 
+ 
+;******************************************************************** 
+;	function: 
+;	description: 
+;	--- Modifies ---------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;		   CPU: 
+;	--- Uses -------------------------------------------------- 
+;		   IO : 
+;		   Mem: 
+;	--- Input ------------------------------------------------- 
+;	--- Output ------------------------------------------------ 
+;	--- Notes ------------------------------------------------- 
+;==================================================================== 
+ISR_EXIT MACRO 
+        jarl OSIntExit, lp                      ;Call OSIntExit() 
+	jr OS_Restore_CPU_Context               ;Restore processors registers and execute RETI 
+        ENDMAC 

libcpu/v850/stack.c

@@ -0,0 +1,61 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2010-06-29     lgnq         the first version
+ *
+ * For       : NEC V850E
+ * Toolchain : IAR Embedded Workbench for V850 v3.71
+*/
+
+#include <rtthread.h>
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;     
+   
+    stk    = (rt_uint32_t *)stack_addr;          /* Load stack pointer                                      */   
+    *(--stk) = (rt_uint32_t) 0x23232323;         /* r23 */   
+    *(--stk) = (rt_uint32_t) 0x24242424;         /* r24 */   
+    *(--stk) = (rt_uint32_t) 0x25252525;         /* r25 */   
+    *(--stk) = (rt_uint32_t) 0x26262626;         /* r26 */   
+    *(--stk) = (rt_uint32_t) 0x27272727;         /* r27 */   
+    *(--stk) = (rt_uint32_t) 0x28282828;         /* r28 */   
+    *(--stk) = (rt_uint32_t) 0x29292929;         /* r29 */   
+    *(--stk) = (rt_uint32_t) 0x30303030;         /* r30 */   
+    *(--stk) = (rt_uint32_t) 0x31313131;         /* r31 */   
+    *(--stk) = (rt_uint32_t) 0x00000000;         /* Task PSW = Interrupts enabled                                 */   
+    *(--stk) = (rt_uint32_t) tentry;             /* Task's PC */   
+    *(--stk) = (rt_uint32_t) 0x16161616;         /* r16 */   
+    *(--stk) = (rt_uint32_t) 0x15151515;         /* r15 */   
+    *(--stk) = (rt_uint32_t) 0x14141414;         /* r14 */   
+    *(--stk) = (rt_uint32_t) 0x13131313;         /* r13 */   
+    *(--stk) = (rt_uint32_t) 0x12121212;         /* r12 */   
+    *(--stk) = (rt_uint32_t) 0x11111111;         /* r11 */   
+    *(--stk) = (rt_uint32_t) 0x10101010;         /* r10 */   
+    *(--stk) = (rt_uint32_t) 0x09090909;         /* r9 */   
+    *(--stk) = (rt_uint32_t) 0x08080808;         /* r8 */   
+    *(--stk) = (rt_uint32_t) 0x07070707;         /* r7 */   
+    *(--stk) = (rt_uint32_t) 0x06060606;         /* r6 */   
+    *(--stk) = (rt_uint32_t) 0x05050505;         /* r5 */   
+    *(--stk) = (rt_uint32_t) 0x02020202;         /* r2 */   
+    *(--stk) = (rt_uint32_t) parameter;          /* r1 */   
+    return ((rt_uint8_t *)stk); 
+}