Merge pull request #5094 from aisino2200/master

ACM32F4XX-nucleo bsp add

bsp/acm32f4xx-nucleo/.ignore_format.yml

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+# files format check exclude path, please follow the instructions below to modify;
+# If you need to exclude an entire folder, add the folder path in dir_path;
+# If you need to exclude a file, add the path to the file in file_path.
+
+dir_path:
+- libraries

bsp/acm32f4xx-nucleo/Kconfig

@@ -0,0 +1,22 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+source "$BSP_DIR/drivers/Kconfig"
+

bsp/acm32f4xx-nucleo/README.md

@@ -0,0 +1,56 @@
+# acm32f0x0板级支持包
+
+## 1. 简介
+
+ACM32F4xx芯片是上海爱信诺航芯电子科技有限公司(后续简称上海航芯)一系列支持多种低功耗模式的通用MCU。包括如下硬件特性：
+
+|--------------------------|--------------------|
+|         硬件             |         描述       |
+| -------------------------|--------------------|
+|芯片型号                  | ACM32F4XX系列      |
+|CPU                       | ARM Cortex-M33     |
+|主频                      | 180MHz             |
+|片内SRAM                  | 192K               |
+|片内Flash                 | 512K               |
+|--------------------------|--------------------|
+
+具体型号及资源请参考上海航芯官方网站[ACM32F4](www.aisinochip.com/index.php/product/child1/id/219.html)。
+
+## 2. 编译说明
+
+推荐使用[env工具][1]，可以在console下进入到`bsp/acm32f4xx-nucleo`目录中，运行以下命令：
+
+`scons`
+
+来编译这个板级支持包。如果编译正确无误，会产生rtthread.elf、rtthread.bin文件。其中rtthread.bin需要烧写到设备中进行运行。
+
+也可以通过`scons --target=mdk5`生成keil工程，再使用keil进行编译。
+
+## 3. 烧写及执行
+
+开发板的使用请参考上海航芯官方网站相应型号的[开发工具](www.aisinochip.com/index.php/product/detail/id/25.html)。
+
+### 3.1 运行结果
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+## 4. 驱动支持情况及计划
+
+| **片上外设**  | **支持情况** |               **备注**                |
+| ------------- | ------------ | ------------------------------------- |
+| GPIO          |     支持     | PA0, PA1... PF4 ---> PIN: 0, 1...83  |
+| UART          |     支持     |              UART1/UART2              |
+| LED           |     支持     |              LED1                     |
+
+## 5. 联系人信息
+
+维护人：AisinoChip < xiangfeng.liu@aisinochip.com >
+
+## 6. 参考
+
+* 板子[数据手册][2]
+* 芯片[数据手册][3]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: www.aisinochip.com/index.php/product/detail/id/50.html
+  [3]: www.aisinochip.com/index.php/product/detail/id/50.html

bsp/acm32f4xx-nucleo/SConscript

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd  = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/acm32f4xx-nucleo/SConstruct

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+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread_acm32f4xx.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/acm32f4xx-nucleo/applications/SConscript

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+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = os.path.join(str(Dir('#')), 'applications')
+src = Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/acm32f4xx-nucleo/applications/main.c

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+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-17     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <drivers/pin.h>
+
+#define LED_PIN_NUM    83     /* PF3 */
+
+int main(void)
+{
+    rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN_NUM, PIN_LOW);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+        rt_pin_write(LED_PIN_NUM, PIN_HIGH);
+        rt_thread_delay(RT_TICK_PER_SECOND / 2);
+    }
+}

bsp/acm32f4xx-nucleo/drivers/Kconfig

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+menu "Hardware Drivers Config"
+
+choice
+    prompt "select chip type"
+    default SOC_ACM32F403RET7
+
+    config SOC_ACM32F403KCU7
+    bool "SOC_ACM32F403KCU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403KEU7
+    bool "SOC_ACM32F403KEU7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CCT7
+    bool "SOC_ACM32F403CCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403CET7
+    bool "SOC_ACM32F403CET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RCT7
+    bool "SOC_ACM32F403RCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403RET7
+    bool "SOC_ACM32F403RET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VCT7
+    bool "SOC_ACM32F403VCT7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+
+    config SOC_ACM32F403VET7
+    bool "SOC_ACM32F403VET7"
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    help
+        Refer to ACM32F403 DataSheet
+endchoice
+
+menu "ACM32F403RET7"
+    depends on SOC_ACM32F403RET7
+
+    config SOC_SRAM_START_ADDR
+        hex "sram start address"
+        default 0x20000000
+
+    config SOC_SRAM_SIZE
+        hex "sram size(KBytes)"
+        default 0xC0
+
+    config SOC_FLASH_START_ADDR
+        hex "EFlash Start Address"
+        default 0x00000000
+
+    config SOC_FLASH_SIZE
+        hex "EFlash Size(KBytes)"
+        default 0x8000
+endmenu
+
+menu "Onboard Peripheral Drivers"
+
+endmenu
+
+menu "On-chip Peripheral Drivers"
+
+    menu "Hardware GPIO"
+        config BSP_USING_GPIO1
+            bool "Enable GPIOAB"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO2
+            bool "Enable GPIOCD"
+            default y
+            select RT_USING_PIN
+        config BSP_USING_GPIO3
+            bool "Enable GPIOEF"
+            default y
+            select RT_USING_PIN
+    endmenu
+
+    config BSP_USING_ADC
+        bool "Enable ADC"
+        select RT_USING_ADC
+        default n
+
+    config BSP_USING_DAC
+        bool "Enable DAC"
+        select RT_USING_DAC
+        default n
+
+    menu "Hardware UART"
+        config BSP_USING_UART1
+            bool "Enable UART1 (PA9/PA10)"
+            default y
+            select RT_USING_SERIAL
+
+        config BSP_USING_UART2
+            bool "Enable UART2 (PA2/PA3)"
+            default y
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART2
+            config BSP_UART2_RX_USING_DMA
+                bool "Enable UART2 RX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART2_TX_USING_DMA
+                bool "Enable UART2 TX DMA"
+                depends on BSP_USING_UART2
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART3
+            bool "Enable UART3 (PC4/PC5)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART3
+            config BSP_UART3_RX_USING_DMA
+                bool "Enable UART3 RX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART3_TX_USING_DMA
+                bool "Enable UART3 TX DMA"
+                depends on BSP_USING_UART3
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+
+        config BSP_USING_UART4
+            bool "Enable UART4 (PC11/PC10)"
+            default n
+            select RT_USING_SERIAL
+
+        if BSP_USING_UART4
+            config BSP_UART4_RX_USING_DMA
+                bool "Enable UART4 RX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+
+            config BSP_UART4_TX_USING_DMA
+                bool "Enable UART4 TX DMA"
+                depends on BSP_USING_UART4
+                select RT_SERIAL_USING_DMA
+                default n
+        endif
+    endmenu
+
+    config BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    config BSP_USING_LPUART
+        bool "Enable LPUART"
+        select RT_USING_UART
+        default n
+
+    menu "Hardware I2C"
+        config BSP_USING_I2C1
+            bool "Enable I2C1"
+            default n
+            select RT_USING_I2C
+        config BSP_USING_I2C2
+            bool "Enable I2C2"
+            default n
+            select RT_USING_I2C
+    endmenu
+
+    menu "Hardware I2S"
+        config BSP_USING_I2S1
+            bool "Enable I2S1"
+            default n
+            select RT_USING_I2S
+    endmenu
+
+    menu "Hardware CAN"
+        config BSP_USING_CAN1
+            bool "Enable CAN1"
+            default n
+            select RT_USING_CAN
+        config BSP_USING_CAN2
+            bool "Enable CAN2"
+            default n
+            select RT_USING_CAN
+    endmenu
+
+    menu "Hardware TIMER"
+        config BSP_USING_TIM1
+            bool "Enable Timer1"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM2
+            bool "Enable Timer2"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM3
+            bool "Enable Timer3"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM4
+            bool "Enable Timer4"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM6
+            bool "Enable Timer6"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM7
+            bool "Enable Timer7"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM14
+            bool "Enable Timer14"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM15
+            bool "Enable Timer15"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM16
+            bool "Enable Timer16"
+            default n
+            select RT_USING_HWTIMER
+        config BSP_USING_TIM17
+            bool "Enable Timer17"
+            default n
+            select RT_USING_HWTIMER
+    endmenu
+
+    menu "Hardware WDT"
+        config BSP_USING_WDT
+            bool "Enable Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+        config BSP_USING_IWDT
+            bool "Enable Independent Watch Dog Timer"
+            default n
+            select RT_USING_WDT
+    endmenu
+
+    config BSP_USING_LCD
+        bool "Enable LCD"
+        default n
+
+    menu "Hardware SPI"
+        config BSP_USING_SPI1
+            bool "Enable SPI1"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI1
+            config BSP_SPI1_RX_USING_DMA
+                bool "Enable SPI1 RX DMA"
+                default n
+
+            config BSP_SPI1_TX_USING_DMA
+                bool "Enable SPI1 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI2
+            bool "Enable SPI2"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI2
+            config BSP_SPI2_RX_USING_DMA
+                bool "Enable SPI2 RX DMA"
+                default n
+
+            config BSP_SPI2_TX_USING_DMA
+                bool "Enable SPI2 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI3
+            bool "Enable SPI3"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI3
+            config BSP_SPI3_RX_USING_DMA
+                bool "Enable SPI3 RX DMA"
+                default n
+
+            config BSP_SPI3_TX_USING_DMA
+                bool "Enable SPI3 TX DMA"
+                default n
+        endif
+
+        config BSP_USING_SPI4
+            bool "Enable SPI4"
+            select RT_USING_SPI
+            default n
+
+        if BSP_USING_SPI4
+            config BSP_SPI4_RX_USING_DMA
+                bool "Enable SPI4 RX DMA"
+                default n
+
+            config BSP_SPI4_TX_USING_DMA
+                bool "Enable SPI4 TX DMA"
+                default n
+        endif
+    endmenu
+
+    menu "Hardware CRYPTO"
+        config BSP_USING_CRC
+            select RT_HWCRYPTO_USING_CRC
+            bool "Enable CRC"
+            default n
+            select RT_USING_HWCRYPTO
+        config BSP_USING_AES
+            select RT_HWCRYPTO_USING_AES
+            bool "Enable AES"
+            default n
+            select RT_USING_HWCRYPTO
+
+        config BSP_USING_HRNG
+            select RT_HWCRYPTO_USING_RNG
+            bool "Enable HRNG"
+            default n
+            select RT_USING_HWCRYPTO
+    endmenu
+
+    config BSP_USING_CMP
+        bool "Enable Analog Voltage Comparer"
+        default n
+
+    config BSP_USING_OPA
+        bool "Enable Operational Amplifier"
+        default n
+
+    config BSP_USING_TKEY
+        bool "Enable Touch Key"
+        select RT_USING_TOUCH
+        default n
+
+    config BSP_USING_RPMU
+        bool "Enable RTC PMU"
+        select RT_USING_PM
+        default n
+
+    config BSP_USING_USBD
+        bool "Enable USB Device"
+        select RT_USING_USB
+        default n
+
+endmenu
+
+menu "Board extended module Drivers"
+
+endmenu
+
+endmenu
+

bsp/acm32f4xx-nucleo/drivers/SConscript

@@ -0,0 +1,15 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd = GetCurrentDir()
+src = Glob('*.c')
+CPPPATH = [cwd]
+
+#remove other no use files
+#SrcRemove(src, '*.c')
+
+group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
+

bsp/acm32f4xx-nucleo/drivers/board.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-25     AisinoChip   first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "board.h"
+#include <rtdevice.h>
+
+#define SOC_SRAM_END_ADDR   (SOC_SRAM_START_ADDR+SOC_SRAM_SIZE*1024)
+
+extern int  rt_application_init(void);
+
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+    #pragma section="HEAP"
+#else
+    extern int __bss_end;
+#endif
+
+extern void rt_hw_uart_init(void);
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/**
+ * This function will initial EVB board.
+ */
+void rt_hw_board_init(void)
+{
+    /* system init, clock, NVIC */
+    System_Init();
+
+    /* Configure the SysTick */
+    SysTick_Config(System_Get_SystemClock() / RT_TICK_PER_SECOND);
+
+    rt_hw_uart_init();
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+
+#ifdef RT_USING_HEAP
+#if defined(__CC_ARM) || defined(__CLANG_ARM)
+    rt_system_heap_init((void *)&Image$$RW_IRAM1$$ZI$$Limit, (void *)SOC_SRAM_END_ADDR);
+#elif __ICCARM__
+    rt_system_heap_init(__segment_end("HEAP"), (void *)SOC_SRAM_END_ADDR);
+#else
+    /* init memory system */
+    rt_system_heap_init((void *)&__bss_end, (void *)SOC_SRAM_END_ADDR);
+#endif
+#endif /* RT_USING_HEAP */
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+

bsp/acm32f4xx-nucleo/drivers/board.h

@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-22     AisinoCip    add board.h to this bsp
+ */
+
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include <rtconfig.h>
+#include "ACM32Fxx_HAL.h"
+
+/*-------------------------- UART CONFIG BEGIN --------------------------*/
+
+/** After configuring corresponding UART or UART DMA, you can use it.
+  *
+  * STEP 1, define macro define related to the serial port opening based on the serial port number
+  *                 such as     #define BSP_USING_UATR1
+  *
+  * STEP 2, according to the corresponding pin of serial port, modify the related serial port information
+  *                 such as     #define UART1_TX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_RX_PORT            GPIOX   ->   GPIOA
+  *                             #define UART1_TX_PIN        GPIO_PIN_X   ->   GPIO_PIN_9
+  *                             #define UART1_RX_PIN        GPIO_PIN_X   ->   GPIO_PIN_10
+  *
+  * STEP 3, if you want using SERIAL DMA, you must open it in the RT-Thread Settings.
+  *                 RT-Thread Setting -> Components -> Device Drivers -> Serial Device Drivers -> Enable Serial DMA Mode
+  *
+  * STEP 4, according to serial port number to define serial port tx/rx DMA function in the board.h file
+  *                 such as     #define BSP_UART1_RX_USING_DMA
+  *
+  */
+
+#if defined(BSP_USING_UART1)
+    #define UART1_TX_PORT           GPIOA
+    #define UART1_RX_PORT           GPIOA
+    #define UART1_TX_PIN            GPIO_PIN_9
+    #define UART1_RX_PIN            GPIO_PIN_10
+
+    #if defined(BSP_UART1_RX_USING_DMA)
+        #define UART1_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART1_RX_DMA_RCC        BIT12
+        #define UART1_RX_DMA_IRQ        DMA_IRQn
+        #define UART1_RX_DMA_CHANNEL    0
+        #define UART1_RX_DMA_REQUEST    REQ6_UART1_RECV
+    #endif /* BSP_UART1_RX_USING_DMA */
+
+    #if defined(BSP_UART1_TX_USING_DMA)
+        #define UART1_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART1_TX_DMA_RCC        BIT12
+        #define UART1_TX_DMA_IRQ        DMA_IRQn
+        #define UART1_TX_DMA_CHANNEL    1
+        #define UART1_TX_DMA_REQUEST    REQ5_UART1_SEND
+    #endif /* BSP_UART1_TX_USING_DMA */
+
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+    #define UART2_TX_PORT           GPIOA
+    #define UART2_RX_PORT           GPIOA
+    #define UART2_TX_PIN            GPIO_PIN_2
+    #define UART2_RX_PIN            GPIO_PIN_3
+
+    #if defined(BSP_UART2_RX_USING_DMA)
+        #define UART2_RX_DMA_INSTANCE   DMA_Channel0
+        #define UART2_RX_DMA_RCC        BIT12
+        #define UART2_RX_DMA_IRQ        DMA_IRQn
+        #define UART2_RX_DMA_CHANNEL    0
+        #define UART2_RX_DMA_REQUEST    REQ8_UART2_RECV
+    #endif /* BSP_UART2_RX_USING_DMA */
+
+    #if defined(BSP_UART2_TX_USING_DMA)
+        #define UART2_TX_DMA_INSTANCE   DMA_Channel1
+        #define UART2_TX_DMA_RCC        BIT12
+        #define UART2_TX_DMA_IRQ        DMA_IRQn
+        #define UART2_TX_DMA_CHANNEL    1
+        #define UART2_TX_DMA_REQUEST    REQ7_UART2_SEND
+    #endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+    #define UART3_TX_PORT           GPIOB
+    #define UART3_RX_PORT           GPIOB
+    #define UART3_TX_PIN            GPIO_PIN_10
+    #define UART3_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART3_RX_USING_DMA)
+        #define UART3_RX_DMA_INSTANCE   DMA_Channel2
+        #define UART3_RX_DMA_RCC        BIT12
+        #define UART3_RX_DMA_IRQ        DMA_IRQn
+        #define UART3_RX_DMA_CHANNEL    2
+        #define UART3_RX_DMA_REQUEST    REQ29_UART3_RECV
+    #endif /* BSP_UART3_RX_USING_DMA */
+
+    #if defined(BSP_UART3_TX_USING_DMA)
+        #define UART3_TX_DMA_INSTANCE   DMA_Channel3
+        #define UART3_TX_DMA_RCC        BIT12
+        #define UART3_TX_DMA_IRQ        DMA_IRQn
+        #define UART3_TX_DMA_CHANNEL    3
+        #define UART3_TX_DMA_REQUEST    REQ27_UART3_SEND
+    #endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+    #define UART4_TX_PORT           GPIOC
+    #define UART4_RX_PORT           GPIOC
+    #define UART4_TX_PIN            GPIO_PIN_10
+    #define UART4_RX_PIN            GPIO_PIN_11
+
+    #if defined(BSP_UART4_RX_USING_DMA)
+        #define UART4_RX_DMA_INSTANCE   DMA_Channel4
+        #define UART4_RX_DMA_RCC        BIT12
+        #define UART4_RX_DMA_IRQ        DMA_IRQn
+        #define UART4_RX_DMA_CHANNEL    4
+        #define UART4_RX_DMA_REQUEST    REQ46_UART4_RECV
+    #endif /* BSP_UART4_RX_USING_DMA */
+
+    #if defined(BSP_UART4_TX_USING_DMA)
+        #define UART4_TX_DMA_INSTANCE   DMA_Channel5
+        #define UART4_TX_DMA_RCC        BIT12
+        #define UART4_TX_DMA_IRQ        DMA_IRQn
+        #define UART4_TX_DMA_CHANNEL    5
+        #define UART4_TX_DMA_REQUEST    REQ45_UART4_SEND
+    #endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+/*-------------------------- UART CONFIG END --------------------------*/
+
+/* board configuration */
+
+void rt_hw_board_init(void);
+
+#endif /* __BOARD_H__ */
+

bsp/acm32f4xx-nucleo/drivers/drv_gpio.c

@@ -0,0 +1,479 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author            Notes
+ * 2021-09-18     AisinoChip        first version
+ */
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include "board.h"
+
+#ifdef RT_USING_PIN
+
+#define __ACM32_PIN(index, gpio, gpio_index)                                \
+    {                                                                       \
+        index, GPIO##gpio, GPIO_PIN_##gpio_index                            \
+    }
+
+#define __ACM32_PIN_RESERVE                                                 \
+    {                                                                       \
+        -1, 0, 0                                                            \
+    }
+
+/* ACM32 GPIO driver */
+struct pin_index
+{
+    int             index;
+    enum_GPIOx_t    gpio;
+    uint32_t        pin;
+};
+
+struct pin_irq_map
+{
+    rt_uint16_t         line;
+    EXTI_HandleTypeDef  handle;
+};
+
+static const struct pin_index pins[] =
+{
+#if defined(BSP_USING_GPIO1)
+    __ACM32_PIN(0,   A, 0),
+    __ACM32_PIN(1,   A, 1),
+    __ACM32_PIN(2,   A, 2),
+    __ACM32_PIN(3,   A, 3),
+    __ACM32_PIN(4,   A, 4),
+    __ACM32_PIN(5,   A, 5),
+    __ACM32_PIN(6,   A, 6),
+    __ACM32_PIN(7,   A, 7),
+    __ACM32_PIN(8,   A, 8),
+    __ACM32_PIN(9,   A, 9),
+    __ACM32_PIN(10,  A, 10),
+    __ACM32_PIN(11,  A, 11),
+    __ACM32_PIN(12,  A, 12),
+    __ACM32_PIN(13,  A, 13),
+    __ACM32_PIN(14,  A, 14),
+    __ACM32_PIN(15,  A, 15),
+    __ACM32_PIN(16,  B, 0),
+    __ACM32_PIN(17,  B, 1),
+    __ACM32_PIN(18,  B, 2),
+    __ACM32_PIN(19,  B, 3),
+    __ACM32_PIN(20,  B, 4),
+    __ACM32_PIN(21,  B, 5),
+    __ACM32_PIN(22,  B, 6),
+    __ACM32_PIN(23,  B, 7),
+    __ACM32_PIN(24,  B, 8),
+    __ACM32_PIN(25,  B, 9),
+    __ACM32_PIN(26,  B, 10),
+    __ACM32_PIN(27,  B, 11),
+    __ACM32_PIN(28,  B, 12),
+    __ACM32_PIN(29,  B, 13),
+    __ACM32_PIN(30,  B, 14),
+    __ACM32_PIN(31,  B, 15),
+#if defined(BSP_USING_GPIO2)
+    __ACM32_PIN(32,  C, 0),
+    __ACM32_PIN(33,  C, 1),
+    __ACM32_PIN(34,  C, 2),
+    __ACM32_PIN(35,  C, 3),
+    __ACM32_PIN(36,  C, 4),
+    __ACM32_PIN(37,  C, 5),
+    __ACM32_PIN(38,  C, 6),
+    __ACM32_PIN(39,  C, 7),
+    __ACM32_PIN(40,  C, 8),
+    __ACM32_PIN(41,  C, 9),
+    __ACM32_PIN(42,  C, 10),
+    __ACM32_PIN(43,  C, 11),
+    __ACM32_PIN(44,  C, 12),
+    __ACM32_PIN(45,  C, 13),
+    __ACM32_PIN(46,  C, 14),
+    __ACM32_PIN(47,  C, 15),
+    __ACM32_PIN(48,  D, 0),
+    __ACM32_PIN(49,  D, 1),
+    __ACM32_PIN(50,  D, 2),
+    __ACM32_PIN(51,  D, 3),
+    __ACM32_PIN(52,  D, 4),
+    __ACM32_PIN(53,  D, 5),
+    __ACM32_PIN(54,  D, 6),
+    __ACM32_PIN(55,  D, 7),
+    __ACM32_PIN(56,  D, 8),
+    __ACM32_PIN(57,  D, 9),
+    __ACM32_PIN(58,  D, 10),
+    __ACM32_PIN(59,  D, 11),
+    __ACM32_PIN(60,  D, 12),
+    __ACM32_PIN(61,  D, 13),
+    __ACM32_PIN(62,  D, 14),
+    __ACM32_PIN(63,  D, 15),
+#if defined(BSP_USING_GPIO3)
+    __ACM32_PIN(64,  E, 0),
+    __ACM32_PIN(65,  E, 1),
+    __ACM32_PIN(66,  E, 2),
+    __ACM32_PIN(67,  E, 3),
+    __ACM32_PIN(68,  E, 4),
+    __ACM32_PIN(69,  E, 5),
+    __ACM32_PIN(70,  E, 6),
+    __ACM32_PIN(71,  E, 7),
+    __ACM32_PIN(72,  E, 8),
+    __ACM32_PIN(73,  E, 9),
+    __ACM32_PIN(74,  E, 10),
+    __ACM32_PIN(75,  E, 11),
+    __ACM32_PIN(76,  E, 12),
+    __ACM32_PIN(77,  E, 13),
+    __ACM32_PIN(78,  E, 14),
+    __ACM32_PIN(79,  E, 15),
+    __ACM32_PIN(80,  F, 0),
+    __ACM32_PIN(81,  F, 1),
+    __ACM32_PIN(82,  F, 2),
+    __ACM32_PIN(83,  F, 3),
+    __ACM32_PIN(84,  F, 4),
+#endif /* defined(BSP_USING_GPIO3) */
+#endif /* defined(BSP_USING_GPIO2) */
+#endif /* defined(BSP_USING_GPIO1) */
+};
+
+static struct pin_irq_map pin_irq_map[] =
+{
+    {EXTI_LINE_0,  {0}},
+    {EXTI_LINE_1,  {0}},
+    {EXTI_LINE_2,  {0}},
+    {EXTI_LINE_3,  {0}},
+    {EXTI_LINE_4,  {0}},
+    {EXTI_LINE_5,  {0}},
+    {EXTI_LINE_6,  {0}},
+    {EXTI_LINE_7,  {0}},
+    {EXTI_LINE_8,  {0}},
+    {EXTI_LINE_9,  {0}},
+    {EXTI_LINE_10, {0}},
+    {EXTI_LINE_11, {0}},
+    {EXTI_LINE_12, {0}},
+    {EXTI_LINE_13, {0}},
+    {EXTI_LINE_14, {0}},
+    {EXTI_LINE_15, {0}},
+};
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
+{
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+    {-1, 0, RT_NULL, RT_NULL},
+};
+static uint32_t pin_irq_enable_mask = 0;
+
+#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
+static const struct pin_index *get_pin(uint8_t pin)
+{
+    const struct pin_index *index;
+
+    if (pin < ITEM_NUM(pins))
+    {
+        index = &pins[pin];
+        if (index->index == -1)
+            index = RT_NULL;
+    }
+    else
+    {
+        index = RT_NULL;
+    }
+
+    return index;
+};
+
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    const struct pin_index *index;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    HAL_GPIO_WritePin(index->gpio, index->pin, (enum_PinState_t)value);
+}
+
+static int _pin_read(rt_device_t dev, rt_base_t pin)
+{
+    int value;
+    const struct pin_index *index;
+
+    value = PIN_LOW;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return value;
+    }
+
+    value = HAL_GPIO_ReadPin(index->gpio, index->pin);
+
+    return value;
+}
+
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    const struct pin_index *index;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return;
+    }
+
+    /* Configure GPIO_InitStructure */
+    GPIO_InitStruct.Pin = index->pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+
+    if (mode == PIN_MODE_OUTPUT)
+    {
+        /* output setting */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT)
+    {
+        /* input setting: not pull. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLUP)
+    {
+        /* input setting: pull up. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLUP;
+    }
+    else if (mode == PIN_MODE_INPUT_PULLDOWN)
+    {
+        /* input setting: pull down. */
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+        GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+    }
+    else if (mode == PIN_MODE_OUTPUT_OD)
+    {
+        /* output setting: od. */
+        GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+        GPIO_InitStruct.Pull = GPIO_NOPULL;
+    }
+
+    /* special PIN process */
+    __HAL_RTC_PC13_DIGIT();
+
+    HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+}
+
+#define     PIN2INDEX(pin)      ((pin) % 16)
+
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                     rt_uint32_t mode, void (*hdr)(void *args), void *args)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == pin &&
+            pin_irq_hdr_tab[irqindex].hdr == hdr &&
+            pin_irq_hdr_tab[irqindex].mode == mode &&
+            pin_irq_hdr_tab[irqindex].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    if (pin_irq_hdr_tab[irqindex].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EBUSY;
+    }
+
+    pin_irq_hdr_tab[irqindex].pin = pin;
+    pin_irq_hdr_tab[irqindex].hdr = hdr;
+    pin_irq_hdr_tab[irqindex].mode = mode;
+    pin_irq_hdr_tab[irqindex].args = args;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    const struct pin_index *index;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+
+    level = rt_hw_interrupt_disable();
+    if (pin_irq_hdr_tab[irqindex].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+    pin_irq_hdr_tab[irqindex].pin = -1;
+    pin_irq_hdr_tab[irqindex].hdr = RT_NULL;
+    pin_irq_hdr_tab[irqindex].mode = 0;
+    pin_irq_hdr_tab[irqindex].args = RT_NULL;
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                     rt_uint32_t enabled)
+{
+    const struct pin_index *index;
+    struct pin_irq_map *irqmap;
+    rt_base_t level;
+    rt_int32_t irqindex = -1;
+    GPIO_InitTypeDef GPIO_InitStruct;
+
+    index = get_pin(pin);
+    if (index == RT_NULL)
+    {
+        return RT_ENOSYS;
+    }
+
+    irqindex = PIN2INDEX(pin);
+    irqmap = &pin_irq_map[irqindex];
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if (pin_irq_hdr_tab[irqindex].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return RT_ENOSYS;
+        }
+
+        /* Configure GPIO_InitStructure */
+        GPIO_InitStruct.Pin = index->pin;
+        GPIO_InitStruct.Alternate = GPIO_FUNCTION_0;
+        GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
+
+        irqmap->handle.u32_Line = irqmap->line;
+        irqmap->handle.u32_Mode = EXTI_MODE_INTERRUPT;
+
+        switch (pin_irq_hdr_tab[irqindex].mode)
+        {
+        case PIN_IRQ_MODE_RISING:
+            GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING;
+            break;
+        case PIN_IRQ_MODE_FALLING:
+            GPIO_InitStruct.Pull = GPIO_PULLUP;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_FALLING;
+            break;
+        case PIN_IRQ_MODE_RISING_FALLING:
+            GPIO_InitStruct.Pull = GPIO_NOPULL;
+            irqmap->handle.u32_Trigger = EXTI_TRIGGER_RISING_FALLING;
+            break;
+        }
+        HAL_GPIO_Init(index->gpio, &GPIO_InitStruct);
+
+        irqmap->handle.u32_GPIOSel = pin / 16;
+
+        HAL_EXTI_SetConfigLine(&irqmap->handle);
+
+        pin_irq_enable_mask |= 1 << irqindex;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if (enabled == PIN_IRQ_DISABLE)
+    {
+        if ((pin_irq_enable_mask & (1 << irqindex)) == 0)
+        {
+            return RT_ENOSYS;
+        }
+
+        level = rt_hw_interrupt_disable();
+
+        EXTI->IENR &= ~irqmap->line;
+        EXTI->EENR &= ~irqmap->line;
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops _acm32_pin_ops =
+{
+    _pin_mode,
+    _pin_write,
+    _pin_read,
+    _pin_attach_irq,
+    _pin_dettach_irq,
+    _pin_irq_enable,
+};
+
+rt_inline void pin_irq_hdr(int irqno)
+{
+    if (pin_irq_hdr_tab[irqno].hdr)
+    {
+        pin_irq_hdr_tab[irqno].hdr(pin_irq_hdr_tab[irqno].args);
+    }
+}
+
+int rt_hw_pin_init(void)
+{
+    return rt_device_pin_register("pin", &_acm32_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+void EXTI_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < 16; i++)
+    {
+        if (EXTI->PDR & pin_irq_map[i].line)
+        {
+            EXTI->PDR = pin_irq_map[i].line;
+            pin_irq_hdr(i);
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+#endif /* RT_USING_PIN */
+

bsp/acm32f4xx-nucleo/drivers/drv_uart.c

@@ -0,0 +1,663 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "board.h"
+#include "uart_config.h"
+
+#ifdef RT_USING_SERIAL
+
+#ifdef RT_SERIAL_USING_DMA
+struct dma_config
+{
+    DMA_Channel_TypeDef *Instance;
+    rt_uint32_t         dma_rcc;
+    IRQn_Type           dma_irq;
+
+    rt_uint32_t         channel;
+    rt_uint32_t         request;
+};
+#endif
+
+#ifdef RT_SERIAL_USING_DMA
+    static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag);
+#endif /* RT_SERIAL_USING_DMA */
+
+struct acm32_uart_config
+{
+    const char          *name;
+    UART_TypeDef        *Instance;
+    IRQn_Type           irq_type;
+    enum_Enable_ID_t    enable_id;
+
+#ifdef RT_SERIAL_USING_DMA
+    struct dma_config   *dma_rx;
+    struct dma_config   *dma_tx;
+#endif
+
+    enum_GPIOx_t        tx_port;
+    enum_GPIOx_t        rx_port;
+    rt_uint32_t         tx_pin;
+    rt_uint32_t         rx_pin;
+};
+
+struct acm32_uart
+{
+    UART_HandleTypeDef          handle;
+    struct acm32_uart_config    *config;
+#ifdef RT_SERIAL_USING_DMA
+    struct
+    {
+        DMA_HandleTypeDef       handle;
+        rt_size_t               last_index;
+    } dma_rx;
+
+    struct
+    {
+        DMA_HandleTypeDef       handle;
+    } dma_tx;
+#endif
+
+    rt_uint16_t                 uart_dma_flag;
+    struct rt_serial_device     serial;
+};
+
+static rt_err_t uart_rx_indicate_cb(rt_device_t dev, rt_size_t size)
+{
+    return RT_EOK;
+}
+
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    uart->handle.Instance = uart->config->Instance;
+
+    uart->handle.Init.BaudRate = cfg->baud_rate;
+    if (cfg->data_bits == DATA_BITS_8)
+    {
+        uart->handle.Init.WordLength = UART_WORDLENGTH_8B;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    if (cfg->stop_bits == STOP_BITS_1)
+    {
+        uart->handle.Init.StopBits = UART_STOPBITS_1;
+    }
+    else if (cfg->stop_bits == STOP_BITS_2)
+    {
+        uart->handle.Init.StopBits = UART_STOPBITS_2;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    if (cfg->parity == PARITY_NONE)
+    {
+        uart->handle.Init.Parity = UART_PARITY_NONE;
+    }
+    else if (cfg->parity == PARITY_ODD)
+    {
+        uart->handle.Init.Parity = UART_PARITY_ODD;
+    }
+    else if (cfg->parity == PARITY_EVEN)
+    {
+        uart->handle.Init.Parity = UART_PARITY_EVEN;
+    }
+    else     /* not support */
+    {
+        return -RT_EINVAL;
+    }
+
+    uart->handle.Init.Mode       = UART_MODE_TX_RX;
+    uart->handle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+
+    HAL_UART_Init(&uart->handle);
+
+    uart->handle.Instance->LCRH &= ~UART_LCRH_FEN;
+    return RT_EOK;
+}
+
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct acm32_uart *uart;
+#ifdef RT_SERIAL_USING_DMA
+    rt_ubase_t ctrl_arg = (rt_ubase_t)arg;
+#endif
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        NVIC_DisableIRQ(uart->config->irq_type);
+        /* Disable RX interrupt */
+        uart->handle.Instance->IE &= ~UART_IE_RXI;
+        break;
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        NVIC_EnableIRQ(uart->config->irq_type);
+        /* Enable RX interrupt */
+        uart->handle.Instance->IE |= UART_IE_RXI;
+        break;
+#ifdef RT_SERIAL_USING_DMA
+    /* UART config */
+    case RT_DEVICE_CTRL_CONFIG :
+        DMA_Configuration(serial, (rt_uint32_t)ctrl_arg);
+        rt_device_set_rx_indicate((rt_device_t)serial, uart_rx_indicate_cb);
+        break;
+#endif /* RT_SERIAL_USING_DMA */
+    }
+    return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    while (uart->handle.Instance->FR & UART_FR_TXFF);    /* wait Tx FIFO not full */
+    uart->handle.Instance->DR = c;
+    while ((uart->handle.Instance->FR & UART_FR_BUSY)); /* wait TX Complete */
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+
+    int ch;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    ch = -1;
+    if (!(uart->handle.Instance->FR & UART_FR_RXFE))   /* Rx FIFO not empty */
+    {
+        ch = uart->handle.Instance->DR & 0xff;
+    }
+
+    return ch;
+}
+
+#ifdef RT_SERIAL_USING_DMA
+/**
+ * Serial port receive idle process. This need add to uart idle ISR.
+ *
+ * @param serial serial device
+ */
+static void dma_uart_rx_idle_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    rt_size_t recv_total_index, recv_len;
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    recv_total_index = uart->handle.lu32_RxSize - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
+    recv_len = recv_total_index - uart->handle.lu32_RxCount;
+    uart->handle.lu32_RxCount = recv_total_index;
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+}
+
+/*
+ DMA receive done process. This need add to DMA receive done ISR.
+
+ @param serial serial device
+*/
+static void dma_rx_done_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart;
+    struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    rt_size_t recv_len;
+    rt_base_t level;
+
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
+
+    recv_len = serial->config.bufsz - (uart->handle.HDMA_Rx->Instance->CTRL & 0xFFF);
+    uart->dma_rx.last_index = 0;
+
+    DMA->INT_TC_CLR |= 1 << (uart->config->dma_rx->channel);      /* clear channel0 TC flag */
+
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
+
+    if (recv_len)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8));
+    }
+
+    HAL_UART_Receive_DMA(&(uart->handle), &rx_fifo->buffer[rx_fifo->put_index], serial->config.bufsz);
+}
+
+static rt_size_t _uart_dma_transmit(struct rt_serial_device *serial, rt_uint8_t *buf, rt_size_t size, int direction)
+{
+    struct acm32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    if (size == 0)
+    {
+        return 0;
+    }
+
+    if (RT_SERIAL_DMA_TX == direction)
+    {
+        if (HAL_UART_Transmit_DMA(&uart->handle, buf, size) == HAL_OK)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE);
+            return size;
+        }
+        else
+        {
+            return 0;
+        }
+    }
+    return 0;
+}
+
+#endif /* RT_SERIAL_USING_DMA */
+
+static const struct rt_uart_ops acm32_uart_ops =
+{
+    _uart_configure,
+    _uart_control,
+    _uart_putc,
+    _uart_getc,
+#ifdef RT_SERIAL_USING_DMA
+    _uart_dma_transmit,
+#endif
+};
+
+#ifdef RT_SERIAL_USING_DMA
+static void DMA_Configuration(struct rt_serial_device *serial, rt_uint32_t flag)
+{
+    struct rt_serial_rx_fifo *rx_fifo;
+    DMA_HandleTypeDef *DMA_Handle;
+    struct dma_config *dma_config;
+    struct acm32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        DMA_Handle = &uart->dma_rx.handle;
+        dma_config = uart->config->dma_rx;
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        DMA_Handle = &uart->dma_tx.handle;
+        dma_config = uart->config->dma_tx;
+    }
+    else
+    {
+        return;
+    }
+
+    DMA_Handle->Instance                 = dma_config->Instance;
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        DMA_Handle->Init.Data_Flow          = DMA_DATA_FLOW_P2M;
+        DMA_Handle->Init.Mode               = DMA_NORMAL;
+        DMA_Handle->Init.Source_Inc         = DMA_SOURCE_ADDR_INCREASE_DISABLE;
+        DMA_Handle->Init.Desination_Inc     = DMA_DST_ADDR_INCREASE_ENABLE;
+
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        DMA_Handle->Init.Data_Flow          = DMA_DATA_FLOW_M2P;
+        DMA_Handle->Init.Mode               = DMA_NORMAL;
+        DMA_Handle->Init.Source_Inc         = DMA_SOURCE_ADDR_INCREASE_ENABLE;
+        DMA_Handle->Init.Desination_Inc     = DMA_DST_ADDR_INCREASE_DISABLE;
+    }
+
+    DMA_Handle->Init.Request_ID             = dma_config->request;
+    DMA_Handle->Init.Source_Width           = DMA_SRC_WIDTH_BYTE;
+    DMA_Handle->Init.Desination_Width       = DMA_DST_WIDTH_BYTE;
+
+    if (HAL_DMA_Init(DMA_Handle) != HAL_OK)
+    {
+        RT_ASSERT(0);
+    }
+
+    if (RT_DEVICE_FLAG_DMA_RX == flag)
+    {
+        __HAL_LINK_DMA(uart->handle, HDMA_Rx, uart->dma_rx.handle);
+    }
+    else if (RT_DEVICE_FLAG_DMA_TX == flag)
+    {
+        __HAL_LINK_DMA(uart->handle, HDMA_Tx, uart->dma_tx.handle);
+    }
+    /* enable interrupt */
+    if (flag == RT_DEVICE_FLAG_DMA_RX)
+    {
+        rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx;
+        /* Start DMA transfer */
+        if (HAL_UART_Receive_DMA(&(uart->handle), rx_fifo->buffer, serial->config.bufsz) != HAL_OK)
+        {
+            /* Transfer error in reception process */
+            RT_ASSERT(0);
+        }
+
+    }
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+enum
+{
+#ifdef BSP_USING_UART1
+    UART1_INDEX,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_INDEX,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_INDEX,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_INDEX,
+#endif
+    UART_MAX_INDEX,
+};
+
+static struct acm32_uart_config uart_config[] =
+{
+#ifdef BSP_USING_UART1
+    UART1_CONFIG,
+#endif
+#ifdef BSP_USING_UART2
+    UART2_CONFIG,
+#endif
+#ifdef BSP_USING_UART3
+    UART3_CONFIG,
+#endif
+#ifdef BSP_USING_UART4
+    UART4_CONFIG,
+#endif
+};
+
+static struct acm32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+#ifdef RT_SERIAL_USING_DMA
+static void uart_get_dma_config(void)
+{
+#if defined(BSP_USING_UART1)
+#if defined(BSP_UART1_RX_USING_DMA)
+    static struct dma_config uart1_rx_dma_conf = UART1_DMA_RX_CONFIG;
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART1_INDEX].dma_rx = &uart1_rx_dma_conf;
+#endif /* BSP_UART1_RX_USING_DMA */
+#if defined(BSP_UART1_TX_USING_DMA)
+    static struct dma_config uart1_tx_dma_conf = UART1_DMA_TX_CONFIG;
+    uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART1_INDEX].dma_tx = &uart1_tx_dma_conf;
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+#if defined(BSP_UART2_RX_USING_DMA)
+    static struct dma_config uart2_rx_dma_conf = UART2_DMA_RX_CONFIG;
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART2_INDEX].dma_rx = &uart2_rx_dma_conf;
+#endif /* BSP_UART2_RX_USING_DMA */
+#if defined(BSP_UART2_TX_USING_DMA)
+    static struct dma_config uart2_tx_dma_conf = UART2_DMA_TX_CONFIG;
+    uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART2_INDEX].dma_tx = &uart2_tx_dma_conf;
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+#if defined(BSP_UART3_RX_USING_DMA)
+    static struct dma_config uart3_rx_dma_conf = UART3_DMA_RX_CONFIG;
+    uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART3_INDEX].dma_rx = &uart3_rx_dma_conf;
+#endif /* BSP_UART3_RX_USING_DMA */
+#if defined(BSP_UART3_TX_USING_DMA)
+    static struct dma_config uart3_tx_dma_conf = UART3_DMA_TX_CONFIG;
+    uart_obj[UART3_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART3_INDEX].dma_tx = &uart3_tx_dma_conf;
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+#if defined(BSP_UART4_RX_USING_DMA)
+    static struct dma_config uart4_rx_dma_conf = UART4_DMA_RX_CONFIG;
+    uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX;
+    uart_config[UART4_INDEX].dma_rx = &uart4_rx_dma_conf;
+#endif /* BSP_UART4_RX_USING_DMA */
+#if defined(BSP_UART3_TX_USING_DMA)
+    static struct dma_config uart4_tx_dma_conf = UART4_DMA_TX_CONFIG;
+    uart_obj[UART4_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX;
+    uart_config[UART4_INDEX].dma_tx = &uart4_tx_dma_conf;
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* BSP_USING_UART4 */
+}
+#endif
+
+rt_err_t rt_hw_uart_init(void)
+{
+    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct acm32_uart);
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    rt_err_t rc = RT_EOK;
+
+#ifdef RT_SERIAL_USING_DMA
+    uart_get_dma_config();
+#endif
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        uart_obj[i].config          = &uart_config[i];
+
+        uart_obj[i].serial.ops      = &acm32_uart_ops;
+        uart_obj[i].serial.config   = config;
+
+        /* register UART device */
+        rc = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name,
+                                   RT_DEVICE_FLAG_RDWR
+                                   | RT_DEVICE_FLAG_INT_RX
+                                   | RT_DEVICE_FLAG_INT_TX
+                                   | uart_obj[i].uart_dma_flag
+                                   , NULL);
+        RT_ASSERT(rc == RT_EOK);
+    }
+
+    return rc;
+}
+
+static void uart_isr(struct rt_serial_device *serial)
+{
+    struct acm32_uart *uart = rt_container_of(serial, struct acm32_uart, serial);
+
+    RT_ASSERT(serial != RT_NULL);
+
+    /* receive interrupt enabled */
+    if (uart->handle.Instance->IE & UART_IE_RXI)
+    {
+        if (uart->handle.Instance->RIS & UART_RIS_RXI)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+        }
+    }
+
+#ifdef RT_SERIAL_USING_DMA
+    if (uart->handle.Instance->IE & UART_IE_RTI)   /* Receive TimeOut Interrupt */
+    {
+        dma_uart_rx_idle_isr(serial);
+        /* Clear RTI Status */
+        uart->handle.Instance->ICR = UART_ICR_RTI;
+    }
+#endif /* RT_SERIAL_USING_DMA */
+
+    if (uart->handle.Instance->IE & UART_IE_TXI && \
+            uart->handle.Instance->RIS & UART_RIS_TXI)
+    {
+        /* Clear TXI Status */
+        uart->handle.Instance->ICR = UART_ICR_TXI;
+        if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX)
+        {
+            rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DONE);
+        }
+        /* Disable TX interrupt */
+        uart->handle.Instance->IE &= ~UART_IE_TXI;
+    }
+}
+
+#if defined(BSP_USING_UART1)
+void UART1_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART1_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+void UART2_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART2_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+void UART3_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART3_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+void UART4_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    uart_isr(&uart_obj[UART4_INDEX].serial);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART4 */
+
+#ifdef RT_SERIAL_USING_DMA
+void DMA_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    for (int i = 0; i < UART_MAX_INDEX; i++)
+    {
+        if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_rx->channel))
+        {
+            dma_rx_done_isr(&uart_obj[i].serial);
+            break;
+        }
+
+        if (DMA->RAW_INT_TC_STATUS & (1 << uart_obj[i].config->dma_tx->channel))
+        {
+            DMA->INT_TC_CLR |= 1 << (uart_obj[i].config->dma_tx->channel);      /* clear channel0 TC flag */
+            break;
+        }
+    }
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* RT_SERIAL_USING_DMA */
+
+void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+    struct acm32_uart *uart;
+    GPIO_InitTypeDef  GPIO_Uart;
+
+    RT_ASSERT(huart != RT_NULL);
+
+    /* get uart object */
+    uart = rt_container_of(huart, struct acm32_uart, handle);
+
+    /* Enable Clock */
+    System_Module_Enable(uart->config->enable_id);
+
+    /* Initialization GPIO */
+    GPIO_Uart.Pin       = uart->config->tx_pin;
+    GPIO_Uart.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Uart.Pull      = GPIO_PULLUP;
+    GPIO_Uart.Alternate = GPIO_FUNCTION_2;
+    HAL_GPIO_Init(uart->config->tx_port, &GPIO_Uart);
+
+    GPIO_Uart.Pin       = uart->config->rx_pin;
+    GPIO_Uart.Mode      = GPIO_MODE_AF_PP;
+    GPIO_Uart.Pull      = GPIO_PULLUP;
+    GPIO_Uart.Alternate = GPIO_FUNCTION_2;
+    HAL_GPIO_Init(uart->config->rx_port, &GPIO_Uart);
+
+    /* NVIC Config */
+    NVIC_ClearPendingIRQ(uart->config->irq_type);
+    NVIC_SetPriority(uart->config->irq_type, 5);
+    NVIC_EnableIRQ(uart->config->irq_type);
+}
+
+#endif /* RT_USING_SEARIAL */
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.icf

@@ -0,0 +1,34 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0007FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x2002FFFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x0800;
+define symbol __ICFEDIT_size_heap__   = 0x0000;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region ROM_region      = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region      = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block CSTACK, block HEAP };
+
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.lds

@@ -0,0 +1,156 @@
+/*
+ * linker script for ACM32F4xx with GNU ld
+ */
+
+/* describes the location and size of blocks of memory in the target. */
+MEMORY
+{
+    CODE (rx) : ORIGIN = 0x00000000, LENGTH = 512k /* 512KB flash */
+    DATA (rw) : ORIGIN = 0x20000000, LENGTH = 192k /* 192KB sram */
+}
+/* Program Entry, set to mark it as "used" and avoid gc */
+ENTRY(Reset_Handler)
+_system_stack_size = 0x800;
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+        _stext = .;
+        KEEP(*(.isr_vector))            /* Startup code */
+        . = ALIGN(4);
+        *(.text)                        /* remaining code */
+        *(.text.*)                      /* remaining code */
+        *(.rodata)                      /* read-only data (constants) */
+        *(.rodata*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.gnu.linkonce.t*)
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for initial. */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+        . = ALIGN(4);
+
+        PROVIDE(__ctors_start__ = .);
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        PROVIDE(__ctors_end__ = .);
+
+        . = ALIGN(4);
+        _etext = .;
+    } > CODE
+
+    /* .ARM.exidx is sorted, so has to go in its own output section.  */
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+
+        /* This is used by the startup in order to initialize the .data secion */
+        _sidata = .;
+    } > CODE
+    __exidx_end = .;
+
+    /* .data section which is used for initialized data */
+
+    .data : AT (_sidata)
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _sdata = . ;
+
+        *(.data)
+        *(.data.*)
+        *(.gnu.linkonce.d*)
+
+
+        PROVIDE(__dtors_start__ = .);
+        KEEP(*(SORT(.dtors.*)))
+        KEEP(*(.dtors))
+        PROVIDE(__dtors_end__ = .);
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .data secion */
+        _edata = . ;
+    } >DATA
+
+    .stack :
+    {
+        . = ALIGN(8);
+        _sstack = .;
+        . = . + _system_stack_size;
+        . = ALIGN(8);
+        _estack = .;
+    } >DATA
+
+    __bss_start = .;
+    .bss :
+    {
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _sbss = .;
+
+        *(.bss)
+        *(.bss.*)
+        *(COMMON)
+
+        . = ALIGN(4);
+        /* This is used by the startup in order to initialize the .bss secion */
+        _ebss = . ;
+
+        *(.bss.init)
+    } > DATA
+    __bss_end = .;
+
+    _end = .;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+}
+

bsp/acm32f4xx-nucleo/drivers/linker_scripts/link.sct

@@ -0,0 +1,16 @@
+; *************************************************************
+; *** Scatter-Loading Description File generated by uVision ***
+; *************************************************************
+
+LR_IROM1 0x00000000 0x00080000  {    ; load region size_region
+  ER_IROM1 0x00000000 0x00080000  {  ; load address = execution address
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+   .ANY (+XO)
+  }
+  RW_IRAM1 0x20000000 0x00030000  {  ; RW data
+   .ANY (+RW +ZI)
+  }
+}
+

bsp/acm32f4xx-nucleo/drivers/uart_config.h

@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-08-23     AisinoChip   the first version
+ */
+
+#ifndef __UART_CONFIG_H__
+#define __UART_CONFIG_H__
+
+#include <rtthread.h>
+#include "board.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(RT_USING_SERIAL)
+
+#if defined(BSP_USING_UART1)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART1_RX_USING_DMA)
+#ifndef UART1_DMA_RX_CONFIG
+#define UART1_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_RX_DMA_RCC,                               \
+        .dma_irq  = UART1_RX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_RX_CONFIG */
+#endif /* BSP_UART1_RX_USING_DMA */
+
+#if defined(BSP_UART1_TX_USING_DMA)
+#ifndef UART1_DMA_TX_CONFIG
+#define UART1_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART1_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART1_TX_DMA_RCC,                               \
+        .dma_irq  = UART1_TX_DMA_IRQ,                               \
+        .channel  = UART1_RX_DMA_CHANNEL,                           \
+        .request  = UART1_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART1_DMA_TX_CONFIG */
+#endif /* BSP_UART1_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART1_CONFIG
+#define UART1_CONFIG                                                \
+    {                                                               \
+        .name = "uart1",                                            \
+        .Instance = UART1,                                          \
+        .irq_type = UART1_IRQn,                                     \
+        .enable_id = EN_UART1,                                      \
+        .tx_port  = UART1_TX_PORT,                                  \
+        .rx_port  = UART1_RX_PORT,                                  \
+        .tx_pin   = UART1_TX_PIN,                                   \
+        .rx_pin   = UART1_RX_PIN,                                   \
+    }
+#endif /* UART1_CONFIG */
+#endif /* BSP_USING_UART1 */
+
+#if defined(BSP_USING_UART2)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART2_RX_USING_DMA)
+#ifndef UART2_DMA_RX_CONFIG
+#define UART2_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_RX_DMA_RCC,                               \
+        .dma_irq  = UART2_RX_DMA_IRQ,                               \
+        .channel  = UART2_RX_DMA_CHANNEL,                           \
+        .request  = UART2_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_RX_CONFIG */
+#endif /* BSP_UART2_RX_USING_DMA */
+
+#if defined(BSP_UART2_TX_USING_DMA)
+#ifndef UART2_DMA_TX_CONFIG
+#define UART2_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART2_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART2_TX_DMA_RCC,                               \
+        .dma_irq  = UART2_TX_DMA_IRQ,                               \
+        .channel  = UART2_TX_DMA_CHANNEL,                           \
+        .request  = UART2_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART2_DMA_TX_CONFIG */
+#endif /* BSP_UART2_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART2_CONFIG
+#define UART2_CONFIG                                                \
+    {                                                               \
+        .name = "uart2",                                            \
+        .Instance = UART2,                                          \
+        .irq_type = UART2_IRQn,                                     \
+        .enable_id = EN_UART2,                                      \
+        .tx_port  = UART2_TX_PORT,                                  \
+        .rx_port  = UART2_RX_PORT,                                  \
+        .tx_pin   = UART2_TX_PIN,                                   \
+        .rx_pin   = UART2_RX_PIN,                                   \
+    }
+#endif /* UART2_CONFIG */
+#endif /* BSP_USING_UART2 */
+
+#if defined(BSP_USING_UART3)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART3_RX_USING_DMA)
+#ifndef UART3_DMA_RX_CONFIG
+#define UART3_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_RX_DMA_RCC,                               \
+        .dma_irq  = UART3_RX_DMA_IRQ,                               \
+        .channel  = UART3_RX_DMA_CHANNEL,                           \
+        .request  = UART3_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_RX_CONFIG */
+#endif /* BSP_UART3_RX_USING_DMA */
+
+#if defined(BSP_UART3_TX_USING_DMA)
+#ifndef UART3_DMA_TX_CONFIG
+#define UART3_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART3_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART3_TX_DMA_RCC,                               \
+        .dma_irq  = UART3_TX_DMA_IRQ,                               \
+        .channel  = UART3_TX_DMA_CHANNEL,                           \
+        .request  = UART3_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART3_DMA_TX_CONFIG */
+#endif /* BSP_UART3_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART3_CONFIG
+#define UART3_CONFIG                                                \
+    {                                                               \
+        .name = "uart3",                                            \
+        .Instance = UART3,                                          \
+        .irq_type = UART3_IRQn,                                     \
+        .enable_id = EN_UART3,                                      \
+        .tx_port  = UART3_TX_PORT,                                  \
+        .rx_port  = UART3_RX_PORT,                                  \
+        .tx_pin   = UART3_TX_PIN,                                   \
+        .rx_pin   = UART3_RX_PIN,                                   \
+    }
+#endif /* UART3_CONFIG */
+#endif /* BSP_USING_UART3 */
+
+#if defined(BSP_USING_UART4)
+
+#if defined(RT_SERIAL_USING_DMA)
+#if defined(BSP_UART4_RX_USING_DMA)
+#ifndef UART4_DMA_RX_CONFIG
+#define UART4_DMA_RX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_RX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_RX_DMA_RCC,                               \
+        .dma_irq  = UART4_RX_DMA_IRQ,                               \
+        .channel  = UART4_RX_DMA_CHANNEL,                           \
+        .request  = UART4_RX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_RX_CONFIG */
+#endif /* BSP_UART4_RX_USING_DMA */
+
+#if defined(BSP_UART4_TX_USING_DMA)
+#ifndef UART4_DMA_TX_CONFIG
+#define UART4_DMA_TX_CONFIG                                         \
+    {                                                               \
+        .Instance = UART4_TX_DMA_INSTANCE,                          \
+        .dma_rcc  = UART4_TX_DMA_RCC,                               \
+        .dma_irq  = UART4_TX_DMA_IRQ,                               \
+        .channel  = UART4_TX_DMA_CHANNEL,                           \
+        .request  = UART4_TX_DMA_REQUEST,                           \
+    }
+#endif /* UART4_DMA_TX_CONFIG */
+#endif /* BSP_UART4_TX_USING_DMA */
+#endif /* RT_SERIAL_USING_DMA */
+
+#ifndef UART4_CONFIG
+#define UART4_CONFIG                                                \
+    {                                                               \
+        .name = "uart4",                                            \
+        .Instance = UART4,                                          \
+        .irq_type = UART4_IRQn,                                     \
+        .enable_id = EN_UART4,                                      \
+        .tx_port  = UART4_TX_PORT,                                  \
+        .rx_port  = UART4_RX_PORT,                                  \
+        .tx_pin   = UART4_TX_PIN,                                   \
+        .rx_pin   = UART4_RX_PIN,                                   \
+    }
+#endif /* UART4_CONFIG */
+#endif /* BSP_USING_UART4 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* RT_USING_SERIAL */
+
+#endif /* __UART_CONFIG_H__ */
+

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_armclang.h

@@ -0,0 +1,1444 @@
+/**************************************************************************//**
+ * @file     cmsis_armclang.h
+ * @brief    CMSIS compiler armclang (Arm Compiler 6) header file
+ * @version  V5.2.0
+ * @date     08. May 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */
+
+#ifndef __CMSIS_ARMCLANG_H
+#define __CMSIS_ARMCLANG_H
+
+#pragma clang system_header   /* treat file as system include file */
+
+#ifndef __ARM_COMPAT_H
+#include <arm_compat.h>    /* Compatibility header for Arm Compiler 5 intrinsics */
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static __inline
+#endif
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma clang diagnostic push
+  #pragma clang diagnostic ignored "-Wpacked"
+/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma clang diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __main
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              Image$$ARM_LIB_STACK$$ZI$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             Image$$ARM_LIB_STACK$$ZI$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute((used, section("RESET")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();  see arm_compat.h */
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq   /* see arm_compat.h */
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __get_FPSCR      (uint32_t)__builtin_arm_get_fpscr
+#else
+#define __get_FPSCR()      ((uint32_t)0U)
+#endif
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#define __set_FPSCR      __builtin_arm_set_fpscr
+#else
+#define __set_FPSCR(x)      ((void)(x))
+#endif
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP          __builtin_arm_nop
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI          __builtin_arm_wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE          __builtin_arm_wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV          __builtin_arm_sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB()        __builtin_arm_isb(0xF)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()        __builtin_arm_dsb(0xF)
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB()        __builtin_arm_dmb(0xF)
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV(value)   __builtin_bswap32(value)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV16(value) __ROR(__REV(value), 16)
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REVSH(value) (int16_t)__builtin_bswap16(value)
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)     __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __RBIT            __builtin_arm_rbit
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB        (uint8_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH        (uint16_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW        (uint32_t)__builtin_arm_ldrex
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXB        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXH        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define __STREXW        (uint32_t)__builtin_arm_strex
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX             __builtin_arm_clrex
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT             __builtin_arm_ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT             __builtin_arm_usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+  uint32_t result;
+
+  __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
+  return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+  __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+  __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+  __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define     __LDAEXB                 (uint8_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define     __LDAEXH                 (uint16_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define     __LDAEX                  (uint32_t)__builtin_arm_ldaex
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXB                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEXH                 (uint32_t)__builtin_arm_stlex
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#define     __STLEX                  (uint32_t)__builtin_arm_stlex
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+#define     __SADD8                 __builtin_arm_sadd8
+#define     __QADD8                 __builtin_arm_qadd8
+#define     __SHADD8                __builtin_arm_shadd8
+#define     __UADD8                 __builtin_arm_uadd8
+#define     __UQADD8                __builtin_arm_uqadd8
+#define     __UHADD8                __builtin_arm_uhadd8
+#define     __SSUB8                 __builtin_arm_ssub8
+#define     __QSUB8                 __builtin_arm_qsub8
+#define     __SHSUB8                __builtin_arm_shsub8
+#define     __USUB8                 __builtin_arm_usub8
+#define     __UQSUB8                __builtin_arm_uqsub8
+#define     __UHSUB8                __builtin_arm_uhsub8
+#define     __SADD16                __builtin_arm_sadd16
+#define     __QADD16                __builtin_arm_qadd16
+#define     __SHADD16               __builtin_arm_shadd16
+#define     __UADD16                __builtin_arm_uadd16
+#define     __UQADD16               __builtin_arm_uqadd16
+#define     __UHADD16               __builtin_arm_uhadd16
+#define     __SSUB16                __builtin_arm_ssub16
+#define     __QSUB16                __builtin_arm_qsub16
+#define     __SHSUB16               __builtin_arm_shsub16
+#define     __USUB16                __builtin_arm_usub16
+#define     __UQSUB16               __builtin_arm_uqsub16
+#define     __UHSUB16               __builtin_arm_uhsub16
+#define     __SASX                  __builtin_arm_sasx
+#define     __QASX                  __builtin_arm_qasx
+#define     __SHASX                 __builtin_arm_shasx
+#define     __UASX                  __builtin_arm_uasx
+#define     __UQASX                 __builtin_arm_uqasx
+#define     __UHASX                 __builtin_arm_uhasx
+#define     __SSAX                  __builtin_arm_ssax
+#define     __QSAX                  __builtin_arm_qsax
+#define     __SHSAX                 __builtin_arm_shsax
+#define     __USAX                  __builtin_arm_usax
+#define     __UQSAX                 __builtin_arm_uqsax
+#define     __UHSAX                 __builtin_arm_uhsax
+#define     __USAD8                 __builtin_arm_usad8
+#define     __USADA8                __builtin_arm_usada8
+#define     __SSAT16                __builtin_arm_ssat16
+#define     __USAT16                __builtin_arm_usat16
+#define     __UXTB16                __builtin_arm_uxtb16
+#define     __UXTAB16               __builtin_arm_uxtab16
+#define     __SXTB16                __builtin_arm_sxtb16
+#define     __SXTAB16               __builtin_arm_sxtab16
+#define     __SMUAD                 __builtin_arm_smuad
+#define     __SMUADX                __builtin_arm_smuadx
+#define     __SMLAD                 __builtin_arm_smlad
+#define     __SMLADX                __builtin_arm_smladx
+#define     __SMLALD                __builtin_arm_smlald
+#define     __SMLALDX               __builtin_arm_smlaldx
+#define     __SMUSD                 __builtin_arm_smusd
+#define     __SMUSDX                __builtin_arm_smusdx
+#define     __SMLSD                 __builtin_arm_smlsd
+#define     __SMLSDX                __builtin_arm_smlsdx
+#define     __SMLSLD                __builtin_arm_smlsld
+#define     __SMLSLDX               __builtin_arm_smlsldx
+#define     __SEL                   __builtin_arm_sel
+#define     __QADD                  __builtin_arm_qadd
+#define     __QSUB                  __builtin_arm_qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+  int32_t result;
+
+  __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCLANG_H */

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_compiler.h

@@ -0,0 +1,283 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+  #ifndef   __COMPILER_BARRIER
+    #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
+    #define __COMPILER_BARRIER()                   (void)0
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_gcc.h

@@ -0,0 +1,2177 @@
+/**************************************************************************//**
+ * @file     cmsis_gcc.h
+ * @brief    CMSIS compiler GCC header file
+ * @version  V5.3.0
+ * @date     26. March 2020
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_GCC_H
+#define __CMSIS_GCC_H
+
+/* ignore some GCC warnings */
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsign-conversion"
+#pragma GCC diagnostic ignored "-Wconversion"
+#pragma GCC diagnostic ignored "-Wunused-parameter"
+
+/* Fallback for __has_builtin */
+#ifndef __has_builtin
+  #define __has_builtin(x) (0)
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
+#endif                                           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __attribute__((__noreturn__))
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        struct __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         union __attribute__((packed, aligned(1)))
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #pragma GCC diagnostic push
+  #pragma GCC diagnostic ignored "-Wpacked"
+  #pragma GCC diagnostic ignored "-Wattributes"
+  __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+  #pragma GCC diagnostic pop
+  #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER()                   __ASM volatile("":::"memory")
+#endif
+
+/* #########################  Startup and Lowlevel Init  ######################## */
+
+#ifndef __PROGRAM_START
+
+/**
+  \brief   Initializes data and bss sections
+  \details This default implementations initialized all data and additional bss
+           sections relying on .copy.table and .zero.table specified properly
+           in the used linker script.
+  
+ */
+__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
+{
+  extern void _start(void) __NO_RETURN;
+  
+  typedef struct {
+    uint32_t const* src;
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __copy_table_t;
+  
+  typedef struct {
+    uint32_t* dest;
+    uint32_t  wlen;
+  } __zero_table_t;
+  
+  extern const __copy_table_t __copy_table_start__;
+  extern const __copy_table_t __copy_table_end__;
+  extern const __zero_table_t __zero_table_start__;
+  extern const __zero_table_t __zero_table_end__;
+
+  for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = pTable->src[i];
+    }
+  }
+ 
+  for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
+    for(uint32_t i=0u; i<pTable->wlen; ++i) {
+      pTable->dest[i] = 0u;
+    }
+  }
+ 
+  _start();
+}
+  
+#define __PROGRAM_START           __cmsis_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              __StackTop
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             __StackLimit
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __Vectors
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  __attribute__((used, section(".vectors")))
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i" : : : "memory");
+}
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i" : : : "memory");
+}
+
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Control Register (non-secure)
+  \details Returns the content of the non-secure Control Register when in secure mode.
+  \return               non-secure Control Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Control Register (non-secure)
+  \details Writes the given value to the non-secure Control Register when in secure state.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control)
+{
+  __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp"  : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
+  \return               PSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, psp_ns"  : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSP(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Main Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
+  \return               MSP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Main Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
+}
+#endif
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Stack Pointer (non-secure)
+  \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
+  \return               SP Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
+  return(result);
+}
+
+
+/**
+  \brief   Set Stack Pointer (non-secure)
+  \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
+  \param [in]    topOfStack  Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack)
+{
+  __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
+}
+#endif
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Priority Mask (non-secure)
+  \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
+  \return               Priority Mask value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Priority Mask (non-secure)
+  \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
+}
+#endif
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f" : : : "memory");
+}
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+__STATIC_FORCEINLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f" : : : "memory");
+}
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Base Priority (non-secure)
+  \details Returns the current value of the non-secure Base Priority register when in secure state.
+  \return               Base Priority register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Base Priority (non-secure)
+  \details Assigns the given value to the non-secure Base Priority register when in secure state.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
+}
+#endif
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Fault Mask (non-secure)
+  \details Returns the current value of the non-secure Fault Mask register when in secure state.
+  \return               Fault Mask register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
+  return(result);
+}
+#endif
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Set Fault Mask (non-secure)
+  \details Assigns the given value to the non-secure Fault Mask register when in secure state.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+/**
+  \brief   Get Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+  
+  \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim"  : "=r" (result) );
+  return result;
+#endif
+}
+
+#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
+/**
+  \brief   Get Process Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \return               PSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Process Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+  
+  \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Process Stack Pointer (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
+  \param [in]    ProcStackPtrLimit  Process Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure PSPLIM is RAZ/WI
+  (void)ProcStackPtrLimit;
+#else
+  __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
+#endif
+}
+#endif
+
+
+/**
+  \brief   Get Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always in non-secure
+  mode.
+
+  \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim" : "=r" (result) );
+  return result;
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Get Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence zero is returned always.
+
+  \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
+  \return               MSPLIM Register value
+ */
+__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  return 0U;
+#else
+  uint32_t result;
+  __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
+  return result;
+#endif
+}
+#endif
+
+
+/**
+  \brief   Set Main Stack Pointer Limit
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored in non-secure
+  mode.
+
+  \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
+  \param [in]    MainStackPtrLimit  Main Stack Pointer Limit value to set
+ */
+__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+    (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+
+
+#if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
+/**
+  \brief   Set Main Stack Pointer Limit (non-secure)
+  Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
+  Stack Pointer Limit register hence the write is silently ignored.
+
+  \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
+  \param [in]    MainStackPtrLimit  Main Stack Pointer value to set
+ */
+__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
+{
+#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)))
+  // without main extensions, the non-secure MSPLIM is RAZ/WI
+  (void)MainStackPtrLimit;
+#else
+  __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
+#endif
+}
+#endif
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_get_fpscr) 
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  return __builtin_arm_get_fpscr();
+#else
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#endif
+#else
+  return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+#if __has_builtin(__builtin_arm_set_fpscr)
+// Re-enable using built-in when GCC has been fixed
+// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
+  /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
+  __builtin_arm_set_fpscr(fpscr);
+#else
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
+#endif
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/* Define macros for porting to both thumb1 and thumb2.
+ * For thumb1, use low register (r0-r7), specified by constraint "l"
+ * Otherwise, use general registers, specified by constraint "r" */
+#if defined (__thumb__) && !defined (__thumb2__)
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
+#define __CMSIS_GCC_RW_REG(r) "+l" (r)
+#define __CMSIS_GCC_USE_REG(r) "l" (r)
+#else
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
+#define __CMSIS_GCC_RW_REG(r) "+r" (r)
+#define __CMSIS_GCC_USE_REG(r) "r" (r)
+#endif
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP()                             __ASM volatile ("nop")
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI()                             __ASM volatile ("wfi":::"memory")
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE()                             __ASM volatile ("wfe":::"memory")
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV()                             __ASM volatile ("sev")
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+__STATIC_FORCEINLINE void __ISB(void)
+{
+  __ASM volatile ("isb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+__STATIC_FORCEINLINE void __DSB(void)
+{
+  __ASM volatile ("dsb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+__STATIC_FORCEINLINE void __DMB(void)
+{
+  __ASM volatile ("dmb 0xF":::"memory");
+}
+
+
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
+  return __builtin_bswap32(value);
+#else
+  uint32_t result;
+
+  __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+}
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
+{
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+  return (int16_t)__builtin_bswap16(value);
+#else
+  int16_t result;
+
+  __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return result;
+#endif
+}
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
+{
+  op2 %= 32U;
+  if (op2 == 0U)
+  {
+    return op1;
+  }
+  return (op1 >> op2) | (op1 << (32U - op2));
+}
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+   __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
+#else
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+#endif
+  return result;
+}
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
+{
+  /* Even though __builtin_clz produces a CLZ instruction on ARM, formally
+     __builtin_clz(0) is undefined behaviour, so handle this case specially.
+     This guarantees ARM-compatible results if happening to compile on a non-ARM
+     target, and ensures the compiler doesn't decide to activate any
+     optimisations using the logic "value was passed to __builtin_clz, so it
+     is non-zero".
+     ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
+     single CLZ instruction.
+   */
+  if (value == 0U)
+  {
+    return 32U;
+  }
+  return __builtin_clz(value);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
+   return(result);
+}
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
+   return(result);
+}
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+__STATIC_FORCEINLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex" ::: "memory");
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+     (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+     (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    )
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT(ARG1, ARG2) \
+__extension__ \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  ARG1  Value to be saturated
+  \param [in]  ARG2  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT(ARG1, ARG2) \
+ __extension__ \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value)
+{
+  uint32_t result;
+
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
+  return(result);
+}
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint8_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
+#else
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
+       accepted by assembler. So has to use following less efficient pattern.
+    */
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
+#endif
+   return ((uint16_t) result);    /* Add explicit type cast here */
+}
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
+   return(result);
+}
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
+}
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
+}
+
+#else  /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__      ) && (__ARM_ARCH_7M__      == 1)) || \
+           (defined (__ARM_ARCH_7EM__     ) && (__ARM_ARCH_7EM__     == 1)) || \
+           (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))    ) */
+
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+/**
+  \brief   Load-Acquire (8 bit)
+  \details Executes a LDAB instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (16 bit)
+  \details Executes a LDAH instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire (32 bit)
+  \details Executes a LDA instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release (8 bit)
+  \details Executes a STLB instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
+{
+   __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (16 bit)
+  \details Executes a STLH instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
+{
+   __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Store-Release (32 bit)
+  \details Executes a STL instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
+{
+   __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (8 bit)
+  \details Executes a LDAB exclusive instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint8_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (16 bit)
+  \details Executes a LDAH exclusive instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return ((uint16_t) result);
+}
+
+
+/**
+  \brief   Load-Acquire Exclusive (32 bit)
+  \details Executes a LDA exclusive instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
+{
+    uint32_t result;
+
+   __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (8 bit)
+  \details Executes a STLB exclusive instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (16 bit)
+  \details Executes a STLH exclusive instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+
+/**
+  \brief   Store-Release Exclusive (32 bit)
+  \details Executes a STL exclusive instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+{
+   uint32_t result;
+
+   __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
+   return(result);
+}
+
+#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+           (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
+
+__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1, ARG2) \
+({                          \
+  int32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+#define __USAT16(ARG1, ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) : "cc" ); \
+  __RES; \
+ })
+
+__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
+{
+  uint32_t result;
+
+  __ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
+
+  return result;
+}
+
+__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
+{
+  union llreg_u{
+    uint32_t w32[2];
+    uint64_t w64;
+  } llr;
+  llr.w64 = acc;
+
+#ifndef __ARMEB__   /* Little endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
+#else               /* Big endian */
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
+#endif
+
+  return(llr.w64);
+}
+
+__STATIC_FORCEINLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QADD( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__STATIC_FORCEINLINE  int32_t __QSUB( int32_t op1,  int32_t op2)
+{
+  int32_t result;
+
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#if 0
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else \
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+#endif
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
+{
+ int32_t result;
+
+ __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );
+ return(result);
+}
+
+#endif /* (__ARM_FEATURE_DSP == 1) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#pragma GCC diagnostic pop
+
+#endif /* __CMSIS_GCC_H */

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_iccarm.h

@@ -0,0 +1,968 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.2.0
+ * @date     28. January 2020
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2019 IAR Systems
+// Copyright (c) 2017-2019 Arm Limited. All rights reserved. 
+//
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef   __COMPILER_BARRIER
+  #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+#ifndef __PROGRAM_START
+#define __PROGRAM_START           __iar_program_start
+#endif
+
+#ifndef __INITIAL_SP
+#define __INITIAL_SP              CSTACK$$Limit
+#endif
+
+#ifndef __STACK_LIMIT
+#define __STACK_LIMIT             CSTACK$$Base
+#endif
+
+#ifndef __VECTOR_TABLE
+#define __VECTOR_TABLE            __vector_table
+#endif
+
+#ifndef __VECTOR_TABLE_ATTRIBUTE
+#define __VECTOR_TABLE_ATTRIBUTE  @".intvec"
+#endif
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM volatile("RRX      %0, %1" : "=r"(result) : "r" (value));
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
+
+#endif /* __CMSIS_ICCARM_H__ */

bsp/acm32f4xx-nucleo/libraries/CMSIS/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.3
+ * @date     24. June 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2019 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 3U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

bsp/acm32f4xx-nucleo/libraries/CMSIS/core_cm33.h

@@ -0,0 +1,2910 @@
+/**************************************************************************//**
+ * @file     core_cm33.h
+ * @brief    CMSIS Cortex-M33 Core Peripheral Access Layer Header File
+ * @version  V5.1.0
+ * @date     12. November 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM33_H_GENERIC
+#define __CORE_CM33_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M33
+  @{
+ */
+
+#include "cmsis_version.h"
+
+/*  CMSIS CM33 definitions */
+#define __CM33_CMSIS_VERSION_MAIN  (__CM_CMSIS_VERSION_MAIN)                   /*!< \deprecated [31:16] CMSIS HAL main version */
+#define __CM33_CMSIS_VERSION_SUB   (__CM_CMSIS_VERSION_SUB)                    /*!< \deprecated [15:0]  CMSIS HAL sub version */
+#define __CM33_CMSIS_VERSION       ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
+                                     __CM33_CMSIS_VERSION_SUB           )      /*!< \deprecated CMSIS HAL version number */
+
+#define __CORTEX_M                 (33U)                                       /*!< Cortex-M Core */
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined (__TARGET_FPU_VFP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined (__ARM_FP)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined (__ARMVFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
+    #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
+      #define __DSP_USED       1U
+    #else
+      #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
+      #define __DSP_USED         0U
+    #endif
+  #else
+    #define __DSP_USED         0U
+  #endif
+
+#elif defined ( __TI_ARM__ )
+  #if defined (__TI_VFP_SUPPORT__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined (__FPU_VFP__)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "cmsis_compiler.h"               /* CMSIS compiler specific defines */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM33_H_DEPENDANT
+#define __CORE_CM33_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM33_REV
+    #define __CM33_REV                0x0000U
+    #warning "__CM33_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __SAUREGION_PRESENT
+    #define __SAUREGION_PRESENT       0U
+    #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __DSP_PRESENT
+    #define __DSP_PRESENT             0U
+    #warning "__DSP_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          3U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    1U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M33 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core SAU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack-pointer select */
+    uint32_t FPCA:1;                     /*!< bit:      2  Floating-point context active */
+    uint32_t SFPA:1;                     /*!< bit:      3  Secure floating-point active */
+    uint32_t _reserved1:28;              /*!< bit:  4..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_SFPA_Pos                    3U                                            /*!< CONTROL: SFPA Position */
+#define CONTROL_SFPA_Msk                   (1UL << CONTROL_SFPA_Pos)                      /*!< CONTROL: SFPA Mask */
+
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[16U];              /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[16U];
+  __IOM uint32_t ICER[16U];              /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[16U];
+  __IOM uint32_t ISPR[16U];              /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[16U];
+  __IOM uint32_t ICPR[16U];              /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[16U];
+  __IOM uint32_t IABR[16U];              /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[16U];
+  __IOM uint32_t ITNS[16U];              /*!< Offset: 0x280 (R/W)  Interrupt Non-Secure State Register */
+        uint32_t RESERVED5[16U];
+  __IOM uint8_t  IPR[496U];              /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED6[580U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHPR[12U];              /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t ID_PFR[2U];             /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t ID_DFR;                 /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ID_ADR;                 /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t ID_MMFR[4U];            /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ID_ISAR[6U];            /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+  __IM  uint32_t CLIDR;                  /*!< Offset: 0x078 (R/ )  Cache Level ID register */
+  __IM  uint32_t CTR;                    /*!< Offset: 0x07C (R/ )  Cache Type register */
+  __IM  uint32_t CCSIDR;                 /*!< Offset: 0x080 (R/ )  Cache Size ID Register */
+  __IOM uint32_t CSSELR;                 /*!< Offset: 0x084 (R/W)  Cache Size Selection Register */
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+  __IOM uint32_t NSACR;                  /*!< Offset: 0x08C (R/W)  Non-Secure Access Control Register */
+        uint32_t RESERVED3[92U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0x200 ( /W)  Software Triggered Interrupt Register */
+        uint32_t RESERVED4[15U];
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x240 (R/ )  Media and VFP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x244 (R/ )  Media and VFP Feature Register 1 */
+  __IM  uint32_t MVFR2;                  /*!< Offset: 0x248 (R/ )  Media and VFP Feature Register 2 */
+        uint32_t RESERVED5[1U];
+  __OM  uint32_t ICIALLU;                /*!< Offset: 0x250 ( /W)  I-Cache Invalidate All to PoU */
+        uint32_t RESERVED6[1U];
+  __OM  uint32_t ICIMVAU;                /*!< Offset: 0x258 ( /W)  I-Cache Invalidate by MVA to PoU */
+  __OM  uint32_t DCIMVAC;                /*!< Offset: 0x25C ( /W)  D-Cache Invalidate by MVA to PoC */
+  __OM  uint32_t DCISW;                  /*!< Offset: 0x260 ( /W)  D-Cache Invalidate by Set-way */
+  __OM  uint32_t DCCMVAU;                /*!< Offset: 0x264 ( /W)  D-Cache Clean by MVA to PoU */
+  __OM  uint32_t DCCMVAC;                /*!< Offset: 0x268 ( /W)  D-Cache Clean by MVA to PoC */
+  __OM  uint32_t DCCSW;                  /*!< Offset: 0x26C ( /W)  D-Cache Clean by Set-way */
+  __OM  uint32_t DCCIMVAC;               /*!< Offset: 0x270 ( /W)  D-Cache Clean and Invalidate by MVA to PoC */
+  __OM  uint32_t DCCISW;                 /*!< Offset: 0x274 ( /W)  D-Cache Clean and Invalidate by Set-way */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_PENDNMISET_Pos            31U                                            /*!< SCB ICSR: PENDNMISET Position */
+#define SCB_ICSR_PENDNMISET_Msk            (1UL << SCB_ICSR_PENDNMISET_Pos)               /*!< SCB ICSR: PENDNMISET Mask */
+
+#define SCB_ICSR_NMIPENDSET_Pos            SCB_ICSR_PENDNMISET_Pos                        /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
+#define SCB_ICSR_NMIPENDSET_Msk            SCB_ICSR_PENDNMISET_Msk                        /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
+
+#define SCB_ICSR_PENDNMICLR_Pos            30U                                            /*!< SCB ICSR: PENDNMICLR Position */
+#define SCB_ICSR_PENDNMICLR_Msk            (1UL << SCB_ICSR_PENDNMICLR_Pos)               /*!< SCB ICSR: PENDNMICLR Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_STTNS_Pos                 24U                                            /*!< SCB ICSR: STTNS Position (Security Extension) */
+#define SCB_ICSR_STTNS_Msk                 (1UL << SCB_ICSR_STTNS_Pos)                    /*!< SCB ICSR: STTNS Mask (Security Extension) */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIS_Pos                 14U                                            /*!< SCB AIRCR: PRIS Position */
+#define SCB_AIRCR_PRIS_Msk                 (1UL << SCB_AIRCR_PRIS_Pos)                    /*!< SCB AIRCR: PRIS Mask */
+
+#define SCB_AIRCR_BFHFNMINS_Pos            13U                                            /*!< SCB AIRCR: BFHFNMINS Position */
+#define SCB_AIRCR_BFHFNMINS_Msk            (1UL << SCB_AIRCR_BFHFNMINS_Pos)               /*!< SCB AIRCR: BFHFNMINS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQS_Pos          3U                                            /*!< SCB AIRCR: SYSRESETREQS Position */
+#define SCB_AIRCR_SYSRESETREQS_Msk         (1UL << SCB_AIRCR_SYSRESETREQS_Pos)            /*!< SCB AIRCR: SYSRESETREQS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEPS_Pos              3U                                            /*!< SCB SCR: SLEEPDEEPS Position */
+#define SCB_SCR_SLEEPDEEPS_Msk             (1UL << SCB_SCR_SLEEPDEEPS_Pos)                /*!< SCB SCR: SLEEPDEEPS Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_BP_Pos                     18U                                            /*!< SCB CCR: BP Position */
+#define SCB_CCR_BP_Msk                     (1UL << SCB_CCR_BP_Pos)                        /*!< SCB CCR: BP Mask */
+
+#define SCB_CCR_IC_Pos                     17U                                            /*!< SCB CCR: IC Position */
+#define SCB_CCR_IC_Msk                     (1UL << SCB_CCR_IC_Pos)                        /*!< SCB CCR: IC Mask */
+
+#define SCB_CCR_DC_Pos                     16U                                            /*!< SCB CCR: DC Position */
+#define SCB_CCR_DC_Msk                     (1UL << SCB_CCR_DC_Pos)                        /*!< SCB CCR: DC Mask */
+
+#define SCB_CCR_STKOFHFNMIGN_Pos           10U                                            /*!< SCB CCR: STKOFHFNMIGN Position */
+#define SCB_CCR_STKOFHFNMIGN_Msk           (1UL << SCB_CCR_STKOFHFNMIGN_Pos)              /*!< SCB CCR: STKOFHFNMIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_HARDFAULTPENDED_Pos      21U                                            /*!< SCB SHCSR: HARDFAULTPENDED Position */
+#define SCB_SHCSR_HARDFAULTPENDED_Msk      (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)         /*!< SCB SHCSR: HARDFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTPENDED_Pos    20U                                            /*!< SCB SHCSR: SECUREFAULTPENDED Position */
+#define SCB_SHCSR_SECUREFAULTPENDED_Msk    (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)       /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
+
+#define SCB_SHCSR_SECUREFAULTENA_Pos       19U                                            /*!< SCB SHCSR: SECUREFAULTENA Position */
+#define SCB_SHCSR_SECUREFAULTENA_Msk       (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)          /*!< SCB SHCSR: SECUREFAULTENA Mask */
+
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_NMIACT_Pos                5U                                            /*!< SCB SHCSR: NMIACT Position */
+#define SCB_SHCSR_NMIACT_Msk               (1UL << SCB_SHCSR_NMIACT_Pos)                  /*!< SCB SHCSR: NMIACT Mask */
+
+#define SCB_SHCSR_SECUREFAULTACT_Pos        4U                                            /*!< SCB SHCSR: SECUREFAULTACT Position */
+#define SCB_SHCSR_SECUREFAULTACT_Msk       (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)          /*!< SCB SHCSR: SECUREFAULTACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_HARDFAULTACT_Pos          2U                                            /*!< SCB SHCSR: HARDFAULTACT Position */
+#define SCB_SHCSR_HARDFAULTACT_Msk         (1UL << SCB_SHCSR_HARDFAULTACT_Pos)            /*!< SCB SHCSR: HARDFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)               /*!< SCB CFSR (MMFSR): MMARVALID Position */
+#define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)                /*!< SCB CFSR (MMFSR): MMARVALID Mask */
+
+#define SCB_CFSR_MLSPERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 5U)               /*!< SCB CFSR (MMFSR): MLSPERR Position */
+#define SCB_CFSR_MLSPERR_Msk               (1UL << SCB_CFSR_MLSPERR_Pos)                  /*!< SCB CFSR (MMFSR): MLSPERR Mask */
+
+#define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)               /*!< SCB CFSR (MMFSR): MSTKERR Position */
+#define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)                  /*!< SCB CFSR (MMFSR): MSTKERR Mask */
+
+#define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)               /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
+#define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)                /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
+
+#define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)               /*!< SCB CFSR (MMFSR): DACCVIOL Position */
+#define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)                 /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
+
+#define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)               /*!< SCB CFSR (MMFSR): IACCVIOL Position */
+#define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)             /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
+
+/* BusFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)                  /*!< SCB CFSR (BFSR): BFARVALID Position */
+#define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)                 /*!< SCB CFSR (BFSR): BFARVALID Mask */
+
+#define SCB_CFSR_LSPERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 5U)                  /*!< SCB CFSR (BFSR): LSPERR Position */
+#define SCB_CFSR_LSPERR_Msk               (1UL << SCB_CFSR_LSPERR_Pos)                    /*!< SCB CFSR (BFSR): LSPERR Mask */
+
+#define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)                  /*!< SCB CFSR (BFSR): STKERR Position */
+#define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)                    /*!< SCB CFSR (BFSR): STKERR Mask */
+
+#define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)                  /*!< SCB CFSR (BFSR): UNSTKERR Position */
+#define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)                  /*!< SCB CFSR (BFSR): UNSTKERR Mask */
+
+#define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)                  /*!< SCB CFSR (BFSR): IMPRECISERR Position */
+#define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)               /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
+
+#define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)                  /*!< SCB CFSR (BFSR): PRECISERR Position */
+#define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)                 /*!< SCB CFSR (BFSR): PRECISERR Mask */
+
+#define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)                  /*!< SCB CFSR (BFSR): IBUSERR Position */
+#define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)                   /*!< SCB CFSR (BFSR): IBUSERR Mask */
+
+/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
+#define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)                  /*!< SCB CFSR (UFSR): DIVBYZERO Position */
+#define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)                 /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
+
+#define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)                  /*!< SCB CFSR (UFSR): UNALIGNED Position */
+#define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)                 /*!< SCB CFSR (UFSR): UNALIGNED Mask */
+
+#define SCB_CFSR_STKOF_Pos                (SCB_CFSR_USGFAULTSR_Pos + 4U)                  /*!< SCB CFSR (UFSR): STKOF Position */
+#define SCB_CFSR_STKOF_Msk                (1UL << SCB_CFSR_STKOF_Pos)                     /*!< SCB CFSR (UFSR): STKOF Mask */
+
+#define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)                  /*!< SCB CFSR (UFSR): NOCP Position */
+#define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)                      /*!< SCB CFSR (UFSR): NOCP Mask */
+
+#define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)                  /*!< SCB CFSR (UFSR): INVPC Position */
+#define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)                     /*!< SCB CFSR (UFSR): INVPC Mask */
+
+#define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)                  /*!< SCB CFSR (UFSR): INVSTATE Position */
+#define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)                  /*!< SCB CFSR (UFSR): INVSTATE Mask */
+
+#define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)                  /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
+#define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)                /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/* SCB Non-Secure Access Control Register Definitions */
+#define SCB_NSACR_CP11_Pos                 11U                                            /*!< SCB NSACR: CP11 Position */
+#define SCB_NSACR_CP11_Msk                 (1UL << SCB_NSACR_CP11_Pos)                    /*!< SCB NSACR: CP11 Mask */
+
+#define SCB_NSACR_CP10_Pos                 10U                                            /*!< SCB NSACR: CP10 Position */
+#define SCB_NSACR_CP10_Msk                 (1UL << SCB_NSACR_CP10_Pos)                    /*!< SCB NSACR: CP10 Mask */
+
+#define SCB_NSACR_CPn_Pos                   0U                                            /*!< SCB NSACR: CPn Position */
+#define SCB_NSACR_CPn_Msk                  (1UL /*<< SCB_NSACR_CPn_Pos*/)                 /*!< SCB NSACR: CPn Mask */
+
+/* SCB Cache Level ID Register Definitions */
+#define SCB_CLIDR_LOUU_Pos                 27U                                            /*!< SCB CLIDR: LoUU Position */
+#define SCB_CLIDR_LOUU_Msk                 (7UL << SCB_CLIDR_LOUU_Pos)                    /*!< SCB CLIDR: LoUU Mask */
+
+#define SCB_CLIDR_LOC_Pos                  24U                                            /*!< SCB CLIDR: LoC Position */
+#define SCB_CLIDR_LOC_Msk                  (7UL << SCB_CLIDR_LOC_Pos)                     /*!< SCB CLIDR: LoC Mask */
+
+/* SCB Cache Type Register Definitions */
+#define SCB_CTR_FORMAT_Pos                 29U                                            /*!< SCB CTR: Format Position */
+#define SCB_CTR_FORMAT_Msk                 (7UL << SCB_CTR_FORMAT_Pos)                    /*!< SCB CTR: Format Mask */
+
+#define SCB_CTR_CWG_Pos                    24U                                            /*!< SCB CTR: CWG Position */
+#define SCB_CTR_CWG_Msk                    (0xFUL << SCB_CTR_CWG_Pos)                     /*!< SCB CTR: CWG Mask */
+
+#define SCB_CTR_ERG_Pos                    20U                                            /*!< SCB CTR: ERG Position */
+#define SCB_CTR_ERG_Msk                    (0xFUL << SCB_CTR_ERG_Pos)                     /*!< SCB CTR: ERG Mask */
+
+#define SCB_CTR_DMINLINE_Pos               16U                                            /*!< SCB CTR: DminLine Position */
+#define SCB_CTR_DMINLINE_Msk               (0xFUL << SCB_CTR_DMINLINE_Pos)                /*!< SCB CTR: DminLine Mask */
+
+#define SCB_CTR_IMINLINE_Pos                0U                                            /*!< SCB CTR: ImInLine Position */
+#define SCB_CTR_IMINLINE_Msk               (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)            /*!< SCB CTR: ImInLine Mask */
+
+/* SCB Cache Size ID Register Definitions */
+#define SCB_CCSIDR_WT_Pos                  31U                                            /*!< SCB CCSIDR: WT Position */
+#define SCB_CCSIDR_WT_Msk                  (1UL << SCB_CCSIDR_WT_Pos)                     /*!< SCB CCSIDR: WT Mask */
+
+#define SCB_CCSIDR_WB_Pos                  30U                                            /*!< SCB CCSIDR: WB Position */
+#define SCB_CCSIDR_WB_Msk                  (1UL << SCB_CCSIDR_WB_Pos)                     /*!< SCB CCSIDR: WB Mask */
+
+#define SCB_CCSIDR_RA_Pos                  29U                                            /*!< SCB CCSIDR: RA Position */
+#define SCB_CCSIDR_RA_Msk                  (1UL << SCB_CCSIDR_RA_Pos)                     /*!< SCB CCSIDR: RA Mask */
+
+#define SCB_CCSIDR_WA_Pos                  28U                                            /*!< SCB CCSIDR: WA Position */
+#define SCB_CCSIDR_WA_Msk                  (1UL << SCB_CCSIDR_WA_Pos)                     /*!< SCB CCSIDR: WA Mask */
+
+#define SCB_CCSIDR_NUMSETS_Pos             13U                                            /*!< SCB CCSIDR: NumSets Position */
+#define SCB_CCSIDR_NUMSETS_Msk             (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)           /*!< SCB CCSIDR: NumSets Mask */
+
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos        3U                                            /*!< SCB CCSIDR: Associativity Position */
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk       (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)      /*!< SCB CCSIDR: Associativity Mask */
+
+#define SCB_CCSIDR_LINESIZE_Pos             0U                                            /*!< SCB CCSIDR: LineSize Position */
+#define SCB_CCSIDR_LINESIZE_Msk            (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)           /*!< SCB CCSIDR: LineSize Mask */
+
+/* SCB Cache Size Selection Register Definitions */
+#define SCB_CSSELR_LEVEL_Pos                1U                                            /*!< SCB CSSELR: Level Position */
+#define SCB_CSSELR_LEVEL_Msk               (7UL << SCB_CSSELR_LEVEL_Pos)                  /*!< SCB CSSELR: Level Mask */
+
+#define SCB_CSSELR_IND_Pos                  0U                                            /*!< SCB CSSELR: InD Position */
+#define SCB_CSSELR_IND_Msk                 (1UL /*<< SCB_CSSELR_IND_Pos*/)                /*!< SCB CSSELR: InD Mask */
+
+/* SCB Software Triggered Interrupt Register Definitions */
+#define SCB_STIR_INTID_Pos                  0U                                            /*!< SCB STIR: INTID Position */
+#define SCB_STIR_INTID_Msk                 (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)            /*!< SCB STIR: INTID Mask */
+
+/* SCB D-Cache Invalidate by Set-way Register Definitions */
+#define SCB_DCISW_WAY_Pos                  30U                                            /*!< SCB DCISW: Way Position */
+#define SCB_DCISW_WAY_Msk                  (3UL << SCB_DCISW_WAY_Pos)                     /*!< SCB DCISW: Way Mask */
+
+#define SCB_DCISW_SET_Pos                   5U                                            /*!< SCB DCISW: Set Position */
+#define SCB_DCISW_SET_Msk                  (0x1FFUL << SCB_DCISW_SET_Pos)                 /*!< SCB DCISW: Set Mask */
+
+/* SCB D-Cache Clean by Set-way Register Definitions */
+#define SCB_DCCSW_WAY_Pos                  30U                                            /*!< SCB DCCSW: Way Position */
+#define SCB_DCCSW_WAY_Msk                  (3UL << SCB_DCCSW_WAY_Pos)                     /*!< SCB DCCSW: Way Mask */
+
+#define SCB_DCCSW_SET_Pos                   5U                                            /*!< SCB DCCSW: Set Position */
+#define SCB_DCCSW_SET_Msk                  (0x1FFUL << SCB_DCCSW_SET_Pos)                 /*!< SCB DCCSW: Set Mask */
+
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
+#define SCB_DCCISW_WAY_Pos                 30U                                            /*!< SCB DCCISW: Way Position */
+#define SCB_DCCISW_WAY_Msk                 (3UL << SCB_DCCISW_WAY_Pos)                    /*!< SCB DCCISW: Way Mask */
+
+#define SCB_DCCISW_SET_Pos                  5U                                            /*!< SCB DCCISW: Set Position */
+#define SCB_DCCISW_SET_Msk                 (0x1FFUL << SCB_DCCISW_SET_Pos)                /*!< SCB DCCISW: Set Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+  __IOM uint32_t CPPWR;                  /*!< Offset: 0x00C (R/W)  Coprocessor Power Control  Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[32U];
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  ITM Device Architecture Register */
+        uint32_t RESERVED6[4U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Stimulus Port Register Definitions */
+#define ITM_STIM_DISABLED_Pos               1U                                            /*!< ITM STIM: DISABLED Position */
+#define ITM_STIM_DISABLED_Msk              (0x1UL << ITM_STIM_DISABLED_Pos)               /*!< ITM STIM: DISABLED Mask */
+
+#define ITM_STIM_FIFOREADY_Pos              0U                                            /*!< ITM STIM: FIFOREADY Position */
+#define ITM_STIM_FIFOREADY_Msk             (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)          /*!< ITM STIM: FIFOREADY Mask */
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)     /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TRACEBUSID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TRACEBUSID_Msk             (0x7FUL << ITM_TCR_TRACEBUSID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPRESCALE_Pos              8U                                            /*!< ITM TCR: TSPRESCALE Position */
+#define ITM_TCR_TSPRESCALE_Msk             (3UL << ITM_TCR_TSPRESCALE_Pos)                /*!< ITM TCR: TSPRESCALE Mask */
+
+#define ITM_TCR_STALLENA_Pos                5U                                            /*!< ITM TCR: STALLENA Position */
+#define ITM_TCR_STALLENA_Msk               (1UL << ITM_TCR_STALLENA_Pos)                  /*!< ITM TCR: STALLENA Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+        uint32_t RESERVED3[1U];
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+        uint32_t RESERVED5[1U];
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED6[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+        uint32_t RESERVED7[1U];
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+        uint32_t RESERVED8[1U];
+  __IOM uint32_t COMP4;                  /*!< Offset: 0x060 (R/W)  Comparator Register 4 */
+        uint32_t RESERVED9[1U];
+  __IOM uint32_t FUNCTION4;              /*!< Offset: 0x068 (R/W)  Function Register 4 */
+        uint32_t RESERVED10[1U];
+  __IOM uint32_t COMP5;                  /*!< Offset: 0x070 (R/W)  Comparator Register 5 */
+        uint32_t RESERVED11[1U];
+  __IOM uint32_t FUNCTION5;              /*!< Offset: 0x078 (R/W)  Function Register 5 */
+        uint32_t RESERVED12[1U];
+  __IOM uint32_t COMP6;                  /*!< Offset: 0x080 (R/W)  Comparator Register 6 */
+        uint32_t RESERVED13[1U];
+  __IOM uint32_t FUNCTION6;              /*!< Offset: 0x088 (R/W)  Function Register 6 */
+        uint32_t RESERVED14[1U];
+  __IOM uint32_t COMP7;                  /*!< Offset: 0x090 (R/W)  Comparator Register 7 */
+        uint32_t RESERVED15[1U];
+  __IOM uint32_t FUNCTION7;              /*!< Offset: 0x098 (R/W)  Function Register 7 */
+        uint32_t RESERVED16[1U];
+  __IOM uint32_t COMP8;                  /*!< Offset: 0x0A0 (R/W)  Comparator Register 8 */
+        uint32_t RESERVED17[1U];
+  __IOM uint32_t FUNCTION8;              /*!< Offset: 0x0A8 (R/W)  Function Register 8 */
+        uint32_t RESERVED18[1U];
+  __IOM uint32_t COMP9;                  /*!< Offset: 0x0B0 (R/W)  Comparator Register 9 */
+        uint32_t RESERVED19[1U];
+  __IOM uint32_t FUNCTION9;              /*!< Offset: 0x0B8 (R/W)  Function Register 9 */
+        uint32_t RESERVED20[1U];
+  __IOM uint32_t COMP10;                 /*!< Offset: 0x0C0 (R/W)  Comparator Register 10 */
+        uint32_t RESERVED21[1U];
+  __IOM uint32_t FUNCTION10;             /*!< Offset: 0x0C8 (R/W)  Function Register 10 */
+        uint32_t RESERVED22[1U];
+  __IOM uint32_t COMP11;                 /*!< Offset: 0x0D0 (R/W)  Comparator Register 11 */
+        uint32_t RESERVED23[1U];
+  __IOM uint32_t FUNCTION11;             /*!< Offset: 0x0D8 (R/W)  Function Register 11 */
+        uint32_t RESERVED24[1U];
+  __IOM uint32_t COMP12;                 /*!< Offset: 0x0E0 (R/W)  Comparator Register 12 */
+        uint32_t RESERVED25[1U];
+  __IOM uint32_t FUNCTION12;             /*!< Offset: 0x0E8 (R/W)  Function Register 12 */
+        uint32_t RESERVED26[1U];
+  __IOM uint32_t COMP13;                 /*!< Offset: 0x0F0 (R/W)  Comparator Register 13 */
+        uint32_t RESERVED27[1U];
+  __IOM uint32_t FUNCTION13;             /*!< Offset: 0x0F8 (R/W)  Function Register 13 */
+        uint32_t RESERVED28[1U];
+  __IOM uint32_t COMP14;                 /*!< Offset: 0x100 (R/W)  Comparator Register 14 */
+        uint32_t RESERVED29[1U];
+  __IOM uint32_t FUNCTION14;             /*!< Offset: 0x108 (R/W)  Function Register 14 */
+        uint32_t RESERVED30[1U];
+  __IOM uint32_t COMP15;                 /*!< Offset: 0x110 (R/W)  Comparator Register 15 */
+        uint32_t RESERVED31[1U];
+  __IOM uint32_t FUNCTION15;             /*!< Offset: 0x118 (R/W)  Function Register 15 */
+        uint32_t RESERVED32[934U];
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R  )  Lock Status Register */
+        uint32_t RESERVED33[1U];
+  __IM  uint32_t DEVARCH;                /*!< Offset: 0xFBC (R/ )  Device Architecture Register */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCDISS_Pos               23U                                         /*!< DWT CTRL: CYCDISS Position */
+#define DWT_CTRL_CYCDISS_Msk               (0x1UL << DWT_CTRL_CYCDISS_Pos)             /*!< DWT CTRL: CYCDISS Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_ID_Pos                27U                                         /*!< DWT FUNCTION: ID Position */
+#define DWT_FUNCTION_ID_Msk                (0x1FUL << DWT_FUNCTION_ID_Pos)             /*!< DWT FUNCTION: ID Mask */
+
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_ACTION_Pos             4U                                         /*!< DWT FUNCTION: ACTION Position */
+#define DWT_FUNCTION_ACTION_Msk            (0x1UL << DWT_FUNCTION_ACTION_Pos)          /*!< DWT FUNCTION: ACTION Mask */
+
+#define DWT_FUNCTION_MATCH_Pos              0U                                         /*!< DWT FUNCTION: MATCH Position */
+#define DWT_FUNCTION_MATCH_Msk             (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)       /*!< DWT FUNCTION: MATCH Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IM  uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IOM uint32_t PSCR;                   /*!< Offset: 0x308 (R/W)  Periodic Synchronization Control Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER Register */
+  __IM  uint32_t ITFTTD0;                /*!< Offset: 0xEEC (R/ )  Integration Test FIFO Test Data 0 Register */
+  __IOM uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/W)  Integration Test ATB Control Register 2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  Integration Test ATB Control Register 0 */
+  __IM  uint32_t ITFTTD1;                /*!< Offset: 0xEFC (R/ )  Integration Test FIFO Test Data 1 Register */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  Device Configuration Register */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  Device Type Identifier Register */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_FOnMan_Pos                 6U                                         /*!< TPI FFCR: FOnMan Position */
+#define TPI_FFCR_FOnMan_Msk                (0x1UL << TPI_FFCR_FOnMan_Pos)              /*!< TPI FFCR: FOnMan Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration Test FIFO Test Data 0 Register Definitions */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
+#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data2_Pos      16U                                         /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
+#define TPI_ITFTTD0_ATB_IF1_data2_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data1_Pos       8U                                         /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
+#define TPI_ITFTTD0_ATB_IF1_data1_Msk      (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)   /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
+
+#define TPI_ITFTTD0_ATB_IF1_data0_Pos       0U                                          /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
+#define TPI_ITFTTD0_ATB_IF1_data0_Msk      (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 2 Register Definitions */
+#define TPI_ITATBCTR2_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID2S Position */
+#define TPI_ITATBCTR2_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)      /*!< TPI ITATBCTR2: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR2_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR2: AFVALID1S Position */
+#define TPI_ITATBCTR2_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)      /*!< TPI ITATBCTR2: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR2_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY2S Position */
+#define TPI_ITATBCTR2_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY2S Mask */
+
+#define TPI_ITATBCTR2_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR2: ATREADY1S Position */
+#define TPI_ITATBCTR2_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR2: ATREADY1S Mask */
+
+/* TPI Integration Test FIFO Test Data 1 Register Definitions */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos    29U                                         /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos  27U                                         /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
+#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos    26U                                         /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
+#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk    (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)  /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
+
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos  24U                                         /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
+#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk  (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data2_Pos      16U                                         /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
+#define TPI_ITFTTD1_ATB_IF2_data2_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data1_Pos       8U                                         /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
+#define TPI_ITFTTD1_ATB_IF2_data1_Msk      (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)   /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
+
+#define TPI_ITFTTD1_ATB_IF2_data0_Pos       0U                                          /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
+#define TPI_ITFTTD1_ATB_IF2_data0_Msk      (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
+
+/* TPI Integration Test ATB Control Register 0 Definitions */
+#define TPI_ITATBCTR0_AFVALID2S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID2S Position */
+#define TPI_ITATBCTR0_AFVALID2S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)      /*!< TPI ITATBCTR0: AFVALID2SS Mask */
+
+#define TPI_ITATBCTR0_AFVALID1S_Pos         1U                                         /*!< TPI ITATBCTR0: AFVALID1S Position */
+#define TPI_ITATBCTR0_AFVALID1S_Msk        (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)      /*!< TPI ITATBCTR0: AFVALID1SS Mask */
+
+#define TPI_ITATBCTR0_ATREADY2S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY2S Position */
+#define TPI_ITATBCTR0_ATREADY2S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY2S Mask */
+
+#define TPI_ITATBCTR0_ATREADY1S_Pos         0U                                         /*!< TPI ITATBCTR0: ATREADY1S Position */
+#define TPI_ITATBCTR0_ATREADY1S_Msk        (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)  /*!< TPI ITATBCTR0: ATREADY1S Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_FIFOSZ_Pos                6U                                         /*!< TPI DEVID: FIFOSZ Position */
+#define TPI_DEVID_FIFOSZ_Msk               (0x7UL << TPI_DEVID_FIFOSZ_Pos)             /*!< TPI DEVID: FIFOSZ Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_SubType_Pos             4U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+#define TPI_DEVTYPE_MajorType_Pos           0U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  MPU Region Limit Address Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Region Base Address Register Alias 1 */
+  __IOM uint32_t RLAR_A1;                /*!< Offset: 0x018 (R/W)  MPU Region Limit Address Register Alias 1 */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Region Base Address Register Alias 2 */
+  __IOM uint32_t RLAR_A2;                /*!< Offset: 0x020 (R/W)  MPU Region Limit Address Register Alias 2 */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Region Base Address Register Alias 3 */
+  __IOM uint32_t RLAR_A3;                /*!< Offset: 0x028 (R/W)  MPU Region Limit Address Register Alias 3 */
+        uint32_t RESERVED0[1];
+  union {
+  __IOM uint32_t MAIR[2];
+  struct {
+  __IOM uint32_t MAIR0;                  /*!< Offset: 0x030 (R/W)  MPU Memory Attribute Indirection Register 0 */
+  __IOM uint32_t MAIR1;                  /*!< Offset: 0x034 (R/W)  MPU Memory Attribute Indirection Register 1 */
+  };
+  };
+} MPU_Type;
+
+#define MPU_TYPE_RALIASES                  4U
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos                   5U                                            /*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk                  (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)             /*!< MPU RBAR: BASE Mask */
+
+#define MPU_RBAR_SH_Pos                     3U                                            /*!< MPU RBAR: SH Position */
+#define MPU_RBAR_SH_Msk                    (0x3UL << MPU_RBAR_SH_Pos)                     /*!< MPU RBAR: SH Mask */
+
+#define MPU_RBAR_AP_Pos                     1U                                            /*!< MPU RBAR: AP Position */
+#define MPU_RBAR_AP_Msk                    (0x3UL << MPU_RBAR_AP_Pos)                     /*!< MPU RBAR: AP Mask */
+
+#define MPU_RBAR_XN_Pos                     0U                                            /*!< MPU RBAR: XN Position */
+#define MPU_RBAR_XN_Msk                    (01UL /*<< MPU_RBAR_XN_Pos*/)                  /*!< MPU RBAR: XN Mask */
+
+/* MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos                  5U                                            /*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk                 (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)            /*!< MPU RLAR: LIMIT Mask */
+
+#define MPU_RLAR_AttrIndx_Pos               1U                                            /*!< MPU RLAR: AttrIndx Position */
+#define MPU_RLAR_AttrIndx_Msk              (0x7UL << MPU_RLAR_AttrIndx_Pos)               /*!< MPU RLAR: AttrIndx Mask */
+
+#define MPU_RLAR_EN_Pos                     0U                                            /*!< MPU RLAR: Region enable bit Position */
+#define MPU_RLAR_EN_Msk                    (1UL /*<< MPU_RLAR_EN_Pos*/)                   /*!< MPU RLAR: Region enable bit Disable Mask */
+
+/* MPU Memory Attribute Indirection Register 0 Definitions */
+#define MPU_MAIR0_Attr3_Pos                24U                                            /*!< MPU MAIR0: Attr3 Position */
+#define MPU_MAIR0_Attr3_Msk                (0xFFUL << MPU_MAIR0_Attr3_Pos)                /*!< MPU MAIR0: Attr3 Mask */
+
+#define MPU_MAIR0_Attr2_Pos                16U                                            /*!< MPU MAIR0: Attr2 Position */
+#define MPU_MAIR0_Attr2_Msk                (0xFFUL << MPU_MAIR0_Attr2_Pos)                /*!< MPU MAIR0: Attr2 Mask */
+
+#define MPU_MAIR0_Attr1_Pos                 8U                                            /*!< MPU MAIR0: Attr1 Position */
+#define MPU_MAIR0_Attr1_Msk                (0xFFUL << MPU_MAIR0_Attr1_Pos)                /*!< MPU MAIR0: Attr1 Mask */
+
+#define MPU_MAIR0_Attr0_Pos                 0U                                            /*!< MPU MAIR0: Attr0 Position */
+#define MPU_MAIR0_Attr0_Msk                (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)            /*!< MPU MAIR0: Attr0 Mask */
+
+/* MPU Memory Attribute Indirection Register 1 Definitions */
+#define MPU_MAIR1_Attr7_Pos                24U                                            /*!< MPU MAIR1: Attr7 Position */
+#define MPU_MAIR1_Attr7_Msk                (0xFFUL << MPU_MAIR1_Attr7_Pos)                /*!< MPU MAIR1: Attr7 Mask */
+
+#define MPU_MAIR1_Attr6_Pos                16U                                            /*!< MPU MAIR1: Attr6 Position */
+#define MPU_MAIR1_Attr6_Msk                (0xFFUL << MPU_MAIR1_Attr6_Pos)                /*!< MPU MAIR1: Attr6 Mask */
+
+#define MPU_MAIR1_Attr5_Pos                 8U                                            /*!< MPU MAIR1: Attr5 Position */
+#define MPU_MAIR1_Attr5_Msk                (0xFFUL << MPU_MAIR1_Attr5_Pos)                /*!< MPU MAIR1: Attr5 Mask */
+
+#define MPU_MAIR1_Attr4_Pos                 0U                                            /*!< MPU MAIR1: Attr4 Position */
+#define MPU_MAIR1_Attr4_Msk                (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)            /*!< MPU MAIR1: Attr4 Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SAU     Security Attribution Unit (SAU)
+  \brief    Type definitions for the Security Attribution Unit (SAU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Security Attribution Unit (SAU).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SAU Control Register */
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x004 (R/ )  SAU Type Register */
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  SAU Region Number Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  SAU Region Base Address Register */
+  __IOM uint32_t RLAR;                   /*!< Offset: 0x010 (R/W)  SAU Region Limit Address Register */
+#else
+        uint32_t RESERVED0[3];
+#endif
+  __IOM uint32_t SFSR;                   /*!< Offset: 0x014 (R/W)  Secure Fault Status Register */
+  __IOM uint32_t SFAR;                   /*!< Offset: 0x018 (R/W)  Secure Fault Address Register */
+} SAU_Type;
+
+/* SAU Control Register Definitions */
+#define SAU_CTRL_ALLNS_Pos                  1U                                            /*!< SAU CTRL: ALLNS Position */
+#define SAU_CTRL_ALLNS_Msk                 (1UL << SAU_CTRL_ALLNS_Pos)                    /*!< SAU CTRL: ALLNS Mask */
+
+#define SAU_CTRL_ENABLE_Pos                 0U                                            /*!< SAU CTRL: ENABLE Position */
+#define SAU_CTRL_ENABLE_Msk                (1UL /*<< SAU_CTRL_ENABLE_Pos*/)               /*!< SAU CTRL: ENABLE Mask */
+
+/* SAU Type Register Definitions */
+#define SAU_TYPE_SREGION_Pos                0U                                            /*!< SAU TYPE: SREGION Position */
+#define SAU_TYPE_SREGION_Msk               (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)           /*!< SAU TYPE: SREGION Mask */
+
+#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
+/* SAU Region Number Register Definitions */
+#define SAU_RNR_REGION_Pos                  0U                                            /*!< SAU RNR: REGION Position */
+#define SAU_RNR_REGION_Msk                 (0xFFUL /*<< SAU_RNR_REGION_Pos*/)             /*!< SAU RNR: REGION Mask */
+
+/* SAU Region Base Address Register Definitions */
+#define SAU_RBAR_BADDR_Pos                  5U                                            /*!< SAU RBAR: BADDR Position */
+#define SAU_RBAR_BADDR_Msk                 (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)            /*!< SAU RBAR: BADDR Mask */
+
+/* SAU Region Limit Address Register Definitions */
+#define SAU_RLAR_LADDR_Pos                  5U                                            /*!< SAU RLAR: LADDR Position */
+#define SAU_RLAR_LADDR_Msk                 (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)            /*!< SAU RLAR: LADDR Mask */
+
+#define SAU_RLAR_NSC_Pos                    1U                                            /*!< SAU RLAR: NSC Position */
+#define SAU_RLAR_NSC_Msk                   (1UL << SAU_RLAR_NSC_Pos)                      /*!< SAU RLAR: NSC Mask */
+
+#define SAU_RLAR_ENABLE_Pos                 0U                                            /*!< SAU RLAR: ENABLE Position */
+#define SAU_RLAR_ENABLE_Msk                (1UL /*<< SAU_RLAR_ENABLE_Pos*/)               /*!< SAU RLAR: ENABLE Mask */
+
+#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
+
+/* Secure Fault Status Register Definitions */
+#define SAU_SFSR_LSERR_Pos                  7U                                            /*!< SAU SFSR: LSERR Position */
+#define SAU_SFSR_LSERR_Msk                 (1UL << SAU_SFSR_LSERR_Pos)                    /*!< SAU SFSR: LSERR Mask */
+
+#define SAU_SFSR_SFARVALID_Pos              6U                                            /*!< SAU SFSR: SFARVALID Position */
+#define SAU_SFSR_SFARVALID_Msk             (1UL << SAU_SFSR_SFARVALID_Pos)                /*!< SAU SFSR: SFARVALID Mask */
+
+#define SAU_SFSR_LSPERR_Pos                 5U                                            /*!< SAU SFSR: LSPERR Position */
+#define SAU_SFSR_LSPERR_Msk                (1UL << SAU_SFSR_LSPERR_Pos)                   /*!< SAU SFSR: LSPERR Mask */
+
+#define SAU_SFSR_INVTRAN_Pos                4U                                            /*!< SAU SFSR: INVTRAN Position */
+#define SAU_SFSR_INVTRAN_Msk               (1UL << SAU_SFSR_INVTRAN_Pos)                  /*!< SAU SFSR: INVTRAN Mask */
+
+#define SAU_SFSR_AUVIOL_Pos                 3U                                            /*!< SAU SFSR: AUVIOL Position */
+#define SAU_SFSR_AUVIOL_Msk                (1UL << SAU_SFSR_AUVIOL_Pos)                   /*!< SAU SFSR: AUVIOL Mask */
+
+#define SAU_SFSR_INVER_Pos                  2U                                            /*!< SAU SFSR: INVER Position */
+#define SAU_SFSR_INVER_Msk                 (1UL << SAU_SFSR_INVER_Pos)                    /*!< SAU SFSR: INVER Mask */
+
+#define SAU_SFSR_INVIS_Pos                  1U                                            /*!< SAU SFSR: INVIS Position */
+#define SAU_SFSR_INVIS_Msk                 (1UL << SAU_SFSR_INVIS_Pos)                    /*!< SAU SFSR: INVIS Mask */
+
+#define SAU_SFSR_INVEP_Pos                  0U                                            /*!< SAU SFSR: INVEP Position */
+#define SAU_SFSR_INVEP_Msk                 (1UL /*<< SAU_SFSR_INVEP_Pos*/)                /*!< SAU SFSR: INVEP Mask */
+
+/*@} end of group CMSIS_SAU */
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_LSPENS_Pos               29U                                            /*!< FPCCR: LSPENS Position */
+#define FPU_FPCCR_LSPENS_Msk               (1UL << FPU_FPCCR_LSPENS_Pos)                  /*!< FPCCR: LSPENS bit Mask */
+
+#define FPU_FPCCR_CLRONRET_Pos             28U                                            /*!< FPCCR: CLRONRET Position */
+#define FPU_FPCCR_CLRONRET_Msk             (1UL << FPU_FPCCR_CLRONRET_Pos)                /*!< FPCCR: CLRONRET bit Mask */
+
+#define FPU_FPCCR_CLRONRETS_Pos            27U                                            /*!< FPCCR: CLRONRETS Position */
+#define FPU_FPCCR_CLRONRETS_Msk            (1UL << FPU_FPCCR_CLRONRETS_Pos)               /*!< FPCCR: CLRONRETS bit Mask */
+
+#define FPU_FPCCR_TS_Pos                   26U                                            /*!< FPCCR: TS Position */
+#define FPU_FPCCR_TS_Msk                   (1UL << FPU_FPCCR_TS_Pos)                      /*!< FPCCR: TS bit Mask */
+
+#define FPU_FPCCR_UFRDY_Pos                10U                                            /*!< FPCCR: UFRDY Position */
+#define FPU_FPCCR_UFRDY_Msk                (1UL << FPU_FPCCR_UFRDY_Pos)                   /*!< FPCCR: UFRDY bit Mask */
+
+#define FPU_FPCCR_SPLIMVIOL_Pos             9U                                            /*!< FPCCR: SPLIMVIOL Position */
+#define FPU_FPCCR_SPLIMVIOL_Msk            (1UL << FPU_FPCCR_SPLIMVIOL_Pos)               /*!< FPCCR: SPLIMVIOL bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_SFRDY_Pos                 7U                                            /*!< FPCCR: SFRDY Position */
+#define FPU_FPCCR_SFRDY_Msk                (1UL << FPU_FPCCR_SFRDY_Pos)                   /*!< FPCCR: SFRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_S_Pos                     2U                                            /*!< FPCCR: Security status of the FP context bit Position */
+#define FPU_FPCCR_S_Msk                    (1UL << FPU_FPCCR_S_Pos)                       /*!< FPCCR: Security status of the FP context bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+        uint32_t RESERVED4[1U];
+  __IOM uint32_t DAUTHCTRL;              /*!< Offset: 0x014 (R/W)  Debug Authentication Control Register */
+  __IOM uint32_t DSCSR;                  /*!< Offset: 0x018 (R/W)  Debug Security Control and Status Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESTART_ST_Pos   26U                                            /*!< CoreDebug DHCSR: S_RESTART_ST Position */
+#define CoreDebug_DHCSR_S_RESTART_ST_Msk   (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)      /*!< CoreDebug DHCSR: S_RESTART_ST Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/* Debug Authentication Control Register Definitions */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos  3U                                            /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
+#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)    /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
+
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos  2U                                            /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)    /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
+
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos   1U                                            /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */
+#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk  (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)     /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */
+
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos   0U                                            /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */
+#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk  (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */
+
+/* Debug Security Control and Status Register Definitions */
+#define CoreDebug_DSCSR_CDS_Pos            16U                                            /*!< CoreDebug DSCSR: CDS Position */
+#define CoreDebug_DSCSR_CDS_Msk            (1UL << CoreDebug_DSCSR_CDS_Pos)               /*!< CoreDebug DSCSR: CDS Mask */
+
+#define CoreDebug_DSCSR_SBRSEL_Pos          1U                                            /*!< CoreDebug DSCSR: SBRSEL Position */
+#define CoreDebug_DSCSR_SBRSEL_Msk         (1UL << CoreDebug_DSCSR_SBRSEL_Pos)            /*!< CoreDebug DSCSR: SBRSEL Mask */
+
+#define CoreDebug_DSCSR_SBRSELEN_Pos        0U                                            /*!< CoreDebug DSCSR: SBRSELEN Position */
+#define CoreDebug_DSCSR_SBRSELEN_Msk       (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)      /*!< CoreDebug DSCSR: SBRSELEN Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register. This parameter is interpreted as an uint32_t type.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Core Hardware */
+  #define SCS_BASE            (0xE000E000UL)                             /*!< System Control Space Base Address */
+  #define ITM_BASE            (0xE0000000UL)                             /*!< ITM Base Address */
+  #define DWT_BASE            (0xE0001000UL)                             /*!< DWT Base Address */
+  #define TPI_BASE            (0xE0040000UL)                             /*!< TPI Base Address */
+  #define CoreDebug_BASE      (0xE000EDF0UL)                             /*!< Core Debug Base Address */
+  #define SysTick_BASE        (SCS_BASE +  0x0010UL)                     /*!< SysTick Base Address */
+  #define NVIC_BASE           (SCS_BASE +  0x0100UL)                     /*!< NVIC Base Address */
+  #define SCB_BASE            (SCS_BASE +  0x0D00UL)                     /*!< System Control Block Base Address */
+
+  #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE         ) /*!< System control Register not in SCB */
+  #define SCB                 ((SCB_Type       *)     SCB_BASE         ) /*!< SCB configuration struct */
+  #define SysTick             ((SysTick_Type   *)     SysTick_BASE     ) /*!< SysTick configuration struct */
+  #define NVIC                ((NVIC_Type      *)     NVIC_BASE        ) /*!< NVIC configuration struct */
+  #define ITM                 ((ITM_Type       *)     ITM_BASE         ) /*!< ITM configuration struct */
+  #define DWT                 ((DWT_Type       *)     DWT_BASE         ) /*!< DWT configuration struct */
+  #define TPI                 ((TPI_Type       *)     TPI_BASE         ) /*!< TPI configuration struct */
+  #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE   ) /*!< Core Debug configuration struct */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE          (SCS_BASE +  0x0D90UL)                     /*!< Memory Protection Unit */
+    #define MPU               ((MPU_Type       *)     MPU_BASE         ) /*!< Memory Protection Unit */
+  #endif
+
+  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+    #define SAU_BASE          (SCS_BASE +  0x0DD0UL)                     /*!< Security Attribution Unit */
+    #define SAU               ((SAU_Type       *)     SAU_BASE         ) /*!< Security Attribution Unit */
+  #endif
+
+  #define FPU_BASE            (SCS_BASE +  0x0F30UL)                     /*!< Floating Point Unit */
+  #define FPU                 ((FPU_Type       *)     FPU_BASE         ) /*!< Floating Point Unit */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+  #define SCS_BASE_NS         (0xE002E000UL)                             /*!< System Control Space Base Address (non-secure address space) */
+  #define CoreDebug_BASE_NS   (0xE002EDF0UL)                             /*!< Core Debug Base Address           (non-secure address space) */
+  #define SysTick_BASE_NS     (SCS_BASE_NS +  0x0010UL)                  /*!< SysTick Base Address              (non-secure address space) */
+  #define NVIC_BASE_NS        (SCS_BASE_NS +  0x0100UL)                  /*!< NVIC Base Address                 (non-secure address space) */
+  #define SCB_BASE_NS         (SCS_BASE_NS +  0x0D00UL)                  /*!< System Control Block Base Address (non-secure address space) */
+
+  #define SCnSCB_NS           ((SCnSCB_Type    *)     SCS_BASE_NS      ) /*!< System control Register not in SCB(non-secure address space) */
+  #define SCB_NS              ((SCB_Type       *)     SCB_BASE_NS      ) /*!< SCB configuration struct          (non-secure address space) */
+  #define SysTick_NS          ((SysTick_Type   *)     SysTick_BASE_NS  ) /*!< SysTick configuration struct      (non-secure address space) */
+  #define NVIC_NS             ((NVIC_Type      *)     NVIC_BASE_NS     ) /*!< NVIC configuration struct         (non-secure address space) */
+  #define CoreDebug_NS        ((CoreDebug_Type *)     CoreDebug_BASE_NS) /*!< Core Debug configuration struct   (non-secure address space) */
+
+  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+    #define MPU_BASE_NS       (SCS_BASE_NS +  0x0D90UL)                  /*!< Memory Protection Unit            (non-secure address space) */
+    #define MPU_NS            ((MPU_Type       *)     MPU_BASE_NS      ) /*!< Memory Protection Unit            (non-secure address space) */
+  #endif
+
+  #define FPU_BASE_NS         (SCS_BASE_NS +  0x0F30UL)                  /*!< Floating Point Unit               (non-secure address space) */
+  #define FPU_NS              ((FPU_Type       *)     FPU_BASE_NS      ) /*!< Floating Point Unit               (non-secure address space) */
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+#ifdef CMSIS_NVIC_VIRTUAL
+  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
+    #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
+  #endif
+  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetPriorityGrouping    __NVIC_SetPriorityGrouping
+  #define NVIC_GetPriorityGrouping    __NVIC_GetPriorityGrouping
+  #define NVIC_EnableIRQ              __NVIC_EnableIRQ
+  #define NVIC_GetEnableIRQ           __NVIC_GetEnableIRQ
+  #define NVIC_DisableIRQ             __NVIC_DisableIRQ
+  #define NVIC_GetPendingIRQ          __NVIC_GetPendingIRQ
+  #define NVIC_SetPendingIRQ          __NVIC_SetPendingIRQ
+  #define NVIC_ClearPendingIRQ        __NVIC_ClearPendingIRQ
+  #define NVIC_GetActive              __NVIC_GetActive
+  #define NVIC_SetPriority            __NVIC_SetPriority
+  #define NVIC_GetPriority            __NVIC_GetPriority
+  #define NVIC_SystemReset            __NVIC_SystemReset
+#endif /* CMSIS_NVIC_VIRTUAL */
+
+#ifdef CMSIS_VECTAB_VIRTUAL
+  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
+  #endif
+  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
+#else
+  #define NVIC_SetVector              __NVIC_SetVector
+  #define NVIC_GetVector              __NVIC_GetVector
+#endif  /* (CMSIS_VECTAB_VIRTUAL) */
+
+#define NVIC_USER_IRQ_OFFSET          16
+
+
+/* Special LR values for Secure/Non-Secure call handling and exception handling                                               */
+
+/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS                   */ 
+#define FNC_RETURN                 (0xFEFFFFFFUL)     /* bit [0] ignored when processing a branch                             */
+
+/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
+#define EXC_RETURN_PREFIX          (0xFF000000UL)     /* bits [31:24] set to indicate an EXC_RETURN value                     */
+#define EXC_RETURN_S               (0x00000040UL)     /* bit [6] stack used to push registers: 0=Non-secure 1=Secure          */
+#define EXC_RETURN_DCRS            (0x00000020UL)     /* bit [5] stacking rules for called registers: 0=skipped 1=saved       */
+#define EXC_RETURN_FTYPE           (0x00000010UL)     /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
+#define EXC_RETURN_MODE            (0x00000008UL)     /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode      */
+#define EXC_RETURN_SPSEL           (0x00000004UL)     /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP           */
+#define EXC_RETURN_ES              (0x00000001UL)     /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
+
+/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking                            */
+#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)  /* Value for processors with floating-point extension:                  */
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125AUL)     /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE                   */
+#else 
+#define EXC_INTEGRITY_SIGNATURE     (0xFEFA125BUL)     /* Value for processors without floating-point extension                */
+#endif
+
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt
+  \details Enables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    __COMPILER_BARRIER();
+    NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __COMPILER_BARRIER();
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status
+  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt
+  \details Disables a device specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+    __DSB();
+    __ISB();
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Get Interrupt Target State
+  \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+  \return             1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Target State
+  \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |=  ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Clear Interrupt Target State
+  \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  if interrupt is assigned to Secure
+                      1  if interrupt is assigned to Non Secure
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
+    return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every processor exception.
+ */
+__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of a device specific interrupt or a processor exception.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   Set Interrupt Vector
+  \details Sets an interrupt vector in SRAM based interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+           VTOR must been relocated to SRAM before.
+  \param [in]   IRQn      Interrupt number
+  \param [in]   vector    Address of interrupt handler function
+ */
+__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+  __DSB();
+}
+
+
+/**
+  \brief   Get Interrupt Vector
+  \details Reads an interrupt vector from interrupt vector table.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn      Interrupt number.
+  \return                 Address of interrupt handler function
+ */
+__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
+{
+  uint32_t *vectors = (uint32_t *)SCB->VTOR;
+  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   Set Priority Grouping (non-secure)
+  \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB_NS->AIRCR;                                                /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)  );              /* Insert write key and priority group */
+  SCB_NS->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping (non-secure)
+  \details Reads the priority grouping field from the non-secure NVIC when in secure state.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
+{
+  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable Interrupt (non-secure)
+  \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Enable status (non-secure)
+  \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt is not enabled.
+  \return             1  Interrupt is enabled.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Disable Interrupt (non-secure)
+  \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Pending Interrupt (non-secure)
+  \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Pending Interrupt (non-secure)
+  \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Clear Pending Interrupt (non-secure)
+  \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
+  \param [in]      IRQn  Device specific interrupt number.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+  }
+}
+
+
+/**
+  \brief   Get Active Interrupt (non-secure)
+  \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
+  \param [in]      IRQn  Device specific interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+  \note    IRQn must not be negative.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+  }
+  else
+  {
+    return(0U);
+  }
+}
+
+
+/**
+  \brief   Set Interrupt Priority (non-secure)
+  \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+  \note    The priority cannot be set for every non-secure processor exception.
+ */
+__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) >= 0)
+  {
+    NVIC_NS->IPR[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority (non-secure)
+  \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
+           The interrupt number can be positive to specify a device specific interrupt,
+           or negative to specify a processor exception.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) >= 0)
+  {
+    return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+#endif /*  defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+/* ##########################  MPU functions  #################################### */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
+
+#include "mpu_armv8.h"
+
+#endif
+
+/* ##########################  FPU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_FpuFunctions FPU Functions
+  \brief    Function that provides FPU type.
+  @{
+ */
+
+/**
+  \brief   get FPU type
+  \details returns the FPU type
+  \returns
+   - \b  0: No FPU
+   - \b  1: Single precision FPU
+   - \b  2: Double + Single precision FPU
+ */
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)
+{
+  uint32_t mvfr0;
+
+  mvfr0 = FPU->MVFR0;
+  if      ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
+  {
+    return 2U;           /* Double + Single precision FPU */
+  }
+  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
+  {
+    return 1U;           /* Single precision FPU */
+  }
+  else
+  {
+    return 0U;           /* No FPU */
+  }
+}
+
+
+/*@} end of CMSIS_Core_FpuFunctions */
+
+
+
+/* ##########################   SAU functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SAUFunctions SAU Functions
+  \brief    Functions that configure the SAU.
+  @{
+ */
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+
+/**
+  \brief   Enable SAU
+  \details Enables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Enable(void)
+{
+    SAU->CTRL |=  (SAU_CTRL_ENABLE_Msk);
+}
+
+
+
+/**
+  \brief   Disable SAU
+  \details Disables the Security Attribution Unit (SAU).
+ */
+__STATIC_INLINE void TZ_SAU_Disable(void)
+{
+    SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
+}
+
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+/*@} end of CMSIS_Core_SAUFunctions */
+
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
+/**
+  \brief   System Tick Configuration (non-secure)
+  \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+
+ */
+__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                         /* Reload value impossible */
+  }
+
+  SysTick_NS->LOAD  = (uint32_t)(ticks - 1UL);                            /* set reload register */
+  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick_NS->VAL   = 0UL;                                                /* Load the SysTick Counter Value */
+  SysTick_NS->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                      SysTick_CTRL_TICKINT_Msk   |
+                      SysTick_CTRL_ENABLE_Msk;                            /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                           /* Function successful */
+}
+#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                              /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY  ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM33_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */

bsp/acm32f4xx-nucleo/libraries/CMSIS/mpu_armv8.h

@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/Device/ACM32F4.h

@@ -0,0 +1,848 @@
+/*
+  ******************************************************************************
+  * @file    ACM32F4.h
+  * @brief   CMSIS ACM32F4 Device Peripheral Access Layer Header File.
+  *
+  *          This file contains:
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral¡¯s registers hardware
+  *
+  ******************************************************************************
+*/
+#ifndef __ACM32F4_H__
+#define __ACM32F4_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+///*------------------- Interrupt Number Definition ----------------------*/
+typedef enum IRQn
+{
+/* ----------------------------------  Cortex-M33 Processor Exceptions Numbers ----------------------------------- */
+    Reset_IRQn                = -15,       /* -15 Reset Vector, invoked on Power up and warm reset                 */
+    NonMaskableInt_IRQn       = -14,       /* -14 Non maskable Interrupt, cannot be stopped or preempted           */
+    HardFault_IRQn            = -13,       /* -13 Hard Fault, all classes of Fault                                 */
+    MemoryManagement_IRQn     = -12,       /* -12 Memory Management, MPU mismatch, including Access Violation
+                                                  and No Match                                                     */
+    BusFault_IRQn             = -11,       /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                  related Fault                                                    */
+    UsageFault_IRQn           = -10,       /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
+    SVCall_IRQn               =  -5,       /* -5  System Service Call via SVC instruction                          */
+    DebugMonitor_IRQn         =  -4,       /* -4  Debug Monitor                                                    */
+    PendSV_IRQn               =  -2,       /* -2  Pendable request for system service                              */
+    SysTick_IRQn              =  -1,       /* -1  System Tick Timer                                                */
+
+/* -------------------------------------  ARMCM0 Specific Interrupt Numbers -------------------------------------- */
+    WDT_IRQn                    = 0,       /* 0:  WDT_IRQHandler                                                   */
+    RTC_IRQn                    = 1,       /* 1:  RTC_IRQHandler                                                   */
+    EFC_IRQn                    = 2,       /* 2:  EFC_IRQHandler                                                   */
+    GPIOAB_IRQn                 = 3,       /* 3:  GPIOAB_IRQHandler                                                */
+    GPIOCD_IRQn                 = 4,       /* 4:  GPIOCD_IRQHandler                                                */
+    EXTI_IRQn                   = 5,       /* 5:  EXTI_IRQHandler                                                  */
+    SRAM_PARITY_IRQn            = 6,       /* 6:  SRAM_PARITY_IRQHandler                                           */
+    CLKRDY_IRQn                 = 7,       /* 7:  CLKRDY_IRQHandler                                                */
+    UART4_IRQn                  = 8,       /* 8:  UART4_IRQHandler                                                 */
+    DMA_IRQn                    = 9,       /* 9:  DMA_IRQHandler                                                   */
+    UART3_IRQn                  = 10,      /* 10: UART3_IRQHandler                                                 */
+    ADC_IRQn                    = 12,      /* 12: ADC_IRQHandler                                                   */
+    TIM1_BRK_UP_TRG_COM_IRQn    = 13,      /* 13: TIM1_BRK_UP_TRG_COM_IRQHandler                                   */
+    TIM1_CC_IRQn                = 14,      /* 14: TIM1_CC_IRQHandler                                               */
+    TIM2_IRQn                   = 15,      /* 15: TIM2_IRQHandler                                                  */
+    TIM3_IRQn                   = 16,      /* 16: TIM3_IRQHandler                                                  */
+    TIM6_IRQn                   = 17,      /* 17: TIM6_IRQHandler                                                  */
+    TIM7_IRQn                   = 18,      /* 18: TIM7_IRQHandler                                                  */
+    TIM14_IRQn                  = 19,      /* 19: TIM14_IRQHandler                                                 */
+    TIM15_IRQn                  = 20,      /* 20: TIM15_IRQHandler                                                 */
+    TIM16_IRQn                  = 21,      /* 21: TIM16_IRQHandler                                                 */
+    TIM17_IRQn                  = 22,      /* 22: TIM17_IRQHandler                                                 */
+    I2C1_IRQn                   = 23,      /* 23: I2C1_IRQHandler                                                  */
+    I2C2_IRQn                   = 24,      /* 24: I2C2_IRQHandler                                                  */
+    SPI1_IRQn                   = 25,      /* 25: SPI1_IRQHandler                                                  */
+    SPI2_IRQn                   = 26,      /* 26: SPI2_IRQHandler                                                  */
+    UART1_IRQn                  = 27,      /* 27: UART1_IRQHandler                                                 */
+    UART2_IRQn                  = 28,      /* 28: UART2_IRQHandler                                                 */
+    LPUART_IRQn                 = 29,      /* 29: LPUART_IRQHandler                                                */
+    SPI3_IRQn                   = 30,      /* 30: SPI3_IRQHandler                                                  */
+    AES_IRQn                    = 31,      /* 31: AES_IRQHandler                                                   */
+    USB_IRQn                    = 32,      /* 32: USB_IRQHandler                                                   */
+    DAC_IRQn                    = 33,      /* 33: DAC_IRQHandler                                                   */
+    I2S_IRQn                    = 34,      /* 34: I2S_IRQHandler                                                   */
+    GPIOEF_IRQ                  = 35,      /* 35: GPIOEF_IRQHandler                                                */
+    CAN1_IRQn                   = 36,      /* 36: CAN1_IRQHandler                                                  */
+    CAN2_IRQn                   = 37,      /* 37: CAN2_IRQHandler                                                  */
+    FPU_IRQn                    = 38,      /* 38: FPU_IRQHandler                                                   */
+    TIM4_IRQn                   = 39,      /* 39: TIM4_IRQHandler                                                  */
+    SPI4_IRQn                   = 40,      /* 40: SPI4_IRQHandler                                                  */
+} IRQn_Type;
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* Configuration of the Cortex-M33 Processor and Core Peripherals */
+#define __MPU_PRESENT           1       /*!< mcu does not provide a MPU present or not       */
+#define __NVIC_PRIO_BITS        3       /*!< mcu Supports 3 Bits for the Priority Levels     */
+#define __Vendor_SysTickConfig  0       /*!< Set to 1 if different SysTick Config is used         */  
+
+#define   ARM_MATH_CM4          1 
+#define __TARGET_FPU_VFP        1 
+#define __FPU_PRESENT           1 
+#define __DSP_PRESENT           1 
+#define __ARM_COMPAT_H          1 
+#define __ACCELERATE_PRESENT    1  
+#define __ACCELERATE_EH_PRESENT 0         
+
+#include "core_cm33.h"         /* Processor and core peripherals */
+
+#include "stdio.h"
+#include "stdint.h"
+#include "stdbool.h"
+#include "string.h"
+
+///*------------------- Bit Opertions ----------------------*/
+#define BIT0            (1U << 0)
+#define BIT1            (1U << 1)
+#define BIT2            (1U << 2)
+#define BIT3            (1U << 3)
+#define BIT4            (1U << 4)
+#define BIT5            (1U << 5)
+#define BIT6            (1U << 6)
+#define BIT7            (1U << 7)
+#define BIT8            (1U << 8)
+#define BIT9            (1U << 9)
+#define BIT10           (1U << 10)
+#define BIT11           (1U << 11)
+#define BIT12           (1U << 12)
+#define BIT13           (1U << 13)
+#define BIT14           (1U << 14)
+#define BIT15           (1U << 15)
+#define BIT16           (1U << 16)
+#define BIT17           (1U << 17)
+#define BIT18           (1U << 18)
+#define BIT19           (1U << 19)
+#define BIT20           (1U << 20)
+#define BIT21           (1U << 21)
+#define BIT22           (1U << 22)
+#define BIT23           (1U << 23)
+#define BIT24           (1U << 24)
+#define BIT25           (1U << 25)
+#define BIT26           (1U << 26)
+#define BIT27           (1U << 27)
+#define BIT28           (1U << 28)
+#define BIT29           (1U << 29)
+#define BIT30           (1U << 30)
+#define BIT31           (1U << 31)
+
+
+/** @Addtogroup Peripheral_Registers_Structures
+  * @{
+  */
+
+///*------------------- FLASH Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t SEC;
+    __IO uint32_t ADCT;
+    __IO uint32_t TERASE;
+    __IO uint32_t TPROG;
+    __IO uint32_t STATUS;
+    __IO uint32_t INTSTATUS;
+    __IO uint32_t INTEN;
+    __IO uint32_t CONFIG;
+    __IO uint32_t EDCTRL;
+    __IO uint32_t RDN0;
+    __IO uint32_t RDN1;
+    __IO uint32_t RDN2;
+    __IO uint32_t RDN3;
+    __IO uint32_t TNVS;
+    __IO uint32_t TMODE_SEC;
+    __IO uint32_t TDOUT;
+    __IO uint32_t TDIN;
+    __IO uint32_t TCTRL;
+}EFC_TypeDef;
+
+
+///*------------------- Timer Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t CR1;
+    __IO uint32_t CR2;
+    __IO uint32_t SMCR;
+    __IO uint32_t DIER;
+    __IO uint32_t SR;
+    __IO uint32_t EGR;
+    __IO uint32_t CCMR1;
+    __IO uint32_t CCMR2;
+    __IO uint32_t CCER;
+    __IO uint32_t CNT;
+    __IO uint32_t PSC;
+    __IO uint32_t ARR;
+    __IO uint32_t RCR;
+    __IO uint32_t CCR1;
+    __IO uint32_t CCR2;
+    __IO uint32_t CCR3;
+    __IO uint32_t CCR4;
+    __IO uint32_t BDTR;
+    __IO uint32_t DCR;
+    __IO uint32_t DMAR;
+    __IO uint32_t RSV0[4];
+    __IO uint32_t AF1;
+    __IO uint32_t RSV1;
+    __IO uint32_t TISEL;
+    __IO uint32_t DBER;
+}TIM_TypeDef;
+
+
+///*------------------- RTC¡¢PMU Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t WP;
+    __IO uint32_t IE;
+    __IO uint32_t SR;
+    __IO uint32_t SEC;
+    __IO uint32_t MIN;
+    __IO uint32_t HOUR;
+    __IO uint32_t DATE;
+    __IO uint32_t WEEK;
+    __IO uint32_t MONTH;
+    __IO uint32_t YEAR;
+    __IO uint32_t ALM;
+    __IO uint32_t CR;
+    __IO uint32_t ADJUST;
+    __IO uint32_t RSV0[4];
+    __IO uint32_t CLKSTAMP1_TIME;
+    __IO uint32_t CALSTAMP1_DATE;
+    __IO uint32_t CLKSTAMP2_TIME;
+    __IO uint32_t CALSTAMP2_DATE;
+    __IO uint32_t RSV2[7];
+    __IO uint32_t BAKUP[5];
+}RTC_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t CR1;
+    __IO uint32_t SR;
+    __IO uint32_t IOSEL;
+    __IO uint32_t IOCR;
+    __IO uint32_t ANACR;
+    __IO uint32_t CR2;
+}PMU_TypeDef;
+
+
+///*------------------- WDT Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t LOAD;
+    __IO uint32_t COUNT;
+    __IO uint32_t CTRL;
+    __IO uint32_t FEED;
+    __IO uint32_t INTCLRTIME;
+    __IO uint32_t RIS;
+}WDT_TypeDef;
+
+
+///*------------------- IWDT Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t CMDR;
+    __IO uint32_t PR;
+    __IO uint32_t RLR;
+    __IO uint32_t SR;
+    __IO uint32_t WINR;
+    __IO uint32_t WUTR;
+}IWDT_TypeDef;
+
+
+///*------------------- UART Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DR;
+    __IO uint32_t RSR;
+    __IO uint32_t RSV0[4];
+    __IO uint32_t FR;
+    __IO uint32_t RSV1;
+    __IO uint32_t ILPR;
+    __IO uint32_t IBRD;
+    __IO uint32_t FBRD;
+    __IO uint32_t LCRH;
+    __IO uint32_t CR;
+    __IO uint32_t IFLS;
+    __IO uint32_t IE;
+    __IO uint32_t RIS;
+    __IO uint32_t MIS;
+    __IO uint32_t ICR;
+    __IO uint32_t DMACR;
+    __IO uint32_t RSV2[2];
+    __IO uint32_t CR2;
+    __IO uint32_t BCNT;
+}UART_TypeDef;
+
+
+///*------------------- I2C Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t SLAVE_ADDR1;
+    __IO uint32_t CLK_DIV;
+    __IO uint32_t CR;
+    __IO uint32_t SR;
+    __IO uint32_t DR;
+    __IO uint32_t SLAVE_ADDR2_3;
+    __IO uint32_t RSV[3];
+    __IO uint32_t TIMEOUT;
+}I2C_TypeDef;
+
+
+///*------------------- CAN Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t ACR[4];
+    __IO uint32_t AMR[4];
+    __IO uint32_t RSV[5];
+}Filter_typedef;
+
+typedef union 
+{
+    __IO uint32_t  DATABUF[13];
+    Filter_typedef FILTER;
+}DF_typedef;
+
+typedef struct
+{
+    __IO uint32_t MOD;
+    __IO uint32_t CMR;
+    __IO uint32_t SR;
+    __IO uint32_t IR;
+    __IO uint32_t IER;
+    __IO uint32_t RSV0;
+    __IO uint32_t BTR0;
+    __IO uint32_t BTR1;
+    __IO uint32_t OCR;
+    __IO uint32_t RSV1;
+    __IO uint32_t RSV2;
+    __IO uint32_t ALC;
+    __IO uint32_t ECC;
+    __IO uint32_t EWLR;
+    __IO uint32_t RXERR;
+    __IO uint32_t TXERR;
+    __IO DF_typedef    DF;
+    __IO uint32_t RMC;
+    __IO uint32_t RBSA;
+    __IO uint32_t CDR;
+    __IO uint32_t RXFIFO[64];
+    __IO uint32_t TXFIFO[13];
+}CAN_TypeDef;
+
+
+///*------------------- DAC Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t CR;
+    __IO uint32_t SWTRIGR;
+    __IO uint32_t DHR12R1;
+    __IO uint32_t DHR12L1;
+    __IO uint32_t DHR8R1;
+    __IO uint32_t DHR12R2;
+    __IO uint32_t DHR12L2;
+    __IO uint32_t DHR8R2;
+    __IO uint32_t DHR12RD;
+    __IO uint32_t DHR12LD;
+    __IO uint32_t DHR8RD;
+    __IO uint32_t DOR1;
+    __IO uint32_t DOR2;
+    __IO uint32_t SR;
+    __IO uint32_t CCR;
+    __IO uint32_t MCR;
+    __IO uint32_t SHSR1;
+    __IO uint32_t SHSR2;
+    __IO uint32_t SHHR;
+    __IO uint32_t SHRR;
+}DAC_TypeDef;
+
+
+///*------------------- LPUART Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t RXDR;
+    __IO uint32_t TXDR;
+    __IO uint32_t LCR;
+    __IO uint32_t CR;
+    __IO uint32_t IBAUD;
+    __IO uint32_t FBAUD;
+    __IO uint32_t IE;
+    __IO uint32_t SR;
+    __IO uint32_t ADDR;
+}LPUART_TypeDef;
+
+
+///*------------------- COMP Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t CR1;
+    __IO uint32_t CR2;
+    __IO uint32_t SR;
+}COMP_TypeDef;
+
+
+///*------------------- OPA Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t OPA1_CSR;
+    __IO uint32_t OPA2_CSR;
+    __IO uint32_t OPA3_CSR;
+}OPA_TypeDef;
+
+
+///*------------------- EXTI Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t IENR;
+    __IO uint32_t EENR;
+    __IO uint32_t RTENR;
+    __IO uint32_t FTENR;
+    __IO uint32_t SWIER;
+    __IO uint32_t PDR;
+    __IO uint32_t EXTICR1;
+    __IO uint32_t EXTICR2;
+}EXTI_TypeDef;
+
+
+///*------------------- SCU Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t RCR;
+    __IO uint32_t RSR;
+    __IO uint32_t IPRST2;
+    __IO uint32_t IPRST1;
+    __IO uint32_t CCR1;
+    __IO uint32_t CCR2;
+    __IO uint32_t CIR;
+    __IO uint32_t IPCKENR1;
+    __IO uint32_t IPCKENR2;
+    __IO uint32_t RCHCR;
+    __IO uint32_t XTHCR;
+    __IO uint32_t PLLCR;
+    __IO uint32_t LDOCR;
+    __IO uint32_t RSV0;
+    __IO uint32_t WMR;
+    __IO uint32_t CLKOCR;
+    __IO uint32_t VER;
+    __IO uint32_t SYSCFG1;
+    __IO uint32_t LVDCFG;
+    __IO uint32_t STOPCFG;
+    __IO uint32_t RSV1;
+    __IO uint32_t PHYCR;
+    __IO uint32_t MEMCFG;
+    __IO uint32_t DUMMY;
+    __IO uint32_t PASEL1;
+    __IO uint32_t PASEL2;
+    __IO uint32_t PBSEL1;
+    __IO uint32_t PBSEL2;
+    __IO uint32_t PABPUR;
+    __IO uint32_t PABPDR;
+    __IO uint32_t PASTR;
+    __IO uint32_t PBSTR;
+    __IO uint32_t PABSMTR;
+    __IO uint32_t PABODR;
+    __IO uint32_t PABADS;
+    __IO uint32_t RSV2;
+    __IO uint32_t PCSEL1;
+    __IO uint32_t PCSEL2;
+    __IO uint32_t PDSEL1;
+    __IO uint32_t PDSEL2;
+    __IO uint32_t PCDPUR;
+    __IO uint32_t PCDPDR;
+    __IO uint32_t PCSTR;
+    __IO uint32_t PDSTR;
+    __IO uint32_t PCDSMTR;
+    __IO uint32_t PCDODR;
+    __IO uint32_t PCDADS;
+    __IO uint32_t RSV3;
+    __IO uint32_t PESEL1;
+    __IO uint32_t PESEL2;
+    __IO uint32_t PFSEL1;
+    __IO uint32_t RSV4;
+    __IO uint32_t PEFPUR;
+    __IO uint32_t PEFPDR;
+    __IO uint32_t PESTR;
+    __IO uint32_t PFSTR;
+    __IO uint32_t PEFSMTR;
+    __IO uint32_t PEFODR;
+    __IO uint32_t PEFADS;
+}SCU_TypeDef;
+
+
+///*------------------- CRC Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DATA;
+    __IO uint32_t CTRL;
+    __IO uint32_t INIT;
+    __IO uint32_t RSV0;
+    __IO uint32_t OUTXOR;
+    __IO uint32_t POLY;
+    __IO uint32_t FDATA;
+}CRC_TypeDef;
+
+
+///*------------------- ADC Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t SR;
+    __IO uint32_t IE;
+    __IO uint32_t CR1;
+    __IO uint32_t CR2;
+    __IO uint32_t SMPR1;
+    __IO uint32_t SMPR2;
+    __IO uint32_t HTR;
+    __IO uint32_t LTR;
+    __IO uint32_t SQR1;
+    __IO uint32_t SQR2;
+    __IO uint32_t SQR3;
+    __IO uint32_t JSQR;
+    __IO uint32_t JDR;
+    __IO uint32_t DR;
+    __IO uint32_t DIFF;
+    __IO uint32_t SIGN;
+    __IO uint32_t TSREF;
+    __IO uint32_t SMPR3;
+}ADC_TypeDef;
+
+
+///*------------------- I2S Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DAT;
+    __IO uint32_t CTL;
+    __IO uint32_t PSC;
+    __IO uint32_t IE;
+    __IO uint32_t STATUS;
+}I2S_TypeDef;
+
+
+///*------------------- GPIO Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DIR;
+    __IO uint32_t RSV0; 
+    __IO uint32_t SET;
+    __IO uint32_t CLR;
+    __IO uint32_t ODATA;
+    __IO uint32_t IDATA;
+    __IO uint32_t IEN;
+    __IO uint32_t IS;
+    __IO uint32_t IBE;
+    __IO uint32_t IEV;
+    __IO uint32_t IC;
+    __IO uint32_t RIS;
+    __IO uint32_t MIS;
+}GPIO_TypeDef;
+
+
+///*------------------- SPI Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DAT;
+    __IO uint32_t BAUD;
+    __IO uint32_t CTL;
+    __IO uint32_t TX_CTL;
+    __IO uint32_t RX_CTL;
+    __IO uint32_t IE;
+    __IO uint32_t STATUS;
+    __IO uint32_t TX_DELAY;
+    __IO uint32_t BATCH;
+    __IO uint32_t CS;
+    __IO uint32_t OUT_EN;
+    __IO uint32_t MEMO_ACC;
+    __IO uint32_t CMD;
+    __IO uint32_t PARA;
+}SPI_TypeDef;
+
+
+///*------------------- DMA Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t INT_STATUS;
+    __IO uint32_t INT_TC_STATUS;
+    __IO uint32_t INT_TC_CLR;
+    __IO uint32_t INT_ERR_STATUS;
+    __IO uint32_t INT_ERR_CLR;
+    __IO uint32_t RAW_INT_TC_STATUS;
+    __IO uint32_t RAW_INT_ERR_STATUS;
+    __IO uint32_t EN_CH_STATUS;
+    __IO uint32_t RSV0[4];
+    __IO uint32_t CONFIG;
+    __IO uint32_t SYNCLO;
+    __IO uint32_t SYNCHI;
+}DMA_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t SRC_ADDR;
+    __IO uint32_t DEST_ADDR;
+    __IO uint32_t LLI;
+    __IO uint32_t CTRL;
+    __IO uint32_t CONFIG;
+}DMA_Channel_TypeDef;
+
+
+///*------------------- AES Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DATAIN;
+    __IO uint32_t KEYIN;
+    __IO uint32_t RSV0;
+    __IO uint32_t CONTROL;
+    __IO uint32_t STATE;
+    __IO uint32_t DATAOUT;
+}AES_TypeDef;
+
+
+///*------------------- FAU Registers ----------------------*/
+typedef struct
+{
+	__IO uint32_t CTRL1;            //0x00
+	__IO uint32_t STAUTS;           //0x04
+
+	__IO uint32_t CORDIC_X_DATAIN;  //0x08  
+	__IO uint32_t CORDIC_Y_DATAIN;  //0x0c	
+	__IO uint32_t RESULT1;          //0x10  
+	__IO uint32_t RESULT2;          //0x14  
+}FAU_TypeDef;
+
+
+///*------------------- HRNG Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t CTRL;
+    __IO uint32_t LFSR;
+}HRNG_TypeDef;
+
+
+///*------------------- HASH Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t DATAIN;
+    __IO uint32_t MIDDATA;
+    __IO uint32_t CTRL;
+    __IO uint32_t DATAOUT;
+}HASH_TypeDef;
+
+
+///*------------------- USB Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t WORKING_MODE;
+    __IO uint32_t EPxCSR[5]; 
+    __IO uint32_t USB_ADDR;
+    __IO uint32_t SETIP_0_3_DATA;
+    __IO uint32_t SETIP_4_7_DATA;
+    __IO uint32_t EPADDR_CFG;
+    __IO uint32_t CURRENT_PID;
+    __IO uint32_t CURRENT_FRAME_NUMBER;
+    __IO uint32_t CRC_ERROR_CNT;
+    __IO uint32_t USB_STATUS_DETECT_CNT;
+    __IO uint32_t RSV0;
+    __IO uint32_t RSV1;
+    __IO uint32_t EPxSENDBN[5];
+}USB_CTRLTypeDef;
+
+///*------------------- USB interrupt access Registers ----------------------*/
+typedef struct
+{
+    __IO uint32_t INT_STAT_RAW;    
+    __IO uint32_t INT_EN;  
+    __IO uint32_t RSV;  
+    __IO uint32_t INT_CLR;       
+}USB_INTTypeDef;  
+
+/**
+  * @}
+  */
+
+
+
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+///*------------------- Peripheral memory map ----------------------*/
+#define EFLASH_BASE        (0x00000000UL)
+#define SRAM_BASE          (0x20000000UL)
+#define PERIPH_BASE        (0x40000000UL)
+#define QSPI_BASE          (0x90000000UL)
+
+#define APB1PERIPH_BASE       (PERIPH_BASE)
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
+#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000UL)
+
+///*---------------------- EFC peripherals ------------------------*/
+#define EFLASH_REG_BASE   (EFLASH_BASE + 0x00100000)
+
+///*---------------------- APB1 peripherals ------------------------*/
+#define TIM2_BASE         (APB1PERIPH_BASE + 0x00000000UL) 
+#define TIM3_BASE         (APB1PERIPH_BASE + 0x00000400UL) 
+#define TIM4_BASE         (APB1PERIPH_BASE + 0x00000800UL) 
+#define TIM6_BASE         (APB1PERIPH_BASE + 0x00001000UL) 
+#define TIM7_BASE         (APB1PERIPH_BASE + 0x00001400UL) 
+#define TIM14_BASE        (APB1PERIPH_BASE + 0x00002000UL) 
+#define PMU_BASE          (APB1PERIPH_BASE + 0x00002400UL) 
+#define RTC_BASE          (APB1PERIPH_BASE + 0x00002800UL) 
+#define WDT_BASE          (APB1PERIPH_BASE + 0x00002C00UL) 
+#define IWDT_BASE         (APB1PERIPH_BASE + 0x00003000UL) 
+#define UART2_BASE        (APB1PERIPH_BASE + 0x00004400UL) 
+#define UART3_BASE        (APB1PERIPH_BASE + 0x00004800UL) 
+#define UART4_BASE        (APB1PERIPH_BASE + 0x00004C00UL) 
+#define I2C1_BASE         (APB1PERIPH_BASE + 0x00005400UL) 
+#define I2C2_BASE         (APB1PERIPH_BASE + 0x00005800UL) 
+#define CAN1_BASE         (APB1PERIPH_BASE + 0x00006400UL) 
+#define CAN2_BASE         (APB1PERIPH_BASE + 0x00006800UL) 
+#define DAC_BASE          (APB1PERIPH_BASE + 0x00007400UL) 
+#define LPUART_BASE       (APB1PERIPH_BASE + 0x00008000UL) 
+
+///*---------------------- APB2 peripherals ------------------------*/
+#define COMP_BASE         (APB2PERIPH_BASE + 0x00000200UL) 
+#define OPA_BASE          (APB2PERIPH_BASE + 0x00000300UL) 
+#define EXTI_BASE         (APB2PERIPH_BASE + 0x00000400UL) 
+#define SCU_BASE          (APB2PERIPH_BASE + 0x00000800UL) 
+#define CRC_BASE          (APB2PERIPH_BASE + 0x00000C00UL) 
+#define ADC_BASE          (APB2PERIPH_BASE + 0x00002400UL) 
+#define TIM1_BASE         (APB2PERIPH_BASE + 0x00002C00UL) 
+#define I2S1_BASE         (APB2PERIPH_BASE + 0x00003000UL) 
+#define UART1_BASE        (APB2PERIPH_BASE + 0x00003800UL) 
+#define TIM15_BASE        (APB2PERIPH_BASE + 0x00004000UL) 
+#define TIM16_BASE        (APB2PERIPH_BASE + 0x00004400UL) 
+#define TIM17_BASE        (APB2PERIPH_BASE + 0x00004800UL) 
+#define GPIOAB_BASE       (APB2PERIPH_BASE + 0x0000F000UL) 
+#define GPIOCD_BASE       (APB2PERIPH_BASE + 0x0000F400UL) 
+#define GPIOEF_BASE       (APB2PERIPH_BASE + 0x0000F800UL) 
+
+///*---------------------- AHB peripherals ------------------------*/
+#define SPI1_BASE            (AHBPERIPH_BASE)
+#define SPI2_BASE            (AHBPERIPH_BASE + 0x00000400UL)
+#define SPI3_BASE            (AHBPERIPH_BASE + 0x00000800UL)
+#define SPI4_BASE            (AHBPERIPH_BASE + 0x00000C00UL)
+#define DMA_BASE             (AHBPERIPH_BASE + 0x00001000UL)
+#define DMA_Channel0_BASE    (AHBPERIPH_BASE + 0x00001100UL)
+#define DMA_Channel1_BASE    (AHBPERIPH_BASE + 0x00001120UL)
+#define DMA_Channel2_BASE    (AHBPERIPH_BASE + 0x00001140UL)
+#define DMA_Channel3_BASE    (AHBPERIPH_BASE + 0x00001160UL)
+#define DMA_Channel4_BASE    (AHBPERIPH_BASE + 0x00001180UL)
+#define DMA_Channel5_BASE    (AHBPERIPH_BASE + 0x000011A0UL)
+#define DMA_Channel6_BASE    (AHBPERIPH_BASE + 0x000011C0UL)
+#define DMA_Channel7_BASE    (AHBPERIPH_BASE + 0x000011E0UL)
+#define AES_BASE             (AHBPERIPH_BASE + 0x00010000UL)
+#define FAU_BASE             (AHBPERIPH_BASE + 0x00010400UL)
+#define HRNG_BASE            (AHBPERIPH_BASE + 0x00010800UL)
+#define HASH_BASE            (AHBPERIPH_BASE + 0x00010C00UL)
+#define USB_BASE             (AHBPERIPH_BASE + 0x00020000UL)   
+
+///*---------------------- QSPI Memory ------------------------*/
+#define QSPI3_BASE           (QSPI_BASE)
+
+/**
+  * @}
+  */
+
+
+
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define EFC                 ((EFC_TypeDef *)EFLASH_REG_BASE)
+#define TIM2                ((TIM_TypeDef *)TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *)TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *)TIM4_BASE)
+#define TIM6                ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *)TIM7_BASE)
+#define TIM14               ((TIM_TypeDef *)TIM14_BASE)
+#define PMU                 ((PMU_TypeDef *)PMU_BASE)
+#define RTC                 ((RTC_TypeDef *)RTC_BASE)
+#define WDT                 ((WDT_TypeDef *)WDT_BASE)
+#define IWDT                ((IWDT_TypeDef *)IWDT_BASE)
+#define UART2               ((UART_TypeDef *)UART2_BASE)
+#define UART3               ((UART_TypeDef *)UART3_BASE)
+#define UART4               ((UART_TypeDef *)UART4_BASE)
+#define I2C1                ((I2C_TypeDef *)I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *)I2C2_BASE)
+#define CAN1                ((CAN_TypeDef *)CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *)CAN2_BASE)
+#define DAC                 ((DAC_TypeDef *)DAC_BASE)
+#define LPUART              ((LPUART_TypeDef *)LPUART_BASE)
+#define COMP                ((COMP_TypeDef *)COMP_BASE)
+#define OPA                 ((OPA_TypeDef *)OPA_BASE)
+#define EXTI                ((EXTI_TypeDef *)EXTI_BASE)
+#define SCU                 ((SCU_TypeDef *)SCU_BASE)
+#define CRC                 ((CRC_TypeDef *)CRC_BASE)
+#define ADC                 ((ADC_TypeDef *)ADC_BASE)
+#define TIM1                ((TIM_TypeDef *)TIM1_BASE)
+#define I2S1                ((I2S_TypeDef *)I2S1_BASE)
+#define UART1               ((UART_TypeDef *)UART1_BASE)
+#define TIM15               ((TIM_TypeDef *)TIM15_BASE)
+#define TIM16               ((TIM_TypeDef *)TIM16_BASE) 
+#define TIM17               ((TIM_TypeDef *)TIM17_BASE)    
+#define GPIOAB              ((GPIO_TypeDef *)GPIOAB_BASE)
+#define GPIOCD              ((GPIO_TypeDef *)GPIOCD_BASE)
+#define GPIOEF              ((GPIO_TypeDef *)GPIOEF_BASE)
+#define SPI1                ((SPI_TypeDef *)SPI1_BASE)
+#define SPI2                ((SPI_TypeDef *)SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *)SPI3_BASE)
+#define SPI4                ((SPI_TypeDef *)SPI4_BASE)
+#define DMA                 ((DMA_TypeDef *)DMA_BASE)
+#define DMA_Channel0        ((DMA_Channel_TypeDef *)DMA_Channel0_BASE)
+#define DMA_Channel1        ((DMA_Channel_TypeDef *)DMA_Channel1_BASE)
+#define DMA_Channel2        ((DMA_Channel_TypeDef *)DMA_Channel2_BASE)
+#define DMA_Channel3        ((DMA_Channel_TypeDef *)DMA_Channel3_BASE)
+#define DMA_Channel4        ((DMA_Channel_TypeDef *)DMA_Channel4_BASE)
+#define DMA_Channel5        ((DMA_Channel_TypeDef *)DMA_Channel5_BASE)
+#define DMA_Channel6        ((DMA_Channel_TypeDef *)DMA_Channel6_BASE)
+#define DMA_Channel7        ((DMA_Channel_TypeDef *)DMA_Channel7_BASE)
+#define AES                 ((AES_TypeDef *)AES_BASE)
+#define FAU                 ((FAU_TypeDef *)FAU_BASE)
+#define HRNG                ((HRNG_TypeDef *)HRNG_BASE)
+#define HASH                ((HASH_TypeDef *)HASH_BASE)
+#define USBCTRL             ((USB_CTRLTypeDef *)USB_BASE)
+#define USBINT              ((USB_INTTypeDef *)(USB_BASE+0xFFE4))
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)            ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)          ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)           ((REG) & (BIT))
+
+#define CLEAR_REG(REG)               ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)          ((REG) = (VAL))
+
+#define READ_REG(REG)                ((REG))
+
+#define MODIFY_REG(REG,MASK,BITS)    ((REG) = (((REG)&(~(MASK)))|((BITS)&(MASK))))
+
+typedef   signed           char INT8;
+typedef   signed short     int  INT16;
+typedef   signed           int  INT32;
+
+    /* exact-width unsigned integer types */
+typedef unsigned           char UINT8;
+typedef unsigned short     int  UINT16;
+typedef unsigned           int  UINT32;  
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* ACM32F4_H */

bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4.s

@@ -0,0 +1,271 @@
+;* File Name          : Startup_ACM32F4.s
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F4 Devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* All rights reserved.
+;*******************************************************************************
+
+Stack_Size      EQU     0x00000800
+Heap_Size       EQU     0x00000000
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT __Vectors
+
+__Vectors       
+                DCD     __initial_sp                    ; Top of Stack
+                DCD     Reset_Handler                   ; Reset Handler
+                DCD     NMI_Handler                     ; NMI Handler
+                DCD     HardFault_Handler               ; Hard Fault Handler
+                DCD     MemManage_Handler               ; MPU Fault Handler
+                DCD     BusFault_Handler                ; Bus Fault Handler
+                DCD     UsageFault_Handler              ; Usage Fault Handler
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     0                               ; Reserved
+                DCD     SVC_Handler                     ; SVCall Handler
+                DCD     DebugMon_Handler                ; Debug Monitor Handler
+                DCD     0                               ; Reserved
+                DCD     PendSV_Handler                  ; PendSV Handler
+                DCD     SysTick_Handler                 ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WDT_IRQHandler                  ; 0:  WDT_IRQHandler
+                DCD     RTC_IRQHandler                  ; 1:  RTC_IRQHandler
+                DCD     EFC_IRQHandler                  ; 2:  EFC_IRQHandler
+                DCD     GPIOAB_IRQHandler               ; 3:  GPIOAB_IRQHandler
+                DCD     GPIOCD_IRQHandler               ; 4:  GPIOCD_IRQHandler
+                DCD     EXTI_IRQHandler                 ; 5:  EXTI_IRQHandler 
+                DCD     SRAM_PARITY_IRQHandler          ; 6:  SRAM_PARITY_IRQHandler
+                DCD     CLKRDY_IRQHandler               ; 7:  CLKRDY_IRQHandler
+                DCD     UART4_IRQHandler                ; 8:  UART4_IRQHandler
+                DCD     DMA_IRQHandler                  ; 9:  DMA_IRQHandler
+                DCD     UART3_IRQHandler                ; 10: UART3_IRQHandler
+                DCD     RSV_IRQHandler                  ; 11: RSV
+                DCD     ADC_IRQHandler                  ; 12: ADC_IRQHandler
+                DCD     TIM1_BRK_UP_TRG_COM_IRQHandler  ; 13: TIM1_BRK_UP_TRG_COM_IRQHandler
+                DCD     TIM1_CC_IRQHandler              ; 14: TIM1_CC_IRQHandler
+                DCD     TIM2_IRQHandler                 ; 15: TIM2_IRQHandler
+                DCD     TIM3_IRQHandler                 ; 16: TIM3_IRQHandler 
+                DCD     TIM6_IRQHandler                 ; 17: TIM6_IRQHandler
+                DCD     TIM7_IRQHandler                 ; 18: TIM7_IRQHandler
+                DCD     TIM14_IRQHandler                ; 19: TIM14_IRQHandler
+                DCD     TIM15_IRQHandler                ; 20: TIM15_IRQHandler
+                DCD     TIM16_IRQHandler                ; 21: TIM16_IRQHandler
+                DCD     TIM17_IRQHandler                ; 22: TIM17_IRQHandler
+                DCD     I2C1_IRQHandler                 ; 23: I2C1_IRQHandler
+                DCD     I2C2_IRQHandler                 ; 24: I2C2_IRQHandler
+                DCD     SPI1_IRQHandler                 ; 25: SPI1_IRQHandler
+                DCD     SPI2_IRQHandler                 ; 26: SPI2_IRQHandler
+                DCD     UART1_IRQHandler                ; 27: UART1_IRQHandler
+                DCD     UART2_IRQHandler                ; 28: UART2_IRQHandler
+                DCD     LPUART_IRQHandler               ; 29: LPUART_IRQHandler
+                DCD     SPI3_IRQHandler                 ; 30: SPI3_IRQHandler
+                DCD     AES_IRQHandler                  ; 31: AES_IRQHandler
+                DCD     USB_IRQHandler                  ; 32: USB_IRQHandler
+                DCD     DAC_IRQHandler                  ; 33: DAC_IRQHandler
+                DCD     I2S_IRQHandler                  ; 34: I2S_IRQHandler
+                DCD     GPIOEF_IRQHandler               ; 35: GPIOEF_IRQHandler
+                DCD     CAN1_IRQHandler                 ; 36: CAN1_IRQHandler
+                DCD     CAN2_IRQHandler                 ; 37: CAN2_IRQHandler
+                DCD     FPU_IRQHandler                  ; 38: FPU_IRQHandler
+                DCD     TIM4_IRQHandler                 ; 39: TIM4_IRQHandler 
+                DCD     SPI4_IRQHandler                 ; 40: SPI4_IRQHandler
+                AREA    |.text|, CODE, READONLY
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  System_Core_Config
+                IMPORT  __main
+                LDR     R0, =System_Core_Config
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+                EXPORT   WDT_IRQHandler                 [WEAK]
+                EXPORT   RTC_IRQHandler                 [WEAK]
+                EXPORT   EFC_IRQHandler                 [WEAK]
+                EXPORT   GPIOAB_IRQHandler              [WEAK]
+                EXPORT   GPIOCD_IRQHandler              [WEAK]
+                EXPORT   EXTI_IRQHandler                [WEAK]
+                EXPORT   SRAM_PARITY_IRQHandler         [WEAK]
+                EXPORT   CLKRDY_IRQHandler              [WEAK]
+                EXPORT   UART4_IRQHandler               [WEAK]
+                EXPORT   DMA_IRQHandler                 [WEAK]
+                EXPORT   UART3_IRQHandler               [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+                EXPORT   ADC_IRQHandler                 [WEAK]
+                EXPORT   TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
+                EXPORT   TIM1_CC_IRQHandler             [WEAK]
+                EXPORT   TIM2_IRQHandler                [WEAK]
+                EXPORT   TIM3_IRQHandler                [WEAK]
+                EXPORT   TIM6_IRQHandler                [WEAK]
+                EXPORT   TIM7_IRQHandler                [WEAK]
+                EXPORT   TIM14_IRQHandler               [WEAK]
+                EXPORT   TIM15_IRQHandler               [WEAK]
+                EXPORT   TIM16_IRQHandler               [WEAK]
+                EXPORT   TIM17_IRQHandler               [WEAK]
+                EXPORT   I2C1_IRQHandler                [WEAK]
+                EXPORT   I2C2_IRQHandler                [WEAK]
+                EXPORT   SPI1_IRQHandler                [WEAK]
+                EXPORT   SPI2_IRQHandler                [WEAK]
+                EXPORT   UART1_IRQHandler               [WEAK]
+                EXPORT   UART2_IRQHandler               [WEAK]
+                EXPORT   LPUART_IRQHandler              [WEAK]
+                EXPORT   SPI3_IRQHandler                [WEAK]
+                EXPORT   AES_IRQHandler                 [WEAK]
+                EXPORT   USB_IRQHandler                 [WEAK]
+                EXPORT   RSV_IRQHandler                 [WEAK]
+                EXPORT   DAC_IRQHandler                 [WEAK]
+                EXPORT   I2S_IRQHandler                 [WEAK]
+                EXPORT   GPIOEF_IRQHandler              [WEAK]
+                EXPORT   CAN1_IRQHandler                [WEAK]
+                EXPORT   CAN2_IRQHandler                [WEAK]
+                EXPORT   FPU_IRQHandler                 [WEAK]
+                EXPORT   TIM4_IRQHandler                [WEAK]
+                EXPORT   SPI4_IRQHandler                [WEAK]
+WDT_IRQHandler
+RTC_IRQHandler
+EFC_IRQHandler
+GPIOAB_IRQHandler
+GPIOCD_IRQHandler
+EXTI_IRQHandler
+SRAM_PARITY_IRQHandler
+CLKRDY_IRQHandler
+UART4_IRQHandler
+DMA_IRQHandler
+UART3_IRQHandler
+ADC_IRQHandler
+TIM1_BRK_UP_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM6_IRQHandler
+TIM7_IRQHandler
+TIM14_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+I2C1_IRQHandler
+I2C2_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+UART1_IRQHandler
+UART2_IRQHandler
+LPUART_IRQHandler
+SPI3_IRQHandler
+AES_IRQHandler
+USB_IRQHandler
+RSV_IRQHandler
+DAC_IRQHandler
+I2S_IRQHandler
+GPIOEF_IRQHandler
+CAN1_IRQHandler
+CAN2_IRQHandler
+FPU_IRQHandler
+TIM4_IRQHandler
+SPI4_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 
+                IF      :DEF:__MICROLIB
+                 
+                EXPORT  __initial_sp
+                EXPORT  __heap_base
+                EXPORT  __heap_limit
+                 
+                ELSE
+                 
+                IMPORT  __use_two_region_memory
+                EXPORT  __user_initial_stackheap
+__user_initial_stackheap
+                 
+                LDR     R0, =  Heap_Mem
+                LDR     R1, =(Stack_Mem + Stack_Size)
+                LDR     R2, = (Heap_Mem +  Heap_Size)
+                LDR     R3, = Stack_Mem
+                BX      LR
+
+                ALIGN
+
+                ENDIF
+
+                END

bsp/acm32f4xx-nucleo/libraries/Device/Startup_ACM32F4_iar.s

@@ -0,0 +1,362 @@
+;********************************************************************************
+;* File Name          : Startup_ACM32F4.s
+;* Description        : This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR
+;*                        address.
+;*                      - Branches to main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;*
+;* <h2><center>&copy; Copyright (c) 2021 Aisinochip.
+;* All rights reserved.</center></h2>
+;*
+;*******************************************************************************
+
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler              ; Reset Handler
+        DCD     NMI_Handler                ; NMI Handler
+        DCD     HardFault_Handler          ; Hard Fault Handler
+        DCD     MemManage_Handler          ; MPU Fault Handler
+        DCD     BusFault_Handler           ; Bus Fault Handler
+        DCD     UsageFault_Handler         ; Usage Fault Handler
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     0                          ; Reserved
+        DCD     SVC_Handler                ; SVCall Handler
+        DCD     DebugMon_Handler           ; Debug Monitor Handler
+        DCD     0                          ; Reserved
+        DCD     PendSV_Handler             ; PendSV Handler
+        DCD     SysTick_Handler            ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WDT_IRQHandler                    ; WDT_IRQHandle
+        DCD     RTC_IRQHandler                    ; RTC_IRQHandler
+        DCD     EFC_IRQHandler                    ; EFC_IRQHandler
+        DCD     GPIOAB_IRQHandler                 ; GPIOAB_IRQHandler
+        DCD     GPIOCD_IRQHandler                 ; GPIOCD_IRQHandler
+        DCD     EXTI_IRQHandler                   ; EXTI_IRQHandler
+        DCD     SRAM_PARITY_IRQHandler            ; SRAM_PARITY_IRQHandler
+        DCD     CLKRDY_IRQHandler                 ; CLKRDY_IRQHandler
+        DCD     UART4_IRQHandler                  ; UART4_IRQHandler
+        DCD     DMA_IRQHandler                    ; DMA_IRQHandler
+        DCD     UART3_IRQHandler                  ; UART3_IRQHandler
+        DCD     RSV_IRQHandler                    ; RSV_IRQHandler
+        DCD     ADC_IRQHandler                    ; ADC_IRQHandler
+        DCD     TIM1_BRK_UP_TRG_COM_IRQHandler    ; TIM1_BRK_UP_TRG_COM_IRQHandler
+        DCD     TIM1_CC_IRQHandler                ; TIM1_CC_IRQHandler
+        DCD     TIM2_IRQHandler                   ; TIM2_IRQHandler
+        DCD     TIM3_IRQHandler                   ; TIM3_IRQHandler
+        DCD     TIM6_IRQHandler                   ; TIM6_IRQHandler
+        DCD     TIM7_IRQHandler                   ; TIM7_IRQHandler
+        DCD     TIM14_IRQHandler                  ; TIM14_IRQHandler
+        DCD     TIM15_IRQHandler                  ; TIM15_IRQHandler
+        DCD     TIM16_IRQHandler                  ; TIM16_IRQHandler
+        DCD     TIM17_IRQHandler                  ; TIM17_IRQHandler
+        DCD     I2C1_IRQHandler                   ; I2C1_IRQHandler
+        DCD     I2C2_IRQHandler                   ; I2C2_IRQHandler
+        DCD     SPI1_IRQHandler                   ; SPI1_IRQHandler
+        DCD     SPI2_IRQHandler                   ; SPI2_IRQHandler
+        DCD     UART1_IRQHandler                  ; UART1_IRQHandler
+        DCD     UART2_IRQHandler                  ; UART2_IRQHandler
+        DCD     LPUART_IRQHandler                 ; LPUART_IRQHandler
+        DCD     SPI3_IRQHandler                   ; SPI3_IRQHandler
+        DCD     AES_IRQHandler                    ; AES_IRQHandler
+        DCD     USB_IRQHandler                    ; USB_IRQHandler
+        DCD     DAC_IRQHandler                    ; DAC_IRQHandler
+        DCD     I2S_IRQHandler                    ; I2S_IRQHandler
+        DCD     GPIOEF_IRQHandler                 ; GPIOEF_IRQHandler
+        DCD     CAN1_IRQHandler                   ; CAN1_IRQHandler
+        DCD     CAN2_IRQHandler                   ; CAN2_IRQHandler
+        DCD     FPU_IRQHandler                    ; FPU_IRQHandler
+        DCD     TIM4_IRQHandler                   ; TIM4_IRQHandler
+        DCD     SPI4_IRQHandler                   ; SPI4_IRQHandler
+__Vectors_End
+
+__Vectors       EQU   __vector_table
+__Vectors_Size  EQU   __Vectors_End - __Vectors
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WDT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WDT_IRQHandler
+        B WDT_IRQHandler
+
+        PUBWEAK RTC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_IRQHandler
+        B RTC_IRQHandler
+
+        PUBWEAK EFC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EFC_IRQHandler
+        B EFC_IRQHandler
+
+        PUBWEAK GPIOAB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOAB_IRQHandler
+        B GPIOAB_IRQHandler
+
+        PUBWEAK GPIOCD_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOCD_IRQHandler
+        B GPIOCD_IRQHandler
+
+        PUBWEAK EXTI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI_IRQHandler
+        B EXTI_IRQHandler
+
+        PUBWEAK SRAM_PARITY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SRAM_PARITY_IRQHandler
+        B SRAM_PARITY_IRQHandler
+
+        PUBWEAK CLKRDY_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CLKRDY_IRQHandler
+        B CLKRDY_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK DMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA_IRQHandler
+        B DMA_IRQHandler
+
+        PUBWEAK UART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART3_IRQHandler
+        B UART3_IRQHandler
+
+        PUBWEAK RSV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RSV_IRQHandler
+        B RSV_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_UP_TRG_COM_IRQHandler
+        B TIM1_BRK_UP_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_IRQHandler
+        B TIM6_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM14_IRQHandler
+        B TIM14_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK I2C1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_IRQHandler
+        B I2C1_IRQHandler
+
+        PUBWEAK I2C2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_IRQHandler
+        B I2C2_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK UART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART1_IRQHandler
+        B UART1_IRQHandler
+
+        PUBWEAK UART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART2_IRQHandler
+        B UART2_IRQHandler
+
+        PUBWEAK LPUART_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART_IRQHandler
+        B LPUART_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK AES_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+AES_IRQHandler
+        B AES_IRQHandler
+
+        PUBWEAK USB_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USB_IRQHandler
+        B USB_IRQHandler
+
+        PUBWEAK DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC_IRQHandler
+        B DAC_IRQHandler
+
+        PUBWEAK I2S_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2S_IRQHandler
+        B I2S_IRQHandler
+
+        PUBWEAK GPIOEF_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GPIOEF_IRQHandler
+        B GPIOEF_IRQHandler
+
+        PUBWEAK CAN1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN1_IRQHandler
+        B CAN1_IRQHandler
+
+        PUBWEAK CAN2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CAN2_IRQHandler
+        B CAN2_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+
+        END
+/************************ (C) COPYRIGHT Aisinochip *****END OF FILE****/

bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.c

@@ -0,0 +1,744 @@
+/*
+  ******************************************************************************
+  * @file    System_ACM32F4.c
+  * @version V1.0.0
+  * @date    2021 
+  * @brief   System Source File, includes clock management, reset management 
+  *          and IO configuration, ...   
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+uint32_t gu32_SystemClock;
+uint32_t gu32_APBClock;        
+
+/* System count in SysTick_Handler */
+volatile uint32_t gu32_SystemCount;
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x0U /*!< Vector Table base offset field.
+                                   This value must be a multiple of 0x200. */
+/******************************************************************************/
+
+/*********************************************************************************
+* Function    : HardFault_Handler
+* Description : Hard Fault handle, while(1) loop, wait for debug 
+* Input       : none 
+* Output      : none   
+* Author      : xwl                           
+**********************************************************************************/  
+//void HardFault_Handler(void)	//implemented in context_rvds.S
+//{
+//    while(1);   
+//} 
+
+/*********************************************************************************
+* Function    : SysTick_Handler
+* Description : System tick handler
+* Input       : none 
+* Output      : none 
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+//void SysTick_Handler(void)	//implemented in board.c
+//{
+//    gu32_SystemCount++;
+//}
+
+/*********************************************************************************
+* Function    : System_SysTick_Init
+* Description : System Tick Init. Period is 1 ms
+* Input       : none 
+* Output      : none 
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+//void System_SysTick_Init(void)	//implemented in board.c/rt_hw_board_init()
+//{
+//    gu32_SystemCount = 0;   
+//    SysTick_Config(gu32_SystemClock / 1000);  //1ms/tick  
+//}
+
+/*********************************************************************************
+* Function    : System_SysTick_Off
+* Description : Turn off System Tick  
+* Input       : none 
+* Output      : none 
+* Author      : xwl                         
+**********************************************************************************/
+//void System_SysTick_Off(void)  
+//{
+//    SysTick->CTRL = 0;   
+//}
+/*********************************************************************************
+* Function    : System_Init
+* Description : Initialize the system clock, accelerate function and system tick.   
+* Input       : none 
+* Output      : none 
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Init(void)
+{
+    SCU->RCR |= SCU_RCR_REMAP_EN;   // always remap enabled  
+    System_Set_Buzzer_Divider(80, FUNC_DISABLE); // disable clock out   
+    /* 3 bits for pre-emption priority, 0 bits for subpriority */ 
+    NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUP_3);    
+
+    /* Initialize the system clock */
+    if (false == System_Clock_Init(DEFAULT_SYSTEM_CLOCK))
+    {
+        while(1);  
+    }
+    
+#if (__ACCELERATE_PRESENT == 1)
+    System_EnableIAccelerate();
+#endif
+    
+#if (__ACCELERATE_EH_PRESENT == 1)   
+    System_EnableDAccelerate();
+#endif  
+
+#ifdef HAL_SYSTICK_ENABLED  // To activate macro in ACM32Fxx_HAL.h      
+    //System_SysTick_Init();
+#endif
+}
+
+/*********************************************************************************
+* Function    : System_Core_Config
+* Description : configure FPU and vector table address  
+* Input       : none  
+* Output      : none   
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Core_Config(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+    /* set CP10 and CP11 Full Access */
+    SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));
+#endif
+
+    /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;    /* Vector Table Relocation in Internal SRAM */
+#else
+    SCB->VTOR = EFLASH_BASE | VECT_TAB_OFFSET;  /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+
+/*********************************************************************************
+* Function    : System_Clock_Init
+* Description : Clock init
+* Input       : fu32_Clock: System core clock frequency, measured as Hz   
+* Output      : 0: success, other value: fail reason  
+* Author      : xwl                         
+**********************************************************************************/
+bool System_Clock_Init(uint32_t fu32_Clock)
+{
+    volatile uint32_t lu32_sysdiv, lu32_pclkdiv, lu32_timeout, lu32_pll_src, lu32_pclk_div_para, lu32_result;     
+          
+    SET_EFC_RD_WAIT(RD_WAIT_ENSURE_OK)    
+    lu32_result = 0;  
+    lu32_pll_src = PLL_SOURCE_FROM;   
+       
+    if(0 == (SCU->RCHCR & SCU_RCHCR_RCHRDY))  
+    {
+       SCU->RCHCR |=  SCU_RCHCR_RCH_EN;   
+       while(0 == (SCU->RCHCR & SCU_RCHCR_RCHRDY));  // wait RCH ready         
+    }
+    SCU->CCR1 = 0;  // select RC64M as default  
+
+    if (fu32_Clock <= 64000000)  
+    {
+        if ((SCU->RCHCR) & SCU_RCHCR_RCH_DIV)
+        {
+            SCU->RCHCR &= (~SCU_RCHCR_RCH_DIV);   
+            while(0 == (SCU->RCHCR & SCU_RCHCR_RCHRDY));    
+        }
+        
+        if (fu32_Clock == 32000000)
+        {
+            gu32_SystemClock = fu32_Clock;
+            lu32_sysdiv = 2;  
+            lu32_pclkdiv = 1;  // pclk = hclk 
+        }
+        else
+        {
+            gu32_SystemClock = 64000000;
+            lu32_sysdiv = 1;  
+            lu32_pclkdiv = 1;   
+        }
+              
+        gu32_APBClock = gu32_SystemClock/lu32_pclkdiv;     
+    }
+    // select pll as system clock 
+    else
+    {
+        if (PLLCLK_SRC_RC4M == lu32_pll_src)
+        {
+            SCU->RCHCR |= SCU_RCHCR_RCH_DIV;   
+            while(!(SCU->RCHCR & SCU_RCHCR_RCHRDY));
+
+            SCU->PLLCR |=  SCU_PLLCR_PLL_EN;
+            SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP);
+            while(!(SCU->PLLCR & SCU_PLLCR_PLL_FREE_RUN));
+
+            switch(fu32_Clock)
+            {
+                case 180000000:  // 180M 
+                {
+                    SCU->PLLCR  = (SCU->PLLCR & ~(0xFFFF8)) | (33 << 3);
+                    SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN;  
+                    while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) );       
+
+                    lu32_sysdiv = 1;  
+                    lu32_pclkdiv = 2; // pclk = hclk/2 
+                }break;
+
+                case 120000000:  // 120M
+                {
+                    SCU->PLLCR  = (SCU->PLLCR & ~(0xFFFF8)) | (18U << 3);      
+                    SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN;  
+                    while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) );    
+
+                    lu32_sysdiv = 1;  
+                    lu32_pclkdiv = 2; // pclk = hclk/2
+                }break;
+                
+                default: lu32_result = 1; break; 
+            }
+            gu32_SystemClock = fu32_Clock;  
+            gu32_APBClock = gu32_SystemClock/lu32_pclkdiv;        
+            SCU->CCR1 = SCU_CCR1_SYS_PLL;  // configure system clock as PLL clock     
+        }
+        else if (SCU_XTHCR_XTH_EN == lu32_pll_src)   
+        {
+            lu32_timeout = 0;  
+        
+            SCU->XTHCR = SCU_XTHCR_XTH_EN | SCU_XTHCR_READYTIME_32768;
+            while (0 == (SCU->XTHCR & SCU_XTHCR_XTHRDY))
+            {     
+                if (lu32_timeout == SYSTEM_TIMEOUT)
+                {
+                    lu32_result = 2;  
+                    break;     
+                }  
+                lu32_timeout++;    
+            } 
+            
+            if  (0 == lu32_result)
+            {
+                SCU->PLLCR |=  SCU_PLLCR_PLL_EN;  
+                SCU->PLLCR &= ~(SCU_PLLCR_PLL_SLEEP);   
+                while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ));     
+            
+                switch(fu32_Clock) 
+                {
+                    case 180000000:  // 180M 
+                    {
+                        SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (1U << 12) | (0U << 16);   
+                        SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1);   
+                        SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN;   
+                        while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) );     
+                   
+                        lu32_sysdiv = 1;  
+                        lu32_pclkdiv = 2; // pclk = hclk/2  
+                    }break;
+
+                    case 120000000:  // 120M 
+                    {
+                        SCU->PLLCR = (SCU->PLLCR &(~(0x1FFFFU << 3))) | (18U << 3) | (2U << 12) | (0U << 16);   
+                        SCU->PLLCR = (SCU->PLLCR & (~(0x3U << 1)) ) | (3 << 1); // select XTH  
+                        SCU->PLLCR |= SCU_PLLCR_PLL_UPDATE_EN;   
+                        while(!(SCU->PLLCR & (SCU_PLLCR_PLL_FREE_RUN) ) );     
+                   
+                        lu32_sysdiv = 1;  
+                        lu32_pclkdiv = 2; // pclk = hclk/2  
+                    }break;
+               
+                    default: lu32_result = 1; break;  
+                }
+            }
+            gu32_SystemClock = fu32_Clock;  
+            gu32_APBClock = gu32_SystemClock/lu32_pclkdiv;        
+            SCU->CCR1 = SCU_CCR1_SYS_PLL;  // configure system clock as PLL clock   
+        }  
+        else
+        {
+            lu32_result = 3;    
+        }
+    }
+    
+    if (0 == lu32_result)
+    {
+        if (1 == lu32_pclkdiv)
+        {
+            lu32_pclk_div_para = 0;    
+        }
+        else if (2 == lu32_pclkdiv)
+        {
+            lu32_pclk_div_para = 4;    // pclk = hclk/2   
+        } 
+        else
+        {
+            lu32_pclk_div_para = 5;    // pclk = hclk/4       
+        }
+    }
+    else
+    {
+        lu32_sysdiv = 1;   
+        lu32_pclk_div_para = 0;  
+    }
+  
+    SCU->CCR2 = (SCU->CCR2 & (~0x7FFU)) | (lu32_sysdiv-1) | (lu32_pclk_div_para << 8);   
+    while((SCU->CCR2 & SCU_CCR2_DIVDONE) == 0x00);  // wait divide done   
+
+    HAL_EFlash_Init(gu32_SystemClock);    
+    
+    return (lu32_result == 0);    
+}
+
+/*********************************************************************************
+* Function    : System_Get_SystemClock
+* Description : get AHB clock frequency   
+* Input       : none 
+* Output      : frequency, measured as Hz    
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+uint32_t System_Get_SystemClock(void)
+{
+    return gu32_SystemClock;
+}
+
+/*********************************************************************************
+* Function    : System_Get_APBClock
+* Description : get APB clock frequency   
+* Input       : none 
+* Output      : frequency, measured as Hz  
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+uint32_t System_Get_APBClock(void)
+{
+    return gu32_APBClock;
+}
+
+/*********************************************************************************
+* Function    : System_Module_Reset
+* Description : reset module 
+* Input       : module id 
+* Output      : none 
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Module_Reset(enum_RST_ID_t fe_ID_Index)
+{
+    if (fe_ID_Index > 31) 
+    {
+        SCU->IPRST2 &= ~(1 << (fe_ID_Index - 32));         
+        System_Delay(5);
+        SCU->IPRST2 |= 1 << (fe_ID_Index - 32);   
+    }
+    else 
+    {
+        SCU->IPRST1 &= ~(1 << fe_ID_Index);       
+        System_Delay(5);  
+        SCU->IPRST1 |= 1 << fe_ID_Index;       
+    }
+}
+
+/*********************************************************************************
+* Function    : System_Module_Enable
+* Description : enable module clock  
+* Input       : module id     
+* Output      : none 
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Module_Enable(enum_Enable_ID_t fe_ID_Index)
+{
+    if (fe_ID_Index > 13) 
+    {
+        SCU->IPCKENR1 |= 1 << (fe_ID_Index - 14);
+    }
+    else 
+    {
+        SCU->IPCKENR2 |= 1 << fe_ID_Index;
+    }
+    
+    System_Delay(2);   
+}
+
+/*********************************************************************************
+* Function    : System_Module_Disable
+* Description : disable module clock 
+* Input       : module id  
+* Output      : none 
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Module_Disable(enum_Enable_ID_t fe_ID_Index)
+{
+    if (fe_ID_Index > 13) 
+    {
+        SCU->IPCKENR1 &= ~(1 << (fe_ID_Index - 14));
+    }
+    else 
+    {
+        SCU->IPCKENR2 &= ~(1 << fe_ID_Index);
+    }
+}
+
+/*********************************************************************************
+* Function    : System_Delay
+* Description : NOP delay
+* Input       : count 
+* Output      : none  
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Delay(volatile uint32_t fu32_Delay)
+{
+    while (fu32_Delay--);
+}
+
+/*********************************************************************************
+* Function    : System_Delay_MS
+* Description : ms delay. Use this Function must call System_SysTick_Init()
+* Input       : delay period, measured as ms  
+* Output      : none  
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+void System_Delay_MS(volatile uint32_t fu32_Delay)
+{
+    uint32_t lu32_SystemCountBackup;
+    
+    lu32_SystemCountBackup = gu32_SystemCount;
+    
+    while ( (gu32_SystemCount - lu32_SystemCountBackup) < fu32_Delay);  
+}
+
+/*********************************************************************************
+* Function    : System_Enable_RC32K
+* Description : Enable RC32K, make sure RTC Domain Access is allowed    
+* Input       : none 
+* Output      : none 
+* Author      : CWT                         
+**********************************************************************************/
+void System_Enable_RC32K(void)
+{
+    PMU->ANACR |= (1 << 8); 
+    while(0 == ((PMU->ANACR) & (1U << 9)));
+}
+
+/*********************************************************************************
+* Function    : System_Disable_RC32K
+* Description : Disable RC32K
+* Input       : none  
+* Output      : none 
+* Author      : CWT                        
+**********************************************************************************/
+void System_Disable_RC32K(void)
+{
+    PMU->ANACR &= (~(1 << 8));
+}
+
+/*********************************************************************************
+* Function    : System_Enable_XTAL
+* Description : Enable XTAL, make sure RTC Domain Access is allowed 
+* Input       : none 
+* Output      : none  
+* Author      : CWT                         
+**********************************************************************************/
+void System_Enable_XTAL(void)
+{
+    PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0);
+    PMU->ANACR |= RPMU_ANACR_XTLEN;
+    while(!(PMU->ANACR & RPMU_ANACR_XTLRDY));
+    PMU->CR1 |= RTC_CLOCK_XTL;
+}
+
+/*********************************************************************************
+* Function    : System_Disable_XTAL
+* Description : Disable XTAL
+* Input       : none 
+* Output      : none 
+* Author      : CWT                       
+**********************************************************************************/
+void System_Disable_XTAL(void)
+{
+    PMU->ANACR &= (~(RPMU_ANACR_XTLEN));   
+}
+
+/*********************************************************************************
+* Function    : System_Enable_Disable_RTC_Domain_Access
+* Description : Enable or Disable  RTC Domain Access.
+* Input       : enable or  disable  
+* Output      : none   
+* Author      : CWT                         
+**********************************************************************************/
+void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable)  
+{
+    if (FUNC_DISABLE == enable_disable)
+    {
+        SCU->STOPCFG &= (~SCU_STOPCFG_RTC_WE);
+    }
+    else
+    {
+        SCU->STOPCFG |= SCU_STOPCFG_RTC_WE;  
+        System_Delay(1);     
+        RTC->WP = 0xCA53CA53U;  
+    }
+}
+
+/*********************************************************************************
+* Function    : System_Enable_Disable_Reset
+* Description : Enable or Disable  System Reset source.
+* Input       : none 
+* Output      : none 
+* Author      : CWT                         
+**********************************************************************************/
+void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable)  
+{
+    switch(source)
+    {
+        /* reset source: from bit0 to bit3  */  
+        case RESET_ENABLE_SOURCE_LVD:
+        case RESET_ENABLE_SOURCE_WDT:
+        case RESET_ENABLE_SOURCE_IWDT:
+        case RESET_ENABLE_SOURCE_LOCKUP:   
+
+        if (FUNC_DISABLE == enable_disable)
+        {
+            SCU->RCR &= (~(1U << source));  
+        }
+        else
+        {
+            SCU->RCR |= (1U << source);    
+        }	
+        break; 
+
+        default: break;  
+    }
+}
+
+/*********************************************************************************
+* Function    : System_Reset_MCU
+* Description : reset mcu  
+* Input       : reset source  
+* Output      : none 
+* Author      : xwl                          
+**********************************************************************************/
+void System_Reset_MCU(RESET_SOURCE source)  
+{
+    switch(source)
+    {
+        case RESET_SOURCE_EFC:
+        {
+            SCU->RCR &= (~BIT29);     
+            while(1);
+        }break;
+        
+        case RESET_SOURCE_NVIC_RESET:
+        {
+            NVIC_SystemReset();
+            while(1);  
+        }break;
+        
+        case RESET_SOFT_RESET:
+        {
+            SCU->RCR &= (~BIT30);               
+            while(1);
+        }break;
+
+        default: break;
+    }
+}
+
+/*********************************************************************************
+* Function    : System_Enter_Standby_Mode   
+* Description : try to enter standby mode
+* Input       : none         
+* Output      : none
+* Author      : xwl                         Date : 2021  
+**********************************************************************************/
+void System_Enter_Standby_Mode(void)
+{
+    __set_PRIMASK(1);    // disable interrupt 
+    SysTick->CTRL = 0;   // disable systick   
+    SCU->STOPCFG |= BIT11;  // set PDDS=1  
+    
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 
+    __WFI();     
+    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));      
+    System_Delay(100);  
+    
+    printfS("Enter Standby Mode Failed! \n");   // should not go here   
+}
+
+/*********************************************************************************
+* Function    : System_Clear_Stop_Wakeup
+* Description : clear all stop setting and status 
+* Input       : none
+* Output      : none 
+* Author      : CWT                         Date : 2021?¨º
+**********************************************************************************/
+void System_Clear_Stop_Wakeup(void) 
+{
+    EXTI->IENR = 0;  
+    EXTI->RTENR = 0;  
+    EXTI->FTENR = 0;  
+    EXTI->SWIER = 0;  
+    EXTI->PDR = 0x7FFFFFU;
+}
+
+/*********************************************************************************
+* Function    : System_Enter_Stop_Mode
+* Description : try to enter stop mode
+* Input       : STOPEntry: STOPENTRY_WFI or STOPENTRY_WFE             
+* Output      : none  
+* Author      : CWT                         Date : 2021  
+**********************************************************************************/
+void System_Enter_Stop_Mode(uint8_t STOPEntry)
+{
+    /* Set SLEEPDEEP bit of Cortex System Control Register */
+    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 
+    
+    SCU->STOPCFG &= (~BIT11);  // PDDS=0     
+    
+    //System_SysTick_Off();  
+    /* Select Stop mode entry */
+    if(STOPEntry == STOPENTRY_WFI)
+    {
+        /* Wait For Interrupt */   
+        __WFI();
+    }
+    else
+    {
+        __SEV();   
+        __WFE();
+        __WFE();    /* Wait For Event */  
+    }
+    
+    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));  
+    
+#ifdef HAL_SYSTICK_ENABLED  // To activate macro in ACM32Fxx_HAL.h      
+    //System_SysTick_Init();
+#endif  
+}
+
+/*********************************************************************************
+* Function    : System_Enter_Sleep_Mode
+* Description : try to enter sleep mode
+* Input       : SleepEntry: SLEEPENTRY_WFI or SLEEPENTRY_WFE                     
+* Output      : none  
+* Author      : CWT                         Date : 2021  
+**********************************************************************************/
+void System_Enter_Sleep_Mode(uint8_t SleepEntry)
+{
+    /* clear SLEEPDEEP bit of Cortex System Control Register */
+    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));         
+
+    /* Select Stop mode entry */
+    if(SleepEntry == SLEEPENTRY_WFI)       
+    {
+        /* Wait For Interrupt */
+        __WFI();
+    }
+    else
+    {
+        
+        __SEV();      
+        __WFE();
+        __WFE(); /*Wait For Event */     
+    }
+        
+}
+
+
+ /*********************************************************************************
+* Function    : System_Return_Last_Reset_Reason
+* Description : Get System Last Reset Reason
+* Input       : none 
+* Output      : RESET_REASON
+* Author      : CWT                         Date : 2021?¨º
+**********************************************************************************/
+RESET_REASON System_Return_Last_Reset_Reason(void)
+{
+    RESET_REASON Reset_Reason_Save;   
+    RESET_REASON i = RESET_REASON_POR;    
+    
+    for(i = RESET_REASON_POR; i >= RESET_REASON_POR12; i--)       
+    {
+        if ((SCU->RSR) & (1U << i))  
+        {
+            SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags  
+            Reset_Reason_Save = i;  
+            return i;  
+        }
+    } 
+    
+    for(i = RESET_REASON_LOW_VOLTAGE; i <= RESET_REASON_SOFT; i++)    
+    {
+        if ((SCU->RSR) & (1U << i))    
+        {
+            SCU->RSR |= SCU_RSR_RSTFLAG_CLR; // clear reset reason flags  
+            Reset_Reason_Save = i;  
+            return i;  
+        }
+    }  
+
+    return RESET_REASON_INVALID;  // this should not happen 
+}
+
+ /*********************************************************************************
+* Function    : System_Set_Buzzer_Divider
+* Description : set buzzer divide factor 
+* Input       : 
+              div: div factor, if div = 80 then output buzzer freq=HCLK/80   
+              enable: FUNC_DISABLE and FUNC_ENABLE      
+* Output      : none
+* Author      : xwl                         Date : 2021?¡§o
+**********************************************************************************/
+void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable)  
+{      
+    if (FUNC_ENABLE == enable)
+    {
+        SCU->CLKOCR = (SCU->CLKOCR & (~(0x1FFFFU << 5) ) ) | (div << 5);      
+        SCU->CLKOCR |= BIT23;  
+    }
+    else
+    {
+        SCU->CLKOCR &= (~BIT23);   
+    }
+}
+
+/*********************************************************************************
+* Function    : System_USB_PHY_Config
+* Description : Configure USB PHY, such as clock select, pll...
+* Input       : none  
+* Output      : 0: fail, 1:success 
+* Author      : xwl                         Date : 2021?¨º
+**********************************************************************************/
+uint32_t System_USB_PHY_Config(void) 
+{
+    volatile uint32_t delay_count; 
+       
+    SCU->PHYCR &= (~BIT2); // exit power down, auto select clock source 
+    
+    delay_count = SYSTEM_TIMEOUT;  
+    while(delay_count--)
+    {
+        if (SCU->PHYCR & (BIT19)) // clksel_end flag = 1  
+        {
+            break;  
+        }
+    }  
+
+    if (delay_count) 
+    {
+        return HAL_OK;   
+    }
+    else
+    {
+        return HAL_TIMEOUT;     
+    }
+}
+

bsp/acm32f4xx-nucleo/libraries/Device/System_ACM32F4.h

@@ -0,0 +1,671 @@
+/*
+  ******************************************************************************
+  * @file    System_ACM32F4.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   CMSIS Cortex-M33 Device Peripheral Access Layer System Headler File.
+  ******************************************************************************
+*/
+#ifndef __SYSTEM_ACM32F4_H__
+#define __SYSTEM_ACM32F4_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/* ================================================================================ */
+/* =======================     Use Uart to Debug print     ======================== */
+/* ================================================================================ */
+#define UART_DEBUG_ENABLE
+
+#ifdef UART_DEBUG_ENABLE
+    #define printfS    printf
+#else
+    #define printfS(format, ...)    ((void)0)
+#endif
+/* ================================================================================ */
+
+#define PLLCLK_SRC_RC4M                      (0x00)   
+#define PLLCLK_SRC_XTH                       (0x01)  
+
+#define DEFAULT_SYSTEM_CLOCK    (180000000)    // system clock frequency, 32M/64M/120M/180M
+#define PLL_SOURCE_FROM         (PLLCLK_SRC_RC4M) 
+
+/* CLK source Index */
+#define SYS_CLK_SRC_RCH                      (0x00)    // CLK source from RC64M
+#define SYS_CLK_SRC_RC32K                    (0x01)    // CLK source from RC32K
+#define SYS_CLK_SRC_XTH                      (0x02)    // CLK source from XTH
+#define SYS_CLK_SRC_XTL                      (0x03)    // CLK source from XTL
+#define SYS_CLK_SRC_PLLCLK                   (0x04)    // CLK source from PLLCLK 
+
+/* APB Frequencey Division */
+#define APB_CLK_DIV_0                        (0 << 8)
+#define APB_CLK_DIV_2                        (4 << 8)
+#define APB_CLK_DIV_4                        (5 << 8)
+#define APB_CLK_DIV_8                        (6 << 8)
+#define APB_CLK_DIV_16                       (7 << 8)
+
+/* STOP WAKEUP Sorce */
+#define STOP_WAKEUP_GPIO_PIN0         BIT0
+#define STOP_WAKEUP_GPIO_PIN1         BIT1
+#define STOP_WAKEUP_GPIO_PIN2         BIT2
+#define STOP_WAKEUP_GPIO_PIN3         BIT3
+#define STOP_WAKEUP_GPIO_PIN4         BIT4
+#define STOP_WAKEUP_GPIO_PIN5         BIT5
+#define STOP_WAKEUP_GPIO_PIN6         BIT6
+#define STOP_WAKEUP_GPIO_PIN7         BIT7
+#define STOP_WAKEUP_GPIO_PIN8         BIT8
+#define STOP_WAKEUP_GPIO_PIN9         BIT9
+#define STOP_WAKEUP_GPIO_PIN10        BIT10
+#define STOP_WAKEUP_GPIO_PIN11        BIT11
+#define STOP_WAKEUP_GPIO_PIN12        BIT12
+#define STOP_WAKEUP_GPIO_PIN13        BIT13
+#define STOP_WAKEUP_GPIO_PIN14        BIT14   
+#define STOP_WAKEUP_GPIO_PIN15        BIT15 
+#define STOP_WAKEUP_PERIPHERAL_LVD    BIT16
+#define STOP_WAKEUP_PERIPHERAL_RTC    BIT17
+#define STOP_WAKEUP_PERIPHERAL_LPUART BIT18
+#define STOP_WAKEUP_PERIPHERAL_IWDT   BIT19    
+#define STOP_WAKEUP_PERIPHERAL_COMP1  BIT20
+#define STOP_WAKEUP_PERIPHERAL_COMP2  BIT21 
+#define STOP_WAKEUP_RESERVE           BIT22   
+#define STOP_WAKEUP_PERIPHERAL_USB    BIT23     
+#define STOP_WAKEUP_ALL               (0xFFFFFFU)   
+
+#define STANDBY_WAKEUP_PINS        6              
+#define STANDBY_WAKEUP_SOURCE_IO1  BIT0   
+#define STANDBY_WAKEUP_SOURCE_IO2  BIT1  
+#define STANDBY_WAKEUP_SOURCE_IO3  BIT2   
+#define STANDBY_WAKEUP_SOURCE_IO4  BIT3  
+#define STANDBY_WAKEUP_SOURCE_IO5  BIT4   
+#define STANDBY_WAKEUP_SOURCE_IO6  BIT5 
+#define STANDBY_WAKEUP_SOURCE_RTC  BIT6    
+#define STANDBY_WAKEUP_SOURCE_ALL  0x7FU    
+
+// sleep/low power mode definition  
+#define STOPENTRY_WFI   0  
+#define STOPENTRY_WFE   1 
+
+#define SLEEPENTRY_WFI  0  
+#define SLEEPENTRY_WFE  1  
+/*
+ * @brief  STOP WAKEUP EDGE structures definition
+ */
+typedef enum  
+{
+    WAKEUP_RISING = 0,
+    WAKEUP_FALLING = 1,
+    WAKEUP_RISING_FALLING = 2, // 0:rising, 1:falling, 2: rising and falling   
+}STOP_WAKEUP_EDGE;    
+
+typedef enum
+{
+    FUNC_DISABLE = 0x00U,
+    FUNC_ENABLE  = 0x01U,  
+}FUNC_DISABLE_ENABLE;    
+
+typedef enum
+{
+    RESET_ENABLE_SOURCE_LVD   = 0x00U,
+	RESET_ENABLE_SOURCE_WDT   = 0x01U,  
+	RESET_ENABLE_SOURCE_IWDT  = 0x02U,  
+	RESET_ENABLE_SOURCE_LOCKUP  = 0x03U,          
+}RESET_ENABLE_SOURCE;   
+
+typedef enum
+{
+    RESET_SOURCE_EFC   = 0x00U,
+	RESET_SOURCE_NVIC_RESET  = 0x01U,  
+	RESET_SOFT_RESET  = 0x02U,             
+}RESET_SOURCE; 
+
+/*
+ * @brief  Peripheral Reset structures definition
+ */
+typedef enum
+{
+    RST_SPI4   = 38,
+    RST_GPIOEF = 37,
+    RST_SPI3   = 36,
+    RST_UART4  = 35,
+    RST_TIM4   = 34,
+    RST_CAN2   = 33,
+    RST_I2S1   = 32,
+    
+    RST_CAN1   = 31,
+    RST_TIM2   = 30,
+    RST_USB    = 29,
+    RST_UAC    = 28,
+    RST_TIM17  = 27,
+    RST_TIM16  = 26,
+    RST_TIM15  = 25,
+    RST_TIM14  = 24,
+    RST_TIM7   = 23,
+    RST_TIM6   = 22,
+    RST_TIM3   = 21,
+    RST_TIM1   = 20,
+    RST_UART3  = 19,
+    RST_EXTI   = 18,
+    RST_OPA    = 17,
+    RST_COMP   = 16,
+    RST_TKEY   = 15,
+    RST_ADC    = 14,
+    RST_DAC    = 13,
+    RST_DMA    = 12,
+    RST_CRC    = 11,
+    RST_IWDT   = 10,
+    RST_WDT    = 9,
+    RST_LPUART = 8,
+    RST_I2C2   = 7,
+    RST_I2C1   = 6,
+    RST_SPI2   = 5,
+    RST_SPI1   = 4,
+    RST_UART2  = 3,
+    RST_UART1  = 2,
+    RST_GPIOCD = 1,
+    RST_GPIOAB = 0,
+}enum_RST_ID_t;
+
+/****************  Bit definition for SCU RCR register  ***********************/
+#define SCU_RCR_SOFT_RST                    BIT30
+#define SCU_RCR_EFC_RST                     BIT29
+#define SCU_RCR_REMAP_EN                    BIT16
+#define SCU_RCR_LOCKRST_EN                  BIT3
+#define SCU_RCR_IWDTRST_EN                  BIT2
+#define SCU_RCR_WDTRST_EN                   BIT1
+#define SCU_RCR_LVDRST_EN                   BIT0
+	
+/****************  Bit definition for SCU RSR register  ***********************/	
+#define SCU_RSR_RSTFLAG_CLR                 BIT16
+#define SCU_RSR_PWRRST_F                    BIT10
+#define SCU_RSR_POR12RST_F                  BIT9
+#define SCU_RSR_SRST_F                      BIT8
+#define SCU_RSR_SRSTNM_F                    BIT7
+#define SCU_RSR_EFC_RST_F                   BIT6
+#define SCU_RSR_RSTN_F                      BIT5
+#define SCU_RSR_SYSREQRST_F                 BIT4
+#define SCU_RSR_LOCKRST_F                   BIT3
+#define SCU_RSR_IWDTRST_F                   BIT2
+#define SCU_RSR_WDTRST_F                    BIT1
+#define SCU_RSR_VDLRST_F                    BIT0
+
+/****************  Bit definition for SCU IPRST register  **********************/
+#define SCU_IPRST_UACRST                    BIT28
+#define SCU_IPRST_TIM17RST                  BIT27
+#define SCU_IPRST_TIM16RST                  BIT26
+#define SCU_IPRST_TIM15RST                  BIT25
+#define SCU_IPRST_TIM14RST                  BIT24
+#define SCU_IPRST_TIM6RST                   BIT22
+#define SCU_IPRST_TIM3RST                   BIT21
+#define SCU_IPRST_TIM1RST                   BIT20
+#define SCU_IPRST_UART3RST                  BIT19
+#define SCU_IPRST_EXTIRST                   BIT18
+#define SCU_IPRST_OPARST                    BIT17
+#define SCU_IPRST_CMPRST                    BIT16
+#define SCU_IPRST_TKEYRST                   BIT15
+#define SCU_IPRST_ADCRST                    BIT14
+#define SCU_IPRST_DMACRST                   BIT12
+#define SCU_IPRST_CRCRST                    BIT11
+#define SCU_IPRST_IWDTRST                   BIT10
+#define SCU_IPRST_WDTRST                    BIT9
+#define SCU_IPRST_LPUART                    BIT8
+#define SCU_IPRST_I2C2RST                   BIT7
+#define SCU_IPRST_I2C1RST                   BIT6
+#define SCU_IPRST_SPI2RST                   BIT5
+#define SCU_IPRST_SPI1RST                   BIT4
+#define SCU_IPRST_UART2RST                  BIT3
+#define SCU_IPRST_UART1RST                  BIT2
+#define SCU_IPRST_GPIO2RST                  BIT1
+#define SCU_IPRST_GPIO1RST                  BIT0
+
+/****************  Bit definition for SCU CCR1 register  ***********************/
+#define SCU_CCR1_SYS_CLK_SEL               (BIT2|BIT1|BIT0)
+#define SCU_CCR1_SYS_PLL                   (BIT2)
+
+/****************  Bit definition for SCU CCR2 register  ***********************/
+#define SCU_CCR2_DIVDONE                    BIT31
+#define SCU_CCR2_TKSCLK_SEL                 BIT16
+#define SCU_CCR2_FLTCLK_SEL                 BIT15
+#define SCU_CCR2_LPUCLK_SEL                (BIT14|BIT13)
+#define SCU_CCR2_LPUARTDIV                 (BIT12|BIT11)
+#define SCU_CCR2_PCLKDIV                   (BIT10|BIT9|BIT8)
+#define SCU_CCR2_SYSDIV1                   (BIT7|BIT6|BIT5|BIT4)
+#define SCU_CCR2_SYSDIV0                   (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU CIR register  ***********************/
+#define SCU_CIR_RC4MRDYIC                   BIT21
+#define SCU_CIR_PLLLOCKIC                   BIT20
+#define SCU_CIR_XTHRDYIC                    BIT19
+#define SCU_CIR_RCHRDYIC                    BIT18
+#define SCU_CIR_XTLRDYIC                    BIT17
+#define SCU_CIR_RC32KRDYIC                  BIT16
+#define SCU_CIR_RC4MRDYIE                   BIT13
+#define SCU_CIR_PLLLOCKIE                   BIT12
+#define SCU_CIR_XTHRDYIE                    BIT11
+#define SCU_CIR_RCHRDYIE                    BIT10
+#define SCU_CIR_XTLRDYIE                    BIT9
+#define SCU_CIR_RC32KRDYIE                  BIT8
+#define SCU_CIR_RC4MRDYIF                   BIT5
+#define SCU_CIR_PLLLOCKIF                   BIT4
+#define SCU_CIR_XTHRDYIF                    BIT3
+#define SCU_CIR_RCHRDYIF                    BIT2
+#define SCU_CIR_XTLRDYIF                    BIT1
+#define SCU_CIR_RC32KRDYIF                  BIT0
+
+/****************  Bit definition for SCU IPCKENR register  ********************/
+#define SCU_IPCKENR_ROMCLKEN                BIT30
+#define SCU_IPCKENR_HRNGCLKEN               BIT29
+#define SCU_IPCKENR_AESCLKEN                BIT28
+#define SCU_IPCKENR_TIM17CLKEN              BIT27
+#define SCU_IPCKENR_TIM16CLKEN              BIT26
+#define SCU_IPCKENR_TIM15CLKEN              BIT25
+#define SCU_IPCKENR_TIM14CLKEN              BIT24
+#define SCU_IPCKENR_TIM6CLKEN               BIT22
+#define SCU_IPCKENR_TIM3CLKEN               BIT21
+#define SCU_IPCKENR_TIM1CLKEN               BIT20
+#define SCU_IPCKENR_UART3CLKEN              BIT19
+#define SCU_IPCKENR_OPACLKEN                BIT17
+#define SCU_IPCKENR_CMPCLKEN                BIT16
+#define SCU_IPCKENR_TKEYCLKEN               BIT15
+#define SCU_IPCKENR_ADCCLKEN                BIT14
+#define SCU_IPCKENR_RTCCLKEN                BIT13
+#define SCU_IPCKENR_DMACCLKEN               BIT12
+#define SCU_IPCKENR_CRCCLKEN                BIT11
+#define SCU_IPCKENR_LPUARTCLKEN             BIT8
+#define SCU_IPCKENR_I2C2CLKEN               BIT7
+#define SCU_IPCKENR_I2C1CLKEN               BIT6
+#define SCU_IPCKENR_SPI2CLKEN               BIT5
+#define SCU_IPCKENR_SPI1CLKEN               BIT4
+#define SCU_IPCKENR_UART2CLKEN              BIT3
+#define SCU_IPCKENR_UART1CLKEN              BIT2
+
+/****************  Bit definition for SCU IPCKENR2 register  ********************/
+#define SCU_IPCKENR2_EFCCLKEN               BIT6
+#define SCU_IPCKENR2_SRAMCLKEN              BIT5
+#define SCU_IPCKENR2_EXTICLKEN              BIT4
+#define SCU_IPCKENR2_IWDTCLKEN              BIT3
+#define SCU_IPCKENR2_WDTCLKEN               BIT2
+#define SCU_IPCKENR2_GPIO2CLKEN             BIT1
+#define SCU_IPCKENR2_GPIO1CLKEN             BIT0
+
+/****************  Bit definition for SCU RCHCR register  **********************/
+#define SCU_RCHCR_RC4MRDY                   BIT22
+#define SCU_RCHCR_RC4M_TRIM                (BIT21|BIT20|BIT19|BIT18|BIT17)
+#define SCU_RCHCR_RC4M_EN                   BIT16
+#define SCU_RCHCR_RCHRDY                    BIT9
+#define SCU_RCHCR_RCH_DIV                   BIT8
+#define SCU_RCHCR_RCH_TRIM                 (BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1)
+#define SCU_RCHCR_RCH_EN                    BIT0
+
+/****************  Bit definition for SCU RCHCR register  **********************/
+#define SCU_XTHCR_XTHRDY                    BIT4
+#define SCU_XTHCR_XTH_RDYTIME              (BIT3|BIT2)
+#define SCU_XTHCR_XTH_BYP                   BIT1
+#define SCU_XTHCR_XTH_EN                    BIT0
+#define SCU_XTHCR_READYTIME_1024             0
+#define SCU_XTHCR_READYTIME_4096             BIT2 
+#define SCU_XTHCR_READYTIME_16384            BIT3
+#define SCU_XTHCR_READYTIME_32768            (BIT3|BIT2)    
+
+/****************  Bit definition for SCU PLLCR register  **********************/
+#define SCU_PLLCR_PLL_LOCK_SEL              BIT31
+#define SCU_PLLCR_PLL_FREE_RUN              BIT30
+#define SCU_PLLCR_PLL_LOCK                  BIT29
+#define SCU_PLLCR_PLL_RUN_DLY              (BIT28|BIT27|BIT26|BIT25|BIT24|BIT23)
+#define SCU_PLLCR_PLL_UPDATE_EN             BIT22
+#define SCU_PLLCR_PLL_SLEEP                 BIT21
+#define SCU_PLLCR_PLL_OD                   (BIT19|BIT18)
+#define SCU_PLLCR_PLL_N                    (BIT15|BIT14)
+#define SCU_PLLCR_PLL_M                    (BIT6|BIT5|BIT4|BIT3)
+#define SCU_PLLCR_PLL_SRC_SEL              (BIT2|BIT1)
+#define SCU_PLLCR_PLL_EN                   (BIT0)
+
+/****************  Bit definition for SCU LDOCR register  **********************/
+#define SCU_LDOCR_LPLDO12_TRIM              (BIT28|BIT27|BIT26)
+#define SCU_LDOCR_LPSTP_SFT                  BIT25
+#define SCU_LDOCR_LPLDO12_EN_SFT             BIT24
+#define SCU_LDOCR_MLDO12_LOWP_SFT            BIT22
+#define SCU_LDOCR_MLDO12_LV_SFT             (BIT21|BIT20)
+#define SCU_LDOCR_LDO18A_EN                  BIT19
+#define SCU_LDOCR_ANATEST_SEL               (BIT18|BIT17|BIT16)
+#define SCU_LDOCR_LDO18A_TRIM               (BIT15|BIT14|BIT13)
+#define SCU_LDOCR_LDO18_TRIM                (BIT12|BIT11|BIT10)
+#define SCU_LDOCR_LDO18_EN                   BIT9
+#define SCU_LDOCR_LDOCTL_SEL                 BIT8
+#define SCU_LDOCR_LDO12_TRIM                (BIT7|BIT6|BIT5|BIT4)
+#define SCU_LDOCR_VREF_TRIM                 (BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU WMR register  ***********************/
+#define SCU_WMR_RTC_READY                    BIT6
+#define SCU_WMR_REMAP_FLAG                   BIT4
+#define SCU_WMR_BOOTPIN                      BIT3
+
+/****************  Bit definition for SCU CLKOCR register  ********************/
+#define SCU_CLKOCR_BUZZER2_EN                BIT31
+#define SCU_CLKOCR_BUZZER2_POL               BIT30
+#define SCU_CLKOCR_BUZZER2_DIV              (BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)
+#define SCU_CLKOCR_BUZZER_EN                 BIT23
+#define SCU_CLKOCR_BUZZER_POL                BIT22
+#define SCU_CLKOCR_BUZZER_DIV               (0x3FFFE0)
+#define SCU_CLKOCR_CLKOUT_SEL                BIT4
+#define SCU_CLKOCR_CLKTEST_SEL              (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU SYSCFG1 register  ********************/
+#define SCU_SYSCFG1_TIM15_CH2_SEL           (BIT25|BIT24)
+#define SCU_SYSCFG1_TIM15_CH1_SEL           (BIT23|BIT22)
+#define SCU_SYSCFG1_TIM14_CH1_SEL            BIT20
+#define SCU_SYSCFG1_IR_MODE                 (BIT18|BIT17)
+#define SCU_SYSCFG1_IR_POL                   BIT16
+#define SCU_SYSCFG1_SRAM_PEF                 BIT8
+#define SCU_SYSCFG1_LVD_LOCK                 BIT2
+#define SCU_SYSCFG1_SRAM_PARITY_LOCK         BIT1
+#define SCU_SYSCFG1_LOCKUP_LOCK              BIT0
+
+/****************  Bit definition for SCU LVDCFG register  ********************/
+#define SCU_LVDCFG_LVD_VALUE                 BIT15
+#define SCU_LVDCFG_LVD_FILTER                BIT14
+#define SCU_LVDCFG_FLT_TIME                 (BIT11|BIT10|BIT9)
+#define SCU_LVDCFG_LVD_FLTEN                 BIT8
+#define SCU_LVDCFG_LVD_TRIM                 (BIT4|BIT3|BIT2|BIT1)
+#define SCU_LVDCFG_LVDEN                     BIT0
+
+/****************  Bit definition for SCU STOPCFG register  ********************/
+#define SCU_STOPCFG_LPLDO12_LV              (BIT15|BIT14|BIT13)
+#define SCU_STOPCFG_TKPCLK_SEL               BIT12
+#define SCU_STOPCFG_PDDS                     BIT11
+#define SCU_STOPCFG_TK_LPLDOLV               BIT10
+#define SCU_STOPCFG_LPSTOP                   BIT9
+#define SCU_STOPCFG_RCH_DIV_EN               BIT8
+#define SCU_STOPCFG_MLDO12_LOWP              BIT6
+#define SCU_STOPCFG_MLDO12_LV               (BIT5|BIT4)
+#define SCU_STOPCFG_RC64MPDEN                BIT3
+#define SCU_STOPCFG_RTC_WE                   BIT0
+
+/**************  Bit definition for SCU VECTOROFFSET register  *****************/
+#define SCU_VECTOROFFSET_VOFFSETEN           BIT0
+
+/****************  Bit definition for SCU PASEL1 register  *********************/
+#define SCU_PASEL1_PA7_SEL                  (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PASEL1_PA6_SEL                  (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PASEL1_PA5_SEL                  (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PASEL1_PA4_SEL                  (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PASEL1_PA3_SEL                  (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PASEL1_PA2_SEL                  (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PASEL1_PA1_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PASEL1_PA0_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PASEL2 register  *********************/
+#define SCU_PASEL2_PA15_SEL                 (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PASEL2_PA14_SEL                 (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PASEL2_PA13_SEL                 (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PASEL2_PA12_SEL                 (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PASEL2_PA11_SEL                 (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PASEL2_PA10_SEL                 (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PASEL2_PA9_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PASEL2_PA8_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PBSEL1 register  *********************/
+#define SCU_PBSEL1_PB7_SEL                  (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PBSEL1_PB6_SEL                  (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PBSEL1_PB5_SEL                  (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PBSEL1_PB4_SEL                  (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PBSEL1_PB3_SEL                  (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PBSEL1_PB2_SEL                  (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PBSEL1_PB1_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PBSEL1_PB0_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PBSEL2 register  *********************/
+#define SCU_PBSEL2_PB15_SEL                 (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PBSEL2_PB14_SEL                 (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PBSEL2_PB13_SEL                 (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PBSEL2_PB12_SEL                 (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PBSEL2_PB11_SEL                 (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PBSEL2_PB10_SEL                 (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PBSEL2_PB9_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PBSEL2_PB8_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PASTR register  **********************/
+#define SCU_PASTR_PA15_STH                  (BIT31|BIT30)
+#define SCU_PASTR_PA14_STH                  (BIT29|BIT28)
+#define SCU_PASTR_PA13_STH                  (BIT27|BIT26)
+#define SCU_PASTR_PA12_STH                  (BIT25|BIT24)
+#define SCU_PASTR_PA11_STH                  (BIT23|BIT22)
+#define SCU_PASTR_PA10_STH                  (BIT21|BIT20)
+#define SCU_PASTR_PA9_STH                   (BIT19|BIT18)
+#define SCU_PASTR_PA8_STH                   (BIT17|BIT16)
+#define SCU_PASTR_PA7_STH                   (BIT15|BIT14)
+#define SCU_PASTR_PA6_STH                   (BIT13|BIT12)
+#define SCU_PASTR_PA5_STH                   (BIT11|BIT10)
+#define SCU_PASTR_PA4_STH                   (BIT9|BIT8)
+#define SCU_PASTR_PA3_STH                   (BIT7|BIT6)
+#define SCU_PASTR_PA2_STH                   (BIT5|BIT4)
+#define SCU_PASTR_PA1_STH                   (BIT3|BIT2)
+#define SCU_PASTR_PA0_STH                   (BIT1|BIT0)
+
+/****************  Bit definition for SCU PBSTR register  **********************/
+#define SCU_PBSTR_PB15_STH                  (BIT31|BIT30)
+#define SCU_PBSTR_PB14_STH                  (BIT29|BIT28)
+#define SCU_PBSTR_PB13_STH                  (BIT27|BIT26)
+#define SCU_PBSTR_PB12_STH                  (BIT25|BIT24)
+#define SCU_PBSTR_PB11_STH                  (BIT23|BIT22)
+#define SCU_PBSTR_PB10_STH                  (BIT21|BIT20)
+#define SCU_PBSTR_PB9_STH                   (BIT19|BIT18)
+#define SCU_PBSTR_PB8_STH                   (BIT17|BIT16)
+#define SCU_PBSTR_PB7_STH                   (BIT15|BIT14)
+#define SCU_PBSTR_PB6_STH                   (BIT13|BIT12)
+#define SCU_PBSTR_PB5_STH                   (BIT11|BIT10)
+#define SCU_PBSTR_PB4_STH                   (BIT9|BIT8)
+#define SCU_PBSTR_PB3_STH                   (BIT7|BIT6)
+#define SCU_PBSTR_PB2_STH                   (BIT5|BIT4)
+#define SCU_PBSTR_PB1_STH                   (BIT3|BIT2)
+#define SCU_PBSTR_PB0_STH                   (BIT1|BIT0)
+
+/****************  Bit definition for SCU PCSEL1 register  *********************/
+#define SCU_PCSEL1_PC7_SEL                  (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PCSEL1_PC6_SEL                  (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PCSEL1_PC5_SEL                  (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PCSEL1_PC4_SEL                  (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PCSEL1_PC3_SEL                  (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PCSEL1_PC2_SEL                  (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PCSEL1_PC1_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PCSEL1_PC0_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PCSEL2 register  *********************/
+#define SCU_PCSEL2_PC15_SEL                 (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PCSEL2_PC14_SEL                 (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PCSEL2_PC13_SEL                 (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PCSEL2_PC12_SEL                 (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PCSEL2_PC11_SEL                 (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PCSEL2_PC10_SEL                 (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PCSEL2_PC9_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PCSEL2_PC8_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PDSEL1 register  *********************/
+#define SCU_PDSEL1_PD7_SEL                  (BIT31|BIT30|BIT29|BIT28)
+#define SCU_PDSEL1_PD6_SEL                  (BIT27|BIT26|BIT25|BIT24)
+#define SCU_PDSEL1_PD5_SEL                  (BIT23|BIT22|BIT21|BIT20)
+#define SCU_PDSEL1_PD4_SEL                  (BIT19|BIT18|BIT17|BIT16)
+#define SCU_PDSEL1_PD3_SEL                  (BIT15|BIT14|BIT13|BIT12)
+#define SCU_PDSEL1_PD2_SEL                  (BIT11|BIT10|BIT9|BIT8)
+#define SCU_PDSEL1_PD1_SEL                  (BIT7|BIT6|BIT5|BIT4)
+#define SCU_PDSEL1_PD0_SEL                  (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for SCU PCSTR register  **********************/
+#define SCU_PCSTR_PC12_STH                  (BIT25|BIT24)
+#define SCU_PCSTR_PC11_STH                  (BIT23|BIT22)
+#define SCU_PCSTR_PC10_STH                  (BIT21|BIT20)
+#define SCU_PCSTR_PC9_STH                   (BIT19|BIT18)
+#define SCU_PCSTR_PC8_STH                   (BIT17|BIT16)
+#define SCU_PCSTR_PC7_STH                   (BIT15|BIT14)
+#define SCU_PCSTR_PC6_STH                   (BIT13|BIT12)
+#define SCU_PCSTR_PC5_STH                   (BIT11|BIT10)
+#define SCU_PCSTR_PC4_STH                   (BIT9|BIT8)
+#define SCU_PCSTR_PC3_STH                   (BIT7|BIT6)
+#define SCU_PCSTR_PC2_STH                   (BIT5|BIT4)
+#define SCU_PCSTR_PC1_STH                   (BIT3|BIT2)
+#define SCU_PCSTR_PC0_STH                   (BIT1|BIT0)
+
+/****************  Bit definition for SCU PDSTR register  **********************/
+#define SCU_PDSTR_PD7_STH                   (BIT15|BIT14)
+#define SCU_PDSTR_PD6_STH                   (BIT13|BIT12)
+#define SCU_PDSTR_PD5_STH                   (BIT11|BIT10)
+#define SCU_PDSTR_PD4_STH                   (BIT9|BIT8)
+#define SCU_PDSTR_PD3_STH                   (BIT7|BIT6)
+#define SCU_PDSTR_PD2_STH                   (BIT5|BIT4)
+#define SCU_PDSTR_PD1_STH                   (BIT3|BIT2)
+#define SCU_PDSTR_PD0_STH                   (BIT1|BIT0)
+
+/*
+ * @brief  Peripheral Enable structures definition
+ */
+typedef enum
+{
+    EN_CAN1   = 45,
+    EN_ROM    = 44,
+    EN_HRNG   = 43,
+    EN_AES    = 42,
+    EN_TIM17  = 41,
+    EN_TIM16  = 40,
+    EN_TIM15  = 39,
+    EN_TIM14  = 38,
+    EN_TIM7   = 37,
+    EN_TIM6   = 36,
+    EN_TIM3   = 35,
+    EN_TIM1   = 34,
+    EN_UART3  = 33,
+    EN_TIM2   = 32,
+    EN_OPA    = 31,
+    EN_COMP   = 30,
+    EN_TKEY   = 29,
+    EN_ADC    = 28,
+    EN_RTC    = 27,
+    EN_DMA    = 26,
+    EN_CRC    = 25,
+    EN_DAC    = 24,
+    EN_USB    = 23,
+    EN_LPUART = 22,
+    EN_I2C2   = 21,
+    EN_I2C1   = 20,
+    EN_SPI2   = 19,
+    EN_SPI1   = 18,
+    EN_UART2  = 17,
+    EN_UART1  = 16,
+    EN_CAN2   = 15,
+    EN_I2S1   = 14,
+    
+    EN_SPI4   = 13,
+    EN_GPIOEF = 12,
+    EN_SPI3   = 11,
+    EN_UART4  = 10,
+    EN_TIM4   = 9,
+    EN_FAU    = 8,
+    EN_EFC    = 6,
+    EN_SRAM   = 5,
+    EN_EXTI   = 4,
+    EN_IWDT   = 3,
+    EN_WDT    = 2,
+    EN_GPIOCD = 1,
+    EN_GPIOAB = 0,
+}enum_Enable_ID_t;
+
+typedef enum
+{
+    RESET_REASON_LOW_VOLTAGE   = 0x00U,   // low voltage detected, leads to reset  
+	RESET_REASON_WDT           = 0x01U,   // System WDT reset 
+	RESET_REASON_IWDT          = 0x02U,   // IWDT reset 
+	RESET_REASON_LOCKUP        = 0x03U,   // cortex-m0 lockup leads to reset  
+	RESET_REASON_SYSREQ        = 0x04U,   // system reset 
+	RESET_REASON_RSTN          = 0x05U,   // RSTN negative pulse leads to reset   
+	RESET_REASON_EFC           = 0x06U,   // efc reset leads to reset   
+    RESET_REASON_SOFT          = 0x07U,   // soft reset 
+	RESET_REASON_POR12         = 0x09U,   // core power on reset, rtc not reset, eg:wakeup from standby   
+	RESET_REASON_POR           = 0x0AU,   // chip power on reset 
+	RESET_REASON_INVALID,  
+}RESET_REASON; 
+
+#define NVIC_PRIORITY_GROUP_3  0x00000004U   // 3 bits for pre-emption priority, 0 bit for subpriority   
+#define NVIC_PRIORITY_GROUP_2  0x00000005U   // 2 bits for pre-emption priority, 1 bit for subpriority    
+#define NVIC_PRIORITY_GROUP_1  0x00000006U   // 1 bits for pre-emption priority, 2 bit for subpriority    
+#define NVIC_PRIORITY_GROUP_0  0x00000007U   // 0 bits for pre-emption priority, 3 bit for subpriority         
+
+#define SYSTEM_TIMEOUT  (1000000)   
+
+
+/* System_Init */
+void System_Init(void);
+
+/* System_Core_Config */
+void System_Core_Config(void);
+
+/* System_Clock_Init */
+bool System_Clock_Init(uint32_t fu32_Clock);
+
+/* System_SysTick_Init */
+void System_SysTick_Init(void);
+
+/* System_Get_SystemClock */
+uint32_t System_Get_SystemClock(void);
+
+/* System_Get_APBClock */
+uint32_t System_Get_APBClock(void);
+
+/* System_Module_Reset */
+void System_Module_Reset(enum_RST_ID_t fe_ID_Index);
+
+/* System_Module_Enable */
+void System_Module_Enable(enum_Enable_ID_t fe_ID_Index);
+
+/* System_Module_Disable */
+void System_Module_Disable(enum_Enable_ID_t fe_ID_Index);
+
+/* System_Delay */
+void System_Delay(volatile uint32_t fu32_Delay); 
+
+/* System_Delay_MS */
+void System_Delay_MS(volatile uint32_t fu32_Delay);
+
+/* System_Enable_RC32K */
+void System_Enable_RC32K(void);
+
+/* System_Disable_RC32K */
+void System_Disable_RC32K(void);
+
+/* System_Enable_XTAL */
+void System_Enable_XTAL(void);
+
+/* System_Disable_XTAL */
+void System_Disable_XTAL(void);
+ 
+/* System_Clear_Stop_Wakeup */
+void System_Clear_Stop_Wakeup(void);
+
+/* System_Enter_Standby_Mode */
+void System_Enter_Standby_Mode(void);       
+
+/* System_Enter_Stop_Mode */
+void System_Enter_Stop_Mode(uint8_t STOPEntry);    
+
+/* System_Enter_Sleep_Mode */     
+void System_Enter_Sleep_Mode(uint8_t SleepEntry);   
+
+/* System_Enable_Disable_Reset */
+void System_Enable_Disable_Reset(RESET_ENABLE_SOURCE source, FUNC_DISABLE_ENABLE enable_disable);   
+
+/* System_Reset_MCU */   
+void System_Reset_MCU(RESET_SOURCE source);    
+
+/* System_Enable_Disable_RTC_Domain_Access */
+void System_Enable_Disable_RTC_Domain_Access(FUNC_DISABLE_ENABLE enable_disable);  
+
+/* System_Return_Last_Reset_Reason */
+RESET_REASON System_Return_Last_Reset_Reason(void) ;   
+
+/* System_Set_Buzzer_Divider */    
+void System_Set_Buzzer_Divider(uint32_t div, FUNC_DISABLE_ENABLE enable);     
+
+/* System_USB_PHY_Config */  
+uint32_t System_USB_PHY_Config(void);  
+
+#endif  
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/Device/System_Accelerate.h

@@ -0,0 +1,28 @@
+/*
+  ******************************************************************************
+  * @file    System_Accelerate.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   MCU Accelerate Peripheral Access Layer System header File.
+  ******************************************************************************
+*/
+#ifndef __SYSTEM_ACCELERATE_H__
+#define __SYSTEM_ACCELERATE_H__
+
+
+
+/* System_EnableIAccelerate */ 
+void System_EnableIAccelerate(void);
+
+/* System_DisableIAccelerate */
+void System_DisableIAccelerate(void);
+
+/* System_EnableDAccelerate */
+void System_EnableDAccelerate(void);
+
+/* System_DisableDAccelerate */
+void System_DisableDAccelerate(void);
+
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/Device/startup_ACM32F4_gcc.s

@@ -0,0 +1,344 @@
+/*********************** (C) COPYRIGHT 2020 Aisinochip *************************
+;* File Name          : Startup_ACM32F4.s
+;* Author             : AisinoChip Firmware Team
+;* Version            : V1.0.0
+;* Date               : 2020
+;* Description        : ACM32F4 Devices vector table for GCC toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Configure the clock system
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M33 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2020 AisinoChip.
+;* All rights reserved.
+;*******************************************************************************/
+
+  .syntax unified
+  .cpu cortex-m33
+  .fpu softvfp 
+  .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+/*.equ  BootRAM, 0xF108F85F */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+  .section .text.Reset_Handler
+  .weak Reset_Handler
+  .type Reset_Handler, %function
+Reset_Handler:
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs r1, #0
+  b LoopCopyDataInit
+
+CopyDataInit:
+  ldr r3, =_sidata
+  ldr r3, [r3, r1]
+  str r3, [r0, r1]
+  adds r1, r1, #4
+
+LoopCopyDataInit:
+  ldr r0, =_sdata
+  ldr r3, =_edata
+  adds r2, r0, r1
+  cmp r2, r3
+  bcc CopyDataInit
+  ldr r2, =_sbss
+  b LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs r3, #0
+  str r3, [r2], #4
+
+LoopFillZerobss:
+  ldr r3, = _ebss
+  cmp r2, r3
+  bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+  /*  bl  SystemInit */
+/* Call static constructors */
+  /*  bl __libc_init_array */
+/* Call the application's entry point.*/
+  bl entry
+  bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ *
+ * @param  None
+ * @retval : None
+*/
+    .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b Infinite_Loop
+  .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3.  Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+  .section .isr_vector,"a",%progbits
+  .type g_pfnVectors, %object
+  .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+
+  .word _estack
+  .word Reset_Handler
+  .word NMI_Handler
+  .word HardFault_Handler
+  .word MemManage_Handler
+  .word BusFault_Handler
+  .word UsageFault_Handler
+  .word 0
+  .word 0
+  .word 0
+  .word 0
+  .word SVC_Handler
+  .word DebugMon_Handler
+  .word 0
+  .word PendSV_Handler
+  .word SysTick_Handler
+
+  /* External Interrupts */
+  .word WDT_IRQHandler
+  .word RTC_IRQHandler
+  .word EFC_IRQHandler
+  .word GPIOAB_IRQHandler
+  .word GPIOCD_IRQHandler
+  .word EXIT_IRQHandler
+  .word SRAM_PAPITY_IRQHandler
+  .word CLKRDY_IRQHandler
+  .word UART4_IRQHandler
+  .word DMA_IRQHandler
+  .word UART3_IRQHandler
+  .word RSV_IRQHandler
+  .word ADC_IRQHandler
+  .word TIM1_BRK_UP_TRG_COM_IRQHandler
+  .word TIM1_CC_IRQHandler
+  .word TIM2_IRQHandler
+  .word TIM3_IRQHandler
+  .word TIM6_IRQHandler
+  .word TIM7_IRQHandler
+  .word TIM14_IRQHandler
+  .word TIM15_IRQHandler
+  .word TIM16_IRQHandler
+  .word TIM17_IRQHandler
+  .word I2C1_IRQHandler
+  .word I2C2_IRQHandler
+  .word SPI1_IRQHandler
+  .word SPI2_IRQHandler
+  .word UART1_IRQHandler
+  .word UART2_IRQHandler
+  .word LPUART_IRQHandler
+  .word SPI3_IRQHandler
+  .word AES_IRQHandler
+  .word USB_IRQHandler
+  .word DAC_IRQHandler
+  .word I2S_IRQHandler
+  .word GPIOEF_IRQHandler
+  .word CAN1_IRQHandler
+  .word CAN2_IRQHandler
+  .word FPU_IRQHandler
+  .word TIM4_IRQHandler
+  .word SPI4_IRQHandler
+
+                          
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+  .weak NMI_Handler
+  .thumb_set NMI_Handler,Default_Handler
+
+  .weak HardFault_Handler
+  .thumb_set HardFault_Handler,Default_Handler
+
+  .weak MemManage_Handler
+  .thumb_set MemManage_Handler,Default_Handler
+
+  .weak BusFault_Handler
+  .thumb_set BusFault_Handler,Default_Handler
+
+  .weak UsageFault_Handler
+  .thumb_set UsageFault_Handler,Default_Handler
+
+  .weak SVC_Handler
+  .thumb_set SVC_Handler,Default_Handler
+
+  .weak DebugMon_Handler
+  .thumb_set DebugMon_Handler,Default_Handler
+
+  .weak PendSV_Handler
+  .thumb_set PendSV_Handler,Default_Handler
+
+  .weak SysTick_Handler
+  .thumb_set SysTick_Handler,Default_Handler
+
+  .weak WDT_IRQHandler
+  .thumb_set WDT_IRQHandler,Default_Handler
+
+  .weak RTC_IRQHandler
+  .thumb_set RTC_IRQHandler,Default_Handler
+
+  .weak EFC_IRQHandler
+  .thumb_set EFC_IRQHandler,Default_Handler
+
+  .weak GPIOAB_IRQHandler
+  .thumb_set GPIOAB_IRQHandler,Default_Handler
+
+  .weak GPIOCD_IRQHandler
+  .thumb_set GPIOCD_IRQHandler,Default_Handler
+
+  .weak EXIT_IRQHandler
+  .thumb_set EXIT_IRQHandler,Default_Handler
+
+  .weak SRAM_PAPITY_IRQHandler
+  .thumb_set SRAM_PAPITY_IRQHandler,Default_Handler
+
+  .weak CLKRDY_IRQHandler
+  .thumb_set CLKRDY_IRQHandler,Default_Handler
+
+  .weak UART4_IRQHandler
+  .thumb_set UART4_IRQHandler,Default_Handler
+
+  .weak DMA_IRQHandler
+  .thumb_set DMA_IRQHandler,Default_Handler
+
+  .weak UART3_IRQHandler
+  .thumb_set UART3_IRQHandler,Default_Handler
+
+  .weak RSV_IRQHandler
+  .thumb_set RSV_IRQHandler,Default_Handler
+
+  .weak ADC_IRQHandler
+  .thumb_set ADC_IRQHandler,Default_Handler
+
+  .weak TIM1_BRK_UP_TRG_COM_IRQHandler
+  .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
+
+  .weak TIM1_CC_IRQHandler
+  .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+  .weak TIM2_IRQHandler
+  .thumb_set TIM2_IRQHandler,Default_Handler
+
+  .weak TIM3_IRQHandler
+  .thumb_set TIM3_IRQHandler,Default_Handler
+
+  .weak TIM6_IRQHandler
+  .thumb_set TIM6_IRQHandler,Default_Handler
+
+  .weak TIM7_IRQHandler
+  .thumb_set TIM7_IRQHandler,Default_Handler
+
+  .weak TIM14_IRQHandler
+  .thumb_set TIM14_IRQHandler,Default_Handler
+
+  .weak TIM15_IRQHandler
+  .thumb_set TIM15_IRQHandler,Default_Handler
+
+  .weak TIM16_IRQHandler
+  .thumb_set TIM16_IRQHandler,Default_Handler
+
+  .weak TIM17_IRQHandler
+  .thumb_set TIM17_IRQHandler,Default_Handler
+
+  .weak I2C1_IRQHandler
+  .thumb_set I2C1_IRQHandler,Default_Handler
+
+  .weak I2C2_IRQHandler
+  .thumb_set I2C2_IRQHandler,Default_Handler
+
+  .weak SPI1_IRQHandler
+  .thumb_set SPI1_IRQHandler,Default_Handler
+
+  .weak SPI2_IRQHandler
+  .thumb_set SPI2_IRQHandler,Default_Handler
+
+  .weak UART1_IRQHandler
+  .thumb_set UART1_IRQHandler,Default_Handler
+
+  .weak UART2_IRQHandler
+  .thumb_set UART2_IRQHandler,Default_Handler
+
+  .weak LPUART_IRQHandler
+  .thumb_set LPUART_IRQHandler,Default_Handler
+
+  .weak SPI3_IRQHandler
+  .thumb_set SPI3_IRQHandler,Default_Handler
+
+  .weak AES_IRQHandler
+  .thumb_set AES_IRQHandler,Default_Handler
+
+  .weak USB_IRQHandler
+  .thumb_set USB_IRQHandler,Default_Handler
+
+  .weak DAC_IRQHandler
+  .thumb_set DAC_IRQHandler,Default_Handler
+
+  .weak I2S_IRQHandler
+  .thumb_set I2S_IRQHandler,Default_Handler
+
+  .weak GPIOEF_IRQHandler
+  .thumb_set GPIOEF_IRQHandler,Default_Handler
+
+  .weak CAN1_IRQHandler
+  .thumb_set CAN1_IRQHandler,Default_Handler
+
+  .weak CAN2_IRQHandler
+  .thumb_set CAN2_IRQHandler,Default_Handler
+
+  .weak FPU_IRQHandler
+  .thumb_set FPU_IRQHandler,Default_Handler
+
+  .weak TIM4_IRQHandler
+  .thumb_set TIM4_IRQHandler,Default_Handler
+
+  .weak SPI4_IRQHandler
+  .thumb_set SPI4_IRQHandler,Default_Handler
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/ACM32Fxx_HAL.h

@@ -0,0 +1,207 @@
+/*
+  ******************************************************************************
+  * @file    ACM32Fxx_HAL.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   HAL Config header file.
+  ******************************************************************************
+*/
+#ifndef __ACM32FXX_HAL_H__
+#define __ACM32FXX_HAL_H__
+
+/* 
+    Uncomment the line below according to the target device used in your application 
+*/
+/* #define ACM32F3XX */    /*!< ACM32F303xx */
+   #define ACM32F4XX       /*!< ACM32F403xx */
+/* #define ACM32FPXX */    /*!< ACM32FP400xx ACM32FP401xx */
+
+
+/** @addtogroup Device_Included
+  * @{
+  */
+#if defined(ACM32F3XX)
+    #include "ACM32F3.h"
+#elif defined(ACM32F4XX)
+    #include "ACM32F4.h"
+#elif defined(ACM32FPXX)
+    #include "ACM32FP.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+/**
+  * @}
+  */
+
+
+/*
+ * @brief  HAL Status structures definition
+ */
+typedef enum
+{
+    HAL_OK       = 0x00U,
+    HAL_ERROR    = 0x01U,
+    HAL_BUSY     = 0x02U,
+    HAL_TIMEOUT  = 0x03U
+}HAL_StatusTypeDef;
+
+
+//#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */
+  #ifndef __weak
+    #define __weak  __attribute__((weak))
+  #endif
+//#endif
+
+
+/* USE FULL ASSERT */
+#define USE_FULL_ASSERT    (1)
+
+
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_EXTI_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_I2S_MODULE_ENABLED
+#define HAL_IWDT_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIMER_MODULE_ENABLED
+#define HAL_EFLASH_MODULE_ENABLED
+#ifdef  ACM32F4XX
+#define HAL_OPA_MODULE_ENABLED
+#endif
+#ifndef ACM32FPXX
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+#endif
+#define HAL_LPUART_MODULE_ENABLED
+#define HAL_WDT_MODULE_ENABLED 
+#define HAL_FSUSB_MODULE_ENABLED
+#define HAL_SYSTICK_ENABLED
+#define HAL_CRC_ENABLED  
+#define HAL_FAU_ENABLED  
+#define HAL_AES_ENABLED  
+#define HAL_HASH_SHA1_ENABLED 
+#define HAL_HASH_SHA256_ENABLED 
+#define HAL_HRNG_ENABLED  
+
+#if defined(ACM32F3XX)
+    #include "System_ACM32F3.h"
+#elif defined(ACM32F4XX)
+    #include "System_ACM32F4.h"
+#elif defined(ACM32FPXX)
+    #include "System_ACM32FP.h"
+#else
+    #error "Please select first the target device used in your application (in ACM32Fxx_HAL.h file)"
+#endif
+
+#include "System_Accelerate.h"
+
+#ifdef HAL_DMA_MODULE_ENABLED
+    #include "HAL_DMA.h"
+#endif
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+    #include "HAL_GPIO.h"
+#endif
+
+#ifdef HAL_UART_MODULE_ENABLED
+    #include "HAL_UART.h"
+    #include "HAL_UART_EX.h"
+#endif
+
+#ifdef HAL_ADC_MODULE_ENABLED
+    #include "HAL_ADC.h"
+#endif
+
+#ifdef HAL_DAC_MODULE_ENABLED
+    #include "HAL_DAC.h"
+#endif
+
+#ifdef HAL_EXTI_MODULE_ENABLED
+    #include "HAL_EXTI.h"
+#endif
+
+#ifdef HAL_I2C_MODULE_ENABLED
+    #include "HAL_I2C.h"
+#endif
+
+#ifdef HAL_I2S_MODULE_ENABLED
+    #include "HAL_I2S.h"
+#endif
+
+#ifdef HAL_RTC_MODULE_ENABLED
+    #include "HAL_RTC.h"
+#endif
+
+#ifdef HAL_SPI_MODULE_ENABLED
+    #include "HAL_SPI.h"
+#endif
+
+#ifdef HAL_IWDT_MODULE_ENABLED
+    #include "HAL_IWDT.h"
+#endif
+
+#ifdef HAL_EFLASH_MODULE_ENABLED
+    #include "HAL_EFlash.h"
+    #include "HAL_EFlash_EX.h"
+#endif
+
+#ifdef HAL_OPA_MODULE_ENABLED
+    #include "HAL_OPA.h"
+#endif
+
+#ifdef HAL_COMP_MODULE_ENABLED
+    #include "HAL_COMP.h"
+#endif
+
+#ifdef HAL_CAN_MODULE_ENABLED
+    #include "HAL_CAN.h"
+#endif
+
+#ifdef HAL_LPUART_MODULE_ENABLED
+    #include "HAL_LPUART.h"
+#endif
+
+#ifdef HAL_WDT_MODULE_ENABLED
+    #include "HAL_WDT.h"
+#endif
+
+#ifdef HAL_TIMER_MODULE_ENABLED
+    #include "HAL_TIMER.h"  
+    #include "HAL_TIMER_EX.h"
+#endif  
+
+#ifdef HAL_FSUSB_MODULE_ENABLED
+    #include "HAL_FSUSB.h"
+#endif
+
+#ifdef HAL_CRC_ENABLED  
+#include  "HAL_CRC.h"
+#endif  
+
+#ifdef  HAL_AES_ENABLED
+#include  "HAL_AES.h"  
+#endif    
+
+#ifdef HAL_FAU_ENABLED    
+#include  "HAL_FAU.h"       
+#endif 
+
+#ifdef HAL_HASH_SHA1_ENABLED 
+#include "HAL_SHA1.h"  
+#endif 
+
+#ifdef HAL_HASH_SHA256_ENABLED 
+#include "HAL_SHA256.h"  
+#endif  
+
+#ifdef HAL_HRNG_ENABLED     
+#include "HAL_HRNG.h"    
+#endif    
+
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_ADC.h

@@ -0,0 +1,637 @@
+/*
+  ******************************************************************************
+  * @file    HAL_ADC.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_ADC_H__
+#define __HAL_ADC_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Total definition for ADC  **************************/
+#define ADC_CH_MASK                           (BIT4|BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_SR register  **************************/
+#define ADC_SR_AWD                            (BIT5)
+#define ADC_SR_OVERF                          (BIT4)
+#define ADC_SR_EOG                            (BIT3)
+#define ADC_SR_JEOC                           (BIT2)
+#define ADC_SR_EOC                            (BIT1)
+#define ADC_SR_ADRDY                          (BIT0)
+
+/****************  Bit definition for ADC_IE register  **************************/
+#define ADC_IE_AWDIE                          (BIT5)
+#define ADC_IE_OVERFIE                        (BIT4)
+#define ADC_IE_EOGIE                          (BIT3)
+#define ADC_IE_JEOCIE                         (BIT2)
+#define ADC_IE_EOCIE                          (BIT1)
+
+/****************  Bit definition for ADC_CR1 register  **************************/
+#define ADC_CR1_AWDJCH_POS                     (27U)
+#define ADC_CR1_AWDJCH_MASK                    (BIT31|BIT30|BIT29|BIT28|BIT27)
+#define ADC_CR1_DISCNUM_POS                    (23U)
+#define ADC_CR1_DISCNUM_MASK                   (BIT26|BIT25|BIT24|BIT23)
+#define ADC_CR1_DISCEN                         BIT22
+#define ADC_CR1_CONT                           BIT21
+#define ADC_CR1_SWSTART                        BIT20
+#define ADC_CR1_JSWSTART                       BIT19
+#define ADC_CR1_EXTSEL_POS                     (16U)
+#define ADC_CR1_EXTSEL_MASK                    (BIT18|BIT17|BIT16)
+#define ADC_CR1_JEXTSEL_POS                    (13U)
+#define ADC_CR1_JEXTSEL_MASK                   (BIT15|BIT14|BIT13)
+#define ADC_CR1_DMA                            BIT12
+#define ADC_CR1_AWDEN                          BIT11
+#define ADC_CR1_JAWDEN                         BIT10
+#define ADC_CR1_JEN                            BIT9
+#define ADC_CR1_AWDSGL                         BIT8
+#define ADC_CR1_AWDCH_POS                      (0U)
+#define ADC_CR1_AWDCH_MASK                     (BIT4|BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_CR2 register  **************************/
+#define ADC_CR2_FASTMOD                        BIT27
+#define ADC_CR2_AFE_RSTN                       BIT26
+#define ADC_CR2_JOVSE                          BIT25
+#define ADC_CR2_JTOVS                          BIT24
+#define ADC_CR2_OVSS_POS                      (20U)
+#define ADC_CR2_OVSS_MASK                     (BIT23|BIT22|BIT21|BIT20)
+#define ADC_CR2_OVSR_POS                      (17U)
+#define ADC_CR2_OVSR_MASK                     (BIT19|BIT18|BIT17)
+#define ADC_CR2_OVSE                           BIT16
+#define ADC_CR2_BUF_STIME_POS                 (8U)
+#define ADC_CR2_BUF_STIME_MASK                (BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)
+#define ADC_CR2_EN_BUF                         BIT7
+#define ADC_CR2_DIV_POS                       (3U)
+#define ADC_CR2_DIV_MASK                      (BIT6|BIT5|BIT4|BIT3)
+#define ADC_CR2_ADC_STP                        BIT2
+#define ADC_CR2_OVRMOD                         BIT1
+#define ADC_CR2_ADC_EN                         BIT0
+
+/****************  Bit definition for ADC_SMPR1 register  **************************/
+#define ADC_SMPR_CH_MASK                      (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_DIFF register  **************************/
+#define ADC_DIFF_DIFF7_F                       BIT7
+#define ADC_DIFF_DIFF6_E                       BIT6
+#define ADC_DIFF_DIFF5_D                       BIT5
+#define ADC_DIFF_DIFF4_C                       BIT4
+#define ADC_DIFF_DIFF3_B                       BIT3
+#define ADC_DIFF_DIFF2_A                       BIT2
+#define ADC_DIFF_DIFF1_9                       BIT1
+#define ADC_DIFF_DIFF0_8                       BIT0 
+
+/****************  Bit definition for ADC_HTR register  ***********************/
+#define ADC_HTR_DHT                           (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
+#define ADC_HTR_HT                            (BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_LTR register  ***********************/
+#define ADC_LTR_DLT                           (BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)
+#define ADC_LTR_LT                            (BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_SQR1 register  ***********************/
+#define ADC_SQR1_L                            (BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_JSQR register  ***********************/
+#define ADC_JSQR_JSQ                          (BIT4|BIT3|BIT2|BIT1|BIT0)
+
+/****************  Bit definition for ADC_JDR register  ***********************/
+#define ADC_JDR_JCH                           (BIT20|BIT19|BIT18|BIT17|BIT16)
+
+/****************  Bit definition for ADC_DR register  ***********************/
+#define ADC_DR_CH                             (BIT20|BIT19|BIT18|BIT17|BIT16)
+
+/****************  Bit definition for ADC_SIGN register  ***********************/
+#define ADC_SIGN_SIGN7_F                       BIT7
+#define ADC_SIGN_SIGN6_E                       BIT6
+#define ADC_SIGN_SIGN5_D                       BIT5
+#define ADC_SIGN_SIGN4_C                       BIT4
+#define ADC_SIGN_SIGN3_B                       BIT3
+#define ADC_SIGN_SIGN2_A                       BIT2
+#define ADC_SIGN_SIGN1_9                       BIT1
+#define ADC_SIGN_SIGN0_8                       BIT0 
+
+/****************  Bit definition for ADC_TSREF register  ***********************/
+#define ADC_TSREF_HIZ_EN                       BIT27
+#define ADC_TSREF_VREFBI_SEL_POS              (25U)
+#define ADC_TSREF_VREFBI_SEL_MASK             (BIT26|BIT25)
+#define ADC_TSREF_VREFBI_EN                    BIT24
+#define ADC_TSREF_VTRIM_POS                   (19U)
+#define ADC_TSREF_VTRIM_MASK                  (BIT23|BIT22|BIT21|BIT20|BIT19)
+#define ADC_TSREF_TTRIM_POS                   (15U)
+#define ADC_TSREF_TTRIM_MASK                  (BIT18|BIT17|BIT16|BIT15)
+#define ADC_TSREF_ALG_MEAN_POS                (9U)
+#define ADC_TSREF_ALG_MEAN_MASK               (BIT10|BIT9)
+#define ADC_TSREF_ADJ_TD_OS_POS               (5U)
+#define ADC_TSREF_ADJ_TD_OS_MASK              (BIT8|BIT7|BIT6|BIT5)
+#define ADC_TSREF_ADJ_TD_GA_POS               (1U)
+#define ADC_TSREF_ADJ_TD_GA_MASK              (BIT4|BIT3|BIT2|BIT1)
+#define ADC_TSREF_EN_TS                        BIT0
+
+/****************  Macro definition for register operation **************************/
+
+
+/**************** Enable the specified ADC. **************************/
+#define __HAL_ADC_ENABLE(__HANDLE__)                                           \
+  (SET_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADC_EN)))
+    
+/**************** Disable the specified ADC. **************************/
+#define __HAL_ADC_DISABLE(__HANDLE__)                                          \
+  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADC_EN)))
+    
+/**************** Enable the specified ADC interrupt source. **************************/
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+  (SET_BIT((__HANDLE__)->Instance->IE, (__INTERRUPT__)))
+    
+/**************** Disable the specified ADC interrupt source. **************************/
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+  (CLEAR_BIT((__HANDLE__)->Instance->IE, (__INTERRUPT__)))
+  
+/**************** Checks if the specified ADC interrupt source is enabled or disabled. **************************/
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IE & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**************** Get the selected ADC's flag status. **************************/
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+  ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+    
+/**************** Clear the selected ADC's flag status. **************************/
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+  (SET_BIT((__HANDLE__)->Instance->SR, (__FLAG__)))
+
+/**************** Checks if the ADC regular group trig source is the specified source. **************************/
+#define __HAL_ADC_CHECK_TRIG_REGULAR(__HANDLE__, __TRIGSOURCE__)                     \
+  ((((__HANDLE__)->Instance->CR1 & ADC_CR1_EXTSEL_MASK) >> ADC_CR1_EXTSEL_POS) == (__TRIGSOURCE__))
+
+/**************** Checks if the ADC injected channel trig source is the specified source. **************************/
+#define __HAL_ADC_CHECK_TRIG_INJECTED(__HANDLE__, __TRIGSOURCE__)                     \
+  ((((__HANDLE__)->Instance->CR1 & ADC_CR1_JEXTSEL_MASK) >> ADC_CR1_JEXTSEL_POS) == (__TRIGSOURCE__))
+  
+/****************  Bit definition for ADC_SMPR3 register  **************************/
+#define ADC_SMPR3_CONV_PLUS_POS               (20U)
+#define ADC_SMPR3_CONV_PLUS_MASK              (BIT21|BIT20)
+
+/** 
+  * @brief  ADC ExTigger structure definition
+  */
+typedef struct
+{
+  uint32_t ExTrigSel;                     /*!< Configures the regular channel trig mode. */
+  uint32_t JExTrigSel;                    /*!< Configures the inject channel trig mode. */
+}ADC_ExTrigTypeDef;
+
+/** 
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_CR2_OVSR_2X*/
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_CR2_OVSS_0 */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of 
+                                               0 : trig 1 time; other: trig N times, N refer to the oversampling Ratio*/
+}ADC_OversamplingTypeDef;
+
+/******************************** ADC Init mode define *******************************/
+/******************************** ConConvMode define *******************************/
+#define  ADC_CONCONVMODE_DISABLE                (0)
+#define  ADC_CONCONVMODE_ENABLE                 (1)
+
+/******************************** JChannelMode define *******************************/
+#define  ADC_JCHANNELMODE_DISABLE               (0)
+#define  ADC_JCHANNELMODE_ENABLE                (1)
+
+/******************************** DiffMode define *******************************/
+#define  ADC_DIFFMODE_DISABLE                   (0)
+#define  ADC_DIFFMODE_ENABLE                    (1)
+
+/******************************** DMAMode define *******************************/
+#define  ADC_DMAMODE_DISABLE                    (0)
+#define  ADC_DMAMODE_ENABLE                     (1)
+
+/******************************** OverMode define *******************************/
+#define  ADC_OVERMODE_DISABLE                   (0)
+#define  ADC_OVERMODE_ENABLE                    (1)
+
+/******************************** OverSampMode define *******************************/
+#define  ADC_OVERSAMPMODE_DISABLE               (0)
+#define  ADC_OVERSAMPMODE_ENABLE                (1)
+
+/******************************** AnalogWDGEn define *******************************/
+#define  ADC_ANALOGWDGEN_DISABLE                (0)
+#define  ADC_ANALOGWDGEN_ENABLE                 (1)
+
+/**
+  * @brief  ADC Configuration Structure definition
+  */
+typedef struct
+{
+    uint32_t ClockDiv;              /*!< Specify the ADC clock div from the PCLK. 
+                                      This parameter can be set to ADC_CLOCK_DIV1 | ADC_CLOCK_DIV2 |... ADC_CLOCK_DIV16 */
+
+    uint32_t ConConvMode;           /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,
+                                       after the first ADC conversion start trigger occurred (software start or external trigger).
+                                       This parameter can be set to ADC_CONCONVMODE_DISABLE or ADC_CONCONVMODE_ENABLE. */
+    uint32_t JChannelMode;          /*!< Specify if support inject channel. This parameter can be set to ADC_JCHANNELMODE_DISABLE or ADC_JCHANNELMODE_ENABLE*/
+    uint32_t DiffMode;              /*!< Specify the differential parameters. 
+                                       ADC_DIFFMODE_DISABLE:single end mode, 
+                                       ADC_DIFFMODE_ENABLE:differential end mode */
+    uint32_t ChannelEn;             /*!< Specify the enable ADC channels. 
+                                       This parameter can be set to ADC_CHANNEL_0_EN | ADC_CHANNEL_1_EN |... ADC_CHANNEL_15_EN*/
+
+    ADC_ExTrigTypeDef ExTrigMode;    /*!< ADC ExTigger structure, config the regular and inject channel trig mode */
+                                                                                                        
+    uint32_t DMAMode;                /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached)
+                                       or in continuous mode (DMA transfer unlimited, whatever number of conversions).
+                                       This parameter can be set to ADC_DMAMODE_ENABLE or ADC_DMAMODE_DISABLE.
+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */
+
+    uint32_t OverMode;               /*!<  ADC_OVERMODE_DISABLE,ADC_OVERMODE_ENABLE*/
+
+    uint32_t OverSampMode;          /*!< Specify whether the oversampling feature is enabled or disabled.
+                                           This parameter can be set to ADC_OVERSAMPMODE_ENABLE or ADC_OVERSAMPMODE_DISABLE.
+                                           Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */
+    ADC_OversamplingTypeDef Oversampling;   /*!< Specify ADC group regular oversampling structure. */
+    
+    uint32_t AnalogWDGEn;
+}ADC_InitTypeDef;
+
+
+typedef struct
+{
+    uint32_t RjMode;                /*!< Specify the channel mode, 0:regular, Other:inject*/
+    uint32_t Channel;               /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_CHANNEL_0
+                                        Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
+
+    uint32_t Sq;                    /*!< Add or remove the channel from ADC regular group sequencer and specify its conversion rank.
+                                        This parameter is dependent on ScanConvMode:
+                                        - sequencer configured to fully configurable:
+                                          Channels ordering into each rank of scan sequence:
+                                          whatever channel can be placed into whatever rank.
+                                        - sequencer configured to not fully configurable:
+                                          rank of each channel is fixed by channel HW number.
+                                          (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                          Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
+                                        This parameter can be a value of @ref ADC_SEQUENCE_SQ1 */
+
+    uint32_t Smp;                    /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles 
+                                        This parameter can be a value of @ref ADC_SMP_CLOCK_3 */
+}ADC_ChannelConfTypeDef;
+
+typedef struct
+{
+    uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC group regular.
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure.
+                                   This parameter can be a value of @ref ADC_ANALOGWATCHDOG_RCH_ALL. */
+
+    uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').
+                                   This parameter can be a value of @ref ADC_CHANNEL_0. */
+
+    uint32_t ITMode;            /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+
+    uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value. */
+
+    uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value. */
+}ADC_AnalogWDGConfTypeDef;
+
+/******************************** ADC Over Sample Shift define *******************************/
+#define ADC_CR2_OVSS_0                (0U)
+#define ADC_CR2_OVSS_1                (1U)
+#define ADC_CR2_OVSS_2                (2U)
+#define ADC_CR2_OVSS_3                (3U)
+#define ADC_CR2_OVSS_4                (4U)
+#define ADC_CR2_OVSS_5                (5U)
+#define ADC_CR2_OVSS_6                (6U)
+#define ADC_CR2_OVSS_7                (7U)
+#define ADC_CR2_OVSS_8                (8U)
+
+/******************************** ADC Over Sample Rate define *******************************/
+#define ADC_CR2_OVSR_2X               (0U)
+#define ADC_CR2_OVSR_4X               (1U)
+#define ADC_CR2_OVSR_8X               (2U)
+#define ADC_CR2_OVSR_16X              (3U)
+#define ADC_CR2_OVSR_32X              (4U)
+#define ADC_CR2_OVSR_64X              (5U)
+#define ADC_CR2_OVSR_128X             (6U)
+#define ADC_CR2_OVSR_256X             (7U)
+
+/******************************** ADC Sample period define *******************************/
+#define ADC_SMP_CLOCK_3               (0U)
+#define ADC_SMP_CLOCK_5               (1U)
+#define ADC_SMP_CLOCK_7               (2U)
+#define ADC_SMP_CLOCK_10              (3U)
+#define ADC_SMP_CLOCK_13              (4U)
+#define ADC_SMP_CLOCK_16              (5U)
+#define ADC_SMP_CLOCK_20              (6U)
+#define ADC_SMP_CLOCK_30              (7U)
+#define ADC_SMP_CLOCK_60              (8U)
+#define ADC_SMP_CLOCK_80              (9U)
+#define ADC_SMP_CLOCK_100             (10U)
+#define ADC_SMP_CLOCK_120             (11U)
+#define ADC_SMP_CLOCK_160             (12U)
+#define ADC_SMP_CLOCK_320             (13U)
+#define ADC_SMP_CLOCK_480             (14U)
+#define ADC_SMP_CLOCK_640             (15U)
+
+
+/******************************** ADC ClockPrescale define *******************************/
+#define  ADC_CLOCK_DIV1                              (0U)    
+#define  ADC_CLOCK_DIV2                              (1U)    
+#define  ADC_CLOCK_DIV3                              (2U)    
+#define  ADC_CLOCK_DIV4                              (3U)    
+#define  ADC_CLOCK_DIV5                              (4U)    
+#define  ADC_CLOCK_DIV6                              (5U)    
+#define  ADC_CLOCK_DIV7                              (6U)    
+#define  ADC_CLOCK_DIV8                              (7U)    
+#define  ADC_CLOCK_DIV9                              (8U)    
+#define  ADC_CLOCK_DIV10                             (9U)    
+#define  ADC_CLOCK_DIV11                             (10U)    
+#define  ADC_CLOCK_DIV12                             (11U)    
+#define  ADC_CLOCK_DIV13                             (12U)    
+#define  ADC_CLOCK_DIV14                             (13U)    
+#define  ADC_CLOCK_DIV15                             (14U)    
+#define  ADC_CLOCK_DIV16                             (15U) 
+
+/************************ADC_AnalogWDGConfTypeDef->WatchdogMode define********************/
+#define  ADC_ANALOGWATCHDOG_RCH_ALL                 (1U)   //All regular channels
+#define  ADC_ANALOGWATCHDOG_JCH_ALL                 (2U)   //All inject channels
+#define  ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL         (3U)   //All regular and inject channels
+#define  ADC_ANALOGWATCHDOG_RCH_SINGLE              (4U)   //Single regular channel
+#define  ADC_ANALOGWATCHDOG_JCH_SINGLE              (5U)   //Single Inject channel
+#define  ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE       (6U)   //Regular or inject channel
+
+/******************************** ADC sequence number define *******************************/
+#define  ADC_SEQUENCE_SQ1                           (1U)
+#define  ADC_SEQUENCE_SQ2                           (2U)
+#define  ADC_SEQUENCE_SQ3                           (3U)
+#define  ADC_SEQUENCE_SQ4                           (4U)
+#define  ADC_SEQUENCE_SQ5                           (5U)
+#define  ADC_SEQUENCE_SQ6                           (6U)
+#define  ADC_SEQUENCE_SQ7                           (7U)
+#define  ADC_SEQUENCE_SQ8                           (8U)
+#define  ADC_SEQUENCE_SQ9                           (9U)
+#define  ADC_SEQUENCE_SQ10                          (10U)
+#define  ADC_SEQUENCE_SQ11                          (11U)
+#define  ADC_SEQUENCE_SQ12                          (12U)
+#define  ADC_SEQUENCE_SQ13                          (13U)
+#define  ADC_SEQUENCE_SQ14                          (14U)
+#define  ADC_SEQUENCE_SQ15                          (15U)
+#define  ADC_SEQUENCE_SQ16                          (16U)
+
+/******************************** ADC channel number define *******************************/
+#define  ADC_CHANNEL_0                              (0U)    
+#define  ADC_CHANNEL_1                              (1U)    
+#define  ADC_CHANNEL_2                              (2U)    
+#define  ADC_CHANNEL_3                              (3U)    
+#define  ADC_CHANNEL_4                              (4U)    
+#define  ADC_CHANNEL_5                              (5U)    
+#define  ADC_CHANNEL_6                              (6U)    
+#define  ADC_CHANNEL_7                              (7U)    
+#define  ADC_CHANNEL_8                              (8U)    
+#define  ADC_CHANNEL_9                              (9U)    
+#define  ADC_CHANNEL_10                             (10U)    
+#define  ADC_CHANNEL_11                             (11U)    
+#define  ADC_CHANNEL_12                             (12U)    
+#define  ADC_CHANNEL_13                             (13U)    
+#define  ADC_CHANNEL_14                             (14U)    
+#define  ADC_CHANNEL_15                             (15U)    
+#define  ADC_CHANNEL_TEMP                           (16U)    
+#define  ADC_CHANNEL_VBAT                           (17U)    
+#define  ADC_CHANNEL_VBGR                           (18U)    
+#define  ADC_CHANNEL_EXT2                           (19U)    
+#define  ADC_CHANNEL_EXT3                           (20U)    
+
+/******************************** ADC channel enable define *******************************/
+#define  ADC_CHANNEL_0_EN                              (BIT0)    
+#define  ADC_CHANNEL_1_EN                              (BIT1)    
+#define  ADC_CHANNEL_2_EN                              (BIT2)    
+#define  ADC_CHANNEL_3_EN                              (BIT3)    
+#define  ADC_CHANNEL_4_EN                              (BIT4)    
+#define  ADC_CHANNEL_5_EN                              (BIT5)    
+#define  ADC_CHANNEL_6_EN                              (BIT6)    
+#define  ADC_CHANNEL_7_EN                              (BIT7)    
+#define  ADC_CHANNEL_8_EN                              (BIT8)    
+#define  ADC_CHANNEL_9_EN                              (BIT9)    
+#define  ADC_CHANNEL_10_EN                             (BIT10)    
+#define  ADC_CHANNEL_11_EN                             (BIT11)    
+#define  ADC_CHANNEL_12_EN                             (BIT12)    
+#define  ADC_CHANNEL_13_EN                             (BIT13)    
+#define  ADC_CHANNEL_14_EN                             (BIT14)    
+#define  ADC_CHANNEL_15_EN                             (BIT15)    
+#define  ADC_CHANNEL_TEMP_EN                           (BIT16)    
+#define  ADC_CHANNEL_VBAT_EN                           (BIT17)    
+#define  ADC_CHANNEL_VBGR_EN                           (BIT18)    
+#define  ADC_CHANNEL_EXT2_EN                           (BIT19)    
+#define  ADC_CHANNEL_EXT3_EN                           (BIT20)    
+
+/******************************** ADC Trig source define*******************************
+ *  |     Trig Source           |     ACM32FXXX/FPXXX    |      ACM32F0X0          | *
+ *  |     ADC_SOFTWARE_START    |     SWSTART/JSWSTART   |      SWSTART/JSWSTART   | *
+ *  |     ADC_EXTERNAL_TIG1     |     TIM1_TRGO          |      TIM1_TRGO          | *
+ *  |     ADC_EXTERNAL_TIG2     |     TIM1_CC4           |      TIM1_CC4           | *
+ *  |     ADC_EXTERNAL_TIG3     |     TIM2_TRGO          |      RSV                | *
+ *  |     ADC_EXTERNAL_TIG4     |     TIM3_TRGO          |      TIM3_TRGO          | *
+ *  |     ADC_EXTERNAL_TIG5     |     TIM4_TRGO          |      TIM15_TRGO         | *
+ *  |     ADC_EXTERNAL_TIG6     |     TIM6_TRGO          |      TIM6_TRGO          | *
+ *  |     ADC_EXTERNAL_TIG7     |     EXTi Line 11       |      EXTi Line 11       | */
+#define  ADC_SOFTWARE_START                           (0U)
+#define  ADC_EXTERNAL_TIG1                            (1U)
+#define  ADC_EXTERNAL_TIG2                            (2U)
+#define  ADC_EXTERNAL_TIG3                            (3U)
+#define  ADC_EXTERNAL_TIG4                            (4U)
+#define  ADC_EXTERNAL_TIG5                            (5U)
+#define  ADC_EXTERNAL_TIG6                            (6U)
+#define  ADC_EXTERNAL_TIG7                            (7U)
+
+
+/******************************** ADC results flag define for HAL level*******************************/
+#define HAL_ADC_EOC_FLAG            0x80000000
+#define HAL_ADC_JEOC_FLAG           0x40000000
+#define HAL_ADC_AWD_FLAG            0x20000000
+
+/**
+  * @brief  ADC handle Structure definition
+  */
+typedef struct __ADC_HandleTypeDef
+{
+    ADC_TypeDef                     *Instance;                              /*!< Register base address */
+    ADC_InitTypeDef                 Init;                                   /*!< ADC initialization parameters and regular conversions setting */
+    DMA_HandleTypeDef               *DMA_Handle;                            /*!< Pointer DMA Handler */
+    uint32_t                        ChannelNum;                             /*!< Total enable regular group channel number*/
+    uint32_t                        *AdcResults;                            /*!< Point to the convert results*/
+    void (*ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC conversion complete callback */
+    void (*GroupCpltCallback)(struct __ADC_HandleTypeDef *hadc);            /*!< ADC regular group conversion complete callback */
+    void (*InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC injected conversion complete callback */
+    void (*LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog callback */
+}ADC_HandleTypeDef;
+
+/******************************** ADC Instances *******************************/
+#define IS_ADC_ALL_INSTANCE(INSTANCE)    ((INSTANCE) == ADC)
+#define IS_ADC_ALL_CONCONVMODE(CONCONVMODE)     (((CONCONVMODE) == ADC_CONCONVMODE_DISABLE) || \
+                                                 ((CONCONVMODE) == ADC_CONCONVMODE_ENABLE))
+
+#define IS_ADC_ALL_JCHANNELMODE(JCHANNELMODE)    (((JCHANNELMODE) == ADC_JCHANNELMODE_DISABLE) || \
+                                                  ((JCHANNELMODE) == ADC_JCHANNELMODE_ENABLE))
+
+#define IS_ADC_ALL_DIFFMODE(DIFFMODE)            (((DIFFMODE) == ADC_DIFFMODE_DISABLE) || \
+                                                  ((DIFFMODE) == ADC_DIFFMODE_ENABLE))
+
+#define IS_ADC_ALL_DMAMODE(DMAMODE)              (((DMAMODE) == ADC_DMAMODE_DISABLE) || \
+                                                  ((DMAMODE) == ADC_DMAMODE_ENABLE))
+
+#define IS_ADC_ALL_OVERMODE(OVERMODE)            (((OVERMODE) == ADC_OVERMODE_DISABLE) || \
+                                                  ((OVERMODE) == ADC_OVERMODE_ENABLE))
+
+#define IS_ADC_ALL_OVERSAMPMODE(OVERSAMPMODE)    (((OVERSAMPMODE) == ADC_OVERSAMPMODE_DISABLE) || \
+                                                  ((OVERSAMPMODE) == ADC_OVERSAMPMODE_ENABLE))
+                                                  
+#define IS_ADC_ALL_OVSS(_OVSS)             (((_OVSS) == ADC_CR2_OVSS_0) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_1) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_2) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_3) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_4) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_5) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_6) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_7) || \
+                                            ((_OVSS) == ADC_CR2_OVSS_8))
+                                            
+#define IS_ADC_ALL_OVSR(_OVSR)             (((_OVSR) == ADC_CR2_OVSR_2X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_4X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_8X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_16X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_32X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_64X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_128X) || \
+                                            ((_OVSR) == ADC_CR2_OVSR_256X))
+                                            
+#define IS_ADC_ALL_ANALOGWDGEN(ANALOGWDGEN)      (((ANALOGWDGEN) == ADC_ANALOGWDGEN_DISABLE) || \
+                                                  ((ANALOGWDGEN) == ADC_ANALOGWDGEN_ENABLE))
+
+#define IS_ADC_ALL_CLOCKDIV(CLOCKDIV)      (((CLOCKDIV) == ADC_CLOCK_DIV1) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV2) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV3) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV4) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV5) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV6) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV7) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV8) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV9) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV10) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV11) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV12) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV13) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV14) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV15) || \
+                                            ((CLOCKDIV) == ADC_CLOCK_DIV16))
+
+#define IS_ADC_ALL_SEQUENCE(SEQUENCE)      (((SEQUENCE) == ADC_SEQUENCE_SQ1) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ2) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ3) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ4) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ5) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ6) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ7) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ8) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ9) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ10) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ11) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ12) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ13) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ14) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ15) || \
+                                            ((SEQUENCE) == ADC_SEQUENCE_SQ16))
+
+#define IS_ADC_ALL_CHANNEL(CHANNEL)        (((CHANNEL) == ADC_CHANNEL_0) || \
+                                            ((CHANNEL) == ADC_CHANNEL_1) || \
+                                            ((CHANNEL) == ADC_CHANNEL_2) || \
+                                            ((CHANNEL) == ADC_CHANNEL_3) || \
+                                            ((CHANNEL) == ADC_CHANNEL_4) || \
+                                            ((CHANNEL) == ADC_CHANNEL_5) || \
+                                            ((CHANNEL) == ADC_CHANNEL_6) || \
+                                            ((CHANNEL) == ADC_CHANNEL_7) || \
+                                            ((CHANNEL) == ADC_CHANNEL_8) || \
+                                            ((CHANNEL) == ADC_CHANNEL_9) || \
+                                            ((CHANNEL) == ADC_CHANNEL_10) || \
+                                            ((CHANNEL) == ADC_CHANNEL_11) || \
+                                            ((CHANNEL) == ADC_CHANNEL_12) || \
+                                            ((CHANNEL) == ADC_CHANNEL_13) || \
+                                            ((CHANNEL) == ADC_CHANNEL_14) || \
+                                            ((CHANNEL) == ADC_CHANNEL_15) || \
+                                            ((CHANNEL) == ADC_CHANNEL_TEMP) || \
+                                            ((CHANNEL) == ADC_CHANNEL_VBAT) || \
+                                            ((CHANNEL) == ADC_CHANNEL_VBGR) || \
+                                            ((CHANNEL) == ADC_CHANNEL_EXT2) || \
+                                            ((CHANNEL) == ADC_CHANNEL_EXT3))
+
+#define IS_ADC_ALL_CHANNELEN(CHANNELEN)    ((CHANNELEN) <= 0x1FFFFF)
+
+#define IS_ADC_ALL_SMPCLOCK(SMPCLOCK)      (((SMPCLOCK) == ADC_SMP_CLOCK_3) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_5) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_7) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_10) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_13) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_16) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_20) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_30) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_60) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_80) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_100) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_120) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_160) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_320) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_480) || \
+                                            ((SMPCLOCK) == ADC_SMP_CLOCK_640))
+                                            
+#define IS_ADC_ALL_TRIG(_TRIG)             (((_TRIG) == ADC_SOFTWARE_START) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG1) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG2) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG3) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG4) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG5) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG6) || \
+                                            ((_TRIG) == ADC_EXTERNAL_TIG7))
+
+#define IS_ADC_EVENT_TYPE(_EVENT)          (((_EVENT) == ADC_SR_AWD) || \
+                                            ((_EVENT) == ADC_SR_OVERF) || \
+                                            ((_EVENT) == ADC_SR_EOG) || \
+                                            ((_EVENT) == ADC_SR_JEOC) || \
+                                            ((_EVENT) == ADC_SR_EOC))
+
+/* Function : HAL_ADC_IRQHandler */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout);
+
+#endif
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_AES.h

@@ -0,0 +1,94 @@
+/***********************************************************************
+ * All rights reserved.
+ * Filename    : aes.h
+ * Description : aes driver header file
+ * Author(s)   : Eric  
+ * version     : V1.0
+ * Modify date : 2016-03-24
+ ***********************************************************************/
+#ifndef __AES_H__
+#define __AES_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define AES_ENCRYPTION   		1
+#define AES_DECRYPTION   		0
+#define AES_ECB_MODE	   		0
+#define AES_CBC_MODE	   		1 
+#define AES_SWAP_ENABLE  		1
+#define AES_SWAP_DISABLE 		0
+
+#define AES_NORMAL_MODE   	0x12345678
+#define AES_SECURITY_MODE 	0
+
+#define AES_KEY_128     0
+#define AES_KEY_192     1
+#define AES_KEY_256     2
+
+#define AES_FAIL   0x00
+#define AES_PASS   0xa59ada68
+
+#define BIT_AES        (1<<28)
+
+/************************************************************************
+ * function   : delay
+ * Description: delay for a while.  
+ * input : 
+ *         count: count to decrease 
+ * return: none 
+ ************************************************************************/
+ extern void delay(uint32_t count);
+ 
+
+/******************************************************************************
+ * Name:     HAL_AES_SetKey
+ * Function: set key of AES
+ * Input:
+		     keyin		 --	pointer to buffer of key 
+		     key_len     --	select length of key(AES_KEY_128/ AES_KEY_192/ AES_KEY_256) 					
+		     swap_en     -- AES_SWAP_ENABLE, AES_SWAP_DISABLE						
+ * Return:	 None
+*******************************************************************************/
+void HAL_AES_SetKey(UINT32 *keyin, UINT8 key_len, UINT8 swap_en);
+void HAL_AES_SetKey_U8(UINT8 *keyin, UINT8 key_len, UINT8 swap_en);
+
+
+/******************************************************************************
+Name:		 HAL_AES_Crypt
+Function:	 Function for AES encryption and decryption
+Input:
+         indata		       --   pointer to buffer of input
+         outdata	       --	pointer to buffer of result
+         block_len	       --	block(128bit) length for aes cryption
+         operation	       --	AES_ENCRYPTION,AES_DECRYPTION
+         mode              --   AES_ECB_MODE, AES_CBC_MODE,
+         iv                --   initial vector for CBC mode
+         security_mode     --   AES_NORMAL_MODE, AES_SECURITY_MDOE£¬
+Return:	 None
+
+*******************************************************************************/
+uint32_t HAL_AES_Crypt(
+    uint32_t *indata,
+    uint32_t *outdata,
+    uint32_t block_len,
+    uint8_t  operation,
+    uint8_t  mode,
+    uint32_t *iv,
+    uint32_t security_mode
+);
+
+
+uint32_t HAL_AES_Crypt_U8(
+    uint8_t *indata,
+    uint8_t *outdata,
+    uint32_t block_len,
+    uint8_t  operation,
+    uint8_t  mode,
+    uint8_t *iv,
+    uint32_t security_mode
+);
+
+#endif
+/******************************************************************************
+ * end of file
+*******************************************************************************/

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CAN.h

@@ -0,0 +1,394 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Can.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CAN_H__
+#define __HAL_CAN_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/**
+  * @}
+  */
+	
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+/******************************************************************************/
+/*                                    (CAN)                                   */
+/******************************************************************************/
+
+/****************  Bit definition for CAN MOD register  ***********************/
+#define CAN_MOD_RM                      BIT0
+#define CAN_MOD_LOM                     BIT1
+#define CAN_MOD_STM                     BIT2
+#define CAN_MOD_AFM                     BIT3
+#define CAN_MOD_SM                      BIT4
+/****************  Bit definition for CAN CMR register  ***********************/
+#define CAN_CMR_TR                      BIT0
+#define CAN_CMR_AT                      BIT1
+#define CAN_CMR_RRB                     BIT2
+#define CAN_CMR_CDO                     BIT3
+#define CAN_CMR_SRR                     BIT4
+/****************  Bit definition for CAN SR register  ***********************/
+#define CAN_SR_RBS                      BIT0
+#define CAN_SR_DOS                      BIT1
+#define CAN_SR_TBS                      BIT2
+#define CAN_SR_TCS                      BIT3
+#define CAN_SR_RS                       BIT4
+#define CAN_SR_TS                       BIT5
+#define CAN_SR_ES                       BIT6
+#define CAN_SR_BS                       BIT7
+/****************  Bit definition for CAN IR register  ***********************/
+#define CAN_IR_RI                       BIT0  
+#define CAN_IR_TI                       BIT1 
+#define CAN_IR_EI                       BIT2 
+#define CAN_IR_DOI                      BIT3 
+#define CAN_IR_WUI                      BIT4 
+#define CAN_IR_EPI                      BIT5 
+#define CAN_IR_ALI                      BIT6 
+#define CAN_IR_BEI                      BIT7 
+/****************  Bit definition for CAN IER register  ***********************/
+#define CAN_IER_RIE                     BIT0  
+#define CAN_IER_TIE                     BIT1 
+#define CAN_IER_EIE                     BIT2 
+#define CAN_IER_DOIE                    BIT3 
+#define CAN_IER_WUIE                    BIT4 
+#define CAN_IER_EPIE                    BIT5 
+#define CAN_IER_ALIE                    BIT6 
+#define CAN_IER_BEIE                    BIT7 
+
+/** 
+  * @brief  CAN  init structure definition
+  */
+typedef struct
+{
+    uint32_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                This parameter can be a value of 
+                                @ref CAN_mode  e.g:CAN_Mode_Normal   CAN_Mode_Normal*/ 
+    
+    uint32_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                the CAN hardware is allowed to lengthen or 
+                                shorten a bit to perform resynchronization.
+                                This parameter can be a value of 
+                                @ref CAN_SJW  e.g:CAN_SJW_1tq--CAN_SJW_4tq*/
+    
+    uint32_t CAN_BRP ;          /*!< Specifies the number of time quanta in Bit 
+                                Segment 1. This parameter can be a value between 0 and 63 */
+    
+    uint32_t CAN_TSEG1;          /*!< Specifies the number of time quanta in Bit 
+                                Segment 1. This parameter can be a value of 
+                                @ref CAN_TSEG1  e.g: CAN_TSEG1_1tq-CAN_TSEG1_16tq*/
+    
+    uint32_t CAN_TSEG2;          /*!< Specifies the number of time quanta in Bit 
+                                Segment 2.This parameter can be a value of 
+                                @ref CAN_TSEG2  e.g:CAN_TSEG1_1tq-CAN_TSEG16_tq*/
+    
+    uint32_t CAN_SAM ;           /*!< Specifies the CAN operating mode.
+                                This parameter can be a value of 
+                                @ref CAN_SAM e.g:CAN_SAM_1time  CAN_SAM_3time*/
+} CAN_InitTypeDef;
+
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+
+typedef struct
+{
+    uint32_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                        This parameter can be a value of 
+                                        @ref CAN_filter_mode  e.g:CAN_FilterMode_Dual    CAN_FilterMode_Single*/
+    
+    uint32_t CAN_FilterId1;             /*!< Specifies the filter identification number 
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+    
+    uint32_t CAN_FilterId2;             /*!< Specifies the filter identification number 
+                                        only CAN_FilterMode=CAN_FilterMode_Dual Enable
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+    
+    uint32_t CAN_FilterMaskId1;         /*!< Specifies the filter identification mask number 
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+    
+    uint32_t CAN_FilterMaskId2;         /*!< Specifies the filter identification mask number 
+                                        only CAN_FilterMode=CAN_FilterMode_Dual Enable
+                                        This parameter can be a value between 0x0000 and 0x1FFFFFFF */
+} CAN_FilterInitTypeDef;
+
+
+
+/** 
+  * @brief  CAN RxTxMessege structure definition
+  */
+typedef struct
+{
+    uint32_t StdId;                     /*!< Specifies the standard identifier.
+                                        This parameter can be a value between 0 to 0x7FF. */
+    
+    uint32_t ExtId;                     /*!< Specifies the extended identifier.
+                                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+    
+    uint32_t IDE;                        /*!< Specifies the type of identifier for the message that 
+                                        will be transmitted. This parameter can be a value 
+                                        of @ref CAN_identifier_type  e.g: CAN_Id_Standard  CAN_Id_Extended*/
+    
+    uint32_t RTR;                        /*!< Specifies the type of frame for the message that will 
+                                        be transmitted. This parameter can be a value of 
+                                        @ref CAN_remote_transmission    e.g: CAN_RTR_Data  CAN_RTR_Remote */
+    
+    uint32_t DLC;                        /*!< Specifies the length of the frame that will be 
+                                        transmitted. This parameter can be a value between 0 to 8 */
+    
+    uint8_t Data[8];                    /*!< Contains the data to be transmitted. It ranges from 0 to 0xFF. */
+} CanTxRxMsg;
+
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct __CAN_HandleTypeDef
+{
+    CAN_TypeDef         *Instance;                 /*!< Register base address */
+    
+    CAN_InitTypeDef      Init;                      /*!< CAN required parameters */
+    
+    CanTxRxMsg          *RxMessage;                 /*!< CAN RxMessage */
+    
+    void (*CAN_ReceiveIT_Callback)(struct __CAN_HandleTypeDef *hcan);     /* CAN  ReceiveIT complete callback */ 
+    
+    void (*CAN_TransmitIT_Callback)(struct __CAN_HandleTypeDef *hcan);     /* CAN TransmitIT complete callback */ 
+    
+} CAN_HandleTypeDef;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000001)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+/**
+  * @}
+  */
+/** @defgroup CAN_remote_transmission
+  * @{
+  */
+
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000001)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/**
+  * @}
+  */
+/** @defgroup CAN_TxRxMessege 
+  * @{
+  */
+
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_SR_RBS)  || ((FLAG) == CAN_SR_DOS)   || \
+                               ((FLAG) == CAN_SR_TBS)  || ((FLAG) == CAN_SR_TCS)   || \
+                               ((FLAG) == CAN_SR_RS)  || ((FLAG) == CAN_SR_TS)  || \
+                               ((FLAG) == CAN_SR_ES)  || ((FLAG) == CAN_SR_BS))	
+
+#define IS_CAN_BRP(BRP) 	(((BRP) >= 0) && ((BRP) <= 63))
+
+/**
+  * @defgroup CAN_Mode 
+  * @{
+  */  
+#define CAN_Mode_Normal         ((uint8_t)0x00) /*!< Normal mode */
+#define CAN_Mode_SlefTest       ((uint8_t)0x01) /*!< SlefTest mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) ||\
+                            ((MODE) == CAN_Mode_SlefTest))
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Operating_Mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Normal           ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Initialization   ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Listen           ((uint8_t)0x02) /*!< Listen mode */
+#define CAN_OperatingMode_SelfTest           ((uint8_t)0x04) /*!< Listen mode */
+#define CAN_OperatingMode_Sleep            ((uint8_t)0x10) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+                                    ((MODE) == CAN_OperatingMode_Sleep)|| \
+                                    ((MODE) == CAN_OperatingMode_SelfTest)|| \
+                                    ((MODE) == CAN_OperatingMode_Listen))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_SAM 
+  * @{
+  */
+
+#define CAN_SAM_1time       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SAM_3time       ((uint8_t)0x01)  /*!< 2 time quantum */
+
+#define IS_CAN_SAM(SAM)     (((SAM) == CAN_SAM_1time) || ((SAM) == CAN_SAM_3time))
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+
+#define CAN_SJW_1tq         ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq         ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq         ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq         ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+	
+	/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+
+#define CAN_TSEG1_1tq       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_TSEG1_2tq       ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_TSEG1_3tq       ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_TSEG1_4tq       ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_TSEG1_5tq       ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_TSEG1_6tq       ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_TSEG1_7tq       ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_TSEG1_8tq       ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_TSEG1_9tq       ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_TSEG1_10tq      ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_TSEG1_11tq      ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_TSEG1_12tq      ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_TSEG1_13tq      ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_TSEG1_14tq      ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_TSEG1_15tq      ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_TSEG1_16tq      ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_TSEG1(TSEG1) ((TSEG1) <= CAN_TSEG1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+
+#define CAN_TSEG2_1tq       ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_TSEG2_2tq       ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_TSEG2_3tq       ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_TSEG2_4tq       ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_TSEG2_5tq       ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_TSEG2_6tq       ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_TSEG2_7tq       ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_TSEG2_8tq       ((uint8_t)0x07)  /*!< 8 time quantum */
+#define IS_CAN_TSEG2(TSEG) ((TSEG) <= CAN_TSEG2_8tq)
+/**
+  * @}
+  */
+
+	  
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FilterMode_Dual         ((uint8_t)0x00)  /*!< identifier list mode */
+#define CAN_FilterMode_Single       ((uint8_t)0x01)  /*!< identifier/mask mode */
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_Dual) || \
+                                  ((MODE) == CAN_FilterMode_Single))
+
+	/**
+  * @}
+  */
+
+/** @defgroup CAN_ErrorCode 
+  * @{
+  */
+#define CAN_ErrorType_ErrCode         ((uint8_t)0xC0)  /*!< identifier list mode */
+#define CAN_ErrorType_Direction       ((uint8_t)0x20)  /*!< identifier/mask mode */
+#define CAN_ErrorType_SegCode      		 ((uint8_t)0x1F)  /*!< identifier/mask mode */
+#define IS_CAN_ErrorType(ErrorType) (((ErrorType) == CAN_ErrorType_ErrCode) || \
+                                    ((ErrorType) == CAN_ErrorType_Direction)|| \
+                                    ((ErrorType) == CAN_ErrorType_SegCode))
+/**
+  * @}
+  */
+/* Initialization and Configuration functions *********************************/
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+
+/* Transmit functions *********************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage);
+
+void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan);
+
+/* Receive functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage);
+
+/* Operation modes functions **************************************************/
+HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode);
+
+void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+
+/* Error Code management functions **********************************/
+int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type);
+
+int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan);
+
+int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan);
+
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_COMP.h

@@ -0,0 +1,216 @@
+/*
+  ******************************************************************************
+  * @file    HAL_COMP.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_COMP_H__
+#define __HAL_COMP_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define COMP1        (0x01)
+#define COMP2        (0x02)
+
+/****************  Bit definition for COMP_CR1 and COMP_CR2 register  **************************/
+#define COMP_CR_LOCK                            (BIT31)
+#define COMP_CR_BLANKTIME_POS                   (29U)
+#define COMP_CR_BLANKTIME_MASK                  (BIT30|BIT29)
+#define COMP_CR_CRV_CFG_POS                     (25U)
+#define COMP_CR_CRV_CFG_MASK                    (BIT28|BIT27|BIT26|BIT25)
+#define COMP_CR_CRV_SEL                         (BIT24)
+#define COMP_CR_CRV_EN                          (BIT23)
+#define COMP_CR_WINMODE                         (BIT22)
+#define COMP_CR_WINOUT                          (BIT21)
+#define COMP_CR_POLARITY                        (BIT20)
+#define COMP_CR_FLTEN                           (BIT19)
+#define COMP_CR_FLTTIME_POS                     (16U)
+#define COMP_CR_FLTTIME_MASK                    (BIT18|BIT17|BIT16)
+#define COMP_CR_BLANKSEL_POS                    (12U)
+#define COMP_CR_BLANKSEL_MASK                   (BIT15|BIT14|BIT13|BIT12)
+#define COMP_CR_INPSEL_POS                      (8U)
+#define COMP_CR_INPSEL_MASK                     (BIT11|BIT10|BIT9|BIT8)
+#define COMP_CR_INMSEL_POS                      (4U)
+#define COMP_CR_INMSEL_MASK                     (BIT7|BIT6|BIT5|BIT4)
+#define COMP_CR_HYS_POS                         (1U)
+#define COMP_CR_HYS_MASK                        (BIT3|BIT2|BIT1)
+#define COMP_CR_EN                              (BIT0)
+
+/****************  Bit definition for COMP_SR register  **************************/
+#define COMP_SR_VCOUT2_ORG                      (BIT3)
+#define COMP_SR_VCOUT1_ORG                      (BIT2)
+#define COMP_SR_VCOUT2                          (BIT1)
+#define COMP_SR_VCOUT1                          (BIT0)
+
+/**
+  * @brief  COMP Configuration Structure definition
+  */
+typedef struct
+{
+    uint8_t             Comparator;        /*!< Specify witch comparator be selected */
+    uint32_t            Crv_En;        
+    uint32_t            BlankTime;        
+    uint32_t            Crv_Sel;        
+    uint32_t            Crv_Cfg;
+    uint32_t            WinMode;
+    uint32_t            WinOut;
+    uint32_t            Polarity;
+    uint32_t            FltEn;
+    uint32_t            FltTime;
+    uint32_t            BlankSel;
+    uint32_t            InPSel;
+    uint32_t            InMSel;
+    uint32_t            HYS;
+}COMP_InitTypeDef;
+
+/**
+  * @brief  COMP handle Structure definition
+  */
+typedef struct
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  uint8_t            OutputLevel_Org; /*!< COMP OutputLevel original */
+  uint8_t            OutputLevel;     /*!< COMP OutputLevel with filter */
+} COMP_HandleTypeDef;
+
+#define COMP_CR_CRV_EN_DISABLE           (0U)       
+#define COMP_CR_CRV_EN_ENABLE            (1U)   
+
+#define COMP_CR_CRV_SEL_AVDD             (0U)       
+#define COMP_CR_CRV_SEL_VREF             (1U)  
+
+#define COMP_CR1_WINMODE_COMP1_INPSEL           (0U)       
+#define COMP_CR1_WINMODE_COMP2_INPSEL           (1U)   
+
+#define COMP_CR2_WINMODE_COMP2_INPSEL           (0U)       
+#define COMP_CR2_WINMODE_COMP1_INPSEL           (1U)   
+
+#define COMP_CR1_WINOUT_VCOUT1                 (0U)       
+#define COMP_CR2_WINOUT_VCOUT2                 (0U)       
+#define COMP_CR_WINOUT_VCOUT12                 (1U)   
+
+#define COMP_CR_POLARITY_P                     (0U)   
+#define COMP_CR_POLARITY_N                     (1U)   
+
+#define COMP_CR_FLTEN_DISABLE                  (0U)       
+#define COMP_CR_FLTEN_ENABLE                   (1U)   
+
+#define COMP_CR_FLTTIME_1_CLK                  (0U)   
+#define COMP_CR_FLTTIME_2_CLK                  (1U)   
+#define COMP_CR_FLTTIME_4_CLK                  (2U)   
+#define COMP_CR_FLTTIME_16_CLK                 (3U)   
+#define COMP_CR_FLTTIME_64_CLK                 (4U)   
+#define COMP_CR_FLTTIME_256_CLK                (5U)   
+#define COMP_CR_FLTTIME_1024_CLK               (6U)   
+#define COMP_CR_FLTTIME_4095_CLK               (7U)   
+
+#define COMP_CR_BLANKTIME_32_CLK               (0U)   
+#define COMP_CR_BLANKTIME_64_CLK               (1U)   
+#define COMP_CR_BLANKTIME_128_CLK              (2U)   
+#define COMP_CR_BLANKTIME_256_CLK              (3U)   
+
+#define COMP_CR_BLANKSEL_NONE                  (0U)   
+#define COMP_CR_BLANKSEL_1                     (1U)   
+#define COMP_CR_BLANKSEL_2                     (2U)   
+#define COMP_CR_BLANKSEL_3                     (4U)   
+#define COMP_CR_BLANKSEL_4                     (8U)   
+
+#define COMP_CR_INPSEL_0                      (0U)   
+#define COMP_CR_INPSEL_1                      (1U)   
+#define COMP_CR_INPSEL_2                      (2U)   
+
+#define COMP_CR_INMSEL_0                      (0U)   
+#define COMP_CR_INMSEL_1                      (1U)   
+#define COMP_CR_INMSEL_2                      (2U)   
+#define COMP_CR_INMSEL_3                      (3U)   
+
+#define COMP_CR_HYS_DISABLE                   (0U) 
+#define COMP_CR_HYS_1                         (4U) 
+#define COMP_CR_HYS_2                         (5U) 
+#define COMP_CR_HYS_3                         (6U) 
+#define COMP_CR_HYS_4                         (7U) 
+
+/******************************** COMP Instances *******************************/
+#define IS_COMP_ALL_INSTANCE(INSTANCE)    ((INSTANCE) == COMP)
+#define IS_COMP_ALL_COMP(_COMP)     (((_COMP) == COMP1) || \
+                                  ((_COMP) == COMP2))
+
+#define IS_COMP_ALL_CRV_EN(_CRV_EN)        (((_CRV_EN) == COMP_CR_CRV_EN_DISABLE) || \
+                                           ((_CRV_EN) == COMP_CR_CRV_EN_ENABLE))
+
+#define IS_COMP_ALL_CRV_SEL(_CRV_SEL)      (((_CRV_SEL) == COMP_CR_CRV_SEL_AVDD) || \
+                                           ((_CRV_SEL) == COMP_CR_CRV_SEL_VREF))
+
+#define IS_COMP_ALL_CRV_CFG(_CRV_CFG)      ((_CRV_CFG) <= 15U)
+                                           
+#define IS_COMP_ALL_WINMODE(WINMODE)       (((WINMODE) == COMP_CR1_WINMODE_COMP1_INPSEL) || \
+                                           ((WINMODE) == COMP_CR1_WINMODE_COMP2_INPSEL) || \
+                                           ((WINMODE) == COMP_CR2_WINMODE_COMP2_INPSEL) || \
+                                           ((WINMODE) == COMP_CR2_WINMODE_COMP1_INPSEL))
+                                           
+#define IS_COMP_ALL_WINOUT(_WINOUT)        (((_WINOUT) == COMP_CR1_WINOUT_VCOUT1) || \
+                                           ((_WINOUT) == COMP_CR2_WINOUT_VCOUT2) || \
+                                           ((_WINOUT) == COMP_CR_WINOUT_VCOUT12))
+                                           
+#define IS_COMP_ALL_POLARITY(POLARITY)     (((POLARITY) == COMP_CR_POLARITY_N) || \
+                                           ((POLARITY) == COMP_CR_POLARITY_P))
+
+#define IS_COMP_ALL_FLTEN(FLTEN)           (((FLTEN) == COMP_CR_FLTEN_DISABLE) || \
+                                           ((FLTEN) == COMP_CR_FLTEN_ENABLE))
+
+#define IS_COMP_ALL_FLTTIME(FLTTIME)       (((FLTTIME) == COMP_CR_FLTTIME_1_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_2_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_4_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_16_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_64_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_256_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_1024_CLK) || \
+                                           ((FLTTIME) == COMP_CR_FLTTIME_4095_CLK))
+
+#define IS_COMP_ALL_BLANKTIME(BLANKTIME)   (((BLANKTIME) == COMP_CR_BLANKTIME_32_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_64_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_128_CLK) || \
+                                           ((BLANKTIME) == COMP_CR_BLANKTIME_256_CLK))
+
+#define IS_COMP_ALL_BLANKSEL(BLANKSEL)     (((BLANKSEL) == COMP_CR_BLANKSEL_NONE) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_1) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_2) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_3) || \
+                                           ((BLANKSEL) == COMP_CR_BLANKSEL_4))
+
+#define IS_COMP_ALL_INPSEL(INPSEL)         (((INPSEL) == COMP_CR_INPSEL_0) || \
+                                           ((INPSEL) == COMP_CR_INPSEL_1) || \
+                                           ((INPSEL) == COMP_CR_INPSEL_2))   
+
+#define IS_COMP_ALL_INMSEL(INMSEL)         (((INMSEL) == COMP_CR_INMSEL_0 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_1 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_2 ) || \
+                                           ((INMSEL) == COMP_CR_INMSEL_3 ))
+
+#define IS_COMP_ALL_HYS(_HYS)              (((_HYS) == COMP_CR_HYS_DISABLE) || \
+                                           ((_HYS) == COMP_CR_HYS_1) || \
+                                           ((_HYS) == COMP_CR_HYS_2) || \
+                                           ((_HYS) == COMP_CR_HYS_3) || \
+                                           ((_HYS) == COMP_CR_HYS_4))
+
+/* Function */
+void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp);
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp);
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+
+#endif
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_CRC.h

@@ -0,0 +1,154 @@
+/*
+  ******************************************************************************
+  * @file    HAL_CRC.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of CRC HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_CRC_H__
+#define __HAL_CRC_H__
+#include  "ACM32Fxx_HAL.h"
+
+/** @defgroup CRC POLY Reverse
+  * @{
+  */ 
+ #define CRC_POLY_REV_EN                    (0x00000400U)    /*!< Poly Reverse Enable */
+ #define CRC_POLY_REV_DIS                   (0x00000000U)    /*!< Poly Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC OUTXOR Reverse
+  * @{
+  */ 
+ #define CRC_OUTXOR_REV_EN                   (0x00000200U)    /*!< OUTXOR Reverse Enable */
+ #define CRC_OUTXOR_REV_DIS                  (0x00000000U)    /*!< OUTXOR Reverse Disable */
+/**
+  * @}
+  */
+ 
+/** @defgroup CRC INIT Reverse
+  * @{
+  */ 
+ #define CRC_INIT_REV_EN                     (0x00000100U)    /*!< INIT Reverse Enable */
+ #define CRC_INIT_REV_DIS                    (0x00000000U)    /*!< INIT Reverse Disable */
+/**
+  * @}
+  */
+  
+/** @defgroup CRC RSLT Reverse
+  * @{
+  */ 
+ #define CRC_RSLT_REV_EN                     (0x00000080U)    /*!< RSLT Reverse Enable */
+ #define CRC_RSLT_REV_DIS                    (0x00000000U)    /*!< RSLT Reverse Disable */
+/**
+  * @}
+  */
+
+/** @defgroup CRC DATA Reverse
+  * @{
+  */ 
+ #define CRC_DATA_REV_DISABLE                (0x00000000U)    /*!< DATA Reverse Disable */
+ #define CRC_DATA_REV_BY_BYTE                (0x00000020U)    /*!< DATA Reverse By Byte */
+ #define CRC_DATA_REV_BY_HALFWORD            (0x00000040U)    /*!< DATA Reverse By HalfWord */
+ #define CRC_DATA_REV_BY_WORD                (0x00000060U)    /*!< DATA Reverse By Word */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Poly Len
+  * @{
+  */ 
+ #define CRC_POLTY_LEN_32                    (0x00000000U)    /*!< POLY len = 32bit */
+ #define CRC_POLTY_LEN_16                    (0x00000008U)    /*!< POLY len = 16bit */
+ #define CRC_POLTY_LEN_8                     (0x00000010U)    /*!< POLY len = 8bit  */
+ #define CRC_POLTY_LEN_7                     (0x00000018U)    /*!< POLY len = 7bit  */
+/**
+  * @}
+  */
+
+/** @defgroup CRC Data Len
+  * @{
+  */ 
+ #define CRC_DATA_LEN_1B                    (0x00000000U)    /*!< DATA len = 1 Byte */
+ #define CRC_DATA_LEN_2B                    (0x00000002U)    /*!< DATA len = 2 Byte */
+ #define CRC_DATA_LEN_3B                    (0x00000004U)    /*!< DATA len = 3 Byte */
+ #define CRC_DATA_LEN_4B                    (0x00000006U)    /*!< DATA len = 4 Byte */
+/**
+  * @}
+  */
+
+/** @defgroup CRC RST
+  * @{
+  */ 
+ #define CRC_RST_EN                          (0x00000001U)    /*!< RST CRC_DATA To CRC_INIT */
+ #define CRC_RST_DIS                         (0x00000000U)    /*!< RST CRC_DATA To CRC_INIT */
+
+/**
+  * @}
+  */
+  
+/*
+ * @brief CRC Init Structure definition
+ */
+typedef struct
+{
+    uint32_t PolyRev;                  /*!< Specifies if the Poly is reversed in CRC
+                                            This parameter can be a value of @ref CRC POLY Reverse. */
+    uint32_t OutxorRev;                /*!< Specifies if the Outxor is reversed in CRC
+                                            This parameter can be a value of @ref CRC OUTXOR Reverse. */
+    uint32_t InitRev;                  /*!< Specifies if the Init is reversed in CRC
+                                            This parameter can be a value of @ref CRC INIT Reverse. */
+    uint32_t RsltRev;                  /*!< Specifies if the Result is reversed in CRC
+                                            This parameter can be a value of @ref CRC RSLT Reverse. */
+    uint32_t DataRev;                  /*!< Specifies if the Data is reversed in CRC
+                                            This parameter can be a value of @ref CRC DATA Reverse. */
+    uint32_t PolyLen;                  /*!< Specifies the Poly Len in CRC
+                                            This parameter can be a value of @ref CRC Poly Len. */
+    uint32_t DataLen;                  /*!< Specifies the Data Len in CRC
+                                            This parameter can be a value of @ref CRC Data Len. */
+    uint32_t RST;                      /*!< Specifies if CRC is reset
+                                            This parameter can be a value of @ref CRC RST. */
+	
+    uint32_t InitData;                 /*!< This member configures the InitData. */
+	
+    uint32_t OutXorData;               /*!< This member configures the OutXorData. */
+	
+    uint32_t PolyData;                 /*!< This member configures the PolyData. */
+	
+    uint32_t FData;                    /*!< This member configures the FData. */
+	
+}CRC_InitTypeDef;
+
+/*
+ * @brief  UART handle Structure definition
+ */
+typedef struct
+{
+    CRC_TypeDef           *Instance;                /*!< CRC registers base address  */
+
+    CRC_InitTypeDef        Init;                    /*!< CRC calculate parameters  */
+	
+    uint8_t* CRC_Data_Buff;                         /*!< CRC databuff base address */
+	
+    uint32_t CRC_Data_Len;                          /*!< amount of CRC data to be calculated */
+    
+}CRC_HandleTypeDef;  
+  
+ 
+/*********************************************************************************
+* Function    : HAL_CRC_Calculate
+* Description : Calculate the crc calue of input data.
+* Input       : hcrc: CRC handle.
+* Output      : CRC value
+* Author      : cl                        Data : 2021 
+**********************************************************************************/
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc);  
+
+
+#endif
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DAC.h

@@ -0,0 +1,589 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Can.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_DAC_H__
+#define __HAL_DAC_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/**
+  * @}
+  */
+	
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+/******************************************************************************/
+/*                                    (DAC)                                   */
+/******************************************************************************/
+
+/****************  Bit definition for DAC CR register  ***********************/
+#define DAC_CR_EN1_Pos              (0U)
+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */
+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */
+
+#define DAC_CR_TEN1_Pos             (2U)
+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */
+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */
+
+#define DAC_CR_TSEL1_Pos            (3U)
+#define DAC_CR_TSEL1_Msk            (0x7UL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */
+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[3:0] (DAC channel1 Trigger selection) */
+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000004 */
+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000008 */
+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                /*!< 0x00000010 */
+
+#define DAC_CR_WAVE1_Pos            (6U)
+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */
+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000040 */
+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                /*!< 0x00000080 */
+
+#define DAC_CR_MAMP1_Pos            (8U)
+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */
+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000100 */
+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000200 */
+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000400 */
+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                /*!< 0x00000800 */
+
+#define DAC_CR_DMAEN1_Pos           (12U)
+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */
+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */
+
+#define DAC_CR_DMAUDRIE1_Pos        (13U)
+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */
+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/
+
+#define DAC_CR_CEN1_Pos             (14U)
+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */
+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/
+
+#define DAC_CR_EN2_Pos              (16U)
+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */
+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */
+
+#define DAC_CR_TEN2_Pos             (18U)
+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */
+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */
+
+#define DAC_CR_TSEL2_Pos            (19U)
+#define DAC_CR_TSEL2_Msk            (0x7UL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */
+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                /*!< 0x00040000 */
+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                /*!< 0x00080000 */
+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                /*!< 0x00100000 */
+
+#define DAC_CR_WAVE2_Pos            (22U)
+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */
+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                /*!< 0x00400000 */
+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                /*!< 0x00800000 */
+
+#define DAC_CR_MAMP2_Pos            (24U)
+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */
+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                /*!< 0x01000000 */
+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                /*!< 0x02000000 */
+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                /*!< 0x04000000 */
+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                /*!< 0x08000000 */
+
+#define DAC_CR_DMAEN2_Pos           (28U)
+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */
+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */
+
+#define DAC_CR_DMAUDRIE2_Pos        (29U)
+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */
+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/
+
+#define DAC_CR_CEN2_Pos             (30U)
+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */
+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/
+
+/****************  Bit definition for DAC SWTRIGR register  ***********************/
+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)
+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */
+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */
+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)
+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */
+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */
+
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/
+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)
+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/
+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)
+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R1 register  ******************/
+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)
+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/
+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)
+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/
+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)
+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8R2 register  ******************/
+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)
+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12RD register  ******************/
+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)
+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */
+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */
+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)
+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */
+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */
+
+/*****************  Bit definition for DAC_DHR12LD register  ******************/
+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)
+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */
+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */
+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)
+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */
+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */
+
+/******************  Bit definition for DAC_DHR8RD register  ******************/
+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)
+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */
+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */
+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)
+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */
+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */
+
+/*******************  Bit definition for DAC_DOR1 register  *******************/
+#define DAC_DOR1_DACC1DOR_Pos       (0U)
+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */
+
+/*******************  Bit definition for DAC_DOR2 register  *******************/
+#define DAC_DOR2_DACC2DOR_Pos       (0U)
+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */
+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */
+
+/********************  Bit definition for DAC_SR register  ********************/
+#define DAC_SR_SAMOV1_Pos          (8U)
+#define DAC_SR_SAMOV1_Msk          (0x1UL << DAC_SR_SAMOV1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_SAMOV1               DAC_SR_SAMOV1_Msk                         /*!<DAC channel1 DMA SAMOV1 flag */
+
+#define DAC_SR_DMAUDR1_Pos          (13U)
+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */
+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */
+
+#define DAC_SR_CAL_FLAG1_Pos        (14U)
+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */
+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */
+
+#define DAC_SR_SAMOV2_Pos          (24U)
+#define DAC_SR_SAMOV2_Msk          (0x1UL << DAC_SR_SAMOV2_Pos)              /*!< 0x00002000 */
+#define DAC_SR_SAMOV2               DAC_SR_SAMOV2_Msk                         /*!<DAC channel1 DMA SAMOV1 flag */
+
+#define DAC_SR_DMAUDR2_Pos          (29U)
+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */
+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */
+#define DAC_SR_CAL_FLAG2_Pos        (30U)
+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */
+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */
+
+/****************  Bit definition for DAC CCR register  ***********************/
+#define DAC_CCR_OTRIM1_Pos          (0U)
+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */
+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */
+#define DAC_CCR_OTRIM2_Pos          (16U)
+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */
+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */
+
+/*******************  Bit definition for DAC_MCR register  *******************/
+#define DAC_MCR_MODE1_Pos           (0U)
+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */
+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */
+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000001 */
+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000002 */
+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000004 */
+
+#define DAC_MCR_MODE2_Pos           (16U)
+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */
+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */
+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)               /*!< 0x00010000 */
+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)               /*!< 0x00020000 */
+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)               /*!< 0x00040000 */
+
+
+/******************  Bit definition for DAC_SHSR1 register  ******************/
+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)
+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */
+
+/******************  Bit definition for DAC_SHSR2 register  ******************/
+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)
+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */
+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */
+
+/******************  Bit definition for DAC_SHHR register  ******************/
+#define DAC_SHHR_THOLD1_Pos         (0U)
+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */
+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */
+#define DAC_SHHR_THOLD2_Pos         (16U)
+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */
+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */
+
+/******************  Bit definition for DAC_SHRR register  ******************/
+#define DAC_SHRR_TREFRESH1_Pos      (0U)
+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */
+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */
+#define DAC_SHRR_TREFRESH2_Pos      (16U)
+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */
+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */
+/**
+  * @brief   DAC Configuration sample and hold Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+}
+DAC_SampleAndHoldConfTypeDef;
+
+typedef struct
+{
+  uint32_t DAC_Calibration ;          /*!< Specifies the Sample time for the selected channel.
+                                          This parameter can be a value of @ref DAC_Calibration */
+
+  uint32_t DAC_Calibration_TRIM ;            /*!< Specifies the hold time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+}
+DAC_CalibrationConfTypeDef;
+
+/**
+  * @brief   DAC Configuration regular Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
+                                              This parameter can be a value of @ref DAC_SampleAndHold */
+
+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref DAC_output_buffer */
+  
+
+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
+
+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
+                                              This parameter must be a value of @ref DAC_UserTrimming
+                                              DAC_UserTrimming is either factory or user trimming */
+
+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
+
+} DAC_ChannelConfTypeDef;
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct 
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+    
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
+    
+
+} DAC_HandleTypeDef;
+
+
+#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC))
+
+
+
+/** @defgroup DAC_SampleAndHold DAC power mode
+  * @{
+  */
+#define IS_DAC_SAMPLETIME(TIME)                 ((TIME) <= 0x000003FFU)
+#define IS_DAC_HOLDTIME(TIME)                   ((TIME) <= 0x000003FFU)
+#define IS_DAC_REFRESHTIME(TIME)                 ((TIME) <= 0x000000FFU)
+
+
+/** @defgroup DAC_CHANNEL 
+  * @{
+  */
+
+#define DAC_CHANNEL_1                        0x00000000U
+#define DAC_CHANNEL_2                        0x00000010U
+#define DAC_CHANNEL_Dual                     0x00000020U
+#define IS_DAC_CHANNEL(CHANNEL)             (((CHANNEL) == DAC_CHANNEL_1) || \
+                                            ((CHANNEL) == DAC_CHANNEL_2) || \
+                                            ((CHANNEL) == DAC_CHANNEL_Dual))
+/**
+  * @}
+  */
+
+  /** @defgroup DAC_trigger 
+  * @{
+  */                                             
+#define DAC_TRIGGER_T6_TRGO          (0x00000000U| DAC_CR_TEN1)      
+#define DAC_TRIGGER_T3_TRGO         ( DAC_CR_TSEL1_0| DAC_CR_TEN1)  
+#define DAC_TRIGGER_T7_TRGO         ( DAC_CR_TSEL1_1| DAC_CR_TEN1 )  
+#define DAC_TRIGGER_T15_TRGO        ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0| DAC_CR_TEN1) 
+#define DAC_TRIGGER_T2_TRGO         ( DAC_CR_TSEL1_2 | DAC_CR_TEN1)   
+#define DAC_TRIGGER_T1_TRGO         ( DAC_CR_TSEL1_2  | DAC_CR_TSEL1_0| DAC_CR_TEN1)   
+#define DAC_TRIGGER_EXT_IT9         ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1| DAC_CR_TEN1 )   
+#define DAC_TRIGGER_SOFTWARE        ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0| DAC_CR_TEN1)   
+#define IS_DAC_TRIGGER(TRIGGER)     (((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                    ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
+                                    ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                    ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
+                                    ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                     ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
+                                     ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                     ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None             0x00000000U
+#define DAC_WaveGeneration_Noise            0x00000001U
+#define DAC_WaveGeneration_Triangle         0x00000002U
+#define IS_DAC_GENERATE_WAVE(WAVE)      (((WAVE) == DAC_WaveGeneration_None) || \
+                                        ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                        ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                0x00000000U                                                         /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            0x00000000U                                                         /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE)      (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                          ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                          ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+/**
+  * @}
+  */
+  
+  /** @defgroup DAC_MODE
+  * @{
+  */
+
+#define DAC_Mode_Normal_BufferEnable_OutPAD                                   0x00000000U
+#define DAC_Mode_Normal_BufferEnable_OutPAD_OutInternal                       0x00000001U
+#define DAC_Mode_Normal_BufferDisable_OutPAD                                  0x00000002U
+#define DAC_Mode_Normal_BufferDisable_OutPAD_OutInternal                      0x00000003U
+
+#define DAC_Mode_SampleAndHold_BufferEnable_OutPAD                            0x00000004U
+#define DAC_Mode_SampleAndHold_BufferEnable_OutPAD_OutInternal                0x00000005U
+#define DAC_Mode_SampleAndHold_BufferDisable_OutPAD_OutInternal               0x00000006U
+#define DAC_Mode_SampleAndHold_BufferDisable_OutInternal                      0x00000007U
+#define IS_DAC_MODE(MODE)               (((MODE) == DAC_Mode_Normal_BufferEnable_OutPAD) || \
+                                        ((MODE) == DAC_Mode_Normal_BufferEnable_OutPAD_OutInternal) || \
+                                        ((MODE) == DAC_Mode_Normal_BufferDisable_OutPAD)|| \
+                                        ((MODE) == DAC_Mode_Normal_BufferDisable_OutPAD_OutInternal)|| \
+                                        ((MODE) == DAC_Mode_SampleAndHold_BufferEnable_OutPAD)|| \
+                                        ((MODE) == DAC_Mode_SampleAndHold_BufferEnable_OutPAD_OutInternal)|| \
+                                        ((MODE) == DAC_Mode_SampleAndHold_BufferDisable_OutPAD_OutInternal)|| \
+                                        ((MODE) == DAC_Mode_SampleAndHold_BufferDisable_OutInternal))
+/**
+  * @}
+  */
+  
+  /** @defgroup DAC_SampleAndHold DAC power mode
+  * @{
+  */
+#define DAC_SAMPLEANDHOLD_DISABLE     0x00000000U
+#define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
+  #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
+                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
+/**
+  * @}
+  */
+
+                                    
+  /** @defgroup DAC_UserTrimming DAC User Trimming
+* @{
+*/
+
+#define DAC_TRIMMING_FACTORY        0x00000000U           /*!< Factory trimming */
+#define DAC_TRIMMING_USER           0x00000001U           /*!< User trimming */
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+                                     ((TRIMMING) == DAC_TRIMMING_USER))
+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+/**
+  * @}
+  */
+  
+  /** @defgroup DAC_Calibration 
+  * @{
+  */
+
+#define DAC_Calibration_Disable                  0x00000000U
+#define DAC_Calibration_Enable                   0x00000001U
+#define IS_DAC_Calibration(Calibration)         (((Calibration) == DAC_Calibration_Disable) || \
+                                                ((Calibration) == DAC_Calibration_Enable))
+                                    
+#define IS_DAC_Calibration_TRIM(TRIM)            ((TRIM) <= 0x1FU)                                  
+/**
+  * @}
+  */
+  /** @defgroup DAC_output_buffer DAC output buffer
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
+#define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
+ #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+/**
+  * @}
+  */
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+  * @{
+  */
+#define DAC_CHIPCONNECT_DISABLE    0x00000000U
+#define DAC_CHIPCONNECT_ENABLE     (DAC_MCR_MODE1_0)
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))     
+/**
+  * @}
+  */
+                          
+                                           
+  /** @defgroup DAC_data_alignment DAC data alignment
+  * @{
+  */
+
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__)        (0x00000008U + (__ALIGNMENT__))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__)        (0x00000014U + (__ALIGNMENT__))
+
+
+
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__)        (0x00000020U + (__ALIGNMENT__))
+
+#define DAC_ALIGN_12B_R                    0x00000000U
+#define DAC_ALIGN_12B_L                    0x00000004U
+#define DAC_ALIGN_8B_R                     0x00000008U
+#define IS_DAC_ALIGN(ALIGN)               (((ALIGN) == DAC_ALIGN_12B_R) || \
+                                         ((ALIGN) == DAC_ALIGN_12B_L) || \
+                                         ((ALIGN) == DAC_ALIGN_8B_R))
+/**
+  * @}
+  */
+  
+  
+  
+  
+/* Initialization/de-initialization functions *********************************/
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);  
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); 
+
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+
+/* I/O operation functions ****************************************************/ 
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude) ;
+ 
+ 
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+ 
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_DMA.h

@@ -0,0 +1,297 @@
+/*
+  ******************************************************************************
+  * @file    HAL_DMA.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_DMA_H__
+#define __HAL_DMA_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define DMA_CHANNEL_NUM     (8)
+
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+
+/****************  Bit definition for DMA CONFIG register  ***********************/
+#define DMA_CONFIG_M2ENDIAN             BIT2
+#define DMA_CONFIG_M1ENDIAN             BIT1
+#define DMA_CONFIG_EN                   BIT0
+
+/****************  Bit definition for DMA Channel CTRL register  ***********************/
+#define DMA_CHANNEL_CTRL_ITC            BIT31
+#define DMA_CHANNEL_CTRL_DI             BIT27
+#define DMA_CHANNEL_CTRL_SI             BIT26
+
+
+/****************  Bit definition for DMA Channel CONFIG register  ***********************/
+#define DMA_CHANNEL_CONFIG_DEST_PERIPH         (BIT19|BIT20|BIT21|BIT22|BIT23|BIT24)
+#define DMA_CHANNEL_CONFIG_DEST_PERIPH_POS     (19)
+#define DMA_CHANNEL_CONFIG_HALT                 BIT18
+#define DMA_CHANNEL_CONFIG_ACTIVE               BIT17
+#define DMA_CHANNEL_CONFIG_LOCK                 BIT16
+#define DMA_CHANNEL_CONFIG_ITC                  BIT15
+#define DMA_CHANNEL_CONFIG_IE                   BIT14
+#define DMA_CHANNEL_CONFIG_FLOW_CTRL           (BIT11|BIT12|BIT13)
+#define DMA_CHANNEL_CONFIG_SRC_PERIPH          (BIT1|BIT2|BIT3|BIT4|BIT5|BIT6)
+#define DMA_CHANNEL_CONFIG_SRC_PERIPH_POS      (1)
+#define DMA_CHANNEL_CONFIG_EN                   BIT0
+
+/** @defgroup DMA_DATA_FLOW
+ *  @{
+ */
+#define    DMA_DATA_FLOW_M2M    (0x00000000)
+#define    DMA_DATA_FLOW_M2P    (0x00000800)
+#define    DMA_DATA_FLOW_P2M    (0x00001000)
+/**
+  * @}
+  */
+
+
+/** @defgroup REQUEST_ID
+ *  @{
+ */
+#define    REG_M2M                        (0)
+
+#define    REQ0_ADC                       (0)
+#define    REQ1_SPI1_SEND                 (1)
+#define    REQ2_SPI1_RECV                 (2)
+#define    REQ3_SPI2_SEND                 (3)
+#define    REQ4_SPI2_RECV                 (4)
+#define    REQ5_UART1_SEND                (5)
+#define    REQ6_UART1_RECV                (6)
+#define    REQ7_UART2_SEND                (7)
+#define    REQ8_UART2_RECV                (8)
+#define    REQ9_I2C1_SEND                 (9)
+#define    REQ10_I2C1_RECV                (10)
+#define    REQ11_I2C2_SEND                (11)
+#define    REQ12_I2C2_RECV                (12)
+#define    REQ13_TIM1_CH1                 (13)
+#define    REQ14_TIM1_CH2                 (14)
+#define    REQ15_TIM1_CH3                 (15)
+#define    REQ16_TIM1_CH4                 (16)
+#define    REQ17_TIM1_UP                  (17)
+#define    REQ18_TIM1_TRIG_COM            (18)
+#define    REQ19_TIM3_CH3                 (19)
+#define    REQ20_TIM3_CH4_OR_UP           (20)
+#define    REQ21_TIM3_CH1_OR_TRIG         (21)
+#define    REQ22_TIM3_CH2                 (22)
+#define    REQ23_TIM6_UP                  (23)
+#define    REQ24_TIM15_CH1_UP_TRIG_COM    (24)
+#define    REQ25_TIM15_CH2                (25)
+#define    REQ26_TIM16_CH1_UP             (26)
+#define    REQ27_TIM16_TRIG_COM           (27)
+#define    REQ27_UART3_SEND               (27)
+#define    REQ28_TIM17_CH1_UP             (28)
+#define    REQ29_TIM17_TRIG_COM           (29)
+#define    REQ29_UART3_RECV               (29)
+#define    REQ30_LPUART_SEND              (30)
+#define    REQ31_LPUART_RECV              (31)
+#define    REQ32_TIM2_CH3                 (32)
+#define    REQ33_TIM2_CH4                 (33)
+#define    REQ34_TIM2_CH1                 (34)
+#define    REQ35_TIM2_CH2                 (35)
+#define    REQ36_TIM7_UP                  (36)
+#define    REQ37_I2S1_TX                  (37)
+#define    REQ38_I2S1_RX                  (38)
+#define    REQ39_DAC1_CH1                 (39)
+#define    REQ40_DAC1_CH2                 (40)
+#define    REQ41_TIM4_CH3                 (41)
+#define    REQ42_TIM4_CH4                 (42)
+#define    REQ43_TIM4_CH1                 (43)
+#define    REQ44_TIM4_CH2                 (44)
+#define    REQ45_UART4_SEND               (45)
+#define    REQ46_UART4_RECV               (46)
+#define    REQ47_SPI3_SEND                (47)
+#define    REQ48_SPI3_RECV                (48)
+#define    REQ49_SPI4_SEND                (49)
+#define    REQ50_SPI4_RECV                (50)
+
+#define    REQ_MAX_LIMIT                  (51)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_SOURCE_ADDR_INCREASE
+ *  @{
+ */
+#define    DMA_SOURCE_ADDR_INCREASE_DISABLE    (0x00000000)
+#define    DMA_SOURCE_ADDR_INCREASE_ENABLE     (0x04000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_DST_ADDR_INCREASE
+ *  @{
+ */
+#define    DMA_DST_ADDR_INCREASE_DISABLE    (0x00000000)
+#define    DMA_DST_ADDR_INCREASE_ENABLE     (0x08000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_SRC_WIDTH
+ *  @{
+ */
+#define    DMA_SRC_WIDTH_BYTE         (0x00000000)    /*  8bit */
+#define    DMA_SRC_WIDTH_HALF_WORD    (0x00040000)    /* 16bit */
+#define    DMA_SRC_WIDTH_WORD         (0x00080000)    /* 36bit */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_DST_WIDTH
+ *  @{
+ */
+#define    DMA_DST_WIDTH_BYTE         (0x00000000)    /*  8bit */
+#define    DMA_DST_WIDTH_HALF_WORD    (0x00200000)    /* 16bit */
+#define    DMA_DST_WIDTH_WORD         (0x00400000)    /* 36bit */
+/**
+  * @}
+  */
+  
+ /** @defgroup DMA_MODE DMA MODE
+ *  @{
+ */
+#define DMA_NORMAL                    0x00000000U                  /*!< Normal mode                  */
+#define DMA_CIRCULAR                  0x00000001U                  /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/**
+  * @brief  DMA burst length Structure definition
+  */
+typedef enum
+{
+    DMA_BURST_LENGTH_1   = 0,
+    DMA_BURST_LENGTH_4   = 1,
+    DMA_BURST_LENGTH_8   = 2,
+    DMA_BURST_LENGTH_16  = 3,
+    DMA_BURST_LENGTH_32  = 4,
+    DMA_BURST_LENGTH_64  = 5,
+    DMA_BURST_LENGTH_128 = 6,
+    DMA_BURST_LENGTH_256 = 7,
+}DMA_BURST_LENGTH;
+
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct 
+{
+    uint32_t Mode;                  /* This parameter can be a value of @ref DMA_MODE */
+
+    uint32_t Data_Flow;             /* This parameter can be a value of @ref DMA_DATA_FLOW */
+
+    uint32_t Request_ID;            /* This parameter can be a value of @ref REQUEST_ID */
+
+    uint32_t Source_Inc;            /* This parameter can be a value of @ref DMA_SOURCE_ADDR_INCREASE */
+
+    uint32_t Desination_Inc;        /* This parameter can be a value of @ref DMA_DST_ADDR_INCREASE */
+
+    uint32_t Source_Width;          /* This parameter can be a value of @ref DMA_SRC_WIDTH */
+
+    uint32_t Desination_Width;      /* This parameter can be a value of @ref DMA_DST_WIDTH */
+
+}DMA_InitParaTypeDef;
+
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct 
+{
+    DMA_Channel_TypeDef    *Instance;    /* DMA registers base address */
+
+    DMA_InitParaTypeDef     Init;        /* DMA initialization parameters */
+
+    void (*DMA_ITC_Callback)(void);      /* DMA transfer complete callback */
+    
+    void (*DMA_IE_Callback)(void);       /* DMA error complete callback */
+    
+}DMA_HandleTypeDef;
+
+/**
+  * @brief  DMA Link List Item Structure
+  */
+typedef struct DMA_NextLink
+{
+    uint32_t SrcAddr;               /* source address */
+
+    uint32_t DstAddr;               /* desination address */
+
+    struct DMA_NextLink *Next;      /* Next Link */
+
+    uint32_t Control;               /* Control */
+
+}DMA_LLI_InitTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR)) 
+
+#define IS_DMA_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == DMA_Channel0) || \
+                                          ((INSTANCE) == DMA_Channel1) || \
+                                          ((INSTANCE) == DMA_Channel2) || \
+                                          ((INSTANCE) == DMA_Channel3) || \
+                                          ((INSTANCE) == DMA_Channel4) || \
+                                          ((INSTANCE) == DMA_Channel5) || \
+                                          ((INSTANCE) == DMA_Channel6) || \
+                                          ((INSTANCE) == DMA_Channel7))
+
+#define IS_DMA_DATA_FLOW(DATA_FLOW)     (((DATA_FLOW) == DMA_DATA_FLOW_M2M) || \
+                                         ((DATA_FLOW) == DMA_DATA_FLOW_M2P) || \
+                                         ((DATA_FLOW) == DMA_DATA_FLOW_P2M))
+
+#define IS_DMA_REQUEST_ID(REQUEST_ID)    ((REQUEST_ID < REQ_MAX_LIMIT) ? true : false)
+
+#define IS_DMA_SRC_WIDTH(WIDTH)     (((WIDTH) == DMA_SRC_WIDTH_BYTE)      || \
+                                     ((WIDTH) == DMA_SRC_WIDTH_HALF_WORD) || \
+                                     ((WIDTH) == DMA_SRC_WIDTH_WORD))
+
+#define IS_DMA_DST_WIDTH(WIDTH)     (((WIDTH) == DMA_DST_WIDTH_BYTE)      || \
+                                     ((WIDTH) == DMA_DST_WIDTH_HALF_WORD) || \
+                                     ((WIDTH) == DMA_DST_WIDTH_WORD))
+                                     
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+#define __HAL_LINK_DMA(_HANDLE_, _DMA_LINK_, _DMA_HANDLE_)    (_HANDLE_._DMA_LINK_ = &_DMA_HANDLE_)
+
+/* HAL_DMA_IRQHandler */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_Init */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_DeInit */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_Start */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
+
+/* HAL_DMA_Start */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size);
+
+/* HAL_DMA_Abort */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+
+/* HAL_DMA_GetState */
+HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash.h

@@ -0,0 +1,45 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EFlash HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_H__
+#define __HAL_EFlash_H__
+
+#include "ACM32Fxx_HAL.h"
+
+#define EFLASH_PAGE_SIZE    (512UL)
+
+#define HAL_EFLASH_READ_WORD(Addr)        (*(volatile uint32_t *)(Addr))    // Read By Word
+#define HAL_EFLASH_READ_HALFWORD(Addr)    (*(volatile uint16_t *)(Addr))    // Read By Half Word
+#define HAL_EFLASH_READ_BYTE(Addr)        (*(volatile uint8_t *)(Addr))     // Read By Byte
+
+/********************  Bit definition for EFC_CTRL register  ******************/
+#define EFC_CTRL_CHIP_ERASE_MODE        (1 << 2)
+#define EFC_CTRL_PAGE_ERASE_MODE        (1 << 1)
+#define EFC_CTRL_PROGRAM_MODE           (1 << 0)
+
+/********************  Bit definition for EFC_STATUS register  ***************/
+#define EFC_STATUS_NVR4_LOCK            (1 << 4)
+#define EFC_STATUS_NVR3_LOCK            (1 << 3)
+#define EFC_STATUS_NVR2_LOCK            (1 << 2)
+#define EFC_STATUS_NVR1_LOCK            (1 << 1)
+#define EFC_STATUS_EFLASH_RDY           (1 << 0)
+
+#define RD_WAIT_ENSURE_OK   8 
+#define SET_EFC_RD_WAIT(wait)     {EFC->CTRL   = (EFC->CTRL & ~(0x1F << 7)) | (wait << 7);}     
+
+/* Exported functions --------------------------------------------------------*/  
+
+/* HAL_EFlash_Init */  
+void HAL_EFlash_Init(uint32_t fu32_freq);  
+/* HAL_EFlash_ErasePage */
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr);
+
+/* HAL_EFlash_Program_Word */
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EFlash_EX.h

@@ -0,0 +1,26 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash_EX.h
+  * @version V1.0.0
+  * @date    2021
+  * @brief   Header file of EFlash extention module   
+  ******************************************************************************
+*/
+#ifndef __HAL_EFlash_EX_H__
+#define __HAL_EFlash_EX_H__
+
+#include "stdint.h"
+
+/* HAL_EFlash_Return_To_Boot */
+void HAL_EFlash_Return_to_Boot(void);
+
+/* HAL_EFlash_Init_Para */ 
+void HAL_EFlash_Init_Para(uint32_t fu32_freq);   
+
+/* HAL_EFlash_ErasePage_EX */   
+void HAL_EFlash_ErasePage_EX(uint32_t fu32_Addr);  
+
+/* HAL_EFlash_Program_Word_EX */     
+void HAL_EFlash_Program_Word_EX(uint32_t fu32_Addr, uint32_t fu32_Data);  
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_EXTI.h

@@ -0,0 +1,166 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EXTI.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of EXTI HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_EXTI_H__
+#define __HAL_EXTI_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup EXTI_Line  EXTI Line
+  * @{
+  */
+#define EXTI_LINE_0                (0x000001)
+#define EXTI_LINE_1                (0x000002)
+#define EXTI_LINE_2                (0x000004)
+#define EXTI_LINE_3                (0x000008)
+#define EXTI_LINE_4                (0x000010)
+#define EXTI_LINE_5                (0x000020)
+#define EXTI_LINE_6                (0x000040)
+#define EXTI_LINE_7                (0x000080)
+#define EXTI_LINE_8                (0x000100)
+#define EXTI_LINE_9                (0x000200)
+#define EXTI_LINE_10               (0x000300)
+#define EXTI_LINE_11               (0x000400)
+#define EXTI_LINE_12               (0x001000)
+#define EXTI_LINE_13               (0x002000)
+#define EXTI_LINE_14               (0x004000)
+#define EXTI_LINE_15               (0x008000)
+#define EXTI_LINE_16               (0x010000)
+#define EXTI_LINE_17               (0x020000)
+#define EXTI_LINE_18               (0x040000)
+#define EXTI_LINE_19               (0x080000)
+#define EXTI_LINE_20               (0x100000)
+#define EXTI_LINE_21               (0x200000)
+#define EXTI_LINE_22               (0x400000)
+#define EXTI_LINE_23               (0x800000) 
+#define EXTI_LINE_MASK             (0xFFFFFFU)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Mode  EXTI Mode
+  * @{
+  */
+#define EXTI_MODE_INTERRUPT         (0x00000001)
+#define EXTI_MODE_EVENT             (0x00000002)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_Trigger  EXTI Trigger
+  * @{
+  */
+#define EXTI_TRIGGER_RISING                 (0x00000001)
+#define EXTI_TRIGGER_FALLING                (0x00000002)
+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
+/**
+  * @}
+  */
+
+
+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel
+  * @brief
+  * @{
+  */
+#define EXTI_GPIOA                          0x00000000u
+#define EXTI_GPIOB                          0x00000001u
+#define EXTI_GPIOC                          0x00000002u
+#define EXTI_GPIOD                          0x00000003u
+#define EXTI_GPIOE                          0x00000004u
+#define EXTI_GPIOF                          0x00000005u
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  EXTI Configuration structure definition
+  */
+typedef struct
+{
+    uint32_t u32_Line;        /*!< The Exti line to be configured. This parameter
+                                   can be a value of @ref EXTI_Line */
+    uint32_t u32_Mode;        /*!< The Exit Mode to be configured for a core.
+                                   This parameter can be a combination of @ref EXTI_Mode */
+    uint32_t u32_Trigger;     /*!< The Exti Trigger to be configured. This parameter
+                                   can be a value of @ref EXTI_Trigger */
+    uint32_t u32_GPIOSel;     /*!< The Exti GPIO multiplexer selection to be configured.
+                                   This parameter is only possible for line 0 to 15. It
+                                   can be a value of @ref EXTI_GPIOSel */
+}EXTI_HandleTypeDef;
+
+
+/** @defgroup  EXTI Private Macros
+  * @{
+  */
+#define IS_EXTI_ALL_LINE(LINE)    ( (LINE) | (EXTI_LINE_MASK) )      
+
+#define IS_EXTI_MODE(__MODE__)     (((__MODE__) == EXTI_MODE_INTERRUPT) || \
+                                    ((__MODE__) == EXTI_MODE_EVENT))
+
+#define IS_EXTI_TRIGGER(__TRIGGER__)     (((__TRIGGER__) == EXTI_TRIGGER_RISING)  || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_FALLING) || \
+                                          ((__TRIGGER__) == EXTI_TRIGGER_RISING_FALLING))
+
+#define IS_EXTI_GPIOSEL(__GPIOSEL__)     (((__GPIOSEL__) == EXTI_GPIOA) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOB) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOC) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOD) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOE) || \
+                                          ((__GPIOSEL__) == EXTI_GPIOF))
+/**
+  * @}
+  */
+
+/** @brief  __HAL_EXTI_LINE_IT_ENABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_ENABLE(__LINE__)    (EXTI->IENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_IT_DISABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_IT_DISABLE(__LINE__)    (EXTI->IENR &= ~(__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_ENABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_ENABLE(__LINE__)    (EXTI->EENR |= (__LINE__))
+
+/** @brief  __HAL_EXTI_LINE_EVENT_DISABLE 
+  * @param  __LINE__: EXTI line.
+  *         This parameter can be a value of @ref EXTI_Line
+  */
+#define __HAL_EXTI_LINE_EVENT_DISABLE(__LINE__)    (EXTI->EENR &= ~(__LINE__))
+
+
+/* HAL_EXTI_IRQHandler */
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *huart);
+
+/* HAL_EXTI_SetConfigLine */
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_SoftTrigger */
+void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_GetPending */
+bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti);
+
+/* HAL_EXTI_ClearPending */
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti);  
+
+/* HAL_EXTI_ClearAllPending */   
+void HAL_EXTI_ClearAllPending(void);  
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FAU.h

@@ -0,0 +1,170 @@
+
+#ifndef __FAU_H_
+#define __FAU_H_
+
+#define RANGE 2147483648U  //2^31
+#define CORDIC_F_31  0xD2C90A46 // CORDIC gain F
+
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 1 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_1(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 2 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_2(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 3 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_3(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 4 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_4(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 5 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_5(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 6 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_6(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 7 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_7(int angle_para, int* cos_data, int* sin_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_CosSin( precision 8 )
+* Description    : calculate the sin & cos value of the input angle
+* Input          : - angle_para   : input angle data in radians, divided by ¦Ð[range[-1,1],Q31 format];
+* Output		     : - * cos_data   : the cos value of the input angle[range[-1,1],Q31 format]
+                   - * sin_data   : the sin value of the input angle[range[-1,1],Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_CosSin_8(int angle_para, int* cos_data, int* sin_data);
+
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 1 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_1(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 2 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_2(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 3 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_3(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 4 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_4(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 5 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_5(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 6 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_6(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 7 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_7(int x, int y, int*sqrt_data, int* atan_data);
+/**************************************************************************
+* Function Name  : HAL_CORDIC_AtanSqrt( precision 8 )
+* Description    : calculate the atan & sqrt value of the input x,y
+* Input          : - x             : input x data[range[-1,1],Q31 format];
+*				         : - y             : input y data[range[-1,1],Q31 format];
+                 : - precision     : the precison used in calculation
+* Output		     : - * sqrt_data   : the sqrt value of the input x,y[Q31 format]
+                   - * atan_data   : the atan value of the input x,y[Q31 format]
+* Return         : None
+**************************************************************************/
+void HAL_CORDIC_AtanSqrt_8(int x, int y, int*sqrt_data, int* atan_data);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_FSUSB.h

@@ -0,0 +1,105 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Uart.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_FSUSB_H__
+#define __HAL_FSUSB_H__  
+
+#include "ACM32Fxx_HAL.h"
+
+
+#define     HIGH_SPEED     1 
+#define     FULL_SPEED     0 
+
+#define     USB_EP0        0
+#define     USB_EP1        1        
+#define     USB_EP2        2      
+#define     USB_EP3        3        
+#define     USB_EP4        4   
+
+#define     USB_EP_IN      USB_EP1
+#define     USB_EP_OUT     USB_EP1
+
+#define     EP_DIR_IN      0x80  
+#define     EP_DIR_OUT     0x00   
+
+#define 	HID_REPORT_SIZE         1024
+
+#define     EP0_MAX_PACKET_SIZE     64
+#define     EPX_MAX_PACKET_SIZE     64
+//#define     EPX_MAX_PACKET_SIZE_HS     512
+//#define     EPX_MAX_PACKET_SIZE_FS     64
+
+#define     MASK_EPX_IN(x)		(1<<(6+3*x))   
+#define     MASK_EPX_OUT(x)     (1<<(7+3*x))   
+#define     MASK_EPX_ACK(x)     (1<<(8+3*x)) 
+#define     MASK_EPX_TIMEOUT(x) (1<< (25+x))
+
+typedef __PACKED_STRUCT _device_request
+{
+	uint8_t  bmRequestType;
+	uint8_t  bRequest;
+	uint16_t wValue;
+	uint16_t wIndex;
+	uint16_t wLength;
+} DEVICE_REQUEST;
+
+
+
+#define USB_BUS_RESET         	0x01
+#define USB_SUSPEND           	0x02
+#define USB_RESUME           	0x04
+#define USB_SOF            		0x08
+#define USB_SETUPTOK         	0x10
+#define USB_EP0_SETUP_PACKET  	0x20
+#define USB_EP0_IN		  		0x40
+#define USB_EP0_OUT_PACKET 		0x80
+#define USB_EP0_ACK  			0x100
+#define USB_EP1_IN		  		0x200
+#define USB_EP1_OUT_PACKET    	0x400
+#define USB_EP1_ACK		    	0x800
+#define USB_EP2_IN		  		0x1000
+#define USB_EP2_OUT_PACKET    	0x2000
+#define USB_EP2_ACK		    	0x4000
+#define USB_EP3_IN		  		0x8000
+#define USB_EP3_OUT_PACKET    	0x10000
+#define USB_EP3_ACK		    	0x20000
+#define USB_EP4_IN		  		0x40000
+#define USB_EP4_OUT_PACKET    	0x80000
+#define USB_EP4_ACK		    	0x100000
+#define USB_IN_TIMEOUT	    	0x200000
+#define USB_SETADDR		    	0x400000
+#define USB_CRC_ERR 	    	0x800000
+#define USB_MORETHAN_64     	0x1000000
+#define USB_EP0_IN_ERR      	0x2000000
+#define USB_EP1_IN_ERR      	0x4000000
+#define USB_EP2_IN_ERR      	0x8000000
+#define USB_EP3_IN_ERR      	0x10000000
+#define USB_EP4_IN_ERR      	0x20000000
+#define USB_NOEOP_ERR      		0x40000000
+#define USB_TOGGLE_ERR      	0x80000000
+
+
+
+#define ERROR_OUT_OUT            4  // received a same out packet 
+#define ERROR_IN_OUT             2  // received a pakcet when try to send packet   
+
+
+
+uint32_t HAL_FSUSB_Init(void);     
+void HAL_FSUSB_Read_EP_MEM8(uint8_t *dst, uint32_t length, uint32_t fifo_offset, uint8_t ep_index);  
+uint8_t HAL_FSUSB_Send_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index);   
+void HAL_FSUSB_Receive_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index);  
+uint16_t HAL_USB_Get_Stall_Status(uint8_t ep_index, uint8_t ep_dir);  
+void HAL_FSUSB_EP0_Send_Empty_Packet(void);  
+void HAL_FSUSB_EP0_Send_Stall(void);    
+void usb_clear_stall(uint8_t ep_index, uint8_t ep_dir);  
+void usb_send_stall(uint8_t ep_index, uint8_t ep_dir);
+uint16_t HAL_FSUSB_Get_FIFO_Length(uint8_t ep_index);      
+
+#endif  
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_GPIO.h

@@ -0,0 +1,214 @@
+/*
+  ******************************************************************************
+  * @file    HAL_GPIO.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_GPIO_H__
+#define __HAL_GPIO_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+
+#define GPIO_PIN_MASK              (0x0000FFFFu) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_mode GPIO mode
+  * @{
+  */
+#define  GPIO_MODE_INPUT                    (0x00010000u)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                (0x00010001u)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                (0x00011002u)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                    (0x00000003u)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                    (0x00001004u)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_ANALOG                   (0x00000005u)   /*!< Analog Mode                           */
+#define  GPIO_MODE_IT_RISING                (0x10010000u)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING               (0x10010001u)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING        (0x10010002u)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_IT_HIGH_LEVEL            (0x10010003u)   /*!< External Interrupt Mode with high level trigger detection  */
+#define  GPIO_MODE_IT_LOW_LEVEL             (0x10010004u)   /*!< External Interrupt Mode with low level trigger detection  */
+
+#define  GPIO_MODE_OD_MASK                  (0x00001000u)   /*!< OD Mode Mask                          */
+#define  GPIO_MODE_IO_MASK                  (0x00010000u)   /*!< Use GPIO Function Mask                */
+#define  GPIO_MODE_IT_MASK                  (0x10000000u)   /*!< GPIO interrupt Mask                */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO_pull GPIO pull
+  * @{
+  */
+#define  GPIO_NOPULL        (0x00000000u)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        (0x00000001u)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      (0x00000002u)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIOEx_function_selection GPIO pull
+  * @{
+  */
+#define  GPIO_FUNCTION_0        (0x00000000u)
+#define  GPIO_FUNCTION_1        (0x00000001u)
+#define  GPIO_FUNCTION_2        (0x00000002u)
+#define  GPIO_FUNCTION_3        (0x00000003u)
+#define  GPIO_FUNCTION_4        (0x00000004u)
+#define  GPIO_FUNCTION_5        (0x00000005u)
+#define  GPIO_FUNCTION_6        (0x00000006u)
+#define  GPIO_FUNCTION_7        (0x00000007u)
+#define  GPIO_FUNCTION_8        (0x00000008u)
+#define  GPIO_FUNCTION_9        (0x00000009u)
+/**
+  * @}
+  */
+
+
+
+/** @defgroup GPIOx Index
+  * @{
+  */
+typedef enum
+{
+    GPIOA,
+    GPIOB,
+    GPIOC,
+    GPIOD,
+    GPIOE,
+    GPIOF,
+}enum_GPIOx_t;
+/**
+  * @}
+  */
+
+
+/** @defgroup GPIO Bit SET and Bit RESET enumeration
+  * @{
+  */
+typedef enum
+{
+  GPIO_PIN_CLEAR = 0u,
+  GPIO_PIN_SET   = 1u,
+}enum_PinState_t;
+/**
+  * @}
+  */
+
+
+
+/*
+ * @brief   GPIO Init structure definition
+ */
+typedef struct
+{
+    uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                              This parameter can be any value of @ref GPIO_pins */
+
+    uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                              This parameter can be a value of @ref GPIO_mode */
+
+    uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                              This parameter can be a value of @ref GPIO_pull */
+
+    uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins
+                               This parameter can be a value of @ref GPIOEx_function_selection */
+} GPIO_InitTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
+                                        ((INSTANCE) == GPIOB) || \
+                                        ((INSTANCE) == GPIOC) || \
+                                        ((INSTANCE) == GPIOD) || \
+                                        ((INSTANCE) == GPIOE) || \
+                                        ((INSTANCE) == GPIOF))
+
+#define IS_GPIO_PIN(__PIN__)           ((((uint32_t)(__PIN__) &  GPIO_PIN_MASK) != 0x00u) &&\
+                                        (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
+
+
+#define IS_GPIO_MODE(__MODE__)         (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                        ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                        ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                        ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                        ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                        ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                        ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                        ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                        ((__MODE__) == GPIO_MODE_IT_HIGH_LEVEL)      ||\
+                                        ((__MODE__) == GPIO_MODE_IT_LOW_LEVEL)       ||\
+                                        ((__MODE__) == GPIO_MODE_ANALOG))
+
+
+
+
+#define IS_GPIO_PULL(__PULL__)         (((__PULL__) == GPIO_NOPULL)   ||\
+                                        ((__PULL__) == GPIO_PULLUP)   ||\
+                                        ((__PULL__) == GPIO_PULLDOWN))
+
+#define IS_GPIO_PIN_ACTION(ACTION)     (((ACTION) == GPIO_PIN_CLEAR) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_FUNCTION(__FUNCTION__)    (((__FUNCTION__) == GPIO_FUNCTION_0) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_1) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_2) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_3) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_4) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_5) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_6) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_7) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_8) ||\
+                                           ((__FUNCTION__) == GPIO_FUNCTION_9))
+                                     
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+
+/* HAL_GPIO_IRQHandler */
+void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin);
+
+/* HAL_GPIO_Init */
+void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init);
+
+/* HAL_GPIO_DeInit */
+void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin);
+
+/* HAL_GPIO_AnalogEnable */
+void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin);
+
+/* HAL_GPIO_WritePin */
+void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState);
+
+/* HAL_GPIO_ReadPin */
+enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_HRNG.h

@@ -0,0 +1,53 @@
+/***********************************************************************f
+ * Filename    : hrng.h
+ * Description : hrng header file
+ * Author(s)   : cc  
+ * version     : V1.0
+ * Modify date : 2021-03-24
+ ***********************************************************************/
+
+#ifndef __HRNG_H__
+#define __HRNG_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_Initial
+* Description    : initial hrng module
+* Input          : None
+* Output         : None
+* Return         : None
+*********************************************************************************/
+void HAL_HRNG_Initial(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng_8
+* Description    : get 8bit random number
+* Input          : None
+* Output         : None
+* Return         : 8 bit random number
+*********************************************************************************/
+UINT8 HAL_HRNG_GetHrng_8(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng_32
+* Description    : get 32bit random number
+* Input          : None
+* Output         : None
+* Return         : 32 bit random number
+*********************************************************************************/
+UINT32 HAL_HRNG_GetHrng_32(void);
+
+/*********************************************************************************
+* Function Name  : HAL_HRNG_GetHrng
+* Description    : get random number
+* Input          : byte_len :  the byte length of random number
+* Output         : *hdata   :  the start address of random number
+* Return         : 0: hrng data is ok; 1: hrng data is bad
+*********************************************************************************/
+UINT8 HAL_HRNG_GetHrng(UINT8 *hdata, UINT32 byte_len);
+
+#endif
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2C.h

@@ -0,0 +1,253 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2C.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+*/
+
+#ifndef __HAL_I2C_H__
+#define __HAL_I2C_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Bit definition for I2C CR register  ********************/
+#define I2C_CR_STOPF_INTEN                  BIT20
+#define I2C_CR_RX_ADDR3_INTEN               BIT19
+#define I2C_CR_DMA_EN                       BIT18
+#define I2C_CR_TXE_SEL                      BIT17
+#define I2C_CR_MARLO_INTEN                  BIT16
+#define I2C_CR_TX_AUTO_EN                   BIT15
+#define I2C_CR_OD_MODE                      BIT14
+#define I2C_CR_RX_ADDR2_INT_EN              BIT12
+#define I2C_CR_OVR_INT_EN                   BIT11
+#define I2C_CR_RXNE_INT_EN                  BIT10
+#define I2C_CR_TXE_INT_EN                   BIT9
+#define I2C_CR_RX_ADDR1_INT_EN              BIT8
+#define I2C_CR_MTF_INT_EN                   BIT7
+#define I2C_CR_TACK                         BIT6
+#define I2C_CR_STOP                         BIT5
+#define I2C_CR_START                        BIT4
+#define I2C_CR_TX                           BIT3
+#define I2C_CR_MASTER                       BIT2
+#define I2C_CR_NOSTRETCH                    BIT1
+#define I2C_CR_MEN                          BIT0
+
+/****************  Bit definition for I2C SR register  ********************/
+#define I2C_SR_TIMEOUTBF                    BIT16
+#define I2C_SR_TIMEOUTAF                    BIT15
+#define I2C_SR_RX_ADDR3                     BIT14
+#define I2C_SR_RX_ADDR2                     BIT12
+#define I2C_SR_OVR                          BIT11
+#define I2C_SR_RXNE                         BIT10
+#define I2C_SR_TXE                          BIT9
+#define I2C_SR_RX_ADDR1                     BIT8
+#define I2C_SR_MTF                          BIT7
+#define I2C_SR_MARLO                        BIT6
+#define I2C_SR_TX_RX_FLAG                   BIT5
+#define I2C_SR_BUS_BUSY                     BIT4
+#define I2C_SR_SRW                          BIT3
+#define I2C_SR_STOPF                        BIT2
+#define I2C_SR_STARTF                       BIT1
+#define I2C_SR_RACK                         BIT0
+
+/**************  Bit definition for I2C SLAVE ADDR2/3 register  **************/
+#define I2C_ADDR3_EN                        BIT8
+#define I2C_ADDR2_EN                        BIT0
+
+/**************  Bit definition for I2C TIMEOUT register  **************/
+#define I2C_TIMEOUT_EXTEN                   BIT31
+#define I2C_TOUTB_INTEN                     BIT30
+#define I2C_EXT_MODE                        BIT29
+#define I2C_TIMEOUT_TIMOUTEN                BIT15
+#define I2C_TOUTA_INTEN                     BIT14
+
+/** @defgroup I2C_MODE
+ *  @{
+ */
+#define    I2C_MODE_SLAVE     (0U)
+#define    I2C_MODE_MASTER    (1U)
+/**
+  * @}
+  */
+
+/** @defgroup CLOCK_SPEED
+ *  @{
+ */
+#define    CLOCK_SPEED_STANDARD     (100000U)
+#define    CLOCK_SPEED_FAST         (400000U)
+#define    CLOCK_SPEED_FAST_PLUS    (1000000U)
+/**
+  * @}
+  */
+
+
+/** @defgroup TX_AUTO_EN
+ *  @{
+ */
+#define    TX_AUTO_EN_DISABLE    (0U)
+#define    TX_AUTO_EN_ENABLE     (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup NO_STRETCH_MODE
+ *  @{
+ */
+#define    NO_STRETCH_MODE_STRETCH      (0U)
+#define    NO_STRETCH_MODE_NOSTRETCH    (1U)
+/**
+  * @}
+  */
+
+/** @defgroup SLAVE State machine
+ *  @{
+ */
+#define    SLAVE_RX_STATE_IDLE         (0U)
+#define    SLAVE_RX_STATE_RECEIVING    (1U)
+#define    SLAVE_TX_STATE_IDLE         (0U)
+#define    SLAVE_TX_STATE_SENDING      (1U)
+/**
+  * @}
+  */
+  
+ /** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            (0U)
+#define I2C_MEMADD_SIZE_16BIT           (1U)
+/**
+  * @}
+  */
+ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macros I2C Private Macros
+  * @{
+  */
+#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+ 
+/**
+  * @brief  I2C Configuration Structure definition
+  */
+  
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->SR) & (__FLAG__))  == (__FLAG__) ) ? 1 : 0) 
+
+typedef enum 
+{
+  RESET = 0, 
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef struct
+{
+    uint32_t  I2C_Mode;               /* This parameter can be a value of @ref I2C_MODE */
+    
+    uint32_t  Tx_Auto_En;             /* This parameter can be a value of @ref TX_AUTO_EN */
+    
+    uint32_t  No_Stretch_Mode;        /* This parameter can be a value of @ref NO_STRETCH_MODE */
+    
+    uint32_t  Own_Address;            /* This parameter can be a 7-bit address */
+    
+    uint32_t  Clock_Speed;            /* This parameter can be a value of @ref CLOCK_SPEED */
+} I2C_InitTypeDef;
+
+/******************************** Check I2C Parameter *******************************/
+#define IS_I2C_ALL_MODE(I2C_MODE)    (((I2C_MODE) == I2C_MODE_SLAVE) || \
+                                      ((I2C_MODE) == I2C_MODE_MASTER))
+
+#define IS_I2C_CLOCK_SPEED(CLOCK_SPEED)    (((CLOCK_SPEED) > 0U) && ((CLOCK_SPEED) <=1000000U))
+
+#define IS_I2C_TX_AUTO_EN(TX_AUTO_EN)      (((TX_AUTO_EN) == TX_AUTO_EN_DISABLE) || \
+                                            ((TX_AUTO_EN) == TX_AUTO_EN_ENABLE))
+
+#define IS_I2C_STRETCH_EN(STRETCH_EN)    (((STRETCH_EN) == NO_STRETCH_MODE_STRETCH) || \
+                                          ((STRETCH_EN) == NO_STRETCH_MODE_NOSTRETCH))
+
+/**
+  * @brief  I2C handle Structure definition
+  */
+typedef struct
+{
+    I2C_TypeDef         *Instance;         /* I2C registers base address */
+
+    I2C_InitTypeDef      Init;             /* I2C communication parameters */
+    
+    uint32_t               Slave_RxState;    /* I2C Slave state machine */
+    uint32_t               Slave_TxState;    /* I2C Slave state machine */
+    
+    uint8_t               *Rx_Buffer;        /* I2C Rx Buffer */
+    uint8_t               *Tx_Buffer;        /* I2C Tx Buffer */
+    
+    uint32_t               Rx_Size;          /* I2C Rx Size */
+    uint32_t               Tx_Size;          /* I2C Tx Size */
+    
+    uint32_t               Rx_Count;         /* I2C Rx Count */
+    uint32_t               Tx_Count;         /* I2C Tx Count */
+
+    DMA_HandleTypeDef   *HDMA_Rx;          /* I2C Rx DMA handle parameters */
+    DMA_HandleTypeDef   *HDMA_Tx;          /* I2C Tx DMA handle parameters */
+
+    void (*I2C_STOPF_Callback)(void);      /* I2C STOP flag interrupt callback */
+
+}I2C_HandleTypeDef;
+
+/******************************** I2C Instances *******************************/
+#define IS_I2C_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == I2C1) || ((INSTANCE) == I2C2))
+
+/* Function : HAL_I2C_IRQHandler */
+void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_MspInit */
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_MspDeInit */
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_Init */
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_DeInit */
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_Master_Transmit */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Master_Receive */
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Transmit */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Slave_Receive */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+ 
+/* Function : HAL_I2C_Slave_Transmit_IT */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+
+/* Function : HAL_I2C_Slave_Receive_IT */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Slave_Receive_DMA */
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Slave_Transmit_DMA */
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_I2C_Mem_Write */
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_Mem_Read */
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+
+/* Function : HAL_I2C_GetSlaveRxState */
+uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c);
+
+/* Function : HAL_I2C_GetSlaveTxState */
+uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_I2S.h

@@ -0,0 +1,248 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2S.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of I2S HAL module.
+  ******************************************************************************
+*/
+
+#ifndef __HAL_I2S_H__
+#define __HAL_I2S_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************************/
+/*                             Registers Bits Definition                            */
+/************************************************************************************/
+
+/****************  Bit definition for I2S CTL Register  ***********************/
+#define I2S_CTL_I2SEN               (BIT10)
+#define I2S_CTL_I2SOPMOD            (BIT9|BIT8)
+#define I2S_CTL_PCMSMOD             (BIT7)
+#define I2S_CTL_I2SSTD              (BIT5|BIT4)
+#define I2S_CTL_CKPL                (BIT3)
+#define I2S_CTL_DTLEN               (BIT2|BIT1)
+#define I2S_CTL_CHLEN               (BIT0)
+
+/****************  Bit definition for I2S PSC Register  ***********************/
+#define I2S_PSC_MCKOEN              (BIT10)
+#define I2S_PSC_OF                  (BIT9)
+#define I2S_PSC_DIV                 (0x1FF)
+
+/****************  Bit definition for I2S DIE Register  ***********************/
+#define I2S_DIE_TBEIE               (BIT7)
+#define I2S_DIE_RBNEIE              (BIT6)
+#define I2S_DIE_ERRIE               (BIT5)
+#define I2S_DIE_DMATEN              (BIT1)
+#define I2S_DIE_DMAREN              (BIT0)
+
+/****************  Bit definition for I2S STATUS Register  ***********************/
+#define I2S_STATUS_FERR             (BIT8)
+#define I2S_STATUS_TRANS            (BIT7)
+#define I2S_STATUS_RXORERR          (BIT6)
+#define I2S_STATUS_TXURERR          (BIT3)
+#define I2S_STATUS_I2SCH            (BIT2)
+#define I2S_STATUS_TXBE             (BIT1)
+#define I2S_STATUS_RXBNE            (BIT0)
+
+
+
+/** @defgroup I2S_Mode I2S Mode
+  * @{
+  */
+#define I2S_MODE_SLAVE_TX                (0x00000000)
+#define I2S_MODE_SLAVE_RX                (0x00000100)
+#define I2S_MODE_MASTER_TX               (0x00000200)
+#define I2S_MODE_MASTER_RX               (I2S_CTL_I2SOPMOD)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Standard I2S Standard
+  * @{
+  */
+#define I2S_STANDARD_PHILIPS             (0x00000000U)
+#define I2S_STANDARD_MSB                 (0x00000010U)
+#define I2S_STANDARD_LSB                 (0x00000020U)
+#define I2S_STANDARD_PCM_SHORT           (I2S_CTL_I2SSTD)
+#define I2S_STANDARD_PCM_LONG            (I2S_CTL_I2SSTD | I2S_CTL_PCMSMOD)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Data_Format I2S Data Format
+  * @{
+  */
+#define I2S_DATAFORMAT_16B               (0x00000000U)
+#define I2S_DATAFORMAT_16B_EXTENDED      (I2S_CTL_CHLEN)
+#define I2S_DATAFORMAT_24B               (I2S_CTL_CHLEN | 0x02)
+#define I2S_DATAFORMAT_32B               (I2S_CTL_CHLEN | 0x04)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_MCLK_Output I2S MCLK Output
+  * @{
+  */
+#define I2S_MCLKOUTPUT_ENABLE            (I2S_PSC_MCKOEN)
+#define I2S_MCLKOUTPUT_DISABLE           (0x00000000U)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
+  * @{
+  */
+#define I2S_CPOL_LOW                     (0x00000000U)
+#define I2S_CPOL_HIGH                    (I2S_CTL_CKPL)
+/**
+  * @}
+  */
+
+
+/** @defgroup I2S_Audio_FrequencyOF I2S Clock Frequency OF
+  * @{
+  */
+#define I2S_FREQ_OF_DISABLE              (0x00000000U)
+#define I2S_FREQ_OF_ENABLE               (I2S_PSC_OF)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+    HAL_I2S_STATE_RESET      = 0x00U,    /*!< I2S not yet initialized or disabled                */
+    HAL_I2S_STATE_READY      = 0x01U,    /*!< I2S initialized and ready for use                  */
+    HAL_I2S_STATE_BUSY       = 0x02U,    /*!< I2S internal process is ongoing                    */
+    HAL_I2S_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
+    HAL_I2S_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
+    HAL_I2S_STATE_TIMEOUT    = 0x06U,    /*!< I2S timeout state                                  */
+    HAL_I2S_STATE_ERROR      = 0x07U     /*!< I2S error state                                    */
+}enum_I2S_State;
+
+
+/**
+  * @brief I2S Init structure definition
+  */
+typedef struct
+{
+    uint32_t u32_Mode;            /*!< Specifies the I2S operating mode.
+                                       This parameter can be a value of @ref I2S_Mode */
+    
+    uint32_t u32_Standard;        /*!< Specifies the standard used for the I2S communication.
+                                       This parameter can be a value of @ref I2S_Standard */
+    
+    uint32_t u32_DataFormat;      /*!< Specifies the data format for the I2S communication.
+                                       This parameter can be a value of @ref I2S_Data_Format */
+    
+    uint32_t u32_MCLKOutput;      /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                       This parameter can be a value of @ref I2S_MCLK_Output */
+
+    uint32_t u32_CPOL;            /*!< Specifies the idle state of the I2S clock.
+                                       This parameter can be a value of @ref I2S_Clock_Polarity */
+
+    uint32_t u32_FreqOF;          /*!< Specifies the frequency selected for the I2S communication.
+                                       This parameter can be a value of @ref I2S_Audio_FrequencyFO */
+
+    uint32_t u32_FreqDIV;         /*!< Specifies the frequency selected for the I2S communication.
+                                       This parameter must be a number between Min_Data = 0x001 and Max_Data = 0x1FF */
+}I2S_InitTypeDef;
+
+
+
+/**
+  * @brief I2S handle Structure definition
+  */
+typedef struct
+{
+    I2S_TypeDef           *Instance;     /*!< I2S registers base address */
+
+    I2S_InitTypeDef        Init;         /*!< I2S communication parameters */
+
+    enum_I2S_State         I2S_Status;
+
+    uint32_t              *u32_Rx_Buffer;        /* I2S Rx Buffer */
+    uint32_t              *u32_Tx_Buffer;        /* I2S Tx Buffer */
+    
+    uint32_t               u32_Rx_Size;          /* I2S Rx Size */
+    uint32_t               u32_Tx_Size;          /* I2S Tx Size */
+    
+    uint32_t               u32_Rx_Count;         /* I2S RX Count */
+    uint32_t               u32_Tx_Count;         /* I2S TX Count */
+
+    DMA_HandleTypeDef   *HDMA_Rx;          /* SPI Rx DMA handle parameters */
+    DMA_HandleTypeDef   *HDMA_Tx;          /* SPI Tx DMA handle parameters */
+
+}I2S_HandleTypeDef;
+
+
+/** @defgroup  RTC Private Macros
+  * @{
+  */
+#define IS_I2S_MODE(__MODE__)             (((__MODE__) == I2S_MODE_SLAVE_TX)  || \
+                                           ((__MODE__) == I2S_MODE_SLAVE_RX)  || \
+                                           ((__MODE__) == I2S_MODE_MASTER_TX) || \
+                                           ((__MODE__) == I2S_MODE_MASTER_RX))
+
+#define IS_I2S_STANDARD(__STANDARD__)     (((__STANDARD__) == I2S_STANDARD_PHILIPS)   || \
+                                           ((__STANDARD__) == I2S_STANDARD_MSB)       || \
+                                           ((__STANDARD__) == I2S_STANDARD_LSB)       || \
+                                           ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \
+                                           ((__STANDARD__) == I2S_STANDARD_PCM_LONG))
+                                           
+#define IS_I2S_DATAFORMAT(__DATAFORMAT__)       (((__DATAFORMAT__) == I2S_DATAFORMAT_16B)           || \
+                                                 ((__DATAFORMAT__) == I2S_DATAFORMAT_16B_EXTENDED)  || \
+                                                 ((__DATAFORMAT__) == I2S_DATAFORMAT_24B)           || \
+                                                 ((__DATAFORMAT__) == I2S_DATAFORMAT_32B))
+
+#define IS_I2S_MCLK_OUTPUT(__MCLK_OUTPUT__)     (((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_ENABLE)  || \
+                                                 ((__MCLK_OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))
+
+#define IS_I2S_MCLK_CPOL(__CPOL__)              (((__CPOL__) == I2S_CPOL_LOW)  || \
+                                                 ((__CPOL__) == I2S_CPOL_HIGH))
+
+#define IS_I2S_OF(__OF__)                       (((__OF__) == I2S_FREQ_OF_DISABLE)  || \
+                                                 ((__OF__) == I2S_FREQ_OF_ENABLE))
+
+#define IS_I2S_DIV(__DIV__)                      ((__DIV__) >= 0x001 && (__DIV__) <= 0x1FF)
+/**
+  * @}
+  */
+
+/* HAL_I2S_IRQHandler */
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
+
+/* HAL_I2S_MspInit */
+void HAL_I2S_MspInit(I2S_HandleTypeDef *hspi);
+
+/* HAL_I2S_Init */
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
+
+/* HAL_I2S_Transmit */
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout);
+
+/* HAL_I2S_Receive */
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout);
+
+/* HAL_I2S_Transmit_IT */
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+/* HAL_I2S_Receive_IT */
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+/* HAL_I2S_Transmit_DMA */
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+/* HAL_I2S_Receive_DMA */
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size);
+
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_IWDT.h

@@ -0,0 +1,56 @@
+
+/***********************************************************************
+ * Filename    : HAL_IWDT.h
+ * Description : IHAL WDT driver header file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17  
+ ***********************************************************************/
+
+#ifndef __HAL_IWDT_H__
+#define __HAL_IWDT_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+/****************  Bit definition for IWDT register  ***********************/
+
+
+/*----------------------macro definition------------------------*/
+#define IWDT_ENABLE_COMMAND  (0xCCCCU)
+#define IWDT_WRITE_ENABLE_COMMAND  (0x5555U)  
+#define IWDT_WAKEUP_ENABLE_COMMAND  (0x6666U)  
+#define IWDT_WAKEUP_DISABLE_COMMAND  (0x9999U) 
+#define IWDT_RELOAD_COMMAND  (0xAAAAU)    
+
+#define IWDT_RELOAD_MAX_VALUE  (0x0FFFU)  
+
+/*----------------------type definition------------------------*/
+typedef enum _IWDT_CLOCK_PRESCALER{       
+    IWDT_CLOCK_PRESCALER_4   = 0, 
+    IWDT_CLOCK_PRESCALER_8   = 1,    
+    IWDT_CLOCK_PRESCALER_16  = 2,  
+    IWDT_CLOCK_PRESCALER_32  = 3,  
+    IWDT_CLOCK_PRESCALER_64  = 4,  
+    IWDT_CLOCK_PRESCALER_128 = 5,   
+    IWDT_CLOCK_PRESCALER_256 = 6,  
+}IWDT_CLOCK_PRESCALER;  
+
+typedef struct
+{
+    uint32_t Prescaler;                            
+    uint32_t Reload;                              
+    uint32_t Window;     
+    uint32_t Wakeup;  
+} IWDT_InitTypeDef;
+
+typedef struct
+{
+    IWDT_TypeDef                 *Instance;  /*!< Register base address    */  
+    IWDT_InitTypeDef             Init;       /*!< IWDT required parameters */
+} IWDT_HandleTypeDef;
+
+
+ HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt);  
+ HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt);   
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_LPUART.h

@@ -0,0 +1,173 @@
+/*
+  ******************************************************************************
+  * @file    HAL_LPUART.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_LPUART_H__
+#define __HAL_LPUART_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+#define IS_LPUART_INSTANCE(INSTANCE)          ((INSTANCE) == LPUART)
+
+#define LPUART_PEN_INDEX  0   
+#define LPUART_SPS_INDEX  1   
+#define LPUART_EPS_INDEX  2
+
+#define LPUART_IE_RX_INDEX         0  //has wakeup function 
+#define LPUART_IE_TX_FINISH_INDEX  1
+#define LPUART_IE_TX_EMPTY_INDEX   2
+
+#define LPUART_SR_RX_INDEX         0  
+#define LPUART_SR_TX_FINISH_INDEX  1
+#define LPUART_SR_TX_EMPTY_INDEX   2 
+#define LPUART_SR_RX_FULL_INDEX    6    
+#define LPUART_SR_MATCH_INDEX      8  //has wakeup function 
+#define LPUART_SR_START_INDEX      9  //has wakeup function    
+#define LPUART_SR_BITS_ALL         0x1FFU
+
+#define LPUART_WAKEUP_RX_BIT       BIT0              
+#define LPUART_WAKEUP_MATCH_BIT    BIT8
+#define LPUART_WAKEUP_START_BIT    BIT9
+
+#define LPUART_CR_RXE_INDEX  0  
+#define LPUART_CR_TXE_INDEX  1  
+#define LPUART_CR_DMA_EN_INDEX  2   
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */                      
+typedef enum
+{
+    LPUART_RXWKS_START = 0x00, 
+    LPUART_RXWKS_OneByte = 0x01,
+    LPUART_RXWKS_DataCompare = 0x02,     
+    LPUART_RXWKS_NoWake = 0x03,  
+} LPUART_RXWKS;  
+
+typedef enum
+{
+    LPUART_WKCK_Check = 0x00, 
+    LPUART_WKCK_NoCheck = 0x01,
+} LPUART_WKCK ;
+
+/**
+  * @}
+  */
+
+
+
+/*
+ * @brief  LPUART DATABITS  definition
+ */
+typedef enum
+{
+    LPUART_DATABITS_8 = 0x00, 
+    LPUART_DATABITS_7 = 0x01,   
+} LPUART_DATABITS;  
+
+/*
+ * @brief  LPUART STOPBITS  definition
+ */
+typedef enum
+{
+    LPUART_STOPBITS_ONE = 0x00U,  
+    LPUART_STOPBITS_TWO = 0x01U, 
+}LPUART_STOPBITS;  
+
+/*
+ * @brief  LPUART CLOCK_SOURCE  definition
+ */
+typedef enum
+{
+    LPUART_CLOCK_SOURCE_RC32K = 0x00U,  
+    LPUART_CLOCK_SOURCE_XTAL = 0x01U, 
+    LPUART_CLOCK_SOURCE_PLL_DIV = 0x02U, 
+}LPUART_CLOCK_SOURCE;  
+
+/*
+ * @brief  LPUART PARITY  definition
+ */
+typedef enum
+{
+    LPUART_PARITY_NONE = 0x00U,  
+    LPUART_PARITY_SELECT_ODD = 0x01U,  
+    LPUART_PARITY_SELECT_EVEN = 0x02U,             
+    LPUART_PARITY_SELECT_ONE = 0x03U,  
+    LPUART_PARITY_SELECT_ZERO = 0x04U,  
+}LPUART_PARITY_SELECT;  
+
+/** 
+  * @brief  LPUART  Config structure definition
+  */
+typedef struct
+{
+    uint8_t  WordLength;  // LPUART_DATABITS           
+    uint8_t  StopBits;    // LPUART_STOPBITS           
+    uint8_t  Parity;     // LPUART_PARITY_SELECT   
+    uint8_t  ClockSrc;   // LPUART_CLOCK_SOURCE   
+    uint32_t BaudRate;   
+}LPUART_ConfigParam;
+
+/** 
+  * @brief  LPUART  Config structure definition
+  */
+typedef struct
+{
+    uint8_t  Wakeup_Source;  // Wakeup_Source  
+    uint8_t  Wakeup_Check;  // Wakeup_Check 
+    uint8_t  Wakeup_Addr;  // Wakeup_Addr 
+ 
+}LPUART_StopWakeupDef;
+
+
+
+/** 
+  * @brief  LPUART  init structure definition
+  */
+typedef struct
+{
+    LPUART_TypeDef *Instance;
+    LPUART_ConfigParam ConfigParam;  
+    LPUART_StopWakeupDef StopWakeup;  
+    volatile uint8_t *rx_buffer;  
+    volatile uint16_t rx_buffer_size;  
+    volatile uint16_t rx_write_index;  
+    volatile uint16_t rx_read_index;    
+    volatile uint16_t tx_busy;   
+    DMA_HandleTypeDef *dma_rx_handler;  
+	DMA_HandleTypeDef *dma_tx_handler;  	
+}LPUART_HandleTypeDef;
+
+/* HAL_LPUART_Init */
+HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart);
+
+HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart);
+
+void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart);
+
+void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart);
+
+/* HAL_LPUART_Send_Bytes */
+void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);  
+
+/* HAL_LPUART_IRQHander */
+void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart); 
+
+/* HAL_LPUART_Receive_Bytes_Timeout */
+uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms);   
+
+/* HAL_LPUART_Receive_Bytes */
+uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length);
+
+/* HAL_LPUART_DMA_Send_Bytes */
+void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length);  
+
+/* HAL_LPUART_Clear_Wakeup_Flags */
+void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits); 
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_OPA.h

@@ -0,0 +1,187 @@
+/*
+  ******************************************************************************
+  * @file    HAL_OPA.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of OPA HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_OPA_H__
+#define __HAL_OPA_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Bit definition for OPA_CR1 and OPA_CR2 register  **************************/
+#define OPA_CSR_LOCK                           (BIT31)
+#define OPA_CSR_HSM                            (BIT28)
+#define OPA_CSR_GAIN_SEL_POS                   (23U)
+#define OPA_CSR_GAIN_SEL_MASK                  (BIT27|BIT26|BIT25|BIT24|BIT23)
+#define OPA_CSR_POL_SEL_POS                    (21U)
+#define OPA_CSR_POL_SEL_MASK                   (BIT22|BIT21)
+#define OPA_CSR_VINM0_SEL_POS                  (BIT20)
+#define OPA_CSR_MODE_SEL_POS                   (18U)
+#define OPA_CSR_MODE_SEL_MASK                  (BIT19|BIT18)
+#define OPA_CSR_VINP_SEL_POS                   (16U)
+#define OPA_CSR_VINP_SEL_MASK                  (BIT17|BIT16)
+#define OPA_CSR_OUT_SEL_POS                    (14U)
+#define OPA_CSR_OUT_SEL_MASK                   (BIT14|BIT15)
+#define OPA_CSR_TRIM_OSN_POS                   (9U)
+#define OPA_CSR_TRIM_OSN_MASK                  (BIT13|BIT12|BIT11|BIT10|BIT9)
+#define OPA_CSR_TRIM_OSP_POS                   (4U)
+#define OPA_CSR_TRIM_OSP_MASK                  (BIT8|BIT7|BIT6|BIT5|BIT4)
+#define OPA_CSR_CAL_OUT                        (BIT3)
+#define OPA_CSR_CAL_NEN                        (BIT2)
+#define OPA_CSR_CAL_PEN                        (BIT1)
+#define OPA_CSR_EN                             (BIT0)
+
+/** @defgroup OPAx Index
+  * @{
+  */
+#define OPA1        (0x01)
+#define OPA2        (0x02)
+#define OPA3        (0x03)
+
+/** @defgroup HSM driver mode
+  * @{
+  */
+#define OPA_HSM_LOW         (0u)
+#define OPA_HSM_HIGH        (1u)
+
+/** @defgroup OPA Gain select.
+  * @{
+  */
+#define OPA_GAIN_64_63           (0u)
+#define OPA_GAIN_32_31           (1u)
+#define OPA_GAIN_16_15           (2u)
+#define OPA_GAIN_8_7             (4u)
+#define OPA_GAIN_4_3             (8u)
+#define OPA_GAIN_2_1             (16u)
+
+/** @defgroup Polarity select.
+  * @{
+  */
+#define OPA_POL_NONINVERT        (0u)
+#define OPA_POL_INVERT           (1u)
+
+/** @defgroup OPA work mode select.
+  * @{
+  */
+#define OPA_MODE_SA              (0u)
+#define OPA_MODE_UG              (1u)
+#define OPA_MODE_PGA             (2u)
+#define OPA_MODE_SA1             (3u)
+
+/** @defgroup OPA VINP vin p select.
+  * @{
+  */
+#define OPA_VINP_0           (0u)
+#define OPA_VINP_1           (1u)
+#define OPA_VINP_2           (2u)
+#define OPA_VINP_3             (3u)
+
+/** @defgroup OPA output select.
+  * @{
+  */
+#define OPA_OUT_GPIO             (0u)
+#define OPA_OUT_INTERNAL         (1u)
+
+/** @defgroup OPA VINM0 enable.
+  * @{
+  */
+#define OPA_CSR_VINM0_DISABLE           (0U)   
+#define OPA_CSR_VINM0_ENABLE            (1U)
+
+/** @defgroup OPA trim enable.
+  * @{
+  */
+#define OPA_CSR_TRIM_DISABLE           (0U)   
+#define OPA_CSR_TRIM_ENABLE            (1U)   
+
+/**
+  * @brief  OPA Configuration Structure definition
+  */
+typedef struct
+{
+    uint8_t             OpaX;       /*!< Specify witch opa be selected */
+    uint8_t             Hsm;        /*!< Specify the opa HSM driver mode:OPA_HSM_LOW or OPA_HSM_HIGH */
+    uint8_t             Gain;       /*!< Specify the opa gain select */
+    uint8_t             PolSel;     /*!< Specify the opa Polarity select */
+    uint8_t             VinM0En;    /*!< Specify the opa VinM0 enable */     
+    uint8_t             OpaMode;    /*!< Specify the opa work mode select */
+    uint8_t             VinPSel;    /*!< Specify the opa VINP vin p select */       
+    uint8_t             OutSel;     /*!< Specify the opa output select */  
+    uint8_t             TrimEn;     /*!< Specify if the opa auto trim */  
+}OPA_InitTypeDef;
+
+/**
+  * @brief  OPA handle Structure definition
+  */
+typedef struct
+{
+  OPA_TypeDef       *Instance;       /*!< Register base address    */
+  OPA_InitTypeDef   Init;            /*!< OPA required parameters */
+} OPA_HandleTypeDef;
+
+/******************************** OPA Instances *******************************/
+#define IS_OPA_ALL_INSTANCE(INSTANCE)      (((INSTANCE) == OPA))
+
+/******************************** OPA OPAX definition*******************************/
+#define IS_OPA_ALL_OPAX(_OPAX)         (((_OPAX) == OPA1) || \
+                                        ((_OPAX) == OPA2) || \
+                                        ((_OPAX) == OPA3))
+
+/******************************** OPA HSM definition*******************************/
+#define IS_OPA_ALL_HSM(_HSM)           (((_HSM) == OPA_HSM_LOW) || \
+                                        ((_HSM) == OPA_HSM_HIGH))
+
+/******************************** OPA GAIN definition*******************************/
+#define IS_OPA_ALL_GAIN(_GAIN)         (((_GAIN) == OPA_GAIN_64_63) || \
+                                        ((_GAIN) == OPA_GAIN_32_31) || \
+                                        ((_GAIN) == OPA_GAIN_16_15) || \
+                                        ((_GAIN) == OPA_GAIN_8_7) || \
+                                        ((_GAIN) == OPA_GAIN_4_3) || \
+                                        ((_GAIN) == OPA_GAIN_2_1))
+
+/******************************** OPA Polarity definition*******************************/
+#define IS_OPA_ALL_POL(_POL)           (((_POL) == OPA_POL_NONINVERT) || \
+                                        ((_POL) == OPA_POL_INVERT))
+
+/******************************** OPA work mode definition*******************************/
+#define IS_OPA_ALL_MODE(_MODE)         (((_MODE) == OPA_MODE_SA) || \
+                                        ((_MODE) == OPA_MODE_UG) || \
+                                        ((_MODE) == OPA_MODE_PGA) || \
+                                        ((_MODE) == OPA_MODE_SA1))
+                                        
+/******************************** OPA VINP select definition*******************************/
+#define IS_OPA_ALL_VINP(_VINP)         (((_VINP) == OPA_VINP_0) || \
+                                        ((_VINP) == OPA_VINP_1) || \
+                                        ((_VINP) == OPA_VINP_2) || \
+                                        ((_VINP) == OPA_VINP_3))
+                                        
+/******************************** OPA OUT select definition*******************************/
+#define IS_OPA_ALL_OUT(_OUT)           (((_OUT) == OPA_OUT_GPIO) || \
+                                        ((_OUT) == OPA_OUT_INTERNAL))
+
+/******************************** OPA VINM0 enable definition*******************************/
+#define IS_OPA_ALL_VINM0(_VINM0)       (((_VINM0) == OPA_CSR_VINM0_DISABLE) || \
+                                        ((_VINM0) == OPA_CSR_VINM0_ENABLE))
+                                        
+/******************************** OPA trim enable definition*******************************/
+#define IS_OPA_ALL_TRIM(_TRIM)         (((_TRIM) == OPA_CSR_TRIM_DISABLE) || \
+                                        ((_TRIM) == OPA_CSR_TRIM_ENABLE))
+
+/* Function : HAL_OPA */
+void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa);
+void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_DeInit(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Enable(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa);
+HAL_StatusTypeDef HAL_OPA_Lock(OPA_HandleTypeDef* hopa);
+
+#endif
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_RTC.h

@@ -0,0 +1,685 @@
+/*
+  ******************************************************************************
+  * @file    HAL_RTC.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of RTC HAL module.
+  ******************************************************************************
+*/
+
+#ifndef __HAL_RTC_H__
+#define __HAL_RTC_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************************/
+/*                             Registers Bits Definition                            */
+/************************************************************************************/
+
+/****************  Bit definition for RTC IE Register  ***********************/
+#define RTC_IE_STP2RIE       (BIT16)
+#define RTC_IE_STP2FIE       (BIT15)
+#define RTC_IE_STP1RIE       (BIT14)
+#define RTC_IE_STP1FIE       (BIT13)
+#define RTC_IE_ADJ32         (BIT12)    
+#define RTC_IE_ALM           (BIT11)
+#define RTC_IE_1KHZ          (BIT10)
+#define RTC_IE_256HZ         (BIT9)
+#define RTC_IE_64HZ          (BIT8)
+#define RTC_IE_16HZ          (BIT7)
+#define RTC_IE_8HZ           (BIT6)
+#define RTC_IE_4HZ           (BIT5)
+#define RTC_IE_2HZ           (BIT4)
+#define RTC_IE_SEC           (BIT3)
+#define RTC_IE_MIN           (BIT2)
+#define RTC_IE_HOUR          (BIT1)
+#define RTC_IE_DATE          (BIT0)
+
+/****************  Bit definition for RTC SR Register  ***********************/
+#define RTC_SR_STP2RIE       (BIT16)
+#define RTC_SR_STP2FIE       (BIT15)
+#define RTC_SR_STP1RIE       (BIT14)
+#define RTC_SR_STP1FIE       (BIT13)
+#define RTC_SR_ADJ32         (BIT12)    
+#define RTC_SR_ALM           (BIT11)
+#define RTC_SR_1KHZ          (BIT10)
+#define RTC_SR_256HZ         (BIT9)
+#define RTC_SR_64HZ          (BIT8)
+#define RTC_SR_16HZ          (BIT7)
+#define RTC_SR_8HZ           (BIT6)
+#define RTC_SR_4HZ           (BIT5)
+#define RTC_SR_2HZ           (BIT4)
+#define RTC_SR_SEC           (BIT3)
+#define RTC_SR_MIN           (BIT2)
+#define RTC_SR_HOUR          (BIT1)
+#define RTC_SR_DATE          (BIT0)
+
+/****************  Bit definition for RTC CR Register  ***********************/
+#define RTC_CR_TAMPFLTCLK    (BIT22)
+#define RTC_CR_TS2EDGE       (BIT21)
+#define RTC_CR_TAMP2FLT      (BIT19|BIT20)
+#define RTC_CR_TAMP2FLTEN    (BIT18)
+#define RTC_CR_TAMP2FCLR     (BIT17)
+#define RTC_CR_TAMP2RCLR     (BIT16)
+#define RTC_CR_TS1EDGE       (BIT15)
+#define RTC_CR_TAMP1FLT      (BIT13|BIT14)
+#define RTC_CR_TAMP1FLTEN    (BIT12)
+#define RTC_CR_ALM_MKSD      (BIT11)
+#define RTC_CR_ALM_MSKH      (BIT10)
+#define RTC_CR_ALM_MSKM      (BIT9)
+#define RTC_CR_TAMP1FCLR     (BIT8)
+#define RTC_CR_TAMP1RCLR     (BIT7)
+#define RTC_CR_TAMP2EN       (BIT6)
+#define RTC_CR_TAMP1EN       (BIT5)
+#define RTC_CR_ALM_EN        (BIT4)
+#define RTC_CR_FSEL          (BIT0|BIT1|BIT2|BIT3)
+
+/****************  Bit definition for RTC_PMU CR Register  ***********************/
+#define RPMU_CR_WU6FILEN            BIT29
+#define RPMU_CR_WU5FILEN            BIT28
+#define RPMU_CR_WU4FILEN            BIT27
+#define RPMU_CR_WU3FILEN            BIT26
+#define RPMU_CR_WU2FILEN            BIT25
+#define RPMU_CR_WU1FILEN            BIT24
+#define RPMU_CR_EWUP6               BIT21
+#define RPMU_CR_EWUP5               BIT20
+#define RPMU_CR_EWUP4               BIT19
+#define RPMU_CR_EWUP3               BIT18
+#define RPMU_CR_EWUP2               BIT17
+#define RPMU_CR_EWUP1               BIT16
+#define RPMU_CR_BORRST_EN           BIT12
+#define RPMU_CR_WK_TIME            (BIT9|BIT10|BIT11)
+#define RPMU_CR_STB_EN              BIT8
+#define RPMU_CR_BDRST               BIT6
+#define RPMU_CR_RTCEN               BIT5
+#define RPMU_CR_RTCSEL             (BIT2|BIT3)
+#define RPMU_CR_CWUF                BIT1
+#define RPMU_CR_CSBF                BIT0
+
+/****************  Bit definition for RTC_PMU ANACR Register  ***********************/
+#define RPMU_SR_BORWUF              BIT13
+#define RPMU_SR_IWDTWUF             BIT12
+#define RPMU_SR_RSTWUF              BIT11
+#define RPMU_SR_RTCWUF              BIT10
+#define RPMU_SR_WUP6F               BIT6
+#define RPMU_SR_WUP5F               BIT5
+#define RPMU_SR_WUP4F               BIT4
+#define RPMU_SR_WUP3F               BIT3
+#define RPMU_SR_WUP2F               BIT2
+#define RPMU_SR_WUP1F               BIT1
+#define RPMU_SR_SBF                 BIT0
+
+/****************  Bit definition for RTC_PMU ANACR Register  ***********************/
+#define RPMU_ANACR_BOR_CFG                 (BIT24|BIT25)
+#define RPMU_ANACR_BOR_EN                   BIT23
+#define RPMU_ANACR_LPBGR_TRIM              (BIT20|BIT21|BIT22)
+#define RPMU_ANACR_RC32K_TRIM              (BIT10|BIT11|BIT12|BIT13|BIT14|BIT15)
+#define RPMU_ANACR_RC32K_RDY                BIT9
+#define RPMU_ANACR_RC32K_EN                 BIT8
+#define RPMU_ANACR_XTLDRV_2                 BIT5
+#define RPMU_ANACR_XTLDRV_1                 BIT4
+#define RPMU_ANACR_XTLDRV_0                 BIT3
+#define RPMU_ANACR_XTLDRV                  (BIT3|BIT4|BIT5)
+#define RPMU_ANACR_XTLBYO                   BIT2
+#define RPMU_ANACR_XTLRDY                   BIT1
+#define RPMU_ANACR_XTLEN                    BIT0
+
+
+/** @defgroup ClockSource
+  * @{
+  */
+#define RTC_CLOCK_RC32K       (0x00000000)
+#define RTC_CLOCK_XTL         (0x00000004)
+/**
+  * @}
+  */
+
+
+/** @defgroup Clock_Compensation
+  * @{
+  */
+#define COMPENSATION_INCREASE      (0x00000000)
+#define COMPENSATION_DECREASE      (0x00000400)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+  * @{
+  */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY           (0x01)
+#define RTC_MONTH_FEBRUARY          (0x02)
+#define RTC_MONTH_MARCH             (0x03)
+#define RTC_MONTH_APRIL             (0x04)
+#define RTC_MONTH_MAY               (0x05)
+#define RTC_MONTH_JUNE              (0x06)
+#define RTC_MONTH_JULY              (0x07)
+#define RTC_MONTH_AUGUST            (0x08)
+#define RTC_MONTH_SEPTEMBER         (0x09)
+#define RTC_MONTH_OCTOBER           (0x10)
+#define RTC_MONTH_NOVEMBER          (0x11)
+#define RTC_MONTH_DECEMBER          (0x12)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+  * @{
+  */
+#define RTC_WEEKDAY_MONDAY          (0x01)
+#define RTC_WEEKDAY_TUESDAY         (0x02)
+#define RTC_WEEKDAY_WEDNESDAY       (0x03)
+#define RTC_WEEKDAY_THURSDAY        (0x04)
+#define RTC_WEEKDAY_FRIDAY          (0x05)
+#define RTC_WEEKDAY_SATURDAY        (0x06)
+#define RTC_WEEKDAY_SUNDAY          (0x07)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Alarm_Mode Definitions
+  * @{
+  */
+#define RTC_ALARM_WEEK_MODE       (0x00000000)
+#define RTC_ALARM_DAY_MODE        (0x80000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_AlarmInterrupt Definitions
+  * @{
+  */
+#define RTC_ALARM_INT_ENABLE       (0x00000000)
+#define RTC_ALARM_INT_DISABLE      (0x00000001)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_DayMask Definitions
+  * @{
+  */
+#define RTC_ALARM_DAY_MASK_ENABLE       RTC_CR_ALM_MKSD
+#define RTC_ALARM_DAY_MASK_DISABLE      (0x00000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_HourMask Definitions
+  * @{
+  */
+#define RTC_ALARM_HOUR_MASK_ENABLE       RTC_CR_ALM_MSKH
+#define RTC_ALARM_HOUR_MASK_DISABLE      (0x00000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_MinMask Definitions
+  * @{
+  */
+#define RTC_ALARM_MIN_MASK_ENABLE       RTC_CR_ALM_MSKM
+#define RTC_ALARM_MIN_MASK_DISABLE      (0x00000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Alarm_WeekSelect Definitions
+  * @{
+  */
+#define RTC_ALARM_WEEK_SUNDAY       (0x01000000)
+#define RTC_ALARM_WEEK_MONDAY       (0x02000000)
+#define RTC_ALARM_WEEK_TUESDAY      (0x04000000)
+#define RTC_ALARM_WEEK_WEDNESDAY    (0x08000000)
+#define RTC_ALARM_WEEK_THURSDAY     (0x10000000)
+#define RTC_ALARM_WEEK_FRIDAY       (0x20000000)
+#define RTC_ALARM_WEEK_SATURDAY     (0x40000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Temper_edge Definitions
+  * @{
+  */
+#define RTC_TEMP_EDGE_RISING       (0x00000000)
+#define RTC_TEMP_EDGE_FALLING      (0x00000001)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_TemperInterrupt Definitions
+  * @{
+  */
+#define RTC_TEMP_INT_DISABLE      (0x00000000)
+#define RTC_TEMP_INT_ENABLE       (0x00000001)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_ClearBackup Definitions
+  * @{
+  */
+#define RTC_TEMP_CLEAR_DISABLE       (0x00000000)
+#define RTC_TEMP_CLEAR_ENABLE        (0x00000001)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_TemperFilter Definitions
+  * @{
+  */
+#define RTC_TEMP_FILTER_DISABLE         (0x00000000)
+#define RTC_TEMP_FILTER_512_RTCCLK      (0x00000001)
+#define RTC_TEMP_FILTER_1_RTCCLK        (0x00000002)
+#define RTC_TEMP_FILTER_2_RTCCLK        (0x00000003)
+#define RTC_TEMP_FILTER_4_RTCCLK        (0x00000004)
+#define RTC_TEMP_FILTER_8_RTCCLK        (0x00000005)
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  RTC Temper index definition
+  */
+typedef enum
+{
+    RTC_TEMPER_1,
+    RTC_TEMPER_2,
+}enum_Temper_t;
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  RTC wakeup source form standby
+  */
+typedef enum
+{
+    RTC_WAKEUP_RTC_INT = 0,
+    RTC_WAKEUP_WKUP1  = 0x00010000,  // PA0
+    RTC_WAKEUP_WKUP2  = 0x00020000,  // PC13   
+    RTC_WAKEUP_WKUP3  = 0x00040000,  // PA2 
+    RTC_WAKEUP_WKUP4  = 0x00080000,  // PC5  
+    RTC_WAKEUP_WKUP5  = 0x00100000,  // PB5  
+    RTC_WAKEUP_WKUP6  = 0x00200000,  // PB15  
+    RTC_WAKEUP_STAMP2 = (RTC_IE_STP2RIE | RTC_IE_STP2FIE),
+    RTC_WAKEUP_STAMP1 = (RTC_IE_STP1RIE | RTC_IE_STP1FIE),
+    RTC_WAKEUP_32S    = RTC_IE_ADJ32,
+    RTC_WAKEUP_ALARM  = RTC_IE_ALM,
+    RTC_WAKEUP_SEC    = RTC_IE_SEC,
+    RTC_WAKEUP_MIN    = RTC_IE_MIN,
+    RTC_WAKEUP_HOUR   = RTC_IE_HOUR,
+    RTC_WAKEUP_DATE   = RTC_IE_DATE,
+}enum_WKUP_t; 
+
+#define STANDBY_WAKEUP_RISING     0  
+#define STANDBY_WAKEUP_FALLING    1     
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Check RTC wakeup source form standby
+  */
+#define RTC_WAKEUP_SOURCE_BORWUF    (0x00002000)
+#define RTC_WAKEUP_SOURCE_IWDTWUF   (0x00001000)
+#define RTC_WAKEUP_SOURCE_RSTWUF    (0x00000800)
+#define RTC_WAKEUP_SOURCE_RTCWUF    (0x00000400)
+#define RTC_WAKEUP_SOURCE_WKUP6     (0x00000040)
+#define RTC_WAKEUP_SOURCE_WKUP5     (0x00000020)
+#define RTC_WAKEUP_SOURCE_WKUP4     (0x00000010)
+#define RTC_WAKEUP_SOURCE_WKUP3     (0x00000008)
+#define RTC_WAKEUP_SOURCE_WKUP2     (0x00000004)
+#define RTC_WAKEUP_SOURCE_WKUP1     (0x00000002)
+/**
+  * @}
+  */
+
+/**
+  * @brief  RTC Configuration Structure definition
+  */
+typedef struct
+{
+    uint32_t u32_ClockSource;           /*!< The RTC Clock Source to be configured. 
+                                             This parameter can be a value of @ref ClockSource */
+
+    uint32_t u32_Compensation;          /*!< The RTC Clock Compensation to be configured. 
+                                             This parameter can be a value of @ref Clock_Compensation */
+
+    uint32_t u32_CompensationValue;     /*!< The RTC Clock Compensation Value to be configured. 
+                                             This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x1FF */
+}RTC_ConfigTypeDef;
+
+
+/**
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+    uint8_t u8_Year;     /*!< Specifies the RTC Date Year.
+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x99 */
+
+    uint8_t u8_Month;    /*!< Specifies the RTC Date Month (in BCD format).
+                              This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+    uint8_t u8_Date;     /*!< Specifies the RTC Date.
+                              This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31 */
+
+    uint8_t u8_WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                              This parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_DateTypeDef;
+/* Attention: Year、Month、Date、Week use BCD code */
+
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+    uint8_t u8_Hours;       /*!< Specifies the RTC Time Hour.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23 */
+
+    uint8_t u8_Minutes;     /*!< Specifies the RTC Time Minutes.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */
+
+    uint8_t u8_Seconds;     /*!< Specifies the RTC Time Seconds.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */
+}RTC_TimeTypeDef;
+/* Attention: Hour、Minute、Second use BCD code */
+
+
+/**
+  * @brief  RTC Time structure definition
+  */
+typedef struct
+{
+    uint32_t u32_AlarmMode;         /*!< Specifies the RTC alarm Mode.
+                                         This parameter can be a value of @ref RTC_Alarm_Mode */
+
+    uint32_t u32_AlarmInterrupt;    /*!< Specifies the RTC alarm interrupt Enable or Disable.
+                                         This parameter can be a value of @ref RTC_AlarmInterrupt */
+
+    uint32_t u32_DayMask;           /*!< Specifies the RTC alarm Day/Week Mask. 
+                                         This parameter can be a value of @ref RTC_DayMask */
+    
+    uint32_t u32_HourMask;          /*!< Specifies the RTC alarm Hour Mask. 
+                                         This parameter can be a value of @ref RTC_HourMask */
+    
+    uint32_t u32_MinMask;           /*!< Specifies the RTC alarm Min Mask. 
+                                         This parameter can be a value of @ref RTC_MinMask */
+    
+    uint32_t u32_AlarmWeek;         /*!< Specifies the RTC alarm week select(Select WeekMode this parameter is valid).
+                                         This parameter can be a value of @ref RTC_Alarm_WeekSelect */
+    
+    uint32_t u32_AlarmDay;          /*!< Specifies the RTC alarm day  select(Select DayMode this parameter is valid).
+                                         This parameter must be a number between Min_Data = 0x01 and Max_Data = 0x31 */
+    
+    uint32_t u32_Hours;             /*!< Specifies the RTC alarm Hour.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x23 */
+
+    uint32_t u32_Minutes;           /*!< Specifies the RTC alarm Minutes.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */
+
+    uint32_t u32_Seconds;           /*!< Specifies the RTC alarm Seconds.
+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x59 */
+}RTC_AlarmTypeDef;
+
+
+/**
+  * @brief  RTC Temper structure definition
+  */
+typedef struct 
+{
+    uint32_t u32_TemperEdge;      /*!< Specifies the RTC Temper edge select.
+                                       This parameter can be a value of @ref RTC_Temper_edge */
+
+    uint32_t u32_InterruptEN;     /*!< Specifies the RTC Temper interrupt enable.
+                                       This parameter can be a value of @ref RTC_TemperInterrupt */
+
+    uint32_t u32_ClearBackup;     /*!< Specifies the RTC Temper clear backup register.
+                                       This parameter can be a value of @ref RTC_ClearBackup */
+
+    uint32_t u32_Filter;          /*!< Specifies the RTC Temper Filter select.
+                                       This parameter can be a value of @ref RTC_TemperFilter */
+}RTC_TemperTypeDef;
+
+
+/** @brief  PC13 function select 
+  * @param  __FUNC__: PC13 function select.
+  *         This parameter can be 0: GPIO�1�RTC Fout�2�RTC tamper 3�PC13 Value
+  */
+#define __HAL_RTC_PC13_SEL(__FUNC__)    (PMU->IOSEL |= (PMU->IOSEL & ~(0x3)) | (__FUNC__))
+
+/** @brief  PC14 function select 
+  * @param  __FUNC__: PC14 function select.
+  *         This parameter can be 0: GPIO�1�PC14 Value
+  */
+#define __HAL_RTC_PC14_SEL(__FUNC__)    (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 3)) | (__FUNC__ << 3))
+
+/** @brief  PC15 function select 
+  * @param  __FUNC__: PC15 function select.
+  *         This parameter can be 0: GPIO�1�PC15 Value
+  */
+#define __HAL_RTC_PC15_SEL(__FUNC__)    (PMU->IOSEL |= (PMU->IOSEL & ~(0x3 << 5)) | (__FUNC__ << 5))
+
+/** @brief  PC13 Value set 
+  * @param  __FUNC__: PC13 Value set.
+  *         This parameter can be 0: set�1�claer
+  */
+#define __HAL_RTC_PC13_VALUE(__VALUE__)    (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 8)) | (__VALUE__ << 8))
+
+/** @brief  PC14 Value set 
+  * @param  __FUNC__: PC14 Value set.
+  *         This parameter can be 0: set�1�claer
+  */
+#define __HAL_RTC_PC14_VALUE(__VALUE__)    (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 9)) | (__VALUE__ << 9))
+
+/** @brief  PC15 Value set 
+  * @param  __FUNC__: PC15 Value set.
+  *         This parameter can be 0: set�1�claer
+  */
+#define __HAL_RTC_PC15_VALUE(__VALUE__)    (PMU->IOSEL |= (PMU->IOSEL & ~(1 << 10)) | (__VALUE__ << 10))
+
+/* @brief  PC13、PC14、PC15 pull up or pull down */
+#define __HAL_RTC_PC13_PULL_UP_ENABLE()       (PMU->IOCR |=  BIT0)
+#define __HAL_RTC_PC13_PULL_UP_DISABLE()      (PMU->IOCR &= ~BIT0)
+#define __HAL_RTC_PC13_PULL_DOWN_ENABLE()     (PMU->IOCR |=  BIT1)
+#define __HAL_RTC_PC13_PULL_DOWN_DISABLE()    (PMU->IOCR &= ~BIT1)
+
+#define __HAL_RTC_PC14_PULL_UP_ENABLE()       (PMU->IOCR |=  BIT8)
+#define __HAL_RTC_PC14_PULL_UP_DISABLE()      (PMU->IOCR &= ~BIT8)
+#define __HAL_RTC_PC14_PULL_DOWN_ENABLE()     (PMU->IOCR |=  BIT9)
+#define __HAL_RTC_PC14_PULL_DOWN_DISABLE()    (PMU->IOCR &= ~BIT9)
+
+#define __HAL_RTC_PC15_PULL_UP_ENABLE()       (PMU->IOCR |=  BIT16)
+#define __HAL_RTC_PC15_PULL_UP_DISABLE()      (PMU->IOCR &= ~BIT16)
+#define __HAL_RTC_PC15_PULL_DOWN_ENABLE()     (PMU->IOCR |=  BIT17)
+#define __HAL_RTC_PC15_PULL_DOWN_DISABLE()    (PMU->IOCR &= ~BIT17)
+
+/* @brief  PC13、PC14、PC15 digit or analog */
+#define __HAL_RTC_PC13_ANALOG()    (PMU->IOCR |=  BIT6)
+#define __HAL_RTC_PC13_DIGIT()     (PMU->IOCR &= ~BIT6)
+
+#define __HAL_RTC_PC14_ANALOG()    (PMU->IOCR |=  BIT14)
+#define __HAL_RTC_PC14_DIGIT()     (PMU->IOCR &= ~BIT14)
+
+#define __HAL_RTC_PC15_ANALOG()    (PMU->IOCR |=  BIT22)
+#define __HAL_RTC_PC15_DIGIT()     (PMU->IOCR &= ~BIT22)
+
+
+/** @defgroup  RTC Private Macros
+  * @{
+  */
+#define IS_RTC_CLOCKSRC(__CLOCKSRC__)     (((__CLOCKSRC__) == RTC_CLOCK_RC32K) || \
+                                           ((__CLOCKSRC__) == RTC_CLOCK_XTL))
+
+#define IS_RTC_COMPENSATION(__COMPENSATION__)     (((__COMPENSATION__) == COMPENSATION_INCREASE) || \
+                                                   ((__COMPENSATION__) == COMPENSATION_DECREASE))
+
+#define IS_RTC_YEAR(__YEAR__)       ((__YEAR__) >= 0x00 && (__YEAR__) <= 0x99)
+
+#define IS_RTC_MONTH(__MONTH__)     (((__MONTH__) == RTC_MONTH_JANUARY)   || \
+                                     ((__MONTH__) == RTC_MONTH_FEBRUARY)  || \
+                                     ((__MONTH__) == RTC_MONTH_MARCH)     || \
+                                     ((__MONTH__) == RTC_MONTH_APRIL)     || \
+                                     ((__MONTH__) == RTC_MONTH_MAY)       || \
+                                     ((__MONTH__) == RTC_MONTH_JUNE)      || \
+                                     ((__MONTH__) == RTC_MONTH_JULY)      || \
+                                     ((__MONTH__) == RTC_MONTH_AUGUST)    || \
+                                     ((__MONTH__) == RTC_MONTH_SEPTEMBER) || \
+                                     ((__MONTH__) == RTC_MONTH_OCTOBER)   || \
+                                     ((__MONTH__) == RTC_MONTH_NOVEMBER)  || \
+                                     ((__MONTH__) == RTC_MONTH_DECEMBER))
+
+#define IS_RTC_DAY(__DAY__)          ((__DAY__) >= 0x01 && (__DAY__) <= 0x31)
+
+#define IS_RTC_WEEKDAY(__WEEKDAY__)   (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY)    || \
+                                       ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY)   || \
+                                       ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \
+                                       ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY)  || \
+                                       ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY)    || \
+                                       ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY)  || \
+                                       ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_HOUR(__HOUR__)    ((__HOUR__) >= 0x00 && (__HOUR__) <= 0x23)
+
+#define IS_RTC_MIN(__MIN__)      ((__MIN__) >= 0x00 && (__MIN__) <= 0x59)
+
+#define IS_RTC_SEC(__SEC__)      ((__SEC__) >= 0x00 && (__SEC__) <= 0x59)
+
+
+#define IS_RTC_ALARM_MODE(__MODE__)      (((__MODE__) == RTC_ALARM_WEEK_MODE) || \
+                                          ((__MODE__) == RTC_ALARM_DAY_MODE))
+
+#define IS_RTC_ALARM_INT(__INT__)        (((__INT__) == RTC_ALARM_INT_ENABLE) || \
+                                          ((__INT__) == RTC_ALARM_INT_DISABLE))
+
+#define IS_RTC_ALARM_DAY_MASK(__MASKD__)     (((__MASKD__) == RTC_ALARM_DAY_MASK_ENABLE) || \
+                                              ((__MASKD__) == RTC_ALARM_DAY_MASK_DISABLE))
+                                              
+#define IS_RTC_ALARM_HOUR_MASK(__MASKH__)    (((__MASKH__) == RTC_ALARM_HOUR_MASK_ENABLE) || \
+                                              ((__MASKH__) == RTC_ALARM_HOUR_MASK_DISABLE))
+
+#define IS_RTC_ALARM_MIN_MASK(__MASKM__)     (((__MASKM__) == RTC_ALARM_MIN_MASK_ENABLE) || \
+                                              ((__MASKM__) == RTC_ALARM_MIN_MASK_DISABLE))
+
+#define IS_RTC_ALARM_WEEKDAY(__WEEKDAY__)    (((__WEEKDAY__) == RTC_ALARM_WEEK_SUNDAY)    || \
+                                              ((__WEEKDAY__) == RTC_ALARM_WEEK_MONDAY)    || \
+                                              ((__WEEKDAY__) == RTC_ALARM_WEEK_TUESDAY)   || \
+                                              ((__WEEKDAY__) == RTC_ALARM_WEEK_WEDNESDAY) || \
+                                              ((__WEEKDAY__) == RTC_ALARM_WEEK_THURSDAY)  || \
+                                              ((__WEEKDAY__) == RTC_ALARM_WEEK_FRIDAY)    || \
+                                              ((__WEEKDAY__) == RTC_ALARM_WEEK_SATURDAY)  || \
+                                              ((__WEEKDAY__) >= 0x01000000 && (__WEEKDAY__) <= 0x7F000000))
+
+
+#define IS_RTC_TEMP_EDGE(__EDGE__)           (((__EDGE__) == RTC_TEMP_EDGE_RISING) || \
+                                              ((__EDGE__) == RTC_TEMP_EDGE_FALLING))
+
+#define IS_RTC_TEMP_INT(__INT__)             (((__INT__) == RTC_TEMP_INT_ENABLE) || \
+                                              ((__INT__) == RTC_TEMP_INT_DISABLE))
+
+#define IS_RTC_TEMP_CLEAR_BACKUP(__CLEAR__)    (((__CLEAR__) == RTC_TEMP_CLEAR_DISABLE) || \
+                                                ((__CLEAR__) == RTC_TEMP_CLEAR_ENABLE))
+
+#define IS_RTC_TEMP_FILTER(__FILTER__)         (((__FILTER__) == RTC_TEMP_FILTER_DISABLE)    || \
+                                                ((__FILTER__) == RTC_TEMP_FILTER_512_RTCCLK) || \
+                                                ((__FILTER__) == RTC_TEMP_FILTER_1_RTCCLK)   || \
+                                                ((__FILTER__) == RTC_TEMP_FILTER_2_RTCCLK)   || \
+                                                ((__FILTER__) == RTC_TEMP_FILTER_4_RTCCLK)   || \
+                                                ((__FILTER__) == RTC_TEMP_FILTER_8_RTCCLK))
+/**
+  * @}
+  */
+
+/* RTC stamp1 interrupt enable、disable */
+#define __HAL_RTC_ENABLE_STAMP1_IT         (RTC->IE |= (RTC_IE_STP1RIE | RTC_IE_STP1FIE))
+#define __HAL_RTC_DISABLE_STAMP1_IT        (RTC->IE &= ~(RTC_IE_STP1RIE | RTC_IE_STP1FIE))
+
+/* RTC stamp2 interrupt enable、disable */
+#define __HAL_RTC_ENABLE_STAMP2_IT         (RTC->IE |= (RTC_IE_STP2RIE | RTC_IE_STP2FIE))
+#define __HAL_RTC_DISABLE_STAMP2_IT        (RTC->IE &= ~(RTC_IE_STP2RIE | RTC_IE_STP2FIE))
+
+/* RTC 32S interrupt enable、disable */
+#define __HAL_RTC_ENABLE_32S_IT            (RTC->IE |= RTC_IE_ADJ32)
+#define __HAL_RTC_DISABLE_32S_IT           (RTC->IE &= ~RTC_IE_ADJ32)
+
+/* RTC alarm interrupt enable、disable */
+#define __HAL_RTC_ENABLE_ALM_IT            (RTC->IE |= RTC_IE_ALM)
+#define __HAL_RTC_DISABLE_ALM_IT           (RTC->IE &= RTC_IE_ALM)
+
+/* RTC sec interrupt enable、disable */
+#define __HAL_RTC_ENABLE_SEC_IT            (RTC->IE |= RTC_IE_SEC)
+#define __HAL_RTC_DISABLE_SEC_IT           (RTC->IE &= ~RTC_IE_SEC)
+
+/* RTC Minutes interrupt enable、disable */
+#define __HAL_RTC_ENABLE_MIN_IT            (RTC->IE |= RTC_IE_MIN)
+#define __HAL_RTC_DISABLE_MIN_IT           (RTC->IE &= ~RTC_IE_MIN)
+
+/* RTC Hour interrupt enable、disable */
+#define __HAL_RTC_ENABLE_HOUR_IT           (RTC->IE |= RTC_IE_HOUR)
+#define __HAL_RTC_DISABLE_HOUR_IT          (RTC->IE &= ~RTC_IE_HOUR)
+
+/* RTC Date interrupt enable、disable */
+#define __HAL_RTC_ENABLE_DATE_IT           (RTC->IE |= RTC_IE_DATE)
+#define __HAL_RTC_DISABLE_DATE_IT          (RTC->IE &= ~RTC_IE_DATE)
+
+/* HAL_RTC_Config */
+HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc);
+
+/* HAL_RTC_SetTime */
+void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time);
+
+/* HAL_RTC_GetTime */
+void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time);
+
+/* HAL_RTC_SetDate */
+void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date);
+
+/* HAL_RTC_GetDate */
+void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date);
+
+
+/* HAL_RTC_AlarmConfig */
+void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm);
+
+/* HAL_RTC_AlarmEnable */
+void HAL_RTC_AlarmEnable(void);
+
+/* HAL_RTC_AlarmDisable */
+void HAL_RTC_AlarmDisable(void);
+
+/* HAL_RTC_Tamper */
+void HAL_RTC_Tamper(enum_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper);
+
+/* HAL_RTC_TamperEnable */
+void HAL_RTC_TamperEnable(enum_Temper_t fe_Temper);
+
+/* HAL_RTC_TamperDisable */
+void HAL_RTC_TamperDisable(enum_Temper_t fe_Temper);
+
+/* HAL_RTC_Standby_Wakeup */
+void HAL_RTC_Standby_Wakeup(enum_WKUP_t fe_Wakeup, uint32_t fu32_Edge);
+
+/* HAL_RTC_Get_StandbyStatus */
+bool HAL_RTC_Get_StandbyStatus(void);
+
+/* HAL_RTC_Get_StandbyWakeupSource */
+uint32_t HAL_RTC_Get_StandbyWakeupSource(void);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA1.h

@@ -0,0 +1,77 @@
+/***********************************************************************
+ * Filename    : sha1.h
+ * Description : sha1 header file
+ * Author(s)   : firmware team   
+ * version     : V1.0
+ * Modify date : 2020-07-29
+ ***********************************************************************/
+#ifndef __SHA1_H__
+#define __SHA1_H__
+
+#include "ACM32Fxx_HAL.h"
+/**********************************************************
+*	structure
+**********************************************************/
+//SHA1 context
+typedef struct {
+  UINT32 state[5];        //state (ABCD)
+  UINT32 count[2];        // number of bits, modulo 2^64 (msb first) 
+  uint8_t  buffer[64];    // input buffer
+} SHA1_CTX;
+
+/**************************************************************************
+* Function Name  : HAL_SHA1_Init
+* Description    : SHA1 initialization. Begins an SHA1 operation, writing a new context.
+* Input          : None
+* Output         : - *context : the point of sha1 context
+* Return         : None
+**************************************************************************/
+void HAL_SHA1_Init(SHA1_CTX *context);	
+
+/**************************************************************************
+* Function Name  : HAL_SHA1_Update
+* Description    : SHA1 block update operation. Continues an SHA1 message-digest
+*				 : operation, processing another message block, and updating the
+*				 : context.
+* Input          : - *context : context before transform
+*				 : - *input   : input message
+*                : - inputlen : the byte length of input message
+* Output		 : - *context : context after transform
+* Return         : None
+**************************************************************************/
+void HAL_SHA1_Update(SHA1_CTX *context,uint8_t *input,UINT32 inputLen);
+
+/**************************************************************************
+* Function Name  : HAL_SHA1_Final
+* Description    : SHA1 finalization. Ends an MD5 message-digest operation, writing the
+*                : the message digest and zeroizing the context.
+* Input          : - *context : context before transform
+* Output		 : - *digest  : message digest
+* Return         : None
+**************************************************************************/
+void HAL_SHA1_Final(uint8_t *digest, SHA1_CTX *context);
+	
+/**************************************************************************
+* Function Name  : HAL_SHA1_Hash
+* Description    : transform message to digest in SHA1 algorithm
+* Input          : - *pDataIn : input message to be tranformed;
+				 : - DataLen  : the byte length of message;
+* Output		 : - *pDigest : output the digest;
+* Return         : None
+**************************************************************************/
+void HAL_SHA1_Hash(uint8_t *pDataIn,UINT32 DataLen,uint8_t *pDigest);
+	
+/**************************************************************************
+* Function Name  : SHA_encode
+* Description    : Encodes input (UINT32) into output (unsigned char)[Big-Endian]
+* Input          : - *input   : input data to be tranformed;
+				 : -  len     : byte len of the input data(len is a multiple of 4);
+* Output		 : - *output  : output data;
+* Return         : None
+**************************************************************************/
+void SHA_encode (uint8_t *output, UINT32 *input, UINT32 len);
+void SHA_memcpy (uint8_t *output,uint8_t *input, UINT32 len);
+void SHA_memset (uint8_t *output, int value, UINT32 len);
+
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SHA256.h

@@ -0,0 +1,77 @@
+/***********************************************************************
+ * Filename    : sha256.h
+ * Description : sha256 header file
+ * Author(s)   : Eric  
+ * version     : V1.0
+ * Modify date : 2020-07-09
+ ***********************************************************************/
+
+#ifndef __SHA256_H__
+#define __SHA256_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/**********************************************************
+*	structure
+**********************************************************/
+//SHA256 context
+typedef struct {
+  UINT32 state[8];                                   //state (ABCD)
+  UINT32 count[2];        // number of bits, modulo 2^64 (msb first) 
+  uint8_t  buffer[64];                         // input buffer
+} SHA256_CTX;
+
+/**********************************************************
+*	extern functions
+***********************************************************/
+void SHA_memcpy (uint8_t *output,uint8_t *input, UINT32 len);
+void SHA_memset (uint8_t *output, int value, UINT32 len);
+void SHA_encode (uint8_t *output, UINT32 *input, UINT32 len);
+/**********************************************************
+*	extern variable
+***********************************************************/
+extern const unsigned char PADDING[128];
+
+/**************************************************************************
+* Function Name  : HAL_SHA256_Init
+* Description    : SHA256 initialization. Begins an SHA1 operation, writing a new context.
+* Input          : None
+* Output         : - *context : the point of sha1 context
+* Return         : None
+**************************************************************************/
+void HAL_SHA256_Init(SHA256_CTX *context);
+	
+/**************************************************************************
+* Function Name  : HAL_SHA256_Update
+* Description    : SHA256 block update operation. Continues an SHA1 message-digest
+*				 : operation, processing another message block, and updating the
+*				 : context.
+* Input          : - *context : context before transform
+*				 : - *input   : input message
+*                : - inputlen : the byte length of input message
+* Output		 : - *context : context after transform
+* Return         : None
+**************************************************************************/
+void HAL_SHA256_Update(SHA256_CTX *context, uint8_t *input,UINT32 inputLen);
+
+/**************************************************************************
+* Function Name  : HAL_SHA256_Final
+* Description    : SHA256 finalization. Ends an SHA256 message-digest operation, writing the
+*                : the message digest and zeroizing the context.
+* Input          : - *context : context before transform
+* Output		 : - *digest  : message digest
+* Return         : None
+**************************************************************************/
+void HAL_SHA256_Final(uint8_t *digest, SHA256_CTX *context);
+
+/**************************************************************************
+* Function Name  : HAL_SHA256_Hash
+* Description    : transform message to digest in SHA1 algorithm
+* Input          : - *pDataIn : input message to be tranformed;
+				 : - DataLen  : the byte length of message;
+* Output		 : - *pDigest : output the digest;
+* Return         : None
+**************************************************************************/
+void HAL_SHA256_Hash(uint8_t *pDataIn,UINT32 DataLen,uint8_t *pDigest);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_SPI.h

@@ -0,0 +1,301 @@
+/*
+  ******************************************************************************
+  * @file    HAL_SPI.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of SPI HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_SPI_H__
+#define __HAL_SPI_H__
+
+#include  "ACM32Fxx_HAL.h" 
+
+/****************  Bit definition for SPI_CTL register  **************************/
+#define SPI_CTL_CS_TIME                       (BIT11|BIT12|BIT13|BIT14|BIT15|BIT16|BIT17|BIT18)
+#define SPI_CTL_CS_FILTER                      BIT10
+#define SPI_CTL_CS_RST                         BIT9
+#define SPI_CTL_SLAVE_EN                       BIT8
+#define SPI_CTL_IO_MODE                        BIT7
+#define SPI_CTL_X_MODE                        (BIT6|BIT5)
+#define SPI_CTL_LSB_FIRST                      BIT4
+#define SPI_CTL_CPOL                           BIT3
+#define SPI_CTL_CPHA                           BIT2
+#define SPI_CTL_SFILTER                        BIT1
+#define SPI_CTL_MST_MODE                       BIT0
+
+/****************  Bit definition for SPI_TX_CTL register  ***********************/
+#define SPI_TX_CTL_DMA_LEVEL                  (BIT4|BIT5|BIT6|BIT7)
+#define SPI_TX_CTL_DMA_LEVEL_3                 BIT7
+#define SPI_TX_CTL_DMA_LEVEL_2                 BIT6
+#define SPI_TX_CTL_DMA_LEVEL_1                 BIT5
+#define SPI_TX_CTL_DMA_LEVEL_0                 BIT4
+#define SPI_TX_CTL_DMA_REQ_EN                  BIT3
+#define SPI_TX_CTL_MODE                        BIT2
+#define SPI_TX_CTL_FIFO_RESET                  BIT1
+#define SPI_TX_CTL_EN                          BIT0
+
+/****************  Bit definition for SPI_RX_CTL register  ***********************/
+#define SPI_RX_CTL_DMA_LEVEL                  (BIT4|BIT5|BIT6|BIT7)
+#define SPI_RX_CTL_DMA_LEVEL_3                 BIT7
+#define SPI_RX_CTL_DMA_LEVEL_2                 BIT6
+#define SPI_RX_CTL_DMA_LEVEL_1                 BIT5
+#define SPI_RX_CTL_DMA_LEVEL_0                 BIT4
+#define SPI_RX_CTL_DMA_REQ_EN                  BIT3
+#define SPI_RX_CTL_FIFO_RESET                  BIT1
+#define SPI_RX_CTL_EN                          BIT0
+
+/****************  Bit definition for SPI_IE register  ***************************/
+#define SPI_IE_RX_BATCH_DONE_EN                BIT15
+#define SPI_IE_TX_BATCH_DONE_EN                BIT14
+#define SPI_IE_RX_FIFO_FULL_OV_EN              BIT13
+#define SPI_IE_RX_FIFO_EMPTY_OV_EN             BIT12
+#define SPI_IE_RX_NOT_EMPTY_EN                 BIT11
+#define SPI_IE_CS_POS_EN                       BIT10
+#define SPI_IE_RX_FIFO_HALF_FULL_EN            BIT9
+#define SPI_IE_RX_FIFO_HALF_EMPTY_EN           BIT8
+#define SPI_IE_TX_FIFO_HALF_FULL_EN            BIT7
+#define SPI_IE_TX_FIFO_HALF_EMPTY_EN           BIT6
+#define SPI_IE_RX_FIFO_FULL_EN                 BIT5
+#define SPI_IE_RX_FIFO_EMPTY_EN                BIT4
+#define SPI_IE_TX_FIFO_FULL_EN                 BIT3
+#define SPI_IE_TX_FIFO_EMPTY_EN                BIT2
+#define SPI_IE_BATCH_DONE_EN                   BIT1
+
+/****************  Bit definition for SPI_STATUS register  ***********************/
+#define SPI_STATUS_RX_BATCH_DONE               BIT15
+#define SPI_STATUS_TX_BATCH_DONE               BIT14
+#define SPI_STATUS_RX_FIFO_FULL_OV             BIT13
+#define SPI_STATUS_RX_FIFO_EMPTY_OV            BIT12
+#define SPI_STATUS_RX_NOT_EMPTY                BIT11
+#define SPI_STATUS_CS_POS                      BIT10
+#define SPI_STATUS_RX_FIFO_HALF_FULL           BIT9
+#define SPI_STATUS_RX_FIFO_HALF_EMPTY          BIT8
+#define SPI_STATUS_TX_FIFO_HALF_FULL           BIT7
+#define SPI_STATUS_TX_FIFO_HALF_EMPTY          BIT6
+#define SPI_STATUS_RX_FIFO_FULL                BIT5
+#define SPI_STATUS_RX_FIFO_EMPTY               BIT4
+#define SPI_STATUS_TX_FIFO_FULL                BIT3
+#define SPI_STATUS_TX_FIFO_EMPTY               BIT2
+#define SPI_STATUS_BATCH_DONE                  BIT1
+#define SPI_STATUS_TX_BUSY                     BIT0
+
+/****************  Bit definition for SPI_CS register  ***************************/
+#define SPI_CS_CSX                             BIT1
+#define SPI_CS_CS0                             BIT0
+
+/****************  Bit definition for SPI_OUT_EN register  ***********************/
+#define SPI_HOLD_EN                            BIT3
+#define SPI_HOLD_WP_EN                         BIT2
+#define SPI_HOLD_MISO_EN                       BIT1
+#define SPI_HOLD_MOSI_EN                       BIT0
+
+/****************  Bit definition for SPI_MEMO_ACC register  ***********************/
+#define SPI_ADDR_WIDTH                        (BIT14|BIT15|BIT16|BIT17|BIT18)
+#define SPI_PARA_NO2                          (BIT9|BIT10|BIT11|BIT12|BIT13)
+#define SPI_PARA_NO1                          (BIT5|BIT6|BIT7|BIT8)
+#define SPI_CON_RD_EN                          BIT3
+#define SPI_PARA_ORD2                          BIT2
+#define SPI_PARA_ORD1                          BIT1
+#define SPI_ACC_EN                             BIT0
+
+/** @defgroup SLAVE State machine
+ *  @{
+ */
+#define    SPI_RX_STATE_IDLE         (0U)
+#define    SPI_RX_STATE_RECEIVING    (1U)
+#define    SPI_TX_STATE_IDLE         (0U)
+#define    SPI_TX_STATE_SENDING      (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_MODE
+ *  @{
+ */
+#define    SPI_MODE_SLAVE     (0U)
+#define    SPI_MODE_MASTER    (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_WORK_MODE
+  * @{
+  */
+#define SPI_WORK_MODE_0    (0x00000000)
+#define SPI_WORK_MODE_1    (0x00000004)
+#define SPI_WORK_MODE_2    (0x00000008)
+#define SPI_WORK_MODE_3    (0x0000000C)
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_CLOCK_PHASE SPI Clock Phase
+  * @{
+  */
+#define SPI_PHASE_1EDGE    (0U)
+#define SPI_PHASE_2EDGE    (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup X_MODE SPI Clock Phase
+  * @{
+  */
+#define SPI_1X_MODE    (0x00000000)
+#define SPI_2X_MODE    (0x00000020)
+#define SPI_4X_MODE    (0x00000040)
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_MSB_LSB_FIRST
+  * @{
+  */
+#define SPI_FIRSTBIT_MSB    (0U)
+#define SPI_FIRSTBIT_LSB    (1U)
+/**
+  * @}
+  */
+
+
+/** @defgroup BAUDRATE_PRESCALER
+  * @{
+  */
+#define SPI_BAUDRATE_PRESCALER_4      (4U)
+#define SPI_BAUDRATE_PRESCALER_8      (8U)
+#define SPI_BAUDRATE_PRESCALER_16     (16U)
+#define SPI_BAUDRATE_PRESCALER_32     (32U)
+#define SPI_BAUDRATE_PRESCALER_64     (64U)
+#define SPI_BAUDRATE_PRESCALER_128    (128U)
+#define SPI_BAUDRATE_PRESCALER_254    (254U)
+/**
+  * @}
+  */
+
+
+/**
+  * @brief  SPI Configuration Structure definition
+  */
+typedef struct
+{
+    uint32_t  SPI_Mode;              /* This parameter can be a value of @ref SPI_MODE */
+    
+    uint32_t  SPI_Work_Mode;         /* This parameter can be a value of @ref SPI_WORK_MODE */
+    
+    uint32_t  X_Mode;                /* This parameter can be a value of @ref X_MODE */
+    
+    uint32_t  First_Bit;             /* This parameter can be a value of @ref SPI_MSB_LSB_FIRST */
+    
+    uint32_t  BaudRate_Prescaler;    /* This parameter can be a value of @ref BAUDRATE_PRESCALER */
+}SPI_InitTypeDef;
+
+/******************************** Check SPI Parameter *******************************/
+#define IS_SPI_ALL_MODE(SPI_Mode)          (((SPI_Mode) == SPI_MODE_SLAVE) || \
+                                            ((SPI_Mode) == SPI_MODE_MASTER))
+
+#define IS_SPI_WORK_MODE(WORK_MODE)        (((WORK_MODE) == SPI_WORK_MODE_0) || \
+                                            ((WORK_MODE) == SPI_WORK_MODE_1) || \
+                                            ((WORK_MODE) == SPI_WORK_MODE_2) || \
+                                            ((WORK_MODE) == SPI_WORK_MODE_3))
+
+#define IS_SPI_X_MODE(X_MODE)              (((X_MODE) == SPI_1X_MODE) || \
+                                            ((X_MODE) == SPI_2X_MODE) || \
+                                            ((X_MODE) == SPI_4X_MODE))
+
+#define IS_SPI_FIRST_BIT(FIRST_BIT)        (((FIRST_BIT) == SPI_FIRSTBIT_MSB) || \
+                                            ((FIRST_BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_BAUDRATE_PRESCALER(BAUDRATE)    (((BAUDRATE) == SPI_BAUDRATE_PRESCALER_4)   || \
+                                                ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_8)   || \
+                                                ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_16)  || \
+                                                ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_32)  || \
+                                                ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_64)  || \
+                                                ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_128) || \
+                                                ((BAUDRATE) == SPI_BAUDRATE_PRESCALER_254))
+
+/**
+  * @brief  SPI handle Structure definition
+  */
+typedef struct
+{
+    SPI_TypeDef         *Instance;         /* SPI registers base address */
+
+    SPI_InitTypeDef      Init;             /* SPI communication parameters */
+    
+    uint32_t               RxState;          /* SPI state machine */
+    uint32_t               TxState;          /* SPI state machine */
+    
+    uint8_t               *Rx_Buffer;        /* SPI Rx Buffer */
+    uint8_t               *Tx_Buffer;        /* SPI Tx Buffer */
+    
+    uint32_t               Rx_Size;          /* SPI Rx Size */
+    uint32_t               Tx_Size;          /* SPI Tx Size */
+    
+    uint32_t               Rx_Count;         /* SPI RX Count */
+    uint32_t               Tx_Count;         /* SPI TX Count */
+    
+    DMA_HandleTypeDef   *HDMA_Rx;          /* SPI Rx DMA handle parameters */
+    DMA_HandleTypeDef   *HDMA_Tx;          /* SPI Tx DMA handle parameters */
+
+}SPI_HandleTypeDef;
+
+/******************************** SPI Instances *******************************/
+#define IS_SPI_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == SPI1) || ((INSTANCE) == SPI2) || ((INSTANCE) == SPI3) || ((INSTANCE) == SPI4))
+
+/* Function : HAL_SPI_IRQHandler */
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+
+/* Function : HAL_SPI_MspInit */
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+
+/* Function : HAL_SPI_MspDeInit */
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+
+/* Function : HAL_SPI_Init */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+
+/* Function : HAL_SPI_DeInit */
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
+
+/* Function : HAL_SPI_Transmit */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_SPI_Transmit_DMA */
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_SPI_Receive */
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_SPI_Receive_DMA */
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_SPI_Wire_Config */
+HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode);
+
+/* Function : HAL_SPI_Transmit_IT */
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_SPI_Receive_IT */
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size);
+
+/* Function : HAL_SPI_TransmitReceive */
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout);
+
+/* Function : HAL_SPI_GetTxState */
+uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi);
+
+/* Function : HAL_SPI_GetRxState */
+uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi);
+
+#endif
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER.h

@@ -0,0 +1,520 @@
+/***********************************************************************
+ * Filename    : hal_timer.h
+ * Description : timer driver header file
+ * Author(s)   : Eric  
+ * version     : V1.0
+ * Modify date : 2016-03-24
+ ***********************************************************************/
+#ifndef __HAL_TIMER_H__
+#define __HAL_TIMER_H__  
+
+#include "ACM32Fxx_HAL.h"     
+
+#define IS_TIMER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1) || ((INSTANCE) == TIM2) || ((INSTANCE) == TIM3) \
+																			|| ((INSTANCE) == TIM4) || ((INSTANCE) == TIM6) || ((INSTANCE) == TIM7)\
+																			|| ((INSTANCE) == TIM14) || ((INSTANCE) == TIM15) || ((INSTANCE) == TIM16)\
+																			| ((INSTANCE) == TIM17) )
+
+/****************** TIM Instances : supporting the break function *************/
+#define IS_TIM_BREAK_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)    || \
+                                            ((INSTANCE) == TIM15)   || \
+                                            ((INSTANCE) == TIM16)   || \
+                                            ((INSTANCE) == TIM17))
+
+/************** TIM Instances : supporting Break source selection *************/
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                               ((INSTANCE) == TIM15)  || \
+                                               ((INSTANCE) == TIM16)  || \
+                                               ((INSTANCE) == TIM17))
+
+
+/************* TIM Instances : at least 1 capture/compare channel *************/
+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+																				 ((INSTANCE) == TIM3)   || \
+																				 ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM14)  || \
+                                         ((INSTANCE) == TIM15)  || \
+                                         ((INSTANCE) == TIM16)  || \
+                                         ((INSTANCE) == TIM17))
+
+/************ TIM Instances : at least 2 capture/compare channels *************/
+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+																				 ((INSTANCE) == TIM3)   || \
+																				 ((INSTANCE) == TIM4)   || \
+                                         ((INSTANCE) == TIM15))
+
+/************ TIM Instances : at least 3 capture/compare channels *************/
+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+																				 ((INSTANCE) == TIM2)   || \
+																				 ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4))
+
+/************ TIM Instances : at least 4 capture/compare channels *************/
+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \
+                                         ((INSTANCE) == TIM2)   || \
+																				 ((INSTANCE) == TIM3)   || \
+                                         ((INSTANCE) == TIM4))
+
+
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/
+#define IS_TIM_UDMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM1)   || \
+                                            ((INSTANCE) == TIM3)   || \
+                                            ((INSTANCE) == TIM6)   || \
+                                            ((INSTANCE) == TIM7)   || \
+                                            ((INSTANCE) == TIM15)  || \
+                                            ((INSTANCE) == TIM16)  || \
+                                            ((INSTANCE) == TIM17))
+
+/******************* TIM Instances : output(s) available **********************/
+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
+    ( (((INSTANCE) == TIM1) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4) ) )          \
+     ||                                        \
+     (((INSTANCE) == TIM2) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)) )           \
+		 ||                                        \
+     (((INSTANCE) == TIM3) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)) )           \
+			     ||                                        \
+     (((INSTANCE) == TIM4) &&                  \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2) ||          \
+      ((CHANNEL) == TIM_CHANNEL_3) ||          \
+      ((CHANNEL) == TIM_CHANNEL_4)) )           \
+     ||                                        \
+     (((INSTANCE) == TIM14) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)) )           \
+     ||                                        \
+     (((INSTANCE) == TIM15) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1) ||          \
+      ((CHANNEL) == TIM_CHANNEL_2)) )           \
+     ||                                        \
+     (((INSTANCE) == TIM16) &&                 \
+     (((CHANNEL) == TIM_CHANNEL_1)) )           \
+     ||                                        \
+     (((INSTANCE) == TIM17) &&                 \
+      ((CHANNEL) == TIM_CHANNEL_1) ) ) 
+
+/****************** TIM Instances : supporting complementary output(s) ********/
+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
+   ((( (INSTANCE) == TIM1) &&                    \
+     (((CHANNEL) == TIM_CHANNEL_1) ||           \
+      ((CHANNEL) == TIM_CHANNEL_2) ||           \
+      ((CHANNEL) == TIM_CHANNEL_3)) )            \
+    ||                                          \
+    (((INSTANCE) == TIM15) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM16) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1))              \
+    ||                                          \
+    (((INSTANCE) == TIM17) &&                   \
+     ((CHANNEL) == TIM_CHANNEL_1)  ) )
+
+/****************** TIM Instances : supporting clock division *****************/
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)    || \
+                                                    ((INSTANCE) == TIM2)    || \
+																										((INSTANCE) == TIM3)    || \
+																										((INSTANCE) == TIM4)    || \
+                                                    ((INSTANCE) == TIM14)   || \
+                                                    ((INSTANCE) == TIM15)   || \
+                                                    ((INSTANCE) == TIM16)   || \
+                                                    ((INSTANCE) == TIM17))
+
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) \
+																												((INSTANCE) == TIM3) \
+																												((INSTANCE) == TIM4) )
+
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
+                                                        ((INSTANCE) == TIM2) \
+																												((INSTANCE) == TIM3) \
+																												((INSTANCE) == TIM4) ) 
+
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)    ((INSTANCE) == TIM1)
+
+/****************** TIM Instances : supporting commutation event generation ***/
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                     ((INSTANCE) == TIM15)  || \
+                                                     ((INSTANCE) == TIM16)  || \
+                                                     ((INSTANCE) == TIM17))
+
+/****************** TIM Instances : supporting encoder interface **************/
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                      ((INSTANCE) == TIM2) \
+																											((INSTANCE) == TIM3) \
+																											((INSTANCE) == TIM4) ) 
+
+/****************** TIM Instances : supporting Hall sensor interface **********/
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \
+                                                      ((INSTANCE) == TIM2) \
+																											((INSTANCE) == TIM3) \
+																											((INSTANCE) == TIM4) )  
+
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)  || \
+                                            ((INSTANCE) == TIM2)  || \
+																						((INSTANCE) == TIM3)  || \
+																						((INSTANCE) == TIM4)  || \
+                                            ((INSTANCE) == TIM15))
+
+/****************** TIM Instances : supporting repetition counter *************/
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \
+                                                       ((INSTANCE) == TIM15) || \
+                                                       ((INSTANCE) == TIM16) || \
+                                                       ((INSTANCE) == TIM17))
+																											 
+#define HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))   
+#define HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) 
+
+#define HAL_TIM_ENABLE_IT_EX(__INSTANCE__, __INTERRUPT__)    ((__INSTANCE__)->DIER |= (__INTERRUPT__))   
+#define HAL_TIM_DISABLE_IT_EX(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->DIER &= ~(__INTERRUPT__)) 
+
+#define HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA_REQ__)    ((__HANDLE__)->Instance->DIER |= (__DMA_REQ__))   
+#define HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA_REQ__)   ((__HANDLE__)->Instance->DIER &= ~(__DMA_REQ__))  
+
+
+
+#define TIM_CR2_CCPC_Pos          (0U)
+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  
+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             
+#define TIM_CR2_CCUS_Pos          (2U)
+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                
+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             
+#define TIM_CR2_CCDS_Pos          (3U)
+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                
+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                         
+
+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                    
+#define TIM_COMMUTATION_SOFTWARE          0x00000000U  
+
+#define TIM_IT_UPDATE                      BIT0                                    
+#define TIM_IT_CC1                         BIT1                     
+#define TIM_IT_CC2                         BIT2                      
+#define TIM_IT_CC3                         BIT3                    
+#define TIM_IT_CC4                         BIT4                      
+#define TIM_IT_COM                         BIT5                   
+#define TIM_IT_TRIGGER                     BIT6                           
+#define TIM_IT_BREAK                       BIT7   
+
+#define TIM_DMA_UPDATE                      BIT8                                      
+#define TIM_DMA_CC1                         BIT9                    
+#define TIM_DMA_CC2                         BIT10                      
+#define TIM_DMA_CC3                         BIT11                   
+#define TIM_DMA_CC4                         BIT12                     
+#define TIM_DMA_COM                         BIT13                  
+#define TIM_DMA_TRIGGER                     BIT14                          
+#define TIM_DMA_BREAK                       BIT15     
+
+
+
+#define TIM_EVENTSOURCE_UPDATE              BIT0     /*!< Reinitialize the counter and generates an update of the registers */
+#define TIM_EVENTSOURCE_CC1                 BIT1     /*!< A capture/compare event is generated on channel 1 */
+#define TIM_EVENTSOURCE_CC2                 BIT2     /*!< A capture/compare event is generated on channel 2 */
+#define TIM_EVENTSOURCE_CC3                 BIT3     /*!< A capture/compare event is generated on channel 3 */
+#define TIM_EVENTSOURCE_CC4                 BIT4     /*!< A capture/compare event is generated on channel 4 */
+#define TIM_EVENTSOURCE_COM                 BIT5     /*!< A commutation event is generated */
+#define TIM_EVENTSOURCE_TRIGGER             BIT6     /*!< A trigger event is generated */
+#define TIM_EVENTSOURCE_BREAK               BIT7     /*!< A break event is generated */
+
+#define TIM_ARR_PRELOAD_DISABLE   0  
+#define TIM_ARR_PRELOAD_ENABLE    1    
+
+#define TIM_COUNTERMODE_DIR_INDEX          4 
+#define TIM_COUNTERMODE_UP                 (0 << TIM_COUNTERMODE_DIR_INDEX)                          
+#define TIM_COUNTERMODE_DOWN               (1 << TIM_COUNTERMODE_DIR_INDEX)  
+
+#define TIM_COUNTERMODE_CMS_INDEX          5     
+#define TIM_COUNTERMODE_CENTERALIGNED1     (1 << TIM_COUNTERMODE_CMS_INDEX)                      
+#define TIM_COUNTERMODE_CENTERALIGNED2     (2 << TIM_COUNTERMODE_CMS_INDEX)                        
+#define TIM_COUNTERMODE_CENTERALIGNED3     (3 << TIM_COUNTERMODE_CMS_INDEX)                                       
+
+#define TIM_CLKCK_DIV_INDEX                8   
+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */
+#define TIM_CLOCKDIVISION_DIV2             (1U << TIM_CLKCK_DIV_INDEX)          /*!< Clock division: tDTS=2*tCK_INT */
+#define TIM_CLOCKDIVISION_DIV4             (2U << TIM_CLKCK_DIV_INDEX)          /*!< Clock division: tDTS=4*tCK_INT */     
+
+#define TIM_TRGO_RESET       (0 << 4) 
+#define TIM_TRGO_ENABLE      (1 << 4)    
+#define TIM_TRGO_UPDATE      (2 << 4) 
+#define TIM_TRGO_CMP_PULSE   (3 << 4)  
+#define TIM_TRGO_OC1REF      (4 << 4) 
+#define TIM_TRGO_OC2REF      (5 << 4)    
+#define TIM_TRGO_OC3REF      (6 << 4)  
+#define TIM_TRGO_OC4REF      (7 << 4)     
+
+#define TIM_MASTERSLAVEMODE_DISABLE  0       
+#define TIM_MASTERSLAVEMODE_ENABLE   BIT7  
+
+
+#define TIM_SLAVE_MODE_INDEX     0 
+#define TIM_SLAVE_MODE_DIS       (0U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_ENC1      (1U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_ENC2      (2U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_ENC3      (3U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_RST       (4U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_GATE      (5U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_TRIG      (6U << TIM_SLAVE_MODE_INDEX) 
+#define TIM_SLAVE_MODE_EXT1      (7U << TIM_SLAVE_MODE_INDEX)   
+   
+#define TIM_TRIGGER_SOURCE_INDEX        4   
+#define TIM_TRIGGER_SOURCE_ITR0         (0U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_ITR1         (1U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_ITR2         (2U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_ITR3         (3U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_TI1F_ED      (4U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_TI1FP1       (5U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_TI2FP2       (6U << TIM_TRIGGER_SOURCE_INDEX) 
+#define TIM_TRIGGER_SOURCE_ETRF         (7U << TIM_TRIGGER_SOURCE_INDEX)        
+
+#define TIMER_SR_UIF    BIT0 
+#define TIMER_SR_CC1IF  BIT1
+#define TIMER_SR_CC2IF  BIT2
+#define TIMER_SR_CC3IF  BIT3
+#define TIMER_SR_CC4IF  BIT4
+#define TIMER_SR_COMIF  BIT5
+#define TIMER_SR_TIF    BIT6
+#define TIMER_SR_BIF    BIT7
+#define TIMER_SR_CC1OF  BIT9
+#define TIMER_SR_CC2OF  BIT10
+#define TIMER_SR_CC3OF  BIT11
+#define TIMER_SR_CC4OF  BIT12     
+
+#define TIMER_INT_EN_UPD       BIT0    
+#define TIMER_INT_EN_CC1       BIT1
+#define TIMER_INT_EN_CC2       BIT2
+#define TIMER_INT_EN_CC3       BIT3
+#define TIMER_INT_EN_CC4       BIT4
+#define TIMER_INT_EN_COM       BIT5
+#define TIMER_INT_EN_TRI       BIT6
+#define TIMER_INT_EN_BRK       BIT7   
+
+#define TIMER_DMA_EN_UPD       BIT8    
+#define TIMER_DMA_EN_CC1       BIT9
+#define TIMER_DMA_EN_CC2       BIT10
+#define TIMER_DMA_EN_CC3       BIT11
+#define TIMER_DMA_EN_CC4       BIT12
+#define TIMER_DMA_EN_COM       BIT13
+#define TIMER_DMA_EN_TRI       BIT14   
+
+#define TIM_CHANNEL_1                      0                       
+#define TIM_CHANNEL_2                      1                       
+#define TIM_CHANNEL_3                      2                         
+#define TIM_CHANNEL_4                      3      
+
+#define OUTPUT_FAST_MODE_DISABLE  0  
+#define OUTPUT_FAST_MODE_ENABLE   1    
+
+#define OUTPUT_POL_ACTIVE_HIGH  0  
+#define OUTPUT_POL_ACTIVE_LOW   1      
+
+#define OUTPUT_DISABLE_IDLE_STATE  0 
+#define OUTPUT_ENABLE_IDLE_STATE   1 
+
+#define OUTPUT_IDLE_STATE_0     0  
+#define OUTPUT_IDLE_STATE_1     1  
+
+#define OUTPUT_MODE_FROZEN          0
+#define OUTPUT_MODE_MATCH_HIGH      1
+#define OUTPUT_MODE_MATCH_LOW       2 
+#define OUTPUT_MODE_MATCH_TOGGLE    3 
+#define OUTPUT_MODE_FORCE_LOW       4
+#define OUTPUT_MODE_FORCE_HIGH      5   
+#define OUTPUT_MODE_PWM1            6  
+#define OUTPUT_MODE_PWM2            7   
+            
+#define TIM_CLOCKSOURCE_INT       0                                                              
+#define TIM_CLOCKSOURCE_ITR0      1                        
+#define TIM_CLOCKSOURCE_ITR1      2                   
+#define TIM_CLOCKSOURCE_ITR2      3                        
+#define TIM_CLOCKSOURCE_ITR3      4                         
+#define TIM_CLOCKSOURCE_TI1FP1    5                    
+#define TIM_CLOCKSOURCE_TI2FP2    6                    
+#define TIM_CLOCKSOURCE_ETR       7     
+
+#define TIM_ETR_POLAIRTY_HIGH     0    
+#define TIM_ETR_POLAIRTY_LOW      (BIT15)       
+#define TIM_ETR_FILTER_LVL(x)     (x << 8)   //BIT8-BIT11  
+
+#define TIM_ETR_PRESCALER_1    0  
+#define TIM_ETR_PRESCALER_2    (BIT12)
+#define TIM_ETR_PRESCALER_4    (BIT13) 
+#define TIM_ETR_PRESCALER_8    (BIT12|BIT13)  
+
+#define ETR_SELECT_GPIO        0  
+#define ETR_SELECT_COMP1_OUT   BIT14   
+#define ETR_SELECT_COMP2_OUT   BIT15  
+#define ETR_SELECT_ADC_AWD     BIT14|BIT15    
+#define ETR_SELECT_MASK        (BIT14|BIT15)    
+
+#define TIM_TI1_FILTER_LVL(x)     (x << 4)          
+#define TIM_TI2_FILTER_LVL(x)     (x << 12)     
+#define TIM_TI3_FILTER_LVL(x)     (x << 4) 
+#define TIM_TI4_FILTER_LVL(x)     (x << 12)    
+
+#define TIM_IC1_PRESCALER_1    0  
+#define TIM_IC1_PRESCALER_2    (BIT2)
+#define TIM_IC1_PRESCALER_4    (BIT3) 
+#define TIM_IC1_PRESCALER_8    (BIT2|BIT3)  
+
+#define TIM_IC2_PRESCALER_1    0  
+#define TIM_IC2_PRESCALER_2    (BIT10)
+#define TIM_IC2_PRESCALER_4    (BIT11) 
+#define TIM_IC2_PRESCALER_8    (BIT10|BIT11)    
+
+#define TIM_IC3_PRESCALER_1    0  
+#define TIM_IC3_PRESCALER_2    (BIT2)
+#define TIM_IC3_PRESCALER_4    (BIT3) 
+#define TIM_IC3_PRESCALER_8    (BIT2|BIT3)  
+
+#define TIM_IC4_PRESCALER_1    0  
+#define TIM_IC4_PRESCALER_2    (BIT10)
+#define TIM_IC4_PRESCALER_4    (BIT11) 
+#define TIM_IC4_PRESCALER_8    (BIT10|BIT11)    
+
+typedef struct
+{
+  uint32_t ClockSource;     //TIMER clock sources                              
+  uint32_t ClockPolarity;   //TIMER clock polarity                               
+  uint32_t ClockPrescaler;  //TIMER clock prescaler                                
+  uint32_t ClockFilter;     //TIMER clock filter          
+} TIM_ClockConfigTypeDef;
+
+typedef struct
+{
+  uint32_t OCMode;        // Specifies the TIM mode. 
+  uint32_t Pulse;         // Specifies the pulse value to be loaded into the Capture Compare Register.
+  uint32_t OCPolarity;    // Specifies the output polarity. 
+  uint32_t OCNPolarity;   // Specifies the complementary output polarity.   
+  uint32_t OCFastMode;    // Specifies the Fast mode state.
+  uint32_t OCIdleState;   // Specifies the TIM Output Compare pin state during Idle state.   
+  uint32_t OCNIdleState;  // Specifies the TIM Output Compare complementary pin state during Idle state. 
+} TIM_OC_InitTypeDef; 
+      
+
+#define TIM_SLAVE_CAPTURE_ACTIVE_RISING          0    
+#define TIM_SLAVE_CAPTURE_ACTIVE_FALLING         1    
+#define TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING  2               
+
+#define TIM_ICSELECTION_DIRECTTI    0  
+#define TIM_ICSELECTION_INDIRECTTI  1        
+
+#define TIM_CC1_SLAVE_CAPTURE_POL_RISING    (0)    
+#define TIM_CC1_SLAVE_CAPTURE_POL_FALLING   (BIT1)    
+#define TIM_CC1_SLAVE_CAPTURE_POL_BOTH      (BIT1 | BIT3)    
+
+#define TIM_CC2_SLAVE_CAPTURE_POL_RISING    (0)    
+#define TIM_CC2_SLAVE_CAPTURE_POL_FALLING   (BIT5)    
+#define TIM_CC2_SLAVE_CAPTURE_POL_BOTH      (BIT5 | BIT7)   
+
+#define TIM_CC3_SLAVE_CAPTURE_POL_RISING    (0)  
+#define TIM_CC3_SLAVE_CAPTURE_POL_FALLING   (BIT9)   
+#define TIM_CC3_SLAVE_CAPTURE_POL_BOTH      (BIT9 | BIT11)   
+
+#define TIM_CC4_SLAVE_CAPTURE_POL_RISING    (0)  
+#define TIM_CC4_SLAVE_CAPTURE_POL_FALLING   (BIT13)   
+#define TIM_CC4_SLAVE_CAPTURE_POL_BOTH      (BIT13 | BIT15)     
+
+typedef struct
+{
+  uint32_t  SlaveMode;         // Slave mode selection
+  uint32_t  InputTrigger;      // Input Trigger source
+  uint32_t  TriggerPolarity;   // Input Trigger polarity 
+  uint32_t  TriggerPrescaler;  // input prescaler, only for ETR input 
+  uint32_t  TriggerFilter;     // Input trigger filter  
+} TIM_SlaveConfigTypeDef;
+
+typedef struct
+{
+  uint32_t ICPolarity;   // Specifies the active edge of the input signal.
+  uint32_t ICSelection;  // Specifies the input  
+  uint32_t ICPrescaler;  // Specifies the Input Capture Prescaler. 
+  uint32_t TIFilter;     // Specifies the input capture filter.
+} TIM_IC_InitTypeDef;         
+
+typedef struct   
+{
+  uint32_t  MasterOutputTrigger;   // Trigger output (TRGO) selection
+  uint32_t  MasterSlaveMode;       // Master/slave mode selection  
+} TIM_MasterConfigTypeDef;     
+
+#define TIM_DMA_UPDATE_INDEX    0  
+#define TIM_DMA_CC1_INDEX       1   
+#define TIM_DMA_CC2_INDEX       2  
+#define TIM_DMA_CC3_INDEX       3  
+#define TIM_DMA_CC4_INDEX       4  
+#define TIM_DMA_COM_INDEX       5  
+#define TIM_DMA_TRIG_INDEX      6          
+
+#define MAX_DMA_REQ_ONE_TIMER   7  
+
+typedef struct
+{
+  uint32_t Prescaler;         // Specifies the prescaler value used to divide the TIM clock.   
+  uint32_t Period;            // Specifies the ARR value  	
+  uint32_t ARRPreLoadEn;      // Specifies the preload enable or disable 
+  uint32_t RepetitionCounter; // Specifies the repetition counter value     
+  uint32_t CounterMode;       // Specifies the counter mode.Up/Down/Center    
+  uint32_t ClockDivision;     // Specifies the clock division, used for deadtime or sampling      
+} TIM_Base_InitTypeDef; 
+
+typedef struct
+{
+    TIM_TypeDef *Instance;         
+    TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */  
+    DMA_HandleTypeDef        *hdma[MAX_DMA_REQ_ONE_TIMER];   
+}TIM_HandleTypeDef;   
+
+/* HAL_TIMER_MSP_Init */  
+extern uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim);  
+/* HAL_TIMER_Slave_Mode_Config */  
+extern uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);   
+/* HAL_TIMER_Base_Init */ 
+extern uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim);   
+/* HAL_TIMER_Output_Config */ 
+extern uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel);     
+/* HAL_TIMER_Base_Start */ 
+extern void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx);    
+/* HAL_TIM_PWM_Output_Start */ 
+extern uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel);   
+/* HAL_TIM_PWM_Output_Stop */    
+extern HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel);     
+/* HAL_TIMER_OC_Start */ 
+extern uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel);  
+/* HAL_TIMER_OCxN_Start */    
+extern uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel);      
+/* HAL_TIMER_OC_Stop */ 
+extern HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel);      
+/* HAL_TIM_Capture_Start */ 
+extern uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel);       
+/* HAL_TIM_Capture_Stop */   
+extern uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel);    
+/* HAL_TIMER_Capture_Config */
+extern uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel);    
+/* HAL_TIMER_Master_Mode_Config */   
+extern uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig);  
+/* HAL_TIMER_SelectClockSource */  
+extern HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);  
+/* HAL_TIMER_ReadCapturedValue */   
+extern uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);   
+/* HAL_TIMER_Clear_Capture_Flag */     
+extern void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel);   
+#endif  
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_TIMER_EX.h

@@ -0,0 +1,128 @@
+/***********************************************************************
+ * Filename    : hal_timer_ex.h
+ * Description : timer driver header file
+ * Author(s)   : xwl  
+ * version     : V1.0
+ * Modify date : 2021-03-24
+ ***********************************************************************/
+#ifndef __HAL_TIMER_EX_H__
+#define __HAL_TIMER_EX_H__  
+
+#include "ACM32Fxx_HAL.h"     
+
+
+#define TIM_BDTR_DTG_Pos          (0U)
+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */
+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000001 */
+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000002 */
+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000004 */
+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000008 */
+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000010 */
+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000020 */
+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                 /*!< 0x00000040 */
+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)    
+
+#define TIM_BDTR_LOCK_Pos         (8U)
+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */
+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */
+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000100 */
+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)    
+
+#define TIM_BDTR_OSSI_Pos         (10U)
+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */
+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */
+#define TIM_BDTR_OSSR_Pos         (11U)
+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */
+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */
+#define TIM_BDTR_BKE_Pos          (12U)
+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */
+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break 1 */
+#define TIM_BDTR_BKP_Pos          (13U)
+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */
+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break 1 */
+#define TIM_BDTR_AOE_Pos          (14U)
+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */
+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */
+#define TIM_BDTR_MOE_Pos          (15U)
+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */
+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */
+
+#define TIM_BDTR_BKF_Pos          (16U)
+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */
+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk       
+
+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */
+#ifdef HAL_COMP_MODULE_ENABLED  
+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */
+#endif /* COMP1 && COMP2 */
+
+#define TIM_BREAKINPUT_BRK     0x00000001U     
+
+#define TIM1_AF1_BKINE_Pos        (0U)
+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */
+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BRK BKIN input enable */
+#define TIM1_AF1_BKCMP1E_Pos      (1U)
+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */
+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BRK COMP1 enable */
+#define TIM1_AF1_BKCMP2E_Pos      (2U)
+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */
+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BRK COMP2 enable */
+#define TIM1_AF1_BKINP_Pos        (9U)
+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */
+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRK BKIN input polarity */
+#define TIM1_AF1_BKCMP1P_Pos      (10U)
+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */
+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BRK COMP1 input polarity */
+#define TIM1_AF1_BKCMP2P_Pos      (11U)
+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */
+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk  
+
+
+typedef struct
+{
+  uint32_t OffStateRunMode;           // TIM off state in run mode
+  uint32_t OffStateIDLEMode;          // TIM off state in IDLE mode
+  uint32_t LockLevel;                 // TIM Lock level
+  uint32_t DeadTime;                  // TIM dead Time
+  uint32_t BreakState;                // TIM Break State
+  uint32_t BreakPolarity;             // TIM Break input polarity
+  uint32_t BreakFilter;               // Specifies the break input filter.
+  uint32_t AutomaticOutput;           // TIM Automatic Output Enable state   
+} TIM_BreakDeadTimeConfigTypeDef;     
+
+typedef struct
+{
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */
+}
+TIMEx_BreakInputConfigTypeDef;
+
+/*******************  Bit definition for TIM_TISEL register  *********************/
+#define TIM_TISEL_TI1SEL_Pos      (0U)
+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */
+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM1 TI1 SEL)*/
+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000001 */
+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000002 */
+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000004 */
+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x00000008 */
+
+#define TIM_TISEL_TI2SEL_Pos      (8U)
+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */
+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM1 TI2 SEL)*/
+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000100 */
+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000200 */
+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000400 */
+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000800 */    
+
+
+#endif  
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_UART.h

@@ -0,0 +1,305 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Uart.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_UART_H__
+#define __HAL_UART_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/******************************************************************************/
+/*                    Peripheral Registers Bits Definition                    */
+/******************************************************************************/
+
+/****************  Bit definition for UART FR register  ***********************/
+#define UART_FR_TXFE                    BIT7
+#define UART_FR_RXFF                    BIT6
+#define UART_FR_TXFF                    BIT5
+#define UART_FR_RXFE                    BIT4
+#define UART_FR_BUSY                    BIT3
+#define UART_FR_CTS                     BIT0
+/***************  Bit definition for UART LCRH register  **********************/
+#define UART_LCRH_SPS                   BIT7
+#define UART_LCRH_WLEN                 (BIT6|BIT5)
+#define UART_LCRH_FEN                   BIT4
+#define UART_LCRH_STP2                  BIT3
+#define UART_LCRH_EPS                   BIT2
+#define UART_LCRH_PEN                   BIT1
+#define UART_LCRH_BRK                   BIT0
+/****************  Bit definition for UART CR register  ***********************/
+#define UART_CR_CTSEN                   BIT15
+#define UART_CR_RTSEN                   BIT14
+#define UART_CR_RTS                     BIT11
+#define UART_CR_RXE                     BIT9
+#define UART_CR_TXE                     BIT8
+#define UART_CR_UARTEN                  BIT0
+/***************  Bit definition for UART IFLS register  **********************/
+#define UART_IFLS_RXIFLSEL             (BIT3|BIT4|BIT5)
+#define UART_IFLS_TXIFLSEL             (BIT0|BIT1|BIT2)
+/****************  Bit definition for UART IE register  ***********************/
+#define UART_IE_OEI                     BIT10
+#define UART_IE_BEI                     BIT9
+#define UART_IE_PEI                     BIT8
+#define UART_IE_FEI                     BIT7
+#define UART_IE_RTI                     BIT6
+#define UART_IE_TXI                     BIT5
+#define UART_IE_RXI                     BIT4
+/****************  Bit definition for UART RIS register  ***********************/
+#define UART_RIS_OEI                    BIT10
+#define UART_RIS_BEI                    BIT9
+#define UART_RIS_PEI                    BIT8
+#define UART_RIS_FEI                    BIT7
+#define UART_RIS_RTI                    BIT6
+#define UART_RIS_TXI                    BIT5
+#define UART_RIS_RXI                    BIT4
+/****************  Bit definition for UART ICR register  ***********************/
+#define UART_ICR_OEI                    BIT10
+#define UART_ICR_BEI                    BIT9
+#define UART_ICR_PEI                    BIT8
+#define UART_ICR_FEI                    BIT7
+#define UART_ICR_RTI                    BIT6
+#define UART_ICR_TXI                    BIT5
+#define UART_ICR_RXI                    BIT4
+/*****************  Bit definition for UART DMACR register  ***********************/
+#define UART_DMACR_DMAONERR             BIT2
+#define UART_DMACR_TXDMAE               BIT1
+#define UART_DMACR_RXDMAE               BIT0
+/*****************  Bit definition for UART CR2 register  ***********************/
+#define UART_CR2_TXOE_SEL               BIT1
+#define UART_CR2_RX_SEL                 BIT0
+
+
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_5B                  (0x00000000U)    /*!< 5-bit Word Length */
+#define UART_WORDLENGTH_6B                  (0x00000020U)    /*!< 6-bit Word Length */
+#define UART_WORDLENGTH_7B                  (0x00000040U)    /*!< 7-bit Word Length */
+#define UART_WORDLENGTH_8B                  (0x00000060U)    /*!< 8-bit Word Length */
+/**
+  * @}
+  */
+
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    (0x00000000U)    /*!< No parity   */
+#define UART_PARITY_EVEN                    (0x00000006U)    /*!< Even parity */
+#define UART_PARITY_ODD                     (0x00000002U)    /*!< Odd parity  */
+#define UART_PARITY_0                       (0x00000086U)    /*!< 0 parity  */
+#define UART_PARITY_1                       (0x00000082U)    /*!< 1 parity  */
+/**
+  * @}
+  */
+
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_1                     (0x00000000U)    /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_2                     (0x00008000U)    /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  (0x00000000U)        /*!< No hardware control       */
+#define UART_HWCONTROL_CTS                   (0x00008000U)        /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS                   (0x00004000U)        /*!< Request To Send           */
+#define UART_HWCONTROL_CTS_RTS               (UART_HWCONTROL_CTS | UART_HWCONTROL_RTS)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        (0x00000200)        /*!< RX mode        */
+#define UART_MODE_TX                        (0x00000100)        /*!< TX mode        */
+#define UART_MODE_TX_RX                     (0x00000300)        /*!< RX and TX mode */
+#define UART_MODE_TX_RX_DEBUG               (0x10000300)        /*!< RX¡¢TX mode and Debug use this uart */
+#define UART_MODE_HALF_DUPLEX               (0x20000300)        /*!< Single half duplex */
+/**
+  * @}
+  */
+
+
+/** @defgroup FIFO interrupt Config
+  * @{
+  */
+#define UART_TX_FIFO_1_16             (0x00000005)        /*!< Transfer 1 Data  */
+#define UART_TX_FIFO_1_8              (0x00000000)        /*!< Transfer 2 Data  */
+#define UART_TX_FIFO_1_4              (0x00000001)        /*!< Transfer 4 Data  */
+#define UART_TX_FIFO_1_2              (0x00000002)        /*!< Transfer 8 Data  */
+#define UART_TX_FIFO_3_4              (0x00000003)        /*!< Transfer 12 Data */
+#define UART_TX_FIFO_7_8              (0x00000004)        /*!< Transfer 14 Data */
+
+#define UART_RX_FIFO_1_16             (0x00000028)        /*!< Receive  1 Data  */
+#define UART_RX_FIFO_1_8              (0x00000000)        /*!< Receive  2 Data  */
+#define UART_RX_FIFO_1_4              (0x00000008)        /*!< Receive  4 Data  */
+#define UART_RX_FIFO_1_2              (0x00000010)        /*!< Receive  8 Data  */
+#define UART_RX_FIFO_3_4              (0x00000018)        /*!< Receive  12 Data */
+#define UART_RX_FIFO_7_8              (0x00000020)        /*!< Receive  14 Data */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Code UART Error Code
+  * @{
+  */
+#define HAL_UART_ERROR_NONE              0x00000000U   /*!< No error            */
+#define HAL_UART_ERROR_PE                0x00000001U   /*!< Parity error        */
+#define HAL_UART_ERROR_NE                0x00000002U   /*!< Noise error         */
+#define HAL_UART_ERROR_FE                0x00000004U   /*!< Frame error         */
+#define HAL_UART_ERROR_ORE               0x00000008U   /*!< Overrun error       */
+#define HAL_UART_ERROR_DMA               0x00000010U   /*!< DMA transfer error  */
+/**
+  * @}
+  */
+
+
+/*
+ * @brief UART Init Structure definition
+ */
+typedef struct
+{
+    uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate. */
+
+    uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
+                                             This parameter can be a value of @ref UARTEx_Word_Length. */
+
+    uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                             This parameter can be a value of @ref UART_Stop_Bits. */
+
+    uint32_t Parity;                    /*!< Specifies the parity mode. 
+                                             This parameter can be a value of @ref UART_Parity. */
+
+    uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                             This parameter can be a value of @ref UART_Mode. */
+
+    uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                             This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+}UART_InitTypeDef;
+
+/*
+ * @brief  UART handle Structure definition
+ */
+typedef struct
+{
+    UART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+    UART_InitTypeDef         Init;                    /*!< UART communication parameters      */
+
+    uint32_t                 lu32_TxSize;             /*!< UART Transmit parameters in interrupt  */
+    __IO uint32_t            lu32_TxCount;
+    uint8_t                 *lu8_TxData;
+    
+    uint32_t                 lu32_RxSize;             /*!< UART Receive parameters in interrupt  */
+    __IO uint32_t            lu32_RxCount; 
+    uint32_t                 lu32_fifo_level_minus1;   
+    uint8_t                 *lu8_RxData;  
+    
+    
+    __IO uint8_t             lu8_TxBusy;  
+    __IO uint8_t             lu8_RxBusy;  
+    
+    DMA_HandleTypeDef       *HDMA_Tx;                 /*!< UART Tx DMA handle parameters */
+    DMA_HandleTypeDef       *HDMA_Rx;                 /*!< UART Rx DMA handle parameters */ 
+
+	__IO uint32_t           ErrorCode;                /*!<UART Error Code */
+
+}UART_HandleTypeDef;
+
+
+/** @defgroup  GPIO Private Macros
+  * @{
+  */
+#define IS_UART_ALL_INSTANCE(INSTANCE)    (((INSTANCE) == UART1) || \
+                                           ((INSTANCE) == UART2) || \
+                                           ((INSTANCE) == UART3) || \
+                                           ((INSTANCE) == UART4))
+
+#define IS_UART_WORDLENGTH(__WORDLENGTH__)    (((__WORDLENGTH__) == UART_WORDLENGTH_5B) || \
+                                               ((__WORDLENGTH__) == UART_WORDLENGTH_6B) || \
+                                               ((__WORDLENGTH__) == UART_WORDLENGTH_7B) || \
+                                               ((__WORDLENGTH__) == UART_WORDLENGTH_8B))
+
+#define IS_UART_STOPBITS(__STOPBITS__)    (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                           ((__STOPBITS__) == UART_STOPBITS_2))
+
+#define IS_UART_PARITY(__PARITY__)        (((__PARITY__) == UART_PARITY_NONE) || \
+                                           ((__PARITY__) == UART_PARITY_EVEN) || \
+                                           ((__PARITY__) == UART_PARITY_ODD))
+
+#define IS_UART_MODE(__MODE__)            (((__MODE__) == UART_MODE_RX)          || \
+                                           ((__MODE__) == UART_MODE_TX)          || \
+                                           ((__MODE__) == UART_MODE_TX_RX)       || \
+                                           ((__MODE__) == UART_MODE_TX_RX_DEBUG) || \
+                                           ((__MODE__) == UART_MODE_HALF_DUPLEX))
+                                           
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)    (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+                                                       ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+                                                       ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+                                                       ((__CONTROL__) == UART_HWCONTROL_CTS_RTS))
+/**
+  * @}
+  */
+
+/* HAL_UART_IRQHandler */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+
+/* HAL_UART_MspInit */
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+
+/* HAL_UART_Init */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+
+/* HAL_UART_DeInit */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+
+/* HAL_UART_GetState */
+HAL_StatusTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
+
+/* HAL_UART_GetError*/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
+
+/* HAL_UART_Abort*/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+
+/* HAL_UART_DMAPause */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+
+/* HAL_UART_DMAResume */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+
+
+/* HAL_UART_Transmit */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout);
+
+/* HAL_UART_Receive */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout);
+
+/* HAL_UART_Transmit_IT */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size);
+
+/* HAL_UART_Receive_IT */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size);
+
+/* HAL_UART_Transmit_DMA */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size);
+
+/* HAL_UART_Receive_DMA */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_UART_EX.h

@@ -0,0 +1,36 @@
+/*
+  ******************************************************************************
+  * @file    HAL_UART_EX.h
+  * @version V1.0.0
+  * @date    2020
+  * @brief   Header file of UART EX HAL module.
+  ******************************************************************************
+*/
+#ifndef __HAL_UART_EX_H__
+#define __HAL_UART_EX_H__
+
+#include "ACM32Fxx_HAL.h"
+
+/****************  Bit definition for UART IE register  ***********************/
+#define UART_EX_IE_BCNTI                    BIT12
+#define UART_EX_IE_LBDI                     BIT11
+
+/****************  Bit definition for UART RIS register  ***********************/
+#define UART_EX_RIS_BCNTI                   BIT12
+#define UART_EX_RIS_LBDI                    BIT11
+
+/****************  Bit definition for UART BCNT register  ***********************/
+#define UART_EX_BCNT_START                   BIT8
+#define UART_EX_BCNT_VALUE_POS              (0U)
+#define UART_EX_BCNT_VALUE_MASK             (0xFFU)
+
+/****************  Definition of LIN BUS VERSION  ***********************/
+#define UART_LIN_V1D3         0    //Lin bus version 1.3
+#define UART_LIN_V2DX         1    //Lin bus version 2.0/2.1/2.2
+
+void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size);
+void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size);
+uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout);
+uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Inc/HAL_WDT.h

@@ -0,0 +1,118 @@
+
+/***********************************************************************
+ * Filename    : HAL_WDT.h
+ * Description : HAL WDT driver header file
+ * Author(s)   : CWT
+ * version     : V1.0
+ * Modify date : 2020-04-17  
+ ***********************************************************************/
+
+#ifndef __HAL_WDT_H__
+#define __HAL_WDT_H__
+
+#include "ACM32Fxx_HAL.h"
+
+
+/****************  Bit definition for WDT CTRL register  ********************/
+#define WDT_CTRL_EN                         BIT7
+#define WDT_CTRL_MODE                       BIT6
+#define WDT_CTRL_INTEN                      BIT4
+#define WDT_CTRL_DIVISOR                    (BIT0|BIT1|BIT2)
+
+/****************  Bit definition for WDTRIS register  ********************/
+#define WDT_WDTRIS                          BIT0 
+
+typedef enum
+{
+    WDT_MODE_RST = 0x00U, 
+    WDT_MODE_INT = 0x01U,  
+} WDT_MODE;  
+
+typedef enum
+{
+    WDT_DIVISOR_NONE = 0x00U,  
+    WDT_DIVISOR_2 = 0x01U,
+    WDT_DIVISOR_4 = 0x02U,
+    WDT_DIVISOR_8 = 0x03U,
+    WDT_DIVISOR_16 = 0x04U,
+    WDT_DIVISOR_32 = 0x05U,
+    WDT_DIVISOR_64 = 0x06U,
+    WDT_DIVISOR_128 = 0x07U,
+} WDT_DIVISOR; 
+
+typedef struct
+{          
+    WDT_DIVISOR WDTDivisor;             
+    WDT_MODE WDTMode; 
+    uint32_t WDTLoad;
+    uint32_t WDTINTCLRTIME;
+} WDT_InitTypeDef;
+
+typedef struct
+{
+    WDT_TypeDef            *Instance;                /*!< WDT registers base address        */
+    WDT_InitTypeDef         Init;                    /*!< WDT communication parameters      */
+}WDT_HandleTypeDef;
+
+#define WDT_ENABLE                      (0x01 << 7)
+#define WDT_DISABLE                     (~WDT_ENABLE) 
+#define WDT_INT_ENABLE                  (0x01 << 4)
+#define WDT_INT_DISABLE                 (~WDT_INT_ENABLE) 
+/************************************************************************
+ * function   : HAL_WDT_Feed
+ * Description: WDT feed. 
+ * input : 
+ *         none 
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_IRQHandler
+ * Description: WDT interrupt service routine. 
+ * input : 
+ *         none 
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : HAL_WDT_Init
+ * Description: WDT initiation. 
+ * input : 
+ *         pinit initiation parameters 
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Init(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Start
+ * Description: WDT start
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Start(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Stop
+ * Description: WDT stop
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Int_Enable
+ * Description: WDT int enable
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt);
+/************************************************************************
+ * function   : WDT_Int_Disable
+ * Description: WDT int disable
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+ void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt);
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_ADC.c

@@ -0,0 +1,913 @@
+/*
+  ******************************************************************************
+  * @file    HAL_ADC.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   ADC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC) peripheral:
+  *           @ Initialization  functions
+  *           @ IO operation functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+extern ADC_HandleTypeDef ADC_Handle;
+
+/************************************************************************
+ * function   : HAL_ADC_IRQHandler
+ * Description: This function handles SPI interrupt request.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ ************************************************************************/
+__weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+    __IO uint32_t Status;
+    
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return;
+    if(!IS_ADC_ALL_CONCONVMODE(hadc->Init.ConConvMode)) return;  
+  
+    Status = hadc->Instance->SR;
+    /************ Check End of Conversion flag for injected ************/
+    if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_JEOCIE))
+    {
+        if((Status & ADC_SR_JEOC) == ADC_SR_JEOC)
+        {
+            if(__HAL_ADC_CHECK_TRIG_INJECTED(hadc, ADC_SOFTWARE_START)     || 
+                ((__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START))  &&
+                (hadc->Init.ConConvMode == 0)))
+            {
+                /* Disable ADC end of conversion interrupt on group injected */
+                __HAL_ADC_DISABLE_IT(hadc, ADC_IE_JEOCIE);
+
+            }
+
+            /* Conversion complete callback */ 
+            if (NULL != hadc->InjectedConvCpltCallback)
+                hadc->InjectedConvCpltCallback(hadc);
+      
+            /* Clear injected group conversion flag */
+            __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC);
+        }
+    }
+
+    /************ Check Conversion flag for regular group ************/
+    if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_EOCIE))
+    {
+        if((Status & ADC_SR_EOC) == ADC_SR_EOC)
+        {      
+            /* Conversion complete callback */
+            if (NULL != hadc->ConvCpltCallback)
+                hadc->ConvCpltCallback(hadc);
+      
+            /* Clear conversion flag */
+            __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOC);
+        }
+    }
+
+    /************ Check Analog watchdog flags ************/
+    if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_AWDIE))
+    {
+        if((Status & ADC_SR_AWD) == ADC_SR_AWD)
+        {
+            /* Level out of window callback */ 
+            if (NULL != hadc->LevelOutOfWindowCallback)
+                hadc->LevelOutOfWindowCallback(hadc);
+
+            /* Clear the ADC analog watchdog flag */
+            __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_AWD);
+        }
+    }  
+    
+    /************ Check End of Conversion flag for regular group ************/
+    if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IE_EOGIE))
+    {
+        if((Status & ADC_SR_EOG) == ADC_SR_EOG)
+        {      
+            if((__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START)) && 
+             (hadc->Init.ConConvMode == 0))
+            {
+                /* Disable ADC end of conversion interrupt on group regular */
+                __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOGIE);
+            }
+      
+            /* Conversion complete callback */
+            if (NULL != hadc->GroupCpltCallback)
+                hadc->GroupCpltCallback(hadc);
+
+            /* Clear regular group conversion flag */
+            __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOG);
+        }
+    }
+}
+
+/************************************************************************
+ * function   : HAL_ADC_MspInit
+ * Description: 
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : none
+ ************************************************************************/
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+    uint32_t i;
+    uint32_t ADC_Pin_Map[][3] =
+    {
+        { ADC_CHANNEL_0_EN, GPIOC, GPIO_PIN_5 }, 
+        { ADC_CHANNEL_1_EN, GPIOA, GPIO_PIN_7 },
+        { ADC_CHANNEL_2_EN, GPIOA, GPIO_PIN_5 },
+        { ADC_CHANNEL_3_EN, GPIOA, GPIO_PIN_3 },
+        { ADC_CHANNEL_4_EN, GPIOC, GPIO_PIN_3 },
+        { ADC_CHANNEL_5_EN, GPIOC, GPIO_PIN_1 },
+        { ADC_CHANNEL_6_EN, GPIOA, GPIO_PIN_0 },
+        { ADC_CHANNEL_8_EN, GPIOC, GPIO_PIN_4 },
+        { ADC_CHANNEL_9_EN, GPIOA, GPIO_PIN_6 },
+        { ADC_CHANNEL_10_EN, GPIOA, GPIO_PIN_4 },
+        { ADC_CHANNEL_11_EN, GPIOA, GPIO_PIN_2 },
+        { ADC_CHANNEL_12_EN, GPIOC, GPIO_PIN_2 },
+        { ADC_CHANNEL_13_EN, GPIOC, GPIO_PIN_0 },
+        { ADC_CHANNEL_VBAT_EN, GPIOA, GPIO_PIN_1 },
+        { ADC_CHANNEL_EXT2_EN, GPIOB, GPIO_PIN_1 },
+        { ADC_CHANNEL_EXT3_EN, GPIOB, GPIO_PIN_2 },
+        { 0xffffffff, 0 }, //结束标志
+    };    
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_Handle; 
+
+    //Set gpio to analog.
+    for(i = 0; ADC_Pin_Map[i][0] != 0xffffffff; i++)
+    {
+        if(hadc->Init.ChannelEn & ADC_Pin_Map[i][0])
+        {
+            GPIO_Handle.Pin            = ADC_Pin_Map[i][2];
+            GPIO_Handle.Mode           = GPIO_MODE_ANALOG;
+            GPIO_Handle.Pull           = GPIO_NOPULL;
+            HAL_GPIO_Init(ADC_Pin_Map[i][1], &GPIO_Handle);             
+        }
+    }
+    
+    /* Enable ADC Clock */
+    System_Module_Enable(EN_ADC);
+    
+    /* Clear Pending Interrupt */
+    NVIC_ClearPendingIRQ(ADC_IRQn);
+    
+    /* Enable External Interrupt */
+    NVIC_EnableIRQ(ADC_IRQn);
+}
+
+/************************************************************************
+ * function   : HAL_ADC_MspDeInit
+ * Description: 
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : none
+ ************************************************************************/
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{    
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */    
+    if(hadc->Init.DMAMode)
+    {
+        HAL_DMA_DeInit(hadc->DMA_Handle);
+
+        hadc->DMA_Handle = NULL;
+    }
+    
+    /* Disable ADC Clock */
+    System_Module_Disable(EN_ADC);
+    
+    /* Clear Pending Interrupt */
+    NVIC_ClearPendingIRQ(ADC_IRQn);
+    
+    /* Disable External Interrupt */
+    NVIC_DisableIRQ(ADC_IRQn);
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Init
+ * Description: Init the ADC module
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
+{
+    /* Check the ADC handle allocation */
+    if (hadc == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    if(!IS_ADC_ALL_CONCONVMODE(hadc->Init.ConConvMode)) return HAL_ERROR;
+    if(!IS_ADC_ALL_JCHANNELMODE(hadc->Init.JChannelMode)) return HAL_ERROR;
+    if(!IS_ADC_ALL_DIFFMODE(hadc->Init.DiffMode)) return HAL_ERROR;
+    if(!IS_ADC_ALL_DMAMODE(hadc->Init.DMAMode)) return HAL_ERROR;
+    if(!IS_ADC_ALL_OVERMODE(hadc->Init.OverMode)) return HAL_ERROR;
+    if(!IS_ADC_ALL_OVERSAMPMODE(hadc->Init.OverSampMode)) return HAL_ERROR;    
+    if(!IS_ADC_ALL_OVSR(hadc->Init.Oversampling.Ratio)) return HAL_ERROR;    
+    if(!IS_ADC_ALL_OVSS(hadc->Init.Oversampling.RightBitShift)) return HAL_ERROR;    
+    if(!IS_ADC_ALL_ANALOGWDGEN(hadc->Init.AnalogWDGEn)) return HAL_ERROR;
+    if(!IS_ADC_ALL_CLOCKDIV(hadc->Init.ClockDiv)) return HAL_ERROR;   
+    if(!IS_ADC_ALL_CHANNELEN(hadc->Init.ChannelEn)) return HAL_ERROR;
+    if(!IS_ADC_ALL_TRIG(hadc->Init.ExTrigMode.ExTrigSel)) return HAL_ERROR;
+    if(!IS_ADC_ALL_CHANNELEN(hadc->Init.ExTrigMode.JExTrigSel)) return HAL_ERROR;
+    
+    /* Init the low level hardware : GPIO, CLOCK, NVIC, DMA */
+    HAL_ADC_MspInit(hadc);
+    
+   //Reset AFE.
+    SET_BIT(hadc->Instance->CR2,ADC_CR2_AFE_RSTN);
+   //Set Clock DIV.
+    MODIFY_REG(hadc->Instance->CR2,ADC_CR2_DIV_MASK,hadc->Init.ClockDiv<<ADC_CR2_DIV_POS);
+    
+    //Set continued convert mode
+    if(hadc->Init.ConConvMode)
+        SET_BIT(hadc->Instance->CR1,ADC_CR1_CONT);
+    else
+        CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_CONT);
+        
+    //Overflow
+    if(hadc->Init.OverMode == ADC_OVERMODE_ENABLE)
+        SET_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD);
+    else
+        CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_OVRMOD);
+    
+    //Over Sample Set
+    if(hadc->Init.OverSampMode)
+    {
+        if(hadc->Init.JChannelMode)
+        {
+            SET_BIT(hadc->Instance->CR2,ADC_CR2_JOVSE); // Inject channel over sample en.
+            if(hadc->Init.Oversampling.TriggeredMode)
+                SET_BIT(hadc->Instance->CR2,ADC_CR2_JTOVS); // N times sample every trig.
+            else
+                CLEAR_BIT(hadc->Instance->CR2,ADC_CR2_JTOVS); // 1 time sample every trig.
+        }
+        
+        MODIFY_REG(hadc->Instance->CR2,ADC_CR2_OVSR_MASK,hadc->Init.Oversampling.Ratio<<ADC_CR2_OVSR_POS);   //over sample rate
+        MODIFY_REG(hadc->Instance->CR2,ADC_CR2_OVSS_MASK,hadc->Init.Oversampling.RightBitShift<<ADC_CR2_OVSS_POS); //over sample right shift.
+        SET_BIT(hadc->Instance->CR2,ADC_CR2_OVSE); // Regular channel over sample en.
+    }
+    
+    //ExTrigSel set
+    MODIFY_REG(hadc->Instance->CR1,ADC_CR1_EXTSEL_MASK,hadc->Init.ExTrigMode.ExTrigSel<<ADC_CR1_EXTSEL_POS);
+    if(hadc->Init.JChannelMode)
+    {
+        /* Enable the inject channel */
+        SET_BIT(hadc->Instance->CR1, ADC_CR1_JEN);
+        //JExTrigSel set
+        MODIFY_REG(hadc->Instance->CR1,ADC_CR1_JEXTSEL_MASK,hadc->Init.ExTrigMode.JExTrigSel<<ADC_CR1_JEXTSEL_POS);        
+    }
+
+    //Clear the sequence length.
+    CLEAR_BIT(hadc->Instance->SQR1,ADC_SQR1_L); //Clear the sequence length.
+    
+    return  HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_DeInit
+ * Description: DeInit the ADC module
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
+{
+    /* Check the ADC handle allocation */
+    if (hadc == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    HAL_ADC_MspDeInit(hadc);
+    
+    hadc->ChannelNum = 0;
+    hadc->ConvCpltCallback = NULL;
+    hadc->InjectedConvCpltCallback = NULL;
+    hadc->LevelOutOfWindowCallback = NULL;
+    memset(&hadc->Init, 0, sizeof(hadc->Init));
+    
+    return  HAL_OK;
+}
+    
+/************************************************************************
+ * function   : HAL_ADC_ConfigChannel
+ * Description: Config the regular channel
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ *              sConfig : pointer to a ADC_ChannelConfTypeDef structure that contains
+ *                     the configuration information for ADC channel
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
+{    
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    if(!IS_ADC_ALL_CHANNEL(sConfig->Channel)) return HAL_ERROR;
+    if(!IS_ADC_ALL_SMPCLOCK(sConfig->Smp)) return HAL_ERROR;
+    if(!IS_ADC_ALL_SEQUENCE(sConfig->Sq)) return HAL_ERROR;
+
+    /* Differential mode set*/
+    if(hadc->Init.DiffMode)
+    {
+        if(sConfig->Channel < 8)
+        {
+            SET_BIT(hadc->Instance->DIFF,1<<sConfig->Channel);
+            SET_BIT(hadc->Instance->SIGN,1<<sConfig->Channel);     //If define differential mode ,set as sign resault
+        }
+        else
+            return HAL_ERROR;
+    }
+    else if(sConfig->Channel < 8)
+    {
+        CLEAR_BIT(hadc->Instance->DIFF,1<<sConfig->Channel);
+        CLEAR_BIT(hadc->Instance->SIGN,1<<sConfig->Channel);   //If define differential mode ,set as unsign resault
+    }
+
+    if((sConfig->Channel >= 8) && (hadc->Instance->DIFF & (1<<(sConfig->Channel-8)))) return HAL_ERROR;
+
+    if(sConfig->RjMode == 0)
+    {
+        if((sConfig->Sq >= 1)&&(sConfig->Sq <= 5)) 
+            MODIFY_REG(hadc->Instance->SQR1,(ADC_CH_MASK << (5*sConfig->Sq )),(sConfig->Channel << (5*sConfig->Sq )));
+        else if((sConfig->Sq >= 6)&&(sConfig->Sq <= 11))
+            MODIFY_REG(hadc->Instance->SQR2,(ADC_CH_MASK << (5*(sConfig->Sq-6))),(sConfig->Channel << (5*(sConfig->Sq-6))));
+        else if((sConfig->Sq >= 12)&&(sConfig->Sq <= 16))
+            MODIFY_REG(hadc->Instance->SQR3,(ADC_CH_MASK << (5*(sConfig->Sq-12))),(sConfig->Channel << (5*(sConfig->Sq-12))));
+        else
+            return HAL_ERROR;
+    }
+    else
+    { 
+        /* Inject channel */
+        MODIFY_REG(hadc->Instance->JSQR,ADC_CH_MASK,sConfig->Channel);
+    }
+    
+    MODIFY_REG(hadc->Instance->SQR1,ADC_SQR1_L,(ADC_Handle.ChannelNum-1));
+
+    /* Set the SMPR to every register*/
+    if(sConfig->Channel <= ADC_CHANNEL_7) 
+        MODIFY_REG(hadc->Instance->SMPR1,(ADC_SMPR_CH_MASK << (4*sConfig->Channel )),(sConfig->Smp << (4*sConfig->Channel )));
+    else if((sConfig->Channel >= ADC_CHANNEL_8)&&(sConfig->Channel <= ADC_CHANNEL_15))
+        MODIFY_REG(hadc->Instance->SMPR2,(ADC_SMPR_CH_MASK << (4*(sConfig->Channel-8))),(sConfig->Smp << (4*(sConfig->Channel-8))));
+    else if((sConfig->Channel >= ADC_CHANNEL_TEMP)&&(sConfig->Channel <= ADC_CHANNEL_EXT3))
+        MODIFY_REG(hadc->Instance->SMPR3,(ADC_SMPR_CH_MASK << (4*(sConfig->Channel-16))),(sConfig->Smp << (4*(sConfig->Channel-16))));
+    else
+        return HAL_ERROR;
+    
+    if(hadc->Init.ChannelEn & ADC_CHANNEL_TEMP_EN)
+    {
+        SET_BIT(hadc->Instance->TSREF,ADC_TSREF_EN_TS);//Enable the temperature sensor
+        System_Delay(1000);
+    }    
+    
+    if(hadc->Init.ChannelEn & (ADC_CHANNEL_VBGR_EN | ADC_CHANNEL_EXT2_EN | ADC_CHANNEL_EXT3_EN))
+    {
+        SET_BIT(hadc->Instance->CR2,ADC_CR2_EN_BUF);//Enable the buffer
+        System_Delay(1000);
+    }
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_AnalogWDGConfig
+ * Description: Config the analog watchdog
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ *              AnalogWDGConfig : pointer to a ADC_AnalogWDGConfTypeDef structure that contains
+ *                     the configuration information for ADC analog watchdog
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
+{                                 
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    if(!IS_ADC_ALL_CHANNEL(AnalogWDGConfig->Channel)) return HAL_ERROR;
+    
+    if (hadc->Init.AnalogWDGEn)
+    {
+        switch(AnalogWDGConfig->WatchdogMode)
+        {
+                /* AWDSGL:0; AWDEN:1; JAWDEN:0 */
+            case ADC_ANALOGWATCHDOG_RCH_ALL:
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);
+                break;
+                /* AWDSGL:0; AWDEN:0; JAWDEN:1 */
+            case ADC_ANALOGWATCHDOG_JCH_ALL:
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL);
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);
+                break;
+                /* AWDSGL:0; AWDEN:1; JAWDEN:1 */
+            case ADC_ANALOGWATCHDOG_RCH_AND_JCH_ALL:
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);
+                break;
+                /* AWDSGL:1; AWDEN:1; JAWDEN:0 */
+            case ADC_ANALOGWATCHDOG_RCH_SINGLE:
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);
+                MODIFY_REG(hadc->Instance->CR1,ADC_CH_MASK,AnalogWDGConfig->Channel);  //The regular watchdog channel set
+                break;
+                /* AWDSGL:1; AWDEN:0; JAWDEN:1 */
+            case ADC_ANALOGWATCHDOG_JCH_SINGLE:
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL);
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);   
+                MODIFY_REG(hadc->Instance->CR1,(ADC_CH_MASK<<27),AnalogWDGConfig->Channel<<27);  //The inject watchdog channel set
+                break;
+                /* AWDSGL:1; AWDEN:1; JAWDEN:1 */
+            case ADC_ANALOGWATCHDOG_RCH_OR_JCH_SINGLE:
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDSGL);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                SET_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);
+                MODIFY_REG(hadc->Instance->CR1,ADC_CH_MASK,AnalogWDGConfig->Channel);  //The regular watchdog channel set
+                MODIFY_REG(hadc->Instance->CR1,(ADC_CH_MASK<<27),AnalogWDGConfig->Channel<<27);  //The inject watchdog channel set
+                break;
+
+                /* AWDSGL:x; AWDEN:0; JAWDEN:0 */
+            default: /* ADC_ANALOGWATCHDOG_NONE */
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_AWDEN);
+                CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_JAWDEN);
+                break;
+        }
+      
+          /* Configure ADC analog watchdog interrupt */
+        if(AnalogWDGConfig->ITMode)
+            __HAL_ADC_ENABLE_IT(hadc,ADC_IE_AWDIE);
+        else
+            __HAL_ADC_DISABLE_IT(hadc,ADC_IE_AWDIE);
+    }
+    
+    if(hadc->Init.DiffMode)
+    {
+        hadc->Instance->HTR = AnalogWDGConfig->HighThreshold<<16;
+        hadc->Instance->LTR = AnalogWDGConfig->LowThreshold<<16;
+    }
+    else
+    {
+        hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
+        hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
+    }
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Start
+ * Description: Enable and start the ADC convertion
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
+{
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    
+    /* check the total number of the enabled channels */
+    if((READ_BIT(hadc->Instance->SQR1,ADC_SQR1_L)+1) != hadc->ChannelNum) return HAL_ERROR;
+    
+    /* Enable the ADC */
+    __HAL_ADC_ENABLE(hadc);
+
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY);
+
+    /* Wait ADC ready */
+    while(!(hadc->Instance->SR & ADC_SR_ADRDY));
+    
+    if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START))
+    {
+        /* Start covertion */
+        SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART);
+    }
+    
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Stop
+ * Description: Stop ADC conversion of regular group (and injected channels in 
+ *              case of auto_injection mode), disable ADC peripheral.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
+{
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+  
+    if(hadc->Init.ConConvMode)
+    {
+        /* Set stop flag */
+        SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP);        
+        /* Waitting stop flag be cleared */    
+        while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP));
+    }
+    
+    /* Disable the ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY);
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Start_IT
+ * Description: Enable ADC, start conversion of regular group with interruption.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
+{  
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+      
+    /* Enable the ADC */
+    __HAL_ADC_ENABLE(hadc);
+
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY);      
+      
+    /* Disable all interruptions before enabling the desired ones */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE);  
+    
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE);
+    
+      
+    /* Enable ADC overrun interrupt */
+    /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is
+     ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal
+     behavior and no CPU time is lost for a non-processed interruption */
+    if (hadc->Init.OverMode == ADC_OVERMODE_DISABLE)
+    {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IE_OVERFIE);
+    }
+      
+    if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START))
+    {
+        /* Start covertion */
+        SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART);
+    }
+  
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Stop_IT
+ * Description: Stop ADC conversion of regular group (and injected group in 
+ *              case of auto_injection mode), disable interrution of 
+ *              end-of-conversion, disable ADC peripheral.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
+{
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+  
+    if(hadc->Init.ConConvMode)
+    {
+        /* Set stop flag */
+        SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP);        
+        /* Waitting stop flag be cleared */    
+        while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP));
+    }
+ 
+    /* Disable the ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+
+    /* Disable all interruptions before enabling the desired ones */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE);  
+
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY);
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Start_DMA
+ * Description: Enable ADC, start conversion of regular group and transfer result through DMA.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ *            : pData : Destination Buffer address.
+ *            : Length : Number of data to be transferred from ADC peripheral to memory.
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
+{
+    HAL_StatusTypeDef tmp_hal_status;
+  
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+      
+    /* Specific case for first call occurrence of this function (DMA transfer */
+    /* not activated and ADC disabled), DMA transfer must be activated        */
+    /* with ADC disabled.                                                     */
+    if (READ_BIT(hadc->Instance->CR1,ADC_CR1_DMA) == 0UL)
+    {
+      if(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_EN))
+      {
+        /* Disable ADC */
+        __HAL_ADC_DISABLE(hadc);
+      }
+      
+      /* Enable ADC DMA mode */
+      SET_BIT(hadc->Instance->CR1,ADC_CR1_DMA);
+    }
+    
+    /* Enable the ADC peripheral */
+    __HAL_ADC_ENABLE(hadc);
+    
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY);      
+      
+    /* Disable all interruptions before enabling the desired ones */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE);  
+           
+    /* Start the DMA channel */
+    tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+    /* Enable conversion of regular group.                                  */
+    /* If software start has been selected, conversion starts immediately.  */
+    /* If external trigger has been selected, conversion will start at next */
+    /* trigger event.                                                       */
+    
+    /* Start ADC group regular conversion */
+    if(__HAL_ADC_CHECK_TRIG_REGULAR(hadc, ADC_SOFTWARE_START))
+    {
+        /* Start covertion */
+        SET_BIT(hadc->Instance->CR1,ADC_CR1_SWSTART);
+    }
+  
+    /* Return function status */
+    return tmp_hal_status;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Stop_DMA
+ * Description: Stop ADC conversion of regular group (and injected group in 
+ *              case of auto_injection mode), disable ADC DMA transfer, disable 
+ *              ADC peripheral.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
+{  
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    
+    if(hadc->Init.ConConvMode)
+    {
+        /* Set stop flag */
+        SET_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP);        
+        /* Waitting stop flag be cleared */    
+        while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP));
+    }
+    
+    /* Waitting stop flag be cleared */    
+    while(READ_BIT(hadc->Instance->CR2, ADC_CR2_ADC_STP));
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    HAL_DMA_Abort(hadc->DMA_Handle);
+    
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IE_OVERFIE);
+    
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep  */
+    /* in memory a potential failing status.                                  */
+
+    /* Disable the ADC peripheral */
+    __HAL_ADC_DISABLE(hadc);
+
+    /* Disable all interruptions before enabling the desired ones */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IE_EOCIE | ADC_IE_EOGIE | ADC_IE_OVERFIE | ADC_IE_JEOCIE);  
+
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc,ADC_SR_AWD | ADC_SR_OVERF | ADC_SR_EOG | ADC_SR_JEOC | ADC_SR_EOC | ADC_SR_ADRDY);
+
+    /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+    CLEAR_BIT(hadc->Instance->CR1,ADC_CR1_DMA);
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_GetValue
+ * Description: ADC retrieve conversion value intended to be used with polling or interruption
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : uint32_t the ADC covert result.
+ ************************************************************************/
+uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
+{
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    
+    return (hadc->Instance->DR);
+}
+
+/************************************************************************
+ * function   : HAL_ADC_PollForEvent
+ * Description: Poll for ADC event.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ *            : EventType: the ADC event type. can be ：ADC_SR_AWD,ADC_SR_OVERF,ADC_SR_EOG,ADC_SR_JEOC,ADC_SR_EOC
+ *            : Timeout : Polling timeout.
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+    __IO uint32_t uiTimeout;
+    
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    if(!IS_ADC_EVENT_TYPE(EventType)) return HAL_ERROR;
+
+    uiTimeout = Timeout;
+    /* Check selected event flag */
+    while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+    {
+        /* Check if timeout is disabled (set to infinite wait) */
+        if(uiTimeout)
+        {
+            uiTimeout--;
+            if(uiTimeout == 0)
+                return HAL_TIMEOUT;
+        }
+    }
+
+    if(EventType == ADC_SR_OVERF)
+    {
+        __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_OVERF);
+        if (hadc->Init.OverMode == ADC_OVERMODE_ENABLE)
+        {
+            /* Clear ADC Overrun flag only if Overrun is set to ADC_OVERMODE_ENABLE(Over written) */
+            return HAL_ERROR;
+        }
+    }
+    else
+    {
+        __HAL_ADC_CLEAR_FLAG(hadc, EventType);
+    }
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_InjectedStart_IT
+ * Description: Enable ADC, start conversion of injected channel with interruption.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_InjectedStart_IT(ADC_HandleTypeDef* hadc)
+{  
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+
+    /* Clear the SR register */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC);      
+            
+    __HAL_ADC_ENABLE_IT(hadc, ADC_IE_JEOCIE);    
+      
+    /* Enable ADC overrun interrupt */
+    /* If hadc->Init.OverMode is set to ADC_OVERMODE_DISABLE, only then is
+     ADC_IE_OVERFIE enabled; otherwise data overwrite is considered as normal
+     behavior and no CPU time is lost for a non-processed interruption */
+    if (hadc->Init.OverMode == ADC_OVERMODE_DISABLE)
+    {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IE_OVERFIE);
+    }
+      
+    if(__HAL_ADC_CHECK_TRIG_INJECTED(hadc, ADC_SOFTWARE_START))
+    {
+        /* Start covertion */
+        SET_BIT(hadc->Instance->CR1,ADC_CR1_JSWSTART);
+    }
+  
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_ADC_InjectedStop_IT
+ * Description: Stop ADC conversion of injected channel, disable interrution of 
+ *              end-of-conversion, disable ADC peripheral.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_InjectedStop_IT(ADC_HandleTypeDef* hadc)
+{
+    /* Return function status */
+    return (HAL_ADC_Stop_IT(hadc));
+}
+
+/************************************************************************
+ * function   : HAL_ADC_InjectedGetValue
+ * Description: ADC retrieve injected channel conversion value intended to be used with polling or interruption
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ * return     : uint32_t the ADC covert result.
+ ************************************************************************/
+uint32_t HAL_ADC_InjectedGetValue(ADC_HandleTypeDef *hadc)
+{
+    /* Check the parameters */
+    if(!IS_ADC_ALL_INSTANCE(hadc->Instance)) return HAL_ERROR;
+    
+    return (hadc->Instance->JDR);
+}
+
+/************************************************************************
+ * function   : HAL_ADC_Polling
+ * Description: Polling to get the results of the ADC converter.
+ * input      : hadc : pointer to a ADC_HandleTypeDef structure that contains
+ *                     the configuration information for ADC module
+ *            : pData : Destination Buffer address.
+ *            : Length : Number of data to be transferred from ADC peripheral to memory.
+ *            : Timeout : Polling timeout.
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_ADC_Polling(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length, uint32_t Timeout)
+{
+    uint32_t tmp_hal_status;
+    __IO uint32_t uiTimeout;    
+
+    if(HAL_ADC_Start(hadc) != HAL_OK)  return HAL_ERROR; 
+    if(!pData)  return HAL_ERROR;
+    
+    hadc->AdcResults = pData;
+    uiTimeout = Timeout;
+    
+    while(Length)
+    {
+        tmp_hal_status = hadc->Instance->SR;
+        if(tmp_hal_status & ADC_SR_EOC)
+        {
+            *hadc->AdcResults = hadc->Instance->DR | HAL_ADC_EOC_FLAG;
+             __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOC);
+       
+            hadc->AdcResults++;
+            Length--;
+        }
+        if(tmp_hal_status & ADC_SR_JEOC)
+        {
+            *hadc->AdcResults = hadc->Instance->JDR | HAL_ADC_JEOC_FLAG;
+             __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_JEOC);
+            hadc->AdcResults++;
+            Length--;
+        }
+        if(tmp_hal_status & ADC_SR_OVERF)
+        {
+            __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_OVERF);
+        }        
+        if(tmp_hal_status & ADC_SR_EOG)
+        {
+            __HAL_ADC_CLEAR_FLAG(hadc, ADC_SR_EOG);
+            break;
+        }
+        
+        if(uiTimeout)
+        {
+            uiTimeout--;
+            if(uiTimeout == 0)
+                return HAL_TIMEOUT;
+        }
+    }
+    
+    HAL_ADC_Stop(hadc); 
+    
+    return HAL_OK;
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CAN.c

@@ -0,0 +1,732 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Can.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   CAN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (CAN).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_CAN_OperatingModeRequest
+* Description : Select the CAN Operation mode.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Input       : CAN_OperatingMode:CAN Operating Mode. This parameter can be one  of @ref CAN_OperatingMode enumeration.
+* Output      : HAL status
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_OperatingModeRequest(CAN_HandleTypeDef *hcan, uint8_t CAN_OperatingMode)
+{
+    uint8_t status = HAL_ERROR;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR;
+    if(!IS_CAN_OPERATING_MODE(CAN_OperatingMode)) return HAL_ERROR;
+    if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+    {
+        hcan->Instance->MOD |= CAN_OperatingMode_Initialization;  // enter Initialization 
+        if ((hcan->Instance->MOD & CAN_MOD_RM) != CAN_OperatingMode_Initialization)
+        {
+            status = HAL_ERROR;
+        }
+        else
+        {
+            status = HAL_OK;
+        }
+    }
+    else if(CAN_OperatingMode == CAN_OperatingMode_Normal)
+    {
+        hcan->Instance->MOD &=~ CAN_OperatingMode_Initialization;   //1-->0 enter Normal 
+        if ((hcan->Instance->MOD & CAN_MOD_RM) != CAN_OperatingMode_Normal)
+        {
+            status = HAL_ERROR;
+        }
+        else
+        {
+            status = HAL_OK;
+        }
+    }
+    else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+    {
+        hcan->Instance->MOD |= CAN_OperatingMode_Sleep;  // enter Normal 
+        if ((hcan->Instance->MOD & CAN_MOD_SM) != CAN_OperatingMode_Sleep)
+        {
+            status = HAL_ERROR;
+        }
+        else
+        {
+            status = HAL_OK;
+        }
+    }
+    else if(CAN_OperatingMode == CAN_OperatingMode_Listen)
+    {
+        hcan->Instance->MOD |= CAN_OperatingMode_Listen;  // enter Normal 
+        if((hcan->Instance->MOD & CAN_MOD_LOM) != CAN_OperatingMode_Listen)
+        {
+            status = HAL_ERROR;
+        }
+        else
+        {
+            status = HAL_OK;
+        }
+    }
+    else
+    {
+        status = HAL_ERROR;
+    }
+    return  (uint8_t) status;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_MspInit
+* Description : Initialize the CAN MSP.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
+{
+    /* NOTE : This function should not be modified, when the callback is needed,
+                the HAL_UART_MspInit can be implemented in the user file
+    */
+    /* For Example */
+    GPIO_InitTypeDef   GPIO_InitStruct;
+    if(hcan->Instance==CAN1)
+    {
+        /* Enable CAN clock */
+        System_Module_Enable(EN_CAN1);
+        GPIO_InitTypeDef GPIO_InitStructure;   	
+        /* Initialization GPIO */
+        /* PA11:Rx */  /* PA12:Tx */
+        GPIO_InitStructure.Pin = GPIO_PIN_11|GPIO_PIN_12;	
+        GPIO_InitStructure.Alternate=GPIO_FUNCTION_5;
+        GPIO_InitStructure.Pull=GPIO_PULLUP;
+        GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
+        HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
+        
+    }
+    else if(hcan->Instance==CAN2)
+    {
+        /* Enable CAN clock */
+        System_Module_Enable(EN_CAN2);
+        GPIO_InitTypeDef GPIO_InitStructure;   	
+        /* Initialization GPIO */
+        /* PB5:Rx */  /* PB6:Tx */
+        GPIO_InitStructure.Pin = GPIO_PIN_5|GPIO_PIN_6;	
+        GPIO_InitStructure.Alternate=GPIO_FUNCTION_5;
+        GPIO_InitStructure.Pull=GPIO_PULLUP;
+        GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
+        HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
+        
+        /* Enable the CAN Receive interrupt */
+        hcan->Instance->IER |= CAN_IER_RIE;
+        NVIC_ClearPendingIRQ(CAN2_IRQn);
+        NVIC_SetPriority(CAN2_IRQn, 5);
+        NVIC_EnableIRQ(CAN2_IRQn);
+    }
+    
+}
+/*********************************************************************************
+* Function    : HAL_CAN_MspDeInit
+* Description :	CAN MSP De-Initialization 
+*               This function frees the hardware resources used in this example:
+*              - Disable the Peripheral's clock
+*              - Revert GPIO configuration to their default state
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
+{
+    if(hcan->Instance==CAN1)
+    {
+        /* Reset CAN clock */
+        System_Module_Disable(EN_CAN1);
+        GPIO_InitTypeDef GPIO_InitStructure;   	
+        /* Initialization GPIO */
+        /* PA11:Rx */  /* PA12:Tx */
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12);
+        }
+        else if(hcan->Instance==CAN2)
+        {
+        /* Reset CAN clock */
+        System_Module_Disable(EN_CAN2);
+        GPIO_InitTypeDef GPIO_InitStructure;   	
+        /* Initialization GPIO */
+        /* PB5:Rx */  /* PB6:Tx */
+        HAL_GPIO_DeInit(GPIOB, GPIO_PIN_5);
+        HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6);
+    }
+}
+/*********************************************************************************
+* Function    : HAL_CAN_Init
+* Description :	Initializes the CAN peripheral according to the specified  parameters in the CAN_HandleTypeDef..
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : HAL status
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
+{
+    uint8_t InitStatus = HAL_ERROR;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR;
+    if(!IS_CAN_MODE(hcan->Init.CAN_Mode)) return HAL_ERROR;
+    if(!IS_CAN_SJW(hcan->Init.CAN_SJW)) return HAL_ERROR;
+    if(!IS_CAN_TSEG1(hcan->Init.CAN_TSEG1)) return HAL_ERROR;
+    if(!IS_CAN_TSEG2(hcan->Init.CAN_TSEG2)) return HAL_ERROR;
+    if(!IS_CAN_BRP(hcan->Init.CAN_BRP)) return HAL_ERROR;
+    if(!IS_CAN_SAM(hcan->Init.CAN_SAM)) return HAL_ERROR;
+    /* Reset the CANx */
+    if(hcan->Instance==CAN1)
+    {
+        System_Module_Reset(RST_CAN1);
+    }
+    else
+    {
+        System_Module_Reset(RST_CAN2);
+    }
+    HAL_CAN_MspInit(hcan);
+    HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Initialization);//enter CAN_OperatingMode_Initialization
+    hcan->Instance->BTR0=0xff;
+    hcan->Instance->BTR0=(hcan->Init.CAN_SJW<<6)|(hcan->Init.CAN_BRP);
+    hcan->Instance->BTR1=(hcan->Init.CAN_SAM<<7)|(hcan->Init.CAN_TSEG2<<4)|(hcan->Init.CAN_TSEG1);
+    HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Normal);//enter CAN_OperatingMode_Normal
+    return HAL_OK;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_DeInit
+* Description :	Deinitializes the CAN peripheral registers to their default
+*               reset values.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : HAL status
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
+{
+    /* Check CAN handle */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR;
+
+    HAL_CAN_MspDeInit(hcan);
+    
+    /* Reset the CAN peripheral */
+    SET_BIT(hcan->Instance->MOD, CAN_MOD_RM);
+    
+    /* Return function status */
+    return HAL_OK;
+}
+/*********************************************************************************
+* Function    : HAL_CAN_Transmit
+* Description :	Initiates the transmission of a message.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Input       : TxMessage : ppointer to a structure which contains CAN Id, CAN
+  *                         DLC and CAN data.
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, CanTxRxMsg* TxMessage)
+{
+    uint8_t i = 0;
+    uint8_t can_id[4];  
+    uint32_t frame_header;  
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ;
+    if(!IS_CAN_IDTYPE(TxMessage->IDE)) return HAL_ERROR;
+    if(!IS_CAN_RTR(TxMessage->RTR)) return HAL_ERROR;
+    if(!IS_CAN_DLC(TxMessage->DLC)) return HAL_ERROR;
+    /* Set up the DLC */
+    frame_header =TxMessage->DLC & 0x0F;  // standard data frame 
+    /* Set up the Id */
+    if(TxMessage->IDE==CAN_Id_Standard)//Standard ID
+    {
+        can_id[0] = TxMessage->StdId >>3; 
+        can_id[1] = (TxMessage->StdId&0x07)<<5;   
+        for(i=0;i<2;i++)
+        {
+            hcan->Instance->DF.DATABUF[1+i] = can_id[i];  
+        }
+    }
+    else//Id_Extended
+    {
+        can_id[0] = TxMessage->ExtId>>21; 
+        can_id[1] = (TxMessage->ExtId&0x1FE000)>>13;   
+        can_id[2] = (TxMessage->ExtId&0x1FE0)>>5; 
+        can_id[3] = (TxMessage->ExtId&0x1F)<<3;
+        frame_header |= (CAN_Id_Extended<<7);  // extended data frame 
+        for(i=0;i<4;i++)
+        {
+            hcan->Instance->DF.DATABUF[1+i] = can_id[i];  
+        }
+    }
+    if(TxMessage->RTR==CAN_RTR_Data)//CAN_RTR_Data
+    {
+        frame_header&=~(CAN_RTR_Remote<<6);
+        for(i=0; i<TxMessage->DLC; i++)  
+        {
+            hcan->Instance->DF.DATABUF[3+(TxMessage->IDE*2)+i] = TxMessage->Data[i];      
+        }
+    }
+    else//CAN_RTR_Remote
+    {
+        frame_header|=(CAN_RTR_Remote<<6);
+    }
+    hcan->Instance->DF.DATABUF[0]=frame_header;
+    hcan->Instance->CMR = CAN_CMR_TR;  // transfer request
+    while((hcan->Instance->SR & CAN_SR_TCS)==0x00); //wait for send ok	
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_CancelTransmit
+* Description :	Cancels a transmit request.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_CancelTransmit(CAN_HandleTypeDef *hcan)
+{
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return ;
+    /* abort transmission */
+    hcan->Instance->CMR |= CAN_CMR_AT; //Abort Transmission 
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_Receive
+* Description :	Receives a message.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Input       : RxMessage : pointer to a structure receive message which contains 
+*                           CAN Id, CAN DLC, CAN datas  .
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage)
+{
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ;
+    
+    hcan->RxMessage=RxMessage;
+
+    /* Enable the CAN Receive interrupt */
+    hcan->Instance->IER |= CAN_IER_RIE;
+    NVIC_ClearPendingIRQ(CAN1_IRQn);
+    NVIC_SetPriority(CAN1_IRQn, 5);
+    NVIC_EnableIRQ(CAN1_IRQn);
+
+    return HAL_OK;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_Receive
+* Description :	Receives a message.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Input       : RxMessage : pointer to a structure receive message which contains 
+*                           CAN Id, CAN DLC, CAN datas  .
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage)
+{
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR ;
+    while(!(hcan->Instance->SR & CAN_SR_RBS));
+    HAL_CAN_GetRxMessage(hcan, RxMessage);
+    return HAL_OK;
+}
+
+void HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, CanTxRxMsg* RxMessage)
+{
+    uint8_t i=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return ;
+    if(0 == (hcan->Instance->SR & CAN_SR_RBS) ) return;  // receive fifo not empty  
+    /* Get the IDE */
+    RxMessage->IDE = (uint8_t)(0x80 & hcan->Instance->DF.DATABUF[0])>>7;
+    /* Get the RTR */
+    RxMessage->RTR = (uint8_t)(0x40 & hcan->Instance->DF.DATABUF[0])>>6;
+    /* Get the DLC */
+    RxMessage->DLC = (uint8_t)0x0F & hcan->Instance->DF.DATABUF[0];
+    if (RxMessage->IDE == CAN_Id_Standard)
+    {
+        RxMessage->StdId = (uint32_t)(( hcan->Instance->DF.DATABUF[1]<<8) |  hcan->Instance->DF.DATABUF[2])>>5;;
+        for(i=0; i<RxMessage->DLC; i++)  
+        {
+            RxMessage->Data[i] = hcan->Instance->DF.DATABUF[3+i];       
+        }
+    }
+    else
+    {
+        RxMessage->ExtId = (uint32_t)(( hcan->Instance->DF.DATABUF[1]<<24) | ( hcan->Instance->DF.DATABUF[2]<<16) | ( hcan->Instance->DF.DATABUF[3]<<8) | (hcan->Instance->DF.DATABUF[4] ))>>3;;
+        for(i=0; i<RxMessage->DLC; i++)  
+        {
+            RxMessage->Data[i] = hcan->Instance->DF.DATABUF[5+i];       
+        }
+    }
+    /* Release the FIFO */
+    hcan->Instance->CMR |= CAN_CMR_RRB; //Release Receive Buffer
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  CANx:   where x can be 1 or 2 to to select the CAN peripheral.
+            CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef
+  *                               structure that contains the configuration 
+  *                               information.
+  * @retval None.
+  */
+
+/*********************************************************************************
+* Function    : HAL_CAN_ConfigFilter
+* Description :	Initializes the CAN peripheral according to the specified  parameters in the CAN_FilterInitStruct.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Input       : CAN_FilterInitStruct : pointer to a CAN_FilterInitTypeDef structure that contains the configuration 
+*                                       information.
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan,CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+    HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Initialization);//enter CAN_OperatingMode_Initialization
+    /* Filter Mode */
+    if (CAN_FilterInitStruct->CAN_FilterMode ==CAN_FilterMode_Dual) /*Dual mode*/
+    {
+        hcan->Instance->MOD &= ~CAN_MOD_AFM;
+        /*Dual mode ACR set*/    
+        hcan->Instance->DF.FILTER.ACR[0] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE00000)>>21;	/*Dual mode ACR0=ID28...ID21 of ID1*/
+        hcan->Instance->DF.FILTER.ACR[1] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE000)>>13; 		/*Dual mode ACR0=ID20...ID13 of ID1*/
+        hcan->Instance->DF.FILTER.ACR[2] = (CAN_FilterInitStruct->CAN_FilterId2&0x1FE00000)>>21;  /*Dual mode ACR0=ID28...ID21 of ID2*/
+        hcan->Instance->DF.FILTER.ACR[3] = (CAN_FilterInitStruct->CAN_FilterId2&0x1FE000)>>13;     /*Dual mode ACR0=ID20...ID13 of ID2*/
+        /*Dual mode AMR set*/   
+        hcan->Instance->DF.FILTER.AMR[0] = (CAN_FilterInitStruct->CAN_FilterMaskId1)>>24; 
+        hcan->Instance->DF.FILTER.AMR[1] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF0000)>>16; 
+        hcan->Instance->DF.FILTER.AMR[2] = (CAN_FilterInitStruct->CAN_FilterMaskId2)>>24; 
+        hcan->Instance->DF.FILTER.AMR[3] = (CAN_FilterInitStruct->CAN_FilterMaskId2&0xFF0000)>>16; 
+    }
+    else /*Single mode*/
+    {
+        hcan->Instance->MOD |= CAN_MOD_AFM;
+        /*Single mode ACR set*/    
+        hcan->Instance->DF.FILTER.ACR[0] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE00000)>>21;	/*Single mode ACR0=ID28...ID21*/
+        hcan->Instance->DF.FILTER.ACR[1] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE000)>>13; 		/*Single mode ACR1=ID20...ID13*/
+        hcan->Instance->DF.FILTER.ACR[2] = (CAN_FilterInitStruct->CAN_FilterId1&0x1FE0)>>5; 			/*Single mode ACR2=ID12...ID5*/
+        hcan->Instance->DF.FILTER.ACR[3] = (CAN_FilterInitStruct->CAN_FilterId1&0x1F)<<3;  				/*Single mode ACR3=ID4...ID0*/
+        /*Single mode AMR set*/   
+        hcan->Instance->DF.FILTER.AMR[0] = (CAN_FilterInitStruct->CAN_FilterMaskId1)>>24; 
+        hcan->Instance->DF.FILTER.AMR[1] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF0000)>>16; 
+        hcan->Instance->DF.FILTER.AMR[2] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF00)>>8; 
+        hcan->Instance->DF.FILTER.AMR[3] = (CAN_FilterInitStruct->CAN_FilterMaskId1&0xFF);   
+    }
+
+    HAL_CAN_OperatingModeRequest(hcan,CAN_OperatingMode_Normal);//enter CAN_OperatingMode_Initialization
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_Sleep
+* Description :	Enters the sleep mode.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan)
+{
+    HAL_StatusTypeDef status;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR;
+    /* Request Sleep mode */
+    hcan->Instance->MOD |= CAN_MOD_SM; //Enter Sleep Mode
+   
+    /* Sleep mode status */
+    if ((hcan->Instance->MOD & CAN_MOD_SM) == CAN_MOD_SM)
+    {
+    /* Sleep mode entered */
+        status= HAL_OK;
+    }else
+    {
+        status=HAL_ERROR;
+    }
+    /* return sleep mode status */
+    return status;
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_WakeUp
+* Description :	Wakes the CAN up.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+    HAL_StatusTypeDef status;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return HAL_ERROR;
+    /* sleep wake mode */
+    hcan->Instance->MOD &=~ CAN_MOD_SM; //Enter Sleep Mode
+   
+    /* sleep wake status */
+    if ((hcan->Instance->MOD & CAN_MOD_SM)== CAN_MOD_SM)
+    {
+        /* sleep wake not entered */
+        status= HAL_ERROR;
+    }else
+    {
+        status=HAL_OK;
+    }
+    /* return sleep mode status */
+    return status;
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetTransmitErrorCounter
+* Description :	Returns the CANx Transmit Error Counter(TXERR).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetTransmitErrorCounter(CAN_HandleTypeDef *hcan)
+{
+    uint8_t counter=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    /* Get the  CANx Transmit Error Counter(TXERR) */
+    counter = (uint8_t)(hcan->Instance->TXERR);
+    /* Return the CANx Transmit Error Counter(TXERR) */
+    return counter;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetReceiveErrorCounter
+* Description :	Returns the  CANx Receive Error Counter(RXERR).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetReceiveErrorCounter(CAN_HandleTypeDef *hcan)
+{
+    uint8_t counter=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    /* Get the  CANx Receive Error Counter(RXERR) */
+    counter = (uint8_t)(hcan->Instance->RXERR);
+    /* Return the CANx Receive Error Counter(RXERR) */
+    return counter;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetErrorCode
+* Description :	Returns the CANx's  error code (ECC).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Input       : Error_Type:This parameter can be one of the following flags: 
+*														CAN_ErrorType_SegCode
+*														CAN_ErrorType_Direction
+*														CAN_ErrorType_ErrCode
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetErrorCode(CAN_HandleTypeDef *hcan,uint32_t Error_Type)
+{
+    uint8_t ErrorCode=0;
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    if(!IS_CAN_ErrorType(Error_Type)) return -1;
+    /* Get the CANx  Error SegCode */
+    if(Error_Type==CAN_ErrorType_SegCode)
+    {
+        ErrorCode= (uint8_t)(hcan->Instance->ECC & CAN_ErrorType_SegCode);
+    }
+    /* Get the CANx  Error Direction */
+    else if(Error_Type==CAN_ErrorType_Direction)
+    {
+        ErrorCode= (uint8_t)((hcan->Instance->ECC & CAN_ErrorType_Direction)>>5);
+    }
+    /* Get the CANx  Error ErrCode */
+    else
+    {
+        ErrorCode= (uint8_t)((hcan->Instance->ECC & CAN_ErrorType_ErrCode)>>6);
+    }
+    return ErrorCode;
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetErrorAlarmCounter
+* Description :	Returns the  CANx Error  Alarm Counter(EWLR).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetErrorAlarmCounter(CAN_HandleTypeDef *hcan)
+{
+    uint8_t counter=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    /* Get the  CANx Error Alarm Counter(EWLR) */
+    counter = (uint8_t)(hcan->Instance->EWLR);
+    /* Return the CANx Error Alarm Counter(EWLR) */
+    return counter;
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetArbitrationErrorPosition
+* Description :	Returns the  CANx Arbitration Error Position(ALC).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetArbitrationErrorPosition(CAN_HandleTypeDef *hcan)
+{
+    uint8_t position=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    /* Get the  CANx Arbitration Error Counter(ALC) */
+    position = (uint8_t)((hcan->Instance->ALC)+1);
+    /* Return the CANx Arbitration Error Counter(ALC) */
+    return position;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetReceiveFiFoCounter
+* Description :	Returns the  CANx Receive FiFo Counter(RMC).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetReceiveFiFoCounter(CAN_HandleTypeDef *hcan)
+{
+    uint8_t counter=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    /* Get the  CANx Receive FiFo Counter(RMC) */
+    counter = (uint8_t)(hcan->Instance->RMC);
+    /* Return the CANx Receive FiFo Counter(RMC) */
+    return counter;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_GetReceiveFiFoAddr
+* Description :	 Returns the  CANx Receive FiFo start address(RBSA).
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+int8_t HAL_CAN_GetReceiveFiFoAddr(CAN_HandleTypeDef *hcan)
+{
+    uint8_t addr=0;
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return -1;
+    /* Get the  CANx Receive FiFo start address(RBSA) */
+    addr = (uint8_t)(hcan->Instance->RBSA);
+    /* Return the CANx Receive FiFo start address(RBSA) */
+    return addr;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_ReleaseReceiveFIFO
+* Description :	Releases the Receive FIFO.
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_ReleaseReceiveFIFO(CAN_HandleTypeDef *hcan)
+{
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return;
+    /* Releases the Receive FIFO. */
+    hcan->Instance->CMR|=CAN_CMR_RRB;	
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_ClearOverload
+* Description : Clear Overload
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_ClearOverload(CAN_HandleTypeDef *hcan)
+{
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return;
+    /* Clear Overload. */
+    hcan->Instance->CMR|=CAN_CMR_CDO;	
+}
+
+
+/*********************************************************************************
+* Function    : HAL_CAN_SlefReceive
+* Description : Slef Receive
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_SelfReceive(CAN_HandleTypeDef *hcan)
+{
+    /* Check the parameters */
+    if(!IS_CAN_ALL_PERIPH(hcan->Instance)) return;
+    /* Slef Receive. */
+    hcan->Instance->CMR|=CAN_CMR_SRR;	
+    while((hcan->Instance->SR & CAN_SR_TCS)==0x00); //wait for send ok	
+}
+
+/*********************************************************************************
+* Function    : HAL_CAN_IRQHandler
+* Description : This function handles CAN interrupt request.
+* Input       : hdma : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+    volatile uint32_t lu32_IR;
+    lu32_IR = hcan->Instance->IR;//read clear 
+
+    if(lu32_IR & CAN_IR_RI) //RI
+    {
+        /* CAN ReceiveIT complete callback */ 
+        HAL_CAN_GetRxMessage(hcan, hcan->RxMessage);  
+        hcan->CAN_ReceiveIT_Callback(hcan);  
+    }
+    if(lu32_IR & CAN_IR_TI) //TI
+    {
+        /* CAN TransmitIT complete callback */ 
+        hcan->CAN_TransmitIT_Callback(hcan);  
+    }
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_COMP.c

@@ -0,0 +1,320 @@
+/*
+  ******************************************************************************
+  * @file    HAL_COMP.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   COMP HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Comparator Peripheral (COMP).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************
+ * function   : HAL_COMP_MspInit
+ * Description: Inition the comparator gpio and clock
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ * output     : none
+ ************************************************************************/
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_Handle; 
+    
+    System_Module_Enable(EN_COMP);
+    
+    if(hcomp->Init.Comparator == COMP1 )
+    {
+        /* COMP1 GPIO inition VINP:PC4(INP_0)*/
+        /* COMP1 GPIO inition VINM:PA4(INM_0)*/
+        /* COMP1 GPIO inition VOUT:PA0(FUNCTION_7)*/
+        GPIO_Handle.Pin            = GPIO_PIN_4;
+        GPIO_Handle.Mode           = GPIO_MODE_ANALOG;
+        GPIO_Handle.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOC, &GPIO_Handle);
+        
+        GPIO_Handle.Pin            = GPIO_PIN_4;
+        GPIO_Handle.Mode           = GPIO_MODE_ANALOG;
+        GPIO_Handle.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_Handle);
+        
+        GPIO_Handle.Pin            = GPIO_PIN_0;
+        GPIO_Handle.Mode           = GPIO_MODE_AF_PP;
+        GPIO_Handle.Alternate      = GPIO_FUNCTION_7;
+        GPIO_Handle.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_Handle);            
+    }
+    else if(hcomp->Init.Comparator == COMP2 )
+    {
+        /* COMP2 GPIO inition VINP:PA3(INP_1)*/
+        /* COMP2 GPIO inition VOUT:PA7(FUNCTION_7)*/
+        GPIO_Handle.Pin            = GPIO_PIN_3;
+        GPIO_Handle.Mode           = GPIO_MODE_ANALOG;
+        GPIO_Handle.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_Handle);
+        
+        GPIO_Handle.Pin            = GPIO_PIN_7;
+        GPIO_Handle.Mode           = GPIO_MODE_AF_PP;
+        GPIO_Handle.Alternate      = GPIO_FUNCTION_7;
+        GPIO_Handle.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_Handle);
+    }
+}
+
+/************************************************************************
+ * function   : HAL_COMP_MspDeInit
+ * Description: De-Inition the comparator gpio and clock
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ * output     : none
+ ************************************************************************/
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    System_Module_Reset(RST_COMP);
+    System_Module_Enable(EN_COMP);
+}
+
+/************************************************************************
+ * function   : HAL_COMP_Init
+ * Description: Inition the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef* hcomp)
+{    
+    uint32_t u32RegTemp;
+    __IO uint32_t *gu32RegCrx;
+
+    /* Check the COMP handle allocation */
+    if (hcomp == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR;
+    if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR;
+    if(!IS_COMP_ALL_CRV_EN(hcomp->Init.Crv_En)) return HAL_ERROR;
+    if(!IS_COMP_ALL_CRV_SEL(hcomp->Init.Crv_Sel)) return HAL_ERROR;
+    if(!IS_COMP_ALL_CRV_CFG(hcomp->Init.Crv_Cfg)) return HAL_ERROR;
+    if(!IS_COMP_ALL_WINMODE(hcomp->Init.WinMode)) return HAL_ERROR;
+    if(!IS_COMP_ALL_WINOUT(hcomp->Init.WinOut)) return HAL_ERROR;
+    if(!IS_COMP_ALL_POLARITY(hcomp->Init.Polarity)) return HAL_ERROR;
+    if(!IS_COMP_ALL_FLTEN(hcomp->Init.FltEn)) return HAL_ERROR;
+    if(!IS_COMP_ALL_FLTTIME(hcomp->Init.FltTime)) return HAL_ERROR;
+    if(!IS_COMP_ALL_BLANKTIME(hcomp->Init.BlankTime)) return HAL_ERROR;
+    if(!IS_COMP_ALL_BLANKSEL(hcomp->Init.BlankSel)) return HAL_ERROR;
+    if(!IS_COMP_ALL_INPSEL(hcomp->Init.InPSel)) return HAL_ERROR;
+    if(!IS_COMP_ALL_INMSEL(hcomp->Init.InMSel)) return HAL_ERROR;
+    if(!IS_COMP_ALL_HYS(hcomp->Init.HYS)) return HAL_ERROR;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_COMP_MspInit(hcomp);
+                 
+    if(hcomp->Init.Comparator == COMP1 )
+        gu32RegCrx = &hcomp->Instance->CR1;
+    else
+        gu32RegCrx = &hcomp->Instance->CR2;
+     
+    //Check if the register is locked
+    if(READ_BIT(*gu32RegCrx , COMP_CR_LOCK))
+    {
+        System_Module_Reset(RST_COMP);    
+    }
+    
+    //Check if the comparetor is enable
+    if(READ_BIT(*gu32RegCrx , COMP_CR_EN))
+        CLEAR_BIT(*gu32RegCrx , COMP_CR_EN);
+    
+    u32RegTemp = *gu32RegCrx ;
+    
+    u32RegTemp = u32RegTemp | ((hcomp->Init.Crv_Cfg << COMP_CR_CRV_CFG_POS)& COMP_CR_CRV_CFG_MASK) | \
+                              ((hcomp->Init.Crv_Sel << 24) & COMP_CR_CRV_SEL) | \
+                              ((hcomp->Init.Crv_En << 23) & COMP_CR_CRV_EN) | \
+                              ((hcomp->Init.WinMode << 22) & COMP_CR_WINMODE) | \
+                              ((hcomp->Init.WinOut << 21) & COMP_CR_WINOUT) | \
+                              ((hcomp->Init.Polarity << 20) & COMP_CR_POLARITY) | \
+                              ((hcomp->Init.FltEn << 19) & COMP_CR_FLTEN) | \
+                              ((hcomp->Init.FltTime << COMP_CR_FLTTIME_POS)& COMP_CR_FLTTIME_MASK) | \
+                              ((hcomp->Init.BlankTime << COMP_CR_BLANKTIME_POS)& COMP_CR_BLANKTIME_MASK) | \
+                              ((hcomp->Init.BlankSel << COMP_CR_BLANKSEL_POS)& COMP_CR_BLANKSEL_MASK) | \
+                              ((hcomp->Init.InPSel << COMP_CR_INPSEL_POS)& COMP_CR_INPSEL_MASK) | \
+                              ((hcomp->Init.InMSel << COMP_CR_INMSEL_POS)& COMP_CR_INMSEL_MASK) | \
+                              ((hcomp->Init.HYS << COMP_CR_HYS_POS)& COMP_CR_HYS_MASK);
+    
+    //Write the COMP_CR register .
+    WRITE_REG(*gu32RegCrx,u32RegTemp);
+
+    SET_BIT(*gu32RegCrx , COMP_CR_EN); //enable
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_COMP_Enable
+ * Description: Enable the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_Enable(COMP_HandleTypeDef* hcomp)
+{
+    __IO uint32_t *gu32RegCrx;
+    
+    /* Check the COMP handle allocation */
+    if (hcomp == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR;
+    if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR;
+
+    if(hcomp->Init.Comparator == COMP1 )
+        gu32RegCrx = &hcomp->Instance->CR1;
+    else
+        gu32RegCrx = &hcomp->Instance->CR2;
+
+    SET_BIT(*gu32RegCrx , COMP_CR_EN); //enable
+    
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_COMP_DeInit
+ * Description: Deinit and reset the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef* hcomp)
+{
+    /* Check the COMP handle allocation */
+    if (hcomp == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    HAL_COMP_MspDeInit(hcomp); 
+
+    memset(&hcomp->Init, 0, sizeof(hcomp->Init));
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_COMP_Disable
+ * Description: Disable the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_Disable(COMP_HandleTypeDef* hcomp)
+{
+    __IO uint32_t *gu32RegCrx;
+    
+    /* Check the COMP handle allocation */
+    if (hcomp == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR;
+    if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR;
+
+    if(hcomp->Init.Comparator == COMP1 )
+        gu32RegCrx = &hcomp->Instance->CR1;
+    else
+        gu32RegCrx = &hcomp->Instance->CR2;
+
+    CLEAR_BIT(*gu32RegCrx , COMP_CR_EN); //disable
+    
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_COMP_GetOutputLevel
+ * Description: Get the output level of the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_GetOutputLevel(COMP_HandleTypeDef* hcomp)
+{
+    uint32_t u32RegTemp;
+    /* Check the parameters */
+    if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR;
+    if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR;
+
+    u32RegTemp = READ_REG(hcomp->Instance->SR);
+    
+    if(hcomp->Init.Comparator == COMP1 )
+    {
+        hcomp->OutputLevel_Org = (u32RegTemp & COMP_SR_VCOUT1_ORG)? 1:0;
+        hcomp->OutputLevel = (u32RegTemp & COMP_SR_VCOUT1)? 1:0;
+    }
+    else
+    {
+        hcomp->OutputLevel_Org = (u32RegTemp & COMP_SR_VCOUT2_ORG)? 1:0;
+        hcomp->OutputLevel = (u32RegTemp & COMP_SR_VCOUT2)? 1:0;
+    }
+     
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_COMP_Lock
+ * Description: Lock the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef* hcomp)
+{
+    __IO uint32_t *gu32RegCrx;
+    
+    /* Check the COMP handle allocation */
+    if (hcomp == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_COMP_ALL_INSTANCE(hcomp->Instance)) return HAL_ERROR;
+    if(!IS_COMP_ALL_COMP(hcomp->Init.Comparator)) return HAL_ERROR;
+
+    if(hcomp->Init.Comparator == COMP1 )
+        gu32RegCrx = &hcomp->Instance->CR1;
+    else
+        gu32RegCrx = &hcomp->Instance->CR2;
+    
+    SET_BIT(*gu32RegCrx , COMP_CR_LOCK); //lock
+    /* Return function status */
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_COMP_Start
+ * Description: Start the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+    return(HAL_COMP_Enable(hcomp));
+}
+
+
+/************************************************************************
+ * function   : HAL_COMP_Stop
+ * Description: Stop the comparator
+ * input      : COMP_HandleTypeDef* hcomp: pointer to comparator structure.
+ ************************************************************************/
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+    return(HAL_COMP_Disable(hcomp));
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_CRC.c

@@ -0,0 +1,54 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Crc.c
+  * @author  Firmware Team
+  * @version V1.0.0
+  * @date    2020
+  * @brief   CRC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include  "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_CRC_Init
+* Description : Initialize the CRC MSP.
+* Input       : hcrc: CRC handle.
+* Output      : 
+* Author      : cl                         Data : 2021 
+**********************************************************************************/
+void HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
+{
+	System_Module_Enable(EN_CRC);
+	hcrc->Instance->CTRL = hcrc->Init.PolyRev | hcrc->Init.OutxorRev | hcrc->Init.InitRev | hcrc->Init.RsltRev |
+	                       hcrc->Init.DataRev | hcrc->Init.PolyLen   | hcrc->Init.DataLen;
+
+	hcrc->Instance->INIT = hcrc->Init.InitData;	
+	hcrc->Instance->OUTXOR = hcrc->Init.OutXorData;
+	hcrc->Instance->POLY = hcrc->Init.PolyData;
+}
+
+/*********************************************************************************
+* Function    : HAL_CRC_Calculate
+* Description : Calculate the crc calue of input data.
+* Input       : hcrc:         CRC handle.
+* Output      : CRC value
+* Author      : cl                        Data : 2021 
+**********************************************************************************/
+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc)
+{
+	HAL_CRC_Init(hcrc);
+
+    while(hcrc->CRC_Data_Len--)
+    {
+        hcrc->Instance->DATA = *hcrc->CRC_Data_Buff++;
+    }
+
+	return (hcrc->Instance->DATA);
+}
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DAC.c

@@ -0,0 +1,828 @@
+/*
+  ******************************************************************************
+  * @file    HAL_DAC.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   DAC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (DAC).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+  /*********************************************************************************
+* Function    : HAL_DAC_IRQHandler
+* Description : This function uses the interruption of DMA  underrun.
+* Input       : hdac : pointer to a DAC_HandleTypeDef structure that contains
+*                      the configuration information for DAC module
+* Output      : 
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
+{
+    if((hdac->Instance->SR&DAC_SR_DMAUDR1)==DAC_SR_DMAUDR1||(hdac->Instance->SR &DAC_SR_DMAUDR2)==DAC_SR_DMAUDR2)
+    {
+        //clear the DMA underrun
+        hdac->Instance->SR|=DAC_SR_DMAUDR1|DAC_SR_DMAUDR2;   
+    }
+}
+/*********************************************************************************
+* Function    : HAL_DAC_MspInit
+* Description : Initialize the DAC MSP.
+* Input       : hdac : pointer to a DAC_HandleTypeDef structure that contains
+*                      the configuration information for DAC module
+* Output      : 
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
+{
+    /* NOTE : This function should not be modified, when the callback is needed,
+    the HAL_DAC_MspInit can be implemented in the user file
+    */
+    /* For Example */
+    if(hdac->Instance==DAC)
+    { 
+        /* Enable DAC clock */
+        System_Module_Enable(EN_DAC);
+        GPIO_InitTypeDef GPIO_InitStructure;   	
+        /* Initialization GPIO */
+        /**DAC1 GPIO Configuration    
+        PB1  ------> DAC_OUT1 
+        PB0  ------> DAC_OUT2 
+        */
+        GPIO_InitStructure.Pin = GPIO_PIN_1|GPIO_PIN_0;	
+        GPIO_InitStructure.Pull=GPIO_NOPULL;
+        GPIO_InitStructure.Mode = GPIO_MODE_ANALOG;
+        HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
+        
+        /* Enable the DAC DMA underrun interrupt */
+        hdac->Instance->CR |= DAC_CR_DMAUDRIE1|DAC_CR_DMAUDRIE2;
+        NVIC_ClearPendingIRQ(DAC_IRQn);
+        NVIC_SetPriority(DAC_IRQn, 5);
+        NVIC_EnableIRQ(DAC_IRQn);
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_MspDeInit
+* Description : DAC MSP De-Initialization.
+* Input       : hdac : pointer to a DAC_HandleTypeDef structure that contains
+*                      the configuration information for DAC module
+* Output      : 
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+    if(hdac->Instance==DAC)
+    {
+        /* USER CODE BEGIN DAC1_MspDeInit 0 */
+
+        /* USER CODE END DAC1_MspDeInit 0 */
+        /* Peripheral clock disable */
+        System_Module_Disable(EN_DAC);
+        /**DAC1 GPIO Configuration    
+        PB1  ------> DAC_OUT1 
+        PB0  ------> DAC_OUT2 
+        */
+        HAL_GPIO_DeInit(GPIOB, GPIO_PIN_0);
+        HAL_GPIO_DeInit(GPIOB, GPIO_PIN_1);
+        /* DAC1 DMA DeInit */
+        HAL_DMA_DeInit(hdac->DMA_Handle1);
+        HAL_DMA_DeInit(hdac->DMA_Handle2);
+        /* USER CODE BEGIN DAC1_MspDeInit 1 */
+
+        /* USER CODE END DAC1_MspDeInit 1 */
+    }
+
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_Init
+* Description :	Initializes the CAN peripheral according to the specified  parameters in the DAC_HandleTypeDef..
+* Input       : hdac : pointer to a DAC_HandleTypeDef structure that contains
+*                      the configuration information for DAC module
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
+{
+    uint8_t InitStatus = HAL_ERROR;
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+
+    System_Module_Reset(RST_DAC);
+    HAL_DAC_MspInit(hdac);
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_DeInit
+* Description :	Deinitialize the DAC peripheral registers to their default reset values.
+* Input       : hdac : pointer to a DAC_HandleTypeDef structure that contains
+*                      the configuration information for DAC module
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
+{
+    /* Check DAC handle */
+    if (hdac == NULL)
+    {
+        return HAL_ERROR;
+    }
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    HAL_DAC_MspDeInit(hdac);
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_ConfigChannel
+* Description :	Configures the selected DAC channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               sConfig:DAC configuration structure
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @argDAC_CHANNEL_2
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{
+    uint32_t tmpreg1, tmpreg2;
+    uint32_t tickstart = 0U;
+    uint32_t ConnectOnChipPeripheral=0U;
+    /* Check the DAC parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_TRIGGER(sConfig->DAC_Trigger)) return HAL_ERROR;
+    if(!IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)) return HAL_ERROR;
+    if(!IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)) return HAL_ERROR;
+    if(!IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)) return HAL_ERROR;
+    if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
+    {
+        if(!IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)) return HAL_ERROR;
+    }
+    if(!IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)) return HAL_ERROR;
+    if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
+    {
+        if(!IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)) return HAL_ERROR;
+        if(!IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)) return HAL_ERROR;
+        if(!IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)) return HAL_ERROR;
+    }
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR;
+
+
+
+    if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
+    /* Sample on old configuration */
+    {
+        /* SampleTime */
+        if (Channel == DAC_CHANNEL_1)
+        {
+            hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+        }
+        else /* Channel 2 */
+
+            hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+    
+        /* HoldTime */
+        MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+        /* RefreshTime */
+        MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL), (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+    }
+
+    if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
+    /* USER TRIMMING */
+    {
+        /* Get the DAC CCR value */
+        tmpreg1 = hdac->Instance->CCR;
+        /* Clear trimming value */
+        tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
+        /* Configure for the selected trimming offset */
+        tmpreg2 = sConfig->DAC_TrimmingValue;
+        /* Calculate CCR register value depending on DAC_Channel */
+        tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+        /* Write to DAC CCR */
+        hdac->Instance->CCR = tmpreg1;
+    }
+    else
+    {
+        /*  factory trimming in NVR,read to DAC_CCR */
+        uint32_t OTRIM=*(uint32_t *)(0x80248);
+        uint32_t OTRIM_high=(OTRIM&0xffff0000)>>16;
+        uint32_t OTRIM_low=(OTRIM&0xffff);
+        if (OTRIM_low==((~OTRIM_high)&0xffff))
+            {
+                tmpreg1=(OTRIM_low&0x1f)|(((OTRIM_low&0x3E0)>>5)<<16);
+                hdac->Instance->CCR = tmpreg1;  
+            }
+    }
+
+
+    /* Get the DAC MCR value */
+    tmpreg1 = hdac->Instance->MCR;
+    /* Clear DAC_MCR_MODEx bits */
+    tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
+    /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
+    ConnectOnChipPeripheral=sConfig->DAC_ConnectOnChipPeripheral;
+    if((sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)&&(sConfig->DAC_OutputBuffer==DAC_OUTPUTBUFFER_DISABLE))
+    {
+        ConnectOnChipPeripheral=(!ConnectOnChipPeripheral);
+    }
+    tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | ConnectOnChipPeripheral); 
+    /* Calculate MCR register value depending on DAC_Channel */
+    tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+    /* Write to DAC MCR */
+    hdac->Instance->MCR = tmpreg1;
+
+    /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
+    CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
+
+    /* Get the DAC CR value */
+    tmpreg1 = hdac->Instance->CR;
+    /* Clear TENx, TSELx, WAVEx and MAMPx bits */
+    tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
+    /* Configure for the selected DAC channel: trigger */
+    /* Set TSELx and TENx bits according to DAC_Trigger value */
+    tmpreg2 = sConfig->DAC_Trigger;
+    /* Calculate CR register value depending on DAC_Channel */
+    tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+    /* Write to DAC CR */
+    hdac->Instance->CR = tmpreg1;
+
+    /* Disable wave generation */
+    hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));
+
+
+    /* Return function status */
+    return HAL_OK;  
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_Start
+* Description :	 Enables DAC and starts conversion of channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @argDAC_CHANNEL_2
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; 
+      uint32_t tmp1 = 0U, tmp2 = 0U;
+    
+    if (Channel == DAC_CHANNEL_1)
+    {
+        hdac->Instance->CR|=DAC_CR_EN1;  
+        tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
+        tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
+         /* Check if software trigger enabled */
+    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
+    {
+        /* Enable the selected DAC software conversion */
+        hdac->Instance->SWTRIGR|=DAC_SWTRIGR_SWTRIG1;
+    }
+    }
+    else
+    {
+        hdac->Instance->CR|=DAC_CR_EN2; 
+        tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
+        tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;    
+         /* Check if software trigger enabled */
+    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
+    {
+        /* Enable the selected DAC software conversion */
+        hdac->Instance->SWTRIGR|=DAC_SWTRIGR_SWTRIG2;
+    }
+    }
+    /* Return function status */
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_Stop
+* Description :	Disables DAC and stop conversion of channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @argDAC_CHANNEL_2
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; 
+  
+    /* Disable the Peripheral */
+    if (Channel == DAC_CHANNEL_1)
+    {
+        hdac->Instance->CR&=~DAC_CR_EN1;  
+    }
+    else
+    {
+        hdac->Instance->CR&=~DAC_CR_EN2;  
+    }
+ 
+    /* Return function status */
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_Start_DMA
+* Description :	Enables DAC and starts conversion of channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @argDAC_CHANNEL_2 @arg DAC_CHANNEL_Dual
+*               pData: The destination peripheral Buffer address.
+*               Length: The length of data to be transferred from memory to DAC peripheral
+*               Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values:
+                            @arg DAC_ALIGN_8B_R   @arg DAC_ALIGN_12B_L   @arg DAC_ALIGN_12B_R  
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, uint32_t Alignment)
+{
+    HAL_StatusTypeDef status;
+    uint32_t DstAddr = 0U;
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; 
+    if(!IS_DAC_ALIGN(Alignment)) return HAL_ERROR;  
+    
+    if (Channel == DAC_CHANNEL_1)
+    {
+        /* Enable the DAC DMA underrun interrupt */
+        /* Enable the selected DAC channel2 DMA request */
+        hdac->Instance->CR |= DAC_CR_EN1|DAC_CR_DMAEN1|DAC_CR_DMAUDRIE1;   
+        /* Case of use of channel 1 */
+        switch (Alignment)
+        {
+            case DAC_ALIGN_12B_R:
+            /* Get DHR12R1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR12R1;
+            break;
+            case DAC_ALIGN_12B_L:
+            /* Get DHR12L1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR12L1;
+            break;
+            case DAC_ALIGN_8B_R:
+            /* Get DHR8R1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR8R1;
+            break;
+            default:
+            break;
+        }
+        status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, DstAddr, Length); 
+    }
+    else if(Channel == DAC_CHANNEL_2)
+    {
+        /* Enable the DAC DMA underrun interrupt */
+        /* Enable the selected DAC channel2 DMA request */
+        hdac->Instance->CR |= DAC_CR_EN2|DAC_CR_DMAEN2|DAC_CR_DMAUDRIE2;   
+      
+        /* Case of use of channel 1 */
+        switch (Alignment)
+        {
+            case DAC_ALIGN_12B_R:
+            /* Get DHR12R1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR12R2;
+            break;
+            case DAC_ALIGN_12B_L:
+            /* Get DHR12L1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR12L2;
+            break;
+            case DAC_ALIGN_8B_R:
+            /* Get DHR8R1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR8R2;
+            break;
+            default:
+            break;
+        }
+        status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, DstAddr, Length); 
+    }
+    else/* DualChannel */
+    {
+        hdac->Instance->CR |= DAC_CR_EN1|DAC_CR_DMAEN1|DAC_CR_DMAUDRIE1|DAC_CR_EN2 ;   
+        /* Case of use of channel_1 DMA change two DAC channel */
+        switch (Alignment)
+        {
+            case DAC_ALIGN_12B_R:
+            /* Get DHR12R1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR12RD;
+            break;
+            case DAC_ALIGN_12B_L:
+            /* Get DHR12L1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR12LD;
+            break;
+            case DAC_ALIGN_8B_R:
+            /* Get DHR8R1 address */
+            DstAddr = (uint32_t)&hdac->Instance->DHR8RD;
+            break;
+            default:
+            break;
+        }
+        status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, DstAddr, Length); 
+    }
+    /* Return function status */
+    return status;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_Stop_DMA
+* Description :	Disables DAC and stop conversion of channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @argDAC_CHANNEL_2 @arg DAC_CHANNEL_Dual
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+    HAL_StatusTypeDef status = HAL_OK;
+
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; 
+  
+    /* Disable the selected DAC channel DMA request */
+    /* Disable the DMA Channel */
+    /* Channel1 is used */
+    if(Channel == DAC_CHANNEL_1)
+    { 
+        hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+        /* Disable the Peripheral */
+        hdac->Instance->CR&=~DAC_CR_EN1;
+        status = HAL_DMA_Abort(hdac->DMA_Handle1);
+    }
+  
+    else if(Channel == DAC_CHANNEL_2) /* Channel2 is used for */
+    { 
+        hdac->Instance->CR &= ~DAC_CR_DMAEN2;
+        hdac->Instance->CR&=~DAC_CR_EN2;
+        status = HAL_DMA_Abort(hdac->DMA_Handle2); 
+    }
+    else
+    {
+        hdac->Instance->CR &= ~DAC_CR_DMAEN1;
+        hdac->Instance->CR &= ~DAC_CR_DMAEN2;
+        /* Disable the Peripheral */
+        hdac->Instance->CR&=~DAC_CR_EN1;
+        hdac->Instance->CR&=~DAC_CR_EN2;
+        status = HAL_DMA_Abort(hdac->DMA_Handle1)|HAL_DMA_Abort(hdac->DMA_Handle2);
+    }
+  
+    /* Return function status */
+    return status;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_SetChannelValue
+* Description :	Set the specified data holding register value for DAC channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @argDAC_CHANNEL_2
+*               Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values:
+*                             @arg DAC_ALIGN_8B_R   @arg DAC_ALIGN_12B_L   @arg DAC_ALIGN_12B_R  
+*                 Data:The destination peripheral Buffer address.          
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+    __IO uint32_t tmp = 0;
+
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; 
+    if(!IS_DAC_ALIGN(Alignment)) return HAL_ERROR; 
+    
+    tmp = (uint32_t)hdac->Instance;
+    if (Channel == DAC_CHANNEL_1)
+    {
+        tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+    }
+    else
+    {
+        tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+    }
+    
+    /* Calculate and set dual DAC data holding register value */
+    if (Alignment == DAC_ALIGN_12B_L)
+    {
+        Data = (uint32_t)Data << 4;
+    }
+  
+    /* Set the DAC channel selected data holding register */
+    *(__IO uint32_t *) tmp = Data;
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DACEx_DualSetValue
+* Description :	Set the specified data holding register value for dual DAC channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Alignment: Specifies the data alignment for DAC channel.This parameter can be one of the following values:
+*                             @arg DAC_ALIGN_8B_R   @arg DAC_ALIGN_12B_L   @arg DAC_ALIGN_12B_R  
+*               Datax:The destination peripheral Buffer address.          
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+    uint32_t data, tmp;
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_ALIGN(Alignment)) return HAL_ERROR; 
+
+    /* Calculate and set dual DAC data holding register value */
+    if (Alignment == DAC_ALIGN_12B_L)
+    {
+        data = ((uint32_t)Data2 << 20U) | (Data1<<4);
+    }
+    else
+    {
+        data = ((uint32_t)Data2 << 16U) | Data1;
+    }
+
+    tmp = (uint32_t)hdac->Instance;
+    tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+    /* Set the dual DAC selected data holding register */
+    *(__IO uint32_t *)tmp = data;
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DAC_GetValue
+* Description :	Returns the last data output value of the selected DAC channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:This parameter can be one of the following values:  @arg  DAC_CHANNEL_1   @arg DAC_CHANNEL_2     
+* Output      : The selected DAC channel data output value.
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR; 
+  
+    /* Returns the DAC channel data output register value */
+    if(Channel == DAC_CHANNEL_1)
+    {
+        return hdac->Instance->DOR1;
+    }
+    else
+    {
+        return hdac->Instance->DOR2;
+    }
+
+}
+
+
+/*********************************************************************************
+* Function    : HAL_DACEx_DualGetValue
+* Description :	Return the last data output value of the selected DAC channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.      
+* Output      : The selected DAC channel data output value.
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    uint32_t tmp = 0U;
+
+    tmp |= hdac->Instance->DOR1;
+
+    tmp |= hdac->Instance->DOR2 << 16U;
+
+    /* Returns the DAC channel data output register value */
+    return tmp;
+}
+
+/*********************************************************************************
+* Function    :HAL_DACEx_TriangleWaveGenerate
+* Description :	Enable or disable the selected DAC channel wave generation.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:The selected DAC channel.   This parameter can be one of the following values:
+*                       @arg DAC_CHANNEL_1: DAC Channel1 selected
+*                       @arg DAC_CHANNEL_2: DAC Channel2 selected
+*              Amplitude:  Amplitude Select max triangle amplitude.
+*                          This parameter can be one of the following values:
+*                         @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+*                         @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+*                         @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+*                         @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+*                         @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+*                         @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+*                         @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+*                         @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+*                         @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+*                         @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+*                         @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+*                         @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR;
+    if(!IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)) return HAL_ERROR;
+    /* Enable the triangle wave generation for the selected DAC channel */
+    MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+
+    /* Return function status */
+    return HAL_OK;
+}
+
+
+  
+  /*********************************************************************************
+* Function    : HAL_DACEx_NoiseWaveGenerate
+* Description :	Enable or disable the selected DAC channel wave generation
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:The selected DAC channel.   This parameter can be one of the following values:
+*                       @arg DAC_CHANNEL_1: DAC Channel1 selected
+*                       @arg DAC_CHANNEL_2: DAC Channel2 selected
+*            Amplitude: Amplitude Unmask DAC channel LFSR for noise wave generation.
+*                        This parameter can be one of the following values:
+*                        @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+*                        @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR;
+    if(!IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)) return HAL_ERROR;
+    /* Enable the noise wave generation for the selected DAC channel */
+    MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL), (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+    /* Return function status */
+    return HAL_OK;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_DACEx_SelfCalibrate
+* Description :	SRun the self calibration of one DAC channel.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               sConfig:sConfig DAC channel configuration structure
+*               Channel:The selected DAC channel.   This parameter can be one of the following values:
+*                       @arg DAC_CHANNEL_1: DAC Channel1 selected
+*                       @arg DAC_CHANNEL_2: DAC Channel2 selected
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR;
+
+    HAL_StatusTypeDef status = HAL_OK;
+
+    __IO uint32_t tmp;
+    uint32_t trimmingvalue;
+    uint32_t laststatus=0;
+    uint32_t nowstatus=0;
+    
+    SET_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
+    tmp = (uint32_t)hdac->Instance;
+    if (Channel == DAC_CHANNEL_1)
+    {
+        tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
+    }
+    else
+    {
+        tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
+    }
+
+    *(__IO uint32_t *) tmp = 0x0800U;
+
+    /* Enable the selected DAC channel calibration */
+    /* i.e. set DAC_CR_CENx bit */
+    SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+    /* Init trimming counter */
+    /* Medium value ,trimmingvalue:0-31(0x1f)*/
+    for(trimmingvalue=0;trimmingvalue<32;trimmingvalue++)
+    {
+        /* Set candidate trimming */
+        MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+        System_Delay_MS(1);
+        laststatus=nowstatus;
+        nowstatus=(hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))>>(DAC_SR_CAL_FLAG1_Pos +Channel);
+        /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */
+        /* i.e. minimum time needed between two calibration steps */
+        if (nowstatus==1&&laststatus==0)
+        {
+            break;
+        }
+    }
+    
+    /* Disable the selected DAC channel calibration */
+    /* i.e. clear DAC_CR_CENx bit */
+    CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+    /* Disable the selected DAC channel */
+    CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
+
+    sConfig->DAC_TrimmingValue = trimmingvalue;
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+
+    return status;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_DACEx_SetUserTrimming
+* Description :	Set the trimming mode and trimming value (user trimming mode applied).
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               sConfig:sConfig DAC channel configuration structure
+*               Channel:The selected DAC channel.   This parameter can be one of the following values:
+*                       @arg DAC_CHANNEL_1: DAC Channel1 selected
+*                       @arg DAC_CHANNEL_2: DAC Channel2 selected
+*               NewTrimmingValue: DAC new trimming value
+* Output      : HAL status
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
+{
+    HAL_StatusTypeDef status = HAL_OK;
+
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR;
+    if(!IS_DAC_Calibration_TRIM(NewTrimmingValue)) return HAL_ERROR;
+    
+    /* Check the DAC handle allocation */
+    if (hdac == NULL)
+    {
+        status = HAL_ERROR;
+    }
+    else
+    {
+        /* Set new trimming */
+        MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
+        /* Update trimming mode */
+        sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+        sConfig->DAC_TrimmingValue = NewTrimmingValue;
+    }
+    return status;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_DACEx_GetTrimOffset
+* Description :	Return the DAC trimming value.
+* Input       : hdac : hdac pointer to a DAC_HandleTypeDef structure that contains
+*                     the configuration information for the specified DAC.
+*               Channel:The selected DAC channel.   This parameter can be one of the following values:
+*                       @arg DAC_CHANNEL_1: DAC Channel1 selected
+*                       @arg DAC_CHANNEL_2: DAC Channel2 selected
+* Output      : Trimming value : range: 0->31
+* Author      : CWT                         Data : 2020定
+**********************************************************************************/
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+    /* Check the parameters */
+    if(!IS_DAC_ALL_PERIPH(hdac->Instance)) return HAL_ERROR;
+    if(!IS_DAC_CHANNEL(Channel)) return HAL_ERROR;
+
+    /* Retrieve trimming  */
+    return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_DMA.c

@@ -0,0 +1,422 @@
+/*
+  ******************************************************************************
+  * @file    HAL_DMA.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   DMA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Direct Memory Access (DMA) peripheral:
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/**************** Used in cycle mode ****************/
+static DMA_LLI_InitTypeDef Cycle_Channel[DMA_CHANNEL_NUM];
+
+/*********************************************************************************
+* Function    : HAL_DMA_IRQHandler
+* Description : This function handles DMA interrupt request.
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+__weak void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+    uint32_t lu32_Channel_Index;
+    
+    /* Get DMA Channel number */
+    lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20;
+
+    /* Channel has been interrupted */
+    if (DMA->INT_STATUS & (1 << lu32_Channel_Index))
+    {
+        /* Transfer complete interrupt */
+        if (DMA->INT_TC_STATUS & (1 << lu32_Channel_Index))
+        {
+            DMA->INT_TC_CLR |= (1 << lu32_Channel_Index);
+
+            if (NULL != hdma->DMA_ITC_Callback)
+            {
+                hdma->DMA_ITC_Callback();
+            }
+        }
+        
+        /* Transfer error interrupt */
+        if (DMA->INT_ERR_STATUS & (1 << lu32_Channel_Index))
+        {
+            DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index);
+
+            if (NULL != hdma->DMA_IE_Callback)
+            {
+                hdma->DMA_IE_Callback();
+            }
+        }
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_Init
+* Description : DMA initial with parameters. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) 
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))                 return HAL_ERROR;
+    if (!IS_DMA_DATA_FLOW(hdma->Init.Data_Flow))              return HAL_ERROR;
+    if (!IS_DMA_REQUEST_ID(hdma->Init.Request_ID))            return HAL_ERROR;
+    if (!IS_DMA_SRC_WIDTH(hdma->Init.Source_Width))           return HAL_ERROR;
+    if (!IS_DMA_DST_WIDTH(hdma->Init.Desination_Width))       return HAL_ERROR;
+#endif
+
+    /* Enable DMA Module */
+    System_Module_Enable(EN_DMA);
+    
+    /* Enable External Interrupt */
+    NVIC_ClearPendingIRQ(DMA_IRQn);
+    NVIC_EnableIRQ(DMA_IRQn);
+
+    /* Default Little-Endian、Enable DMA */
+    DMA->CONFIG = DMA_CONFIG_EN;
+
+    /* Clear Channel Config */
+    hdma->Instance->CONFIG = 0x00000000; 
+    
+    if (hdma->Init.Data_Flow == DMA_DATA_FLOW_M2P) 
+    {
+        hdma->Init.Request_ID <<= DMA_CHANNEL_CONFIG_DEST_PERIPH_POS;
+    }
+    else if (hdma->Init.Data_Flow == DMA_DATA_FLOW_P2M) 
+    {
+        hdma->Init.Request_ID <<= DMA_CHANNEL_CONFIG_SRC_PERIPH_POS;
+    }
+
+    hdma->Instance->CONFIG = hdma->Init.Data_Flow | hdma->Init.Request_ID;
+    
+    /* Config Channel Control */
+    hdma->Instance->CTRL = DMA_CHANNEL_CTRL_ITC;
+    /* Source or Desination address increase */
+    hdma->Instance->CTRL |= (hdma->Init.Desination_Inc | hdma->Init.Source_Inc);
+    /* Source or Desination date width */
+    hdma->Instance->CTRL |= (hdma->Init.Desination_Width | hdma->Init.Source_Width);
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_DeInit
+* Description : DMA De-initial with parameters. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) 
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))                 return HAL_ERROR;
+    if (!IS_DMA_DATA_FLOW(hdma->Init.Data_Flow))              return HAL_ERROR;
+    if (!IS_DMA_REQUEST_ID(hdma->Init.Request_ID))            return HAL_ERROR;
+    if (!IS_DMA_SRC_WIDTH(hdma->Init.Source_Width))           return HAL_ERROR;
+    if (!IS_DMA_DST_WIDTH(hdma->Init.Desination_Width))       return HAL_ERROR;
+#endif
+
+    /* Reset DMA Module */
+    System_Module_Reset(RST_DMA);
+    
+    /* Disable DMA Module */
+    System_Module_Disable(EN_DMA);
+    
+    /* Disable Interrupt */
+    NVIC_ClearPendingIRQ(DMA_IRQn);
+    NVIC_DisableIRQ(DMA_IRQn);
+    
+    hdma->DMA_IE_Callback = NULL;
+    hdma->DMA_ITC_Callback = NULL;
+
+    memset(&hdma->Init, 0, sizeof(hdma->Init));
+    
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_NormalMode_Start
+* Description : DMA transfer start. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Input       : fu32_SrcAddr: source address
+* Input       : fu32_DstAddr: desination address
+* Input       : fu32_Size:    transfer size (This parameter can be a 12-bit Size)
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_NormalMode_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))    return HAL_ERROR;
+#endif
+    
+    if (fu32_Size > 0xFFF) 
+    {
+        return HAL_ERROR;
+    }
+
+    /* Set source address and desination address */
+    hdma->Instance->SRC_ADDR  = fu32_SrcAddr;
+    hdma->Instance->DEST_ADDR = fu32_DstAddr;
+
+    /* Set Transfer Size */
+    hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size;
+
+    /* DMA Channel Enable */
+    hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_EN;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_NormalMode_Start_IT
+* Description : DMA transfer start with interrupt. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Input       : fu32_SrcAddr: source address
+* Input       : fu32_DstAddr: desination address
+* Input       : fu32_Size:    transfer size (This parameter can be a 12-bit Size)
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_NormalMode_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))    return HAL_ERROR;
+#endif
+
+    /* Set source address and desination address */
+    hdma->Instance->SRC_ADDR  = fu32_SrcAddr;
+    hdma->Instance->DEST_ADDR = fu32_DstAddr;
+
+    /* Set Transfer Size and enable LLI interrupt */
+    hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size;
+
+    /* DMA Channel Enable and enable transfer error interrupt and transfer complete interrupt*/
+    hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_ITC | DMA_CHANNEL_CONFIG_IE | DMA_CHANNEL_CONFIG_EN;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_CycleMode_Start
+* Description : DMA Cycle transfer start. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Input       : fu32_SrcAddr: source address
+* Input       : fu32_DstAddr: desination address
+* Input       : fu32_Size:    transfer size (This parameter can be a 12-bit Size)
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_CycleMode_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size)
+{
+    uint32_t lu32_Channel_Index;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))    return HAL_ERROR;
+#endif
+
+    /* Get DMA Channel number */
+    lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20;
+    
+    /* Set source address and desination address */
+    hdma->Instance->SRC_ADDR  = fu32_SrcAddr;
+    hdma->Instance->DEST_ADDR = fu32_DstAddr;
+
+    /* Set Next Link */
+    hdma->Instance->LLI = (uint32_t)&Cycle_Channel[lu32_Channel_Index];
+
+    /* Set Transfer Size */
+    hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size;
+
+    /* The list point to oneself */
+    Cycle_Channel[lu32_Channel_Index].SrcAddr = fu32_SrcAddr;
+    Cycle_Channel[lu32_Channel_Index].DstAddr = fu32_DstAddr;
+    Cycle_Channel[lu32_Channel_Index].Next    = &Cycle_Channel[lu32_Channel_Index];
+    Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size;
+
+    /* DMA Channel Enable */
+    hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_EN;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_CycleMode_Start_IT
+* Description : DMA Cycle transfer start with interrupt. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Input       : fu32_SrcAddr: source address
+* Input       : fu32_DstAddr: desination address
+* Input       : fu32_Size:    transfer size (This parameter can be a 12-bit Size)
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_CycleMode_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size)
+{
+    uint32_t lu32_Channel_Index;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))    return HAL_ERROR;
+#endif
+
+    /* Get DMA Channel number */
+    lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20;
+    
+    /* Set source address and desination address */
+    hdma->Instance->SRC_ADDR  = fu32_SrcAddr;
+    hdma->Instance->DEST_ADDR = fu32_DstAddr;
+
+    /* Set Next Link */
+    hdma->Instance->LLI = (uint32_t)&Cycle_Channel[lu32_Channel_Index];
+
+    /* Set Transfer Size */
+    hdma->Instance->CTRL = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size;
+
+    /* The list point to oneself */
+    Cycle_Channel[lu32_Channel_Index].SrcAddr = fu32_SrcAddr;
+    Cycle_Channel[lu32_Channel_Index].DstAddr = fu32_DstAddr;
+    Cycle_Channel[lu32_Channel_Index].Next    = &Cycle_Channel[lu32_Channel_Index];
+    Cycle_Channel[lu32_Channel_Index].Control = (hdma->Instance->CTRL & (~0xFFF)) | fu32_Size;
+
+    /* DMA Channel Enable and enable transfer error interrupt and transfer complete interrupt*/
+    hdma->Instance->CONFIG |= DMA_CHANNEL_CONFIG_ITC | DMA_CHANNEL_CONFIG_IE | DMA_CHANNEL_CONFIG_EN;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_Start
+* Description : DMA transfer start. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Input       : fu32_SrcAddr: source address
+* Input       : fu32_DstAddr: desination address
+* Input       : fu32_Size:    transfer size (This parameter can be a 12-bit Size)
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size)
+{
+    /* Check DMA Parameter */
+    if (!IS_DMA_MODE(hdma->Init.Mode))    return HAL_ERROR;
+        
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+        return HAL_DMA_NormalMode_Start(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size);
+    }
+    else
+    {
+        return HAL_DMA_CycleMode_Start(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size);
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_Start_IT
+* Description : DMA transfer start with interrupt. 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Input       : fu32_SrcAddr: source address
+* Input       : fu32_DstAddr: desination address
+* Input       : fu32_Size:    transfer size (This parameter can be a 12-bit Size)
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t fu32_SrcAddr, uint32_t fu32_DstAddr, uint32_t fu32_Size)
+{
+    /* Check DMA Parameter */
+    if (!IS_DMA_MODE(hdma->Init.Mode))    return HAL_ERROR;
+
+    if (hdma->Init.Mode == DMA_NORMAL)
+    {
+        return HAL_DMA_NormalMode_Start_IT(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size);
+    }
+    else
+    {
+        return HAL_DMA_CycleMode_Start_IT(hdma, fu32_SrcAddr, fu32_DstAddr, fu32_Size);
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_Abort
+* Description : Abort the DMA Transfer 
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+    uint32_t lu32_Channel_Index;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check DMA Parameter */
+    if (!IS_DMA_ALL_INSTANCE(hdma->Instance))    return HAL_ERROR;
+#endif
+
+    /* Get DMA Channel number */
+    lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20;
+
+    /* DMA Channel Disable */
+    hdma->Instance->CONFIG &= ~(1 << 0);
+
+    /* Clear TC ERR Falg */
+    DMA->INT_TC_CLR  |= (1 << lu32_Channel_Index);
+    DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index);
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_DMA_GetState
+* Description : Returns the DMA state..
+* Input       : hdma : pointer to a DMA_HandleTypeDef structure that contains
+*                      the configuration information for DMA module
+* Output      : 
+* Author      :                          Data : 2021
+**********************************************************************************/
+HAL_StatusTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+    uint32_t lu32_Channel_Index;
+    HAL_StatusTypeDef States = HAL_ERROR;
+    
+    /* Get DMA Channel number */
+    lu32_Channel_Index = ((uint32_t)(hdma->Instance) - (uint32_t)(DMA_Channel0)) / 0x20;
+
+    /* Transfer complete interrupt */
+    if (DMA->RAW_INT_TC_STATUS & (1 << lu32_Channel_Index))
+    {
+        DMA->INT_TC_CLR |= (1 << lu32_Channel_Index);
+
+        States = HAL_OK;
+    }
+    
+    /* Transfer error interrupt */
+    if (DMA->RAW_INT_ERR_STATUS & (1 << lu32_Channel_Index))
+    {
+        DMA->INT_ERR_CLR |= (1 << lu32_Channel_Index);
+
+        States = HAL_ERROR;
+    }
+    
+    return States;
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EFlash.c

@@ -0,0 +1,114 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EFlash.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   EFlash HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           @ Program operations functions
+  *           @ Erase   operations functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_EFlash_Init
+* Description : Configure eflash parameter as system clock 
+* Input       : system clock frequency 
+* Output      : None
+* Author      : Chris_Kyle                      
+**********************************************************************************/
+void HAL_EFlash_Init(uint32_t fu32_freq)
+{
+    HAL_EFlash_Init_Para(fu32_freq);     
+} 
+
+#if (__ACCELERATE_EH_PRESENT == 0)    
+/*********************************************************************************
+* Function    : HAL_EFlash_Erase_Page
+* Description : Erase a Page, TERASE has been configured in System_Clock_Init()
+* Input       : 
+* Output      : false: FAIL
+                true:  SUCCESS
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr)
+{
+    EFC->CTRL |= EFC_CTRL_PAGE_ERASE_MODE;
+    
+    EFC->SEC = 0x55AAAA55;
+
+    *((volatile uint32_t *)fu32_Addr) = 0;
+    
+    while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY));
+    
+    EFC->CTRL &= ~EFC_CTRL_PAGE_ERASE_MODE;
+
+    return true;
+}
+
+/*********************************************************************************
+* Function    : HAL_EFlash_Programe
+* Description : Program a word, TPROG has been configured in System_Clock_Init()
+* Input       : 
+* Output      : false: FAIL
+                true:  SUCCESS
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data)
+{
+    if (fu32_Addr % 4)
+    {
+        return false; 
+    }
+
+    EFC->CTRL |= EFC_CTRL_PROGRAM_MODE;
+
+    EFC->SEC = 0x55AAAA55;
+
+    *((volatile uint32_t *)fu32_Addr) = fu32_Data;
+
+    while (!(EFC->STATUS & EFC_STATUS_EFLASH_RDY));
+
+    EFC->CTRL &= ~EFC_CTRL_PROGRAM_MODE;
+    
+    return true;
+}
+#else
+/*********************************************************************************
+* Function    : HAL_EFlash_Erase_Page
+* Description : Erase a Page, TERASE has been configured in System_Clock_Init()
+* Input       : 
+* Output      : false: FAIL
+                true:  SUCCESS
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+bool HAL_EFlash_ErasePage(uint32_t fu32_Addr)
+{
+    HAL_EFlash_ErasePage_EX(fu32_Addr);    
+
+    return true;
+}
+
+/*********************************************************************************
+* Function    : HAL_EFlash_Programe
+* Description : Program a word, TPROG has been configured in System_Clock_Init()
+* Input       : 
+* Output      : false: FAIL
+                true:  SUCCESS
+* Author      : Chris_Kyle                         
+**********************************************************************************/
+bool HAL_EFlash_Program_Word(uint32_t fu32_Addr, uint32_t fu32_Data)
+{
+    if (fu32_Addr % 4)
+    {
+        return false; 
+    }
+
+    HAL_EFlash_Program_Word_EX(fu32_Addr, fu32_Data);     
+    
+    return true;
+} 
+
+#endif

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_EXTI.c

@@ -0,0 +1,184 @@
+/*
+  ******************************************************************************
+  * @file    HAL_EXTI.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   EXTI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (EXTI) peripheral:
+  *           + Initialization functions
+  *           + IO operation functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_EXTI_IRQHandler
+* Description : Handle EXTI interrupt request.
+* Input       : huart: EXTI handle.
+* Output      : 
+* Author      : Chris_Kyle                         Data : 2020��
+**********************************************************************************/ 
+void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti)
+{
+    if (EXTI->PDR & hexti->u32_Line) 
+    {
+        EXTI->PDR = hexti->u32_Line;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_SetConfigLine
+* Description : 
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti)
+{
+    uint32_t lu32_IndexLine;
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))      return HAL_ERROR;
+    if (!IS_EXTI_MODE(hexti->u32_Mode))          return HAL_ERROR;
+    if (!IS_EXTI_TRIGGER(hexti->u32_Trigger))    return HAL_ERROR;
+    
+    /* Line0 ~ 15 trigger from GPIO */
+    if (!(hexti->u32_Line >> 16))
+    {
+        if (!IS_EXTI_GPIOSEL(hexti->u32_GPIOSel))    return HAL_ERROR;
+    }
+#endif
+
+    lu32_IndexLine = hexti->u32_Line;
+    
+    /* Interrupt Mode */
+    if (hexti->u32_Mode == EXTI_MODE_INTERRUPT)
+    {
+        EXTI->IENR |=  lu32_IndexLine;
+        EXTI->EENR &= ~lu32_IndexLine;
+
+        NVIC_ClearPendingIRQ(EXTI_IRQn);
+        NVIC_EnableIRQ(EXTI_IRQn);
+    }
+    /* Event Mode */
+    else if (hexti->u32_Mode == EXTI_MODE_EVENT)
+    {
+        EXTI->EENR |=  lu32_IndexLine;
+        EXTI->IENR &= ~lu32_IndexLine;
+    }
+
+
+    if (hexti->u32_Trigger == EXTI_TRIGGER_RISING) 
+    {
+        EXTI->RTENR |=  lu32_IndexLine;
+        EXTI->FTENR &= ~lu32_IndexLine;
+    }
+    else if (hexti->u32_Trigger == EXTI_TRIGGER_FALLING)
+    {
+        EXTI->FTENR |=  lu32_IndexLine;
+        EXTI->RTENR &= ~lu32_IndexLine;
+    }
+    else 
+    {
+        EXTI->FTENR |= lu32_IndexLine;
+        EXTI->RTENR |= lu32_IndexLine;
+    }
+    
+    /* Line0 ~ 15 trigger from GPIO */
+    if (!(hexti->u32_Line >> 16))
+    {
+        lu32_IndexLine = 0;
+        
+        while(hexti->u32_Line >> lu32_IndexLine != 0x01)
+        {
+            lu32_IndexLine++;
+        }
+        
+        /* Line0 ~ 7 */
+        if (lu32_IndexLine < 8) 
+        {
+            EXTI->EXTICR1 = (EXTI->EXTICR1 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4);
+        }
+        /* Line8 ~ 15 */
+        else 
+        {
+            lu32_IndexLine -= 8;
+            
+            EXTI->EXTICR2 = (EXTI->EXTICR2 & ~(0x0F << (lu32_IndexLine * 4))) | hexti->u32_GPIOSel << (lu32_IndexLine * 4);
+        }
+    }
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_SoftTrigger
+* Description : Software trigger EXTI
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+void HAL_EXTI_SoftTrigger(EXTI_HandleTypeDef *hexti)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))    return;
+#endif
+
+    /* Set pending BIT */
+    EXTI->SWIER |= hexti->u32_Line;
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_GetPending
+* Description : Get interrupt pending bit of a dedicated line.
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+bool HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))    return HAL_ERROR;
+#endif
+
+    if (hexti->u32_Line & EXTI->PDR) 
+    {
+        return true;
+    }
+    else 
+    {
+        return false;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_EXTI_ClearPending
+* Description : Clear interrupt pending bit of a dedicated line.
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020年
+**********************************************************************************/
+void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_EXTI_ALL_LINE(hexti->u32_Line))    return;
+#endif
+
+    /* Clear pending status */
+    EXTI->PDR |= hexti->u32_Line;
+}  
+
+/*********************************************************************************
+* Function    : HAL_EXTI_ClearAllPending  
+* Description : Clear all interrupt pending bit.  
+* Input       : 
+* Outpu       : 
+* Author      : xwl                         Data : 2021年
+**********************************************************************************/
+void HAL_EXTI_ClearAllPending(void)
+{
+    /* Clear pending status */
+    EXTI->PDR |= EXTI_LINE_MASK;   
+}
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_FSUSB.c

@@ -0,0 +1,372 @@
+/***********************************************************************
+ * Filename    : hal_lpuart.c
+ * Description : lpuart driver source file
+ * Author(s)   : xwl  
+ * version     : V1.0
+ * Modify date : 2019-11-19
+ ***********************************************************************/
+#include "ACM32Fxx_HAL.h"  
+
+static uint16_t ep1_stall[2]= {0};    // EP1 stall状态
+static uint16_t ep2_stall[2]= {0};    // EP2 stall状态
+static uint16_t ep3_stall[2]= {0};    // EP3 stall状态
+static uint16_t ep4_stall[2]= {0};    // EP3 stall状态     
+
+uint32_t HAL_FSUSB_MSP_Init(void)  
+{
+    GPIO_InitTypeDef    GPIO_init_para;  
+
+    System_Module_Reset(RST_USB); 
+    System_Module_Enable(EN_USB);  
+           
+    if( HAL_OK != System_USB_PHY_Config())
+    {
+        return HAL_ERROR;    
+    } 
+    
+    SCU->PABADS = (SCU->PABADS | ( (0x3 << 11)) );       
+//    GPIO_init_para.Pin       = GPIO_PIN_11 | GPIO_PIN_12;
+//    GPIO_init_para.Mode      = GPIO_MODE_ANALOG;
+//    GPIO_init_para.Pull      = GPIO_NOPULL;
+//    GPIO_init_para.Alternate = GPIO_FUNCTION_0; 
+//    HAL_GPIO_Init(GPIOA, &GPIO_init_para);  
+    
+    NVIC_ClearPendingIRQ(USB_IRQn);  
+	NVIC_EnableIRQ(USB_IRQn); 
+    
+    return HAL_OK;    
+}   
+
+uint32_t HAL_FSUSB_Init(void)  
+{
+    if (HAL_OK != HAL_FSUSB_MSP_Init())
+    {
+       return HAL_ERROR;    
+    }
+    
+    System_Delay(10);    
+    
+    USBCTRL->WORKING_MODE = 0x04;  //disconnect usb/ reset USBC    
+	System_Delay(3000);   
+	USBCTRL->WORKING_MODE = 0x09 ;  //auto reset, fullspeed  
+    
+    USBCTRL->EPxCSR[0] |= 1<<8;	//enable EP0  
+    USBCTRL->EPxCSR[1] |= 1<<8;	//enable EP1  
+    USBCTRL->EPxCSR[2] |= 1<<8;	//enable EP2  
+    USBCTRL->EPxCSR[3] |= 1<<8;	//enable EP3  
+    USBCTRL->EPxCSR[4] |= 1<<8;	//enable EP4  
+    USBCTRL->EPADDR_CFG = 0x4321;  
+    
+    USBINT->INT_EN = 0x92427;   // enable Reset,Resume,Suspend,setup, EP1/2/3/4 OUT interrupt	  
+     
+	USBCTRL->WORKING_MODE  |= (1<<6)|(1<<4);	//connect   
+    
+    return HAL_OK;   
+}  
+
+uint16_t HAL_FSUSB_Get_FIFO_Length(uint8_t ep_index)
+{
+	return USBCTRL->EPxCSR[ep_index]&0xff;             	
+}
+
+void HAL_USB_Clear_FIFO(uint8_t ep_index, uint8_t ep_dir)  
+{
+	USBCTRL->EPxCSR[ep_index] |= 1<<9;	  
+} 
+
+uint16_t HAL_USB_Get_Stall_Status(uint8_t ep_index, uint8_t ep_dir) 
+{
+	switch(ep_index)
+	{
+		case USB_EP1: 
+		{    
+			if(ep_dir == EP_DIR_IN)		return ep1_stall[0];	  //in
+			else			  			return ep1_stall[1];	  //out	    
+		}
+		case USB_EP2: 
+		{    
+			if(ep_dir == EP_DIR_IN)		return ep2_stall[0];	  //in
+			else			  			return ep2_stall[1];	  //out	    
+		}
+		case USB_EP3: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	return ep3_stall[0];	  //in
+			else			  			return ep3_stall[1];	  //out	    
+		}
+		case USB_EP4: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	return ep4_stall[0];	  //in
+			else			  			return ep4_stall[1];	  //out	    
+		}
+
+		default:    	 	  return 0xff;
+	}	
+}
+
+void usb_clear_stall(uint8_t ep_index, uint8_t ep_dir)
+{
+	switch(ep_index)
+	{
+		case USB_EP1: 
+		{    
+			if(ep_dir == EP_DIR_IN)	 	ep1_stall[0]=0x0000;	  //in
+			else			  			ep1_stall[1]=0x0000;	  //out	
+			break;  
+		}
+		case USB_EP2: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	ep2_stall[0]=0x0000;	  //in
+			else			  			ep2_stall[1]=0x0000;	  //out				  
+			break;   
+		}
+		case USB_EP3: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	ep3_stall[0]=0x0000;	  //in
+			else			  			ep3_stall[1]=0x0000;	  //out		  
+			break;   
+		}
+		case USB_EP4: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	ep4_stall[0]=0x0000;	  //in
+			else			  			ep4_stall[1]=0x0000;	  //out					  
+			break;    
+		}
+
+		default: return;
+	}
+
+	USBCTRL->EPxCSR[ep_index] = 0x02100;		   //clear in/out toggle,stall,stall status
+	USBCTRL->EPxCSR[ep_index] |= (1<<18)|(1<<15);  //enable change
+//	flag_clear_stall=0;  		 
+}
+
+
+
+void usb_send_stall(uint8_t ep_index, uint8_t ep_dir)
+{
+	switch(ep_index)
+	{
+		case USB_EP1: 
+		{    
+			if(ep_dir == EP_DIR_IN)	 	ep1_stall[0]=0x0001;	  //in
+			else			  			ep1_stall[1]=0x0001;	  //out	
+			break;  
+		}
+		case USB_EP2: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	ep2_stall[0]=0x0001;	  //in
+			else			  			ep2_stall[1]=0x0001;	  //out				  
+			break;   
+		}
+		case USB_EP3: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	ep3_stall[0]=0x0001;	  //in
+			else			  			ep3_stall[1]=0x0001;	  //out		  
+			break;   
+		}
+		case USB_EP4: 
+		{    
+			if(ep_dir == EP_DIR_IN)	  	ep4_stall[0]=0x0001;	  //in
+			else			  			ep4_stall[1]=0x0001;	  //out					  
+			break;    
+		}
+
+		default: return;
+	}
+
+	USBCTRL->EPxCSR[ep_index] |= (1<<12);    
+}
+
+
+void HAL_FSUSB_Read_EP_MEM8(uint8_t *dst, uint32_t length, uint32_t fifo_offset, uint8_t ep_index)
+{
+	uint8_t *src;
+
+	src = (uint8_t *)(USB_BASE+0x200+(ep_index<<6)+fifo_offset);       
+	while(length--)
+	{
+		*dst++ = *src++;
+	}		 
+}
+ 
+void HAL_FSUSB_Write_EP_MEM8(uint8_t *src, uint32_t length, uint32_t fifo_offset, uint8_t ep_index)
+{
+
+	uint8_t *dst;
+
+	dst = (uint8_t *)(USB_BASE+0x200+(ep_index<<6)+fifo_offset); 
+
+	while(length--)
+	{
+		*dst++ = *src++;
+	}
+}
+
+
+uint8_t HAL_FSUSB_Start_EP_Transfer(uint32_t length,uint8_t ep_index)
+{
+	uint8_t intoken_cnt;
+	
+	USBCTRL->EPxSENDBN[ep_index]= length;
+	
+	while(1)
+	{
+		// if a new out data packet received, return error to caller  
+	    if( (USBINT->INT_STAT_RAW & MASK_EPX_OUT(ep_index)) && (USBINT->INT_STAT_RAW & MASK_EPX_ACK(ep_index)) )
+		{
+		    USBINT->INT_CLR  = MASK_EPX_OUT(ep_index);	
+	        USBINT->INT_CLR  = MASK_EPX_ACK(ep_index);
+			return ERROR_OUT_OUT;
+		}
+		// wait for IN token to start transfer 
+        if(USBINT->INT_STAT_RAW & MASK_EPX_IN(ep_index) )
+        {
+		    USBINT->INT_CLR  = MASK_EPX_IN(ep_index);
+			USBCTRL->WORKING_MODE  |= (1<<11);//return NAK when timeout
+			USBCTRL->EPxCSR[ep_index] |= (1<<10);//data is ready for tx
+			break;
+        }			
+	}
+	
+
+	while(1)
+	{
+		if( USBCTRL->EPxCSR[ep_index]&0x1000000 ) //received ACK from host 
+		{
+			USBINT->INT_CLR  = MASK_EPX_ACK(ep_index);
+			USBINT->INT_CLR  = MASK_EPX_IN(ep_index);
+			return 0;//pass
+		}
+		
+		if(USBINT->INT_STAT_RAW & (1<<21) ) // timeout occurs when wait ACK 
+		{
+            USBINT->INT_CLR  = (1<<21);
+			intoken_cnt = 4;
+			while(intoken_cnt) // wait 3 SOF frame for bad signal, during this time, device will send NACK when IN token received  
+			{               
+                if(USBINT->INT_STAT_RAW & (1<<3))				
+				{
+				    intoken_cnt --;
+					USBINT->INT_CLR  = (1<<3);
+				}
+			}
+			USBINT->INT_CLR  = MASK_EPX_TIMEOUT(ep_index); // device recover to send data packet after IN token received  		
+		}	
+		
+		if(USBINT->INT_STAT_RAW & MASK_EPX_OUT(ep_index))
+		{
+			return ERROR_IN_OUT; 
+		}		
+	}	
+}
+
+   
+uint8_t HAL_FSUSB_Send_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index)
+{
+	uint8_t ret;
+	
+	while(length>=EPX_MAX_PACKET_SIZE)
+	{    		
+		HAL_FSUSB_Write_EP_MEM8(buffer,EPX_MAX_PACKET_SIZE,0, ep_index);  		   
+		ret = HAL_FSUSB_Start_EP_Transfer(EPX_MAX_PACKET_SIZE, ep_index);
+		if(ret == ERROR_OUT_OUT)
+		{
+		    if( USBCTRL->EPxCSR[ep_index] & ( 1<< 19) )//Toggle error
+		    {
+		        USBCTRL->EPxCSR[ep_index] ^= (1<<17);  //out toggle want
+			    USBCTRL->EPxCSR[ep_index] |= (1<<18);  //update want toggle;			 			             			
+		    }
+			USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready  	
+            continue;	// received a same packet, has processed this packet, just fill respoonse to fifo and send it to host 		
+		}
+		else if(ret != 0)
+		{
+			return 1; // send data fail, exit with error code to let caller know 
+		}
+	 	length -= EPX_MAX_PACKET_SIZE;
+	  	buffer += EPX_MAX_PACKET_SIZE;		
+	}
+	// remaining data, less than EPX_MAX_PACKET_SIZE  
+	while(length>0)  
+	{
+		HAL_FSUSB_Write_EP_MEM8(buffer,length,0,ep_index);  	     
+		ret = HAL_FSUSB_Start_EP_Transfer(length,ep_index);
+		if(ret == ERROR_OUT_OUT)
+		{
+		    if( USBCTRL->EPxCSR[ep_index] & ( 1<< 19) )//Toggle error
+		    {
+		        USBCTRL->EPxCSR[ep_index] ^= (1<<17); //out toggle want
+			    USBCTRL->EPxCSR[ep_index] |= (1<<18); //update want toggle;			 			             			
+		    }
+			USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready  
+            continue;				
+		}
+		else if(ret != 0)
+		{
+			return 1; // send data fail, exit with error code to let caller know   
+		}
+	 	length -= length;
+	  	buffer += length;
+	}
+	
+	return 0;  
+}
+
+
+void HAL_FSUSB_Receive_Data(uint8_t *buffer,uint32_t length,uint8_t ep_index)  
+{
+	uint32_t len;
+
+	while(length>0)	
+	{			
+		while(1)
+		{
+			// wait an out data packet and device has sent an ACK to HOST  
+			if( (USBINT->INT_STAT_RAW & MASK_EPX_OUT(ep_index)) && (USBINT->INT_STAT_RAW & MASK_EPX_ACK(ep_index)) )
+			{
+				break;
+			}
+		}		
+		USBINT->INT_CLR  = MASK_EPX_OUT(ep_index);	
+	    USBINT->INT_CLR  = MASK_EPX_ACK(ep_index);		
+		
+		if( USBCTRL->EPxCSR[ep_index] & ( 1<< 19) )//Toggle error 
+		{
+		    USBCTRL->EPxCSR[ep_index] ^= (1<<17); //out toggle want
+			USBCTRL->EPxCSR[ep_index] |= (1<<18); //update want toggle; 
+			USBCTRL->EPxCSR[ep_index] |= 1<<11;   //set rx ready, wait for a new packet 
+			continue;  //discard this packet          			
+		}		
+	
+		len	=HAL_FSUSB_Get_FIFO_Length(ep_index);
+		HAL_FSUSB_Read_EP_MEM8(buffer,len,0,ep_index);	
+		USBCTRL->EPxCSR[ep_index] |= 1<<11; //set rx ready to wait next packet 
+
+		length -= len;
+		buffer += len;
+	}		
+} 
+
+
+//ep_index表示端点编号
+void HAL_FSUSB_EP0_Send_Empty_Packet(void)
+{
+	HAL_FSUSB_Start_EP_Transfer(0,USB_EP0);    
+} 
+  
+void HAL_FSUSB_EP0_Send_Stall(void)
+{
+	USBCTRL->EPxCSR[0] |= 1<<12;
+	while(!(USBCTRL->EPxCSR[0] &0x2000));
+	USBCTRL->EPxCSR[0] |= 0x2000;    
+}         
+
+
+
+
+
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_GPIO.c

@@ -0,0 +1,703 @@
+/*
+  ******************************************************************************
+  * @file    HAL_GPIO.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           @ Initialization  functions
+  *           @ IO operation functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_GPIO_IRQHandler
+* Description : GPIO interrupt Handler
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020?¨º
+**********************************************************************************/
+void HAL_GPIO_IRQHandler(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin)
+{
+    GPIO_TypeDef *GPIOx;
+    
+    switch (fe_GPIO)
+    {
+        case GPIOA: 
+        case GPIOB: 
+        {
+            GPIOx = GPIOAB;
+        }break;
+
+        case GPIOC: 
+        case GPIOD: 
+        {
+            GPIOx = GPIOCD;
+        }break;
+
+        case GPIOE: 
+        case GPIOF: 
+        {
+            GPIOx = GPIOEF;
+        }break;
+
+        default: break;
+    }
+
+    if (fe_GPIO == GPIOB || fe_GPIO == GPIOD || fe_GPIO == GPIOF)
+    {
+        fu32_GPIO_Pin <<= 16;
+    }
+
+    if (GPIOx->RIS & fu32_GPIO_Pin) 
+    {   
+        GPIOx->IC = fu32_GPIO_Pin;
+        
+        /* user can call your application process function here */ 
+        /* ...... */
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_GPIO_Init
+* Description : Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init
+* Input       : fe_GPIO: to select the GPIO peripheral.
+* Input       : GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+                           the configuration information for the specified GPIO peripheral.
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020?¨º
+**********************************************************************************/
+void HAL_GPIO_Init(enum_GPIOx_t fe_GPIO, GPIO_InitTypeDef *GPIO_Init)
+{
+    uint32_t lu32_Position = 0;
+    uint32_t lu32_Current_Pin;
+    uint32_t lu32_Position_Mask;
+    
+    volatile uint32_t *lu32_SEL1 = NULL;        // ???¨° -> 1¨¹???¡ä¨®???¡ä??¡Â1
+    volatile uint32_t *lu32_SEL2 = NULL;        // ???¨° -> 1¨¹???¡ä¨®???¡ä??¡Â2
+    volatile uint32_t *lu32_PollUP   = NULL;    // ???¨° -> ¨¦?¨¤-??????¡ä??¡Â
+    volatile uint32_t *lu32_PollDown = NULL;    // ???¨° -> ??¨¤-??????¡ä??¡Â
+    volatile uint32_t *lu32_ODEnable = NULL;    // ???¨° -> ?a??¨º1?¨¹??¡ä??¡Â
+    volatile uint32_t *lu32_ADS      = NULL;    // ???¨° -> ¨ºy¡Á??¡é?¡ê?a??????¡ä??¡Â
+    
+    GPIO_TypeDef *GPIOx;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check the parameters */
+    if (!IS_GPIO_ALL_INSTANCE(fe_GPIO))             return;
+    if (!IS_GPIO_PIN(GPIO_Init->Pin))               return;
+    if (!IS_GPIO_MODE(GPIO_Init->Mode))             return;   
+#endif
+
+    switch (fe_GPIO)
+    {
+        case GPIOA: 
+        case GPIOB: 
+        {
+            GPIOx = GPIOAB;
+            
+            System_Module_Enable(EN_GPIOAB);
+            
+            lu32_PollUP   = &(SCU->PABPUR);
+            lu32_PollDown = &(SCU->PABPDR);
+            lu32_ODEnable = &(SCU->PABODR);
+            lu32_ADS      = &(SCU->PABADS);
+            
+            if (fe_GPIO == GPIOB) 
+            {
+                GPIO_Init->Pin <<= 16;
+                
+                lu32_SEL1 = &(SCU->PBSEL1);
+                lu32_SEL2 = &(SCU->PBSEL2);
+            }
+            else 
+            {
+                lu32_SEL1 = &(SCU->PASEL1);
+                lu32_SEL2 = &(SCU->PASEL2);
+            }
+        }break;
+
+        case GPIOC: 
+        case GPIOD: 
+        {
+            GPIOx = GPIOCD;
+            
+            System_Module_Enable(EN_GPIOCD);
+
+            lu32_PollUP   = &(SCU->PCDPUR);
+            lu32_PollDown = &(SCU->PCDPDR);
+            lu32_ODEnable = &(SCU->PCDODR);
+            lu32_ADS      = &(SCU->PCDADS);
+            
+            if (fe_GPIO == GPIOD) 
+            {
+                GPIO_Init->Pin <<= 16;
+                
+                lu32_SEL1 = &(SCU->PDSEL1);
+                lu32_SEL2 = &(SCU->PDSEL2);
+            }
+            else 
+            {
+                lu32_SEL1 = &(SCU->PCSEL1);
+                lu32_SEL2 = &(SCU->PCSEL2);
+            }
+        }break;
+
+        case GPIOE: 
+        case GPIOF: 
+        {
+            GPIOx = GPIOEF;
+            
+            System_Module_Enable(EN_GPIOEF);
+
+            lu32_PollUP   = &(SCU->PEFPUR);
+            lu32_PollDown = &(SCU->PEFPDR);
+            lu32_ODEnable = &(SCU->PEFODR);
+            lu32_ADS      = &(SCU->PEFADS);
+            
+            if (fe_GPIO == GPIOF) 
+            {
+                GPIO_Init->Pin <<= 16;
+                
+                lu32_SEL1 = &(SCU->PFSEL1);
+            }
+            else 
+            {
+                lu32_SEL1 = &(SCU->PESEL1);
+                lu32_SEL2 = &(SCU->PESEL2);
+            }
+        }break;
+
+        default: break; 
+    }
+
+    /* Configure Select pins */
+    while ((GPIO_Init->Pin) >> lu32_Position != 0) 
+    {
+        /* Get current pin position */
+        lu32_Current_Pin = (GPIO_Init->Pin) & (1uL << lu32_Position);
+        
+        if (lu32_Current_Pin) 
+        {
+            switch (GPIO_Init->Mode)
+            {
+                /* GPIO IN Function */
+                case GPIO_MODE_INPUT:
+                {
+                    GPIOx->DIR &= ~lu32_Current_Pin;
+                }break;
+                
+                /* GPIO OUT Function */
+                case GPIO_MODE_OUTPUT_PP: 
+                case GPIO_MODE_OUTPUT_OD: 
+                {
+                    GPIOx->DIR |= lu32_Current_Pin;
+                }break;
+
+                /* Alternate Function */
+                case GPIO_MODE_AF_PP:
+                case GPIO_MODE_AF_OD:
+                {
+                    /* Get Position Mask */
+                    if (lu32_Position < 16) 
+                    {   /* GOIOA?¡éGPIOC?¡éGPIOE */
+                        lu32_Position_Mask = lu32_Position;
+                    }
+                    else 
+                    {   /* GPIOB?¡éGPIOD?¡éGPIOF */
+                        lu32_Position_Mask = lu32_Position - 16;
+                    }
+                    
+                    /* SET GPIO Function */
+                    if (lu32_Position_Mask < 8) 
+                    {
+                        *lu32_SEL1 = (*lu32_SEL1 & ~(0xF << (lu32_Position_Mask * 4))) | (GPIO_Init->Alternate << (lu32_Position_Mask * 4));
+                    }
+                    else 
+                    {
+                        *lu32_SEL2 = (*lu32_SEL2 & ~(0xF << ((lu32_Position_Mask - 8) * 4))) | (GPIO_Init->Alternate << ((lu32_Position_Mask - 8) * 4));
+                    }
+                }break;
+
+                /* GPIO INT Function */
+                case GPIO_MODE_IT_RISING:
+                case GPIO_MODE_IT_FALLING:
+                case GPIO_MODE_IT_RISING_FALLING:
+                case GPIO_MODE_IT_HIGH_LEVEL:
+                case GPIO_MODE_IT_LOW_LEVEL:
+                {
+                    /* Set direction Input?¡éEnable INT */
+                    GPIOx->DIR &= ~lu32_Current_Pin;
+                    GPIOx->IEN |=  lu32_Current_Pin;
+
+                    /* Single edge */
+                    if (GPIO_Init->Mode == GPIO_MODE_IT_RISING || GPIO_Init->Mode == GPIO_MODE_IT_FALLING) 
+                    {
+                        /* edge trigger */
+                        GPIOx->IS  &= ~lu32_Current_Pin;
+                        /* Single trigger */
+                        GPIOx->IBE &= ~lu32_Current_Pin;
+                        
+                        if (GPIO_Init->Mode == GPIO_MODE_IT_RISING) 
+                        {
+                            GPIOx->IEV |= lu32_Current_Pin;
+                        }
+                        else 
+                        {
+                            GPIOx->IEV &= ~lu32_Current_Pin;
+                        }
+                    }
+
+                    /* Double edge */
+                    if (GPIO_Init->Mode == GPIO_MODE_IT_RISING_FALLING) 
+                    {
+                        /* edge trigger */
+                        GPIOx->IS  &= ~lu32_Current_Pin;
+                        /* Double trigger */
+                        GPIOx->IBE |=  lu32_Current_Pin;
+                    }
+                    
+                    /* LEVEL trigger */
+                    if (GPIO_Init->Mode == GPIO_MODE_IT_HIGH_LEVEL || GPIO_Init->Mode == GPIO_MODE_IT_LOW_LEVEL) 
+                    {
+                        /* LEVEL trigger */
+                        GPIOx->IS |= lu32_Current_Pin;
+
+                        if (GPIO_Init->Mode == GPIO_MODE_IT_HIGH_LEVEL) 
+                        {
+                            GPIOx->IEV |= lu32_Current_Pin;
+                        }
+                        else 
+                        {
+                            GPIOx->IEV &= ~lu32_Current_Pin;
+                        }
+                    }
+                }break;
+
+                default: break; 
+            }
+
+            /* Set Pull UP or DOWN or NO */
+            if (GPIO_Init->Pull == GPIO_NOPULL) 
+            {
+                *lu32_PollUP   &= ~lu32_Current_Pin;
+                *lu32_PollDown &= ~lu32_Current_Pin;
+            }
+            else if (GPIO_Init->Pull == GPIO_PULLUP) 
+            {
+                *lu32_PollUP   |=  lu32_Current_Pin;
+                *lu32_PollDown &= ~lu32_Current_Pin;
+            }
+            else if (GPIO_Init->Pull == GPIO_PULLDOWN) 
+            {
+                *lu32_PollUP   &= ~lu32_Current_Pin;
+                *lu32_PollDown |=  lu32_Current_Pin;
+            }
+
+            /* Set Open Drain Mode */
+            if (GPIO_Init->Mode & GPIO_MODE_OD_MASK) 
+            {
+                *lu32_ODEnable |= lu32_Current_Pin;
+            }
+            else 
+            {
+                *lu32_ODEnable &= ~lu32_Current_Pin;
+            }
+            
+            /* GPIO Function */
+            if (GPIO_Init->Mode & GPIO_MODE_IO_MASK) 
+            {
+                /* Get Position Mask */
+                if (lu32_Position < 16) 
+                {   /* GOIOA?¡éGPIOC?¡éGPIOE */
+                    lu32_Position_Mask = lu32_Position;
+                }
+                else 
+                {   /* GPIOB?¡éGPIOD?¡éGPIOF */
+                    lu32_Position_Mask = lu32_Position - 16;
+                }
+                
+                /* SET GPIO Function */
+                if (lu32_Position_Mask < 8) 
+                {
+                    *lu32_SEL1 = (*lu32_SEL1 & ~(0xF << (lu32_Position_Mask * 4))) | (GPIO_FUNCTION_0 << (lu32_Position_Mask * 4));
+                }
+                else 
+                {
+                    *lu32_SEL2 = (*lu32_SEL2 & ~(0xF << ((lu32_Position_Mask - 8) * 4))) | (GPIO_FUNCTION_0 << ((lu32_Position_Mask - 8) * 4));
+                }
+            }
+
+            /* SET Digital or Analog */
+            if (GPIO_Init->Mode == GPIO_MODE_ANALOG) 
+            {
+                *lu32_ADS |= lu32_Current_Pin;
+            }
+            else 
+            {
+                *lu32_ADS &= ~lu32_Current_Pin;
+            }
+        }
+
+        lu32_Position++;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_GPIO_DeInit
+* Description : De-initializes the GPIOx peripheral registers to their default reset values.
+* Input       : fe_GPIO¡êoto select the GPIO peripheral.
+* Input       : fu32_Pin¡êospecifies the port bit to be written.
+                This parameter can be one of GPIO_PIN_x where x can be (0..15).
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+void HAL_GPIO_DeInit(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin)
+{
+    uint32_t lu32_Position = 0;
+    uint32_t lu32_Current_Pin;
+    uint32_t lu32_Position_Mask;
+    
+    volatile uint32_t *lu32_SEL1 = NULL;        // ???¨° -> 1¨¹???¡ä¨®???¡ä??¡Â1
+    volatile uint32_t *lu32_SEL2 = NULL;        // ???¨° -> 1¨¹???¡ä¨®???¡ä??¡Â2
+    volatile uint32_t *lu32_PollUP   = NULL;    // ???¨° -> ¨¦?¨¤-??????¡ä??¡Â
+    volatile uint32_t *lu32_PollDown = NULL;    // ???¨° -> ??¨¤-??????¡ä??¡Â
+    volatile uint32_t *lu32_ODEnable = NULL;    // ???¨° -> ?a??¨º1?¨¹??¡ä??¡Â
+    volatile uint32_t *lu32_ADS      = NULL;    // ???¨° -> ¨ºy¡Á??¡é?¡ê?a??????¡ä??¡Â
+    
+    GPIO_TypeDef *GPIOx;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check the parameters */
+    if (!IS_GPIO_ALL_INSTANCE(fe_GPIO))    return;
+    if (!IS_GPIO_PIN(fu32_Pin))            return;
+#endif
+
+    switch (fe_GPIO)
+    {
+        case GPIOA: 
+        case GPIOB: 
+        {
+            GPIOx = GPIOAB;
+            
+            System_Module_Enable(EN_GPIOAB);
+            
+            lu32_PollUP   = &(SCU->PABPUR);
+            lu32_PollDown = &(SCU->PABPDR);
+            lu32_ODEnable = &(SCU->PABODR);
+            lu32_ADS      = &(SCU->PABADS);
+            
+            if (fe_GPIO == GPIOB) 
+            {
+                fu32_Pin <<= 16;
+                
+                lu32_SEL1 = &(SCU->PBSEL1);
+                lu32_SEL2 = &(SCU->PBSEL2);
+            }
+            else 
+            {
+                lu32_SEL1 = &(SCU->PASEL1);
+                lu32_SEL2 = &(SCU->PASEL2);
+            }
+        }break;
+
+        case GPIOC: 
+        case GPIOD: 
+        {
+            GPIOx = GPIOCD;
+            
+            System_Module_Enable(EN_GPIOCD);
+
+            lu32_PollUP   = &(SCU->PCDPUR);
+            lu32_PollDown = &(SCU->PCDPDR);
+            lu32_ODEnable = &(SCU->PCDODR);
+            lu32_ADS      = &(SCU->PCDADS);
+            
+            if (fe_GPIO == GPIOD) 
+            {
+                fu32_Pin <<= 16;
+                
+                lu32_SEL1 = &(SCU->PDSEL1);
+                lu32_SEL2 = &(SCU->PDSEL2);
+            }
+            else 
+            {
+                lu32_SEL1 = &(SCU->PCSEL1);
+                lu32_SEL2 = &(SCU->PCSEL2);
+            }
+        }break;
+
+        case GPIOE: 
+        case GPIOF: 
+        {
+            GPIOx = GPIOEF;
+            
+            System_Module_Enable(EN_GPIOEF);
+
+            lu32_PollUP   = &(SCU->PEFPUR);
+            lu32_PollDown = &(SCU->PEFPDR);
+            lu32_ODEnable = &(SCU->PEFODR);
+            lu32_ADS      = &(SCU->PEFADS);
+            
+            if (fe_GPIO == GPIOF) 
+            {
+                fu32_Pin <<= 16;
+                
+                lu32_SEL1 = &(SCU->PFSEL1);
+            }
+            else 
+            {
+                lu32_SEL1 = &(SCU->PESEL1);
+                lu32_SEL2 = &(SCU->PESEL2);
+            }
+        }break;
+
+        default: break; 
+    }
+    
+    /* Configure Select pins */
+    while (fu32_Pin >> lu32_Position != 0) 
+    {
+        /* Get current pin position */
+        lu32_Current_Pin = fu32_Pin & (1uL << lu32_Position);
+        
+        if (lu32_Current_Pin) 
+        {
+            /* GPIO IN Function */
+            GPIOx->DIR &= ~lu32_Current_Pin;
+            GPIOx->CLR |=  lu32_Current_Pin;
+
+            /* Disable Enable INT */
+            GPIOx->IEN &= ~lu32_Current_Pin;
+
+            /* Clear trigger config */
+            GPIOx->IS  &= ~lu32_Current_Pin;
+            GPIOx->IBE &= ~lu32_Current_Pin;
+            GPIOx->IEV &= ~lu32_Current_Pin;
+
+
+            /* Get Position Mask */
+            if (lu32_Position < 16) 
+            {   /* GOIOA?¡éGPIOC?¡éGPIOE */
+                lu32_Position_Mask = lu32_Position;
+            }
+            else 
+            {   /* GPIOB?¡éGPIOD?¡éGPIOF */
+                lu32_Position_Mask = lu32_Position - 16;
+            }
+
+            /* SET GPIO Function */
+            if (lu32_Position_Mask < 8) 
+            {
+                *lu32_SEL1 &= ~(0xF << (lu32_Position_Mask * 4));
+            }
+            else 
+            {
+                *lu32_SEL2 &= ~(0xF << ((lu32_Position_Mask - 8) * 4));
+            }
+
+            /* NO Pull */
+            *lu32_PollUP   &= ~lu32_Current_Pin;
+            *lu32_PollDown &= ~lu32_Current_Pin;
+            
+            /* Not Open Drain */
+            *lu32_ODEnable &= ~lu32_Current_Pin;
+
+            /* Analog Mode */
+            *lu32_ADS |= lu32_Current_Pin;
+        }
+
+        lu32_Position++;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_GPIO_AnalogEnable
+* Description : Quickly Configure to analog function
+* Input       : fe_GPIO¡êoto select the GPIO peripheral.
+* Input       : fu32_Pin¡êospecifies the port bit to be written.
+                This parameter can be one of GPIO_PIN_x where x can be (0..15).
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020?¨º
+**********************************************************************************/
+void HAL_GPIO_AnalogEnable(enum_GPIOx_t fe_GPIO, uint32_t fu32_Pin)
+{
+    uint32_t lu32_Position = 0;
+    uint32_t lu32_Current_Pin;
+
+    volatile uint32_t *lp32_ADS = NULL;    // ???¨° -> ¨ºy¡Á??¡é?¡ê?a??????¡ä??¡Â
+
+    GPIO_TypeDef *GPIOx;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check the parameters */
+    if (!IS_GPIO_ALL_INSTANCE(fe_GPIO))      return;
+    if (!IS_GPIO_PIN(fu32_Pin))              return;
+#endif
+
+    switch (fe_GPIO)
+    {
+        case GPIOA: 
+        case GPIOB: 
+        {
+            System_Module_Enable(EN_GPIOAB);
+            
+            lp32_ADS = &(SCU->PABADS);
+            
+            if (fe_GPIO == GPIOB) 
+            {
+                fu32_Pin <<= 16;
+            }
+        }break;
+
+        case GPIOC: 
+        case GPIOD: 
+        {
+            System_Module_Enable(EN_GPIOCD);
+
+            lp32_ADS = &(SCU->PCDADS);
+            
+            if (fe_GPIO == GPIOD) 
+            {
+                fu32_Pin <<= 16;
+            }
+        }break;
+
+        case GPIOE: 
+        case GPIOF: 
+        {
+            System_Module_Enable(EN_GPIOEF);
+
+            lp32_ADS = &(SCU->PEFADS);
+            
+            if (fe_GPIO == GPIOF) 
+            {
+                fu32_Pin <<= 16;
+            }
+        }break;
+
+        default: break; 
+    }
+    
+    /* Configure Select pins */
+    while ((fu32_Pin) >> lu32_Position != 0) 
+    {
+        /* Get current pin position */
+        lu32_Current_Pin = (fu32_Pin) & (1uL << lu32_Position);
+        
+        if (lu32_Current_Pin) 
+        {
+            *lp32_ADS |= lu32_Current_Pin;
+        }
+
+        lu32_Position++;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_GPIO_WritePin
+* Description : Set or clear the selected data port bit.
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020?¨º
+**********************************************************************************/
+void HAL_GPIO_WritePin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin, enum_PinState_t fe_PinState)
+{
+    GPIO_TypeDef *GPIOx;
+
+#if (USE_FULL_ASSERT == 1)
+    /* Check the parameters */
+    if (!IS_GPIO_ALL_INSTANCE(fe_GPIO))      return;
+    if (!IS_GPIO_PIN(fu32_GPIO_Pin))         return;
+    if (!IS_GPIO_PIN_ACTION(fe_PinState))    return;
+#endif
+
+    switch (fe_GPIO)
+    {
+        case GPIOA: 
+        case GPIOB: 
+        {
+            GPIOx = GPIOAB;
+        }break;
+
+        case GPIOC: 
+        case GPIOD: 
+        {
+            GPIOx = GPIOCD;
+        }break;
+
+        case GPIOE: 
+        case GPIOF: 
+        {
+            GPIOx = GPIOEF;
+        }break;
+
+        default: break;
+    }
+
+    if (fe_GPIO == GPIOB || fe_GPIO == GPIOD || fe_GPIO == GPIOF)
+    {
+        fu32_GPIO_Pin <<= 16;
+    }
+
+    if (GPIO_PIN_SET == fe_PinState) 
+    {
+        GPIOx->ODATA |= fu32_GPIO_Pin;
+    }
+    else 
+    {
+        GPIOx->ODATA &= ~fu32_GPIO_Pin;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_GPIO_ReadPin
+* Description : Read the specified input port pin.
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020?¨º
+**********************************************************************************/
+enum_PinState_t HAL_GPIO_ReadPin(enum_GPIOx_t fe_GPIO, uint32_t fu32_GPIO_Pin)
+{
+    GPIO_TypeDef *GPIOx;
+
+    switch (fe_GPIO)
+    {
+        case GPIOA: 
+        case GPIOB: 
+        {
+            GPIOx = GPIOAB;
+        }break;
+
+        case GPIOC: 
+        case GPIOD: 
+        {
+            GPIOx = GPIOCD;
+        }break;
+
+        case GPIOE: 
+        case GPIOF: 
+        {
+            GPIOx = GPIOEF;
+        }break;
+
+        default: break;
+    }
+    
+    if (fe_GPIO == GPIOB || fe_GPIO == GPIOD || fe_GPIO == GPIOF)
+    {
+        fu32_GPIO_Pin <<= 16;
+    }
+    
+    if (GPIOx->IDATA & fu32_GPIO_Pin) 
+    {
+        return GPIO_PIN_SET;
+    }
+    else 
+    {
+        return GPIO_PIN_CLEAR;
+    }
+}
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2C.c

@@ -0,0 +1,1143 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2C.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   I2C HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include  "ACM32Fxx_HAL.h" 
+
+/* Private functions for I2C */
+static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed);
+static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout);
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
+/************************************************************************
+ * function   : HAL_I2C_IRQHandler
+ * Description: This function handles I2C interrupt request.
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ ************************************************************************/
+__weak void HAL_I2C_IRQHandler(I2C_HandleTypeDef *hi2c)
+{
+    uint32_t i;
+    
+    /* Slave ADDR1 Interrupt */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1))
+    {
+        /* Clear ADDR1 Interrupt Flag */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1);
+
+        /* Slave Transmit */
+        if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW))
+        {
+            i = 1;
+
+            /* Wait for transmission End*/
+            while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF));
+            /* Clear MTF */
+            hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+            /* BUS BUSY */
+            while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY))
+            {
+                if (i >= hi2c->Tx_Size && hi2c->Tx_Size != 0) 
+                {
+                    break;
+                }
+
+                if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) 
+                {
+                    /* Clear MTF */
+                    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+                }
+
+                if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE))
+                {
+                    hi2c->Instance->DR = hi2c->Tx_Buffer[i++];
+                    hi2c->Tx_Count++;
+                }
+            }
+            
+            /* Set Slave machine is DILE */
+            hi2c->Slave_TxState = SLAVE_TX_STATE_IDLE;
+        }
+        /* Slave Receive */
+        else 
+        {
+            i = 0;
+
+            /* Wait for transmission End*/
+            while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF));
+            /* Clear MTF */
+            hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+            /* BUS BUSY */
+            while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY))
+            {
+                /* Receive Data */
+                if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE))
+                {
+                    hi2c->Rx_Buffer[i++] = hi2c->Instance->DR;
+
+                    /* Wait for transmission End*/
+                    while(!READ_BIT(hi2c->Instance->SR, I2C_SR_MTF));
+                    /* Clear MTF */
+                    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+                    hi2c->Rx_Count++;
+
+                    if (hi2c->Rx_Size != 0) 
+                    {
+                        if (i >= hi2c->Rx_Size) 
+                        {
+                            break;
+                        }
+                    }
+                }
+            }
+            
+            /* Set Slave machine is DILE */
+            hi2c->Slave_RxState = SLAVE_RX_STATE_IDLE;
+        }
+
+        if (hi2c->Slave_RxState == SLAVE_RX_STATE_IDLE && hi2c->Slave_TxState == SLAVE_TX_STATE_IDLE) 
+        {
+            /* Disable RX_ADDR1_INT_EN */
+            CLEAR_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN);
+        }
+    }
+    
+    /* STOP Flag Interrupt */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF))
+    {
+        /* Clear STOPF Interrupt Flag */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF);
+        
+        /* Clear STOPF */
+        CLEAR_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN);
+        
+        if (hi2c->I2C_STOPF_Callback != NULL) 
+        {
+            hi2c->I2C_STOPF_Callback();
+        }
+    }
+}
+
+/************************************************************************
+ * function   : HAL_I2C_MspInit
+ * Description: 
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ ************************************************************************/
+__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_Handle; 
+    
+    /* I2C1 */
+    if (hi2c->Instance == I2C1)
+    {
+        /* Enable Clock */
+        System_Module_Enable(EN_I2C1);
+        System_Module_Enable(EN_GPIOAB);
+
+        /* I2C1 SDA  PortB Pin7 */
+        /* I2C1 SCL  PortB Pin6 */
+        GPIO_Handle.Pin            = GPIO_PIN_6 | GPIO_PIN_7;
+        GPIO_Handle.Mode           = GPIO_MODE_AF_PP;
+        GPIO_Handle.Pull           = GPIO_PULLUP;
+        GPIO_Handle.Alternate      = GPIO_FUNCTION_6;
+        HAL_GPIO_Init(GPIOB, &GPIO_Handle);
+        
+        /* Clear Pending Interrupt */
+        NVIC_ClearPendingIRQ(I2C1_IRQn);
+        
+        /* Enable External Interrupt */
+        NVIC_EnableIRQ(I2C1_IRQn);
+    }
+    /* I2C2 */
+    else if (hi2c->Instance == I2C2) 
+    {
+    }
+}
+
+/************************************************************************
+ * function   : HAL_I2C_MspDeInit
+ * Description: 
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ ************************************************************************/
+__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_Handle; 
+    
+    /* I2C1 */
+    if (hi2c->Instance == I2C1)
+    {
+        /* Disable Clock */
+        System_Module_Disable(EN_I2C1);
+
+        /* I2C1 SDA  PortB Pin7 */
+        /* I2C1 SCL  PortB Pin6 */
+        HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6 | GPIO_PIN_7);
+        /* Clear Pending Interrupt */
+        NVIC_ClearPendingIRQ(I2C1_IRQn);
+        
+        /* Disable External Interrupt */
+        NVIC_DisableIRQ(I2C1_IRQn);
+    }
+    /* I2C2 */
+    else if (hi2c->Instance == I2C2) 
+    {
+    }
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Init
+ * Description: I2c initial with parameters. 
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
+{
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))              return HAL_ERROR;
+    if (!IS_I2C_ALL_MODE(hi2c->Init.I2C_Mode))             return HAL_ERROR;
+    if (!IS_I2C_CLOCK_SPEED(hi2c->Init.Clock_Speed))       return HAL_ERROR;
+    if (!IS_I2C_TX_AUTO_EN(hi2c->Init.Tx_Auto_En))         return HAL_ERROR;
+    if (!IS_I2C_STRETCH_EN(hi2c->Init.No_Stretch_Mode))    return HAL_ERROR;
+
+    /* Disable the selected I2C peripheral */
+    CLEAR_BIT(hi2c->Instance->CR, I2C_CR_MEN); 
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_I2C_MspInit(hi2c);
+
+    switch (hi2c->Init.I2C_Mode)
+    {
+        /* Master Mode */
+        case I2C_MODE_MASTER:
+        {
+            /* Set Master Mode */
+            SET_BIT(hi2c->Instance->CR, I2C_CR_MASTER);
+            
+            /* Set Clock Speed */
+            I2C_Set_Clock_Speed(hi2c, hi2c->Init.Clock_Speed);
+            
+            /* Set SDA auto change the direction */
+            if (hi2c->Init.Tx_Auto_En == TX_AUTO_EN_ENABLE)
+                SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN);
+            else
+                CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN);
+            
+            /* Enable the selected I2C peripheral */
+            SET_BIT(hi2c->Instance->CR, I2C_CR_MEN);
+        }break;
+        
+        /* Slave Mode */
+        case I2C_MODE_SLAVE: 
+        {
+            SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL);
+
+            /* Set SDA auto change the direction */
+            if (hi2c->Init.Tx_Auto_En == TX_AUTO_EN_ENABLE)
+                SET_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN);
+            else
+                CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TX_AUTO_EN);
+            
+            /* Set Clock Stretch Mode */
+            if (hi2c->Init.No_Stretch_Mode == NO_STRETCH_MODE_NOSTRETCH)
+                SET_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH);
+            else
+                CLEAR_BIT(hi2c->Instance->CR, I2C_CR_NOSTRETCH);
+
+            /* Set Address 1 */
+            hi2c->Instance->SLAVE_ADDR1 = hi2c->Init.Own_Address;
+            
+            /* Enable the selected I2C peripheral */
+            SET_BIT(hi2c->Instance->CR, I2C_CR_MEN);
+        }break;
+        
+        default: break; 
+    }
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_DeInit
+ * Description: I2c De-initial with parameters. 
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
+{
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+    
+    hi2c->Slave_RxState = SLAVE_RX_STATE_IDLE;
+    hi2c->Slave_TxState = SLAVE_TX_STATE_IDLE;
+    
+    HAL_I2C_MspDeInit(hi2c);
+    
+    hi2c->Tx_Size = 0;
+    hi2c->Rx_Size = 0;
+    hi2c->Tx_Count = 0;
+    hi2c->Rx_Count = 0;
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Master_Transmit
+ * Description: Transmits in master mode an amount of data in blocking mode.
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              DevAddress : Target device address
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ *              Timeout    : Timeout value
+************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+    
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+    
+    hi2c->Tx_Buffer = pData;
+    hi2c->Tx_Size = Size;
+    hi2c->Tx_Count = 0;
+    
+    /* Send Write Access Request */
+    if (I2C_Master_Request_Write(hi2c, DevAddress, 0) == HAL_OK)
+    {
+        for (i = 0; i < hi2c->Tx_Size; i++)
+        {
+            /* Wait TXE Flag */
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+            
+            /* Send Data */
+            hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++];
+            
+            /* Wait for transmission End*/
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+            
+            /* Clear MTF */
+            hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+            
+            /* Get NACK */
+            if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+            {
+                /* Generate Stop */
+                SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+                
+                /* Wait for the bus to idle */
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+                
+                return HAL_ERROR;
+            }
+        }
+        
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+        
+        /* Wait for the bus to idle */
+         if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+    }
+    else
+    {
+        return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Master_Receive
+ * Description: Transmits in master mode an amount of data in blocking mode.
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              DevAddress : Target device address
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be Receive
+ *              Timeout    : Timeout value
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+    
+    hi2c->Rx_Buffer = pData;
+    hi2c->Rx_Size = Size;
+    hi2c->Rx_Count = 0;
+    
+    /* Send Read Access Request */
+    if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK)
+    {
+        /* Wait Master Transition receiving state */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+        /* Clear TX_RX_FLAG */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG);
+        /* Generate ACK */
+        CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+
+        for (i = 0; i < hi2c->Rx_Size - 1; i++)
+        {
+            /* Wait RXNE Flag */
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+            /* Read Data */
+            hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR;
+            /* Wait for transmission End*/
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+            /* Clear MTF */
+            hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+        }
+
+        /* Prepare for Generate NACK */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+        /* Prepare for Generate STOP */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+
+        /* Wait RXNE Flag */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+        /* Read Data */
+        hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR;
+        /* Wait for transmission End*/
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+        /* Clear MTF */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+        
+        /* Wait for the bus to idle */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+
+        /* Generate ACK */
+        CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+    }
+    else
+    {
+        return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Slave_Transmit
+ * Description: Transmits in Slave mode an amount of data in blocking mode.
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ *              Timeout    : Timeout value
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+    uint32_t i = 0;
+    
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+    
+    hi2c->Tx_Buffer = pData;
+    hi2c->Tx_Size = Size;
+    hi2c->Tx_Count = 0;
+
+    /* Clear RX_ADDR1 Flag */    
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1);  
+    /* Match the Address 1 */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+    /* Clear RX_ADDR1 Flag */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1);
+
+    /* Slave Transmit */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_SRW))
+    {
+        /* BUS BUSY */
+        while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY))
+        {
+            if (READ_BIT(hi2c->Instance->SR, I2C_SR_MTF)) 
+            {
+                /* Clear MTF */
+                hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+                hi2c->Tx_Count++;
+            }
+
+            if (READ_BIT(hi2c->Instance->SR, I2C_SR_TXE))
+            {
+                if (i < hi2c->Tx_Size || hi2c->Tx_Size == 0) 
+                {
+                    hi2c->Instance->DR = hi2c->Tx_Buffer[i++];
+                }
+            }
+        }
+        hi2c->Instance->SR = READ_REG(hi2c->Instance->SR);
+    }
+    else
+    {
+        return HAL_ERROR;
+    }
+
+    hi2c->Tx_Count--;
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Slave_Transmit_IT
+ * Description: Transmit in slave mode an amount of data in non-blocking mode with Interrupt
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size)
+{
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+
+    /* Rx machine is running */
+    if (hi2c->Slave_TxState != SLAVE_TX_STATE_IDLE)
+        return HAL_ERROR;
+
+    /* Set Slave machine is sending */
+    hi2c->Slave_TxState = SLAVE_TX_STATE_SENDING;
+
+    hi2c->Tx_Buffer = pData;
+    hi2c->Tx_Size   = Size;
+    hi2c->Tx_Count = 0;
+
+    CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL);
+
+    hi2c->Instance->DR = hi2c->Tx_Buffer[0];
+
+    hi2c->Tx_Count++;
+
+    /* Clear RX ADDR1 Flag */
+    SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1);
+    /* RX ADDR1 Interrupt Enable */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN);
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Slave_Receive
+ * Description: Receive in Slave mode an amount of data in blocking mode.
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              pData : Pointer to data buffer
+ *              Size  : Amount of data to be sent
+ *              Timeout    : Timeout value
+ * return     : HAL_StatusTypeDef
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+    uint32_t i = 0;
+    HAL_StatusTypeDef Status;
+    
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;;
+    
+    hi2c->Rx_Buffer = pData;
+    hi2c->Rx_Size = Size;
+    hi2c->Rx_Count = 0;
+    
+    /* Match the Address 1 */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RX_ADDR1, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+    /* Clear RX_ADDR1 Flag */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1);
+    
+    /* Slave Receive */
+    if (!READ_BIT(hi2c->Instance->SR, I2C_SR_SRW))
+    {
+        /* Wait for transmission End*/
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+        /* Clear MTF */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+        /* BUS BUSY */
+        while(READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY))
+        {
+            /* Receive Data */
+            if (READ_BIT(hi2c->Instance->SR, I2C_SR_RXNE))
+            {
+                hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR;
+                
+                /* Wait for transmission End*/
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                /* Clear MTF */
+                hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+                if (hi2c->Rx_Size != 0) 
+                {
+                    if (hi2c->Rx_Count >= hi2c->Rx_Size) 
+                    {
+                        break;
+                    }
+                }
+            }
+        }
+        
+        /* Generate ACK */
+        CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+        
+        hi2c->Instance->SR = READ_REG(hi2c->Instance->SR);
+    }
+    /* Slave Transmit */
+    else 
+    {
+       return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Slave_Receive_IT
+ * Description: Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size)
+{
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+
+    /* Rx machine is running */
+    if (hi2c->Slave_RxState != SLAVE_RX_STATE_IDLE)
+        return HAL_ERROR;
+
+    /* Set Slave machine is receiving */
+    hi2c->Slave_RxState = SLAVE_RX_STATE_RECEIVING;
+    
+    hi2c->Rx_Buffer = pData;
+    hi2c->Rx_Size   = Size;
+    hi2c->Rx_Count = 0;
+    
+    /* Clear RX ADDR1 Flag */
+    SET_BIT(hi2c->Instance->SR, I2C_SR_RX_ADDR1);
+    /* RX ADDR1 Interrupt Enable */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_RX_ADDR1_INT_EN);
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Slave_Receive_DMA
+ * Description: Receive in slave mode an amount of data in non-blocking mode with DMA
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size)
+{
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+
+    hi2c->Rx_Buffer = pData;
+    hi2c->Rx_Size   = Size;
+    hi2c->Rx_Count = Size;
+
+    /* DMA Enable */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN);
+
+    /* Clear STOPF Interrupt Flag */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_STOPF);
+    /* STOPF Interrupt Enable */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_STOPF_INTEN);
+
+    HAL_DMA_Start(hi2c->HDMA_Rx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->Rx_Buffer, hi2c->Rx_Size);
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Slave_Transmit_DMA
+ * Description: Transmit in slave mode an amount of data in non-blocking mode with DMA
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint32_t Size)
+{
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+
+    hi2c->Tx_Buffer = pData;
+    hi2c->Tx_Size   = Size;
+    hi2c->Tx_Count = Size;
+    
+    /* Must Set TXE_SEL In DMA Mode !!! */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_TXE_SEL);
+    /* DMA Enable */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_DMA_EN);
+
+    HAL_DMA_Start_IT(hi2c->HDMA_Tx, (uint32_t)hi2c->Tx_Buffer, (uint32_t)&hi2c->Instance->DR, hi2c->Tx_Size);
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Mem_Write
+ * Description: Write an amount of data in blocking mode to a specific memory address
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              DevAddress : Target device address
+ *              MemAddress : MemAddress Internal memory address
+ *              MemAddSize : MemAddSize Size of internal memory address
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ *              Timeout    : Timeout value
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+    
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+
+    hi2c->Tx_Buffer = pData;
+    hi2c->Tx_Size   = Size;
+    hi2c->Tx_Count = 0;
+    
+    /* Bus Busy */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) 
+        return HAL_ERROR;
+    
+    /* Send Write Access Request */
+    if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK)
+    {
+        /* If Memory address size is 8Bit */
+        if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+        {
+            /* Send Memory Address */
+            hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+        }
+        /* If Memory address size is 16Bit */ 
+        else
+        {
+            /* Send Memory Address MSB*/
+            hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+            /* Wait for transmission End*/
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+            /* Clear MTF */
+            hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+            /* Send Memory Address LSB*/
+            hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+        }
+        
+        /* Wait for transmission End*/
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+        /* Clear MTF */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+        
+        /* Get NACK */
+        if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+        {
+            /* Generate Stop */
+            SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+            
+            /* Wait for the bus to idle */
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK)  return HAL_ERROR;
+            
+            return HAL_ERROR;
+        }
+        /* Get ACK */
+        else 
+        {
+            for (i = 0; i < hi2c->Tx_Size; i++)
+            {
+                /* Wait TXE Flag */
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TXE, RESET, Timeout)!= HAL_OK)  return HAL_ERROR;
+                
+                /* Send Data */
+                hi2c->Instance->DR = hi2c->Tx_Buffer[hi2c->Tx_Count++];
+                
+                /* Wait for transmission End*/
+                 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                /* Clear MTF */
+                hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+                
+                /* Get NACK */
+                if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+                {
+                    /* Generate Stop */
+                    SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+                    
+                    /* Wait for the bus to idle */
+                    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK)  return HAL_ERROR;
+                    return HAL_ERROR;
+                }
+            }
+            
+            /* Generate Stop */
+            SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+            
+            /* Wait for the bus to idle */
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK)  return HAL_ERROR;
+            /* Check Device Ready */
+            while(I2C_Check_Device_Ready(hi2c, DevAddress, Timeout) != HAL_OK);
+        }
+    }
+    else
+    {
+        return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_Mem_Read
+ * Description: Read an amount of data in blocking mode to a specific memory address
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              DevAddress : Target device address
+ *              MemAddress : MemAddress Internal memory address
+ *              MemAddSize : MemAddSize Size of internal memory address
+ *              pData      : Pointer to data buffer
+ *              Size       : Amount of data to be sent
+ *              Timeout    : Timeout value
+ ************************************************************************/
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+    
+    /* Check I2C Parameter */
+    if (!IS_I2C_ALL_INSTANCE(hi2c->Instance))    return HAL_ERROR;
+
+    hi2c->Rx_Buffer = pData;
+    hi2c->Rx_Size   = Size;
+    hi2c->Rx_Count = 0;
+    
+    /* Bus Busy */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) 
+        return HAL_ERROR;
+    
+    /* Send Write Access Request */
+    if (I2C_Master_Request_Write(hi2c, DevAddress,0) == HAL_OK)
+    {
+        /* If Memory address size is 8Bit */
+        if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
+        {
+            /* Send Memory Address */
+            hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+        }
+        /* If Memory address size is 16Bit */ 
+        else
+        {
+            /* Send Memory Address MSB*/
+            hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
+            /* Wait for transmission End*/
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+            /* Clear MTF */
+            hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+            /* Send Memory Address LSB*/
+            hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
+        }
+        
+        /* Wait for transmission End*/
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+        /* Clear MTF */
+        hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+        
+        /* Get NACK */
+        if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+        {
+            /* Generate Stop */
+            SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+            
+            /* Wait for the bus to idle */
+            if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK)  return HAL_ERROR;
+            
+            return HAL_ERROR;
+        }
+        /* Get ACK */
+        else
+        {
+            /* Send Write Read Request */
+            if (I2C_Master_Request_Read(hi2c, DevAddress, Timeout) == HAL_OK)
+            {
+                /* Wait Master Transition receiving state */
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_TX_RX_FLAG, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                /* Clear TX_RX_FLAG */
+                hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_TX_RX_FLAG);
+
+                /* Generate ACK */
+                CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+
+                for (i = 0; i < hi2c->Rx_Size - 1; i++)
+                {
+                    /* Wait RXNE Flag */
+                    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                    /* Read Data */
+                    hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR;
+                    /* Wait for transmission End*/
+                    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                    /* Clear MTF */
+                    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+                }
+
+                /* Prepare for Generate NACK */
+                SET_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+                /* Prepare for Generate STOP */
+                SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+
+                /* Wait RXNE Flag */
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_RXNE, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                /* Read Data */
+                hi2c->Rx_Buffer[hi2c->Rx_Count++] = hi2c->Instance->DR;
+                /* Wait for transmission End*/
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK)  return HAL_ERROR;
+                /* Clear MTF */
+                hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+                /* Wait for the bus to idle */
+                if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK)  return HAL_ERROR;
+                /* Generate ACK */
+                CLEAR_BIT(hi2c->Instance->CR, I2C_CR_TACK);
+            }
+            else 
+            {
+            /* Get NACK */
+            return HAL_ERROR;
+            }
+        }
+    }
+    else
+    {
+    return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_GetSlaveRxState
+ * Description: Get Slave Rx State
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ * return     : Slave State
+ ************************************************************************/
+uint8_t HAL_I2C_GetSlaveRxState(I2C_HandleTypeDef *hi2c)
+{
+    return hi2c->Slave_RxState;
+}
+
+/************************************************************************
+ * function   : HAL_I2C_GetSlaveTxState
+ * Description: Get Slave Tx State
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ * return     : Slave State
+ ************************************************************************/
+uint8_t HAL_I2C_GetSlaveTxState(I2C_HandleTypeDef *hi2c)
+{
+    return hi2c->Slave_TxState;
+}
+
+/************************************************************************
+ * function   : I2C_Set_Clock_Speed
+ * Description: Set I2C Clock Speed
+ * input      : hi2c : pointer to a I2C_HandleTypeDef structure that contains
+ *                     the configuration information for I2C module
+ *              ClockSpeed: I2C Clock Speed
+ ************************************************************************/
+static HAL_StatusTypeDef I2C_Set_Clock_Speed(I2C_HandleTypeDef *hi2c, uint32_t ClockSpeed)
+{
+    uint32_t APB_Clock;
+
+    APB_Clock = System_Get_APBClock();
+
+    hi2c->Instance->CLK_DIV = APB_Clock / (4 * ClockSpeed) - 1;
+
+    return HAL_OK;
+}
+
+/**
+  * @brief  This function handles I2C Communication Timeout.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *         the configuration information for I2C module
+  * @param  Flag specifies the I2C flag to check.
+  * @param  Status The new Flag status (SET or RESET).
+  * @param  Timeout Timeout duration
+  * @param  Tickstart Tick start value
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
+{
+    __IO uint32_t lu32_Timeout;
+    /* have no timeout */
+    if (Timeout == 0) 
+    {
+        while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status);
+    }
+    else 
+    {
+        lu32_Timeout = Timeout * 0xFF;
+            
+        while (__HAL_I2C_GET_FLAG(hi2c, Flag)==Status)
+        {
+            if (lu32_Timeout-- == 0) 
+            {
+                return HAL_ERROR;
+            }
+        }
+    }
+    return HAL_OK;
+}
+/************************************************************************
+ * function   : I2C_Master_Request_Write
+ * Description: I2C Write Access Request
+ * input      : hi2c  : pointer to a I2C_HandleTypeDef structure 
+ *              DevAddress: Device address
+ *              Timeout: Timeout value
+ ************************************************************************/
+static HAL_StatusTypeDef I2C_Master_Request_Write(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout)
+{
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_START);
+
+    /* Clear MTF, To Prevent Errors */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+    /* Send Device Address */
+    hi2c->Instance->DR = DevAddress & 0xFE;
+
+    /* Wait for transmission End*/
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+    /* Clear MTF */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+
+    /* Get NACK */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+    {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+        
+        /* Wait for the bus to idle */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+        
+        return HAL_ERROR;
+    }
+    /* Get ACK */
+    else 
+    {
+        return HAL_OK;
+    }
+}
+
+/************************************************************************
+ * function   : I2C_Master_Request_Read
+ * Description: I2C Read Access Request
+ * input      : hi2c  : pointer to a I2C_HandleTypeDef structure 
+ *              DevAddress: Device address
+ *              Timeout: Timeout value
+ ************************************************************************/
+static HAL_StatusTypeDef I2C_Master_Request_Read(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout)
+{
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_START);
+
+    /* Clear MTF, To Prevent Errors */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+    
+    /* Send Device Address */
+    hi2c->Instance->DR = DevAddress | 0x01;
+    
+    /* Wait for transmission End */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+    /* Clear MTF */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+    
+    /* Get NACK */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+    {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+        
+        /* Wait for the bus to idle */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+        
+        return HAL_ERROR;
+    }
+    /* Get ACK */
+    else 
+    {
+        return HAL_OK;
+    }
+}
+
+/************************************************************************
+ * function   : I2C_Check_Device_Ready
+ * Description: Check Device Ready
+ * input      : hi2c  : pointer to a I2C_HandleTypeDef structure 
+ *              DevAddress: Device address
+ *              Timeout: Timeout value
+ ************************************************************************/
+static HAL_StatusTypeDef I2C_Check_Device_Ready(I2C_HandleTypeDef *hi2c, uint8_t DevAddress, uint32_t Timeout)
+{
+    /* Bus Busy */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_BUS_BUSY)) 
+        return HAL_ERROR;
+
+    /* Generate Start */
+    SET_BIT(hi2c->Instance->CR, I2C_CR_START);
+    
+    /* Send Device Address */
+    hi2c->Instance->DR = DevAddress;
+    
+    /* Wait for transmission End */
+    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_MTF, RESET, Timeout) != HAL_OK) return HAL_ERROR;
+    /* Clear MTF */
+    hi2c->Instance->SR = READ_BIT(hi2c->Instance->SR, I2C_SR_MTF);
+    
+    /* Get NACK */
+    if (READ_BIT(hi2c->Instance->SR, I2C_SR_RACK))
+    {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+        
+        /* Wait for the bus to idle */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+        
+        return HAL_ERROR;
+    }
+    /* Get ACK */
+    else 
+    {
+        /* Generate Stop */
+        SET_BIT(hi2c->Instance->CR, I2C_CR_STOP);
+        
+        /* Wait for the bus to idle */
+        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_SR_BUS_BUSY, SET, Timeout) != HAL_OK) return HAL_ERROR;
+        
+        return HAL_OK;
+    }
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_I2S.c

@@ -0,0 +1,491 @@
+/*
+  ******************************************************************************
+  * @file    HAL_I2S.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   I2S HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
+  *           + Initialization functions
+  *           + IO operation functions
+  *           + Peripheral State 
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_I2S_IRQHandler
+* Description : This function handles I2S interrupt request.
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
+{
+    /* Tx Buffer empty */
+    if (hi2s->Instance->STATUS & I2S_STATUS_TXBE) 
+    {
+        if (hi2s->u32_Tx_Count < hi2s->u32_Tx_Size) 
+        {
+            hi2s->Instance->DAT = hi2s->u32_Tx_Buffer[hi2s->u32_Tx_Count++];
+        }
+        else 
+        {
+            hi2s->Instance->IE &= ~I2S_DIE_TBEIE;
+            
+            hi2s->I2S_Status = HAL_I2S_STATE_READY;
+        }
+    }
+    
+    /* Rx Buffer not empty */
+    if (hi2s->Instance->STATUS & I2S_STATUS_RXBNE) 
+    {
+        if (hi2s->u32_Rx_Count < hi2s->u32_Rx_Size) 
+        {
+            hi2s->u32_Tx_Buffer[hi2s->u32_Rx_Count++] = hi2s->Instance->DAT;
+        }
+        else 
+        {
+            /* Disable I2S */
+            hi2s->Instance->CTL &= ~I2S_CTL_I2SEN;
+    
+            hi2s->Instance->IE &= ~I2S_DIE_RBNEIE;
+
+            hi2s->I2S_Status = HAL_I2S_STATE_READY;
+        }
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_MspInit
+* Description : 
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+__weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_Handle; 
+        
+    if (hi2s->Instance == I2S1) 
+    {
+        /* Enable Clock */
+        System_Module_Enable(EN_I2S1);
+        System_Module_Enable(EN_GPIOAB);
+
+        /* I2S1 WS   PortA Pin4 */
+        /* I2S1 CLK  PortA Pin5 */
+        /* I2S1 MCK  PortA Pin6 */
+        /* I2S1 SD   PortA Pin7 */
+        GPIO_Handle.Pin       = GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
+        GPIO_Handle.Mode      = GPIO_MODE_AF_PP;
+        GPIO_Handle.Pull      = GPIO_PULLUP;
+        GPIO_Handle.Alternate = GPIO_FUNCTION_8;
+        HAL_GPIO_Init(GPIOA, &GPIO_Handle);
+
+        /* Clear Pending Interrupt */
+        NVIC_ClearPendingIRQ(I2S_IRQn);
+        
+        /* Enable External Interrupt */
+        NVIC_EnableIRQ(I2S_IRQn);
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_MspDeInit
+* Description : 
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+__weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    if (hi2s->Instance == I2S1) 
+    {
+        /* I2S1 WS   PortA Pin4 */
+        /* I2S1 CLK  PortA Pin5 */
+        /* I2S1 MCK  PortA Pin6 */
+        /* I2S1 SD   PortA Pin7 */
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+
+        /* Clear Pending Interrupt */
+        NVIC_ClearPendingIRQ(I2S_IRQn);
+        
+        /* Disable External Interrupt */
+        NVIC_DisableIRQ(I2S_IRQn);
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Init
+* Description : Initializes the I2S according to the specified parameters
+*               in the I2S_InitTypeDef and create the associated handle.
+* Input       : hi2s: pointer to a I2S_HandleTypeDef structure that contains
+*                     the configuration information for I2S module
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check I2S Parameter */
+    if (!IS_I2S_MODE(hi2s->Init.u32_Mode))                 return HAL_ERROR;
+    if (!IS_I2S_STANDARD(hi2s->Init.u32_Standard))         return HAL_ERROR;
+    if (!IS_I2S_DATAFORMAT(hi2s->Init.u32_DataFormat))     return HAL_ERROR;
+    if (!IS_I2S_MCLK_OUTPUT(hi2s->Init.u32_MCLKOutput))    return HAL_ERROR;
+    if (!IS_I2S_MCLK_CPOL(hi2s->Init.u32_CPOL))            return HAL_ERROR;
+    if (!IS_I2S_OF(hi2s->Init.u32_FreqOF))                 return HAL_ERROR;
+    if (!IS_I2S_DIV(hi2s->Init.u32_FreqDIV))               return HAL_ERROR;
+#endif
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
+    HAL_I2S_MspInit(hi2s);
+    
+    /* Clear Config */
+    hi2s->Instance->CTL = 0x00000000;
+    hi2s->Instance->PSC = 0x00000000;
+
+    /* Mode、Standard、CPOL、Dataformat */
+    hi2s->Instance->CTL = hi2s->Init.u32_Mode | hi2s->Init.u32_Standard | hi2s->Init.u32_CPOL | hi2s->Init.u32_DataFormat;
+    /* Frequency */
+    hi2s->Instance->PSC = hi2s->Init.u32_MCLKOutput | hi2s->Init.u32_FreqOF | hi2s->Init.u32_FreqDIV;
+
+    /* I2S Enable */
+    if (hi2s->Init.u32_Mode != I2S_MODE_MASTER_RX) 
+    {
+        hi2s->Instance->CTL |= I2S_CTL_I2SEN;
+    }
+    
+    /* I2S Status ready */
+    hi2s->I2S_Status = HAL_I2S_STATE_READY;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_DeInit
+* Description : DeInitializes the I2S peripheral
+* Input       : hi2s: pointer to a I2S_HandleTypeDef structure that contains
+*                     the configuration information for I2S module
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
+{
+    /* Check the I2S handle allocation */
+    if (hi2s == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+    HAL_I2S_MspDeInit(hi2s);
+    
+    System_Module_Reset(RST_I2S1);
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Transmit
+* Description : Transmit an amount of data in blocking mode
+* Input       : hi2s: pointer to a I2S_HandleTypeDef structure that contains
+*                     the configuration information for I2S module
+* Input       : fp32_Data: 32-bit pointer to data buffer.
+* Input       : Size: number of data sample to be sent
+* Input       : fu32_Timeout: Timeout duration
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout)
+{
+    uint32_t i;
+
+    uint32_t lu32_Timeout;
+
+    /* Parameter Check */
+    if ((fp32_Data == NULL) || (fu32_Size == 0U))
+    {
+        return  HAL_ERROR;
+    }
+    
+    /* I2S Ready? */
+    if (hi2s->I2S_Status != HAL_I2S_STATE_READY) 
+    {
+        return  HAL_BUSY;
+    }
+    
+    hi2s->I2S_Status = HAL_I2S_STATE_BUSY_TX;
+    
+    /* transmit */
+    for (i = 0; i < fu32_Size; i++)
+    {
+        hi2s->Instance->DAT = fp32_Data[i];
+
+        /* have no timeout */
+        if (fu32_Timeout == 0) 
+        {
+            while(!(hi2s->Instance->STATUS & I2S_STATUS_TXBE));
+        }
+        else 
+        {
+            lu32_Timeout = fu32_Timeout * 0xFF;
+
+            while(!(hi2s->Instance->STATUS & I2S_STATUS_TXBE))
+            {
+                if (lu32_Timeout-- == 0) 
+                {
+                    hi2s->I2S_Status = HAL_I2S_STATE_READY;
+                    
+                    return HAL_TIMEOUT;
+                }
+            }
+        }
+    }
+
+    /* Wait for the last Byte */
+    while (hi2s->Instance->STATUS & I2S_STATUS_TRANS);
+    
+    hi2s->I2S_Status = HAL_I2S_STATE_READY;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Receive
+* Description : Receive an amount of data in blocking mode
+* Input       : hi2s pointer to a I2S_HandleTypeDef structure that contains
+*               the configuration information for I2S module
+* Input       : fp32_Data: a 32-bit pointer to data buffer.
+* Input       : Size: number of data sample to be Receive
+* Input       : fu32_Timeout: Timeout duration
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size, uint32_t fu32_Timeout)
+{
+    uint32_t i;
+
+    uint32_t lu32_Timeout;
+    
+    /* Parameter Check */
+    if ((fp32_Data == NULL) || (fu32_Size == 0U))
+    {
+        return  HAL_ERROR;
+    }
+
+    /* I2S Ready? */
+    if (hi2s->I2S_Status != HAL_I2S_STATE_READY) 
+    {
+        return  HAL_BUSY;
+    }
+
+    hi2s->I2S_Status = HAL_I2S_STATE_BUSY_RX;
+
+    /* I2S Enable */
+    hi2s->Instance->CTL |= I2S_CTL_I2SEN;
+    
+    /* Receive */
+    for (i = 0; i < fu32_Size; i++)
+    {
+        /* have no timeout */
+        if (fu32_Timeout == 0) 
+        {
+            while(!(hi2s->Instance->STATUS & I2S_STATUS_RXBNE));
+            fp32_Data[i] = hi2s->Instance->DAT;
+        }
+        else 
+        {
+            lu32_Timeout = fu32_Timeout * 0xFF;
+
+            while(!(hi2s->Instance->STATUS & I2S_STATUS_RXBNE))
+            {
+                if (lu32_Timeout-- == 0) 
+                {
+                    hi2s->I2S_Status = HAL_I2S_STATE_READY;
+
+                    return HAL_TIMEOUT;
+                }
+            }
+
+            fp32_Data[i] = hi2s->Instance->DAT;
+        }
+    }
+
+    /* Disable I2S */
+    hi2s->Instance->CTL &= ~I2S_CTL_I2SEN;
+
+    hi2s->I2S_Status = HAL_I2S_STATE_READY;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Transmit_IT
+* Description : Transmit an amount of data in non-blocking mode with Interrupt
+* Input       : hi2s pointer to a I2S_HandleTypeDef structure that contains
+*               the configuration information for I2S module
+* Input       : fp32_Data: a 32-bit pointer to data buffer.
+* Input       : Size: number of data sample to be send
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size)
+{
+    /* Parameter Check */
+    if ((fp32_Data == NULL) || (fu32_Size == 0U))
+    {
+        return  HAL_ERROR;
+    }
+
+    /* I2S Ready? */
+    if (hi2s->I2S_Status != HAL_I2S_STATE_READY) 
+    {
+        return  HAL_BUSY;
+    }
+
+    hi2s->I2S_Status = HAL_I2S_STATE_BUSY_TX;
+    
+    hi2s->u32_Tx_Buffer = fp32_Data;
+    hi2s->u32_Tx_Size   = fu32_Size;
+    hi2s->u32_Tx_Count  = 0;
+    
+    hi2s->Instance->IE |= I2S_DIE_TBEIE;
+    
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Receive_IT
+* Description : Receive an amount of data in non-blocking mode with Interrupt
+* Input       : hi2s pointer to a I2S_HandleTypeDef structure that contains
+*               the configuration information for I2S module
+* Input       : fp32_Data: a 32-bit pointer to data buffer.
+* Input       : Size: number of data sample to be Receive
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size)
+{
+    uint32_t lu32_Tempvalue;
+    
+    /* Parameter Check */
+    if ((fp32_Data == NULL) || (fu32_Size == 0U))
+    {
+        return  HAL_ERROR;
+    }
+
+    /* I2S Ready? */
+    if (hi2s->I2S_Status != HAL_I2S_STATE_READY) 
+    {
+        return  HAL_BUSY;
+    }
+    
+    /* Clear Rx Buffer */
+    while (hi2s->Instance->STATUS & I2S_STATUS_RXBNE) 
+    {
+        lu32_Tempvalue = hi2s->Instance->DAT;
+    }
+
+    hi2s->I2S_Status = HAL_I2S_STATE_BUSY_RX;
+
+    hi2s->u32_Rx_Buffer = fp32_Data;
+    hi2s->u32_Rx_Size   = fu32_Size;
+    hi2s->u32_Rx_Count  = 0;
+
+    hi2s->Instance->IE |= I2S_DIE_RBNEIE;
+
+    /* I2S Enable */
+    hi2s->Instance->CTL |= I2S_CTL_I2SEN;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Transmit_DMA
+* Description : Transmit an amount of data in non-blocking mode with DMA
+* Input       : hi2s: pointer to a I2S_HandleTypeDef structure that contains
+*                     the configuration information for I2S module
+* Input       : fp32_Data: 32-bit pointer to data buffer.
+* Input       : Size: number of data sample to be sent
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size)
+{
+    /* Parameter Check */
+    if ((fp32_Data == NULL) || (fu32_Size == 0U))
+    {
+        return  HAL_ERROR;
+    }
+
+    /* DMA transfer complete */
+    if (!(hi2s->I2S_Status & I2S_STATUS_TRANS))
+    {
+        hi2s->I2S_Status = HAL_I2S_STATE_READY;
+    }
+
+    /* I2S Ready? */
+    if (hi2s->I2S_Status != HAL_I2S_STATE_READY) 
+    {
+        return  HAL_BUSY;
+    }
+
+    hi2s->I2S_Status = HAL_I2S_STATE_BUSY_TX;
+
+    hi2s->Instance->IE |= I2S_DIE_DMATEN;
+
+    HAL_DMA_Start_IT(hi2s->HDMA_Tx, (uint32_t)fp32_Data, (uint32_t)&hi2s->Instance->DAT, fu32_Size);
+    
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_I2S_Receive_DMA
+* Description : Receive an amount of data in non-blocking mode with DMA
+* Input       : hi2s pointer to a I2S_HandleTypeDef structure that contains
+*               the configuration information for I2S module
+* Input       : fp32_Data: a 32-bit pointer to data buffer.
+* Input       : Size: number of data sample to be Receive
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint32_t *fp32_Data, uint32_t fu32_Size)
+{
+    /* Parameter Check */
+    if ((fp32_Data == NULL) || (fu32_Size == 0U))
+    {
+        return  HAL_ERROR;
+    }
+
+    /* DMA transfer complete */
+    if (!(hi2s->I2S_Status & I2S_STATUS_TRANS))
+    {
+        hi2s->I2S_Status = HAL_I2S_STATE_READY;
+    }
+
+    /* I2S Ready? */
+    if (hi2s->I2S_Status != HAL_I2S_STATE_READY) 
+    {
+        return  HAL_BUSY;
+    }
+
+    hi2s->I2S_Status = HAL_I2S_STATE_BUSY_RX;
+
+    hi2s->Instance->IE |= I2S_DIE_DMATEN;
+
+    HAL_DMA_Start_IT(hi2s->HDMA_Rx, (uint32_t)&hi2s->Instance->DAT, (uint32_t)fp32_Data, fu32_Size);
+
+    return HAL_OK;
+}
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_IWDT.c

@@ -0,0 +1,72 @@
+/***********************************************************************
+ * Filename    : HAL_IWDT.c
+ * Description : HAL IWDT driver source file
+ * Author(s)   : CWT  
+ * version     : V1.0
+ * Modify date : 2020-04-17  
+ ***********************************************************************/
+#include  "ACM32Fxx_HAL.h" 
+
+
+HAL_StatusTypeDef HAL_IWDT_Init(IWDT_HandleTypeDef * hidt)
+{
+    if (hidt == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    System_Module_Enable(EN_IWDT); 	    
+    System_Delay(1);  
+
+    System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);  
+    System_Enable_RC32K();      
+    System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_IWDT, FUNC_ENABLE);  
+    /*Enable IWDT  */
+    hidt->Instance->CMDR = IWDT_ENABLE_COMMAND;
+    System_Delay(10);  	
+    /*Enable Write  */
+    hidt->Instance->CMDR = IWDT_WRITE_ENABLE_COMMAND;      
+    System_Delay(10);          
+
+    hidt->Instance->PR = hidt->Init.Prescaler;   
+    hidt->Instance->RLR = hidt->Init.Reload;	
+    hidt->Instance->WINR = hidt->Init.Window; 		
+    hidt->Instance->WUTR = hidt->Init.Wakeup;    	
+    System_Delay(1);    
+    while(hidt->Instance->SR & (0x0F)){}; // wait for configuration done         
+
+    if (hidt->Init.Reload > hidt->Init.Wakeup)	
+    {
+        /*Enable Wake up  */
+        hidt->Instance->CMDR = IWDT_WAKEUP_ENABLE_COMMAND;  
+    }
+
+    hidt->Instance->CMDR = IWDT_RELOAD_COMMAND;
+    System_Delay(1);	
+    while(hidt->Instance->SR & (1 << 4)){};      
+
+    return HAL_OK;  
+
+}
+
+HAL_StatusTypeDef HAL_IWDT_Kick_Watchdog_Wait_For_Done(IWDT_HandleTypeDef * hidt)  
+{
+    hidt->Instance->CMDR = IWDT_RELOAD_COMMAND;  
+    System_Delay(1);   
+    while(hidt->Instance->SR & (1 << 4)){};  //wait for kick watchdog done       
+
+    return HAL_OK;  
+}
+
+
+
+
+
+
+
+
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_LPUART.c

@@ -0,0 +1,452 @@
+/*
+  ******************************************************************************
+  * @file    HAL_LPUART.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   LPUART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (LPUART).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_LPUART_IRQHander
+* Description : LPUART IRQHander 
+* Input       : 
+* Outpu       : 
+* Author      : CWT                         Data : 2020Äê
+**********************************************************************************/ 
+void HAL_LPUART_IRQHander(LPUART_HandleTypeDef *hlpuart)  
+{
+    while ( (hlpuart->Instance->SR) & (1U << LPUART_SR_RX_INDEX))        
+    {
+        if(hlpuart->rx_read_index != (((hlpuart->rx_write_index) + 1)% (hlpuart->rx_buffer_size) ) )     
+        {
+            hlpuart->rx_buffer[hlpuart->rx_write_index] = hlpuart->Instance->RXDR;   
+            hlpuart->rx_write_index = ((hlpuart->rx_write_index + 1)%(hlpuart->rx_buffer_size) );        
+        }
+        else
+        {
+            hlpuart->Instance->SR = (1U << LPUART_SR_RX_INDEX);  // buffer overflow  
+            return;  
+        }
+    }
+}
+/************************************************************************
+ * function   : HAL_UART_Buffer_Init
+ * Description: uart buffer initiation.  
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ * return: 0: FAIL; 1: SUCCESS 
+ ************************************************************************/
+HAL_StatusTypeDef HAL_LPUART_Buffer_Init(LPUART_HandleTypeDef *hlpuart) 
+{
+    if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance))   
+    {
+        return HAL_ERROR;  
+    }
+    hlpuart->rx_read_index = 0;
+    hlpuart->rx_write_index = 0;
+    hlpuart->tx_busy = 0;  
+    return HAL_OK;  
+}
+
+/**********************************************************************************
+ * function   : HAL_LPUART_MSPInit  
+ * Description: UART MCU specific initiation, such as IO share, module clock, ...  
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ * return: 0: FAIL; 1: SUCCESS 
+ ***************************************************************************************/ 
+ 
+__weak void HAL_LPUART_MSPInit(LPUART_HandleTypeDef *hlpuart) 
+{ 
+    GPIO_InitTypeDef gpio_init; 
+
+    System_Module_Reset(RST_LPUART); 
+    gpio_init.Pin = GPIO_PIN_2|GPIO_PIN_3;  // TX PA2 RX PA3 
+    gpio_init.Mode = GPIO_MODE_AF_PP;   
+    gpio_init.Pull = GPIO_PULLUP;   
+    gpio_init.Alternate = GPIO_FUNCTION_6;  
+    HAL_GPIO_Init(GPIOA,&gpio_init);   
+    System_Module_Enable(EN_LPUART);  
+}
+
+/*********************************************************************************
+* Function    : HAL_LPUART_MspDeInit
+* Description :	LPUART MSP De-Initialization 
+*               This function frees the hardware resources used in this example:
+*              - Disable the Peripheral's clock
+*              - Revert GPIO configuration to their default state
+* Input       : hcan : pointer to a CAN_HandleTypeDef structure that contains
+*                      the configuration information for CAN module
+* Output      : 
+* Author      : CWT                         Data : 2020Äê
+**********************************************************************************/
+void HAL_LPUART_MspDeInit(LPUART_HandleTypeDef *hlpuart)
+{
+    GPIO_InitTypeDef GPIO_InitStructure;   	
+    /* Initialization GPIO */
+    /* // TX PA2    RX PA3 */
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_2);
+    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_3);
+}
+/**********************************************************************************
+ * function   : HAL_LPUART_Set_Baud_Rate
+ * Description: set uart module's baud rate. It should be set when UART is disabled. 
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ * return: 0: FAIL; 1: SUCCESS 
+ ***************************************************************************************/ 
+uint8_t HAL_LPUART_Set_Baud_Rate(LPUART_HandleTypeDef *hlpuart, uint32_t lpuart_clk, uint32_t baud_rate)
+{
+    uint32_t ibaud, fbaud, rxsamp;   
+
+    if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance))   
+    {
+        return 0;  
+    }
+    ibaud = 2;
+    fbaud = 0x952;   
+    rxsamp = 1;    
+    switch(lpuart_clk)  
+    {
+        case 32000:
+        case 32768: 
+        switch(baud_rate) 
+        {
+        case 9600:
+        ibaud = 2;
+        fbaud = 0x952; 
+        break;
+
+        case 4800: 
+        ibaud = 5;
+        fbaud = 0xefb;    
+        break;
+
+        case 2400: 
+        ibaud = 12;
+        fbaud = 0x6db;   
+        break;
+
+        case 1200: 
+        ibaud = 26;
+        fbaud = 0x492;   
+        break;   
+        default: 
+        ibaud = 2;
+        fbaud = 0x952; 
+        break;  
+        }
+        rxsamp = ibaud >> 1;    
+        break; 
+
+        case 1875000:  // for ABP CLK=120M/2=60M  lpuart clk = 60M/32=1.875M
+        switch(baud_rate) 
+        {
+            case 256000:
+            ibaud = 6; 
+            fbaud = 0x888; 
+            break;
+
+            case 115200:  
+            ibaud = 15;  
+            fbaud = 0x888; 
+            break;
+        }
+        rxsamp = ibaud >> 1;    
+        break; 
+       
+        default:  //  for ABP CLK=180M/2=90M  lpuart clk = 90M/32=2.8125M
+        switch(baud_rate) 
+        {
+            case 256000:
+            ibaud = 9;  //2.8125M/256000=10.984  ibaud=(10-1)
+            fbaud = 0x7FE; // 0.984 *11=10
+            break;
+
+            case 115200:  
+            ibaud = 23;  //2.8125M/115200=24.4140625  ibaud=(24-1)
+            fbaud = 0x249; //0.4140625*11=4
+            break;
+        }
+        rxsamp = ibaud >> 1;    
+        break;  
+    } 
+    hlpuart->Instance->IBAUD = ibaud | (rxsamp << 8); 
+    hlpuart->Instance->FBAUD = fbaud;  
+    return 1;   
+}
+
+/************************************************************************
+ * function   : HAL_LPUART_Config
+ * Description: Configure UART module parameters, such as baudrate, parity, 
+ *              stop bits, dataword. 
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ * return: 0: FAIL; 1: SUCCESS  
+ ************************************************************************/
+uint8_t HAL_LPUART_Config(LPUART_HandleTypeDef *hlpuart)  
+{   
+    volatile uint32_t temp_reg;
+    if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) 
+    {
+        return 0;  
+    }
+    temp_reg = 1U << 7; // default value  
+    temp_reg |= ((hlpuart->ConfigParam.WordLength << 4) | (hlpuart->ConfigParam.StopBits << 3));
+    switch(hlpuart->ConfigParam.Parity)
+    {
+        case LPUART_PARITY_NONE:
+        break;  // do nothing 
+
+        case LPUART_PARITY_SELECT_ODD:
+        case LPUART_PARITY_SELECT_EVEN:
+        temp_reg |= (((hlpuart->ConfigParam.Parity - LPUART_PARITY_SELECT_ODD) << LPUART_EPS_INDEX) | (1 << LPUART_PEN_INDEX));    
+        break;  
+
+        case LPUART_PARITY_SELECT_ONE:
+        case LPUART_PARITY_SELECT_ZERO: 
+        temp_reg |= (((hlpuart->ConfigParam.Parity - LPUART_PARITY_SELECT_ONE) << LPUART_EPS_INDEX) | (1 << LPUART_SPS_INDEX) | (1 << LPUART_PEN_INDEX) );    
+        break;
+    }
+    hlpuart->Instance->LCR = temp_reg;  
+    return 1;  
+}
+
+/*********************************************************************************
+* Function    : LPUART_Clock_Select
+* Description : Select the LPUART clock. 
+* Input       : lpuart_clk_src:Could be LPUART_CLOCK_SOURCE_RC32K        LPUART_CLOCK_SOURCE_XTAL       LPUART_CLOCK_SOURCE_PLL_DIV
+* Outpu       : 
+* Author      : CWT                         Data : 2020Äê
+**********************************************************************************/ 
+void LPUART_Clock_Select(uint8_t lpuart_clk_src)
+{
+    if (0 == lpuart_clk_src)
+    {
+        SCU->CCR2 &= (~(BIT13 | BIT14) );     // RC32K 
+    }
+    else if (1 == lpuart_clk_src) 
+    {
+        SCU->CCR2 = (SCU->CCR2 & (~(BIT13 | BIT14) )) | (BIT13);     // XTAL 
+    }
+    else
+    {
+        SCU->CCR2 = (SCU->CCR2 & (~(BIT11 | BIT12| BIT13 | BIT14) )) | (BIT11 | BIT12 | BIT14);  // pclk/32          
+    }
+}
+/************************************************************************
+ * function   : HAL_LPUART_Init
+ * Description: uart initial with parameters. 
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ * return: 0: FAIL; 1: SUCCESS   
+ ************************************************************************/
+HAL_StatusTypeDef HAL_LPUART_Init(LPUART_HandleTypeDef *hlpuart) 
+{  
+    uint32_t lpuart_clock;
+    if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) 
+    {
+        return HAL_ERROR;;  
+    }
+
+    HAL_LPUART_Buffer_Init(hlpuart);    
+    /*reset module, configure tx and rx, enable module clock*/
+    HAL_LPUART_MSPInit(hlpuart); 
+
+    if (LPUART_CLOCK_SOURCE_RC32K == hlpuart->ConfigParam.ClockSrc)
+    {
+        lpuart_clock = 32000;  
+        System_Module_Enable(EN_RTC); 
+        System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);
+        System_Enable_RC32K(); 
+        LPUART_Clock_Select(0);
+    }
+    else if (LPUART_CLOCK_SOURCE_XTAL == hlpuart->ConfigParam.ClockSrc)
+    {
+        lpuart_clock = 32768;  
+        System_Module_Enable(EN_RTC); 
+       System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);
+        System_Enable_XTAL();   
+        LPUART_Clock_Select(1);
+    }
+    else
+    {
+        lpuart_clock = System_Get_APBClock()/32;      
+        LPUART_Clock_Select(2);  
+    }
+    HAL_LPUART_Set_Baud_Rate(hlpuart, lpuart_clock, hlpuart->ConfigParam.BaudRate);    
+
+    HAL_LPUART_Config(hlpuart);     
+
+    hlpuart->Instance->SR = LPUART_SR_BITS_ALL;  
+    hlpuart->Instance->IE = (1U << LPUART_IE_RX_INDEX);   
+    hlpuart->Instance->CR = (1U << LPUART_CR_RXE_INDEX) | (1 << LPUART_CR_TXE_INDEX);  
+    hlpuart->Instance->LCR=((hlpuart->StopWakeup.Wakeup_Source<<5)|(hlpuart->StopWakeup.Wakeup_Check<<7)); 
+    hlpuart->Instance->ADDR=(hlpuart->StopWakeup.Wakeup_Addr);
+    NVIC_ClearPendingIRQ(LPUART_IRQn);
+    NVIC_EnableIRQ(LPUART_IRQn);  
+    return HAL_OK;;  
+}
+HAL_StatusTypeDef HAL_LPUART_DeInit(LPUART_HandleTypeDef *hlpuart)
+{
+    /* Check  handle */
+    if(!IS_LPUART_INSTANCE(hlpuart->Instance)) return HAL_ERROR;
+    HAL_LPUART_MspDeInit(hlpuart);
+    /* Disable LPUART clock */
+    System_Module_Disable(EN_LPUART);
+    /* Return function status */
+    return HAL_OK;
+}
+/************************************************************************
+ * function   : HAL_LPUART_Wait_TX_Done
+ * Description: wait uart not busy 
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ * return: 0: FAIL; 1: SUCCESS   
+ ************************************************************************/
+HAL_StatusTypeDef HAL_LPUART_Wait_TX_Done(LPUART_HandleTypeDef *hlpuart) 
+{   
+    while (0 == (hlpuart->Instance->SR & (1 << LPUART_SR_TX_FINISH_INDEX) ) ) {};  
+    hlpuart->Instance->SR = (1 << LPUART_SR_TX_FINISH_INDEX);     
+    return HAL_OK;  
+}  
+
+void HAL_LPUART_Output(LPUART_HandleTypeDef *hlpuart, unsigned char c)     
+{
+    if ((hlpuart->Instance->SR) & (1U << LPUART_SR_TX_EMPTY_INDEX) )  
+    {
+        hlpuart->Instance->TXDR = c;  
+    }
+
+    HAL_LPUART_Wait_TX_Done(hlpuart);   
+}
+
+/************************************************************************
+ * function   : uart_send_bytes
+ * Description: uart send bytes
+ * input :
+ *         UINT32 uart_index: Serial port number 
+ *         UINT8* buff: out buffer
+ *         UINT32 length: buffer length
+ * return: none
+ ************************************************************************/
+void HAL_LPUART_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length)    
+{
+    uint32_t i;
+    for (i = 0; i < length; i++)
+    {
+        HAL_LPUART_Output(hlpuart, *buff++);     
+    }
+}
+
+/************************************************************************
+ * function   : HAL_LPUART_Receive_Bytes_Timeout  
+ * Description: uart receive bytes 
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ *         UINT8* buff: out buffer
+ *         UINT32 length: buffer length 
+ *         UINT32 ms: number of ms to delay one byte 
+ * return: received bytes 
+ ************************************************************************/
+uint32_t HAL_LPUART_Receive_Bytes_Timeout(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length, uint32_t ms) 
+{
+    volatile uint32_t i, timeout, count;;    
+    if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) 
+    {
+        return 0;  
+    } 
+    timeout = (System_Get_APBClock() >> 13) * ms;  
+    count = timeout;  
+    i = 0;
+    while(i < length) 
+    {
+        if((hlpuart->rx_read_index) != (hlpuart->rx_write_index)) 
+        {
+            rxbuff[i] = hlpuart->rx_buffer[hlpuart->rx_read_index];  
+            hlpuart->rx_read_index = (((hlpuart->rx_read_index) + 1)%(hlpuart->rx_buffer_size) );   
+            count = timeout;   
+            i++;
+        }
+        else
+        {       
+            if (0 == count)//timeout 
+            {
+                break;  
+            }
+            else
+            {
+                count--;  
+            }
+        }
+    }
+    return i; 
+}     
+/************************************************************************
+ * function   : HAL_LPUART_Receive_Bytes
+ * Description: LPUART receive bytes.
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ *         buff:receive data buff
+ *         length:length of buff
+ * return:length  
+ ************************************************************************/
+uint32_t HAL_LPUART_Receive_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t * rxbuff, uint32_t length) 
+{
+    volatile uint32_t i, ie_backup;       
+    if(0x00 == IS_LPUART_INSTANCE(hlpuart->Instance)) 
+    {
+        return 0;  
+    }
+    ie_backup = hlpuart->Instance->IE;   
+    hlpuart->Instance->IE = 0;  
+    i = 0;
+    while(i < length) 
+    {
+        if( (hlpuart->Instance->SR) & (1U << LPUART_SR_RX_INDEX) ) 
+        {
+            rxbuff[i] = hlpuart->Instance->RXDR; 
+            i++; 
+        }
+    }
+    hlpuart->Instance->IE = ie_backup;    
+    return length; 
+}   
+/************************************************************************
+ * function   : HAL_LPUART_DMA_Send_Bytes
+ * Description: LPUART send bytes by DMA.
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ *         buff:send data buff
+ *         length:length of buff
+ * return:none  
+ ************************************************************************/
+void HAL_LPUART_DMA_Send_Bytes(LPUART_HandleTypeDef *hlpuart, uint8_t *buff, uint32_t length)    
+{
+    hlpuart->Instance->CR |= (1U << LPUART_CR_DMA_EN_INDEX);   
+    hlpuart->tx_busy = 1;   
+    HAL_DMA_Start_IT(hlpuart->dma_tx_handler, (uint32_t)buff, (uint32_t)&hlpuart->Instance->TXDR, length);   
+ }   
+
+/************************************************************************
+ * function   : HAL_LPUART_Clear_Wakeup_Flags
+ * Description: Clear the LPUART STOP wake up flag.
+ * input : 
+ *         UART_HandleTypeDef *huart: pointer to uart handle structure
+ *         Wakeup_Bits:LPUART wakeup flag,could be: LPUART_WAKEUP_RX_BIT    LPUART_WAKEUP_MATCH_BIT    LPUART_WAKEUP_START_BIT
+ * return:none  
+ ************************************************************************/
+
+void HAL_LPUART_Clear_Wakeup_Flags(LPUART_HandleTypeDef *hlpuart, uint32_t Wakeup_Bits)  
+{
+    hlpuart->Instance->SR = Wakeup_Bits;   
+} 
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_OPA.c

@@ -0,0 +1,329 @@
+/*
+  ******************************************************************************
+  * @file    HAL_OPA.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   OPA HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Operational Amplifier (OPA).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************
+ * function   : HAL_OPA_MspInit
+ * Description: OPA MCU specific initiation, such as IO share, module clock, ... 
+ * input      :
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ * return: none
+************************************************************************/
+__weak void HAL_OPA_MspInit(OPA_HandleTypeDef* hopa)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_OPA; 
+
+    /* Enable Clock */
+    System_Module_Enable(EN_OPA);
+        
+    if(hopa->Init.OpaX == OPA1)
+    {
+        /* OPA1 GPIO inition VINP:PC4*/
+        /* OPA1 GPIO inition VINM:PA3*/
+        /* OPA1 GPIO inition OPA1_VOUT:PA2*/
+        GPIO_OPA.Pin            = GPIO_PIN_2 | GPIO_PIN_3;
+        GPIO_OPA.Mode           = GPIO_MODE_ANALOG;
+        GPIO_OPA.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_OPA);
+
+        GPIO_OPA.Pin            = GPIO_PIN_4;
+        GPIO_OPA.Mode           = GPIO_MODE_ANALOG;
+        GPIO_OPA.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOC, &GPIO_OPA);    
+    }
+    
+    else if(hopa->Init.OpaX == OPA2)
+    {
+        /* OPA2 GPIO inition VINP:PA7*/
+        /* OPA2 GPIO inition VINM:PC5*/
+        /* OPA2 GPIO inition OPA2_VOUT:PA6*/
+        GPIO_OPA.Pin            = GPIO_PIN_6 | GPIO_PIN_7;
+        GPIO_OPA.Mode           = GPIO_MODE_ANALOG;
+        GPIO_OPA.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_OPA);
+        
+        GPIO_OPA.Pin            = GPIO_PIN_5;
+        GPIO_OPA.Mode           = GPIO_MODE_ANALOG;
+        GPIO_OPA.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOC, &GPIO_OPA);
+
+    }
+    else if(hopa->Init.OpaX == OPA3)
+    {
+        /* OPA3 GPIO inition VINP:PA4*/
+        /* OPA3 GPIO inition VINM:PB10*/
+        /* OPA3 GPIO inition OPA2_VOUT:PB1*/
+        GPIO_OPA.Pin            = GPIO_PIN_4;
+        GPIO_OPA.Mode           = GPIO_MODE_ANALOG;
+        GPIO_OPA.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOA, &GPIO_OPA);
+        
+        GPIO_OPA.Pin            = GPIO_PIN_1 | GPIO_PIN_10;
+        GPIO_OPA.Mode           = GPIO_MODE_ANALOG;
+        GPIO_OPA.Pull           = GPIO_NOPULL;
+        HAL_GPIO_Init(GPIOB, &GPIO_OPA);
+    }
+}
+
+/************************************************************************
+ * function   : HAL_OPA_MspDeInit
+ * Description: OPA MCU De-initiation, such as IO share, module clock, ... 
+ * input      :
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ * return: none
+************************************************************************/
+__weak void HAL_OPA_MspDeInit(OPA_HandleTypeDef* hopa)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    
+    /* Reset the OPA */
+    System_Module_Reset(RST_OPA);
+    /* Disable Clock */
+    System_Module_Disable(EN_OPA);
+
+}
+
+/************************************************************************
+ * function   : HAL_OPA_Init
+ * Description: opa initial with parameters. 
+ * input : 
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ ************************************************************************/
+HAL_StatusTypeDef HAL_OPA_Init(OPA_HandleTypeDef* hopa)
+{            
+    uint32_t u32RegTemp, u32NvrTrimValue;
+    __IO uint32_t *gu32RegCrx;
+    uint8_t trim_value;
+    
+    /* Check the OPA handle allocation */
+    if (hopa == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR;
+    if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR;
+    if(!IS_OPA_ALL_HSM(hopa->Init.Hsm)) return HAL_ERROR;
+    if(!IS_OPA_ALL_GAIN(hopa->Init.Gain)) return HAL_ERROR;
+    if(!IS_OPA_ALL_POL(hopa->Init.PolSel)) return HAL_ERROR;
+    if(!IS_OPA_ALL_MODE(hopa->Init.OpaMode)) return HAL_ERROR;
+    if(!IS_OPA_ALL_VINP(hopa->Init.VinPSel)) return HAL_ERROR;
+    if(!IS_OPA_ALL_OUT(hopa->Init.OutSel)) return HAL_ERROR;
+    if(!IS_OPA_ALL_VINM0(hopa->Init.VinM0En)) return HAL_ERROR;
+    if(!IS_OPA_ALL_TRIM(hopa->Init.TrimEn)) return HAL_ERROR;
+
+    if(hopa->Init.OpaX == OPA1)
+        gu32RegCrx = &hopa->Instance->OPA1_CSR;
+    else if(hopa->Init.OpaX == OPA2)
+        gu32RegCrx = &hopa->Instance->OPA2_CSR;
+    else if(hopa->Init.OpaX == OPA3)
+        gu32RegCrx = &hopa->Instance->OPA3_CSR;
+
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_OPA_MspInit(hopa);
+    
+    if(READ_BIT(*gu32RegCrx, OPA_CSR_LOCK))
+    {
+        System_Module_Reset(RST_OPA);
+    }
+    
+    u32RegTemp = *gu32RegCrx;
+    
+    u32RegTemp =    ((hopa->Init.Hsm << 28) & OPA_CSR_HSM) | \
+                    ((hopa->Init.Gain << OPA_CSR_GAIN_SEL_POS) & OPA_CSR_GAIN_SEL_MASK) | \
+                    ((hopa->Init.PolSel << OPA_CSR_POL_SEL_POS) & OPA_CSR_POL_SEL_MASK) | \
+                    ((hopa->Init.VinM0En << 20) & OPA_CSR_VINM0_SEL_POS) | \
+                    ((hopa->Init.OpaMode << OPA_CSR_MODE_SEL_POS) & OPA_CSR_MODE_SEL_MASK) | \
+                    ((hopa->Init.VinPSel << OPA_CSR_VINP_SEL_POS) & OPA_CSR_VINP_SEL_MASK) | \
+                    ((hopa->Init.OutSel << OPA_CSR_OUT_SEL_POS) & OPA_CSR_OUT_SEL_MASK);
+    
+    *gu32RegCrx = u32RegTemp;
+
+    /* Enable the opa */
+    SET_BIT(*gu32RegCrx, OPA_CSR_EN); 
+    
+    if(hopa->Init.TrimEn == OPA_CSR_TRIM_ENABLE)
+    {
+        /* Trim the OPA_CSR_CAL_H N channel */    
+        SET_BIT(*gu32RegCrx, OPA_CSR_CAL_NEN);
+        CLEAR_BIT(*gu32RegCrx, OPA_CSR_CAL_PEN);
+        
+        for(trim_value=0;trim_value<31;trim_value++)
+        {
+            MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_OSN_MASK,(trim_value)<<OPA_CSR_TRIM_OSN_POS);
+            System_Delay(1000);
+            if(READ_BIT(*gu32RegCrx,OPA_CSR_CAL_OUT)) break;
+        }        
+        /* Trim the OPA_CSR_CAL_L P channel */    
+        SET_BIT(*gu32RegCrx, OPA_CSR_CAL_PEN);
+        CLEAR_BIT(*gu32RegCrx, OPA_CSR_CAL_NEN);
+        
+        for(trim_value=0;trim_value<31;trim_value++)
+        {
+            MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_OSP_MASK,(trim_value)<<OPA_CSR_TRIM_OSP_POS);
+            System_Delay(1000);
+            if(READ_BIT(*gu32RegCrx,OPA_CSR_CAL_OUT)) break;
+        }    
+    }
+    else
+    {
+        /* Use the Trim value */    
+        u32NvrTrimValue = *(volatile uint32_t*)(0x0008024C+(hopa->Init.OpaX-1)*4); //Read the OPA trim value;
+        if(((~(u32NvrTrimValue>>16))&0xFFFF) != (u32NvrTrimValue&0xFFFF)) return HAL_ERROR;
+        
+        u32NvrTrimValue = u32NvrTrimValue & 0xFFFF;
+            
+        MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_OSN_MASK,((u32NvrTrimValue&0x1F)<<OPA_CSR_TRIM_OSN_POS));
+            
+        MODIFY_REG(*gu32RegCrx,OPA_CSR_TRIM_OSP_MASK,(((u32NvrTrimValue>>5)&0x1F)<<OPA_CSR_TRIM_OSP_POS));    
+    }
+ 
+    /* enable the trim*/    
+    SET_BIT(*gu32RegCrx, OPA_CSR_CAL_PEN);
+    SET_BIT(*gu32RegCrx, OPA_CSR_CAL_NEN);
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_OPA_DeInit
+ * Description: opa De-initial with parameters. 
+ * input : 
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ ************************************************************************/
+HAL_StatusTypeDef HAL_OPA_DeInit(OPA_HandleTypeDef* hopa)
+{                
+    /* Check the OPA handle allocation */
+    if (hopa == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    HAL_OPA_MspDeInit(hopa);
+    
+    memset(&hopa->Init, 0, sizeof(hopa->Init));
+    
+    return HAL_OK;
+}
+/************************************************************************
+ * function   : HAL_OPA_Enable
+ * Description: opa enable. 
+ * input : 
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ ************************************************************************/
+HAL_StatusTypeDef HAL_OPA_Enable(OPA_HandleTypeDef* hopa)
+{    
+    uint32_t u32RegTemp;
+    __IO uint32_t *gu32RegCrx;
+    
+    /* Check the OPA handle allocation */
+    if (hopa == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR;
+    if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR;
+    
+    if(hopa->Init.OpaX == OPA1)
+        gu32RegCrx = &hopa->Instance->OPA1_CSR;
+    else if(hopa->Init.OpaX == OPA2)
+        gu32RegCrx = &hopa->Instance->OPA2_CSR;
+    else if(hopa->Init.OpaX == OPA3)
+        gu32RegCrx = &hopa->Instance->OPA3_CSR;
+        
+    /* Enable the opa */
+    SET_BIT(*gu32RegCrx, OPA_CSR_EN); 
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_OPA_Disable
+ * Description: opa disable. 
+ * input : 
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ ************************************************************************/
+HAL_StatusTypeDef HAL_OPA_Disable(OPA_HandleTypeDef* hopa)
+{        
+    uint32_t u32RegTemp;
+    __IO uint32_t *gu32RegCrx;
+    
+    /* Check the OPA handle allocation */
+    if (hopa == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR;
+    if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR;
+    
+    if(hopa->Init.OpaX == OPA1)
+        gu32RegCrx = &hopa->Instance->OPA1_CSR;
+    else if(hopa->Init.OpaX == OPA2)
+        gu32RegCrx = &hopa->Instance->OPA2_CSR;
+    else if(hopa->Init.OpaX == OPA3)
+        gu32RegCrx = &hopa->Instance->OPA3_CSR;
+            
+    /* Disable the opa */
+    CLEAR_BIT(*gu32RegCrx, OPA_CSR_EN); 
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_OPA_Lock
+ * Description: opa lock. 
+ * input : 
+ *         OPA_HandleTypeDef *hopa: pointer to opa handle structure
+ ************************************************************************/
+HAL_StatusTypeDef HAL_OPA_Lock(OPA_HandleTypeDef* hopa)
+{        
+    uint32_t u32RegTemp;
+    __IO uint32_t *gu32RegCrx;
+    
+    /* Check the OPA handle allocation */
+    if (hopa == NULL)
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Check the parameters */
+    if(!IS_OPA_ALL_INSTANCE(hopa->Instance)) return HAL_ERROR;
+    if(!IS_OPA_ALL_OPAX(hopa->Init.OpaX)) return HAL_ERROR;
+    
+    if(hopa->Init.OpaX == OPA1)
+        gu32RegCrx = &hopa->Instance->OPA1_CSR;
+    else if(hopa->Init.OpaX == OPA2)
+        gu32RegCrx = &hopa->Instance->OPA2_CSR;
+    else if(hopa->Init.OpaX == OPA3)
+        gu32RegCrx = &hopa->Instance->OPA3_CSR;
+            
+    /* Lock the opa */
+    SET_BIT(*gu32RegCrx, OPA_CSR_LOCK); 
+    
+    return HAL_OK;
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_RTC.c

@@ -0,0 +1,485 @@
+/*
+  ******************************************************************************
+  * @file    HAL_RTC.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   RTC HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           + Initialization functions
+  *           + Time and Date configuration
+  *           + Alarm configuration
+  *           + WakeUp Timer configuration
+  *           + TimeStamp configuration
+  *           + Tampers configuration
+  *           + Backup Data Registers configuration
+  *           + RTC Tamper and TimeStamp Pins Selection
+  *           + Interrupts and flags management
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/*********************************************************************************
+* Function    : HAL_RTC_Config
+* Description : Initialize the RTC peripheral
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+HAL_StatusTypeDef HAL_RTC_Config(RTC_ConfigTypeDef *hrtc)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check RTC Parameter */
+    if (!IS_RTC_CLOCKSRC(hrtc->u32_ClockSource))         return HAL_ERROR;
+    if (!IS_RTC_COMPENSATION(hrtc->u32_Compensation))    return HAL_ERROR;
+#endif
+
+    /* RTC domain write enable */
+    SCU->STOPCFG |= (1 << 0);
+
+    PMU->CR1 |= RPMU_CR_RTCEN;
+
+    switch (hrtc->u32_ClockSource)
+    {
+        case RTC_CLOCK_RC32K: 
+        {
+            PMU->ANACR |= RPMU_ANACR_RC32K_EN;
+            while(!(PMU->ANACR & RPMU_ANACR_RC32K_RDY));
+
+            PMU->CR1 &= ~RTC_CLOCK_XTL;
+        }break;
+
+        case RTC_CLOCK_XTL: 
+        {
+            PMU->ANACR = (PMU->ANACR & ~RPMU_ANACR_XTLDRV) | (RPMU_ANACR_XTLDRV_1 | RPMU_ANACR_XTLDRV_0);
+            
+            PMU->ANACR |= RPMU_ANACR_XTLEN;
+            while(!(PMU->ANACR & RPMU_ANACR_XTLRDY));
+
+            PMU->CR1 |= RTC_CLOCK_XTL;
+        }break;
+
+        default: break; 
+    }
+
+    if (hrtc->u32_CompensationValue) 
+    {
+        RTC->ADJUST = hrtc->u32_Compensation | hrtc->u32_CompensationValue;
+    }
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_SetTime
+* Description : Set RTC current time.
+* Input       : fp_Time Pointer to Time structure.
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_SetTime(RTC_TimeTypeDef *fp_Time)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check RTC Parameter */
+    if (!IS_RTC_HOUR(fp_Time->u8_Hours))     return;
+    if (!IS_RTC_MIN(fp_Time->u8_Minutes))    return;
+    if (!IS_RTC_SEC(fp_Time->u8_Seconds))    return;
+#endif
+    
+    /* Write-Protect Disable */
+    RTC->WP = 0xCA53CA53;
+
+    RTC->HOUR = fp_Time->u8_Hours;
+    RTC->MIN  = fp_Time->u8_Minutes;
+    RTC->SEC  = fp_Time->u8_Seconds;
+
+    /* Write-Protect Enable */
+    RTC->WP = 0;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_GetTime
+* Description : Get RTC current time.
+* Input       : fp_Time Pointer to Time structure.
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_GetTime(RTC_TimeTypeDef *fp_Time)
+{
+    fp_Time->u8_Hours   = RTC->HOUR;
+    fp_Time->u8_Minutes = RTC->MIN;
+    fp_Time->u8_Seconds = RTC->SEC;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_SetDate
+* Description : Set RTC current Date.
+* Input       : fp_Date Pointer to Date structure.
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_SetDate(RTC_DateTypeDef *fp_Date)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check RTC Parameter */
+    if (!IS_RTC_YEAR(fp_Date->u8_Year))          return;
+    if (!IS_RTC_MONTH(fp_Date->u8_Month))        return;
+    if (!IS_RTC_DAY(fp_Date->u8_Date))           return;
+    if (!IS_RTC_WEEKDAY(fp_Date->u8_WeekDay))    return;
+#endif
+
+    /* Write-Protect Disable */
+    RTC->WP = 0xCA53CA53;
+
+    RTC->YEAR  = fp_Date->u8_Year;
+    RTC->MONTH = fp_Date->u8_Month;
+    RTC->DATE  = fp_Date->u8_Date;
+    RTC->WEEK  = fp_Date->u8_WeekDay;
+
+    /* Write-Protect Enable */
+    RTC->WP = 0;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_GetDate
+* Description : Get RTC current Date.
+* Input       : fp_Date Pointer to Date structure.
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_GetDate(RTC_DateTypeDef *fp_Date)
+{
+    fp_Date->u8_Year    = RTC->YEAR;
+    fp_Date->u8_Month   = RTC->MONTH;
+    fp_Date->u8_Date    = RTC->DATE;
+    fp_Date->u8_WeekDay = RTC->WEEK;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_AlarmConfig
+* Description : Alarm Config
+* Input       : fp_Alarm Pointer to ALarm structure.
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_AlarmConfig(RTC_AlarmTypeDef *fp_Alarm)
+{
+    uint32_t lu32_WeekDay;
+    
+#if (USE_FULL_ASSERT == 1)
+    /* Check RTC Parameter */
+    if (!IS_RTC_ALARM_MODE(fp_Alarm->u32_AlarmMode))        return;
+    if (!IS_RTC_ALARM_INT(fp_Alarm->u32_AlarmInterrupt))    return;
+    if (!IS_RTC_ALARM_DAY_MASK(fp_Alarm->u32_DayMask))      return;
+    if (!IS_RTC_ALARM_HOUR_MASK(fp_Alarm->u32_HourMask))    return;
+    if (!IS_RTC_ALARM_MIN_MASK(fp_Alarm->u32_MinMask))      return;
+    
+    if (fp_Alarm->u32_AlarmMode == RTC_ALARM_WEEK_MODE) 
+    {
+        if (!IS_RTC_ALARM_WEEKDAY(fp_Alarm->u32_AlarmWeek))    return;
+    }
+    else 
+    {
+        if (!IS_RTC_DAY(fp_Alarm->u32_AlarmDay))    return;
+    }
+    
+    if (!IS_RTC_HOUR(fp_Alarm->u32_Hours))     return;
+    if (!IS_RTC_MIN(fp_Alarm->u32_Minutes))    return;
+    if (!IS_RTC_SEC(fp_Alarm->u32_Seconds))    return;
+#endif
+
+    if (fp_Alarm->u32_AlarmMode == RTC_ALARM_WEEK_MODE) 
+    {
+        lu32_WeekDay = fp_Alarm->u32_AlarmWeek;
+    }
+    else 
+    {
+        lu32_WeekDay = fp_Alarm->u32_AlarmDay;
+    }
+
+    /* Coinfig Week/Day、Hour、Min、Sec */
+    RTC->ALM = fp_Alarm->u32_AlarmMode | lu32_WeekDay | fp_Alarm->u32_Hours << 16 | fp_Alarm->u32_Minutes << 8 | fp_Alarm->u32_Seconds;
+
+    /* Interrupt Enable */
+    if (RTC_ALARM_INT_ENABLE == fp_Alarm->u32_AlarmInterrupt) 
+    {
+        RTC->IE |= RTC_IE_ALM;
+    }
+
+    RTC->CR |= (fp_Alarm->u32_DayMask) ? RTC_ALARM_DAY_MASK_ENABLE : RTC_ALARM_DAY_MASK_DISABLE;
+
+    RTC->CR |= (fp_Alarm->u32_HourMask) ? RTC_ALARM_HOUR_MASK_ENABLE : RTC_ALARM_HOUR_MASK_DISABLE;
+
+    RTC->CR |= (fp_Alarm->u32_MinMask) ? RTC_ALARM_MIN_MASK_ENABLE : RTC_ALARM_MIN_MASK_DISABLE;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_AlarmEnable
+* Description : Alarm Enable
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_AlarmEnable(void)
+{
+    RTC->CR |= RTC_CR_ALM_EN;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_AlarmDisable
+* Description : Alarm Disable
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_AlarmDisable(void)
+{
+    RTC->CR &= ~RTC_CR_ALM_EN;
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_Tamper
+* Description : Temper1 use PC13、Temper2 use PA0
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_Tamper(enum_Temper_t fe_Temper, RTC_TemperTypeDef *fp_Temper)
+{
+#if (USE_FULL_ASSERT == 1)
+    /* Check RTC Parameter */
+    if (!IS_RTC_TEMP_EDGE(fp_Temper->u32_TemperEdge))             return;
+    if (!IS_RTC_TEMP_INT(fp_Temper->u32_InterruptEN))             return;
+    if (!IS_RTC_TEMP_CLEAR_BACKUP(fp_Temper->u32_ClearBackup))    return;
+    if (!IS_RTC_TEMP_FILTER(fp_Temper->u32_Filter))               return;
+#endif
+
+    switch (fe_Temper)
+    {
+        case RTC_TEMPER_1: 
+        {
+            PMU->IOCR  &= ~0x40;  // Configure PC13 as digital IO   
+            PMU->IOSEL |=  0x02;  // Configure PC13 as tamper function   
+            
+            /* Clear Config */
+            RTC->CR &= ~(RTC_CR_TAMP1RCLR | RTC_CR_TAMP1FCLR | RTC_CR_TAMP1FLTEN | RTC_CR_TAMP1FLT | RTC_CR_TS1EDGE | RTC_CR_TAMPFLTCLK);
+            /* Edge select */
+            RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TS1EDGE : 0x00;
+            /* Auto clear backup register */
+            if (fp_Temper->u32_ClearBackup) 
+            {
+                RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TAMP1FCLR : RTC_CR_TAMP1RCLR;
+            }
+            /* Temper filter */
+            if (fp_Temper->u32_Filter) 
+            {
+                if (fp_Temper->u32_Filter == RTC_TEMP_FILTER_512_RTCCLK) 
+                {
+                    RTC->CR |= RTC_CR_TAMPFLTCLK;
+                }
+                else 
+                {
+                    RTC->CR |= (fp_Temper->u32_Filter - 2) << 13;
+                }
+            }  
+            
+            RTC->CR |= RTC_CR_TAMP1EN;  
+            System_Delay(2000);       
+            RTC->SR |= (RTC_SR_STP1FIE|RTC_SR_STP1RIE);   
+            RTC->IE &= (~(RTC_IE_STP1FIE|RTC_IE_STP1RIE));      
+            
+            /* Put Temper Interrupt enable here !!!*/   
+            if (fp_Temper->u32_InterruptEN) 
+            {
+                RTC->IE |= fp_Temper->u32_TemperEdge ? RTC_IE_STP1FIE : RTC_IE_STP1RIE;
+            }               
+ 
+        }break;
+        
+        case RTC_TEMPER_2:
+        {
+            /* Clear Config */
+            RTC->CR &= ~(RTC_CR_TAMP2RCLR | RTC_CR_TAMP2FCLR | RTC_CR_TAMP2FLTEN | RTC_CR_TAMP2FLT | RTC_CR_TS2EDGE | RTC_CR_TAMPFLTCLK);
+            /* Edge select */
+            RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TS2EDGE : 0x00;
+            /* Auto clear backup register */
+            if (fp_Temper->u32_ClearBackup) 
+            {
+                RTC->CR |= fp_Temper->u32_TemperEdge ? RTC_CR_TAMP2FCLR : RTC_CR_TAMP2RCLR;
+            }
+            /* Temper filter */
+            if (fp_Temper->u32_Filter) 
+            {
+                if (fp_Temper->u32_Filter == RTC_TEMP_FILTER_512_RTCCLK) 
+                {
+                    RTC->CR |= RTC_CR_TAMPFLTCLK;
+                }
+                else 
+                {
+                    RTC->CR |= (fp_Temper->u32_Filter - 2) << 19;
+                }
+            }
+            
+            RTC->CR |= RTC_CR_TAMP2EN;  
+            System_Delay(2000);     
+            RTC->SR |= (RTC_SR_STP2FIE|RTC_SR_STP2RIE);   
+            RTC->IE &= (~(RTC_IE_STP2FIE|RTC_IE_STP2RIE));  
+            
+            /* Temper Interrupt */
+            if (fp_Temper->u32_InterruptEN) 
+            {
+                RTC->IE |= fp_Temper->u32_TemperEdge ? RTC_IE_STP2FIE : RTC_IE_STP2RIE;
+            }
+
+        }break;
+
+        default: break; 
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_TamperEnable
+* Description : 
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_TamperEnable(enum_Temper_t fe_Temper)
+{
+    if (fe_Temper == RTC_TEMPER_1) 
+    {
+        RTC->CR |= RTC_CR_TAMP1EN;
+    }
+    else 
+    {
+        RTC->CR |= RTC_CR_TAMP2EN;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_TamperDisable
+* Description : 
+* Input       : 
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+**********************************************************************************/
+void HAL_RTC_TamperDisable(enum_Temper_t fe_Temper)
+{
+    if (fe_Temper == RTC_TEMPER_1) 
+    {
+        RTC->CR &= ~RTC_CR_TAMP1EN;
+    }
+    else 
+    {
+        RTC->CR &= ~RTC_CR_TAMP2EN;
+    }
+}
+
+/***************************************************************************************************
+* Function    : HAL_RTC_Standby_Wakeup
+* Description : wakeup source select
+* Input       : fu32_Edge 0: Rising edge
+*                         1: Falling edge
+*               fe_Wakeup  : wakeup source select, STANDBY_WAKEUP_RISING, STANDBY_WAKEUP_FALLING  
+* Outpu       : 
+* Author      : Chris_Kyle                         Data : 2020定
+*******************************************************************************************************/
+void HAL_RTC_Standby_Wakeup(enum_WKUP_t fe_Wakeup, uint32_t fu32_Edge)
+{
+    switch (fe_Wakeup)
+    {
+        case RTC_WAKEUP_WKUP1: 
+        case RTC_WAKEUP_WKUP2: 
+        case RTC_WAKEUP_WKUP3: 
+        case RTC_WAKEUP_WKUP4: 
+        case RTC_WAKEUP_WKUP5: 
+        case RTC_WAKEUP_WKUP6:   
+        {
+            /* Clear flags、Standby Enable */
+            PMU->CR1 |= RPMU_CR_STB_EN | RPMU_CR_CWUF | RPMU_CR_CSBF;
+
+            /* Wakeup IO Filter Enable */
+            PMU->CR1 |= fe_Wakeup << 8;
+            /* Wakeup IO Enable */
+            PMU->CR1 |= fe_Wakeup;
+
+            if (fe_Wakeup == RTC_WAKEUP_WKUP2) 
+            {
+                /* PC13 */
+                PMU->IOCR &= ~0x40;  // must configure PC13 as digital function     
+            }
+            
+            if (fu32_Edge) 
+            {
+                PMU->CR2 |= fe_Wakeup >> 16;
+            }
+            else 
+            {
+                PMU->CR2 &= ~(fe_Wakeup >> 16);   
+            }
+
+            PMU->CR1 |= RPMU_CR_CWUF; // clear wakeup flag     
+            System_Enter_Standby_Mode();              
+        }break;
+
+        case RTC_WAKEUP_STAMP2:
+        case RTC_WAKEUP_STAMP1:
+        case RTC_WAKEUP_32S:
+        case RTC_WAKEUP_SEC:
+        case RTC_WAKEUP_MIN:
+        case RTC_WAKEUP_HOUR:
+        case RTC_WAKEUP_DATE:     
+        {
+            /* Clear flags、Standby Enable */
+            PMU->CR1 |= RPMU_CR_STB_EN | RPMU_CR_CWUF | RPMU_CR_CSBF;
+
+            RTC->SR |= fe_Wakeup;
+            RTC->IE |= fe_Wakeup;
+
+            System_Enter_Standby_Mode();  
+        }break;
+
+        default: break; 
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_GetStandbyStatus
+* Description : Check MCU have entered standby mode
+* Input       : 
+* Outpu       : 0: Not Enter Standby Mode
+                1: Entered Standby Mode
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+bool HAL_RTC_Get_StandbyStatus(void)
+{
+    if (PMU->SR & RPMU_SR_SBF) 
+    {
+        return true;
+    }
+    else 
+    {
+        return false;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_RTC_Get_StandbyWakeupSource
+* Description : Get MCU Standby Wakeup Source
+* Input       : 
+* Outpu       : RTC_WAKEUP_SOURCE_BORWUF
+                RTC_WAKEUP_SOURCE_IWDTWUF
+                RTC_WAKEUP_SOURCE_RSTWUF
+                RTC_WAKEUP_SOURCE_RTCWUF
+                RTC_WAKEUP_SOURCE_WKUP6
+                RTC_WAKEUP_SOURCE_WKUP5
+                RTC_WAKEUP_SOURCE_WKUP4
+                RTC_WAKEUP_SOURCE_WKUP3
+                RTC_WAKEUP_SOURCE_WKUP2
+                RTC_WAKEUP_SOURCE_WKUP1
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+uint32_t HAL_RTC_Get_StandbyWakeupSource(void)
+{
+    return PMU->SR;
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_SPI.c

@@ -0,0 +1,1080 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Spi.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Serial Peripheral Interface (SPI) peripheral.
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include  "ACM32Fxx_HAL.h" 
+
+#define SPI_RX_TIMEOUT    2000
+#define SPI_TX_DMA_TIMEOUT    2000
+volatile uint32_t lu32_ReceiveTimeOut = SPI_RX_TIMEOUT;
+volatile uint32_t lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT;
+/************************************************************************
+ * function   : HAL_SPI_IRQHandler
+ * Description: This function handles SPI interrupt request.
+ * input      : hspi : pointer to a SPI_HandleTypeDef structure that contains
+ *                     the configuration information for SPI module
+ ************************************************************************/
+__weak void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
+{
+    uint8_t lu8_TempValue = 0;
+    
+    uint32_t lu32_Length = 0;
+    
+    /* 
+      NOTE : This function should be modified by the user.
+    */    
+    if ( (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) && ((hspi->Instance->IE) & SPI_STATUS_RX_NOT_EMPTY) )
+    {
+        /* In master mode */
+        if (hspi->Instance->CTL & SPI_CTL_MST_MODE)
+        {
+            while (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY)
+            {
+                hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
+                
+                if (hspi->Rx_Count >= hspi->Rx_Size) 
+                {
+                    /* Wait Transmit Done */
+                    while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE));
+                    
+                    /* Clear Batch Done Flag  */
+                    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+                    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+                    /* Rx Disable */
+                    hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+
+                    /* Receive End */
+                    hspi->Instance->CS &= (~SPI_CS_CS0);
+
+
+                    /* Disable Rx Not Empty Interrupt */
+                    CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY);
+                    
+                    if(hspi->Instance == SPI1)
+                        NVIC_ClearPendingIRQ(SPI1_IRQn);
+                    else if(hspi->Instance == SPI2)
+                        NVIC_ClearPendingIRQ(SPI2_IRQn);
+                    else if(hspi->Instance == SPI3)
+                        NVIC_ClearPendingIRQ(SPI3_IRQn);
+                    else if(hspi->Instance == SPI4)
+                        NVIC_ClearPendingIRQ(SPI4_IRQn);
+                    
+                    /* Clear Batch Done Flag  */
+                    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+                    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+                    
+                    /* Set machine is DILE */
+                    hspi->RxState = SPI_RX_STATE_IDLE;
+                }
+            }
+        }
+        /* In Slave mode */
+        else 
+        {
+            while ((hspi->Rx_Count < hspi->Rx_Size) && (lu32_ReceiveTimeOut > 0) )   
+            {
+                if (hspi->Instance->STATUS & SPI_STATUS_RX_NOT_EMPTY) 
+                {
+                    hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
+                    lu32_ReceiveTimeOut = SPI_RX_TIMEOUT;       //If recieve data, Reset the timeout value  
+                }
+                else
+                {
+                    lu32_ReceiveTimeOut--;   
+                }
+                
+            }
+
+            /* Rx Disable */
+            hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+            
+            /* Disable Rx Not Empty Interrupt */
+            CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY);
+            
+            if(hspi->Instance == SPI1)
+                NVIC_ClearPendingIRQ(SPI1_IRQn);
+            else if(hspi->Instance == SPI2)
+                NVIC_ClearPendingIRQ(SPI2_IRQn);
+            else if(hspi->Instance == SPI3)
+                NVIC_ClearPendingIRQ(SPI3_IRQn);
+            else if(hspi->Instance == SPI4)
+                NVIC_ClearPendingIRQ(SPI4_IRQn);
+            
+            /* Clear Batch Done Flag  */
+            SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+            SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+            
+            /* Set machine is DILE */
+            hspi->RxState = SPI_RX_STATE_IDLE;
+        }
+    }
+    
+    if ( (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_HALF_EMPTY) && ((hspi->Instance->IE) & SPI_IE_TX_FIFO_HALF_EMPTY_EN) )
+    {
+        while (hspi->Tx_Count < hspi->Tx_Size)   
+        {
+            if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL))
+            {
+                hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
+            }
+            else
+            {
+                break;   
+            }
+            
+        }
+        /* Clear Tx FIFO half empty Flag  */
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY);
+        if(hspi->Tx_Count == hspi->Tx_Size)
+        {
+            /* Disable Tx FIFO half empty Interrupt  */
+            CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN);
+        }                
+    }
+    if ((hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_IE_TX_BATCH_DONE_EN) )     
+    {
+        /* Clear Batch Done Flag  */
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+        /* Disable TX Batch Done Interrupt */
+        CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE);
+        /* Disable Tx FIFO half empty Interrupt  */
+        CLEAR_BIT(hspi->Instance->IE, SPI_IE_TX_FIFO_HALF_EMPTY_EN);
+            
+        if(hspi->Instance == SPI1)
+            NVIC_ClearPendingIRQ(SPI1_IRQn);
+        else if(hspi->Instance == SPI2)
+            NVIC_ClearPendingIRQ(SPI2_IRQn);
+        else if(hspi->Instance == SPI3)
+            NVIC_ClearPendingIRQ(SPI3_IRQn);
+        else if(hspi->Instance == SPI4)
+            NVIC_ClearPendingIRQ(SPI4_IRQn);
+        
+        lu32_TX_DMA_TimeOut = SPI_TX_DMA_TIMEOUT;   
+        while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY)
+        {
+             lu32_TX_DMA_TimeOut--;
+             if(0 == lu32_TX_DMA_TimeOut) 
+             {
+                 break;  
+             }
+        }
+
+        /* Tx Disable */
+        hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);  
+        hspi->Instance->TX_CTL &= (~SPI_TX_CTL_DMA_REQ_EN);         
+        
+        if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) 
+        {
+            /* Transmit End */
+            hspi->Instance->CS &= (~SPI_CS_CS0);
+        }
+        
+        /* Tx Disable */
+        hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
+
+        hspi->TxState = SPI_TX_STATE_IDLE;
+    }
+
+    if ( (hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE) && ((hspi->Instance->IE) & SPI_STATUS_RX_BATCH_DONE) )         
+    {
+        /* Clear Batch Done Flag  */
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+        /* Disable RX Batch Done Interrupt */
+        CLEAR_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE);
+
+        if(hspi->Instance == SPI1)
+            NVIC_ClearPendingIRQ(SPI1_IRQn);
+        else if(hspi->Instance == SPI2)
+            NVIC_ClearPendingIRQ(SPI2_IRQn);
+        else if(hspi->Instance == SPI3)
+            NVIC_ClearPendingIRQ(SPI3_IRQn);
+        else if(hspi->Instance == SPI4)
+            NVIC_ClearPendingIRQ(SPI4_IRQn);
+
+        /* Rx Disable */
+        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_DMA_REQ_EN); 
+        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+
+        if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) 
+        {
+            /* Receive End */
+            hspi->Instance->CS &= (~SPI_CS_CS0);
+        }
+
+        hspi->RxState = SPI_RX_STATE_IDLE;
+    }
+}
+
+/************************************************************************
+ * function   : HAL_SPI_MspInit
+ * Description: 
+ * input      : hspi : pointer to a SPI_HandleTypeDef structure that contains
+ *                     the configuration information for SPI module
+ ************************************************************************/
+__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    GPIO_InitTypeDef GPIO_Handle; 
+    
+    /* SPI1 */
+    if (hspi->Instance == SPI1)
+    {
+    }
+    /* SPI2 */
+    else if (hspi->Instance == SPI2) 
+    {
+    }
+    /* SPI3 */
+    else if (hspi->Instance == SPI3)
+    {
+        /* Enable Clock */
+        System_Module_Enable(EN_SPI3);
+        
+        /* SPI3 CS   PortA Pin15 */
+        /* SPI3 CLK  PortC Pin10 */
+        /* SPI3 MOSI PortC Pin12 */
+        /* SPI3 MISO PortC Pin11 */
+        GPIO_Handle.Pin            = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
+        GPIO_Handle.Mode           = GPIO_MODE_AF_PP;
+        GPIO_Handle.Pull           = GPIO_PULLUP;
+        GPIO_Handle.Alternate      = GPIO_FUNCTION_3;
+        HAL_GPIO_Init(GPIOC, &GPIO_Handle);
+
+        GPIO_Handle.Pin            = GPIO_PIN_15;
+        GPIO_Handle.Mode           = GPIO_MODE_AF_PP;
+        GPIO_Handle.Pull           = GPIO_PULLUP;
+        GPIO_Handle.Alternate      = GPIO_FUNCTION_5;
+        HAL_GPIO_Init(GPIOA, &GPIO_Handle);
+        
+        if (hspi->Init.X_Mode == SPI_4X_MODE) 
+        {
+            /* SPI3 IO3 PortC Pin8 */
+            /* SPI3 IO2 PortC Pin9 */
+            GPIO_Handle.Pin            = GPIO_PIN_8 | GPIO_PIN_9;
+            GPIO_Handle.Mode           = GPIO_MODE_AF_PP;
+            GPIO_Handle.Pull           = GPIO_PULLUP;
+            GPIO_Handle.Alternate       = GPIO_FUNCTION_3;
+            HAL_GPIO_Init(GPIOC, &GPIO_Handle);
+        }
+        
+        /* Clear Pending Interrupt */
+        NVIC_ClearPendingIRQ(SPI3_IRQn);
+        
+        /* Enable External Interrupt */
+        NVIC_EnableIRQ(SPI3_IRQn);
+    }
+}
+
+/************************************************************************
+ * function   : HAL_SPI_MspDeInit
+ * Description: SPI De-Initialize the SPI clock, GPIO, IRQ.
+ * input      : hspi : pointer to a SPI_HandleTypeDef structure that contains
+ *                     the configuration information for SPI module
+ ************************************************************************/
+__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
+{
+    /* 
+      NOTE : This function should be modified by the user.
+    */
+    
+    /* For Example */
+    
+    /* SPI1 */
+    if (hspi->Instance == SPI1)
+    {
+    }
+    /* SPI2 */
+    else if (hspi->Instance == SPI2) 
+    {
+    }
+    /* SPI3 */
+    else if (hspi->Instance == SPI3)
+    {
+        /* Disable Clock */
+        System_Module_Disable(EN_SPI3);
+        
+        /* Reset the used GPIO to analog */
+        HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12);
+        HAL_GPIO_DeInit(GPIOA, GPIO_PIN_15);
+
+        if (hspi->Init.X_Mode == SPI_4X_MODE) 
+        {
+            HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8 | GPIO_PIN_9);
+        }
+        
+        /* Clear Pending Interrupt */
+        NVIC_ClearPendingIRQ(SPI3_IRQn);
+        
+        /* Disable External Interrupt */
+        NVIC_DisableIRQ(SPI3_IRQn);
+    }
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Init 
+ * Description: SPI initial with parameters. 
+ * input      : hspi : pointer to a SPI_HandleTypeDef structure that contains
+ *                     the configuration information for SPI module
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
+{
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))                         return HAL_ERROR;
+    if (!IS_SPI_ALL_MODE(hspi->Init.SPI_Mode))                        return HAL_ERROR;
+    if (!IS_SPI_WORK_MODE(hspi->Init.SPI_Work_Mode))                  return HAL_ERROR;
+    if (!IS_SPI_X_MODE(hspi->Init.X_Mode))                            return HAL_ERROR;
+    if (!IS_SPI_FIRST_BIT(hspi->Init.First_Bit))                      return HAL_ERROR;
+    if (!IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRate_Prescaler))    return HAL_ERROR;
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_SPI_MspInit(hspi);
+    
+    /* Automatic change direction */
+    hspi->Instance->CTL |= (SPI_CTL_IO_MODE);
+    
+    /* Set SPI Work mode */
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
+    {
+        SET_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE);
+    }
+    else 
+    {
+        CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_MST_MODE);
+        
+        hspi->Instance->BATCH = (hspi->Instance->BATCH & (~0x000FFFFFU)) | (1 << 0);
+        
+        hspi->Instance->TX_CTL |= SPI_TX_CTL_MODE | (0x88 << 8);  // dummy data = 0x88  
+        
+        if (hspi->Init.X_Mode != SPI_1X_MODE) 
+        {
+            hspi->Instance->CTL |= SPI_CTL_SFILTER;
+        }
+        
+        /* Slave Alternate Enable */
+        hspi->Instance->CTL |= SPI_CTL_SLAVE_EN;
+        
+        /* Slave Mode Enable Rx By Default */
+        hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
+    }
+
+    /* Set SPI First Bit */
+    if (hspi->Init.First_Bit == SPI_FIRSTBIT_LSB)
+        SET_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST);
+    else
+        CLEAR_BIT(hspi->Instance->CTL, SPI_CTL_LSB_FIRST);
+
+    /* Set SPI Work Mode */
+    hspi->Instance->CTL = ((hspi->Instance->CTL) & (~(SPI_CTL_CPHA | SPI_CTL_CPOL))) | (hspi->Init.SPI_Work_Mode);
+    
+    /* Set SPI X_Mode */
+    hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | (hspi->Init.X_Mode);
+
+    /* Set SPI BaudRate Prescaler */
+    hspi->Instance->BAUD = ((hspi->Instance->BAUD) & (~0x0000FFFF)) | (hspi->Init.BaudRate_Prescaler);
+
+    /* Disable All Interrupt */
+    hspi->Instance->IE = 0x00000000;
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_DeInit 
+ * Description: De-Initialize the SPI peripheral. 
+ * input      : hspi : pointer to a SPI_HandleTypeDef structure that contains
+ *                     the configuration information for SPI module
+ * return     : HAL_StatusTypeDef : HAL status
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
+{
+    /* Check the SPI handle allocation */
+    if (hspi == NULL)
+    {
+    return HAL_ERROR;
+    }
+
+    /* Check SPI Instance parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))   return HAL_ERROR;
+
+    hspi->RxState = SPI_RX_STATE_IDLE;
+    hspi->TxState = SPI_TX_STATE_IDLE;
+
+    /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
+    HAL_SPI_MspDeInit(hspi);
+
+    hspi->Rx_Size = 0;
+    hspi->Tx_Size = 0;
+    hspi->Rx_Count = 0;
+    hspi->Tx_Count = 0;
+
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Transmit
+ * Description: Transmits an amount of data in blocking mode.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pData : Pointer to data buffer
+ *              Size  : Amount of data to be sent
+ *              Timeout : Transmit Timeout
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+    HAL_StatusTypeDef Status = HAL_OK;
+    __IO uint32_t uiTimeout;
+
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    if(!Size)    return HAL_ERROR;
+    if (pData == NULL)    return HAL_ERROR;
+    
+    hspi->Tx_Count = 0;
+    hspi->Tx_Size = Size;
+    hspi->Tx_Buffer = pData;
+    
+    uiTimeout = Timeout;
+
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+    
+    /* Clear TX FIFO */
+    SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
+    CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
+    
+    /* Set Data Size */
+    hspi->Instance->BATCH = Size;
+    
+    /* Tx Enable */
+    hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
+
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) 
+    {
+        /* Transmit Start */
+        hspi->Instance->CS |= SPI_CS_CS0;
+    }
+    else
+    {
+        /* Rx Disable */
+        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+    }
+    
+    while(hspi->Tx_Size > 0)
+    {
+        /* Wait Tx FIFO Not Full */
+        while (hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)
+        {
+            if(uiTimeout)
+            {
+                uiTimeout--;
+                if (uiTimeout == 0)
+                {
+                    Status = HAL_TIMEOUT;
+                    goto End;
+                }
+            }
+        }        
+        hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
+        hspi->Tx_Size--;
+        uiTimeout = Timeout;
+    }
+    
+    if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) 
+    {
+        /* Wait Transmit Done */
+        while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BUSY));
+        while (hspi->Instance->STATUS & SPI_STATUS_TX_BUSY)
+        {
+            if(uiTimeout)
+            {
+                uiTimeout--;
+                if (uiTimeout == 0)
+                {
+                    Status = HAL_TIMEOUT;
+                    goto End;
+                }
+            }
+        }
+    }
+    else
+    {
+        /* Wait Transmit Done */
+        while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE));
+        Status = HAL_OK;
+    }
+    
+End:
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+    /* Tx Disable */
+    hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
+    
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)  
+    {
+        /* Transmit End */
+        hspi->Instance->CS &= (~SPI_CS_CS0);
+    }
+
+    return Status;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Transmit_DMA
+ * Description: Transmits an amount of data in blocking mode with DMA.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pData : Pointer to data buffer
+ *              Size  : Amount of data to be sent
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
+{
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    
+    /* Rx machine is running */
+    if (hspi->TxState != SPI_TX_STATE_IDLE) 
+    {
+        return HAL_ERROR;
+    }
+    /* Set machine is Sending */
+    hspi->TxState = SPI_TX_STATE_SENDING;
+
+
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+    
+    /* Enable Tx Batch Done Interrupt */
+    SET_BIT(hspi->Instance->IE, SPI_STATUS_TX_BATCH_DONE);
+    
+    /* Set Data Size */
+    hspi->Instance->BATCH = Size;
+    
+    /* Tx FIFO */
+    hspi->Instance->TX_CTL &= ~SPI_TX_CTL_DMA_LEVEL;
+    hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_LEVEL_0;    
+
+    /* Tx Enable */
+    hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
+    
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
+    {
+        /* Transmit Start */
+        hspi->Instance->CS |= SPI_CS_CS0;
+    }
+    else
+    {
+        /* Rx Disable */
+        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+    }
+    
+    HAL_DMA_Start(hspi->HDMA_Tx, (uint32_t)pData, (uint32_t)&hspi->Instance->DAT, Size);
+
+    hspi->Instance->TX_CTL |= SPI_TX_CTL_DMA_REQ_EN;  
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Receive
+ * Description: Receive an amount of data in blocking mode.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pData : Pointer to data buffer
+ *              Size  : Amount of data to be Receive
+ *              Timeout  : Receive Timeout
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+    HAL_StatusTypeDef Status = HAL_OK;
+    __IO uint32_t uiTimeout;
+    
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    if (pData == NULL)    return HAL_ERROR;
+    
+    hspi->Rx_Count = 0;
+    hspi->Rx_Size = Size;
+    hspi->Rx_Buffer = pData;
+    uiTimeout = Timeout;
+    
+    if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) 
+    {
+        hspi->Instance->BATCH = 1;
+        /* Rx Enable */
+        hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
+        
+        while ( hspi->Rx_Size > 0) 
+        { 
+            while (READ_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_FIFO_EMPTY))
+            {
+                if(uiTimeout)
+                {
+                    uiTimeout--;
+                    if (uiTimeout == 0) 
+                    {
+                        /* Rx Disable */
+                        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+                        return HAL_TIMEOUT;
+                    }
+                }
+            }           
+            
+            hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
+            hspi->Rx_Size--;
+            uiTimeout = Timeout;
+        }
+
+        /* Rx Disable */
+        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+
+        return HAL_OK;
+    }
+
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+    
+    /* Set Data Size */
+    hspi->Instance->BATCH = Size;
+    
+    /* Rx Enable */
+    hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
+    
+    /* Receive Start */
+    hspi->Instance->CS |= SPI_CS_CS0;
+    
+    while(hspi->Rx_Size > 0)
+    {
+        /* have no timeout */
+        if (uiTimeout == 0) 
+        {
+            /* Wait Rx FIFO Not Empty */
+            while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY);
+        }
+        else
+        {
+            while (hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)
+            {
+                if (uiTimeout-- == 0) 
+                {
+                    Status = HAL_TIMEOUT;
+                    goto End; 
+                }
+            }
+        }
+        
+        hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
+        hspi->Rx_Size--;
+    }
+
+    Status = HAL_OK;
+    
+    /* Wait Transmit Done */
+    while (!(hspi->Instance->STATUS & SPI_STATUS_RX_BATCH_DONE));
+
+End:   
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+    /* Rx Disable */
+    hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+
+    /* Receive End */
+    hspi->Instance->CS &= (~SPI_CS_CS0);
+    
+    return Status;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Receive_DMA
+ * Description: Receive an amount of data in blocking mode with DMA.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pData : Pointer to data buffer
+ *              Size  : Amount of data to be Receive
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
+{
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    
+    /* Rx machine is running */
+    if (hspi->RxState != SPI_RX_STATE_IDLE) 
+    {
+        return HAL_ERROR;
+    }
+    /* Set Slave machine is receiving */
+    hspi->RxState = SPI_RX_STATE_RECEIVING;
+
+
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+    /* Enable Rx Batch Done Interrupt */
+    SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_BATCH_DONE);
+
+    /* Set Data Size */
+    hspi->Instance->BATCH = Size;
+
+    /* Rx Enable */
+    hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
+    /* Rx FIFO */
+    hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_LEVEL_0;
+
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) 
+    {
+        /* Receive Start */
+        hspi->Instance->CS |= SPI_CS_CS0;
+    }
+
+    HAL_DMA_Start(hspi->HDMA_Rx, (uint32_t)&hspi->Instance->DAT, (uint32_t)pData, Size);
+    
+    hspi->Instance->RX_CTL |= SPI_RX_CTL_DMA_REQ_EN; 
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Wire_Config
+ * Description: SPI Wire Config
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              Mode : This parameter can be a value of @ref X_MODE
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Wire_Config(SPI_HandleTypeDef *hspi, uint32_t X_Mode)
+{
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    
+    /* Set SPI X_Mode */
+    hspi->Instance->CTL = ((hspi->Instance->CTL) & (~SPI_CTL_X_MODE)) | X_Mode;
+    
+    return HAL_OK;
+}
+/************************************************************************
+ * function   : HAL_SPI_Transmit_IT
+ * Description: Transmit an amount of data in blocking mode with interrupt.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pData : Pointer to data buffer
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
+{
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    
+    /* Tx machine is running */
+    if (hspi->TxState != SPI_TX_STATE_IDLE) 
+    {
+        return HAL_ERROR;
+    }
+    
+    hspi->Tx_Size   = Size;
+    hspi->Tx_Buffer = pData; 
+    hspi->Tx_Count = 0;   
+
+    /* Set machine is Sending */
+    hspi->TxState = SPI_TX_STATE_SENDING;
+    
+    /* Clear TX FIFO */
+    SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
+    CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
+    
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+    
+    /* Set Data Size */
+    hspi->Instance->BATCH = Size;
+
+    /* Tx Enable */
+    hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
+
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
+    {
+        /* Transmit Start */
+        hspi->Instance->CS |= SPI_CS_CS0;
+    }
+    else
+    {
+        /* Rx Disable */
+        hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+    }
+    
+    while (hspi->Tx_Count < hspi->Tx_Size)   
+    {
+        if (!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL))
+            hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
+        else
+            break;           
+    }
+    /* Clear Tx FIFO half empty Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_FIFO_HALF_EMPTY);
+
+
+    /* Enable Tx FIFO half empty Interrupt and Tx batch done Interrupt*/
+    SET_BIT(hspi->Instance->IE, (SPI_IE_TX_FIFO_HALF_EMPTY_EN | SPI_IE_TX_BATCH_DONE_EN));
+
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_Receive_IT
+ * Description: Receive an amount of data in blocking mode with interrupt.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pData : Pointer to data buffer
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint32_t Size)
+{
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    
+    /* Rx machine is running */
+    if (hspi->RxState != SPI_RX_STATE_IDLE) 
+    {
+        return HAL_ERROR;
+    }
+    
+    /* Set Slave machine is receiving */
+    hspi->RxState = SPI_RX_STATE_RECEIVING;
+    
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER)
+    {
+        /* Clear Batch Done Flag  */
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_RX_BATCH_DONE);
+        SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+        
+        /* Set Data Size */
+        hspi->Instance->BATCH = Size;
+        
+        /* Rx Enable */
+        hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
+        
+        /* Receive Start */
+        hspi->Instance->CS |= SPI_CS_CS0;
+    }
+    else
+    {
+        /* Reset BATCH register */
+        hspi->Instance->BATCH = 1;
+        hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;   
+    }
+
+    hspi->Rx_Size   = Size;
+    hspi->Rx_Buffer = pData; 
+    hspi->Rx_Count = 0;   
+    lu32_ReceiveTimeOut = SPI_RX_TIMEOUT;   
+
+    /* Enable Rx FIFO Not Empty Interrupt */
+    SET_BIT(hspi->Instance->IE, SPI_STATUS_RX_NOT_EMPTY);
+    
+    return HAL_OK;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_TransmitReceive
+ * Description: Transmits and recieve an amount of data in blocking mode.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ *              pTxData : Pointer to transmit data buffer
+ *              pRxData : Pointer to recieve data buffer
+ *              Size  : Amount of data to be sent
+ *              Timeout  : TransmitReceive Timeout
+ ************************************************************************/
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint32_t Size, uint32_t Timeout)
+{
+    uint32_t i;
+    __IO uint32_t TxFlag = 1U, uiTimeout;
+    HAL_StatusTypeDef Status = HAL_OK;
+
+    /* Check SPI Parameter */
+    if (!IS_SPI_ALL_INSTANCE(hspi->Instance))    return HAL_ERROR;
+    if ((pTxData == NULL)||(pRxData == NULL))    return HAL_ERROR;
+    
+    hspi->Tx_Count = 0;
+    hspi->Rx_Count = 0;
+    hspi->Tx_Buffer = pTxData;
+    hspi->Rx_Buffer = pRxData;
+    hspi->Tx_Size = Size;   
+    hspi->Rx_Size = Size;   
+    uiTimeout = Timeout;
+    
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+    /* Tx Enable */
+    hspi->Instance->TX_CTL |= SPI_TX_CTL_EN;
+
+    /* Rx Enable */
+    hspi->Instance->RX_CTL |= SPI_RX_CTL_EN;
+
+    /* Clear TX FIFO */
+    SET_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
+    CLEAR_BIT(hspi->Instance->TX_CTL, SPI_TX_CTL_FIFO_RESET);
+    
+        
+    if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) 
+    {        
+        hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
+        hspi->Tx_Size--;
+        TxFlag = 0;
+    }
+    else
+    {       
+        /* Set Data Size */
+        hspi->Instance->BATCH = hspi->Tx_Size;
+
+        /* Transmit Start */
+        hspi->Instance->CS |= SPI_CS_CS0;
+        TxFlag = 1;
+    }
+    
+    while((hspi->Tx_Size>0) || (hspi->Rx_Size>0))
+    {
+        if (hspi->Init.SPI_Mode == SPI_MODE_SLAVE) 
+        {
+            /* Wait Rx FIFO Not Empty */
+            if((!(hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0))
+            {
+                hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
+                hspi->Rx_Size--;
+                TxFlag = 1U;
+            }        
+            /* Wait Tx FIFO Not Full */
+            if((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U))
+            {
+                hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
+                hspi->Tx_Size--;
+                TxFlag = 0;
+            }
+        }
+        else
+        {
+            /* Wait Tx FIFO Not Full */
+            if((!(hspi->Instance->STATUS & SPI_STATUS_TX_FIFO_FULL)) && (hspi->Tx_Size>0) && (TxFlag == 1U))
+            {
+                hspi->Instance->DAT = hspi->Tx_Buffer[hspi->Tx_Count++];
+                hspi->Tx_Size--;
+                TxFlag = 0;
+            }
+            
+            /* Wait Rx FIFO Not Empty */
+            if((!(hspi->Instance->STATUS & SPI_STATUS_RX_FIFO_EMPTY)) && (hspi->Rx_Size>0))
+            {
+                hspi->Rx_Buffer[hspi->Rx_Count++] = hspi->Instance->DAT;
+                hspi->Rx_Size--;
+                TxFlag = 1U;
+            }
+        }
+        
+        /* Wait Timeout */
+        if(uiTimeout)
+        {
+            uiTimeout--;
+            if(uiTimeout == 0)
+            {
+                Status = HAL_TIMEOUT;
+                goto End;
+            }
+        }
+    }        
+    /* Wait Transmit Done */
+    while (!(hspi->Instance->STATUS & SPI_STATUS_TX_BATCH_DONE));
+    
+    Status = HAL_OK;
+
+End:    
+    /* Clear Batch Done Flag  */
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_TX_BATCH_DONE);
+    SET_BIT(hspi->Instance->STATUS, SPI_STATUS_BATCH_DONE);
+
+    /* Tx Disable */
+    hspi->Instance->TX_CTL &= (~SPI_TX_CTL_EN);
+    
+    /* Rx Disable */
+    hspi->Instance->RX_CTL &= (~SPI_RX_CTL_EN);
+
+    if (hspi->Init.SPI_Mode == SPI_MODE_MASTER) 
+    {
+        /* Transmit End */
+        hspi->Instance->CS &= (~SPI_CS_CS0);
+    }
+
+    return Status;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_GetTxState
+ * Description: Get Tx state.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ ************************************************************************/
+uint8_t HAL_SPI_GetTxState(SPI_HandleTypeDef *hspi)
+{
+    return hspi->TxState;
+}
+
+/************************************************************************
+ * function   : HAL_SPI_GetRxState
+ * Description: Get Rx state.
+ * input      : hspi  : pointer to a SPI_HandleTypeDef structure that contains
+ *                      the configuration information for SPI module
+ ************************************************************************/
+uint8_t HAL_SPI_GetRxState(SPI_HandleTypeDef *hspi)
+{
+    return hspi->RxState;
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER.c

@@ -0,0 +1,1553 @@
+/***********************************************************************
+ * Filename    : hal_lpuart.c
+ * Description : lpuart driver source file
+ * Author(s)   : xwl  
+ * version     : V1.0
+ * Modify date : 2019-11-19
+ ***********************************************************************/
+#include "ACM32Fxx_HAL.h"  
+
+static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
+static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);  
+static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);  
+static void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter);
+static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter);  
+static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter);
+static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t filter);   
+
+/*********************************************************************************
+* Function    : HAL_TIMER_MSP_Init
+* Description : MSP init, mainly about clock, nvic   
+* Input       : timer handler 
+* Output      : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/
+__weak uint32_t HAL_TIMER_MSP_Init(TIM_HandleTypeDef * htim)  
+{
+	uint32_t Timer_Instance;
+	
+	if (0 == IS_TIMER_INSTANCE(htim->Instance))
+	{
+		return HAL_ERROR; //instance error 
+	}
+	
+	Timer_Instance = (uint32_t)(htim->Instance); 
+	
+	switch(Timer_Instance) 
+	{
+		case TIM1_BASE: 
+		System_Module_Reset(RST_TIM1);   
+		System_Module_Enable(EN_TIM1);  
+        NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn);     
+        NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);  
+		break; 
+        
+        case TIM2_BASE: 
+		System_Module_Reset(RST_TIM2); 
+		System_Module_Enable(EN_TIM2); 
+        NVIC_ClearPendingIRQ(TIM2_IRQn);     
+        NVIC_EnableIRQ(TIM2_IRQn);    
+		break; 
+
+		case TIM3_BASE: 
+		System_Module_Reset(RST_TIM3); 
+		System_Module_Enable(EN_TIM3); 
+        NVIC_ClearPendingIRQ(TIM3_IRQn);     
+        NVIC_EnableIRQ(TIM3_IRQn);    
+		break;  
+        
+        case TIM4_BASE: 
+		System_Module_Reset(RST_TIM4); 
+		System_Module_Enable(EN_TIM4); 
+        NVIC_ClearPendingIRQ(TIM4_IRQn);     
+        NVIC_EnableIRQ(TIM4_IRQn);    
+		break;
+		
+		case TIM6_BASE:  
+		System_Module_Reset(RST_TIM6); 			
+		System_Module_Enable(EN_TIM6);
+        NVIC_ClearPendingIRQ(TIM6_IRQn);   
+        NVIC_EnableIRQ(TIM6_IRQn);   
+		break; 
+        
+        case TIM7_BASE:  
+		System_Module_Reset(RST_TIM7); 			
+		System_Module_Enable(EN_TIM7);
+        NVIC_ClearPendingIRQ(TIM7_IRQn);   
+        NVIC_EnableIRQ(TIM7_IRQn);   
+		break; 
+		
+		case TIM14_BASE:   
+		System_Module_Reset(RST_TIM14); 				
+		System_Module_Enable(EN_TIM14); 
+		NVIC_ClearPendingIRQ(TIM14_IRQn);   
+		NVIC_EnableIRQ(TIM14_IRQn);  
+		break;
+		
+		case TIM15_BASE:   
+		System_Module_Reset(RST_TIM15);   	  		
+		System_Module_Enable(EN_TIM15); 
+		NVIC_ClearPendingIRQ(TIM15_IRQn);   
+		NVIC_EnableIRQ(TIM15_IRQn);  
+		break;
+		
+		case TIM16_BASE: 
+		System_Module_Reset(RST_TIM16); 	  	
+		System_Module_Enable(EN_TIM16);   
+		NVIC_ClearPendingIRQ(TIM16_IRQn);   
+		NVIC_EnableIRQ(TIM16_IRQn); 
+		break;
+		
+		case TIM17_BASE: 
+		System_Module_Reset(RST_TIM17); 	 		
+		System_Module_Enable(EN_TIM17); 
+		NVIC_ClearPendingIRQ(TIM17_IRQn);   
+		NVIC_EnableIRQ(TIM17_IRQn); 
+		break;  
+		
+		default:
+		return HAL_ERROR;  
+	}
+	
+	return HAL_OK;    
+}  
+
+
+__weak uint32_t HAL_TIMER_Base_MspDeInit(TIM_HandleTypeDef * htim)  
+{
+	uint32_t Timer_Instance;
+	
+	if (0 == IS_TIMER_INSTANCE(htim->Instance))
+	{
+		return HAL_ERROR; //instance error 
+	}
+	
+	Timer_Instance = (uint32_t)(htim->Instance); 
+	
+	switch(Timer_Instance) 
+	{
+		case TIM1_BASE: 
+		System_Module_Disable(EN_TIM1);  
+        NVIC_ClearPendingIRQ(TIM1_BRK_UP_TRG_COM_IRQn);     
+        NVIC_DisableIRQ(TIM1_BRK_UP_TRG_COM_IRQn);           
+		break; 
+        
+        case TIM2_BASE: 
+		System_Module_Disable(EN_TIM2);  
+        NVIC_ClearPendingIRQ(TIM2_IRQn);     
+        NVIC_DisableIRQ(TIM2_IRQn);   
+		break; 
+
+		case TIM3_BASE: 
+ 		System_Module_Disable(EN_TIM3);  
+        NVIC_ClearPendingIRQ(TIM3_IRQn);     
+        NVIC_DisableIRQ(TIM3_IRQn);         
+		break;  
+        
+        case TIM4_BASE: 
+        System_Module_Disable(EN_TIM4);  
+        NVIC_ClearPendingIRQ(TIM4_IRQn);     
+        NVIC_DisableIRQ(TIM4_IRQn);     
+		break;
+		
+		case TIM6_BASE:  
+		System_Module_Disable(EN_TIM6);  
+        NVIC_ClearPendingIRQ(TIM6_IRQn);     
+        NVIC_DisableIRQ(TIM6_IRQn);   
+		break; 
+        
+        case TIM7_BASE:  
+		System_Module_Disable(EN_TIM7);  
+        NVIC_ClearPendingIRQ(TIM7_IRQn);     
+        NVIC_DisableIRQ(TIM7_IRQn);   
+		break; 
+		
+		case TIM14_BASE:   
+		System_Module_Disable(EN_TIM14);  
+        NVIC_ClearPendingIRQ(TIM14_IRQn);     
+        NVIC_DisableIRQ(TIM14_IRQn);           
+		break;
+		
+		case TIM15_BASE:   
+		System_Module_Disable(EN_TIM15);  
+        NVIC_ClearPendingIRQ(TIM15_IRQn);     
+        NVIC_DisableIRQ(TIM15_IRQn); 
+		break;
+		
+		case TIM16_BASE: 
+		System_Module_Disable(EN_TIM16);  
+        NVIC_ClearPendingIRQ(TIM16_IRQn);     
+        NVIC_DisableIRQ(TIM16_IRQn); 
+		break;
+		
+		case TIM17_BASE: 
+		System_Module_Disable(EN_TIM17);  
+        NVIC_ClearPendingIRQ(TIM17_IRQn);     
+        NVIC_DisableIRQ(TIM17_IRQn);               
+		break;  
+		
+		default:
+		return HAL_ERROR;  
+	}
+	
+	return HAL_OK;    
+}  
+/*********************************************************************************
+* Function    : HAL_TIMER_Slave_Mode_Config 
+* Description : configure timer in slave mode  
+* Input       : 
+              htim: timer handler
+              sSlaveConfig: slave mode parameter strcture
+                            SlaveMode: TIM_SLAVE_MODE_DIS, TIM_SLAVE_MODE_ENC1...
+                            InputTrigger: TIM_TRIGGER_SOURCE_ITR0, TIM_TRIGGER_SOURCE_ITR1... 
+                            TriggerPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... 
+                            TriggerPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2... 
+* Output      : 0: success; else:error   
+* Author      : xwl                       
+**********************************************************************************/
+uint32_t HAL_TIMER_Slave_Mode_Config(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)  
+{
+	if (0 == IS_TIM_SLAVE_INSTANCE(htim->Instance) )   
+	{
+		return 1;  // not supported 
+	}
+    /*reset SMS and TS bits*/
+	htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2|BIT4|BIT5|BIT6));       
+    /*SET SMS bits*/
+	htim->Instance->SMCR |= (sSlaveConfig->SlaveMode & (BIT0|BIT1|BIT2) ); 
+    /*SET TS bits*/
+	htim->Instance->SMCR |= (sSlaveConfig->InputTrigger & (BIT4|BIT5|BIT6) );   
+	
+	switch (sSlaveConfig->InputTrigger)   
+    {
+        case TIM_TRIGGER_SOURCE_TI1FP1:  
+		TIMER_TI1FP1_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter);
+		break;
+		
+		case TIM_TRIGGER_SOURCE_TI2FP2: 
+		TIMER_TI2FP2_ConfigInputStage(htim->Instance, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter);  
+		break; 
+		
+        case TIM_TRIGGER_SOURCE_ETRF:  
+        TIMER_ETR_SetConfig(htim->Instance, sSlaveConfig->TriggerPrescaler, sSlaveConfig->TriggerPolarity, sSlaveConfig->TriggerFilter);  
+        break;  
+        
+        case TIM_TRIGGER_SOURCE_ITR0: 
+        case TIM_TRIGGER_SOURCE_ITR1:
+        case TIM_TRIGGER_SOURCE_ITR2:
+        case TIM_TRIGGER_SOURCE_ITR3: 
+        // don't need do anything here 
+        break;  
+        
+		default:
+		return 1;  
+	}
+	
+	return 0;  
+}     
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Master_Mode_Config 
+* Description : configure timer in master mode  
+* Input       : 
+              TIMx: timer instance 
+              sMasterConfig: master mode parameter structure 
+                             MasterSlaveMode: TIM_TRGO_RESET, TIM_TRGO_ENABLE...   
+                             MasterOutputTrigger: TIM_MASTERSLAVEMODE_DISABLE, TIM_MASTERSLAVEMODE_ENABLE  
+* Output      : 0: success; else:error 
+* Author      : xwl                       
+**********************************************************************************/
+uint32_t HAL_TIMER_Master_Mode_Config(TIM_TypeDef *TIMx, TIM_MasterConfigTypeDef * sMasterConfig)    
+{
+    /*reset bits*/
+	TIMx->SMCR &= (~BIT7);  
+	TIMx->CR2  &= (~(BIT4|BIT5|BIT6));       
+	
+	TIMx->SMCR |= sMasterConfig->MasterSlaveMode;  
+	TIMx->CR2  |= sMasterConfig->MasterOutputTrigger;     
+	
+	return 0;  
+}
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Output_Config  
+* Description : configure output parameter   
+* Input       : 
+              TIMx: timer instance  
+              Output_Config: output configration parameter structure  
+                             OCMode: OUTPUT_MODE_FROZEN, OUTPUT_MODE_MATCH_HIGH... 
+                             Pulse: write to ccrx register 
+                             OCPolarity: OC channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW 
+                             OCNPolarity: OCN channel output polarity: OUTPUT_POL_ACTIVE_HIGH, OUTPUT_POL_ACTIVE_LOW  
+                             OCFastMode: OUTPUT_FAST_MODE_DISABLE, OUTPUT_FAST_MODE_ENABLE 
+                             OCIdleState: OC channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1
+                             OCNIdleState: OCN channel idle state, OUTPUT_IDLE_STATE_0, OUTPUT_IDLE_STATE_1 
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...  
+* Output      : 0: success; else:error 
+* Author      : xwl                       
+**********************************************************************************/
+uint32_t HAL_TIMER_Output_Config(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef * Output_Config, uint32_t Channel)
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+	
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1:
+		TIMx->CCER &= (~BIT0);  //disable OC1 
+		if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity)
+		{
+			TIMx->CCER &= (~BIT1);  
+		}
+		else
+		{
+			TIMx->CCER |= (BIT1);   
+		}
+		
+		if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER &= (~BIT2);  //disable OC1N  
+			
+			if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity)   
+			{
+				TIMx->CCER &= (~BIT3);  
+			}
+			else
+			{
+				TIMx->CCER |= (BIT3);     
+			}  
+		}
+		
+		TIMx->CCMR1 &= (~0x00FFU); // reset low 8 bits   
+		TIMx->CCR1 = Output_Config->Pulse;   
+		if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode)  
+		{
+			TIMx->CCMR1 |= (BIT2);  
+		}
+		TIMx->CCMR1 |= (BIT3);  // preload enable 	
+		
+		if (IS_TIM_BREAK_INSTANCE(TIMx)) 
+		{
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState)
+			{
+				TIMx->CR2 &= (~BIT8); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT8; 
+			}
+			
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState)  
+			{
+				TIMx->CR2 &= (~BIT9); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT9;   
+			}  
+			
+		}
+		TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4);   
+		break;
+		
+		case TIM_CHANNEL_2:
+		TIMx->CCER &= (~BIT4);  //disable OC2
+		if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity)
+		{
+			TIMx->CCER &= (~BIT5);  
+		}
+		else
+		{
+			TIMx->CCER |= (BIT5);   
+		}
+		
+		if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER &= (~BIT6);  //disable OC2N  
+			
+			if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity)   
+			{
+				TIMx->CCER &= (~BIT7);  
+			}
+			else
+			{
+				TIMx->CCER |= (BIT7);     
+			}  
+		}
+		
+		TIMx->CCMR1 &= (~0xFF00U); // reset high 8 bits 
+		TIMx->CCR2 = Output_Config->Pulse;   // write value to ccr before preload enable 
+		if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode)  
+		{
+			TIMx->CCMR1 |= (BIT10);  
+		}
+		TIMx->CCMR1 |= (BIT11);  // preload enable 
+		
+		if (IS_TIM_BREAK_INSTANCE(TIMx)) 
+		{
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState)
+			{
+				TIMx->CR2 &= (~BIT10); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT10; 
+			}
+			
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState)  
+			{
+				TIMx->CR2 &= (~BIT11); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT11;   
+			}
+			
+		}
+		TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12);   
+		break;
+		
+		case TIM_CHANNEL_3:
+		TIMx->CCER &= (~BIT8);  //disable OC3  
+		if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity)
+		{
+			TIMx->CCER &= (~BIT9);  
+		}
+		else
+		{
+			TIMx->CCER |= (BIT9);   
+		}
+		
+		if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER &= (~BIT10);  //disable OC3N   
+			
+			if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCNPolarity)   
+			{
+				TIMx->CCER &= (~BIT11);  
+			}
+			else
+			{
+				TIMx->CCER |= (BIT11);     
+			}  
+		}
+		
+		TIMx->CCMR2 &= (~0x00FF); // reset low 8 bits 
+		TIMx->CCMR2 |= (BIT3);  // preload enable   
+		if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode)  
+		{
+			TIMx->CCMR2 |= (BIT2);  
+		}
+		 
+		TIMx->CCR3 = Output_Config->Pulse;  	
+		if (IS_TIM_BREAK_INSTANCE(TIMx)) 
+		{
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState)
+			{
+				TIMx->CR2 &= (~BIT12); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT12; 
+			}
+			
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCNIdleState)  
+			{
+				TIMx->CR2 &= (~BIT13); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT13;     
+			} 
+			
+		}
+		TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT4|BIT5|BIT6))) | (Output_Config->OCMode << 4);     
+		break;
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER &= (~BIT12);  //disable OC4  
+		if (OUTPUT_POL_ACTIVE_HIGH == Output_Config->OCPolarity)
+		{
+			TIMx->CCER &= (~BIT13);  
+		}
+		else
+		{
+			TIMx->CCER |= (BIT13);     
+		}
+		
+		TIMx->CCMR2 &= (~0xFF00); // reset high 8 bits    
+		TIMx->CCR4 = Output_Config->Pulse;   
+		if (OUTPUT_FAST_MODE_ENABLE == Output_Config->OCFastMode)  
+		{
+			TIMx->CCMR2 |= (BIT10);  // fast mode  
+		}
+		TIMx->CCMR2 |= (BIT11);  // preload enable 
+	
+		if (IS_TIM_BREAK_INSTANCE(TIMx)) 
+		{
+			if (OUTPUT_IDLE_STATE_0 == Output_Config->OCIdleState)
+			{
+				TIMx->CR2 &= (~BIT14); 
+			}
+			else
+			{
+				TIMx->CR2 |= BIT14;    
+			}
+			
+		}
+		TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT12|BIT13|BIT14))) | (Output_Config->OCMode << 12);     
+		break;
+		
+		default:
+			return 1; // error parameter 
+	} 
+	
+	return 0;  
+}   
+
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Capture_Config  
+* Description : configure capture parameters   
+* Input       : 
+              TIMx: timer instance 
+              Capture_Config: capture configuration parameter strcture 
+                            ICPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... 
+                            ICSelection: TIM_ICSELECTION_DIRECTTI, TIM_ICSELECTION_INDIRECTTI
+                            ICFilter: TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x), x:0-15 
+                            ICPrescaler: TIM_IC1_PRESCALER_1, TIM_IC2_PRESCALER_1... 
+              Channel: channel id, TIM_CHANNEL_1, TIM_CHANNEL_2...   
+* Output      : 0: success; else:error 
+* Author      : xwl                       
+**********************************************************************************/  	
+uint32_t HAL_TIMER_Capture_Config(TIM_TypeDef *TIMx, TIM_IC_InitTypeDef * Capture_Config, uint32_t Channel)  
+{
+	switch(Channel) 
+	{
+		case TIM_CHANNEL_1:   
+		TIMER_IC1_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter);  
+         
+        /* Reset the IC1PSC Bits */
+        TIMx->CCMR1 &= (~BIT2|BIT3);   
+        /* Set the IC1PSC value */
+        TIMx->CCMR1 |= Capture_Config->ICPrescaler;   
+		break;  
+		
+		case TIM_CHANNEL_2:  
+        TIMER_IC2_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter); 
+
+        
+        /* Reset the IC2PSC Bits */
+        TIMx->CCMR1 &= (~BIT10|BIT11);
+        /* Set the IC2PSC value */
+        TIMx->CCMR1 |= Capture_Config->ICPrescaler;  
+		break; 
+		
+		case TIM_CHANNEL_3:    
+        TIMER_IC3_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter);    
+
+        /* Reset the IC3PSC Bits */
+        TIMx->CCMR2 &= (~BIT2|BIT3);
+        /* Set the IC3PSC value */
+        TIMx->CCMR2 |= Capture_Config->ICPrescaler;      
+                
+		break; 
+		
+		case TIM_CHANNEL_4:   
+        TIMER_IC4_SetConfig(TIMx, Capture_Config->ICPolarity, Capture_Config->ICSelection, Capture_Config->TIFilter);         
+        
+        /* Reset the IC4PSC Bits */
+        TIMx->CCMR2 &= (~BIT10|BIT11);   
+        /* Set the IC4PSC value */
+        TIMx->CCMR2 |= Capture_Config->ICPrescaler;  
+		break;   
+		
+		default:  
+		return 1;     
+	}
+		
+	return 0;  
+}    
+
+
+
+/*********************************************************************************
+* Function    : HAL_TIMER_SelectClockSource  
+* Description : select timer counter source, internal or external 
+* Input:
+  htim : timer handler 
+  sClockSourceConfig: configuration parameters, includes following members:  
+                      ClockSource: TIM_CLOCKSOURCE_INT,  TIM_CLOCKSOURCE_ETR... 
+                      ClockPolarity: TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING... 
+                      ClockPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2...  
+                      ClockFilter: TIM_ETR_FILTER_LVL(x), TIM_IC1_FILTER_LVL(x), TIM_IC2_FILTER_LVL(x)  
+* Output      : HAL_ERROR:error, HAL_OK:OK     
+* Author      : xwl                       
+**********************************************************************************/  
+HAL_StatusTypeDef HAL_TIMER_SelectClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
+{
+  htim->Instance->SMCR &= (~(BIT0|BIT1|BIT2));  
+    
+  switch (sClockSourceConfig->ClockSource)
+  {
+    case TIM_CLOCKSOURCE_INT:
+    {
+        // do nothing here   
+        break;
+    }
+
+    case TIM_CLOCKSOURCE_ETR:
+    {
+
+      /* Configure the ETR Clock source */
+      TIMER_ETR_SetConfig(htim->Instance,
+                        sClockSourceConfig->ClockPrescaler,
+                        sClockSourceConfig->ClockPolarity,
+                        sClockSourceConfig->ClockFilter);
+      /* Enable the External clock mode2 */
+      htim->Instance->SMCR |= BIT14;  // ECE=1,external clock mode 2   
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI1FP1:
+    {
+	  
+      TIMER_TI1FP1_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter); 
+        
+      htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6));  // trigger selection 
+      htim->Instance->SMCR |= (5  << 4);   // Trigger select TI1FP1      
+        
+      htim->Instance->SMCR |= (BIT0|BIT1|BIT2);  // select external clock mode 1  
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_TI2FP2:
+    {
+      TIMER_TI2FP2_ConfigInputStage(htim->Instance,
+                               sClockSourceConfig->ClockPolarity,
+                               sClockSourceConfig->ClockFilter); 
+        
+      htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6));  // trigger selection     
+      htim->Instance->SMCR |= (6  << 4);   // Trigger select TI2FP2    
+        
+      htim->Instance->SMCR |= (BIT0|BIT1|BIT2);  // select external clock mode 1  
+      break;
+    }
+
+    case TIM_CLOCKSOURCE_ITR0:
+    case TIM_CLOCKSOURCE_ITR1: 
+    case TIM_CLOCKSOURCE_ITR2:
+    case TIM_CLOCKSOURCE_ITR3:
+    {
+        htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6));  
+        htim->Instance->SMCR |= ( (sClockSourceConfig->ClockSource - TIM_CLOCKSOURCE_ITR0) << 4);    
+        
+        htim->Instance->SMCR |= (BIT0|BIT1|BIT2);  // select external clock mode 1  
+        break;
+    }
+
+    default:
+      return HAL_ERROR;   
+  }
+
+  return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Base_Init  
+* Description : timer base initiation   
+* Input       : timer handler 
+* Output      : 0: success; else:error 
+* Author      : xwl                       
+**********************************************************************************/  	
+uint32_t HAL_TIMER_Base_Init(TIM_HandleTypeDef * htim)
+{
+	if (0 == IS_TIMER_INSTANCE(htim->Instance))
+	{
+		return 1; //instance error 
+	}
+	
+	htim->Instance->CR1 = BIT2;  // CEN=0, URS=1, OPM = 0   
+	
+	if (htim->Init.ARRPreLoadEn)  
+	{
+		htim->Instance->CR1 |= (BIT7);		
+	}
+	else
+	{
+		htim->Instance->CR1 &= (~BIT7);   
+	}		
+	htim->Instance->ARR = htim->Init.Period; 
+	htim->Instance->PSC = htim->Init.Prescaler;   
+	if (IS_TIM_REPETITION_COUNTER_INSTANCE(htim->Instance))
+	{
+		htim->Instance->RCR = htim->Init.RepetitionCounter;   
+	}
+	htim->Instance->EGR = BIT0;     // no UIF generated because URS=1 
+
+	if (IS_TIM_CLOCK_DIVISION_INSTANCE(htim->Instance))  
+	{
+		htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT8|BIT9))) | ((htim->Init.ClockDivision) & (BIT8|BIT9));     
+	}
+	//up/down/center mode 
+	htim->Instance->CR1 = (htim->Instance->CR1 & (~(BIT4|BIT5|BIT6))) | ((htim->Init.CounterMode) & (BIT4|BIT5|BIT6));    
+	
+	htim->Instance->CR1 &= (~BIT2); //URS = 0     
+	
+	return 0;  
+} 
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Base_DeInit  
+* Description : timer base deinitiation, disable Timer, turn off module clock and nvic  
+* Input       : timer handler 
+* Output      : HAL_OK: success; HAL_ERROR:error 
+* Author      : xwl                       
+**********************************************************************************/ 
+HAL_StatusTypeDef HAL_TIMER_Base_DeInit(TIM_HandleTypeDef *htim)
+{
+  htim->Instance->CR1 &= (~BIT0);  
+    
+  HAL_TIMER_Base_MspDeInit(htim);     
+
+  return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Base_Start  
+* Description : start timer   
+* Input       : timer instance  
+* Output      : none 
+* Author      : xwl                       
+**********************************************************************************/  	
+void HAL_TIMER_Base_Start(TIM_TypeDef *TIMx)
+{
+	if (0 == IS_TIM_SLAVE_INSTANCE(TIMx) )     
+	{
+		TIMx->CR1 |= BIT0;    
+		return;    
+	}
+	
+	if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )  
+	{
+		TIMx->CR1 |= BIT0;      
+		return;     
+	}
+	
+	return;       
+}
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Base_Stop  
+* Description : stop timer 
+* Input       : timer handler   
+* Output      : none 
+* Author      : xwl                       
+**********************************************************************************/  
+HAL_StatusTypeDef HAL_TIMER_Base_Stop(TIM_TypeDef *TIMx)
+{
+    TIMx->CR1 &= (~BIT0);  
+    HAL_TIM_DISABLE_IT_EX(TIMx, TIM_IT_UPDATE);         
+
+    return HAL_OK;   
+}
+
+/*********************************************************************************
+* Function    : HAL_TIMER_OnePulse_Init     
+* Description : start timer with one pulse mode 
+* Input       : 
+              htim: timer handler 
+              mode: 0 means normal mode, 1 means one pulse mode  
+* Output      : HAL_OK, success; HAL_ERROR, fail     
+* Author      : xwl                       
+**********************************************************************************/  	  
+HAL_StatusTypeDef HAL_TIMER_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t mode)
+{
+    /* Check the TIM handle allocation */
+    if(htim == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    HAL_TIMER_Base_Init(htim);    
+  
+    /*reset  the OPM Bit */
+    htim->Instance->CR1 &= (~BIT3);   
+    if (0 != mode)
+    {
+        /*set  the OPM Bit */  
+        htim->Instance->CR1 |= BIT3; 
+    }  
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_TIM_PWM_Output_Start      
+* Description : start timer output 
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/    
+uint32_t HAL_TIM_PWM_Output_Start(TIM_TypeDef *TIMx, uint32_t Channel)  
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+	
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+		TIMx->CCER |= BIT0; 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT2;  
+		}
+		break; 
+		
+		case TIM_CHANNEL_2:  
+		TIMx->CCER |= BIT4; 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT6;  
+		}
+		break;  
+		
+		case TIM_CHANNEL_3:   
+		TIMx->CCER |= BIT8; 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT10;    
+		}
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER |= BIT12;   
+		break;  
+		
+		default:
+			return 1;  
+	}
+
+    if(IS_TIM_BREAK_INSTANCE(TIMx) != 0)  
+    {
+        /* Enable the main output */
+        TIMx->BDTR |= BIT15;     
+    }
+	
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 |= BIT0;         
+    }
+	
+	return 0;  
+}  
+/*********************************************************************************
+* Function    : HAL_TIM_PWM_Output_Stop       
+* Description : stop timer pwm output 
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/ 
+HAL_StatusTypeDef HAL_TIM_PWM_Output_Stop(TIM_TypeDef *TIMx, uint32_t Channel)    
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+		TIMx->CCER &= (~(BIT0 | BIT2)); 
+		break; 
+		
+		case TIM_CHANNEL_2:  
+		TIMx->CCER &= (~(BIT4 | BIT6));    
+		break;  
+		
+		case TIM_CHANNEL_3:   
+		TIMx->CCER &= (~(BIT8 | BIT10));   
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER &= (~(BIT12));       
+		break;  
+		
+		default:
+			return 1;  
+	}
+
+    if(IS_TIM_BREAK_INSTANCE(TIMx) != 0)  
+    {
+        /* Enable the main output */
+        TIMx->BDTR &= (~BIT15);     
+    }
+	
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 &= (~BIT0);         
+    }
+	
+  /* Return function status */
+  return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_TIMER_OC_Start      
+* Description : start timer output 
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/    
+uint32_t HAL_TIMER_OC_Start(TIM_TypeDef *TIMx, uint32_t Channel)    
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+	
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+		TIMx->CCER |= BIT0; 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT2;  
+		}
+		break; 
+		
+		case TIM_CHANNEL_2:  
+		TIMx->CCER |= BIT4; 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT6;  
+		}
+		break;  
+		
+		case TIM_CHANNEL_3:   
+		TIMx->CCER |= BIT8; 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT10;    
+		}
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER |= BIT12;   
+		break;  
+		
+		default:
+			return 1;  
+	}
+
+    if(IS_TIM_BREAK_INSTANCE(TIMx) != 0)  
+    {
+        /* Enable the main output */
+        TIMx->BDTR |= BIT15;     
+    }
+	
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 |= BIT0;         
+    }
+	
+	return 0;  
+}  
+
+/*********************************************************************************
+* Function    : HAL_TIMER_OCxN_Start       
+* Description : start timer OCxN output 
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/    
+uint32_t HAL_TIMER_OCxN_Start(TIM_TypeDef *TIMx, uint32_t Channel)    
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+	
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT2;  
+		}
+		break; 
+		
+		case TIM_CHANNEL_2:  
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT6;  
+		}
+		break;  
+		
+		case TIM_CHANNEL_3:   
+        if (IS_TIM_CCXN_INSTANCE(TIMx, Channel) )  
+		{
+			TIMx->CCER |= BIT10;    
+		}
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER |= BIT12;   
+		break;  
+		
+		default:
+			return 1;  
+	}
+
+    if(IS_TIM_BREAK_INSTANCE(TIMx) != 0)  
+    {
+        /* Enable the main output */
+        TIMx->BDTR |= BIT15;     
+    }
+	
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 |= BIT0;         
+    }
+	
+	return 0;  
+} 
+
+/*********************************************************************************
+* Function    : HAL_TIMER_OC_Stop      
+* Description : stop timer output 
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/ 
+HAL_StatusTypeDef HAL_TIMER_OC_Stop(TIM_TypeDef *TIMx, uint32_t Channel)    
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+		TIMx->CCER &= (~(BIT0 | BIT2)); 
+		break; 
+		
+		case TIM_CHANNEL_2:  
+		TIMx->CCER &= (~(BIT4 | BIT6));    
+		break;  
+		
+		case TIM_CHANNEL_3:   
+		TIMx->CCER &= (~(BIT8 | BIT10));   
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER &= (~(BIT12));       
+		break;  
+		
+		default:
+			return 1;  
+	}
+
+    if(IS_TIM_BREAK_INSTANCE(TIMx) != 0)  
+    {
+        /* Enable the main output */
+        TIMx->BDTR &= (~BIT15);     
+    }
+	
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 &= (~BIT0);         
+    }
+	
+  /* Return function status */
+  return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_TIM_Capture_Start      
+* Description : start timer capture  
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/    
+uint32_t HAL_TIM_Capture_Start(TIM_TypeDef *TIMx, uint32_t Channel)    
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+    
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+		TIMx->CCER |= BIT0; 
+		break; 
+		
+		case TIM_CHANNEL_2:  
+		TIMx->CCER |= BIT4; 
+		break;  
+		
+		case TIM_CHANNEL_3:   
+		TIMx->CCER |= BIT8;   
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER |= BIT12;   
+		break;  
+		
+		default:
+			return 1;  
+	}
+    
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 |= BIT0;         
+    }
+		
+	return 0;  
+}    
+
+
+/*********************************************************************************
+* Function    : HAL_TIM_Capture_Stop      
+* Description : stop timer capture  
+* Input       : 
+              TIMx: timer instance
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : : 0: success; else:error    
+* Author      : xwl                       
+**********************************************************************************/    
+uint32_t HAL_TIM_Capture_Stop(TIM_TypeDef *TIMx, uint32_t Channel)    
+{
+	if (0 == IS_TIM_CCX_INSTANCE(TIMx, Channel) )  
+	{
+		return 1;  // error parameter   
+	}
+    
+	switch(Channel)
+	{
+		case TIM_CHANNEL_1: 
+		TIMx->CCER &= (~BIT0); 
+		break; 
+		
+		case TIM_CHANNEL_2:  
+		TIMx->CCER &= (~BIT4); 
+		break;  
+		
+		case TIM_CHANNEL_3:   
+		TIMx->CCER &= (~BIT8);  
+		break;  
+		
+		case TIM_CHANNEL_4: 
+		TIMx->CCER &= (~BIT12);         
+		break;  
+		
+		default:
+			return 1;  
+	}
+    
+    if (TIM_SLAVE_MODE_TRIG != (TIMx->SMCR & (BIT0|BIT1|BIT2) ) )    
+    {
+        TIMx->CR1 &= (~BIT0);            
+    }
+		
+	return 0;  
+}    
+
+
+/*********************************************************************************
+* Function    : HAL_TIMEx_ETRSelection      
+* Description : select ETR signal, it can ben GPIO, COMP1_OUT, COMP2_OUT, ADC analog watchdog output 
+* Input       : 
+              htim: timer handler 
+              ETRSelection: ETR_SELECT_GPIO, ETR_SELECT_COMP1_OUT...         
+* Output      : HAL_OK, Success; HAL_ERROR:Fail     
+* Author      : xwl                       
+**********************************************************************************/ 
+HAL_StatusTypeDef  HAL_TIMEx_ETRSelection(TIM_HandleTypeDef *htim, uint32_t ETRSelection)
+{
+    HAL_StatusTypeDef status = HAL_OK;
+  
+    htim->Instance->AF1 &= (~ETR_SELECT_MASK);      
+    htim->Instance->AF1 |= ETRSelection;  
+  
+    return status;
+}   
+
+/*********************************************************************************
+* Function    : HAL_TIMER_ReadCapturedValue      
+* Description : read capture value as channel  
+* Input       : 
+              htim: timer handler  
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : capture value     
+* Author      : xwl                       
+**********************************************************************************/     
+uint32_t HAL_TIMER_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+  uint32_t capture_data = 0U;
+
+  switch (Channel)
+  {
+    case TIM_CHANNEL_1:
+    {
+      /* Return the capture 1 value */
+      capture_data =  htim->Instance->CCR1;
+      break;
+    }
+    case TIM_CHANNEL_2:
+    {
+      /* Return the capture 2 value */
+      capture_data =   htim->Instance->CCR2;
+      break;
+    }
+    case TIM_CHANNEL_3:
+    {
+      /* Return the capture 3 value */
+      capture_data =   htim->Instance->CCR3;
+      break;
+    }
+    case TIM_CHANNEL_4:
+    {
+      /* Return the capture 4 value */
+      capture_data =   htim->Instance->CCR4;
+      break;
+    }
+    default:
+      break;
+  }
+
+  return capture_data;
+}   
+
+/*********************************************************************************
+* Function    : HAL_TIMER_GenerateEvent  
+* Description : Generate event by software
+* Input:
+  htim : timer handler 
+  EventSource: TIM_EVENTSOURCE_UPDATE, TIM_EVENTSOURCE_CC1...
+* Output      : HAL_ERROR:error, HAL_OK:OK     
+* Author      : xwl                       
+**********************************************************************************/ 
+HAL_StatusTypeDef HAL_TIMER_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
+{
+  htim->Instance->EGR = EventSource;
+
+  return HAL_OK;
+} 
+
+/*********************************************************************************
+* Function    : HAL_TIMER_Clear_Capture_Flag        
+* Description : clear capture flag as channel id   
+* Input       : 
+              htim: timer handler  
+              Channel: TIM_CHANNEL_1, TIM_CHANNEL_2...    
+* Output      : capture value     
+* Author      : xwl                       
+**********************************************************************************/
+void HAL_TIMER_Clear_Capture_Flag(TIM_HandleTypeDef *htim, uint32_t Channel)
+{
+    switch (Channel)
+    {
+        case TIM_CHANNEL_1:
+        {
+            htim->Instance->SR &= (~(BIT1|BIT9));  
+            break;  
+        }
+        case TIM_CHANNEL_2:
+        {
+            htim->Instance->SR &= (~(BIT2|BIT10));  
+            break;
+        }
+        case TIM_CHANNEL_3:
+        {
+            htim->Instance->SR &= (~(BIT3|BIT11));  
+            break;
+        }
+        case TIM_CHANNEL_4:
+        {
+            htim->Instance->SR &= (~(BIT4|BIT12));      
+            break;
+        }
+        default:
+        break;
+    }
+}
+
+/*********************************************************************************
+* Function    : TIMER_ETR_SetConfig  
+* Description : configure ETR channel polarity, prescaler and filter 
+* Input:
+  TIMx : timer instance  
+  TIM_ExtTRGPrescaler: TIM_ETR_PRESCALER_1, TIM_ETR_PRESCALER_2...  
+  TIM_ExtTRGPolarity:  TIM_ETR_POLAIRTY_HIGH, TIM_ETR_POLAIRTY_LOW
+  ExtTRGFilter:  TIM_ETR_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/ 
+static void TIMER_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+{
+  /* Reset the ETR Bits */
+  TIMx->SMCR &= (~0xFF00U);     
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  TIMx->SMCR |= (TIM_ExtTRGPrescaler | TIM_ExtTRGPolarity | ExtTRGFilter);   
+}
+
+/*********************************************************************************
+* Function    : TIMER_TI1FP1_ConfigInputStage  
+* Description : configure TI1FP1 channel polarity and filter 
+* Input:
+  TIMx : timer instance    
+  TIM_ICPolarity:  TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING...   
+  Filter:  TIM_TI1_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/ 
+static void TIMER_TI1FP1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter)
+{    
+    TIMx->CCER &= (~BIT0);  //Disable the Channel 1: Reset the CC1E Bit   
+    TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1)) | BIT0);    // CH1 as input 
+  
+    TIMx->CCMR1 &= (~0xF0U); // reset TI1 filter   
+    TIMx->CCMR1 |= Filter; 
+    
+    if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING;   
+	}
+	else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING;      
+	}
+	else
+	{
+		TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH;     
+	}
+}
+
+/*********************************************************************************
+* Function    : TIMER_TI2FP2_ConfigInputStage  
+* Description : configure TI2FP2 channel polarity and filter 
+* Input:
+  TIMx : timer instance    
+  TIM_ICPolarity:  TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING...   
+  Filter:  TIM_TI2_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/ 
+static void TIMER_TI2FP2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t Filter)
+{    
+    TIMx->CCER &= (~BIT4);  //Disable the Channel 2: Reset the CC2E Bit   
+    TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9)) | BIT8);    // CH2 as input 
+  
+    TIMx->CCMR1 &= (~0xF000U); // reset TI2 filter    
+    TIMx->CCMR1 |= Filter;   
+    
+    if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING;   
+	}
+	else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING;      
+	}
+	else
+	{
+		TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH;     
+	}
+}
+
+/*********************************************************************************
+* Function    : TIMER_IC1_SetConfig  
+* Description : configure TI1FP1 or TI2FP1 channel polarity and filter 
+* Input:
+  TIMx : timer instance    
+  TIM_ICPolarity:  TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING...   
+  Filter:  TIM_TI1_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/ 
+void TIMER_IC1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter)
+{
+    /* Disable the Channel 1: Reset the CC1E Bit */
+    TIMx->CCER &= (~BIT0);  
+
+    if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity)  
+    {
+        TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_RISING;   
+    }
+    else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity)  
+    {
+		TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_FALLING;      
+    }
+	else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC1_SLAVE_CAPTURE_POL_BOTH;     
+	}
+		
+    if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection)     
+    {
+        TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT0;   
+        TIMx->CCMR1 &= (~0xF0U);  
+    }
+    else
+    {
+        TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT0|BIT1))) | BIT1;     
+        TIMx->CCMR1 &= (~0xF000U);    
+    }
+    
+    TIMx->CCMR1 |= Filter;  
+       
+}
+
+/*********************************************************************************
+* Function    : TIMER_IC2_SetConfig  
+* Description : configure TI1FP2 or TI2FP2 channel polarity and filter 
+* Input:
+  TIMx : timer instance    
+  TIM_ICPolarity:  TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING...   
+  Filter:  TIM_TI2_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/ 
+static void TIMER_IC2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter)
+{
+    /* Disable the Channel 2, Reset the CC2E Bit */
+    TIMx->CCER &= (~BIT4); 
+    if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity)  
+    {
+		TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_RISING;    
+    }
+	else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_FALLING;         
+	}
+	else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity)  
+	{
+		TIMx->CCER |= TIM_CC2_SLAVE_CAPTURE_POL_BOTH;       
+	}
+		
+	if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection)     
+	{
+		TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT8; 
+        TIMx->CCMR1 &= (~0xF000U);   
+	}
+	else
+	{
+		TIMx->CCMR1 = (TIMx->CCMR1 & (~(BIT8|BIT9))) | BIT9; 
+        TIMx->CCMR1 &= (~0xF0U);     
+	}
+    
+    TIMx->CCMR1 |= Filter;     
+      
+}  
+
+/*********************************************************************************
+* Function    : TIMER_IC3_SetConfig  
+* Description : configure TI3FP3 or TI4FP3 channel polarity and filter 
+* Input:
+  TIMx : timer instance    
+  TIM_ICPolarity:  TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING...   
+  Filter:  TIM_TI3_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/ 
+static void TIMER_IC3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter)
+{
+    /* Disable the Channel 3, Reset the CC3E Bit */
+    TIMx->CCER &= (~BIT8); 
+    
+    if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity)  
+	{
+        TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_RISING;    
+	}
+    else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity)  
+    {
+        TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_FALLING;         
+    }
+    else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity)  
+    {
+        TIMx->CCER |= TIM_CC3_SLAVE_CAPTURE_POL_BOTH;       
+    }
+		
+    if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection)        
+    {
+        TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT0;    
+        TIMx->CCMR2 &= (~0xF0U);    
+    }
+    else
+    {
+        TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT0|BIT1))) | BIT1;       
+        TIMx->CCMR2 &= (~0xF000U);     
+    }
+     
+
+    TIMx->CCMR2 |= Filter;  
+}
+
+
+/*********************************************************************************
+* Function    : TIMER_IC4_SetConfig  
+* Description : configure TI3FP4 or TI4FP4 channel polarity and filter 
+* Input:
+  TIMx : timer instance    
+  TIM_ICPolarity:  TIM_SLAVE_CAPTURE_ACTIVE_RISING, TIM_SLAVE_CAPTURE_ACTIVE_FALLING...   
+  Filter:  TIM_TI4_FILTER_LVL(x), x=0-15  
+* Output      : none  
+* Author      : xwl                             
+**********************************************************************************/ 
+static void TIMER_IC4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t Filter)
+{
+     /* Disable the Channel 3, Reset the CC3E Bit */
+    TIMx->CCER &= (~BIT12);   
+    
+    if(TIM_SLAVE_CAPTURE_ACTIVE_RISING == TIM_ICPolarity)  
+    {
+        TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_RISING;    
+    }
+    else if (TIM_SLAVE_CAPTURE_ACTIVE_FALLING == TIM_ICPolarity)  
+    {
+        TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_FALLING;         
+    }
+    else if (TIM_SLAVE_CAPTURE_ACTIVE_RISING_FALLING == TIM_ICPolarity)    
+    {
+        TIMx->CCER |= TIM_CC4_SLAVE_CAPTURE_POL_BOTH;         
+    }
+
+    if(TIM_ICSELECTION_DIRECTTI == TIM_ICSelection)     
+    {
+        TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT8;    
+        TIMx->CCMR2 &= (~0xF000U);    
+    }
+    else
+    {
+        TIMx->CCMR2 = (TIMx->CCMR2 & (~(BIT8|BIT9))) | BIT9;    
+        TIMx->CCMR2 &= (~0xF0U);           
+    }
+
+    TIMx->CCMR2 |= Filter;     
+       
+}
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_TIMER_EX.c

@@ -0,0 +1,160 @@
+/***********************************************************************
+ * Filename    : hal_lpuart.c
+ * Description : lpuart driver source file
+ * Author(s)   : xwl  
+ * version     : V1.0
+ * Modify date : 2021-04-02
+ ***********************************************************************/
+#include "ACM32Fxx_HAL.h"  
+
+
+/*********************************************************************************
+* Function    : HAL_TIMER_ConfigBreakDeadTime  
+* Description : configure deadtime parameter   
+* Input       : timer handler, break and deadtime configuration  
+* Output      : none  
+* Author      : xwl                       
+**********************************************************************************/  
+void HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
+{
+  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
+    uint32_t break_deadtime_reg = 0U;
+
+    /* Set the BDTR bits */
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_DTG,  sBreakDeadTimeConfig->DeadTime);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
+    MODIFY_REG(break_deadtime_reg, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
+  
+    /* Set TIMx_BDTR */
+    htim->Instance->BDTR = break_deadtime_reg;  
+
+}
+  
+/*********************************************************************************
+* Function    : HAL_TIMEx_ConfigBreakInput  
+* Description : Configures the break input source.  
+* Input       :
+              htim: timer handler 
+              BreakInput: TIM_BREAKINPUT_BRK  
+              sBreakInputConfig: Break input source configuration   
+* Output      :   
+* Author      : xwl                       
+**********************************************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
+{
+    uint32_t tmporx;
+    uint32_t bkin_enable_mask;
+    uint32_t bkin_polarity_mask;
+    uint32_t bkin_enable_bitpos;
+    uint32_t bkin_polarity_bitpos;   
+
+    switch(sBreakInputConfig->Source)
+    {
+        case TIM_BREAKINPUTSOURCE_BKIN:
+        {
+            bkin_enable_mask = TIM1_AF1_BKINE;
+            bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
+            bkin_polarity_mask = TIM1_AF1_BKINP;
+            bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
+            break;
+        }
+#ifdef HAL_COMP_MODULE_ENABLED  
+        case TIM_BREAKINPUTSOURCE_COMP1:
+        {
+            bkin_enable_mask = TIM1_AF1_BKCMP1E;
+            bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos;
+            bkin_polarity_mask = TIM1_AF1_BKCMP1P;
+            bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos;
+            break;
+        }
+        case TIM_BREAKINPUTSOURCE_COMP2:
+        {
+            bkin_enable_mask = TIM1_AF1_BKCMP2E;
+            bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos;
+            bkin_polarity_mask = TIM1_AF1_BKCMP2P;
+            bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
+            break;
+        }
+#endif /* COMP1 && COMP2 */
+
+        default:
+        {
+            bkin_enable_mask = 0U;
+            bkin_enable_bitpos = 0U;
+            bkin_polarity_mask = 0U;
+            bkin_polarity_bitpos = 0U;
+            break;
+        }
+    }
+  
+    switch(BreakInput)
+    {
+        case TIM_BREAKINPUT_BRK:
+        {
+            /* Get the TIMx_AF1 register value */
+            tmporx = htim->Instance->AF1;
+        
+            /* Enable the break input */
+            tmporx &= ~bkin_enable_mask;
+            tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+        
+            /* Set the break input polarity */
+            tmporx &= ~bkin_polarity_mask;
+            tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+        
+            /* Set TIMx_AF1 */
+            htim->Instance->AF1 = tmporx;        
+            break;
+    }
+
+    default:
+      break;
+    }
+
+    return HAL_OK;  
+}   
+
+
+/*********************************************************************************
+* Function    : HAL_TIMEx_ConfigCommutEvent  
+* Description : Configure the TIM commutation event sequence. This function is mandatory to use the commutation event 
+                in order to update the configuration at each commutation detection on the TRGI input of the Timer.
+* Input       :
+              htim: timer handler 
+              InputTrigger: TIM_TRIGGER_SOURCE_ITR0, TIM_TRIGGER_SOURCE_ITR1...   
+              CommutationSource: TIM_COMMUTATION_TRGI, TIM_COMMUTATION_SOFTWARE  
+* Output      :   
+* Author      : xwl                       
+**********************************************************************************/ 
+void HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource)
+{
+
+    if ((InputTrigger == TIM_TRIGGER_SOURCE_ITR0) || (InputTrigger == TIM_TRIGGER_SOURCE_ITR1) ||
+      (InputTrigger == TIM_TRIGGER_SOURCE_ITR2) || (InputTrigger == TIM_TRIGGER_SOURCE_ITR3))
+    {
+        /* Select the Input trigger */
+        htim->Instance->SMCR &= (~(BIT4|BIT5|BIT6));
+        htim->Instance->SMCR |= InputTrigger;
+    }
+
+    /* Select the Capture Compare preload feature */
+    htim->Instance->CR2 |= TIM_CR2_CCPC;
+    /* Select the Commutation event source */
+    htim->Instance->CR2 &= ~TIM_CR2_CCUS;
+    htim->Instance->CR2 |= CommutationSource;
+
+    /* Disable Commutation Interrupt */
+    HAL_TIM_DISABLE_IT(htim, TIM_IT_COM);
+
+  /* Disable Commutation DMA request */
+    HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM);
+
+}
+
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART.c

@@ -0,0 +1,904 @@
+/*
+  ******************************************************************************
+  * @file    HAL_Uart.c
+  * @version V1.0.0
+  * @date    2020
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+
+/* If Use 'UART_MODE_TX_RX_DEBUG', Point to Debug Uart */
+UART_TypeDef    *Uart_Debug = NULL;
+
+/* Private function prototypes -----------------------------------------------*/
+static void UART_Config_BaudRate(UART_HandleTypeDef *huart);
+static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart);
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+
+/*********************************************************************************
+* Function    : HAL_UART_IRQHandler
+* Description : Handle UART interrupt request.
+* Input       : huart: UART handle.
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+    uint32_t  read_bytes_number;
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return;
+#endif
+
+    uint32_t isrflags =READ_REG(huart->Instance->RIS);
+    uint32_t ieits    =READ_REG(huart->Instance->IE);
+	uint32_t errorflags =0x00U;
+    errorflags =(isrflags & (uint32_t)(UART_ICR_PEI|UART_ICR_OEI|UART_ICR_FEI|UART_ICR_BEI));
+
+    /* Enable TXI */
+    if (huart->Instance->IE & UART_IE_TXI)
+    {
+        if (huart->Instance->RIS & UART_RIS_TXI)
+        {
+            /* Clear TXI Status */
+            SET_BIT(huart->Instance->ICR , UART_ICR_TXI);
+
+            for(;;)
+            {
+                if(huart->lu32_TxCount == huart->lu32_TxSize)
+                {
+                    huart->lu8_TxBusy = false;
+
+                    /* Disable TX interrupt */
+                    CLEAR_BIT(huart->Instance->IE, UART_IE_TXI);
+
+                    HAL_UART_TxCpltCallback(huart);
+                    break;
+                }
+
+                if (READ_BIT(huart->Instance->FR, UART_FR_TXFF))
+                {
+                    break;
+                }
+
+                huart->Instance->DR = huart->lu8_TxData[huart->lu32_TxCount++];
+            }
+        }
+    }
+
+    /* RXI */
+    if ((huart->Instance->IE & UART_IE_RXI || huart->Instance->IE& UART_IE_RTI) && errorflags == 0)
+	{
+		if (huart->Instance->RIS & UART_RIS_RXI)
+		{
+            read_bytes_number = 0;
+			/* Clear RXI Status */
+			SET_BIT(huart->Instance->ICR, UART_ICR_RXI);
+
+			/* Receive end */
+			while(huart->lu32_RxCount <huart->lu32_RxSize )
+			{
+				if(!READ_BIT(huart->Instance->FR, UART_FR_RXFE))
+				{
+					 /* Store Data in buffer */
+					 huart->lu8_RxData[huart->lu32_RxCount++] = huart->Instance->DR;
+                     read_bytes_number++;
+				}
+				else
+			    {
+					break;
+			    }
+                if (read_bytes_number == huart->lu32_fifo_level_minus1)
+                {
+                    break;
+                }
+			}
+			if(huart->lu32_RxCount ==huart->lu32_RxSize )
+			{
+				huart->lu8_RxBusy = false;
+
+				/* Disable RX and RTI interrupt */
+				CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI|UART_IE_RTI));
+
+				/* clear error interrupt */
+				CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI);
+
+				HAL_UART_RxCpltCallback(huart);
+		   }
+		}
+		else if(huart->Instance->RIS & UART_RIS_RTI)
+		{
+			/*clear RTI Status */
+			SET_BIT(huart->Instance->ICR ,UART_ICR_RTI);
+
+			while(!READ_BIT(huart->Instance->FR, UART_FR_RXFE))
+			{
+				huart->lu8_RxData[huart->lu32_RxCount++] = huart->Instance->DR;
+			}
+
+			huart->lu8_RxBusy = false;
+
+			/* Disable RX and RTI interrupt */
+			CLEAR_BIT(huart->Instance->IE, (UART_IE_RXI|UART_IE_RTI));
+
+			/* clear error interrupt */
+			CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI);
+
+			HAL_UART_RxCpltCallback(huart);
+		}
+	}
+	/* if some errors occurred */
+	if(errorflags != 0 &&(ieits & (UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI)))
+	{
+		/* UART parity error interrupt occurred */
+	    if (((isrflags & UART_RIS_PEI) != 0) && ((ieits & UART_IE_PEI) != 0))
+	    {
+	    	/* Clear parity error status */
+			SET_BIT(huart->Instance->ICR, UART_ICR_PEI);
+	      	huart->ErrorCode |= HAL_UART_ERROR_PE;
+	    }
+
+	    /* UART break error interrupt occurred */
+	    if (((isrflags & UART_RIS_BEI) != 0) && ((ieits & UART_IE_BEI) != 0))
+	    {
+	    	SET_BIT(huart->Instance->ICR, UART_RIS_BEI);
+	      	huart->ErrorCode |= HAL_UART_ERROR_NE;
+	    }
+
+	    /* UART frame error interrupt occurred */
+	    if (((isrflags & UART_RIS_FEI) != 0) && ((ieits & UART_IE_FEI) != 0))
+	    {
+	    	SET_BIT(huart->Instance->ICR, UART_RIS_FEI);
+	      	huart->ErrorCode |= HAL_UART_ERROR_FE;
+	    }
+
+	    /* UART Over-Run interrupt occurred */
+	    if (((isrflags & UART_RIS_OEI) != 0) && ((ieits & UART_IE_OEI) != 0))
+	    {
+	    	SET_BIT(huart->Instance->ICR, UART_RIS_OEI);
+	      	huart->ErrorCode |= HAL_UART_ERROR_ORE;
+	    }
+
+		/* clear error interrupt */
+		CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI);
+
+		HAL_UART_ErrorCallback(huart);
+	}
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Wait_Tx_Done
+* Description : wait Tx FIFO empty
+* Input       : huart: UART handle.
+* Output      :
+**********************************************************************************/
+static HAL_StatusTypeDef HAL_UART_Wait_Tx_Done(UART_HandleTypeDef *huart)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))         return HAL_ERROR;
+#endif
+	/* wait FIFO empty */
+	while(READ_BIT(huart->Instance->FR, UART_FR_BUSY));
+
+	return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_MspInit
+* Description : Initialize the UART MSP.
+* Input       : huart: UART handle.
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+    /*
+      NOTE: This function should be modified, when the callback is needed,
+      the HAL_UART_MspInit can be implemented in the user file.
+    */
+
+    /* For Example */
+    GPIO_InitTypeDef    GPIO_Uart1;
+
+    if (huart->Instance == UART1)
+    {
+        /* Enable Clock */
+        System_Module_Enable(EN_UART1);
+        //System_Module_Enable(EN_GPIOAB);
+
+        /* Initialization GPIO */
+        /* A9:Tx  A10:Rx */
+        GPIO_Uart1.Pin       = GPIO_PIN_9 | GPIO_PIN_10;
+        GPIO_Uart1.Mode      = GPIO_MODE_AF_PP;
+        GPIO_Uart1.Pull      = GPIO_PULLUP;
+        GPIO_Uart1.Alternate = GPIO_FUNCTION_2;
+
+        HAL_GPIO_Init(GPIOA, &GPIO_Uart1);
+
+        if (huart->Init.HwFlowCtl & UART_HWCONTROL_CTS)
+        {
+            /* A11:CTS */
+            GPIO_Uart1.Pin = GPIO_PIN_11;
+
+            HAL_GPIO_Init(GPIOA, &GPIO_Uart1);
+        }
+
+        if (huart->Init.HwFlowCtl & UART_HWCONTROL_RTS)
+        {
+            /* A12:RTS */
+            GPIO_Uart1.Pin = GPIO_PIN_12;
+
+            HAL_GPIO_Init(GPIOA, &GPIO_Uart1);
+        }
+
+        /* NVIC Config */
+        NVIC_ClearPendingIRQ(UART1_IRQn);
+        NVIC_SetPriority(UART1_IRQn, 5);
+        NVIC_EnableIRQ(UART1_IRQn);
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Init
+* Description : Initialize the UART mode according to the specified parameters
+*               in the UART_InitTypeDef
+* Input       : huart: UART handle.
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))                   return HAL_ERROR;
+    if (!IS_UART_WORDLENGTH(huart->Init.WordLength))              return HAL_ERROR;
+    if (!IS_UART_STOPBITS(huart->Init.StopBits))                  return HAL_ERROR;
+    if (!IS_UART_PARITY(huart->Init.Parity))                      return HAL_ERROR;
+    if (!IS_UART_MODE(huart->Init.Mode))                          return HAL_ERROR;
+    if (!IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl))    return HAL_ERROR;
+#endif
+
+    /* Init the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_UART_MspInit(huart);
+
+    /* Config BaudRate */
+    UART_Config_BaudRate(huart);
+
+    /* Set the UART Communication parameters */
+    //huart->Instance->LCRH = huart->Init.WordLength | UART_LCRH_FEN | huart->Init.StopBits | huart->Init.Parity;
+    huart->Instance->LCRH = huart->Init.WordLength | huart->Init.StopBits | huart->Init.Parity;
+    huart->Instance->CR = huart->Init.HwFlowCtl | huart->Init.Mode | UART_CR_UARTEN;
+
+    if (huart->Init.Mode == UART_MODE_TX_RX_DEBUG)
+    {
+        Uart_Debug = huart->Instance;
+    }
+    else if (huart->Init.Mode == UART_MODE_HALF_DUPLEX)
+    {
+        huart->Instance->CR2 = UART_CR2_TXOE_SEL;
+    }
+	return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_MspDeInit
+* Description : DeInitialize the UART MSP.
+* Input       : huart: UART handle.
+* Output      :
+**********************************************************************************/
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+    /*
+      NOTE: This function should be modified, when the callback is needed,
+      the HAL_UART_MspDeInit can be implemented in the user file.
+    */
+    if (huart->Instance == UART1)
+    {
+        /* Disable Clock */
+        System_Module_Disable(EN_UART1);
+
+        /* DeInitialization GPIO */
+        /* A9:Tx  A10:Rx */
+        HAL_GPIO_DeInit(GPIOA,GPIO_PIN_9 | GPIO_PIN_10);
+
+		if (huart->Init.HwFlowCtl & UART_HWCONTROL_CTS)
+        {
+            /* A11:CTS */
+            HAL_GPIO_DeInit(GPIOA, GPIO_PIN_11);
+        }
+
+        if (huart->Init.HwFlowCtl & UART_HWCONTROL_RTS)
+        {
+            /* A12:RTS */
+            HAL_GPIO_DeInit(GPIOA, GPIO_PIN_12);
+        }
+
+        /* NVIC DeInit */
+        NVIC_DisableIRQ(UART1_IRQn);
+
+    }
+	else if(huart->Instance == UART2)
+	{
+
+	}
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Init
+* Description : Initialize the UART mode according to the specified parameters
+*               in the UART_InitTypeDef
+* Input       : huart: UART handle.
+* Output      :
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))         return HAL_ERROR;
+#endif
+
+    /* DeInit the low level hardware : GPIO, CLOCK, NVIC */
+    HAL_UART_MspDeInit(huart);
+
+	return HAL_OK;
+
+}
+
+
+/*********************************************************************************
+* Function    : HAL_UART_Transmit
+* Description : Send an amount of data in blocking mode.
+* Input       : huart:        UART handle.
+* Input       : fu8_Data:     Pointer to data buffer.
+* Input       : fu32_Size:    Amount of data elements to be sent.
+* Input       : fu32_Timeout: Timeout duration.
+* Output      : HAL status
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout)
+{
+    uint32_t lu32_Timeout;
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+    huart->lu32_TxCount = 0;
+
+    while (fu32_Size--)
+    {
+        huart->Instance->DR = *fu8_Data++;
+
+        huart->lu32_TxCount++;
+
+        /* have no timeout */
+        if (fu32_Timeout == 0)
+        {
+            while (huart->Instance->FR & UART_FR_TXFF);
+        }
+        else
+        {
+            lu32_Timeout = fu32_Timeout *256;
+
+            while (huart->Instance->FR & UART_FR_TXFF)
+            {
+                if (lu32_Timeout-- == 0)
+                {
+                    return HAL_TIMEOUT;
+                }
+            }
+        }
+    }
+
+    while ((huart->Instance->FR & UART_FR_BUSY));
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Receive
+* Description : Receive an amount of data in blocking mode.
+* Input       : huart:        UART handle.
+* Input       : fu8_Data:     Pointer to data buffer.
+* Input       : fu32_Size:    Amount of data elements to be receive.
+* Input       : fu32_Timeout: Timeout duration.
+* Output      : HAL status
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size, uint32_t fu32_Timeout)
+{
+    uint32_t lu32_Timeout;
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+    huart->lu32_RxCount = 0;
+
+    /* Half duplex Use Tx GPIO Receive Data */
+    if (huart->Init.Mode == UART_MODE_HALF_DUPLEX)
+    {
+        huart->Instance->CR2 |= UART_CR2_RX_SEL;
+    }
+
+    while (fu32_Size--)
+    {
+        if (fu32_Timeout == 0)
+        {
+            while(huart->Instance->FR & UART_FR_RXFE);
+
+            *fu8_Data++ = huart->Instance->DR;
+
+            huart->lu32_RxCount++;
+        }
+        else
+        {
+            lu32_Timeout = fu32_Timeout * 256;
+
+            while(huart->Instance->FR & UART_FR_RXFE)
+            {
+                if (lu32_Timeout-- == 0)
+                {
+                    /* Clear Half duplex */
+                    huart->Instance->CR2 &= ~UART_CR2_RX_SEL;
+
+                    return HAL_TIMEOUT;
+                }
+            }
+
+            *fu8_Data++ = huart->Instance->DR;
+
+            huart->lu32_RxCount++;
+        }
+    }
+
+    /* Clear Half duplex */
+    huart->Instance->CR2 &= ~UART_CR2_RX_SEL;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Transmit_IT
+* Description : Send an amount of data in interrupt mode.
+* Input       : huart:        UART handle.
+* Input       : fu8_Data:     Pointer to data buffer.
+* Input       : fu32_Size:    Amount of data elements to be receive.
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+    if (huart->lu8_TxBusy == true)
+    {
+        return HAL_BUSY;
+    }
+
+    if (fu32_Size == 0 || fu8_Data == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    huart->lu32_TxSize  = fu32_Size;
+    huart->lu32_TxCount = 0;
+    huart->lu8_TxData   = fu8_Data;
+    huart->lu8_TxBusy   = true;
+
+    /* Clear TXI Status */
+    huart->Instance->ICR = UART_ICR_TXI;
+    /* FIFO Enable */
+    SET_BIT(huart->Instance->LCRH, UART_LCRH_FEN);
+	/*FIFO Select*/
+	SET_BIT(huart->Instance->IFLS,UART_TX_FIFO_1_2);
+
+    for(;;)
+    {
+        /*Data Size less than 16Byte */
+	    if(fu32_Size == huart->lu32_TxCount)
+	    {
+	        huart->lu8_TxBusy = false;
+
+			while ((huart->Instance->FR & UART_FR_BUSY)){}
+
+	        HAL_UART_TxCpltCallback(huart);
+
+	        return HAL_OK;
+	    }
+	    if(READ_BIT(huart->Instance->FR, UART_FR_TXFF))
+	    {
+	         break;
+	    }
+	    huart->Instance->DR = huart->lu8_TxData[huart->lu32_TxCount++];
+    }
+
+    /* Enable TX interrupt */
+    huart->Instance->IE |= UART_IE_TXI;
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Receive_IT
+* Description : Receive an amount of data in interrupt mode.
+* Input       :
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+    if (huart->lu8_RxBusy == true)
+    {
+        return HAL_BUSY;
+    }
+
+    if (fu32_Size == 0 || fu8_Data == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    huart->lu32_RxSize  = fu32_Size;
+    huart->lu32_RxCount = 0;
+    huart->lu8_RxData   = fu8_Data;
+    huart->lu8_RxBusy   = true;
+
+    /* Clear RXI Status */
+    huart->Instance->ICR = UART_ICR_RXI;
+    /* FIFO Enable */
+    SET_BIT(huart->Instance->LCRH, UART_LCRH_FEN);
+	/*FIFO Select*/
+	MODIFY_REG(huart->Instance->IFLS, UART_IFLS_RXIFLSEL, UART_RX_FIFO_1_2);
+    huart->lu32_fifo_level_minus1 = 8-1;  // 16/2 - 1
+	/* Enable the UART Errors interrupt */
+	SET_BIT(huart->Instance->IE,UART_IE_OEI|UART_IE_BEI|UART_IE_PEI|UART_IE_FEI);
+    /* Enable RX and RTI interrupt */
+    SET_BIT(huart->Instance->IE,UART_IE_RXI|UART_IE_RTI);
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Transmit_DMA
+* Description : Send an amount of data in DMA mode.
+* Input       : huart:        UART handle.
+* Input       : fu8_Data:     Pointer to data buffer.
+* Input       : fu32_Size:    Amount of data elements to be Send.
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+    if (huart->lu8_TxBusy == true)
+    {
+        return HAL_BUSY;
+    }
+
+    if (fu32_Size == 0 || fu8_Data == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    huart->Instance->DMACR |= UART_DMACR_TXDMAE;
+
+    if (HAL_DMA_Start_IT(huart->HDMA_Tx, (uint32_t)fu8_Data, (uint32_t)(&huart->Instance->DR), fu32_Size))
+    {
+        return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+/*********************************************************************************
+<<<<<<< .mine
+* Function    : HAL_UART_Receive_DMA
+* Description : Receive an amount of data in DMA mode.
+* Input       : huart:        UART handle.
+* Input       : fu8_Data:     Pointer to data buffer.
+* Input       : fu32_Size:    Amount of data elements to be receive.
+* Output      :
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *fu8_Data, uint32_t fu32_Size)
+{
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+    if (huart->lu8_RxBusy == true)
+    {
+        return HAL_BUSY;
+    }
+
+    if (fu32_Size == 0 || fu8_Data == NULL)
+    {
+        return HAL_ERROR;
+    }
+
+    huart->Instance->DMACR |= UART_DMACR_RXDMAE;
+
+    if (HAL_DMA_Start_IT(huart->HDMA_Rx, (uint32_t)(&huart->Instance->DR), (uint32_t)fu8_Data, fu32_Size))
+    {
+        return HAL_ERROR;
+    }
+
+    return HAL_OK;
+}
+
+
+
+/*********************************************************************************
+* Function    : HAL_UART_TxCpltCallback
+* Description : Tx Transfer completed callbacks.
+* Input       :
+* Output       :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+    /*
+      NOTE: This function Should be modified, when the callback is needed,
+      the HAL_UART_TxCpltCallback could be implemented in the user file.
+    */
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_RxCpltCallback
+* Description : Rx Transfer completed callbacks.
+* Input       :
+* Output       :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+    /*
+      NOTE: This function Should be modified, when the callback is needed,
+      the HAL_UART_RxCpltCallback could be implemented in the user file.
+    */
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_ErrorCallBack
+* Description : Recv Error callbacks.
+* Input       :
+* Output      :
+**********************************************************************************/
+__weak void HAL_UART_ErrorCallBack(UART_HandleTypeDef *huart)
+{
+    /*
+      NOTE: This function Should be modified, when the callback is needed,
+      the HAL_UART_ErrorCallBack could be implemented in the user file.
+    */
+}
+
+/*********************************************************************************
+* Function    : UART_Config_BaudRate
+* Description : Config BaudRate
+* Input       :
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+static void UART_Config_BaudRate(UART_HandleTypeDef *huart)
+{
+    uint32_t lu32_PCLK;
+    uint32_t lu32_IBAUD, lu32_FBAUD;
+    uint64_t lu64_TempValue;
+
+    lu32_PCLK = System_Get_APBClock();
+
+    /* Integral part */
+    lu32_IBAUD = lu32_PCLK / (huart->Init.BaudRate * 16);
+
+    /* Fractional part */
+    lu64_TempValue = lu32_PCLK % (huart->Init.BaudRate * 16);
+    lu64_TempValue = (lu64_TempValue * 1000000) / (huart->Init.BaudRate * 16);
+    lu32_FBAUD     = (lu64_TempValue * 64 + 500000) / 1000000;
+
+    if (lu32_FBAUD >= 64)
+    {
+        huart->Instance->IBRD = lu32_IBAUD + 1;
+        huart->Instance->FBRD = 0;
+    }
+    else
+    {
+        huart->Instance->IBRD = lu32_IBAUD;
+        huart->Instance->FBRD = lu32_FBAUD;
+    }
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_GetState
+* Description : Return the uart State
+* Input       :
+* Output      :
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
+{
+
+#if (USE_FULL_ASSERT == 1)
+    if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+	if(huart->lu8_TxBusy || huart->lu8_RxBusy)
+	{
+		return HAL_BUSY;
+	}
+
+	return HAL_OK;
+}
+
+
+/*********************************************************************************
+* Function    : HAL_UART_GetError
+* Description : Return the uart Error
+* Input       :
+* Output      :
+**********************************************************************************/
+uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
+{
+  	return huart->ErrorCode;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_Abort
+* Description : Abort ongoing transfers(blocking mode)
+* Input       : UART handle
+* Output      :
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+#if (USE_FULL_ASSERT == 1)
+	if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+	/*disble all interrupt*/
+	huart->Instance->IE  =0x00;
+
+	/* Disable the UART DMA Tx request if enable */
+	if(READ_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE))
+	{
+		CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE);
+
+		/* Abort the UART Tx Channel   */
+		if(huart->HDMA_Tx)
+		{
+			/*Set the UART DMA Abort callback to Null */
+			huart->HDMA_Tx->DMA_ITC_Callback =NULL;
+
+			if(HAL_DMA_Abort(huart->HDMA_Tx)!=HAL_OK)
+			{
+				return HAL_TIMEOUT;
+			}
+		}
+	}
+
+	/* Disable the UART DMA Rx request if enable */
+	if(READ_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE))
+	{
+		CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE);
+
+		/* Abort the UART Rx Channel   */
+		if(huart->HDMA_Rx)
+		{
+			/*Set the UART DMA Abort callback to Null */
+			huart->HDMA_Rx->DMA_ITC_Callback =NULL;
+
+			if(HAL_DMA_Abort(huart->HDMA_Rx)!=HAL_OK)
+			{
+				return HAL_TIMEOUT;
+			}
+		}
+	}
+
+	/*Reset Tx and Rx Transfer size*/
+	huart->lu32_TxSize = 0;
+	huart->lu32_RxSize = 0;
+
+	/* Restore huart->lu8_TxBusy and huart->lu8_RxBusy to Ready */
+	huart->lu8_TxBusy = false;
+	huart->lu8_RxBusy = false;
+
+	return HAL_OK;
+}
+
+/*********************************************************************************
+* Function    : HAL_UART_DMAPause
+* Description : Pause the DMA Transfer
+* Input       : UART handle
+* Output      :
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+#if (USE_FULL_ASSERT == 1)
+		if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+  if(READ_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE))
+  {
+    /* Disable the UART DMA Tx request */
+    CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE);
+  }
+
+  if (READ_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE))
+  {
+    /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+    CLEAR_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_FEI);
+
+    /* Disable the UART DMA Rx request */
+    CLEAR_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE);
+  }
+
+  return HAL_OK;
+}
+
+
+/*********************************************************************************
+* Function	  : HAL_UART_DMAResume
+* Description : Resume the DMA Transfer
+* Input 	  : UART handle
+* Output	  :
+**********************************************************************************/
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+#if (USE_FULL_ASSERT == 1)
+		if (!IS_UART_ALL_INSTANCE(huart->Instance))    return HAL_ERROR;
+#endif
+
+  if (huart->lu8_TxBusy == false)
+  {
+	/* Enable the UART DMA Tx request */
+	SET_BIT(huart->Instance->DMACR, UART_DMACR_TXDMAE);
+  }
+
+  if (huart->lu8_RxBusy == false)
+  {
+	/* Reenable PE and ERR (Frame error, noise error, overrun error) interrupts */
+	SET_BIT(huart->Instance->IE, UART_IE_OEI|UART_IE_BEI|UART_IE_FEI);
+
+	/* Enable the UART DMA Rx request */
+	SET_BIT(huart->Instance->DMACR, UART_DMACR_RXDMAE);
+  }
+
+  return HAL_OK;
+}
+
+#if 0
+/*********************************************************************************
+* Function    : fputc
+* Description :
+* Input       :
+* Output      :
+* Author      : Chris_Kyle                         Data : 2020
+**********************************************************************************/
+__weak int fputc(int ch, FILE *f)
+{
+    if (Uart_Debug == NULL)
+    {
+        return 0;
+    }
+
+    Uart_Debug->DR = ch;
+
+    while ((Uart_Debug->FR & UART_FR_BUSY));
+
+    return ch;
+}
+#endif
+

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_UART_EX.c

@@ -0,0 +1,247 @@
+/*
+  ******************************************************************************
+  * @file    HAL_UART_EX.c
+  * @version V1.0.0
+  * @date    2021
+  * @brief   LIN HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the extensional module: Local Interconnect Network Peripheral (LIN).
+  *           @ Initialization and de-initialization functions
+  *           @ IO operation functions
+  *           @ Peripheral Control functions
+  ******************************************************************************
+*/
+#include "ACM32Fxx_HAL.h"
+
+/************************************************************************
+ * function   : HAL_UART_LIN_Master_Transmit
+ * Description: Uart lin master transmit data
+ * input :none
+ *         UART_HandleTypeDef *huart: Serial port number 
+ *         uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX.
+ *         uint8_t Lin_Id: LIN id 
+ *         uint8_t *pData: point to the transmit data buffer. 
+ *         uint8_t Size: Transmit buffer Size. 
+ * return: none
+ ************************************************************************/
+void HAL_UART_LIN_Master_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size)
+{
+    uint8_t Lin_P0,Lin_P1,ucI;
+    uint16_t Lin_Check_Sum = 0;
+    
+    if((Size>8)||(pData == 0))
+        return;
+
+    CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI);
+    huart->Instance->CR = 0x0101; //disable uart_rx
+    
+    MODIFY_REG(huart->Instance->BCNT, UART_EX_BCNT_VALUE_MASK, (13)<<UART_EX_BCNT_VALUE_POS);
+    //Transmit break field.
+    SET_BIT(huart->Instance->BCNT, UART_EX_BCNT_START);
+    SET_BIT(huart->Instance->LCRH, UART_LCRH_BRK);
+    
+    while(!(READ_BIT(huart->Instance->RIS, UART_EX_RIS_BCNTI))){}  //Check BCNTI.
+    CLEAR_BIT(huart->Instance->LCRH, UART_LCRH_BRK);
+
+    HAL_UART_Transmit(huart, (uint8_t*)"\x55", 1, 0);   //Transmit sync field
+        
+    Lin_Id &= 0x3F; //Lin address check, 0-63.
+    Lin_P0 = (Lin_Id^(Lin_Id>>1)^(Lin_Id>>2)^(Lin_Id>>4))&0x01;         //P0 = ID0^ID1^ID2^ID4
+    Lin_P1 = (~((Lin_Id>>1)^(Lin_Id>>3)^(Lin_Id>>4)^(Lin_Id>>5)))&0x01;    //P1 = ~(ID1^ID3^ID4^ID5)
+    Lin_Id = Lin_Id | (Lin_P0<<6) | (Lin_P1<<7);
+
+    HAL_UART_Transmit(huart, &Lin_Id, 1, 0);   //Transmit pid field
+        
+    if(Lin_Version==UART_LIN_V2DX)
+        Lin_Check_Sum = Lin_Id;       //LIN 2.X check sum calc with PID.
+    
+    if(Size)
+    {
+        for(ucI=0;ucI<Size;ucI++)
+        {
+            Lin_Check_Sum += pData[ucI];
+            if(Lin_Check_Sum>0xFF)
+                Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF;
+        }
+        Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF;
+        
+        HAL_UART_Transmit(huart, pData, Size, 0);   //Transmit data field
+        
+        HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0);   //Transmit Lin_Check_Sum field
+    }
+}
+
+/************************************************************************
+ * function   : HAL_UART_LIN_Slave_Transmit
+ * Description: Uart lin slave transmit data
+ * input :none
+ *         UART_HandleTypeDef *huart: Serial port number 
+ *         uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX.
+ *         uint8_t Lin_Id: LIN id 
+ *         uint8_t *pData: point to the transmit data buffer. 
+ *         uint8_t Size: Transmit buffer Size. 
+ * return: none
+ ************************************************************************/
+void HAL_UART_LIN_Slave_Transmit(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint8_t Size)
+{
+    uint8_t Lin_P0,Lin_P1,ucI;
+    uint16_t Lin_Check_Sum = 0;
+    
+    if((Size>8)||(pData == 0))
+        return;
+    
+    CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI);//disable LBDI int
+    huart->Instance->CR = 0x0101; //disable uart_rx
+        
+    if(Lin_Version==UART_LIN_V2DX)
+        Lin_Check_Sum = Lin_Id;       //LIN 2.X check sum calc with PID.
+    
+    for(ucI=0;ucI<Size;ucI++)
+    {
+        Lin_Check_Sum += pData[ucI];
+        if(Lin_Check_Sum>0xFF)
+            Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF;
+    }
+    Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF;
+    
+    HAL_UART_Transmit(huart, pData, Size, 0);   //Transmit data field
+    
+    HAL_UART_Transmit(huart, (uint8_t*)&Lin_Check_Sum, 1, 0);   //Transmit Lin_Check_Sum field
+}
+
+/************************************************************************
+ * function   : HAL_UART_LIN_Master_Receive
+ * Description: Uart lin master receive data
+ * input :none
+ *         UART_HandleTypeDef *huart: Serial port number 
+ *         uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX.
+ *         uint8_t Lin_Id: LIN id 
+ *         uint8_t *pData: point to the data buffer. 
+ * return: uint8_t RxSize
+ ************************************************************************/
+uint8_t HAL_UART_LIN_Master_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t Lin_Id, uint8_t *pData, uint32_t Timeout)
+{
+    uint8_t Lin_P0,Lin_P1,ucI,RxSize;
+    uint8_t Lin_Rx_Buf[16];
+    uint8_t ucStatus;
+    uint16_t Lin_Check_Sum = 0;
+    uint32_t u32_Timeout;
+    
+    if(pData == 0)
+        return 0;
+     
+    huart->Instance->CR =  0x0201; //disable uart_tx
+    huart->Instance->ICR =  0xfff; //clear int
+    huart->Instance->LCRH = 0x70;  //8 data bit,1 stop bit,0 verify bit,enable FIFO
+    huart->Instance->IFLS = 0x12; //FIFO send and receive number is 8
+    huart->Instance->IE = 0x00;  //Disable all interrupt
+    
+    HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout);    
+        
+    if(Lin_Version==UART_LIN_V2DX)
+        Lin_Check_Sum = Lin_Id;       //LIN 2.X check sum calc with PID.
+    
+    if(huart->lu32_RxCount)
+    {
+        for(ucI=0;ucI<(huart->lu32_RxCount-1);ucI++)
+        {
+            Lin_Check_Sum += Lin_Rx_Buf[ucI];
+            if(Lin_Check_Sum>0xFF)
+                Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF;
+        }
+        Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF;  
+        if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI])
+        {
+            RxSize = huart->lu32_RxCount;
+            memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize);
+        }
+        else
+            RxSize = 0xFF;
+    }
+    else
+        RxSize = 0;
+    
+    return RxSize;     
+}
+
+/************************************************************************
+ * function   : HAL_UART_LIN_Slave_Receive
+ * Description: Uart lin slave receive head
+ * input :none
+ *         UART_HandleTypeDef *huart: Serial port number 
+ *         uint8_t Lin_Version: LIN version ,should be UART_LIN_V1D3 or UART_LIN_V2DX.
+ *         uint8_t *pData: point to the data buffer. 
+ * return: uint8_t RxSize
+ ************************************************************************/
+uint8_t HAL_UART_LIN_Slave_Receive(UART_HandleTypeDef *huart, uint8_t Lin_Version, uint8_t *pData, uint32_t Timeout)
+{
+    uint8_t Lin_P0,Lin_P1,ucI,RxSize;
+    uint8_t Lin_Rx_Buf[16];
+    uint8_t ucStatus;
+    uint16_t Lin_Check_Sum = 0;
+    uint32_t u32_Timeout;
+    
+    if(pData == 0)
+        return 0;
+
+    huart->Instance->CR =  0x0201; //disable uart_tx
+    huart->Instance->ICR =  0xfff; //clear int
+    CLEAR_BIT(huart->Instance->IE, UART_EX_IE_LBDI); //Disable LBDI int
+
+    if (Timeout == 0) 
+    {
+        while(!READ_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI));
+    }
+    else 
+    {
+        u32_Timeout = Timeout * 0xFF;
+        
+        while(!READ_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI))
+        {
+            if (u32_Timeout-- == 0) 
+            {                
+                return 0;
+            }
+        }
+    }  
+    CLEAR_BIT(huart->Instance->RIS, UART_EX_RIS_LBDI);        
+    
+    huart->Instance->LCRH = 0x70;  //8 data bit,1 stop bit,0 verify bit,enable FIFO
+    huart->Instance->IFLS = 0x12; //FIFO send and receive number is 8
+    huart->Instance->IE = 0x00;  //Disable all interrupt
+        
+    HAL_UART_Receive(huart, Lin_Rx_Buf, sizeof(Lin_Rx_Buf), Timeout);  //waitting rx completed.  
+       
+    if(huart->lu32_RxCount > 3)
+    {
+        if(Lin_Version==UART_LIN_V2DX)
+            Lin_Check_Sum = Lin_Rx_Buf[2];       //LIN 2.X check sum calc with PID.
+        
+        if(huart->lu32_RxCount)
+        {
+            for(ucI=3;ucI<(huart->lu32_RxCount-1);ucI++)
+            {
+                Lin_Check_Sum += Lin_Rx_Buf[ucI];
+                if(Lin_Check_Sum>0xFF)
+                    Lin_Check_Sum = ((Lin_Check_Sum>>8)+Lin_Check_Sum)&0xFF;
+            }
+            Lin_Check_Sum = (~Lin_Check_Sum) & 0xFF;  
+            if((uint8_t)Lin_Check_Sum == Lin_Rx_Buf[ucI])
+            {
+                RxSize = huart->lu32_RxCount;
+                memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize);
+            }
+            else
+                RxSize = 0xFF;
+        }
+    }
+    else if(huart->lu32_RxCount<=3)
+    {
+        RxSize = huart->lu32_RxCount;
+        memcpy(pData, (uint8_t*)Lin_Rx_Buf, RxSize);
+    }
+    else
+        RxSize = 0;
+    
+    return RxSize;     
+}

bsp/acm32f4xx-nucleo/libraries/HAL_Driver/Src/HAL_WDT.c

@@ -0,0 +1,110 @@
+/***********************************************************************
+ * Filename    : HAL_WDT.c
+ * Description : HAL WDT driver source file
+ * Author(s)   : CWT  
+ * version     : V1.0
+ * Modify date : 2020-04-17  
+ ***********************************************************************/
+#include  "ACM32Fxx_HAL.h"
+
+/************************************************************************
+ * function   : HAL_WDT_Feed
+ * Description: WDT feed. 
+ * input : 
+ *         none 
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Feed(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->FEED = 0xAA55A55A; 
+}
+/************************************************************************
+ * function   : HAL_WDT_IRQHandler
+ * Description: WDT interrupt service routine. 
+ * input : 
+ *         none 
+ * return: none
+ ************************************************************************/
+void HAL_WDT_IRQHandler(WDT_HandleTypeDef* hwdt)
+{
+    volatile uint32_t wdt_ris = 0;
+    wdt_ris = hwdt->Instance->RIS;
+    HAL_WDT_Feed(hwdt);
+    NVIC_ClearPendingIRQ(WDT_IRQn);  
+}
+
+/************************************************************************
+ * function   : HAL_WDT_Init
+ * Description: WDT initiation. 
+ * input : 
+ *         pinit initiation parameters 
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Init(WDT_HandleTypeDef* hwdt)
+{
+    System_Module_Enable(EN_WDT);    
+    System_Delay(1);
+    System_Enable_Disable_RTC_Domain_Access(FUNC_ENABLE);  
+    System_Enable_Disable_Reset(RESET_ENABLE_SOURCE_WDT, FUNC_ENABLE);  
+    
+    hwdt->Instance->LOAD = hwdt->Init.WDTLoad;
+    hwdt->Instance->CTRL = (hwdt->Instance->CTRL & ~0x47) | (hwdt->Init.WDTDivisor) | (hwdt->Init.WDTMode << 6);	 
+
+    if (WDT_MODE_INT == hwdt->Init.WDTMode)
+    {
+        hwdt->Instance->INTCLRTIME = hwdt->Init.WDTINTCLRTIME; 
+        HAL_WDT_Int_Enable(hwdt);   
+    }
+}
+
+/************************************************************************
+ * function   : HAL_WDT_Start
+ * Description: WDT start
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Start(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL |= WDT_ENABLE;
+}
+
+/************************************************************************
+ * function   : WDT_Stop
+ * Description: WDT stop
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Stop(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL &= WDT_DISABLE;
+}
+
+/************************************************************************
+ * function   : WDT_Int_Enable
+ * Description: WDT int enable
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Int_Enable(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL |= WDT_INT_ENABLE; 
+    NVIC_ClearPendingIRQ(WDT_IRQn);  
+    NVIC_EnableIRQ(WDT_IRQn);
+}
+
+/************************************************************************
+ * function   : WDT_Int_Disable
+ * Description: WDT int disable
+ * input : none
+ *         
+ * return: none
+ ************************************************************************/
+void HAL_WDT_Int_Disable(WDT_HandleTypeDef* hwdt)
+{
+    hwdt->Instance->CTRL &= WDT_INT_DISABLE;
+}
+
+

bsp/acm32f4xx-nucleo/libraries/SConscript

@@ -0,0 +1,35 @@
+import rtconfig
+Import('RTT_ROOT')
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+src = Split("""
+Device/System_ACM32F4.c
+HAL_Driver/Src/HAL_EFlash.c
+HAL_Driver/Src/HAL_DMA.c
+HAL_Driver/Src/HAL_GPIO.c
+HAL_Driver/Src/HAL_UART.c
+HAL_Driver/Src/HAL_EXTI.c
+""")
+
+
+libpath = ['.', cwd + '/Device', cwd + '/HAL_Driver/Src']
+libs = ['System_Accelerate', 'HAL_EFlash_EX']
+
+if rtconfig.CROSS_TOOL == 'gcc':
+    src += ['Device/Startup_ACM32F4_gcc.s']
+elif rtconfig.CROSS_TOOL == 'keil':
+    src += ['Device/Startup_ACM32F4.s']
+elif rtconfig.CROSS_TOOL == 'iar':
+    src += ['Device/Startup_ACM32F4_iar.s']
+
+path = [cwd + '/HAL_Driver/Inc',
+    cwd + '/Device',
+    cwd + '/CMSIS']
+
+group = DefineGroup('ACM32_HAL', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath)
+
+Return('group')
+

bsp/acm32f4xx-nucleo/project.uvoptx

@@ -0,0 +1,985 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ACM32F4XX</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>14</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI_V8M</Key>
+          <Name>-X"CMSIS-DAP AISINOCHIP V1.0" -UCMSIS-DAP AISINOCHIP V1.0 -O206 -S10 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>-UV0VVV123 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
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bsp/acm32f4xx-nucleo/project.uvprojx

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+  <Header>### uVision Project, (C) Keil Software</Header>
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+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20200000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define>RT_USING_ARM_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND</Define>
+              <Undefine></Undefine>
+              <IncludePath>libraries\HAL_Driver\Inc;libraries\Device;libraries\CMSIS;applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m33;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;drivers;..\..\components\finsh;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common;..\..\components\libc\compilers\common\nogcc;..\..\examples\utest\testcases\kernel</IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+      <Groups>
+        <Group>
+          <GroupName>ACM32_HAL</GroupName>
+          <Files>
+            <File>
+              <FileName>HAL_UART.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\HAL_Driver\Src\HAL_UART.c</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_EXTI.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\HAL_Driver\Src\HAL_EXTI.c</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_DMA.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\HAL_Driver\Src\HAL_DMA.c</FilePath>
+            </File>
+            <File>
+              <FileName>Startup_ACM32F4.s</FileName>
+              <FileType>2</FileType>
+              <FilePath>libraries\Device\Startup_ACM32F4.s</FilePath>
+            </File>
+            <File>
+              <FileName>System_ACM32F4.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\Device\System_ACM32F4.c</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_GPIO.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\HAL_Driver\Src\HAL_GPIO.c</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_EFlash.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>libraries\HAL_Driver\Src\HAL_EFlash.c</FilePath>
+            </File>
+            <File>
+              <FileName>System_Accelerate.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>libraries\Device\System_Accelerate.lib</FilePath>
+            </File>
+            <File>
+              <FileName>HAL_EFlash_EX.lib</FileName>
+              <FileType>4</FileType>
+              <FilePath>libraries\HAL_Driver\Src\HAL_EFlash_EX.lib</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>CPU</GroupName>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>syscall_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m33\syscall_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m33\context_rvds.S</FilePath>
+            </File>
+            <File>
+              <FileName>trustzone.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m33\trustzone.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\libcpu\arm\cortex-m33\cpuport.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <Files>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\ringblk_buf.c</FilePath>
+            </File>
+            <File>
+              <FileName>waitqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\waitqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\msh.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\finsh\cmd.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Kernel</GroupName>
+          <Files>
+            <File>
+              <FileName>mem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mem.c</FilePath>
+            </File>
+            <File>
+              <FileName>idle.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\idle.c</FilePath>
+            </File>
+            <File>
+              <FileName>irq.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\irq.c</FilePath>
+            </File>
+            <File>
+              <FileName>scheduler.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\scheduler.c</FilePath>
+            </File>
+            <File>
+              <FileName>mempool.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\mempool.c</FilePath>
+            </File>
+            <File>
+              <FileName>ipc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\ipc.c</FilePath>
+            </File>
+            <File>
+              <FileName>clock.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\clock.c</FilePath>
+            </File>
+            <File>
+              <FileName>device.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\device.c</FilePath>
+            </File>
+            <File>
+              <FileName>object.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\object.c</FilePath>
+            </File>
+            <File>
+              <FileName>kservice.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\kservice.c</FilePath>
+            </File>
+            <File>
+              <FileName>thread.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\thread.c</FilePath>
+            </File>
+            <File>
+              <FileName>timer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\timer.c</FilePath>
+            </File>
+            <File>
+              <FileName>components.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\src\components.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>libc</GroupName>
+          <Files>
+            <File>
+              <FileName>libc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\libc.c</FilePath>
+            </File>
+            <File>
+              <FileName>syscalls.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\syscalls.c</FilePath>
+            </File>
+            <File>
+              <FileName>mem_std.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\armlibc\mem_std.c</FilePath>
+            </File>
+            <File>
+              <FileName>stdlib.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\common\stdlib.c</FilePath>
+            </File>
+            <File>
+              <FileName>time.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\libc\compilers\common\time.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+      </Groups>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>

bsp/acm32f4xx-nucleo/rtconfig.h

@@ -0,0 +1,215 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 4
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 100
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 256
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_DEVICE_OPS
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart1"
+#define RT_VER_NUM 0x40004
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+
+/* C++ features */
+
+
+/* Command shell */
+
+#define RT_USING_FINSH
+#define RT_USING_MSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device virtual file system */
+
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_PIPE_BUFSZ 512
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* POSIX layer and C standard library */
+
+#define RT_USING_LIBC
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* Network */
+
+/* Socket abstraction layer */
+
+
+/* Network interface device */
+
+
+/* light weight TCP/IP stack */
+
+
+/* AT commands */
+
+
+/* VBUS(Virtual Software BUS) */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+
+/* multimedia packages */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+
+/* peripheral libraries and drivers */
+
+
+/* miscellaneous packages */
+
+
+/* samples: kernel and components samples */
+
+
+/* Hardware Drivers Config */
+
+#define SOC_ACM32F403RET7
+
+/* ACM32F403RET7 */
+
+#define SOC_SRAM_START_ADDR 0x20000000
+#define SOC_SRAM_SIZE 0xC0
+#define SOC_FLASH_START_ADDR 0x00000000
+#define SOC_FLASH_SIZE 0x8000
+
+/* Onboard Peripheral Drivers */
+
+/* On-chip Peripheral Drivers */
+
+/* Hardware GPIO */
+
+#define BSP_USING_GPIO1
+#define BSP_USING_GPIO2
+#define BSP_USING_GPIO3
+
+/* Hardware UART */
+
+#define BSP_USING_UART1
+#define BSP_USING_UART2
+#define BSP_UART2_RX_USING_DMA
+#define BSP_UART2_TX_USING_DMA
+#define BSP_USING_UART3
+#define BSP_UART3_RX_USING_DMA
+#define BSP_UART3_TX_USING_DMA
+#define BSP_USING_UART4
+#define BSP_UART4_RX_USING_DMA
+#define BSP_UART4_TX_USING_DMA
+
+/* Hardware I2C */
+
+
+/* Hardware CAN */
+
+
+/* Hardware TIMER */
+
+
+/* Hardware WDT */
+
+
+/* Hardware SPI */
+
+
+/* Hardware CRYPTO */
+
+
+/* Board extended module Drivers */
+
+
+#endif

bsp/acm32f4xx-nucleo/rtconfig.py

@@ -0,0 +1,151 @@
+import os
+
+# toolchains options
+ARCH='arm'
+CPU='cortex-m33'
+CROSS_TOOL='gcc'
+
+# bsp lib config
+BSP_LIBRARY_TYPE = None
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+
+# cross_tool provides the cross compiler
+# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM     = 'gcc'
+    EXEC_PATH     = r'/opt/gcc-arm-none-eabi-6_2-2016q4/bin'
+elif CROSS_TOOL == 'keil':
+    PLATFORM    = 'armcc'
+    EXEC_PATH   = r'D:/Keil_v5'
+elif CROSS_TOOL == 'iar':
+    PLATFORM    = 'iar'
+    EXEC_PATH   = r'D:/Program Files (x86)/IAR Systems/Embedded Workbench 8.2'
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+#BUILD = 'release'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    CXX = PREFIX + 'g++'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb '
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T drivers/linker_scripts/link.lds'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2 -g'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    CXXFLAGS = CFLAGS
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armclang'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --cpu ' + CPU
+    CFLAGS = ' -xc -std=c99 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c'
+    CFLAGS += ' -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -D__MICROLIB -mlittle-endian -ffunction-sections'
+
+    AFLAGS = ' --cpu=Cortex-M33 --fpu=FPv5-SP --li --pd "__MICROLIB SETA 1" --pd "__UVISION_VERSION SETA 531" --pd "ARMCM33_DSP_FP SETA 1"'
+
+    LFLAGS = ' --cpu=Cortex-M33 --info sizes --info totals --info unused --info veneers --list ./build/ACM32F4.map --scatter ./build/ACM32F4.sct'
+    LFLAGS += ' --library_type=microlib --strict'
+    LFLAGS += ' --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols'
+
+    EXEC_PATH += '/ARM/ARMCLANG/bin'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -gdwarf-3 -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -gdwarf-3 -O1'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    CXX = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = '-Dewarm'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse'
+    CFLAGS += ' --no_unroll'
+    CFLAGS += ' --no_inline'
+    CFLAGS += ' --no_code_motion'
+    CFLAGS += ' --no_tbaa'
+    CFLAGS += ' --no_clustering'
+    CFLAGS += ' --no_scheduling'
+    CFLAGS += ' --debug'
+    CFLAGS += ' --endian=little'
+    CFLAGS += ' --cpu=' + CPU
+    CFLAGS += ' -e'
+    CFLAGS += ' --fpu=VFPv4_sp'
+    CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"'
+    CFLAGS += ' --silent'
+
+    AFLAGS = DEVICE
+    AFLAGS += ' -s+'
+    AFLAGS += ' -w+'
+    AFLAGS += ' -r'
+    AFLAGS += ' --cpu ' + CPU
+    AFLAGS += ' --fpu VFPv4_sp'
+    AFLAGS += ' -S'
+
+    if BUILD == 'debug':
+        CFLAGS += ' --debug'
+        CFLAGS += ' -On'
+    else:
+        CFLAGS += ' -Oh'
+
+    CXXFLAGS = CFLAGS
+    LFLAGS = ' --config "drivers/linker_scripts/link.icf"'
+    LFLAGS += ' --entry __iar_program_start'
+
+
+    CXXFLAGS = CFLAGS
+
+    EXEC_PATH = EXEC_PATH + '/arm/bin/'
+    POST_ACTION = 'ielftool --bin $TARGET rtthread.bin'
+
+def dist_handle(BSP_ROOT, dist_dir):
+    import sys
+    cwd_path = os.getcwd()
+    sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools'))
+    from sdk_dist import dist_do_building
+    dist_do_building(BSP_ROOT, dist_dir)
+

bsp/acm32f4xx-nucleo/template.uvoptx

@@ -0,0 +1,321 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
+
+  <SchemaVersion>1.0</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Extensions>
+    <cExt>*.c</cExt>
+    <aExt>*.s*; *.src; *.a*</aExt>
+    <oExt>*.obj; *.o</oExt>
+    <lExt>*.lib</lExt>
+    <tExt>*.txt; *.h; *.inc; *.md</tExt>
+    <pExt>*.plm</pExt>
+    <CppX>*.cpp</CppX>
+    <nMigrate>0</nMigrate>
+  </Extensions>
+
+  <DaveTm>
+    <dwLowDateTime>0</dwLowDateTime>
+    <dwHighDateTime>0</dwHighDateTime>
+  </DaveTm>
+
+  <Target>
+    <TargetName>ACM32F4XX</TargetName>
+    <ToolsetNumber>0x4</ToolsetNumber>
+    <ToolsetName>ARM-ADS</ToolsetName>
+    <TargetOption>
+      <CLKADS>12000000</CLKADS>
+      <OPTTT>
+        <gFlags>1</gFlags>
+        <BeepAtEnd>1</BeepAtEnd>
+        <RunSim>0</RunSim>
+        <RunTarget>1</RunTarget>
+        <RunAbUc>0</RunAbUc>
+      </OPTTT>
+      <OPTHX>
+        <HexSelection>1</HexSelection>
+        <FlashByte>65535</FlashByte>
+        <HexRangeLowAddress>0</HexRangeLowAddress>
+        <HexRangeHighAddress>0</HexRangeHighAddress>
+        <HexOffset>0</HexOffset>
+      </OPTHX>
+      <OPTLEX>
+        <PageWidth>79</PageWidth>
+        <PageLength>66</PageLength>
+        <TabStop>8</TabStop>
+        <ListingPath>.\build\keil\</ListingPath>
+      </OPTLEX>
+      <ListingPage>
+        <CreateCListing>1</CreateCListing>
+        <CreateAListing>1</CreateAListing>
+        <CreateLListing>1</CreateLListing>
+        <CreateIListing>0</CreateIListing>
+        <AsmCond>1</AsmCond>
+        <AsmSymb>1</AsmSymb>
+        <AsmXref>0</AsmXref>
+        <CCond>1</CCond>
+        <CCode>0</CCode>
+        <CListInc>0</CListInc>
+        <CSymb>0</CSymb>
+        <LinkerCodeListing>0</LinkerCodeListing>
+      </ListingPage>
+      <OPTXL>
+        <LMap>1</LMap>
+        <LComments>1</LComments>
+        <LGenerateSymbols>1</LGenerateSymbols>
+        <LLibSym>1</LLibSym>
+        <LLines>1</LLines>
+        <LLocSym>1</LLocSym>
+        <LPubSym>1</LPubSym>
+        <LXref>0</LXref>
+        <LExpSel>0</LExpSel>
+      </OPTXL>
+      <OPTFL>
+        <tvExp>1</tvExp>
+        <tvExpOptDlg>0</tvExpOptDlg>
+        <IsCurrentTarget>1</IsCurrentTarget>
+      </OPTFL>
+      <CpuCode>7</CpuCode>
+      <DebugOpt>
+        <uSim>0</uSim>
+        <uTrg>1</uTrg>
+        <sLdApp>1</sLdApp>
+        <sGomain>1</sGomain>
+        <sRbreak>1</sRbreak>
+        <sRwatch>1</sRwatch>
+        <sRmem>1</sRmem>
+        <sRfunc>1</sRfunc>
+        <sRbox>1</sRbox>
+        <tLdApp>1</tLdApp>
+        <tGomain>1</tGomain>
+        <tRbreak>1</tRbreak>
+        <tRwatch>1</tRwatch>
+        <tRmem>1</tRmem>
+        <tRfunc>0</tRfunc>
+        <tRbox>1</tRbox>
+        <tRtrace>1</tRtrace>
+        <sRSysVw>1</sRSysVw>
+        <tRSysVw>1</tRSysVw>
+        <sRunDeb>0</sRunDeb>
+        <sLrtime>0</sLrtime>
+        <bEvRecOn>1</bEvRecOn>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>14</nTsel>
+        <sDll></sDll>
+        <sDllPa></sDllPa>
+        <sDlgDll></sDlgDll>
+        <sDlgPa></sDlgPa>
+        <sIfile></sIfile>
+        <tDll></tDll>
+        <tDllPa></tDllPa>
+        <tDlgDll></tDlgDll>
+        <tDlgPa></tDlgPa>
+        <tIfile></tIfile>
+        <pMon>BIN\CMSIS_AGDI_V8M.DLL</pMon>
+      </DebugOpt>
+      <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI_V8M</Key>
+          <Name>-X"CMSIS-DAP AISINOCHIP V1.0" -UCMSIS-DAP AISINOCHIP V1.0 -O206 -S10 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>UL2V8M</Key>
+          <Name>-UV0VVV123 -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(1BE12AEB) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC1000 -FN1 -FF0ACM32F4_eflash -FS00 -FL080000</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGTARM</Key>
+          <Name>(6010=-1,-1,-1,-1,0)(6018=-1,-1,-1,-1,0)(6019=-1,-1,-1,-1,0)(6008=-1,-1,-1,-1,0)(6009=-1,-1,-1,-1,0)(6014=-1,-1,-1,-1,0)(6015=-1,-1,-1,-1,0)(6003=-1,-1,-1,-1,0)(6000=-1,-1,-1,-1,0)</Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>ARMDBGFLAGS</Key>
+          <Name></Name>
+        </SetRegEntry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>DLGUARM</Key>
+          <Name></Name>
+        </SetRegEntry>
+      </TargetDriverDllRegistry>
+      <Breakpoint>
+        <Bp>
+          <Number>0</Number>
+          <Type>0</Type>
+          <LineNumber>69</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>10834</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>Z:\Aisinochip\rt-thread\bsp\RT_Thread_v3.13\bsp\uart.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\ACM32F4\../RT_Thread_v3.13/bsp/uart.c\69</Expression>
+        </Bp>
+        <Bp>
+          <Number>1</Number>
+          <Type>0</Type>
+          <LineNumber>140</LineNumber>
+          <EnabledFlag>1</EnabledFlag>
+          <Address>21958</Address>
+          <ByteObject>0</ByteObject>
+          <HtxType>0</HtxType>
+          <ManyObjects>0</ManyObjects>
+          <SizeOfObject>0</SizeOfObject>
+          <BreakByAccess>0</BreakByAccess>
+          <BreakIfRCount>1</BreakIfRCount>
+          <Filename>Z:\Aisinochip\rt-thread\bsp\RT_Thread_v3.13\components\finsh\shell.c</Filename>
+          <ExecCommand></ExecCommand>
+          <Expression>\\ACM32F4\../RT_Thread_v3.13/components/finsh/shell.c\140</Expression>
+        </Bp>
+      </Breakpoint>
+      <WatchWindow1>
+        <Ww>
+          <count>0</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu32_DataBackup</ItemText>
+        </Ww>
+        <Ww>
+          <count>1</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu8_EncrptionData</ItemText>
+        </Ww>
+        <Ww>
+          <count>2</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>lp32_Data</ItemText>
+        </Ww>
+        <Ww>
+          <count>3</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>str_GPIOAB</ItemText>
+        </Ww>
+        <Ww>
+          <count>4</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>str_SCU</ItemText>
+        </Ww>
+        <Ww>
+          <count>5</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu32_GPIOCD</ItemText>
+        </Ww>
+        <Ww>
+          <count>6</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu32_GPIOAB</ItemText>
+        </Ww>
+        <Ww>
+          <count>7</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu8_TxBuffer</ItemText>
+        </Ww>
+        <Ww>
+          <count>8</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>UART1_Handle</ItemText>
+        </Ww>
+        <Ww>
+          <count>9</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu8_RxBuffer</ItemText>
+        </Ww>
+        <Ww>
+          <count>10</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>DMA1</ItemText>
+        </Ww>
+        <Ww>
+          <count>11</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu32_APBClock,0x0A</ItemText>
+        </Ww>
+        <Ww>
+          <count>12</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>gu32_SystemClock,0x0A</ItemText>
+        </Ww>
+        <Ww>
+          <count>13</count>
+          <WinNumber>1</WinNumber>
+          <ItemText>shell</ItemText>
+        </Ww>
+      </WatchWindow1>
+      <MemoryWindow1>
+        <Mm>
+          <WinNumber>1</WinNumber>
+          <SubType>1</SubType>
+          <ItemText>shell</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow1>
+      <MemoryWindow2>
+        <Mm>
+          <WinNumber>2</WinNumber>
+          <SubType>1</SubType>
+          <ItemText>0x40010800</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow2>
+      <MemoryWindow3>
+        <Mm>
+          <WinNumber>3</WinNumber>
+          <SubType>1</SubType>
+          <ItemText>0x10080800</ItemText>
+          <AccSizeX>0</AccSizeX>
+        </Mm>
+      </MemoryWindow3>
+      <Tracepoint>
+        <THDelay>0</THDelay>
+      </Tracepoint>
+      <DebugFlag>
+        <trace>0</trace>
+        <periodic>1</periodic>
+        <aLwin>1</aLwin>
+        <aCover>0</aCover>
+        <aSer1>0</aSer1>
+        <aSer2>0</aSer2>
+        <aPa>0</aPa>
+        <viewmode>1</viewmode>
+        <vrSel>0</vrSel>
+        <aSym>0</aSym>
+        <aTbox>0</aTbox>
+        <AscS1>0</AscS1>
+        <AscS2>0</AscS2>
+        <AscS3>0</AscS3>
+        <aSer3>0</aSer3>
+        <eProf>0</eProf>
+        <aLa>0</aLa>
+        <aPa1>0</aPa1>
+        <AscS4>0</AscS4>
+        <aSer4>0</aSer4>
+        <StkLoc>0</StkLoc>
+        <TrcWin>0</TrcWin>
+        <newCpu>0</newCpu>
+        <uProt>0</uProt>
+      </DebugFlag>
+      <LintExecutable></LintExecutable>
+      <LintConfigFile></LintConfigFile>
+      <bLintAuto>0</bLintAuto>
+      <bAutoGenD>0</bAutoGenD>
+      <LntExFlags>0</LntExFlags>
+      <pMisraName></pMisraName>
+      <pszMrule></pszMrule>
+      <pSingCmds></pSingCmds>
+      <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
+    </TargetOption>
+  </Target>
+
+</ProjectOpt>

bsp/acm32f4xx-nucleo/template.uvprojx

@@ -0,0 +1,401 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
+  <SchemaVersion>2.1</SchemaVersion>
+
+  <Header>### uVision Project, (C) Keil Software</Header>
+
+  <Targets>
+    <Target>
+      <TargetName>ACM32F4XX</TargetName>
+      <ToolsetNumber>0x4</ToolsetNumber>
+      <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
+      <uAC6>1</uAC6>
+      <TargetOption>
+        <TargetCommonOption>
+          <Device>ARMCM33_DSP_FP</Device>
+          <Vendor>ARM</Vendor>
+          <PackID>ARM.CMSIS.5.7.0</PackID>
+          <PackURL>http://www.keil.com/pack/</PackURL>
+          <Cpu>IRAM(0x20000000,0x00020000) IRAM2(0x20200000,0x00020000) IROM(0x00000000,0x00200000) IROM2(0x00200000,0x00200000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP CLOCK(12000000) ESEL ELITTLE</Cpu>
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
+          <FlashDriverDll>UL2V8M(-S0 -C0 -P0 -FD20000000 -FC1000)</FlashDriverDll>
+          <DeviceId>0</DeviceId>
+          <RegisterFile>$$Device:ARMCM33_DSP_FP$Device\ARM\ARMCM33\Include\ARMCM33_DSP_FP.h</RegisterFile>
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
+          <SFDFile></SFDFile>
+          <bCustSvd>0</bCustSvd>
+          <UseEnv>0</UseEnv>
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
+          <TargetStatus>
+            <Error>0</Error>
+            <ExitCodeStop>0</ExitCodeStop>
+            <ButtonStop>0</ButtonStop>
+            <NotGenerated>0</NotGenerated>
+            <InvalidFlash>1</InvalidFlash>
+          </TargetStatus>
+          <OutputDirectory>.\build\keil\</OutputDirectory>
+          <OutputName>ACM32F4XX</OutputName>
+          <CreateExecutable>1</CreateExecutable>
+          <CreateLib>0</CreateLib>
+          <CreateHexFile>1</CreateHexFile>
+          <DebugInformation>1</DebugInformation>
+          <BrowseInformation>1</BrowseInformation>
+          <ListingPath>.\build\keil\</ListingPath>
+          <HexFormatSelection>1</HexFormatSelection>
+          <Merge32K>0</Merge32K>
+          <CreateBatchFile>0</CreateBatchFile>
+          <BeforeCompile>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopU1X>0</nStopU1X>
+            <nStopU2X>0</nStopU2X>
+          </BeforeCompile>
+          <BeforeMake>
+            <RunUserProg1>0</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopB1X>0</nStopB1X>
+            <nStopB2X>0</nStopB2X>
+          </BeforeMake>
+          <AfterMake>
+            <RunUserProg1>1</RunUserProg1>
+            <RunUserProg2>0</RunUserProg2>
+            <UserProg1Name>fromelf.exe --bin --output ./build/ACM32F4.bin ./build/ACM32F4.axf</UserProg1Name>
+            <UserProg2Name></UserProg2Name>
+            <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
+            <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
+            <nStopA1X>0</nStopA1X>
+            <nStopA2X>0</nStopA2X>
+          </AfterMake>
+          <SelectedForBatchBuild>0</SelectedForBatchBuild>
+          <SVCSIdString></SVCSIdString>
+        </TargetCommonOption>
+        <CommonProperty>
+          <UseCPPCompiler>0</UseCPPCompiler>
+          <RVCTCodeConst>0</RVCTCodeConst>
+          <RVCTZI>0</RVCTZI>
+          <RVCTOtherData>0</RVCTOtherData>
+          <ModuleSelection>0</ModuleSelection>
+          <IncludeInBuild>1</IncludeInBuild>
+          <AlwaysBuild>0</AlwaysBuild>
+          <GenerateAssemblyFile>0</GenerateAssemblyFile>
+          <AssembleAssemblyFile>0</AssembleAssemblyFile>
+          <PublicsOnly>0</PublicsOnly>
+          <StopOnExitCode>3</StopOnExitCode>
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
+          <ComprImg>1</ComprImg>
+        </CommonProperty>
+        <DllOption>
+          <SimDllName></SimDllName>
+          <SimDllArguments></SimDllArguments>
+          <SimDlgDll></SimDlgDll>
+          <SimDlgDllArguments></SimDlgDllArguments>
+          <TargetDllName>SARMV8M.DLL</TargetDllName>
+          <TargetDllArguments> -MPU</TargetDllArguments>
+          <TargetDlgDll>TCM.DLL</TargetDlgDll>
+          <TargetDlgDllArguments>-pCM33</TargetDlgDllArguments>
+        </DllOption>
+        <DebugOption>
+          <OPTHX>
+            <HexSelection>1</HexSelection>
+            <HexRangeLowAddress>0</HexRangeLowAddress>
+            <HexRangeHighAddress>0</HexRangeHighAddress>
+            <HexOffset>0</HexOffset>
+            <Oh166RecLen>16</Oh166RecLen>
+          </OPTHX>
+        </DebugOption>
+        <Utilities>
+          <Flash1>
+            <UseTargetDll>1</UseTargetDll>
+            <UseExternalTool>0</UseExternalTool>
+            <RunIndependent>0</RunIndependent>
+            <UpdateFlashBeforeDebugging>0</UpdateFlashBeforeDebugging>
+            <Capability>1</Capability>
+            <DriverSelection>4102</DriverSelection>
+          </Flash1>
+          <bUseTDR>1</bUseTDR>
+          <Flash2>BIN\UL2V8M.DLL</Flash2>
+          <Flash3>"" ()</Flash3>
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
+          <FcArmLst>0</FcArmLst>
+        </Utilities>
+        <TargetArmAds>
+          <ArmAdsMisc>
+            <GenerateListings>0</GenerateListings>
+            <asHll>1</asHll>
+            <asAsm>1</asAsm>
+            <asMacX>1</asMacX>
+            <asSyms>1</asSyms>
+            <asFals>1</asFals>
+            <asDbgD>1</asDbgD>
+            <asForm>1</asForm>
+            <ldLst>0</ldLst>
+            <ldmm>1</ldmm>
+            <ldXref>1</ldXref>
+            <BigEnd>0</BigEnd>
+            <AdsALst>1</AdsALst>
+            <AdsACrf>1</AdsACrf>
+            <AdsANop>0</AdsANop>
+            <AdsANot>0</AdsANot>
+            <AdsLLst>1</AdsLLst>
+            <AdsLmap>1</AdsLmap>
+            <AdsLcgr>1</AdsLcgr>
+            <AdsLsym>1</AdsLsym>
+            <AdsLszi>1</AdsLszi>
+            <AdsLtoi>1</AdsLtoi>
+            <AdsLsun>1</AdsLsun>
+            <AdsLven>1</AdsLven>
+            <AdsLsxf>1</AdsLsxf>
+            <RvctClst>0</RvctClst>
+            <GenPPlst>0</GenPPlst>
+            <AdsCpuType>"Cortex-M33"</AdsCpuType>
+            <RvctDeviceName></RvctDeviceName>
+            <mOS>0</mOS>
+            <uocRom>0</uocRom>
+            <uocRam>0</uocRam>
+            <hadIROM>1</hadIROM>
+            <hadIRAM>1</hadIRAM>
+            <hadXRAM>0</hadXRAM>
+            <uocXRam>0</uocXRam>
+            <RvdsVP>2</RvdsVP>
+            <RvdsMve>0</RvdsMve>
+            <RvdsCdeCp>0</RvdsCdeCp>
+            <hadIRAM2>1</hadIRAM2>
+            <hadIROM2>1</hadIROM2>
+            <StupSel>8</StupSel>
+            <useUlib>1</useUlib>
+            <EndSel>1</EndSel>
+            <uLtcg>0</uLtcg>
+            <nSecure>0</nSecure>
+            <RoSelD>3</RoSelD>
+            <RwSelD>4</RwSelD>
+            <CodeSel>0</CodeSel>
+            <OptFeed>0</OptFeed>
+            <NoZi1>0</NoZi1>
+            <NoZi2>0</NoZi2>
+            <NoZi3>0</NoZi3>
+            <NoZi4>0</NoZi4>
+            <NoZi5>0</NoZi5>
+            <Ro1Chk>0</Ro1Chk>
+            <Ro2Chk>0</Ro2Chk>
+            <Ro3Chk>0</Ro3Chk>
+            <Ir1Chk>1</Ir1Chk>
+            <Ir2Chk>0</Ir2Chk>
+            <Ra1Chk>0</Ra1Chk>
+            <Ra2Chk>0</Ra2Chk>
+            <Ra3Chk>0</Ra3Chk>
+            <Im1Chk>1</Im1Chk>
+            <Im2Chk>0</Im2Chk>
+            <OnChipMemories>
+              <Ocm1>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm1>
+              <Ocm2>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm2>
+              <Ocm3>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm3>
+              <Ocm4>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm4>
+              <Ocm5>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm5>
+              <Ocm6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </Ocm6>
+              <IRAM>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </IRAM>
+              <IROM>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </IROM>
+              <XRAM>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </XRAM>
+              <OCR_RVCT1>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT1>
+              <OCR_RVCT2>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT2>
+              <OCR_RVCT3>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT3>
+              <OCR_RVCT4>
+                <Type>1</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT4>
+              <OCR_RVCT5>
+                <Type>1</Type>
+                <StartAddress>0x200000</StartAddress>
+                <Size>0x200000</Size>
+              </OCR_RVCT5>
+              <OCR_RVCT6>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT6>
+              <OCR_RVCT7>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT7>
+              <OCR_RVCT8>
+                <Type>0</Type>
+                <StartAddress>0x0</StartAddress>
+                <Size>0x0</Size>
+              </OCR_RVCT8>
+              <OCR_RVCT9>
+                <Type>0</Type>
+                <StartAddress>0x20000000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT9>
+              <OCR_RVCT10>
+                <Type>0</Type>
+                <StartAddress>0x20200000</StartAddress>
+                <Size>0x20000</Size>
+              </OCR_RVCT10>
+            </OnChipMemories>
+            <RvctStartVector></RvctStartVector>
+          </ArmAdsMisc>
+          <Cads>
+            <interw>1</interw>
+            <Optim>2</Optim>
+            <oTime>0</oTime>
+            <SplitLS>0</SplitLS>
+            <OneElfS>1</OneElfS>
+            <Strict>0</Strict>
+            <EnumInt>0</EnumInt>
+            <PlainCh>0</PlainCh>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <wLevel>0</wLevel>
+            <uThumb>0</uThumb>
+            <uSurpInc>0</uSurpInc>
+            <uC99>0</uC99>
+            <uGnu>0</uGnu>
+            <useXO>0</useXO>
+            <v6Lang>3</v6Lang>
+            <v6LangP>3</v6LangP>
+            <vShortEn>1</vShortEn>
+            <vShortWch>1</vShortWch>
+            <v6Lto>0</v6Lto>
+            <v6WtE>0</v6WtE>
+            <v6Rtti>0</v6Rtti>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Cads>
+          <Aads>
+            <interw>1</interw>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <thumb>0</thumb>
+            <SplitLS>0</SplitLS>
+            <SwStkChk>0</SwStkChk>
+            <NoWarn>0</NoWarn>
+            <uSurpInc>0</uSurpInc>
+            <useXO>0</useXO>
+            <ClangAsOpt>4</ClangAsOpt>
+            <VariousControls>
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
+            </VariousControls>
+          </Aads>
+          <LDads>
+            <umfTarg>1</umfTarg>
+            <Ropi>0</Ropi>
+            <Rwpi>0</Rwpi>
+            <noStLib>0</noStLib>
+            <RepFail>1</RepFail>
+            <useFile>0</useFile>
+            <TextAddressRange>0x00000000</TextAddressRange>
+            <DataAddressRange>0x20000000</DataAddressRange>
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
+          </LDads>
+        </TargetArmAds>
+      </TargetOption>
+    </Target>
+  </Targets>
+
+  <RTE>
+    <apis/>
+    <components/>
+    <files/>
+  </RTE>
+
+  <LayerInfo>
+    <Layers>
+      <Layer>
+        <LayName>&lt;Project Info&gt;</LayName>
+        <LayTarg>0</LayTarg>
+        <LayPrjMark>1</LayPrjMark>
+      </Layer>
+    </Layers>
+  </LayerInfo>
+
+</Project>