update jz47xx branch code.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@892 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/jz47xx/board.c

@@ -46,6 +46,7 @@ void rt_hw_board_init()
 	/* init hardware UART device */
 	rt_hw_uart_init();
 #endif
+
 #ifdef RT_USING_CONSOLE
 	/* set console device */
 	rt_console_set_device("uart");

bsp/jz47xx/board.h

@@ -17,6 +17,7 @@
 
 void rt_hw_board_init(void);
 
+/* 32M SDRAM */
 #define RT_HW_HEAP_END	(0x80000000 + 32 * 1024 * 1024)
 
 #endif

bsp/jz47xx/jz47xx_ram.lds

@@ -11,20 +11,33 @@
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-08-23     bernard      change to jz47xx
+ * 2010-09-04     bernard      move the beginning entry to 0x80100000
  */
 
 OUTPUT_FORMAT("elf32-tradlittlemips", "elf32-tradlittlemips", "elf32-tradlittlemips")
 OUTPUT_ARCH(mips)
 
-ENTRY(_entry)
+MEMORY
+{
+   /* 16M SDRAM */
+   DRAM : ORIGIN = 0x80100000, LENGTH = 0x01000000
+   /* 16K SRAM  */
+   IRAM : ORIGIN = 0x80000000, LENGTH = 0x00004000
+}
+
+ENTRY(_start)
 SECTIONS
 {
-	.start 0x80000000:
+	. = 0x80100000 ;
+
+	.start :
     {
         *(.start);
-    }
-    
-    .text ALIGN(0x4) : 
+    } > DRAM
+
+    . = ALIGN(4);
+
+	.text : 
     {
      *(.text)
      *(.text.*)
@@ -43,9 +56,11 @@ SECTIONS
      KEEP(*(VSymTab))
      __vsymtab_end = .;
      . = ALIGN(4);
-    }
-    
-	.data ALIGN(0x4) : 
+    } > DRAM
+
+    . = ALIGN(4);
+
+	.data : 
     {
      *(.data)
      *(.data.*)
@@ -58,25 +73,48 @@ SECTIONS
      
      *(.sdata)
      *(.sdata.*)
-    }
+    } > DRAM
+
+    . = ALIGN(4);
+	_iramat = .;
+
+	.iram : AT(_iramat)
+    {
+		_iramstart = .;
+        *(.vectors.1);
+        . = 0x100;
+        *(.vectors.2);
+        . = 0x180;
+        *(.vectors.3);
+        . = 0x200;
+        *(.vectors.4);
+        *(.vectors);
+
+        *(.icode);
+        *(.irodata);
+        *(.idata);
+        KEEP(*(.vectors*))
+		_iramend = .;
+    } > IRAM
+    _iramcopy = LOADADDR(.iram);
 
-	__bss_start = ABSOLUTE(.);
 	.sbss : 
   	{
+	__bss_start = .;
 		*(.sbss)
         *(.sbss.*)
         *(.dynsbss)
 		*(.scommon)
- 	}
- 	
+ 	} > DRAM
+
  	.bss :
  	{
 		*(.bss)
         *(.bss.*)
         *(.dynbss)
 		*(COMMON)
- 	}
-	__bss_end = ABSOLUTE(.);
+	__bss_end = .;
+ 	} > DRAM
 	
     _end = .;
 
@@ -113,4 +151,4 @@ SECTIONS
     .debug_funcnames 0 : { *(.debug_funcnames) }
     .debug_typenames 0 : { *(.debug_typenames) }
     .debug_varnames  0 : { *(.debug_varnames) }
-}
+}

bsp/jz47xx/rtconfig.h

@@ -3,13 +3,13 @@
 #define __RTTHREAD_CFG_H__
 
 /* RT_NAME_MAX*/
-#define RT_NAME_MAX	8
+#define RT_NAME_MAX	10
 
 /* RT_ALIGN_SIZE*/
 #define RT_ALIGN_SIZE	4
 
 /* PRIORITY_MAX */
-#define RT_THREAD_PRIORITY_MAX	32
+#define RT_THREAD_PRIORITY_MAX	256
 
 /* Tick per Second */
 #define RT_TICK_PER_SECOND	100
@@ -57,12 +57,13 @@
 /* SECTION: Device System */
 /* Using Device System */
 #define RT_USING_DEVICE
-/* RT_USING_UART */
-#define RT_USING_UART0
+#define RT_USING_UART
+#define RT_USING_UART1
 #define RT_UART_RX_BUFFER_SIZE	64
 
 /* SECTION: Console options */
 /* the buffer size of console */
+#define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE	128
 
 /* SECTION: finsh, a C-Express shell */

bsp/jz47xx/rtconfig.py

@@ -51,7 +51,7 @@ if rtconfig_ns.has_key('RT_USING_MODULE'):
 ARCH='mips'
 CPU='jz47xx'
 
-CROSS_TOOL      = 'gcc'
+CROSS_TOOL  = 'gcc'
 PLATFORM 	= 'gcc'
 EXEC_PATH 	= 'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin'
 BUILD		= 'debug'
@@ -82,4 +82,6 @@ else:
 	CFLAGS += ' -O2'
 
 RT_USING_MINILIBC = True
-POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+COPY_ACTION = 'copy rtthread.bin usbboot\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + DUMP_ACTION + COPY_ACTION

bsp/jz47xx/startup.c

@@ -25,17 +25,33 @@
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
 
-extern int  rt_application_init(void);
+extern int rt_application_init(void);
+
+void dump_memory(rt_uint8_t* ptr, rt_size_t size)
+{
+	rt_size_t index;
+
+	for (index = 0; index < size; index ++)
+	{
+		rt_kprintf("%02x ", ptr[index] & 0xff);
+		if ((index + 1) % 16 == 0) rt_kprintf("\n");
+	}
+}
 
 /**
  * This function will startup RT-Thread RTOS.
  */
 void rtthread_startup(void)
 {
+	/* init hardware interrupt */
+	rt_hw_interrupt_init();
+
 	/* init board */
 	rt_hw_board_init();
 	rt_show_version();
 
+	dump_memory((rt_uint8_t*)0x80000200, 32);
+
 	/* init tick */
 	rt_system_tick_init();
 

bsp/jz47xx/uart.c

@@ -1,5 +1,6 @@
 #include <rthw.h>
 #include <rtthread.h>
+#include <jz47xx.h>
 
 /**
  * @addtogroup Jz47xx
@@ -9,30 +10,29 @@
 #if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
 
 #define UART_BAUDRATE   115200
-#define DEV_CLK    12000000
-
+#define DEV_CLK         12000000
 
 /*
  * Define macros for UARTIER
  * UART Interrupt Enable Register
  */
-#define UARTIER_RIE	(1 << 0)	/* 0: receive fifo "full" interrupt disable */
-#define UARTIER_TIE	(1 << 1)	/* 0: transmit fifo "empty" interrupt disable */
+#define UARTIER_RIE	    (1 << 0)	/* 0: receive fifo "full" interrupt disable */
+#define UARTIER_TIE	    (1 << 1)	/* 0: transmit fifo "empty" interrupt disable */
 #define UARTIER_RLIE	(1 << 2)	/* 0: receive line status interrupt disable */
-#define UARTIER_MIE	(1 << 3)	/* 0: modem status interrupt disable */
+#define UARTIER_MIE	    (1 << 3)	/* 0: modem status interrupt disable */
 #define UARTIER_RTIE	(1 << 4)	/* 0: receive timeout interrupt disable */
 
 /*
  * Define macros for UARTISR
  * UART Interrupt Status Register
  */
-#define UARTISR_IP	(1 << 0)	/* 0: interrupt is pending  1: no interrupt */
-#define UARTISR_IID	(7 << 1)	/* Source of Interrupt */
+#define UARTISR_IP	        (1 << 0)	/* 0: interrupt is pending  1: no interrupt */
+#define UARTISR_IID	        (7 << 1)	/* Source of Interrupt */
 #define UARTISR_IID_MSI		(0 << 1)	/* Modem status interrupt */
 #define UARTISR_IID_THRI	(1 << 1)	/* Transmitter holding register empty */
 #define UARTISR_IID_RDI		(2 << 1)	/* Receiver data interrupt */
 #define UARTISR_IID_RLSI	(3 << 1)	/* Receiver line status interrupt */
-#define UARTISR_FFMS	(3 << 6)	/* FIFO mode select, set when UARTFCR.FE is set to 1 */
+#define UARTISR_FFMS	    (3 << 6)	/* FIFO mode select, set when UARTFCR.FE is set to 1 */
 #define UARTISR_FFMS_NO_FIFO	(0 << 6)
 #define UARTISR_FFMS_FIFO_MODE	(3 << 6)
 
@@ -40,11 +40,11 @@
  * Define macros for UARTFCR
  * UART FIFO Control Register
  */
-#define UARTFCR_FE	(1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
+#define UARTFCR_FE	    (1 << 0)	/* 0: non-FIFO mode  1: FIFO mode */
 #define UARTFCR_RFLS	(1 << 1)	/* write 1 to flush receive FIFO */
 #define UARTFCR_TFLS	(1 << 2)	/* write 1 to flush transmit FIFO */
-#define UARTFCR_DMS	(1 << 3)	/* 0: disable DMA mode */
-#define UARTFCR_UUE	(1 << 4)	/* 0: disable UART */
+#define UARTFCR_DMS	    (1 << 3)	/* 0: disable DMA mode */
+#define UARTFCR_UUE	    (1 << 4)	/* 0: disable UART */
 #define UARTFCR_RTRG	(3 << 6)	/* Receive FIFO Data Trigger */
 #define UARTFCR_RTRG_1	(0 << 6)
 #define UARTFCR_RTRG_4	(1 << 6)
@@ -62,7 +62,7 @@
 #define UARTLCR_WLEN_8	(3 << 0)
 #define UARTLCR_STOP	(1 << 2)	/* 0: 1 stop bit when word length is 5,6,7,8
 					   1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */
-#define UARTLCR_PE	(1 << 3)	/* 0: parity disable */
+#define UARTLCR_PE	    (1 << 3)	/* 0: parity disable */
 #define UARTLCR_PROE	(1 << 4)	/* 0: even parity  1: odd parity */
 #define UARTLCR_SPAR	(1 << 5)	/* 0: sticky parity disable */
 #define UARTLCR_SBRK	(1 << 6)	/* write 0 normal, write 1 send break */
@@ -72,11 +72,11 @@
  * Define macros for UARTLSR
  * UART Line Status Register
  */
-#define UARTLSR_DR	(1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */
+#define UARTLSR_DR	    (1 << 0)	/* 0: receive FIFO is empty  1: receive data is ready */
 #define UARTLSR_ORER	(1 << 1)	/* 0: no overrun error */
-#define UARTLSR_PER	(1 << 2)	/* 0: no parity error */
-#define UARTLSR_FER	(1 << 3)	/* 0; no framing error */
-#define UARTLSR_BRK	(1 << 4)	/* 0: no break detected  1: receive a break signal */
+#define UARTLSR_PER	    (1 << 2)	/* 0: no parity error */
+#define UARTLSR_FER	    (1 << 3)	/* 0; no framing error */
+#define UARTLSR_BRK	    (1 << 4)	/* 0: no break detected  1: receive a break signal */
 #define UARTLSR_TDRQ	(1 << 5)	/* 1: transmit FIFO half "empty" */
 #define UARTLSR_TEMT	(1 << 6)	/* 1: transmit FIFO and shift registers empty */
 #define UARTLSR_RFER	(1 << 7)	/* 0: no receive error  1: receive error in FIFO mode */
@@ -85,12 +85,12 @@
  * Define macros for UARTMCR
  * UART Modem Control Register
  */
-#define UARTMCR_DTR	(1 << 0)	/* 0: DTR_ ouput high */
-#define UARTMCR_RTS	(1 << 1)	/* 0: RTS_ output high */
+#define UARTMCR_DTR	    (1 << 0)	/* 0: DTR_ ouput high */
+#define UARTMCR_RTS	    (1 << 1)	/* 0: RTS_ output high */
 #define UARTMCR_OUT1	(1 << 2)	/* 0: UARTMSR.RI is set to 0 and RI_ input high */
 #define UARTMCR_OUT2	(1 << 3)	/* 0: UARTMSR.DCD is set to 0 and DCD_ input high */
 #define UARTMCR_LOOP	(1 << 4)	/* 0: normal  1: loopback mode */
-#define UARTMCR_MCE	(1 << 7)	/* 0: modem function is disable */
+#define UARTMCR_MCE	    (1 << 7)	/* 0: modem function is disable */
 
 /*
  * Define macros for UARTMSR
@@ -98,12 +98,12 @@
  */
 #define UARTMSR_DCTS	(1 << 0)	/* 0: no change on CTS_ pin since last read of UARTMSR */
 #define UARTMSR_DDSR	(1 << 1)	/* 0: no change on DSR_ pin since last read of UARTMSR */
-#define UARTMSR_DRI	(1 << 2)	/* 0: no change on RI_ pin since last read of UARTMSR */
+#define UARTMSR_DRI	    (1 << 2)	/* 0: no change on RI_ pin since last read of UARTMSR */
 #define UARTMSR_DDCD	(1 << 3)	/* 0: no change on DCD_ pin since last read of UARTMSR */
-#define UARTMSR_CTS	(1 << 4)	/* 0: CTS_ pin is high */
-#define UARTMSR_DSR	(1 << 5)	/* 0: DSR_ pin is high */
-#define UARTMSR_RI	(1 << 6)	/* 0: RI_ pin is high */
-#define UARTMSR_DCD	(1 << 7)	/* 0: DCD_ pin is high */
+#define UARTMSR_CTS	    (1 << 4)	/* 0: CTS_ pin is high */
+#define UARTMSR_DSR	    (1 << 5)	/* 0: DSR_ pin is high */
+#define UARTMSR_RI	    (1 << 6)	/* 0: RI_ pin is high */
+#define UARTMSR_DCD	    (1 << 7)	/* 0: DCD_ pin is high */
 
 /*
  * Define macros for SIRCR
@@ -209,8 +209,11 @@ static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 	{
 		/* Enable the UART Interrupt */
 		UART_IER(uart->hw_base) |= (UARTIER_RIE | UARTIER_RTIE);
-	}
 
+		/* install interrupt */
+		rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL);
+		rt_hw_interrupt_umask(uart->irq);
+	}
 	return RT_EOK;
 }
 
@@ -293,13 +296,13 @@ static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer
 			if (*ptr == '\n')
 			{
 				/* FIFO status, contain valid data */
-				while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
+				while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
 				/* write data */
 				UART_TDR(uart->hw_base) = '\r';
 			}
 
 			/* FIFO status, contain valid data */
-			while ( !(UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT) == 0x60) );
+			while (!((UART_LSR(uart->hw_base) & (UARTLSR_TDRQ | UARTLSR_TEMT)) == 0x60));
 			/* write data */
 			UART_TDR(uart->hw_base) = *ptr;
 
@@ -336,6 +339,19 @@ void rt_hw_uart_init(void)
 	uart->parent.type = RT_Device_Class_Char;
 	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
 	uart->read_index = uart->save_index = 0;
+#if defined(RT_USING_UART0)
+	uart->hw_base = UART0_BASE;
+	uart->irq = IRQ_UART0;
+#elif defined(RT_USING_UART1)
+	uart->hw_base = UART1_BASE;
+	uart->irq = IRQ_UART1;
+#elif defined(RT_USING_UART2)
+	uart->hw_base = UART2_BASE;
+	uart->irq = IRQ_UART2;
+#elif defined(RT_USING_UART3)
+	uart->hw_base = UART3_BASE;
+	uart->irq = IRQ_UART3;
+#endif
 
 	/* device interface */
 	uart->parent.init 	    = rt_uart_init;