[libcpu][riscv]移除ch32中的冗余文件,使用common下的文件 (#6813)

* [libcpu][riscv]移除ch32中的冗余文件,使用common下的文件

* 修正cpuport.h宏定义

* 规范宏定义格式

bsp/wch/risc-v/Libraries/Kconfig

@@ -14,7 +14,6 @@ config SOC_RISCV_SERIES_CH32V2
 config SOC_RISCV_SERIES_CH32V3
     bool
     select ARCH_RISCV
-    select ARCH_RISCV_FPU
     select SOC_RISCV_FAMILY_CH32
 
 config SOC_FAMILY_CH56X

bsp/wch/risc-v/Libraries/ch32v30x_libraries/bmsis/source/startup_ch32v30x.S

@@ -378,6 +378,10 @@ handle_reset:
  	la t0, _vector_base
     ori t0, t0, 3           
 	csrw mtvec, t0
+    
+    la t0, _eusrstack
+	addi t0, t0, -512
+    csrw mscratch,t0
 
     jal  SystemInit
 	la t0, entry

bsp/wch/risc-v/ch32v208w-r0/rtconfig.py

@@ -49,7 +49,7 @@ if PLATFORM == 'gcc':
     LFLAGS = DEVICE
     LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
     LFLAGS += ' -T ' + LINK_FILE
-
+    AFLAGS += ' -I.'
     CPATH = ''
     LPATH = ''
 

bsp/wch/risc-v/ch32v307v-r1/.config

@@ -65,14 +65,17 @@ CONFIG_RT_USING_HEAP=y
 #
 CONFIG_RT_USING_DEVICE=y
 # CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
 # CONFIG_RT_USING_INTERRUPT_INFO is not set
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40101
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 # CONFIG_RT_USING_CPU_FFS is not set
 CONFIG_ARCH_RISCV=y
-# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
 #
 # RT-Thread Components
@@ -104,6 +107,7 @@ CONFIG_FINSH_ARG_MAX=10
 # Device Drivers
 #
 CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
 CONFIG_RT_USING_SERIAL_V1=y
@@ -118,10 +122,14 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
 # CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
 # CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
 # CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
 # CONFIG_RT_USING_SPI is not set
@@ -129,10 +137,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
 # CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
 # CONFIG_RT_USING_HWCRYPTO is not set
 # CONFIG_RT_USING_PULSE_ENCODER is not set
 # CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
 # CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
 
 #
 # Using USB
@@ -277,6 +288,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_AGILE_FTP is not set
 # CONFIG_PKG_USING_EMBEDDEDPROTO is not set
 # CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
 # CONFIG_PKG_USING_LORA_PKT_FWD is not set
 # CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
 # CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
@@ -284,6 +296,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SMALL_MODBUS is not set
 # CONFIG_PKG_USING_NET_SERVER is not set
 # CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
 
 #
 # security packages
@@ -374,7 +387,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
-# CONFIG_PKG_USING_ULOG_FILE is not set
 # CONFIG_PKG_USING_LOGMGR is not set
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
@@ -408,8 +420,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CBOX is not set
 # CONFIG_PKG_USING_SNOWFLAKE is not set
 # CONFIG_PKG_USING_HASH_MATCH is not set
-# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
 
 #
 # system packages
@@ -445,7 +457,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_UC_CLK is not set
 # CONFIG_PKG_USING_UC_COMMON is not set
 # CONFIG_PKG_USING_UC_MODBUS is not set
-# CONFIG_PKG_USING_RTDUINO is not set
 # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
@@ -480,18 +491,91 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_KMULTI_RTIMER is not set
 # CONFIG_PKG_USING_TFDB is not set
 # CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
 
 #
 # peripheral libraries and drivers
 #
-# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
-# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_FINGERPRINT is not set
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
 # CONFIG_PKG_USING_SHT2X is not set
 # CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_AS7341 is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
-# CONFIG_PKG_USING_RTT_ESP_IDF is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_BUTTON is not set
 # CONFIG_PKG_USING_PCF8574 is not set
@@ -505,7 +589,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 
 #
-# kendryte-sdk: Kendryte SDK
+# Kendryte SDK
 #
 # CONFIG_PKG_USING_K210_SDK is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
@@ -515,12 +599,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
 # CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
-# CONFIG_PKG_USING_AD7746 is not set
 # CONFIG_PKG_USING_PCA9685 is not set
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
-# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
 # CONFIG_PKG_USING_AS608 is not set
 # CONFIG_PKG_USING_RC522 is not set
@@ -570,6 +651,8 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_CW2015 is not set
 # CONFIG_PKG_USING_RFM300 is not set
 # CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
 
 #
 # AI packages
@@ -584,6 +667,12 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_QUEST is not set
 # CONFIG_PKG_USING_NAXOS is not set
 
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
 #
 # miscellaneous packages
 #
@@ -635,7 +724,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_VI is not set
 # CONFIG_PKG_USING_KI is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
-# CONFIG_PKG_USING_UKAL is not set
 # CONFIG_PKG_USING_CRCLIB is not set
 # CONFIG_PKG_USING_LWGPS is not set
 # CONFIG_PKG_USING_STATE_MACHINE is not set
@@ -645,6 +733,213 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
 # CONFIG_PKG_USING_MFBD is not set
 # CONFIG_PKG_USING_SLCAN2RTT is not set
 # CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+
+#
+# Other
+#
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
 CONFIG_SOC_RISCV_FAMILY_CH32=y
 CONFIG_SOC_RISCV_SERIES_CH32V3=y
 
@@ -656,12 +951,31 @@ CONFIG_SOC_CH32V307VC=y
 #
 # On-chip Peripheral Drivers
 #
+CONFIG_BSP_USING_GPIO=y
 CONFIG_BSP_USING_UART=y
 CONFIG_BSP_USING_UART1=y
+# CONFIG_BSP_USING_UART2 is not set
+# CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_UART4 is not set
+# CONFIG_BSP_USING_UART5 is not set
+# CONFIG_BSP_USING_UART6 is not set
+# CONFIG_BSP_USING_UART7 is not set
+# CONFIG_BSP_USING_UART8 is not set
+# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_DAC is not set
+# CONFIG_BSP_USING_SOFT_I2C is not set
+# CONFIG_BSP_USING_SPI is not set
+# CONFIG_BSP_USING_SOFT_SPI is not set
+# CONFIG_BSP_USING_RTC is not set
+CONFIG_LSI_VALUE=40000
+# CONFIG_BSP_USING_IWDT is not set
+# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_TIM is not set
 
 #
 # Onboard Peripheral Drivers
 #
+# CONFIG_BSP_USING_ARDUINO is not set
 
 #
 # Board extended module Drivers

bsp/wch/risc-v/ch32v307v-r1/rtconfig.h

@@ -43,7 +43,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40101
+#define RT_VER_NUM 0x50000
 #define ARCH_RISCV
 
 /* RT-Thread Components */
@@ -69,6 +69,7 @@
 /* Device Drivers */
 
 #define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
 #define RT_USING_SERIAL
 #define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
@@ -156,13 +157,21 @@
 
 /* peripheral libraries and drivers */
 
+/* sensors drivers */
 
-/* kendryte-sdk: Kendryte SDK */
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
 
 
 /* AI packages */
 
 
+/* Signal Processing and Control Algorithm Packages */
+
+
 /* miscellaneous packages */
 
 /* project laboratory */
@@ -172,6 +181,40 @@
 
 /* entertainment: terminal games and other interesting software packages */
 
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
 #define SOC_RISCV_FAMILY_CH32
 #define SOC_RISCV_SERIES_CH32V3
 
@@ -181,11 +224,14 @@
 
 /* On-chip Peripheral Drivers */
 
+#define BSP_USING_GPIO
 #define BSP_USING_UART
 #define BSP_USING_UART1
+#define LSI_VALUE 40000
 
 /* Onboard Peripheral Drivers */
 
+
 /* Board extended module Drivers */
 
 

bsp/wch/risc-v/ch32v307v-r1/rtconfig.py

@@ -47,7 +47,7 @@ if PLATFORM == 'gcc':
     LFLAGS = DEVICE
     LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE
     LFLAGS += ' -T ' + LINK_FILE
-
+    AFLAGS += ' -I.'
     CPATH = ''
     LPATH = ''
 

libcpu/risc-v/SConscript

@@ -18,8 +18,6 @@ elif rtconfig.CPU == "virt64" :
     group = group
 elif rtconfig.CPU == "c906" :
     group = group
-elif rtconfig.CPU == "ch32" :
-    group = group
 elif rtconfig.CPU == "hpmicro":
     group = group
 else :

libcpu/risc-v/ch32/SConscript

@@ -7,10 +7,11 @@ Import('rtconfig')
 cwd     = GetCurrentDir()
 src     = Glob('*.c') + Glob('*.cpp')
 CPPPATH = [cwd]
+ASFLAGS = ' -I ' + cwd 
 
 if rtconfig.PLATFORM == 'gcc':
     src += Glob('*_gcc.S')
 
-group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
 
 Return('group')

libcpu/risc-v/ch32/context_gcc.S

@@ -1,219 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- * 2022-12-27     WangShun   Merge WCH series mcu port files
- */
-
-#include "cpuport.h"
-
-/*
- * #ifdef RT_USING_SMP
- * void rt_hw_context_switch_to(rt_ubase_t to, stuct rt_thread *to_thread);
- * #else
- * void rt_hw_context_switch_to(rt_ubase_t to);
- * #endif
- * a0 --> to
- * a1 --> to_thread
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    /* first save interrupt stack */
-	la t0, _eusrstack
-	addi t0, t0, -512
-    csrw mscratch,t0
-
-    LOAD sp, (a0)
-    LOAD a0,   2 * REGBYTES(sp)
-    csrw mstatus, a0
-    j    rt_hw_context_switch_exit
-
-
-
-/*
- * void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
- * a0 --> from
- * a1 --> to
- */
-	.globl rt_hw_context_switch
-rt_hw_context_switch:
-	/* switch in thread */
-#ifdef ARCH_RISCV_FPU
-	addi sp, sp, -32*FREGBYTES
-
-    FSTORE  f0, 0 * FREGBYTES(sp)
-    FSTORE  f1, 1 * FREGBYTES(sp)
-    FSTORE  f2, 2 * FREGBYTES(sp)
-    FSTORE  f3, 3 * FREGBYTES(sp)
-    FSTORE  f4, 4 * FREGBYTES(sp)
-    FSTORE  f5, 5 * FREGBYTES(sp)
-    FSTORE  f6, 6 * FREGBYTES(sp)
-    FSTORE  f7, 7 * FREGBYTES(sp)
-    FSTORE  f8, 8 * FREGBYTES(sp)
-    FSTORE  f9, 9 * FREGBYTES(sp)
-    FSTORE  f10, 10 * FREGBYTES(sp)
-    FSTORE  f11, 11 * FREGBYTES(sp)
-    FSTORE  f12, 12 * FREGBYTES(sp)
-    FSTORE  f13, 13 * FREGBYTES(sp)
-    FSTORE  f14, 14 * FREGBYTES(sp)
-    FSTORE  f15, 15 * FREGBYTES(sp)
-    FSTORE  f16, 16 * FREGBYTES(sp)
-    FSTORE  f17, 17 * FREGBYTES(sp)
-    FSTORE  f18, 18 * FREGBYTES(sp)
-    FSTORE  f19, 19 * FREGBYTES(sp)
-    FSTORE  f20, 20 * FREGBYTES(sp)
-    FSTORE  f21, 21 * FREGBYTES(sp)
-    FSTORE  f22, 22 * FREGBYTES(sp)
-    FSTORE  f23, 23 * FREGBYTES(sp)
-    FSTORE  f24, 24 * FREGBYTES(sp)
-    FSTORE  f25, 25 * FREGBYTES(sp)
-    FSTORE  f26, 26 * FREGBYTES(sp)
-    FSTORE  f27, 27 * FREGBYTES(sp)
-    FSTORE  f28, 28 * FREGBYTES(sp)
-    FSTORE  f29, 29 * FREGBYTES(sp)
-    FSTORE  f30, 30 * FREGBYTES(sp)
-    FSTORE  f31, 31 * FREGBYTES(sp)
-#endif
-
-	addi sp, sp, -32 * REGBYTES
-	/* save from sp */
-	STORE sp,   0(a0)
-	/* save ra to epc */
-	STORE x1,   0 * REGBYTES(sp)
-	STORE x1,   1 * REGBYTES(sp)
-	STORE x5,   5 * REGBYTES(sp)
-
-	csrr  t0,  mstatus
-	andi  t0, t0, 8
-	/* if MIE be enabled,set MPIE */
-	beqz  t0, 1f
-	li    t0, 0x80
-
-1:  STORE t0,   2 * REGBYTES(sp)
-	STORE x4,   4 * REGBYTES(sp)
-
-	STORE x6,   6 * REGBYTES(sp)
-    STORE x7,   7 * REGBYTES(sp)
-    STORE x8,   8 * REGBYTES(sp)
-    STORE x9,   9 * REGBYTES(sp)
-    STORE x10, 10 * REGBYTES(sp)
-    STORE x11, 11 * REGBYTES(sp)
-    STORE x12, 12 * REGBYTES(sp)
-    STORE x13, 13 * REGBYTES(sp)
-    STORE x14, 14 * REGBYTES(sp)
-    STORE x15, 15 * REGBYTES(sp)
-    STORE x16, 16 * REGBYTES(sp)
-    STORE x17, 17 * REGBYTES(sp)
-    STORE x18, 18 * REGBYTES(sp)
-    STORE x19, 19 * REGBYTES(sp)
-    STORE x20, 20 * REGBYTES(sp)
-    STORE x21, 21 * REGBYTES(sp)
-    STORE x22, 22 * REGBYTES(sp)
-    STORE x23, 23 * REGBYTES(sp)
-    STORE x24, 24 * REGBYTES(sp)
-    STORE x25, 25 * REGBYTES(sp)
-    STORE x26, 26 * REGBYTES(sp)
-    STORE x27, 27 * REGBYTES(sp)
-    STORE x28, 28 * REGBYTES(sp)
-    STORE x29, 29 * REGBYTES(sp)
-    STORE x30, 30 * REGBYTES(sp)
-    STORE x31, 31 * REGBYTES(sp)
-
-	/* get "to" thread sp */
-	LOAD  sp,  0(a1)
-	j  rt_hw_context_switch_exit
-
-
-
-.global rt_hw_context_switch_exit
-rt_hw_context_switch_exit:
-    /* resw ra to mepc */
-    LOAD a0,   0 * REGBYTES(sp)
-    csrw mepc, a0
-
-    LOAD x1,   1 * REGBYTES(sp)
-
-	/* keep machine mode */
-	#if defined (SOC_RISCV_SERIES_CH32V3)
-	li    a0,      0x7800
-	#else
-	li    a0,      0x1800
-	#endif
-	csrs  mstatus, a0
-	/* resume MPIE */
-	LOAD  a0,      2*REGBYTES(sp)
-    csrs  mstatus, a0
-
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
-    addi sp,  sp, 32 * REGBYTES
-
- /* load float reg */
-#ifdef ARCH_RISCV_FPU
-
-    FLOAD   f0, 0 * FREGBYTES(sp)
-    FLOAD   f1, 1 * FREGBYTES(sp)
-    FLOAD   f2, 2 * FREGBYTES(sp)
-    FLOAD   f3, 3 * FREGBYTES(sp)
-    FLOAD   f4, 4 * FREGBYTES(sp)
-    FLOAD   f5, 5 * FREGBYTES(sp)
-    FLOAD   f6, 6 * FREGBYTES(sp)
-    FLOAD   f7, 7 * FREGBYTES(sp)
-    FLOAD   f8, 8 * FREGBYTES(sp)
-    FLOAD   f9, 9 * FREGBYTES(sp)
-    FLOAD   f10, 10 * FREGBYTES(sp)
-    FLOAD   f11, 11 * FREGBYTES(sp)
-    FLOAD   f12, 12 * FREGBYTES(sp)
-    FLOAD   f13, 13 * FREGBYTES(sp)
-    FLOAD   f14, 14 * FREGBYTES(sp)
-    FLOAD   f15, 15 * FREGBYTES(sp)
-    FLOAD   f16, 16 * FREGBYTES(sp)
-    FLOAD   f17, 17 * FREGBYTES(sp)
-    FLOAD   f18, 18 * FREGBYTES(sp)
-    FLOAD   f19, 19 * FREGBYTES(sp)
-    FLOAD   f20, 20 * FREGBYTES(sp)
-    FLOAD   f21, 21 * FREGBYTES(sp)
-    FLOAD   f22, 22 * FREGBYTES(sp)
-    FLOAD   f23, 23 * FREGBYTES(sp)
-    FLOAD   f24, 24 * FREGBYTES(sp)
-    FLOAD   f25, 25 * FREGBYTES(sp)
-    FLOAD   f26, 26 * FREGBYTES(sp)
-    FLOAD   f27, 27 * FREGBYTES(sp)
-    FLOAD   f28, 28 * FREGBYTES(sp)
-    FLOAD   f29, 29 * FREGBYTES(sp)
-    FLOAD   f30, 30 * FREGBYTES(sp)
-    FLOAD   f31, 31 * FREGBYTES(sp)
-    addi    sp, sp, 32 * FREGBYTES
-#endif
-
-    mret

libcpu/risc-v/ch32/cpuport.c

@@ -1,225 +0,0 @@
-/*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- * 2022-12-27     WangShun   Merge WCH series mcu port files
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-#if defined (SOC_RISCV_SERIES_CH32V1)
-#include "ch32v10x.h"
-#elif defined (SOC_RISCV_SERIES_CH32V2)
-#include "ch32v20x.h"
-#elif defined (SOC_RISCV_SERIES_CH32V3)
-#include "ch32v30x.h"
-#else
-#error "CH32 architecture doesn't support!"
-#endif
-
-#include "cpuport.h"
-
-#ifndef RT_USING_SMP
-volatile rt_ubase_t  rt_interrupt_from_thread = 0;
-volatile rt_ubase_t  rt_interrupt_to_thread   = 0;
-volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
-#endif
-
-struct rt_hw_stack_frame
-{
-    rt_ubase_t epc;        /* epc - epc    - program counter                     */
-    rt_ubase_t ra;         /* x1  - ra     - return address for jumps            */
-    rt_ubase_t mstatus;    /*              - machine status register             */
-    rt_ubase_t gp;         /* x3  - gp     - global pointer                      */
-    rt_ubase_t tp;         /* x4  - tp     - thread pointer                      */
-    rt_ubase_t t0;         /* x5  - t0     - temporary register 0                */
-    rt_ubase_t t1;         /* x6  - t1     - temporary register 1                */
-    rt_ubase_t t2;         /* x7  - t2     - temporary register 2                */
-    rt_ubase_t s0_fp;      /* x8  - s0/fp  - saved register 0 or frame pointer   */
-    rt_ubase_t s1;         /* x9  - s1     - saved register 1                    */
-    rt_ubase_t a0;         /* x10 - a0     - return value or function argument 0 */
-    rt_ubase_t a1;         /* x11 - a1     - return value or function argument 1 */
-    rt_ubase_t a2;         /* x12 - a2     - function argument 2                 */
-    rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
-    rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
-    rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
-    rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
-    rt_ubase_t a7;         /* x17 - s7     - function argument 7                 */
-    rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
-    rt_ubase_t s3;         /* x19 - s3     - saved register 3                    */
-    rt_ubase_t s4;         /* x20 - s4     - saved register 4                    */
-    rt_ubase_t s5;         /* x21 - s5     - saved register 5                    */
-    rt_ubase_t s6;         /* x22 - s6     - saved register 6                    */
-    rt_ubase_t s7;         /* x23 - s7     - saved register 7                    */
-    rt_ubase_t s8;         /* x24 - s8     - saved register 8                    */
-    rt_ubase_t s9;         /* x25 - s9     - saved register 9                    */
-    rt_ubase_t s10;        /* x26 - s10    - saved register 10                   */
-    rt_ubase_t s11;        /* x27 - s11    - saved register 11                   */
-    rt_ubase_t t3;         /* x28 - t3     - temporary register 3                */
-    rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
-    rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
-    rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
-
-/* float register */
-#ifdef ARCH_RISCV_FPU
-    rv_floatreg_t f0;      /* f0  */
-    rv_floatreg_t f1;      /* f1  */
-    rv_floatreg_t f2;      /* f2  */
-    rv_floatreg_t f3;      /* f3  */
-    rv_floatreg_t f4;      /* f4  */
-    rv_floatreg_t f5;      /* f5  */
-    rv_floatreg_t f6;      /* f6  */
-    rv_floatreg_t f7;      /* f7  */
-    rv_floatreg_t f8;      /* f8  */
-    rv_floatreg_t f9;      /* f9  */
-    rv_floatreg_t f10;     /* f10 */
-    rv_floatreg_t f11;     /* f11 */
-    rv_floatreg_t f12;     /* f12 */
-    rv_floatreg_t f13;     /* f13 */
-    rv_floatreg_t f14;     /* f14 */
-    rv_floatreg_t f15;     /* f15 */
-    rv_floatreg_t f16;     /* f16 */
-    rv_floatreg_t f17;     /* f17 */
-    rv_floatreg_t f18;     /* f18 */
-    rv_floatreg_t f19;     /* f19 */
-    rv_floatreg_t f20;     /* f20 */
-    rv_floatreg_t f21;     /* f21 */
-    rv_floatreg_t f22;     /* f22 */
-    rv_floatreg_t f23;     /* f23 */
-    rv_floatreg_t f24;     /* f24 */
-    rv_floatreg_t f25;     /* f25 */
-    rv_floatreg_t f26;     /* f26 */
-    rv_floatreg_t f27;     /* f27 */
-    rv_floatreg_t f28;     /* f28 */
-    rv_floatreg_t f29;     /* f29 */
-    rv_floatreg_t f30;     /* f30 */
-    rv_floatreg_t f31;     /* f31 */
-#endif
-};
-
-/*
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void       *tentry,
-                             void       *parameter,
-                             rt_uint8_t *stack_addr,
-                             void       *texit)
-{
-    struct rt_hw_stack_frame *frame;
-    rt_uint8_t         *stk;
-    int                i;
-
-    stk  = stack_addr + sizeof(rt_ubase_t);
-    stk  = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
-    stk -= sizeof(struct rt_hw_stack_frame);
-
-    frame = (struct rt_hw_stack_frame *)stk;
-
-    for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
-    {
-        ((rt_ubase_t *)frame)[i] = 0xdeadbeef;
-    }
-
-    frame->ra      = (rt_ubase_t)texit;
-    frame->a0      = (rt_ubase_t)parameter;
-    frame->epc     = (rt_ubase_t)tentry;
-    #if defined (SOC_RISCV_SERIES_CH32V3)
-    /* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
-    frame->mstatus = 0x00007880;
-    #else
-    /* force to machine mode(MPP=11) and set MPIE to 1 */
-    frame->mstatus = 0x00001880;
-    #endif
-    return stk;
-}
-
-/*
- * trigger soft interrupt
- */
-void sw_setpend(void)
-{
-    /*CH32V103 does not support systick software interrupt*/
-    #if defined (SOC_RISCV_SERIES_CH32V1)
-    NVIC_SetPendingIRQ(Software_IRQn);
-    #else
-    SysTick->CTLR |= (1<<31);
-    #endif
-}
-
-/*
- * clear soft interrupt
- */
-void sw_clearpend(void)
-{
-    /*CH32V103 does not support systick software interrupt*/
-    #if defined (SOC_RISCV_SERIES_CH32V1)
-    NVIC_ClearPendingIRQ(Software_IRQn);
-    #else
-    SysTick->CTLR &= ~(1<<31);
-    #endif
-}
-
-/*
- * disable interrupt and save mstatus
- */
-rt_base_t rt_hw_interrupt_disable(void)
-{
-    rt_base_t value=0;
-    #if defined (SOC_RISCV_SERIES_CH32V3)
-    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800));
-    #else
-    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
-    #endif
-    return value;
-}
-
-/*
- * enable interrupt and resume mstatus
- */
-void rt_hw_interrupt_enable(rt_base_t level)
-{
-    asm("csrw mstatus, %0": :"r"(level));
-}
-
-
-/*
- * #ifdef RT_USING_SMP
- * void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
- * #else
- * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
- * #endif
- */
-void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread)
-{
-    if (rt_thread_switch_interrupt_flag == 0)
-        rt_interrupt_from_thread = from;
-
-    rt_interrupt_to_thread = to;
-    rt_thread_switch_interrupt_flag = 1;
-    /* switch just in sw_handler */
-    sw_setpend();
-}
-
-/* shutdown CPU */
-void rt_hw_cpu_shutdown(void)
-{
-    rt_uint32_t level;
-    rt_kprintf("shutdown...\n");
-
-    level = rt_hw_interrupt_disable();
-    while (level)
-    {
-        RT_ASSERT(0);
-    }
-}

libcpu/risc-v/ch32/cpuport.h

@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2006-2022, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-09-09     WCH        the first version
- */
-
-#ifndef CPUPORT_H__
-#define CPUPORT_H__
-
-/* bytes of register width  */
-//#define ARCH_RISCV_FPU
-#define ARCH_RISCV_FPU_S
-
-#ifdef ARCH_CPU_64BIT
-#define STORE                   sd
-#define LOAD                    ld
-#define REGBYTES                8
-#else
-#define STORE                   sw
-#define LOAD                    lw
-#define REGBYTES                4
-#endif
-
-/* FPU */
-#ifdef ARCH_RISCV_FPU
-#ifdef ARCH_RISCV_FPU_D
-#define FSTORE                  fsd
-#define FLOAD                   fld
-#define FREGBYTES               8
-#define rv_floatreg_t           rt_int64_t
-#endif
-#ifdef ARCH_RISCV_FPU_S
-#define FSTORE                  fsw
-#define FLOAD                   flw
-#define FREGBYTES               4
-#define rv_floatreg_t           rt_int32_t
-#endif
-#endif
-
-#endif

libcpu/risc-v/ch32/interrupt.h

@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2021-09-09     WCH        the first version
+ * 2023-01-04     WangShun   Remove redundant files
+ */
+#if defined (SOC_RISCV_SERIES_CH32V1)
+#include "ch32v10x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V2)
+#include "ch32v20x.h"
+#elif defined (SOC_RISCV_SERIES_CH32V3)
+#include "ch32v30x.h"
+#else
+#error "CH32 architecture doesn't support!"
+#endif
+
+/*
+ * trigger soft interrupt
+ */
+void sw_setpend(void)
+{
+    /*CH32V103 does not support systick software interrupt*/
+#if defined(SOC_RISCV_SERIES_CH32V1)
+    NVIC_SetPendingIRQ(Software_IRQn);
+#else
+    SysTick->CTLR |= (1 << 31);
+#endif
+}
+
+/*
+ * clear soft interrupt
+ */
+void sw_clearpend(void)
+{
+    /*CH32V103 does not support systick software interrupt*/
+#if defined(SOC_RISCV_SERIES_CH32V1)
+    NVIC_ClearPendingIRQ(Software_IRQn);
+#else
+    SysTick->CTLR &= ~(1 << 31);
+#endif
+}
+
+/*
+ * disable interrupt and save mstatus
+ */
+rt_weak rt_base_t rt_hw_interrupt_disable(void)
+{
+    rt_base_t value=0;
+#if defined(SOC_RISCV_SERIES_CH32V3)
+    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x7800));
+#else
+    asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
+#endif
+    return value;
+}
+
+/*
+ * enable interrupt and resume mstatus
+ */
+rt_weak void rt_hw_interrupt_enable(rt_base_t level)
+{
+    asm("csrw mstatus, %0": :"r"(level));
+}
+
+

libcpu/risc-v/ch32/interrupt_gcc.S

@@ -9,6 +9,7 @@
  * 2022-12-27     WangShun   Merge WCH series mcu port files
  */
  
+#define __ASSEMBLY__
 #include "cpuport.h"
 
 .global SW_handler
@@ -59,10 +60,10 @@ SW_handler:
     STORE t0,   2 * REGBYTES(sp)
 
 	/* Temporarily disable HPE  */
-	#if defined (SOC_RISCV_SERIES_CH32V3)
+#if defined (SOC_RISCV_SERIES_CH32V3)
 	li   t0,    0x20
 	csrs 0x804, t0
-	#endif
+#endif
 
     STORE x1,   1 * REGBYTES(sp)
     STORE x4,   4 * REGBYTES(sp)
@@ -123,13 +124,13 @@ SW_handler:
     csrw  mepc, a0
 
 1:  LOAD  x1,   1 * REGBYTES(sp)
-	#if defined (SOC_RISCV_SERIES_CH32V3)
+#if defined (SOC_RISCV_SERIES_CH32V3)
 	li t0,0x7800
 	csrs mstatus, t0
-	#else
+#else
 	li t0,0x1800
 	csrs mstatus, t0	
-	#endif
+#endif
 	LOAD t0, 2*REGBYTES(sp)
 	csrs mstatus, t0
 

libcpu/risc-v/common/context_gcc.S

@@ -213,11 +213,11 @@ rt_hw_context_switch_exit:
     csrw mepc, a0
 
     LOAD x1,   1 * REGBYTES(sp)
-    #ifdef ARCH_RISCV_FPU
+#ifdef ARCH_RISCV_FPU
     li    t0, 0x00007800
-    #else
+#else
     li    t0, 0x00001800
-    #endif
+#endif
     csrw  mstatus, t0
     LOAD a0,   2 * REGBYTES(sp)
     csrs mstatus, a0

libcpu/risc-v/common/cpuport.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,6 +7,7 @@
  * Date           Author       Notes
  * 2018/10/28     Bernard      The unify RISC-V porting code.
  * 2020/11/20     BalanceTWK   Add FPU support
+ * 2023/01/04     WangShun     Adapt to CH32
  */
 
 #include <rthw.h>
@@ -125,7 +126,11 @@ rt_uint8_t *rt_hw_stack_init(void       *tentry,
     frame->epc     = (rt_ubase_t)tentry;
 
     /* force to machine mode(MPP=11) and set MPIE to 1 */
+#ifdef ARCH_RISCV_FPU
     frame->mstatus = 0x00007880;
+#else
+    frame->mstatus = 0x00001880;
+#endif
 
     return stk;
 }
@@ -145,7 +150,9 @@ rt_weak void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_t
 
     rt_interrupt_to_thread = to;
     rt_thread_switch_interrupt_flag = 1;
-
+#if defined(SOC_RISCV_FAMILY_CH32)
+    sw_setpend();
+#endif
     return ;
 }
 #endif /* end of RT_USING_SMP */

libcpu/risc-v/common/cpuport.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2021, RT-Thread Development Team
+ * Copyright (c) 2006-2023, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,12 +7,18 @@
  * Date           Author       Notes
  * 2018-10-03     Bernard      The first version
  * 2020/11/20     BalanceTWK   Add FPU support
+ * 2023/01/04     WangShun     Adapt to CH32
  */
 
 #ifndef CPUPORT_H__
 #define CPUPORT_H__
 
 #include <rtconfig.h>
+#if !defined(__ASSEMBLY__)
+#if defined(SOC_RISCV_FAMILY_CH32)
+#include "interrupt.h"
+#endif
+#endif
 
 #ifndef __ASSEMBLY__
 #ifdef RT_USING_SMP