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@@ -16,8 +16,12 @@
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#if !defined(BSP_USING_PWM1_CH0) && !defined(BSP_USING_PWM1_CH1) && !defined(BSP_USING_PWM1_CH2) && !defined(BSP_USING_PWM1_CH3) && \
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!defined(BSP_USING_PWM2_CH0) && !defined(BSP_USING_PWM2_CH1) && !defined(BSP_USING_PWM2_CH2) && !defined(BSP_USING_PWM2_CH3) && \
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!defined(BSP_USING_PWM3_CH0) && !defined(BSP_USING_PWM3_CH1) && !defined(BSP_USING_PWM3_CH2) && !defined(BSP_USING_PWM3_CH3) && \
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- !defined(BSP_USING_PWM4_CH0) && !defined(BSP_USING_PWM4_CH1) && !defined(BSP_USING_PWM4_CH2) && !defined(BSP_USING_PWM4_CH3)
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-#error "Please define at least one BSP_USING_PWMx_CHx"
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+ !defined(BSP_USING_PWM4_CH0) && !defined(BSP_USING_PWM4_CH1) && !defined(BSP_USING_PWM4_CH2) && !defined(BSP_USING_PWM4_CH3) && \
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+ !defined(BSP_USING_QTMR1_CH0) && !defined(BSP_USING_QTMR1_CH1) && !defined(BSP_USING_QTMR1_CH2) && !defined(BSP_USING_QTMR1_CH3) && \
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+ !defined(BSP_USING_QTMR2_CH0) && !defined(BSP_USING_QTMR2_CH1) && !defined(BSP_USING_QTMR2_CH2) && !defined(BSP_USING_QTMR2_CH3) && \
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+ !defined(BSP_USING_QTMR3_CH0) && !defined(BSP_USING_QTMR3_CH1) && !defined(BSP_USING_QTMR3_CH2) && !defined(BSP_USING_QTMR3_CH3) && \
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+ !defined(BSP_USING_QTMR4_CH0) && !defined(BSP_USING_QTMR4_CH1) && !defined(BSP_USING_QTMR4_CH2) && !defined(BSP_USING_QTMR4_CH3)
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+#error "Please define at least one BSP_USING_PWMx_CHx or BSP_USING_QTMRx_CHx"
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#endif
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#define LOG_TAG "drv.pwm"
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@@ -25,6 +29,9 @@
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#include <rtdevice.h>
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#include "fsl_pwm.h"
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+#if defined(FSL_FEATURE_SOC_TMR_COUNT) && FSL_FEATURE_SOC_TMR_COUNT > 0
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+ #include "fsl_qtmr.h"
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+#endif
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#include "drv_pwm.h"
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#define DEFAULT_PRE 5
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@@ -153,7 +160,7 @@ static rt_err_t imxrt_drv_pwm_init(PWM_Type *base, pwm_submodule_t pwm_submodule
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if (PWM_Init(base, pwm_submodule, &PwmConfig) == kStatus_Fail)
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{
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LOG_E("init pwm failed \n");
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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base->SM[fault_input].DISMAP[0] = 0x00;
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@@ -176,28 +183,28 @@ static rt_err_t imxrt_pwm1_init(PWM_Type *base)
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#ifdef BSP_USING_PWM1_CH0
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if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM1_CH0 */
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#ifdef BSP_USING_PWM1_CH1
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if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM1_CH1 */
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#ifdef BSP_USING_PWM1_CH2
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if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /*BSP_USING_PWM1_CH2 */
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#ifdef BSP_USING_PWM1_CH3
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if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM1_CH3 */
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@@ -213,28 +220,28 @@ static rt_err_t imxrt_pwm2_init(PWM_Type *base)
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#ifdef BSP_USING_PWM2_CH0
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if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM2_CH0 */
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#ifdef BSP_USING_PWM2_CH1
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if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM2_CH1 */
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#ifdef BSP_USING_PWM2_CH2
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if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /*BSP_USING_PWM2_CH2 */
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#ifdef BSP_USING_PWM2_CH3
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if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM2_CH3 */
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@@ -250,28 +257,28 @@ static rt_err_t imxrt_pwm3_init(PWM_Type *base)
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#ifdef BSP_USING_PWM3_CH0
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if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM3_CH0 */
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#ifdef BSP_USING_PWM3_CH1
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if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM3_CH1 */
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#ifdef BSP_USING_PWM3_CH2
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if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /*BSP_USING_PWM3_CH2 */
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#ifdef BSP_USING_PWM3_CH3
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if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM3_CH3 */
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@@ -287,28 +294,28 @@ static rt_err_t imxrt_pwm4_init(PWM_Type *base)
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#ifdef BSP_USING_PWM4_CH0
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if (imxrt_drv_pwm_init(base, kPWM_Module_0, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM4_CH0 */
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#ifdef BSP_USING_PWM4_CH1
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if (imxrt_drv_pwm_init(base, kPWM_Module_1, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM4_CH1 */
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#ifdef BSP_USING_PWM4_CH2
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if (imxrt_drv_pwm_init(base, kPWM_Module_2, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /*BSP_USING_PWM4_CH2 */
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#ifdef BSP_USING_PWM4_CH3
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if (imxrt_drv_pwm_init(base, kPWM_Module_3, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
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{
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- return RT_ERROR;
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+ return -RT_ERROR;
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}
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#endif /* BSP_USING_PWM4_CH3 */
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@@ -317,6 +324,224 @@ static rt_err_t imxrt_pwm4_init(PWM_Type *base)
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#endif /* BSP_USING_PWM4 */
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+static rt_err_t imxrt_drv_qtmr_control(struct rt_device_pwm *device, int cmd, void *arg);
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+
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+static struct rt_pwm_ops imxrt_drv_qtmr_ops =
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+{
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+ .control = imxrt_drv_qtmr_control
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+};
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+
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+static rt_err_t imxrt_drv_qtmr_enable(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration, rt_bool_t enable)
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+{
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+ TMR_Type *base;
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+ base = (TMR_Type *)device->parent.user_data;
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+
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+ if (!enable)
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+ {
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+ QTMR_StopTimer(base, configuration->channel);
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+ base->CHANNEL[configuration->channel].SCTRL |= (TMR_SCTRL_FORCE_MASK | TMR_SCTRL_OEN_MASK);
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+ }
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+ else
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+ {
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+ QTMR_StartTimer(base, configuration->channel, kQTMR_PriSrcRiseEdge);
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t imxrt_drv_qtmr_get(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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+{
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+ TMR_Type *base;
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+ rt_uint32_t high_count, low_count, clk_divider, clk_freq;
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+
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+ base = (TMR_Type *)device->parent.user_data;
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+
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+ low_count = base->CHANNEL[configuration->channel].COMP1;
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+ high_count = base->CHANNEL[configuration->channel].COMP2;
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+ clk_divider = 1 << (((base->CHANNEL[configuration->channel].CTRL & TMR_CTRL_PCS_MASK) >> TMR_CTRL_PCS_SHIFT) - 8);
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+ clk_freq = CLOCK_GetFreq(kCLOCK_IpgClk) / clk_divider;
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+
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+ configuration->period = 1000000000 / clk_freq * (high_count + low_count);
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+ configuration->pulse = 1000000000 / clk_freq * high_count;
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t imxrt_drv_qtmr_set(struct rt_device_pwm *device, struct rt_pwm_configuration *configuration)
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+{
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+ RT_ASSERT(configuration->period > 0);
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+ RT_ASSERT(configuration->pulse <= configuration->period);
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+
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+ TMR_Type *base = (TMR_Type *)device->parent.user_data;
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+
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+ rt_size_t clk_freq = CLOCK_GetFreq(kCLOCK_IpgClk) / (1 << (((base->CHANNEL[configuration->channel].CTRL & TMR_CTRL_PCS_MASK) >> TMR_CTRL_PCS_SHIFT) - 8));
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+ rt_size_t current_period_count = base->CHANNEL[configuration->channel].CMPLD1 + base->CHANNEL[configuration->channel].CMPLD2;
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+ rt_size_t period_count = clk_freq / (1000000000 / configuration->period);
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+ if (current_period_count == period_count)
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+ {
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+ rt_size_t high_count = period_count * configuration->pulse / configuration->period;
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+ rt_size_t low_count = period_count - high_count;
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+ base->CHANNEL[configuration->channel].CMPLD1 = (uint16_t)low_count;
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+ base->CHANNEL[configuration->channel].CMPLD2 = (uint16_t)high_count;
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+ }
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+ else
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+ {
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+ rt_bool_t timer_is_on = base->CHANNEL[configuration->channel].CTRL & TMR_CTRL_CM_MASK;
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+ rt_uint8_t duty = configuration->pulse * 100 / configuration->period;
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+ QTMR_StopTimer(base, configuration->channel);
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+ if (kStatus_Success != QTMR_SetupPwm(base, configuration->channel, 1000000000 / configuration->period, duty, DEFAULT_POLARITY, clk_freq))
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+ {
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+ LOG_E(LOG_TAG" setup pwm failed \n");
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+ return -RT_ERROR;
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+ }
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+ if (timer_is_on)
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+ {
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+ QTMR_StartTimer(base, configuration->channel, kQTMR_PriSrcRiseEdge);
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+ }
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t imxrt_drv_qtmr_control(struct rt_device_pwm *device, int cmd, void *arg)
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+{
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+ struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg;
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+
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+ switch (cmd)
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+ {
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+ case PWM_CMD_ENABLE:
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+ return imxrt_drv_qtmr_enable(device, configuration, RT_TRUE);
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+ case PWM_CMD_DISABLE:
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+ return imxrt_drv_qtmr_enable(device, configuration, RT_FALSE);
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+ case PWM_CMD_SET:
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+ return imxrt_drv_qtmr_set(device, configuration);
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+ case PWM_CMD_GET:
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+ return imxrt_drv_qtmr_get(device, configuration);
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+ default:
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+ return RT_EINVAL;
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+ }
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+}
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+
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+static rt_err_t imxrt_drv_qtmr_init(TMR_Type *base, qtmr_channel_selection_t channel, uint16_t psc, uint32_t fre, uint8_t duty)
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+{
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+ qtmr_config_t qtmr_config;
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+ rt_uint32_t qtmr_clock_freq;
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+ QTMR_GetDefaultConfig(&qtmr_config);
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+
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+ qtmr_config.primarySource = (qtmr_primary_count_source_t)(psc + 8);
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+ qtmr_clock_freq = CLOCK_GetFreq(kCLOCK_IpgClk) / (1 << psc);
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+
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+ QTMR_Init(base, channel, &qtmr_config);
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+
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+ if (kStatus_Success != QTMR_SetupPwm(base, channel, fre, duty, DEFAULT_POLARITY, qtmr_clock_freq))
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+ {
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+ LOG_E(LOG_TAG" setup pwm failed \n");
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+ return -RT_ERROR;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t imxrt_qtmr_init()
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+{
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+ TMR_Type *base_list[] =
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+ {
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+#ifdef BSP_USING_QTMR1
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+ TMR1,
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+#endif
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+#ifdef BSP_USING_QTMR2
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+ TMR2,
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+#endif
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+#ifdef BSP_USING_QTMR3
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+ TMR3,
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+#endif
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+#ifdef BSP_USING_QTMR4
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+ TMR4,
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+#endif
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+ };
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+
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+ rt_uint8_t channel_list[] =
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+ {
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+#ifdef BSP_USING_QTMR1
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+#ifdef BSP_USING_QTMR1_CH0
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+ 1 << 0 |
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+#endif
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+#ifdef BSP_USING_QTMR1_CH1
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+ 1 << 1 |
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+#endif
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+#ifdef BSP_USING_QTMR1_CH2
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+ 1 << 2 |
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+#endif
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+#ifdef BSP_USING_QTMR1_CH3
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+ 1 << 3 |
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+#endif
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+ 0,
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+#endif
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+#ifdef BSP_USING_QTMR2
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+#ifdef BSP_USING_QTMR2_CH0
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+ 1 << 0 |
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+#endif
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+#ifdef BSP_USING_QTMR2_CH1
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+ 1 << 1 |
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+#endif
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+#ifdef BSP_USING_QTMR2_CH2
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+ 1 << 2 |
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+#endif
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+#ifdef BSP_USING_QTMR2_CH3
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+ 1 << 3 |
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+#endif
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+ 0,
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+#endif
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+#ifdef BSP_USING_QTMR3
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+#ifdef BSP_USING_QTMR3_CH0
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+ 1 << 0 |
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+#endif
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+#ifdef BSP_USING_QTMR3_CH1
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+ 1 << 1 |
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+#endif
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+#ifdef BSP_USING_QTMR3_CH2
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+ 1 << 2 |
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+#endif
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+#ifdef BSP_USING_QTMR3_CH3
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+ 1 << 3 |
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+#endif
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+ 0,
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+#endif
|
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+#ifdef BSP_USING_QTMR4
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+#ifdef BSP_USING_QTMR4_CH0
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+ 1 << 0 |
|
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+#endif
|
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+#ifdef BSP_USING_QTMR4_CH1
|
|
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+ 1 << 1 |
|
|
|
+#endif
|
|
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+#ifdef BSP_USING_QTMR4_CH2
|
|
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+ 1 << 2 |
|
|
|
+#endif
|
|
|
+#ifdef BSP_USING_QTMR4_CH3
|
|
|
+ 1 << 3 |
|
|
|
+#endif
|
|
|
+ 0,
|
|
|
+#endif
|
|
|
+ };
|
|
|
+
|
|
|
+ for (rt_uint8_t i = 0; i < sizeof(base_list)/sizeof(TMR_Type *); ++i)
|
|
|
+ {
|
|
|
+ for (rt_uint8_t j = 0; j < 8; ++j)
|
|
|
+ {
|
|
|
+ if ((channel_list[i] >> j) & 1)
|
|
|
+ {
|
|
|
+ if (imxrt_drv_qtmr_init(base_list[i], j, DEFAULT_PRE, DEFAULT_FRE, DEFAULT_DUTY) != RT_EOK)
|
|
|
+ {
|
|
|
+ return -RT_ERROR;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+
|
|
|
+
|
|
|
int rt_hw_pwm_init(void)
|
|
|
{
|
|
|
rt_err_t ret = RT_EOK;
|
|
@@ -391,9 +616,52 @@ int rt_hw_pwm_init(void)
|
|
|
}
|
|
|
#endif /* BSP_USING_PWM4 */
|
|
|
|
|
|
+#if defined(BSP_USING_QTMR1) || defined(BSP_USING_QTMR2) || defined(BSP_USING_QTMR3) || defined(BSP_USING_QTMR4)
|
|
|
+ if (imxrt_qtmr_init() != RT_EOK)
|
|
|
+ {
|
|
|
+ LOG_E(LOG_TAG" init qtmr failed");
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+#ifdef BSP_USING_QTMR1
|
|
|
+ static struct rt_device_pwm qtmr1_device;
|
|
|
+ ret = rt_device_pwm_register(&qtmr1_device, "pwm5", &imxrt_drv_qtmr_ops, TMR1);
|
|
|
+ if (ret != RT_EOK)
|
|
|
+ {
|
|
|
+ LOG_E("%s register failed", "pwm5");
|
|
|
+ }
|
|
|
+#endif /* BSP_USING_QTMR1 */
|
|
|
+
|
|
|
+#ifdef BSP_USING_QTMR2
|
|
|
+ static struct rt_device_pwm qtmr2_device;
|
|
|
+ ret = rt_device_pwm_register(&qtmr2_device, "pwm6", &imxrt_drv_qtmr_ops, TMR2);
|
|
|
+ if (ret != RT_EOK)
|
|
|
+ {
|
|
|
+ LOG_E("%s register failed", "pwm6");
|
|
|
+ }
|
|
|
+#endif /* BSP_USING_QTMR2 */
|
|
|
+
|
|
|
+#ifdef BSP_USING_QTMR3
|
|
|
+ static struct rt_device_pwm qtmr3_device;
|
|
|
+ ret = rt_device_pwm_register(&qtmr3_device, "pwm7", &imxrt_drv_qtmr_ops, TMR3);
|
|
|
+ if (ret != RT_EOK)
|
|
|
+ {
|
|
|
+ LOG_E("%s register failed", "pwm7");
|
|
|
+ }
|
|
|
+#endif /* BSP_USING_QTMR3 */
|
|
|
+
|
|
|
+#ifdef BSP_USING_QTMR4
|
|
|
+ static struct rt_device_pwm qtmr4_device;
|
|
|
+ ret = rt_device_pwm_register(&qtmr4_device, "pwm8", &imxrt_drv_qtmr_ops, TMR4);
|
|
|
+ if (ret != RT_EOK)
|
|
|
+ {
|
|
|
+ LOG_E("%s register failed", "pwm8");
|
|
|
+ }
|
|
|
+#endif /* BSP_USING_QTMR4 */
|
|
|
+
|
|
|
return ret;
|
|
|
}
|
|
|
|
|
|
-INIT_DEVICE_EXPORT(rt_hw_pwm_init);
|
|
|
+INIT_BOARD_EXPORT(rt_hw_pwm_init);
|
|
|
|
|
|
#endif /* BSP_USING_PWM */
|