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@@ -0,0 +1,519 @@
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+/*
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+ * Copyright (c) 2013 Nuvoton Technology Corp.
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+ *
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+ * See file CREDITS for list of people who contributed to this
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+ * project.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of
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+ * the License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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+ * MA 02111-1307 USA
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+ *
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+ * Description: NUC472 MAC driver source file
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+ */
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+
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+#include <rtconfig.h>
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+
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+#ifdef RT_USING_LWIP
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+#include <rtthread.h>
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+#include "nuc472_eth.h"
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+#include <netif/ethernetif.h>
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+#include <netif/etharp.h>
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+#include <lwip/icmp.h>
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+#include "lwipopts.h"
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+
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+#define ETH_TRIGGER_RX() EMAC->RXST = 0
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+#define ETH_TRIGGER_TX() EMAC->TXST = 0
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+#define ETH_ENABLE_TX() EMAC->CTL |= EMAC_CTL_TXON
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+#define ETH_ENABLE_RX() EMAC->CTL |= EMAC_CTL_RXON
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+#define ETH_DISABLE_TX() EMAC->CTL &= ~EMAC_CTL_TXON
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+#define ETH_DISABLE_RX() EMAC->CTL &= ~EMAC_CTL_RXON
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+
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+rt_uint8_t ethaddr[] = {0x00, 0x00, 0x00, 0x59, 0x16, 0x88};
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+
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+struct rt_nuc472_emac
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+{
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+ struct eth_device parent;
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+
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+ EMAC_T *emac_base;
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+
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+ rt_uint8_t dev_addr[6];
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+ struct eth_descriptor volatile *cur_tx_desc_ptr, *cur_rx_desc_ptr, *fin_tx_desc_ptr;
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+
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+ struct eth_descriptor rx_desc[RX_DESCRIPTOR_NUM];
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+ struct eth_descriptor tx_desc[TX_DESCRIPTOR_NUM];
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+ rt_uint8_t rx_buf[RX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
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+ rt_uint8_t tx_buf[TX_DESCRIPTOR_NUM][PACKET_BUFFER_SIZE];
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+};
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+typedef struct rt_nuc472_emac* rt_nuc472_emac_t;
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+struct rt_nuc472_emac nuc472_emac_device;
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+
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+static void mdio_write(rt_nuc472_emac_t emac, rt_uint8_t addr, rt_uint8_t reg, rt_uint16_t val)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ emac_base->MIIMDAT = val;
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+ emac_base->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_WRITE_Msk | EMAC_MIIMCTL_MDCON_Msk;
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+
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+ while (emac_base->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
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+
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+}
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+
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+static rt_uint16_t mdio_read(rt_nuc472_emac_t emac, rt_uint8_t addr, rt_uint8_t reg)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ emac_base->MIIMCTL = (addr << EMAC_MIIMCTL_PHYADDR_Pos) | reg | EMAC_MIIMCTL_BUSY_Msk | EMAC_MIIMCTL_MDCON_Msk;
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+ while (emac_base->MIIMCTL & EMAC_MIIMCTL_BUSY_Msk);
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+
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+ return(emac_base->MIIMDAT);
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+}
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+
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+static int reset_phy(rt_nuc472_emac_t emac)
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+{
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+ rt_uint16_t reg;
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+ rt_uint32_t delay;
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ mdio_write(emac, CONFIG_PHY_ADDR, MII_BMCR, BMCR_RESET);
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+
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+ delay = 2000;
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+ while(delay-- > 0)
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+ {
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+ if((mdio_read(emac, CONFIG_PHY_ADDR, MII_BMCR) & BMCR_RESET) == 0)
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+ break;
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+ }
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+
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+ if(delay == 0)
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+ {
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+ rt_kprintf("Reset phy failed\n");
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+ return(-1);
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+ }
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+
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+ mdio_write(emac, CONFIG_PHY_ADDR, MII_ADVERTISE, ADVERTISE_CSMA |
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+ ADVERTISE_10HALF |
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+ ADVERTISE_10FULL |
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+ ADVERTISE_100HALF |
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+ ADVERTISE_100FULL);
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+
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+ reg = mdio_read(emac, CONFIG_PHY_ADDR, MII_BMCR);
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+ mdio_write(emac, CONFIG_PHY_ADDR, MII_BMCR, reg | BMCR_ANRESTART);
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+
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+ delay = 200000;
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+ while(delay-- > 0)
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+ {
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+ if((mdio_read(emac, CONFIG_PHY_ADDR, MII_BMSR) & (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
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+ == (BMSR_ANEGCOMPLETE | BMSR_LSTATUS))
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+ break;
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+ }
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+
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+ if(delay == 0)
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+ {
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+ rt_kprintf("AN failed. Set to 100 FULL\n");
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+ emac_base->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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+ return(-1);
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+ }
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+ else
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+ {
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+ reg = mdio_read(emac, CONFIG_PHY_ADDR, MII_LPA);
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+
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+ if(reg & ADVERTISE_100FULL)
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+ {
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+ rt_kprintf("100 full\n");
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+ emac_base->CTL |= (EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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+ }
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+ else if(reg & ADVERTISE_100HALF)
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+ {
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+ rt_kprintf("100 half\n");
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+ emac_base->CTL = (EMAC->CTL & ~EMAC_CTL_FUDUP_Msk) | EMAC_CTL_OPMODE_Msk;
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+ }
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+ else if(reg & ADVERTISE_10FULL)
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+ {
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+ rt_kprintf("10 full\n");
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+ emac_base->CTL = (EMAC->CTL & ~EMAC_CTL_OPMODE_Msk) | EMAC_CTL_FUDUP_Msk;
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+ } else
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+ {
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+ rt_kprintf("10 half\n");
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+ emac_base->CTL &= ~(EMAC_CTL_OPMODE_Msk | EMAC_CTL_FUDUP_Msk);
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+ }
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+ }
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+
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+ return(0);
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+}
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+
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+static void init_tx_desc(rt_nuc472_emac_t emac)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+ rt_uint32_t i;
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+
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+ emac->cur_tx_desc_ptr = emac->fin_tx_desc_ptr = &emac->tx_desc[0];
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+
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+ for(i = 0; i < TX_DESCRIPTOR_NUM; i++)
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+ {
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+ emac->tx_desc[i].status1 = TXFD_PADEN | TXFD_CRCAPP | TXFD_INTEN;
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+ emac->tx_desc[i].buf = &emac->tx_buf[i][0];
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+ emac->tx_desc[i].status2 = 0;
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+ emac->tx_desc[i].next = &emac->tx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
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+ }
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+ emac_base->TXDSA = (unsigned int)&emac->tx_desc[0];
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+ return;
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+}
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+
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+static void init_rx_desc(rt_nuc472_emac_t emac)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+ rt_uint32_t i;
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+
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+ emac->cur_rx_desc_ptr = &emac->rx_desc[0];
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+
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+ for(i = 0; i < RX_DESCRIPTOR_NUM; i++)
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+ {
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+ emac->rx_desc[i].status1 = OWNERSHIP_EMAC;
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+ emac->rx_desc[i].buf = &emac->rx_buf[i][0];
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+ emac->rx_desc[i].status2 = 0;
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+ emac->rx_desc[i].next = &emac->rx_desc[(i + 1) % TX_DESCRIPTOR_NUM];
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+ }
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+ emac_base->RXDSA = (unsigned int)&emac->rx_desc[0];
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+ return;
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+}
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+
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+static void set_mac_addr(rt_nuc472_emac_t emac, rt_uint8_t *addr)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ emac_base->CAM0M = (addr[0] << 24) |
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+ (addr[1] << 16) |
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+ (addr[2] << 8) |
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+ addr[3];
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+
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+ emac_base->CAM0L = (addr[4] << 24) |
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+ (addr[5] << 16);
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+
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+ emac_base->CAMCTL = EMAC_CAMCTL_CMPEN_Msk | EMAC_CAMCTL_AMP_Msk | EMAC_CAMCTL_ABP_Msk;
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+ emac_base->CAMEN = 1; // Enable CAM entry 0
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+}
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+
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+void EMAC_init(rt_nuc472_emac_t emac, rt_uint8_t *mac_addr)
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+{
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+ RT_ASSERT(emac->dev_addr != RT_NULL);
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ CLK_EnableModuleClock(EMAC_MODULE);
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+
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+ // Configure MDC clock rate to HCLK / (127 + 1) = 656 kHz if system is running at 84 MHz
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+ CLK_SetModuleClock(EMAC_MODULE, 0, CLK_CLKDIV3_EMAC(127));
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+
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+ // Configure RMII pins
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+ SYS->GPC_MFPL = SYS_GPC_MFPL_PC0MFP_EMAC_REFCLK |
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+ SYS_GPC_MFPL_PC1MFP_EMAC_MII_RXERR |
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+ SYS_GPC_MFPL_PC2MFP_EMAC_MII_RXDV |
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+ SYS_GPC_MFPL_PC3MFP_EMAC_MII_RXD1 |
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+ SYS_GPC_MFPL_PC4MFP_EMAC_MII_RXD0 |
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+ SYS_GPC_MFPL_PC6MFP_EMAC_MII_TXD0 |
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+ SYS_GPC_MFPL_PC7MFP_EMAC_MII_TXD1;
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+
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+ SYS->GPC_MFPH = SYS_GPC_MFPH_PC8MFP_EMAC_MII_TXEN;
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+ // Enable high slew rate on all RMII pins
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+ PC->SLEWCTL |= 0x1DF;
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+
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+ // Configure MDC, MDIO at PB14 & PB15
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+ SYS->GPB_MFPH = SYS_GPB_MFPH_PB14MFP_EMAC_MII_MDC | SYS_GPB_MFPH_PB15MFP_EMAC_MII_MDIO;
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+
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+ // Reset MAC
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+ emac_base->CTL = EMAC_CTL_RST_Msk;
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+
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+ init_tx_desc(emac);
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+ init_rx_desc(emac);
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+
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+ set_mac_addr(emac, mac_addr); // need to reconfigure hardware address 'cos we just RESET emc...
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+ reset_phy(emac);
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+
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+ emac_base->CTL |= EMAC_CTL_STRIPCRC_Msk | EMAC_CTL_RXON_Msk | EMAC_CTL_TXON_Msk | EMAC_CTL_RMIIEN_Msk | EMAC_CTL_RMIIRXCTL_Msk;
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+ emac_base->INTEN |= EMAC_INTEN_RXIEN_Msk |
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+ EMAC_INTEN_RXGDIEN_Msk |
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+ EMAC_INTEN_RDUIEN_Msk |
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+ EMAC_INTEN_RXBEIEN_Msk |
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+ EMAC_INTEN_TXIEN_Msk |
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+ EMAC_INTEN_TXABTIEN_Msk |
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+ EMAC_INTEN_TXCPIEN_Msk |
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+ EMAC_INTEN_TXBEIEN_Msk;
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+ emac_base->RXST = 0; // trigger Rx
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+
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+ //NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
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+ NVIC_SetPriority(EMAC_TX_IRQn, 0);
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+ NVIC_EnableIRQ(EMAC_TX_IRQn);
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+ NVIC_SetPriority(EMAC_RX_IRQn, 1);
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+ NVIC_EnableIRQ(EMAC_RX_IRQn);
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+}
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+
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+void ETH_halt(rt_nuc472_emac_t emac)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ emac_base->CTL &= ~(EMAC_CTL_RXON_Msk | EMAC_CTL_TXON_Msk);
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+}
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+
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+void emac_emac_done(rt_nuc472_emac_t emac)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+ unsigned int status;
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+
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+ status = emac_base->INTSTS & 0xFFFF0000;
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+ emac_base->INTSTS = status;
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+ if(status & EMAC_INTSTS_TSALMIF_Msk)
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+ {
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+ // TODO: time stamp alarm. write me!!
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+ }
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+ if(status & EMAC_INTSTS_TXBEIF_Msk)
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+ {
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+ // Shouldn't goes here, unless descriptor corrupted
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+ return;
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+ }
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+}
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+
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+rt_uint8_t *emac_get_tx_buf(rt_nuc472_emac_t emac)
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+{
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+ if(emac->cur_tx_desc_ptr->status1 & OWNERSHIP_EMAC)
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+ {
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+ return(RT_NULL);
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+ }
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+ else
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+ {
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+ return(emac->cur_tx_desc_ptr->buf);
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+ }
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+}
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+
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+void ETH_trigger_tx(rt_nuc472_emac_t emac, rt_uint16_t length)
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+{
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+ struct eth_descriptor volatile *desc;
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+
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+ emac->cur_tx_desc_ptr->status2 = (unsigned int)length;
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+ desc = emac->cur_tx_desc_ptr->next; // in case TX is transmitting and overwrite next pointer before we can update cur_tx_desc_ptr
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+ emac->cur_tx_desc_ptr->status1 |= OWNERSHIP_EMAC;
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+ emac->cur_tx_desc_ptr = desc;
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+
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+ ETH_TRIGGER_TX();
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+}
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+
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+/*
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+ * NUC472 EMAC Driver for RT-Thread
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2017-12-31 Bluebear233 first implementation
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+ */
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+void rt_nuc472_emac_tx_isr(rt_nuc472_emac_t emac)
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+{
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+ emac_emac_done(emac);
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+}
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+
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+void rt_nuc472_emac_rx_isr(rt_nuc472_emac_t emac)
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+{
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+ EMAC_T *emac_base = emac->emac_base;
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+
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+ unsigned int status = emac_base->INTSTS & 0xFFFF;
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+ emac_base->INTSTS = status;
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+
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+ eth_device_ready(&emac->parent);
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+}
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+
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+void EMAC_TX_IRQHandler(void)
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+{
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+ /* enter interrupt */
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+ rt_interrupt_enter();
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+
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+ rt_nuc472_emac_tx_isr(&nuc472_emac_device);
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+
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+ /* leave interrupt */
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+ rt_interrupt_leave();
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+}
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+
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+void EMAC_RX_IRQHandler(void)
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+{
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+ /* enter interrupt */
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+ rt_interrupt_enter();
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+
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+ rt_nuc472_emac_rx_isr(&nuc472_emac_device);
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+
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+ /* leave interrupt */
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+ rt_interrupt_leave();
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+}
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+
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+static rt_err_t rt_nuc472_emac_init(rt_device_t dev)
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+{
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+ rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev;
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+
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+ EMAC_init(emac, emac->dev_addr);
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+
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+#if LWIP_IPV4 && LWIP_IGMP
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+ netif_set_igmp_mac_filter(stm32_eth->parent.netif, igmp_mac_filter);
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+#endif /* LWIP_IPV4 && LWIP_IGMP */
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t rt_nuc472_emac_open(rt_device_t dev, rt_uint16_t oflag)
|
|
|
+{
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+static rt_err_t rt_nuc472_emac_close(rt_device_t dev)
|
|
|
+{
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+static rt_size_t rt_nuc472_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
|
|
|
+{
|
|
|
+ rt_set_errno(-RT_ENOSYS);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static rt_size_t rt_nuc472_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
|
|
|
+{
|
|
|
+ rt_set_errno(-RT_ENOSYS);
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static rt_err_t rt_nuc472_emac_control(rt_device_t dev, int cmd, void *args)
|
|
|
+{
|
|
|
+ rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev;
|
|
|
+
|
|
|
+ switch(cmd)
|
|
|
+ {
|
|
|
+ case NIOCTL_GADDR:
|
|
|
+ /* get mac address */
|
|
|
+ if(args) rt_memcpy(args, emac->dev_addr, 6);
|
|
|
+ else return -RT_ERROR;
|
|
|
+ break;
|
|
|
+
|
|
|
+ default :
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+rt_err_t rt_nuc472_emac_tx(rt_device_t dev, struct pbuf* p)
|
|
|
+{
|
|
|
+ rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev;
|
|
|
+ struct pbuf* q;
|
|
|
+ rt_uint32_t offset;
|
|
|
+ rt_uint8_t *buf = emac_get_tx_buf(emac);
|
|
|
+
|
|
|
+ /* get free tx buffer */
|
|
|
+ if(buf == RT_NULL)
|
|
|
+ {
|
|
|
+ rt_kprintf("none tx buf\n");
|
|
|
+ return -RT_ERROR;
|
|
|
+ }
|
|
|
+
|
|
|
+ offset = 0;
|
|
|
+ for (q = p; q != NULL; q = q->next)
|
|
|
+ {
|
|
|
+ rt_uint8_t* ptr;
|
|
|
+ rt_uint32_t len;
|
|
|
+
|
|
|
+ len = q->len;
|
|
|
+ ptr = q->payload;
|
|
|
+
|
|
|
+ /* Copy the frame to be sent into memory pointed by the current ETHERNET DMA Tx descriptor */
|
|
|
+ while (len)
|
|
|
+ {
|
|
|
+ buf[offset] = *ptr;
|
|
|
+
|
|
|
+ offset ++;
|
|
|
+ ptr ++;
|
|
|
+ len --;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ ETH_trigger_tx(emac, offset);
|
|
|
+
|
|
|
+ /* Return SUCCESS */
|
|
|
+ return RT_EOK;
|
|
|
+}
|
|
|
+
|
|
|
+struct pbuf *rt_nuc472_emac_rx(rt_device_t dev)
|
|
|
+{
|
|
|
+ rt_nuc472_emac_t emac = (rt_nuc472_emac_t)dev;
|
|
|
+ struct pbuf* p;
|
|
|
+
|
|
|
+ /* init p pointer */
|
|
|
+ p = RT_NULL;
|
|
|
+
|
|
|
+ unsigned int status;
|
|
|
+ status = emac->cur_rx_desc_ptr->status1;
|
|
|
+
|
|
|
+ if(status & OWNERSHIP_EMAC)
|
|
|
+ {
|
|
|
+ goto end;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (status & RXFD_RXGD)
|
|
|
+ {
|
|
|
+ //ethernetif_input(status & 0xFFFF, cur_rx_desc_ptr->buf, cur_rx_desc_ptr->status2, (u32_t)cur_rx_desc_ptr->next);
|
|
|
+ /* allocate buffer */
|
|
|
+ p = pbuf_alloc(PBUF_LINK, status & 0xFFFF, PBUF_RAM);
|
|
|
+ if (p != RT_NULL)
|
|
|
+ {
|
|
|
+ const char * from;
|
|
|
+ struct pbuf* q;
|
|
|
+
|
|
|
+ from = (const char *)(emac->cur_rx_desc_ptr->buf);
|
|
|
+
|
|
|
+ for (q = p; q != RT_NULL; q = q->next)
|
|
|
+ {
|
|
|
+ /* Copy the received frame into buffer from memory pointed by the current ETHERNET DMA Rx descriptor */
|
|
|
+ memcpy(q->payload, from, q->len);
|
|
|
+ from += q->len;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ emac->cur_rx_desc_ptr->status1 = OWNERSHIP_EMAC;
|
|
|
+ emac->cur_rx_desc_ptr = emac->cur_rx_desc_ptr->next;
|
|
|
+
|
|
|
+ return p;
|
|
|
+
|
|
|
+ end:
|
|
|
+ ETH_TRIGGER_RX();
|
|
|
+
|
|
|
+ return p;
|
|
|
+}
|
|
|
+
|
|
|
+static void rt_hw_nuc472_emac_register(rt_nuc472_emac_t emac, char *dev_name, EMAC_T *emac_base, rt_uint8_t *mac_addr)
|
|
|
+{
|
|
|
+ emac->emac_base = emac_base;
|
|
|
+
|
|
|
+ rt_memcpy(emac->dev_addr, mac_addr, sizeof(emac->dev_addr));
|
|
|
+
|
|
|
+ emac->parent.parent.init = rt_nuc472_emac_init;
|
|
|
+ emac->parent.parent.open = rt_nuc472_emac_open;
|
|
|
+ emac->parent.parent.close = rt_nuc472_emac_close;
|
|
|
+ emac->parent.parent.read = rt_nuc472_emac_read;
|
|
|
+ emac->parent.parent.write = rt_nuc472_emac_write;
|
|
|
+ emac->parent.parent.control = rt_nuc472_emac_control;
|
|
|
+ emac->parent.parent.user_data = RT_NULL;
|
|
|
+
|
|
|
+ emac->parent.eth_rx = rt_nuc472_emac_rx;
|
|
|
+ emac->parent.eth_tx = rt_nuc472_emac_tx;
|
|
|
+
|
|
|
+ /* register eth device */
|
|
|
+ eth_device_init(&(emac->parent), dev_name);
|
|
|
+}
|
|
|
+
|
|
|
+void rt_hw_nuc472_emac_init(void)
|
|
|
+{
|
|
|
+ rt_hw_nuc472_emac_register(&nuc472_emac_device, "eh0", EMAC, ethaddr);
|
|
|
+}
|
|
|
+
|
|
|
+#endif
|
bluebear233