Merge branch 'master' into at_client-rt_realloc_iss

# Conflicts:
#	components/net/at/src/at_client.c

.github/ISSUE_TEMPLATE.md

@@ -0,0 +1,3 @@
+<!--- 请清晰详细地描述你遇到的问题，描述问题时请给出芯片/BSP/工具链，RT-Thread版本，复现步骤及现象或者有条理地描述你的问题。在问题得到解决后，请及时关闭issue。欢迎到论坛提问：https://club.rt-thread.org/ -->
+
+<!--- Please describe your problem clearly and in detail. When describing the problem, please use numbers or bullet points to describe your problem coherently. After the problem is resolved, please close the issue in time. Welcome to the forum to ask questions: https://club.rt-thread.io/ -->

.github/workflows/action.yml

@@ -82,6 +82,7 @@ jobs:
          - {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}
+         - {RTT_BSP: "stm32/stm32f407-robomaster-c", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f407-st-discovery", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f410-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
          - {RTT_BSP: "stm32/stm32f411-atk-nano", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -149,10 +150,10 @@ jobs:
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-arm' && success() }}
         shell: bash
         run: |
-          wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
-          sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
-          /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
-          echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin" >> $GITHUB_ENV
+          wget -q https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2
+          sudo tar xjf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C /opt
+          /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc --version
+          echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-10-2020-q4-major/bin" >> $GITHUB_ENV
 
       - name: Install Mips ToolChains
         if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-mips' && success() }}

.github/workflows/action_utest.yml

@@ -11,33 +11,60 @@ jobs:
       fail-fast: false
       matrix:
        legs:
-         - {UTEST: "kernel/ipc",       RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "vexpress-a9", CONFIG_FILE: "examples/utest/configs/utest_self/config.h"}
-         - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9", QEMU_ARCH: "vexpress-a9", CONFIG_FILE: "examples/utest/configs/utest_self/config.h"}
-    
+         - {UTEST: "kernel/mem",       RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/mem.conf",     SD_FILE: "sd.bin"}
+         - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "utest_self/self.conf", SD_FILE: "sd.bin"}
+         - {UTEST: "kernel/mem/riscv64", RTT_BSP: "bsp/qemu-riscv-virt64", QEMU_ARCH: "riscv64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "kernel/mem.conf",   SD_FILE: "None"}
     env:
+      TEST_QEMU_ARCH: ${{ matrix.legs.QEMU_ARCH }}
+      TEST_QEMU_MACHINE: ${{ matrix.legs.QEMU_MACHINE }}
       TEST_BSP_ROOT: ${{ matrix.legs.RTT_BSP }}
       TEST_CONFIG_FILE: ${{ matrix.legs.CONFIG_FILE }}
+      TEST_SD_FILE: ${{ matrix.legs.SD_FILE }}
     steps:
     - uses: actions/checkout@v1
-    - name: Prepare env
+
+    - name: Install Tools
+      shell: bash
+      run: |
+        sudo apt-get update
+        sudo apt-get -yqq install scons qemu-system git
+
+    - name: Install Arm ToolChains
+      if: ${{ matrix.legs.QEMU_ARCH == 'arm' && success() }}
+      shell: bash
+      run: |
+        wget -q https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2
+        sudo tar xjf gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz2 -C /opt
+        /opt/gcc-arm-none-eabi-10-2020-q4-major/bin/arm-none-eabi-gcc --version
+        echo "RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-10-2020-q4-major/bin" >> $GITHUB_ENV
+
+    - name: Install RISC-V ToolChains
+      if: ${{ matrix.legs.QEMU_ARCH == 'riscv64' && success() }}
       run: |
-        sudo apt-get update > /dev/null
-        sudo apt-get -yqq install scons qemu-system-arm git
-        wget -q https://github.com/RT-Thread/toolchains-ci/releases/download/arm-2017q2-v6/gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2
-        sudo tar xjf gcc-arm-none-eabi-6-2017-q2-update-linux.tar.bz2 -C /opt
-    - name: Build bsp
+        wget -q https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
+        sudo tar zxvf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz -C /opt
+        /opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version
+        echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV
+
+    - name: Build BSP
       run: |
-        export RTT_EXEC_PATH=/opt/gcc-arm-none-eabi-6-2017-q2-update/bin
-        /opt/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-gcc --version
-        cp $TEST_CONFIG_FILE $TEST_BSP_ROOT/rtconfig.h
+        echo CONFIG_RT_USING_UTESTCASES=y >> $TEST_BSP_ROOT/.config
+        cat examples/utest/configs/$TEST_CONFIG_FILE >> $TEST_BSP_ROOT/.config
+        scons --pyconfig-silent -C $TEST_BSP_ROOT
         scons -j$(nproc) -C $TEST_BSP_ROOT
-    - name: Start test
+
+    - name: Start Test
+      if: ${{ success() }}
       run: |
         git clone https://github.com/armink/UtestRunner.git
         pushd $TEST_BSP_ROOT
         dd if=/dev/zero of=sd.bin bs=1024 count=65536
         popd
         pushd UtestRunner
-        python3 qemu_runner.py --elf ../$TEST_BSP_ROOT/rtthread.elf --sd ../$TEST_BSP_ROOT/sd.bin
+        if [ $TEST_SD_FILE != "None" ]; then
+          python3 qemu_runner.py --system $TEST_QEMU_ARCH --machine $TEST_QEMU_MACHINE --elf ../$TEST_BSP_ROOT/rtthread.elf --sd ../$TEST_BSP_ROOT/$TEST_SD_FILE
+        else
+          python3 qemu_runner.py --system $TEST_QEMU_ARCH --machine $TEST_QEMU_MACHINE --elf ../$TEST_BSP_ROOT/rtthread.elf
+        fi
         cat rtt_console.log
-        popd
+        popd

.ignore_format.yml

@@ -9,4 +9,5 @@ dir_path:
 - tools
 - components/net/lwip-1.4.1
 - components/net/lwip-2.0.2
+- components/net/lwip-2.0.3
 - components/net/lwip-2.1.2

bsp/CME_M7/rtconfig.h

@@ -91,6 +91,7 @@
 
 /* SECTION: lwip, a lighwight TCP/IP protocol stack */
 #define RT_USING_LWIP
+#define RT_USING_LWIP203
 /* Enable ICMP protocol*/
 #define RT_LWIP_ICMP
 /* Enable UDP protocol*/

bsp/bluetrum/ab32vg1-ab-prougen/.config

@@ -122,6 +122,8 @@ CONFIG_RT_USING_DEVICE_IPC=y
 CONFIG_RT_PIPE_BUFSZ=512
 # CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
 CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
@@ -197,6 +199,7 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_RT_USING_RYM is not set
 # CONFIG_RT_USING_ULOG is not set
 # CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_RT_LINK is not set
 
 #
 # RT-Thread Utestcases
@@ -320,6 +323,8 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_AZUREGUIX is not set
 # CONFIG_PKG_USING_TOUCHGFX2RTT is not set
 # CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
 
 #
 # tools packages
@@ -328,6 +333,7 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_EASYFLASH is not set
 # CONFIG_PKG_USING_EASYLOGGER is not set
 # CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
 # CONFIG_PKG_USING_RDB is not set
 # CONFIG_PKG_USING_QRCODE is not set
 # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
@@ -365,6 +371,24 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 #
 # system packages
 #
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_GUIENGINE is not set
 # CONFIG_PKG_USING_CAIRO is not set
 # CONFIG_PKG_USING_PIXMAN is not set
@@ -389,23 +413,9 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_RAMDISK is not set
 # CONFIG_PKG_USING_MININI is not set
 # CONFIG_PKG_USING_QBOOT is not set
-
-#
-# Micrium: Micrium software products porting for RT-Thread
-#
-# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
-# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
-# CONFIG_PKG_USING_UC_CRC is not set
-# CONFIG_PKG_USING_UC_CLK is not set
-# CONFIG_PKG_USING_UC_COMMON is not set
-# CONFIG_PKG_USING_UC_MODBUS is not set
 # CONFIG_PKG_USING_PPOOL is not set
 # CONFIG_PKG_USING_OPENAMP is not set
 # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
-# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
-# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
-# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
-# CONFIG_PKG_USING_QFPLIB_M3 is not set
 # CONFIG_PKG_USING_LPM is not set
 # CONFIG_PKG_USING_TLSF is not set
 # CONFIG_PKG_USING_EVENT_RECORDER is not set
@@ -433,7 +443,6 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
-# CONFIG_PKG_USING_ROSSERIAL is not set
 # CONFIG_PKG_USING_AGILE_BUTTON is not set
 # CONFIG_PKG_USING_AGILE_LED is not set
 # CONFIG_PKG_USING_AT24CXX is not set
@@ -477,6 +486,9 @@ CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 # CONFIG_PKG_USING_MFOC is not set
 # CONFIG_PKG_USING_TMC51XX is not set
 # CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
 
 #
 # AI packages

bsp/bluetrum/ab32vg1-ab-prougen/applications/mnt.c

@@ -10,7 +10,7 @@
 
 #include <rtthread.h>
 
-#ifdef BSP_USING_SDIO
+#if defined (BSP_USING_SDCARD)
 
 #include <dfs_elm.h>
 #include <dfs_fs.h>
@@ -58,4 +58,23 @@ int ab32_sdcard_mount(void)
     return RT_EOK;
 }
 INIT_APP_EXPORT(ab32_sdcard_mount);
+#elif defined (RT_USING_DFS_ROMFS)
+
+#include <dfs_fs.h>
+#include "dfs_romfs.h"
+
+int ab32_romfs_mount(void)
+{
+    if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0)
+    {
+        rt_kprintf("ROM file system initializated!\n");
+    }
+    else
+    {
+        rt_kprintf("ROM file system initializate failed!\n");
+    }
+
+    return 0;
+}
+INIT_ENV_EXPORT(ab32_romfs_mount);
 #endif

bsp/bluetrum/ab32vg1-ab-prougen/board/ports/audio/drv_sound.c

@@ -388,8 +388,6 @@ static rt_err_t sound_stop(struct rt_audio_device *audio, int stream)
 
     if (stream == AUDIO_STREAM_REPLAY)
     {
-        DACDIGCON0 = 0;
-        AUBUFCON &= ~BIT(4);
         LOG_D("close sound device");
     }
 

bsp/bluetrum/ab32vg1-ab-prougen/link.lds

@@ -34,8 +34,8 @@ SECTIONS
     } > init
 
     .ram1 __ram1_vma : {
-        . = ALIGN(4);
         /* section information for initial */
+        . = ALIGN(4);
         __rt_init_start = .;
         KEEP(*(SORT(.rti_fn*)))
         __rt_init_end = .;
@@ -75,7 +75,6 @@ SECTIONS
         KEEP(*(.vector))
         *(.irq.cache)
         *(.irq*)
-        *components*src**.o (.text* .rodata*)
         *ab32vg1_hal**.o (.text* .rodata*)
         *drv_gpio.o (.text* .rodata*)
         *drv_usart.o (.rodata*)

bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.h

@@ -81,6 +81,7 @@
 #define RT_USING_DEVICE_IPC
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
 #define RT_SERIAL_RB_BUFSZ 64
 #define RT_USING_PIN
 
@@ -145,6 +146,8 @@
 
 /* system packages */
 
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
 
 /* Micrium: Micrium software products porting for RT-Thread */
 

bsp/bluetrum/libraries/hal_drivers/drv_rtc.c

@@ -189,27 +189,27 @@ static rt_err_t ab32_rtc_control(rt_device_t dev, int cmd, void *args)
     switch (cmd)
     {
     case RT_DEVICE_CTRL_RTC_GET_TIME:
-        *(rt_uint32_t *)args = get_rtc_time_stamp();
-        LOG_D("RTC: get rtc_time %x", *(rt_uint32_t *)args);
+        *(time_t *)args = get_rtc_time_stamp();
+        LOG_D("RTC: get rtc_time %x", *(time_t *)args);
         break;
 
     case RT_DEVICE_CTRL_RTC_SET_TIME:
-        if (set_rtc_time_stamp(*(rt_uint32_t *)args))
+        if (set_rtc_time_stamp(*(time_t *)args))
         {
             result = -RT_ERROR;
         }
-        LOG_D("RTC: set rtc_time %x", *(rt_uint32_t *)args);
+        LOG_D("RTC: set rtc_time %x", *(time_t *)args);
         break;
     case RT_DEVICE_CTRL_RTC_SET_ALARM:
-        if (set_rtc_alarm_stamp(*(rt_uint32_t *)args))
+        if (set_rtc_alarm_stamp(*(time_t *)args))
         {
             result = -RT_ERROR;
         }
-        LOG_D("RTC: set alarm_stamp %x", *(rt_uint32_t *)args);
+        LOG_D("RTC: set alarm_stamp %x", *(time_t *)args);
         break;
     case RT_DEVICE_CTRL_RTC_GET_ALARM:
-        *(rt_uint32_t *)args = get_rtc_alarm_stamp();
-        LOG_D("RTC: get alarm_stamp %x", *(rt_uint32_t *)args);
+        *(time_t *)args = get_rtc_alarm_stamp();
+        LOG_D("RTC: get alarm_stamp %x", *(time_t *)args);
         break;
     }
 

bsp/efm32/drv_rtc.c

@@ -24,6 +24,8 @@
  ******************************************************************************/
 
 /* Includes ------------------------------------------------------------------*/
+
+#include <rtdevice.h>
 #include "board.h"
 #include "hdl_interrupt.h"
 #include "drv_rtc.h"

bsp/essemi/es32f0654/.config

@@ -19,7 +19,7 @@ CONFIG_RT_USING_OVERFLOW_CHECK=y
 CONFIG_RT_USING_HOOK=y
 CONFIG_RT_USING_IDLE_HOOK=y
 CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
-CONFIG_IDLE_THREAD_STACK_SIZE=256
+CONFIG_IDLE_THREAD_STACK_SIZE=512
 # CONFIG_RT_USING_TIMER_SOFT is not set
 CONFIG_RT_DEBUG=y
 CONFIG_RT_DEBUG_COLOR=y
@@ -114,26 +114,26 @@ CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
-CONFIG_RT_USING_CAN=y
+# CONFIG_RT_USING_CAN is not set
 # CONFIG_RT_CAN_USING_HDR is not set
-CONFIG_RT_USING_HWTIMER=y
+# CONFIG_RT_USING_HWTIMER is not set
 # CONFIG_RT_USING_CPUTIME is not set
-CONFIG_RT_USING_I2C=y
+# CONFIG_RT_USING_I2C is not set
 # CONFIG_RT_I2C_DEBUG is not set
-CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_USING_I2C_BITOPS is not set
 # CONFIG_RT_I2C_BITOPS_DEBUG is not set
 CONFIG_RT_USING_PIN=y
-CONFIG_RT_USING_ADC=y
+# CONFIG_RT_USING_ADC is not set
 # CONFIG_RT_USING_DAC is not set
-CONFIG_RT_USING_PWM=y
+# CONFIG_RT_USING_PWM is not set
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-CONFIG_RT_USING_PM=y
-CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_RTC is not set
 # CONFIG_RT_USING_ALARM is not set
 # CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_QSPI is not set
 # CONFIG_RT_USING_SPI_MSD is not set
 # CONFIG_RT_USING_SFUD is not set
@@ -159,7 +159,8 @@ CONFIG_RT_USING_SPI=y
 #
 # CONFIG_RT_USING_LIBC is not set
 # CONFIG_RT_USING_PTHREADS is not set
-# CONFIG_RT_LIBC_USING_TIME is not set
+CONFIG_RT_LIBC_USING_TIME=y
+CONFIG_RT_LIBC_FIXED_TIMEZONE=8
 
 #
 # Network
@@ -468,6 +469,8 @@ CONFIG_BSP_USING_GPIO=y
 # CONFIG_BSP_USING_UART1 is not set
 CONFIG_BSP_USING_UART2=y
 # CONFIG_BSP_USING_UART3 is not set
+# CONFIG_BSP_USING_USART0 is not set
+# CONFIG_BSP_USING_USART1 is not set
 
 #
 # SPI Drivers
@@ -484,23 +487,26 @@ CONFIG_BSP_USING_UART2=y
 #
 # CAN Drivers
 #
-# CONFIG_BSP_USING_CAN is not set
+# CONFIG_BSP_USING_CAN0 is not set
 
 #
 # PWM Drivers
 #
-# CONFIG_BSP_USING_PWM0 is not set
-# CONFIG_BSP_USING_PWM1 is not set
-# CONFIG_BSP_USING_PWM2 is not set
-# CONFIG_BSP_USING_PWM3 is not set
+# CONFIG_BSP_USING_AD16C4T0_PWM is not set
+# CONFIG_BSP_USING_GP16C4T0_PWM is not set
+# CONFIG_BSP_USING_GP16C2T0_PWM is not set
+# CONFIG_BSP_USING_GP16C2T1_PWM is not set
 
 #
 # HWtimer Drivers
 #
-# CONFIG_BSP_USING_HWTIMER0 is not set
-# CONFIG_BSP_USING_HWTIMER1 is not set
-# CONFIG_BSP_USING_HWTIMER2 is not set
-# CONFIG_BSP_USING_HWTIMER3 is not set
+# CONFIG_BSP_USING_AD16C4T0_HWTIMER is not set
+# CONFIG_BSP_USING_GP16C4T0_HWTIMER is not set
+# CONFIG_BSP_USING_GP16C2T0_HWTIMER is not set
+# CONFIG_BSP_USING_GP16C2T1_HWTIMER is not set
+# CONFIG_BSP_USING_BS16T0_HWTIMER is not set
+# CONFIG_BSP_USING_BS16T2_HWTIMER is not set
+# CONFIG_BSP_USING_BS16T3_HWTIMER is not set
 
 #
 # RTC Drivers
@@ -515,7 +521,7 @@ CONFIG_BSP_USING_UART2=y
 #
 # ADC Drivers
 #
-# CONFIG_BSP_USING_ADC is not set
+# CONFIG_BSP_USING_ADC0 is not set
 
 #
 # Onboard Peripheral Drivers
@@ -532,6 +538,7 @@ CONFIG_BSP_USING_UART2=y
 # CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set
 # CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set
 # CONFIG_BSP_USING_EXAMPLE_I2C is not set
+# CONFIG_BSP_USING_EXAMPLE_I2C_E2PROM is not set
 # CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set
 # CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set
 # CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set

bsp/essemi/es32f0654/drivers/ES/Kconfig

@@ -0,0 +1,160 @@
+menu "UART Drivers"
+
+    config BSP_USING_UART0
+        bool "Register UART0"
+        select RT_USING_SERIAL
+        default n
+
+    config BSP_USING_UART1
+        bool "Register UART1"
+        select RT_USING_SERIAL
+        default n
+
+    config BSP_USING_UART2
+        bool "Register UART2"
+        select RT_USING_SERIAL
+        default y
+
+    config BSP_USING_UART3
+        bool "Register UART3"
+        select RT_USING_SERIAL
+        default n
+
+    config BSP_USING_USART0
+        bool "Register USART0"
+        select RT_USING_SERIAL
+        default n
+
+    config BSP_USING_USART1
+        bool "Register USART1"
+        select RT_USING_SERIAL
+        default n
+endmenu
+
+menu "SPI Drivers"
+
+    config BSP_USING_SPI0
+        bool "Register SPI0"
+        select RT_USING_SPI
+        select RT_USING_PIN
+        default n
+
+    config BSP_USING_SPI1
+        bool "Register SPI1"
+        select RT_USING_SPI
+        select RT_USING_PIN
+        default n
+endmenu
+
+menu "I2C Drivers"
+    config BSP_USING_I2C0
+        bool "Register I2C0"
+        select RT_USING_I2C
+        default n
+
+    config BSP_USING_I2C1
+        bool "Register I2C1"
+        select RT_USING_I2C
+        default n
+endmenu
+
+menu "CAN Drivers"
+    config BSP_USING_CAN0
+        bool "Register CAN0"
+        select RT_USING_CAN
+        select RT_CAN_USING_HDR
+        default n
+endmenu
+
+menu "PWM Drivers"
+    config BSP_USING_AD16C4T0_PWM
+        bool "Register pwm0"
+        select RT_USING_PWM
+        default n 
+
+    config BSP_USING_GP16C4T0_PWM
+        bool "Register pwm1"
+        select RT_USING_PWM
+        default n
+
+    config BSP_USING_GP16C2T0_PWM
+        bool "Register pwm2"
+        select RT_USING_PWM
+        default n
+
+    config BSP_USING_GP16C2T1_PWM
+        bool "Register pwm3"
+        select RT_USING_PWM
+        default n
+endmenu
+
+menu "HWtimer Drivers"
+    config BSP_USING_AD16C4T0_HWTIMER
+        bool "Register timer0"
+        select RT_USING_HWTIMER
+        default n
+        depends on !BSP_USING_AD16C4T0_PWM
+
+    config BSP_USING_GP16C4T0_HWTIMER
+        bool "Register timer1"
+        select RT_USING_HWTIMER
+        default n
+        depends on !BSP_USING_GP16C4T0_PWM
+
+    config BSP_USING_GP16C2T0_HWTIMER
+        bool "Register timer2"
+        select RT_USING_HWTIMER
+        default n
+        depends on !BSP_USING_GP16C2T0_PWM
+
+    config BSP_USING_GP16C2T1_HWTIMER
+        bool "Register timer3"
+        select RT_USING_HWTIMER
+        default n
+        depends on !BSP_USING_GP16C2T1_PWM
+
+    config BSP_USING_BS16T0_HWTIMER
+        bool "Register timer4"
+        select RT_USING_HWTIMER
+        default n
+
+    config BSP_USING_BS16T1_HWTIMER
+        bool "Register timer5"
+        select RT_USING_HWTIMER
+        default n
+        depends on !BSP_USING_UART2
+
+    config BSP_USING_BS16T2_HWTIMER
+        bool "Register timer6"
+        select RT_USING_HWTIMER
+        default n
+        depends on !BSP_USING_UART3
+
+    config BSP_USING_BS16T3_HWTIMER
+        bool "Register timer7"
+        select RT_USING_HWTIMER
+        default n
+endmenu
+
+menu "RTC Drivers"
+    config BSP_USING_RTC
+        bool "Register RTC"
+        select RT_USING_RTC
+        default n
+endmenu
+
+menu "PM Drivers"
+    config BSP_USING_PM
+        bool "Using PM"
+        select RT_USING_PM
+        default n
+endmenu
+
+menu "ADC Drivers"
+    config BSP_USING_ADC0
+        bool "Using ADC"
+        select RT_USING_ADC
+        select BSP_USING_ADC
+        default n
+endmenu
+

bsp/essemi/es32f0654/drivers/ES/es_conf_info_adc.h

@@ -0,0 +1,97 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_ADC_H__
+#define __ES_CONF_INFO_ADC_H__
+ 
+#include "es_conf_info_map.h"
+
+#include <ald_adc.h>
+
+
+#define ES_C_ADC_CLK_DIV_1     ADC_CKDIV_1      
+#define ES_C_ADC_CLK_DIV_2     ADC_CKDIV_2
+#define ES_C_ADC_CLK_DIV_4     ADC_CKDIV_4
+#define ES_C_ADC_CLK_DIV_8     ADC_CKDIV_8
+#define ES_C_ADC_CLK_DIV_16     ADC_CKDIV_16
+#define ES_C_ADC_CLK_DIV_32     ADC_CKDIV_32  
+#define ES_C_ADC_CLK_DIV_64     ADC_CKDIV_64
+#define ES_C_ADC_CLK_DIV_128     ADC_CKDIV_128
+
+#define ES_C_ADC_ALIGN_RIGHT        ADC_DATAALIGN_RIGHT   
+#define ES_C_ADC_ALIGN_LEFT        ADC_DATAALIGN_LEFT
+
+#define ES_C_ADC_CONV_BIT_6        ADC_CONV_BIT_6 
+#define ES_C_ADC_CONV_BIT_8        ADC_CONV_BIT_8
+#define ES_C_ADC_CONV_BIT_10        ADC_CONV_BIT_10
+#define ES_C_ADC_CONV_BIT_12        ADC_CONV_BIT_12
+   
+#define ES_C_ADC_SAMPLE_TIME_1       ADC_SAMPLETIME_1   
+#define ES_C_ADC_SAMPLE_TIME_2       ADC_SAMPLETIME_2
+#define ES_C_ADC_SAMPLE_TIME_4       ADC_SAMPLETIME_4
+#define ES_C_ADC_SAMPLE_TIME_15       ADC_SAMPLETIME_15
+
+/* ADC 配置 */
+
+/* codes_main */
+
+
+#define ES_ADC0_ALIGN      ES_C_ADC_ALIGN_RIGHT    
+#define ES_ADC1_ALIGN      ES_C_ADC_ALIGN_RIGHT   
+#define ES_ADC1_DATA_BIT   ES_C_ADC_CONV_BIT_12      
+#define ES_ADC0_DATA_BIT   ES_C_ADC_CONV_BIT_12
+
+#ifndef  ES_DEVICE_NAME_ADC0
+#define  ES_DEVICE_NAME_ADC0     "adc0"
+#endif 
+#ifndef  ES_DEVICE_NAME_ADC1
+#define  ES_DEVICE_NAME_ADC1     "adc1"
+#endif
+
+#ifndef  ES_ADC0_CLK_DIV 
+#define ES_ADC0_CLK_DIV    ES_C_ADC_CLK_DIV_128 
+#endif                   
+#ifndef  ES_ADC0_ALIGN 
+#define ES_ADC0_ALIGN      ES_C_ADC_ALIGN_RIGHT
+#endif
+#ifndef  ES_ADC0_DATA_BIT 
+#define ES_ADC0_DATA_BIT   ES_C_ADC_CONV_BIT_12
+#endif
+#ifndef  ES_ADC0_NCH_SAMPLETIME 
+#define ES_ADC0_NCH_SAMPLETIME    ES_C_ADC_SAMPLE_TIME_4
+#endif
+
+#ifndef  ES_ADC1_CLK_DIV 
+#define ES_ADC1_CLK_DIV    ES_C_ADC_CLK_DIV_128 
+#endif                   
+#ifndef  ES_ADC1_ALIGN 
+#define ES_ADC1_ALIGN      ES_C_ADC_ALIGN_RIGHT
+#endif
+#ifndef  ES_ADC1_DATA_BIT 
+#define ES_ADC1_DATA_BIT   ES_C_ADC_CONV_BIT_12
+#endif
+#ifndef  ES_ADC1_NCH_SAMPLETIME 
+#define ES_ADC1_NCH_SAMPLETIME    ES_C_ADC_SAMPLE_TIME_4
+#endif
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_can.h

@@ -0,0 +1,73 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_CAN_H__
+#define __ES_CONF_INFO_CAN_H__
+
+#include "es_conf_info_map.h"
+#include <ald_can.h>
+#include <ald_gpio.h>
+
+
+/*默认的CAN硬件过滤器的编号   0 */
+#define ES_C_CAN_DEFAULT_FILTER_NUMBER   0
+
+/*硬件过滤器，过滤帧类型*/  
+#define ES_C_CAN_FILTER_FRAME_TYPE       0
+
+
+#define ES_C_CAN_SJW_NUM_1   CAN_SJW_1 
+#define ES_C_CAN_SJW_NUM_2   CAN_SJW_2
+#define ES_C_CAN_SJW_NUM_3   CAN_SJW_3
+#define ES_C_CAN_SJW_NUM_4   CAN_SJW_4
+
+
+
+/* CAN 配置 */
+     
+/* codes_main */
+
+
+
+#ifndef  ES_DEVICE_NAME_CAN0
+#define  ES_DEVICE_NAME_CAN0     "can0"
+#endif
+
+#ifndef  ES_CAN0_AUTO_BAN_RE_T
+#define ES_CAN0_AUTO_BAN_RE_T    ES_C_ENABLE
+#endif            
+#ifndef  ES_CAN0_SPEED
+#define ES_CAN0_SPEED           1000000
+#endif
+#ifndef  ES_CAN0_SJW
+#define ES_CAN0_SJW             ES_C_CAN_SJW_NUM_4
+#endif
+
+#define ES_CAN0_CONFIG        \
+{                               \
+        ES_CAN0_SPEED,              \
+        RT_CANMSG_BOX_SZ,       \
+        RT_CANSND_BOX_NUM,      \
+        RT_CAN_MODE_NORMAL,     \
+};
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_cmu.h

@@ -0,0 +1,87 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_CMU_H__
+#define __ES_CONF_INFO_CMU_H__
+
+
+#include <ald_cmu.h> 
+
+
+/* 时钟树 配置 */
+
+#define   ES_C_MUL_9          CMU_PLL1_OUTPUT_36M
+#define   ES_C_MUL_12         CMU_PLL1_OUTPUT_48M
+
+#define  ES_C_DIV_1          CMU_DIV_1  
+#define  ES_C_DIV_2          CMU_DIV_2 
+#define  ES_C_DIV_4          CMU_DIV_4 
+#define  ES_C_DIV_8          CMU_DIV_8 
+#define  ES_C_DIV_16          CMU_DIV_16 
+#define  ES_C_DIV_32          CMU_DIV_32 
+#define  ES_C_DIV_64          CMU_DIV_64 
+#define  ES_C_DIV_128          CMU_DIV_128 
+#define  ES_C_DIV_256          CMU_DIV_256 
+#define  ES_C_DIV_512          CMU_DIV_512 
+#define  ES_C_DIV_1024          CMU_DIV_1024 
+#define  ES_C_DIV_2048          CMU_DIV_2048 
+#define  ES_C_DIV_4096          CMU_DIV_4096 
+
+#define  ES_C_HOSC_DIV_1        CMU_PLL1_INPUT_HOSC
+#define  ES_C_HOSC_DIV_2        CMU_PLL1_INPUT_HOSC_2
+#define  ES_C_HOSC_DIV_3        CMU_PLL1_INPUT_HOSC_3
+#define  ES_C_HOSC_DIV_4        CMU_PLL1_INPUT_HOSC_4
+#define  ES_C_HOSC_DIV_5        CMU_PLL1_INPUT_HOSC_5
+#define  ES_C_HOSC_DIV_6        CMU_PLL1_INPUT_HOSC_6
+#define  ES_C_HRC_DIV_6         CMU_PLL1_INPUT_HRC_6
+
+
+
+
+
+#define   ES_PLL1_REFER_CLK           ES_C_HOSC_DIV_3
+#define   ES_PLL1_OUT_CLK             ES_C_MUL_12
+#define   ES_CMU_PLL1_EN              ES_C_ENABLE
+#define   ES_CMU_PLL1_SAFE_EN         ES_C_DISABLE
+#define   ES_CMU_LOSC_EN              ES_C_ENABLE
+#define   ES_CMU_LRC_EN               ES_C_ENABLE
+#define   ES_CMU_HOSC_EN              ES_C_ENABLE
+#define   ES_CMU_HRC_EN               ES_C_ENABLE
+#define   ES_CMU_SYS_DIV              ES_C_DIV_1
+#define   ES_CMU_HCLK_1_DIV           ES_C_DIV_1
+#define   ES_CMU_PCLK_1_DIV           ES_C_DIV_1
+#define   ES_CMU_PCLK_2_DIV           ES_C_DIV_1
+#define   ES_SYS_CLK_SOURSE           CMU_CLOCK_PLL1
+#define   ES_PLL_CLK                  48000000
+#define   ES_SYS_SOURCE_CLK           48000000
+#define   ES_SYS_CLK                  48000000
+#define   ES_PCLK1_CLK                48000000
+#define   ES_PCLK2_CLK                48000000
+#define   ES_HCLK1_CLK                48000000
+#define   ES_CMU_EXTERN_CLK_LOSC      32768
+#define   ES_CMU_EXTERN_CLK_HOSC      12000000
+
+
+
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_gpio.h

@@ -0,0 +1,5158 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_GPIO_H__
+#define __ES_CONF_INFO_GPIO_H__
+
+#include "es_conf_info_map.h"
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <ald_cmu.h>
+
+/* GPIO 配置 */
+
+typedef struct {
+		uint8_t pin; 
+		uint8_t pin_mode; 
+		uint8_t pin_level;
+		uint8_t irq_en;
+		uint8_t irq_mode;
+        void (*callback)(void *arg); 
+} gpio_conf_t;
+
+/*参数的定义*/
+
+#define ES_C_GPIO_LEVEL_HIGH          PIN_HIGH    
+#define ES_C_GPIO_LEVEL_LOW           PIN_LOW
+
+#define ES_C_GPIO_MODE_OUTPUT           PIN_MODE_OUTPUT    
+#define ES_C_GPIO_MODE_INPUT            PIN_MODE_INPUT    
+#define ES_C_GPIO_MODE_INPUT_PULLUP     PIN_MODE_INPUT_PULLUP  
+#define ES_C_GPIO_MODE_INPUT_PULLDOWN   PIN_MODE_INPUT_PULLDOWN 
+#define ES_C_GPIO_MODE_OUTPUT_OD        PIN_MODE_OUTPUT_OD     
+
+#define ES_C_GPIO_IRQ_ENABLE       PIN_IRQ_ENABLE    
+#define ES_C_GPIO_IRQ_DISABLE      PIN_IRQ_DISABLE
+
+#define ES_C_GPIO_IRQ_MODE_FALL    PIN_IRQ_MODE_FALLING    
+#define ES_C_GPIO_IRQ_MODE_RISE    PIN_IRQ_MODE_RISING
+#define ES_C_GPIO_IRQ_MODE_R_F    PIN_IRQ_MODE_RISING_FALLING
+
+
+
+
+
+/* codes_main */
+//#define ES_INIT_PIN_GPIO_C_8
+//#define ES_INIT_GPIO_C_8_IRQ_EN   ES_C_GPIO_IRQ_ENABLE
+
+
+
+#ifndef  ES_DEVICE_NAME_PIN
+#define  ES_DEVICE_NAME_PIN     "pin"
+#endif
+
+/*GPIO外部中断回调函数控制需要，补充是否中断*/
+#if 11111
+    
+#ifndef  ES_INIT_GPIO_A_0_IRQ_EN
+#define ES_INIT_GPIO_A_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_1_IRQ_EN
+#define ES_INIT_GPIO_A_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_2_IRQ_EN
+#define ES_INIT_GPIO_A_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_3_IRQ_EN
+#define ES_INIT_GPIO_A_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_4_IRQ_EN
+#define ES_INIT_GPIO_A_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_5_IRQ_EN
+#define ES_INIT_GPIO_A_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_6_IRQ_EN
+#define ES_INIT_GPIO_A_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_7_IRQ_EN
+#define ES_INIT_GPIO_A_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_8_IRQ_EN
+#define ES_INIT_GPIO_A_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_9_IRQ_EN
+#define ES_INIT_GPIO_A_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_10_IRQ_EN
+#define ES_INIT_GPIO_A_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_11_IRQ_EN
+#define ES_INIT_GPIO_A_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_12_IRQ_EN
+#define ES_INIT_GPIO_A_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_13_IRQ_EN
+#define ES_INIT_GPIO_A_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_14_IRQ_EN
+#define ES_INIT_GPIO_A_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_A_15_IRQ_EN
+#define ES_INIT_GPIO_A_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_0_IRQ_EN
+#define ES_INIT_GPIO_B_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_1_IRQ_EN
+#define ES_INIT_GPIO_B_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_2_IRQ_EN
+#define ES_INIT_GPIO_B_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_3_IRQ_EN
+#define ES_INIT_GPIO_B_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_4_IRQ_EN
+#define ES_INIT_GPIO_B_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_5_IRQ_EN
+#define ES_INIT_GPIO_B_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_6_IRQ_EN
+#define ES_INIT_GPIO_B_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_7_IRQ_EN
+#define ES_INIT_GPIO_B_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_8_IRQ_EN
+#define ES_INIT_GPIO_B_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_9_IRQ_EN
+#define ES_INIT_GPIO_B_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_10_IRQ_EN
+#define ES_INIT_GPIO_B_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_11_IRQ_EN
+#define ES_INIT_GPIO_B_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_12_IRQ_EN
+#define ES_INIT_GPIO_B_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_13_IRQ_EN
+#define ES_INIT_GPIO_B_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_14_IRQ_EN
+#define ES_INIT_GPIO_B_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_B_15_IRQ_EN
+#define ES_INIT_GPIO_B_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_0_IRQ_EN
+#define ES_INIT_GPIO_C_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_1_IRQ_EN
+#define ES_INIT_GPIO_C_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_2_IRQ_EN
+#define ES_INIT_GPIO_C_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_3_IRQ_EN
+#define ES_INIT_GPIO_C_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_4_IRQ_EN
+#define ES_INIT_GPIO_C_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_5_IRQ_EN
+#define ES_INIT_GPIO_C_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_6_IRQ_EN
+#define ES_INIT_GPIO_C_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_7_IRQ_EN
+#define ES_INIT_GPIO_C_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_8_IRQ_EN
+#define ES_INIT_GPIO_C_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_9_IRQ_EN
+#define ES_INIT_GPIO_C_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_10_IRQ_EN
+#define ES_INIT_GPIO_C_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_11_IRQ_EN
+#define ES_INIT_GPIO_C_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_12_IRQ_EN
+#define ES_INIT_GPIO_C_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_13_IRQ_EN
+#define ES_INIT_GPIO_C_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_14_IRQ_EN
+#define ES_INIT_GPIO_C_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_C_15_IRQ_EN
+#define ES_INIT_GPIO_C_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_0_IRQ_EN
+#define ES_INIT_GPIO_D_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_1_IRQ_EN
+#define ES_INIT_GPIO_D_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_2_IRQ_EN
+#define ES_INIT_GPIO_D_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_3_IRQ_EN
+#define ES_INIT_GPIO_D_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_4_IRQ_EN
+#define ES_INIT_GPIO_D_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_5_IRQ_EN
+#define ES_INIT_GPIO_D_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_6_IRQ_EN
+#define ES_INIT_GPIO_D_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_7_IRQ_EN
+#define ES_INIT_GPIO_D_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_8_IRQ_EN
+#define ES_INIT_GPIO_D_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_9_IRQ_EN
+#define ES_INIT_GPIO_D_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_10_IRQ_EN
+#define ES_INIT_GPIO_D_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_11_IRQ_EN
+#define ES_INIT_GPIO_D_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_12_IRQ_EN
+#define ES_INIT_GPIO_D_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_13_IRQ_EN
+#define ES_INIT_GPIO_D_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_14_IRQ_EN
+#define ES_INIT_GPIO_D_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_D_15_IRQ_EN
+#define ES_INIT_GPIO_D_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_0_IRQ_EN
+#define ES_INIT_GPIO_E_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_1_IRQ_EN
+#define ES_INIT_GPIO_E_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_2_IRQ_EN
+#define ES_INIT_GPIO_E_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_3_IRQ_EN
+#define ES_INIT_GPIO_E_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_4_IRQ_EN
+#define ES_INIT_GPIO_E_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_5_IRQ_EN
+#define ES_INIT_GPIO_E_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_6_IRQ_EN
+#define ES_INIT_GPIO_E_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_7_IRQ_EN
+#define ES_INIT_GPIO_E_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_8_IRQ_EN
+#define ES_INIT_GPIO_E_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_9_IRQ_EN
+#define ES_INIT_GPIO_E_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_10_IRQ_EN
+#define ES_INIT_GPIO_E_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_11_IRQ_EN
+#define ES_INIT_GPIO_E_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_12_IRQ_EN
+#define ES_INIT_GPIO_E_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_13_IRQ_EN
+#define ES_INIT_GPIO_E_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_14_IRQ_EN
+#define ES_INIT_GPIO_E_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_E_15_IRQ_EN
+#define ES_INIT_GPIO_E_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_0_IRQ_EN
+#define ES_INIT_GPIO_F_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_1_IRQ_EN
+#define ES_INIT_GPIO_F_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_2_IRQ_EN
+#define ES_INIT_GPIO_F_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_3_IRQ_EN
+#define ES_INIT_GPIO_F_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_4_IRQ_EN
+#define ES_INIT_GPIO_F_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_5_IRQ_EN
+#define ES_INIT_GPIO_F_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_6_IRQ_EN
+#define ES_INIT_GPIO_F_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_7_IRQ_EN
+#define ES_INIT_GPIO_F_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_8_IRQ_EN
+#define ES_INIT_GPIO_F_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_9_IRQ_EN
+#define ES_INIT_GPIO_F_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_10_IRQ_EN
+#define ES_INIT_GPIO_F_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_11_IRQ_EN
+#define ES_INIT_GPIO_F_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_12_IRQ_EN
+#define ES_INIT_GPIO_F_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_13_IRQ_EN
+#define ES_INIT_GPIO_F_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_14_IRQ_EN
+#define ES_INIT_GPIO_F_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_F_15_IRQ_EN
+#define ES_INIT_GPIO_F_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_0_IRQ_EN
+#define ES_INIT_GPIO_G_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_1_IRQ_EN
+#define ES_INIT_GPIO_G_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_2_IRQ_EN
+#define ES_INIT_GPIO_G_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_3_IRQ_EN
+#define ES_INIT_GPIO_G_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_4_IRQ_EN
+#define ES_INIT_GPIO_G_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_5_IRQ_EN
+#define ES_INIT_GPIO_G_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_6_IRQ_EN
+#define ES_INIT_GPIO_G_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_7_IRQ_EN
+#define ES_INIT_GPIO_G_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_8_IRQ_EN
+#define ES_INIT_GPIO_G_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_9_IRQ_EN
+#define ES_INIT_GPIO_G_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_10_IRQ_EN
+#define ES_INIT_GPIO_G_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_11_IRQ_EN
+#define ES_INIT_GPIO_G_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_12_IRQ_EN
+#define ES_INIT_GPIO_G_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_13_IRQ_EN
+#define ES_INIT_GPIO_G_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_14_IRQ_EN
+#define ES_INIT_GPIO_G_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_G_15_IRQ_EN
+#define ES_INIT_GPIO_G_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_0_IRQ_EN
+#define ES_INIT_GPIO_H_0_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_1_IRQ_EN
+#define ES_INIT_GPIO_H_1_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_2_IRQ_EN
+#define ES_INIT_GPIO_H_2_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_3_IRQ_EN
+#define ES_INIT_GPIO_H_3_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_4_IRQ_EN
+#define ES_INIT_GPIO_H_4_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_5_IRQ_EN
+#define ES_INIT_GPIO_H_5_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_6_IRQ_EN
+#define ES_INIT_GPIO_H_6_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_7_IRQ_EN
+#define ES_INIT_GPIO_H_7_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_8_IRQ_EN
+#define ES_INIT_GPIO_H_8_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_9_IRQ_EN
+#define ES_INIT_GPIO_H_9_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_10_IRQ_EN
+#define ES_INIT_GPIO_H_10_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_11_IRQ_EN
+#define ES_INIT_GPIO_H_11_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_12_IRQ_EN
+#define ES_INIT_GPIO_H_12_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_13_IRQ_EN
+#define ES_INIT_GPIO_H_13_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_14_IRQ_EN
+#define ES_INIT_GPIO_H_14_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#ifndef  ES_INIT_GPIO_H_15_IRQ_EN
+#define ES_INIT_GPIO_H_15_IRQ_EN   ES_C_GPIO_IRQ_DISABLE
+#endif
+
+#endif //11111
+
+
+
+/*是否需要 GPIO外部中断回调函数 （控制函数本体+声明）*/
+#if 11111
+
+#if (ES_INIT_GPIO_A_0_IRQ_EN)||(ES_INIT_GPIO_B_0_IRQ_EN)||(ES_INIT_GPIO_C_0_IRQ_EN)||(ES_INIT_GPIO_D_0_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_0_IRQ_EN)||(ES_INIT_GPIO_F_0_IRQ_EN)||(ES_INIT_GPIO_G_0_IRQ_EN)||(ES_INIT_GPIO_H_0_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_0
+#endif
+
+#if (ES_INIT_GPIO_A_1_IRQ_EN)||(ES_INIT_GPIO_B_1_IRQ_EN)||(ES_INIT_GPIO_C_1_IRQ_EN)||(ES_INIT_GPIO_D_1_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_1_IRQ_EN)||(ES_INIT_GPIO_F_1_IRQ_EN)||(ES_INIT_GPIO_G_1_IRQ_EN)||(ES_INIT_GPIO_H_1_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_1
+#endif
+
+#if (ES_INIT_GPIO_A_2_IRQ_EN)||(ES_INIT_GPIO_B_2_IRQ_EN)||(ES_INIT_GPIO_C_2_IRQ_EN)||(ES_INIT_GPIO_D_2_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_2_IRQ_EN)||(ES_INIT_GPIO_F_2_IRQ_EN)||(ES_INIT_GPIO_G_2_IRQ_EN)||(ES_INIT_GPIO_H_2_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_2
+#endif
+
+#if (ES_INIT_GPIO_A_3_IRQ_EN)||(ES_INIT_GPIO_B_3_IRQ_EN)||(ES_INIT_GPIO_C_3_IRQ_EN)||(ES_INIT_GPIO_D_3_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_3_IRQ_EN)||(ES_INIT_GPIO_F_3_IRQ_EN)||(ES_INIT_GPIO_G_3_IRQ_EN)||(ES_INIT_GPIO_H_3_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_3
+#endif
+
+#if (ES_INIT_GPIO_A_4_IRQ_EN)||(ES_INIT_GPIO_B_4_IRQ_EN)||(ES_INIT_GPIO_C_4_IRQ_EN)||(ES_INIT_GPIO_D_4_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_4_IRQ_EN)||(ES_INIT_GPIO_F_4_IRQ_EN)||(ES_INIT_GPIO_G_4_IRQ_EN)||(ES_INIT_GPIO_H_4_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_4
+#endif
+
+#if (ES_INIT_GPIO_A_5_IRQ_EN)||(ES_INIT_GPIO_B_5_IRQ_EN)||(ES_INIT_GPIO_C_5_IRQ_EN)||(ES_INIT_GPIO_D_5_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_5_IRQ_EN)||(ES_INIT_GPIO_F_5_IRQ_EN)||(ES_INIT_GPIO_G_5_IRQ_EN)||(ES_INIT_GPIO_H_5_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_5
+#endif
+
+#if (ES_INIT_GPIO_A_6_IRQ_EN)||(ES_INIT_GPIO_B_6_IRQ_EN)||(ES_INIT_GPIO_C_6_IRQ_EN)||(ES_INIT_GPIO_D_6_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_6_IRQ_EN)||(ES_INIT_GPIO_F_6_IRQ_EN)||(ES_INIT_GPIO_G_6_IRQ_EN)||(ES_INIT_GPIO_H_6_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_6
+#endif
+
+#if (ES_INIT_GPIO_A_7_IRQ_EN)||(ES_INIT_GPIO_B_7_IRQ_EN)||(ES_INIT_GPIO_C_7_IRQ_EN)||(ES_INIT_GPIO_D_7_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_7_IRQ_EN)||(ES_INIT_GPIO_F_7_IRQ_EN)||(ES_INIT_GPIO_G_7_IRQ_EN)||(ES_INIT_GPIO_H_7_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_7
+#endif
+
+#if (ES_INIT_GPIO_A_8_IRQ_EN)||(ES_INIT_GPIO_B_8_IRQ_EN)||(ES_INIT_GPIO_C_8_IRQ_EN)||(ES_INIT_GPIO_D_8_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_8_IRQ_EN)||(ES_INIT_GPIO_F_8_IRQ_EN)||(ES_INIT_GPIO_G_8_IRQ_EN)||(ES_INIT_GPIO_H_8_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_8
+#endif
+
+#if (ES_INIT_GPIO_A_9_IRQ_EN)||(ES_INIT_GPIO_B_9_IRQ_EN)||(ES_INIT_GPIO_C_9_IRQ_EN)||(ES_INIT_GPIO_D_9_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_9_IRQ_EN)||(ES_INIT_GPIO_F_9_IRQ_EN)||(ES_INIT_GPIO_G_9_IRQ_EN)||(ES_INIT_GPIO_H_9_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_9
+#endif
+
+#if (ES_INIT_GPIO_A_10_IRQ_EN)||(ES_INIT_GPIO_B_10_IRQ_EN)||(ES_INIT_GPIO_C_10_IRQ_EN)||(ES_INIT_GPIO_D_10_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_10_IRQ_EN)||(ES_INIT_GPIO_F_10_IRQ_EN)||(ES_INIT_GPIO_G_10_IRQ_EN)||(ES_INIT_GPIO_H_10_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_10
+#endif
+
+#if (ES_INIT_GPIO_A_11_IRQ_EN)||(ES_INIT_GPIO_B_11_IRQ_EN)||(ES_INIT_GPIO_C_11_IRQ_EN)||(ES_INIT_GPIO_D_11_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_11_IRQ_EN)||(ES_INIT_GPIO_F_11_IRQ_EN)||(ES_INIT_GPIO_G_11_IRQ_EN)||(ES_INIT_GPIO_H_11_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_11
+#endif
+
+#if (ES_INIT_GPIO_A_12_IRQ_EN)||(ES_INIT_GPIO_B_12_IRQ_EN)||(ES_INIT_GPIO_C_12_IRQ_EN)||(ES_INIT_GPIO_D_12_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_12_IRQ_EN)||(ES_INIT_GPIO_F_12_IRQ_EN)||(ES_INIT_GPIO_G_12_IRQ_EN)||(ES_INIT_GPIO_H_12_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_12
+#endif
+
+#if (ES_INIT_GPIO_A_13_IRQ_EN)||(ES_INIT_GPIO_B_13_IRQ_EN)||(ES_INIT_GPIO_C_13_IRQ_EN)||(ES_INIT_GPIO_D_13_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_13_IRQ_EN)||(ES_INIT_GPIO_F_13_IRQ_EN)||(ES_INIT_GPIO_G_13_IRQ_EN)||(ES_INIT_GPIO_H_13_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_13
+#endif
+
+#if (ES_INIT_GPIO_A_14_IRQ_EN)||(ES_INIT_GPIO_B_14_IRQ_EN)||(ES_INIT_GPIO_C_14_IRQ_EN)||(ES_INIT_GPIO_D_14_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_14_IRQ_EN)||(ES_INIT_GPIO_F_14_IRQ_EN)||(ES_INIT_GPIO_G_14_IRQ_EN)||(ES_INIT_GPIO_H_14_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_14
+#endif
+
+#if (ES_INIT_GPIO_A_15_IRQ_EN)||(ES_INIT_GPIO_B_15_IRQ_EN)||(ES_INIT_GPIO_C_15_IRQ_EN)||(ES_INIT_GPIO_D_15_IRQ_EN)||   \
+     (ES_INIT_GPIO_E_15_IRQ_EN)||(ES_INIT_GPIO_F_15_IRQ_EN)||(ES_INIT_GPIO_G_15_IRQ_EN)||(ES_INIT_GPIO_H_15_IRQ_EN)
+#define  ES_CONF_EXTI_IRQ_15
+#endif
+
+#endif //11111
+
+
+/*GPIO外部中断 声明*/
+#if 11111
+
+#ifdef ES_CONF_EXTI_IRQ_0
+void irq_pin0_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_1
+void irq_pin1_callback(void* arg);    
+#endif   
+
+#ifdef ES_CONF_EXTI_IRQ_2
+void irq_pin2_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_3
+void irq_pin3_callback(void* arg);    
+#endif
+          
+#ifdef ES_CONF_EXTI_IRQ_4
+void irq_pin4_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_5
+void irq_pin5_callback(void* arg);    
+#endif   
+
+#ifdef ES_CONF_EXTI_IRQ_6
+void irq_pin6_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_7
+void irq_pin7_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_8
+void irq_pin8_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_9
+void irq_pin9_callback(void* arg);    
+#endif   
+
+#ifdef ES_CONF_EXTI_IRQ_10
+void irq_pin10_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_11
+void irq_pin11_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_12
+void irq_pin12_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_13
+void irq_pin13_callback(void* arg);    
+#endif   
+
+#ifdef ES_CONF_EXTI_IRQ_14
+void irq_pin14_callback(void* arg);    
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_15
+void irq_pin15_callback(void* arg);    
+#endif
+
+
+#endif //11111
+
+
+
+
+/*是否有配置的管脚*/
+#if defined(ES_INIT_PIN_GPIO_A_0) || defined(ES_INIT_PIN_GPIO_A_1) || defined(ES_INIT_PIN_GPIO_A_2) || defined(ES_INIT_PIN_GPIO_A_3) || \
+    defined(ES_INIT_PIN_GPIO_A_4) || defined(ES_INIT_PIN_GPIO_A_5) || defined(ES_INIT_PIN_GPIO_A_6) || defined(ES_INIT_PIN_GPIO_A_7) || \
+    defined(ES_INIT_PIN_GPIO_A_8) || defined(ES_INIT_PIN_GPIO_A_9) || defined(ES_INIT_PIN_GPIO_A_10) || defined(ES_INIT_PIN_GPIO_A_11) || \
+    defined(ES_INIT_PIN_GPIO_A_12) || defined(ES_INIT_PIN_GPIO_A_13) || defined(ES_INIT_PIN_GPIO_A_14) || defined(ES_INIT_PIN_GPIO_A_15) || \
+    defined(ES_INIT_PIN_GPIO_B_0) || defined(ES_INIT_PIN_GPIO_B_1) || defined(ES_INIT_PIN_GPIO_B_2) || defined(ES_INIT_PIN_GPIO_B_3) || \
+    defined(ES_INIT_PIN_GPIO_B_4) || defined(ES_INIT_PIN_GPIO_B_5) || defined(ES_INIT_PIN_GPIO_B_6) || defined(ES_INIT_PIN_GPIO_B_7) || \
+    defined(ES_INIT_PIN_GPIO_B_8) || defined(ES_INIT_PIN_GPIO_B_9) || defined(ES_INIT_PIN_GPIO_B_10) || defined(ES_INIT_PIN_GPIO_B_11) || \
+    defined(ES_INIT_PIN_GPIO_B_12) || defined(ES_INIT_PIN_GPIO_B_13) || defined(ES_INIT_PIN_GPIO_B_14) || defined(ES_INIT_PIN_GPIO_B_15) || \
+    defined(ES_INIT_PIN_GPIO_C_0) || defined(ES_INIT_PIN_GPIO_C_1) || defined(ES_INIT_PIN_GPIO_C_2) || defined(ES_INIT_PIN_GPIO_C_3) || \
+    defined(ES_INIT_PIN_GPIO_C_4) || defined(ES_INIT_PIN_GPIO_C_5) || defined(ES_INIT_PIN_GPIO_C_6) || defined(ES_INIT_PIN_GPIO_C_7) || \
+    defined(ES_INIT_PIN_GPIO_C_8) || defined(ES_INIT_PIN_GPIO_C_9) || defined(ES_INIT_PIN_GPIO_C_10) || defined(ES_INIT_PIN_GPIO_C_11) || \
+    defined(ES_INIT_PIN_GPIO_C_12) || defined(ES_INIT_PIN_GPIO_C_13) || defined(ES_INIT_PIN_GPIO_C_14) || defined(ES_INIT_PIN_GPIO_C_15) || \
+    defined(ES_INIT_PIN_GPIO_D_0) || defined(ES_INIT_PIN_GPIO_D_1) || defined(ES_INIT_PIN_GPIO_D_2) || defined(ES_INIT_PIN_GPIO_D_3) || \
+    defined(ES_INIT_PIN_GPIO_D_4) || defined(ES_INIT_PIN_GPIO_D_5) || defined(ES_INIT_PIN_GPIO_D_6) || defined(ES_INIT_PIN_GPIO_D_7) || \
+    defined(ES_INIT_PIN_GPIO_D_8) || defined(ES_INIT_PIN_GPIO_D_9) || defined(ES_INIT_PIN_GPIO_D_10) || defined(ES_INIT_PIN_GPIO_D_11) || \
+    defined(ES_INIT_PIN_GPIO_D_12) || defined(ES_INIT_PIN_GPIO_D_13) || defined(ES_INIT_PIN_GPIO_D_14) || defined(ES_INIT_PIN_GPIO_D_15) || \
+    defined(ES_INIT_PIN_GPIO_E_0) || defined(ES_INIT_PIN_GPIO_E_1) || defined(ES_INIT_PIN_GPIO_E_2) || defined(ES_INIT_PIN_GPIO_E_3) || \
+    defined(ES_INIT_PIN_GPIO_E_4) || defined(ES_INIT_PIN_GPIO_E_5) || defined(ES_INIT_PIN_GPIO_E_6) || defined(ES_INIT_PIN_GPIO_E_7) || \
+    defined(ES_INIT_PIN_GPIO_E_8) || defined(ES_INIT_PIN_GPIO_E_9) || defined(ES_INIT_PIN_GPIO_E_10) || defined(ES_INIT_PIN_GPIO_E_11) || \
+    defined(ES_INIT_PIN_GPIO_E_12) || defined(ES_INIT_PIN_GPIO_E_13) || defined(ES_INIT_PIN_GPIO_E_14) || defined(ES_INIT_PIN_GPIO_E_15) || \
+    defined(ES_INIT_PIN_GPIO_F_0) || defined(ES_INIT_PIN_GPIO_F_1) || defined(ES_INIT_PIN_GPIO_F_2) || defined(ES_INIT_PIN_GPIO_F_3) || \
+    defined(ES_INIT_PIN_GPIO_F_4) || defined(ES_INIT_PIN_GPIO_F_5) || defined(ES_INIT_PIN_GPIO_F_6) || defined(ES_INIT_PIN_GPIO_F_7) || \
+    defined(ES_INIT_PIN_GPIO_F_8) || defined(ES_INIT_PIN_GPIO_F_9) || defined(ES_INIT_PIN_GPIO_F_10) || defined(ES_INIT_PIN_GPIO_F_11) || \
+    defined(ES_INIT_PIN_GPIO_F_12) || defined(ES_INIT_PIN_GPIO_F_13) || defined(ES_INIT_PIN_GPIO_F_14) || defined(ES_INIT_PIN_GPIO_F_15) || \
+    defined(ES_INIT_PIN_GPIO_G_0) || defined(ES_INIT_PIN_GPIO_G_1) || defined(ES_INIT_PIN_GPIO_G_2) || defined(ES_INIT_PIN_GPIO_G_3) || \
+    defined(ES_INIT_PIN_GPIO_G_4) || defined(ES_INIT_PIN_GPIO_G_5) || defined(ES_INIT_PIN_GPIO_G_6) || defined(ES_INIT_PIN_GPIO_G_7) || \
+    defined(ES_INIT_PIN_GPIO_G_8) || defined(ES_INIT_PIN_GPIO_G_9) || defined(ES_INIT_PIN_GPIO_G_10) || defined(ES_INIT_PIN_GPIO_G_11) || \
+    defined(ES_INIT_PIN_GPIO_G_12) || defined(ES_INIT_PIN_GPIO_G_13) || defined(ES_INIT_PIN_GPIO_G_14) || defined(ES_INIT_PIN_GPIO_G_15) || \
+    defined(ES_INIT_PIN_GPIO_H_0) || defined(ES_INIT_PIN_GPIO_H_1) || defined(ES_INIT_PIN_GPIO_H_2) || defined(ES_INIT_PIN_GPIO_H_3) || \
+    defined(ES_INIT_PIN_GPIO_H_4) || defined(ES_INIT_PIN_GPIO_H_5) || defined(ES_INIT_PIN_GPIO_H_6) || defined(ES_INIT_PIN_GPIO_H_7) || \
+    defined(ES_INIT_PIN_GPIO_H_8) || defined(ES_INIT_PIN_GPIO_H_9) || defined(ES_INIT_PIN_GPIO_H_10) || defined(ES_INIT_PIN_GPIO_H_11) || \
+    defined(ES_INIT_PIN_GPIO_H_12) || defined(ES_INIT_PIN_GPIO_H_13) || defined(ES_INIT_PIN_GPIO_H_14) || defined(ES_INIT_PIN_GPIO_H_15)    
+
+#define ES_INIT_GPIOS
+
+#endif
+
+
+#ifdef   ES_INIT_GPIOS
+
+static gpio_conf_t gpio_conf_all[] = 
+{
+ 
+#ifdef  ES_INIT_PIN_GPIO_A_0
+
+    {
+      ES_PIN_GPIO_A_0 ,
+
+#ifdef   ES_INIT_GPIO_A_0_MODE
+      ES_INIT_GPIO_A_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_0_LEVEL
+      ES_INIT_GPIO_A_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_0_IRQ_MODE
+      ES_INIT_GPIO_A_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_1
+
+    {
+      ES_PIN_GPIO_A_1 ,
+
+#ifdef   ES_INIT_GPIO_A_1_MODE
+      ES_INIT_GPIO_A_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_1_LEVEL
+      ES_INIT_GPIO_A_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_1_IRQ_MODE
+      ES_INIT_GPIO_A_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_2
+
+    {
+      ES_PIN_GPIO_A_2 ,
+
+#ifdef   ES_INIT_GPIO_A_2_MODE
+      ES_INIT_GPIO_A_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_2_LEVEL
+      ES_INIT_GPIO_A_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_2_IRQ_MODE
+      ES_INIT_GPIO_A_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_3
+
+    {
+      ES_PIN_GPIO_A_3 ,
+
+#ifdef   ES_INIT_GPIO_A_3_MODE
+      ES_INIT_GPIO_A_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_3_LEVEL
+      ES_INIT_GPIO_A_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_3_IRQ_MODE
+      ES_INIT_GPIO_A_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_4
+
+    {
+      ES_PIN_GPIO_A_4 ,
+
+#ifdef   ES_INIT_GPIO_A_4_MODE
+      ES_INIT_GPIO_A_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_4_LEVEL
+      ES_INIT_GPIO_A_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_4_IRQ_MODE
+      ES_INIT_GPIO_A_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_5
+
+    {
+      ES_PIN_GPIO_A_5 ,
+
+#ifdef   ES_INIT_GPIO_A_5_MODE
+      ES_INIT_GPIO_A_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_5_LEVEL
+      ES_INIT_GPIO_A_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_5_IRQ_MODE
+      ES_INIT_GPIO_A_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_6
+
+    {
+      ES_PIN_GPIO_A_6 ,
+
+#ifdef   ES_INIT_GPIO_A_6_MODE
+      ES_INIT_GPIO_A_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_6_LEVEL
+      ES_INIT_GPIO_A_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_6_IRQ_MODE
+      ES_INIT_GPIO_A_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_7
+
+    {
+      ES_PIN_GPIO_A_7 ,
+
+#ifdef   ES_INIT_GPIO_A_7_MODE
+      ES_INIT_GPIO_A_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_7_LEVEL
+      ES_INIT_GPIO_A_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_7_IRQ_MODE
+      ES_INIT_GPIO_A_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_8
+
+    {
+      ES_PIN_GPIO_A_8 ,
+
+#ifdef   ES_INIT_GPIO_A_8_MODE
+      ES_INIT_GPIO_A_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_8_LEVEL
+      ES_INIT_GPIO_A_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_8_IRQ_MODE
+      ES_INIT_GPIO_A_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_9
+
+    {
+      ES_PIN_GPIO_A_9 ,
+
+#ifdef   ES_INIT_GPIO_A_9_MODE
+      ES_INIT_GPIO_A_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_9_LEVEL
+      ES_INIT_GPIO_A_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_9_IRQ_MODE
+      ES_INIT_GPIO_A_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_10
+
+    {
+      ES_PIN_GPIO_A_10 ,
+
+#ifdef   ES_INIT_GPIO_A_10_MODE
+      ES_INIT_GPIO_A_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_10_LEVEL
+      ES_INIT_GPIO_A_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_10_IRQ_MODE
+      ES_INIT_GPIO_A_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_11
+
+    {
+      ES_PIN_GPIO_A_11 ,
+
+#ifdef   ES_INIT_GPIO_A_11_MODE
+      ES_INIT_GPIO_A_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_11_LEVEL
+      ES_INIT_GPIO_A_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_11_IRQ_MODE
+      ES_INIT_GPIO_A_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_12
+
+    {
+      ES_PIN_GPIO_A_12 ,
+
+#ifdef   ES_INIT_GPIO_A_12_MODE
+      ES_INIT_GPIO_A_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_12_LEVEL
+      ES_INIT_GPIO_A_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_12_IRQ_MODE
+      ES_INIT_GPIO_A_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_13
+
+    {
+      ES_PIN_GPIO_A_13 ,
+
+#ifdef   ES_INIT_GPIO_A_13_MODE
+      ES_INIT_GPIO_A_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_13_LEVEL
+      ES_INIT_GPIO_A_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_13_IRQ_MODE
+      ES_INIT_GPIO_A_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_14
+
+    {
+      ES_PIN_GPIO_A_14 ,
+
+#ifdef   ES_INIT_GPIO_A_14_MODE
+      ES_INIT_GPIO_A_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_14_LEVEL
+      ES_INIT_GPIO_A_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_14_IRQ_MODE
+      ES_INIT_GPIO_A_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_A_15
+
+    {
+      ES_PIN_GPIO_A_15 ,
+
+#ifdef   ES_INIT_GPIO_A_15_MODE
+      ES_INIT_GPIO_A_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_A_15_LEVEL
+      ES_INIT_GPIO_A_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_A_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_A_15_IRQ_MODE
+      ES_INIT_GPIO_A_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_A_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_0
+
+    {
+      ES_PIN_GPIO_B_0 ,
+
+#ifdef   ES_INIT_GPIO_B_0_MODE
+      ES_INIT_GPIO_B_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_0_LEVEL
+      ES_INIT_GPIO_B_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_0_IRQ_MODE
+      ES_INIT_GPIO_B_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_1
+
+    {
+      ES_PIN_GPIO_B_1 ,
+
+#ifdef   ES_INIT_GPIO_B_1_MODE
+      ES_INIT_GPIO_B_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_1_LEVEL
+      ES_INIT_GPIO_B_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_1_IRQ_MODE
+      ES_INIT_GPIO_B_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_2
+
+    {
+      ES_PIN_GPIO_B_2 ,
+
+#ifdef   ES_INIT_GPIO_B_2_MODE
+      ES_INIT_GPIO_B_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_2_LEVEL
+      ES_INIT_GPIO_B_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_2_IRQ_MODE
+      ES_INIT_GPIO_B_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_3
+
+    {
+      ES_PIN_GPIO_B_3 ,
+
+#ifdef   ES_INIT_GPIO_B_3_MODE
+      ES_INIT_GPIO_B_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_3_LEVEL
+      ES_INIT_GPIO_B_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_3_IRQ_MODE
+      ES_INIT_GPIO_B_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_4
+
+    {
+      ES_PIN_GPIO_B_4 ,
+
+#ifdef   ES_INIT_GPIO_B_4_MODE
+      ES_INIT_GPIO_B_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_4_LEVEL
+      ES_INIT_GPIO_B_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_4_IRQ_MODE
+      ES_INIT_GPIO_B_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_5
+
+    {
+      ES_PIN_GPIO_B_5 ,
+
+#ifdef   ES_INIT_GPIO_B_5_MODE
+      ES_INIT_GPIO_B_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_5_LEVEL
+      ES_INIT_GPIO_B_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_5_IRQ_MODE
+      ES_INIT_GPIO_B_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_6
+
+    {
+      ES_PIN_GPIO_B_6 ,
+
+#ifdef   ES_INIT_GPIO_B_6_MODE
+      ES_INIT_GPIO_B_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_6_LEVEL
+      ES_INIT_GPIO_B_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_6_IRQ_MODE
+      ES_INIT_GPIO_B_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_7
+
+    {
+      ES_PIN_GPIO_B_7 ,
+
+#ifdef   ES_INIT_GPIO_B_7_MODE
+      ES_INIT_GPIO_B_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_7_LEVEL
+      ES_INIT_GPIO_B_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_7_IRQ_MODE
+      ES_INIT_GPIO_B_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_8
+
+    {
+      ES_PIN_GPIO_B_8 ,
+
+#ifdef   ES_INIT_GPIO_B_8_MODE
+      ES_INIT_GPIO_B_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_8_LEVEL
+      ES_INIT_GPIO_B_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_8_IRQ_MODE
+      ES_INIT_GPIO_B_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_9
+
+    {
+      ES_PIN_GPIO_B_9 ,
+
+#ifdef   ES_INIT_GPIO_B_9_MODE
+      ES_INIT_GPIO_B_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_9_LEVEL
+      ES_INIT_GPIO_B_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_9_IRQ_MODE
+      ES_INIT_GPIO_B_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_10
+
+    {
+      ES_PIN_GPIO_B_10 ,
+
+#ifdef   ES_INIT_GPIO_B_10_MODE
+      ES_INIT_GPIO_B_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_10_LEVEL
+      ES_INIT_GPIO_B_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_10_IRQ_MODE
+      ES_INIT_GPIO_B_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_11
+
+    {
+      ES_PIN_GPIO_B_11 ,
+
+#ifdef   ES_INIT_GPIO_B_11_MODE
+      ES_INIT_GPIO_B_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_11_LEVEL
+      ES_INIT_GPIO_B_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_11_IRQ_MODE
+      ES_INIT_GPIO_B_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_12
+
+    {
+      ES_PIN_GPIO_B_12 ,
+
+#ifdef   ES_INIT_GPIO_B_12_MODE
+      ES_INIT_GPIO_B_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_12_LEVEL
+      ES_INIT_GPIO_B_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_12_IRQ_MODE
+      ES_INIT_GPIO_B_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_13
+
+    {
+      ES_PIN_GPIO_B_13 ,
+
+#ifdef   ES_INIT_GPIO_B_13_MODE
+      ES_INIT_GPIO_B_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_13_LEVEL
+      ES_INIT_GPIO_B_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_13_IRQ_MODE
+      ES_INIT_GPIO_B_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_14
+
+    {
+      ES_PIN_GPIO_B_14 ,
+
+#ifdef   ES_INIT_GPIO_B_14_MODE
+      ES_INIT_GPIO_B_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_14_LEVEL
+      ES_INIT_GPIO_B_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_14_IRQ_MODE
+      ES_INIT_GPIO_B_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_B_15
+
+    {
+      ES_PIN_GPIO_B_15 ,
+
+#ifdef   ES_INIT_GPIO_B_15_MODE
+      ES_INIT_GPIO_B_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_B_15_LEVEL
+      ES_INIT_GPIO_B_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_B_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_B_15_IRQ_MODE
+      ES_INIT_GPIO_B_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_B_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_0
+
+    {
+      ES_PIN_GPIO_C_0 ,
+
+#ifdef   ES_INIT_GPIO_C_0_MODE
+      ES_INIT_GPIO_C_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_0_LEVEL
+      ES_INIT_GPIO_C_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_0_IRQ_MODE
+      ES_INIT_GPIO_C_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_1
+
+    {
+      ES_PIN_GPIO_C_1 ,
+
+#ifdef   ES_INIT_GPIO_C_1_MODE
+      ES_INIT_GPIO_C_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_1_LEVEL
+      ES_INIT_GPIO_C_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_1_IRQ_MODE
+      ES_INIT_GPIO_C_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_2
+
+    {
+      ES_PIN_GPIO_C_2 ,
+
+#ifdef   ES_INIT_GPIO_C_2_MODE
+      ES_INIT_GPIO_C_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_2_LEVEL
+      ES_INIT_GPIO_C_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_2_IRQ_MODE
+      ES_INIT_GPIO_C_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_3
+
+    {
+      ES_PIN_GPIO_C_3 ,
+
+#ifdef   ES_INIT_GPIO_C_3_MODE
+      ES_INIT_GPIO_C_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_3_LEVEL
+      ES_INIT_GPIO_C_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_3_IRQ_MODE
+      ES_INIT_GPIO_C_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_4
+
+    {
+      ES_PIN_GPIO_C_4 ,
+
+#ifdef   ES_INIT_GPIO_C_4_MODE
+      ES_INIT_GPIO_C_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_4_LEVEL
+      ES_INIT_GPIO_C_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_4_IRQ_MODE
+      ES_INIT_GPIO_C_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_5
+
+    {
+      ES_PIN_GPIO_C_5 ,
+
+#ifdef   ES_INIT_GPIO_C_5_MODE
+      ES_INIT_GPIO_C_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_5_LEVEL
+      ES_INIT_GPIO_C_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_5_IRQ_MODE
+      ES_INIT_GPIO_C_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_6
+
+    {
+      ES_PIN_GPIO_C_6 ,
+
+#ifdef   ES_INIT_GPIO_C_6_MODE
+      ES_INIT_GPIO_C_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_6_LEVEL
+      ES_INIT_GPIO_C_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_6_IRQ_MODE
+      ES_INIT_GPIO_C_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_7
+
+    {
+      ES_PIN_GPIO_C_7 ,
+
+#ifdef   ES_INIT_GPIO_C_7_MODE
+      ES_INIT_GPIO_C_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_7_LEVEL
+      ES_INIT_GPIO_C_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_7_IRQ_MODE
+      ES_INIT_GPIO_C_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_8
+
+    {
+      ES_PIN_GPIO_C_8 ,
+
+#ifdef   ES_INIT_GPIO_C_8_MODE
+      ES_INIT_GPIO_C_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_8_LEVEL
+      ES_INIT_GPIO_C_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_8_IRQ_MODE
+      ES_INIT_GPIO_C_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_9
+
+    {
+      ES_PIN_GPIO_C_9 ,
+
+#ifdef   ES_INIT_GPIO_C_9_MODE
+      ES_INIT_GPIO_C_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_9_LEVEL
+      ES_INIT_GPIO_C_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_9_IRQ_MODE
+      ES_INIT_GPIO_C_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_10
+
+    {
+      ES_PIN_GPIO_C_10 ,
+
+#ifdef   ES_INIT_GPIO_C_10_MODE
+      ES_INIT_GPIO_C_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_10_LEVEL
+      ES_INIT_GPIO_C_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_10_IRQ_MODE
+      ES_INIT_GPIO_C_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_11
+
+    {
+      ES_PIN_GPIO_C_11 ,
+
+#ifdef   ES_INIT_GPIO_C_11_MODE
+      ES_INIT_GPIO_C_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_11_LEVEL
+      ES_INIT_GPIO_C_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_11_IRQ_MODE
+      ES_INIT_GPIO_C_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_12
+
+    {
+      ES_PIN_GPIO_C_12 ,
+
+#ifdef   ES_INIT_GPIO_C_12_MODE
+      ES_INIT_GPIO_C_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_12_LEVEL
+      ES_INIT_GPIO_C_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_12_IRQ_MODE
+      ES_INIT_GPIO_C_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_13
+
+    {
+      ES_PIN_GPIO_C_13 ,
+
+#ifdef   ES_INIT_GPIO_C_13_MODE
+      ES_INIT_GPIO_C_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_13_LEVEL
+      ES_INIT_GPIO_C_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_13_IRQ_MODE
+      ES_INIT_GPIO_C_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_14
+
+    {
+      ES_PIN_GPIO_C_14 ,
+
+#ifdef   ES_INIT_GPIO_C_14_MODE
+      ES_INIT_GPIO_C_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_14_LEVEL
+      ES_INIT_GPIO_C_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_14_IRQ_MODE
+      ES_INIT_GPIO_C_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_C_15
+
+    {
+      ES_PIN_GPIO_C_15 ,
+
+#ifdef   ES_INIT_GPIO_C_15_MODE
+      ES_INIT_GPIO_C_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_C_15_LEVEL
+      ES_INIT_GPIO_C_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_C_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_C_15_IRQ_MODE
+      ES_INIT_GPIO_C_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_C_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_0
+
+    {
+      ES_PIN_GPIO_D_0 ,
+
+#ifdef   ES_INIT_GPIO_D_0_MODE
+      ES_INIT_GPIO_D_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_0_LEVEL
+      ES_INIT_GPIO_D_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_0_IRQ_MODE
+      ES_INIT_GPIO_D_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_1
+
+    {
+      ES_PIN_GPIO_D_1 ,
+
+#ifdef   ES_INIT_GPIO_D_1_MODE
+      ES_INIT_GPIO_D_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_1_LEVEL
+      ES_INIT_GPIO_D_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_1_IRQ_MODE
+      ES_INIT_GPIO_D_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_2
+
+    {
+      ES_PIN_GPIO_D_2 ,
+
+#ifdef   ES_INIT_GPIO_D_2_MODE
+      ES_INIT_GPIO_D_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_2_LEVEL
+      ES_INIT_GPIO_D_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_2_IRQ_MODE
+      ES_INIT_GPIO_D_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_3
+
+    {
+      ES_PIN_GPIO_D_3 ,
+
+#ifdef   ES_INIT_GPIO_D_3_MODE
+      ES_INIT_GPIO_D_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_3_LEVEL
+      ES_INIT_GPIO_D_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_3_IRQ_MODE
+      ES_INIT_GPIO_D_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_4
+
+    {
+      ES_PIN_GPIO_D_4 ,
+
+#ifdef   ES_INIT_GPIO_D_4_MODE
+      ES_INIT_GPIO_D_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_4_LEVEL
+      ES_INIT_GPIO_D_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_4_IRQ_MODE
+      ES_INIT_GPIO_D_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_5
+
+    {
+      ES_PIN_GPIO_D_5 ,
+
+#ifdef   ES_INIT_GPIO_D_5_MODE
+      ES_INIT_GPIO_D_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_5_LEVEL
+      ES_INIT_GPIO_D_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_5_IRQ_MODE
+      ES_INIT_GPIO_D_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_6
+
+    {
+      ES_PIN_GPIO_D_6 ,
+
+#ifdef   ES_INIT_GPIO_D_6_MODE
+      ES_INIT_GPIO_D_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_6_LEVEL
+      ES_INIT_GPIO_D_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_6_IRQ_MODE
+      ES_INIT_GPIO_D_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_7
+
+    {
+      ES_PIN_GPIO_D_7 ,
+
+#ifdef   ES_INIT_GPIO_D_7_MODE
+      ES_INIT_GPIO_D_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_7_LEVEL
+      ES_INIT_GPIO_D_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_7_IRQ_MODE
+      ES_INIT_GPIO_D_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_8
+
+    {
+      ES_PIN_GPIO_D_8 ,
+
+#ifdef   ES_INIT_GPIO_D_8_MODE
+      ES_INIT_GPIO_D_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_8_LEVEL
+      ES_INIT_GPIO_D_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_8_IRQ_MODE
+      ES_INIT_GPIO_D_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_9
+
+    {
+      ES_PIN_GPIO_D_9 ,
+
+#ifdef   ES_INIT_GPIO_D_9_MODE
+      ES_INIT_GPIO_D_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_9_LEVEL
+      ES_INIT_GPIO_D_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_9_IRQ_MODE
+      ES_INIT_GPIO_D_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_10
+
+    {
+      ES_PIN_GPIO_D_10 ,
+
+#ifdef   ES_INIT_GPIO_D_10_MODE
+      ES_INIT_GPIO_D_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_10_LEVEL
+      ES_INIT_GPIO_D_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_10_IRQ_MODE
+      ES_INIT_GPIO_D_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_11
+
+    {
+      ES_PIN_GPIO_D_11 ,
+
+#ifdef   ES_INIT_GPIO_D_11_MODE
+      ES_INIT_GPIO_D_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_11_LEVEL
+      ES_INIT_GPIO_D_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_11_IRQ_MODE
+      ES_INIT_GPIO_D_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_12
+
+    {
+      ES_PIN_GPIO_D_12 ,
+
+#ifdef   ES_INIT_GPIO_D_12_MODE
+      ES_INIT_GPIO_D_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_12_LEVEL
+      ES_INIT_GPIO_D_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_12_IRQ_MODE
+      ES_INIT_GPIO_D_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_13
+
+    {
+      ES_PIN_GPIO_D_13 ,
+
+#ifdef   ES_INIT_GPIO_D_13_MODE
+      ES_INIT_GPIO_D_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_13_LEVEL
+      ES_INIT_GPIO_D_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_13_IRQ_MODE
+      ES_INIT_GPIO_D_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_14
+
+    {
+      ES_PIN_GPIO_D_14 ,
+
+#ifdef   ES_INIT_GPIO_D_14_MODE
+      ES_INIT_GPIO_D_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_14_LEVEL
+      ES_INIT_GPIO_D_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_14_IRQ_MODE
+      ES_INIT_GPIO_D_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_D_15
+
+    {
+      ES_PIN_GPIO_D_15 ,
+
+#ifdef   ES_INIT_GPIO_D_15_MODE
+      ES_INIT_GPIO_D_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_D_15_LEVEL
+      ES_INIT_GPIO_D_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_D_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_D_15_IRQ_MODE
+      ES_INIT_GPIO_D_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_D_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_0
+
+    {
+      ES_PIN_GPIO_E_0 ,
+
+#ifdef   ES_INIT_GPIO_E_0_MODE
+      ES_INIT_GPIO_E_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_0_LEVEL
+      ES_INIT_GPIO_E_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_0_IRQ_MODE
+      ES_INIT_GPIO_E_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_1
+
+    {
+      ES_PIN_GPIO_E_1 ,
+
+#ifdef   ES_INIT_GPIO_E_1_MODE
+      ES_INIT_GPIO_E_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_1_LEVEL
+      ES_INIT_GPIO_E_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_1_IRQ_MODE
+      ES_INIT_GPIO_E_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_2
+
+    {
+      ES_PIN_GPIO_E_2 ,
+
+#ifdef   ES_INIT_GPIO_E_2_MODE
+      ES_INIT_GPIO_E_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_2_LEVEL
+      ES_INIT_GPIO_E_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_2_IRQ_MODE
+      ES_INIT_GPIO_E_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_3
+
+    {
+      ES_PIN_GPIO_E_3 ,
+
+#ifdef   ES_INIT_GPIO_E_3_MODE
+      ES_INIT_GPIO_E_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_3_LEVEL
+      ES_INIT_GPIO_E_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_3_IRQ_MODE
+      ES_INIT_GPIO_E_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_4
+
+    {
+      ES_PIN_GPIO_E_4 ,
+
+#ifdef   ES_INIT_GPIO_E_4_MODE
+      ES_INIT_GPIO_E_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_4_LEVEL
+      ES_INIT_GPIO_E_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_4_IRQ_MODE
+      ES_INIT_GPIO_E_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_5
+
+    {
+      ES_PIN_GPIO_E_5 ,
+
+#ifdef   ES_INIT_GPIO_E_5_MODE
+      ES_INIT_GPIO_E_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_5_LEVEL
+      ES_INIT_GPIO_E_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_5_IRQ_MODE
+      ES_INIT_GPIO_E_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_6
+
+    {
+      ES_PIN_GPIO_E_6 ,
+
+#ifdef   ES_INIT_GPIO_E_6_MODE
+      ES_INIT_GPIO_E_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_6_LEVEL
+      ES_INIT_GPIO_E_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_6_IRQ_MODE
+      ES_INIT_GPIO_E_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_7
+
+    {
+      ES_PIN_GPIO_E_7 ,
+
+#ifdef   ES_INIT_GPIO_E_7_MODE
+      ES_INIT_GPIO_E_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_7_LEVEL
+      ES_INIT_GPIO_E_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_7_IRQ_MODE
+      ES_INIT_GPIO_E_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_8
+
+    {
+      ES_PIN_GPIO_E_8 ,
+
+#ifdef   ES_INIT_GPIO_E_8_MODE
+      ES_INIT_GPIO_E_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_8_LEVEL
+      ES_INIT_GPIO_E_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_8_IRQ_MODE
+      ES_INIT_GPIO_E_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_9
+
+    {
+      ES_PIN_GPIO_E_9 ,
+
+#ifdef   ES_INIT_GPIO_E_9_MODE
+      ES_INIT_GPIO_E_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_9_LEVEL
+      ES_INIT_GPIO_E_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_9_IRQ_MODE
+      ES_INIT_GPIO_E_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_10
+
+    {
+      ES_PIN_GPIO_E_10 ,
+
+#ifdef   ES_INIT_GPIO_E_10_MODE
+      ES_INIT_GPIO_E_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_10_LEVEL
+      ES_INIT_GPIO_E_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_10_IRQ_MODE
+      ES_INIT_GPIO_E_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_11
+
+    {
+      ES_PIN_GPIO_E_11 ,
+
+#ifdef   ES_INIT_GPIO_E_11_MODE
+      ES_INIT_GPIO_E_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_11_LEVEL
+      ES_INIT_GPIO_E_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_11_IRQ_MODE
+      ES_INIT_GPIO_E_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_12
+
+    {
+      ES_PIN_GPIO_E_12 ,
+
+#ifdef   ES_INIT_GPIO_E_12_MODE
+      ES_INIT_GPIO_E_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_12_LEVEL
+      ES_INIT_GPIO_E_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_12_IRQ_MODE
+      ES_INIT_GPIO_E_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_13
+
+    {
+      ES_PIN_GPIO_E_13 ,
+
+#ifdef   ES_INIT_GPIO_E_13_MODE
+      ES_INIT_GPIO_E_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_13_LEVEL
+      ES_INIT_GPIO_E_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_13_IRQ_MODE
+      ES_INIT_GPIO_E_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_14
+
+    {
+      ES_PIN_GPIO_E_14 ,
+
+#ifdef   ES_INIT_GPIO_E_14_MODE
+      ES_INIT_GPIO_E_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_14_LEVEL
+      ES_INIT_GPIO_E_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_14_IRQ_MODE
+      ES_INIT_GPIO_E_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_E_15
+
+    {
+      ES_PIN_GPIO_E_15 ,
+
+#ifdef   ES_INIT_GPIO_E_15_MODE
+      ES_INIT_GPIO_E_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_E_15_LEVEL
+      ES_INIT_GPIO_E_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_E_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_E_15_IRQ_MODE
+      ES_INIT_GPIO_E_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_E_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_0
+
+    {
+      ES_PIN_GPIO_F_0 ,
+
+#ifdef   ES_INIT_GPIO_F_0_MODE
+      ES_INIT_GPIO_F_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_0_LEVEL
+      ES_INIT_GPIO_F_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_0_IRQ_MODE
+      ES_INIT_GPIO_F_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_1
+
+    {
+      ES_PIN_GPIO_F_1 ,
+
+#ifdef   ES_INIT_GPIO_F_1_MODE
+      ES_INIT_GPIO_F_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_1_LEVEL
+      ES_INIT_GPIO_F_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_1_IRQ_MODE
+      ES_INIT_GPIO_F_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_2
+
+    {
+      ES_PIN_GPIO_F_2 ,
+
+#ifdef   ES_INIT_GPIO_F_2_MODE
+      ES_INIT_GPIO_F_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_2_LEVEL
+      ES_INIT_GPIO_F_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_2_IRQ_MODE
+      ES_INIT_GPIO_F_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_3
+
+    {
+      ES_PIN_GPIO_F_3 ,
+
+#ifdef   ES_INIT_GPIO_F_3_MODE
+      ES_INIT_GPIO_F_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_3_LEVEL
+      ES_INIT_GPIO_F_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_3_IRQ_MODE
+      ES_INIT_GPIO_F_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_4
+
+    {
+      ES_PIN_GPIO_F_4 ,
+
+#ifdef   ES_INIT_GPIO_F_4_MODE
+      ES_INIT_GPIO_F_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_4_LEVEL
+      ES_INIT_GPIO_F_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_4_IRQ_MODE
+      ES_INIT_GPIO_F_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_5
+
+    {
+      ES_PIN_GPIO_F_5 ,
+
+#ifdef   ES_INIT_GPIO_F_5_MODE
+      ES_INIT_GPIO_F_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_5_LEVEL
+      ES_INIT_GPIO_F_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_5_IRQ_MODE
+      ES_INIT_GPIO_F_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_6
+
+    {
+      ES_PIN_GPIO_F_6 ,
+
+#ifdef   ES_INIT_GPIO_F_6_MODE
+      ES_INIT_GPIO_F_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_6_LEVEL
+      ES_INIT_GPIO_F_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_6_IRQ_MODE
+      ES_INIT_GPIO_F_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_7
+
+    {
+      ES_PIN_GPIO_F_7 ,
+
+#ifdef   ES_INIT_GPIO_F_7_MODE
+      ES_INIT_GPIO_F_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_7_LEVEL
+      ES_INIT_GPIO_F_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_7_IRQ_MODE
+      ES_INIT_GPIO_F_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_8
+
+    {
+      ES_PIN_GPIO_F_8 ,
+
+#ifdef   ES_INIT_GPIO_F_8_MODE
+      ES_INIT_GPIO_F_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_8_LEVEL
+      ES_INIT_GPIO_F_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_8_IRQ_MODE
+      ES_INIT_GPIO_F_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_9
+
+    {
+      ES_PIN_GPIO_F_9 ,
+
+#ifdef   ES_INIT_GPIO_F_9_MODE
+      ES_INIT_GPIO_F_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_9_LEVEL
+      ES_INIT_GPIO_F_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_9_IRQ_MODE
+      ES_INIT_GPIO_F_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_10
+
+    {
+      ES_PIN_GPIO_F_10 ,
+
+#ifdef   ES_INIT_GPIO_F_10_MODE
+      ES_INIT_GPIO_F_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_10_LEVEL
+      ES_INIT_GPIO_F_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_10_IRQ_MODE
+      ES_INIT_GPIO_F_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_11
+
+    {
+      ES_PIN_GPIO_F_11 ,
+
+#ifdef   ES_INIT_GPIO_F_11_MODE
+      ES_INIT_GPIO_F_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_11_LEVEL
+      ES_INIT_GPIO_F_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_11_IRQ_MODE
+      ES_INIT_GPIO_F_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_12
+
+    {
+      ES_PIN_GPIO_F_12 ,
+
+#ifdef   ES_INIT_GPIO_F_12_MODE
+      ES_INIT_GPIO_F_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_12_LEVEL
+      ES_INIT_GPIO_F_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_12_IRQ_MODE
+      ES_INIT_GPIO_F_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_13
+
+    {
+      ES_PIN_GPIO_F_13 ,
+
+#ifdef   ES_INIT_GPIO_F_13_MODE
+      ES_INIT_GPIO_F_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_13_LEVEL
+      ES_INIT_GPIO_F_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_13_IRQ_MODE
+      ES_INIT_GPIO_F_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_14
+
+    {
+      ES_PIN_GPIO_F_14 ,
+
+#ifdef   ES_INIT_GPIO_F_14_MODE
+      ES_INIT_GPIO_F_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_14_LEVEL
+      ES_INIT_GPIO_F_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_14_IRQ_MODE
+      ES_INIT_GPIO_F_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_F_15
+
+    {
+      ES_PIN_GPIO_F_15 ,
+
+#ifdef   ES_INIT_GPIO_F_15_MODE
+      ES_INIT_GPIO_F_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_F_15_LEVEL
+      ES_INIT_GPIO_F_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_F_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_F_15_IRQ_MODE
+      ES_INIT_GPIO_F_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_F_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_0
+
+    {
+      ES_PIN_GPIO_G_0 ,
+
+#ifdef   ES_INIT_GPIO_G_0_MODE
+      ES_INIT_GPIO_G_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_0_LEVEL
+      ES_INIT_GPIO_G_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_0_IRQ_MODE
+      ES_INIT_GPIO_G_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_1
+
+    {
+      ES_PIN_GPIO_G_1 ,
+
+#ifdef   ES_INIT_GPIO_G_1_MODE
+      ES_INIT_GPIO_G_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_1_LEVEL
+      ES_INIT_GPIO_G_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_1_IRQ_MODE
+      ES_INIT_GPIO_G_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_2
+
+    {
+      ES_PIN_GPIO_G_2 ,
+
+#ifdef   ES_INIT_GPIO_G_2_MODE
+      ES_INIT_GPIO_G_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_2_LEVEL
+      ES_INIT_GPIO_G_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_2_IRQ_MODE
+      ES_INIT_GPIO_G_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_3
+
+    {
+      ES_PIN_GPIO_G_3 ,
+
+#ifdef   ES_INIT_GPIO_G_3_MODE
+      ES_INIT_GPIO_G_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_3_LEVEL
+      ES_INIT_GPIO_G_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_3_IRQ_MODE
+      ES_INIT_GPIO_G_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_4
+
+    {
+      ES_PIN_GPIO_G_4 ,
+
+#ifdef   ES_INIT_GPIO_G_4_MODE
+      ES_INIT_GPIO_G_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_4_LEVEL
+      ES_INIT_GPIO_G_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_4_IRQ_MODE
+      ES_INIT_GPIO_G_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_5
+
+    {
+      ES_PIN_GPIO_G_5 ,
+
+#ifdef   ES_INIT_GPIO_G_5_MODE
+      ES_INIT_GPIO_G_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_5_LEVEL
+      ES_INIT_GPIO_G_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_5_IRQ_MODE
+      ES_INIT_GPIO_G_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_6
+
+    {
+      ES_PIN_GPIO_G_6 ,
+
+#ifdef   ES_INIT_GPIO_G_6_MODE
+      ES_INIT_GPIO_G_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_6_LEVEL
+      ES_INIT_GPIO_G_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_6_IRQ_MODE
+      ES_INIT_GPIO_G_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_7
+
+    {
+      ES_PIN_GPIO_G_7 ,
+
+#ifdef   ES_INIT_GPIO_G_7_MODE
+      ES_INIT_GPIO_G_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_7_LEVEL
+      ES_INIT_GPIO_G_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_7_IRQ_MODE
+      ES_INIT_GPIO_G_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_8
+
+    {
+      ES_PIN_GPIO_G_8 ,
+
+#ifdef   ES_INIT_GPIO_G_8_MODE
+      ES_INIT_GPIO_G_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_8_LEVEL
+      ES_INIT_GPIO_G_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_8_IRQ_MODE
+      ES_INIT_GPIO_G_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_9
+
+    {
+      ES_PIN_GPIO_G_9 ,
+
+#ifdef   ES_INIT_GPIO_G_9_MODE
+      ES_INIT_GPIO_G_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_9_LEVEL
+      ES_INIT_GPIO_G_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_9_IRQ_MODE
+      ES_INIT_GPIO_G_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_10
+
+    {
+      ES_PIN_GPIO_G_10 ,
+
+#ifdef   ES_INIT_GPIO_G_10_MODE
+      ES_INIT_GPIO_G_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_10_LEVEL
+      ES_INIT_GPIO_G_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_10_IRQ_MODE
+      ES_INIT_GPIO_G_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_11
+
+    {
+      ES_PIN_GPIO_G_11 ,
+
+#ifdef   ES_INIT_GPIO_G_11_MODE
+      ES_INIT_GPIO_G_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_11_LEVEL
+      ES_INIT_GPIO_G_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_11_IRQ_MODE
+      ES_INIT_GPIO_G_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_12
+
+    {
+      ES_PIN_GPIO_G_12 ,
+
+#ifdef   ES_INIT_GPIO_G_12_MODE
+      ES_INIT_GPIO_G_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_12_LEVEL
+      ES_INIT_GPIO_G_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_12_IRQ_MODE
+      ES_INIT_GPIO_G_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_13
+
+    {
+      ES_PIN_GPIO_G_13 ,
+
+#ifdef   ES_INIT_GPIO_G_13_MODE
+      ES_INIT_GPIO_G_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_13_LEVEL
+      ES_INIT_GPIO_G_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_13_IRQ_MODE
+      ES_INIT_GPIO_G_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_14
+
+    {
+      ES_PIN_GPIO_G_14 ,
+
+#ifdef   ES_INIT_GPIO_G_14_MODE
+      ES_INIT_GPIO_G_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_14_LEVEL
+      ES_INIT_GPIO_G_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_14_IRQ_MODE
+      ES_INIT_GPIO_G_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_G_15
+
+    {
+      ES_PIN_GPIO_G_15 ,
+
+#ifdef   ES_INIT_GPIO_G_15_MODE
+      ES_INIT_GPIO_G_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_G_15_LEVEL
+      ES_INIT_GPIO_G_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_G_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_G_15_IRQ_MODE
+      ES_INIT_GPIO_G_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_G_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_0
+
+    {
+      ES_PIN_GPIO_H_0 ,
+
+#ifdef   ES_INIT_GPIO_H_0_MODE
+      ES_INIT_GPIO_H_0_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_0_LEVEL
+      ES_INIT_GPIO_H_0_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_0_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_0_IRQ_MODE
+      ES_INIT_GPIO_H_0_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_0_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin0_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_1
+
+    {
+      ES_PIN_GPIO_H_1 ,
+
+#ifdef   ES_INIT_GPIO_H_1_MODE
+      ES_INIT_GPIO_H_1_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_1_LEVEL
+      ES_INIT_GPIO_H_1_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_1_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_1_IRQ_MODE
+      ES_INIT_GPIO_H_1_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_1_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin1_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_2
+
+    {
+      ES_PIN_GPIO_H_2 ,
+
+#ifdef   ES_INIT_GPIO_H_2_MODE
+      ES_INIT_GPIO_H_2_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_2_LEVEL
+      ES_INIT_GPIO_H_2_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_2_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_2_IRQ_MODE
+      ES_INIT_GPIO_H_2_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_2_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin2_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_3
+
+    {
+      ES_PIN_GPIO_H_3 ,
+
+#ifdef   ES_INIT_GPIO_H_3_MODE
+      ES_INIT_GPIO_H_3_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_3_LEVEL
+      ES_INIT_GPIO_H_3_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_3_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_3_IRQ_MODE
+      ES_INIT_GPIO_H_3_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_3_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin3_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_4
+
+    {
+      ES_PIN_GPIO_H_4 ,
+
+#ifdef   ES_INIT_GPIO_H_4_MODE
+      ES_INIT_GPIO_H_4_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_4_LEVEL
+      ES_INIT_GPIO_H_4_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_4_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_4_IRQ_MODE
+      ES_INIT_GPIO_H_4_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_4_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin4_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_5
+
+    {
+      ES_PIN_GPIO_H_5 ,
+
+#ifdef   ES_INIT_GPIO_H_5_MODE
+      ES_INIT_GPIO_H_5_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_5_LEVEL
+      ES_INIT_GPIO_H_5_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_5_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_5_IRQ_MODE
+      ES_INIT_GPIO_H_5_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_5_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin5_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_6
+
+    {
+      ES_PIN_GPIO_H_6 ,
+
+#ifdef   ES_INIT_GPIO_H_6_MODE
+      ES_INIT_GPIO_H_6_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_6_LEVEL
+      ES_INIT_GPIO_H_6_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_6_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_6_IRQ_MODE
+      ES_INIT_GPIO_H_6_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_6_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin6_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_7
+
+    {
+      ES_PIN_GPIO_H_7 ,
+
+#ifdef   ES_INIT_GPIO_H_7_MODE
+      ES_INIT_GPIO_H_7_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_7_LEVEL
+      ES_INIT_GPIO_H_7_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_7_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_7_IRQ_MODE
+      ES_INIT_GPIO_H_7_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_7_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin7_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_8
+
+    {
+      ES_PIN_GPIO_H_8 ,
+
+#ifdef   ES_INIT_GPIO_H_8_MODE
+      ES_INIT_GPIO_H_8_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_8_LEVEL
+      ES_INIT_GPIO_H_8_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_8_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_8_IRQ_MODE
+      ES_INIT_GPIO_H_8_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_8_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin8_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_9
+
+    {
+      ES_PIN_GPIO_H_9 ,
+
+#ifdef   ES_INIT_GPIO_H_9_MODE
+      ES_INIT_GPIO_H_9_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_9_LEVEL
+      ES_INIT_GPIO_H_9_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_9_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_9_IRQ_MODE
+      ES_INIT_GPIO_H_9_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_9_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin9_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_10
+
+    {
+      ES_PIN_GPIO_H_10 ,
+
+#ifdef   ES_INIT_GPIO_H_10_MODE
+      ES_INIT_GPIO_H_10_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_10_LEVEL
+      ES_INIT_GPIO_H_10_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_10_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_10_IRQ_MODE
+      ES_INIT_GPIO_H_10_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_10_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin10_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_11
+
+    {
+      ES_PIN_GPIO_H_11 ,
+
+#ifdef   ES_INIT_GPIO_H_11_MODE
+      ES_INIT_GPIO_H_11_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_11_LEVEL
+      ES_INIT_GPIO_H_11_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_11_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_11_IRQ_MODE
+      ES_INIT_GPIO_H_11_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_11_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin11_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_12
+
+    {
+      ES_PIN_GPIO_H_12 ,
+
+#ifdef   ES_INIT_GPIO_H_12_MODE
+      ES_INIT_GPIO_H_12_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_12_LEVEL
+      ES_INIT_GPIO_H_12_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_12_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_12_IRQ_MODE
+      ES_INIT_GPIO_H_12_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_12_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin12_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_13
+
+    {
+      ES_PIN_GPIO_H_13 ,
+
+#ifdef   ES_INIT_GPIO_H_13_MODE
+      ES_INIT_GPIO_H_13_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_13_LEVEL
+      ES_INIT_GPIO_H_13_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_13_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_13_IRQ_MODE
+      ES_INIT_GPIO_H_13_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_13_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin13_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_14
+
+    {
+      ES_PIN_GPIO_H_14 ,
+
+#ifdef   ES_INIT_GPIO_H_14_MODE
+      ES_INIT_GPIO_H_14_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_14_LEVEL
+      ES_INIT_GPIO_H_14_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_14_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_14_IRQ_MODE
+      ES_INIT_GPIO_H_14_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_14_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin14_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+#ifdef  ES_INIT_PIN_GPIO_H_15
+
+    {
+      ES_PIN_GPIO_H_15 ,
+
+#ifdef   ES_INIT_GPIO_H_15_MODE
+      ES_INIT_GPIO_H_15_MODE ,
+#else
+     ES_C_GPIO_MODE_OUTPUT ,
+#endif
+
+#ifdef   ES_INIT_GPIO_H_15_LEVEL
+      ES_INIT_GPIO_H_15_LEVEL ,
+#else
+     ES_C_GPIO_LEVEL_HIGH ,
+#endif
+
+      ES_INIT_GPIO_H_15_IRQ_EN ,
+
+#ifdef   ES_INIT_GPIO_H_15_IRQ_MODE
+      ES_INIT_GPIO_H_15_IRQ_MODE ,
+#else
+     ES_C_GPIO_IRQ_MODE_RISE ,
+#endif
+
+#if (ES_INIT_GPIO_H_15_IRQ_EN == ES_C_GPIO_IRQ_ENABLE)
+      irq_pin15_callback ,
+#else
+     RT_NULL ,
+#endif
+    },
+
+#endif
+
+ 
+
+};    
+
+#endif    
+    
+ 
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_hwtimer.h

@@ -0,0 +1,103 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_HWTIMER_H__
+#define __ES_CONF_INFO_HWTIMER_H__
+
+#include <ald_cmu.h>
+#include <ald_timer.h>
+
+#define ES_C_HWTIMER_MODE_UP         HWTIMER_CNTMODE_UP  
+#define ES_C_HWTIMER_MODE_DOWN         HWTIMER_CNTMODE_DW
+
+/* HWTIMER 配置 */
+
+/* codes_main */
+
+
+
+#ifndef  ES_AD16C4T0_HWTIMER_MODE
+#define ES_AD16C4T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif    
+
+#ifndef  ES_GP16C4T0_HWTIMER_MODE
+#define ES_GP16C4T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+#ifndef  ES_GP16C2T0_HWTIMER_MODE
+#define ES_GP16C2T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+#ifndef  ES_GP1624T1_HWTIMER_MODE
+#define ES_GP16C2T1_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+#ifndef  ES_BS16T0_HWTIMER_MODE
+#define ES_BS16T0_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+#ifndef  ES_BS16T1_HWTIMER_MODE
+#define ES_BS16T1_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+#ifndef  ES_BS16T2_HWTIMER_MODE
+#define ES_BS16T2_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+#ifndef  ES_BS16T3_HWTIMER_MODE
+#define ES_BS16T3_HWTIMER_MODE          ES_C_HWTIMER_MODE_UP  
+#endif
+
+
+
+         
+#define ES_AD16C4T0_HWTIMER_PRES          1 
+#define ES_GP16C4T0_HWTIMER_PRES          1
+#define ES_GP16C2T0_HWTIMER_PRES          1
+#define ES_GP16C2T1_HWTIMER_PRES          1
+#define ES_BS16T0_HWTIMER_PRES          1
+#define ES_BS16T1_HWTIMER_PRES          1
+#define ES_BS16T2_HWTIMER_PRES          1
+#define ES_BS16T3_HWTIMER_PRES          1
+
+#ifndef  ES_DEVICE_NAME_AD16C4T0_HWTIMER
+#define  ES_DEVICE_NAME_AD16C4T0_HWTIMER     "timer0"
+#endif                
+#ifndef  ES_DEVICE_NAME_GP16C4T0_HWTIMER
+#define  ES_DEVICE_NAME_GP16C4T0_HWTIMER     "timer1"
+#endif               
+#ifndef  ES_DEVICE_NAME_GP16C2T0_HWTIMER
+#define  ES_DEVICE_NAME_GP16C2T0_HWTIMER     "timer2"
+#endif                
+#ifndef  ES_DEVICE_NAME_GP16C2T1_HWTIMER
+#define  ES_DEVICE_NAME_GP16C2T1_HWTIMER     "timer3"
+#endif                
+#ifndef  ES_DEVICE_NAME_BS16T0_HWTIMER
+#define  ES_DEVICE_NAME_BS16T0_HWTIMER     "timer4"
+#endif                
+#ifndef  ES_DEVICE_NAME_BS16T1_HWTIMER
+#define  ES_DEVICE_NAME_BS16T1_HWTIMER     "timer5"
+#endif                
+#ifndef  ES_DEVICE_NAME_BS16T2_HWTIMER
+#define  ES_DEVICE_NAME_BS16T2_HWTIMER     "timer6"
+#endif                
+#ifndef  ES_DEVICE_NAME_BS16T3_HWTIMER
+#define  ES_DEVICE_NAME_BS16T3_HWTIMER     "timer7"
+#endif                  
+
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_i2c.h

@@ -0,0 +1,95 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_I2C_H__
+#define __ES_CONF_INFO_I2C_H__
+
+#include "es_conf_info_map.h"
+#include <ald_i2c.h>
+#include <ald_gpio.h>
+#include <rtdbg.h>
+
+#define ES_C_I2C_STRETCH                 I2C_NOSTRETCH_DISABLE  
+#define ES_C_I2C_NO_STRETCH              I2C_NOSTRETCH_ENABLE
+
+#define ES_C_I2C_GENERALCALL             I2C_GENERALCALL_ENABLE
+#define ES_C_I2C_NO_GENERALCALL          I2C_GENERALCALL_DISABLE
+
+ 
+#define ES_C_I2C_ADDR_7_MODE                I2C_ADDR_7BIT   
+#define ES_C_I2C_ADDR_10_MODE                I2C_ADDR_10BIT
+
+
+/* I2C 配置 */
+
+              
+
+/* codes_main */
+
+   
+   
+   
+
+#ifndef  ES_DEVICE_NAME_I2C0
+#define  ES_DEVICE_NAME_I2C0     "i2c0"
+#endif              
+
+#ifndef  ES_DEVICE_NAME_I2C1
+#define  ES_DEVICE_NAME_I2C1     "i2c1"
+#endif                
+   
+#ifndef  ES_I2C0_CLK_SPEED
+#define ES_I2C0_CLK_SPEED                100000
+#endif
+#ifndef  ES_I2C0_OWN_ADDR1
+#define ES_I2C0_OWN_ADDR1                0x20
+#endif
+#ifndef  ES_I2C0_GENERAL_CALL
+#define ES_I2C0_GENERAL_CALL             ES_C_I2C_NO_GENERALCALL
+#endif
+#ifndef  ES_I2C0_STRETCH
+#define ES_I2C0_STRETCH               ES_C_I2C_STRETCH
+#endif
+#ifndef ES_I2C0_ADDR_MODE                                            
+#define ES_I2C0_ADDR_MODE                ES_C_I2C_ADDR_7_MODE 
+#endif
+
+#ifndef  ES_I2C1_CLK_SPEED
+#define ES_I2C1_CLK_SPEED                100000
+#endif
+#ifndef  ES_I2C1_OWN_ADDR1
+#define ES_I2C1_OWN_ADDR1                0x20
+#endif
+#ifndef  ES_I2C1_GENERAL_CALL
+#define ES_I2C1_GENERAL_CALL             ES_C_I2C_NO_GENERALCALL
+#endif
+#ifndef  ES_I2C1_STRETCH
+#define ES_I2C1_STRETCH               ES_C_I2C_STRETCH
+#endif 
+#ifndef ES_I2C1_ADDR_MODE                                            
+#define ES_I2C1_ADDR_MODE                ES_C_I2C_ADDR_7_MODE 
+#endif
+
+                                                 
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_map.h

@@ -0,0 +1,2691 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __es_conf_info_map_H__
+#define __es_conf_info_map_H__
+
+#include <ald_gpio.h>
+
+
+#define __ES_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
+#define __ES_PIN_DEFAULT {-1, 0, 0}
+
+struct pin_index
+{
+    int index;
+    GPIO_TypeDef *gpio;
+    uint32_t pin;
+};
+
+static const struct pin_index pins[] =
+{
+    __ES_PIN_DEFAULT,
+    __ES_PIN_DEFAULT,
+    __ES_PIN(2, C, 13),
+    __ES_PIN(3, C, 14),
+    __ES_PIN(4, C, 15),
+    __ES_PIN(5, H, 0),
+    __ES_PIN(6, H, 1),
+    __ES_PIN_DEFAULT,
+    __ES_PIN(8, C, 0),
+    __ES_PIN(9, C, 1),
+    __ES_PIN(10, C, 2),
+    __ES_PIN(11, C, 3),
+    __ES_PIN(12, H, 3),
+    __ES_PIN(13, H, 4),
+    __ES_PIN(14, A, 0),
+    __ES_PIN(15, A, 1),
+    __ES_PIN(16, A, 2),
+    __ES_PIN(17, A, 3),
+    __ES_PIN(18, F, 0),
+    __ES_PIN(19, F, 1),
+    __ES_PIN(20, A, 4),
+    __ES_PIN(21, A, 5),
+    __ES_PIN(22, A, 6),
+    __ES_PIN(23, A, 7),
+    __ES_PIN(24, C, 4),
+    __ES_PIN(25, C, 5),
+    __ES_PIN(26, B, 0),
+    __ES_PIN(27, B, 1),
+    __ES_PIN(28, B, 2),
+    __ES_PIN(29, B, 10),
+    __ES_PIN(30, B, 11),
+    __ES_PIN_DEFAULT,
+    __ES_PIN_DEFAULT,
+    __ES_PIN(33, B, 12),
+    __ES_PIN(34, B, 13),
+    __ES_PIN(35, B, 14),
+    __ES_PIN(36, B, 15),
+    __ES_PIN(37, C, 6),
+    __ES_PIN(38, C, 7),
+    __ES_PIN(39, C, 8),
+    __ES_PIN(40, C, 9),
+    __ES_PIN(41, A, 8),
+    __ES_PIN(42, A, 9),
+    __ES_PIN(43, A, 10),
+    __ES_PIN(44, A, 11),
+    __ES_PIN(45, A, 12),
+    __ES_PIN(46, A, 13),
+    __ES_PIN_DEFAULT,
+    __ES_PIN_DEFAULT,
+    __ES_PIN(49, A, 14),
+    __ES_PIN(50, A, 15),
+    __ES_PIN(51, C, 10),
+    __ES_PIN(52, C, 11),
+    __ES_PIN(53, C, 12),
+    __ES_PIN(54, D, 2),
+    __ES_PIN(55, B, 3),
+    __ES_PIN(56, B, 4),
+    __ES_PIN(57, B, 5),
+    __ES_PIN(58, B, 6),
+    __ES_PIN(59, B, 7),
+    __ES_PIN(60, H, 2),
+    __ES_PIN(61, B, 8),
+    __ES_PIN(62, B, 9),
+    __ES_PIN_DEFAULT,
+    __ES_PIN_DEFAULT,
+};
+
+#define ES_GPIO_ADC_CH0_GPIO     GPIOC
+#define ES_GPIO_ADC_CH1_GPIO     GPIOC
+#define ES_GPIO_ADC_CH2_GPIO     GPIOC
+#define ES_GPIO_ADC_CH3_GPIO     GPIOC
+#define ES_GPIO_ADC_CH4_GPIO     GPIOA
+#define ES_GPIO_ADC_CH5_GPIO     GPIOA
+#define ES_GPIO_ADC_CH6_GPIO     GPIOA
+#define ES_GPIO_ADC_CH7_GPIO     GPIOA
+#define ES_GPIO_ADC_CH8_GPIO     GPIOA
+#define ES_GPIO_ADC_CH9_GPIO     GPIOA
+#define ES_GPIO_ADC_CH10_GPIO     GPIOA
+#define ES_GPIO_ADC_CH11_GPIO     GPIOA
+#define ES_GPIO_ADC_CH12_GPIO     GPIOC
+#define ES_GPIO_ADC_CH13_GPIO     GPIOC
+#define ES_GPIO_ADC_CH14_GPIO     GPIOB
+#define ES_GPIO_ADC_CH15_GPIO     GPIOB
+
+#define ES_GPIO_ADC_CH0_PIN      GPIO_PIN_0
+#define ES_GPIO_ADC_CH1_PIN      GPIO_PIN_1
+#define ES_GPIO_ADC_CH2_PIN      GPIO_PIN_2
+#define ES_GPIO_ADC_CH3_PIN      GPIO_PIN_3
+#define ES_GPIO_ADC_CH4_PIN      GPIO_PIN_0 
+#define ES_GPIO_ADC_CH5_PIN      GPIO_PIN_1
+#define ES_GPIO_ADC_CH6_PIN      GPIO_PIN_2
+#define ES_GPIO_ADC_CH7_PIN      GPIO_PIN_3
+#define ES_GPIO_ADC_CH8_PIN      GPIO_PIN_4
+#define ES_GPIO_ADC_CH9_PIN      GPIO_PIN_5
+#define ES_GPIO_ADC_CH10_PIN      GPIO_PIN_6
+#define ES_GPIO_ADC_CH11_PIN      GPIO_PIN_7
+#define ES_GPIO_ADC_CH12_PIN      GPIO_PIN_4
+#define ES_GPIO_ADC_CH13_PIN      GPIO_PIN_5
+#define ES_GPIO_ADC_CH14_PIN      GPIO_PIN_0
+#define ES_GPIO_ADC_CH15_PIN      GPIO_PIN_1
+
+
+
+
+#define   ES_PIN_GPIO_C_13   2
+#define   ES_PIN_GPIO_C_14   3
+#define   ES_PIN_GPIO_C_15   4
+#define   ES_PIN_GPIO_H_0   5
+#define   ES_PIN_GPIO_H_1   6
+#define   ES_PIN_GPIO_C_0   8
+#define   ES_PIN_GPIO_C_1   9
+#define   ES_PIN_GPIO_C_2   10
+#define   ES_PIN_GPIO_C_3   11
+#define   ES_PIN_GPIO_H_3   12
+#define   ES_PIN_GPIO_H_4   13
+#define   ES_PIN_GPIO_A_0   14
+#define   ES_PIN_GPIO_A_1   15
+#define   ES_PIN_GPIO_A_2   16
+#define   ES_PIN_GPIO_A_3   17
+#define   ES_PIN_GPIO_F_0   18
+#define   ES_PIN_GPIO_F_1   19
+#define   ES_PIN_GPIO_A_4   20
+#define   ES_PIN_GPIO_A_5   21
+#define   ES_PIN_GPIO_A_6   22
+#define   ES_PIN_GPIO_A_7   23
+#define   ES_PIN_GPIO_C_4   24
+#define   ES_PIN_GPIO_C_5   25
+#define   ES_PIN_GPIO_B_0   26
+#define   ES_PIN_GPIO_B_1   27
+#define   ES_PIN_GPIO_B_2   28
+#define   ES_PIN_GPIO_B_10   29
+#define   ES_PIN_GPIO_B_11   30
+#define   ES_PIN_GPIO_B_12   33
+#define   ES_PIN_GPIO_B_13   34
+#define   ES_PIN_GPIO_B_14   35
+#define   ES_PIN_GPIO_B_15   36
+#define   ES_PIN_GPIO_C_6   37
+#define   ES_PIN_GPIO_C_7   38
+#define   ES_PIN_GPIO_C_8   39
+#define   ES_PIN_GPIO_C_9   40
+#define   ES_PIN_GPIO_A_8   41
+#define   ES_PIN_GPIO_A_9   42
+#define   ES_PIN_GPIO_A_10   43
+#define   ES_PIN_GPIO_A_11   44
+#define   ES_PIN_GPIO_A_12   45
+#define   ES_PIN_GPIO_A_13   46
+#define   ES_PIN_GPIO_A_14   49
+#define   ES_PIN_GPIO_A_15   50
+#define   ES_PIN_GPIO_C_10   51
+#define   ES_PIN_GPIO_C_11   52
+#define   ES_PIN_GPIO_C_12   53
+#define   ES_PIN_GPIO_D_2   54
+#define   ES_PIN_GPIO_B_3   55
+#define   ES_PIN_GPIO_B_4   56
+#define   ES_PIN_GPIO_B_5   57
+#define   ES_PIN_GPIO_B_6   58
+#define   ES_PIN_GPIO_B_7   59
+#define   ES_PIN_GPIO_H_2   60
+#define   ES_PIN_GPIO_B_8   61
+#define   ES_PIN_GPIO_B_9   62
+
+
+
+/* UART_TX */
+
+
+#ifndef ES_UART0_TX_GPIO_FUNC 
+#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PORT 
+#define ES_UART0_TX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PIN 
+#define ES_UART0_TX_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_UART0_TX_PIN 
+#ifdef ES_PIN_GPIO_B_10 
+#define ES_UART0_TX_PIN ES_PIN_GPIO_B_10 
+#endif
+#endif 
+
+#ifndef ES_UART0_TX_GPIO_FUNC 
+#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PORT 
+#define ES_UART0_TX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PIN 
+#define ES_UART0_TX_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_UART0_TX_PIN 
+#ifdef ES_PIN_GPIO_A_9 
+#define ES_UART0_TX_PIN ES_PIN_GPIO_A_9 
+#endif
+#endif 
+
+#ifndef ES_UART0_TX_GPIO_FUNC 
+#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PORT 
+#define ES_UART0_TX_GPIO_PORT GPIOH 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PIN 
+#define ES_UART0_TX_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_UART0_TX_PIN 
+#ifdef ES_PIN_GPIO_H_0 
+#define ES_UART0_TX_PIN ES_PIN_GPIO_H_0 
+#endif
+#endif 
+
+#ifndef ES_UART0_TX_GPIO_FUNC 
+#define ES_UART0_TX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PORT 
+#define ES_UART0_TX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART0_TX_GPIO_PIN 
+#define ES_UART0_TX_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_UART0_TX_PIN 
+#ifdef ES_PIN_GPIO_D_8 
+#define ES_UART0_TX_PIN ES_PIN_GPIO_D_8 
+#endif
+#endif 
+
+#ifndef ES_UART1_TX_GPIO_FUNC 
+#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PORT 
+#define ES_UART1_TX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PIN 
+#define ES_UART1_TX_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_UART1_TX_PIN 
+#ifdef ES_PIN_GPIO_C_0 
+#define ES_UART1_TX_PIN ES_PIN_GPIO_C_0 
+#endif
+#endif 
+
+#ifndef ES_UART1_TX_GPIO_FUNC 
+#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PORT 
+#define ES_UART1_TX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PIN 
+#define ES_UART1_TX_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_UART1_TX_PIN 
+#ifdef ES_PIN_GPIO_C_10 
+#define ES_UART1_TX_PIN ES_PIN_GPIO_C_10 
+#endif
+#endif 
+
+#ifndef ES_UART1_TX_GPIO_FUNC 
+#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PORT 
+#define ES_UART1_TX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PIN 
+#define ES_UART1_TX_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_UART1_TX_PIN 
+#ifdef ES_PIN_GPIO_A_13 
+#define ES_UART1_TX_PIN ES_PIN_GPIO_A_13 
+#endif
+#endif 
+
+#ifndef ES_UART1_TX_GPIO_FUNC 
+#define ES_UART1_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PORT 
+#define ES_UART1_TX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART1_TX_GPIO_PIN 
+#define ES_UART1_TX_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_UART1_TX_PIN 
+#ifdef ES_PIN_GPIO_D_5 
+#define ES_UART1_TX_PIN ES_PIN_GPIO_D_5 
+#endif
+#endif 
+
+#ifndef ES_UART2_TX_GPIO_FUNC 
+#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART2_TX_GPIO_PORT 
+#define ES_UART2_TX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART2_TX_GPIO_PIN 
+#define ES_UART2_TX_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_UART2_TX_PIN 
+#ifdef ES_PIN_GPIO_C_12 
+#define ES_UART2_TX_PIN ES_PIN_GPIO_C_12 
+#endif
+#endif 
+
+#ifndef ES_UART2_TX_GPIO_FUNC 
+#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART2_TX_GPIO_PORT 
+#define ES_UART2_TX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART2_TX_GPIO_PIN 
+#define ES_UART2_TX_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_UART2_TX_PIN 
+#ifdef ES_PIN_GPIO_B_3 
+#define ES_UART2_TX_PIN ES_PIN_GPIO_B_3 
+#endif
+#endif 
+
+#ifndef ES_UART2_TX_GPIO_FUNC 
+#define ES_UART2_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART2_TX_GPIO_PORT 
+#define ES_UART2_TX_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART2_TX_GPIO_PIN 
+#define ES_UART2_TX_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_UART2_TX_PIN 
+#ifdef ES_PIN_GPIO_E_2 
+#define ES_UART2_TX_PIN ES_PIN_GPIO_E_2 
+#endif
+#endif 
+
+#ifndef ES_UART3_TX_GPIO_FUNC 
+#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_UART3_TX_GPIO_PORT 
+#define ES_UART3_TX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART3_TX_GPIO_PIN 
+#define ES_UART3_TX_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_UART3_TX_PIN 
+#ifdef ES_PIN_GPIO_C_4 
+#define ES_UART3_TX_PIN ES_PIN_GPIO_C_4 
+#endif
+#endif 
+
+#ifndef ES_UART3_TX_GPIO_FUNC 
+#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART3_TX_GPIO_PORT 
+#define ES_UART3_TX_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART3_TX_GPIO_PIN 
+#define ES_UART3_TX_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_UART3_TX_PIN 
+#ifdef ES_PIN_GPIO_E_10 
+#define ES_UART3_TX_PIN ES_PIN_GPIO_E_10 
+#endif
+#endif 
+
+#ifndef ES_UART3_TX_GPIO_FUNC 
+#define ES_UART3_TX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_UART3_TX_GPIO_PORT 
+#define ES_UART3_TX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART3_TX_GPIO_PIN 
+#define ES_UART3_TX_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_UART3_TX_PIN 
+#ifdef ES_PIN_GPIO_D_14 
+#define ES_UART3_TX_PIN ES_PIN_GPIO_D_14 
+#endif
+#endif 
+
+
+/* UART_RX */
+
+
+#ifndef ES_UART0_RX_GPIO_FUNC 
+#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PORT 
+#define ES_UART0_RX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PIN 
+#define ES_UART0_RX_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_UART0_RX_PIN 
+#ifdef ES_PIN_GPIO_A_10 
+#define ES_UART0_RX_PIN ES_PIN_GPIO_A_10 
+#endif
+#endif 
+
+#ifndef ES_UART0_RX_GPIO_FUNC 
+#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PORT 
+#define ES_UART0_RX_GPIO_PORT GPIOH 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PIN 
+#define ES_UART0_RX_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_UART0_RX_PIN 
+#ifdef ES_PIN_GPIO_H_1 
+#define ES_UART0_RX_PIN ES_PIN_GPIO_H_1 
+#endif
+#endif 
+
+#ifndef ES_UART0_RX_GPIO_FUNC 
+#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PORT 
+#define ES_UART0_RX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PIN 
+#define ES_UART0_RX_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_UART0_RX_PIN 
+#ifdef ES_PIN_GPIO_B_11 
+#define ES_UART0_RX_PIN ES_PIN_GPIO_B_11 
+#endif
+#endif 
+
+#ifndef ES_UART0_RX_GPIO_FUNC 
+#define ES_UART0_RX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PORT 
+#define ES_UART0_RX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART0_RX_GPIO_PIN 
+#define ES_UART0_RX_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_UART0_RX_PIN 
+#ifdef ES_PIN_GPIO_D_9 
+#define ES_UART0_RX_PIN ES_PIN_GPIO_D_9 
+#endif
+#endif 
+
+#ifndef ES_UART1_RX_GPIO_FUNC 
+#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PORT 
+#define ES_UART1_RX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PIN 
+#define ES_UART1_RX_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_UART1_RX_PIN 
+#ifdef ES_PIN_GPIO_C_11 
+#define ES_UART1_RX_PIN ES_PIN_GPIO_C_11 
+#endif
+#endif 
+
+#ifndef ES_UART1_RX_GPIO_FUNC 
+#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PORT 
+#define ES_UART1_RX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PIN 
+#define ES_UART1_RX_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_UART1_RX_PIN 
+#ifdef ES_PIN_GPIO_C_1 
+#define ES_UART1_RX_PIN ES_PIN_GPIO_C_1 
+#endif
+#endif 
+
+#ifndef ES_UART1_RX_GPIO_FUNC 
+#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PORT 
+#define ES_UART1_RX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PIN 
+#define ES_UART1_RX_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_UART1_RX_PIN 
+#ifdef ES_PIN_GPIO_A_14 
+#define ES_UART1_RX_PIN ES_PIN_GPIO_A_14 
+#endif
+#endif 
+
+#ifndef ES_UART1_RX_GPIO_FUNC 
+#define ES_UART1_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PORT 
+#define ES_UART1_RX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART1_RX_GPIO_PIN 
+#define ES_UART1_RX_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_UART1_RX_PIN 
+#ifdef ES_PIN_GPIO_D_6 
+#define ES_UART1_RX_PIN ES_PIN_GPIO_D_6 
+#endif
+#endif 
+
+#ifndef ES_UART2_RX_GPIO_FUNC 
+#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART2_RX_GPIO_PORT 
+#define ES_UART2_RX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART2_RX_GPIO_PIN 
+#define ES_UART2_RX_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_UART2_RX_PIN 
+#ifdef ES_PIN_GPIO_D_2 
+#define ES_UART2_RX_PIN ES_PIN_GPIO_D_2 
+#endif
+#endif 
+
+#ifndef ES_UART2_RX_GPIO_FUNC 
+#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART2_RX_GPIO_PORT 
+#define ES_UART2_RX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART2_RX_GPIO_PIN 
+#define ES_UART2_RX_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_UART2_RX_PIN 
+#ifdef ES_PIN_GPIO_B_4 
+#define ES_UART2_RX_PIN ES_PIN_GPIO_B_4 
+#endif
+#endif 
+
+#ifndef ES_UART2_RX_GPIO_FUNC 
+#define ES_UART2_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART2_RX_GPIO_PORT 
+#define ES_UART2_RX_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART2_RX_GPIO_PIN 
+#define ES_UART2_RX_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_UART2_RX_PIN 
+#ifdef ES_PIN_GPIO_E_3 
+#define ES_UART2_RX_PIN ES_PIN_GPIO_E_3 
+#endif
+#endif 
+
+#ifndef ES_UART3_RX_GPIO_FUNC 
+#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_UART3_RX_GPIO_PORT 
+#define ES_UART3_RX_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART3_RX_GPIO_PIN 
+#define ES_UART3_RX_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_UART3_RX_PIN 
+#ifdef ES_PIN_GPIO_C_5 
+#define ES_UART3_RX_PIN ES_PIN_GPIO_C_5 
+#endif
+#endif 
+
+#ifndef ES_UART3_RX_GPIO_FUNC 
+#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART3_RX_GPIO_PORT 
+#define ES_UART3_RX_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART3_RX_GPIO_PIN 
+#define ES_UART3_RX_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_UART3_RX_PIN 
+#ifdef ES_PIN_GPIO_E_11 
+#define ES_UART3_RX_PIN ES_PIN_GPIO_E_11 
+#endif
+#endif 
+
+#ifndef ES_UART3_RX_GPIO_FUNC 
+#define ES_UART3_RX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_UART3_RX_GPIO_PORT 
+#define ES_UART3_RX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART3_RX_GPIO_PIN 
+#define ES_UART3_RX_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_UART3_RX_PIN 
+#ifdef ES_PIN_GPIO_D_13 
+#define ES_UART3_RX_PIN ES_PIN_GPIO_D_13 
+#endif
+#endif 
+
+
+/* UART_RTS */
+
+
+#ifndef ES_UART0_RTS_GPIO_FUNC 
+#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART0_RTS_GPIO_PORT 
+#define ES_UART0_RTS_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART0_RTS_GPIO_PIN 
+#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_UART0_RTS_PIN 
+#ifdef ES_PIN_GPIO_B_14 
+#define ES_UART0_RTS_PIN ES_PIN_GPIO_B_14 
+#endif
+#endif 
+
+#ifndef ES_UART0_RTS_GPIO_FUNC 
+#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_RTS_GPIO_PORT 
+#define ES_UART0_RTS_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_UART0_RTS_GPIO_PIN 
+#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_UART0_RTS_PIN 
+#ifdef ES_PIN_GPIO_A_12 
+#define ES_UART0_RTS_PIN ES_PIN_GPIO_A_12 
+#endif
+#endif 
+
+#ifndef ES_UART0_RTS_GPIO_FUNC 
+#define ES_UART0_RTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_RTS_GPIO_PORT 
+#define ES_UART0_RTS_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART0_RTS_GPIO_PIN 
+#define ES_UART0_RTS_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_UART0_RTS_PIN 
+#ifdef ES_PIN_GPIO_D_12 
+#define ES_UART0_RTS_PIN ES_PIN_GPIO_D_12 
+#endif
+#endif 
+
+#ifndef ES_UART1_RTS_GPIO_FUNC 
+#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_RTS_GPIO_PORT 
+#define ES_UART1_RTS_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_RTS_GPIO_PIN 
+#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_UART1_RTS_PIN 
+#ifdef ES_PIN_GPIO_C_12 
+#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_12 
+#endif
+#endif 
+
+#ifndef ES_UART1_RTS_GPIO_FUNC 
+#define ES_UART1_RTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_RTS_GPIO_PORT 
+#define ES_UART1_RTS_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_RTS_GPIO_PIN 
+#define ES_UART1_RTS_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_UART1_RTS_PIN 
+#ifdef ES_PIN_GPIO_C_3 
+#define ES_UART1_RTS_PIN ES_PIN_GPIO_C_3 
+#endif
+#endif 
+
+#ifndef ES_UART2_RTS_GPIO_FUNC 
+#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART2_RTS_GPIO_PORT 
+#define ES_UART2_RTS_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART2_RTS_GPIO_PIN 
+#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_UART2_RTS_PIN 
+#ifdef ES_PIN_GPIO_C_10 
+#define ES_UART2_RTS_PIN ES_PIN_GPIO_C_10 
+#endif
+#endif 
+
+#ifndef ES_UART2_RTS_GPIO_FUNC 
+#define ES_UART2_RTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART2_RTS_GPIO_PORT 
+#define ES_UART2_RTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART2_RTS_GPIO_PIN 
+#define ES_UART2_RTS_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_UART2_RTS_PIN 
+#ifdef ES_PIN_GPIO_E_5 
+#define ES_UART2_RTS_PIN ES_PIN_GPIO_E_5 
+#endif
+#endif 
+
+#ifndef ES_UART3_RTS_GPIO_FUNC 
+#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_UART3_RTS_GPIO_PORT 
+#define ES_UART3_RTS_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART3_RTS_GPIO_PIN 
+#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_UART3_RTS_PIN 
+#ifdef ES_PIN_GPIO_B_1 
+#define ES_UART3_RTS_PIN ES_PIN_GPIO_B_1 
+#endif
+#endif 
+
+#ifndef ES_UART3_RTS_GPIO_FUNC 
+#define ES_UART3_RTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART3_RTS_GPIO_PORT 
+#define ES_UART3_RTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART3_RTS_GPIO_PIN 
+#define ES_UART3_RTS_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_UART3_RTS_PIN 
+#ifdef ES_PIN_GPIO_E_13 
+#define ES_UART3_RTS_PIN ES_PIN_GPIO_E_13 
+#endif
+#endif 
+
+
+/* UART_CTS */
+
+
+#ifndef ES_UART0_CTS_GPIO_FUNC 
+#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART0_CTS_GPIO_PORT 
+#define ES_UART0_CTS_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART0_CTS_GPIO_PIN 
+#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_UART0_CTS_PIN 
+#ifdef ES_PIN_GPIO_B_13 
+#define ES_UART0_CTS_PIN ES_PIN_GPIO_B_13 
+#endif
+#endif 
+
+#ifndef ES_UART0_CTS_GPIO_FUNC 
+#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_CTS_GPIO_PORT 
+#define ES_UART0_CTS_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_UART0_CTS_GPIO_PIN 
+#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_UART0_CTS_PIN 
+#ifdef ES_PIN_GPIO_A_11 
+#define ES_UART0_CTS_PIN ES_PIN_GPIO_A_11 
+#endif
+#endif 
+
+#ifndef ES_UART0_CTS_GPIO_FUNC 
+#define ES_UART0_CTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART0_CTS_GPIO_PORT 
+#define ES_UART0_CTS_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART0_CTS_GPIO_PIN 
+#define ES_UART0_CTS_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_UART0_CTS_PIN 
+#ifdef ES_PIN_GPIO_D_11 
+#define ES_UART0_CTS_PIN ES_PIN_GPIO_D_11 
+#endif
+#endif 
+
+#ifndef ES_UART1_CTS_GPIO_FUNC 
+#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_CTS_GPIO_PORT 
+#define ES_UART1_CTS_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART1_CTS_GPIO_PIN 
+#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_UART1_CTS_PIN 
+#ifdef ES_PIN_GPIO_C_2 
+#define ES_UART1_CTS_PIN ES_PIN_GPIO_C_2 
+#endif
+#endif 
+
+#ifndef ES_UART1_CTS_GPIO_FUNC 
+#define ES_UART1_CTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART1_CTS_GPIO_PORT 
+#define ES_UART1_CTS_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_UART1_CTS_GPIO_PIN 
+#define ES_UART1_CTS_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_UART1_CTS_PIN 
+#ifdef ES_PIN_GPIO_D_2 
+#define ES_UART1_CTS_PIN ES_PIN_GPIO_D_2 
+#endif
+#endif 
+
+#ifndef ES_UART2_CTS_GPIO_FUNC 
+#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART2_CTS_GPIO_PORT 
+#define ES_UART2_CTS_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_UART2_CTS_GPIO_PIN 
+#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_UART2_CTS_PIN 
+#ifdef ES_PIN_GPIO_C_11 
+#define ES_UART2_CTS_PIN ES_PIN_GPIO_C_11 
+#endif
+#endif 
+
+#ifndef ES_UART2_CTS_GPIO_FUNC 
+#define ES_UART2_CTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_UART2_CTS_GPIO_PORT 
+#define ES_UART2_CTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART2_CTS_GPIO_PIN 
+#define ES_UART2_CTS_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_UART2_CTS_PIN 
+#ifdef ES_PIN_GPIO_E_4 
+#define ES_UART2_CTS_PIN ES_PIN_GPIO_E_4 
+#endif
+#endif 
+
+#ifndef ES_UART3_CTS_GPIO_FUNC 
+#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_UART3_CTS_GPIO_PORT 
+#define ES_UART3_CTS_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_UART3_CTS_GPIO_PIN 
+#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_UART3_CTS_PIN 
+#ifdef ES_PIN_GPIO_B_0 
+#define ES_UART3_CTS_PIN ES_PIN_GPIO_B_0 
+#endif
+#endif 
+
+#ifndef ES_UART3_CTS_GPIO_FUNC 
+#define ES_UART3_CTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_UART3_CTS_GPIO_PORT 
+#define ES_UART3_CTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_UART3_CTS_GPIO_PIN 
+#define ES_UART3_CTS_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_UART3_CTS_PIN 
+#ifdef ES_PIN_GPIO_E_12 
+#define ES_UART3_CTS_PIN ES_PIN_GPIO_E_12 
+#endif
+#endif 
+
+
+/* UART_CK */
+
+
+
+/* USART_TX */
+
+
+#ifndef ES_USART0_TX_GPIO_FUNC 
+#define ES_USART0_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART0_TX_GPIO_PORT 
+#define ES_USART0_TX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_USART0_TX_GPIO_PIN 
+#define ES_USART0_TX_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_USART0_TX_PIN 
+#ifdef ES_PIN_GPIO_B_6 
+#define ES_USART0_TX_PIN ES_PIN_GPIO_B_6 
+#endif
+#endif 
+
+#ifndef ES_USART0_TX_GPIO_FUNC 
+#define ES_USART0_TX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART0_TX_GPIO_PORT 
+#define ES_USART0_TX_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_TX_GPIO_PIN 
+#define ES_USART0_TX_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_USART0_TX_PIN 
+#ifdef ES_PIN_GPIO_E_10 
+#define ES_USART0_TX_PIN ES_PIN_GPIO_E_10 
+#endif
+#endif 
+
+#ifndef ES_USART1_TX_GPIO_FUNC 
+#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART1_TX_GPIO_PORT 
+#define ES_USART1_TX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_USART1_TX_GPIO_PIN 
+#define ES_USART1_TX_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_USART1_TX_PIN 
+#ifdef ES_PIN_GPIO_A_2 
+#define ES_USART1_TX_PIN ES_PIN_GPIO_A_2 
+#endif
+#endif 
+
+#ifndef ES_USART1_TX_GPIO_FUNC 
+#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART1_TX_GPIO_PORT 
+#define ES_USART1_TX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_USART1_TX_GPIO_PIN 
+#define ES_USART1_TX_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_USART1_TX_PIN 
+#ifdef ES_PIN_GPIO_B_9 
+#define ES_USART1_TX_PIN ES_PIN_GPIO_B_9 
+#endif
+#endif 
+
+#ifndef ES_USART1_TX_GPIO_FUNC 
+#define ES_USART1_TX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_USART1_TX_GPIO_PORT 
+#define ES_USART1_TX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_USART1_TX_GPIO_PIN 
+#define ES_USART1_TX_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_USART1_TX_PIN 
+#ifdef ES_PIN_GPIO_D_5 
+#define ES_USART1_TX_PIN ES_PIN_GPIO_D_5 
+#endif
+#endif 
+
+
+/* USART_RX */
+
+
+#ifndef ES_USART0_RX_GPIO_FUNC 
+#define ES_USART0_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART0_RX_GPIO_PORT 
+#define ES_USART0_RX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_USART0_RX_GPIO_PIN 
+#define ES_USART0_RX_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_USART0_RX_PIN 
+#ifdef ES_PIN_GPIO_B_7 
+#define ES_USART0_RX_PIN ES_PIN_GPIO_B_7 
+#endif
+#endif 
+
+#ifndef ES_USART0_RX_GPIO_FUNC 
+#define ES_USART0_RX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART0_RX_GPIO_PORT 
+#define ES_USART0_RX_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_RX_GPIO_PIN 
+#define ES_USART0_RX_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_USART0_RX_PIN 
+#ifdef ES_PIN_GPIO_E_11 
+#define ES_USART0_RX_PIN ES_PIN_GPIO_E_11 
+#endif
+#endif 
+
+#ifndef ES_USART1_RX_GPIO_FUNC 
+#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART1_RX_GPIO_PORT 
+#define ES_USART1_RX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_USART1_RX_GPIO_PIN 
+#define ES_USART1_RX_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_USART1_RX_PIN 
+#ifdef ES_PIN_GPIO_A_3 
+#define ES_USART1_RX_PIN ES_PIN_GPIO_A_3 
+#endif
+#endif 
+
+#ifndef ES_USART1_RX_GPIO_FUNC 
+#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_USART1_RX_GPIO_PORT 
+#define ES_USART1_RX_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_USART1_RX_GPIO_PIN 
+#define ES_USART1_RX_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_USART1_RX_PIN 
+#ifdef ES_PIN_GPIO_D_6 
+#define ES_USART1_RX_PIN ES_PIN_GPIO_D_6 
+#endif
+#endif 
+
+#ifndef ES_USART1_RX_GPIO_FUNC 
+#define ES_USART1_RX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART1_RX_GPIO_PORT 
+#define ES_USART1_RX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_USART1_RX_GPIO_PIN 
+#define ES_USART1_RX_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_USART1_RX_PIN 
+#ifdef ES_PIN_GPIO_B_8 
+#define ES_USART1_RX_PIN ES_PIN_GPIO_B_8 
+#endif
+#endif 
+
+
+/* USART_RTS */
+
+
+#ifndef ES_USART0_RTS_GPIO_FUNC 
+#define ES_USART0_RTS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART0_RTS_GPIO_PORT 
+#define ES_USART0_RTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_RTS_GPIO_PIN 
+#define ES_USART0_RTS_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_USART0_RTS_PIN 
+#ifdef ES_PIN_GPIO_E_13 
+#define ES_USART0_RTS_PIN ES_PIN_GPIO_E_13 
+#endif
+#endif 
+
+#ifndef ES_USART0_RTS_GPIO_FUNC 
+#define ES_USART0_RTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART0_RTS_GPIO_PORT 
+#define ES_USART0_RTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_RTS_GPIO_PIN 
+#define ES_USART0_RTS_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_USART0_RTS_PIN 
+#ifdef ES_PIN_GPIO_E_1 
+#define ES_USART0_RTS_PIN ES_PIN_GPIO_E_1 
+#endif
+#endif 
+
+#ifndef ES_USART1_RTS_GPIO_FUNC 
+#define ES_USART1_RTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART1_RTS_GPIO_PORT 
+#define ES_USART1_RTS_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_USART1_RTS_GPIO_PIN 
+#define ES_USART1_RTS_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_USART1_RTS_PIN 
+#ifdef ES_PIN_GPIO_A_1 
+#define ES_USART1_RTS_PIN ES_PIN_GPIO_A_1 
+#endif
+#endif 
+
+#ifndef ES_USART1_RTS_GPIO_FUNC 
+#define ES_USART1_RTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_USART1_RTS_GPIO_PORT 
+#define ES_USART1_RTS_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_USART1_RTS_GPIO_PIN 
+#define ES_USART1_RTS_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_USART1_RTS_PIN 
+#ifdef ES_PIN_GPIO_D_4 
+#define ES_USART1_RTS_PIN ES_PIN_GPIO_D_4 
+#endif
+#endif 
+
+
+/* USART_CTS */
+
+
+#ifndef ES_USART0_CTS_GPIO_FUNC 
+#define ES_USART0_CTS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART0_CTS_GPIO_PORT 
+#define ES_USART0_CTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_CTS_GPIO_PIN 
+#define ES_USART0_CTS_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_USART0_CTS_PIN 
+#ifdef ES_PIN_GPIO_E_12 
+#define ES_USART0_CTS_PIN ES_PIN_GPIO_E_12 
+#endif
+#endif 
+
+#ifndef ES_USART0_CTS_GPIO_FUNC 
+#define ES_USART0_CTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART0_CTS_GPIO_PORT 
+#define ES_USART0_CTS_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_CTS_GPIO_PIN 
+#define ES_USART0_CTS_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_USART0_CTS_PIN 
+#ifdef ES_PIN_GPIO_E_0 
+#define ES_USART0_CTS_PIN ES_PIN_GPIO_E_0 
+#endif
+#endif 
+
+#ifndef ES_USART1_CTS_GPIO_FUNC 
+#define ES_USART1_CTS_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART1_CTS_GPIO_PORT 
+#define ES_USART1_CTS_GPIO_PORT GPIOF 
+#endif 
+#ifndef ES_USART1_CTS_GPIO_PIN 
+#define ES_USART1_CTS_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_USART1_CTS_PIN 
+#ifdef ES_PIN_GPIO_F_7 
+#define ES_USART1_CTS_PIN ES_PIN_GPIO_F_7 
+#endif
+#endif 
+
+#ifndef ES_USART1_CTS_GPIO_FUNC 
+#define ES_USART1_CTS_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_USART1_CTS_GPIO_PORT 
+#define ES_USART1_CTS_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_USART1_CTS_GPIO_PIN 
+#define ES_USART1_CTS_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_USART1_CTS_PIN 
+#ifdef ES_PIN_GPIO_D_3 
+#define ES_USART1_CTS_PIN ES_PIN_GPIO_D_3 
+#endif
+#endif 
+
+
+/* USART_CK */
+
+
+#ifndef ES_USART0_CK_GPIO_FUNC 
+#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_USART0_CK_GPIO_PORT 
+#define ES_USART0_CK_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_USART0_CK_GPIO_PIN 
+#define ES_USART0_CK_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_USART0_CK_PIN 
+#ifdef ES_PIN_GPIO_A_8 
+#define ES_USART0_CK_PIN ES_PIN_GPIO_A_8 
+#endif
+#endif 
+
+#ifndef ES_USART0_CK_GPIO_FUNC 
+#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART0_CK_GPIO_PORT 
+#define ES_USART0_CK_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_CK_GPIO_PIN 
+#define ES_USART0_CK_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_USART0_CK_PIN 
+#ifdef ES_PIN_GPIO_E_6 
+#define ES_USART0_CK_PIN ES_PIN_GPIO_E_6 
+#endif
+#endif 
+
+#ifndef ES_USART0_CK_GPIO_FUNC 
+#define ES_USART0_CK_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART0_CK_GPIO_PORT 
+#define ES_USART0_CK_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART0_CK_GPIO_PIN 
+#define ES_USART0_CK_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_USART0_CK_PIN 
+#ifdef ES_PIN_GPIO_E_7 
+#define ES_USART0_CK_PIN ES_PIN_GPIO_E_7 
+#endif
+#endif 
+
+#ifndef ES_USART1_CK_GPIO_FUNC 
+#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_USART1_CK_GPIO_PORT 
+#define ES_USART1_CK_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_USART1_CK_GPIO_PIN 
+#define ES_USART1_CK_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_USART1_CK_PIN 
+#ifdef ES_PIN_GPIO_A_4 
+#define ES_USART1_CK_PIN ES_PIN_GPIO_A_4 
+#endif
+#endif 
+
+#ifndef ES_USART1_CK_GPIO_FUNC 
+#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_USART1_CK_GPIO_PORT 
+#define ES_USART1_CK_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_USART1_CK_GPIO_PIN 
+#define ES_USART1_CK_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_USART1_CK_PIN 
+#ifdef ES_PIN_GPIO_D_7 
+#define ES_USART1_CK_PIN ES_PIN_GPIO_D_7 
+#endif
+#endif 
+
+#ifndef ES_USART1_CK_GPIO_FUNC 
+#define ES_USART1_CK_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_USART1_CK_GPIO_PORT 
+#define ES_USART1_CK_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_USART1_CK_GPIO_PIN 
+#define ES_USART1_CK_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_USART1_CK_PIN 
+#ifdef ES_PIN_GPIO_E_0 
+#define ES_USART1_CK_PIN ES_PIN_GPIO_E_0 
+#endif
+#endif 
+
+
+/* I2C_SCL */
+
+
+#ifndef ES_I2C0_SCL_GPIO_FUNC 
+#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C0_SCL_GPIO_PORT 
+#define ES_I2C0_SCL_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_I2C0_SCL_GPIO_PIN 
+#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_I2C0_SCL_PIN 
+#ifdef ES_PIN_GPIO_B_6 
+#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_6 
+#endif
+#endif 
+
+#ifndef ES_I2C0_SCL_GPIO_FUNC 
+#define ES_I2C0_SCL_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C0_SCL_GPIO_PORT 
+#define ES_I2C0_SCL_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_I2C0_SCL_GPIO_PIN 
+#define ES_I2C0_SCL_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_I2C0_SCL_PIN 
+#ifdef ES_PIN_GPIO_B_8 
+#define ES_I2C0_SCL_PIN ES_PIN_GPIO_B_8 
+#endif
+#endif 
+
+#ifndef ES_I2C1_SCL_GPIO_FUNC 
+#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C1_SCL_GPIO_PORT 
+#define ES_I2C1_SCL_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_I2C1_SCL_GPIO_PIN 
+#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_I2C1_SCL_PIN 
+#ifdef ES_PIN_GPIO_A_5 
+#define ES_I2C1_SCL_PIN ES_PIN_GPIO_A_5 
+#endif
+#endif 
+
+#ifndef ES_I2C1_SCL_GPIO_FUNC 
+#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C1_SCL_GPIO_PORT 
+#define ES_I2C1_SCL_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_I2C1_SCL_GPIO_PIN 
+#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_I2C1_SCL_PIN 
+#ifdef ES_PIN_GPIO_B_10 
+#define ES_I2C1_SCL_PIN ES_PIN_GPIO_B_10 
+#endif
+#endif 
+
+#ifndef ES_I2C1_SCL_GPIO_FUNC 
+#define ES_I2C1_SCL_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C1_SCL_GPIO_PORT 
+#define ES_I2C1_SCL_GPIO_PORT GPIOH 
+#endif 
+#ifndef ES_I2C1_SCL_GPIO_PIN 
+#define ES_I2C1_SCL_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_I2C1_SCL_PIN 
+#ifdef ES_PIN_GPIO_H_0 
+#define ES_I2C1_SCL_PIN ES_PIN_GPIO_H_0 
+#endif
+#endif 
+
+
+/* I2C_SDA */
+
+
+#ifndef ES_I2C0_SDA_GPIO_FUNC 
+#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C0_SDA_GPIO_PORT 
+#define ES_I2C0_SDA_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_I2C0_SDA_GPIO_PIN 
+#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_I2C0_SDA_PIN 
+#ifdef ES_PIN_GPIO_B_7 
+#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_7 
+#endif
+#endif 
+
+#ifndef ES_I2C0_SDA_GPIO_FUNC 
+#define ES_I2C0_SDA_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C0_SDA_GPIO_PORT 
+#define ES_I2C0_SDA_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_I2C0_SDA_GPIO_PIN 
+#define ES_I2C0_SDA_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_I2C0_SDA_PIN 
+#ifdef ES_PIN_GPIO_B_9 
+#define ES_I2C0_SDA_PIN ES_PIN_GPIO_B_9 
+#endif
+#endif 
+
+#ifndef ES_I2C1_SDA_GPIO_FUNC 
+#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C1_SDA_GPIO_PORT 
+#define ES_I2C1_SDA_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_I2C1_SDA_GPIO_PIN 
+#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_I2C1_SDA_PIN 
+#ifdef ES_PIN_GPIO_A_6 
+#define ES_I2C1_SDA_PIN ES_PIN_GPIO_A_6 
+#endif
+#endif 
+
+#ifndef ES_I2C1_SDA_GPIO_FUNC 
+#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C1_SDA_GPIO_PORT 
+#define ES_I2C1_SDA_GPIO_PORT GPIOH 
+#endif 
+#ifndef ES_I2C1_SDA_GPIO_PIN 
+#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_I2C1_SDA_PIN 
+#ifdef ES_PIN_GPIO_H_1 
+#define ES_I2C1_SDA_PIN ES_PIN_GPIO_H_1 
+#endif
+#endif 
+
+#ifndef ES_I2C1_SDA_GPIO_FUNC 
+#define ES_I2C1_SDA_GPIO_FUNC GPIO_FUNC_5 
+#endif 
+#ifndef ES_I2C1_SDA_GPIO_PORT 
+#define ES_I2C1_SDA_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_I2C1_SDA_GPIO_PIN 
+#define ES_I2C1_SDA_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_I2C1_SDA_PIN 
+#ifdef ES_PIN_GPIO_B_11 
+#define ES_I2C1_SDA_PIN ES_PIN_GPIO_B_11 
+#endif
+#endif 
+
+
+/* SPI_MISO */
+
+
+#ifndef ES_SPI0_MISO_GPIO_FUNC 
+#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_MISO_GPIO_PORT 
+#define ES_SPI0_MISO_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI0_MISO_GPIO_PIN 
+#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_SPI0_MISO_PIN 
+#ifdef ES_PIN_GPIO_B_4 
+#define ES_SPI0_MISO_PIN ES_PIN_GPIO_B_4 
+#endif
+#endif 
+
+#ifndef ES_SPI0_MISO_GPIO_FUNC 
+#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_SPI0_MISO_GPIO_PORT 
+#define ES_SPI0_MISO_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_SPI0_MISO_GPIO_PIN 
+#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_SPI0_MISO_PIN 
+#ifdef ES_PIN_GPIO_A_6 
+#define ES_SPI0_MISO_PIN ES_PIN_GPIO_A_6 
+#endif
+#endif 
+
+#ifndef ES_SPI0_MISO_GPIO_FUNC 
+#define ES_SPI0_MISO_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_MISO_GPIO_PORT 
+#define ES_SPI0_MISO_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_SPI0_MISO_GPIO_PIN 
+#define ES_SPI0_MISO_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_SPI0_MISO_PIN 
+#ifdef ES_PIN_GPIO_D_4 
+#define ES_SPI0_MISO_PIN ES_PIN_GPIO_D_4 
+#endif
+#endif 
+
+#ifndef ES_SPI1_MISO_GPIO_FUNC 
+#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_MISO_GPIO_PORT 
+#define ES_SPI1_MISO_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_SPI1_MISO_GPIO_PIN 
+#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_SPI1_MISO_PIN 
+#ifdef ES_PIN_GPIO_C_2 
+#define ES_SPI1_MISO_PIN ES_PIN_GPIO_C_2 
+#endif
+#endif 
+
+#ifndef ES_SPI1_MISO_GPIO_FUNC 
+#define ES_SPI1_MISO_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_MISO_GPIO_PORT 
+#define ES_SPI1_MISO_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI1_MISO_GPIO_PIN 
+#define ES_SPI1_MISO_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_SPI1_MISO_PIN 
+#ifdef ES_PIN_GPIO_B_14 
+#define ES_SPI1_MISO_PIN ES_PIN_GPIO_B_14 
+#endif
+#endif 
+
+
+/* SPI_MOSI */
+
+
+#ifndef ES_SPI0_MOSI_GPIO_FUNC 
+#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_MOSI_GPIO_PORT 
+#define ES_SPI0_MOSI_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI0_MOSI_GPIO_PIN 
+#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_SPI0_MOSI_PIN 
+#ifdef ES_PIN_GPIO_B_5 
+#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_B_5 
+#endif
+#endif 
+
+#ifndef ES_SPI0_MOSI_GPIO_FUNC 
+#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_SPI0_MOSI_GPIO_PORT 
+#define ES_SPI0_MOSI_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_SPI0_MOSI_GPIO_PIN 
+#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_SPI0_MOSI_PIN 
+#ifdef ES_PIN_GPIO_A_7 
+#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_A_7 
+#endif
+#endif 
+
+
+#ifndef ES_SPI0_MOSI_GPIO_FUNC 
+#define ES_SPI0_MOSI_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_MOSI_GPIO_PORT 
+#define ES_SPI0_MOSI_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_SPI0_MOSI_GPIO_PIN 
+#define ES_SPI0_MOSI_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_SPI0_MOSI_PIN 
+#ifdef ES_PIN_GPIO_D_7 
+#define ES_SPI0_MOSI_PIN ES_PIN_GPIO_D_7 
+#endif
+#endif 
+
+#ifndef ES_SPI1_MOSI_GPIO_FUNC 
+#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_MOSI_GPIO_PORT 
+#define ES_SPI1_MOSI_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI1_MOSI_GPIO_PIN 
+#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_15 
+#endif 
+
+#ifndef ES_SPI1_MOSI_PIN 
+#ifdef ES_PIN_GPIO_B_15 
+#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_B_15 
+#endif
+#endif 
+
+#ifndef ES_SPI1_MOSI_GPIO_FUNC 
+#define ES_SPI1_MOSI_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_MOSI_GPIO_PORT 
+#define ES_SPI1_MOSI_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_SPI1_MOSI_GPIO_PIN 
+#define ES_SPI1_MOSI_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_SPI1_MOSI_PIN 
+#ifdef ES_PIN_GPIO_C_3 
+#define ES_SPI1_MOSI_PIN ES_PIN_GPIO_C_3 
+#endif
+#endif 
+
+
+/* SPI_SCK */
+
+
+#ifndef ES_SPI0_SCK_GPIO_FUNC 
+#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_SCK_GPIO_PORT 
+#define ES_SPI0_SCK_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI0_SCK_GPIO_PIN 
+#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_SPI0_SCK_PIN 
+#ifdef ES_PIN_GPIO_B_3 
+#define ES_SPI0_SCK_PIN ES_PIN_GPIO_B_3 
+#endif
+#endif 
+
+#ifndef ES_SPI0_SCK_GPIO_FUNC 
+#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_SPI0_SCK_GPIO_PORT 
+#define ES_SPI0_SCK_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_SPI0_SCK_GPIO_PIN 
+#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_SPI0_SCK_PIN 
+#ifdef ES_PIN_GPIO_A_5 
+#define ES_SPI0_SCK_PIN ES_PIN_GPIO_A_5 
+#endif
+#endif 
+
+#ifndef ES_SPI0_SCK_GPIO_FUNC 
+#define ES_SPI0_SCK_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_SCK_GPIO_PORT 
+#define ES_SPI0_SCK_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_SPI0_SCK_GPIO_PIN 
+#define ES_SPI0_SCK_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_SPI0_SCK_PIN 
+#ifdef ES_PIN_GPIO_D_3 
+#define ES_SPI0_SCK_PIN ES_PIN_GPIO_D_3 
+#endif
+#endif 
+
+#ifndef ES_SPI1_SCK_GPIO_FUNC 
+#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_SCK_GPIO_PORT 
+#define ES_SPI1_SCK_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI1_SCK_GPIO_PIN 
+#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_SPI1_SCK_PIN 
+#ifdef ES_PIN_GPIO_B_13 
+#define ES_SPI1_SCK_PIN ES_PIN_GPIO_B_13 
+#endif
+#endif 
+
+#ifndef ES_SPI1_SCK_GPIO_FUNC 
+#define ES_SPI1_SCK_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_SCK_GPIO_PORT 
+#define ES_SPI1_SCK_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_SPI1_SCK_GPIO_PIN 
+#define ES_SPI1_SCK_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_SPI1_SCK_PIN 
+#ifdef ES_PIN_GPIO_C_1 
+#define ES_SPI1_SCK_PIN ES_PIN_GPIO_C_1 
+#endif
+#endif 
+
+
+/* SPI_NSS */
+
+
+#ifndef ES_SPI0_NSS_GPIO_FUNC 
+#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_SPI0_NSS_GPIO_PORT 
+#define ES_SPI0_NSS_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_SPI0_NSS_GPIO_PIN 
+#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_SPI0_NSS_PIN 
+#ifdef ES_PIN_GPIO_A_4 
+#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_4 
+#endif
+#endif 
+
+#ifndef ES_SPI0_NSS_GPIO_FUNC 
+#define ES_SPI0_NSS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI0_NSS_GPIO_PORT 
+#define ES_SPI0_NSS_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_SPI0_NSS_GPIO_PIN 
+#define ES_SPI0_NSS_GPIO_PIN GPIO_PIN_15 
+#endif 
+
+#ifndef ES_SPI0_NSS_PIN 
+#ifdef ES_PIN_GPIO_A_15 
+#define ES_SPI0_NSS_PIN ES_PIN_GPIO_A_15 
+#endif
+#endif 
+
+#ifndef ES_SPI1_NSS_GPIO_FUNC 
+#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_NSS_GPIO_PORT 
+#define ES_SPI1_NSS_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_SPI1_NSS_GPIO_PIN 
+#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_SPI1_NSS_PIN 
+#ifdef ES_PIN_GPIO_C_0 
+#define ES_SPI1_NSS_PIN ES_PIN_GPIO_C_0 
+#endif
+#endif 
+
+#ifndef ES_SPI1_NSS_GPIO_FUNC 
+#define ES_SPI1_NSS_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_SPI1_NSS_GPIO_PORT 
+#define ES_SPI1_NSS_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_SPI1_NSS_GPIO_PIN 
+#define ES_SPI1_NSS_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_SPI1_NSS_PIN 
+#ifdef ES_PIN_GPIO_B_12 
+#define ES_SPI1_NSS_PIN ES_PIN_GPIO_B_12 
+#endif
+#endif 
+
+
+/* CAN_TX */
+
+
+#ifndef ES_CAN0_TX_GPIO_FUNC 
+#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_CAN0_TX_GPIO_PORT 
+#define ES_CAN0_TX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_CAN0_TX_GPIO_PIN 
+#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_CAN0_TX_PIN 
+#ifdef ES_PIN_GPIO_A_12 
+#define ES_CAN0_TX_PIN ES_PIN_GPIO_A_12 
+#endif
+#endif 
+
+#ifndef ES_CAN0_TX_GPIO_FUNC 
+#define ES_CAN0_TX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_CAN0_TX_GPIO_PORT 
+#define ES_CAN0_TX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_CAN0_TX_GPIO_PIN 
+#define ES_CAN0_TX_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_CAN0_TX_PIN 
+#ifdef ES_PIN_GPIO_B_9 
+#define ES_CAN0_TX_PIN ES_PIN_GPIO_B_9 
+#endif
+#endif 
+
+
+/* CAN_RX */
+
+
+#ifndef ES_CAN0_RX_GPIO_FUNC 
+#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_CAN0_RX_GPIO_PORT 
+#define ES_CAN0_RX_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_CAN0_RX_GPIO_PIN 
+#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_CAN0_RX_PIN 
+#ifdef ES_PIN_GPIO_A_11 
+#define ES_CAN0_RX_PIN ES_PIN_GPIO_A_11 
+#endif
+#endif 
+
+#ifndef ES_CAN0_RX_GPIO_FUNC 
+#define ES_CAN0_RX_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_CAN0_RX_GPIO_PORT 
+#define ES_CAN0_RX_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_CAN0_RX_GPIO_PIN 
+#define ES_CAN0_RX_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_CAN0_RX_PIN 
+#ifdef ES_PIN_GPIO_B_8 
+#define ES_CAN0_RX_PIN ES_PIN_GPIO_B_8 
+#endif
+#endif 
+
+
+/* AD16C4T_CH1 */
+
+
+#ifndef ES_AD16C4T0_CH1_GPIO_FUNC 
+#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH1_GPIO_PORT 
+#define ES_AD16C4T0_CH1_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_AD16C4T0_CH1_GPIO_PIN 
+#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_AD16C4T0_CH1_PIN 
+#ifdef ES_PIN_GPIO_A_8 
+#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_A_8 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH1_GPIO_FUNC 
+#define ES_AD16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH1_GPIO_PORT 
+#define ES_AD16C4T0_CH1_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH1_GPIO_PIN 
+#define ES_AD16C4T0_CH1_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_AD16C4T0_CH1_PIN 
+#ifdef ES_PIN_GPIO_E_9 
+#define ES_AD16C4T0_CH1_PIN ES_PIN_GPIO_E_9 
+#endif
+#endif 
+
+
+/* AD16C4T_CH2 */
+
+
+#ifndef ES_AD16C4T0_CH2_GPIO_FUNC 
+#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH2_GPIO_PORT 
+#define ES_AD16C4T0_CH2_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_AD16C4T0_CH2_GPIO_PIN 
+#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_AD16C4T0_CH2_PIN 
+#ifdef ES_PIN_GPIO_A_9 
+#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_A_9 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH2_GPIO_FUNC 
+#define ES_AD16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH2_GPIO_PORT 
+#define ES_AD16C4T0_CH2_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH2_GPIO_PIN 
+#define ES_AD16C4T0_CH2_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_AD16C4T0_CH2_PIN 
+#ifdef ES_PIN_GPIO_E_11 
+#define ES_AD16C4T0_CH2_PIN ES_PIN_GPIO_E_11 
+#endif
+#endif 
+
+
+/* AD16C4T_CH3 */
+
+
+#ifndef ES_AD16C4T0_CH3_GPIO_FUNC 
+#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH3_GPIO_PORT 
+#define ES_AD16C4T0_CH3_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_AD16C4T0_CH3_GPIO_PIN 
+#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_AD16C4T0_CH3_PIN 
+#ifdef ES_PIN_GPIO_A_10 
+#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_A_10 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH3_GPIO_FUNC 
+#define ES_AD16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH3_GPIO_PORT 
+#define ES_AD16C4T0_CH3_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH3_GPIO_PIN 
+#define ES_AD16C4T0_CH3_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_AD16C4T0_CH3_PIN 
+#ifdef ES_PIN_GPIO_E_13 
+#define ES_AD16C4T0_CH3_PIN ES_PIN_GPIO_E_13 
+#endif
+#endif 
+
+
+/* AD16C4T_CH4 */
+
+
+#ifndef ES_AD16C4T0_CH4_GPIO_FUNC 
+#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH4_GPIO_PORT 
+#define ES_AD16C4T0_CH4_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH4_GPIO_PIN 
+#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_AD16C4T0_CH4_PIN 
+#ifdef ES_PIN_GPIO_E_14 
+#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_E_14 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH4_GPIO_FUNC 
+#define ES_AD16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH4_GPIO_PORT 
+#define ES_AD16C4T0_CH4_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_AD16C4T0_CH4_GPIO_PIN 
+#define ES_AD16C4T0_CH4_GPIO_PIN GPIO_PIN_11 
+#endif 
+
+#ifndef ES_AD16C4T0_CH4_PIN 
+#ifdef ES_PIN_GPIO_A_11 
+#define ES_AD16C4T0_CH4_PIN ES_PIN_GPIO_A_11 
+#endif
+#endif 
+
+
+/* AD16C4T_CH1N */
+
+
+#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC 
+#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_4 
+#endif 
+#ifndef ES_AD16C4T0_CH1N_GPIO_PORT 
+#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_AD16C4T0_CH1N_GPIO_PIN 
+#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_AD16C4T0_CH1N_PIN 
+#ifdef ES_PIN_GPIO_A_7 
+#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_A_7 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC 
+#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH1N_GPIO_PORT 
+#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_AD16C4T0_CH1N_GPIO_PIN 
+#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_AD16C4T0_CH1N_PIN 
+#ifdef ES_PIN_GPIO_B_13 
+#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_B_13 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH1N_GPIO_FUNC 
+#define ES_AD16C4T0_CH1N_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH1N_GPIO_PORT 
+#define ES_AD16C4T0_CH1N_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH1N_GPIO_PIN 
+#define ES_AD16C4T0_CH1N_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_AD16C4T0_CH1N_PIN 
+#ifdef ES_PIN_GPIO_E_8 
+#define ES_AD16C4T0_CH1N_PIN ES_PIN_GPIO_E_8 
+#endif
+#endif 
+
+
+/* AD16C4T_CH2N */
+
+
+#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC 
+#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_AD16C4T0_CH2N_GPIO_PORT 
+#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_AD16C4T0_CH2N_GPIO_PIN 
+#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_AD16C4T0_CH2N_PIN 
+#ifdef ES_PIN_GPIO_B_0 
+#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_0 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC 
+#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH2N_GPIO_PORT 
+#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_AD16C4T0_CH2N_GPIO_PIN 
+#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_AD16C4T0_CH2N_PIN 
+#ifdef ES_PIN_GPIO_B_14 
+#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_B_14 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH2N_GPIO_FUNC 
+#define ES_AD16C4T0_CH2N_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH2N_GPIO_PORT 
+#define ES_AD16C4T0_CH2N_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH2N_GPIO_PIN 
+#define ES_AD16C4T0_CH2N_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_AD16C4T0_CH2N_PIN 
+#ifdef ES_PIN_GPIO_E_10 
+#define ES_AD16C4T0_CH2N_PIN ES_PIN_GPIO_E_10 
+#endif
+#endif 
+
+
+/* AD16C4T_CH3N */
+
+
+#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC 
+#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_AD16C4T0_CH3N_GPIO_PORT 
+#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_AD16C4T0_CH3N_GPIO_PIN 
+#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_AD16C4T0_CH3N_PIN 
+#ifdef ES_PIN_GPIO_B_1 
+#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_1 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC 
+#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH3N_GPIO_PORT 
+#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_AD16C4T0_CH3N_GPIO_PIN 
+#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_15 
+#endif 
+
+#ifndef ES_AD16C4T0_CH3N_PIN 
+#ifdef ES_PIN_GPIO_B_15 
+#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_B_15 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_CH3N_GPIO_FUNC 
+#define ES_AD16C4T0_CH3N_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_CH3N_GPIO_PORT 
+#define ES_AD16C4T0_CH3N_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_CH3N_GPIO_PIN 
+#define ES_AD16C4T0_CH3N_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_AD16C4T0_CH3N_PIN 
+#ifdef ES_PIN_GPIO_E_12 
+#define ES_AD16C4T0_CH3N_PIN ES_PIN_GPIO_E_12 
+#endif
+#endif 
+
+
+/* AD16C4T_CH4N */
+
+
+
+/* AD16C4T_ET */
+
+
+#ifndef ES_AD16C4T0_ET_GPIO_FUNC 
+#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_ET_GPIO_PORT 
+#define ES_AD16C4T0_ET_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_AD16C4T0_ET_GPIO_PIN 
+#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_AD16C4T0_ET_PIN 
+#ifdef ES_PIN_GPIO_A_12 
+#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_A_12 
+#endif
+#endif 
+
+#ifndef ES_AD16C4T0_ET_GPIO_FUNC 
+#define ES_AD16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_AD16C4T0_ET_GPIO_PORT 
+#define ES_AD16C4T0_ET_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_AD16C4T0_ET_GPIO_PIN 
+#define ES_AD16C4T0_ET_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_AD16C4T0_ET_PIN 
+#ifdef ES_PIN_GPIO_E_7 
+#define ES_AD16C4T0_ET_PIN ES_PIN_GPIO_E_7 
+#endif
+#endif 
+
+
+/* GP32C4T_CH1 */
+
+
+
+/* GP32C4T_CH2 */
+
+
+
+/* GP32C4T_CH3 */
+
+
+
+/* GP32C4T_CH4 */
+
+
+
+/* GP32C4T_ET */
+
+
+
+/* GP16C4T_CH1 */
+
+
+#ifndef ES_GP16C4T0_CH1_GPIO_FUNC 
+#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH1_GPIO_PORT 
+#define ES_GP16C4T0_CH1_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C4T0_CH1_GPIO_PIN 
+#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_GP16C4T0_CH1_PIN 
+#ifdef ES_PIN_GPIO_B_6 
+#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_B_6 
+#endif
+#endif 
+
+#ifndef ES_GP16C4T0_CH1_GPIO_FUNC 
+#define ES_GP16C4T0_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH1_GPIO_PORT 
+#define ES_GP16C4T0_CH1_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_GP16C4T0_CH1_GPIO_PIN 
+#define ES_GP16C4T0_CH1_GPIO_PIN GPIO_PIN_12 
+#endif 
+
+#ifndef ES_GP16C4T0_CH1_PIN 
+#ifdef ES_PIN_GPIO_D_12 
+#define ES_GP16C4T0_CH1_PIN ES_PIN_GPIO_D_12 
+#endif
+#endif 
+
+
+/* GP16C4T_CH2 */
+
+
+#ifndef ES_GP16C4T0_CH2_GPIO_FUNC 
+#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH2_GPIO_PORT 
+#define ES_GP16C4T0_CH2_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C4T0_CH2_GPIO_PIN 
+#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_GP16C4T0_CH2_PIN 
+#ifdef ES_PIN_GPIO_B_7 
+#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_B_7 
+#endif
+#endif 
+
+#ifndef ES_GP16C4T0_CH2_GPIO_FUNC 
+#define ES_GP16C4T0_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH2_GPIO_PORT 
+#define ES_GP16C4T0_CH2_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_GP16C4T0_CH2_GPIO_PIN 
+#define ES_GP16C4T0_CH2_GPIO_PIN GPIO_PIN_13 
+#endif 
+
+#ifndef ES_GP16C4T0_CH2_PIN 
+#ifdef ES_PIN_GPIO_D_13 
+#define ES_GP16C4T0_CH2_PIN ES_PIN_GPIO_D_13 
+#endif
+#endif 
+
+
+/* GP16C4T_CH3 */
+
+
+#ifndef ES_GP16C4T0_CH3_GPIO_FUNC 
+#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH3_GPIO_PORT 
+#define ES_GP16C4T0_CH3_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_GP16C4T0_CH3_GPIO_PIN 
+#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_14 
+#endif 
+
+#ifndef ES_GP16C4T0_CH3_PIN 
+#ifdef ES_PIN_GPIO_D_14 
+#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_D_14 
+#endif
+#endif 
+
+#ifndef ES_GP16C4T0_CH3_GPIO_FUNC 
+#define ES_GP16C4T0_CH3_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH3_GPIO_PORT 
+#define ES_GP16C4T0_CH3_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C4T0_CH3_GPIO_PIN 
+#define ES_GP16C4T0_CH3_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_GP16C4T0_CH3_PIN 
+#ifdef ES_PIN_GPIO_B_8 
+#define ES_GP16C4T0_CH3_PIN ES_PIN_GPIO_B_8 
+#endif
+#endif 
+
+
+/* GP16C4T_CH4 */
+
+
+#ifndef ES_GP16C4T0_CH4_GPIO_FUNC 
+#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH4_GPIO_PORT 
+#define ES_GP16C4T0_CH4_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C4T0_CH4_GPIO_PIN 
+#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_9 
+#endif 
+
+#ifndef ES_GP16C4T0_CH4_PIN 
+#ifdef ES_PIN_GPIO_B_9 
+#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_B_9 
+#endif
+#endif 
+
+#ifndef ES_GP16C4T0_CH4_GPIO_FUNC 
+#define ES_GP16C4T0_CH4_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_CH4_GPIO_PORT 
+#define ES_GP16C4T0_CH4_GPIO_PORT GPIOD 
+#endif 
+#ifndef ES_GP16C4T0_CH4_GPIO_PIN 
+#define ES_GP16C4T0_CH4_GPIO_PIN GPIO_PIN_15 
+#endif 
+
+#ifndef ES_GP16C4T0_CH4_PIN 
+#ifdef ES_PIN_GPIO_D_15 
+#define ES_GP16C4T0_CH4_PIN ES_PIN_GPIO_D_15 
+#endif
+#endif 
+
+
+/* GP16C4T_ET */
+
+
+#ifndef ES_GP16C4T0_ET_GPIO_FUNC 
+#define ES_GP16C4T0_ET_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C4T0_ET_GPIO_PORT 
+#define ES_GP16C4T0_ET_GPIO_PORT GPIOE 
+#endif 
+#ifndef ES_GP16C4T0_ET_GPIO_PIN 
+#define ES_GP16C4T0_ET_GPIO_PIN GPIO_PIN_0 
+#endif 
+
+#ifndef ES_GP16C4T0_ET_PIN 
+#ifdef ES_PIN_GPIO_E_0 
+#define ES_GP16C4T0_ET_PIN ES_PIN_GPIO_E_0 
+#endif
+#endif 
+
+
+/* GP16C2T_CH1 */
+
+
+#ifndef ES_GP16C2T0_CH1_GPIO_FUNC 
+#define ES_GP16C2T0_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C2T0_CH1_GPIO_PORT 
+#define ES_GP16C2T0_CH1_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_GP16C2T0_CH1_GPIO_PIN 
+#define ES_GP16C2T0_CH1_GPIO_PIN GPIO_PIN_15 
+#endif 
+
+#ifndef ES_GP16C2T0_CH1_PIN 
+#ifdef ES_PIN_GPIO_A_15 
+#define ES_GP16C2T0_CH1_PIN ES_PIN_GPIO_A_15 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T0_CH1_GPIO_FUNC 
+#define ES_GP16C2T0_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C2T0_CH1_GPIO_PORT 
+#define ES_GP16C2T0_CH1_GPIO_PORT GPIOF 
+#endif 
+#ifndef ES_GP16C2T0_CH1_GPIO_PIN 
+#define ES_GP16C2T0_CH1_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_GP16C2T0_CH1_PIN 
+#ifdef ES_PIN_GPIO_F_7 
+#define ES_GP16C2T0_CH1_PIN ES_PIN_GPIO_F_7 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH1_GPIO_FUNC 
+#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_GP16C2T1_CH1_GPIO_PORT 
+#define ES_GP16C2T1_CH1_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_GP16C2T1_CH1_GPIO_PIN 
+#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_GP16C2T1_CH1_PIN 
+#ifdef ES_PIN_GPIO_A_6 
+#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_A_6 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH1_GPIO_FUNC 
+#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_GP16C2T1_CH1_GPIO_PORT 
+#define ES_GP16C2T1_CH1_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_GP16C2T1_CH1_GPIO_PIN 
+#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_6 
+#endif 
+
+#ifndef ES_GP16C2T1_CH1_PIN 
+#ifdef ES_PIN_GPIO_C_6 
+#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_C_6 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH1_GPIO_FUNC 
+#define ES_GP16C2T1_CH1_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C2T1_CH1_GPIO_PORT 
+#define ES_GP16C2T1_CH1_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C2T1_CH1_GPIO_PIN 
+#define ES_GP16C2T1_CH1_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_GP16C2T1_CH1_PIN 
+#ifdef ES_PIN_GPIO_B_4 
+#define ES_GP16C2T1_CH1_PIN ES_PIN_GPIO_B_4 
+#endif
+#endif 
+
+
+/* GP16C2T_CH2 */
+
+
+#ifndef ES_GP16C2T0_CH2_GPIO_FUNC 
+#define ES_GP16C2T0_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C2T0_CH2_GPIO_PORT 
+#define ES_GP16C2T0_CH2_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_GP16C2T0_CH2_GPIO_PIN 
+#define ES_GP16C2T0_CH2_GPIO_PIN GPIO_PIN_1 
+#endif 
+
+#ifndef ES_GP16C2T0_CH2_PIN 
+#ifdef ES_PIN_GPIO_A_1 
+#define ES_GP16C2T0_CH2_PIN ES_PIN_GPIO_A_1 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T0_CH2_GPIO_FUNC 
+#define ES_GP16C2T0_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C2T0_CH2_GPIO_PORT 
+#define ES_GP16C2T0_CH2_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C2T0_CH2_GPIO_PIN 
+#define ES_GP16C2T0_CH2_GPIO_PIN GPIO_PIN_3 
+#endif 
+
+#ifndef ES_GP16C2T0_CH2_PIN 
+#ifdef ES_PIN_GPIO_B_3 
+#define ES_GP16C2T0_CH2_PIN ES_PIN_GPIO_B_3 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH2_GPIO_FUNC 
+#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_GP16C2T1_CH2_GPIO_PORT 
+#define ES_GP16C2T1_CH2_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_GP16C2T1_CH2_GPIO_PIN 
+#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_GP16C2T1_CH2_PIN 
+#ifdef ES_PIN_GPIO_A_7 
+#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_A_7 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH2_GPIO_FUNC 
+#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_3 
+#endif 
+#ifndef ES_GP16C2T1_CH2_GPIO_PORT 
+#define ES_GP16C2T1_CH2_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_GP16C2T1_CH2_GPIO_PIN 
+#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_7 
+#endif 
+
+#ifndef ES_GP16C2T1_CH2_PIN 
+#ifdef ES_PIN_GPIO_C_7 
+#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_C_7 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH2_GPIO_FUNC 
+#define ES_GP16C2T1_CH2_GPIO_FUNC GPIO_FUNC_2 
+#endif 
+#ifndef ES_GP16C2T1_CH2_GPIO_PORT 
+#define ES_GP16C2T1_CH2_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C2T1_CH2_GPIO_PIN 
+#define ES_GP16C2T1_CH2_GPIO_PIN GPIO_PIN_5 
+#endif 
+
+#ifndef ES_GP16C2T1_CH2_PIN 
+#ifdef ES_PIN_GPIO_B_5 
+#define ES_GP16C2T1_CH2_PIN ES_PIN_GPIO_B_5 
+#endif
+#endif 
+
+
+/* GP16C2T_CH1N */
+
+
+#ifndef ES_GP16C2T0_CH1N_GPIO_FUNC 
+#define ES_GP16C2T0_CH1N_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_GP16C2T0_CH1N_GPIO_PORT 
+#define ES_GP16C2T0_CH1N_GPIO_PORT GPIOA 
+#endif 
+#ifndef ES_GP16C2T0_CH1N_GPIO_PIN 
+#define ES_GP16C2T0_CH1N_GPIO_PIN GPIO_PIN_2 
+#endif 
+
+#ifndef ES_GP16C2T0_CH1N_PIN 
+#ifdef ES_PIN_GPIO_A_2 
+#define ES_GP16C2T0_CH1N_PIN ES_PIN_GPIO_A_2 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T0_CH1N_GPIO_FUNC 
+#define ES_GP16C2T0_CH1N_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_GP16C2T0_CH1N_GPIO_PORT 
+#define ES_GP16C2T0_CH1N_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_GP16C2T0_CH1N_GPIO_PIN 
+#define ES_GP16C2T0_CH1N_GPIO_PIN GPIO_PIN_10 
+#endif 
+
+#ifndef ES_GP16C2T0_CH1N_PIN 
+#ifdef ES_PIN_GPIO_C_10 
+#define ES_GP16C2T0_CH1N_PIN ES_PIN_GPIO_C_10 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH1N_GPIO_FUNC 
+#define ES_GP16C2T1_CH1N_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_GP16C2T1_CH1N_GPIO_PORT 
+#define ES_GP16C2T1_CH1N_GPIO_PORT GPIOC 
+#endif 
+#ifndef ES_GP16C2T1_CH1N_GPIO_PIN 
+#define ES_GP16C2T1_CH1N_GPIO_PIN GPIO_PIN_4 
+#endif 
+
+#ifndef ES_GP16C2T1_CH1N_PIN 
+#ifdef ES_PIN_GPIO_C_4 
+#define ES_GP16C2T1_CH1N_PIN ES_PIN_GPIO_C_4 
+#endif
+#endif 
+
+#ifndef ES_GP16C2T1_CH1N_GPIO_FUNC 
+#define ES_GP16C2T1_CH1N_GPIO_FUNC GPIO_FUNC_6 
+#endif 
+#ifndef ES_GP16C2T1_CH1N_GPIO_PORT 
+#define ES_GP16C2T1_CH1N_GPIO_PORT GPIOB 
+#endif 
+#ifndef ES_GP16C2T1_CH1N_GPIO_PIN 
+#define ES_GP16C2T1_CH1N_GPIO_PIN GPIO_PIN_8 
+#endif 
+
+#ifndef ES_GP16C2T1_CH1N_PIN 
+#ifdef ES_PIN_GPIO_B_8 
+#define ES_GP16C2T1_CH1N_PIN ES_PIN_GPIO_B_8 
+#endif
+#endif 
+
+
+/* GP16C2T_CH2N */
+
+
+
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_pm.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_PM_H__
+#define __ES_CONF_INFO_PM_H__
+
+#include <ald_cmu.h>
+#include <ald_pmu.h>
+
+#define ES_PMU_SAVE_LOAD_UART 
+
+/* PM 配置 */
+
+ 
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_pwm.h

@@ -0,0 +1,72 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_PWM_H__
+#define __ES_CONF_INFO_PWM_H__
+
+#include "es_conf_info_map.h"
+#include <ald_cmu.h>
+#include <ald_timer.h>
+#include <ald_gpio.h>
+
+
+#define ES_C_PWM_OC_POL_HIGH   TIMER_OC_POLARITY_HIGH
+#define ES_C_PWM_OC_POL_LOW    TIMER_OC_POLARITY_LOW
+
+#define  ES_C_PWM_OC_MODE_PWM1     TIMER_OC_MODE_PWM1
+#define  ES_C_PWM_OC_MODE_PWM2     TIMER_OC_MODE_PWM2
+
+
+    
+/* PWM 配置 */
+
+
+/* codes_main */
+
+
+
+#define ES_PWM_OC_POLARITY   ES_C_PWM_OC_POL_HIGH
+#define ES_PWM_OC_MODE       ES_C_PWM_OC_MODE_PWM1
+
+#ifndef ES_PWM_OC_POLARITY
+#define ES_PWM_OC_POLARITY   ES_C_PWM_OC_POL_HIGH
+#endif    
+#ifndef ES_PWM_OC_MODE 
+#define ES_PWM_OC_MODE       ES_C_PWM_OC_MODE_PWM2
+#endif
+
+#ifndef  ES_DEVICE_NAME_AD16C4T0_PWM
+#define  ES_DEVICE_NAME_AD16C4T0_PWM     "pwm0"
+#endif          
+#ifndef  ES_DEVICE_NAME_GP16C4T0_PWM
+#define  ES_DEVICE_NAME_GP16C4T0_PWM     "pwm1"
+#endif              
+#ifndef  ES_DEVICE_NAME_GP16C2T0_PWM
+#define  ES_DEVICE_NAME_GP16C2T0_PWM     "pwm2"
+#endif              
+#ifndef  ES_DEVICE_NAME_GP16C2T1_PWM
+#define  ES_DEVICE_NAME_GP16C2T1_PWM     "pwm3"
+#endif              
+
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_rtc.h

@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_RTC_H__
+#define __ES_CONF_INFO_RTC_H__
+
+#include <ald_cmu.h>
+#include <ald_rtc.h>
+
+/* RTC 配置 */
+
+#define ES_C_RTC_SOURCE_LRC      RTC_SOURCE_LRC
+#define ES_C_RTC_SOURCE_LOSC      RTC_SOURCE_LOSC
+
+#define ES_RTC_CLK_SOURCE        ES_C_RTC_SOURCE_LOSC
+
+
+
+
+/* codes_main */
+
+
+#ifndef  ES_DEVICE_NAME_RTC
+#define  ES_DEVICE_NAME_RTC     "rtc"
+#endif 
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_select.h

@@ -0,0 +1,44 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_SELECT_H__
+#define __ES_CONF_INFO_SELECT_H__
+
+
+#define ES_C_ENABLE     1
+#define ES_C_DISABLE    0
+    
+
+/* codes_main */
+//#define  ES_USE_ASSERT    ES_C_ENABLE
+
+#ifndef  ES_USE_ASSERT
+#define  ES_USE_ASSERT    ES_C_DISABLE
+#endif
+
+
+#if ES_USE_ASSERT 
+    #define USE_ASSERT
+#endif
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_spi.h

@@ -0,0 +1,132 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_SPI_H__
+#define __ES_CONF_INFO_SPI_H__
+
+#include "es_conf_info_map.h"
+#include <ald_spi.h>
+#include <ald_gpio.h>
+#include <ald_cmu.h>
+
+/* SPI 配置 */
+
+#define SPI_BUS_CONFIG(_CONF_,_I_)       do{_CONF_.mode = 0U;                                         \
+                                            _CONF_.mode |= ( ES_SPI##_I_##_MASTER_SLAVE |             \
+                                                             ES_SPI##_I_##_WIRE_3_4     |             \
+                                                             ES_SPI##_I_##_CPHA_1_2     |             \
+                                                             ES_SPI##_I_##_CPOL_H_L     |             \
+                                                             ES_SPI##_I_##_CS           |             \
+                                                             ES_SPI##_I_##_M_L_SB          );         \
+                                            _CONF_.data_width = ES_SPI##_I_##_DATA_W;                 \
+                                            _CONF_.max_hz = ES_SPI##_I_##_MAX_HZ;                     \
+                                            }while(0)
+
+                                            
+//    spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
+//    spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
+//    spi_config.mode |= RT_SPI_CPHA;   /* 第二边沿采样 */
+//    spi_config.mode |= RT_SPI_CPOL;   /* 空闲高电平 */
+//    spi_config.mode |= RT_SPI_NO_CS;  /* 禁用软件从机选择管理 */
+//    spi_config.mode |= RT_SPI_MSB;    /* 高位在前 */
+//    spi_config.data_width = 8;        /* 数据长度：8 */
+//    spi_config.max_hz = 2000000;      /* 最快时钟频率 */
+
+#define ES_C_SPI_CLK_POL_HIGH            RT_SPI_CPOL  
+#define ES_C_SPI_CLK_POL_LOW             !RT_SPI_CPOL    
+                                            
+#define ES_C_SPI_CLK_PHA_FIRST            !RT_SPI_CPHA  
+#define ES_C_SPI_CLK_PHA_SECOND           RT_SPI_CPHA
+                                            
+#define ES_C_SPI_MSB                      RT_SPI_MSB     
+#define ES_C_SPI_LSB                      RT_SPI_LSB                      
+
+#define ES_C_SPI_CS_LOW_LEVEL             0
+#define ES_C_SPI_CS_HIGH_LEVEL            1
+
+/* codes_main */
+
+
+#ifndef  ES_DEVICE_NAME_SPI0_BUS
+#define  ES_DEVICE_NAME_SPI0_BUS     "spi0"
+#endif             
+#ifndef  ES_DEVICE_NAME_SPI0_DEV0
+#define  ES_DEVICE_NAME_SPI0_DEV0     "spi00"
+#endif           
+
+#ifndef  ES_DEVICE_NAME_SPI1_BUS
+#define  ES_DEVICE_NAME_SPI1_BUS     "spi1"
+#endif             
+#ifndef  ES_DEVICE_NAME_SPI1_DEV0
+#define  ES_DEVICE_NAME_SPI1_DEV0     "spi10"
+#endif    
+             
+
+#define ES_SPI_CS_LEVEL               ES_C_SPI_CS_LOW_LEVEL
+
+#ifndef   ES_SPI0_CPHA_1_2      
+#define   ES_SPI0_CPHA_1_2               ES_C_SPI_CLK_PHA_SECOND
+#endif                         
+#ifndef   ES_SPI0_CPOL_H_L      
+#define   ES_SPI0_CPOL_H_L               ES_C_SPI_CLK_POL_HIGH   
+#endif    
+#ifndef   ES_SPI0_M_L_SB
+#define   ES_SPI0_M_L_SB                 RT_SPI_MSB    
+#endif
+#ifndef   ES_SPI0_MAX_HZ        
+#define   ES_SPI0_MAX_HZ                 2000000
+#endif  
+#ifndef   ES_SPI0_NSS_PIN
+#define ES_SPI0_NSS_PIN 0xFFFFFFFF
+#endif     
+                                                                      
+#ifndef   ES_SPI1_CPHA_1_2      
+#define   ES_SPI1_CPHA_1_2               ES_C_SPI_CLK_PHA_SECOND
+#endif                         
+#ifndef   ES_SPI1_CPOL_H_L      
+#define   ES_SPI1_CPOL_H_L               ES_C_SPI_CLK_POL_HIGH   
+#endif        
+#ifndef   ES_SPI1_M_L_SB
+#define   ES_SPI1_M_L_SB                 RT_SPI_MSB    
+#endif
+#ifndef   ES_SPI1_MAX_HZ        
+#define   ES_SPI1_MAX_HZ                 2000000
+#endif  
+#ifndef   ES_SPI1_NSS_PIN
+#define ES_SPI1_NSS_PIN 0xFFFFFFFF
+#endif     
+              
+
+
+#define   ES_SPI0_MASTER_SLAVE           !RT_SPI_SLAVE
+#define   ES_SPI0_WIRE_3_4               !RT_SPI_3WIRE
+#define   ES_SPI0_CS                     RT_SPI_NO_CS
+#define   ES_SPI0_DATA_W                 8
+         
+#define   ES_SPI1_MASTER_SLAVE           !RT_SPI_SLAVE
+#define   ES_SPI1_WIRE_3_4               !RT_SPI_3WIRE
+#define   ES_SPI1_CS                     RT_SPI_NO_CS
+#define   ES_SPI1_DATA_W                 8
+         
+
+#endif

bsp/essemi/es32f0654/drivers/ES/es_conf_info_uart.h

@@ -0,0 +1,206 @@
+/*
+ *  Change Logs:
+ *  Date            Author          Notes
+ *  2021-04-20      liuhy          the first version
+ *
+ * Copyright (C) 2021 Shanghai Eastsoft Microelectronics Co., Ltd. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ */
+
+#ifndef __ES_CONF_INFO_UART_H__
+#define __ES_CONF_INFO_UART_H__
+
+#include "es_conf_info_map.h"
+#include <ald_gpio.h>
+#include <ald_uart.h>   
+#include <ald_usart.h>
+#include <ald_cmu.h>
+ 
+ 
+
+#define ES_C_UART_PARITY_NONE        PARITY_NONE    
+#define ES_C_UART_PARITY_ODD         PARITY_ODD
+#define ES_C_UART_PARITY_EVEN        PARITY_EVEN
+
+#define ES_C_UART_STOP_1          STOP_BITS_1  
+#define ES_C_UART_STOP_2          STOP_BITS_2
+
+
+/* UART 配置 */
+
+/* codes_main */
+
+
+
+#ifndef  ES_DEVICE_NAME_UART0
+#define  ES_DEVICE_NAME_UART0     "uart0"
+#endif       
+#ifndef  ES_DEVICE_NAME_UART1
+#define  ES_DEVICE_NAME_UART1     "uart1"
+#endif
+#ifndef  ES_DEVICE_NAME_UART2
+#define  ES_DEVICE_NAME_UART2     "uart2"
+#endif
+#ifndef  ES_DEVICE_NAME_UART3
+#define  ES_DEVICE_NAME_UART3     "uart3"
+#endif
+#ifndef  ES_DEVICE_NAME_USART0
+#define  ES_DEVICE_NAME_USART0     "usart0"
+#endif                                  
+#ifndef  ES_DEVICE_NAME_USART1
+#define  ES_DEVICE_NAME_USART1     "usart1"
+#endif
+
+#ifndef ES_CONF_UART0_BAUD_RATE
+#define ES_CONF_UART0_BAUD_RATE         115200  
+#endif
+#ifndef ES_CONF_UART0_PARITY
+#define ES_CONF_UART0_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_UART0_STOP_BITS
+#define ES_CONF_UART0_STOP_BITS        ES_C_UART_STOP_1
+#endif          
+
+#ifndef ES_CONF_UART1_BAUD_RATE
+#define ES_CONF_UART1_BAUD_RATE         115200  
+#endif
+#ifndef ES_CONF_UART1_PARITY
+#define ES_CONF_UART1_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_UART1_STOP_BITS
+#define ES_CONF_UART1_STOP_BITS        ES_C_UART_STOP_1
+#endif           
+
+#ifndef ES_CONF_UART2_BAUD_RATE
+#define ES_CONF_UART2_BAUD_RATE         115200  
+#endif
+#ifndef ES_CONF_UART2_PARITY
+#define ES_CONF_UART2_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_UART2_STOP_BITS
+#define ES_CONF_UART2_STOP_BITS        ES_C_UART_STOP_1
+#endif   
+
+#ifndef ES_CONF_UART3_BAUD_RATE
+#define ES_CONF_UART3_BAUD_RATE         115200  
+#endif
+#ifndef ES_CONF_UART3_PARITY
+#define ES_CONF_UART3_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_UART3_STOP_BITS
+#define ES_CONF_UART3_STOP_BITS        ES_C_UART_STOP_1
+#endif   
+
+#ifndef ES_CONF_USART0_BAUD_RATE
+#define ES_CONF_USART0_BAUD_RATE         115200  
+#endif
+#ifndef ES_CONF_USART0_PARITY
+#define ES_CONF_USART0_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_USART0_STOP_BITS
+#define ES_CONF_USART0_STOP_BITS        ES_C_UART_STOP_1
+#endif   
+
+#ifndef ES_CONF_USART1_BAUD_RATE
+#define ES_CONF_USART1_BAUD_RATE         115200  
+#endif
+#ifndef ES_CONF_USART1_PARITY
+#define ES_CONF_USART1_PARITY         ES_C_UART_PARITY_NONE
+#endif
+#ifndef ES_CONF_USART1_STOP_BITS
+#define ES_CONF_USART1_STOP_BITS        ES_C_UART_STOP_1
+#endif   
+
+                                     
+#define ES_UART0_CONFIG                         \
+{                                               \
+    ES_CONF_UART0_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_UART0_STOP_BITS,                                \
+    ES_CONF_UART0_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+        
+
+#define ES_UART1_CONFIG                         \
+{                                               \
+    ES_CONF_UART1_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_UART1_STOP_BITS,                                \
+    ES_CONF_UART1_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+               
+                                     
+#define ES_UART2_CONFIG                         \
+{                                               \
+    ES_CONF_UART2_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_UART2_STOP_BITS,                                \
+    ES_CONF_UART2_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+                            
+                                     
+#define ES_UART3_CONFIG                         \
+{                                               \
+    ES_CONF_UART3_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_UART3_STOP_BITS,                                \
+    ES_CONF_UART3_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+
+#define ES_USART0_CONFIG                         \
+{                                               \
+    ES_CONF_USART0_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_USART0_STOP_BITS,                                \
+    ES_CONF_USART0_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+                     
+                                     
+#define ES_USART1_CONFIG                         \
+{                                               \
+    ES_CONF_USART1_BAUD_RATE,                           \
+    DATA_BITS_8,                                \
+    ES_CONF_USART1_STOP_BITS,                                \
+    ES_CONF_USART1_PARITY,                                \
+    BIT_ORDER_LSB,                              \
+    NRZ_NORMAL,                                 \
+    RT_SERIAL_RB_BUFSZ,                         \
+    0                                           \
+}
+
+#endif

bsp/essemi/es32f0654/drivers/Kconfig

@@ -6,129 +6,7 @@ menu "Hardware Drivers Config"
             select RT_USING_PIN
             default y
 
-        menu "UART Drivers"
-            config BSP_USING_UART0
-                bool "Enable UART0 PB10/PB11(T/R)"
-                select RT_USING_SERIAL
-                default n
-
-            config BSP_USING_UART1
-                bool "Enable UART1 PC10/PC11(T/R)"
-                select RT_USING_SERIAL
-                default n
-
-            config BSP_USING_UART2
-                bool "Enable UART2 PC12/PD02(T/R)"
-                select RT_USING_SERIAL
-                default y
-                depends on !BSP_USING_HWTIMER1
-
-            config BSP_USING_UART3
-                bool "Enable UART3 PC04/PC05(T/R)"
-                select RT_USING_SERIAL
-                default n
-                depends on !BSP_USING_HWTIMER2
-        endmenu
-
-        menu "SPI Drivers"
-            config BSP_USING_SPI0
-                bool "Enable SPI0 BUS PB03/PB04/PB05(CLK/MISO/MOSI)"
-                select RT_USING_SPI
-                select RT_USING_PIN
-                default n
-
-            config BSP_USING_SPI1
-                bool "Enable SPI1 BUS PB13/PB14/PB15(CLK/MISO/MOSI)"
-                select RT_USING_SPI
-                select RT_USING_PIN
-                default n
-        endmenu
-
-        menu "I2C Drivers"
-            config BSP_USING_I2C0
-                bool "Enable I2C0 BUS PB08/PB09(SCL/SDA)"
-                select RT_USING_I2C
-                default n
-
-            config BSP_USING_I2C1
-                bool "Enable I2C1 BUS PB10/PB11(SCL/SDA)"
-                select RT_USING_I2C
-                default n
-        endmenu
-
-        menu "CAN Drivers"
-            config BSP_USING_CAN
-                bool "Enable CAN BUS PA11/PA12(RX/TX)"
-                select RT_USING_CAN
-                default n
-        endmenu
-
-        menu "PWM Drivers"
-            config BSP_USING_PWM0
-                bool "Using PWM0 PA08/PA09/PA10/PA11"
-                select RT_USING_PWM
-                default n 
-
-            config BSP_USING_PWM1
-                bool "Using PWM1 PB06/PB07/PB08/PB09"
-                select RT_USING_PWM
-                default n
-
-            config BSP_USING_PWM2
-                bool "Using PWM2 PA00/PA01"
-                select RT_USING_PWM
-                default n
-
-            config BSP_USING_PWM3
-                bool "Using PWM3 PC06/PC07"
-                select RT_USING_PWM
-                default n
-        endmenu
-
-        menu "HWtimer Drivers"
-            config BSP_USING_HWTIMER0
-                bool "Using timer0"
-                select RT_USING_HWTIMER
-                default n
-
-            config BSP_USING_HWTIMER1
-                bool "Using timer1"
-                select RT_USING_HWTIMER
-                default n
-                depends on !BSP_USING_UART2
-
-            config BSP_USING_HWTIMER2
-                bool "Using timer2"
-                select RT_USING_HWTIMER
-                default n
-                depends on !BSP_USING_UART3
-
-            config BSP_USING_HWTIMER3
-                bool "Using timer3"
-                select RT_USING_HWTIMER
-                default n
-        endmenu
-
-        menu "RTC Drivers"
-            config BSP_USING_RTC
-                bool "Using RTC"
-                select RT_USING_RTC
-                default n
-        endmenu
-
-        menu "PM Drivers"
-            config BSP_USING_PM
-                bool "Using PM"
-                select RT_USING_PM
-                default n
-        endmenu
-
-        menu "ADC Drivers"
-            config BSP_USING_ADC
-                bool "Using ADC"
-                select RT_USING_ADC
-                default n
-        endmenu
+    source "drivers/ES/Kconfig"    
 
     endmenu
 
@@ -137,11 +15,21 @@ menu "Hardware Drivers Config"
         config BSP_USING_SPI_FLASH
             bool "Enable SPI FLASH (W25Q64 spi0)"
             select BSP_USING_SPI
-            select BSP_USING_SPI0
             select RT_USING_SFUD
             select RT_SFUD_USING_SFDP
             default n
 
+if BSP_USING_SPI_FLASH
+
+        config ES_DEVICE_NAME_SPI_DEV
+            string "The name of spi device (registered)"
+            default "spi00"
+
+        config ES_DEVICE_NAME_SPI_FALSH_DEV
+            string "The name of spi flash device"
+            default "W25Q64"
+endif
+
     endmenu
 
     menu "Offboard Peripheral Drivers"
@@ -163,13 +51,17 @@ menu "Hardware Drivers Config"
             bool "BSP_USING_EXAMPLE_I2C"
             default n
 
+        config BSP_USING_EXAMPLE_I2C_E2PROM
+            bool "BSP_USING_EXAMPLE_I2C_E2PROM"
+            default n
+
         config BSP_USING_EXAMPLE_LED_BLINK
             bool "BSP_USING_EXAMPLE_LED_BLINK"
-            default y
+            default n
 
         config BSP_USING_EXAMPLE_PIN_BEEP
             bool "BSP_USING_EXAMPLE_PIN_BEEP"
-            default y
+            default n
 
         config BSP_USING_EXAMPLE_PWM_LED
             bool "BSP_USING_EXAMPLE_PWM_LED"
@@ -185,7 +77,7 @@ menu "Hardware Drivers Config"
 
         config BSP_USING_EXAMPLE_UART
             bool "BSP_USING_EXAMPLE_UART"
-            default y
+            default n
 
         config BSP_USING_EXAMPLE_CAN
             bool "BSP_USING_EXAMPLE_CAN"

bsp/essemi/es32f0654/drivers/SConscript

@@ -14,7 +14,10 @@ if GetDepend('RT_USING_PIN'):
     src += ['drv_gpio.c']
 
 # add serial driver code
-if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3'):
+if  GetDepend('BSP_USING_UART0') or GetDepend('BSP_USING_UART1') or GetDepend('BSP_USING_UART2') or GetDepend('BSP_USING_UART3') or \
+    GetDepend('BSP_USING_UART4') or GetDepend('BSP_USING_UART5') or \
+    GetDepend('BSP_USING_USART0') or GetDepend('BSP_USING_USART1') or GetDepend('BSP_USING_USART2') or GetDepend('BSP_USING_USART3') or \
+    GetDepend('BSP_USING_USART4') or GetDepend('BSP_USING_USART5'):
     src += ['drv_uart.c']
 
 # add spi driver code
@@ -26,40 +29,50 @@ if  GetDepend('BSP_USING_I2C0') or GetDepend('BSP_USING_I2C1'):
     src += ['drv_i2c.c']
 
 # add can driver code
-if  GetDepend('BSP_USING_CAN'):
+if  GetDepend('BSP_USING_CAN') or GetDepend('BSP_USING_CAN0') or GetDepend('RT_USING_CAN'):
     src += ['drv_can.c']
 
+
+# add adc driver code
+if GetDepend(['BSP_USING_ADC0']) or GetDepend('BSP_USING_ADC'):
+    src += ['drv_adc.c']
+
+# add rtc driver code
+if GetDepend(['BSP_USING_RTC']):
+    src += ['drv_rtc.c']
+
 # add spi flash driver code
 if GetDepend('BSP_USING_SPI_FLASH'):
     src += ['drv_spiflash.c']
 
-# add pwm driver code
-if GetDepend('BSP_USING_PWM0') or GetDepend('BSP_USING_PWM1') or GetDepend('BSP_USING_PWM2') or GetDepend('BSP_USING_PWM3'):
-    src += ['drv_pwm.c']
-
 # add hwtimer driver code
-if GetDepend('BSP_USING_HWTIMER0') or GetDepend('BSP_USING_HWTIMER1') or GetDepend('BSP_USING_HWTIMER2') or GetDepend('BSP_USING_HWTIMER3'):
+if GetDepend('BSP_USING_AD16C4T0_HWTIMER') or GetDepend('BSP_USING_AD16C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP32C4T0_HWTIMER') or GetDepend('BSP_USING_GP32C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP16C2T0_HWTIMER') or GetDepend('BSP_USING_GP16C2T1_HWTIMER') or \
+    GetDepend('BSP_USING_GP16C4T0_HWTIMER') or GetDepend('BSP_USING_GP16C4T1_HWTIMER') or \
+    GetDepend('BSP_USING_BS16T0_HWTIMER') or GetDepend('BSP_USING_BS16T1_HWTIMERIMER') or \
+    GetDepend('BSP_USING_BS16T2_HWTIMER') or GetDepend('BSP_USING_BS16T3_HWTIMER'):
     src += ['drv_hwtimer.c']
 
-# add rtc driver code
-if GetDepend(['BSP_USING_RTC']):
-    src += ['drv_rtc.c']
+# add pwm driver code
+if GetDepend('BSP_USING_AD16C4T0_PWM') or GetDepend('BSP_USING_AD16C4T1_PWM') or \
+    GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM') or \
+    GetDepend('BSP_USING_GP16C2T0__PWM') or GetDepend('BSP_USING_GP16C2T1_PWM') or \
+    GetDepend('BSP_USING_GP32C4T0_PWM') or GetDepend('BSP_USING_GP32C4T1_PWM') or \
+    GetDepend('BSP_USING_GP16C4T0_PWM') or GetDepend('BSP_USING_GP16C4T1_PWM'):
+    src += ['drv_pwm.c']
 
 # add pm driver code
 if GetDepend(['BSP_USING_PM']):
     src += ['drv_pm.c']
-
-# add adc driver code
-if GetDepend(['BSP_USING_ADC']):
-    src += ['drv_adc.c']
-
 CPPPATH = [cwd]
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
 objs = objs + group
 
 src   = []
 cwd   = GetCurrentDir()
-include_path = [cwd]
+include_path = [cwd + '/ES']
 
 if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'):
     src += ['bsp_driver_example/adc_vol_sample.c']
@@ -70,6 +83,9 @@ if GetDepend('BSP_USING_EXAMPLE_HWTIMER'):
 if GetDepend('BSP_USING_EXAMPLE_I2C'):
     src += ['bsp_driver_example/i2c_sample.c']
 
+if GetDepend('BSP_USING_EXAMPLE_I2C_E2PROM'):
+    src += ['bsp_driver_example/i2c_e2_sample.c']
+
 if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'):
     src += ['bsp_driver_example/led_blink_sample.c']
 

bsp/essemi/es32f0654/drivers/board.c

@@ -1,12 +1,25 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-23     wangyq        the first version
- * 2019-11-01     wangyq        update libraries
+ * 2019-11-01     wangyq        update libraries 
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rthw.h>
@@ -14,7 +27,6 @@
 #include "board.h"
 #include "drv_uart.h"
 #include "drv_gpio.h"
-#include <ald_cmu.h>
 #include <ald_gpio.h>
 
 /**
@@ -43,11 +55,65 @@ void NVIC_Configuration(void)
  *******************************************************************************/
 void  SystemClock_Config(void)
 {
-    /* hosc 12MHz, from hosc/3 pll to 48MHz */
-    ald_cmu_pll1_config(CMU_PLL1_INPUT_HOSC_3, CMU_PLL1_OUTPUT_48M);
+	SYSCFG_UNLOCK();
+#if  ES_CMU_LRC_EN   
+    SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
+#else
+    CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);
+#endif  /*ES_CMU_LRC_EN*/  
+ 
+#if ES_CMU_LOSC_EN 
+    SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
+#else
+    CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);
+#endif  /*ES_CMU_LOSC_EN*/    
+    
+#if ES_CMU_HRC_EN     
+    SET_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
+#else
+    CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HRCEN_MSK);
+#endif  /*ES_CMU_HRC_EN*/    
+    
+#if ES_CMU_HOSC_EN     
+    SET_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
+#else
+    CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_HOSCEN_MSK);
+#endif  /*ES_CMU_HOSC_EN*/    
 
-    /*  MCLK 48MHz*/
-    ald_cmu_clock_config(CMU_CLOCK_PLL1, 48000000);
+	SYSCFG_LOCK();
+
+#if  ES_CMU_PLL1_EN   
+    /*PLL的源必须是4M*/
+    ald_cmu_pll1_config(ES_PLL1_REFER_CLK, ES_PLL1_OUT_CLK);
+    
+    #if ES_CMU_PLL1_SAFE_EN
+        ald_cmu_pll_safe_config(ENABLE);
+    #else
+        ald_cmu_pll_safe_config(DISABLE);
+    #endif
+    
+#else
+    CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_PLL1EN_MSK);
+#endif  /*ES_CMU_PLL1_EN*/ 
+    
+    ald_cmu_clock_config(ES_SYS_CLK_SOURSE, ES_SYS_CLK);
+    
+    ald_cmu_div_config(CMU_SYS,ES_CMU_SYS_DIV);
+    ald_cmu_div_config(CMU_HCLK_1,ES_CMU_HCLK_1_DIV);
+    ald_cmu_div_config(CMU_PCLK_1,ES_CMU_PCLK_1_DIV);
+    ald_cmu_div_config(CMU_PCLK_2,ES_CMU_PCLK_2_DIV);
+    
+    ald_cmu_perh_clock_config(CMU_PERH_ALL, ENABLE);
+    
+/*低功耗时钟使能*/    
+#ifdef RT_USING_PM
+        SYSCFG_UNLOCK();
+        SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);
+        SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);
+        SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);
+        SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);
+        SYSCFG_LOCK();
+#endif
 }
 
 /*******************************************************************************
@@ -71,13 +137,22 @@ void SysTick_Handler(void)
 {
     /* enter interrupt */
     rt_interrupt_enter();
-
+    ald_inc_tick();
     rt_tick_increase();
 
     /* leave interrupt */
     rt_interrupt_leave();
 }
 
+/**
+ * This is the cmu interrupt service.
+ *
+ */
+void CMU_Handler(void)
+{
+    ald_cmu_irq_handler();
+}
+
 /*@}*/
 /**
  * This function will initial ES32F0 board.

bsp/essemi/es32f0654/drivers/board.h

@@ -1,11 +1,24 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author        Notes
- * 2019-01-23     wangyq        the first version
+ * 2019-01-23     wangyq        the first version 
+ * 2021-04-20     liuhy         the second version
  */
 
 // <<< Use Configuration Wizard in Context Menu >>>
@@ -13,6 +26,7 @@
 #define __BOARD_H__
 
 #include <es32f065x.h>
+#include "es_conf_info_cmu.h"
 
 #define ES32F0_SRAM_SIZE    0x8000
 #define ES32F0_SRAM_END     (0x20000000 + ES32F0_SRAM_SIZE)

bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c

@@ -18,6 +18,9 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
+
+#ifdef RT_USING_ADC
+
 #define ADC_DEV_NAME        "adc0"      /* ADC 设备名称 */
 #define ADC_DEV_CHANNEL     5           /* PA1 ADC 通道 */
 #define REFER_VOLTAGE       330         /* 参考电压 3.3V,数据精度乘以100保留2位小数*/
@@ -55,3 +58,5 @@ static int adc_vol_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c

@@ -18,7 +18,9 @@
 #include <rtthread.h>
 #include "rtdevice.h"
 
-#define CAN_DEV_NAME       "can"      /* CAN 设备名称 */
+#ifdef RT_USING_CAN
+
+#define CAN_DEV_NAME       "can0"      /* CAN 设备名称 */
 
 static struct rt_semaphore rx_sem;     /* 用于接收消息的信号量 */
 static rt_device_t can_dev;            /* CAN 设备句柄 */
@@ -142,3 +144,5 @@ int can_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(can_sample, can device sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c

@@ -17,7 +17,9 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
-#define HWTIMER_DEV_NAME   "timer0"     /* 定时器名称 */
+#ifdef RT_USING_HWTIMER
+
+#define HWTIMER_DEV_NAME   "timer1"     /* 定时器名称 */
 
 /* 定时器超时回调函数 */
 static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
@@ -83,3 +85,5 @@ static int hwtimer_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_e2_sample.c

@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-12-15     liuhy       first implementation.
+ */
+/*
+ * 程序清单：这是一个 I2C 设备使用例程
+ * 例程导出了 i2c_e2_sample 命令到控制终端
+ * 命令调用格式：i2c_e2_sample
+ * 命令解释：使用默认的I2C总线设备i2c0
+ * 程序功能：通过 I2C 设备写读e2prom，ST24C04WP。
+*/
+                         
+/*ST24C04WP 有2个Block ：Block0 的从机地址为：0x50,Block1 的从机地址为：0x51
+            一个Block有 256字节，一页16字节,写只可在一页内(超过一页的范围后,会回到页的开始),读无页限制*/
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#ifdef RT_USING_I2C
+
+#define I2C_BUS_NAME    "i2c0"                   /*I2C总线设备名称 */
+#define SLAVE_ADDR      0x50                     /*从机地址*/
+#define MEM_ADDR        0x00                     /*从机的起始储存地址,范围：0x00到0xEF(例程写读范围：2页)*/
+#define ADDR_LEN        1                        /*定义从机储存地址的长度，默认8位,1字节*/
+#define STR_LEN         16                       /*接收发送的页数据长度 ,最大16*/     
+
+static rt_uint8_t mem_addr,rx_buffer[33] = { 0U };  /*读两页,需要32字节，字符串结束'\0'*/                 
+/*第一个字节' '用来放 E2PROM 的内存地址,最后一个字节'\0'作为子串的结束，不存入e2prom*/
+static rt_uint8_t tx_buffer1[STR_LEN + ADDR_LEN + 1] = " e2prom example !\0";                                          
+static rt_uint8_t tx_buffer2[STR_LEN + ADDR_LEN + 1] = " ABCDEFGH12345678\0";  
+
+static void i2c_e2_sample(int argc, char *argv[])
+{
+    struct rt_i2c_bus_device *i2c_bus = RT_NULL;     /* I2C总线设备句柄 */
+    struct rt_i2c_msg i2c_msg[2];                    /* I2C消息 */
+    rt_size_t s_stat;
+    
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME);    /* 通过名字获取I2C总线设备的句柄 */
+    
+    if( i2c_bus == RT_NULL)
+    {
+        rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME);
+        return;
+    }
+         
+        /*写T24C04WP
+                如果  (MEM_ADDR & 0x0F) + STR_LEN <= 16, 写的范围为：(MEM_ADDR        , MEM_ADDR + STR_LEN        )
+                                                                     (0x10 + MEM_ADDR , 0x10 + MEM_ADDR + STR_LEN )
+                如果  (MEM_ADDR & 0x0F) + STR_LEN >  16, 超出范围的部分会在页内循环写。*/
+        tx_buffer1[0] = MEM_ADDR;
+    
+        /*初始化消息*/
+        i2c_msg[0].addr = SLAVE_ADDR;                /* 从机地址 */
+        i2c_msg[0].len  = ADDR_LEN + STR_LEN ;       /* 写入的长度，地址+数据 */
+        i2c_msg[0].buf = tx_buffer1;                 /* 待写入第一段数据 */
+        i2c_msg[0].flags = RT_I2C_WR;                /* I2C写 */   
+        s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1);   /* 写入第一段数据 */
+    
+        if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer1[1]);
+                    else rt_kprintf("device %s write fail \n",I2C_BUS_NAME);
+        
+        tx_buffer2[0] = MEM_ADDR + 0x10;     /*加一页*/
+        i2c_msg[0].buf = tx_buffer2;         /* 待写入第二段数据 */
+        s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,1);   /* 写入第二段数据 */
+    
+        if( s_stat == 1 )rt_kprintf("write successful. \nmessage: %s\n",&tx_buffer2[1]);
+                    else rt_kprintf("device %s write fail \n",I2C_BUS_NAME);
+    
+        /*读T24C04WP  读2页的数据。读数据需要2条消息：第一条消息：发送读取的地址。
+                                                      第二条消息：读取具体的数据。*/
+       
+        mem_addr = MEM_ADDR & 0xF0;   /*从页的开始读*/
+        
+        i2c_msg[0].len = ADDR_LEN;        
+        i2c_msg[0].buf = &mem_addr;
+        
+        i2c_msg[1].addr = SLAVE_ADDR;          /* 从机地址 */                     
+        i2c_msg[1].len  = 32;                  /* 读取的数据长度：2*16 */
+        i2c_msg[1].buf = rx_buffer;            /* 数据存放地址 */
+        i2c_msg[1].flags = RT_I2C_RD;          /* I2C读 */
+        s_stat = rt_i2c_transfer(i2c_bus,i2c_msg,2);   /* 读已写的2页 */
+        
+        if( s_stat == 2 )rt_kprintf(" read successful \n messege : %s \n",rx_buffer);
+                    else
+            rt_kprintf("read  fail \n");
+        
+        return;
+    
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(i2c_e2_sample, i2c e2prom sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/i2c_sample.c

@@ -1,7 +1,19 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -11,14 +23,16 @@
  * 程序清单：这是一个 I2C 设备使用例程
  * 例程导出了 i2c_io_sample 命令到控制终端
  * 命令调用格式：i2c_io_sample
- * 命令解释：使用默认的I2C总线设备
+ * 命令解释：使用默认的I2C总线设备i2c0
  * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。
 */
 
 #include <rtthread.h>
 #include <rtdevice.h>
 
-#define I2C_BUS_NAME          "i2c1"  /* I2C总线设备名称 */
+#ifdef RT_USING_I2C
+
+#define I2C_BUS_NAME          "i2c0"  /* I2C总线设备名称 */
 #define SLAVE_ADDR                  0x2D    /* 从机地址 */
 #define STR_LEN                       16    /* 接收发送的数据长度 */
 
@@ -95,3 +109,5 @@ static void i2c_io_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(i2c_io_sample, i2c io sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/pm_sample.c

@@ -1,7 +1,19 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -11,15 +23,18 @@
  * 程序清单：这是一个 pm睡眠唤醒的使用例程
  * 例程导出了 pm_sample 命令到控制终端
  * 命令调用格式：pm_sample
- * 命令解释：进入不同的睡眠模式，然后用按键唤醒
+ * 命令解释：进入不同的睡眠模式，然后用按键唤醒。
  * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。
+ * 注意：进入睡眠前，如果有中断挂起（SYSTICK、UART、EXTI等），睡眠将被瞬间唤醒。
 */
 
 #include <rtthread.h>
 #include <rtdevice.h>
 
+
+#ifdef RT_USING_PM
 #define PM_NAME       "pm"      /* 设备名称 */
-#define WAKE_UP_PIN     18      /* 唤醒源 */
+#define WAKE_UP_PIN     19      /* 唤醒源 */
 #define SLEEP_TIMES     12      /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */
 
 
@@ -65,8 +80,9 @@ void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data)
                                 break;
         /*睡眠唤醒后*/
         case RT_PM_EXIT_SLEEP:  g_pm_data.flag = 0;  /*睡眠唤醒后*/
+                                /*从深睡眠唤醒后，等待UART时钟未恢复稳定，输出可能丢失*/
                                 rt_kprintf("\n\rEXIT\n\r");
-                                rt_pm_release(mode);   /*释放休眠模式*/
+                                rt_pm_request(PM_SLEEP_MODE_NONE);  /*进无休眠模式*/
                                 return;
         
         default: break;
@@ -125,6 +141,9 @@ static void pm_test(void *parameter)
             g_pm_data.flag = 2;  
        
        }
+        
+       /*彻底释放无休眠模式*/
+       rt_pm_release_all(PM_SLEEP_MODE_NONE);  
        
        /*请求选择的休眠模式*/
        rt_pm_request(in_mode[i%6]);
@@ -137,15 +156,21 @@ static void pm_test(void *parameter)
            rt_thread_mdelay(500);
        }
        
-       /*释放选择的休眠模式*/
-       rt_pm_release(in_mode[i%6]);
+       /*释放选择的休眠模式 ，彻底释放*/
+       rt_pm_release_all(in_mode[i%6]);
        
        i++;
        
    }
-      /*清除回调函数和私有数据*/
+   
+    /*切换为无睡眠模式*/
+    rt_pm_request(PM_SLEEP_MODE_NONE);
+   
+    /*清除回调函数和私有数据*/
     rt_pm_notify_set(RT_NULL,RT_NULL);
-   rt_kprintf("thread pm_test close\n\r");
+   
+    rt_kprintf("thread pm_test close\n\r");
+   
 }
 
 /*按键唤醒的回调函数*/
@@ -181,3 +206,5 @@ static int pm_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(pm_sample, pm sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/pwm_led_sample.c

@@ -17,9 +17,12 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
+
+#ifdef RT_USING_PWM
+
 #define LED_PIN_NUM         16      /* LED PIN脚编号，查看驱动文件drv_gpio.c确定 */
 #define PWM_DEV_NAME        "pwm1"  /* PWM设备名称 */
-#define PWM_DEV_CHANNEL     4       /* PB9 PWM通道 */
+#define PWM_DEV_CHANNEL     1       /* PA8 PWM通道 */
 
 struct rt_device_pwm *pwm_dev;      /* PWM设备句柄 */
 
@@ -70,3 +73,6 @@ static int pwm_led_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(pwm_led_sample, pwm sample);
+
+#endif
+

bsp/essemi/es32f0654/drivers/bsp_driver_example/rtc_sample.c

@@ -17,6 +17,8 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
+#ifdef RT_USING_RTC
+
 static int rtc_sample(int argc, char *argv[])
 {
     rt_err_t ret = RT_EOK;
@@ -49,3 +51,5 @@ static int rtc_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(rtc_sample, rtc sample);
+
+#endif

bsp/essemi/es32f0654/drivers/bsp_driver_example/spi_sample.c

@@ -1,7 +1,19 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author       Notes
@@ -17,13 +29,14 @@
 #include <rtthread.h>
 #include <rtdevice.h>
 
+#ifdef RT_USING_SPI
+
 #define SPI_DEVICE_NAME     "spi00"
 #define BUF_LEN             16
 
 static void spi_io_sample(int argc, char *argv[])
 {
     struct rt_spi_device * spi_dev;          /* spi设备的句柄 */
-    struct rt_spi_configuration spi_config;
     rt_uint8_t i,buffer[BUF_LEN] = { 0U };
     rt_err_t s_stat;
     rt_err_t result;
@@ -37,23 +50,8 @@ static void spi_io_sample(int argc, char *argv[])
         return;
     }
     
-    
-    /* 清空配置结构体 */
-    rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration));
-    
-    spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
-    spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
-    spi_config.mode |= RT_SPI_CPHA;   /* 第二边沿采样 */
-    spi_config.mode |= RT_SPI_CPOL;   /* 空闲高电平 */
-    spi_config.mode |= RT_SPI_NO_CS;  /* 禁用软件从机选择管理 */
-    spi_config.mode |= RT_SPI_MSB;    /* 高位在前 */
-    
-    spi_config.data_width = 8;        /* 数据长度：8 */
-    
-    spi_config.max_hz = 2000000;      /* 最快时钟频率 */
-    
     /* 配置SPI设备 */
-    s_stat = rt_spi_configure(spi_dev,&spi_config);
+    s_stat = rt_spi_configure(spi_dev,&(spi_dev->config));
     
     if(s_stat != RT_EOK)
     {
@@ -150,3 +148,5 @@ static void spi_io_sample(int argc, char *argv[])
 }
 /* 导出到 msh 命令列表中 */
 MSH_CMD_EXPORT(spi_io_sample, spi  sample);
+
+#endif

bsp/essemi/es32f0654/drivers/drv_adc.c

@@ -1,12 +1,25 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author        Notes
  * 2019-04-03     wangyq        the first version
  * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rthw.h>
@@ -59,77 +72,69 @@ static adc_channel_t es32f0_adc_get_channel(rt_uint32_t channel)
     {
     case  0:
         es32f0_channel = ADC_CHANNEL_0;
-        ald_gpio_init(GPIOC, GPIO_PIN_0, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH0_GPIO, ES_GPIO_ADC_CH0_PIN, &gpio_initstruct);
         break;
     case  1:
         es32f0_channel = ADC_CHANNEL_1;
-        ald_gpio_init(GPIOC, GPIO_PIN_1, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH1_GPIO, ES_GPIO_ADC_CH1_PIN, &gpio_initstruct);
         break;
     case  2:
         es32f0_channel = ADC_CHANNEL_2;
-        ald_gpio_init(GPIOC, GPIO_PIN_2, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH2_GPIO, ES_GPIO_ADC_CH2_PIN, &gpio_initstruct);
         break;
     case  3:
         es32f0_channel = ADC_CHANNEL_3;
-        ald_gpio_init(GPIOC, GPIO_PIN_3, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH3_GPIO, ES_GPIO_ADC_CH3_PIN, &gpio_initstruct);
         break;
     case  4:
         es32f0_channel = ADC_CHANNEL_4;
-        ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH4_GPIO, ES_GPIO_ADC_CH4_PIN, &gpio_initstruct);
         break;
     case  5:
         es32f0_channel = ADC_CHANNEL_5;
-        ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH5_GPIO, ES_GPIO_ADC_CH5_PIN, &gpio_initstruct);
         break;
     case  6:
         es32f0_channel = ADC_CHANNEL_6;
-        ald_gpio_init(GPIOA, GPIO_PIN_2, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH6_GPIO, ES_GPIO_ADC_CH6_PIN, &gpio_initstruct);
         break;
     case  7:
         es32f0_channel = ADC_CHANNEL_7;
-        ald_gpio_init(GPIOA, GPIO_PIN_3, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH7_GPIO, ES_GPIO_ADC_CH7_PIN, &gpio_initstruct);
         break;
     case  8:
         es32f0_channel = ADC_CHANNEL_8;
-        ald_gpio_init(GPIOA, GPIO_PIN_4, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH8_GPIO, ES_GPIO_ADC_CH8_PIN, &gpio_initstruct);
         break;
     case  9:
         es32f0_channel = ADC_CHANNEL_9;
-        ald_gpio_init(GPIOA, GPIO_PIN_5, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH9_GPIO, ES_GPIO_ADC_CH9_PIN, &gpio_initstruct);
         break;
     case 10:
         es32f0_channel = ADC_CHANNEL_10;
-        ald_gpio_init(GPIOA, GPIO_PIN_6, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH10_GPIO, ES_GPIO_ADC_CH10_PIN, &gpio_initstruct);
         break;
     case 11:
         es32f0_channel = ADC_CHANNEL_11;
-        ald_gpio_init(GPIOA, GPIO_PIN_7, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH11_GPIO, ES_GPIO_ADC_CH11_PIN, &gpio_initstruct);
         break;
     case 12:
         es32f0_channel = ADC_CHANNEL_12;
-        ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH12_GPIO, ES_GPIO_ADC_CH12_PIN, &gpio_initstruct);
         break;
     case 13:
         es32f0_channel = ADC_CHANNEL_13;
-        ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH13_GPIO, ES_GPIO_ADC_CH13_PIN, &gpio_initstruct);
         break;
     case 14:
         es32f0_channel = ADC_CHANNEL_14;
-        ald_gpio_init(GPIOB, GPIO_PIN_0, &gpio_initstruct);
+        ald_gpio_init(ES_GPIO_ADC_CH14_GPIO, ES_GPIO_ADC_CH14_PIN, &gpio_initstruct);
         break;
     case 15:
         es32f0_channel = ADC_CHANNEL_15;
-        ald_gpio_init(GPIOB, GPIO_PIN_1, &gpio_initstruct);
-        break;
-    case 16:
-        es32f0_channel = ADC_CHANNEL_16;
-        break;
-    case 17:
-        es32f0_channel = ADC_CHANNEL_17;
-        break;
-    case 18:
-        es32f0_channel = ADC_CHANNEL_18;
+        ald_gpio_init(ES_GPIO_ADC_CH15_GPIO, ES_GPIO_ADC_CH15_PIN, &gpio_initstruct);
         break;
+    
     default:
         break;
     }
@@ -148,6 +153,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c
     /* config adc channel */
     nm_config.ch       = es32f0_adc_get_channel(channel);
     nm_config.idx          = ADC_NCH_IDX_1;
+	
+/*aaabbbccc*/
+    nm_config.samp = ES_ADC0_NCH_SAMPLETIME;
     nm_config.samp = ADC_SAMPLETIME_4;
     ald_adc_normal_channel_config(_hadc, &nm_config);
 
@@ -168,24 +176,34 @@ static const struct rt_adc_ops es32f0_adc_ops =
 int rt_hw_adc_init(void)
 {
     int result = RT_EOK;
+ 
+    adc_handle_t _h_adc;
+
+    _h_adc.init.scan = DISABLE;
+    _h_adc.init.cont = DISABLE;
+    _h_adc.init.disc = ADC_ALL_DISABLE;
+    _h_adc.init.disc_nr = ADC_DISC_NR_1;
+    _h_adc.init.nche_sel = ADC_NCHESEL_MODE_ALL;
+    _h_adc.init.n_ref = ADC_NEG_REF_VSS;
+    _h_adc.init.p_ref = ADC_POS_REF_VDD;   
+    _h_adc.init.nch_nr = ADC_NCH_NR_16; 
+    
+#ifdef BSP_USING_ADC0
+    
     static adc_handle_t _h_adc0;
-
-    /* adc function initialization */
+    
+    _h_adc0.init = _h_adc.init;
+    
     _h_adc0.perh = ADC0;
-    _h_adc0.init.align = ADC_DATAALIGN_RIGHT;
-    _h_adc0.init.scan = DISABLE;
-    _h_adc0.init.cont = DISABLE;
-    _h_adc0.init.disc = ADC_ALL_DISABLE;
-    _h_adc0.init.disc_nr = ADC_DISC_NR_1;
-    _h_adc0.init.data_bit = ADC_CONV_BIT_12;
-    _h_adc0.init.div = ADC_CKDIV_128;
-    _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
-    _h_adc0.init.n_ref = ADC_NEG_REF_VSS;
-    _h_adc0.init.p_ref = ADC_POS_REF_VDD;
+    _h_adc0.init.align = ES_ADC0_ALIGN;
+    _h_adc0.init.data_bit = ES_ADC0_DATA_BIT;
+    _h_adc0.init.div = ES_ADC0_CLK_DIV;    
     ald_adc_init(&_h_adc0);
-
-    rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);
-
+    
+    result = rt_hw_adc_register(&_device_adc0, ES_DEVICE_NAME_ADC0, &es32f0_adc_ops, &_h_adc0);
+    
+#endif /*BSP_USING_ADC0*/
+ 
     return result;
 }
 INIT_BOARD_EXPORT(rt_hw_adc_init);

bsp/essemi/es32f0654/drivers/drv_adc.h

@@ -3,14 +3,29 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-04-03     wangyq        the first version
+ * 2021-04-20     liuhy         the second version
  */
 
 #ifndef DRV_ADC_H__
 #define DRV_ADC_H__
 
+#include "es_conf_info_adc.h"
+
 int rt_hw_adc_init(void);
 
 #endif

bsp/essemi/es32f0654/drivers/drv_can.c

@@ -1,51 +1,94 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author        Notes
- * 2019-11-09     wangyq        the first version
+ * 2019-11-09     wangyq        the first version  
+ * 2021-04-20     liuhy         the second version
  */
 
 #include "drv_can.h"
 
-#ifdef BSP_USING_CAN
+#ifdef RT_USING_CAN
 
-static struct es32f0_can can;
 
-/* attention !!! baud calculation example: Pclk / ((sjw + seg1 + seg2) * psc)  48 / ((1 + 3 + 2) * 8) = 1MHz */
-static const struct es32f0_baud_rate_tab can_baud_rate_tab[] =
-{
-    {CAN1MBaud, 8},
-    {CAN800kBaud, 10},
-    {CAN500kBaud, 16},
-    {CAN250kBaud, 32},
-    {CAN125kBaud, 64},
-    {CAN100kBaud, 80},
-    {CAN50kBaud, 160},
-    {CAN20kBaud, 400},
-    {CAN10kBaud, 800}
-};
+static struct es32f0_can can;
 
-static rt_uint32_t get_can_baud_index(rt_uint32_t baud)
-{
-    rt_uint32_t len, index;
 
-    len = sizeof(can_baud_rate_tab) / sizeof(can_baud_rate_tab[0]);
-    for (index = 0; index < len; index++)
+static rt_uint32_t get_can_baud_index(rt_uint32_t baud,can_init_t * init)
+{ 
+/* attention !!! baud calculation example: Pclk / ((1 + seg1 + seg2) * psc)       Pclk=48 / ((1 + seg1=3 + seg2=2) * 8) = 1MHz */
+    double target,temp,min;
+    uint32_t i,j,j_max,near = 0;
+    target = (double)(ald_cmu_get_pclk1_clock());
+    target/= baud;                               /*计算误差1*/
+    
+    min = 0xFFFFFFFF;
+    
+    for(i = 1 + 16 + 8 ;i > 2;i--)     /*SYNC_SEG + SEG1 + SEG2*/
     {
-        if (can_baud_rate_tab[index].baud_rate == baud)
-            return index;
+        j_max = target/i/(0.98) + 1;                          /*缩小范围*/
+        j_max = (j_max > 1024) ? (1024) : (j_max);
+        
+        for(j = target/i/1.02 ;j < j_max;j++)
+        {   
+            temp = target/i/j;                      /*计算误差2*/
+            temp = (temp > 1) ? (temp - 1) : (1 - temp);
+            temp+= ((1.0 * i * j) / 0xFFFFFFFF) ;       
+            
+            if(temp < min)
+            {
+                if(temp > 0.000001)
+                {
+                     near = (i<<16) + j;
+                     min = temp;
+                }
+                else                         
+                {
+                     init->seg1 = (can_seg1_t)((i - 1)*2/3-1);
+                     init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1);
+                     init->psc = j;
+                
+                     return 0;
+                 }
+             }
+         }
     }
 
-    return 0; /* default baud is CAN1MBaud */
+    if(min < 0.01)
+    {
+        i = near>>16;
+        j = near % (1<<16);
+        init->seg1 = (can_seg1_t)((i - 1)*2/3-1);
+        init->seg2 = (can_seg2_t)(i - init->seg1 - 1 - 1 - 1);
+        init->psc = j;
+        
+        return 0;
+    }
+    else
+    {
+        return 1; 
+    }
 }
+   
 
 static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configure *cfg)
 {
     struct es32f0_can *drv_can;
-    rt_uint32_t baud_index;
 
     RT_ASSERT(can_device);
     RT_ASSERT(cfg);
@@ -56,7 +99,7 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu
     drv_can->CanHandle.init.ttcm = DISABLE;
     drv_can->CanHandle.init.abom = ENABLE;
     drv_can->CanHandle.init.awk = DISABLE;
-    drv_can->CanHandle.init.artx = DISABLE;
+    drv_can->CanHandle.init.artx = (type_func_t)ES_CAN0_AUTO_BAN_RE_T;
     drv_can->CanHandle.init.rfom   = DISABLE;
     drv_can->CanHandle.init.txmp   = ENABLE;
 
@@ -75,12 +118,20 @@ static rt_err_t _can_config(struct rt_can_device *can_device, struct can_configu
         drv_can->CanHandle.init.mode = CAN_MODE_SILENT_LOOPBACK;
         break;
     }
+    /*配置参数*/
+    if(get_can_baud_index(cfg->baud_rate,&(drv_can->CanHandle.init)))
+    {
+        return -RT_ERROR; 
+    }
+    drv_can->CanHandle.init.sjw = (can_sjw_t)(cfg->reserved);
+    
+    /* init can */
 
-    baud_index = get_can_baud_index(cfg->baud_rate);
-    drv_can->CanHandle.init.sjw = CAN_SJW_1;
-    drv_can->CanHandle.init.seg1 = CAN_SEG1_3;
-    drv_can->CanHandle.init.seg2 = CAN_SEG2_2;
-    drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data;
+   // baud_index = get_can_baud_index(cfg->baud_rate);
+    //drv_can->CanHandle.init.sjw = CAN_SJW_1;
+   // drv_can->CanHandle.init.seg1 = CAN_SEG1_3;
+   // drv_can->CanHandle.init.seg2 = CAN_SEG2_2;
+   // drv_can->CanHandle.init.psc = can_baud_rate_tab[baud_index].config_data;
     /* init can */
     if (ald_can_init(&drv_can->CanHandle) != OK)
     {
@@ -96,7 +147,10 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
 {
     rt_uint32_t argval;
     struct es32f0_can *drv_can;
+
+#ifdef RT_CAN_USING_HDR
     struct rt_can_filter_config *filter_cfg;
+#endif
 
     RT_ASSERT(can_device != RT_NULL);
     drv_can = (struct es32f0_can *)can_device->parent.user_data;
@@ -108,8 +162,12 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
         argval = (rt_uint32_t) arg;
         if (argval == RT_DEVICE_FLAG_INT_RX)
         {
-            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FF0 | CAN_IT_FOV0 |
-                                     CAN_IT_FP1 | CAN_IT_FF1 | CAN_IT_FOV1), DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, DISABLE);
         }
         else if (argval == RT_DEVICE_FLAG_INT_TX)
         {
@@ -117,8 +175,11 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
         }
         else if (argval == RT_DEVICE_CAN_INT_ERR)
         {
-            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF |
-                                     CAN_IT_PRERR | CAN_IT_ERR), DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, DISABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, DISABLE);
         }
         break;
     case RT_DEVICE_CTRL_SET_INT:
@@ -127,8 +188,14 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
         {
             NVIC_SetPriority(CAN0_IRQn, 1);
             NVIC_EnableIRQ(CAN0_IRQn);
-
-            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_FP0 | CAN_IT_FP1), ENABLE);
+            
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP0, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF0, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV0, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FP1, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FF1, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_FOV1, ENABLE);
+            
         }
         else if (argval == RT_DEVICE_FLAG_INT_TX)
         {
@@ -141,11 +208,16 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
         {
             NVIC_SetPriority(CAN0_IRQn, 1);
             NVIC_EnableIRQ(CAN0_IRQn);
-
-            ald_can_interrupt_config(&drv_can->CanHandle, (can_it_t)(CAN_IT_WARN | CAN_IT_PERR | CAN_IT_BOF |
-                                     CAN_IT_PRERR | CAN_IT_ERR), ENABLE);
+            
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_WARN, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PERR, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_BOF, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_PRERR, ENABLE);
+            ald_can_interrupt_config(&drv_can->CanHandle, CAN_IT_ERR, ENABLE);
+            
         }
         break;
+#ifdef RT_CAN_USING_HDR
     case RT_CAN_CMD_SET_FILTER:
         if (RT_NULL == arg)
         {
@@ -157,8 +229,55 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
             filter_cfg = (struct rt_can_filter_config *)arg;
             /* get default filter */
             for (int i = 0; i < filter_cfg->count; i++)
-            {
-                drv_can->FilterConfig.number = filter_cfg->items[i].hdr;
+            {   
+                
+                /*默认过滤表判断*/
+                if(filter_cfg->items[i].hdr < drv_can->device.config.maxhdr)           
+                    drv_can->FilterConfig.number = filter_cfg->items[i].hdr;
+                else       
+                    drv_can->FilterConfig.number = ES_C_CAN_DEFAULT_FILTER_NUMBER;
+
+               if(filter_cfg->items[i].mode)
+               {
+                    /*标识符列表模式： 类型匹配 ，id匹配为：接收的id = 配置的id
+                                                                或者 = 配置的mask ，通过*/
+                    /*扩展帧*/
+                    if(filter_cfg->items[i].ide)  
+                    {    
+//                         filter_cfg->items[i].id =  filter_cfg->items[i].id ;    /*id 29 位*/
+                         filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 3) |
+                                                    (filter_cfg->items[i].ide << 2) |
+                                                    (filter_cfg->items[i].rtr << 1));  
+                    }
+                    else  /*标准帧*/
+                    {
+                         filter_cfg->items[i].id = (filter_cfg->items[i].id << 18);   
+                         filter_cfg->items[i].mask = ((filter_cfg->items[i].mask << 21) |
+                                                    (filter_cfg->items[i].ide << 2) |
+                                                    (filter_cfg->items[i].rtr << 1));  
+                    }   
+                }
+                else
+                {
+                    /*标识符掩码模式*/
+                    /*扩展帧*/
+                    if(filter_cfg->items[i].ide)  
+                    {    
+                         filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<3;     
+                    }
+                    else  /*标准帧*/
+                    {
+                         filter_cfg->items[i].id = (filter_cfg->items[i].id)<<18; 
+                         filter_cfg->items[i].mask = (filter_cfg->items[i].mask)<<21;
+                    }   
+                
+#if   ES_C_CAN_FILTER_FRAME_TYPE
+                    /*匹配类型*/
+                    filter_cfg->items[i].mask |= 0x6;
+#endif            
+                
+                }
+
                 drv_can->FilterConfig.id_high = (filter_cfg->items[i].id >> 13) & 0xFFFF;
                 drv_can->FilterConfig.id_low = ((filter_cfg->items[i].id << 3) |
                                                 (filter_cfg->items[i].ide << 2) |
@@ -171,6 +290,8 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
             }
         }
         break;
+
+#endif
     case RT_CAN_CMD_SET_MODE:
         argval = (rt_uint32_t) arg;
         if (argval != RT_CAN_MODE_NORMAL &&
@@ -188,18 +309,7 @@ static rt_err_t _can_control(struct rt_can_device *can_device, int cmd, void *ar
         break;
     case RT_CAN_CMD_SET_BAUD:
         argval = (rt_uint32_t) arg;
-        if (argval != CAN1MBaud &&
-                argval != CAN800kBaud &&
-                argval != CAN500kBaud &&
-                argval != CAN250kBaud &&
-                argval != CAN125kBaud &&
-                argval != CAN100kBaud &&
-                argval != CAN50kBaud  &&
-                argval != CAN20kBaud  &&
-                argval != CAN10kBaud)
-        {
-            return -RT_ERROR;
-        }
+    
         if (argval != drv_can->device.config.baud_rate)
         {
             drv_can->device.config.baud_rate = argval;
@@ -423,8 +533,11 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
         /* RX interrupt */
         else
         {
+           if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO0) != 0) 
+            {                                                     
             /* save to user list */
             rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+            }
 
             /* Clear FIFO0 rx Flag */
             SET_BIT(h_can->perh->RXF0, CAN_RXF0_FREE_MSK);
@@ -441,8 +554,11 @@ static void _can_rx_isr(struct rt_can_device *can, rt_uint32_t fifo)
         /* RX interrupt */
         else
         {
+            if(CAN_RX_MSG_PENDING(h_can, CAN_RX_FIFO1) != 0) 
+            {                                                     
             /* save to user list */
             rt_hw_can_isr(can, RT_CAN_EVENT_RX_IND | fifo << 8);
+            }
 
             /* Clear FIFO0 rx Flag */
             SET_BIT(h_can->perh->RXF1, CAN_RXF1_FREE_MSK);
@@ -549,20 +665,12 @@ void CAN0_Handler(void)
         can.device.status.errcode = errtype & 0x07;
         h_can->perh->IFC |= CAN_IFC_ERRIFC_MSK;
     }
-
     rt_interrupt_leave();
 }
 
 int rt_hw_can_init(void)
 {
     gpio_init_t h_gpio;
-    struct can_configure config = CANDEFAULTCONFIG;
-
-    config.privmode = RT_CAN_MODE_NOPRIV;
-    config.ticks = 50;
-#ifdef RT_CAN_USING_HDR
-    config.maxhdr = 14;
-#endif
 
     /* Initialize can common pin */
     h_gpio.odos = GPIO_PUSH_PULL;
@@ -570,15 +678,22 @@ int rt_hw_can_init(void)
     h_gpio.odrv = GPIO_OUT_DRIVE_NORMAL;
     h_gpio.flt  = GPIO_FILTER_DISABLE;
     h_gpio.type = GPIO_TYPE_TTL;
-    h_gpio.func = GPIO_FUNC_4;
 
+#if  defined(ES_CAN0_RX_GPIO_FUNC)&&defined(ES_CAN0_RX_GPIO_PORT)&&defined(ES_CAN0_RX_GPIO_PIN)    
     /* Initialize can rx pin */
-    h_gpio.mode = GPIO_MODE_INPUT;
-    ald_gpio_init(GPIOA, GPIO_PIN_11, &h_gpio);
-
+    h_gpio.mode = GPIO_MODE_INPUT; 
+    h_gpio.func = ES_CAN0_RX_GPIO_FUNC;
+    ald_gpio_init(ES_CAN0_RX_GPIO_PORT, ES_CAN0_RX_GPIO_PIN, &h_gpio);
+#endif                            
+             
+ 
+#if  defined(ES_CAN0_TX_GPIO_FUNC)&&defined(ES_CAN0_TX_GPIO_PORT)&&defined(ES_CAN0_TX_GPIO_PIN)     
     /* Initialize can tx pin */
-    h_gpio.mode = GPIO_MODE_OUTPUT;
-    ald_gpio_init(GPIOA, GPIO_PIN_12, &h_gpio);
+    h_gpio.mode = GPIO_MODE_OUTPUT; 
+    h_gpio.func = ES_CAN0_TX_GPIO_FUNC;
+    ald_gpio_init(ES_CAN0_TX_GPIO_PORT, ES_CAN0_TX_GPIO_PIN, &h_gpio);
+#endif                            
+             
 
     /* config default filter */
     can_filter_t filter = {0};
@@ -587,15 +702,21 @@ int rt_hw_can_init(void)
     filter.mask_id_high = 0x0000;
     filter.mask_id_low = 0x0000;
     filter.fifo = CAN_FILTER_FIFO0;
-    filter.number = 0;
+    filter.number = ES_C_CAN_DEFAULT_FILTER_NUMBER;
     filter.mode = CAN_FILTER_MODE_MASK;
     filter.scale = CAN_FILTER_SCALE_32;
     filter.active = ENABLE;
 
     can.FilterConfig = filter;
-    can.device.config = config;
+    can.device.config = (struct can_configure)ES_CAN0_CONFIG; 
+#ifdef RT_CAN_USING_HDR
+    can.device.config.maxhdr = 14;
+#endif
+    can.device.config.privmode = RT_CAN_MODE_NOPRIV;
+    can.device.config.ticks = 50;
+    can.device.config.reserved = ES_CAN0_SJW;
     /* register CAN1 device */
-    rt_hw_can_register(&can.device, "can", &_can_ops, &can);
+    rt_hw_can_register(&can.device, ES_DEVICE_NAME_CAN0, &_can_ops, &can);
 
     return 0;
 }

bsp/essemi/es32f0654/drivers/drv_can.h

@@ -3,9 +3,22 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
- * 2019-11-09     wangyq        the first version
+ * 2019-11-09     wangyq        the first version  
+ * 2021-04-20     liuhy         the second version
  */
 
 #ifndef DRV_CAN_H__
@@ -14,16 +27,9 @@
 #include <board.h>
 #include <rtdevice.h>
 #include <rtthread.h>
+#include "es_conf_info_can.h"
 
-#include <ald_can.h>
-#include <ald_gpio.h>
-
-struct es32f0_baud_rate_tab
-{
-    rt_uint32_t baud_rate;
-    rt_uint32_t config_data;
-};
-
+#ifdef RT_USING_CAN
 /* es32f0 can device */
 struct es32f0_can
 {
@@ -34,4 +40,5 @@ struct es32f0_can
 
 int rt_hw_can_init(void);
 
+#endif
 #endif /*DRV_CAN_H__ */

bsp/essemi/es32f0654/drivers/drv_gpio.c

@@ -1,102 +1,33 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-23     wangyq        the first version
- * 2019-11-01     wangyq        update libraries
+ * 2019-11-01     wangyq        update libraries 
+ * 2021-04-20     liuhy         the second version
  */
 
-#include <rthw.h>
-#include <rtdevice.h>
 #include "board.h"
 #include "drv_gpio.h"
-#include <ald_cmu.h>
-#include <ald_gpio.h>
-
-#ifdef RT_USING_PIN
 
-#define __ES32F0_PIN(index, gpio, gpio_index) {index, GPIO##gpio, GPIO_PIN_##gpio_index}
-#define __ES32F0_PIN_DEFAULT {-1, 0, 0}
+/*管脚映射在 es_conf_info_map.h 的 pins[] 中*/
 
-/* ES32F0 GPIO driver */
-struct pin_index
-{
-    int index;
-    GPIO_TypeDef *gpio;
-    uint32_t pin;
-};
-
-static const struct pin_index pins[] =
-{
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN(2, C, 13),
-    __ES32F0_PIN(3, C, 14),
-    __ES32F0_PIN(4, C, 15),
-    __ES32F0_PIN(5, H, 0),
-    __ES32F0_PIN(6, H, 1),
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN(8, C, 0),
-    __ES32F0_PIN(9, C, 1),
-    __ES32F0_PIN(10, C, 2),
-    __ES32F0_PIN(11, C, 3),
-    __ES32F0_PIN(12, H, 3),
-    __ES32F0_PIN(13, H, 4),
-    __ES32F0_PIN(14, A, 0),
-    __ES32F0_PIN(15, A, 1),
-    __ES32F0_PIN(16, A, 2),
-    __ES32F0_PIN(17, A, 3),
-    __ES32F0_PIN(18, F, 0),
-    __ES32F0_PIN(19, F, 1),
-    __ES32F0_PIN(20, A, 4),
-    __ES32F0_PIN(21, A, 5),
-    __ES32F0_PIN(22, A, 6),
-    __ES32F0_PIN(23, A, 7),
-    __ES32F0_PIN(24, C, 4),
-    __ES32F0_PIN(25, C, 5),
-    __ES32F0_PIN(26, B, 0),
-    __ES32F0_PIN(27, B, 1),
-    __ES32F0_PIN(28, B, 2),
-    __ES32F0_PIN(29, B, 10),
-    __ES32F0_PIN(30, B, 11),
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN(33, B, 12),
-    __ES32F0_PIN(34, B, 13),
-    __ES32F0_PIN(35, B, 14),
-    __ES32F0_PIN(36, B, 15),
-    __ES32F0_PIN(37, C, 6),
-    __ES32F0_PIN(38, C, 7),
-    __ES32F0_PIN(39, C, 8),
-    __ES32F0_PIN(40, C, 9),
-    __ES32F0_PIN(41, A, 8),
-    __ES32F0_PIN(42, A, 9),
-    __ES32F0_PIN(43, A, 10),
-    __ES32F0_PIN(44, A, 11),
-    __ES32F0_PIN(45, A, 12),
-    __ES32F0_PIN(46, A, 13),
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN(49, A, 14),
-    __ES32F0_PIN(50, A, 15),
-    __ES32F0_PIN(51, C, 10),
-    __ES32F0_PIN(52, C, 11),
-    __ES32F0_PIN(53, C, 12),
-    __ES32F0_PIN(54, D, 2),
-    __ES32F0_PIN(55, B, 3),
-    __ES32F0_PIN(56, B, 4),
-    __ES32F0_PIN(57, B, 5),
-    __ES32F0_PIN(58, B, 6),
-    __ES32F0_PIN(59, B, 7),
-    __ES32F0_PIN(60, H, 2),
-    __ES32F0_PIN(61, B, 8),
-    __ES32F0_PIN(62, B, 9),
-    __ES32F0_PIN_DEFAULT,
-    __ES32F0_PIN_DEFAULT,
-};
+#ifdef RT_USING_PIN
 
 struct pin_irq_map
 {
@@ -143,6 +74,150 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
     { -1, 0, RT_NULL, RT_NULL},
 };
 
+#ifdef ES_CONF_EXTI_IRQ_0
+
+RT_WEAK void irq_pin0_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 0\r\n");
+}      
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_1 
+
+RT_WEAK void irq_pin1_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 1\r\n");
+}      
+  
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_2
+  
+   RT_WEAK void irq_pin2_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 2\r\n"); 
+}   
+
+#endif
+
+#ifdef ES_CONF_EXTI_IRQ_3
+  
+RT_WEAK void irq_pin3_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 3\r\n"); 
+}      
+  
+#endif  
+
+#ifdef ES_CONF_EXTI_IRQ_4
+  
+RT_WEAK void irq_pin4_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 4\r\n"); 
+}     
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_5
+  
+RT_WEAK void irq_pin5_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 5\r\n"); 
+}      
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_6
+  
+RT_WEAK void irq_pin6_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 6\r\n"); 
+}     
+  
+#endif    
+    
+#ifdef ES_CONF_EXTI_IRQ_7
+  
+RT_WEAK void irq_pin7_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 7\r\n"); 
+}      
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_8
+  
+RT_WEAK void irq_pin8_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 8\r\n"); 
+}     
+  
+#endif    
+   
+#ifdef ES_CONF_EXTI_IRQ_9
+  
+RT_WEAK void irq_pin9_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 9\r\n"); 
+}     
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_10
+  
+RT_WEAK void irq_pin10_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 10\r\n"); 
+}    
+  
+#endif    
+ 
+#ifdef ES_CONF_EXTI_IRQ_11
+  
+RT_WEAK void irq_pin11_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 11\r\n"); 
+}    
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_12
+  
+RT_WEAK void irq_pin12_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 12\r\n"); 
+}    
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_13
+  
+RT_WEAK void irq_pin13_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 13\r\n"); 
+}   
+  
+#endif    
+  
+#ifdef ES_CONF_EXTI_IRQ_14
+  
+RT_WEAK void irq_pin14_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 14\r\n"); 
+}    
+  
+#endif    
+
+#ifdef ES_CONF_EXTI_IRQ_15
+  
+RT_WEAK void irq_pin15_callback(void* arg)
+{
+    rt_kprintf("\r\nEXTI 15\r\n"); 
+}    
+  
+#endif    
+
+
 #define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
 const struct pin_index *get_pin(uint8_t pin)
 {
@@ -408,18 +483,9 @@ const static struct rt_pin_ops _es32f0_pin_ops =
     es32f0_pin_attach_irq,
     es32f0_pin_detach_irq,
     es32f0_pin_irq_enable,
-    RT_NULL,
+    /*RT_NULL,*/
 };
 
-int rt_hw_pin_init(void)
-{
-    int result;
-    ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
-    result = rt_device_pin_register("pin", &_es32f0_pin_ops, RT_NULL);
-    return result;
-}
-INIT_BOARD_EXPORT(rt_hw_pin_init);
-
 rt_inline void pin_irq_hdr(uint16_t GPIO_Pin)
 {
     uint16_t irqno;
@@ -488,4 +554,44 @@ void EXTI12_15_Handler(void)
     rt_interrupt_leave();
 }
 
+int rt_hw_pin_init(void)
+{
+    int result;
+   
+
+#ifdef   ES_INIT_GPIOS
+                                                              
+    rt_size_t i,gpio_conf_num = sizeof(gpio_conf_all) / sizeof(gpio_conf_t);
+
+#endif       
+
+    ald_cmu_perh_clock_config(CMU_PERH_GPIO, ENABLE);
+    
+    result = rt_device_pin_register(ES_DEVICE_NAME_PIN, &_es32f0_pin_ops, RT_NULL);
+
+    if(result != RT_EOK)return result;
+
+#ifdef   ES_INIT_GPIOS
+
+       for(i = 0;i < gpio_conf_num;i++)
+    {
+        rt_pin_mode( gpio_conf_all[i].pin,gpio_conf_all[i].pin_mode);
+    
+        if((gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT)||(gpio_conf_all[i].pin_mode == ES_C_GPIO_MODE_OUTPUT_OD))
+        rt_pin_write(gpio_conf_all[i].pin,gpio_conf_all[i].pin_level);
+        
+        if(!gpio_conf_all[i].irq_en)continue;
+        
+        rt_pin_attach_irq(gpio_conf_all[i].pin, gpio_conf_all[i].irq_mode, gpio_conf_all[i].callback, RT_NULL);
+        rt_pin_irq_enable(gpio_conf_all[i].pin, gpio_conf_all[i].irq_en);
+    }
+    
+#endif        
+    
+
+    
+    return result;
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
 #endif

bsp/essemi/es32f0654/drivers/drv_gpio.h

@@ -3,14 +3,29 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-23     wangyq        the first version
+ * 2021-04-20     liuhy         the second version  
  */
 
 #ifndef DRV_GPIO_H__
 #define DRV_GPIO_H__
 
+#include "es_conf_info_gpio.h"
+
 int rt_hw_pin_init(void);
 
 #endif

bsp/essemi/es32f0654/drivers/drv_hwtimer.c

@@ -1,21 +1,33 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author       Notes
  * 2019-3-19      wangyq       the first version
  * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <drv_hwtimer.h>
-#include <board.h>
-#include <ald_cmu.h>
-#include <ald_timer.h>
+#include <board.h> 
+
 
 #ifdef RT_USING_HWTIMER
 
@@ -26,93 +38,172 @@ struct es32f0_hwtimer_dev
     IRQn_Type IRQn;
 };
 
-#ifdef BSP_USING_HWTIMER0
-static struct es32f0_hwtimer_dev hwtimer0;
+#ifdef BSP_USING_AD16C4T0_HWTIMER
+static struct es32f0_hwtimer_dev ad16c4t0_hwtimer;
 
-void BS16T0_Handler(void)
+static struct rt_hwtimer_info ad16c4t0_info =
 {
-    ald_timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE);
-    rt_device_hwtimer_isr(&hwtimer0.parent);
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_AD16C4T0_HWTIMER_MODE
+};
 
-    if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode)
-    {
-        ald_timer_base_stop(hwtimer0.hwtimer_periph);
-    }
+void AD16C4T0_BRK_UP_TRIG_COM_Handler(void)
+{
+    ald_timer_clear_flag_status(ad16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&ad16c4t0_hwtimer.parent);
 }
+
 #endif
 
-#ifdef BSP_USING_HWTIMER1
-static struct es32f0_hwtimer_dev hwtimer1;
-/* can not use when UART2 Handler is enabled */
-void BS16T1_UART2_Handler(void)
+#ifdef BSP_USING_GP16C4T0_HWTIMER
+
+static struct es32f0_hwtimer_dev gp16c4t0_hwtimer;
+
+static struct rt_hwtimer_info gp16c4t0_info =
 {
-    /* if BS16T1 it */
-    if (ald_timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) &&
-            ald_timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE))
-    {
-        ald_timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE);
-        rt_device_hwtimer_isr(&hwtimer1.parent);
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_GP16C4T0_HWTIMER_MODE
+};
 
-        if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode)
-        {
-            ald_timer_base_stop(hwtimer1.hwtimer_periph);
-        }
-    }
+void GP16C4T0_LCD_Handler(void)
+{
+    ald_timer_clear_flag_status(gp16c4t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&gp16c4t0_hwtimer.parent);
 }
+
 #endif
 
-#ifdef BSP_USING_HWTIMER2
-static struct es32f0_hwtimer_dev hwtimer2;
-/* can not use when UART3 Handler is enabled */
-void BS16T2_UART3_Handler(void)
+#ifdef BSP_USING_GP16C2T0_HWTIMER
+
+static struct es32f0_hwtimer_dev gp16c2t0_hwtimer;
+
+static struct rt_hwtimer_info gp16c2t0_info =
 {
-    /* if BS16T2 it */
-    if (ald_timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) &&
-            ald_timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE))
-    {
-        ald_timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE);
-        rt_device_hwtimer_isr(&hwtimer2.parent);
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_GP16C2T0_HWTIMER_MODE
+};
 
-        if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode)
-        {
-            ald_timer_base_stop(hwtimer2.hwtimer_periph);
-        }
-    }
+void GP16C2T0_Handler(void)
+{
+    ald_timer_clear_flag_status(gp16c2t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&gp16c2t0_hwtimer.parent);
 }
+
 #endif
 
-#ifdef BSP_USING_HWTIMER3
-static struct es32f0_hwtimer_dev hwtimer3;
-/* can not use when DAC0 Handler is enabled */
-void BS16T3_DAC0_Handler(void)
+#ifdef BSP_USING_GP16C2T1_HWTIMER
+
+static struct es32f0_hwtimer_dev gp16c2t1_hwtimer;
+
+static struct rt_hwtimer_info gp16c2t1_info =
 {
-    /* if BS16T3 it */
-    if (ald_timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) &&
-            ald_timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE))
-    {
-        ald_timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE);
-        rt_device_hwtimer_isr(&hwtimer3.parent);
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_GP16C2T1_HWTIMER_MODE
+};
 
-        if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode)
-        {
-            ald_timer_base_stop(hwtimer3.hwtimer_periph);
-        }
-    }
+void GP16C2T1_Handler(void)
+{
+    ald_timer_clear_flag_status(gp16c2t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&gp16c2t1_hwtimer.parent);
+}
+
+#endif
+
+#ifdef BSP_USING_BS16T0_HWTIMER
+
+static struct es32f0_hwtimer_dev bs16t0_hwtimer;
+
+static struct rt_hwtimer_info bs16t0_info =
+{
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_BS16T0_HWTIMER_MODE
+};
+
+void BS16T0_Handler(void)
+{
+    ald_timer_clear_flag_status(bs16t0_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&bs16t0_hwtimer.parent);
 }
+
+#endif
+
+#ifdef BSP_USING_BS16T1_HWTIMER
+
+static struct es32f0_hwtimer_dev bs16t1_hwtimer;
+
+static struct rt_hwtimer_info bs16t1_info =
+{
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_BS16T1_HWTIMER_MODE
+};
+
+void BS16T1_UART2_Handler(void)
+{
+    ald_timer_clear_flag_status(bs16t1_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&bs16t1_hwtimer.parent);
+}
+
 #endif
 
-static struct rt_hwtimer_info es32f0_hwtimer_info =
+#ifdef BSP_USING_BS16T2_HWTIMER
+
+static struct es32f0_hwtimer_dev bs16t2_hwtimer;
+
+static struct rt_hwtimer_info bs16t2_info =
 {
-    48000000, /* maximum count frequency */
-    1,        /* minimum count frequency */
-    65535,    /* counter maximum value */
-    HWTIMER_CNTMODE_UP
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_BS16T2_HWTIMER_MODE
 };
 
+void BS16T2_UART3_Handler(void)
+{
+    ald_timer_clear_flag_status(bs16t2_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&bs16t2_hwtimer.parent);
+}
+
+#endif
+
+#ifdef BSP_USING_BS16T3_HWTIMER
+
+static struct es32f0_hwtimer_dev bs16t3_hwtimer;
+
+static struct rt_hwtimer_info bs16t3_info =
+{
+    ES_SYS_CLK >> ES_CMU_PCLK_1_DIV, /* maximum count frequency */
+    (ES_SYS_CLK >> ES_CMU_PCLK_1_DIV)/(1U<<16),        /* minimum count frequency */
+    0xFFFF,    /* counter maximum value */
+    ES_BS16T3_HWTIMER_MODE
+};
+
+void BS16T3_DAC0_Handler(void)
+{
+    ald_timer_clear_flag_status(bs16t3_hwtimer.hwtimer_periph, TIMER_FLAG_UPDATE);
+    rt_device_hwtimer_isr(&bs16t3_hwtimer.parent);
+}
+
+#endif
+
 static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
 {
     struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data;
 
+    struct rt_hwtimer_info *hwtimer_info = (struct rt_hwtimer_info *)timer->info;
+
+    
     RT_ASSERT(hwtimer != RT_NULL);
 
     if (1 == state)
@@ -121,9 +212,10 @@ static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
         ald_timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE);
         NVIC_EnableIRQ(hwtimer->IRQn);
     }
-    hwtimer->parent.freq = ald_cmu_get_pclk1_clock();
-    es32f0_hwtimer_info.maxfreq = ald_cmu_get_pclk1_clock();
-    es32f0_hwtimer_info.minfreq = ald_cmu_get_pclk1_clock();
+    
+    hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
+    hwtimer_info->maxfreq = hwtimer->parent.freq;
+    hwtimer_info->minfreq = (hwtimer->parent.freq)/0xFFFF;
 }
 
 static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer,
@@ -175,10 +267,37 @@ static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer,
     {
     case HWTIMER_CTRL_FREQ_SET:
         freq = *(rt_uint32_t *)args;
-        if (freq != ald_cmu_get_pclk1_clock())
-        {
-            ret = -RT_ERROR;
+    
+        ret = -RT_ERROR;
+    
+        if(freq)
+        {   
+            double temp,target;
+            temp = (double)ald_cmu_get_pclk1_clock();
+            target = temp/freq;
+        
+            if(target < 0x10001)   /*×î´ó·ÖƵ = max(PRES)+1*/
+            {
+                temp = target - (int)(target);
+            
+                if((temp > 0.998)&&(target < 0x10000))
+                {
+                    hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target;
+                    ret = RT_EOK;
+                }
+                if((temp < 0.002)&&(target >= 0x1))
+                {
+                    hwtimer->hwtimer_periph->perh->PRES = (uint32_t)target - 1;
+                    ret = RT_EOK;
+                }
+             
+            }
+            
+            if(ret == RT_EOK)     /*¸üÐÂÐÅÏ¢*/
+                hwtimer->parent.freq = ald_cmu_get_pclk1_clock()/((hwtimer->hwtimer_periph->perh->PRES & 0xFFFF)+1);
+    
         }
+       
         break;
 
     case HWTIMER_CTRL_STOP:
@@ -206,46 +325,127 @@ int rt_hw_hwtimer_init(void)
 {
     rt_err_t ret = RT_EOK;
 
-#ifdef BSP_USING_HWTIMER0
-    static timer_handle_t _hwtimer_periph0;
-    _hwtimer_periph0.perh = BS16T0;
-    hwtimer0.IRQn = BS16T0_IRQn;
-    hwtimer0.hwtimer_periph = &_hwtimer_periph0;
-    hwtimer0.parent.info = &es32f0_hwtimer_info;
-    hwtimer0.parent.ops = &es32f0_hwtimer_ops;
-    ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0);
-#endif
-
-#ifdef BSP_USING_HWTIMER1
-    static timer_handle_t _hwtimer_periph1;
-    _hwtimer_periph1.perh = BS16T1;
-    hwtimer1.IRQn = BS16T1_UART2_IRQn;
-    hwtimer1.hwtimer_periph = &_hwtimer_periph1;
-    hwtimer1.parent.info = &es32f0_hwtimer_info;
-    hwtimer1.parent.ops = &es32f0_hwtimer_ops;
-    ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1);
-#endif
-
-#ifdef BSP_USING_HWTIMER2
-    static timer_handle_t _hwtimer_periph2;
-    _hwtimer_periph2.perh = BS16T2;
-    hwtimer2.IRQn = BS16T2_UART3_IRQn;
-    hwtimer2.hwtimer_periph = &_hwtimer_periph2;
-    hwtimer2.parent.info = &es32f0_hwtimer_info;
-    hwtimer2.parent.ops = &es32f0_hwtimer_ops;
-    ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2);
-#endif
-
-#ifdef BSP_USING_HWTIMER3
-    static timer_handle_t _hwtimer_periph3;
-    _hwtimer_periph3.perh = BS16T3;
-    hwtimer3.IRQn = BS16T3_DAC0_IRQn;
-    hwtimer3.hwtimer_periph = &_hwtimer_periph3;
-    hwtimer3.parent.info = &es32f0_hwtimer_info;
-    hwtimer3.parent.ops = &es32f0_hwtimer_ops;
-    ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3);
+#ifdef BSP_USING_AD16C4T0_HWTIMER
+    static timer_handle_t ad16c4t0_hwtimer_periph;
+    
+    ad16c4t0_hwtimer_periph.perh = AD16C4T0;
+    ad16c4t0_hwtimer.IRQn = AD16C4T0_BRK_UP_TRIG_COM_IRQn;
+    
+    ad16c4t0_hwtimer_periph.init.prescaler = ES_AD16C4T0_HWTIMER_PRES - 1;  
+    ad16c4t0_hwtimer_periph.init.mode = ( ES_AD16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    ad16c4t0_hwtimer.hwtimer_periph = &ad16c4t0_hwtimer_periph;
+    
+    ad16c4t0_hwtimer.parent.info = &ad16c4t0_info;
+    ad16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&ad16c4t0_hwtimer.parent, ES_DEVICE_NAME_AD16C4T0_HWTIMER, &ad16c4t0_hwtimer);
+#endif
+
+#ifdef BSP_USING_GP16C4T0_HWTIMER
+    static timer_handle_t gp16c4t0_hwtimer_periph;
+    
+    gp16c4t0_hwtimer_periph.perh = GP16C4T0;
+    gp16c4t0_hwtimer.IRQn = GP16C4T0_LCD_IRQn;
+    
+    gp16c4t0_hwtimer_periph.init.prescaler = ES_GP16C4T0_HWTIMER_PRES - 1;  
+    gp16c4t0_hwtimer_periph.init.mode = ( ES_GP16C4T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    gp16c4t0_hwtimer.hwtimer_periph = &gp16c4t0_hwtimer_periph;
+    
+    gp16c4t0_hwtimer.parent.info = &gp16c4t0_info;
+    gp16c4t0_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&gp16c4t0_hwtimer.parent, ES_DEVICE_NAME_GP16C4T0_HWTIMER, &gp16c4t0_hwtimer);
+#endif
+
+#ifdef BSP_USING_GP16C2T0_HWTIMER
+    static timer_handle_t gp16c2t0_hwtimer_periph;
+    
+    gp16c2t0_hwtimer_periph.perh = GP16C2T0;
+    gp16c2t0_hwtimer.IRQn = GP16C2T0_IRQn;
+    
+    gp16c2t0_hwtimer_periph.init.prescaler = ES_GP16C2T0_HWTIMER_PRES - 1;  
+    gp16c2t0_hwtimer_periph.init.mode = ( ES_GP16C2T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    gp16c2t0_hwtimer.hwtimer_periph = &gp16c2t0_hwtimer_periph;
+    
+    gp16c2t0_hwtimer.parent.info = &gp16c2t0_info;
+    gp16c2t0_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&gp16c2t0_hwtimer.parent, ES_DEVICE_NAME_GP16C2T0_HWTIMER, &gp16c2t0_hwtimer);
 #endif
 
+#ifdef BSP_USING_GP16C2T1_HWTIMER
+    static timer_handle_t gp16c2t1_hwtimer_periph;
+    
+    gp16c2t1_hwtimer_periph.perh = GP16C2T1;
+    gp16c2t1_hwtimer.IRQn = GP16C2T1_IRQn;
+    
+    gp16c2t1_hwtimer_periph.init.prescaler = ES_GP16C2T1_HWTIMER_PRES - 1;  
+    gp16c2t1_hwtimer_periph.init.mode = ( ES_GP16C2T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    gp16c2t1_hwtimer.hwtimer_periph = &gp16c2t1_hwtimer_periph;
+    
+    gp16c2t1_hwtimer.parent.info = &gp16c2t1_info;
+    gp16c2t1_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&gp16c2t1_hwtimer.parent, ES_DEVICE_NAME_GP16C2T1_HWTIMER, &gp16c2t1_hwtimer);
+#endif
+
+#ifdef BSP_USING_BS16T0_HWTIMER
+    static timer_handle_t bs16t0_hwtimer_periph;
+    
+    bs16t0_hwtimer_periph.perh = BS16T0;
+    bs16t0_hwtimer.IRQn = BS16T0_IRQn;
+    
+    bs16t0_hwtimer_periph.init.prescaler = ES_BS16T0_HWTIMER_PRES - 1;  
+    bs16t0_hwtimer_periph.init.mode = ( ES_BS16T0_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    bs16t0_hwtimer.hwtimer_periph = &bs16t0_hwtimer_periph;
+    
+    bs16t0_hwtimer.parent.info = &bs16t0_info;
+    bs16t0_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&bs16t0_hwtimer.parent, ES_DEVICE_NAME_BS16T0_HWTIMER, &bs16t0_hwtimer);
+#endif
+
+#ifdef BSP_USING_BS16T1_HWTIMER
+    static timer_handle_t bs16t1_hwtimer_periph;
+    
+    bs16t1_hwtimer_periph.perh = BS16T1;
+    bs16t1_hwtimer.IRQn = BS16T1_UART2_IRQn;
+    
+    bs16t1_hwtimer_periph.init.prescaler = ES_BS16T1_HWTIMER_PRES - 1;  
+    bs16t1_hwtimer_periph.init.mode = ( ES_BS16T1_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    bs16t1_hwtimer.hwtimer_periph = &bs16t1_hwtimer_periph;
+    
+    bs16t1_hwtimer.parent.info = &bs16t1_info;
+    bs16t1_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&bs16t1_hwtimer.parent, ES_DEVICE_NAME_BS16T1_HWTIMER, &bs16t1_hwtimer);
+#endif
+
+#ifdef BSP_USING_BS16T2_HWTIMER
+    static timer_handle_t bs16t2_hwtimer_periph;
+    
+    bs16t2_hwtimer_periph.perh = BS16T2;
+    bs16t2_hwtimer.IRQn = BS16T2_UART3_IRQn;
+    
+    bs16t2_hwtimer_periph.init.prescaler = ES_BS16T2_HWTIMER_PRES - 1;  
+    bs16t2_hwtimer_periph.init.mode = ( ES_BS16T2_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    bs16t2_hwtimer.hwtimer_periph = &bs16t2_hwtimer_periph;
+    
+    bs16t2_hwtimer.parent.info = &bs16t2_info;
+    bs16t2_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&bs16t2_hwtimer.parent, ES_DEVICE_NAME_BS16T2_HWTIMER, &bs16t2_hwtimer);
+#endif
+
+#ifdef BSP_USING_BS16T3_HWTIMER
+    static timer_handle_t bs16t3_hwtimer_periph;
+    
+    bs16t3_hwtimer_periph.perh = BS16T3;
+    bs16t3_hwtimer.IRQn = BS16T3_DAC0_IRQn;
+    
+    bs16t3_hwtimer_periph.init.prescaler = ES_BS16T3_HWTIMER_PRES - 1;  
+    bs16t3_hwtimer_periph.init.mode = ( ES_BS16T3_HWTIMER_MODE == HWTIMER_CNTMODE_UP )? TIMER_CNT_MODE_UP : TIMER_CNT_MODE_DOWN;
+    bs16t3_hwtimer.hwtimer_periph = &bs16t3_hwtimer_periph;
+    
+    bs16t3_hwtimer.parent.info = &bs16t3_info;
+    bs16t3_hwtimer.parent.ops = &es32f0_hwtimer_ops;
+    ret = rt_device_hwtimer_register(&bs16t3_hwtimer.parent, ES_DEVICE_NAME_BS16T3_HWTIMER, &bs16t3_hwtimer);
+#endif
+
+
     return ret;
 }
 INIT_BOARD_EXPORT(rt_hw_hwtimer_init);

bsp/essemi/es32f0654/drivers/drv_hwtimer.h

@@ -3,14 +3,28 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author       Notes
- * 2019-3-19      wangyq       the first version
+ * 2019-3-19      wangyq       the first version   
+ * 2021-04-20     liuhy         the second version
  */
 
 #ifndef DRV_HWTIMER_H__
 #define DRV_HWTIMER_H__
 
+#include "es_conf_info_hwtimer.h"
 int rt_hw_hwtimer_init(void);
 
 #endif

bsp/essemi/es32f0654/drivers/drv_i2c.c

@@ -1,8 +1,19 @@
 /*
- * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-24     wangyq        the first version
@@ -10,19 +21,24 @@
  * 2020-12-15     liuhy         update libraries
  */
 
+#include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
-#include <rtdbg.h>
 #include "board.h"
 #include "drv_i2c.h"
-#include <ald_i2c.h>
-#include <ald_gpio.h>
+
 
 #ifdef RT_USING_I2C
 
 #define TIMEOUT 0x0FFF
 /* I2C struct definition */
-static i2c_handle_t _h_i2c0, _h_i2c1;
+#ifdef BSP_USING_I2C0
+    static i2c_handle_t _h_i2c0;
+#endif
+
+#ifdef BSP_USING_I2C1
+    static i2c_handle_t _h_i2c1;
+#endif
 
 static void _i2c_init(void)
 {
@@ -38,35 +54,55 @@ static void _i2c_init(void)
     gpio_instruct.func = GPIO_FUNC_5;
 
 #ifdef BSP_USING_I2C0
+    
+#if  defined(ES_I2C0_SCL_GPIO_FUNC)&&defined(ES_I2C0_SCL_GPIO_PORT)&&defined(ES_I2C0_SCL_GPIO_PIN)     
+    gpio_instruct.func = ES_I2C0_SCL_GPIO_FUNC;
+    ald_gpio_init(ES_I2C0_SCL_GPIO_PORT, ES_I2C0_SCL_GPIO_PIN, &gpio_instruct);
+#endif                            
+             
+#if  defined(ES_I2C0_SDA_GPIO_FUNC)&&defined(ES_I2C0_SDA_GPIO_PORT)&&defined(ES_I2C0_SDA_GPIO_PIN)
+    gpio_instruct.func = ES_I2C0_SDA_GPIO_FUNC;
+    ald_gpio_init(ES_I2C0_SDA_GPIO_PORT, ES_I2C0_SDA_GPIO_PIN, &gpio_instruct); 
+#endif                            
+
     /* Initialize I2C Function */
     _h_i2c0.perh = I2C0;
-    _h_i2c0.init.clk_speed    = 100000;
     _h_i2c0.init.duty         = I2C_DUTYCYCLE_2;
-    _h_i2c0.init.own_addr1    = 0x0A;
-    _h_i2c0.init.addr_mode    = I2C_ADDR_7BIT;
-    _h_i2c0.init.general_call = I2C_GENERALCALL_DISABLE;
-    _h_i2c0.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
+    _h_i2c0.init.clk_speed    = ES_I2C0_CLK_SPEED;
+    _h_i2c0.init.own_addr1    = ES_I2C0_OWN_ADDR1;
+    _h_i2c0.init.addr_mode    = ES_I2C0_ADDR_MODE;
+    _h_i2c0.init.general_call = ES_I2C0_GENERAL_CALL;
+    _h_i2c0.init.no_stretch   = ES_I2C0_STRETCH;
 
     ald_i2c_reset(&_h_i2c0);
     ald_i2c_init(&_h_i2c0);
-    /* I2C0_SCL->PB8,  I2C0_SDA->PB9 */
-    ald_gpio_init(GPIOB, GPIO_PIN_8 | GPIO_PIN_9, &gpio_instruct);
+               
 #endif
 
 #ifdef BSP_USING_I2C1
+
+#if  defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN)    
+    gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC;
+    ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct);
+#endif          
+                                                               
+#if  defined(ES_I2C1_SDA_GPIO_FUNC)&&defined(ES_I2C1_SDA_GPIO_PORT)&&defined(ES_I2C1_SDA_GPIO_PIN)   
+    gpio_instruct.func = ES_I2C1_SDA_GPIO_FUNC;
+    ald_gpio_init(ES_I2C1_SDA_GPIO_PORT, ES_I2C1_SDA_GPIO_PIN, &gpio_instruct);
+#endif         
+
     /* Initialize i2c function */
     _h_i2c1.perh = I2C1;
-    _h_i2c1.init.clk_speed    = 100000;
-    _h_i2c1.init.duty         = I2C_DUTYCYCLE_2;
-    _h_i2c1.init.own_addr1    = 0xA0;
-    _h_i2c1.init.addr_mode    = I2C_ADDR_7BIT;
-    _h_i2c1.init.general_call = I2C_GENERALCALL_DISABLE;
-    _h_i2c1.init.no_stretch   = I2C_NOSTRETCH_ENABLE;
-
+    _h_i2c1.init.duty         = I2C_DUTYCYCLE_2; 
+    _h_i2c1.init.clk_speed    = ES_I2C1_CLK_SPEED;
+    _h_i2c1.init.own_addr1    = ES_I2C1_OWN_ADDR1;
+    _h_i2c1.init.addr_mode    = ES_I2C1_ADDR_MODE;
+    _h_i2c1.init.general_call = ES_I2C1_GENERAL_CALL;
+    _h_i2c1.init.no_stretch   = ES_I2C1_STRETCH;
+    
     ald_i2c_reset(&_h_i2c1);
     ald_i2c_init(&_h_i2c1);
-    /* I2C1_SCL->PB10, I2C1_SDA->PB11 */
-    ald_gpio_init(GPIOB, GPIO_PIN_10 | GPIO_PIN_11, &gpio_instruct);
+     
 #endif
 }
 
@@ -116,6 +152,8 @@ const struct rt_i2c_bus_device_ops es32f0_i2c_ops =
 
 int rt_hw_i2c_init(void)
 {
+    int result = RT_EOK;
+
     _i2c_init();
 
 #ifdef BSP_USING_I2C0
@@ -124,16 +162,25 @@ int rt_hw_i2c_init(void)
     rt_memset((void *)&_i2c_device0, 0, sizeof(struct rt_i2c_bus_device));
     _i2c_device0.ops = &es32f0_i2c_ops;
     _i2c_device0.priv = &_h_i2c0;
-    rt_i2c_bus_device_register(&_i2c_device0, "i2c0");
+    result = rt_i2c_bus_device_register(&_i2c_device0, ES_DEVICE_NAME_I2C0);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
 #endif
 
 #ifdef BSP_USING_I2C1
     /* define i2c Instance */
     static struct rt_i2c_bus_device _i2c_device1;
     rt_memset((void *)&_i2c_device1, 0, sizeof(struct rt_i2c_bus_device));
+
     _i2c_device1.ops = &es32f0_i2c_ops;
     _i2c_device1.priv = &_h_i2c1;
-    rt_i2c_bus_device_register(&_i2c_device1, "i2c1");
+    rt_i2c_bus_device_register(&_i2c_device1, ES_DEVICE_NAME_I2C1);
+    if (result != RT_EOK)
+    {
+        return result;
+    }
 #endif
 
     return RT_EOK;

bsp/essemi/es32f0654/drivers/drv_i2c.h

@@ -1,16 +1,31 @@
 /*
  * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
  *
- * SPDX-License-Identifier: Apache-2.0
+ * SPDX-License-Identifier: Apache-2.0 
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
  *
  * Change Logs:
  * Date           Author        Notes
- * 2019-01-24     wangyq        the first version
+ * 2019-01-24     wangyq        the first version 
+ * 2021-04-20     liuhy         the second version
  */
 
 #ifndef DRV_I2C_H__
 #define DRV_I2C_H__
 
+#include "es_conf_info_i2c.h"
+
 int rt_hw_i2c_init(void);
 
 #endif

bsp/essemi/es32f0654/drivers/drv_pm.c

@@ -3,20 +3,30 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-04-08     wangyq        the first version
  * 2019-11-01     wangyq        adapt to the new power management interface
+ * 2020-12-15     liuhy        the first version
  */
 
-#include <rthw.h>
-#include <board.h>
-#include <rtdevice.h>
-#include <ald_cmu.h>
-#include <ald_pmu.h>
+#include "drv_pm.h" 
 
 #ifdef RT_USING_PM
 
+
 static void uart_console_reconfig(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
@@ -24,26 +34,14 @@ static void uart_console_reconfig(void)
     rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config);
 }
 
-static void delay(void)
-{
-    long i;
-    rt_base_t level;
-
-    level = rt_hw_interrupt_disable();
-    i = 0;
-    do{
-        i++;
-    }
-    while (i < 10000); 
-    
-    rt_hw_interrupt_enable(level);
-}
-
 /**
- * This function will put ES32F033x into sleep mode.
+ * This function will put ES32F065x into sleep mode.
  *
  * @param pm pointer to power manage structure
  */
+
+
+/* 注意：进入睡眠前，如果有中断挂起（SYSTICK、PENDSV、UART、EXTI等），睡眠将被瞬间唤醒。*/
 static void sleep(struct rt_pm *pm, uint8_t mode)
 {
     switch (mode)
@@ -52,31 +50,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode)
         break;
 
     case PM_SLEEP_MODE_IDLE:
-        //__WFI();
         break;
 
     case PM_SLEEP_MODE_LIGHT:
         /* Enter SLEEP Mode, Main regulator is ON */
         ald_pmu_stop1_enter();
-        delay();
         break;
 
-    case PM_SLEEP_MODE_DEEP:
-        /* Enter STOP 2 mode  */
+    case PM_SLEEP_MODE_DEEP:           
+        /* Enter STOP 2 mode  */   
         ald_pmu_stop2_enter();
-        delay();
         break;
 
     case PM_SLEEP_MODE_STANDBY:
-        /* Enter STANDBY mode */
+        /* Enter STANDBY mode */  
         ald_pmu_stop2_enter();
-        delay();
         break;
 
     case PM_SLEEP_MODE_SHUTDOWN:
-        /* Enter SHUTDOWNN mode */
+        /* Enter SHUTDOWNN mode */       
         ald_pmu_stop2_enter();
-        delay();
         break;
 
     default:

bsp/essemi/es32f0654/drivers/drv_pm.h

@@ -3,7 +3,20 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
+
  * Date           Author        Notes
  * 2019-04-01     wangyq        the first version
  */
@@ -11,6 +24,12 @@
 #ifndef DRV_PM_H__
 #define DRV_PM_H__
 
+#include <rthw.h>
+#include <board.h>
+#include <rtdevice.h>
+#include "es_conf_info_pm.h"
+#include <string.h>
+
 int rt_hw_pm_init(void);
 
 #endif

bsp/essemi/es32f0654/drivers/drv_pwm.c

@@ -3,28 +3,33 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2019-03-11     wangyq       the first version
  * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
 #include <board.h>
-#include <ald_cmu.h>
-#include <ald_timer.h>
-#include <ald_gpio.h>
+#include "es_conf_info_pwm.h"
 
-static void pwm_set_freq(timer_handle_t *timer_initstruct, uint32_t ns)
-{
-    uint64_t _arr = (uint64_t)ald_cmu_get_pclk1_clock() * ns / 1000000000 /
-                    (timer_initstruct->init.prescaler + 1);
 
-    WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
-    timer_initstruct->init.period   = (uint32_t)_arr;
-}
+#ifdef RT_USING_PWM
 
 static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, uint32_t ns)
 {
@@ -44,7 +49,8 @@ static void pwm_set_duty(timer_handle_t *timer_initstruct, timer_channel_t ch, u
 static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *arg)
 {
     rt_err_t ret = RT_EOK;
-    uint32_t _ccep;
+    uint64_t _arr,bus_speed,tmp;
+    uint32_t _maxcnt,_ccep_ch_en = 0U;
     timer_channel_t pwm_channel;
     timer_oc_init_t tim_ocinit;
     timer_handle_t *timer_initstruct = (timer_handle_t *)device->parent.user_data;
@@ -52,39 +58,30 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
 
     RT_ASSERT(timer_initstruct != RT_NULL);
 
-    tim_ocinit.oc_mode      = TIMER_OC_MODE_PWM1;
-    tim_ocinit.oc_polarity  = TIMER_OC_POLARITY_HIGH;
-    tim_ocinit.oc_fast_en   = DISABLE;
-    tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH;
-    tim_ocinit.ocn_idle     = TIMER_OCN_IDLE_RESET;
-    tim_ocinit.oc_idle      = TIMER_OC_IDLE_RESET;
-
     /* select pwm output channel */
     if (1 == cfg->channel)
     {
         pwm_channel = TIMER_CHANNEL_1;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC1EN_MSK;
     }
-    else if (2 == cfg->channel)
+    else if (2 == cfg->channel)  
     {
         pwm_channel = TIMER_CHANNEL_2;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC2EN_MSK;
     }
-    else if (3 == cfg->channel)
+    else if (3 == cfg->channel)     
     {
-        if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1)
-            return RT_EINVAL;
         pwm_channel = TIMER_CHANNEL_3;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC3EN_MSK;
     }
-    else if (4 == cfg->channel)
+    else if (4 == cfg->channel)    
     {
-        if (timer_initstruct->perh == GP16C2T0 || timer_initstruct->perh == GP16C2T1)
-            return RT_EINVAL;
         pwm_channel = TIMER_CHANNEL_4;
+        _ccep_ch_en = timer_initstruct->perh->CCEP & TIMER_CCEP_CC4EN_MSK;
     }
     else
-    {
         return RT_EINVAL;
-    }
-
+    
     switch (cmd)
     {
     case PWM_CMD_ENABLE:
@@ -96,19 +93,44 @@ static rt_err_t es32f0_pwm_control(struct rt_device_pwm *device, int cmd, void *
         break;
 
     case PWM_CMD_SET:
-        _ccep = timer_initstruct->perh->CCEP;
-        /* count registers max 0xFFFF, auto adjust prescaler */
+        
+          /*当通道没开的时候：关通道，设置输出模式和极性，初始化通道*/
+        if(!_ccep_ch_en) 
+        {        
+         tim_ocinit.oc_mode      = ES_PWM_OC_MODE;   
+         tim_ocinit.oc_polarity  = ES_PWM_OC_POLARITY;
+         tim_ocinit.oc_fast_en   = DISABLE;
+         tim_ocinit.ocn_polarity = TIMER_OCN_POLARITY_HIGH;
+         tim_ocinit.ocn_idle     = TIMER_OCN_IDLE_RESET;
+         tim_ocinit.oc_idle      = TIMER_OC_IDLE_RESET;
+            ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
+        }
+        
+        bus_speed = (uint64_t)ald_cmu_get_pclk1_clock();
+
+        /*外设的计数器最大值*/
+        _maxcnt = 0xFFFF;
+        
+        /*当最大分频 <= _maxcnt时：估计大概的分频，加快速度 */
+        tmp = bus_speed * (cfg->period)/1000000000/_maxcnt;
+        timer_initstruct->init.prescaler = (tmp > 2U) ? (tmp - 2U) : 0U ;    /*bus_speed < 500000000*/
+        
+        /* count registers max , auto adjust prescaler */
         do
         {
-            pwm_set_freq(timer_initstruct, cfg->period);
-            timer_initstruct->init.prescaler ++;
+          _arr = bus_speed * (cfg->period) / 1000000000 /(++timer_initstruct->init.prescaler);
+    
         }
-        while (timer_initstruct->init.period > 0xFFFF);
+        while (_arr > _maxcnt); 
+     
+        WRITE_REG(timer_initstruct->perh->AR, (uint32_t)_arr);
+        timer_initstruct->init.period   = (uint32_t)_arr;
+        
         /* update prescaler */
         WRITE_REG(timer_initstruct->perh->PRES, --timer_initstruct->init.prescaler);
-        ald_timer_oc_config_channel(timer_initstruct, &tim_ocinit, pwm_channel);
+        
         pwm_set_duty(timer_initstruct, pwm_channel, cfg->pulse);
-        timer_initstruct->perh->CCEP = _ccep;
+        
         break;
 
     case PWM_CMD_GET:
@@ -139,74 +161,124 @@ int rt_hw_pwm_init(void)
     gpio_initstructure.flt  = GPIO_FILTER_DISABLE;
     gpio_initstructure.type = GPIO_TYPE_TTL;
 
-#ifdef BSP_USING_PWM0 /* 4 channels */
-    static struct rt_device_pwm pwm_dev0;
-    static timer_handle_t timer_initstruct0;
+#ifdef BSP_USING_AD16C4T0_PWM /* 4 channels */
+    static struct rt_device_pwm ad16c4t0_pwm_dev;
+    static timer_handle_t ad16c4t0_timer_initstruct;
 
-    timer_initstruct0.perh = AD16C4T0;
-    ald_timer_pwm_init(&timer_initstruct0);
+    ad16c4t0_timer_initstruct.perh = AD16C4T0;
+    ald_timer_pwm_init(&ad16c4t0_timer_initstruct);
 
     /* gpio initialization */
-    gpio_initstructure.func = GPIO_FUNC_2;
-    ald_gpio_init(GPIOA, GPIO_PIN_8, &gpio_initstructure);
-    ald_gpio_init(GPIOA, GPIO_PIN_9, &gpio_initstructure);
-    ald_gpio_init(GPIOA, GPIO_PIN_10, &gpio_initstructure);
-    ald_gpio_init(GPIOA, GPIO_PIN_11, &gpio_initstructure);
-
-    ret = rt_device_pwm_register(&pwm_dev0, "pwm0", &es32f0_pwm_ops,
-                                 &timer_initstruct0);
+
+#if  defined(ES_AD16C4T0_CH1_GPIO_FUNC)&&defined(ES_AD16C4T0_CH1_GPIO_PORT)&&defined(ES_AD16C4T0_CH1_GPIO_PIN)   
+    gpio_initstructure.func = ES_AD16C4T0_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH1_GPIO_PORT, ES_AD16C4T0_CH1_GPIO_PIN, &gpio_initstructure);
+#endif                 
+                                                           
+#if  defined(ES_AD16C4T0_CH2_GPIO_FUNC)&&defined(ES_AD16C4T0_CH2_GPIO_PORT)&&defined(ES_AD16C4T0_CH2_GPIO_PIN)    
+    gpio_initstructure.func = ES_AD16C4T0_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH2_GPIO_PORT, ES_AD16C4T0_CH2_GPIO_PIN, &gpio_initstructure);
+#endif                 
+
+#if  defined(ES_AD16C4T0_CH3_GPIO_FUNC)&&defined(ES_AD16C4T0_CH3_GPIO_PORT)&&defined(ES_AD16C4T0_CH3_GPIO_FUNC)   
+    gpio_initstructure.func = ES_AD16C4T0_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH3_GPIO_PORT, ES_AD16C4T0_CH3_GPIO_PIN, &gpio_initstructure);
+#endif                 
+
+#if  defined(ES_AD16C4T0_CH4_GPIO_FUNC)&&defined(ES_AD16C4T0_CH4_GPIO_PORT)&&defined(ES_AD16C4T0_CH4_GPIO_PIN)  
+    gpio_initstructure.func = ES_AD16C4T0_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_AD16C4T0_CH4_GPIO_PORT, ES_AD16C4T0_CH4_GPIO_PIN, &gpio_initstructure); 
+#endif                 
+
+    ret = rt_device_pwm_register(&ad16c4t0_pwm_dev, ES_DEVICE_NAME_AD16C4T0_PWM,  &es32f0_pwm_ops,
+                                 &ad16c4t0_timer_initstruct);
 #endif
 
-#ifdef BSP_USING_PWM1 /* 4 channels */
-    static struct rt_device_pwm pwm_dev1;
-    static timer_handle_t timer_initstruct1;
+#ifdef BSP_USING_GP16C4T0_PWM /* 4 channels */
+    static struct rt_device_pwm gp16c4t0_pwm_dev;
+    static timer_handle_t gp16c4t0_timer_initstruct;
 
-    timer_initstruct1.perh = GP16C4T0;
-    ald_timer_pwm_init(&timer_initstruct1);
+    gp16c4t0_timer_initstruct.perh = GP16C4T0;
+    ald_timer_pwm_init(&gp16c4t0_timer_initstruct);
 
     /* gpio initialization */
-    gpio_initstructure.func = GPIO_FUNC_2;
-    ald_gpio_init(GPIOB, GPIO_PIN_6, &gpio_initstructure);
-    ald_gpio_init(GPIOB, GPIO_PIN_7, &gpio_initstructure);
-    ald_gpio_init(GPIOB, GPIO_PIN_8, &gpio_initstructure);
-    ald_gpio_init(GPIOB, GPIO_PIN_9, &gpio_initstructure);
-
-    ret = rt_device_pwm_register(&pwm_dev1, "pwm1", &es32f0_pwm_ops,
-                                 &timer_initstruct1);
+   
+#if  defined(ES_GP16C4T0_CH1_GPIO_FUNC)&&defined(ES_GP16C4T0_CH1_GPIO_PORT)&&defined(ES_GP16C4T0_CH1_GPIO_PIN) 
+    gpio_initstructure.func = ES_GP16C4T0_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH1_GPIO_PORT, ES_GP16C4T0_CH1_GPIO_PIN, &gpio_initstructure);  
+#endif                 
+                                                           
+#if  defined(ES_GP16C4T0_CH2_GPIO_FUNC)&&defined(ES_GP16C4T0_CH2_GPIO_PORT)&&defined(ES_GP16C4T0_CH2_GPIO_PIN) 
+    gpio_initstructure.func = ES_GP16C4T0_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH2_GPIO_PORT, ES_GP16C4T0_CH2_GPIO_PIN, &gpio_initstructure);  
+#endif                 
+
+#if  defined(ES_GP16C4T0_CH3_GPIO_FUNC)&&defined(ES_GP16C4T0_CH3_GPIO_PORT)&&defined(ES_GP16C4T0_CH3_GPIO_PIN)     
+    gpio_initstructure.func = ES_GP16C4T0_CH3_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH3_GPIO_PORT, ES_GP16C4T0_CH3_GPIO_PIN, &gpio_initstructure);
+#endif                 
+
+#if  defined(ES_GP16C4T0_CH4_GPIO_FUNC)&&defined(ES_GP16C4T0_CH4_GPIO_PORT)&&defined(ES_GP16C4T0_CH4_GPIO_PIN)
+    gpio_initstructure.func = ES_GP16C4T0_CH4_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C4T0_CH4_GPIO_PORT, ES_GP16C4T0_CH4_GPIO_PIN, &gpio_initstructure);  
+#endif                
+
+    ret = rt_device_pwm_register(&gp16c4t0_pwm_dev, ES_DEVICE_NAME_GP16C4T0_PWM, &es32f0_pwm_ops,
+                                 &gp16c4t0_timer_initstruct);
 #endif
 
-#ifdef BSP_USING_PWM2 /* 2 channels */
-    static struct rt_device_pwm pwm_dev2;
-    static timer_handle_t timer_initstruct2;
 
-    timer_initstruct2.perh = GP16C2T0;
-    ald_timer_pwm_init(&timer_initstruct2);
+#ifdef BSP_USING_GP16C2T0_PWM /* 2 channels */
+    static struct rt_device_pwm gp16c2t0_pwm_dev;
+    static timer_handle_t gp16c2t0_timer_initstruct;
 
-    /* gpio initialization */
-    gpio_initstructure.func = GPIO_FUNC_2;
-    ald_gpio_init(GPIOA, GPIO_PIN_0, &gpio_initstructure);
-    ald_gpio_init(GPIOA, GPIO_PIN_1, &gpio_initstructure);
+    gp16c2t0_timer_initstruct.perh = GP16C2T0;
+    ald_timer_pwm_init(&gp16c2t0_timer_initstruct);
 
-    ret = rt_device_pwm_register(&pwm_dev2, "pwm2", &es32f0_pwm_ops,
-                                 &timer_initstruct2);
+    /* gpio initialization */
+   
+#if  defined(ES_GP16C2T0_CH1_GPIO_FUNC)&&defined(ES_GP16C2T0_CH1_GPIO_PORT)&&defined(ES_GP16C2T0_CH1_GPIO_PIN) 
+    gpio_initstructure.func = ES_GP16C2T0_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C2T0_CH1_GPIO_PORT, ES_GP16C2T0_CH1_GPIO_PIN, &gpio_initstructure);  
+#endif                 
+                                                           
+#if  defined(ES_GP16C2T0_CH2_GPIO_FUNC)&&defined(ES_GP16C2T0_CH2_GPIO_PORT)&&defined(ES_GP16C2T0_CH2_GPIO_PIN) 
+    gpio_initstructure.func = ES_GP16C2T0_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C2T0_CH2_GPIO_PORT, ES_GP16C2T0_CH2_GPIO_PIN, &gpio_initstructure);  
+#endif                 
+
+    ret = rt_device_pwm_register(&gp16c2t0_pwm_dev, ES_DEVICE_NAME_GP16C2T0_PWM, &es32f0_pwm_ops,
+                                 &gp16c2t0_timer_initstruct);
 #endif
 
-#ifdef BSP_USING_PWM3 /* 2 channels */
-    static struct rt_device_pwm pwm_dev3;
-    static timer_handle_t timer_initstruct3;
 
-    timer_initstruct3.perh = GP16C2T1;
-    ald_timer_pwm_init(&timer_initstruct3);
+#ifdef BSP_USING_GP16C2T1_PWM /* 2 channels */
+    static struct rt_device_pwm gp16c2t1_pwm_dev;
+    static timer_handle_t gp16c2t1_timer_initstruct;
 
-    /* gpio initialization */
-    gpio_initstructure.func = GPIO_FUNC_3;
-    ald_gpio_init(GPIOC, GPIO_PIN_6, &gpio_initstructure);
-    ald_gpio_init(GPIOC, GPIO_PIN_7, &gpio_initstructure);
+    gp16c2t1_timer_initstruct.perh = GP16C2T1;
+    ald_timer_pwm_init(&gp16c2t1_timer_initstruct);
 
-    ret = rt_device_pwm_register(&pwm_dev3, "pwm3", &es32f0_pwm_ops,
-                                 &timer_initstruct3);
+    /* gpio initialization */
+   
+#if  defined(ES_GP16C2T1_CH1_GPIO_FUNC)&&defined(ES_GP16C2T1_CH1_GPIO_PORT)&&defined(ES_GP16C2T1_CH1_GPIO_PIN) 
+    gpio_initstructure.func = ES_GP16C2T1_CH1_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C2T1_CH1_GPIO_PORT, ES_GP16C2T1_CH1_GPIO_PIN, &gpio_initstructure);  
+#endif                 
+                                                           
+#if  defined(ES_GP16C2T1_CH2_GPIO_FUNC)&&defined(ES_GP16C2T1_CH2_GPIO_PORT)&&defined(ES_GP16C2T1_CH2_GPIO_PIN) 
+    gpio_initstructure.func = ES_GP16C2T1_CH2_GPIO_FUNC;
+    ald_gpio_init(ES_GP16C2T1_CH2_GPIO_PORT, ES_GP16C2T1_CH2_GPIO_PIN, &gpio_initstructure);  
+#endif                 
+
+    ret = rt_device_pwm_register(&gp16c2t1_pwm_dev, ES_DEVICE_NAME_GP16C2T1_PWM, &es32f0_pwm_ops,
+                                 &gp16c2t1_timer_initstruct);
 #endif
 
+
+
     return ret;
 }
 INIT_DEVICE_EXPORT(rt_hw_pwm_init);
+
+#endif

bsp/essemi/es32f0654/drivers/drv_pwm.h

@@ -3,6 +3,18 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2019-03-11     wangyq       the first version

bsp/essemi/es32f0654/drivers/drv_rtc.c

@@ -3,26 +3,38 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2019-03-22     wangyq       the first version
  * 2019-11-01     wangyq        update libraries
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rthw.h>
 #include <rtthread.h>
-#include <rtdevice.h>
+#include <rtdevice.h>  
 #include <sys/time.h>
 #include <string.h>
 #include "board.h"
-#include "drv_rtc.h"
-#include <ald_cmu.h>
-#include <ald_rtc.h>
+#include "drv_rtc.h" 
 
 #ifdef RT_USING_RTC
 
 static void __rtc_init(rtc_init_t *init)
 {
+
     assert_param(IS_RTC_HOUR_FORMAT(init->hour_format));
     assert_param(IS_RTC_OUTPUT_SEL(init->output));
     assert_param(IS_RTC_OUTPUT_POLARITY(init->output_polarity));
@@ -117,10 +129,16 @@ int rt_hw_rtc_init(void)
     rt_err_t ret = RT_EOK;
     static struct rt_device rtc_dev;
     rtc_init_t rtc_initstruct;
+    
+    /* enable clk */
+    ald_rtc_source_select(ES_RTC_CLK_SOURCE);
 
-    /* enable external 32.768kHz */
-    CMU_LOSC_ENABLE();
-    ald_cmu_losc_safe_config(ENABLE);
+    if(ES_RTC_CLK_SOURCE == ES_C_RTC_SOURCE_LOSC)
+    {
+        CMU_LOSC_ENABLE();
+        ald_cmu_losc_safe_config(ENABLE);
+    }
+    
     /* set default time */
     RTC_UNLOCK();
     WRITE_REG(RTC->TIME, 0x134251);
@@ -131,6 +149,8 @@ int rt_hw_rtc_init(void)
     rtc_initstruct.asynch_pre_div = 0;
     rtc_initstruct.synch_pre_div = 32767;
     rtc_initstruct.output = RTC_OUTPUT_DISABLE;
+    rtc_initstruct.output_polarity = RTC_OUTPUT_POLARITY_HIGH;
+	
     __rtc_init(&rtc_initstruct);
 
     rtc_dev.type = RT_Device_Class_RTC;
@@ -150,7 +170,7 @@ int rt_hw_rtc_init(void)
 
     rtc_dev.user_data = RTC;
 
-    ret = rt_device_register(&rtc_dev, "rtc", RT_DEVICE_FLAG_RDWR);
+    ret = rt_device_register(&rtc_dev, ES_DEVICE_NAME_RTC, RT_DEVICE_FLAG_RDWR);
 
     return ret;
 }

bsp/essemi/es32f0654/drivers/drv_rtc.h

@@ -3,14 +3,28 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author       Notes
- * 2019-03-22     wangyq       the first version
+ * 2019-03-22     wangyq       the first version   
+ * 2021-04-20     liuhy         the second version
  */
 
 #ifndef DRV_RTC_H__
 #define DRV_RTC_H__
 
+#include "es_conf_info_rtc.h"
 int rt_hw_rtc_init(void);
 
 #endif

bsp/essemi/es32f0654/drivers/drv_spi.c

@@ -3,11 +3,23 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-24     wangyq        the first version
  * 2019-11-01     wangyq        update libraries
- * 2020-12-15     liuhy         update libraries
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rtthread.h>
@@ -16,9 +28,7 @@
 #include <rthw.h>
 #include "board.h"
 #include "drv_spi.h"
-#include <ald_spi.h>
-#include <ald_gpio.h>
-#include <ald_cmu.h>
+
 
 #ifdef RT_USING_SPI
 
@@ -30,6 +40,9 @@ rt_err_t spi_configure(struct rt_spi_device *device,
     spi_handle_t *hspi;
     hspi = (spi_handle_t *)device->bus->parent.user_data;
 
+    hspi->init.ss_en    = DISABLE;
+    hspi->init.crc_calc = DISABLE;
+
     /* config spi mode */
     if (cfg->mode & RT_SPI_SLAVE)
     {
@@ -64,6 +77,16 @@ rt_err_t spi_configure(struct rt_spi_device *device,
     {
         hspi->init.phase = SPI_CPHA_FIRST;
     }
+    
+    if (cfg->mode & RT_SPI_MSB)
+    {
+        hspi->init.first_bit = SPI_FIRSTBIT_MSB;
+    }
+    else
+    {
+        hspi->init.first_bit = SPI_FIRSTBIT_LSB;
+    }
+    
     if (cfg->mode & RT_SPI_CPOL)
     {
         hspi->init.polarity = SPI_CPOL_HIGH;
@@ -72,6 +95,7 @@ rt_err_t spi_configure(struct rt_spi_device *device,
     {
         hspi->init.polarity = SPI_CPOL_LOW;
     }
+    
     if (cfg->mode & RT_SPI_NO_CS)
     {
         hspi->init.ss_en = DISABLE;
@@ -150,74 +174,54 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
 
     hspi = (spi_handle_t *)device->bus->parent.user_data;
     cs = device->parent.user_data;
+
+    if (message->cs_take)
+        {
+            rt_pin_write(cs->pin, ES_SPI_CS_LEVEL);
+        }
     
     if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL)
     {
     /* send & receive */
     if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
     {
-        if (message->cs_take)
-        {
-            rt_pin_write(cs->pin, 0);
-        }
         res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
                                 (rt_int32_t)message->length, SPITIMEOUT);
-        if (message->cs_release)
-        {
-            rt_pin_write(cs->pin, 1);
-        }
-        if (res != RT_EOK)
-            return RT_ERROR;
     }
     else
     {
         /* only send data */
         if (message->recv_buf == RT_NULL)
         {
-            if (message->cs_take)
-            {
-                rt_pin_write(cs->pin, 0);
-            }
             res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
-            if (message->cs_release)
-            {
-                rt_pin_write(cs->pin, 1);
-            }
-            if (res != RT_EOK)
-                return RT_ERROR;
         }
         /* only receive data */
         if (message->send_buf == RT_NULL)
         {
-            if (message->cs_take)
-            {
-                rt_pin_write(cs->pin, 0);
-            }
             res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
-            if (message->cs_release)
-            {
-                rt_pin_write(cs->pin, 1);
-            }
-            if (res != RT_EOK)
-                return RT_ERROR;
         }
     }
-
+    
+     if (message->cs_release)
+     {
+        rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL);
+     }
+     
+     if (res != RT_EOK) 
+         return RT_ERROR;
+     else               
+         return message->length;
+     
     }
     else
     {
-         if (message->cs_take)
-        {
-            rt_pin_write(cs->pin, 0);
-        }
-        
+       
         if (message->cs_release)
         {
-            rt_pin_write(cs->pin, 1);
+            rt_pin_write(cs->pin, !ES_SPI_CS_LEVEL);
         }
             return RT_EOK;
     }
-    return message->length;
     
 }
 
@@ -230,6 +234,7 @@ const struct rt_spi_ops es32f0_spi_ops =
 
 rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
 {
+    int result;
     /* define spi Instance */
     struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
     RT_ASSERT(spi_device != RT_NULL);
@@ -238,7 +243,17 @@ rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const c
     cs_pin->pin = pin;
     rt_pin_mode(pin, PIN_MODE_OUTPUT);
     rt_pin_write(pin, 1);
-    return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+    
+    result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+    
+#ifdef BSP_USING_SPI0                  
+    if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI0_BUS)))SPI_BUS_CONFIG(spi_device->config,0);   
+#endif  
+#ifdef BSP_USING_SPI1 
+    if(!(strcmp(bus_name,ES_DEVICE_NAME_SPI1_BUS)))SPI_BUS_CONFIG(spi_device->config,1); 
+#endif   
+    
+    return result;
 }
 
 #ifdef BSP_USING_SPI0
@@ -259,77 +274,84 @@ int rt_hw_spi_init(void)
     spi_handle_t *spi;
     gpio_init_t gpio_instruct;
 
+        gpio_instruct.odos = GPIO_PUSH_PULL;       
+	    gpio_instruct.type = GPIO_TYPE_CMOS;
+        gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+        gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL;
 #ifdef BSP_USING_SPI0
     _spi0.perh = SPI0;
     spi_bus = &_spi_bus0;
     spi = &_spi0;
-    rt_device_t spi_bus_dev0;
 
     /* SPI0 gpio init */
-        gpio_instruct.mode = GPIO_MODE_OUTPUT;
-        gpio_instruct.odos = GPIO_PUSH_PULL;
-        gpio_instruct.func = GPIO_FUNC_4;
-        gpio_instruct.type = GPIO_TYPE_CMOS;
-        gpio_instruct.flt  = GPIO_FILTER_DISABLE;
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
 
-        /* PB3->SPI0_SCK, PB5->SPI0_MOSI */
-        ald_gpio_init(GPIOB, GPIO_PIN_3 | GPIO_PIN_5, &gpio_instruct);
+#if  defined(ES_SPI0_SCK_GPIO_FUNC)&&defined(ES_SPI0_SCK_GPIO_PORT)&&defined(ES_SPI0_SCK_GPIO_PIN)
+    gpio_instruct.func = ES_SPI0_SCK_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_SCK_GPIO_PORT, ES_SPI0_SCK_GPIO_PIN, &gpio_instruct);
+#endif                                
 
-        /* PB4->SPI0_MISO */
-        gpio_instruct.mode = GPIO_MODE_INPUT;
-        ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
+#if  defined(ES_SPI0_MOSI_GPIO_FUNC)&&defined(ES_SPI0_MOSI_GPIO_PORT)&&defined(ES_SPI0_MOSI_GPIO_PIN)   
+    gpio_instruct.func = ES_SPI0_MOSI_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_MOSI_GPIO_PORT, ES_SPI0_MOSI_GPIO_PIN, &gpio_instruct);
+#endif                                    
+    
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+
+#if  defined(ES_SPI0_MISO_GPIO_FUNC)&&defined(ES_SPI0_MISO_GPIO_PORT)&&defined(ES_SPI0_MISO_GPIO_PIN)        
+    gpio_instruct.func = ES_SPI0_MISO_GPIO_FUNC;
+    ald_gpio_init(ES_SPI0_MISO_GPIO_PORT, ES_SPI0_MISO_GPIO_PIN, &gpio_instruct);
+#endif                            
 
     spi_bus->parent.user_data = spi;
-    result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops);
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI0_BUS, &es32f0_spi_ops);
     if (result != RT_EOK)
     {
         return result;
     }
     
-    rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR);
-    
-    /* SPI0_NSS = PA15 = PIN 50 */
-    result = es32f0_spi_device_attach(50, "spi0", "spi00");
+    result = es32f0_spi_device_attach(ES_SPI0_NSS_PIN, ES_DEVICE_NAME_SPI0_BUS, ES_DEVICE_NAME_SPI0_DEV0);
     
     if (result != RT_EOK)
     {
         return result;
     }
-    
+
 #endif
 
 #ifdef BSP_USING_SPI1
     _spi1.perh = SPI1;
     spi_bus = &_spi_bus1;
     spi = &_spi1;
-    rt_device_t spi_bus_dev0;
 
     /* SPI1 gpio init */
-        gpio_instruct.mode = GPIO_MODE_OUTPUT;
-        gpio_instruct.odos = GPIO_PUSH_PULL;
-        gpio_instruct.func = GPIO_FUNC_4;
-        gpio_instruct.type = GPIO_TYPE_CMOS;
-        gpio_instruct.flt  = GPIO_FILTER_DISABLE;
-
-        /* PB13->SPI1_SCK, PB15->SPI1_MOSI */
-        ald_gpio_init(GPIOB, GPIO_PIN_13 | GPIO_PIN_15, &gpio_instruct);
-
-        /* PB14->SPI1_MISO */
-        gpio_instruct.mode = GPIO_MODE_INPUT;
-        ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
+    gpio_instruct.mode = GPIO_MODE_OUTPUT;
+                
+#if  defined(ES_SPI1_SCK_GPIO_FUNC)&&defined(ES_SPI1_SCK_GPIO_PORT)&&defined(ES_SPI1_SCK_GPIO_PIN)
+    gpio_instruct.func = ES_SPI1_SCK_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_SCK_GPIO_PORT, ES_SPI1_SCK_GPIO_PIN, &gpio_instruct);  
+#endif                            
+                                             
+#if  defined(ES_SPI1_MOSI_GPIO_FUNC)&&defined(ES_SPI1_MOSI_GPIO_PORT)&&defined(ES_SPI1_MOSI_GPIO_PIN) 
+    gpio_instruct.func = ES_SPI1_MOSI_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_MOSI_GPIO_PORT, ES_SPI1_MOSI_GPIO_PIN, &gpio_instruct); 
+#endif                            
+    
+    gpio_instruct.mode = GPIO_MODE_INPUT;
+                                          
+#if  defined(ES_SPI1_MISO_GPIO_FUNC)&&defined(ES_SPI1_MISO_GPIO_PORT)&&defined(ES_SPI1_MISO_GPIO_PIN) 
+    gpio_instruct.func = ES_SPI1_MISO_GPIO_FUNC;
+    ald_gpio_init(ES_SPI1_MISO_GPIO_PORT, ES_SPI1_MISO_GPIO_PIN, &gpio_instruct); 
+#endif                            
 
     spi_bus->parent.user_data = spi;
-    result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops);
+    result = rt_spi_bus_register(spi_bus, ES_DEVICE_NAME_SPI1_BUS, &es32f0_spi_ops);
     if (result != RT_EOK)
     {
         return result;
     }
     
-    rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR);
-    
-    /* SPI1_NSS = PC00 = PIN 8 */
-    result = es32f0_spi_device_attach(8, "spi1", "spi10");
-    
+    result = es32f0_spi_device_attach((ES_SPI1_NSS_PIN, ES_DEVICE_NAME_SPI1_BUS, ES_DEVICE_NAME_SPI1_DEV0);
     if (result != RT_EOK)
     {
         return result;

bsp/essemi/es32f0654/drivers/drv_spi.h

@@ -3,9 +3,22 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
- * 2019-01-24     wangyq        the first version
+ * 2019-01-24     wangyq        the first version  
+ * 2021-04-20     liuhy         the second version
  */
 
 #ifndef DRV_SPI_H__
@@ -14,6 +27,8 @@
 #include <rtthread.h>
 #include <rthw.h>
 #include <rtdevice.h>
+                      
+#include "es_conf_info_spi.h"
 
 struct es32f0_hw_spi_cs
 {

bsp/essemi/es32f0654/drivers/drv_spiflash.c

@@ -9,18 +9,20 @@
  * 2019-11-01     wangyq        update libraries
  */
 
+#include "board.h"
 #include <rtthread.h>
+
+#if defined(BSP_USING_SPI_FLASH)
+
 #include "spi_flash.h"
 #include "drv_spiflash.h"
 #include "spi_flash_sfud.h"
 #include "drv_spi.h"
 
-#if defined(BSP_USING_SPI_FLASH)
 int rt_hw_spi_flash_init(void)
 {
-    es32f0_spi_device_attach(50, "spi0", "spi00");
-
-    if (RT_NULL == rt_sfud_flash_probe("W25Q64", "spi00"))
+  
+    if (RT_NULL == rt_sfud_flash_probe(ES_DEVICE_NAME_SPI_FALSH_DEV, ES_DEVICE_NAME_SPI_DEV))
     {
         return -RT_ERROR;
     };

bsp/essemi/es32f0654/drivers/drv_uart.c

@@ -3,19 +3,30 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-23     wangyq        the first version
- * 2019-11-01     wangyq        update libraries
+ * 2019-11-01     wangyq        update libraries 
+ * 2021-04-20     liuhy         the second version
  */
 
 #include <rthw.h>
 #include <rtthread.h>
 #include <rtdevice.h>
 #include "board.h"
-#include "drv_uart.h"
-#include <ald_gpio.h>
-#include <ald_uart.h>
+#include "es_conf_info_uart.h"
 
 #ifdef RT_USING_SERIAL
 
@@ -24,151 +35,13 @@ struct es32_uart
 {
     uart_handle_t huart;
     IRQn_Type irq;
-};
-
-static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
-{
-    gpio_init_t gpio_initstructure;
-    struct es32_uart *uart;
-    RT_ASSERT(serial != RT_NULL);
-    RT_ASSERT(cfg != RT_NULL);
-    uart = (struct es32_uart *)serial->parent.user_data;
-
-    /* Initialize tx pin */
-    gpio_initstructure.mode = GPIO_MODE_OUTPUT;
-    gpio_initstructure.odos = GPIO_PUSH_PULL;
-    gpio_initstructure.pupd = GPIO_PUSH_UP;
-    gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL;
-    gpio_initstructure.flt  = GPIO_FILTER_DISABLE;
-    gpio_initstructure.type = GPIO_TYPE_TTL;
-
-#ifdef BSP_USING_UART0
-    gpio_initstructure.func = GPIO_FUNC_3;
-    ald_gpio_init(GPIOB, GPIO_PIN_10, &gpio_initstructure);
-
-    /* Initialize rx pin ,the same as txpin except mode */
-    gpio_initstructure.mode = GPIO_MODE_INPUT;
-    ald_gpio_init(GPIOB, GPIO_PIN_11, &gpio_initstructure);
-#endif /* uart0 gpio init */
-
-#ifdef BSP_USING_UART1
-    gpio_initstructure.func = GPIO_FUNC_3;
-    ald_gpio_init(GPIOC, GPIO_PIN_10, &gpio_initstructure);
-
-    /* Initialize rx pin ,the same as txpin except mode */
-    gpio_initstructure.mode = GPIO_MODE_INPUT;
-    ald_gpio_init(GPIOC, GPIO_PIN_11, &gpio_initstructure);
-#endif /* uart1 gpio init */
-
-#ifdef BSP_USING_UART2
-    gpio_initstructure.func = GPIO_FUNC_5;
-    ald_gpio_init(GPIOC, GPIO_PIN_12, &gpio_initstructure);
-
-    /* Initialize rx pin ,the same as txpin except mode */
-    gpio_initstructure.mode = GPIO_MODE_INPUT;
-    ald_gpio_init(GPIOD, GPIO_PIN_2, &gpio_initstructure);
-#endif /* uart2 gpio init */
-
-#ifdef BSP_USING_UART3
-    gpio_initstructure.func = GPIO_FUNC_4;
-    ald_gpio_init(GPIOC, GPIO_PIN_4, &gpio_initstructure);
-
-    /* Initialize rx pin ,the same as txpin except mode */
-    gpio_initstructure.mode = GPIO_MODE_INPUT;
-    ald_gpio_init(GPIOC, GPIO_PIN_5, &gpio_initstructure);
-#endif /* uart3 gpio init */
-
-    uart->huart.init.mode        = UART_MODE_UART;
-    uart->huart.init.baud        = cfg->baud_rate;
-    uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5);
-    uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
-    uart->huart.init.fctl        = UART_HW_FLOW_CTL_DISABLE;
-    ald_uart_init(&uart->huart);
-
-    if (cfg->bit_order == BIT_ORDER_MSB)
-    {
-        UART_MSB_FIRST_ENABLE(&uart->huart);
-    }
-    else
-    {
-        UART_MSB_FIRST_DISABLE(&uart->huart);
-    }
-
-    if (cfg->invert == NRZ_INVERTED)
-    {
-        UART_DATA_INV_ENABLE(&uart->huart);
-    }
-    else
-    {
-        UART_DATA_INV_DISABLE(&uart->huart);
-    }
-
-    /* enable rx int */
-    ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
-
-    return RT_EOK;
-}
-
-static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg)
-{
-    struct es32_uart *uart;
-    RT_ASSERT(serial != RT_NULL);
-
-    uart = (struct es32_uart *)serial->parent.user_data;
-    switch (cmd)
-    {
-    case RT_DEVICE_CTRL_CLR_INT:
-        /* disable rx irq */
-        NVIC_DisableIRQ(uart->irq);
-        /* disable interrupt */
-        ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
-        break;
-
-    case RT_DEVICE_CTRL_SET_INT:
-        /* enable rx irq */
-        NVIC_EnableIRQ(uart->irq);
-        /* enable interrupt */
-        ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
-        break;
-    }
+};                
 
-    return RT_EOK;
-}
-
-static int es32f0x_putc(struct rt_serial_device *serial, char c)
+/* es32 usart driver */
+struct es32_usart
 {
-    struct es32_uart *uart;
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct es32_uart *)serial->parent.user_data;
-
-    while (!(uart->huart.perh->SR & 0x40)) ;
-    WRITE_REG(uart->huart.perh->TBR, c);
-
-    return 1;
-}
-
-static int es32f0x_getc(struct rt_serial_device *serial)
-{
-    int ch = -1;
-    struct es32_uart *uart;
-
-    RT_ASSERT(serial != RT_NULL);
-    uart = (struct es32_uart *)serial->parent.user_data;
-
-    if (uart->huart.perh->SR & 0x01)
-    {
-        ch = (uint8_t)(uart->huart.perh->RBR & 0xFF);
-    }
-
-    return ch;
-}
-
-static const struct rt_uart_ops es32f0x_uart_ops =
-{
-    es32f0x_configure,
-    es32f0x_control,
-    es32f0x_putc,
-    es32f0x_getc,
+    usart_handle_t huart;
+    IRQn_Type irq;
 };
 
 #ifdef BSP_USING_UART0
@@ -266,19 +139,380 @@ void BS16T2_UART3_Handler(void)
     rt_interrupt_leave();
 }
 #endif /* BSP_USING_UART3 */
+        
+#ifdef BSP_USING_USART0
+/* USART0 device driver structure */
+struct es32_usart usart0 =
+{
+    {USART0},
+    USART0_IRQn
+};
+
+struct rt_serial_device serial4;
+
+void USART0_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (USART0->STAT & USART_FLAG_RXNE)
+    {
+        rt_hw_serial_isr(&serial4, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_USART0 */
+
+#ifdef BSP_USING_USART1
+/* USART1 device driver structure */
+struct es32_usart usart1 =
+{
+    {USART1},
+    USART1_IRQn
+};
+
+struct rt_serial_device serial5;
+
+void USART1_Handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    if (USART1->STAT & USART_FLAG_RXNE)
+    {
+        rt_hw_serial_isr(&serial5, RT_SERIAL_EVENT_RX_IND);
+    }
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_USART1 */
+
+static rt_err_t es32f0x_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
+{
+    gpio_init_t gpio_initstructure;
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(cfg != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+
+    /* Initialize tx pin */
+    gpio_initstructure.mode = GPIO_MODE_OUTPUT;
+    gpio_initstructure.odos = GPIO_PUSH_PULL;
+    gpio_initstructure.pupd = GPIO_PUSH_UP;
+    gpio_initstructure.odrv = GPIO_OUT_DRIVE_NORMAL;
+    gpio_initstructure.flt  = GPIO_FILTER_DISABLE;
+    gpio_initstructure.type = GPIO_TYPE_TTL;
+
+    if((uint32_t)(uart->huart.perh) > (uint32_t)UART3)  /*根据外设物理地址区分UART和USART*/
+    {
+       /*USART*/
+        struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data;
+    
+#ifdef BSP_USING_USART0
+        if(usart == (&usart0))
+        {
+#if  defined(ES_USART0_TX_GPIO_FUNC)&&defined(ES_USART0_TX_GPIO_PORT)&&defined(ES_USART0_TX_GPIO_PIN)
+            gpio_initstructure.func = ES_USART0_TX_GPIO_FUNC;
+            ald_gpio_init(ES_USART0_TX_GPIO_PORT, ES_USART0_TX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_USART0_RX_GPIO_FUNC)&&defined(ES_USART0_RX_GPIO_PORT)&&defined(ES_USART0_RX_GPIO_PIN)        
+            /* Initialize rx pin ,the same as txpin except mode */
+            gpio_initstructure.mode = GPIO_MODE_INPUT;
+            gpio_initstructure.func = ES_USART0_RX_GPIO_FUNC;
+            ald_gpio_init(ES_USART0_RX_GPIO_PORT, ES_USART0_RX_GPIO_PIN, &gpio_initstructure);
+#endif
+            ald_cmu_perh_clock_config(CMU_PERH_USART0, ENABLE);
+        }
+    
+#endif /* usart0 gpio init */
+                                 
+#ifdef BSP_USING_USART1
+        if(usart == (&usart1))
+        {
+#if  defined(ES_USART1_TX_GPIO_FUNC)&&defined(ES_USART1_TX_GPIO_PORT)&&defined(ES_USART1_TX_GPIO_PIN)  
+            gpio_initstructure.func = ES_USART1_TX_GPIO_FUNC;
+            ald_gpio_init(ES_USART1_TX_GPIO_PORT, ES_USART1_TX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_USART1_RX_GPIO_FUNC)&&defined(ES_USART1_RX_GPIO_PORT)&&defined(ES_USART1_RX_GPIO_PIN) 
+            /* Initialize rx pin ,the same as txpin except mode */
+            gpio_initstructure.mode = GPIO_MODE_INPUT;
+            gpio_initstructure.func = ES_USART1_RX_GPIO_FUNC;
+            ald_gpio_init(ES_USART1_RX_GPIO_PORT, ES_USART1_RX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+            ald_cmu_perh_clock_config(CMU_PERH_USART1, ENABLE);
+        }
+#endif /* usart1 gpio init */
+        
+        usart->huart.init.mode        = USART_MODE_TX_RX;
+        usart->huart.init.baud        = cfg->baud_rate;  
+        usart->huart.init.word_length = (usart_word_length_t)(cfg->data_bits - 8);   
+        usart->huart.init.stop_bits   = ((cfg->stop_bits == STOP_BITS_1) ?  USART_STOP_BITS_1 : USART_STOP_BITS_2);
+        usart->huart.init.parity = (usart_parity_t)(cfg->parity == PARITY_NONE ?  cfg->parity : (4 - cfg->parity) );
+        usart->huart.init.fctl        = USART_HW_FLOW_CTL_NONE; 
+
+        ald_usart_init(&usart->huart);
+        
+       /*        
+        BIT_ORDER_LSB  BIT_ORDER_MSB   
+        NRZ_NORMAL   NRZ_INVERTED 
+        无相关寄存器*/                 
+
+        /* enable rx int */
+        ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, ENABLE);                         
+        
+    }
+    else
+    {
+       /*UART*/
+       
+#ifdef BSP_USING_UART0
+        if(uart == (&uart0))
+        {
+#if  defined(ES_UART0_TX_GPIO_FUNC)&&defined(ES_UART0_TX_GPIO_PORT)&&defined(ES_UART0_TX_GPIO_PIN)
+            gpio_initstructure.func = ES_UART0_TX_GPIO_FUNC;
+            ald_gpio_init(ES_UART0_TX_GPIO_PORT, ES_UART0_TX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_UART0_RX_GPIO_FUNC)&&defined(ES_UART0_RX_GPIO_PORT)&&defined(ES_UART0_RX_GPIO_PIN)        
+            /* Initialize rx pin ,the same as txpin except mode */
+            gpio_initstructure.mode = GPIO_MODE_INPUT;
+            gpio_initstructure.func = ES_UART0_RX_GPIO_FUNC;
+            ald_gpio_init(ES_UART0_RX_GPIO_PORT, ES_UART0_RX_GPIO_PIN, &gpio_initstructure);
+#endif
+            ald_cmu_perh_clock_config(CMU_PERH_UART0, ENABLE);
+        }
+    
+#endif /* uart0 gpio init */
+                                 
+#ifdef BSP_USING_UART1
+        if(uart == (&uart1))
+        {
+#if  defined(ES_UART1_TX_GPIO_FUNC)&&defined(ES_UART1_TX_GPIO_PORT)&&defined(ES_UART1_TX_GPIO_PIN)  
+            gpio_initstructure.func = ES_UART1_TX_GPIO_FUNC;
+            ald_gpio_init(ES_UART1_TX_GPIO_PORT, ES_UART1_TX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_UART1_RX_GPIO_FUNC)&&defined(ES_UART1_RX_GPIO_PORT)&&defined(ES_UART1_RX_GPIO_PIN) 
+            /* Initialize rx pin ,the same as txpin except mode */
+            gpio_initstructure.mode = GPIO_MODE_INPUT;
+            gpio_initstructure.func = ES_UART1_RX_GPIO_FUNC;
+            ald_gpio_init(ES_UART1_RX_GPIO_PORT, ES_UART1_RX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+            ald_cmu_perh_clock_config(CMU_PERH_UART1, ENABLE);
+        }
+#endif /* uart1 gpio init */
+                               
+#ifdef BSP_USING_UART2
+        if(uart == (&uart2))
+        {
+#if  defined(ES_UART2_TX_GPIO_FUNC)&&defined(ES_UART2_TX_GPIO_PORT)&&defined(ES_UART2_TX_GPIO_PIN)
+            gpio_initstructure.func = ES_UART2_TX_GPIO_FUNC;
+            ald_gpio_init(ES_UART2_TX_GPIO_PORT, ES_UART2_TX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_UART2_RX_GPIO_FUNC)&&defined(ES_UART2_RX_GPIO_PORT)&&defined(ES_UART2_RX_GPIO_PIN)
+            /* Initialize rx pin ,the same as txpin except mode */
+            gpio_initstructure.mode = GPIO_MODE_INPUT;
+            gpio_initstructure.func = ES_UART2_RX_GPIO_FUNC;
+            ald_gpio_init(ES_UART2_RX_GPIO_PORT, ES_UART2_RX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+            ald_cmu_perh_clock_config(CMU_PERH_UART2, ENABLE);
+        }
+#endif /* uart2 gpio init */
+                                 
+#ifdef BSP_USING_UART3
+        if(uart == (&uart3))
+        {
+#if  defined(ES_UART3_TX_GPIO_FUNC)&&defined(ES_UART3_TX_GPIO_PORT)&&defined(ES_UART3_TX_GPIO_PIN)   
+            gpio_initstructure.func = ES_UART3_TX_GPIO_FUNC;
+            ald_gpio_init(ES_UART3_TX_GPIO_PORT, ES_UART3_TX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+#if  defined(ES_UART3_RX_GPIO_FUNC)&&defined(ES_UART3_RX_GPIO_PORT)&&defined(ES_UART3_RX_GPIO_PIN)
+            /* Initialize rx pin ,the same as txpin except mode */
+            gpio_initstructure.mode = GPIO_MODE_INPUT;
+            gpio_initstructure.func = ES_UART3_RX_GPIO_FUNC;
+            ald_gpio_init(ES_UART3_RX_GPIO_PORT, ES_UART3_RX_GPIO_PIN, &gpio_initstructure);
+#endif
+
+            ald_cmu_perh_clock_config(CMU_PERH_UART3, ENABLE);   
+        }
+#endif /* uart3 gpio init */
+
+        uart->huart.init.mode        = UART_MODE_UART;
+        uart->huart.init.baud        = cfg->baud_rate;  
+        uart->huart.init.word_length = (uart_word_length_t)(cfg->data_bits - 5); 
+        uart->huart.init.stop_bits   = (uart_stop_bits_t)cfg->stop_bits;
+        uart->huart.init.parity = (uart_parity_t)(cfg->parity == PARITY_EVEN ? UART_PARITY_EVEN : cfg->parity);
+        uart->huart.init.fctl        = UART_HW_FLOW_CTL_DISABLE; 
+
+        ald_uart_init(&uart->huart);
+
+        if (cfg->bit_order == BIT_ORDER_MSB)
+        {
+            UART_MSB_FIRST_ENABLE(&uart->huart);
+        }
+        else
+        {
+            UART_MSB_FIRST_DISABLE(&uart->huart);
+        }
+
+        if (cfg->invert == NRZ_INVERTED)
+        {
+            UART_DATA_INV_ENABLE(&uart->huart);
+        }
+        else
+        {
+            UART_DATA_INV_DISABLE(&uart->huart);
+        }
+
+        /* enable rx int */
+        ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
+            
+    }
+    
+
+    return RT_EOK;
+}
+
+static rt_err_t es32f0x_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = (struct es32_uart *)serial->parent.user_data;
+    
+    if((uint32_t)(uart->huart.perh) > (uint32_t)UART3)  /*根据外设物理地址区分UART和USART*/
+    {  
+       /*USART*/
+        struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data; 
+        
+        switch (cmd)
+        {
+        case RT_DEVICE_CTRL_CLR_INT:
+            /* disable rx irq */
+            NVIC_DisableIRQ(usart->irq);
+            /* disable interrupt */
+            ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, DISABLE);
+            break;
+
+        case RT_DEVICE_CTRL_SET_INT:
+            /* enable rx irq */
+            NVIC_EnableIRQ(usart->irq);
+            /* enable interrupt */
+            ald_usart_interrupt_config(&usart->huart, USART_IT_RXNE, ENABLE);
+            break;
+        }
+    
+    }
+    else 
+    {    
+       /*UART*/
+       
+        switch (cmd)
+        {
+        case RT_DEVICE_CTRL_CLR_INT:
+            /* disable rx irq */
+            NVIC_DisableIRQ(uart->irq);
+            /* disable interrupt */
+            ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, DISABLE);
+            break;
+
+        case RT_DEVICE_CTRL_SET_INT:
+            /* enable rx irq */
+            NVIC_EnableIRQ(uart->irq);
+            /* enable interrupt */
+            ald_uart_interrupt_config(&uart->huart, UART_IT_RXRD, ENABLE);
+            break;
+        }
+    }
+    
+
+    return RT_EOK;
+}
+
+static int es32f0x_putc(struct rt_serial_device *serial, char c)
+{
+    struct es32_uart *uart;
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+    
+    if((uint32_t)(uart->huart.perh) > (uint32_t)UART3)  /*根据外设物理地址区分UART和USART*/
+    {  
+       /*USART*/
+        struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data;    
+        while (!(usart->huart.perh->STAT & USART_STAT_TXEMPIF_MSK)) ;
+        WRITE_REG(usart->huart.perh->DATA, c);
+    }
+    else 
+    {    
+       /*UART*/   
+        while (!(uart->huart.perh->SR & 0x40)) ;
+        WRITE_REG(uart->huart.perh->TBR, c);
+    }
+
+    return 1;
+}
+
+static int es32f0x_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct es32_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = (struct es32_uart *)serial->parent.user_data;
+                               
+    if((uint32_t)(uart->huart.perh) > (uint32_t)UART3)  /*根据外设物理地址区分UART和USART*/
+    {  
+       /*USART*/
+        struct es32_usart *usart= (struct es32_usart *)serial->parent.user_data;   
+        if (usart->huart.perh->STAT & USART_STAT_RXNEIF_MSK)
+        {
+            ch = (uint8_t)(usart->huart.perh->DATA & 0xFF);
+        }
+    }
+    else 
+    {    
+       /*UART*/   
+        if (uart->huart.perh->SR & 0x01)
+        {
+            ch = (uint8_t)(uart->huart.perh->RBR & 0xFF);
+        }
+    }
+
+    return ch;
+}
+
+static const struct rt_uart_ops es32f0x_uart_ops =
+{
+    es32f0x_configure,
+    es32f0x_control,
+    es32f0x_putc,
+    es32f0x_getc,
+};
 
 int rt_hw_uart_init(void)
 {
+#if (defined(BSP_USING_UART0)||defined(BSP_USING_UART1)||defined(BSP_USING_UART2)||defined(BSP_USING_UART3))
     struct es32_uart *uart;
-    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+#endif   
+#if (defined(BSP_USING_USART0)||defined(BSP_USING_USART1))
+    struct es32_usart *usart;
+#endif
 
 #ifdef BSP_USING_UART0
     uart = &uart0;
     serial0.ops = &es32f0x_uart_ops;
-    serial0.config = config;
+    serial0.config = (struct serial_configure)ES_UART0_CONFIG;
 
     /* register UART0 device */
-    rt_hw_serial_register(&serial0, "uart0",
+    rt_hw_serial_register(&serial0, ES_DEVICE_NAME_UART0,
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* BSP_USING_UART0 */
@@ -286,10 +520,10 @@ int rt_hw_uart_init(void)
 #ifdef BSP_USING_UART1
     uart = &uart1;
     serial1.ops = &es32f0x_uart_ops;
-    serial1.config = config;
+    serial1.config = (struct serial_configure)ES_UART1_CONFIG;
 
     /* register UART1 device */
-    rt_hw_serial_register(&serial1, "uart1",
+    rt_hw_serial_register(&serial1, ES_DEVICE_NAME_UART1,
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* BSP_USING_UART1 */
@@ -297,10 +531,10 @@ int rt_hw_uart_init(void)
 #ifdef BSP_USING_UART2
     uart = &uart2;
     serial2.ops = &es32f0x_uart_ops;
-    serial2.config = config;
+    serial2.config = (struct serial_configure)ES_UART2_CONFIG;
 
     /* register UART2 device */
-    rt_hw_serial_register(&serial2, "uart2",
+    rt_hw_serial_register(&serial2, ES_DEVICE_NAME_UART2,
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* BSP_USING_UART2 */
@@ -308,14 +542,35 @@ int rt_hw_uart_init(void)
 #ifdef BSP_USING_UART3
     uart = &uart3;
     serial3.ops = &es32f0x_uart_ops;
-    serial3.config = config;
+    serial3.config = (struct serial_configure)ES_UART3_CONFIG;
 
     /* register UART3 device */
-    rt_hw_serial_register(&serial3, "uart3",
+    rt_hw_serial_register(&serial3, ES_DEVICE_NAME_UART3,
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
                           uart);
 #endif /* BSP_USING_UART3 */
+   
+#ifdef BSP_USING_USART0
+    usart = &usart0;
+    serial4.ops = &es32f0x_uart_ops;
+    serial4.config = (struct serial_configure)ES_USART0_CONFIG;
+
+    /* register USART0 device */
+    rt_hw_serial_register(&serial4, ES_DEVICE_NAME_USART0,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          usart);
+#endif /* BSP_USING_USART0 */
+
+#ifdef BSP_USING_USART1
+    usart = &usart1;
+    serial5.ops = &es32f0x_uart_ops;
+    serial5.config = (struct serial_configure)ES_USART1_CONFIG;
 
+    /* register USART1 device */
+    rt_hw_serial_register(&serial5, ES_DEVICE_NAME_USART1,
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                          usart);
+#endif /* BSP_USING_USART1 */
     return 0;
 }
 INIT_BOARD_EXPORT(rt_hw_uart_init);

bsp/essemi/es32f0654/drivers/drv_uart.h

@@ -3,6 +3,18 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
  * Change Logs:
  * Date           Author        Notes
  * 2019-01-23     wangyq        the first version

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_acmp.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_adc.h

@@ -9,6 +9,20 @@
  * @note
  *
  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
  *
  ******************************************************************************
  */

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_bkpc.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_calc.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_can.h

@@ -10,6 +10,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ******************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_cmu.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_conf.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crc.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_crypt.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dbgc.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_dma.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_flash.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_gpio.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_i2c.h

@@ -10,6 +10,20 @@
  * @note
  *
  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
  *
  ********************************************************************************
  */

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_iap.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pis.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_pmu.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rmu.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_rtc.h

@@ -10,6 +10,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *******************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_smartcard.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_spi.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_syscfg.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_timer.h

@@ -12,6 +12,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_trng.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_tsense.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_uart.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_usart.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/ald_wdt.h

@@ -10,6 +10,20 @@
  * @note
  *
  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+  *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
  *
  ********************************************************************************
  */

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/type.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 
@@ -22,6 +36,7 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "es_conf_info_select.h"
 
 
 #if defined (__CC_ARM)

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Include/utils.h

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_acmp.c

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_adc.c

@@ -24,6 +24,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_bkpc.c

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_calc.c

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_can.c

@@ -14,6 +14,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   ********************************************************************************
   * @verbatim
   ==============================================================================

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_cmu.c

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   * @verbatim
   ==============================================================================

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crc.c

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_crypt.c

@@ -12,6 +12,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   */
 

bsp/essemi/es32f0654/libraries/ES32F065x_ALD_StdPeriph_Driver/Source/ald_dma.c

@@ -11,6 +11,20 @@
   *
   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
   *
+  * SPDX-License-Identifier: Apache-2.0
+  *
+  * Licensed under the Apache License, Version 2.0 (the License); you may
+  * not use this file except in compliance with the License.
+  * You may obtain a copy of the License at
+  *
+  * www.apache.org/licenses/LICENSE-2.0
+  *
+  * Unless required by applicable law or agreed to in writing, software
+  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
   *********************************************************************************
   * @verbatim
   ==============================================================================