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@@ -1,10 +1,10 @@
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/******************************************************************************************************************************************
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-* 恅璃靡備: system_SWM320.c
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-* 髡夔佽隴: SWM320等⑵儂腔奀笘扢离
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-* 撮扲盓厥: http://www.synwit.com.cn/e/tool/gbook/?bid=1
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-* 蛁砩岈砐:
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-* 唳掛゜ヽ: V1.1.0 2017爛10堎25゜
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-* 汔撰暮翹:
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+* ��辣�滨妍: system_SWM320.c
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+* �蠘�霂湔�: SWM320�閧��箇��園�霈曄蔭
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+* ���舀𣈲��: http://www.synwit.com.cn/e/tool/gbook/?bid=1
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+* 瘜冽�鈭钅★:
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+* ��𧋦�交�: V1.1.0 2017撟�10��25��
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+* ��漣霈啣�:
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*
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*
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*******************************************************************************************************************************************
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@@ -23,13 +23,13 @@
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/******************************************************************************************************************************************
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- * 炵苀奀笘扢隅
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+ * 蝟餌��園�霈曉�
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*****************************************************************************************************************************************/
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-#define SYS_CLK_20MHz 0 //0 囀窒詢ⅰ20MHz RC淥絕け
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-#define SYS_CLK_40MHz 1 //1 囀窒詢ⅰ40MHz RC淥絕け
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-#define SYS_CLK_32KHz 2 //2 囀窒腴ⅰ32KHz RC淥絕け
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-#define SYS_CLK_XTAL 3 //3 俋窒儒极淥絕けㄗ2-30MHzㄘ
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-#define SYS_CLK_PLL 4 //4 ⑵囀坶眈遠怀堤
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+#define SYS_CLK_20MHz 0 //0 ���擃㗛�20MHz RC�航㨃��
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+#define SYS_CLK_40MHz 1 //1 ���擃㗛�40MHz RC�航㨃��
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+#define SYS_CLK_32KHz 2 //2 ���雿𡡞�32KHz RC�航㨃��
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+#define SYS_CLK_XTAL 3 //3 憭㚚��嗡��航㨃�剁�2-30MHz嚗�
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+#define SYS_CLK_PLL 4 //4 �����㮾�航���
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#define SYS_CLK SYS_CLK_PLL
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@@ -40,16 +40,16 @@
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#define SYS_CLK_DIV SYS_CLK_DIV_1
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-#define __HSI (20000000UL) //詢厒囀窒奀笘
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-#define __LSI ( 32000UL) //腴厒囀窒奀笘
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-#define __HSE (20000000UL) //詢厒俋窒奀笘
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+#define __HSI (20000000UL) //擃㗛�笔��冽𧒄��
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+#define __LSI ( 32000UL) //雿𡡞�笔��冽𧒄��
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+#define __HSE (20000000UL) //擃㗛�笔��冽𧒄��
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-/********************************** PLL 扢隅 **********************************************
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- * VCO怀堤ⅰ薹 = PLL怀⻌奀笘 / INDIV * 4 * FBDIV
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- * PLL怀堤ⅰ薹 = PLL怀⻌奀笘 / INDIV * 4 * FBDIV / OUTDIV = VCO怀堤ⅰ薹 / OUTDIV
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+/********************************** PLL 霈曉� **********************************************
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+ * VCO颲枏枂憸𤑳� = PLL颲枏��園� / INDIV * 4 * FBDIV
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+ * PLL颲枏枂憸𤑳� = PLL颲枏��園� / INDIV * 4 * FBDIV / OUTDIV = VCO颲枏枂憸𤑳� / OUTDIV
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*****************************************************************************************/
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-#define SYS_PLL_SRC SYS_CLK_20MHz //褫龰硉SYS_CLK_20MHz﹜SYS_CLK_XTAL
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+#define SYS_PLL_SRC SYS_CLK_20MHz //�臬��嘯YS_CLK_20MHz��YS_CLK_XTAL
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#define PLL_IN_DIV 5
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@@ -69,11 +69,11 @@ uint32_t CyclesPerUs = (__HSI / 1000000); //Cycles per micro second
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/******************************************************************************************************************************************
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-* 滲杅靡備:
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-* 髡夔佽隴: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed
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-* 怀 ⻌:
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-* 怀 堤:
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-* 蛁砩岈砐:
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+* �賣㺭�滨妍:
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+* �蠘�霂湔�: This function is used to update the variable SystemCoreClock and must be called whenever the core clock is changed
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+* 颲� ��:
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+* 颲� ��:
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+* 瘜冽�鈭钅★:
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******************************************************************************************************************************************/
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void SystemCoreClockUpdate(void)
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{
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@@ -122,11 +122,11 @@ void SystemCoreClockUpdate(void)
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}
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/******************************************************************************************************************************************
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-* 滲杅靡備:
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-* 髡夔佽隴: The necessary initializaiton of systerm
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-* 怀 ⻌:
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-* 怀 堤:
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-* 蛁砩岈砐:
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+* �賣㺭�滨妍:
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+* �蠘�霂湔�: The necessary initializaiton of systerm
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+* 颲� ��:
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+* 颲� ��:
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+* 瘜冽�鈭钅★:
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******************************************************************************************************************************************/
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void SystemInit(void)
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{
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@@ -136,23 +136,23 @@ void SystemInit(void)
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switch(SYS_CLK)
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{
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- case SYS_CLK_20MHz: //0 囀窒詢ⅰ20MHz RC淥絕け
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+ case SYS_CLK_20MHz: //0 ���擃㗛�20MHz RC�航㨃��
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switchCLK_20MHz();
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break;
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- case SYS_CLK_40MHz: //1 囀窒詢ⅰ40MHz RC淥絕け
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+ case SYS_CLK_40MHz: //1 ���擃㗛�40MHz RC�航㨃��
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switchCLK_40MHz();
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break;
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- case SYS_CLK_32KHz: //2 囀窒腴ⅰ32KHz RC淥絕け
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+ case SYS_CLK_32KHz: //2 ���雿𡡞�32KHz RC�航㨃��
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switchCLK_32KHz();
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break;
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- case SYS_CLK_XTAL: //3 俋窒儒极淥絕けㄗ2-30MHzㄘ
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+ case SYS_CLK_XTAL: //3 憭㚚��嗡��航㨃�剁�2-30MHz嚗�
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switchCLK_XTAL();
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break;
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- case SYS_CLK_PLL: //4 ⑵囀坶眈遠怀堤
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+ case SYS_CLK_PLL: //4 �����㮾�航���
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switchCLK_PLL();
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break;
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}
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@@ -276,5 +276,5 @@ void PLLInit(void)
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SYS->PLLCR &= ~(1 << SYS_PLLCR_OFF_Pos);
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- while(SYS->PLLLOCK == 0); //脹渾PLL坶隅
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+ while(SYS->PLLLOCK == 0); //蝑匧�PLL���
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}
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yanmowudi