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@@ -10,6 +10,7 @@
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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+ * 2013-07-12 aozima update for auto initial.
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*/
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#include <rthw.h>
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@@ -19,6 +20,10 @@
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#include "stm32f10x_fsmc.h"
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#include "board.h"
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+#ifdef RT_USING_COMPONENTS_INIT
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+#include <components.h>
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+#endif /* RT_USING_COMPONENTS_INIT */
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+
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/**
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* @addtogroup STM32
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*/
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@@ -35,19 +40,19 @@
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void NVIC_Configuration(void)
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{
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#ifdef VECT_TAB_RAM
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- /* Set the Vector Table base location at 0x20000000 */
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- NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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+ /* Set the Vector Table base location at 0x20000000 */
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+ NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
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#else /* VECT_TAB_FLASH */
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- /* Set the Vector Table base location at 0x08000000 */
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- NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
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+ /* Set the Vector Table base location at 0x08000000 */
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+ NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
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#endif
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}
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#if STM32_EXT_SRAM
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void EXT_SRAM_Configuration(void)
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{
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- FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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- FSMC_NORSRAMTimingInitTypeDef p;
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+ FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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+ FSMC_NORSRAMTimingInitTypeDef p;
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/* FSMC GPIO configure */
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{
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@@ -117,35 +122,35 @@ void EXT_SRAM_Configuration(void)
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}
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/* FSMC GPIO configure */
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- /*-- FSMC Configuration ------------------------------------------------------*/
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- p.FSMC_AddressSetupTime = 0;
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- p.FSMC_AddressHoldTime = 0;
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- p.FSMC_DataSetupTime = 2;
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- p.FSMC_BusTurnAroundDuration = 0;
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- p.FSMC_CLKDivision = 0;
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- p.FSMC_DataLatency = 0;
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- p.FSMC_AccessMode = FSMC_AccessMode_A;
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-
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- FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
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- FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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- FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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- FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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- FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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- FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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- FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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- FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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- FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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-
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- FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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-
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- /* Enable FSMC Bank1_SRAM Bank */
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- FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
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+ /*-- FSMC Configuration ------------------------------------------------------*/
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+ p.FSMC_AddressSetupTime = 0;
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+ p.FSMC_AddressHoldTime = 0;
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+ p.FSMC_DataSetupTime = 2;
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+ p.FSMC_BusTurnAroundDuration = 0;
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+ p.FSMC_CLKDivision = 0;
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+ p.FSMC_DataLatency = 0;
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+ p.FSMC_AccessMode = FSMC_AccessMode_A;
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+
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+ FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
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+ FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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+ FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
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+ FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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+ FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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+ FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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+ FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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+ FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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+ FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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+
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+ FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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+
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+ /* Enable FSMC Bank1_SRAM Bank */
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+ FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
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}
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#endif
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@@ -155,13 +160,13 @@ void EXT_SRAM_Configuration(void)
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*/
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void SysTick_Handler(void)
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{
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- /* enter interrupt */
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- rt_interrupt_enter();
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+ /* enter interrupt */
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+ rt_interrupt_enter();
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- rt_tick_increase();
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+ rt_tick_increase();
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- /* leave interrupt */
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- rt_interrupt_leave();
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+ /* leave interrupt */
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+ rt_interrupt_leave();
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}
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/**
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@@ -169,18 +174,22 @@ void SysTick_Handler(void)
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*/
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void rt_hw_board_init(void)
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{
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- /* NVIC Configuration */
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- NVIC_Configuration();
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+ /* NVIC Configuration */
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+ NVIC_Configuration();
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/* Configure the SysTick */
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SysTick_Config( SystemCoreClock / RT_TICK_PER_SECOND );
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#if STM32_EXT_SRAM
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- EXT_SRAM_Configuration();
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+ EXT_SRAM_Configuration();
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#endif
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- rt_hw_usart_init();
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- rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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+ rt_hw_usart_init();
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+ rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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+
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+#ifdef RT_USING_COMPONENTS_INIT
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+ rt_components_board_init();
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+#endif
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}
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/*@}*/
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