Merge remote-tracking branch 'gitee/gitee_master'

bsp/essemi/es32f0334/.config

@@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
-CONFIG_RT_VER_NUM=0x40002
+CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
@@ -115,18 +115,29 @@ CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
 # CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
+CONFIG_RT_USING_HWTIMER=y
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
 CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_ADC is not set
-# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_ADC=y
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_PM=y
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@@ -192,11 +203,15 @@ CONFIG_RT_USING_PIN=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
 # CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -223,6 +238,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -235,8 +251,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -251,6 +269,15 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
 # CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 
 #
 # security packages
@@ -258,6 +285,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -274,6 +303,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
 
 #
 # tools packages
@@ -289,6 +319,12 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
 # CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
 
 #
 # system packages
@@ -299,6 +335,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -307,6 +344,15 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEFS is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_PPOOL is not set
 
 #
 # peripheral libraries and drivers
@@ -323,6 +369,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_SX12XX is not set
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
@@ -336,9 +386,27 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
 # CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_LCD_DRIVERS is not set
 # CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
 
 #
 # miscellaneous packages
@@ -373,8 +441,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
 
 #
 # Hardware Drivers Config
@@ -442,4 +516,18 @@ CONFIG_BSP_USING_UART1=y
 #
 # Offboard Peripheral Drivers
 #
+
+#
+# Peripheral Drivers test example
+#
+# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set
+# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set
+# CONFIG_BSP_USING_EXAMPLE_I2C is not set
+# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set
+# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set
+# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set
+# CONFIG_BSP_USING_EXAMPLE_RTC is not set
+# CONFIG_BSP_USING_EXAMPLE_SPI is not set
+# CONFIG_BSP_USING_EXAMPLE_UART is not set
+# CONFIG_BSP_USING_EXAMPLE_PM is not set
 CONFIG_SOC_ES32F0334LT=y

bsp/essemi/es32f0334/README.md

@@ -86,6 +86,22 @@ msh >
 
 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
 
+    a）如果需要使用内核用例，先配置rt-thread内核，如图：
+
+    ![kernel_config](figures/k_conf.jpg)
+
+    然后配置内核用例，如图：
+
+    ![kernel_samples](figures/k_ex.jpg)
+
+    b）如果需要使用驱动用例：先使能驱动，如图：
+
+    ![driver_config](figures/drv_conf.jpg)
+
+     然后配置驱动用例，如图：
+
+    ![driver_sample](figures/drv_ex.jpg)
+
 3. 输入`pkgs --update`命令更新软件包。
 
 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
@@ -94,7 +110,7 @@ msh >
 
 ## 4. 联系人信息
 
-- [wangyongquan](https://github.com/wangyq2018) 
+- [liuhongyan](https://gitee.com/liuhongyan98) 
 
 ## 5. 参考
 

bsp/essemi/es32f0334/drivers/Kconfig

@@ -127,4 +127,50 @@ menu "Hardware Drivers Config"
 
     endmenu
 
+
+    menu "Peripheral Drivers test example"
+
+        config BSP_USING_EXAMPLE_ADC_VOL
+            bool "BSP_USING_EXAMPLE_ADC_VOL"
+            default n
+        
+        config BSP_USING_EXAMPLE_HWTIMER
+            bool "BSP_USING_EXAMPLE_HWTIMER"
+            default n
+
+        config BSP_USING_EXAMPLE_I2C
+            bool "BSP_USING_EXAMPLE_I2C"
+            default n
+
+        config BSP_USING_EXAMPLE_LED_BLINK
+            bool "BSP_USING_EXAMPLE_LED_BLINK"
+            default y
+
+        config BSP_USING_EXAMPLE_PIN_BEEP
+            bool "BSP_USING_EXAMPLE_PIN_BEEP"
+            default y
+
+        config BSP_USING_EXAMPLE_PWM_LED
+            bool "BSP_USING_EXAMPLE_PWM_LED"
+            default n
+
+        config BSP_USING_EXAMPLE_RTC
+            bool "BSP_USING_EXAMPLE_RTC"
+            default n
+
+        config BSP_USING_EXAMPLE_SPI
+            bool "BSP_USING_EXAMPLE_SPI"
+            default n
+
+        config BSP_USING_EXAMPLE_UART
+            bool "BSP_USING_EXAMPLE_UART"
+            default y
+
+        config BSP_USING_EXAMPLE_PM
+            bool "BSP_USING_EXAMPLE_PM"
+            default n
+
+
+    endmenu
+
 endmenu

bsp/essemi/es32f0334/drivers/SConscript

@@ -2,6 +2,8 @@ from building import *
 
 cwd = GetCurrentDir()
 
+objs = []
+
 # add the general drivers.
 src = Split('''
 board.c
@@ -50,5 +52,43 @@ if GetDepend(['BSP_USING_ADC']):
 
 CPPPATH = [cwd]
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+objs = objs + group
+
+src   = []
+cwd   = GetCurrentDir()
+include_path = [cwd]
+
+if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'):
+    src += ['bsp_driver_example/adc_vol_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_HWTIMER'):
+    src += ['bsp_driver_example/hwtimer_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_I2C'):
+    src += ['bsp_driver_example/i2c_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'):
+    src += ['bsp_driver_example/led_blink_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'):
+    src += ['bsp_driver_example/pin_beep_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_PWM_LED'):
+    src += ['bsp_driver_example/pwm_led_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_RTC'):
+    src += ['bsp_driver_example/rtc_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_UART'):
+    src += ['bsp_driver_example/uart_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_SPI'):
+    src += ['bsp_driver_example/spi_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_PM'):
+    src += ['bsp_driver_example/pm_sample.c']
+
+group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path)
 
-Return('group')
+objs = objs + group
+Return('objs')

bsp/essemi/es32f0334/drivers/bsp_driver_example/.gitignore

@@ -0,0 +1,52 @@
+# Prerequisites
+*.d
+
+# Object files
+*.o
+*.ko
+*.obj
+*.elf
+
+# Linker output
+*.ilk
+*.map
+*.exp
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Libraries
+*.lib
+*.a
+*.la
+*.lo
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+*.i*86
+*.x86_64
+*.hex
+
+# Debug files
+*.dSYM/
+*.su
+*.idb
+*.pdb
+
+# Kernel Module Compile Results
+*.mod*
+*.cmd
+.tmp_versions/
+modules.order
+Module.symvers
+Mkfile.old
+dkms.conf

bsp/essemi/es32f0334/drivers/bsp_driver_example/README.md

@@ -0,0 +1,47 @@
+# 外设驱动测试用例
+
+## 1、介绍
+
+这个软件包包含一些外设设备操作的例程。
+
+### 1.1 例程说明
+
+| 文件             | 说明                            |
+| ---------------- | ------------------------------- |
+| adc_vol_sample.c       | 使用 ADC 设备转换电压数据 |
+| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 |
+| hwtimer_sample.c       | 使用 硬件定时器定时 |
+| i2c_sample.c     | 使用 i2c 设备进行读写 |
+| pm.c | 反复进入不同程度的睡眠。 |
+| led_blink_sample.c     |  使用 pin 设备控制 LED 闪烁 |
+| pin_beep_sample.c      | 使用 pin 设备控制蜂鸣器 |
+| pwm_led_sample.c       | 使用 pwm 设备控制 LED 的亮度 |
+| rtc_sample.c           | 使用 rtc 设备设置年月日时分秒信息 |
+| spi_sample.c     | 使用 spi 设备进行读写 |
+| uart_sample.c          | 使用 serial 设备中断接收及轮询发送模式收发数据 |
+
+### 1.2 依赖
+
+依赖设备管理模块提供的设备驱动。
+
+## 2、如何打开 外设驱动测试用例
+
+使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下：
+
+```
+Hardware Driver Config --->
+    Peripheral Driver test example--->
+```
+
+## 3、使用 外设驱动测试用例
+
+在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。
+
+## 4、注意事项
+
+暂无。
+
+## 5、联系方式 & 感谢
+
+* 维护：[misonyo](https://github.com/misonyo)
+* 主页：https://github.com/RT-Thread-packages/peripheral-sample

bsp/essemi/es32f0334/drivers/bsp_driver_example/adc_vol_sample.c

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-29     misonyo      first implementation.
+ */
+/*
+ * 程序清单： ADC 设备使用例程
+ * 例程导出了 adc_sample 命令到控制终端
+ * 命令调用格式：adc_sample
+ * 程序功能：通过 ADC 设备采样电压值并转换为数值。
+ *           示例代码参考电压为3.3V,转换位数为12位。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define ADC_DEV_NAME        "adc0"      /* ADC 设备名称 */
+#define ADC_DEV_CHANNEL     5           /* PA1 ADC 通道 */
+#define REFER_VOLTAGE       330         /* 参考电压 3.3V,数据精度乘以100保留2位小数*/
+#define CONVERT_BITS        (1 << 12)   /* 转换位数为12位 */
+
+static int adc_vol_sample(int argc, char *argv[])
+{
+    rt_adc_device_t adc_dev;
+    rt_uint32_t value, vol;
+    rt_err_t ret = RT_EOK;
+
+    /* 查找设备 */
+    adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
+    if (adc_dev == RT_NULL)
+    {
+        rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    /* 使能设备 */
+    ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
+
+    /* 读取采样值 */
+    value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
+    rt_kprintf("the value is :%d \n", value);
+
+    /* 转换为对应电压值 */
+    vol = value * REFER_VOLTAGE / CONVERT_BITS;
+    rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
+
+    /* 关闭通道 */
+    ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/can_sample.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-06-25     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 CAN 设备使用例程
+ * 例程导出了 can_sample 命令到控制终端
+ * 命令调用格式：can_sample can2
+ * 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备
+ * 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。
+*/
+
+#include <rtthread.h>
+#include "rtdevice.h"
+
+#define CAN_DEV_NAME       "can2"      /* CAN 设备名称 */
+
+static struct rt_semaphore rx_sem;     /* 用于接收消息的信号量 */
+static rt_device_t can_dev;            /* CAN 设备句柄 */
+
+/* 接收数据回调函数 */
+static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
+{
+    /* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
+    rt_sem_release(&rx_sem);
+
+    return RT_EOK;
+}
+
+static void can_rx_thread(void *parameter)
+{
+    int i;
+    struct rt_can_msg rxmsg = {0};
+
+    /* 设置接收回调函数 */
+    rt_device_set_rx_indicate(can_dev, can_rx_call);
+
+#ifdef RT_CAN_USING_HDR
+    
+    rt_err_t res;
+    
+    struct rt_can_filter_item items[5] =
+    {
+        RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */
+        RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */
+        RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */
+        RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL),                  /* std,match ID:0x486，hdr为-1 */
+        {0x555, 0, 0, 0, 0x7ff, 7,}                                       /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */
+    };
+    struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */
+    /* 设置硬件过滤表 */
+    res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
+    RT_ASSERT(res == RT_EOK);
+#endif
+
+    while (1)
+    {
+        /* hdr值为-1，表示直接从uselist链表读取数据 */
+        rxmsg.hdr = -1;
+        /* 阻塞等待接收信号量 */
+        rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
+        /* 从CAN读取一帧数据 */
+        rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
+        /* 打印数据ID及内容 */
+        rt_kprintf("ID:%x  ", rxmsg.id);
+        for (i = 0; i < 8; i++)
+        {
+            rt_kprintf("%2x ", rxmsg.data[i]);
+        }
+
+        rt_kprintf("\n");
+    }
+}
+
+int can_sample(int argc, char *argv[])
+{
+    struct rt_can_msg msg = {0};
+    rt_err_t res;
+    rt_size_t  size;
+    rt_thread_t thread;
+    char can_name[RT_NAME_MAX];
+    
+    if (argc == 2)
+    {
+        rt_strncpy(can_name, argv[1], RT_NAME_MAX);
+    }
+    else
+    {
+        rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX);
+    }
+
+    can_dev = rt_device_find(can_name);
+    if (!can_dev)
+    {
+        rt_kprintf("find %s failed!\n", can_name);
+        return RT_ERROR;
+    }
+
+    /* 初始化CAN接收信号量 */
+    rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
+
+    /* 以中断接收及发送方式打开CAN设备 */
+    res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
+    RT_ASSERT(res == RT_EOK);
+
+    thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        rt_kprintf("create can_rx thread failed!\n");
+    }
+
+    msg.id = 0x78;              /* ID为0x78 */
+    msg.ide = RT_CAN_STDID;     /* 标准格式 */
+    msg.rtr = RT_CAN_DTR;       /* 数据帧 */
+    msg.len = 8;                /* 数据长度为8 */
+    /* 待发送的8字节数据 */
+    msg.data[0] = 0x00;
+    msg.data[1] = 0x11;
+    msg.data[2] = 0x22;
+    msg.data[3] = 0x33;
+    msg.data[4] = 0x44;
+    msg.data[5] = 0x55;
+    msg.data[6] = 0x66;
+    msg.data[7] = 0x77;
+    /* 发送一帧CAN数据 */
+    size = rt_device_write(can_dev, 0, &msg, sizeof(msg));
+    if (size == 0)
+    {
+        rt_kprintf("can dev write data failed!\n");
+    }
+    
+    return res;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(can_sample, can device sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/hwtimer_sample.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-30     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 hwtimer 设备使用例程
+ * 例程导出了 hwtimer_sample 命令到控制终端
+ * 命令调用格式：hwtimer_sample
+ * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define HWTIMER_DEV_NAME   "timer0"     /* 定时器名称 */
+
+/* 定时器超时回调函数 */
+static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("tick is :%d !\n", rt_tick_get());
+
+    return 0;
+}
+
+static int hwtimer_sample(int argc, char *argv[])
+{
+    rt_err_t ret = RT_EOK;
+    rt_hwtimerval_t timeout_s;      /* 定时器超时值 */
+    rt_device_t hw_dev = RT_NULL;   /* 定时器设备句柄 */
+    rt_hwtimer_mode_t mode;         /* 定时器模式 */
+
+    /* 查找定时器设备 */
+    hw_dev = rt_device_find(HWTIMER_DEV_NAME);
+    if (hw_dev == RT_NULL)
+    {
+        rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    /* 以读写方式打开设备 */
+    ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
+        return ret;
+    }
+
+    /* 设置超时回调函数 */
+    rt_device_set_rx_indicate(hw_dev, timeout_cb);
+
+    /* 设置模式为周期性定时器 */
+    mode = HWTIMER_MODE_PERIOD;
+    ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set mode failed! ret is :%d\n", ret);
+        return ret;
+    }
+
+    /* 设置定时器超时值为5s并启动定时器 */
+    timeout_s.sec = 5;      /* 秒 */
+    timeout_s.usec = 0;     /* 微秒 */
+
+    if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
+    {
+        rt_kprintf("set timeout value failed\n");
+        return RT_ERROR;
+    }
+
+    /* 延时3500ms */
+    rt_thread_mdelay(3500);
+
+    /* 读取定时器当前值 */
+    rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
+    rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/i2c_sample.c

@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-12-15     liuhy       first implementation.
+ */
+/*
+ * 程序清单：这是一个 I2C 设备使用例程
+ * 例程导出了 i2c_io_sample 命令到控制终端
+ * 命令调用格式：i2c_io_sample
+ * 命令解释：使用默认的I2C总线设备
+ * 程序功能：通过 I2C 设备接收数据并打印，然后将接收的字符加1输出。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define I2C_BUS_NAME          "i2c1"  /* I2C总线设备名称 */
+#define SLAVE_ADDR                  0x2D    /* 从机地址 */
+#define STR_LEN                       16    /* 接收发送的数据长度 */
+
+static void i2c_io_sample(int argc, char *argv[])
+{
+    
+    struct rt_i2c_bus_device *i2c_bus = RT_NULL;     /* I2C总线设备句柄 */
+    struct rt_i2c_msg temp_msg;                             /* I2C消息 */
+    rt_uint8_t buffer[STR_LEN] = { 0U }; 
+    rt_uint32_t i,num_msg;
+    rt_size_t s_stat;
+    
+    i2c_bus = (struct rt_i2c_bus_device *)rt_device_find(I2C_BUS_NAME);    /* 通过名字获取I2C总线设备的句柄 */
+    
+    if( i2c_bus == RT_NULL)
+    {
+        rt_kprintf("can't find i2c device :%s !\n",I2C_BUS_NAME);
+        
+        return;
+    }
+    
+        /*初始化消息*/
+        temp_msg.addr = SLAVE_ADDR;  /* 从机地址 */
+        temp_msg.len  = STR_LEN;     /* 传输的数据长度 */
+        temp_msg.buf = buffer;       /* 读写缓存器 */
+    
+        num_msg = 1;             /* 传输一条消息 */
+    
+        temp_msg.flags = RT_I2C_RD;             /* I2C读 */
+        s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg);   /* 传输消息 */
+        
+        rt_thread_mdelay(400); 
+        
+        if( s_stat == num_msg )
+        {
+            rt_kprintf("receive successful. \n receive messege : %s \n:",buffer);
+            
+            for( i = 0 ; i < STR_LEN ; i++)
+            rt_kprintf(" %x",(unsigned int)buffer[i]);
+            
+            rt_kprintf("\n");
+        }
+        else
+        {
+            rt_kprintf("device s% recieve fail \n buffer : s%\n",I2C_BUS_NAME,buffer);
+            return;
+        }
+        
+        for( i = 0 ; i < STR_LEN ; i++)
+        buffer[i]++;
+    
+        temp_msg.flags = RT_I2C_WR;             /* I2C写 */
+        s_stat = rt_i2c_transfer(i2c_bus,&temp_msg,num_msg);   /* 传输一条 */
+        
+        rt_thread_mdelay(400);
+        
+        if( s_stat == num_msg )
+        {
+            rt_kprintf(" send successful \n messege : %s \n:",buffer);
+            
+            for( i = 0 ; i < STR_LEN ; i++)
+            rt_kprintf(" %x",(unsigned int)buffer[i]);
+            
+            rt_kprintf("\n");
+        }
+        else
+        {
+            rt_kprintf("device s% send fail \n",I2C_BUS_NAME);
+            return;
+        }
+        
+        return;
+    
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(i2c_io_sample, i2c io sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/led_blink_sample.c

@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-09-25     misonyo      first edition.
+ */
+/*
+ * 程序清单：这是一个通过PIN脚控制LED亮灭的使用例程
+ * 例程导出了 led_sample 命令到控制终端
+ * 命令调用格式：led_sample 
+ * 命令解释：命令第二个参数是要使用的PIN脚编号，为空则使用例程默认的引脚编号。
+ * 程序功能：程序创建一个led线程，线程每隔1000ms改变PIN脚状态，达到控制led灯
+ *            亮灭的效果。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <stdlib.h>
+
+/* PIN脚编号，查看驱动文件drv_gpio.c确定 */
+#define LED_PIN_NUM    45  /*PA12*/
+static int pin_num;
+
+static void led_entry(void *parameter)
+{
+    int count = 0;
+    /* 设置PIN脚模式为输出 */
+    rt_pin_mode(pin_num, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        count++;
+        rt_kprintf("thread run count : %d\r\n", count);
+        /* 拉低PIN脚 */
+        rt_pin_write(pin_num, PIN_LOW);
+        rt_kprintf("led on!\r\n");
+        /* 延时1000ms */
+        rt_thread_mdelay(1000);
+
+        /* 拉高PIN脚 */
+        rt_pin_write(pin_num, PIN_HIGH);
+        rt_kprintf("led off!\r\n");
+        rt_thread_mdelay(1000);
+    }
+}
+
+static int led_sample(int argc, char *argv[])
+{
+    rt_thread_t tid;
+    rt_err_t ret = RT_EOK;
+
+    /* 判断命令行参数是否给定了PIN脚编号 */
+    if (argc == 2)
+    {
+        pin_num = atoi(argv[1]);
+    }
+    else
+    {
+        pin_num = LED_PIN_NUM;
+    }
+
+    tid = rt_thread_create("led",
+                           led_entry,
+                           RT_NULL,
+                           512,
+                           RT_THREAD_PRIORITY_MAX / 3,
+                           20);
+    if (tid != RT_NULL)
+    {
+        rt_thread_startup(tid);
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(led_sample, led sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/pin_beep_sample.c

@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-15     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 PIN 设备使用例程
+ * 例程导出了 pin_beep_sample 命令到控制终端
+ * 命令调用格式：pin_beep_sample
+ * 程序功能：通过按键控制蜂鸣器对应引脚的电平状态控制蜂鸣器
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+/* 引脚编号，通过查看驱动文件drv_gpio.c确定 */
+#ifndef BEEP_PIN_NUM
+    #define BEEP_PIN_NUM            45  /* PA12 */
+#endif
+#ifndef KEY0_PIN_NUM
+    #define KEY0_PIN_NUM            18  /* PF0 */
+#endif
+#ifndef KEY1_PIN_NUM
+    #define KEY1_PIN_NUM            19  /* PF1 */
+#endif
+
+void beep_on(void *args)
+{
+    rt_kprintf("turn on beep!\n");
+
+    rt_pin_write(BEEP_PIN_NUM, PIN_HIGH);
+}
+
+void beep_off(void *args)
+{
+    rt_kprintf("turn off beep!\n");
+
+    rt_pin_write(BEEP_PIN_NUM, PIN_LOW);
+}
+
+static void pin_beep_sample(void)
+{
+    /* 蜂鸣器引脚为输出模式 */
+    rt_pin_mode(BEEP_PIN_NUM, PIN_MODE_OUTPUT);
+    /* 默认低电平 */
+    rt_pin_write(BEEP_PIN_NUM, PIN_LOW);
+
+    /* 按键0引脚为输入模式 */
+    rt_pin_mode(KEY0_PIN_NUM, PIN_MODE_INPUT_PULLUP);
+    /* 绑定中断，下降沿模式，回调函数名为beep_on */
+    rt_pin_attach_irq(KEY0_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_on, RT_NULL);
+    /* 使能中断 */
+    rt_pin_irq_enable(KEY0_PIN_NUM, PIN_IRQ_ENABLE);
+
+    /* 按键1引脚为输入模式 */
+    rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP);
+    /* 绑定中断，下降沿模式，回调函数名为beep_off */
+    rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, beep_off, RT_NULL);
+    /* 使能中断 */
+    rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE);
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(pin_beep_sample, pin beep sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/pm_sample.c

@@ -0,0 +1,182 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-12-15     liuhy       first implementation.
+ */
+/*
+ * 程序清单：这是一个 pm睡眠唤醒的使用例程
+ * 例程导出了 pm_sample 命令到控制终端
+ * 命令调用格式：pm_sample
+ * 命令解释：进入不同的睡眠模式，然后用按键唤醒
+ * 程序功能：通过串口输出字符串，告知进入睡眠和唤醒睡眠的情况。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define PM_NAME       "pm"      /* 设备名称 */
+#define WAKE_UP_PIN     18      /* 唤醒源 */
+#define SLEEP_TIMES     12      /* 进入睡眠次数，轮流进入不同的睡眠模式，包括无睡眠模式 */
+
+struct pm_callback_t
+{
+     volatile int in_fun_times;   /*进入函数的次数*/
+     volatile char flag;          /*标志*/
+     volatile int mode;           /*需要打印的模式*/
+};
+
+volatile struct pm_callback_t g_pm_data;
+
+/*进入睡眠前，睡眠唤醒后，都会进入。*/
+/*函数打印睡眠相关的信息*/
+void sleep_in_out_callback(rt_uint8_t event, rt_uint8_t mode, void *data)
+{
+    /*没有标志，不处理*/
+    if(!(g_pm_data.flag))
+    {
+        return;
+    }
+    
+    /*标志不正常，清空标志*/
+    if((g_pm_data.flag) > 2)
+    {
+        (g_pm_data.flag) = 0;
+        return;
+    }
+    
+    /*模式不匹配*/
+    if(g_pm_data.mode != mode )
+    {
+        return;
+    }
+ 
+    /*进入的事件*/
+    switch(event)
+    {
+        /*进入睡眠前*/
+        case RT_PM_ENTER_SLEEP: g_pm_data.flag = 1;
+                                rt_kprintf("\n\r##%d :  ENTER  ",g_pm_data.in_fun_times);
+                                g_pm_data.in_fun_times++;     /*进入睡眠次数+1*/
+                                break;
+        /*睡眠唤醒后*/
+        case RT_PM_EXIT_SLEEP:  g_pm_data.flag = 0;  /*睡眠唤醒后*/
+                                rt_kprintf("\n\rEXIT\n\r");
+                                rt_pm_release(mode);   /*释放休眠模式*/
+                                return;
+        
+        default: break;
+        
+    };
+    
+    /*当前的睡眠模式*/
+    switch(mode)
+    {
+        case PM_SLEEP_MODE_NONE: rt_kprintf("PM_SLEEP_MODE_NONE\n\r");
+                                break;
+        case PM_SLEEP_MODE_IDLE:  rt_kprintf("PM_SLEEP_MODE_IDLE\n\r");
+                                break;
+        case PM_SLEEP_MODE_LIGHT: rt_kprintf("PM_SLEEP_MODE_LIGHT\n\r");
+                                break;
+        case PM_SLEEP_MODE_DEEP:  rt_kprintf("PM_SLEEP_MODE_DEEP\n\r");
+                                break;
+        case PM_SLEEP_MODE_STANDBY: rt_kprintf("PM_SLEEP_MODE_STANDBY\n\r");
+                                break;
+        case PM_SLEEP_MODE_SHUTDOWN:  rt_kprintf("PM_SLEEP_MODE_SHUTDOWN\n\r");
+                                break;      
+        case PM_SLEEP_MODE_MAX:  rt_kprintf("PM_SLEEP_MODE_MAX\n\r");
+                                break;
+        default: break;           
+    }
+    
+}
+
+/* pm测试函数 */
+static void pm_test(void *parameter)
+{
+    int in_mode[7],i = 0;
+    
+        g_pm_data.in_fun_times = 0;
+        g_pm_data.flag = 0;
+    
+        in_mode[0] = PM_SLEEP_MODE_NONE;
+        in_mode[1] = PM_SLEEP_MODE_IDLE;
+        in_mode[2] = PM_SLEEP_MODE_LIGHT;
+        in_mode[3] = PM_SLEEP_MODE_DEEP;
+        in_mode[4] = PM_SLEEP_MODE_STANDBY;
+        in_mode[5] = PM_SLEEP_MODE_SHUTDOWN;
+        in_mode[6] = PM_SLEEP_MODE_MAX;
+    
+    /*设置回调函数和私有数据*/
+    rt_pm_notify_set(sleep_in_out_callback,RT_NULL);
+       
+    while(i < SLEEP_TIMES)
+   {
+       
+       g_pm_data.mode = in_mode[i%6];
+       
+       /*无休眠模式，不赋予标志*/
+       if(g_pm_data.mode != PM_SLEEP_MODE_NONE)
+       {
+            g_pm_data.flag = 2;  
+       
+       }
+       
+       /*请求选择的休眠模式*/
+       rt_pm_request(in_mode[i%6]);
+
+       rt_thread_mdelay(500);
+       
+       /*无休眠模式，不需要额外的等待*/
+       while(( g_pm_data.flag != 0 )&&(g_pm_data.mode != PM_SLEEP_MODE_NONE))
+       {
+           rt_thread_mdelay(500);
+       }
+       
+       /*释放选择的休眠模式*/
+       rt_pm_release(in_mode[i%6]);
+       
+       i++;
+       
+   }
+      /*清除回调函数和私有数据*/
+    rt_pm_notify_set(RT_NULL,RT_NULL);
+   rt_kprintf("thread pm_test close\n\r");
+}
+
+/*按键唤醒的回调函数*/
+void wake_by_pin(void *args)
+{
+
+}
+
+static int pm_sample(int argc, char *argv[])
+{
+    rt_thread_t thread;
+    
+    /* 按键引脚为输入模式 */
+    rt_pin_mode(WAKE_UP_PIN, PIN_MODE_INPUT_PULLUP);
+    
+    /* 绑定中断，下降沿模式，回调函数名为wake_by_pin */
+    rt_pin_attach_irq(WAKE_UP_PIN, PIN_IRQ_MODE_RISING, wake_by_pin, RT_NULL);
+    /* 使能中断 */
+    rt_pin_irq_enable(WAKE_UP_PIN, PIN_IRQ_ENABLE);
+    
+    thread = rt_thread_create("pm_test", pm_test, RT_NULL, 1024, 25, 10);
+    
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        rt_kprintf("create pm_test thread failed!\n\r");
+    }
+    
+    return RT_EOK;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(pm_sample, pm sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/pwm_led_sample.c

@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-25     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 PWM 设备使用例程
+ * 例程导出了 pwm_led_sample 命令到控制终端
+ * 命令调用格式：pwm_led_sample
+ * 程序功能：通过 PWM 设备控制 LED 灯的亮度，可以看到LED不停的由暗变到亮，然后又从亮变到暗。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN_NUM         45      /* PA12 LED PIN脚编号，查看驱动文件drv_gpio.c确定 */
+#define PWM_DEV_NAME        "pwm0"  /* PWM设备名称 */
+#define PWM_DEV_CHANNEL     2       /* PA9 PWM通道 */
+
+struct rt_device_pwm *pwm_dev;      /* PWM设备句柄 */
+
+static int pwm_led_sample(int argc, char *argv[])
+{
+    rt_uint32_t period, pulse, dir;
+
+    period = 500000;    /* 周期为0.5ms，单位为纳秒ns */
+    dir = 1;            /* PWM脉冲宽度值的增减方向 */
+    pulse = 0;          /* PWM脉冲宽度值，单位为纳秒ns */
+
+    /* 查找设备 */
+    pwm_dev = (struct rt_device_pwm *)rt_device_find(PWM_DEV_NAME);
+    if (pwm_dev == RT_NULL)
+    {
+        rt_kprintf("pwm sample run failed! can't find %s device!\n", PWM_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    /* 设置PWM周期和脉冲宽度默认值 */
+    rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
+    /* 使能设备 */
+    rt_pwm_enable(pwm_dev, PWM_DEV_CHANNEL);
+    
+    while (1)
+    {
+        rt_thread_mdelay(50);
+        if (dir)
+        {
+            pulse += 5000;      /* 从0值开始每次增加5000ns */
+        }
+        else
+        {
+            pulse -= 5000;      /* 从最大值开始每次减少5000ns */
+        }
+        if (pulse >= period)
+        {
+            dir = 0;
+        }
+        if (0 == pulse)
+        {
+            dir = 1;
+        }
+
+        /* 设置PWM周期和脉冲宽度 */
+        rt_pwm_set(pwm_dev, PWM_DEV_CHANNEL, period, pulse);
+    }
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(pwm_led_sample, pwm sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/rtc_sample.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-30     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 RTC 设备使用例程
+ * 例程导出了 rtc_sample 命令到控制终端
+ * 命令调用格式：rtc_sample
+ * 程序功能：设置RTC设备的日期和时间，延时一段时间后获取当前时间并打印显示。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+static int rtc_sample(int argc, char *argv[])
+{
+    rt_err_t ret = RT_EOK;
+    time_t now;
+
+    /* 设置日期 */
+    ret = set_date(2018, 12, 3);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set RTC date failed\n");
+        return ret;
+    }
+
+    /* 设置时间 */
+    ret = set_time(11, 15, 50);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set RTC time failed\n");
+        return ret;
+    }
+
+    /* 延时3秒 */
+    rt_thread_mdelay(3000);
+
+    /* 获取时间 */
+    now = time(RT_NULL);
+    rt_kprintf("%s\n", ctime(&now));
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(rtc_sample, rtc sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/spi_sample.c

@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2020-12-15     liuhy       first implementation.
+ */
+/*
+ * 程序清单：这是一个 SPI 设备使用例程
+ * 例程导出了 spi_io_sample 命令到控制终端
+ * 命令调用格式：spi_io_sample
+ * 程序功能：通过SPI设备先读取数据，然后每个字符加1后输出。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define SPI_DEVICE_NAME     "spi00"
+#define BUF_LEN             16
+
+static void spi_io_sample(int argc, char *argv[])
+{
+    struct rt_spi_device * spi_dev;          /* spi设备的句柄 */
+    struct rt_spi_configuration spi_config;
+    rt_uint8_t i,buffer[BUF_LEN] = { 0U };
+    rt_err_t s_stat;
+    rt_err_t result;
+    
+     /* 查找 spi设备 获取spi设备句柄 */
+    spi_dev = (struct rt_spi_device *)rt_device_find(SPI_DEVICE_NAME);
+    
+    if (spi_dev == RT_NULL)
+    {
+        rt_kprintf("spi sample run failed! can't find %s device!\n", SPI_DEVICE_NAME);
+        return;
+    }
+    
+    
+    /* 清空配置结构体 */
+    rt_memset(&spi_config,0,sizeof(struct rt_spi_configuration));
+    
+    spi_config.mode &= ~RT_SPI_SLAVE; /* 主机模式 */
+    spi_config.mode &= ~RT_SPI_3WIRE; /* 4线，双向传输 */
+    spi_config.mode |= RT_SPI_CPHA;   /* 第二边沿采样 */
+    spi_config.mode |= RT_SPI_CPOL;   /* 空闲高电平 */
+    spi_config.mode |= RT_SPI_NO_CS;  /* 禁用软件从机选择管理 */
+    spi_config.mode |= RT_SPI_MSB;    /* 高位在前 */
+    
+    spi_config.data_width = 8;        /* 数据长度：8 */
+    
+    spi_config.max_hz = 2000000;      /* 最快时钟频率 */
+    
+    /* 配置SPI设备 */
+    s_stat = rt_spi_configure(spi_dev,&spi_config);
+    
+    if(s_stat != RT_EOK)
+    {
+        rt_kprintf(" spi config fail !\n ");
+        return;
+    }
+    
+    
+    /* 获取总线 ，防止总线被多个线程同时使用 */
+    result = rt_spi_take_bus(spi_dev);
+    
+    if (result != RT_EOK)
+    {
+        rt_kprintf(" %s take spi bus  failed! \n", SPI_DEVICE_NAME);
+        return;
+    }
+    
+    /* 选中片选 */
+    result = rt_spi_take(spi_dev);
+    
+    if (result != RT_EOK)
+    {
+        rt_kprintf(" %s take spi cs  failed! \n", SPI_DEVICE_NAME);
+        return;
+    }
+    
+    
+    /*接收一次数据*/
+    result = rt_spi_recv(spi_dev,buffer,BUF_LEN);
+    
+    if(result != BUF_LEN)
+    {
+        rt_kprintf("receive fail. \n buffer is : %s \n:",buffer);
+            
+        for( i = 0 ; i < BUF_LEN ; i++)
+         rt_kprintf(" %x",(unsigned int)buffer[i]);
+            
+        rt_kprintf("\n");
+        
+        return;
+    }
+    
+    rt_kprintf("receive successful. \n buffer is : %s \n:",buffer);
+            
+    for( i = 0 ; i < BUF_LEN ; i++)
+    rt_kprintf(" %x",(unsigned int)buffer[i]);
+            
+    rt_kprintf("\n");
+    
+    /* 将接收到的数据加1 */
+    for( i = 0 ; i < BUF_LEN ; i++)
+      buffer[i]++;
+    
+    /*发送数据*/
+    result = rt_spi_send(spi_dev,buffer,BUF_LEN);
+    
+    if(result != BUF_LEN)
+    {
+        rt_kprintf("send fail. \n buffer is : %s \n:",buffer);
+            
+        for( i = 0 ; i < BUF_LEN ; i++)
+         rt_kprintf(" %x",(unsigned int)buffer[i]);
+            
+        rt_kprintf("\n");
+        
+        return;
+    }
+    
+    rt_kprintf("send successful. \n buffer is : %s \n:",buffer);
+            
+    for( i = 0 ; i < BUF_LEN ; i++)
+    rt_kprintf(" %x",(unsigned int)buffer[i]);
+            
+    rt_kprintf("\n");
+   
+    /* 释放片选 */
+    result = rt_spi_release(spi_dev);
+    
+    if (result != RT_EOK)
+    {
+        rt_kprintf(" %s release spi cs failed! \n", SPI_DEVICE_NAME);
+        return;
+    } 
+    
+    /* 释放总线 */
+    result = rt_spi_release_bus(spi_dev);
+    
+    if (result != RT_EOK)
+    {
+        rt_kprintf(" %s release spi bus  failed! \n", SPI_DEVICE_NAME);
+        return;
+    }
+    
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(spi_io_sample, spi  sample);

bsp/essemi/es32f0334/drivers/bsp_driver_example/uart_sample.c

@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-08-15     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 串口 设备使用例程
+ * 例程导出了 uart_sample 命令到控制终端
+ * 命令调用格式：uart_sample uart2
+ * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备
+ * 程序功能：通过串口输出字符串"hello RT-Thread!"，然后错位输出输入的字符
+*/
+
+#include <rtthread.h>
+
+#define SAMPLE_UART_NAME       "uart1"      /* 串口设备名称 */
+
+/* 用于接收消息的信号量 */
+static struct rt_semaphore rx_sem;
+static rt_device_t serial;
+
+/* 接收数据回调函数 */
+static rt_err_t uart_input(rt_device_t dev, rt_size_t size)
+{
+    /* 串口接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
+    rt_sem_release(&rx_sem);
+
+    return RT_EOK;
+}
+
+static void serial_thread_entry(void *parameter)
+{
+    char ch;
+
+    while (1)
+    {
+        /* 从串口读取一个字节的数据，没有读取到则等待接收信号量 */
+        while (rt_device_read(serial, -1, &ch, 1) != 1)
+        {
+            /* 阻塞等待接收信号量，等到信号量后再次读取数据 */
+            rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
+        }
+        /* 读取到的数据通过串口错位输出 */
+        ch = ch + 1;
+        rt_device_write(serial, 0, &ch, 1);
+    }
+}
+
+static int uart_sample(int argc, char *argv[])
+{
+    rt_err_t ret = RT_EOK;
+    char uart_name[RT_NAME_MAX];
+    char str[] = "hello RT-Thread!\r\n";
+
+    if (argc == 2)
+    {
+        rt_strncpy(uart_name, argv[1], RT_NAME_MAX);
+    }
+    else
+    {
+        rt_strncpy(uart_name, SAMPLE_UART_NAME, RT_NAME_MAX);
+    }
+
+    /* 查找串口设备 */
+    serial = rt_device_find(uart_name);
+    if (!serial)
+    {
+        rt_kprintf("find %s failed!\n", uart_name);
+        return RT_ERROR;
+    }
+
+    /* 初始化信号量 */
+    rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
+    /* 以中断接收及轮询发送方式打开串口设备 */
+    rt_device_open(serial, RT_DEVICE_FLAG_INT_RX);
+    /* 设置接收回调函数 */
+    rt_device_set_rx_indicate(serial, uart_input);
+    /* 发送字符串 */
+    rt_device_write(serial, 0, str, (sizeof(str) - 1));
+
+    /* 创建 serial 线程 */
+    rt_thread_t thread = rt_thread_create("serial", serial_thread_entry, RT_NULL, 1024, 25, 10);
+    /* 创建成功则启动线程 */
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        ret = RT_ERROR;
+    }
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(uart_sample, uart device sample);

bsp/essemi/es32f0334/drivers/drv_adc.c

@@ -146,9 +146,9 @@ static rt_err_t es32f0_get_adc_value(struct rt_adc_device *device, rt_uint32_t c
     RT_ASSERT(value != RT_NULL);
 
     /* config adc channel */
-    nm_config.channel       = es32f0_adc_get_channel(channel);
-    nm_config.rank          = ADC_NCH_RANK_1;
-    nm_config.samp_time = ADC_SAMPLETIME_4;
+    nm_config.ch       = es32f0_adc_get_channel(channel);
+    nm_config.idx          = ADC_NCH_IDX_1;
+    nm_config.samp = ADC_SAMPLETIME_4;
     ald_adc_normal_channel_config(_hadc, &nm_config);
 
     ald_adc_normal_start(_hadc);
@@ -172,16 +172,16 @@ int rt_hw_adc_init(void)
 
     /* adc function initialization */
     _h_adc0.perh = ADC0;
-    _h_adc0.init.data_align = ADC_DATAALIGN_RIGHT;
-    _h_adc0.init.scan_mode = DISABLE;
-    _h_adc0.init.cont_mode = DISABLE;
-    _h_adc0.init.disc_mode = ADC_ALL_DISABLE;
-    _h_adc0.init.disc_nbr = ADC_DISC_NBR_1;
-    _h_adc0.init.conv_res = ADC_CONV_RES_10;
-    _h_adc0.init.clk_div = ADC_CKDIV_128;
+    _h_adc0.init.align = ADC_DATAALIGN_RIGHT;
+    _h_adc0.init.scan = DISABLE;
+    _h_adc0.init.cont = DISABLE;
+    _h_adc0.init.disc = ADC_ALL_DISABLE;
+    _h_adc0.init.disc_nr = ADC_DISC_NR_1;
+    _h_adc0.init.data_bit = ADC_CONV_BIT_12;
+    _h_adc0.init.div = ADC_CKDIV_128;
     _h_adc0.init.nche_sel = ADC_NCHESEL_MODE_ALL;
-    _h_adc0.init.neg_ref = ADC_NEG_REF_VSS;
-    _h_adc0.init.pos_ref = ADC_POS_REF_VDD;
+    _h_adc0.init.n_ref = ADC_NEG_REF_VSS;
+    _h_adc0.init.p_ref = ADC_POS_REF_VDD;
     ald_adc_init(&_h_adc0);
 
     rt_hw_adc_register(&_device_adc0, "adc0", &es32f0_adc_ops, &_h_adc0);

bsp/essemi/es32f0334/drivers/drv_i2c.c

@@ -7,6 +7,7 @@
  * Date           Author        Notes
  * 2019-03-19     wangyq        the first version
  * 2019-11-01     wangyq        update libraries
+ * 2020-12-15     liuhy         update libraries
  */
 
 #include <rtthread.h>
@@ -29,7 +30,7 @@ static void _i2c_init(void)
 
     /* Initialize I2C Pin */
     gpio_instruct.mode = GPIO_MODE_OUTPUT;
-    gpio_instruct.odos = GPIO_PUSH_PULL;
+    gpio_instruct.odos = GPIO_OPEN_DRAIN;
     gpio_instruct.pupd = GPIO_PUSH_UP;
     gpio_instruct.odrv = GPIO_OUT_DRIVE_NORMAL;
     gpio_instruct.flt  = GPIO_FILTER_DISABLE;

bsp/essemi/es32f0334/drivers/drv_pm.c

@@ -8,7 +8,7 @@
  * 2019-04-08     wangyq        the first version
  * 2019-11-01     wangyq        adapt to the new power management interface
  */
-
+#include <rthw.h>
 #include <board.h>
 #include <rtdevice.h>
 #include <drv_lptim.h>
@@ -24,6 +24,21 @@ static void uart_console_reconfig(void)
     rt_device_control(rt_console_get_device(), RT_DEVICE_CTRL_CONFIG, &config);
 }
 
+static void delay(void)
+{
+    long i;
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+    i = 0;
+    do{
+        i++;
+    }
+    while (i < 10000); 
+    
+    rt_hw_interrupt_enable(level);
+}
+
 /**
  * This function will put ES32F033x into sleep mode.
  *
@@ -50,22 +65,26 @@ static void sleep(struct rt_pm *pm, uint8_t mode)
         {
             /* Enter SLEEP Mode, Main regulator is ON */
             ald_pmu_stop1_enter();
+            delay();
         }
         break;
 
     case PM_SLEEP_MODE_DEEP:
         /* Enter STOP 2 mode  */
         ald_pmu_stop2_enter();
+        delay();
         break;
 
     case PM_SLEEP_MODE_STANDBY:
         /* Enter STANDBY mode */
         ald_pmu_stop2_enter();
+        delay();
         break;
 
     case PM_SLEEP_MODE_SHUTDOWN:
         /* Enter SHUTDOWNN mode */
         ald_pmu_stop2_enter();
+        delay();
         break;
 
     default:

bsp/essemi/es32f0334/drivers/drv_spi.c

@@ -5,8 +5,9 @@
  *
  * Change Logs:
  * Date           Author        Notes
- * 2019-03-19     wangyq        the first version
+ * 2019-01-24     wangyq        the first version
  * 2019-11-01     wangyq        update libraries
+ * 2020-12-15     liuhy         update libraries
  */
 
 #include <rtthread.h>
@@ -146,19 +147,21 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
     RT_ASSERT(device != RT_NULL);
     RT_ASSERT(device->bus != RT_NULL);
     RT_ASSERT(device->bus->parent.user_data != RT_NULL);
-    RT_ASSERT(message->send_buf != RT_NULL || message->recv_buf != RT_NULL);
 
     hspi = (spi_handle_t *)device->bus->parent.user_data;
     cs = device->parent.user_data;
-
-    /* only send data */
-    if (message->recv_buf == RT_NULL)
+    
+    if(message->send_buf != RT_NULL || message->recv_buf != RT_NULL)
+    {
+    /* send & receive */
+    if ((message->send_buf != RT_NULL) && (message->recv_buf != RT_NULL))
     {
         if (message->cs_take)
         {
             rt_pin_write(cs->pin, 0);
         }
-        res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+        res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
+                                (rt_int32_t)message->length, SPITIMEOUT);
         if (message->cs_release)
         {
             rt_pin_write(cs->pin, 1);
@@ -166,41 +169,56 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         if (res != RT_EOK)
             return RT_ERROR;
     }
-
-    /* only receive data */
-    if (message->send_buf == RT_NULL)
+    else
     {
-        if (message->cs_take)
+        /* only send data */
+        if (message->recv_buf == RT_NULL)
         {
-            rt_pin_write(cs->pin, 0);
+            if (message->cs_take)
+            {
+                rt_pin_write(cs->pin, 0);
+            }
+            res = ald_spi_send(hspi, (rt_uint8_t *)message->send_buf, (rt_int32_t)message->length, SPITIMEOUT);
+            if (message->cs_release)
+            {
+                rt_pin_write(cs->pin, 1);
+            }
+            if (res != RT_EOK)
+                return RT_ERROR;
         }
-        res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
-        if (message->cs_release)
+        /* only receive data */
+        if (message->send_buf == RT_NULL)
         {
-            rt_pin_write(cs->pin, 1);
+            if (message->cs_take)
+            {
+                rt_pin_write(cs->pin, 0);
+            }
+            res = ald_spi_recv(hspi, (rt_uint8_t *)message->recv_buf, (rt_int32_t)message->length, SPITIMEOUT);
+            if (message->cs_release)
+            {
+                rt_pin_write(cs->pin, 1);
+            }
+            if (res != RT_EOK)
+                return RT_ERROR;
         }
-        if (res != RT_EOK)
-            return RT_ERROR;
     }
 
-    /* send & receive */
+    }
     else
     {
-        if (message->cs_take)
+         if (message->cs_take)
         {
             rt_pin_write(cs->pin, 0);
         }
-        res = ald_spi_send_recv(hspi, (rt_uint8_t *)message->send_buf, (rt_uint8_t *)message->recv_buf,
-                                (rt_int32_t)message->length, SPITIMEOUT);
+        
         if (message->cs_release)
         {
             rt_pin_write(cs->pin, 1);
         }
-        if (res != RT_EOK)
-            return RT_ERROR;
+            return RT_EOK;
     }
-
     return message->length;
+    
 }
 
 const struct rt_spi_ops es32f0_spi_ops =
@@ -209,21 +227,45 @@ const struct rt_spi_ops es32f0_spi_ops =
     spixfer,
 };
 
-static struct rt_spi_bus _spi_bus0, _spi_bus1;
-static spi_handle_t _spi0, _spi1;
-int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
+
+rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
+{
+    /* define spi Instance */
+    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(spi_device != RT_NULL);
+    struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs));
+    RT_ASSERT(cs_pin != RT_NULL);
+    cs_pin->pin = pin;
+    rt_pin_mode(pin, PIN_MODE_OUTPUT);
+    rt_pin_write(pin, 1);
+    return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+}
+
+#ifdef BSP_USING_SPI0
+    static struct rt_spi_bus _spi_bus0;
+    static spi_handle_t _spi0;
+#endif
+
+#ifdef BSP_USING_SPI1
+    static struct rt_spi_bus _spi_bus1;
+    static spi_handle_t _spi1;
+#endif
+
+int rt_hw_spi_init(void)
 {
+   int result = RT_EOK;
+
     struct rt_spi_bus *spi_bus;
     spi_handle_t *spi;
     gpio_init_t gpio_instruct;
 
-    if (SPIx == SPI0)
-    {
-        _spi0.perh = SPI0;
-        spi_bus = &_spi_bus0;
-        spi = &_spi0;
+#ifdef BSP_USING_SPI0
+    _spi0.perh = SPI0;
+    spi_bus = &_spi_bus0;
+    spi = &_spi0;
+    rt_device_t spi_bus_dev0;
 
-        /* SPI0 gpio init */
+    /* SPI0 gpio init */
         gpio_instruct.mode = GPIO_MODE_OUTPUT;
         gpio_instruct.odos = GPIO_PUSH_PULL;
         gpio_instruct.func = GPIO_FUNC_4;
@@ -236,14 +278,33 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
         /* PB4->SPI0_MISO */
         gpio_instruct.mode = GPIO_MODE_INPUT;
         ald_gpio_init(GPIOB, GPIO_PIN_4, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi0", &es32f0_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
     }
-    else if (SPIx == SPI1)
+    
+    rt_device_register(spi_bus_dev0, "spi00", RT_DEVICE_FLAG_RDWR);
+    
+    /* SPI0_NSS = PA15 = PIN 50 */
+    result = es32f0_spi_device_attach(50, "spi0", "spi00");
+    
+    if (result != RT_EOK)
     {
-        _spi1.perh = SPI1;
-        spi_bus = &_spi_bus1;
-        spi = &_spi1;
+        return result;
+    }
+    
+#endif
 
-        /* SPI1 gpio init */
+#ifdef BSP_USING_SPI1
+    _spi1.perh = SPI1;
+    spi_bus = &_spi_bus1;
+    spi = &_spi1;
+    rt_device_t spi_bus_dev0;
+
+    /* SPI1 gpio init */
         gpio_instruct.mode = GPIO_MODE_OUTPUT;
         gpio_instruct.odos = GPIO_PUSH_PULL;
         gpio_instruct.func = GPIO_FUNC_4;
@@ -256,39 +317,24 @@ int es32f0_spi_register_bus(SPI_TypeDef *SPIx, const char *name)
         /* PB14->SPI1_MISO */
         gpio_instruct.mode = GPIO_MODE_INPUT;
         ald_gpio_init(GPIOB, GPIO_PIN_14, &gpio_instruct);
+
+    spi_bus->parent.user_data = spi;
+    result = rt_spi_bus_register(spi_bus, "spi1", &es32f0_spi_ops);
+    if (result != RT_EOK)
+    {
+        return result;
     }
-    else
+    
+    rt_device_register(spi_bus_dev0, "spi10", RT_DEVICE_FLAG_RDWR);
+    
+    /* SPI1_NSS = PC00 = PIN 8 */
+    result = es32f0_spi_device_attach(8, "spi1", "spi10");
+    
+    if (result != RT_EOK)
     {
-        return -1;
+        return result;
     }
-    spi_bus->parent.user_data = spi;
-
-    return rt_spi_bus_register(spi_bus, name, &es32f0_spi_ops);
-}
-
-rt_err_t es32f0_spi_device_attach(rt_uint32_t pin, const char *bus_name, const char *device_name)
-{
-    /* define spi Instance */
-    struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
-    RT_ASSERT(spi_device != RT_NULL);
-    struct es32f0_hw_spi_cs *cs_pin = (struct es32f0_hw_spi_cs *)rt_malloc(sizeof(struct es32f0_hw_spi_cs));
-    RT_ASSERT(cs_pin != RT_NULL);
-    cs_pin->pin = pin;
-    rt_pin_mode(pin, PIN_MODE_OUTPUT);
-    rt_pin_write(pin, 1);
-    return rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
-}
-
-int rt_hw_spi_init(void)
-{
-    int result = 0;
-
-#ifdef BSP_USING_SPI0
-    result = es32f0_spi_register_bus(SPI0, "spi0");
-#endif
-
-#ifdef BSP_USING_SPI1
-    result = es32f0_spi_register_bus(SPI1, "spi1");
+    
 #endif
 
     return result;

bsp/essemi/es32f0334/libraries/CMSIS/Device/EastSoft/ES32F033x/Include/es32f033x.h

@@ -40,7 +40,7 @@ typedef enum IRQn {
 	/* es32f0xx specific interrupt index */
 	WWDG_IWDG_IRQn                = 0,
 	LVD_IRQn                      = 1,
-	RTC_TSENSE_IRQn                 = 2,
+	RTC_TSENSE_IRQn               = 2,
 	CRYPT_TRNG_IRQn               = 3,
 	CMU_IRQn                      = 4,
 	EXTI0_3_IRQn                  = 5,
@@ -284,21 +284,11 @@ typedef struct
 #define	BKPC_PCCR_RTCCS_POSE	1U 
 #define	BKPC_PCCR_RTCCS_MSK	BITS(BKPC_PCCR_RTCCS_POSS,BKPC_PCCR_RTCCS_POSE)
 
-/****************** Bit definition for BKPC_PCR register ************************/
-
-#define	BKPC_PCR_BORS_POSS	1U 
-#define	BKPC_PCR_BORS_POSE	4U 
-#define	BKPC_PCR_BORS_MSK	BITS(BKPC_PCR_BORS_POSS,BKPC_PCR_BORS_POSE)
-
-#define	BKPC_PCR_BOREN_POS	0U 
-#define	BKPC_PCR_BOREN_MSK	BIT(BKPC_PCR_BOREN_POS)
-
 typedef struct
 {
 	__IO uint32_t PROT;
 	__IO uint32_t CR;
 	__IO uint32_t PCCR;
-	__IO uint32_t PCR;
 } BKPC_TypeDef;
 
 /****************** Bit definition for PMU_CR register ************************/
@@ -1847,18 +1837,18 @@ typedef struct
 #define	RTC_TAMPCON_TAMPTS_POS	16U 
 #define	RTC_TAMPCON_TAMPTS_MSK	BIT(RTC_TAMPCON_TAMPTS_POS)
 
-#define	RTC_TAMPCON_TAMP2LV_POS	9U 
-#define	RTC_TAMPCON_TAMP2LV_MSK	BIT(RTC_TAMPCON_TAMP2LV_POS)
-
-#define	RTC_TAMPCON_TAMP2EN_POS	8U 
-#define	RTC_TAMPCON_TAMP2EN_MSK	BIT(RTC_TAMPCON_TAMP2EN_POS)
-
-#define	RTC_TAMPCON_TAMP1LV_POS	1U 
+#define	RTC_TAMPCON_TAMP1LV_POS	9U 
 #define	RTC_TAMPCON_TAMP1LV_MSK	BIT(RTC_TAMPCON_TAMP1LV_POS)
 
-#define	RTC_TAMPCON_TAMP1EN_POS	0U 
+#define	RTC_TAMPCON_TAMP1EN_POS	8U 
 #define	RTC_TAMPCON_TAMP1EN_MSK	BIT(RTC_TAMPCON_TAMP1EN_POS)
 
+#define	RTC_TAMPCON_TAMP0LV_POS	1U 
+#define	RTC_TAMPCON_TAMP0LV_MSK	BIT(RTC_TAMPCON_TAMP0LV_POS)
+
+#define	RTC_TAMPCON_TAMP0EN_POS	0U 
+#define	RTC_TAMPCON_TAMP0EN_MSK	BIT(RTC_TAMPCON_TAMP0EN_POS)
+
 /****************** Bit definition for RTC_TIME register ************************/
 
 #define	RTC_TIME_PM_POS	22U 
@@ -2151,12 +2141,12 @@ typedef struct
 #define	RTC_IER_RSC_POS	16U 
 #define	RTC_IER_RSC_MSK	BIT(RTC_IER_RSC_POS)
 
-#define	RTC_IER_TAMP2_POS	13U 
-#define	RTC_IER_TAMP2_MSK	BIT(RTC_IER_TAMP2_POS)
-
-#define	RTC_IER_TAMP1_POS	12U 
+#define	RTC_IER_TAMP1_POS	13U 
 #define	RTC_IER_TAMP1_MSK	BIT(RTC_IER_TAMP1_POS)
 
+#define	RTC_IER_TAMP0_POS	12U 
+#define	RTC_IER_TAMP0_MSK	BIT(RTC_IER_TAMP0_POS)
+
 #define	RTC_IER_TSOV_POS	11U 
 #define	RTC_IER_TSOV_MSK	BIT(RTC_IER_TSOV_POS)
 
@@ -2204,12 +2194,12 @@ typedef struct
 #define	RTC_IFR_RSCF_POS	16U 
 #define	RTC_IFR_RSCF_MSK	BIT(RTC_IFR_RSCF_POS)
 
-#define	RTC_IFR_TAMP2F_POS	13U 
-#define	RTC_IFR_TAMP2F_MSK	BIT(RTC_IFR_TAMP2F_POS)
-
-#define	RTC_IFR_TAMP1F_POS	12U 
+#define	RTC_IFR_TAMP1F_POS	13U 
 #define	RTC_IFR_TAMP1F_MSK	BIT(RTC_IFR_TAMP1F_POS)
 
+#define	RTC_IFR_TAMP0F_POS	12U 
+#define	RTC_IFR_TAMP0F_MSK	BIT(RTC_IFR_TAMP0F_POS)
+
 #define	RTC_IFR_TSOVF_POS	11U 
 #define	RTC_IFR_TSOVF_MSK	BIT(RTC_IFR_TSOVF_POS)
 
@@ -2257,17 +2247,17 @@ typedef struct
 #define	RTC_IFCR_RSCFC_POS	16U 
 #define	RTC_IFCR_RSCFC_MSK	BIT(RTC_IFCR_RSCFC_POS)
 
-#define	RTC_IFCR_TAMP2FC_POS	13U 
-#define	RTC_IFCR_TAMP2FC_MSK	BIT(RTC_IFCR_TAMP2FC_POS)
-
-#define	RTC_IFCR_TAMP1FC_POS	12U 
+#define	RTC_IFCR_TAMP1FC_POS	13U 
 #define	RTC_IFCR_TAMP1FC_MSK	BIT(RTC_IFCR_TAMP1FC_POS)
 
+#define	RTC_IFCR_TAMP0FC_POS	12U 
+#define	RTC_IFCR_TAMP0FC_MSK	BIT(RTC_IFCR_TAMP0FC_POS)
+
 #define	RTC_IFCR_TSOVFC_POS	11U 
 #define	RTC_IFCR_TSOVFC_MSK	BIT(RTC_IFCR_TSOVFC_POS)
 
-#define	RTC_IFCR_TSSTC_POS	10U 
-#define	RTC_IFCR_TSSTC_MSK	BIT(RTC_IFCR_TSSTC_POS)
+#define	RTC_IFCR_TSFC_POS	10U 
+#define	RTC_IFCR_TSFC_MSK	BIT(RTC_IFCR_TSFC_POS)
 
 #define	RTC_IFCR_ALMBFC_POS	9U 
 #define	RTC_IFCR_ALMBFC_MSK	BIT(RTC_IFCR_ALMBFC_POS)
@@ -2310,12 +2300,12 @@ typedef struct
 #define	RTC_ISR_RSCF_POS	16U 
 #define	RTC_ISR_RSCF_MSK	BIT(RTC_ISR_RSCF_POS)
 
-#define	RTC_ISR_TAMP2F_POS	13U 
-#define	RTC_ISR_TAMP2F_MSK	BIT(RTC_ISR_TAMP2F_POS)
-
-#define	RTC_ISR_TAMP1F_POS	12U 
+#define	RTC_ISR_TAMP1F_POS	13U 
 #define	RTC_ISR_TAMP1F_MSK	BIT(RTC_ISR_TAMP1F_POS)
 
+#define	RTC_ISR_TAMP0F_POS	12U 
+#define	RTC_ISR_TAMP0F_MSK	BIT(RTC_ISR_TAMP0F_POS)
+
 #define	RTC_ISR_TSOVF_POS	11U 
 #define	RTC_ISR_TSOVF_MSK	BIT(RTC_ISR_TSOVF_POS)
 
@@ -4361,736 +4351,6 @@ typedef struct
 	__IO uint32_t RT;
 } I2C_TypeDef;
 
-/****************** Bit definition for CAN_CON register ************************/
-
-#define	CAN_CON_DBGSTP_POS	16U 
-#define	CAN_CON_DBGSTP_MSK	BIT(CAN_CON_DBGSTP_POS)
-
-#define	CAN_CON_RST_POS	15U 
-#define	CAN_CON_RST_MSK	BIT(CAN_CON_RST_POS)
-
-#define	CAN_CON_TTCEN_POS	7U 
-#define	CAN_CON_TTCEN_MSK	BIT(CAN_CON_TTCEN_POS)
-
-#define	CAN_CON_ABOFFEN_POS	6U 
-#define	CAN_CON_ABOFFEN_MSK	BIT(CAN_CON_ABOFFEN_POS)
-
-#define	CAN_CON_AWKEN_POS	5U 
-#define	CAN_CON_AWKEN_MSK	BIT(CAN_CON_AWKEN_POS)
-
-#define	CAN_CON_ARTXDIS_POS	4U 
-#define	CAN_CON_ARTXDIS_MSK	BIT(CAN_CON_ARTXDIS_POS)
-
-#define	CAN_CON_RXFOPM_POS	3U 
-#define	CAN_CON_RXFOPM_MSK	BIT(CAN_CON_RXFOPM_POS)
-
-#define	CAN_CON_TXMP_POS	2U 
-#define	CAN_CON_TXMP_MSK	BIT(CAN_CON_TXMP_POS)
-
-#define	CAN_CON_SLPREQ_POS	1U 
-#define	CAN_CON_SLPREQ_MSK	BIT(CAN_CON_SLPREQ_POS)
-
-#define	CAN_CON_INIREQ_POS	0U 
-#define	CAN_CON_INIREQ_MSK	BIT(CAN_CON_INIREQ_POS)
-
-/****************** Bit definition for CAN_STAT register ************************/
-
-#define	CAN_STAT_RX_POS	11U 
-#define	CAN_STAT_RX_MSK	BIT(CAN_STAT_RX_POS)
-
-#define	CAN_STAT_PRESMP_POS	10U 
-#define	CAN_STAT_PRESMP_MSK	BIT(CAN_STAT_PRESMP_POS)
-
-#define	CAN_STAT_RXSTAT_POS	9U 
-#define	CAN_STAT_RXSTAT_MSK	BIT(CAN_STAT_RXSTAT_POS)
-
-#define	CAN_STAT_TXSTAT_POS	8U 
-#define	CAN_STAT_TXSTAT_MSK	BIT(CAN_STAT_TXSTAT_POS)
-
-#define	CAN_STAT_SLPIF_POS	4U 
-#define	CAN_STAT_SLPIF_MSK	BIT(CAN_STAT_SLPIF_POS)
-
-#define	CAN_STAT_WKIF_POS	3U 
-#define	CAN_STAT_WKIF_MSK	BIT(CAN_STAT_WKIF_POS)
-
-#define	CAN_STAT_ERRIF_POS	2U 
-#define	CAN_STAT_ERRIF_MSK	BIT(CAN_STAT_ERRIF_POS)
-
-#define	CAN_STAT_SLPSTAT_POS	1U 
-#define	CAN_STAT_SLPSTAT_MSK	BIT(CAN_STAT_SLPSTAT_POS)
-
-#define	CAN_STAT_INISTAT_POS	0U 
-#define	CAN_STAT_INISTAT_MSK	BIT(CAN_STAT_INISTAT_POS)
-
-/****************** Bit definition for CAN_IFC register ************************/
-
-#define	CAN_IFC_SLPIFC_POS	4U 
-#define	CAN_IFC_SLPIFC_MSK	BIT(CAN_IFC_SLPIFC_POS)
-
-#define	CAN_IFC_WKIFC_POS	3U 
-#define	CAN_IFC_WKIFC_MSK	BIT(CAN_IFC_WKIFC_POS)
-
-#define	CAN_IFC_ERRIFC_POS	2U 
-#define	CAN_IFC_ERRIFC_MSK	BIT(CAN_IFC_ERRIFC_POS)
-
-/****************** Bit definition for CAN_TXSTAT register ************************/
-
-#define	CAN_TXSTAT_TXM2LPF_POS	31U 
-#define	CAN_TXSTAT_TXM2LPF_MSK	BIT(CAN_TXSTAT_TXM2LPF_POS)
-
-#define	CAN_TXSTAT_TXM1LPF_POS	30U 
-#define	CAN_TXSTAT_TXM1LPF_MSK	BIT(CAN_TXSTAT_TXM1LPF_POS)
-
-#define	CAN_TXSTAT_TXM0LPF_POS	29U 
-#define	CAN_TXSTAT_TXM0LPF_MSK	BIT(CAN_TXSTAT_TXM0LPF_POS)
-
-#define	CAN_TXSTAT_TXM2EF_POS	28U 
-#define	CAN_TXSTAT_TXM2EF_MSK	BIT(CAN_TXSTAT_TXM2EF_POS)
-
-#define	CAN_TXSTAT_TXM1EF_POS	27U 
-#define	CAN_TXSTAT_TXM1EF_MSK	BIT(CAN_TXSTAT_TXM1EF_POS)
-
-#define	CAN_TXSTAT_TXM0EF_POS	26U 
-#define	CAN_TXSTAT_TXM0EF_MSK	BIT(CAN_TXSTAT_TXM0EF_POS)
-
-#define	CAN_TXSTAT_CODE_POSS	24U 
-#define	CAN_TXSTAT_CODE_POSE	25U 
-#define	CAN_TXSTAT_CODE_MSK	BITS(CAN_TXSTAT_CODE_POSS,CAN_TXSTAT_CODE_POSE)
-
-#define	CAN_TXSTAT_M2STPREQ_POS	23U 
-#define	CAN_TXSTAT_M2STPREQ_MSK	BIT(CAN_TXSTAT_M2STPREQ_POS)
-
-#define	CAN_TXSTAT_M2TXERR_POS	19U 
-#define	CAN_TXSTAT_M2TXERR_MSK	BIT(CAN_TXSTAT_M2TXERR_POS)
-
-#define	CAN_TXSTAT_M2ARBLST_POS	18U 
-#define	CAN_TXSTAT_M2ARBLST_MSK	BIT(CAN_TXSTAT_M2ARBLST_POS)
-
-#define	CAN_TXSTAT_M2TXC_POS	17U 
-#define	CAN_TXSTAT_M2TXC_MSK	BIT(CAN_TXSTAT_M2TXC_POS)
-
-#define	CAN_TXSTAT_M2REQC_POS	16U 
-#define	CAN_TXSTAT_M2REQC_MSK	BIT(CAN_TXSTAT_M2REQC_POS)
-
-#define	CAN_TXSTAT_M1STPREQ_POS	15U 
-#define	CAN_TXSTAT_M1STPREQ_MSK	BIT(CAN_TXSTAT_M1STPREQ_POS)
-
-#define	CAN_TXSTAT_M1TXERR_POS	11U 
-#define	CAN_TXSTAT_M1TXERR_MSK	BIT(CAN_TXSTAT_M1TXERR_POS)
-
-#define	CAN_TXSTAT_M1ARBLST_POS	10U 
-#define	CAN_TXSTAT_M1ARBLST_MSK	BIT(CAN_TXSTAT_M1ARBLST_POS)
-
-#define	CAN_TXSTAT_M1TXC_POS	9U 
-#define	CAN_TXSTAT_M1TXC_MSK	BIT(CAN_TXSTAT_M1TXC_POS)
-
-#define	CAN_TXSTAT_M1REQC_POS	8U 
-#define	CAN_TXSTAT_M1REQC_MSK	BIT(CAN_TXSTAT_M1REQC_POS)
-
-#define	CAN_TXSTAT_M0STPREQ_POS	7U 
-#define	CAN_TXSTAT_M0STPREQ_MSK	BIT(CAN_TXSTAT_M0STPREQ_POS)
-
-#define	CAN_TXSTAT_M0TXERR_POS	3U 
-#define	CAN_TXSTAT_M0TXERR_MSK	BIT(CAN_TXSTAT_M0TXERR_POS)
-
-#define	CAN_TXSTAT_M0ARBLST_POS	2U 
-#define	CAN_TXSTAT_M0ARBLST_MSK	BIT(CAN_TXSTAT_M0ARBLST_POS)
-
-#define	CAN_TXSTAT_M0TXC_POS	1U 
-#define	CAN_TXSTAT_M0TXC_MSK	BIT(CAN_TXSTAT_M0TXC_POS)
-
-#define	CAN_TXSTAT_M0REQC_POS	0U 
-#define	CAN_TXSTAT_M0REQC_MSK	BIT(CAN_TXSTAT_M0REQC_POS)
-
-/****************** Bit definition for CAN_TXSTATC register ************************/
-
-#define	CAN_TXSTATC_M2TXERR_POS	19U 
-#define	CAN_TXSTATC_M2TXERR_MSK	BIT(CAN_TXSTATC_M2TXERR_POS)
-
-#define	CAN_TXSTATC_M2ARBLST_POS	18U 
-#define	CAN_TXSTATC_M2ARBLST_MSK	BIT(CAN_TXSTATC_M2ARBLST_POS)
-
-#define	CAN_TXSTATC_M2TXC_POS	17U 
-#define	CAN_TXSTATC_M2TXC_MSK	BIT(CAN_TXSTATC_M2TXC_POS)
-
-#define	CAN_TXSTATC_M2REQC_POS	16U 
-#define	CAN_TXSTATC_M2REQC_MSK	BIT(CAN_TXSTATC_M2REQC_POS)
-
-#define	CAN_TXSTATC_M1TXERR_POS	11U 
-#define	CAN_TXSTATC_M1TXERR_MSK	BIT(CAN_TXSTATC_M1TXERR_POS)
-
-#define	CAN_TXSTATC_M1ARBLST_POS	10U 
-#define	CAN_TXSTATC_M1ARBLST_MSK	BIT(CAN_TXSTATC_M1ARBLST_POS)
-
-#define	CAN_TXSTATC_M1TXC_POS	9U 
-#define	CAN_TXSTATC_M1TXC_MSK	BIT(CAN_TXSTATC_M1TXC_POS)
-
-#define	CAN_TXSTATC_M1REQC_POS	8U 
-#define	CAN_TXSTATC_M1REQC_MSK	BIT(CAN_TXSTATC_M1REQC_POS)
-
-#define	CAN_TXSTATC_M0TXERR_POS	3U 
-#define	CAN_TXSTATC_M0TXERR_MSK	BIT(CAN_TXSTATC_M0TXERR_POS)
-
-#define	CAN_TXSTATC_M0ARBLST_POS	2U 
-#define	CAN_TXSTATC_M0ARBLST_MSK	BIT(CAN_TXSTATC_M0ARBLST_POS)
-
-#define	CAN_TXSTATC_M0TXC_POS	1U 
-#define	CAN_TXSTATC_M0TXC_MSK	BIT(CAN_TXSTATC_M0TXC_POS)
-
-#define	CAN_TXSTATC_M0REQC_POS	0U 
-#define	CAN_TXSTATC_M0REQC_MSK	BIT(CAN_TXSTATC_M0REQC_POS)
-
-/****************** Bit definition for CAN_RXF0 register ************************/
-
-#define	CAN_RXF0_FREE_POS	5U 
-#define	CAN_RXF0_FREE_MSK	BIT(CAN_RXF0_FREE_POS)
-
-#define	CAN_RXF0_OVR_POS	4U 
-#define	CAN_RXF0_OVR_MSK	BIT(CAN_RXF0_OVR_POS)
-
-#define	CAN_RXF0_FULL_POS	3U 
-#define	CAN_RXF0_FULL_MSK	BIT(CAN_RXF0_FULL_POS)
-
-#define	CAN_RXF0_PEND_POSS	0U 
-#define	CAN_RXF0_PEND_POSE	1U 
-#define	CAN_RXF0_PEND_MSK	BITS(CAN_RXF0_PEND_POSS,CAN_RXF0_PEND_POSE)
-
-/****************** Bit definition for CAN_RXF0C register ************************/
-
-#define	CAN_RXF0C_OVRC_POS	4U 
-#define	CAN_RXF0C_OVRC_MSK	BIT(CAN_RXF0C_OVRC_POS)
-
-#define	CAN_RXF0C_FULLC_POS	3U 
-#define	CAN_RXF0C_FULLC_MSK	BIT(CAN_RXF0C_FULLC_POS)
-
-/****************** Bit definition for CAN_RXF1 register ************************/
-
-#define	CAN_RXF1_FREE_POS	5U 
-#define	CAN_RXF1_FREE_MSK	BIT(CAN_RXF1_FREE_POS)
-
-#define	CAN_RXF1_OVR_POS	4U 
-#define	CAN_RXF1_OVR_MSK	BIT(CAN_RXF1_OVR_POS)
-
-#define	CAN_RXF1_FULL_POS	3U 
-#define	CAN_RXF1_FULL_MSK	BIT(CAN_RXF1_FULL_POS)
-
-#define	CAN_RXF1_PEND_POSS	0U 
-#define	CAN_RXF1_PEND_POSE	1U 
-#define	CAN_RXF1_PEND_MSK	BITS(CAN_RXF1_PEND_POSS,CAN_RXF1_PEND_POSE)
-
-/****************** Bit definition for CAN_RXF1C register ************************/
-
-#define	CAN_RXF1C_OVRC_POS	4U 
-#define	CAN_RXF1C_OVRC_MSK	BIT(CAN_RXF1C_OVRC_POS)
-
-#define	CAN_RXF1C_FULLC_POS	3U 
-#define	CAN_RXF1C_FULLC_MSK	BIT(CAN_RXF1C_FULLC_POS)
-
-/****************** Bit definition for CAN_IE register ************************/
-
-#define	CAN_IE_SLPIE_POS	17U 
-#define	CAN_IE_SLPIE_MSK	BIT(CAN_IE_SLPIE_POS)
-
-#define	CAN_IE_WKIE_POS	16U 
-#define	CAN_IE_WKIE_MSK	BIT(CAN_IE_WKIE_POS)
-
-#define	CAN_IE_ERRIE_POS	15U 
-#define	CAN_IE_ERRIE_MSK	BIT(CAN_IE_ERRIE_POS)
-
-#define	CAN_IE_PRERRIE_POS	11U 
-#define	CAN_IE_PRERRIE_MSK	BIT(CAN_IE_PRERRIE_POS)
-
-#define	CAN_IE_BOFFIE_POS	10U 
-#define	CAN_IE_BOFFIE_MSK	BIT(CAN_IE_BOFFIE_POS)
-
-#define	CAN_IE_PERRIE_POS	9U 
-#define	CAN_IE_PERRIE_MSK	BIT(CAN_IE_PERRIE_POS)
-
-#define	CAN_IE_WARNIE_POS	8U 
-#define	CAN_IE_WARNIE_MSK	BIT(CAN_IE_WARNIE_POS)
-
-#define	CAN_IE_F1OVRIE_POS	6U 
-#define	CAN_IE_F1OVRIE_MSK	BIT(CAN_IE_F1OVRIE_POS)
-
-#define	CAN_IE_F1FULIE_POS	5U 
-#define	CAN_IE_F1FULIE_MSK	BIT(CAN_IE_F1FULIE_POS)
-
-#define	CAN_IE_F1PIE_POS	4U 
-#define	CAN_IE_F1PIE_MSK	BIT(CAN_IE_F1PIE_POS)
-
-#define	CAN_IE_F0OVRIE_POS	3U 
-#define	CAN_IE_F0OVRIE_MSK	BIT(CAN_IE_F0OVRIE_POS)
-
-#define	CAN_IE_F0FULIE_POS	2U 
-#define	CAN_IE_F0FULIE_MSK	BIT(CAN_IE_F0FULIE_POS)
-
-#define	CAN_IE_F0PIE_POS	1U 
-#define	CAN_IE_F0PIE_MSK	BIT(CAN_IE_F0PIE_POS)
-
-#define	CAN_IE_TXMEIE_POS	0U 
-#define	CAN_IE_TXMEIE_MSK	BIT(CAN_IE_TXMEIE_POS)
-
-/****************** Bit definition for CAN_ERRSTAT register ************************/
-
-#define	CAN_ERRSTAT_RXERRC_POSS	24U 
-#define	CAN_ERRSTAT_RXERRC_POSE	31U 
-#define	CAN_ERRSTAT_RXERRC_MSK	BITS(CAN_ERRSTAT_RXERRC_POSS,CAN_ERRSTAT_RXERRC_POSE)
-
-#define	CAN_ERRSTAT_TXERRC_POSS	16U 
-#define	CAN_ERRSTAT_TXERRC_POSE	23U 
-#define	CAN_ERRSTAT_TXERRC_MSK	BITS(CAN_ERRSTAT_TXERRC_POSS,CAN_ERRSTAT_TXERRC_POSE)
-
-#define	CAN_ERRSTAT_PRERRF_POSS	4U 
-#define	CAN_ERRSTAT_PRERRF_POSE	6U 
-#define	CAN_ERRSTAT_PRERRF_MSK	BITS(CAN_ERRSTAT_PRERRF_POSS,CAN_ERRSTAT_PRERRF_POSE)
-
-#define	CAN_ERRSTAT_BOFF_POS	2U 
-#define	CAN_ERRSTAT_BOFF_MSK	BIT(CAN_ERRSTAT_BOFF_POS)
-
-#define	CAN_ERRSTAT_PERRF_POS	1U 
-#define	CAN_ERRSTAT_PERRF_MSK	BIT(CAN_ERRSTAT_PERRF_POS)
-
-#define	CAN_ERRSTAT_WARNF_POS	0U 
-#define	CAN_ERRSTAT_WARNF_MSK	BIT(CAN_ERRSTAT_WARNF_POS)
-
-/****************** Bit definition for CAN_BTIME register ************************/
-
-#define	CAN_BTIME_SILENT_POS	31U 
-#define	CAN_BTIME_SILENT_MSK	BIT(CAN_BTIME_SILENT_POS)
-
-#define	CAN_BTIME_LOOP_POS	30U 
-#define	CAN_BTIME_LOOP_MSK	BIT(CAN_BTIME_LOOP_POS)
-
-#define	CAN_BTIME_RESJW_POSS	24U 
-#define	CAN_BTIME_RESJW_POSE	25U 
-#define	CAN_BTIME_RESJW_MSK	BITS(CAN_BTIME_RESJW_POSS,CAN_BTIME_RESJW_POSE)
-
-#define	CAN_BTIME_SEG2_POSS	20U 
-#define	CAN_BTIME_SEG2_POSE	22U 
-#define	CAN_BTIME_SEG2_MSK	BITS(CAN_BTIME_SEG2_POSS,CAN_BTIME_SEG2_POSE)
-
-#define	CAN_BTIME_SEG1_POSS	16U 
-#define	CAN_BTIME_SEG1_POSE	19U 
-#define	CAN_BTIME_SEG1_MSK	BITS(CAN_BTIME_SEG1_POSS,CAN_BTIME_SEG1_POSE)
-
-#define	CAN_BTIME_BPSC_POSS	0U 
-#define	CAN_BTIME_BPSC_POSE	9U 
-#define	CAN_BTIME_BPSC_MSK	BITS(CAN_BTIME_BPSC_POSS,CAN_BTIME_BPSC_POSE)
-
-/****************** Bit definition for CAN_TXID0 register ************************/
-
-#define	CAN_TXID0_STDID_POSS	21U 
-#define	CAN_TXID0_STDID_POSE	31U 
-#define	CAN_TXID0_STDID_MSK	BITS(CAN_TXID0_STDID_POSS,CAN_TXID0_STDID_POSE)
-
-#define	CAN_TXID0_EXID_POSS	3U 
-#define	CAN_TXID0_EXID_POSE	20U 
-#define	CAN_TXID0_EXID_MSK	BITS(CAN_TXID0_EXID_POSS,CAN_TXID0_EXID_POSE)
-
-#define	CAN_TXID0_IDE_POS	2U 
-#define	CAN_TXID0_IDE_MSK	BIT(CAN_TXID0_IDE_POS)
-
-#define	CAN_TXID0_RTR_POS	1U 
-#define	CAN_TXID0_RTR_MSK	BIT(CAN_TXID0_RTR_POS)
-
-#define	CAN_TXID0_TXMREQ_POS	0U 
-#define	CAN_TXID0_TXMREQ_MSK	BIT(CAN_TXID0_TXMREQ_POS)
-
-/****************** Bit definition for CAN_TXFCON0 register ************************/
-
-#define	CAN_TXFCON0_STAMP_POSS	16U 
-#define	CAN_TXFCON0_STAMP_POSE	31U 
-#define	CAN_TXFCON0_STAMP_MSK	BITS(CAN_TXFCON0_STAMP_POSS,CAN_TXFCON0_STAMP_POSE)
-
-#define	CAN_TXFCON0_TXGT_POS	8U 
-#define	CAN_TXFCON0_TXGT_MSK	BIT(CAN_TXFCON0_TXGT_POS)
-
-#define	CAN_TXFCON0_DLEN_POSS	0U 
-#define	CAN_TXFCON0_DLEN_POSE	3U 
-#define	CAN_TXFCON0_DLEN_MSK	BITS(CAN_TXFCON0_DLEN_POSS,CAN_TXFCON0_DLEN_POSE)
-
-/****************** Bit definition for CAN_TXDL0 register ************************/
-
-#define	CAN_TXDL0_BYTE3_POSS	24U 
-#define	CAN_TXDL0_BYTE3_POSE	31U 
-#define	CAN_TXDL0_BYTE3_MSK	BITS(CAN_TXDL0_BYTE3_POSS,CAN_TXDL0_BYTE3_POSE)
-
-#define	CAN_TXDL0_BYTE2_POSS	16U 
-#define	CAN_TXDL0_BYTE2_POSE	23U 
-#define	CAN_TXDL0_BYTE2_MSK	BITS(CAN_TXDL0_BYTE2_POSS,CAN_TXDL0_BYTE2_POSE)
-
-#define	CAN_TXDL0_BYTE1_POSS	8U 
-#define	CAN_TXDL0_BYTE1_POSE	15U 
-#define	CAN_TXDL0_BYTE1_MSK	BITS(CAN_TXDL0_BYTE1_POSS,CAN_TXDL0_BYTE1_POSE)
-
-#define	CAN_TXDL0_BYTE0_POSS	0U 
-#define	CAN_TXDL0_BYTE0_POSE	7U 
-#define	CAN_TXDL0_BYTE0_MSK	BITS(CAN_TXDL0_BYTE0_POSS,CAN_TXDL0_BYTE0_POSE)
-
-/****************** Bit definition for CAN_TXDH0 register ************************/
-
-#define	CAN_TXDH0_BYTE7_POSS	24U 
-#define	CAN_TXDH0_BYTE7_POSE	31U 
-#define	CAN_TXDH0_BYTE7_MSK	BITS(CAN_TXDH0_BYTE7_POSS,CAN_TXDH0_BYTE7_POSE)
-
-#define	CAN_TXDH0_BYTE6_POSS	16U 
-#define	CAN_TXDH0_BYTE6_POSE	23U 
-#define	CAN_TXDH0_BYTE6_MSK	BITS(CAN_TXDH0_BYTE6_POSS,CAN_TXDH0_BYTE6_POSE)
-
-#define	CAN_TXDH0_BYTE5_POSS	8U 
-#define	CAN_TXDH0_BYTE5_POSE	15U 
-#define	CAN_TXDH0_BYTE5_MSK	BITS(CAN_TXDH0_BYTE5_POSS,CAN_TXDH0_BYTE5_POSE)
-
-#define	CAN_TXDH0_BYTE4_POSS	0U 
-#define	CAN_TXDH0_BYTE4_POSE	7U 
-#define	CAN_TXDH0_BYTE4_MSK	BITS(CAN_TXDH0_BYTE4_POSS,CAN_TXDH0_BYTE4_POSE)
-
-/****************** Bit definition for CAN_TXID1 register ************************/
-
-#define	CAN_TXID1_STDID_POSS	21U 
-#define	CAN_TXID1_STDID_POSE	31U 
-#define	CAN_TXID1_STDID_MSK	BITS(CAN_TXID1_STDID_POSS,CAN_TXID1_STDID_POSE)
-
-#define	CAN_TXID1_EXID_POSS	3U 
-#define	CAN_TXID1_EXID_POSE	20U 
-#define	CAN_TXID1_EXID_MSK	BITS(CAN_TXID1_EXID_POSS,CAN_TXID1_EXID_POSE)
-
-#define	CAN_TXID1_IDE_POS	2U 
-#define	CAN_TXID1_IDE_MSK	BIT(CAN_TXID1_IDE_POS)
-
-#define	CAN_TXID1_RTR_POS	1U 
-#define	CAN_TXID1_RTR_MSK	BIT(CAN_TXID1_RTR_POS)
-
-#define	CAN_TXID1_TXMREQ_POS	0U 
-#define	CAN_TXID1_TXMREQ_MSK	BIT(CAN_TXID1_TXMREQ_POS)
-
-/****************** Bit definition for CAN_TXFCON1 register ************************/
-
-#define	CAN_TXFCON1_STAMP_POSS	16U 
-#define	CAN_TXFCON1_STAMP_POSE	31U 
-#define	CAN_TXFCON1_STAMP_MSK	BITS(CAN_TXFCON1_STAMP_POSS,CAN_TXFCON1_STAMP_POSE)
-
-#define	CAN_TXFCON1_TXGT_POS	8U 
-#define	CAN_TXFCON1_TXGT_MSK	BIT(CAN_TXFCON1_TXGT_POS)
-
-#define	CAN_TXFCON1_DLEN_POSS	0U 
-#define	CAN_TXFCON1_DLEN_POSE	3U 
-#define	CAN_TXFCON1_DLEN_MSK	BITS(CAN_TXFCON1_DLEN_POSS,CAN_TXFCON1_DLEN_POSE)
-
-/****************** Bit definition for CAN_TXDL1 register ************************/
-
-#define	CAN_TXDL1_BYTE3_POSS	24U 
-#define	CAN_TXDL1_BYTE3_POSE	31U 
-#define	CAN_TXDL1_BYTE3_MSK	BITS(CAN_TXDL1_BYTE3_POSS,CAN_TXDL1_BYTE3_POSE)
-
-#define	CAN_TXDL1_BYTE2_POSS	16U 
-#define	CAN_TXDL1_BYTE2_POSE	23U 
-#define	CAN_TXDL1_BYTE2_MSK	BITS(CAN_TXDL1_BYTE2_POSS,CAN_TXDL1_BYTE2_POSE)
-
-#define	CAN_TXDL1_BYTE1_POSS	8U 
-#define	CAN_TXDL1_BYTE1_POSE	15U 
-#define	CAN_TXDL1_BYTE1_MSK	BITS(CAN_TXDL1_BYTE1_POSS,CAN_TXDL1_BYTE1_POSE)
-
-#define	CAN_TXDL1_BYTE0_POSS	0U 
-#define	CAN_TXDL1_BYTE0_POSE	7U 
-#define	CAN_TXDL1_BYTE0_MSK	BITS(CAN_TXDL1_BYTE0_POSS,CAN_TXDL1_BYTE0_POSE)
-
-/****************** Bit definition for CAN_TXDH1 register ************************/
-
-#define	CAN_TXDH1_BYTE7_POSS	24U 
-#define	CAN_TXDH1_BYTE7_POSE	31U 
-#define	CAN_TXDH1_BYTE7_MSK	BITS(CAN_TXDH1_BYTE7_POSS,CAN_TXDH1_BYTE7_POSE)
-
-#define	CAN_TXDH1_BYTE6_POSS	16U 
-#define	CAN_TXDH1_BYTE6_POSE	23U 
-#define	CAN_TXDH1_BYTE6_MSK	BITS(CAN_TXDH1_BYTE6_POSS,CAN_TXDH1_BYTE6_POSE)
-
-#define	CAN_TXDH1_BYTE5_POSS	8U 
-#define	CAN_TXDH1_BYTE5_POSE	15U 
-#define	CAN_TXDH1_BYTE5_MSK	BITS(CAN_TXDH1_BYTE5_POSS,CAN_TXDH1_BYTE5_POSE)
-
-#define	CAN_TXDH1_BYTE4_POSS	0U 
-#define	CAN_TXDH1_BYTE4_POSE	7U 
-#define	CAN_TXDH1_BYTE4_MSK	BITS(CAN_TXDH1_BYTE4_POSS,CAN_TXDH1_BYTE4_POSE)
-
-/****************** Bit definition for CAN_TXID2 register ************************/
-
-#define	CAN_TXID2_STDID_POSS	21U 
-#define	CAN_TXID2_STDID_POSE	31U 
-#define	CAN_TXID2_STDID_MSK	BITS(CAN_TXID2_STDID_POSS,CAN_TXID2_STDID_POSE)
-
-#define	CAN_TXID2_EXID_POSS	3U 
-#define	CAN_TXID2_EXID_POSE	20U 
-#define	CAN_TXID2_EXID_MSK	BITS(CAN_TXID2_EXID_POSS,CAN_TXID2_EXID_POSE)
-
-#define	CAN_TXID2_IDE_POS	2U 
-#define	CAN_TXID2_IDE_MSK	BIT(CAN_TXID2_IDE_POS)
-
-#define	CAN_TXID2_RTR_POS	1U 
-#define	CAN_TXID2_RTR_MSK	BIT(CAN_TXID2_RTR_POS)
-
-#define	CAN_TXID2_TXMREQ_POS	0U 
-#define	CAN_TXID2_TXMREQ_MSK	BIT(CAN_TXID2_TXMREQ_POS)
-
-/****************** Bit definition for CAN_TXFCON2 register ************************/
-
-#define	CAN_TXFCON2_STAMP_POSS	16U 
-#define	CAN_TXFCON2_STAMP_POSE	31U 
-#define	CAN_TXFCON2_STAMP_MSK	BITS(CAN_TXFCON2_STAMP_POSS,CAN_TXFCON2_STAMP_POSE)
-
-#define	CAN_TXFCON2_TXGT_POS	8U 
-#define	CAN_TXFCON2_TXGT_MSK	BIT(CAN_TXFCON2_TXGT_POS)
-
-#define	CAN_TXFCON2_DLEN_POSS	0U 
-#define	CAN_TXFCON2_DLEN_POSE	3U 
-#define	CAN_TXFCON2_DLEN_MSK	BITS(CAN_TXFCON2_DLEN_POSS,CAN_TXFCON2_DLEN_POSE)
-
-/****************** Bit definition for CAN_TXDL2 register ************************/
-
-#define	CAN_TXDL2_BYTE3_POSS	24U 
-#define	CAN_TXDL2_BYTE3_POSE	31U 
-#define	CAN_TXDL2_BYTE3_MSK	BITS(CAN_TXDL2_BYTE3_POSS,CAN_TXDL2_BYTE3_POSE)
-
-#define	CAN_TXDL2_BYTE2_POSS	16U 
-#define	CAN_TXDL2_BYTE2_POSE	23U 
-#define	CAN_TXDL2_BYTE2_MSK	BITS(CAN_TXDL2_BYTE2_POSS,CAN_TXDL2_BYTE2_POSE)
-
-#define	CAN_TXDL2_BYTE1_POSS	8U 
-#define	CAN_TXDL2_BYTE1_POSE	15U 
-#define	CAN_TXDL2_BYTE1_MSK	BITS(CAN_TXDL2_BYTE1_POSS,CAN_TXDL2_BYTE1_POSE)
-
-#define	CAN_TXDL2_BYTE0_POSS	0U 
-#define	CAN_TXDL2_BYTE0_POSE	7U 
-#define	CAN_TXDL2_BYTE0_MSK	BITS(CAN_TXDL2_BYTE0_POSS,CAN_TXDL2_BYTE0_POSE)
-
-/****************** Bit definition for CAN_TXDH2 register ************************/
-
-#define	CAN_TXDH2_BYTE7_POSS	24U 
-#define	CAN_TXDH2_BYTE7_POSE	31U 
-#define	CAN_TXDH2_BYTE7_MSK	BITS(CAN_TXDH2_BYTE7_POSS,CAN_TXDH2_BYTE7_POSE)
-
-#define	CAN_TXDH2_BYTE6_POSS	16U 
-#define	CAN_TXDH2_BYTE6_POSE	23U 
-#define	CAN_TXDH2_BYTE6_MSK	BITS(CAN_TXDH2_BYTE6_POSS,CAN_TXDH2_BYTE6_POSE)
-
-#define	CAN_TXDH2_BYTE5_POSS	8U 
-#define	CAN_TXDH2_BYTE5_POSE	15U 
-#define	CAN_TXDH2_BYTE5_MSK	BITS(CAN_TXDH2_BYTE5_POSS,CAN_TXDH2_BYTE5_POSE)
-
-#define	CAN_TXDH2_BYTE4_POSS	0U 
-#define	CAN_TXDH2_BYTE4_POSE	7U 
-#define	CAN_TXDH2_BYTE4_MSK	BITS(CAN_TXDH2_BYTE4_POSS,CAN_TXDH2_BYTE4_POSE)
-
-/****************** Bit definition for CAN_RXF0ID register ************************/
-
-#define	CAN_RXF0ID_STDID_POSS	21U 
-#define	CAN_RXF0ID_STDID_POSE	31U 
-#define	CAN_RXF0ID_STDID_MSK	BITS(CAN_RXF0ID_STDID_POSS,CAN_RXF0ID_STDID_POSE)
-
-#define	CAN_RXF0ID_EXID_POSS	3U 
-#define	CAN_RXF0ID_EXID_POSE	20U 
-#define	CAN_RXF0ID_EXID_MSK	BITS(CAN_RXF0ID_EXID_POSS,CAN_RXF0ID_EXID_POSE)
-
-#define	CAN_RXF0ID_IDE_POS	2U 
-#define	CAN_RXF0ID_IDE_MSK	BIT(CAN_RXF0ID_IDE_POS)
-
-#define	CAN_RXF0ID_RTR_POS	1U 
-#define	CAN_RXF0ID_RTR_MSK	BIT(CAN_RXF0ID_RTR_POS)
-
-/****************** Bit definition for CAN_RXF0INF register ************************/
-
-#define	CAN_RXF0INF_STAMP_POSS	16U 
-#define	CAN_RXF0INF_STAMP_POSE	31U 
-#define	CAN_RXF0INF_STAMP_MSK	BITS(CAN_RXF0INF_STAMP_POSS,CAN_RXF0INF_STAMP_POSE)
-
-#define	CAN_RXF0INF_FLTIDX_POSS	8U 
-#define	CAN_RXF0INF_FLTIDX_POSE	15U 
-#define	CAN_RXF0INF_FLTIDX_MSK	BITS(CAN_RXF0INF_FLTIDX_POSS,CAN_RXF0INF_FLTIDX_POSE)
-
-#define	CAN_RXF0INF_DLEN_POSS	0U 
-#define	CAN_RXF0INF_DLEN_POSE	3U 
-#define	CAN_RXF0INF_DLEN_MSK	BITS(CAN_RXF0INF_DLEN_POSS,CAN_RXF0INF_DLEN_POSE)
-
-/****************** Bit definition for CAN_RXF0DL register ************************/
-
-#define	CAN_RXF0DL_BYTE3_POSS	24U 
-#define	CAN_RXF0DL_BYTE3_POSE	31U 
-#define	CAN_RXF0DL_BYTE3_MSK	BITS(CAN_RXF0DL_BYTE3_POSS,CAN_RXF0DL_BYTE3_POSE)
-
-#define	CAN_RXF0DL_BYTE2_POSS	16U 
-#define	CAN_RXF0DL_BYTE2_POSE	23U 
-#define	CAN_RXF0DL_BYTE2_MSK	BITS(CAN_RXF0DL_BYTE2_POSS,CAN_RXF0DL_BYTE2_POSE)
-
-#define	CAN_RXF0DL_BYTE1_POSS	8U 
-#define	CAN_RXF0DL_BYTE1_POSE	15U 
-#define	CAN_RXF0DL_BYTE1_MSK	BITS(CAN_RXF0DL_BYTE1_POSS,CAN_RXF0DL_BYTE1_POSE)
-
-#define	CAN_RXF0DL_BYTE0_POSS	0U 
-#define	CAN_RXF0DL_BYTE0_POSE	7U 
-#define	CAN_RXF0DL_BYTE0_MSK	BITS(CAN_RXF0DL_BYTE0_POSS,CAN_RXF0DL_BYTE0_POSE)
-
-/****************** Bit definition for CAN_RXF0DH register ************************/
-
-#define	CAN_RXF0DH_BYTE7_POSS	24U 
-#define	CAN_RXF0DH_BYTE7_POSE	31U 
-#define	CAN_RXF0DH_BYTE7_MSK	BITS(CAN_RXF0DH_BYTE7_POSS,CAN_RXF0DH_BYTE7_POSE)
-
-#define	CAN_RXF0DH_BYTE6_POSS	16U 
-#define	CAN_RXF0DH_BYTE6_POSE	23U 
-#define	CAN_RXF0DH_BYTE6_MSK	BITS(CAN_RXF0DH_BYTE6_POSS,CAN_RXF0DH_BYTE6_POSE)
-
-#define	CAN_RXF0DH_BYTE5_POSS	8U 
-#define	CAN_RXF0DH_BYTE5_POSE	15U 
-#define	CAN_RXF0DH_BYTE5_MSK	BITS(CAN_RXF0DH_BYTE5_POSS,CAN_RXF0DH_BYTE5_POSE)
-
-#define	CAN_RXF0DH_BYTE4_POSS	0U 
-#define	CAN_RXF0DH_BYTE4_POSE	7U 
-#define	CAN_RXF0DH_BYTE4_MSK	BITS(CAN_RXF0DH_BYTE4_POSS,CAN_RXF0DH_BYTE4_POSE)
-
-/****************** Bit definition for CAN_RXF1ID register ************************/
-
-#define	CAN_RXF1ID_STDID_POSS	21U 
-#define	CAN_RXF1ID_STDID_POSE	31U 
-#define	CAN_RXF1ID_STDID_MSK	BITS(CAN_RXF1ID_STDID_POSS,CAN_RXF1ID_STDID_POSE)
-
-#define	CAN_RXF1ID_EXID_POSS	3U 
-#define	CAN_RXF1ID_EXID_POSE	20U 
-#define	CAN_RXF1ID_EXID_MSK	BITS(CAN_RXF1ID_EXID_POSS,CAN_RXF1ID_EXID_POSE)
-
-#define	CAN_RXF1ID_IDE_POS	2U 
-#define	CAN_RXF1ID_IDE_MSK	BIT(CAN_RXF1ID_IDE_POS)
-
-#define	CAN_RXF1ID_RTR_POS	1U 
-#define	CAN_RXF1ID_RTR_MSK	BIT(CAN_RXF1ID_RTR_POS)
-
-/****************** Bit definition for CAN_RXF1INF register ************************/
-
-#define	CAN_RXF1INF_STAMP_POSS	16U 
-#define	CAN_RXF1INF_STAMP_POSE	31U 
-#define	CAN_RXF1INF_STAMP_MSK	BITS(CAN_RXF1INF_STAMP_POSS,CAN_RXF1INF_STAMP_POSE)
-
-#define	CAN_RXF1INF_FLTIDX_POSS	8U 
-#define	CAN_RXF1INF_FLTIDX_POSE	15U 
-#define	CAN_RXF1INF_FLTIDX_MSK	BITS(CAN_RXF1INF_FLTIDX_POSS,CAN_RXF1INF_FLTIDX_POSE)
-
-#define	CAN_RXF1INF_DLEN_POSS	0U 
-#define	CAN_RXF1INF_DLEN_POSE	3U 
-#define	CAN_RXF1INF_DLEN_MSK	BITS(CAN_RXF1INF_DLEN_POSS,CAN_RXF1INF_DLEN_POSE)
-
-/****************** Bit definition for CAN_RXF1DL register ************************/
-
-#define	CAN_RXF1DL_BYTE3_POSS	24U 
-#define	CAN_RXF1DL_BYTE3_POSE	31U 
-#define	CAN_RXF1DL_BYTE3_MSK	BITS(CAN_RXF1DL_BYTE3_POSS,CAN_RXF1DL_BYTE3_POSE)
-
-#define	CAN_RXF1DL_BYTE2_POSS	16U 
-#define	CAN_RXF1DL_BYTE2_POSE	23U 
-#define	CAN_RXF1DL_BYTE2_MSK	BITS(CAN_RXF1DL_BYTE2_POSS,CAN_RXF1DL_BYTE2_POSE)
-
-#define	CAN_RXF1DL_BYTE1_POSS	8U 
-#define	CAN_RXF1DL_BYTE1_POSE	15U 
-#define	CAN_RXF1DL_BYTE1_MSK	BITS(CAN_RXF1DL_BYTE1_POSS,CAN_RXF1DL_BYTE1_POSE)
-
-#define	CAN_RXF1DL_BYTE0_POSS	0U 
-#define	CAN_RXF1DL_BYTE0_POSE	7U 
-#define	CAN_RXF1DL_BYTE0_MSK	BITS(CAN_RXF1DL_BYTE0_POSS,CAN_RXF1DL_BYTE0_POSE)
-
-/****************** Bit definition for CAN_RXF1DH register ************************/
-
-#define	CAN_RXF1DH_BYTE7_POSS	24U 
-#define	CAN_RXF1DH_BYTE7_POSE	31U 
-#define	CAN_RXF1DH_BYTE7_MSK	BITS(CAN_RXF1DH_BYTE7_POSS,CAN_RXF1DH_BYTE7_POSE)
-
-#define	CAN_RXF1DH_BYTE6_POSS	16U 
-#define	CAN_RXF1DH_BYTE6_POSE	23U 
-#define	CAN_RXF1DH_BYTE6_MSK	BITS(CAN_RXF1DH_BYTE6_POSS,CAN_RXF1DH_BYTE6_POSE)
-
-#define	CAN_RXF1DH_BYTE5_POSS	8U 
-#define	CAN_RXF1DH_BYTE5_POSE	15U 
-#define	CAN_RXF1DH_BYTE5_MSK	BITS(CAN_RXF1DH_BYTE5_POSS,CAN_RXF1DH_BYTE5_POSE)
-
-#define	CAN_RXF1DH_BYTE4_POSS	0U 
-#define	CAN_RXF1DH_BYTE4_POSE	7U 
-#define	CAN_RXF1DH_BYTE4_MSK	BITS(CAN_RXF1DH_BYTE4_POSS,CAN_RXF1DH_BYTE4_POSE)
-
-/****************** Bit definition for CAN_FLTCON register ************************/
-
-#define	CAN_FLTCON_FLTINI_POS	0U 
-#define	CAN_FLTCON_FLTINI_MSK	BIT(CAN_FLTCON_FLTINI_POS)
-
-/****************** Bit definition for CAN_FLTM register ************************/
-
-#define	CAN_FLTM_MOD_POSS	0U 
-#define	CAN_FLTM_MOD_POSE	13U 
-#define	CAN_FLTM_MOD_MSK	BITS(CAN_FLTM_MOD_POSS,CAN_FLTM_MOD_POSE)
-
-/****************** Bit definition for CAN_FLTWS register ************************/
-
-#define	CAN_FLTWS_SEL_POSS	0U 
-#define	CAN_FLTWS_SEL_POSE	13U 
-#define	CAN_FLTWS_SEL_MSK	BITS(CAN_FLTWS_SEL_POSS,CAN_FLTWS_SEL_POSE)
-
-/****************** Bit definition for CAN_FLTAS register ************************/
-
-#define	CAN_FLTAS_ASSIGN_POSS	0U 
-#define	CAN_FLTAS_ASSIGN_POSE	13U 
-#define	CAN_FLTAS_ASSIGN_MSK	BITS(CAN_FLTAS_ASSIGN_POSS,CAN_FLTAS_ASSIGN_POSE)
-
-/****************** Bit definition for CAN_FLTGO register ************************/
-
-#define	CAN_FLTGO_GO_POSS	0U 
-#define	CAN_FLTGO_GO_POSE	13U 
-#define	CAN_FLTGO_GO_MSK	BITS(CAN_FLTGO_GO_POSS,CAN_FLTGO_GO_POSE)
-
-typedef struct {
-	__IO uint32_t TXID;
-	__IO uint32_t TXFCON;
-	__IO uint32_t TXDL;
-	__IO uint32_t TXDH;
-} CAN_TxMailBox_Typedef;
-
-typedef struct {
-	__IO uint32_t RXFID;
-	__IO uint32_t RXFINF;
-	__IO uint32_t RXFDL;
-	__IO uint32_t RXFDH;
-} CAN_RxFIFO_Typedef;
-
-typedef struct {
-	__IO uint32_t FLT1;
-	__IO uint32_t FLT2;
-} CAN_Filter_Typedef;
-
-typedef struct
-{
-	__IO uint32_t CON;
-	__I uint32_t STAT;
-	__O uint32_t IFC;
-	__IO uint32_t TXSTAT;
-	__O uint32_t TXSTATC;
-	__IO uint32_t RXF0;
-	__O uint32_t RXF0C;
-	__IO uint32_t RXF1;
-	__O uint32_t RXF1C;
-	__IO uint32_t IE;
-	__IO uint32_t ERRSTAT;
-	__IO uint32_t BTIME;
-	uint32_t RESERVED0[84] ;
-	CAN_TxMailBox_Typedef TxMailBox[3];
-	CAN_RxFIFO_Typedef RxFIFO[2];
-	uint32_t RESERVED1[12] ;
-	__IO uint32_t FLTCON;
-	__IO uint32_t FLTM;
-	uint32_t RESERVED2 ;
-	__IO uint32_t FLTWS;
-	uint32_t RESERVED3 ;
-	__IO uint32_t FLTAS;
-	uint32_t RESERVED4 ;
-	__IO uint32_t FLTGO;
-	uint32_t RESERVED5[8] ;
-	CAN_Filter_Typedef Filter[14];
-} CAN_TypeDef;
-
 /****************** Bit definition for CRC_CR register ************************/
 #define	CRC_CR_BYTORD_POS	24U 
 #define	CRC_CR_BYTORD_MSK	BIT(CRC_CR_BYTORD_POS)
@@ -6523,20 +5783,16 @@ typedef struct
 #define USART1_BASE	(APB1_BASE + 0x5400)
 #define SPI0_BASE	(APB1_BASE + 0x6000)
 #define SPI1_BASE	(APB1_BASE + 0x6400)
-#define SPI2_BASE	(APB1_BASE + 0x6800)
 #define I2C0_BASE	(APB1_BASE + 0x8000)
 #define I2C1_BASE	(APB1_BASE + 0x8400)
-#define CAN0_BASE	(APB1_BASE + 0xB000)
 #define DMA0_BASE    	(APB1_BASE + 0xC000)
 
 /* APB2 peripherals Base Address */
 #define LPTIM0_BASE	(APB2_BASE + 0x0000)
 #define LPUART0_BASE	(APB2_BASE + 0x1000)
 #define ADC0_BASE	(APB2_BASE + 0x2000)
-#define ADC1_BASE	(APB2_BASE + 0x2400)
 #define ACMP0_BASE	(APB2_BASE + 0x3000)
 #define ACMP1_BASE	(APB2_BASE + 0x3400)
-#define OPAMP_BASE	(APB2_BASE + 0x4000)
 #define DAC0_BASE	(APB2_BASE + 0x5000)
 #define WWDT_BASE	(APB2_BASE + 0x6000)
 #define IWDT_BASE	(APB2_BASE + 0x6400)
@@ -6584,21 +5840,16 @@ typedef struct
 #define USART1		((USART_TypeDef *)USART1_BASE)
 #define SPI0		((SPI_TypeDef *)SPI0_BASE)
 #define SPI1		((SPI_TypeDef *)SPI1_BASE)
-#define SPI2		((SPI_TypeDef *)SPI2_BASE)
 #define I2C0		((I2C_TypeDef *)I2C0_BASE)
 #define I2C1		((I2C_TypeDef *)I2C1_BASE)
-#define CAN0		((CAN_TypeDef *)CAN0_BASE)
 #define DMA0		((DMA_TypeDef *)DMA0_BASE)
 
 /* APB2 peripherals */
 #define LPTIM0		((LPTIM_TypeDef *)LPTIM0_BASE)
 #define LPUART0		((LPUART_TypeDef *)LPUART0_BASE)
 #define ADC0		((ADC_TypeDef *)ADC0_BASE)
-#define ADC1		((ADC_TypeDef *)ADC1_BASE)
 #define ACMP0		((ACMP_TypeDef *)ACMP0_BASE)
 #define ACMP1		((ACMP_TypeDef *)ACMP1_BASE)
-#define OPAMP		((OPAMP_TypeDef *)OPAMP_BASE)
-#define DAC0		((DAC_TypeDef *)DAC0_BASE)
 #define WWDT		((WWDT_TypeDef *)WWDT_BASE)
 #define IWDT		((IWDT_TypeDef *)IWDT_BASE)
 #define LCD     	((LCD_TypeDef *)LCD_BASE)

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_acmp.h

@@ -18,7 +18,7 @@
 #define __ALD_ACMP_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -38,187 +38,171 @@ extern "C" {
 /**
   * @brief Acmp interrupt
   */
-typedef enum
-{
-    ACMP_IT_EDGE   = (1U << 0),	/**< Edge interrupt bit */
-    ACMP_IT_WARMUP = (1U << 1),	/**< Warm up interrupt bit */
+typedef enum {
+	ACMP_IT_EDGE   = (1U << 0),	/**< Edge interrupt bit */
+	ACMP_IT_WARMUP = (1U << 1),	/**< Warm up interrupt bit */
 } acmp_it_t;
 
 /**
   * @brief Acmp interrupt
   */
-typedef enum
-{
-    ACMP_FLAG_EDGE   = (1U << 0),	/**< Edge interrupt flag */
-    ACMP_FLAG_WARMUP = (1U << 1),	/**< Warm up interrupt flag */
+typedef enum {
+	ACMP_FLAG_EDGE   = (1U << 0),	/**< Edge interrupt flag */
+	ACMP_FLAG_WARMUP = (1U << 1),	/**< Warm up interrupt flag */	
 } acmp_flag_t;
 
 /**
   * @brief Acmp interrupt flag
   */
-typedef enum
-{
-    ACMP_STATUS_EDGE    = (1U << 0),	/**< Edge interrupt flag */
-    ACMP_STATUS_WARMUP  = (1U << 1),	/**< Warm up interrupt flag */
+typedef enum {
+	ACMP_STATUS_EDGE    = (1U << 0),	/**< Edge interrupt flag */
+	ACMP_STATUS_WARMUP  = (1U << 1),	/**< Warm up interrupt flag */
 } acmp_status_t;
 
 /**
   * @brief Acmp positive input
   */
-typedef enum
-{
-    ACMP_POS_CH0 = 0,	/**< Channel 0 as positive input */
-    ACMP_POS_CH1 = 1,	/**< Channel 1 as positive input */
-    ACMP_POS_CH2 = 2,	/**< Channel 2 as positive input */
-    ACMP_POS_CH3 = 3,	/**< Channel 3 as positive input */
-    ACMP_POS_CH4 = 4,	/**< Channel 4 as positive input */
-    ACMP_POS_CH5 = 5,	/**< Channel 5 as positive input */
-    ACMP_POS_CH6 = 6,	/**< Channel 6 as positive input */
-    ACMP_POS_CH7 = 7,	/**< Channel 7 as positive input */
+typedef enum {
+	ACMP_POS_CH0 = 0U,	/**< Channel 0 as positive input */
+	ACMP_POS_CH1 = 1U,	/**< Channel 1 as positive input */
+	ACMP_POS_CH2 = 2U,	/**< Channel 2 as positive input */
+	ACMP_POS_CH3 = 3U,	/**< Channel 3 as positive input */
+	ACMP_POS_CH4 = 4U,	/**< Channel 4 as positive input */
+	ACMP_POS_CH5 = 5U,	/**< Channel 5 as positive input */
+	ACMP_POS_CH6 = 6U,	/**< Channel 6 as positive input */
+	ACMP_POS_CH7 = 7U,	/**< Channel 7 as positive input */
 } acmp_pos_input_t;
 
 /**
   * @brief Acmp negative input
   */
-typedef enum
-{
-    ACMP_NEG_CH0      = 0, 	/**< Channel 0 as negative input */
-    ACMP_NEG_CH1      = 1, 	/**< Channel 1 as negative input */
-    ACMP_NEG_CH2      = 2, 	/**< Channel 2 as negative input */
-    ACMP_NEG_CH3      = 3, 	/**< Channel 3 as negative input */
-    ACMP_NEG_CH4      = 4, 	/**< Channel 4 as negative input */
-    ACMP_NEG_CH5      = 5, 	/**< Channel 5 as negative input */
-    ACMP_NEG_CH6      = 6, 	/**< Channel 6 as negative input */
-    ACMP_NEG_CH7      = 7, 	/**< Channel 7 as negative input */
-    ACMP_NEG_1V25     = 8, 	/**< 1.25v as negative input */
-    ACMP_NEG_2V5      = 9, 	/**< 2.5v as negative input */
-    ACMP_NEG_VDD      = 10,	/**< VDD as negative input */
+typedef enum {
+	ACMP_NEG_CH0  = 0U, 	/**< Channel 0 as negative input */
+	ACMP_NEG_CH1  = 1U, 	/**< Channel 1 as negative input */
+	ACMP_NEG_CH2  = 2U, 	/**< Channel 2 as negative input */
+	ACMP_NEG_CH3  = 3U, 	/**< Channel 3 as negative input */
+	ACMP_NEG_CH4  = 4U, 	/**< Channel 4 as negative input */
+	ACMP_NEG_CH5  = 5U, 	/**< Channel 5 as negative input */
+	ACMP_NEG_CH6  = 6U, 	/**< Channel 6 as negative input */
+	ACMP_NEG_CH7  = 7U, 	/**< Channel 7 as negative input */
+	ACMP_NEG_1V25 = 8U, 	/**< 1.25v as negative input */
+	ACMP_NEG_2V5  = 9U, 	/**< 2.5v as negative input */
+	ACMP_NEG_VDD  = 10U,	/**< VDD as negative input */
 } acmp_neg_input_t;
 
 /**
   * @brief Acmp mode
   */
-typedef enum
-{
-    ACMP_ULTRA_LOW_POWER = 0,	/**< Ultra low power mode */
-    ACMP_LOW_POWER       = 1,	/**< Low power mode */
-    ACMP_MIDDLE_POWER    = 2,	/**< Middle power mode */
-    ACMP_HIGH_POWER      = 3,	/**< High power mode */
+typedef enum {
+	ACMP_ULTRA_LOW_POWER = 0U,	/**< Ultra low power mode */
+	ACMP_LOW_POWER       = 1U,	/**< Low power mode */
+	ACMP_MIDDLE_POWER    = 2U,	/**< Middle power mode */
+	ACMP_HIGH_POWER      = 3U,	/**< High power mode */
 } acmp_mode_t;
 
 /**
   * @brief Acmp warm-up time
   */
-typedef enum
-{
-    ACMP_4_PCLK   = 0,	/**< 4 hfperclk cycles */
-    ACMP_8_PCLK   = 1,	/**< 4 hfperclk cycles */
-    ACMP_16_PCLK  = 2,	/**< 4 hfperclk cycles */
-    ACMP_32_PCLK  = 3,	/**< 4 hfperclk cycles */
-    ACMP_64_PCLK  = 4,	/**< 4 hfperclk cycles */
-    ACMP_128_PCLK = 5,	/**< 4 hfperclk cycles */
-    ACMP_256_PCLK = 6,	/**< 4 hfperclk cycles */
-    ACMP_512_PCLK = 7,	/**< 4 hfperclk cycles */
+typedef enum {
+	ACMP_4_PCLK   = 0U,	/**< 4 hfperclk cycles */
+	ACMP_8_PCLK   = 1U,	/**< 4 hfperclk cycles */
+	ACMP_16_PCLK  = 2U,	/**< 4 hfperclk cycles */
+	ACMP_32_PCLK  = 3U,	/**< 4 hfperclk cycles */
+	ACMP_64_PCLK  = 4U,	/**< 4 hfperclk cycles */
+	ACMP_128_PCLK = 5U,	/**< 4 hfperclk cycles */
+	ACMP_256_PCLK = 6U,	/**< 4 hfperclk cycles */
+	ACMP_512_PCLK = 7U,	/**< 4 hfperclk cycles */
 } acmp_warm_time_t;
 
 /**
   * @brief Acmp hysteresis level
   */
-typedef enum
-{
-    ACMP_HYST_0  = 0,	/**< No hysteresis */
-    ACMP_HYST_15 = 1,	/**< 15mV hysteresis */
-    ACMP_HYST_22 = 2,	/**< 22mV hysteresis */
-    ACMP_HYST_29 = 3,	/**< 29mV hysteresis */
-    ACMP_HYST_36 = 4,	/**< 36mV hysteresis */
-    ACMP_HYST_43 = 5,	/**< 43mV hysteresis */
-    ACMP_HYST_50 = 6,	/**< 50mV hysteresis */
-    ACMP_HYST_57 = 7,	/**< 57mV hysteresis */
+typedef enum {
+	ACMP_HYST_0  = 0U,	/**< No hysteresis */
+	ACMP_HYST_15 = 1U,	/**< 15mV hysteresis */
+	ACMP_HYST_22 = 2U,	/**< 22mV hysteresis */
+	ACMP_HYST_29 = 3U,	/**< 29mV hysteresis */
+	ACMP_HYST_36 = 4U,	/**< 36mV hysteresis */
+	ACMP_HYST_43 = 5U,	/**< 43mV hysteresis */
+	ACMP_HYST_50 = 6U,	/**< 50mV hysteresis */
+	ACMP_HYST_57 = 7U,	/**< 57mV hysteresis */
 } acmp_hystsel_t;
 
 /**
   * @brief Acmp inactive state
   */
-typedef enum
-{
-    ACMP_INACTVAL_LOW  = 0,	/**< The inactive value is 0 */
-    ACMP_INACTVAL_HIGH = 1,	/**< The inactive value is 1 */
+typedef enum {
+	ACMP_INACTVAL_LOW  = 0U,	/**< The inactive value is 0 */
+	ACMP_INACTVAL_HIGH = 1U,	/**< The inactive value is 1 */
 } acmp_inactval_t;
 
 /**
   * @brief which edges set up interrupt
   */
-typedef enum
-{
-    ACMP_EDGE_NONE = 0,	/**< Disable EDGE interrupt */
-    ACMP_EDGE_FALL = 1,	/**< Falling edges set EDGE interrupt */
-    ACMP_EDGE_RISE = 2,	/**< rise edges set EDGE interrupt */
-    ACMP_EDGE_ALL  = 3,	/**< Falling edges and rise edges set EDGE interrupt */
+typedef enum {
+	ACMP_EDGE_NONE = 0U,	/**< Disable EDGE interrupt */
+	ACMP_EDGE_FALL = 1U,	/**< Falling edges set EDGE interrupt */
+	ACMP_EDGE_RISE = 2U,	/**< rise edges set EDGE interrupt */
+	ACMP_EDGE_ALL  = 3U,	/**< Falling edges and rise edges set EDGE interrupt */
 } acmp_edge_t;
 
 /**
   * @brief Acmp output function
   */
-typedef enum
-{
-    ACMP_OUT_DISABLE = 0,	/**< Disable acmp output */
-    ACMP_OUT_ENABLE  = 1,	/**< Enable acmp output */
+typedef enum {
+	ACMP_OUT_DISABLE = 0U,	/**< Disable acmp output */
+	ACMP_OUT_ENABLE  = 1U,	/**< Enable acmp output */
 } acmp_out_func_t;
 
 /**
   * @brief Acmp warm-up interrupt function
   */
-typedef enum
-{
-    ACMP_WARM_DISABLE = 0,	/**< Disable acmp warm-up interrupt */
-    ACMP_WARM_ENABLE  = 1,	/**< Enable acmp warm-up interrupt */
+typedef enum {
+	ACMP_WARM_DISABLE = 0U,	/**< Disable acmp warm-up interrupt */
+	ACMP_WARM_ENABLE  = 1U,	/**< Enable acmp warm-up interrupt */
 } acmp_warm_it_func;
 
 /**
   * @brief Acmp gpio output invert
   */
-typedef enum
-{
-    ACMP_GPIO_NO_INV = 0,	/**< Acmp output to gpio is not inverted */
-    ACMP_GPIO_INV    = 1,	/**< Acmp output to gpio is inverted */
+typedef enum {
+	ACMP_GPIO_NO_INV = 0U,	/**< Acmp output to gpio is not inverted */
+	ACMP_GPIO_INV    = 1U,	/**< Acmp output to gpio is inverted */
 } acmp_invert_t;
 
 /**
   * @brief Acmp output config structure definition
   */
-typedef struct
-{
-    acmp_out_func_t out_func;	/**< Acmp output function */
-    acmp_invert_t gpio_inv;   	/**< If invert gpio output */
+typedef struct {
+	acmp_out_func_t out_func;	/**< Acmp output function */
+	acmp_invert_t gpio_inv;   	/**< If invert gpio output */
 } acmp_output_config_t;
 
 /**
   * @brief Acmp init structure definition
   */
-typedef struct
-{
-    acmp_mode_t mode;           	/**< Acmp operation mode */
-    acmp_warm_time_t warm_time; 	/**< Acmp warm up time */
-    acmp_hystsel_t hystsel;     	/**< Acmp hysteresis level */
-    acmp_warm_it_func warm_func;	/**< Acmp warm-up interrupt enable/disable */
-    acmp_pos_input_t pos_port;  	/**< Acmp positive port select */
-    acmp_neg_input_t neg_port;  	/**< Acmp negative port select */
-    acmp_inactval_t inactval;   	/**< Acmp inavtive output value */
-    acmp_edge_t edge;           	/** Select edges to set interrupt flag */
-    uint8_t vdd_level;          	/** Select scaling factor for CDD reference level, MAX is 63 */
+typedef struct {
+	acmp_mode_t mode;           	/**< Acmp operation mode */
+	acmp_warm_time_t warm_time; 	/**< Acmp warm up time */
+	acmp_hystsel_t hystsel;     	/**< Acmp hysteresis level */
+	acmp_warm_it_func warm_func;	/**< Acmp warm-up interrupt enable/disable */
+	acmp_pos_input_t pos_port;  	/**< Acmp positive port select */
+	acmp_neg_input_t neg_port;  	/**< Acmp negative port select */
+	acmp_inactval_t inactval;   	/**< Acmp inavtive output value */
+	acmp_edge_t edge;           	/** Select edges to set interrupt flag */
+	uint8_t vdd_level;          	/** Select scaling factor for CDD reference level, MAX is 63 */
 } acmp_init_t;
 
 /**
   * @brief  ACMP Handle Structure definition
   */
-typedef struct acmp_handle_s
-{
-    ACMP_TypeDef *perh;	/**< Register base address */
-    acmp_init_t init;  	/**< ACMP required parameters */
-    lock_state_t lock; 	/**< Locking object */
+typedef struct acmp_handle_s {
+	ACMP_TypeDef *perh;	/**< Register base address */
+	acmp_init_t init;  	/**< ACMP required parameters */
+	lock_state_t lock; 	/**< Locking object */
 
-    void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg);	/**< Acmp warm-up complete callback */
-    void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg);  	/**< Acmp edge trigger callback */
+	void (*acmp_warmup_cplt_cbk)(struct acmp_handle_s *arg);	/**< Acmp warm-up complete callback */
+	void (*acmp_edge_cplt_cbk)(struct acmp_handle_s *arg);  	/**< Acmp edge trigger callback */
 } acmp_handle_t;
 /**
   * @}
@@ -237,64 +221,64 @@ typedef struct acmp_handle_s
   * @{
   */
 #define IS_ACMP_TYPE(x) 		(((x) == ACMP0) || \
-                                 ((x) == ACMP1))
+				         ((x) == ACMP1))
 #define IS_ACMP_MODE_TYPE(x)		(((x) == ACMP_ULTRA_LOW_POWER) || \
-                                     ((x) == ACMP_LOW_POWER)       || \
-                                     ((x) == ACMP_MIDDLE_POWER)    || \
-                                     ((x) == ACMP_HIGH_POWER))
+					 ((x) == ACMP_LOW_POWER)       || \
+					 ((x) == ACMP_MIDDLE_POWER)    || \
+					 ((x) == ACMP_HIGH_POWER))
 #define IS_ACMP_IT_TYPE(x) 		(((x) == ACMP_IT_EDGE)  || \
-                                 ((x) == ACMP_IT_WARMUP))
+				         ((x) == ACMP_IT_WARMUP))
 #define IS_ACMP_FLAG_TYPE(x) 		(((x) == ACMP_FLAG_EDGE)  || \
-                                     ((x) == ACMP_FLAG_WARMUP))
+				         ((x) == ACMP_FLAG_WARMUP))
 #define IS_ACMP_STATUS_TYPE(x) 	        (((x) == ACMP_STATUS_EDGE)  || \
-        ((x) == ACMP_STATUS_WARMUP))
+				         ((x) == ACMP_STATUS_WARMUP))
 #define IS_ACMP_POS_INPUT_TYPE(x) 	(((x) == ACMP_POS_CH0) || \
-                                     ((x) == ACMP_POS_CH1) || \
-                                     ((x) == ACMP_POS_CH2) || \
-                                     ((x) == ACMP_POS_CH3) || \
-                                     ((x) == ACMP_POS_CH4) || \
-                                     ((x) == ACMP_POS_CH5) || \
-                                     ((x) == ACMP_POS_CH6) || \
-                                     ((x) == ACMP_POS_CH7))
+				         ((x) == ACMP_POS_CH1) || \
+				         ((x) == ACMP_POS_CH2) || \
+				         ((x) == ACMP_POS_CH3) || \
+				         ((x) == ACMP_POS_CH4) || \
+				         ((x) == ACMP_POS_CH5) || \
+				         ((x) == ACMP_POS_CH6) || \
+				         ((x) == ACMP_POS_CH7))
 #define IS_ACMP_NEG_INPUT_TYPE(x) 	(((x) == ACMP_NEG_CH0)      || \
-                                     ((x) == ACMP_NEG_CH1)      || \
-                                     ((x) == ACMP_NEG_CH2)      || \
-                                     ((x) == ACMP_NEG_CH3)      || \
-                                     ((x) == ACMP_NEG_CH4)      || \
-                                     ((x) == ACMP_NEG_CH5)      || \
-                                     ((x) == ACMP_NEG_CH6)      || \
-                                     ((x) == ACMP_NEG_CH7)      || \
-                                     ((x) == ACMP_NEG_1V25)     || \
-                                     ((x) == ACMP_NEG_2V5)      || \
-                                     ((x) == ACMP_NEG_VDD))
+				         ((x) == ACMP_NEG_CH1)      || \
+				         ((x) == ACMP_NEG_CH2)      || \
+				         ((x) == ACMP_NEG_CH3)      || \
+				         ((x) == ACMP_NEG_CH4)      || \
+				         ((x) == ACMP_NEG_CH5)      || \
+				         ((x) == ACMP_NEG_CH6)      || \
+				         ((x) == ACMP_NEG_CH7)      || \
+				         ((x) == ACMP_NEG_1V25)     || \
+				         ((x) == ACMP_NEG_2V5)      || \
+				         ((x) == ACMP_NEG_VDD))
 #define IS_ACMP_WARM_UP_TIME_TYPE(x)    (((x) == ACMP_4_PCLK)   || \
-        ((x) == ACMP_8_PCLK)   || \
-        ((x) == ACMP_16_PCLK)  || \
-        ((x) == ACMP_32_PCLK)  || \
-        ((x) == ACMP_64_PCLK)  || \
-        ((x) == ACMP_128_PCLK) || \
-        ((x) == ACMP_256_PCLK) || \
-        ((x) == ACMP_512_PCLK))
+				         ((x) == ACMP_8_PCLK)   || \
+				         ((x) == ACMP_16_PCLK)  || \
+				         ((x) == ACMP_32_PCLK)  || \
+				         ((x) == ACMP_64_PCLK)  || \
+				         ((x) == ACMP_128_PCLK) || \
+				         ((x) == ACMP_256_PCLK) || \
+				         ((x) == ACMP_512_PCLK))
 #define IS_ACMP_HYSTSEL_TYPE(x)         (((x) == ACMP_HYST_0)  || \
-        ((x) == ACMP_HYST_15) || \
-        ((x) == ACMP_HYST_22) || \
-        ((x) == ACMP_HYST_29) || \
-        ((x) == ACMP_HYST_36) || \
-        ((x) == ACMP_HYST_43) || \
-        ((x) == ACMP_HYST_50) || \
-        ((x) == ACMP_HYST_57))
+				         ((x) == ACMP_HYST_15) || \
+				         ((x) == ACMP_HYST_22) || \
+				         ((x) == ACMP_HYST_29) || \
+				         ((x) == ACMP_HYST_36) || \
+				         ((x) == ACMP_HYST_43) || \
+				         ((x) == ACMP_HYST_50) || \
+				         ((x) == ACMP_HYST_57))
 #define IS_ACMP_INACTVAL_TYPE(x) 	(((x) == ACMP_INACTVAL_LOW) || \
-                                     ((x) == ACMP_INACTVAL_HIGH))
+				         ((x) == ACMP_INACTVAL_HIGH))
 #define IS_ACMP_EDGE_TYPE(x) 	        (((x) == ACMP_EDGE_NONE) || \
-        ((x) == ACMP_EDGE_FALL) || \
-        ((x) == ACMP_EDGE_RISE) || \
-        ((x) == ACMP_EDGE_ALL))
+					 ((x) == ACMP_EDGE_FALL) || \
+				         ((x) == ACMP_EDGE_RISE) || \
+					 ((x) == ACMP_EDGE_ALL))
 #define IS_ACMP_OUT_FUNC_TYPE(x)	(((x) == ACMP_OUT_DISABLE) || \
-                                     ((x) == ACMP_OUT_ENABLE))
+					 ((x) == ACMP_OUT_ENABLE))
 #define IS_ACMP_INVERT_TYPE(x)		(((x) == ACMP_GPIO_NO_INV) || \
-                                     ((x) == ACMP_GPIO_INV))
+					 ((x) == ACMP_GPIO_INV))
 #define IS_ACMP_WARM_FUNC_TYPE(x)	(((x) == ACMP_WARM_DISABLE) || \
-                                     ((x) == ACMP_WARM_ENABLE))
+					 ((x) == ACMP_WARM_ENABLE))
 /**
   * @}
   */
@@ -348,8 +332,7 @@ uint8_t ald_acmp_out_result(acmp_handle_t *hperh);
   * @}
   */
 #ifdef __cplusplus
-extern "C"
-}
+ extern "C" }
 #endif
 
 #endif

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_adc.h

@@ -17,7 +17,7 @@
 #define __ALD_ADC_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -40,368 +40,342 @@ extern "C" {
 /**
   * @brief ADC  State structures definition
   */
-typedef enum
-{
-    ADC_STATE_RESET         = 0x0,    	/**< ADC not yet initialized or disabled */
-    ADC_STATE_READY         = 0x1,    	/**< ADC peripheral ready for use */
-    ADC_STATE_BUSY_INTERNAL = 0x2,    	/**< ADC is busy to internal process */
-    ADC_STATE_TIMEOUT       = 0x4,    	/**< TimeOut occurrence */
-    ADC_STATE_ERROR         = 0x10,   	/**< Internal error occurrence */
-    ADC_STATE_NM_BUSY       = 0x100,  	/**< Conversion on group normal is ongoing or can occur */
-    ADC_STATE_NM_EOC        = 0x200,  	/**< Conversion data available on group normal */
-    ADC_STATE_IST_BUSY      = 0x1000, 	/**< Conversion on group insert is ongoing or can occur */
-    ADC_STATE_IST_EOC       = 0x2000, 	/**< Conversion data available on group insert */
-    ADC_STATE_AWD           = 0x10000,	/**< Out-of-window occurrence of analog watchdog */
+typedef enum {
+	ADC_STATE_RESET    = 0x0U,	/**< ADC not yet initialized or disabled */
+	ADC_STATE_READY    = 0x1U,	/**< ADC peripheral ready for use */
+	ADC_STATE_BUSY     = 0x2U,	/**< ADC is busy to internal process */
+	ADC_STATE_TIMEOUT  = 0x4U,	/**< TimeOut occurrence */
+	ADC_STATE_ERROR    = 0x8U,	/**< Internal error occurrence */
+	ADC_STATE_BUSY_N   = 0x10U,	/**< Normal channel busy */
+	ADC_STATE_BUSY_I   = 0x20U,	/**< Insert channel busy */
+	ADC_STATE_BUSY_WDG = 0x40U,	/**< Insert channel busy */
 } adc_state_t;
 
 /**
   *@brief ADC Error Code
   */
-typedef enum
-{
-    ADC_ERROR_NONE     = 0x0,	/**< No error */
-    ADC_ERROR_INTERNAL = 0x1,	/**< ADC IP internal error*/
-    ADC_ERROR_OVR      = 0x2,	/**< Overrun error */
-    ADC_ERROR_DMA      = 0x4, 	/**< DMA transfer error */
+typedef enum {
+	ADC_ERROR_NONE     = 0x0U,	/**< No error */
+	ADC_ERROR_INTERNAL = 0x1U,	/**< ADC IP internal error*/
+	ADC_ERROR_OVR      = 0x2U,	/**< Overrun error */
+	ADC_ERROR_DMA      = 0x4U, 	/**< DMA transfer error */
 } adc_error_t;
 
 /**
   *@brief ADC data alignment
   */
-typedef enum
-{
-    ADC_DATAALIGN_RIGHT = 0x0,	/**< ADC data alignment right */
-    ADC_DATAALIGN_LEFT  = 0x1,	/**< ADC data alignment left */
+typedef enum {
+	ADC_DATAALIGN_RIGHT = 0x0U,	/**< ADC data alignment right */
+	ADC_DATAALIGN_LEFT  = 0x1U,	/**< ADC data alignment left */
 } adc_align_t;
 
 /**
   *@brief ADC config  hannal trigger the EOC IT mode
   */
-typedef enum
-{
-    ADC_NCHESEL_MODE_ALL = 0x0,	/**< ADC set RCHE after convert sequence finish */
-    ADC_NCHESEL_MODE_ONE = 0x1,	/**< ADC set RCHE after one convert finish */
+typedef enum {
+	ADC_NCHESEL_MODE_ALL = 0x0U,	/**< ADC set RCHE after convert sequence finish */
+	ADC_NCHESEL_MODE_ONE = 0x1U,	/**< ADC set RCHE after one convert finish */
 } adc_nchesel_t;
 
 /**
   *@brief  ADC channels
   */
-typedef enum
-{
-    ADC_CHANNEL_0  = 0x0, 	/**< ADC channel 0 */
-    ADC_CHANNEL_1  = 0x1, 	/**< ADC channel 1 */
-    ADC_CHANNEL_2  = 0x2, 	/**< ADC channel 2 */
-    ADC_CHANNEL_3  = 0x3, 	/**< ADC channel 3 */
-    ADC_CHANNEL_4  = 0x4, 	/**< ADC channel 4 */
-    ADC_CHANNEL_5  = 0x5, 	/**< ADC channel 5 */
-    ADC_CHANNEL_6  = 0x6, 	/**< ADC channel 6 */
-    ADC_CHANNEL_7  = 0x7, 	/**< ADC channel 7 */
-    ADC_CHANNEL_8  = 0x8, 	/**< ADC channel 8 */
-    ADC_CHANNEL_9  = 0x9, 	/**< ADC channel 9 */
-    ADC_CHANNEL_10 = 0xA, 	/**< ADC channel 10 */
-    ADC_CHANNEL_11 = 0xB, 	/**< ADC channel 11 */
-    ADC_CHANNEL_12 = 0xC, 	/**< ADC channel 12 */
-    ADC_CHANNEL_13 = 0xD, 	/**< ADC channel 13 */
-    ADC_CHANNEL_14 = 0xE, 	/**< ADC channel 14 */
-    ADC_CHANNEL_15 = 0xF, 	/**< ADC channel 15 */
-    ADC_CHANNEL_16 = 0x10,	/**< ADC channel 16 */
-    ADC_CHANNEL_17 = 0x11,	/**< ADC channel 17 */
-    ADC_CHANNEL_18 = 0x12,	/**< ADC channel 18 */
-    ADC_CHANNEL_19 = 0x13,	/**< ADC channel 19 */
+typedef enum {
+	ADC_CHANNEL_0  = 0x0U, 	/**< ADC channel 0 */
+	ADC_CHANNEL_1  = 0x1U, 	/**< ADC channel 1 */
+	ADC_CHANNEL_2  = 0x2U, 	/**< ADC channel 2 */
+	ADC_CHANNEL_3  = 0x3U, 	/**< ADC channel 3 */
+	ADC_CHANNEL_4  = 0x4U, 	/**< ADC channel 4 */
+	ADC_CHANNEL_5  = 0x5U, 	/**< ADC channel 5 */
+	ADC_CHANNEL_6  = 0x6U, 	/**< ADC channel 6 */
+	ADC_CHANNEL_7  = 0x7U, 	/**< ADC channel 7 */
+	ADC_CHANNEL_8  = 0x8U, 	/**< ADC channel 8 */
+	ADC_CHANNEL_9  = 0x9U, 	/**< ADC channel 9 */
+	ADC_CHANNEL_10 = 0xAU, 	/**< ADC channel 10 */
+	ADC_CHANNEL_11 = 0xBU, 	/**< ADC channel 11 */
+	ADC_CHANNEL_12 = 0xCU, 	/**< ADC channel 12 */
+	ADC_CHANNEL_13 = 0xDU, 	/**< ADC channel 13 */
+	ADC_CHANNEL_14 = 0xEU, 	/**< ADC channel 14 */
+	ADC_CHANNEL_15 = 0xFU, 	/**< ADC channel 15 */
+	ADC_CHANNEL_16 = 0x10U,	/**< ADC channel 16 */
+	ADC_CHANNEL_17 = 0x11U,	/**< ADC channel 17 */
+	ADC_CHANNEL_18 = 0x12U,	/**< ADC channel 18 */
+	ADC_CHANNEL_19 = 0x13U,	/**< ADC channel 19 */
 } adc_channel_t;
 
 /**
   *@brief  ADC sampling times
   */
-typedef enum
-{
-    ADC_SAMPLETIME_1  = 0x0,	/**< ADC sampling times 1 clk */
-    ADC_SAMPLETIME_2  = 0x1,	/**< ADC sampling times 2 clk */
-    ADC_SAMPLETIME_4  = 0x2,	/**< ADC sampling times 4 clk */
-    ADC_SAMPLETIME_15 = 0x3,	/**< ADC sampling times 15 clk */
+typedef enum {
+	ADC_SAMPLETIME_1  = 0x0U,	/**< ADC sampling times 1 clk */
+	ADC_SAMPLETIME_2  = 0x1U,	/**< ADC sampling times 2 clk */
+	ADC_SAMPLETIME_4  = 0x2U,	/**< ADC sampling times 4 clk */
+	ADC_SAMPLETIME_15 = 0x3U,	/**< ADC sampling times 15 clk */
 } adc_samp_t;
 
 /**
-  *@brief   ADC rank into normal group
-  */
-typedef enum
-{
-    ADC_NCH_RANK_1  = 0x1, 	/**< ADC normal channel rank 1 */
-    ADC_NCH_RANK_2  = 0x2, 	/**< ADC normal channel rank 2 */
-    ADC_NCH_RANK_3  = 0x3, 	/**< ADC normal channel rank 3 */
-    ADC_NCH_RANK_4  = 0x4, 	/**< ADC normal channel rank 4 */
-    ADC_NCH_RANK_5  = 0x5, 	/**< ADC normal channel rank 5 */
-    ADC_NCH_RANK_6  = 0x6, 	/**< ADC normal channel rank 6 */
-    ADC_NCH_RANK_7  = 0x7, 	/**< ADC normal channel rank 7 */
-    ADC_NCH_RANK_8  = 0x8, 	/**< ADC normal channel rank 8 */
-    ADC_NCH_RANK_9  = 0x9, 	/**< ADC normal channel rank 9 */
-    ADC_NCH_RANK_10 = 0xA, 	/**< ADC normal channel rank 10 */
-    ADC_NCH_RANK_11 = 0xB, 	/**< ADC normal channel rank 11 */
-    ADC_NCH_RANK_12 = 0xC, 	/**< ADC normal channel rank 12 */
-    ADC_NCH_RANK_13 = 0xD, 	/**< ADC normal channel rank 13 */
-    ADC_NCH_RANK_14 = 0xE, 	/**< ADC normal channel rank 14 */
-    ADC_NCH_RANK_15 = 0xF, 	/**< ADC normal channel rank 15 */
-    ADC_NCH_RANK_16 = 0x10,	/**< ADC normal channel rank 16 */
-} adc_nch_rank_t;
-
-/**
-  * @brief ADC rank into insert group
-  */
-typedef enum
-{
-    ADC_ICH_RANK_1 = 0x1,	/**< ADC insert channel rank 1 */
-    ADC_ICH_RANK_2 = 0x2,	/**< ADC insert channel rank 2 */
-    ADC_ICH_RANK_3 = 0x3,	/**< ADC insert channel rank 3 */
-    ADC_ICH_RANK_4 = 0x4,	/**< ADC insert channel rank 4 */
-} adc_ich_rank_t;
+  *@brief   ADC index channel in normal group
+  */
+typedef enum {
+	ADC_NCH_IDX_1  = 0x1U, 	/**< ADC normal channel index 1 */
+	ADC_NCH_IDX_2  = 0x2U, 	/**< ADC normal channel index 2 */
+	ADC_NCH_IDX_3  = 0x3U, 	/**< ADC normal channel index 3 */
+	ADC_NCH_IDX_4  = 0x4U, 	/**< ADC normal channel index 4 */
+	ADC_NCH_IDX_5  = 0x5U, 	/**< ADC normal channel index 5 */
+	ADC_NCH_IDX_6  = 0x6U, 	/**< ADC normal channel index 6 */
+	ADC_NCH_IDX_7  = 0x7U, 	/**< ADC normal channel index 7 */
+	ADC_NCH_IDX_8  = 0x8U, 	/**< ADC normal channel index 8 */
+	ADC_NCH_IDX_9  = 0x9U, 	/**< ADC normal channel index 9 */
+	ADC_NCH_IDX_10 = 0xAU, 	/**< ADC normal channel index 10 */
+	ADC_NCH_IDX_11 = 0xBU, 	/**< ADC normal channel index 11 */
+	ADC_NCH_IDX_12 = 0xCU, 	/**< ADC normal channel index 12 */
+	ADC_NCH_IDX_13 = 0xDU, 	/**< ADC normal channel index 13 */
+	ADC_NCH_IDX_14 = 0xEU, 	/**< ADC normal channel index 14 */
+	ADC_NCH_IDX_15 = 0xFU, 	/**< ADC normal channel index 15 */
+	ADC_NCH_IDX_16 = 0x10U,	/**< ADC normal channel index 16 */
+} adc_nch_idx_t;
+
+/**
+  * @brief ADC index channel in insert group
+  */
+typedef enum {
+	ADC_ICH_IDX_1 = 0x1U,	/**< ADC insert channel index 1 */
+	ADC_ICH_IDX_2 = 0x2U,	/**< ADC insert channel index 2 */
+	ADC_ICH_IDX_3 = 0x3U,	/**< ADC insert channel index 3 */
+	ADC_ICH_IDX_4 = 0x4U,	/**< ADC insert channel index 4 */
+} adc_ich_idx_t;
 
 /**
   * @brief ADC analog watchdog mode
   */
-typedef enum
-{
-    ADC_ANAWTD_NONE       = 0x0,     	/**< No watch dog */
-    ADC_ANAWTD_SING_NM    = 0x800200,	/**< One normal channel watch dog */
-    ADC_ANAWTD_SING_IST   = 0x400200,	/**< One inset channel Injec watch dog */
-    ADC_ANAWTD_SING_NMIST = 0xC00200,	/**< One normal and inset channel watch dog */
-    ADC_ANAWTD_ALL_NM     = 0x800000,	/**< All normal channel watch dog */
-    ADC_ANAWTD_ALL_IST    = 0x400000,	/**< All inset channel watch dog */
-    ADC_ANAWTD_ALL_NMIST  = 0xC00000,	/**< All normal and inset channel watch dog */
-} adc_ana_wtd_t;
+typedef enum {
+	ADC_ANAWTD_NONE       = 0x0U,     	/**< No watch dog */
+	ADC_ANAWTD_SING_NM    = 0x800200U,	/**< One normal channel watch dog */
+	ADC_ANAWTD_SING_IST   = 0x400200U,	/**< One insert channel watch dog */
+	ADC_ANAWTD_SING_NMIST = 0xC00200U,	/**< One normal and insert channel watch dog */
+	ADC_ANAWTD_ALL_NM     = 0x800000U,	/**< All normal channel watch dog */
+	ADC_ANAWTD_ALL_IST    = 0x400000U,	/**< All insert channel watch dog */
+	ADC_ANAWTD_ALL_NMIST  = 0xC00000U,	/**< All normal and insert channel watch dog */
+} adc_ana_wdg_t;
 
 /**
   * @brief ADC Event type
   */
-typedef enum
-{
-    ADC_AWD_EVENT = (1U << 0),	/**< ADC analog watch dog event */
+typedef enum {
+	ADC_AWD_EVENT = (1U << 0),	/**< ADC analog watch dog event */
 } adc_event_type_t;
 
 /**
   * @brief ADC interrupts definition
   */
-typedef enum
-{
-    ADC_IT_NCH  = (1U << 5), 	/**< ADC it normal */
-    ADC_IT_AWD = (1U << 6), 	/**< ADC it awd */
-    ADC_IT_ICH  = (1U << 7), 	/**< ADC it insert */
-    ADC_IT_OVR = (1U << 26),	/**< ADC it overring */
+typedef enum {
+	ADC_IT_NCH = (1U << 5), 	/**< ADC it normal */
+	ADC_IT_AWD = (1U << 6), 	/**< ADC it awd */
+	ADC_IT_ICH = (1U << 7), 	/**< ADC it insert */
+	ADC_IT_OVR = (1U << 26),	/**< ADC it overring */
 } adc_it_t;
 
 /**
   * @brief ADC flags definition
   */
-typedef enum
-{
-    ADC_FLAG_AWD  = (1U << 0),	/**<ADC flag awd */
-    ADC_FLAG_NCH  = (1U << 1),	/**<ADC flag normal mode */
-    ADC_FLAG_ICH  = (1U << 2),	/**<ADC flag inset mode */
-    ADC_FLAG_OVR  = (1U << 3),	/**<ADC flag ovr */
-    ADC_FLAG_NCHS = (1U << 8),	/**<ADC flag normal start */
-    ADC_FLAG_ICHS = (1U << 9),	/**<ADC flag inset start */
+typedef enum {
+	ADC_FLAG_AWD  = (1U << 0),	/**<ADC flag awd */
+	ADC_FLAG_NCH  = (1U << 1),	/**<ADC flag normal mode */
+	ADC_FLAG_ICH  = (1U << 2),	/**<ADC flag insert mode */
+	ADC_FLAG_OVR  = (1U << 3),	/**<ADC flag ovr */
+	ADC_FLAG_NCHS = (1U << 8),	/**<ADC flag normal start */
+	ADC_FLAG_ICHS = (1U << 9),	/**<ADC flag insert start */
 } adc_flag_t;
 
 /**
   * @brief ADC CLD DIV definition
   */
-typedef enum
-{
-    ADC_CKDIV_1   = 0x0,	/**< ADC CLK DIV 1 */
-    ADC_CKDIV_2   = 0x1,	/**< ADC CLK DIV 2 */
-    ADC_CKDIV_4   = 0x2,	/**< ADC CLK DIV 4 */
-    ADC_CKDIV_8   = 0x3,	/**< ADC CLK DIV 8 */
-    ADC_CKDIV_16  = 0x4,	/**< ADC CLK DIV 16 */
-    ADC_CKDIV_32  = 0x5,	/**< ADC CLK DIV 32 */
-    ADC_CKDIV_64  = 0x6,	/**< ADC CLK DIV 64 */
-    ADC_CKDIV_128 = 0x7,	/**< ADC CLK DIV 128 */
+typedef enum {
+	ADC_CKDIV_1   = 0x0U,	/**< ADC CLK DIV 1 */
+	ADC_CKDIV_2   = 0x1U,	/**< ADC CLK DIV 2 */
+	ADC_CKDIV_4   = 0x2U,	/**< ADC CLK DIV 4 */
+	ADC_CKDIV_8   = 0x3U,	/**< ADC CLK DIV 8 */
+	ADC_CKDIV_16  = 0x4U,	/**< ADC CLK DIV 16 */
+	ADC_CKDIV_32  = 0x5U,	/**< ADC CLK DIV 32 */
+	ADC_CKDIV_64  = 0x6U,	/**< ADC CLK DIV 64 */
+	ADC_CKDIV_128 = 0x7U,	/**< ADC CLK DIV 128 */
 } adc_clk_div_t;
 
 /**
   * @brief ADC negative reference voltage definition
   */
-typedef enum
-{
-    ADC_NEG_REF_VSS   = 0x0,	/**< ADC negative regerence voltage vss */
-    ADC_NEG_REF_VREFN = 0x1,	/**< ADC negative regerence voltage vrefn */
+typedef enum {
+	ADC_NEG_REF_VSS   = 0x0U,	/**< ADC negative regerence voltage vss */
+	ADC_NEG_REF_VREFN = 0x1U,	/**< ADC negative regerence voltage vrefn */
 } adc_neg_ref_t;
 
 /**
   * @brief ADC positive reference voltage definition
   */
-typedef enum
-{
-    ADC_POS_REF_VDD        = 0x0,	/**< ADC posotove reference is VDD */
-    ADC_POS_REF_VREEFP     = 0x2,	/**< ADC posotove reference is VREEFP */
-    ADC_POS_REF_VREEFP_BUF = 0x3,	/**< ADC posotove reference is VREEFP BUFFER */
+typedef enum {
+	ADC_POS_REF_VDD        = 0x0U,	/**< ADC posotove reference is VDD */
+	ADC_POS_REF_VREEFP     = 0x2U,	/**< ADC posotove reference is VREEFP */
+	ADC_POS_REF_VREEFP_BUF = 0x3U,	/**< ADC posotove reference is VREEFP BUFFER */
 } adc_pos_ref_t;
 
 /**
   * @brief ADC numbers of normal conversion channals
   */
-typedef enum
-{
-    ADC_NCH_LEN_1  = 0x0,	/**< ADC length of normal conversion 1 */
-    ADC_NCH_LEN_2  = 0x1,	/**< ADC length of normal conversion 2 */
-    ADC_NCH_LEN_3  = 0x2,	/**< ADC length of normal conversion 3 */
-    ADC_NCH_LEN_4  = 0x3,	/**< ADC length of normal conversion 4 */
-    ADC_NCH_LEN_5  = 0x4,	/**< ADC length of normal conversion 5 */
-    ADC_NCH_LEN_6  = 0x5,	/**< ADC length of normal conversion 6 */
-    ADC_NCH_LEN_7  = 0x6,	/**< ADC length of normal conversion 7 */
-    ADC_NCH_LEN_8  = 0x7,	/**< ADC length of normal conversion 8 */
-    ADC_NCH_LEN_9  = 0x8,	/**< ADC length of normal conversion 9 */
-    ADC_NCH_LEN_10 = 0x9,	/**< ADC length of normal conversion 10 */
-    ADC_NCH_LEN_11 = 0xA,	/**< ADC length of normal conversion 11 */
-    ADC_NCH_LEN_12 = 0xB,	/**< ADC length of normal conversion 12 */
-    ADC_NCH_LEN_13 = 0xC,	/**< ADC length of normal conversion 13 */
-    ADC_NCH_LEN_14 = 0xD,	/**< ADC length of normal conversion 14 */
-    ADC_NCH_LEN_15 = 0xE,	/**< ADC length of normal conversion 15 */
-    ADC_NCH_LEN_16 = 0xF,	/**< ADC length of normal conversion 16 */
-} adc_nch_len_t;
+typedef enum {
+	ADC_NCH_NR_1  = 0x0U,	/**< ADC number of normal conversion 1 */
+	ADC_NCH_NR_2  = 0x1U,	/**< ADC number of normal conversion 2 */
+	ADC_NCH_NR_3  = 0x2U,	/**< ADC number of normal conversion 3 */
+	ADC_NCH_NR_4  = 0x3U,	/**< ADC number of normal conversion 4 */
+	ADC_NCH_NR_5  = 0x4U,	/**< ADC number of normal conversion 5 */
+	ADC_NCH_NR_6  = 0x5U,	/**< ADC number of normal conversion 6 */
+	ADC_NCH_NR_7  = 0x6U,	/**< ADC number of normal conversion 7 */
+	ADC_NCH_NR_8  = 0x7U,	/**< ADC number of normal conversion 8 */
+	ADC_NCH_NR_9  = 0x8U,	/**< ADC number of normal conversion 9 */
+	ADC_NCH_NR_10 = 0x9U,	/**< ADC number of normal conversion 10 */
+	ADC_NCH_NR_11 = 0xAU,	/**< ADC number of normal conversion 11 */
+	ADC_NCH_NR_12 = 0xBU,	/**< ADC number of normal conversion 12 */
+	ADC_NCH_NR_13 = 0xCU,	/**< ADC number of normal conversion 13 */
+	ADC_NCH_NR_14 = 0xDU,	/**< ADC number of normal conversion 14 */
+	ADC_NCH_NR_15 = 0xEU,	/**< ADC number of normal conversion 15 */
+	ADC_NCH_NR_16 = 0xFU,	/**< ADC number of normal conversion 16 */
+} adc_nch_nr_t;
 
 /**
   * @brief ADC numbers of insert conversion channals
   */
-typedef enum
-{
-    ADC_ICH_LEN_1 = 0x0,	/**< ADC number of insert conversion 1 */
-    ADC_ICH_LEN_2 = 0x1,	/**< ADC number of insert conversion 2 */
-    ADC_ICH_LEN_3 = 0x2,	/**< ADC number of insert conversion 3 */
-    ADC_ICH_LEN_4 = 0x3,	/**< ADC number of insert conversion 4 */
-} adc_ich_len_t;
+typedef enum {
+	ADC_ICH_NR_1 = 0x0U,	/**< ADC number of insert conversion 1 */
+	ADC_ICH_NR_2 = 0x1U,	/**< ADC number of insert conversion 2 */
+	ADC_ICH_NR_3 = 0x2U,	/**< ADC number of insert conversion 3 */
+	ADC_ICH_NR_4 = 0x3U,	/**< ADC number of insert conversion 4 */
+} adc_ich_nr_t;
+
 /**
   * @brief ADC discontinuous mode choose
   */
-typedef enum
-{
-    ADC_ALL_DISABLE = 0x0,	/**< ADC discontinuous mode all disable */
-    ADC_NCH_DISC_EN = 0x1,	/**< ADC normal channel discontinuous mode enable */
-    ADC_ICH_DISC_EN = 0x2,	/**< ADC insert channel discontinuous mode enable */
+typedef enum {
+	ADC_ALL_DISABLE = 0x0U,	/**< ADC discontinuous mode all disable */
+	ADC_NCH_DISC_EN = 0x1U,	/**< ADC normal channel discontinuous mode enable */
+	ADC_ICH_DISC_EN = 0x2U,	/**< ADC insert channel discontinuous mode enable */
 } adc_disc_mode_t;
+
 /**
   * @brief ADC numbers of channals in discontinuous conversion mode
   */
-typedef enum
-{
-    ADC_DISC_NBR_1 = 0x0,	/**< ADC number of discontinuous conversion 1 */
-    ADC_DISC_NBR_2 = 0x1,	/**< ADC number of discontinuous conversion 2 */
-    ADC_DISC_NBR_3 = 0x2,	/**< ADC number of discontinuous conversion 3 */
-    ADC_DISC_NBR_4 = 0x3,	/**< ADC number of discontinuous conversion 4 */
-    ADC_DISC_NBR_5 = 0x4,	/**< ADC number of discontinuous conversion 5 */
-    ADC_DISC_NBR_6 = 0x5,	/**< ADC number of discontinuous conversion 6 */
-    ADC_DISC_NBR_7 = 0x6,	/**< ADC number of discontinuous conversion 7 */
-    ADC_DISC_NBR_8 = 0x7,	/**< ADC number of discontinuous conversion 8 */
-} adc_disc_nbr_t;
+typedef enum {
+	ADC_DISC_NR_1 = 0x0U,	/**< ADC number of discontinuous conversion 1 */
+	ADC_DISC_NR_2 = 0x1U,	/**< ADC number of discontinuous conversion 2 */
+	ADC_DISC_NR_3 = 0x2U,	/**< ADC number of discontinuous conversion 3 */
+	ADC_DISC_NR_4 = 0x3U,	/**< ADC number of discontinuous conversion 4 */
+	ADC_DISC_NR_5 = 0x4U,	/**< ADC number of discontinuous conversion 5 */
+	ADC_DISC_NR_6 = 0x5U,	/**< ADC number of discontinuous conversion 6 */
+	ADC_DISC_NR_7 = 0x6U,	/**< ADC number of discontinuous conversion 7 */
+	ADC_DISC_NR_8 = 0x7U,	/**< ADC number of discontinuous conversion 8 */
+} adc_disc_nr_t;
 
 /**
   * @brief ADC resolution of conversion
   */
-typedef enum
-{
-    ADC_CONV_RES_6  = 0x0,	/**< ADC resolution of conversion 6 */
-    ADC_CONV_RES_8  = 0x1,	/**< ADC resolution of conversion 8 */
-    ADC_CONV_RES_10 = 0x2,	/**< ADC resolution of conversion 10 */
-    ADC_CONV_RES_12 = 0x3,	/**< ADC resolution of conversion 12 */
-} adc_conv_res_t;
+typedef enum {
+	ADC_CONV_BIT_6  = 0x0U,	/**< ADC resolution of conversion 6 */
+	ADC_CONV_BIT_8  = 0x1U,	/**< ADC resolution of conversion 8 */
+	ADC_CONV_BIT_10 = 0x2U,	/**< ADC resolution of conversion 10 */
+	ADC_CONV_BIT_12 = 0x3U,	/**< ADC resolution of conversion 12 */
+} adc_conv_bit_t;
 
 /**
   * @brief  Structure definition of ADC and normal group initialization
   */
-typedef struct
-{
-    adc_align_t data_align;		/**< Specifies ADC data alignment */
-    type_func_t scan_mode;         	/**< Choose scan mode enable or not */
-    type_func_t cont_mode;       	/**< Choose continuous mode enable or not */
-    adc_nch_len_t nch_len;  	/**< Length of normal ranks will be converted */
-    adc_disc_mode_t disc_mode;    	/**< Discontinuous mode enable or not */
-    adc_disc_nbr_t disc_nbr;	/**< Number of discontinuous conversions channel */
-    adc_conv_res_t conv_res;   	/**< The precision of conversion */
-    adc_clk_div_t clk_div;		/**< ADCCLK divider */
-    adc_nchesel_t nche_sel;		/**< Trigger the NCHE FALG mode */
-    adc_neg_ref_t neg_ref;    	/**< The negative reference voltage*/
-    adc_pos_ref_t pos_ref;    	/**< The positive reference voltage*/
+typedef struct {
+	adc_align_t align;		/**< Specifies ADC data alignment */
+	type_func_t scan;         	/**< Choose scan mode enable or not */
+	type_func_t cont;       	/**< Choose continuous mode enable or not */
+	adc_nch_nr_t nch_nr;  		/**< Length of normal ranks will be converted */
+	adc_disc_mode_t disc;    	/**< Discontinuous mode enable or not */
+	adc_disc_nr_t disc_nr;		/**< Number of discontinuous conversions channel */
+	adc_conv_bit_t data_bit;	/**< The precision of conversion */
+	adc_clk_div_t div;		/**< ADCCLK divider */
+	adc_nchesel_t nche_sel;		/**< Trigger the NCHE FALG mode */
+	adc_neg_ref_t n_ref;    	/**< The negative reference voltage*/
+	adc_pos_ref_t p_ref;    	/**< The positive reference voltage*/
 } adc_init_t;
 
 /**
   * @brief  Structure definition of ADC channel for normal group
   */
-typedef struct
-{
-    adc_channel_t channel;        	/**< The channel to configure into ADC normal group */
-    adc_nch_rank_t rank;       	/**< The rank in the normal group sequencer */
-    adc_samp_t samp_time;		/**< Sampling time value to be set */
+typedef struct {
+	adc_channel_t ch;	/**< The channel to configure into ADC normal group */
+	adc_nch_idx_t idx;	/**< The rank in the normal group sequencer */
+	adc_samp_t samp;	/**< Sampling time value to be set */
 } adc_nch_conf_t;
 
 /**
   * @brief  ADC Configuration analog watchdog definition
   */
-typedef struct
-{
-    adc_ana_wtd_t watchdog_mode;		/**< Configures the ADC analog watchdog mode*/
-    adc_channel_t channel;			/**< Selects which ADC channel to monitor by analog watchdog */
-    type_func_t it_mode;             	/**< Whether the analog watchdog is configured in interrupt */
-    uint32_t high_threshold;     	 	/**< The ADC analog watchdog High threshold value. */
-    uint32_t low_threshold;      	 	/**< The ADC analog watchdog Low threshold value. */
+typedef struct {
+	adc_ana_wdg_t mode;	/**< Configures the ADC analog watchdog mode*/
+	adc_channel_t ch;	/**< Selects which ADC channel to monitor by analog watchdog */
+	type_func_t interrupt;	/**< Whether the analog watchdog is configured in interrupt */
+	uint32_t high_thrd;	/**< The ADC analog watchdog High threshold value. */
+	uint32_t low_thrd;	/**< The ADC analog watchdog Low threshold value. */
 } adc_analog_wdg_conf_t;
 
 /**
   * @brief  ADC Configuration insert Channel structure definition
   */
-typedef struct
-{
-    adc_channel_t channel;	/**< Selection of ADC channel to configure */
-    adc_ich_rank_t rank;	/**< Rank in the insert group sequencer */
-    adc_samp_t samp_time;	/**< Sampling time value for selected channel */
-    uint32_t offset;	/**< The offset about converted data */
-    adc_ich_len_t ich_len;	/**< The number of insert ranks */
-    type_func_t auto_inj;	/**< insert sequence's auto function */
+typedef struct {
+	adc_channel_t ch;	/**< Selection of ADC channel to configure */
+	adc_ich_idx_t idx;	/**< Rank in the insert group sequencer */
+	adc_samp_t samp;	/**< Sampling time value for selected channel */
+	uint32_t offset;	/**< The offset about converted data */
+	adc_ich_nr_t nr;	/**< The number of insert ranks */
+	type_func_t auto_m;	/**< insert sequence's auto function */
 } adc_ich_conf_t;
 
 /**
   * @brief  ADC handle Structure definition
   */
-typedef struct adc_handle_s
-{
-    ADC_TypeDef *perh;			/**< Register base address */
-    adc_init_t init;			/**< ADC required parameters */
+typedef struct adc_handle_s {
+	ADC_TypeDef *perh;	/**< Register base address */
+	adc_init_t init;	/**< ADC required parameters */
 #ifdef ALD_DMA
-    dma_handle_t hdma;			/**< Pointer DMA Handler */
-    pis_handle_t hpis;			/**< Pointer PIS Handler for connect adc and dma */
+	dma_handle_t hdma;	/**< Pointer DMA Handler */
+	pis_handle_t hpis;	/**< Pointer PIS Handler for connect adc and dma */
 #endif
-    uint32_t vdd_value;			/**< ADC vdd reference voltage value,unit:mV */
-    lock_state_t lock;			/**< ADC locking object */
-    adc_state_t state;			/**< ADC communication state  */
-    adc_error_t error_code;			/**< ADC Error code */
-
-    void (*adc_reg_cplt_cbk)(struct adc_handle_s *arg);  	/**< Regluar Conversion complete callback */
-    void (*adc_inj_cplt_cbk)(struct adc_handle_s *arg);  	/**< insert Conversion complete callback */
-    void (*adc_out_of_win_cbk)(struct adc_handle_s *arg);	/**< Level out of window callback */
-    void (*adc_error_cbk)(struct adc_handle_s *arg);      	/**< adc error callback */
-    void (*adc_ovr_cbk)(struct adc_handle_s *arg);	      	/**< adc ovr callback */
+	uint32_t vdd_value;	/**< ADC vdd reference voltage value,unit:mV */ 
+	lock_state_t lock;	/**< ADC locking object */
+	adc_state_t state;	/**< ADC communication state  */
+	adc_error_t error_code;	/**< ADC Error code */
+
+	void (*normal_cplt_cbk)( struct adc_handle_s *arg);  	/**< Regluar Conversion complete callback */
+	void (*insert_cplt_cbk)( struct adc_handle_s *arg);  	/**< insert Conversion complete callback */
+	void (*wdg_cbk)( struct adc_handle_s *arg);		/**< Level out of window callback */
+	void (*error_cbk)(struct adc_handle_s *arg);      	/**< adc error callback */
+	void (*ovr_cbk)(struct adc_handle_s *arg);	      	/**< adc ovr callback */
 } adc_handle_t;
 
 /**
   * @brief Timer trigger adc config structure definition
   */
-typedef struct
-{
-    uint32_t time;						/**< Timer period time uint: us */
-    uint16_t size;						/**< Adc convert times */
-    uint16_t *buf;						/**< Convert data buffer */
-    adc_neg_ref_t n_ref;					/**< The negative reference voltage for adc*/
-    adc_pos_ref_t p_ref;					/**< The positive reference voltage for adc*/
-    adc_channel_t adc_ch;					/**< Adc channel */
-    uint8_t dma_ch;						/**< Dma channel */
-    TIMER_TypeDef *p_timer;					/**< Adc peripheral */
-    ADC_TypeDef *p_adc;					/**< Dma peripheral */
-    void (*adc_cplt_cbk)(struct adc_handle_s *arg);	/**< Conversion complete callback */
-
-    /* private variable */
-    lock_state_t lock;		/**< Locking object */
-    pis_handle_t lh_pis;		/**< Handle of PIS module */
-    dma_handle_t lh_dma;		/**< Handle of DMA module */
-    timer_handle_t lh_timer;	/**< Handle of TIMER module */
-    adc_handle_t lh_adc;		/**< Handle of ADC module */
-    adc_nch_conf_t lnm_config;	/**< Struct for chanel configure */
+typedef struct {
+	uint32_t time;		/**< Timer period time uint: us */	
+	uint16_t size;		/**< Adc convert times */	
+	uint16_t *buf;		/**< Convert data buffer */	
+	adc_neg_ref_t n_ref;	/**< The negative reference voltage for adc*/
+	adc_pos_ref_t p_ref;	/**< The positive reference voltage for adc*/
+	adc_channel_t adc_ch;	/**< Adc channel */	
+	uint8_t dma_ch;		/**< Dma channel */	
+	TIMER_TypeDef *p_timer;	/**< Timer peripheral */	
+	ADC_TypeDef *p_adc;	/**< Adc peripheral */	
+	void (*cplt_cbk)( struct adc_handle_s *arg);	/**< Conversion complete callback */
+
+	/* private variable */
+	lock_state_t lock;	/**< Locking object */
+	pis_handle_t h_pis;	/**< Handle of PIS module */
+	dma_handle_t h_dma;	/**< Handle of DMA module */
+	timer_handle_t h_timer;	/**< Handle of TIMER module */
+	adc_handle_t h_adc;	/**< Handle of ADC module */
+	adc_nch_conf_t config;	/**< Struct for channel configure */
 } adc_timer_config_t;
 /**
   * @}
@@ -410,13 +384,17 @@ typedef struct
 /** @defgroup ADC_Public_Macros ADC Public Macros
   * @{
   */
-#define ADC_ENABLE(handle) 			(SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
-#define ADC_DISABLE(handle) 			(CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
-#define ADC_NH_TRIG_BY_SOFT(handle)		(SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
-#define ADC_IH_TRIG_BY_SOFT(handle)		(SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
-#define ADC_RESET_HANDLE_STATE(handle)		((handle)->state = ADC_STATE_RESET)
-#define ADC_VREF_OUT_ENABLE(handle)		(SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
-#define ADC_VREF_OUT_DISABLE(handle)		(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
+#define ADC_ENABLE(handle) 		(SET_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
+#define ADC_DISABLE(handle) 		(CLEAR_BIT((handle)->perh->CON1, ADC_CON1_ADCEN_MSK))
+#define ADC_NH_TRIG_BY_SOFT(handle)	(SET_BIT((handle)->perh->CON1, ADC_CON1_NCHTRG_MSK))
+#define ADC_IH_TRIG_BY_SOFT(handle)	(SET_BIT((handle)->perh->CON1, ADC_CON1_ICHTRG_MSK))
+#define ADC_RESET_HANDLE_STATE(handle)	((handle)->state = ADC_STATE_RESET)
+#define ADC_VREF_OUT_ENABLE(handle)	(SET_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
+#define ADC_VREF_OUT_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_VREFOEN_MSK))
+#define ADC_SPEED_HIGH_ENABLE(handle)	(SET_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
+#define ADC_SPEED_HIGH_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_PWRMODSEL_MSK))
+#define ADC_CALIBRATE_ENABLE(handle)	(SET_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
+#define ADC_CALIBRATE_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CCR, ADC_CCR_TRMEN_MSK))
 /**
   * @}
   */
@@ -424,68 +402,65 @@ typedef struct
 /** @defgroup ADC_Private_Macros ADC Private Macros
   * @{
   */
-#define IS_ADC_ICH_RANK_TYPE(x)			((x) <= ADC_ICH_RANK_4)
-#define IS_ADC_NCH_RANK_TYPE(x)			((x) <= ADC_NCH_RANK_16)
+#define IS_ADC_ICH_IDX_TYPE(x)			((x) <= ADC_ICH_IDX_4)
+#define IS_ADC_NCH_IDX_TYPE(x)			((x) <= ADC_NCH_IDX_16)
 #define IS_ADC_SAMPLING_TIMES_TYPE(x)		(((x) == ADC_SAMPLETIME_1) || \
-        ((x) == ADC_SAMPLETIME_2) || \
-        ((x) == ADC_SAMPLETIME_4) || \
-        ((x) == ADC_SAMPLETIME_15))
+                                                 ((x) == ADC_SAMPLETIME_2) || \
+					         ((x) == ADC_SAMPLETIME_4) || \
+					         ((x) == ADC_SAMPLETIME_15))
 #define IS_ADC_CHANNELS_TYPE(x)			((x) <= ADC_CHANNEL_19)
-#define IS_ADC_SCAN_MODE_TYPE(x)		(((x) == DISABLE) || \
-        ((x) == ENABLE))
 #define IS_ADC_DATA_ALIGN_TYPE(x)		(((x) == ADC_DATAALIGN_RIGHT) || \
-        ((x) == ADC_DATAALIGN_LEFT))
+                                                 ((x) == ADC_DATAALIGN_LEFT))
 #define IS_ADC_ANALOG_WTD_MODE_TYPE(x)  	(((x) == ADC_ANAWTD_NONE)       || \
-        ((x) == ADC_ANAWTD_SING_NM)    || \
-        ((x) == ADC_ANAWTD_SING_IST)   || \
-        ((x) == ADC_ANAWTD_SING_NMIST) || \
-        ((x) == ADC_ANAWTD_ALL_NM)     || \
-        ((x) == ADC_ANAWTD_ALL_IST)    || \
-        ((x) == ADC_ANAWTD_ALL_NMIST))
+						 ((x) == ADC_ANAWTD_SING_NM)    || \
+						 ((x) == ADC_ANAWTD_SING_IST)   || \
+						 ((x) == ADC_ANAWTD_SING_NMIST) || \
+						 ((x) == ADC_ANAWTD_ALL_NM)     || \
+						 ((x) == ADC_ANAWTD_ALL_IST)    || \
+						 ((x) == ADC_ANAWTD_ALL_NMIST))
 #define IS_ADC_IT_TYPE(x)			(((x) == ADC_IT_NCH) || \
-                                     ((x) == ADC_IT_AWD) || \
-                                     ((x) == ADC_IT_ICH) ||  \
-                                     ((x) == ADC_IT_OVR ))
+						 ((x) == ADC_IT_AWD) || \
+						 ((x) == ADC_IT_ICH) ||  \
+						 ((x) == ADC_IT_OVR ))
 #define IS_ADC_FLAGS_TYPE(x)			(((x) == ADC_FLAG_AWD)  || \
-        ((x) == ADC_FLAG_NCH)  || \
-        ((x) == ADC_FLAG_ICH)  || \
-        ((x) == ADC_FLAG_OVR)  || \
-        ((x) == ADC_FLAG_NCHS) || \
-        ((x) == ADC_FLAG_ICHS))
+						 ((x) == ADC_FLAG_NCH)  || \
+						 ((x) == ADC_FLAG_ICH)  || \
+						 ((x) == ADC_FLAG_OVR)  || \
+						 ((x) == ADC_FLAG_NCHS) || \
+						 ((x) == ADC_FLAG_ICHS))
 #define IS_ADC_CLK_DIV_TYPE(x)			(((x) == ADC_CKDIV_1)   || \
-        ((x) == ADC_CKDIV_2)   || \
-        ((x) == ADC_CKDIV_4)   || \
-        ((x) == ADC_CKDIV_8)   || \
-        ((x) == ADC_CKDIV_16)  || \
-        ((x) == ADC_CKDIV_32)  || \
-        ((x) == ADC_CKDIV_64)  || \
-        ((x) == ADC_CKDIV_128))
+						 ((x) == ADC_CKDIV_2)   || \
+						 ((x) == ADC_CKDIV_4)   || \
+						 ((x) == ADC_CKDIV_8)   || \
+						 ((x) == ADC_CKDIV_16)  || \
+						 ((x) == ADC_CKDIV_32)  || \
+						 ((x) == ADC_CKDIV_64)  || \
+						 ((x) == ADC_CKDIV_128))
 #define IS_ADC_NEG_REF_VOLTAGE_TYPE(x)		(((x) == ADC_NEG_REF_VSS ) || \
-        ((x) == ADC_NEG_REF_VREFN ))
+                                                 ((x) == ADC_NEG_REF_VREFN ))
 #define IS_POS_REF_VOLTAGE_TYPE(x)		(((x) == ADC_POS_REF_VDD)    || \
-        ((x) == ADC_POS_REF_VREEFP) || \
-        ((x) == ADC_POS_REF_VREEFP_BUF))
-#define IS_ADC_NCH_LEN_TYPE(x)			((x) <= ADC_NCH_LEN_16)
-#define IS_ADC_NBR_OF_IST_TYPE(x)		((x) <= ADC_ICH_LEN_4)
+						 ((x) == ADC_POS_REF_VREEFP) || \
+						 ((x) == ADC_POS_REF_VREEFP_BUF))
+#define IS_ADC_NCH_NR_TYPE(x)			((x) <= ADC_NCH_NR_16)
+#define IS_ADC_ICH_NR_TYPE(x)			((x) <= ADC_ICH_NR_4)
 #define IS_ADC_DISC_MODE_TYPE(x)		(((x) == ADC_ALL_DISABLE) || \
-        ((x) == ADC_NCH_DISC_EN) || \
-        ((x) == ADC_ICH_DISC_EN))
-#define IS_ADC_DISC_NBR_TYPE(x)			((x) <= ADC_DISC_NBR_8)
-#define IS_ADC_CONV_RES_TYPE(x)			(((x) == ADC_CONV_RES_12) || \
-        ((x) == ADC_CONV_RES_6)  || \
-        ((x) == ADC_CONV_RES_8)  || \
-        ((x) == ADC_CONV_RES_10))
+						 ((x) == ADC_NCH_DISC_EN) || \
+						 ((x) == ADC_ICH_DISC_EN))
+#define IS_ADC_DISC_NR_TYPE(x)			((x) <= ADC_DISC_NR_8)
+#define IS_ADC_CONV_BIT_TYPE(x)			(((x) == ADC_CONV_BIT_12) || \
+                                                 ((x) == ADC_CONV_BIT_6)  || \
+						 ((x) == ADC_CONV_BIT_8)  || \
+						 ((x) == ADC_CONV_BIT_10))
 #define IS_ADC_TRIG_MODE_TYPE(x)		(((x) == ADC_TRIG_SOFT) || \
-        ((x) == ADC_TRIG_PIS)  || \
-        ((x) == ADC_TRIG_PIS_SOFT))
-#define IS_ADC_TYPE(x) 				(((x) == ADC0) || \
-                                     ((x) == ADC1))
+                                                 ((x) == ADC_TRIG_PIS)  || \
+                                                 ((x) == ADC_TRIG_PIS_SOFT))
+#define IS_ADC_TYPE(x) 				(((x) == ADC0))
 #define IS_ADC_NCHESEL_MODE_TYPE(x)		(((x) == ADC_NCHESEL_MODE_ALL) || \
-        ((x) == ADC_NCHESEL_MODE_ONE))
+						 ((x) == ADC_NCHESEL_MODE_ONE))
 #define IS_ADC_EVENT_TYPE(x)			((x) == ADC_AWD_EVENT)
-#define IS_ADC_IST_OFFSET_TYPE(x)		((x) <= 0xfff)
-#define IS_HTR_TYPE(x)				((x) <= 0xfff)
-#define IS_LTR_TYPE(x)				((x) <= 0xfff)
+#define IS_ADC_IST_OFFSET_TYPE(x)		((x) <= 0xFFF)
+#define IS_HTR_TYPE(x)				((x) <= 0xFFF)
+#define IS_LTR_TYPE(x)				((x) <= 0xFFF)
 /**
   * @}
   */
@@ -514,7 +489,7 @@ ald_status_t ald_adc_normal_start_by_it(adc_handle_t *hperh);
 ald_status_t ald_adc_normal_stop_by_it(adc_handle_t *hperh);
 #ifdef ALD_DMA
 ald_status_t ald_adc_start_by_dma(adc_handle_t *hperh, uint16_t *buf, uint16_t size, uint8_t channel);
-ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh);
+ald_status_t ald_adc_stop_by_dma(adc_handle_t *hperh, uint8_t channel);
 ald_status_t ald_adc_timer_trigger_adc_by_dma(adc_timer_config_t *config);
 #endif
 uint32_t ald_adc_normal_get_value(adc_handle_t *hperh);
@@ -524,7 +499,7 @@ ald_status_t ald_adc_insert_stop(adc_handle_t *hperh);
 ald_status_t ald_adc_insert_poll_for_conversion(adc_handle_t *hperh, uint32_t timeout);
 ald_status_t ald_adc_insert_start_by_it(adc_handle_t *hperh);
 ald_status_t ald_adc_insert_stop_by_it(adc_handle_t *hperh);
-uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_rank_t ih_rank);
+uint32_t ald_adc_insert_get_value(adc_handle_t *hperh, adc_ich_idx_t ih_rank);
 void ald_adc_irq_handler(adc_handle_t *hperh);
 /**
   * @}
@@ -565,8 +540,7 @@ uint32_t ald_adc_get_error(adc_handle_t *hperh);
   * @}
   */
 #ifdef __cplusplus
-extern "C"
-}
+ extern "C" }
 #endif
 
-#endif /* __ALD_ADC_H */
+#endif /* __ALD_ADC_H__ */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_bkpc.h

@@ -35,44 +35,44 @@ extern "C" {
 /** @defgroup BKPC_Public_Macros BKPC Public Macros
   * @{
   */
-#define BKPC_LOCK()		(WRITE_REG(BKPC->PROT, 0))
-#define BKPC_UNLOCK()		(WRITE_REG(BKPC->PROT, 0x9669AA55))
+#define BKPC_LOCK()		(WRITE_REG(BKPC->PROT, 0U))
+#define BKPC_UNLOCK()		(WRITE_REG(BKPC->PROT, 0x9669AA55U))
 #define BKPC_LRC_ENABLE()			\
-    do {						\
-        BKPC_UNLOCK();				\
-        SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
-        BKPC_LOCK();				\
-    } while (0)
+do {						\
+	BKPC_UNLOCK();				\
+	SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
 #define BKPC_LRC_DISABLE()			\
-    do {						\
-        BKPC_UNLOCK();				\
-        CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
-        BKPC_LOCK();				\
-    } while (0)
+do {						\
+	BKPC_UNLOCK();				\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
 #define BKPC_LOSM_ENABLE()			\
-    do {						\
-        BKPC_UNLOCK();				\
-        SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);	\
-        BKPC_LOCK();				\
-    } while (0)
+do {						\
+	BKPC_UNLOCK();				\
+	SET_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
 #define BKPC_LOSM_DISABLE()			\
-    do {						\
-        BKPC_UNLOCK();				\
-        CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
-        BKPC_LOCK();				\
-    } while (0)
+do {						\
+	BKPC_UNLOCK();				\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSMEN_MSK);\
+	BKPC_LOCK();				\
+} while (0)
 #define BKPC_LOSC_ENABLE()			\
-    do {						\
-        BKPC_UNLOCK();				\
-        SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);	\
-        BKPC_LOCK();				\
-    } while (0)
+do {						\
+	BKPC_UNLOCK();				\
+	SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);	\
+	BKPC_LOCK();				\
+} while (0)
 #define BKPC_LOSC_DISABLE()			\
-    do {						\
-        BKPC_UNLOCK();				\
-        CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
-        BKPC_LOCK();				\
-    } while (0)
+do {						\
+	BKPC_UNLOCK();				\
+	CLEAR_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);\
+	BKPC_LOCK();				\
+} while (0)
 /**
   * @}
   */
@@ -83,37 +83,31 @@ extern "C" {
 /**
   * @brief BKPC ldo output select
   */
-typedef enum
-{
-    BKPC_LDO_OUTPUT_1_6 = 0x0,	/**< 1.6V */
-    BKPC_LDO_OUTPUT_1_3 = 0x1,	/**< 1.3V */
-    BKPC_LDO_OUTPUT_1_4 = 0x2,	/**< 1.4V */
-    BKPC_LDO_OUTPUT_1_5 = 0x4,	/**< 1.5V */
+typedef enum {
+	BKPC_LDO_OUTPUT_1_6 = 0x0U,	/**< 1.6V */
+	BKPC_LDO_OUTPUT_1_3 = 0x1U,	/**< 1.3V */
+	BKPC_LDO_OUTPUT_1_4 = 0x2U,	/**< 1.4V */
+	BKPC_LDO_OUTPUT_1_5 = 0x4U,	/**< 1.5V */
 } bkpc_ldo_output_t;
 
 /**
-  * @brief BKPC BOR voltage select
-  */
-typedef enum
-{
-    BKPC_BOR_VOL_1_7  = 0x0,	/**< 1.7V */
-    BKPC_BOR_VOL_2_0  = 0x1,	/**< 2.0V */
-    BKPC_BOR_VOL_2_1  = 0x2,	/**< 2.1V */
-    BKPC_BOR_VOL_2_2  = 0x3,	/**< 2.2V */
-    BKPC_BOR_VOL_2_3  = 0x4,	/**< 2.3V */
-    BKPC_BOR_VOL_2_4  = 0x5,	/**< 2.4V */
-    BKPC_BOR_VOL_2_5  = 0x6,	/**< 2.5V */
-    BKPC_BOR_VOL_2_6  = 0x7,	/**< 2.6V */
-    BKPC_BOR_VOL_2_8  = 0x8,	/**< 2.8V */
-    BKPC_BOR_VOL_3_0  = 0x9,	/**< 3.0V */
-    BKPC_BOR_VOL_3_1  = 0xA,	/**< 3.1V */
-    BKPC_BOR_VOL_3_3  = 0xB,	/**< 3.3V */
-    BKPC_BOR_VOL_3_6  = 0xC,	/**< 3.6V */
-    BKPC_BOR_VOL_3_7  = 0xD,	/**< 3.7V */
-    BKPC_BOR_VOL_4_0  = 0xE,	/**< 4.0V */
-    BKPC_BOR_VOL_4_3  = 0xF,	/**< 4.3V */
-} bkpc_bor_vol_t;
+  * @brief Standby wakeup port select
+  */
+typedef enum {
+	PMU_STANDBY_PORT_SEL_PA0  = 0x0U,	/**< Wakeup by PA0 */
+	PMU_STANDBY_PORT_SEL_PA1  = 0x1U,	/**< Wakeup by PA1 */
+	PMU_STANDBY_PORT_SEL_PA2  = 0x2U,	/**< Wakeup by PA2 */
+	PMU_STANDBY_PORT_SEL_PA3  = 0x3U,	/**< Wakeup by PA3 */
+	PMU_STANDBY_PORT_SEL_NONE = 0xFU,	/**< Wakeup by other source */
+} bkpc_wakeup_port_t;
 
+/**
+  * @brief Standby wakeup level
+  */
+typedef enum {
+	PMU_STANDBY_LEVEL_HIGH = 0x0U,	/**< High level */
+	PMU_STANDBY_LEVEL_LOW  = 0x1U,	/**< Low level */
+} bkpc_wakeup_level_t;
 /**
   * @}
   */
@@ -126,22 +120,13 @@ typedef enum
                                  ((x) == BKPC_LDO_OUTPUT_1_3) || \
                                  ((x) == BKPC_LDO_OUTPUT_1_4) || \
                                  ((x) == BKPC_LDO_OUTPUT_1_5))
-#define IS_BKPC_BOR_VOL(x)	(((x) == BKPC_BOR_VOL_1_7) || \
-                             ((x) == BKPC_BOR_VOL_2_0) || \
-                             ((x) == BKPC_BOR_VOL_2_1) || \
-                             ((x) == BKPC_BOR_VOL_2_2) || \
-                             ((x) == BKPC_BOR_VOL_2_3) || \
-                             ((x) == BKPC_BOR_VOL_2_4) || \
-                             ((x) == BKPC_BOR_VOL_2_5) || \
-                             ((x) == BKPC_BOR_VOL_2_6) || \
-                             ((x) == BKPC_BOR_VOL_2_8) || \
-                             ((x) == BKPC_BOR_VOL_3_0) || \
-                             ((x) == BKPC_BOR_VOL_3_1) || \
-                             ((x) == BKPC_BOR_VOL_3_3) || \
-                             ((x) == BKPC_BOR_VOL_3_6) || \
-                             ((x) == BKPC_BOR_VOL_3_7) || \
-                             ((x) == BKPC_BOR_VOL_4_0) || \
-                             ((x) == BKPC_BOR_VOL_4_3))
+#define IS_BKPC_WAKEUP_PORT(x)	(((x) == PMU_STANDBY_PORT_SEL_PA0) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA1) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA2) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_PA3) || \
+                                 ((x) == PMU_STANDBY_PORT_SEL_NONE))
+#define IS_BKPC_WAKEUP_LEVEL(x)	(((x) == PMU_STANDBY_LEVEL_HIGH) || \
+                                 ((x) == PMU_STANDBY_LEVEL_LOW))
 #define IS_BKPC_RAM_IDX(x)	((x) < 32)
 /**
   * @}
@@ -154,8 +139,8 @@ typedef enum
   * @{
   */
 /* control functions */
+extern void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
 extern void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state);
-extern void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state);
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_cmu.h

@@ -37,91 +37,91 @@ extern "C" {
   * @{
   */
 #define CMU_LOSC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LOSC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LOSCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LRC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LRC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_LRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_ULRC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_ULRC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->CLKENR, CMU_CLKENR_ULRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 
 /* Low power mode control */
 #define CMU_LP_LRC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_LRC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->LPENR, CMU_LPENR_LRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_LOSC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_LOSC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->LPENR, CMU_LPENR_LOSCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_HRC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_HRC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->LPENR, CMU_LPENR_HRCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_HOSC_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define CMU_LP_HOSC_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(CMU->LPENR, CMU_LPENR_HOSCEN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 /**
   * @}
   */
@@ -133,287 +133,282 @@ extern "C" {
 /**
   * @brief CMU state structure definition
   */
-typedef	enum
-{
-    CMU_CLOCK_HRC  = 0x1,	/**< HRC */
-    CMU_CLOCK_LRC  = 0x2,	/**< LRC */
-    CMU_CLOCK_LOSC = 0x3,	/**< LOSC */
-    CMU_CLOCK_PLL1 = 0x4,	/**< PLL1 */
-    CMU_CLOCK_HOSC = 0x5,	/**< HOSC */
+typedef	enum {
+	CMU_CLOCK_HRC  = 0x1U,	/**< HRC */
+	CMU_CLOCK_LRC  = 0x2U,	/**< LRC */
+	CMU_CLOCK_LOSC = 0x3U,	/**< LOSC */
+	CMU_CLOCK_PLL1 = 0x4U,	/**< PLL1 */
+	CMU_CLOCK_HOSC = 0x5U,	/**< HOSC */
 } cmu_clock_t;
 
 /**
   * @brief PLL1 output clock
   */
-typedef enum
-{
-    CMU_PLL1_OUTPUT_32M = 0x0,	/**< x8  (32MHz) */
-    CMU_PLL1_OUTPUT_48M = 0x1,	/**< x12 (48MHz) */
+typedef enum {
+	CMU_PLL1_OUTPUT_32M = 0x0U,	/**< x8  (32MHz) */
+	CMU_PLL1_OUTPUT_48M = 0x1U,	/**< x12 (48MHz) */
 } cmu_pll1_output_t;
 
 /**
   * @brief PLL1 referance clock
   */
-typedef enum
-{
-    CMU_PLL1_INPUT_HRC_6  = 0x0,	/**< HRC  / 6 */
-    CMU_PLL1_INPUT_PLL2   = 0x1,	/**< PLL2 */
-    CMU_PLL1_INPUT_HOSC   = 0x2,	/**< HOSC / 1 */
-    CMU_PLL1_INPUT_HOSC_2 = 0x3,	/**< HOSC / 2 */
-    CMU_PLL1_INPUT_HOSC_3 = 0x4,	/**< HOSC / 3 */
-    CMU_PLL1_INPUT_HOSC_4 = 0x5,	/**< HOSC / 4 */
-    CMU_PLL1_INPUT_HOSC_5 = 0x6,	/**< HOSC / 5 */
-    CMU_PLL1_INPUT_HOSC_6 = 0x7,	/**< HOSC / 6 */
+typedef enum {
+	CMU_PLL1_INPUT_HRC_6  = 0x0U,	/**< HRC  / 6 */
+	CMU_PLL1_INPUT_PLL2   = 0x1U,	/**< PLL2 */
+	CMU_PLL1_INPUT_HOSC   = 0x2U,	/**< HOSC / 1 */
+	CMU_PLL1_INPUT_HOSC_2 = 0x3U,	/**< HOSC / 2 */
+	CMU_PLL1_INPUT_HOSC_3 = 0x4U,	/**< HOSC / 3 */
+	CMU_PLL1_INPUT_HOSC_4 = 0x5U,	/**< HOSC / 4 */
+	CMU_PLL1_INPUT_HOSC_5 = 0x6U,	/**< HOSC / 5 */
+	CMU_PLL1_INPUT_HOSC_6 = 0x7U,	/**< HOSC / 6 */
 } cmu_pll1_input_t;
 
 /**
   * @brief HOSC range
   */
-typedef enum
-{
-    CMU_HOSC_2M  = 0x0,
-    CMU_HOSC_4M  = 0x1,
-    CMU_HOSC_8M  = 0x2,
-    CMU_HOSC_16M = 0x3,
-    CMU_HOSC_24M = 0x4,
+typedef enum {
+	CMU_HOSC_2M  = 0x0U,	/**< 0~2MHz */
+	CMU_HOSC_4M  = 0x1U,	/**< 2~4MHz */
+	CMU_HOSC_8M  = 0x2U,	/**< 4~8MHz */
+	CMU_HOSC_16M = 0x3U,	/**< 8~16MHz */
+	CMU_HOSC_24M = 0x4U,	/**< 16~24MHz */
 } cmu_hosc_range_t;
 
 /**
   * @brief Auto-calibrate input
   */
-typedef enum
-{
-    CMU_AUTO_CALIB_INPUT_LOSE = 0x0,
-    CMU_AUTO_CALIB_INPUT_HOSE = 0x1,
+typedef enum {
+	CMU_AUTO_CALIB_INPUT_LOSE = 0x0U,	/**< LOSC */
+	CMU_AUTO_CALIB_INPUT_HOSE = 0x1U,	/**< HOSC */
 } cmu_auto_calib_input_t;
 
 /**
   * @brief Auto-calibrate output
   */
-typedef enum
-{
-    CMU_AUTO_CALIB_OUTPUT_24M = 0x0,
-    CMU_AUTO_CALIB_OUTPUT_2M  = 0x1,
+typedef enum {
+	CMU_AUTO_CALIB_OUTPUT_24M = 0x0U,	/**< HOSC 24MHz */
+	CMU_AUTO_CALIB_OUTPUT_2M  = 0x1U,	/**< HOSC 2MHz */
 } cmu_auto_calib_output_t;
 
+/**
+  * @brief Safe clock source type
+  */
+typedef enum {
+	CMU_SAFE_CLK_HOSC = 0x0U,	/**< HOSC */
+	CMU_SAFE_CLK_LOSC = 0x1U,	/**< LOSC */
+	CMU_SAFE_CLK_PLL  = 0x2U,	/**< PLL */
+} cmu_clock_safe_type_t;
+
 /**
   * @brief Frequency division select bit
   */
-typedef enum
-{
-    CMU_DIV_1    = 0x0,		/**< Division by 1 */
-    CMU_DIV_2    = 0x1,		/**< Division by 2 */
-    CMU_DIV_4    = 0x2,		/**< Division by 4 */
-    CMU_DIV_8    = 0x3,		/**< Division by 8 */
-    CMU_DIV_16   = 0x4,		/**< Division by 16 */
-    CMU_DIV_32   = 0x5,		/**< Division by 32 */
-    CMU_DIV_64   = 0x6,		/**< Division by 64 */
-    CMU_DIV_128  = 0x7,		/**< Division by 128 */
-    CMU_DIV_256  = 0x8,		/**< Division by 256 */
-    CMU_DIV_512  = 0x9,		/**< Division by 512 */
-    CMU_DIV_1024 = 0xA,		/**< Division by 1024 */
-    CMU_DIV_2048 = 0xB,		/**< Division by 2048 */
-    CMU_DIV_4096 = 0xC,		/**< Division by 4096 */
+typedef enum {
+	CMU_DIV_1    = 0x0U,	/**< Division by 1 */
+	CMU_DIV_2    = 0x1U,	/**< Division by 2 */
+	CMU_DIV_4    = 0x2U,	/**< Division by 4 */
+	CMU_DIV_8    = 0x3U,	/**< Division by 8 */
+	CMU_DIV_16   = 0x4U,	/**< Division by 16 */
+	CMU_DIV_32   = 0x5U,	/**< Division by 32 */
+	CMU_DIV_64   = 0x6U,	/**< Division by 64 */
+	CMU_DIV_128  = 0x7U,	/**< Division by 128 */
+	CMU_DIV_256  = 0x8U,	/**< Division by 256 */
+	CMU_DIV_512  = 0x9U,	/**< Division by 512 */
+	CMU_DIV_1024 = 0xAU,	/**< Division by 1024 */
+	CMU_DIV_2048 = 0xBU,	/**< Division by 2048 */
+	CMU_DIV_4096 = 0xCU,	/**< Division by 4096 */
 } cmu_div_t;
 
 /**
   * @brief Bus type
   */
-typedef enum
-{
-    CMU_HCLK_1 = 0x0,		/**< AHB1 bus */
-    CMU_SYS    = 0x1,		/**< SYS bus */
-    CMU_PCLK_1 = 0x2,		/**< APB1 bus */
-    CMU_PCLK_2 = 0x3,		/**< APB2 bus */
+typedef enum {
+	CMU_HCLK_1 = 0x0U,	/**< AHB1 bus */
+	CMU_SYS    = 0x1U,	/**< SYS bus */
+	CMU_PCLK_1 = 0x2U,	/**< APB1 bus */
+	CMU_PCLK_2 = 0x3U,	/**< APB2 bus */
 } cmu_bus_t;
 
 /**
   * @brief Output high clock select
   */
-typedef enum
-{
-    CMU_OUTPUT_HIGH_SEL_HOSC   = 0x0,	/**< Select HOSC */
-    CMU_OUTPUT_HIGH_SEL_LOSC   = 0x1,	/**< Select LOSC */
-    CMU_OUTPUT_HIGH_SEL_HRC    = 0x2,	/**< Select HRC */
-    CMU_OUTPUT_HIGH_SEL_LRC    = 0x3,	/**< Select LRC */
-    CMU_OUTPUT_HIGH_SEL_HOSM   = 0x4,	/**< Select HOSM */
-    CMU_OUTPUT_HIGH_SEL_PLL1   = 0x5,	/**< Select PLL1 */
-    CMU_OUTPUT_HIGH_SEL_PLL2   = 0x6,	/**< Select PLL2 */
-    CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7,	/**< Select SYSCLK */
+typedef enum {
+	CMU_OUTPUT_HIGH_SEL_HOSC   = 0x0U,	/**< Select HOSC */
+	CMU_OUTPUT_HIGH_SEL_LOSC   = 0x1U,	/**< Select LOSC */
+	CMU_OUTPUT_HIGH_SEL_HRC    = 0x2U,	/**< Select HRC */
+	CMU_OUTPUT_HIGH_SEL_LRC    = 0x3U,	/**< Select LRC */
+	CMU_OUTPUT_HIGH_SEL_HOSM   = 0x4U,	/**< Select HOSM */
+	CMU_OUTPUT_HIGH_SEL_PLL1   = 0x5U,	/**< Select PLL1 */
+	CMU_OUTPUT_HIGH_SEL_PLL2   = 0x6U,	/**< Select PLL2 */
+	CMU_OUTPUT_HIGH_SEL_SYSCLK = 0x7U,	/**< Select SYSCLK */
 } cmu_output_high_sel_t;
 
 /**
   * @brief Output frequency division
   */
-typedef enum
-{
-    CMU_OUTPUT_DIV_1   = 0x0,	/**< Division by 1 */
-    CMU_OUTPUT_DIV_2   = 0x1,	/**< Division by 2 */
-    CMU_OUTPUT_DIV_4   = 0x2,	/**< Division by 4 */
-    CMU_OUTPUT_DIV_8   = 0x3,	/**< Division by 8 */
-    CMU_OUTPUT_DIV_16  = 0x4,	/**< Division by 16 */
-    CMU_OUTPUT_DIV_32  = 0x5,	/**< Division by 32 */
-    CMU_OUTPUT_DIV_64  = 0x6,	/**< Division by 64 */
-    CMU_OUTPUT_DIV_128 = 0x7,	/**< Division by 128 */
+typedef enum {
+	CMU_OUTPUT_DIV_1   = 0x0U,	/**< Division by 1 */
+	CMU_OUTPUT_DIV_2   = 0x1U,	/**< Division by 2 */
+	CMU_OUTPUT_DIV_4   = 0x2U,	/**< Division by 4 */
+	CMU_OUTPUT_DIV_8   = 0x3U,	/**< Division by 8 */
+	CMU_OUTPUT_DIV_16  = 0x4U,	/**< Division by 16 */
+	CMU_OUTPUT_DIV_32  = 0x5U,	/**< Division by 32 */
+	CMU_OUTPUT_DIV_64  = 0x6U,	/**< Division by 64 */
+	CMU_OUTPUT_DIV_128 = 0x7U,	/**< Division by 128 */
 } cmu_output_high_div_t;
 
 /**
   * @brief Output low clock select
   */
-typedef enum
-{
-    CMU_OUTPUT_LOW_SEL_LOSC = 0x0,	/**< Select LOSC */
-    CMU_OUTPUT_LOW_SEL_LRC  = 0x1,	/**< Select LRC */
-    CMU_OUTPUT_LOW_SEL_LOSM = 0x2,	/**< Select LOSM */
-    CMU_OUTPUT_LOW_SEL_BUZZ = 0x3,	/**< Select BUZZ */
-    CMU_OUTPUT_LOW_SEL_ULRC = 0x4,	/**< Select ULRC */
+typedef enum {
+	CMU_OUTPUT_LOW_SEL_LOSC = 0x0U,	/**< Select LOSC */
+	CMU_OUTPUT_LOW_SEL_LRC  = 0x1U,	/**< Select LRC */
+	CMU_OUTPUT_LOW_SEL_LOSM = 0x2U,	/**< Select LOSM */
+	CMU_OUTPUT_LOW_SEL_BUZZ = 0x3U,	/**< Select BUZZ */
+	CMU_OUTPUT_LOW_SEL_ULRC = 0x4U,	/**< Select ULRC */
 } cmu_output_low_sel_t;
 
 /**
   * @brief BUZZ frequency division
   */
-typedef enum
-{
-    CMU_BUZZ_DIV_2   = 0x0,		/**< Division by 2 */
-    CMU_BUZZ_DIV_4   = 0x1,		/**< Division by 4 */
-    CMU_BUZZ_DIV_8   = 0x2,		/**< Division by 8 */
-    CMU_BUZZ_DIV_16  = 0x3,		/**< Division by 16 */
-    CMU_BUZZ_DIV_32  = 0x4,		/**< Division by 32 */
-    CMU_BUZZ_DIV_64  = 0x5,		/**< Division by 64 */
-    CMU_BUZZ_DIV_128 = 0x6,		/**< Division by 128 */
-    CMU_BUZZ_DIV_256 = 0x7,		/**< Division by 256 */
+typedef enum {
+	CMU_BUZZ_DIV_2   = 0x0U,	/**< Division by 2 */
+	CMU_BUZZ_DIV_4   = 0x1U,	/**< Division by 4 */
+	CMU_BUZZ_DIV_8   = 0x2U,	/**< Division by 8 */
+	CMU_BUZZ_DIV_16  = 0x3U,	/**< Division by 16 */
+	CMU_BUZZ_DIV_32  = 0x4U,	/**< Division by 32 */
+	CMU_BUZZ_DIV_64  = 0x5U,	/**< Division by 64 */
+	CMU_BUZZ_DIV_128 = 0x6U,	/**< Division by 128 */
+	CMU_BUZZ_DIV_256 = 0x7U,	/**< Division by 256 */
 } cmu_buzz_div_t;
 
 /**
   * @brief Low power peripheral clock select
   */
-typedef enum
-{
-    CMU_LP_PERH_CLOCK_SEL_PCLK2   = 0x0,	/**< Select PCLK2 */
-    CMU_LP_PERH_CLOCK_SEL_PLL1    = 0x1,	/**< Select PLL1 */
-    CMU_LP_PERH_CLOCK_SEL_PLL2    = 0x2,	/**< Select PLL2 */
-    CMU_LP_PERH_CLOCK_SEL_HRC     = 0x3,	/**< Select HRC */
-    CMU_LP_PERH_CLOCK_SEL_HOSC    = 0x4,	/**< Select HOSC */
-    CMU_LP_PERH_CLOCK_SEL_LRC     = 0x5,	/**< Select LRC */
-    CMU_LP_PERH_CLOCK_SEL_LOSC    = 0x6,	/**< Select LOSC */
-    CMU_LP_PERH_CLOCK_SEL_ULRC    = 0x7,	/**< Select ULRC */
-    CMU_LP_PERH_CLOCK_SEL_HRC_1M  = 0x8,	/**< Select HRC down to 1MHz */
-    CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9,	/**< Select HOSC down to 1MHz  */
-    CMU_LP_PERH_CLOCK_SEL_LOSM    = 0xA,	/**< Select LOSM */
-    CMU_LP_PERH_CLOCK_SEL_HOSM    = 0xB,	/**< Select HOSM */
+typedef enum {
+	CMU_LP_PERH_CLOCK_SEL_PCLK2   = 0x0U,	/**< Select PCLK2 */
+	CMU_LP_PERH_CLOCK_SEL_PLL1    = 0x1U,	/**< Select PLL1 */
+	CMU_LP_PERH_CLOCK_SEL_PLL2    = 0x2U,	/**< Select PLL2 */
+	CMU_LP_PERH_CLOCK_SEL_HRC     = 0x3U,	/**< Select HRC */
+	CMU_LP_PERH_CLOCK_SEL_HOSC    = 0x4U,	/**< Select HOSC */
+	CMU_LP_PERH_CLOCK_SEL_LRC     = 0x5U,	/**< Select LRC */
+	CMU_LP_PERH_CLOCK_SEL_LOSC    = 0x6U,	/**< Select LOSC */
+	CMU_LP_PERH_CLOCK_SEL_ULRC    = 0x7U,	/**< Select ULRC */
+	CMU_LP_PERH_CLOCK_SEL_HRC_1M  = 0x8U,	/**< Select HRC down to 1MHz */
+	CMU_LP_PERH_CLOCK_SEL_HOSC_1M = 0x9U,	/**< Select HOSC down to 1MHz  */
+	CMU_LP_PERH_CLOCK_SEL_LOSM    = 0xAU,	/**< Select LOSM */
+	CMU_LP_PERH_CLOCK_SEL_HOSM    = 0xBU,	/**< Select HOSM */
 } cmu_lp_perh_clock_sel_t;
 
 /**
   * @brief LCD clock select
   */
-typedef enum
-{
-    CMU_LCD_SEL_LOSM    = 0x0,	/**< Select LOSM */
-    CMU_LCD_SEL_LOSC    = 0x1,	/**< Select LOSC */
-    CMU_LCD_SEL_LRC     = 0x2,	/**< Select LRC */
-    CMU_LCD_SEL_ULRC    = 0x3,	/**< Select ULRC */
-    CMU_LCD_SEL_HRC_1M  = 0x4,	/**< Select HRC down to 1MHz */
-    CMU_LCD_SEL_HOSC_1M = 0x5,	/**< Select HOSC down to 1MHz */
+typedef enum {
+	CMU_LCD_SEL_LOSM    = 0x0U,	/**< Select LOSM */
+	CMU_LCD_SEL_LOSC    = 0x1U,	/**< Select LOSC */
+	CMU_LCD_SEL_LRC     = 0x2U,	/**< Select LRC */
+	CMU_LCD_SEL_ULRC    = 0x3U,	/**< Select ULRC */
+	CMU_LCD_SEL_HRC_1M  = 0x4U,	/**< Select HRC down to 1MHz */
+	CMU_LCD_SEL_HOSC_1M = 0x5U,	/**< Select HOSC down to 1MHz */
 } cmu_lcd_clock_sel_t;
 
 /**
   * @brief Peripheral clock enable/disable
-  * @note  ES32F065x:
-  *          AD16C4T0--TIMER0
-  *          GP16C4T0--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  *
-  *        ES32F033x:
-  *        ES32F093x:
-  *          GP16C4T0--TIMER0
-  *          GP16C4T1--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  */
-typedef enum
-{
-    CMU_PERH_GPIO    = (1U << 0),			/**< GPIO */
-    CMU_PERH_CRC     = (1U << 1),			/**< CRC */
-    CMU_PERH_CALC    = (1U << 2),			/**< CALC */
-    CMU_PERH_CRYPT   = (1U << 3),			/**< CRYPT */
-    CMU_PERH_TRNG    = (1U << 4),			/**< TRNG */
-    CMU_PERH_PIS     = (1U << 5),			/**< PIS */
-    CMU_PERH_TIMER0  = (1U << 0)  | (1U << 27),	/**< TIMER0 */
-    CMU_PERH_TIMER1  = (1U << 1)  | (1U << 27),	/**< TIMER1 */
-    CMU_PERH_TIMER2  = (1U << 2)  | (1U << 27),	/**< TIMER2 */
-    CMU_PERH_TIMER3  = (1U << 3)  | (1U << 27),	/**< TIMER3 */
-    CMU_PERH_TIMER4  = (1U << 4)  | (1U << 27),	/**< TIMER4 */
-    CMU_PERH_TIMER5  = (1U << 5)  | (1U << 27),	/**< TIMER5 */
-    CMU_PERH_TIMER6  = (1U << 6)  | (1U << 27),	/**< TIMER6 */
-    CMU_PERH_TIMER7  = (1U << 7)  | (1U << 27),	/**< TIMER7 */
-    CMU_PERH_UART0   = (1U << 8)  | (1U << 27),	/**< UART0 */
-    CMU_PERH_UART1   = (1U << 9)  | (1U << 27),	/**< UART1 */
-    CMU_PERH_UART2   = (1U << 10) | (1U << 27),	/**< UART2 */
-    CMU_PERH_UART3   = (1U << 11) | (1U << 27),	/**< UART3 */
-    CMU_PERH_USART0  = (1U << 12) | (1U << 27),	/**< USART0 */
-    CMU_PERH_USART1  = (1U << 13) | (1U << 27),	/**< USART1 */
-    CMU_PERH_SPI0    = (1U << 16) | (1U << 27),	/**< SPI0 */
-    CMU_PERH_SPI1    = (1U << 17) | (1U << 27),	/**< SPI1 */
-    CMU_PERH_SPI2    = (1U << 18) | (1U << 27),	/**< SPI2 */
-    CMU_PERH_I2C0    = (1U << 20) | (1U << 27),	/**< I2C0 */
-    CMU_PERH_I2C1    = (1U << 21) | (1U << 27),	/**< I2C1 */
-    CMU_PERH_CAN     = (1U << 24) | (1U << 27),	/**< CAN */
-    CMU_PERH_LPTIM0  = (1U << 0)  | (1U << 28),	/**< LPTIM0 */
-    CMU_PERH_LPUART0 = (1U << 2)  | (1U << 28),	/**< LPUART0 */
-    CMU_PERH_ADC0    = (1U << 4)  | (1U << 28),	/**< ADC0 */
-    CMU_PERH_ADC1    = (1U << 5)  | (1U << 28),	/**< ADC1 */
-    CMU_PERH_ACMP0   = (1U << 6)  | (1U << 28),	/**< ACMP0 */
-    CMU_PERH_ACMP1   = (1U << 7)  | (1U << 28),	/**< ACMP1 */
-    CMU_PERH_OPAMP   = (1U << 8)  | (1U << 28),	/**< OPAMP */
-    CMU_PERH_DAC0    = (1U << 9)  | (1U << 28),	/**< DAC0 */
-    CMU_PERH_WWDT    = (1U << 12) | (1U << 28),	/**< WWDT */
-    CMU_PERH_LCD     = (1U << 13) | (1U << 28),	/**< LCD */
-    CMU_PERH_IWDT    = (1U << 14) | (1U << 28),	/**< IWDT */
-    CMU_PERH_RTC     = (1U << 15) | (1U << 28),	/**< RTC */
-    CMU_PERH_TSENSE  = (1U << 16) | (1U << 28),	/**< TSENSE */
-    CMU_PERH_BKPC    = (1U << 17) | (1U << 28),	/**< BKPC */
-    CMU_PERH_BKRPAM  = (1U << 18) | (1U << 28),	/**< BKPRAM */
-    CMU_PERH_DBGC    = (1U << 19) | (1U << 28),	/**< DBGC */
-    CMU_PERH_ALL     = (0x7FFFFFFF),		/**< ALL */
+  * @verbatim
+      In this module, for the convenience of code maintenance,
+      TIMERx is used to indicate the sequence of the timer peripheral.
+      Different product series TIMERx represent different meanings:
+      1. For ES32F065x series:
+      TIMER0 ----> AD16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+      TIMER4 ----> BS16T1
+      TIMER5 ----> BS16T2
+      TIMER6 ----> GP16C4T0
+      TIMER7 ----> BS16T3
+     
+      2. For ES32F033x/ES32F093x series:
+      TIMER0 ----> GP16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+      TIMER4 ----> BS16T1
+      TIMER5 ----> BS16T2
+      TIMER6 ----> GP16C4T1
+      TIMER7 ----> BS16T3
+    @endverbatim
+  */
+typedef enum {
+	CMU_PERH_GPIO    = (1U << 0),			/**< GPIO */
+	CMU_PERH_CRC     = (1U << 1),			/**< CRC */
+	CMU_PERH_CALC    = (1U << 2),			/**< CALC */
+	CMU_PERH_CRYPT   = (1U << 3),			/**< CRYPT */
+	CMU_PERH_TRNG    = (1U << 4),			/**< TRNG */
+	CMU_PERH_PIS     = (1U << 5),			/**< PIS */
+	CMU_PERH_TIMER0  = (1U << 0)  | (1U << 27),	/**< TIMER0 */
+	CMU_PERH_TIMER1  = (1U << 1)  | (1U << 27),	/**< TIMER1 */
+	CMU_PERH_TIMER2  = (1U << 2)  | (1U << 27),	/**< TIMER2 */
+	CMU_PERH_TIMER3  = (1U << 3)  | (1U << 27),	/**< TIMER3 */
+	CMU_PERH_TIMER4  = (1U << 4)  | (1U << 27),	/**< TIMER4 */
+	CMU_PERH_TIMER5  = (1U << 5)  | (1U << 27),	/**< TIMER5 */
+	CMU_PERH_TIMER6  = (1U << 6)  | (1U << 27),	/**< TIMER6 */
+	CMU_PERH_TIMER7  = (1U << 7)  | (1U << 27),	/**< TIMER7 */
+	CMU_PERH_UART0   = (1U << 8)  | (1U << 27),	/**< UART0 */
+	CMU_PERH_UART1   = (1U << 9)  | (1U << 27),	/**< UART1 */
+	CMU_PERH_UART2   = (1U << 10) | (1U << 27),	/**< UART2 */
+	CMU_PERH_UART3   = (1U << 11) | (1U << 27),	/**< UART3 */
+	CMU_PERH_USART0  = (1U << 12) | (1U << 27),	/**< USART0 */
+	CMU_PERH_USART1  = (1U << 13) | (1U << 27),	/**< USART1 */
+	CMU_PERH_SPI0    = (1U << 16) | (1U << 27),	/**< SPI0 */
+	CMU_PERH_SPI1    = (1U << 17) | (1U << 27),	/**< SPI1 */
+	CMU_PERH_SPI2    = (1U << 18) | (1U << 27),	/**< SPI2 */
+	CMU_PERH_I2C0    = (1U << 20) | (1U << 27),	/**< I2C0 */
+	CMU_PERH_I2C1    = (1U << 21) | (1U << 27),	/**< I2C1 */
+	CMU_PERH_CAN     = (1U << 24) | (1U << 27),	/**< CAN */
+	CMU_PERH_LPTIM0  = (1U << 0)  | (1U << 28),	/**< LPTIM0 */
+	CMU_PERH_LPUART0 = (1U << 2)  | (1U << 28),	/**< LPUART0 */
+	CMU_PERH_ADC0    = (1U << 4)  | (1U << 28),	/**< ADC0 */
+	CMU_PERH_ADC1    = (1U << 5)  | (1U << 28),	/**< ADC1 */
+	CMU_PERH_ACMP0   = (1U << 6)  | (1U << 28),	/**< ACMP0 */
+	CMU_PERH_ACMP1   = (1U << 7)  | (1U << 28),	/**< ACMP1 */
+	CMU_PERH_OPAMP   = (1U << 8)  | (1U << 28),	/**< OPAMP */
+	CMU_PERH_DAC0    = (1U << 9)  | (1U << 28),	/**< DAC0 */
+	CMU_PERH_WWDT    = (1U << 12) | (1U << 28),	/**< WWDT */
+	CMU_PERH_LCD     = (1U << 13) | (1U << 28),	/**< LCD */
+	CMU_PERH_IWDT    = (1U << 14) | (1U << 28),	/**< IWDT */
+	CMU_PERH_RTC     = (1U << 15) | (1U << 28),	/**< RTC */
+	CMU_PERH_TSENSE  = (1U << 16) | (1U << 28),	/**< TSENSE */
+	CMU_PERH_BKPC    = (1U << 17) | (1U << 28),	/**< BKPC */
+	CMU_PERH_DBGC    = (1U << 19) | (1U << 28),	/**< DBGC */
+	CMU_PERH_ALL     = (0x7FFFFFFF),		/**< ALL */
 } cmu_perh_t;
 
 /**
   * @brief CMU interrupt type
   */
-typedef enum
-{
-    CMU_LOSC_STOP    = 0x0,	/**< LOSC STOP INTERRUPT */
-    CMU_HOSC_STOP    = 0x1,	/**< HOSC STOP INTERRUPT */
-    CMU_PLL1_UNLOCK  = 0x2,	/**< PLL1 UNLOCK INTERRUPT */
-    CMU_LOSC_START   = 0x3,	/**< LOSC START INTERRUPT */
-    CMU_HOSC_START   = 0x4,	/**< HOSC START INTERRUPT */
+typedef enum {
+	CMU_LOSC_STOP    = 0x0U,	/**< LOSC STOP INTERRUPT */
+	CMU_HOSC_STOP    = 0x1U,	/**< HOSC STOP INTERRUPT */
+	CMU_PLL1_UNLOCK  = 0x2U,	/**< PLL1 UNLOCK INTERRUPT */
+	CMU_LOSC_START   = 0x3U,	/**< LOSC START INTERRUPT */
+	CMU_HOSC_START   = 0x4U,	/**< HOSC START INTERRUPT */
 } cmu_security_t;
 
 /**
   * @brief CMU clock state type
   */
-typedef enum
-{
-    CMU_CLOCK_STATE_HOSCACT = (1U << 0),	/**< HOSC active */
-    CMU_CLOCK_STATE_LOSCACT = (1U << 1),	/**< LOSC active */
-    CMU_CLOCK_STATE_HRCACT  = (1U << 2),	/**< HRC active */
-    CMU_CLOCK_STATE_LRCACT  = (1U << 3),	/**< LRC active */
-    CMU_CLOCK_STATE_ULRCACT = (1U << 4),	/**< ULRC active */
-    CMU_CLOCK_STATE_PLLACT  = (1U << 8),	/**< PLL active */
-    CMU_CLOCK_STATE_HOSCRDY = (1U << 16),	/**< HOSC ready */
-    CMU_CLOCK_STATE_LOSCRDY = (1U << 17),	/**< LOSC ready */
-    CMU_CLOCK_STATE_HRCRDY  = (1U << 18),	/**< HRC ready */
-    CMU_CLOCK_STATE_LRCRDY  = (1U << 19),	/**< LRC ready */
-    CMU_CLOCK_STATE_PLLRDY  = (1U << 24),	/**< PLL ready */
+typedef enum {
+	CMU_CLOCK_STATE_HOSCACT = (1U << 0),	/**< HOSC active */
+	CMU_CLOCK_STATE_LOSCACT = (1U << 1),	/**< LOSC active */
+	CMU_CLOCK_STATE_HRCACT  = (1U << 2),	/**< HRC active */
+	CMU_CLOCK_STATE_LRCACT  = (1U << 3),	/**< LRC active */
+	CMU_CLOCK_STATE_ULRCACT = (1U << 4),	/**< ULRC active */
+	CMU_CLOCK_STATE_PLLACT  = (1U << 8),	/**< PLL active */
+	CMU_CLOCK_STATE_HOSCRDY = (1U << 16),	/**< HOSC ready */
+	CMU_CLOCK_STATE_LOSCRDY = (1U << 17),	/**< LOSC ready */
+	CMU_CLOCK_STATE_HRCRDY  = (1U << 18),	/**< HRC ready */
+	CMU_CLOCK_STATE_LRCRDY  = (1U << 19),	/**< LRC ready */
+	CMU_CLOCK_STATE_PLLRDY  = (1U << 24),	/**< PLL ready */
 } cmu_clock_state_t;
 /**
   * @}
@@ -424,10 +419,10 @@ typedef enum
   * @{
   */
 #define IS_CMU_CLOCK(x)		(((x) == CMU_CLOCK_HRC)  || \
-                             ((x) == CMU_CLOCK_LRC)  || \
-                             ((x) == CMU_CLOCK_LOSC) || \
-                             ((x) == CMU_CLOCK_PLL1) || \
-                             ((x) == CMU_CLOCK_HOSC))
+                                 ((x) == CMU_CLOCK_LRC)  || \
+                                 ((x) == CMU_CLOCK_LOSC) || \
+                                 ((x) == CMU_CLOCK_PLL1) || \
+                                 ((x) == CMU_CLOCK_HOSC))
 #define IS_CMU_PLL1_OUTPUT(x)	(((x) == CMU_PLL1_OUTPUT_32M) || \
                                  ((x) == CMU_PLL1_OUTPUT_48M))
 #define IS_CMU_PLL1_INPUT(x)	(((x) == CMU_PLL1_INPUT_HRC_6)  || \
@@ -444,67 +439,70 @@ typedef enum
                                  ((x) == CMU_HOSC_16M) || \
                                  ((x) == CMU_HOSC_24M))
 #define IS_CMU_DIV(x)		(((x) == CMU_DIV_1)    || \
-                             ((x) == CMU_DIV_2)    || \
-                             ((x) == CMU_DIV_4)    || \
-                             ((x) == CMU_DIV_8)    || \
-                             ((x) == CMU_DIV_16)   || \
-                             ((x) == CMU_DIV_32)   || \
-                             ((x) == CMU_DIV_64)   || \
-                             ((x) == CMU_DIV_128)  || \
-                             ((x) == CMU_DIV_256)  || \
-                             ((x) == CMU_DIV_512)  || \
-                             ((x) == CMU_DIV_1024) || \
-                             ((x) == CMU_DIV_2048) || \
-                             ((x) == CMU_DIV_4096))
+                                 ((x) == CMU_DIV_2)    || \
+                                 ((x) == CMU_DIV_4)    || \
+                                 ((x) == CMU_DIV_8)    || \
+                                 ((x) == CMU_DIV_16)   || \
+                                 ((x) == CMU_DIV_32)   || \
+                                 ((x) == CMU_DIV_64)   || \
+                                 ((x) == CMU_DIV_128)  || \
+                                 ((x) == CMU_DIV_256)  || \
+                                 ((x) == CMU_DIV_512)  || \
+                                 ((x) == CMU_DIV_1024) || \
+                                 ((x) == CMU_DIV_2048) || \
+                                 ((x) == CMU_DIV_4096))
 #define IS_CMU_BUS(x)		(((x) == CMU_HCLK_1) || \
-                             ((x) == CMU_SYS)    || \
-                             ((x) == CMU_PCLK_1) || \
-                             ((x) == CMU_PCLK_2))
+                                 ((x) == CMU_SYS)    || \
+                                 ((x) == CMU_PCLK_1) || \
+                                 ((x) == CMU_PCLK_2))
 #define IS_CMU_OUTPUT_HIGH_SEL(x)	(((x) == CMU_OUTPUT_HIGH_SEL_HOSC) || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_HRC)  || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_LRC)  || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \
-                                     ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK))
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_LOSC) || \
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_HRC)  || \
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_LRC)  || \
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_HOSM) || \
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_PLL1) || \
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_PLL2) || \
+                                         ((x) == CMU_OUTPUT_HIGH_SEL_SYSCLK))
 #define IS_CMU_OUTPUT_HIGH_DIV(x)	(((x) == CMU_OUTPUT_DIV_1)  || \
-                                     ((x) == CMU_OUTPUT_DIV_2)  || \
-                                     ((x) == CMU_OUTPUT_DIV_4)  || \
-                                     ((x) == CMU_OUTPUT_DIV_8)  || \
-                                     ((x) == CMU_OUTPUT_DIV_16) || \
-                                     ((x) == CMU_OUTPUT_DIV_32) || \
-                                     ((x) == CMU_OUTPUT_DIV_64) || \
-                                     ((x) == CMU_OUTPUT_DIV_128))
+                                         ((x) == CMU_OUTPUT_DIV_2)  || \
+                                         ((x) == CMU_OUTPUT_DIV_4)  || \
+                                         ((x) == CMU_OUTPUT_DIV_8)  || \
+                                         ((x) == CMU_OUTPUT_DIV_16) || \
+                                         ((x) == CMU_OUTPUT_DIV_32) || \
+                                         ((x) == CMU_OUTPUT_DIV_64) || \
+                                         ((x) == CMU_OUTPUT_DIV_128))
 #define IS_CMU_OUTPUT_LOW_SEL(x)	(((x) == CMU_OUTPUT_LOW_SEL_LOSC) || \
-                                     ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \
-                                     ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \
-                                     ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \
-                                     ((x) == CMU_OUTPUT_LOW_SEL_ULRC))
+                                         ((x) == CMU_OUTPUT_LOW_SEL_LRC ) || \
+                                         ((x) == CMU_OUTPUT_LOW_SEL_LOSM) || \
+                                         ((x) == CMU_OUTPUT_LOW_SEL_BUZZ) || \
+                                         ((x) == CMU_OUTPUT_LOW_SEL_ULRC))
 #define IS_CMU_AUTO_CALIB_INPUT(x)	(((x) == CMU_AUTO_CALIB_INPUT_LOSE) || \
-                                     ((x) == CMU_AUTO_CALIB_INPUT_HOSE))
+                                         ((x) == CMU_AUTO_CALIB_INPUT_HOSE))
 #define IS_CMU_AUTO_CALIB_OUTPUT(x)	(((x) == CMU_AUTO_CALIB_OUTPUT_24M) || \
-                                     ((x) == CMU_AUTO_CALIB_OUTPUT_2M))
+                                         ((x) == CMU_AUTO_CALIB_OUTPUT_2M))
+#define IS_CMU_SAFE_CLOCK_TYPE(x)	(((x) == CMU_SAFE_CLK_HOSC) || \
+                                         ((x) == CMU_SAFE_CLK_LOSC) || \
+                                         ((x) == CMU_SAFE_CLK_PLL))
 #define IS_CMU_BUZZ_DIV(x)	(((x) == CMU_BUZZ_DIV_2)   || \
-                             ((x) == CMU_BUZZ_DIV_4)   || \
-                             ((x) == CMU_BUZZ_DIV_8)   || \
-                             ((x) == CMU_BUZZ_DIV_16)  || \
-                             ((x) == CMU_BUZZ_DIV_32)  || \
-                             ((x) == CMU_BUZZ_DIV_64)  || \
-                             ((x) == CMU_BUZZ_DIV_128) || \
-                             ((x) == CMU_BUZZ_DIV_256))
+                                 ((x) == CMU_BUZZ_DIV_4)   || \
+                                 ((x) == CMU_BUZZ_DIV_8)   || \
+                                 ((x) == CMU_BUZZ_DIV_16)  || \
+                                 ((x) == CMU_BUZZ_DIV_32)  || \
+                                 ((x) == CMU_BUZZ_DIV_64)  || \
+                                 ((x) == CMU_BUZZ_DIV_128) || \
+                                 ((x) == CMU_BUZZ_DIV_256))
 #define IS_CMU_LP_PERH_CLOCK_SEL(x)	(((x) == CMU_LP_PERH_CLOCK_SEL_PCLK2)   || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1)    || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2)    || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_HRC)     || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC)    || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_LRC)     || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC)    || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC)    || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M)  || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM)    || \
-                                     ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM))
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_PLL1)    || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_PLL2)    || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HRC)     || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC)    || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LRC)     || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LOSC)    || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_ULRC)    || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HRC_1M)  || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSC_1M) || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_LOSM)    || \
+                                         ((x) == CMU_LP_PERH_CLOCK_SEL_HOSM))
 #define IS_CMU_LCD_CLOCK_SEL(x)	(((x) == CMU_LCD_SEL_LOSM)   || \
                                  ((x) == CMU_LCD_SEL_LOSC)   || \
                                  ((x) == CMU_LCD_SEL_LRC)    || \
@@ -512,59 +510,58 @@ typedef enum
                                  ((x) == CMU_LCD_SEL_HRC_1M) || \
                                  ((x) == CMU_LCD_SEL_HOSC_1M))
 #define IS_CMU_PERH(x)		(((x) == CMU_PERH_GPIO)    || \
-                             ((x) == CMU_PERH_CRC)     || \
-                             ((x) == CMU_PERH_CALC)    || \
-                             ((x) == CMU_PERH_CRYPT)   || \
-                             ((x) == CMU_PERH_TRNG)    || \
-                             ((x) == CMU_PERH_PIS)     || \
-                             ((x) == CMU_PERH_TIMER0)  || \
-                             ((x) == CMU_PERH_TIMER1)  || \
-                             ((x) == CMU_PERH_TIMER2)  || \
-                             ((x) == CMU_PERH_TIMER3)  || \
-                             ((x) == CMU_PERH_TIMER4)  || \
-                             ((x) == CMU_PERH_TIMER5)  || \
-                             ((x) == CMU_PERH_TIMER6)  || \
-                             ((x) == CMU_PERH_TIMER7)  || \
-                             ((x) == CMU_PERH_UART0)   || \
-                             ((x) == CMU_PERH_UART1)   || \
-                             ((x) == CMU_PERH_UART2)   || \
-                             ((x) == CMU_PERH_UART3)   || \
-                             ((x) == CMU_PERH_USART0)  || \
-                             ((x) == CMU_PERH_USART1)  || \
-                             ((x) == CMU_PERH_SPI0)    || \
-                             ((x) == CMU_PERH_SPI1)    || \
-                             ((x) == CMU_PERH_SPI2)    || \
-                             ((x) == CMU_PERH_I2C0)    || \
-                             ((x) == CMU_PERH_I2C1)    || \
-                             ((x) == CMU_PERH_CAN)     || \
-                             ((x) == CMU_PERH_LPTIM0)  || \
-                             ((x) == CMU_PERH_LPUART0) || \
-                             ((x) == CMU_PERH_ADC0)    || \
-                             ((x) == CMU_PERH_ADC1)    || \
-                             ((x) == CMU_PERH_ACMP0)   || \
-                             ((x) == CMU_PERH_ACMP1)   || \
-                             ((x) == CMU_PERH_OPAMP)   || \
-                             ((x) == CMU_PERH_DAC0)    || \
-                             ((x) == CMU_PERH_WWDT)    || \
-                             ((x) == CMU_PERH_LCD)     || \
-                             ((x) == CMU_PERH_IWDT)    || \
-                             ((x) == CMU_PERH_RTC)     || \
-                             ((x) == CMU_PERH_TSENSE)    || \
-                             ((x) == CMU_PERH_BKPC)    || \
-                             ((x) == CMU_PERH_BKRPAM ) || \
-                             ((x) == CMU_PERH_DBGC)    || \
-                             ((x) == CMU_PERH_ALL))
+                                 ((x) == CMU_PERH_CRC)     || \
+                                 ((x) == CMU_PERH_CALC)    || \
+                                 ((x) == CMU_PERH_CRYPT)   || \
+                                 ((x) == CMU_PERH_TRNG)    || \
+                                 ((x) == CMU_PERH_PIS)     || \
+                                 ((x) == CMU_PERH_TIMER0)  || \
+                                 ((x) == CMU_PERH_TIMER1)  || \
+                                 ((x) == CMU_PERH_TIMER2)  || \
+                                 ((x) == CMU_PERH_TIMER3)  || \
+                                 ((x) == CMU_PERH_TIMER4)  || \
+                                 ((x) == CMU_PERH_TIMER5)  || \
+                                 ((x) == CMU_PERH_TIMER6)  || \
+                                 ((x) == CMU_PERH_TIMER7)  || \
+                                 ((x) == CMU_PERH_UART0)   || \
+                                 ((x) == CMU_PERH_UART1)   || \
+                                 ((x) == CMU_PERH_UART2)   || \
+                                 ((x) == CMU_PERH_UART3)   || \
+                                 ((x) == CMU_PERH_USART0)  || \
+                                 ((x) == CMU_PERH_USART1)  || \
+                                 ((x) == CMU_PERH_SPI0)    || \
+                                 ((x) == CMU_PERH_SPI1)    || \
+                                 ((x) == CMU_PERH_SPI2)    || \
+                                 ((x) == CMU_PERH_I2C0)    || \
+                                 ((x) == CMU_PERH_I2C1)    || \
+                                 ((x) == CMU_PERH_CAN)     || \
+                                 ((x) == CMU_PERH_LPTIM0)  || \
+                                 ((x) == CMU_PERH_LPUART0) || \
+                                 ((x) == CMU_PERH_ADC0)    || \
+                                 ((x) == CMU_PERH_ADC1)    || \
+                                 ((x) == CMU_PERH_ACMP0)   || \
+                                 ((x) == CMU_PERH_ACMP1)   || \
+                                 ((x) == CMU_PERH_OPAMP)   || \
+                                 ((x) == CMU_PERH_DAC0)    || \
+                                 ((x) == CMU_PERH_WWDT)    || \
+                                 ((x) == CMU_PERH_LCD)     || \
+                                 ((x) == CMU_PERH_IWDT)    || \
+                                 ((x) == CMU_PERH_RTC)     || \
+                                 ((x) == CMU_PERH_TSENSE)  || \
+                                 ((x) == CMU_PERH_BKPC)    || \
+                                 ((x) == CMU_PERH_DBGC)    || \
+                                 ((x) == CMU_PERH_ALL))
 #define IS_CMU_CLOCK_STATE(x)	(((x) == CMU_CLOCK_STATE_HOSCACT) || \
                                  ((x) == CMU_CLOCK_STATE_LOSCACT) || \
-                                 ((x) == CMU_CLOCK_STATE_HRCACT) || \
-                                 ((x) == CMU_CLOCK_STATE_LRCACT) || \
-                                 ((x) == CMU_CLOCK_STATE_ULRCACT) || \
-                                 ((x) == CMU_CLOCK_STATE_PLLACT) || \
-                                 ((x) == CMU_CLOCK_STATE_HOSCRDY) || \
-                                 ((x) == CMU_CLOCK_STATE_LOSCRDY) || \
-                                 ((x) == CMU_CLOCK_STATE_HRCRDY) || \
-                                 ((x) == CMU_CLOCK_STATE_LRCRDY) || \
-                                 ((x) == CMU_CLOCK_STATE_PLLRDY))
+				 ((x) == CMU_CLOCK_STATE_HRCACT) || \
+				 ((x) == CMU_CLOCK_STATE_LRCACT) || \
+				 ((x) == CMU_CLOCK_STATE_ULRCACT) || \
+				 ((x) == CMU_CLOCK_STATE_PLLACT) || \
+				 ((x) == CMU_CLOCK_STATE_HOSCRDY) || \
+				 ((x) == CMU_CLOCK_STATE_LOSCRDY) || \
+				 ((x) == CMU_CLOCK_STATE_HRCRDY) || \
+				 ((x) == CMU_CLOCK_STATE_LRCRDY) || \
+				 ((x) == CMU_CLOCK_STATE_PLLRDY))
 /**
   * @}
   */
@@ -605,6 +602,7 @@ uint32_t ald_cmu_get_pclk2_clock(void);
 void ald_cmu_hosc_safe_config(cmu_hosc_range_t clock, type_func_t status);
 void ald_cmu_losc_safe_config(type_func_t status);
 void ald_cmu_pll_safe_config(type_func_t status);
+uint32_t ald_cmu_current_clock_source_get(cmu_clock_safe_type_t type);
 flag_status_t ald_cmu_get_clock_state(cmu_clock_state_t sr);
 void ald_cmu_irq_handler(void);
 void ald_cmu_irq_cbk(cmu_security_t se);
@@ -617,7 +615,7 @@ void ald_cmu_irq_cbk(cmu_security_t se);
   */
 /* Clock output configure */
 void ald_cmu_output_high_clock_config(cmu_output_high_sel_t sel,
-                                      cmu_output_high_div_t div, type_func_t status);
+		cmu_output_high_div_t div, type_func_t status);
 void ald_cmu_output_low_clock_config(cmu_output_low_sel_t sel, type_func_t status);
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crc.h

@@ -18,7 +18,7 @@
 #define __ALD_CRC_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -39,75 +39,69 @@ extern "C" {
 /**
   * @brief CRC mode
   */
-typedef enum
-{
-    CRC_MODE_CCITT = 0,	/**< Ccitt */
-    CRC_MODE_8     = 1,	/**< Crc8 */
-    CRC_MODE_16    = 2,	/**< Crc16 */
-    CRC_MODE_32    = 3,	/**< Crc32 */
+typedef enum {
+	CRC_MODE_CCITT = 0U,	/**< Ccitt */
+	CRC_MODE_8     = 1U,	/**< Crc8 */
+	CRC_MODE_16    = 2U,	/**< Crc16 */
+	CRC_MODE_32    = 3U,	/**< Crc32 */
 } crc_mode_t;
 
 /**
   * @brief CRC input length
   */
-typedef enum
-{
-    CRC_LEN_AUTO    = 0,	/**< Auto */
-    CRC_DATASIZE_8  = 1,	/**< Byte */
-    CRC_DATASIZE_16 = 2,	/**< Half word */
-    CRC_DATASIZE_32 = 3,	/**< Word */
+typedef enum {
+	CRC_LEN_AUTO    = 0U,	/**< Auto */
+	CRC_DATASIZE_8  = 1U,	/**< Byte */
+	CRC_DATASIZE_16 = 2U,	/**< Half word */
+	CRC_DATASIZE_32 = 3U,	/**< Word */
 } crc_datasize_t;
 
 /**
   * @brief CRC whether write error or no
   */
-typedef enum
-{
-    CRC_WERR_NO  = 0,	/**< No error */
-    CRC_WERR_ERR = 1,	/**< Error */
+typedef enum {
+	CRC_WERR_NO  = 0U,	/**< No error */
+	CRC_WERR_ERR = 1U,	/**< Error */
 } crc_werr_t;
 
 /**
   * @brief CRC state structures definition
   */
-typedef enum
-{
-    CRC_STATE_RESET = 0x0,	/**< Peripheral is not initialized */
-    CRC_STATE_READY = 0x1,	/**< Peripheral Initialized and ready for use */
-    CRC_STATE_BUSY  = 0x2,	/**< An internal process is ongoing */
-    CRC_STATE_ERROR = 0x4,	/**< Error */
+typedef enum {
+	CRC_STATE_RESET = 0x0U,	/**< Peripheral is not initialized */
+	CRC_STATE_READY = 0x1U,	/**< Peripheral Initialized and ready for use */
+	CRC_STATE_BUSY  = 0x2U,	/**< An internal process is ongoing */
+	CRC_STATE_ERROR = 0x4U,	/**< Error */
 } crc_state_t;
 
 /**
   * @brief CRC init structure definition
   */
-typedef struct
-{
-    crc_mode_t mode;	/**< CRC mode */
-    type_func_t data_rev;	/**< CRC data reverse or no */
-    type_func_t data_inv;	/**< CRC data inverse or no */
-    type_func_t chs_rev; 	/**< CRC check sum reverse or no */
-    type_func_t chs_inv; 	/**< CRC check sum inverse or no */
-    uint32_t seed;		/**< CRC seed */
+typedef struct {
+	crc_mode_t mode;	/**< CRC mode */
+	type_func_t data_rev;	/**< CRC data reverse or no */
+	type_func_t data_inv;	/**< CRC data inverse or no */
+	type_func_t chs_rev; 	/**< CRC check sum reverse or no */
+	type_func_t chs_inv; 	/**< CRC check sum inverse or no */
+	uint32_t seed;		/**< CRC seed */
 } crc_init_t;
 
 /**
   * @brief  CRC Handle Structure definition
   */
-typedef struct crc_handle_s
-{
-    CRC_TypeDef *perh;	/**< Register base address */
-    crc_init_t init;  	/**< CRC required parameters */
-    uint8_t *cal_buf; 	/**< The pointer of preparing buffer */
-    uint32_t *cal_res;	/**< The pointer of result */
+typedef struct crc_handle_s {
+	CRC_TypeDef *perh;	/**< Register base address */
+	crc_init_t init;  	/**< CRC required parameters */
+	uint8_t *cal_buf; 	/**< The pointer of preparing buffer */
+	uint32_t *cal_res;	/**< The pointer of result */
 #ifdef ALD_DMA
-    dma_handle_t hdma;	/**< CRC DMA handle parameters */
+	dma_handle_t hdma;	/**< CRC DMA handle parameters */
 #endif
-    lock_state_t lock;	/**< Locking object */
-    crc_state_t state;	/**< CRC operation state */
+	lock_state_t lock;	/**< Locking object */
+	crc_state_t state;	/**< CRC operation state */
 
-    void (*cal_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate completed callback */
-    void (*err_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate error callback */
+	void (*cal_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate completed callback */
+	void (*err_cplt_cbk)(struct crc_handle_s *arg);	/**< Calculate error callback */
 } crc_handle_t;
 /**
   * @}
@@ -131,9 +125,9 @@ typedef struct crc_handle_s
   */
 #define IS_CRC(x) 	((x) == CRC)
 #define IS_CRC_MODE(x) 	(((x) == CRC_MODE_CCITT) || \
-                         ((x) == CRC_MODE_8)     || \
-                         ((x) == CRC_MODE_16)    || \
-                         ((x) == CRC_MODE_32))
+			 ((x) == CRC_MODE_8)     || \
+			 ((x) == CRC_MODE_16)    || \
+			 ((x) == CRC_MODE_32))
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_crypt.h

@@ -18,7 +18,7 @@
 #define __ALD_CRYPT_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -39,105 +39,96 @@ extern "C" {
 /**
   * @brief CRYPT encrypt or decrypt select
   */
-typedef enum
-{
-    CRYPT_DECRYPT = 0,	/**< Decrypt */
-    CRYPT_ENCRYPT = 1,	/**< Encrypt */
+typedef enum {
+	CRYPT_DECRYPT = 0U,	/**< Decrypt */
+	CRYPT_ENCRYPT = 1U,	/**< Encrypt */
 } crypt_encs_t;
 
 /**
   * @brief CRYPT mode select
   */
-typedef enum
-{
-    CRYPT_MODE_ECB = 0,	/**< ECB */
-    CRYPT_MODE_CBC = 1,	/**< CBC */
-    CRYPT_MODE_CTR = 2,	/**< CTR */
+typedef enum {
+	CRYPT_MODE_ECB = 0U,	/**< ECB */
+	CRYPT_MODE_CBC = 1U,	/**< CBC */
+	CRYPT_MODE_CTR = 2U,	/**< CTR */
 } crypt_mode_t;
 
 /**
   * @brief CRYPT data type
   */
-typedef enum
-{
-    CRYPT_DATA_CHANGE_NO = 0,	/**< No exchange */
-    CRYPT_DATA_CHANGE_16 = 1,	/**< 16bit exchange */
-    CRYPT_DATA_CHANGE_8  = 2,	/**< 8bit exchange */
-    CRYPT_DATA_CHANGE_1  = 3,	/**< 1bit exchange */
+typedef enum {
+	CRYPT_DATA_CHANGE_NO = 0U,	/**< No exchange */
+	CRYPT_DATA_CHANGE_16 = 1U,	/**< 16bit exchange */
+	CRYPT_DATA_CHANGE_8  = 2U,	/**< 8bit exchange */
+	CRYPT_DATA_CHANGE_1  = 3U,	/**< 1bit exchange */
 } crypt_datatype_t;
 
 /**
   * @brief CRYPT interrupt
   */
-typedef enum
-{
-    CRYPT_IT_IT = 0x80,	/**< Interrupt */
+typedef enum {
+	CRYPT_IT_IT = 0x80U,	/**< Interrupt */
 } crypt_it_t;
 
 /**
   * @brief CRYPT interrupt flag
   */
-typedef enum
-{
-    CRYPT_FLAG_AESIF = 0x1,  	/**< Aes flag */
-    CRYPT_FLAG_DONE  = 0x100,	/**< Complete flag */
+typedef enum {
+	CRYPT_FLAG_AESIF = 0x1U,  	/**< Aes flag */
+	CRYPT_FLAG_DONE  = 0x100U,	/**< Complete flag */
 } crypt_flag_t;
 
 /**
   * @brief CRYPT state structures definition
   */
-typedef enum
-{
-    CRYPT_STATE_RESET = 0x0,	/**< Peripheral is not initialized */
-    CRYPT_STATE_READY = 0x1,	/**< Peripheral Initialized and ready for use */
-    CRYPT_STATE_BUSY  = 0x2,	/**< An internal process is ongoing */
-    CRYPT_STATE_ERROR = 0x4,	/**< Error */
+typedef enum {
+	CRYPT_STATE_RESET = 0x0U,	/**< Peripheral is not initialized */
+	CRYPT_STATE_READY = 0x1U,	/**< Peripheral Initialized and ready for use */
+	CRYPT_STATE_BUSY  = 0x2U,	/**< An internal process is ongoing */
+	CRYPT_STATE_ERROR = 0x4U,	/**< Error */
 } crypt_state_t;
 
 /**
   * @brief CRYPT data type
   */
-typedef enum
-{
-    DATA_32_BIT = 0,	/**< 32 bit data,don't swap */
-    DATA_16_BIT = 1,	/**< 16 bit data,swap */
-    DATA_8_BIT  = 2,	/**< 8 bit data,swap */
-    DATA_1_BIT  = 3,	/**< 1 bit data, swap */
+typedef enum {
+	DATA_32_BIT = 0U,	/**< 32 bit data,don't swap */
+	DATA_16_BIT = 1U,	/**< 16 bit data,swap */
+	DATA_8_BIT  = 2U,	/**< 8 bit data,swap */
+	DATA_1_BIT  = 3U,	/**< 1 bit data, swap */
 } crypt_data_t;
 
 /**
   * @brief CRYPT init structure definition
   */
-typedef struct
-{
-    crypt_mode_t mode;    	/**< Crypt mode */
-    crypt_data_t type;    	/**< Data type select */
+typedef struct {
+	crypt_mode_t mode;    	/**< Crypt mode */
+	crypt_data_t type;    	/**< Data type select */
 } crypt_init_t;
 
 /**
   * @brief  CRYPT Handle Structure definition
   */
-typedef struct crypt_handle_s
-{
-    CRYPT_TypeDef *perh;	/**< Register base address */
-    crypt_init_t init;  	/**< CRYPT required parameters */
+typedef struct crypt_handle_s {
+	CRYPT_TypeDef *perh;	/**< Register base address */
+	crypt_init_t init;  	/**< CRYPT required parameters */
 #ifdef ALD_DMA
-    dma_handle_t hdma_m2p;	/**< CRYPT DMA handle parameters memory to crypt module */
-    dma_handle_t hdma_p2m;	/**< CRYPT DMA handle parameters crypt module to memory */
+	dma_handle_t hdma_m2p;	/**< CRYPT DMA handle parameters memory to crypt module */
+	dma_handle_t hdma_p2m;	/**< CRYPT DMA handle parameters crypt module to memory */
 #endif
-    uint8_t *plain_text; 	/**< Pointer to plain text */
-    uint8_t *cipher_text;	/**< Pointer to cipher text */
-    uint32_t size;       	/**< The size of crypt data buf */
-    uint32_t count;      	/**< The count of crypt data buf */
-    uint32_t step;       	/**< The step of once crypt 4(aes) */
-    uint32_t dir;        	/**< ENCRYPT or DECRYPT */
-    uint32_t iv[4];     	/**< The iv of crypt */
-    uint32_t key[4];     	/**< The key of crypt */
-    lock_state_t lock;   	/**< Locking object */
-    crypt_state_t state; 	/**< CRYPT operation state */
-
-    void (*crypt_cplt_cbk)(struct crypt_handle_s *arg);	/**< Crypt completed callback */
-    void (*err_cplt_cbk)(struct crypt_handle_s *arg);  	/**< Crypt error callback */
+	uint8_t *plain_text; 	/**< Pointer to plain text */
+	uint8_t *cipher_text;	/**< Pointer to cipher text */
+	uint32_t size;       	/**< The size of crypt data buf */
+	uint32_t count;      	/**< The count of crypt data buf */
+	uint32_t step;       	/**< The step of once crypt 4(aes) */
+	uint32_t dir;        	/**< ENCRYPT or DECRYPT */
+	uint32_t iv[4];     	/**< The iv of crypt */
+	uint32_t key[4];     	/**< The key of crypt */
+	lock_state_t lock;   	/**< Locking object */
+	crypt_state_t state; 	/**< CRYPT operation state */
+
+	void (*crypt_cplt_cbk)(struct crypt_handle_s *arg);	/**< Crypt completed callback */
+	void (*err_cplt_cbk)(struct crypt_handle_s *arg);  	/**< Crypt error callback */
 } crypt_handle_t;
 /**
   * @}
@@ -148,7 +139,7 @@ typedef struct crypt_handle_s
   */
 #define CRYPT_GO(handle) 		(SET_BIT((handle)->perh->CON, CRYPT_CON_GO_MSK))
 #define CRYPT_FIFOEN_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
-#define CRYPT_FIFOEN_DISABLE(handle) 	(CLEAR_BIT(handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
+#define CRYPT_FIFOEN_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_FIFOEN_MSK))
 #define CRYPT_IVEN_ENABLE(handle) 	(SET_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
 #define CRYPT_IVEN_DISABLE(handle) 	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_IVEN_MSK))
 #define CRYPT_IE_ENABLE(handle)		(SET_BIT((handle)->perh->CON, CRYPT_CON_IE_MSK))
@@ -156,7 +147,7 @@ typedef struct crypt_handle_s
 #define CRYPT_DMA_ENABLE(handle)	(SET_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
 #define CRYPT_DMA_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON, CRYPT_CON_DMAEN_MSK))
 #define CRYPT_SETDIR(handle, dir)	do {(handle)->perh->CON &= ~(0x1 << CRYPT_CON_ENCS_POS);	\
-        (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
+					   (handle)->perh->CON |= (dir << CRYPT_CON_ENCS_POS);} while (0)
 #define CRYPT_WRITE_FIFO(handle, data)  ((handle)->perh->FIFO = (data))
 #define CRYPT_READ_FIFO(handle)		((handle)->perh->FIFO)
 /**
@@ -168,13 +159,13 @@ typedef struct crypt_handle_s
   */
 #define IS_CRYPT(x)		((x) == CRYPT)
 #define IS_CRYPT_MODE(x) 	(((x) == CRYPT_MODE_ECB) ||   \
-                             ((x) == CRYPT_MODE_CBC) ||   \
-                             ((x) == CRYPT_MODE_CTR))
+				 ((x) == CRYPT_MODE_CBC) ||   \
+				 ((x) == CRYPT_MODE_CTR))
 #define IS_CRYPT_IT(x)		((x) == CRYPT_IT_IT)
 #define IS_CRYPT_FLAG(x) 	(((x) == CRYPT_FLAG_AESIF) || \
-                             ((x) == CRYPT_FLAG_DONE))
+				 ((x) == CRYPT_FLAG_DONE))
 #define IS_CRYPT_IV_LEN(x)	(((x) == IV_2_LEN) || \
-                             ((x) == IV_4_LEN))
+				 ((x) == IV_4_LEN))
 /**
   * @}
   */
@@ -205,9 +196,9 @@ ald_status_t ald_crypt_encrypt_by_it(crypt_handle_t *hperh, uint8_t *plain_text,
 ald_status_t ald_crypt_decrypt_by_it(crypt_handle_t *hperh, uint8_t *cipher_text, uint8_t *plain_text, uint32_t size);
 #ifdef ALD_DMA
 ald_status_t ald_crypt_encrypt_by_dma(crypt_handle_t *hperh, uint8_t *plain_text,
-                                      uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
+             uint8_t *cipher_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
 ald_status_t ald_crypt_decrypt_by_dma(crypt_handle_t *hperh, uint8_t *cipher_text,
-                                      uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
+               uint8_t *plain_text, uint32_t size, uint8_t channel_m2p, uint8_t channel_p2m);
 #endif
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dbgc.h

@@ -18,7 +18,7 @@
 #define __ALD_DBGC_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -41,34 +41,32 @@ extern "C" {
 /**
   * @brief Debug mode select
   */
-typedef enum
-{
-    DEBC_MODE_SLEEP   = (1u << 0),	/**< Sleep mode */
-    DEBC_MODE_STOP1   = (1u << 1),	/**< STOP1 mode */
-    DEBC_MODE_STOP2   = (1u << 2),	/**< STOP2 mode */
-    DEBC_MODE_STANDBY = (1u << 3),	/**< Standby mode */
+typedef enum {
+	DEBC_MODE_SLEEP   = (1U << 0),	/**< Sleep mode */
+	DEBC_MODE_STOP1   = (1U << 1),	/**< STOP1 mode */
+	DEBC_MODE_STOP2   = (1U << 2),	/**< STOP2 mode */
+	DEBC_MODE_STANDBY = (1U << 3),	/**< Standby mode */
 } dbgc_mode_t;
 
 /**
   * @brief Debug peripheral select
   */
-typedef enum
-{
-    DEBC_PERH_TIMER0  = (1u << 0),			/**< AD16C4T0 */
-    DEBC_PERH_TIMER1  = (1u << 1),			/**< BS16T0 */
-    DEBC_PERH_TIMER2  = (1u << 2),			/**< GP16C2T0 */
-    DEBC_PERH_TIMER3  = (1u << 3),			/**< GP16C2T1 */
-    DEBC_PERH_TIMER4  = (1u << 4),			/**< BS16T1 */
-    DEBC_PERH_TIMER5  = (1u << 5),			/**< BS16T2 */
-    DEBC_PERH_TIMER6  = (1u << 6),			/**< GP16C4T0 */
-    DEBC_PERH_TIMER7  = (1u << 7),			/**< BS16T3 */
-    DEBC_PERH_I2C0    = (1u << 8),			/**< I2C0 SMBUS */
-    DEBC_PERH_I2C1    = (1u << 9),			/**< I2C1 SMBUS */
-    DEBC_PERH_CAN     = (1u << 12),			/**< CAN */
-    DEBC_PERH_LPTIM0  = (1u << 0)  | (1u << 16),	/**< LPTIM0 */
-    DEBC_PERH_IWDT    = (1u << 8)  | (1u << 16),	/**< IWDT */
-    DEBC_PERH_WWDT    = (1u << 9)  | (1u << 16),	/**< WWDT */
-    DEBC_PERH_RTC     = (1u << 10) | (1u << 16),	/**< RTC */
+typedef enum {
+	DEBC_PERH_TIMER0  = (1U << 0),			/**< AD16C4T0 */
+	DEBC_PERH_TIMER1  = (1U << 1),			/**< BS16T0 */
+	DEBC_PERH_TIMER2  = (1U << 2),			/**< GP16C2T0 */
+	DEBC_PERH_TIMER3  = (1U << 3),			/**< GP16C2T1 */
+	DEBC_PERH_TIMER4  = (1U << 4),			/**< BS16T1 */
+	DEBC_PERH_TIMER5  = (1U << 5),			/**< BS16T2 */
+	DEBC_PERH_TIMER6  = (1U << 6),			/**< GP16C4T0 */
+	DEBC_PERH_TIMER7  = (1U << 7),			/**< BS16T3 */
+	DEBC_PERH_I2C0    = (1U << 8),			/**< I2C0 SMBUS */
+	DEBC_PERH_I2C1    = (1U << 9),			/**< I2C1 SMBUS */
+	DEBC_PERH_CAN     = (1U << 12),			/**< CAN */
+	DEBC_PERH_LPTIM0  = (1U << 0)  | (1U << 16),	/**< LPTIM0 */
+	DEBC_PERH_IWDT    = (1U << 8)  | (1U << 16),	/**< IWDT */
+	DEBC_PERH_WWDT    = (1U << 9)  | (1U << 16),	/**< WWDT */
+	DEBC_PERH_RTC     = (1U << 10) | (1U << 16),	/**< RTC */
 } dbgc_perh_t;
 /**
   * @}
@@ -83,7 +81,7 @@ typedef enum
   */
 __INLINE uint32_t ald_dbgc_get_rev_id(void)
 {
-    return (DBGC->IDCODE >> 16);
+	return (DBGC->IDCODE >> 16);
 }
 
 /**
@@ -92,7 +90,7 @@ __INLINE uint32_t ald_dbgc_get_rev_id(void)
   */
 __INLINE uint32_t ald_dbgc_get_core_id(void)
 {
-    return (DBGC->IDCODE >> 12) & 0xF;
+	return (DBGC->IDCODE >> 12) & 0xF;
 }
 
 /**
@@ -101,7 +99,7 @@ __INLINE uint32_t ald_dbgc_get_core_id(void)
   */
 __INLINE uint32_t ald_dbgc_get_device_id(void)
 {
-    return DBGC->IDCODE & 0xFFF;
+	return DBGC->IDCODE & 0xFFF;
 }
 
 /**
@@ -112,10 +110,10 @@ __INLINE uint32_t ald_dbgc_get_device_id(void)
   */
 __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
 {
-    if (state)
-        SET_BIT(DBGC->CR, mode);
-    else
-        CLEAR_BIT(DBGC->CR, mode);
+	if (state)
+		SET_BIT(DBGC->CR, mode);
+	else
+		CLEAR_BIT(DBGC->CR, mode);
 }
 
 /**
@@ -126,20 +124,18 @@ __INLINE void ald_dbgc_mode_config(dbgc_mode_t mode, type_func_t state)
   */
 __INLINE void ald_dbgc_perh_config(dbgc_perh_t perh, type_func_t state)
 {
-    if ((perh >> 16) & 0x1)
-    {
-        if (state)
-            SET_BIT(DBGC->APB2FZ, perh);
-        else
-            CLEAR_BIT(DBGC->APB2FZ, perh);
-    }
-    else
-    {
-        if (state)
-            SET_BIT(DBGC->APB1FZ, perh);
-        else
-            CLEAR_BIT(DBGC->APB1FZ, perh);
-    }
+	if ((perh >> 16) & 0x1) {
+		if (state)
+			SET_BIT(DBGC->APB2FZ, perh);
+		else
+			CLEAR_BIT(DBGC->APB2FZ, perh);
+	}
+	else {
+		if (state)
+			SET_BIT(DBGC->APB1FZ, perh);
+		else
+			CLEAR_BIT(DBGC->APB1FZ, perh);
+	}
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_dma.h

@@ -18,7 +18,7 @@
 #define __ALD_DMA_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -36,8 +36,8 @@ extern "C" {
   * @defgroup DMA_Public_Macros DMA Public Macros
   * @{
   */
-#define DMA_CH_COUNT	6
-#define DMA_ERR		31
+#define DMA_CH_COUNT	6U
+#define DMA_ERR		31U
 /**
   * @}
   */
@@ -49,257 +49,260 @@ extern "C" {
 
 /**
   * @brief Input source to DMA channel
-  * @note  ES32F065x:
-  *          AD16C4T0--TIMER0
-  *          GP16C4T0--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  *
-  *        ES32F033x:
-  *        ES32F093x:
-  *          GP16C4T0--TIMER0
-  *          GP16C4T1--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
+  * @verbatim
+      In this module, for the convenience of code maintenance,
+      TIMERx is used to indicate the sequence of the timer peripheral.
+      Different product series TIMERx represent different meanings:
+      1. For ES32F065x series:
+      TIMER0 ----> AD16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+      TIMER4 ----> BS16T1
+      TIMER5 ----> BS16T2
+      TIMER6 ----> GP16C4T0
+      TIMER7 ----> BS16T3
+     
+      2. For ES32F033x/ES32F093x series:
+      TIMER0 ----> GP16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+      TIMER4 ----> BS16T1
+      TIMER5 ----> BS16T2
+      TIMER6 ----> GP16C4T1
+      TIMER7 ----> BS16T3
+    @endverbatim
   */
-typedef enum
-{
-    DMA_MSEL_NONE    = 0x0,		/**< NONE */
-    DMA_MSEL_GPIO    = 0x1,		/**< GPIO */
-    DMA_MSEL_CRYPT   = 0x2,		/**< CRYPT */
-    DMA_MSEL_ACMP    = 0x3,		/**< ACMP */
-    DMA_MSEL_DAC0    = 0x4,		/**< DAC0 */
-    DMA_MSEL_ADC0    = 0x6,		/**< ADC0 */
-    DMA_MSEL_CRC     = 0x7,		/**< CRC */
-    DMA_MSEL_UART0   = 0x8,		/**< UART0 */
-    DMA_MSEL_UART1   = 0x9,		/**< UART1 */
-    DMA_MSEL_UART2   = 0xA,		/**< UART2 */
-    DMA_MSEL_UART3   = 0xB,		/**< UART3 */
-    DMA_MSEL_USART0  = 0xC,		/**< USART0 */
-    DMA_MSEL_USART1  = 0xD,		/**< USART1 */
-    DMA_MSEL_SPI0    = 0xE,		/**< SPI0 */
-    DMA_MSEL_SPI1    = 0xF,		/**< SPI1 */
-    DMA_MSEL_I2C0    = 0x10,	/**< I2C0 */
-    DMA_MSEL_I2C1    = 0x11,	/**< I2C1 */
-    DMA_MSEL_TIMER0  = 0x12,	/**< TIMER0 */
-    DMA_MSEL_TIMER1  = 0x13,	/**< TIMER1 */
-    DMA_MSEL_TIMER2  = 0x14,	/**< TIMER2 */
-    DMA_MSEL_TIMER3  = 0x15,	/**< TIMER3 */
-    DMA_MSEL_RTC     = 0x16,	/**< RTC */
-    DMA_MSEL_LPTIM0  = 0x17,	/**< LPTIM0 */
-    DMA_MSEL_LPUART0 = 0x18,	/**< LPUART0 */
-    DMA_MSEL_DMA     = 0x19,	/**< DMA */
-    DMA_MSEL_SPI2    = 0x1A,	/**< SPI2 */
-    DMA_MSEL_TIMER4  = 0x1B,	/**< TIMER4 */
-    DMA_MSEL_TIMER5  = 0x1C,	/**< TIMER5 */
-    DMA_MSEL_TIMER6  = 0x1D,	/**< TIMER6 */
-    DMA_MSEL_TIMER7  = 0x1E,	/**< TIMER7 */
-    DMA_MSEL_ADC1    = 0x1F,	/**< ADC1 */
-    DMA_MSEL_PIS     = 0x20,	/**< PIS */
-    DMA_MSEL_TRNG    = 0x21,	/**< TRNG */
+typedef enum {
+	DMA_MSEL_NONE    = 0x0U,	/**< NONE */
+	DMA_MSEL_GPIO    = 0x1U,	/**< GPIO */
+	DMA_MSEL_CRYPT   = 0x2U,	/**< CRYPT */
+	DMA_MSEL_ACMP    = 0x3U,	/**< ACMP */
+	DMA_MSEL_DAC0    = 0x4U,	/**< DAC0 */
+	DMA_MSEL_ADC0    = 0x6U,	/**< ADC0 */
+	DMA_MSEL_CRC     = 0x7U,	/**< CRC */
+	DMA_MSEL_UART0   = 0x8U,	/**< UART0 */
+	DMA_MSEL_UART1   = 0x9U,	/**< UART1 */
+	DMA_MSEL_UART2   = 0xAU,	/**< UART2 */
+	DMA_MSEL_UART3   = 0xBU,	/**< UART3 */
+	DMA_MSEL_USART0  = 0xCU,	/**< USART0 */
+	DMA_MSEL_USART1  = 0xDU,	/**< USART1 */
+	DMA_MSEL_SPI0    = 0xEU,	/**< SPI0 */
+	DMA_MSEL_SPI1    = 0xFU,	/**< SPI1 */
+	DMA_MSEL_I2C0    = 0x10U,	/**< I2C0 */
+	DMA_MSEL_I2C1    = 0x11U,	/**< I2C1 */
+	DMA_MSEL_TIMER0  = 0x12U,	/**< TIMER0 */
+	DMA_MSEL_TIMER1  = 0x13U,	/**< TIMER1 */
+	DMA_MSEL_TIMER2  = 0x14U,	/**< TIMER2 */
+	DMA_MSEL_TIMER3  = 0x15U,	/**< TIMER3 */
+	DMA_MSEL_RTC     = 0x16U,	/**< RTC */
+	DMA_MSEL_LPTIM0  = 0x17U,	/**< LPTIM0 */
+	DMA_MSEL_LPUART0 = 0x18U,	/**< LPUART0 */
+	DMA_MSEL_DMA     = 0x19U,	/**< DMA */
+	DMA_MSEL_SPI2    = 0x1AU,	/**< SPI2 */
+	DMA_MSEL_TIMER4  = 0x1BU,	/**< TIMER4 */
+	DMA_MSEL_TIMER5  = 0x1CU,	/**< TIMER5 */
+	DMA_MSEL_TIMER6  = 0x1DU,	/**< TIMER6 */
+	DMA_MSEL_TIMER7  = 0x1EU,	/**< TIMER7 */
+	DMA_MSEL_ADC1    = 0x1FU,	/**< ADC1 */
+	DMA_MSEL_PIS     = 0x20U,	/**< PIS */
+	DMA_MSEL_TRNG    = 0x21U,	/**< TRNG */
 } dma_msel_t;
 
 /**
   * @brief Input signal to DMA channel
   */
-typedef enum
-{
-    DMA_MSIGSEL_NONE           = 0x0,	/**< NONE */
-    DMA_MSIGSEL_EXTI_0         = 0x0,	/**< External interrupt 0 */
-    DMA_MSIGSEL_EXTI_1         = 0x1,	/**< External interrupt 1 */
-    DMA_MSIGSEL_EXTI_2         = 0x2,	/**< External interrupt 2 */
-    DMA_MSIGSEL_EXTI_3         = 0x3,	/**< External interrupt 3 */
-    DMA_MSIGSEL_EXTI_4         = 0x4,	/**< External interrupt 4 */
-    DMA_MSIGSEL_EXTI_5         = 0x5,	/**< External interrupt 5 */
-    DMA_MSIGSEL_EXTI_6         = 0x6,	/**< External interrupt 6 */
-    DMA_MSIGSEL_EXTI_7         = 0x7,	/**< External interrupt 7 */
-    DMA_MSIGSEL_EXTI_8         = 0x8,	/**< External interrupt 8 */
-    DMA_MSIGSEL_EXTI_9         = 0x9,	/**< External interrupt 9 */
-    DMA_MSIGSEL_EXTI_10        = 0xA,	/**< External interrupt 10 */
-    DMA_MSIGSEL_EXTI_11        = 0xB,	/**< External interrupt 11 */
-    DMA_MSIGSEL_EXTI_12        = 0xC,	/**< External interrupt 12 */
-    DMA_MSIGSEL_EXTI_13        = 0xD,	/**< External interrupt 13 */
-    DMA_MSIGSEL_EXTI_14        = 0xE,	/**< External interrupt 14 */
-    DMA_MSIGSEL_EXTI_15        = 0xF,	/**< External interrupt 15 */
-    DMA_MSIGSEL_CRYPT_WRITE    = 0x0,	/**< CRYPT write mode */
-    DMA_MSIGSEL_CRYPT_READ     = 0x1,	/**< CRYPT read mode */
-    DMA_MSIGSEL_CALC_WRITE     = 0x0,	/**< CALC write mode */
-    DMA_MSIGSEL_CALC_READ      = 0x1,	/**< CALC read mode */
-    DMA_MSIGSEL_DAC0_CH0       = 0x0,	/**< DAC0 channel 0 complete */
-    DMA_MSIGSEL_DAC0_CH1       = 0x1,	/**< DAC0 channel 1 complete */
-    DMA_MSIGSEL_ADC       	   = 0x0,	/**< ADC mode */
-    DMA_MSIGSEL_UART_TXEMPTY   = 0x0,	/**< UART transmit */
-    DMA_MSIGSEL_UART_RNR       = 0x1,	/**< UART receive */
-    DMA_MSIGSEL_USART_RNR      = 0x0,	/**< USART reveive */
-    DMA_MSIGSEL_USART_TXEMPTY  = 0x1,	/**< USART transmit */
-    DMA_MSIGSEL_SPI_RNR        = 0x0,	/**< SPI receive */
-    DMA_MSIGSEL_SPI_TXEMPTY    = 0x1,	/**< SPI transmit */
-    DMA_MSIGSEL_I2C_RNR        = 0x0,	/**< I2C receive */
-    DMA_MSIGSEL_I2C_TXEMPTY    = 0x1,	/**< I2C transmit */
-    DMA_MSIGSEL_TIMER_CH1      = 0x0,	/**< TIM channal 1 */
-    DMA_MSIGSEL_TIMER_CH2      = 0x1,	/**< TIM channal 2 */
-    DMA_MSIGSEL_TIMER_CH3      = 0x2,	/**< TIM channal 3 */
-    DMA_MSIGSEL_TIMER_CH4      = 0x3,	/**< TIM channal 4 */
-    DMA_MSIGSEL_TIMER_TRI      = 0x4,	/**< TIM trigger */
-    DMA_MSIGSEL_TIMER_COMP     = 0x5,	/**< TIM compare */
-    DMA_MSIGSEL_TIMER_UPDATE   = 0x6,	/**< TIM update */
-    DMA_MSIGSEL_LPUART_RNR     = 0x0,	/**< LPUART receive */
-    DMA_MSIGSEL_LPUART_TXEMPTY = 0x1,	/**< LPUART transmit */
-    DMA_MSIGSEL_PIS_CH0        = 0x0,	/**< PIS channal 0 */
-    DMA_MSIGSEL_PIS_CH1        = 0x1,	/**< PIS channal 1 */
-    DMA_MSIGSEL_PIS_CH2        = 0x2,	/**< PIS channal 2 */
-    DMA_MSIGSEL_PIS_CH3        = 0x3,	/**< PIS channal 3 */
-    DMA_MSIGSEL_PIS_CH4        = 0x4,	/**< PIS channal 4 */
-    DMA_MSIGSEL_PIS_CH5        = 0x5,	/**< PIS channal 5 */
-    DMA_MSIGSEL_PIS_CH6        = 0x6,	/**< PIS channal 6 */
-    DMA_MSIGSEL_PIS_CH7        = 0x7,	/**< PIS channal 7 */
-    DMA_MSIGSEL_PIS_CH8        = 0x8,	/**< PIS channal 8 */
-    DMA_MSIGSEL_PIS_CH9        = 0x9,	/**< PIS channal 9 */
-    DMA_MSIGSEL_PIS_CH10       = 0xA,	/**< PIS channal 10 */
-    DMA_MSIGSEL_PIS_CH11       = 0xB,	/**< PIS channal 11 */
-    DMA_MSIGSEL_PIS_CH12       = 0xC,	/**< PIS channal 12 */
-    DMA_MSIGSEL_PIS_CH13       = 0xD,	/**< PIS channal 13 */
-    DMA_MSIGSEL_PIS_CH14       = 0xE,	/**< PIS channal 14 */
-    DMA_MSIGSEL_PIS_CH15       = 0xF,	/**< PIS channal 15 */
+typedef enum {
+	DMA_MSIGSEL_NONE           = 0x0U,	/**< NONE */
+	DMA_MSIGSEL_EXTI_0         = 0x0U,	/**< External interrupt 0 */
+	DMA_MSIGSEL_EXTI_1         = 0x1U,	/**< External interrupt 1 */
+	DMA_MSIGSEL_EXTI_2         = 0x2U,	/**< External interrupt 2 */
+	DMA_MSIGSEL_EXTI_3         = 0x3U,	/**< External interrupt 3 */
+	DMA_MSIGSEL_EXTI_4         = 0x4U,	/**< External interrupt 4 */
+	DMA_MSIGSEL_EXTI_5         = 0x5U,	/**< External interrupt 5 */
+	DMA_MSIGSEL_EXTI_6         = 0x6U,	/**< External interrupt 6 */
+	DMA_MSIGSEL_EXTI_7         = 0x7U,	/**< External interrupt 7 */
+	DMA_MSIGSEL_EXTI_8         = 0x8U,	/**< External interrupt 8 */
+	DMA_MSIGSEL_EXTI_9         = 0x9U,	/**< External interrupt 9 */
+	DMA_MSIGSEL_EXTI_10        = 0xAU,	/**< External interrupt 10 */
+	DMA_MSIGSEL_EXTI_11        = 0xBU,	/**< External interrupt 11 */
+	DMA_MSIGSEL_EXTI_12        = 0xCU,	/**< External interrupt 12 */
+	DMA_MSIGSEL_EXTI_13        = 0xDU,	/**< External interrupt 13 */
+	DMA_MSIGSEL_EXTI_14        = 0xEU,	/**< External interrupt 14 */
+	DMA_MSIGSEL_EXTI_15        = 0xFU,	/**< External interrupt 15 */
+	DMA_MSIGSEL_CRYPT_WRITE    = 0x0U,	/**< CRYPT write mode */
+	DMA_MSIGSEL_CRYPT_READ     = 0x1U,	/**< CRYPT read mode */
+	DMA_MSIGSEL_CALC_WRITE     = 0x0U,	/**< CALC write mode */
+	DMA_MSIGSEL_CALC_READ      = 0x1U,	/**< CALC read mode */
+	DMA_MSIGSEL_DAC0_CH0       = 0x0U,	/**< DAC0 channel 0 complete */
+	DMA_MSIGSEL_DAC0_CH1       = 0x1U,	/**< DAC0 channel 1 complete */
+	DMA_MSIGSEL_ADC       	   = 0x0U,	/**< ADC mode */
+	DMA_MSIGSEL_UART_TXEMPTY   = 0x0U,	/**< UART transmit */
+	DMA_MSIGSEL_UART_RNR       = 0x1U,	/**< UART receive */
+	DMA_MSIGSEL_USART_RNR      = 0x0U,	/**< USART reveive */
+	DMA_MSIGSEL_USART_TXEMPTY  = 0x1U,	/**< USART transmit */
+	DMA_MSIGSEL_SPI_RNR        = 0x0U,	/**< SPI receive */
+	DMA_MSIGSEL_SPI_TXEMPTY    = 0x1U,	/**< SPI transmit */
+	DMA_MSIGSEL_I2C_RNR        = 0x0U,	/**< I2C receive */
+	DMA_MSIGSEL_I2C_TXEMPTY    = 0x1U,	/**< I2C transmit */
+	DMA_MSIGSEL_TIMER_CH1      = 0x0U,	/**< TIM channal 1 */
+	DMA_MSIGSEL_TIMER_CH2      = 0x1U,	/**< TIM channal 2 */
+	DMA_MSIGSEL_TIMER_CH3      = 0x2U,	/**< TIM channal 3 */
+	DMA_MSIGSEL_TIMER_CH4      = 0x3U,	/**< TIM channal 4 */
+	DMA_MSIGSEL_TIMER_TRI      = 0x4U,	/**< TIM trigger */
+	DMA_MSIGSEL_TIMER_COMP     = 0x5U,	/**< TIM compare */
+	DMA_MSIGSEL_TIMER_UPDATE   = 0x6U,	/**< TIM update */
+	DMA_MSIGSEL_LPUART_RNR     = 0x0U,	/**< LPUART receive */
+	DMA_MSIGSEL_LPUART_TXEMPTY = 0x1U,	/**< LPUART transmit */
+	DMA_MSIGSEL_PIS_CH0        = 0x0U,	/**< PIS channal 0 */
+	DMA_MSIGSEL_PIS_CH1        = 0x1U,	/**< PIS channal 1 */
+	DMA_MSIGSEL_PIS_CH2        = 0x2U,	/**< PIS channal 2 */
+	DMA_MSIGSEL_PIS_CH3        = 0x3U,	/**< PIS channal 3 */
+	DMA_MSIGSEL_PIS_CH4        = 0x4U,	/**< PIS channal 4 */
+	DMA_MSIGSEL_PIS_CH5        = 0x5U,	/**< PIS channal 5 */
+	DMA_MSIGSEL_PIS_CH6        = 0x6U,	/**< PIS channal 6 */
+	DMA_MSIGSEL_PIS_CH7        = 0x7U,	/**< PIS channal 7 */
+	DMA_MSIGSEL_PIS_CH8        = 0x8U,	/**< PIS channal 8 */
+	DMA_MSIGSEL_PIS_CH9        = 0x9U,	/**< PIS channal 9 */
+	DMA_MSIGSEL_PIS_CH10       = 0xAU,	/**< PIS channal 10 */
+	DMA_MSIGSEL_PIS_CH11       = 0xBU,	/**< PIS channal 11 */
+	DMA_MSIGSEL_PIS_CH12       = 0xCU,	/**< PIS channal 12 */
+	DMA_MSIGSEL_PIS_CH13       = 0xDU,	/**< PIS channal 13 */
+	DMA_MSIGSEL_PIS_CH14       = 0xEU,	/**< PIS channal 14 */
+	DMA_MSIGSEL_PIS_CH15       = 0xFU,	/**< PIS channal 15 */
 } dma_msigsel_t;
 
 /**
   * @brief DMA Descriptor control type
   */
-typedef union
-{
-    struct
-    {
-        uint32_t cycle_ctrl    : 3;	/**< DMA operating mode @ref dma_cycle_ctrl_t */
-        uint32_t next_useburst : 1;	/**< Uses the alternate data structure when complete a DMA cycle */
-        uint32_t n_minus_1     : 10;	/**< Represent the total number of DMA transfers that DMA cycle contains. */
-        uint32_t R_power       : 4;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
-        uint32_t src_prot_ctrl : 3;	/**< Control the state of HPROT when reads the source data. */
-        uint32_t dst_prot_ctrl : 3;	/**< Control the state of HPROT when writes the destination data */
-        uint32_t src_size      : 2;	/**< Source data size @ref dma_data_size_t */
-        uint32_t src_inc       : 2;	/**< Control the source address increment. @ref dma_data_inc_t */
-        uint32_t dst_size      : 2;	/**< Destination data size. @ref dma_data_size_t */
-        uint32_t dst_inc       : 2;	/**< Destination address increment. @ref dma_data_inc_t */
-    };
-    uint32_t word;
+typedef union {
+	struct {
+		uint32_t cycle_ctrl    :3;	/**< DMA operating mode @ref dma_cycle_ctrl_t */
+		uint32_t next_useburst :1;	/**< Uses the alternate data structure when complete a DMA cycle */
+		uint32_t n_minus_1     :10;	/**< Represent the total number of DMA transfers that DMA cycle contains. */
+		uint32_t R_power       :4;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
+		uint32_t src_prot_ctrl :3;	/**< Control the state of HPROT when reads the source data. */
+		uint32_t dst_prot_ctrl :3;	/**< Control the state of HPROT when writes the destination data */
+		uint32_t src_size      :2;	/**< Source data size @ref dma_data_size_t */
+		uint32_t src_inc       :2;	/**< Control the source address increment. @ref dma_data_inc_t */
+		uint32_t dst_size      :2;	/**< Destination data size. @ref dma_data_size_t */
+		uint32_t dst_inc       :2;	/**< Destination address increment. @ref dma_data_inc_t */
+	};
+	uint32_t word;
 } dma_ctrl_t;
 
 /**
   * @brief Channel control data structure
   */
-typedef struct
-{
-    void *src;		/**< Source data end pointer */
-    void *dst;		/**< Destination data end pointer */
-    dma_ctrl_t ctrl;	/**< Control data configuration @ref dma_ctrl_t */
-    uint32_t use;		/**< Reserve for user */
+typedef struct {
+	void *src;		/**< Source data end pointer */
+	void *dst;		/**< Destination data end pointer */
+	dma_ctrl_t ctrl;	/**< Control data configuration @ref dma_ctrl_t */
+	uint32_t use;		/**< Reserve for user */
 } dma_descriptor_t;
 
 /**
   * @brief data increment
   */
-typedef enum
-{
-    DMA_DATA_INC_BYTE     = 0x0,	/**< Address increment by byte */
-    DMA_DATA_INC_HALFWORD = 0x1,	/**< Address increment by halfword */
-    DMA_DATA_INC_WORD     = 0x2,	/**< Address increment by word */
-    DMA_DATA_INC_NONE     = 0x3,	/**< No increment */
+typedef enum {
+	DMA_DATA_INC_BYTE     = 0x0U,	/**< Address increment by byte */
+	DMA_DATA_INC_HALFWORD = 0x1U,	/**< Address increment by halfword */
+	DMA_DATA_INC_WORD     = 0x2U,	/**< Address increment by word */
+	DMA_DATA_INC_NONE     = 0x3U,	/**< No increment */
 } dma_data_inc_t;
 
 /**
   * @brief Data size
   */
-typedef enum
-{
-    DMA_DATA_SIZE_BYTE     = 0x0,	/**< Byte */
-    DMA_DATA_SIZE_HALFWORD = 0x1,	/**< Halfword */
-    DMA_DATA_SIZE_WORD     = 0x2,	/**< Word */
+typedef enum {
+	DMA_DATA_SIZE_BYTE     = 0x0U,	/**< Byte */
+	DMA_DATA_SIZE_HALFWORD = 0x1U,	/**< Halfword */
+	DMA_DATA_SIZE_WORD     = 0x2U,	/**< Word */
 } dma_data_size_t;
 
 /**
   * @brief The operating mode of the DMA cycle
   */
-typedef enum
-{
-    DMA_CYCLE_CTRL_NONE               = 0x0,	/**< Stop */
-    DMA_CYCLE_CTRL_BASIC              = 0x1,	/**< Basic */
-    DMA_CYCLE_CTRL_AUTO               = 0x2,	/**< Auto-request */
-    DMA_CYCLE_CTRL_PINGPONG           = 0x3,	/**< Ping-pong */
-    DMA_CYCLE_CTRL_MEM_SCATTER_GATHER = 0x4,	/**< Memory scatter/gather */
-    DMA_CYCLE_CTRL_PER_SCATTER_GATHER = 0x6,	/**< Peripheral scatter/gather */
+typedef enum {
+	DMA_CYCLE_CTRL_NONE             = 0x0U,	/**< Stop */
+	DMA_CYCLE_CTRL_BASIC            = 0x1U,	/**< Basic */
+	DMA_CYCLE_CTRL_AUTO             = 0x2U,	/**< Auto-request */
+	DMA_CYCLE_CTRL_PINGPONG         = 0x3U,	/**< Ping-pong */
+	DMA_CYCLE_CTRL_MEM_SG_PRIMARY   = 0x4U,	/**< Memory scatter-gather using the primary structure */
+	DMA_CYCLE_CTRL_MEM_SG_ALTERNATE = 0x5U,	/**< Memory scatter-gather using the alternate structure */
+	DMA_CYCLE_CTRL_PER_SG_PRIMARY   = 0x6U,	/**< Peripheral scatter-gather using the primary structure */
+	DMA_CYCLE_CTRL_PER_SG_ALTERNATE = 0x7U,	/**< Peripheral scatter-gather using the alternate structure */
 } dma_cycle_ctrl_t;
 
 /**
   * @brief Control how many DMA transfers can occur
   *        before the controller re-arbitrates
   */
-typedef enum
-{
-    DMA_R_POWER_1    = 0x0,		/**< Arbitrates after each DMA transfer */
-    DMA_R_POWER_2    = 0x1,		/**< Arbitrates after 2 DMA transfer */
-    DMA_R_POWER_4    = 0x2,		/**< Arbitrates after 4 DMA transfer */
-    DMA_R_POWER_8    = 0x3,		/**< Arbitrates after 8 DMA transfer */
-    DMA_R_POWER_16   = 0x4,		/**< Arbitrates after 16 DMA transfer */
-    DMA_R_POWER_32   = 0x5,		/**< Arbitrates after 32 DMA transfer */
-    DMA_R_POWER_64   = 0x6,		/**< Arbitrates after 64 DMA transfer */
-    DMA_R_POWER_128  = 0x7,		/**< Arbitrates after 128 DMA transfer */
-    DMA_R_POWER_256  = 0x8,		/**< Arbitrates after 256 DMA transfer */
-    DMA_R_POWER_512  = 0x9,		/**< Arbitrates after 512 DMA transfer */
-    DMA_R_POWER_1024 = 0xA,		/**< Arbitrates after 1024 DMA transfer */
+typedef enum {
+	DMA_R_POWER_1    = 0x0U,	/**< Arbitrates after each DMA transfer */
+	DMA_R_POWER_2    = 0x1U,	/**< Arbitrates after 2 DMA transfer */
+	DMA_R_POWER_4    = 0x2U,	/**< Arbitrates after 4 DMA transfer */
+	DMA_R_POWER_8    = 0x3U,	/**< Arbitrates after 8 DMA transfer */
+	DMA_R_POWER_16   = 0x4U,	/**< Arbitrates after 16 DMA transfer */
+	DMA_R_POWER_32   = 0x5U,	/**< Arbitrates after 32 DMA transfer */
+	DMA_R_POWER_64   = 0x6U,	/**< Arbitrates after 64 DMA transfer */
+	DMA_R_POWER_128  = 0x7U,	/**< Arbitrates after 128 DMA transfer */
+	DMA_R_POWER_256  = 0x8U,	/**< Arbitrates after 256 DMA transfer */
+	DMA_R_POWER_512  = 0x9U,	/**< Arbitrates after 512 DMA transfer */
+	DMA_R_POWER_1024 = 0xAU,	/**< Arbitrates after 1024 DMA transfer */
 } dma_arbiter_config_t;
 
 /**
   * @brief Callback function pointer and param
   */
-typedef struct
-{
-    void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
-    void (*err_cbk)(void *arg);	/**< DMA occurs error callback */
-    void *cplt_arg;			/**< The parameter of cplt_cbk() */
-    void *err_arg;			/**< The parameter of err_cbk() */
+typedef struct {
+	void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
+	void (*err_cbk)(void* arg);	/**< DMA occurs error callback */
+	void *cplt_arg;			/**< The parameter of cplt_cbk() */
+	void *err_arg;			/**< The parameter of err_cbk() */
 } dma_call_back_t;
 
 /**
   * @brief DMA channal configure structure
   */
-typedef struct
-{
-    void *src;			/**< Source data begin pointer */
-    void *dst;			/**< Destination data begin pointer */
-    uint16_t size;			/**< The total number of DMA transfers that DMA cycle contains */
-    dma_data_size_t data_width;	/**< Data width, @ref dma_data_size_t */
-    dma_data_inc_t src_inc;		/**< Source increment type. @ref dma_data_inc_t */
-    dma_data_inc_t dst_inc;		/**< Destination increment type. @ref dma_data_inc_t */
-    dma_arbiter_config_t R_power;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
-    type_func_t primary;		/**< Use primary descriptor or alternate descriptor */
-    type_func_t burst;		/**< Uses the alternate data structure when complete a DMA cycle */
-    type_func_t high_prio;		/**< High priority or default priority */
-    type_func_t iterrupt;		/**< Enable/disable interrupt */
-    dma_msel_t msel;		/**< Input source to DMA channel @ref dma_msel_t */
-    dma_msigsel_t msigsel;		/**< Input signal to DMA channel @ref dma_msigsel_t */
-    uint8_t channel;		/**< Channel index */
+typedef struct {
+	void *src;			/**< Source data begin pointer */
+	void *dst;			/**< Destination data begin pointer */
+	uint16_t size;			/**< The total number of DMA transfers that DMA cycle contains */
+	dma_data_size_t data_width;	/**< Data width, @ref dma_data_size_t */
+	dma_data_inc_t src_inc;		/**< Source increment type. @ref dma_data_inc_t */
+	dma_data_inc_t dst_inc;		/**< Destination increment type. @ref dma_data_inc_t */
+	dma_arbiter_config_t R_power;	/**< Control how many DMA transfers can occur before re-arbitrates. @ref dma_arbiter_config_t */
+	type_func_t primary;		/**< Use primary descriptor or alternate descriptor */
+	type_func_t burst;		/**< Enable/Disable the useburst setting for this channel */
+	type_func_t high_prio;		/**< High priority or default priority */
+	type_func_t interrupt;		/**< Enable/disable interrupt */
+	dma_msel_t msel;		/**< Input source to DMA channel @ref dma_msel_t */
+	dma_msigsel_t msigsel;		/**< Input signal to DMA channel @ref dma_msigsel_t */
+	uint8_t channel;		/**< Channel index */
 } dma_config_t;
 
 /**
   * @brief DMA handle structure definition
   */
-typedef struct
-{
-    DMA_TypeDef *perh;		/**< DMA registers base address */
-    dma_config_t config;		/**< Channel configure structure. @ref dma_config_t */
-    void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
-    void (*err_cbk)(void *arg);	/**< DMA bus occurs error callback */
-    void *cplt_arg;			/**< The parameter of cplt_cbk() */
-    void *err_arg;			/**< The parameter of err_cbk() */
+typedef struct {
+	DMA_TypeDef *perh;		/**< DMA registers base address */
+	dma_config_t config;		/**< Channel configure structure. @ref dma_config_t */
+	void (*cplt_cbk)(void *arg);	/**< DMA transfers complete callback */
+	void (*err_cbk)(void *arg);	/**< DMA bus occurs error callback */
+	void *cplt_arg;			/**< The parameter of cplt_cbk() */
+	void *err_arg;			/**< The parameter of err_cbk() */
 } dma_handle_t;
+
+/**
+  * @brief Descriptor complete state
+  */
+typedef enum {
+	DMA_DESCP_CPLT_PRI = 0x0U,	/**< Primary descriptor has been completed */
+	DMA_DESCP_CPLT_ALT = 0x1U,	/**< Alternate descriptor has been completed */
+	DMA_DESCP_CPLT_ALL = 0x2U,	/**< Both primary and alternate descriptors have been completed */
+} dma_descrp_cplt_t;
 /**
   * @}
   */
@@ -317,12 +320,14 @@ typedef struct
 #define IS_DMA_DATASIZE_TYPE(x)  (((x) == DMA_DATA_SIZE_BYTE)     || \
                                   ((x) == DMA_DATA_SIZE_HALFWORD) || \
                                   ((x) == DMA_DATA_SIZE_WORD))
-#define IS_CYCLECTRL_TYPE(x)  (((x) == DMA_CYCLE_CTRL_NONE)               || \
-                               ((x) == DMA_CYCLE_CTRL_BASIC)              || \
-                               ((x) == DMA_CYCLE_CTRL_AUTO)               || \
-                               ((x) == DMA_CYCLE_CTRL_PINGPONG)           || \
-                               ((x) == DMA_CYCLE_CTRL_MEM_SCATTER_GATHER) || \
-                               ((x) == DMA_CYCLE_CTRL_PER_SCATTER_GATHER))
+#define IS_CYCLECTRL_TYPE(x)  (((x) == DMA_CYCLE_CTRL_NONE)             || \
+                               ((x) == DMA_CYCLE_CTRL_BASIC)            || \
+                               ((x) == DMA_CYCLE_CTRL_AUTO)             || \
+                               ((x) == DMA_CYCLE_CTRL_PINGPONG)         || \
+                               ((x) == DMA_CYCLE_CTRL_MEM_SG_PRIMARY)   || \
+                               ((x) == DMA_CYCLE_CTRL_MEM_SG_ALTERNATE) || \
+                               ((x) == DMA_CYCLE_CTRL_PER_SG_PRIMARY)   || \
+                               ((x) == DMA_CYCLE_CTRL_PER_SG_ALTERNATE))
 #define IS_DMA_ARBITERCONFIG_TYPE(x)  (((x) == DMA_R_POWER_1)   || \
                                        ((x) == DMA_R_POWER_2)   || \
                                        ((x) == DMA_R_POWER_4)   || \
@@ -354,6 +359,7 @@ typedef struct
 extern void ald_dma_reset(DMA_TypeDef *DMAx);
 extern void ald_dma_init(DMA_TypeDef *DMAx);
 extern void ald_dma_config_struct(dma_config_t *p);
+extern void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory);
 /**
   * @}
   */
@@ -366,11 +372,17 @@ extern void ald_dma_config_struct(dma_config_t *p);
 extern void ald_dma_config_auto(dma_handle_t *hperh);
 extern void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
 extern void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
-                                     uint16_t size, uint8_t channel, void (*cbk)(void *arg));
+                                        uint16_t size, uint8_t channel, void (*cbk)(void *arg));
 extern void ald_dma_config_basic(dma_handle_t *hperh);
 extern void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size);
 extern void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
-                                      dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
+                                 dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
+extern void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
+                                       uint8_t first, void (*cbk)(void *arg));
+extern void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc,
+                                       uint32_t nr, uint8_t channel, void (*cbk)(void *arg));
+extern void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
+                    dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
 /**
   * @}
   */
@@ -384,7 +396,8 @@ extern void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_fu
 extern it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel);
 extern flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
 extern void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel);
-void ald_dma_irq_handler(void);
+extern dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel);
+extern void ald_dma_irq_handler(void);
 /**
   * @}
   */
@@ -393,7 +406,6 @@ void ald_dma_irq_handler(void);
   * @}
   */
 
-
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_flash.h

@@ -36,21 +36,21 @@ extern "C" {
   * @{
   */
 #define FLASH_REG_UNLOCK()				\
-    do {							\
-        if (op_cmd == OP_FLASH)	 {			\
-            WRITE_REG(MSC->FLASHKEY, 0x8ACE0246);	\
-            WRITE_REG(MSC->FLASHKEY, 0x9BDF1357);	\
-        }						\
-        else {						\
-            WRITE_REG(MSC->INFOKEY, 0x7153BFD9);	\
-            WRITE_REG(MSC->INFOKEY, 0x0642CEA8);	\
-        }						\
-    } while (0)
+do {							\
+	if (op_cmd == OP_FLASH)	 {			\
+		WRITE_REG(MSC->FLASHKEY, 0x8ACE0246U);	\
+		WRITE_REG(MSC->FLASHKEY, 0x9BDF1357U);	\
+	}						\
+	else {						\
+		WRITE_REG(MSC->INFOKEY, 0x7153BFD9U);	\
+		WRITE_REG(MSC->INFOKEY, 0x0642CEA8U);	\
+	}						\
+} while (0)
 #define FLASH_REQ()			(SET_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
 #define FLASH_REQ_FIN()			(CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_FLASHREQ_MSK))
 #define FLASH_IAP_ENABLE()		(SET_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
 #define FLASH_IAP_DISABLE()		(CLEAR_BIT(MSC->FLASHCR, MSC_FLASHCR_IAPEN_MSK))
-#define FLASH_BASE_ADDR			0x00000000
+#define FLASH_BASE_ADDR			0x00000000U
 #define	FLASH_PAGE_SIZE			1024UL
 #define FLASH_WORD_SIZE			8UL
 #define FLASH_TOTAL_SIZE		256UL
@@ -67,9 +67,9 @@ extern "C" {
 #define INFO_PAGE_ADDR(ADDR)		((ADDR) & (~INFO_PAGE_MASK))
 
 #ifdef USE_FLASH_FIFO
-#define	FLASH_FIFO 1
+	#define	FLASH_FIFO 1
 #else
-#define	FLASH_FIFO 0
+	#define	FLASH_FIFO 0
 #endif
 /**
   * @}
@@ -78,24 +78,22 @@ extern "C" {
 /** @defgroup FLASH_Private_Types FLASH Private Types
   * @{
   */
-typedef enum
-{
-    FLASH_CMD_AE     = 0x000051AE,	/**< Program area erase all */
-    FLASH_CMD_PE     = 0x00005EA1,	/**< Page erase  */
-    FLASH_CMD_WP     = 0x00005DA2,	/**< Word program */
-    FLASH_CMD_DATAPE = 0x00005BA4,	/**< Data flash page page erase */
-    FLASH_CMD_DATAWP = 0x00005AA5,	/**< Data flash word program */
+typedef enum {
+	FLASH_CMD_AE     = 0x000051AEU,	/**< Program area erase all */
+	FLASH_CMD_PE     = 0x00005EA1U,	/**< Page erase  */
+	FLASH_CMD_WP     = 0x00005DA2U,	/**< Word program */
+	FLASH_CMD_DATAPE = 0x00005BA4U,	/**< Data flash page page erase */
+	FLASH_CMD_DATAWP = 0x00005AA5U,	/**< Data flash word program */
 } flash_cmd_type;
 
-typedef enum
-{
-    OP_FLASH = 0,	/**< Operate Pragram area */
-    OP_INFO  = 1,	/**< Operate info area */
+typedef enum {
+	OP_FLASH = 0U,	/**< Operate Pragram area */
+	OP_INFO  = 1U,	/**< Operate info area */
 } op_cmd_type;
 
 /**
   * @}
-  */
+  */ 
 /** @addtogroup Flash_Private_Functions
   * @{
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_gpio.h

@@ -18,7 +18,7 @@
 #define __ALD_GPIO_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -52,7 +52,7 @@ extern "C" {
 #define GPIO_PIN_13	(1U << 13)
 #define GPIO_PIN_14	(1U << 14)
 #define GPIO_PIN_15	(1U << 15)
-#define GPIO_PIN_ALL	(0xFFFF)
+#define GPIO_PIN_ALL	(0xFFFFU)
 /**
   * @}
   */
@@ -65,125 +65,114 @@ extern "C" {
 /**
   * @brief GPIO mode
   */
-typedef enum
-{
-    GPIO_MODE_CLOSE  = 0x0,	/**< Digital close  Analog open */
-    GPIO_MODE_INPUT  = 0x1,	/**< Input */
-    GPIO_MODE_OUTPUT = 0x2,	/**< Output */
+typedef enum {
+	GPIO_MODE_CLOSE  = 0x0U,	/**< Digital close  Analog open */
+	GPIO_MODE_INPUT  = 0x1U,	/**< Input */
+	GPIO_MODE_OUTPUT = 0x2U,	/**< Output */
 } gpio_mode_t;
 
 /**
   * @brief GPIO open-drain or push-pull
   */
-typedef enum
-{
-    GPIO_PUSH_PULL   = 0x0,	/**< Push-Pull */
-    GPIO_OPEN_DRAIN  = 0x2,	/**< Open-Drain */
-    GPIO_OPEN_SOURCE = 0x3,	/**< Open-Source */
+typedef enum {
+	GPIO_PUSH_PULL   = 0x0U,	/**< Push-Pull */
+	GPIO_OPEN_DRAIN  = 0x2U,	/**< Open-Drain. Can't output high level */
+	GPIO_OPEN_SOURCE = 0x3U,	/**< Open-Source. Can't output low level */
 } gpio_odos_t;
 
 /**
   * @brief GPIO push-up or push-down
   */
-typedef enum
-{
-    GPIO_FLOATING     = 0x0,/**< Floating */
-    GPIO_PUSH_UP      = 0x1,/**< Push-Up */
-    GPIO_PUSH_DOWN    = 0x2,/**< Push-Down */
-    GPIO_PUSH_UP_DOWN = 0x3,/**< Push-Up and Push-Down */
+typedef enum {
+	GPIO_FLOATING     = 0x0U,	/**< Floating */
+	GPIO_PUSH_UP      = 0x1U,	/**< Push-Up */
+	GPIO_PUSH_DOWN    = 0x2U,	/**< Push-Down */
+	GPIO_PUSH_UP_DOWN = 0x3U,	/**< Push-Up and Push-Down */
 } gpio_push_t;
 
 /**
   * @brief GPIO output drive
   */
-typedef enum
-{
-    GPIO_OUT_DRIVE_NORMAL = 0x0,	/**< Normal current flow */
-    GPIO_OUT_DRIVE_STRONG = 0x1,	/**< Strong current flow */
+typedef enum {
+	GPIO_OUT_DRIVE_NORMAL = 0x0U,	/**< Normal current flow */
+	GPIO_OUT_DRIVE_STRONG = 0x1U,	/**< Strong current flow */
 } gpio_out_drive_t;
 
 /**
   * @brief GPIO filter
   */
-typedef enum
-{
-    GPIO_FILTER_DISABLE = 0x0,	/**< Disable filter */
-    GPIO_FILTER_ENABLE  = 0x1,	/**< Enable filter */
+typedef enum {
+	GPIO_FILTER_DISABLE = 0x0U,	/**< Disable filter */
+	GPIO_FILTER_ENABLE  = 0x1U,	/**< Enable filter */
 } gpio_filter_t;
 
 /**
   * @brief GPIO type
   */
-typedef enum
-{
-    GPIO_TYPE_CMOS = 0x0,	/**< CMOS Type */
-    GPIO_TYPE_TTL  = 0x1,	/**< TTL Type */
+typedef enum {
+	GPIO_TYPE_CMOS = 0x0U,	/**< CMOS Type */
+	GPIO_TYPE_TTL  = 0x1U,	/**< TTL Type */
 } gpio_type_t;
 
 /**
   * @brief GPIO functions
   */
-typedef enum
-{
-    GPIO_FUNC_0 = 0,	/**< function #0 */
-    GPIO_FUNC_1 = 1,	/**< function #1 */
-    GPIO_FUNC_2 = 2,	/**< function #2 */
-    GPIO_FUNC_3 = 3,	/**< function #3 */
-    GPIO_FUNC_4 = 4,	/**< function #4 */
-    GPIO_FUNC_5 = 5,	/**< function #5 */
-    GPIO_FUNC_6 = 6,	/**< function #6 */
-    GPIO_FUNC_7 = 7,	/**< function #7 */
+typedef enum {
+	GPIO_FUNC_0 = 0U,	/**< function #0 */
+	GPIO_FUNC_1 = 1U,	/**< function #1 */
+	GPIO_FUNC_2 = 2U,	/**< function #2 */
+	GPIO_FUNC_3 = 3U,	/**< function #3 */
+	GPIO_FUNC_4 = 4U,	/**< function #4 */
+	GPIO_FUNC_5 = 5U,	/**< function #5 */
+	GPIO_FUNC_6 = 6U,	/**< function #6 */
+	GPIO_FUNC_7 = 7U,	/**< function #7 */
 } gpio_func_t;
 
 
 /**
   * @brief GPIO Init Structure definition
   */
-typedef struct
-{
-    gpio_mode_t mode;	/**< Specifies the operating mode for the selected pins.
+typedef struct {
+	gpio_mode_t mode;	/**< Specifies the operating mode for the selected pins.
 				     This parameter can be any value of @ref gpio_mode_t */
-    gpio_odos_t odos;	/**< Specifies the Open-Drain or Push-Pull for the selected pins.
+	gpio_odos_t odos;	/**< Specifies the Open-Drain or Push-Pull for the selected pins.
 				     This parameter can be a value of @ref gpio_odos_t */
-    gpio_push_t pupd;	/**< Specifies the Pull-up or Pull-Down for the selected pins.
+	gpio_push_t pupd;	/**< Specifies the Pull-up or Pull-Down for the selected pins.
 				     This parameter can be a value of @ref gpio_push_t */
-    gpio_out_drive_t odrv;	/**< Specifies the output driver for the selected pins.
+	gpio_out_drive_t odrv;	/**< Specifies the output driver for the selected pins.
 				     This parameter can be a value of @ref gpio_out_drive_t */
-    gpio_filter_t flt;	/**< Specifies the input filter for the selected pins.
+	gpio_filter_t flt;	/**< Specifies the input filter for the selected pins.
 				     This parameter can be a value of @ref gpio_filter_t */
-    gpio_type_t type;	/**< Specifies the type for the selected pins.
+	gpio_type_t type;	/**< Specifies the type for the selected pins.
 				     This parameter can be a value of @ref gpio_type_t */
-    gpio_func_t func;	/**< Specifies the function for the selected pins.
+	gpio_func_t func;	/**< Specifies the function for the selected pins.
 				     This parameter can be a value of @ref gpio_func_t */
 } gpio_init_t;
 
 /**
   * @brief EXTI trigger style
   */
-typedef enum
-{
-    EXTI_TRIGGER_RISING_EDGE   = 0,	/**< Rising edge trigger */
-    EXTI_TRIGGER_TRAILING_EDGE = 1,	/**< Trailing edge trigger */
-    EXTI_TRIGGER_BOTH_EDGE     = 2,	/**< Rising and trailing edge trigger */
+typedef enum {
+	EXTI_TRIGGER_RISING_EDGE   = 0U,	/**< Rising edge trigger */
+	EXTI_TRIGGER_TRAILING_EDGE = 1U,	/**< Trailing edge trigger */
+	EXTI_TRIGGER_BOTH_EDGE     = 2U,	/**< Rising and trailing edge trigger */
 } exti_trigger_style_t;
 
 /**
   * @brief EXTI filter clock select
   */
-typedef enum
-{
-    EXTI_FILTER_CLOCK_10K = 0,	/**< cks = 10KHz */
-    EXTI_FILTER_CLOCK_32K = 1,	/**< cks = 32KHz */
+typedef enum {
+	EXTI_FILTER_CLOCK_10K = 0U,	/**< cks = 10KHz */
+	EXTI_FILTER_CLOCK_32K = 1U,	/**< cks = 32KHz */
 } exti_filter_clock_t;
 
 /**
   * @brief EXTI Init Structure definition
   */
-typedef struct
-{
-    type_func_t filter;		/**< Enable filter. */
-    exti_filter_clock_t cks;	/**< Filter clock select. */
-    uint8_t filter_time;		/**< Filter duration */
+typedef struct {
+	type_func_t filter;		/**< Enable filter. */
+	exti_filter_clock_t cks;	/**< Filter clock select. */
+	uint8_t filter_time;		/**< Filter duration */
 } exti_init_t;
 /**
   * @}
@@ -193,37 +182,37 @@ typedef struct
   * @defgroup GPIO_Private_Macros GPIO Private Macros
   * @{
   */
-#define PIN_MASK	0xFFFF
-#define UNLOCK_KEY	0x55AA
+#define PIN_MASK	0xFFFFU
+#define UNLOCK_KEY	0x55AAU
 
 #define IS_GPIO_PIN(x)	((((x) & (uint16_t)0x00) == 0) && ((x) != (uint16_t)0x0))
 #define IS_GPIO_PORT(GPIOx)	((GPIOx == GPIOA) || \
-                             (GPIOx == GPIOB) || \
-                             (GPIOx == GPIOC) || \
-                             (GPIOx == GPIOD) || \
-                             (GPIOx == GPIOE) || \
-                             (GPIOx == GPIOF) || \
-                             (GPIOx == GPIOG) || \
-                             (GPIOx == GPIOH))
+				 (GPIOx == GPIOB) || \
+				 (GPIOx == GPIOC) || \
+				 (GPIOx == GPIOD) || \
+				 (GPIOx == GPIOE) || \
+				 (GPIOx == GPIOF) || \
+				 (GPIOx == GPIOG) || \
+				 (GPIOx == GPIOH))
 #define IS_GPIO_MODE(x)		(((x) == GPIO_MODE_CLOSE) || \
-                             ((x) == GPIO_MODE_INPUT) || \
-                             ((x) == GPIO_MODE_OUTPUT))
+                                 ((x) == GPIO_MODE_INPUT) || \
+                                 ((x) == GPIO_MODE_OUTPUT))
 #define IS_GPIO_ODOS(x)		(((x) == GPIO_PUSH_PULL)  || \
-                             ((x) == GPIO_OPEN_DRAIN) || \
-                             ((x) == GPIO_OPEN_SOURCE))
+                                 ((x) == GPIO_OPEN_DRAIN) || \
+                                 ((x) == GPIO_OPEN_SOURCE))
 #define IS_GPIO_PUPD(x)		(((x) == GPIO_FLOATING)  || \
-                             ((x) == GPIO_PUSH_UP)   || \
-                             ((x) == GPIO_PUSH_DOWN) || \
-                             ((x) == GPIO_PUSH_UP_DOWN))
+                                 ((x) == GPIO_PUSH_UP)   || \
+                                 ((x) == GPIO_PUSH_DOWN) || \
+                                 ((x) == GPIO_PUSH_UP_DOWN))
 #define IS_GPIO_ODRV(x)		(((x) == GPIO_OUT_DRIVE_NORMAL) || \
-                             ((x) == GPIO_OUT_DRIVE_STRONG))
+                                 ((x) == GPIO_OUT_DRIVE_STRONG))
 #define IS_GPIO_FLT(x)		(((x) == GPIO_FILTER_DISABLE) || \
-                             ((x) == GPIO_FILTER_ENABLE))
+                                 ((x) == GPIO_FILTER_ENABLE))
 #define IS_GPIO_TYPE(x)		(((x) == GPIO_TYPE_TTL) || \
-                             ((x) == GPIO_TYPE_CMOS))
+                                 ((x) == GPIO_TYPE_CMOS))
 #define IS_TRIGGER_STYLE(x)	(((x) == EXTI_TRIGGER_RISING_EDGE)   || \
-                             ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
-                             ((x) == EXTI_TRIGGER_BOTH_EDGE))
+                                 ((x) == EXTI_TRIGGER_TRAILING_EDGE) || \
+                                 ((x) == EXTI_TRIGGER_BOTH_EDGE))
 #define IS_EXTI_FLTCKS_TYPE(x)	(((x) == EXTI_FILTER_CLOCK_10K) || \
                                  ((x) == EXTI_FILTER_CLOCK_32K))
 #define IS_GPIO_FUNC(x)		((x) <= 7)

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_i2c.h

@@ -39,111 +39,102 @@ extern "C" {
 /**
   * @brief I2C Error Code
   */
-typedef enum
-{
-    I2C_ERROR_NONE    = 0x0, 	/**< No error */
-    I2C_ERROR_BERR    = 0x1, 	/**< Berr error */
-    I2C_ERROR_ARLO    = 0x2, 	/**< Arlo error */
-    I2C_ERROR_AF      = 0x4, 	/**< Af error */
-    I2C_ERROR_OVR     = 0x8, 	/**< Ovr error */
-    I2C_ERROR_DMA     = 0x10,	/**< Dma error */
-    I2C_ERROR_TIMEOUT = 0x20,	/**< Timeout error */
+typedef enum {
+	I2C_ERROR_NONE    = 0x0U, 	/**< No error */
+	I2C_ERROR_BERR    = 0x1U, 	/**< Berr error */
+	I2C_ERROR_ARLO    = 0x2U, 	/**< Arlo error */
+	I2C_ERROR_AF      = 0x4U, 	/**< Af error */
+	I2C_ERROR_OVR     = 0x8U, 	/**< Ovr error */
+	I2C_ERROR_DMA     = 0x10U,	/**< Dma error */
+	I2C_ERROR_TIMEOUT = 0x20U,	/**< Timeout error */
 } i2c_error_t;
 
 /**
   * @brief I2C state structure definition
   */
-typedef enum
-{
-    I2C_STATE_RESET   = 0x0, 	/**< Peripheral is not yet Initialized */
-    I2C_STATE_READY   = 0x1,	/**< Peripheral Initialized and ready for use */
-    I2C_STATE_BUSY    = 0x2,	/**< An internal process is ongoing */
-    I2C_STATE_BUSY_TX = 0x3,	/**< Data Transmission process is ongoing */
-    I2C_STATE_BUSY_RX = 0x4,	/**< Data Reception process is ongoing */
-    I2C_STATE_TIMEOUT = 0x5,	/**< timeout state */
-    I2C_STATE_ERROR   = 0x6,	/**< Error */
+typedef enum {
+	I2C_STATE_RESET   = 0x0U, 	/**< Peripheral is not yet Initialized */
+	I2C_STATE_READY   = 0x1U,	/**< Peripheral Initialized and ready for use */
+	I2C_STATE_BUSY    = 0x2U,	/**< An internal process is ongoing */
+	I2C_STATE_BUSY_TX = 0x3U,	/**< Data Transmission process is ongoing */
+	I2C_STATE_BUSY_RX = 0x4U,	/**< Data Reception process is ongoing */
+	I2C_STATE_TIMEOUT = 0x5U,	/**< timeout state */
+	I2C_STATE_ERROR   = 0x6U,	/**< Error */
 } i2c_state_t;
 
 /**
   * @brief I2C Duty Cycle
   */
-typedef enum
-{
-    I2C_DUTYCYCLE_2    = 0x0,   	/**< duty cycle is 2 */
-    I2C_DUTYCYCLE_16_9 = 0x4000,	/**< duty cycle is 16/9 */
+typedef enum {
+	I2C_DUTYCYCLE_2    = 0x0U,   	/**< duty cycle is 2 */
+	I2C_DUTYCYCLE_16_9 = 0x4000U,	/**< duty cycle is 16/9 */
 } i2c_duty_t;
 
 /**
   * @brief I2C Addressing Mode
   */
-typedef enum
-{
-    I2C_ADDR_7BIT  = 0x1,	/**< 7 bit address */
-    I2C_ADDR_10BIT = 0x2,	/**< 10 bit address */
+typedef enum {
+	I2C_ADDR_7BIT  = 0x1U,	/**< 7 bit address */
+	I2C_ADDR_10BIT = 0x2U,	/**< 10 bit address */
 } i2c_addr_t;
 
 /**
   * @brief I2C Dual Addressing Mode
   */
-typedef enum
-{
-    I2C_DUALADDR_DISABLE = 0x0,	/**< dual address is disable */
-    I2C_DUALADDR_ENABLE  = 0x1,	/**< dual address is enable */
+typedef enum {
+	I2C_DUALADDR_DISABLE = 0x0U,	/**< dual address is disable */
+	I2C_DUALADDR_ENABLE  = 0x1U,	/**< dual address is enable */
 } i2c_dual_addr_t;
 
 /**
   * @brief I2C General Call Addressing mode
   */
-typedef enum
-{
-    I2C_GENERALCALL_DISABLE = 0x0, 	/**< feneral call address is disable */
-    I2C_GENERALCALL_ENABLE  = 0x40,	/**< feneral call address is enable */
+typedef enum {
+	I2C_GENERALCALL_DISABLE = 0x0U, 	/**< feneral call address is disable */
+	I2C_GENERALCALL_ENABLE  = 0x40U,	/**< feneral call address is enable */
 } i2c_general_addr_t;
 
 /**
   * @brief I2C Nostretch Mode
   */
-typedef enum
-{
-    I2C_NOSTRETCH_DISABLE = 0x0, 	/**< Nostretch disable */
-    I2C_NOSTRETCH_ENABLE  = 0x80,	/**< Nostretch enable */
+typedef enum {
+	I2C_NOSTRETCH_DISABLE = 0x0U, 	/**< Nostretch disable */
+	I2C_NOSTRETCH_ENABLE  = 0x80U,	/**< Nostretch enable */
 } i2c_nostretch_t;
 
 /**
   * @brief I2C Memory Address Size
   */
-typedef enum
-{
-    I2C_MEMADD_SIZE_8BIT  = 0x1,	/**< 8 bit memory address size */
-    I2C_MEMADD_SIZE_16BIT = 0x10	/**< 10 bit memory address size */
+typedef enum {
+	I2C_MEMADD_SIZE_8BIT  = 0x1U,	/**< 8 bit memory address size */
+	I2C_MEMADD_SIZE_16BIT = 0x10U,	/**< 10 bit memory address size */
 } i2c_addr_size_t;
 
 /**
   * @brief I2C Flag Definition
   */
-typedef enum
-{
-    I2C_FLAG_SB         = (1U << 0),
-    I2C_FLAG_ADDR       = (1U << 1),
-    I2C_FLAG_BTF        = (1U << 2),
-    I2C_FLAG_ADD10      = (1U << 3),
-    I2C_FLAG_STOPF      = (1U << 4),
-    I2C_FLAG_RXNE       = (1U << 6),
-    I2C_FLAG_TXE        = (1U << 7),
-    I2C_FLAG_BERR       = (1U << 8),
-    I2C_FLAG_ARLO       = (1U << 9),
-    I2C_FLAG_AF         = (1U << 10),
-    I2C_FLAG_OVR        = (1U << 11),
-    I2C_FLAG_PECERR     = (1U << 12),
-    I2C_FLAG_TIMEOUT    = (1U << 14),
-    I2C_FLAG_SMBALERT   = (1U << 15),
-    I2C_FLAG_MSL        = (1U << 16),
-    I2C_FLAG_BUSY       = (1U << 17),
-    I2C_FLAG_TRA        = (1U << 18),
-    I2C_FLAG_GENCALL    = (1U << 20),
-    I2C_FLAG_SMBDEFAULT = (1U << 21),
-    I2C_FLAG_SMBHOST    = (1U << 22),
-    I2C_FLAG_DUALF      = (1U << 23),
+typedef enum {
+	I2C_FLAG_SB         = (1U << 0),
+	I2C_FLAG_ADDR       = (1U << 1),
+	I2C_FLAG_BTF        = (1U << 2),
+	I2C_FLAG_ADD10      = (1U << 3),
+	I2C_FLAG_STOPF      = (1U << 4),
+	I2C_FLAG_RXNE       = (1U << 6),
+	I2C_FLAG_TXE        = (1U << 7),
+	I2C_FLAG_BERR       = (1U << 8),
+	I2C_FLAG_ARLO       = (1U << 9),
+	I2C_FLAG_AF         = (1U << 10),
+	I2C_FLAG_OVR        = (1U << 11),
+	I2C_FLAG_PECERR     = (1U << 12),
+	I2C_FLAG_TIMEOUT    = (1U << 14),
+	I2C_FLAG_SMBALERT   = (1U << 15),
+	I2C_FLAG_MSL        = (1U << 16),
+	I2C_FLAG_BUSY       = (1U << 17),
+	I2C_FLAG_TRA        = (1U << 18),
+	I2C_FLAG_GENCALL    = (1U << 20),
+	I2C_FLAG_SMBDEFAULT = (1U << 21),
+	I2C_FLAG_SMBHOST    = (1U << 22),
+	I2C_FLAG_DUALF      = (1U << 23),
 } i2c_flag_t;
 
 /**
@@ -151,193 +142,181 @@ typedef enum
   */
 typedef enum
 {
-    I2C_MODE_NONE   = 0x0, 	/**< No I2C communication on going */
-    I2C_MODE_MASTER = 0x10,	/**< I2C communication is in Master mode */
-    I2C_MODE_SLAVE  = 0x20,	/**< I2C communication is in Slave mode */
-    I2C_MODE_MEM    = 0x40,	/**< I2C communication is in Memory mode */
+	I2C_MODE_NONE   = 0x0U, 	/**< No I2C communication on going */
+	I2C_MODE_MASTER = 0x10U,	/**< I2C communication is in Master mode */
+	I2C_MODE_SLAVE  = 0x20U,	/**< I2C communication is in Slave mode */
+	I2C_MODE_MEM    = 0x40U,	/**< I2C communication is in Memory mode */
 } i2c_mode_t;
 
 /**
   * @brief I2C Clock
   */
-typedef enum
-{
-    I2C_STANDARD_MODE_MAX_CLK = 100000,	/**< Standard mode clock */
-    I2C_FAST_MODE_MAX_CLK     = 400000,	/**< Fast mode clock */
+typedef enum {
+	I2C_STANDARD_MODE_MAX_CLK = 100000U,	/**< Standard mode clock */
+	I2C_FAST_MODE_MAX_CLK     = 400000U,	/**< Fast mode clock */
 } i2c_clock_t;
 
 /**
   * @brief Interrupt Configuration Definition
   */
-typedef enum
-{
-    I2C_IT_BUF = (1U << 10),	/**< Buffer interrupt */
-    I2C_IT_EVT = (1U << 9), 	/**< Event interrupt */
-    I2C_IT_ERR = (1U << 8), 	/**< Error interrupt */
+typedef enum {
+	I2C_IT_BUF = (1U << 10),	/**< Buffer interrupt */
+	I2C_IT_EVT = (1U << 9), 	/**< Event interrupt */
+	I2C_IT_ERR = (1U << 8), 	/**< Error interrupt */
 } i2c_interrupt_t;
 
 /**
   * @brief I2C CON1 Register
   */
-typedef enum
-{
-    I2C_CON1_PEN    = (1U << 0), 	/**< PEN BIT */
-    I2C_CON1_PMOD   = (1U << 1), 	/**< PMOD BIT */
-    I2C_CON1_SMBMOD = (1U << 3), 	/**< SMBMOD  BIT */
-    I2C_CON1_ARPEN  = (1U << 4), 	/**< ARPEN BIT */
-    I2C_CON1_PECEN  = (1U << 5), 	/**< PECEN BIT */
-    I2C_CON1_GCEN   = (1U << 6), 	/**< GCEN  BIT */
-    I2C_CON1_DISCS  = (1U << 7), 	/**< DISCS BIT */
-    I2C_CON1_START  = (1U << 8), 	/**< START BIT */
-    I2C_CON1_STOP   = (1U << 9), 	/**< STOP BIT */
-    I2C_CON1_ACKEN  = (1U << 10),	/**< ACKEN  BIT */
-    I2C_CON1_POSAP  = (1U << 11),	/**< POSAP BIT */
-    I2C_CON1_TRPEC  = (1U << 12),	/**< TRPEC  BIT */
-    I2C_CON1_ALARM  = (1U << 13),	/**< ALARM BIT */
-    I2C_CON1_SRST   = (1U << 15),	/**< SRST BIT */
+typedef enum {
+	I2C_CON1_PEN    = (1U << 0), 	/**< PEN BIT */
+	I2C_CON1_PMOD   = (1U << 1), 	/**< PMOD BIT */
+	I2C_CON1_SMBMOD = (1U << 3), 	/**< SMBMOD  BIT */
+	I2C_CON1_ARPEN  = (1U << 4), 	/**< ARPEN BIT */
+	I2C_CON1_PECEN  = (1U << 5), 	/**< PECEN BIT */
+	I2C_CON1_GCEN   = (1U << 6), 	/**< GCEN  BIT */
+	I2C_CON1_DISCS  = (1U << 7), 	/**< DISCS BIT */
+	I2C_CON1_START  = (1U << 8), 	/**< START BIT */
+	I2C_CON1_STOP   = (1U << 9), 	/**< STOP BIT */
+	I2C_CON1_ACKEN  = (1U << 10),	/**< ACKEN  BIT */
+	I2C_CON1_POSAP  = (1U << 11),	/**< POSAP BIT */
+	I2C_CON1_TRPEC  = (1U << 12),	/**< TRPEC  BIT */
+	I2C_CON1_ALARM  = (1U << 13),	/**< ALARM BIT */
+	I2C_CON1_SRST   = (1U << 15),	/**< SRST BIT */
 } i2c_con1_t;
 
 /**
   * @brief I2C CON2 Register
   */
-typedef enum
-{
-    I2C_CON2_CLKF    =  0x3F,     	/**< CLKF BITS */
-    I2C_CON2_CLKF_0  = (1U << 0), 	/**< CLKF_0 BIT */
-    I2C_CON2_CLKF_1  = (1U << 1), 	/**< CLKF_1 BIT */
-    I2C_CON2_CLKF_2  = (1U << 2), 	/**< CLKF_2 BIT */
-    I2C_CON2_CLKF_3  = (1U << 3), 	/**< CLKF_3 BIT */
-    I2C_CON2_CLKF_4  = (1U << 4), 	/**< CLKF_4 BIT */
-    I2C_CON2_CLKF_5  = (1U << 5), 	/**< CLKF_5 BIT */
-    I2C_CON2_ERRIE   = (1U << 8), 	/**< ERRIE BIT */
-    I2C_CON2_EVTIE   = (1U << 9), 	/**< EVTIE BIT */
-    I2C_CON2_BUFIE   = (1U << 10),	/**< BUFIE BIT */
-    I2C_CON2_DMAEN   = (1U << 11),	/**< DMAEN BIT */
-    I2C_CON2_LDMA    = (1U << 12),	/**< LDMA BIT */
+typedef enum {
+	I2C_CON2_CLKF    =  0x3FU,     	/**< CLKF BITS */
+	I2C_CON2_CLKF_0  = (1U << 0), 	/**< CLKF_0 BIT */
+	I2C_CON2_CLKF_1  = (1U << 1), 	/**< CLKF_1 BIT */
+	I2C_CON2_CLKF_2  = (1U << 2), 	/**< CLKF_2 BIT */
+	I2C_CON2_CLKF_3  = (1U << 3), 	/**< CLKF_3 BIT */
+	I2C_CON2_CLKF_4  = (1U << 4), 	/**< CLKF_4 BIT */
+	I2C_CON2_CLKF_5  = (1U << 5), 	/**< CLKF_5 BIT */
+	I2C_CON2_ERRIE   = (1U << 8), 	/**< ERRIE BIT */
+	I2C_CON2_EVTIE   = (1U << 9), 	/**< EVTIE BIT */
+	I2C_CON2_BUFIE   = (1U << 10),	/**< BUFIE BIT */
+	I2C_CON2_DMAEN   = (1U << 11),	/**< DMAEN BIT */
+	I2C_CON2_LDMA    = (1U << 12),	/**< LDMA BIT */
 } i2c_con2_t;
 
 /**
   * @brief I2C ADDR1 Register
   */
-typedef enum
-{
-    I2C_ADDR1_ADDH0   = (1U << 0), 	/**< ADDH0 BIT */
-    I2C_ADDR1_ADDH1   = (1U << 1), 	/**< ADDH1 BIT */
-    I2C_ADDR1_ADDH2   = (1U << 2), 	/**< ADDH2 BIT */
-    I2C_ADDR1_ADDH3   = (1U << 3), 	/**< ADDH3 BIT */
-    I2C_ADDR1_ADDH4   = (1U << 4), 	/**< ADDH4 BIT */
-    I2C_ADDR1_ADDH5   = (1U << 5), 	/**< ADDH5 BIT */
-    I2C_ADDR1_ADDH6   = (1U << 6), 	/**< ADDH6 BIT */
-    I2C_ADDR1_ADDH7   = (1U << 7), 	/**< ADDH7 BIT */
-    I2C_ADDR1_ADDH8   = (1U << 8), /**< ADDH8 BIT */
-    I2C_ADDR1_ADDH9   = (1U << 9),	/**< ADDH9 BIT */
-    I2C_ADDR1_ADDTYPE = (1U << 15),	/**< ADDTYPE BIT */
+typedef enum {
+	I2C_ADDR1_ADDH0   = (1U << 0), 	/**< ADDH0 BIT */
+	I2C_ADDR1_ADDH1   = (1U << 1), 	/**< ADDH1 BIT */
+	I2C_ADDR1_ADDH2   = (1U << 2), 	/**< ADDH2 BIT */
+	I2C_ADDR1_ADDH3   = (1U << 3), 	/**< ADDH3 BIT */
+	I2C_ADDR1_ADDH4   = (1U << 4), 	/**< ADDH4 BIT */
+	I2C_ADDR1_ADDH5   = (1U << 5), 	/**< ADDH5 BIT */
+	I2C_ADDR1_ADDH6   = (1U << 6), 	/**< ADDH6 BIT */
+	I2C_ADDR1_ADDH7   = (1U << 7), 	/**< ADDH7 BIT */
+	I2C_ADDR1_ADDH8   = (1U << 8), /**< ADDH8 BIT */
+	I2C_ADDR1_ADDH9   = (1U << 9),	/**< ADDH9 BIT */
+	I2C_ADDR1_ADDTYPE = (1U << 15),	/**< ADDTYPE BIT */
 } i2c_addr1_t;
 
 /**
   * @brief I2C ADDR2 Register
   */
-typedef enum
-{
-    I2C_ADDR2_DUALEN = (1U << 0),	/**< DUALEN BIT */
-    I2C_ADDR2_ADD    = (1U << 1),	/**< ADD BIT */
+typedef enum {
+	I2C_ADDR2_DUALEN = (1U << 0),	/**< DUALEN BIT */
+	I2C_ADDR2_ADD    = (1U << 1),	/**< ADD BIT */
 } i2c_addr2_t;
 
 /**
   * @brief I2C STAT1 Register
   */
-typedef enum
-{
-    I2C_STAT1_SB        = (1U << 0), 	/**< SB BIT */
-    I2C_STAT1_ADDR      = (1U << 1), 	/**< ADDR  BIT */
-    I2C_STAT1_BTC       = (1U << 2), 	/**< BTC BIT */
-    I2C_STAT1_SENDADD10 = (1U << 3), 	/**< SENDADD10 BIT */
-    I2C_STAT1_DETSTP    = (1U << 4), 	/**< DETSTP BIT */
-    I2C_STAT1_RXBNE     = (1U << 6), 	/**< RXBNE BIT */
-    I2C_STAT1_TXBE      = (1U << 7), 	/**< TXBE BIT */
-    I2C_STAT1_BUSERR    = (1U << 8), 	/**< BUSERR BIT */
-    I2C_STAT1_LARB      = (1U << 9), 	/**< LARB BIT */
-    I2C_STAT1_ACKERR    = (1U << 10),	/**< ACKERR BIT */
-    I2C_STAT1_ROUERR    = (1U << 11),	/**< ROUERR BIT */
-    I2C_STAT1_PECERR    = (1U << 12),	/**< PECERR BIT */
-    I2C_STAT1_SMBTO     = (1U << 14),	/**< SMBTO BIT */
-    I2C_STAT1_SMBALARM  = (1U << 15),	/**< SMBALARM BIT */
+typedef enum {
+	I2C_STAT1_SB        = (1U << 0), 	/**< SB BIT */
+	I2C_STAT1_ADDR      = (1U << 1), 	/**< ADDR  BIT */
+	I2C_STAT1_BTC       = (1U << 2), 	/**< BTC BIT */
+	I2C_STAT1_SENDADD10 = (1U << 3), 	/**< SENDADD10 BIT */
+	I2C_STAT1_DETSTP    = (1U << 4), 	/**< DETSTP BIT */
+	I2C_STAT1_RXBNE     = (1U << 6), 	/**< RXBNE BIT */
+	I2C_STAT1_TXBE      = (1U << 7), 	/**< TXBE BIT */
+	I2C_STAT1_BUSERR    = (1U << 8), 	/**< BUSERR BIT */
+	I2C_STAT1_LARB      = (1U << 9), 	/**< LARB BIT */
+	I2C_STAT1_ACKERR    = (1U << 10),	/**< ACKERR BIT */
+	I2C_STAT1_ROUERR    = (1U << 11),	/**< ROUERR BIT */
+	I2C_STAT1_PECERR    = (1U << 12),	/**< PECERR BIT */
+	I2C_STAT1_SMBTO     = (1U << 14),	/**< SMBTO BIT */
+	I2C_STAT1_SMBALARM  = (1U << 15),	/**< SMBALARM BIT */
 } i2c_stat1_t;
 
 /**
   * @brief I2C STAT2 Register
   */
-typedef enum
-{
-    I2C_STAT2_MASTER = (1U << 0),	/**< MASTER BIT */
-    I2C_STAT2_BSYF   = (1U << 1),	/**< BSYF  BIT */
-    I2C_STAT2_TRF    = (1U << 2),	/**< TRF BIT */
-    I2C_STAT2_RXGCF  = (1U << 4),	/**< RXGCF BIT */
-    I2C_STAT2_SMBDEF = (1U << 5),	/**< SMBDEF BIT */
-    I2C_STAT2_SMBHH  = (1U << 6),	/**< SMBHH BIT */
-    I2C_STAT2_DUALF  = (1U << 7),	/**< DMF BIT */
-    I2C_STAT2_PECV   = (1U << 8),	/**< PECV BIT */
+typedef enum {
+	I2C_STAT2_MASTER = (1U << 0),	/**< MASTER BIT */
+	I2C_STAT2_BSYF   = (1U << 1),	/**< BSYF  BIT */
+	I2C_STAT2_TRF    = (1U << 2),	/**< TRF BIT */
+	I2C_STAT2_RXGCF  = (1U << 4),	/**< RXGCF BIT */
+	I2C_STAT2_SMBDEF = (1U << 5),	/**< SMBDEF BIT */
+	I2C_STAT2_SMBHH  = (1U << 6),	/**< SMBHH BIT */
+	I2C_STAT2_DUALF  = (1U << 7),	/**< DMF BIT */
+	I2C_STAT2_PECV   = (1U << 8),	/**< PECV BIT */
 } i2c_stat2_t;
 
 /**
   * @brief I2C CKCFG Register
   */
-typedef enum
-{
-    I2C_CKCFG_CLKSET =  0xFFF,    	/**< CLKSET BITS */
-    I2C_CKCFG_DUTY   = (1U << 14),	/**< DUTY BIT */
-    I2C_CKCFG_CLKMOD = (1U << 15),	/**< CLKMOD BIT */
+typedef enum {
+	I2C_CKCFG_CLKSET =  0xFFFU,    	/**< CLKSET BITS */
+	I2C_CKCFG_DUTY   = (1U << 14),	/**< DUTY BIT */
+	I2C_CKCFG_CLKMOD = (1U << 15),	/**< CLKMOD BIT */
 } i2c_ckcfg_t;
 
 /**
   * @brief I2C RT Register
   */
-typedef enum
-{
-    I2C_RT_RISET = 0x3F,	/**< RISET BITS */
+typedef enum {
+	I2C_RT_RISET = 0x3FU,	/**< RISET BITS */
 } i2c_trise_t;
 
 /**
  * @brief I2C Configuration Structure definition
  */
-typedef struct
-{
-    uint32_t clk_speed;                	/**< Specifies the clock frequency */
-    i2c_duty_t duty;			/**< Specifies the I2C fast mode duty cycle */
-    uint32_t own_addr1;               	/**< Specifies the first device own address */
-    i2c_addr_t addr_mode;			/**< Specifies addressing mode */
-    i2c_dual_addr_t dual_addr;		/**< Specifies if dual addressing mode is selected */
-    uint32_t own_addr2;               	/**< Specifies the second device own address */
-    i2c_general_addr_t general_call;	/**< Specifies if general call mode is selected */
-    i2c_nostretch_t no_stretch;     	/**< Specifies if nostretch mode is selected */
+typedef struct {
+	uint32_t clk_speed;                	/**< Specifies the clock frequency */
+	i2c_duty_t duty;			/**< Specifies the I2C fast mode duty cycle */
+	uint32_t own_addr1;               	/**< Specifies the first device own address */
+	i2c_addr_t addr_mode;			/**< Specifies addressing mode */
+	i2c_dual_addr_t dual_addr;		/**< Specifies if dual addressing mode is selected */
+	uint32_t own_addr2;               	/**< Specifies the second device own address */
+	i2c_general_addr_t general_call;	/**< Specifies if general call mode is selected */
+	i2c_nostretch_t no_stretch;     	/**< Specifies if nostretch mode is selected */
 } i2c_init_t;
 
 /**
   * @brief  I2C handle Structure definition
   */
-typedef struct i2c_handle_s
-{
-    I2C_TypeDef *perh;       	/**< I2C registers base address */
-    i2c_init_t init;         	/**< I2C communication parameters */
-    uint8_t *p_buff;         	/**< Pointer to I2C transfer buffer */
-    uint16_t xfer_size;      	/**< I2C transfer size */
-    __IO uint16_t xfer_count;	/**< I2C transfer counter */
+typedef struct i2c_handle_s {
+	I2C_TypeDef *perh;       	/**< I2C registers base address */
+	i2c_init_t init;         	/**< I2C communication parameters */
+	uint8_t *p_buff;         	/**< Pointer to I2C transfer buffer */
+	uint16_t xfer_size;      	/**< I2C transfer size */
+	__IO uint16_t xfer_count;	/**< I2C transfer counter */
 #ifdef ALD_DMA
-    dma_handle_t hdmatx;		/**< I2C Tx DMA handle parameters */
-    dma_handle_t hdmarx;		/**< I2C Rx DMA handle parameters */
+	dma_handle_t hdmatx;		/**< I2C Tx DMA handle parameters */
+	dma_handle_t hdmarx;		/**< I2C Rx DMA handle parameters */
 #endif
-    lock_state_t lock;       	/**< I2C locking object */
-    __IO i2c_state_t state;  	/**< I2C communication state */
-    __IO i2c_mode_t mode;    	/**< I2C communication mode */
-    __IO uint32_t error_code;	/**< I2C Error code */
-
-    void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg);	/**< Master Tx completed callback */
-    void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg);	/**< Master Rx completed callback */
-    void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); 	/**< Slave Tx completed callback */
-    void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); 	/**< Slave Rx completed callback */
-    void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg);   	/**< Tx to Memory completed callback */
-    void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg);   	/**< Rx from Memory completed callback */
-    void (*error_callback)(struct i2c_handle_s *arg);    	/**< Error callback */
+	lock_state_t lock;       	/**< I2C locking object */
+	__IO i2c_state_t state;  	/**< I2C communication state */
+	__IO i2c_mode_t mode;    	/**< I2C communication mode */
+	__IO uint32_t error_code;	/**< I2C Error code */
+
+	void (*master_tx_cplt_cbk)(struct i2c_handle_s *arg);	/**< Master Tx completed callback */
+	void (*master_rx_cplt_cbk)(struct i2c_handle_s *arg);	/**< Master Rx completed callback */
+	void (*slave_tx_cplt_cbk)(struct i2c_handle_s *arg); 	/**< Slave Tx completed callback */
+	void (*slave_rx_cplt_cbk)(struct i2c_handle_s *arg); 	/**< Slave Rx completed callback */
+	void (*mem_tx_cplt_cbk)(struct i2c_handle_s *arg);   	/**< Tx to Memory completed callback */
+	void (*mem_rx_cplt_cbk)(struct i2c_handle_s *arg);   	/**< Rx from Memory completed callback */
+	void (*error_callback)(struct i2c_handle_s *arg);    	/**< Error callback */
 } i2c_handle_t;
 
 /**
@@ -349,19 +328,19 @@ typedef struct i2c_handle_s
   */
 #define I2C_RESET_HANDLE_STATE(x) ((x)->state = I2C_STATE_RESET)
 #define I2C_CLEAR_ADDRFLAG(x)		\
-    do {					\
-        __IO uint32_t tmpreg;		\
-        tmpreg = (x)->perh->STAT1;	\
-        tmpreg = (x)->perh->STAT2;	\
-        UNUSED(tmpreg);			\
-    } while (0)
+do {					\
+	__IO uint32_t tmpreg;		\
+	tmpreg = (x)->perh->STAT1;	\
+	tmpreg = (x)->perh->STAT2;	\
+	UNUSED(tmpreg);			\
+} while (0)
 #define __I2C_CLEAR_STOPFLAG(x)					\
-    do {								\
-        __IO uint32_t tmpreg;					\
-        tmpreg = (x)->perh->STAT1;				\
-        tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN);	\
-        UNUSED(tmpreg);						\
-    } while (0)
+do {								\
+	__IO uint32_t tmpreg;					\
+	tmpreg = (x)->perh->STAT1;				\
+	tmpreg = SET_BIT((x)->perh->CON1, I2C_CON1_PEN);	\
+	UNUSED(tmpreg);						\
+} while (0)
 #define I2C_ENABLE(x)  (SET_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK))
 #define I2C_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, I2C_CON1_PEN_MSK))
 /**
@@ -372,56 +351,56 @@ typedef struct i2c_handle_s
   * @{
   */
 #define IS_I2C_TYPE(x)						(((x) == I2C0) || \
-        ((x) == I2C1))
+								 ((x) == I2C1))
 #define IS_I2C_ADDRESSING_MODE(x)				(((x) == I2C_ADDR_7BIT) || \
-        ((x) == I2C_ADDR_10BIT))
+								 ((x) == I2C_ADDR_10BIT))
 #define IS_I2C_DUAL_ADDRESS(x)					(((x) == I2C_DUALADDR_DISABLE) || \
-        ((x) == I2C_DUALADDR_ENABLE))
+								 ((x) == I2C_DUALADDR_ENABLE))
 #define IS_I2C_GENERAL_CALL(x)					(((x) == I2C_GENERALCALL_DISABLE) || \
-        ((x) == I2C_GENERALCALL_ENABLE))
+								 ((x) == I2C_GENERALCALL_ENABLE))
 #define IS_I2C_MEMADD_size(x)					(((x) == I2C_MEMADD_SIZE_8BIT) || \
-        ((x) == I2C_MEMADD_SIZE_16BIT))
+								 ((x) == I2C_MEMADD_SIZE_16BIT))
 #define IS_I2C_NO_STRETCH(x)					(((x) == I2C_NOSTRETCH_DISABLE) || \
-        ((x) == I2C_NOSTRETCH_ENABLE))
+								 ((x) == I2C_NOSTRETCH_ENABLE))
 #define IS_I2C_OWN_ADDRESS1(x)					(((x) & (uint32_t)(0xFFFFFC00)) == 0)
 #define IS_I2C_OWN_ADDRESS2(x)					(((x) & (uint32_t)(0xFFFFFF01)) == 0)
 #define IS_I2C_CLOCK_SPEED(x)					(((x) > 0) && ((x) <= I2C_FAST_MODE_MAX_CLK))
 #define IS_I2C_DUTY_CYCLE(x)					(((x) == I2C_DUTYCYCLE_2) || \
-        ((x) == I2C_DUTYCYCLE_16_9))
+								 ((x) == I2C_DUTYCYCLE_16_9))
 #define IS_I2C_IT_TYPE(x)					(((x) == I2C_IT_BUF) || \
-        ((x) == I2C_IT_EVT) || \
-        ((x) == I2C_IT_ERR))
+								 ((x) == I2C_IT_EVT) || \
+								 ((x) == I2C_IT_ERR))
 #define IS_I2C_FLAG(x)						(((x) == I2C_FLAG_SB)         || \
-        ((x) == I2C_FLAG_ADDR)       || \
-        ((x) == I2C_FLAG_BTF)        || \
-        ((x) == I2C_FLAG_ADD10)      || \
-        ((x) == I2C_FLAG_STOPF)      || \
-        ((x) == I2C_FLAG_RXNE)       || \
-        ((x) == I2C_FLAG_TXE)        || \
-        ((x) == I2C_FLAG_BERR)       || \
-        ((x) == I2C_FLAG_ARLO)       || \
-        ((x) == I2C_FLAG_AF)         || \
-        ((x) == I2C_FLAG_OVR)        || \
-        ((x) == I2C_FLAG_PECERR)     || \
-        ((x) == I2C_FLAG_TIMEOUT)    || \
-        ((x) == I2C_FLAG_SMBALERT)   || \
-        ((x) == I2C_FLAG_MSL)        || \
-        ((x) == I2C_FLAG_BUSY)       || \
-        ((x) == I2C_FLAG_TRA)        || \
-        ((x) == I2C_FLAG_GENCALL)    || \
-        ((x) == I2C_FLAG_SMBDEFAULT) || \
-        ((x) == I2C_FLAG_SMBHOST)    || \
-        ((x) == I2C_FLAG_DUALF))
+								 ((x) == I2C_FLAG_ADDR)       || \
+								 ((x) == I2C_FLAG_BTF)        || \
+								 ((x) == I2C_FLAG_ADD10)      || \
+								 ((x) == I2C_FLAG_STOPF)      || \
+								 ((x) == I2C_FLAG_RXNE)       || \
+								 ((x) == I2C_FLAG_TXE)        || \
+								 ((x) == I2C_FLAG_BERR)       || \
+								 ((x) == I2C_FLAG_ARLO)       || \
+								 ((x) == I2C_FLAG_AF)         || \
+								 ((x) == I2C_FLAG_OVR)        || \
+								 ((x) == I2C_FLAG_PECERR)     || \
+								 ((x) == I2C_FLAG_TIMEOUT)    || \
+								 ((x) == I2C_FLAG_SMBALERT)   || \
+								 ((x) == I2C_FLAG_MSL)        || \
+								 ((x) == I2C_FLAG_BUSY)       || \
+								 ((x) == I2C_FLAG_TRA)        || \
+								 ((x) == I2C_FLAG_GENCALL)    || \
+								 ((x) == I2C_FLAG_SMBDEFAULT) || \
+								 ((x) == I2C_FLAG_SMBHOST)    || \
+								 ((x) == I2C_FLAG_DUALF))
 
 #define I2C_FREQ_RANGE(x)					((x) / 1000000)
 #define I2C_RISE_TIME(x, u)					(((u) <= I2C_STANDARD_MODE_MAX_CLK) ? ((x) + 1) :\
         ((((x) * 300) / 1000) + 1))
 #define I2C_SPEED_STANDARD(x, y)				(((((x) / ((y) << 1)) & I2C_CKCFG_CLKSET) < 4) ? 4:\
-        ((x) / ((y) << 1)))
+	((x) / ((y) << 1)))
 #define I2C_SPEED_FAST(x, y, z)					(((z) == I2C_DUTYCYCLE_2) ? ((x) / ((y) * 3)) :\
         (((x) / ((y) * 25)) | I2C_DUTYCYCLE_16_9))
 #define I2C_SPEED(x, y, z)					(((y) <= 100000) ? (I2C_SPEED_STANDARD((x), (y))) :\
-        ((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \
+	((I2C_SPEED_FAST((x), (y), (z)) & I2C_CKCFG_CLKSET) == 0) ? 1 : \
         ((I2C_SPEED_FAST((x), (y), (z))) | I2C_CKCFG_CLKMOD))
 #define I2C_MEM_ADD_MSB(x)					((uint8_t)((uint16_t)(((uint16_t)((x) &\
         (uint16_t)(0xFF00))) >> 8)))
@@ -432,7 +411,7 @@ typedef struct i2c_handle_s
 #define I2C_10BIT_HEADER_WRITE(x)				((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\
         (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
 #define I2C_10BIT_HEADER_READ(x)				((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((x) &\
-        (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
+       (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
 /**
   * @}
   */
@@ -454,41 +433,41 @@ ald_status_t ald_i2c_reset(i2c_handle_t *hperh);
 /** @addtogroup I2C_Public_Functions_Group2
  * @{
  */
-/** Blocking mode: Polling */
+ /** Blocking mode: Polling */
 ald_status_t ald_i2c_master_send(i2c_handle_t *hperh, uint16_t dev_addr,
                                  uint8_t *buf, uint16_t size, uint32_t timeout);
 ald_status_t ald_i2c_master_recv(i2c_handle_t *hperh, uint16_t dev_addr,
-                                 uint8_t *buf, uint16_t size, uint32_t timeout);
+                                uint8_t *buf, uint16_t size, uint32_t timeout);
 ald_status_t ald_i2c_slave_send(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
 ald_status_t ald_i2c_slave_recv(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
 ald_status_t ald_i2c_mem_write(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                               i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
+                           i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
 ald_status_t ald_i2c_mem_read(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                              i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
+                          i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint32_t timeout);
 ald_status_t ald_i2c_is_device_ready(i2c_handle_t *hperh, uint16_t dev_addr, uint32_t trials, uint32_t timeout);
 
-/** Non-Blocking mode: Interrupt */
+ /** Non-Blocking mode: Interrupt */
 ald_status_t ald_i2c_master_send_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size);
 ald_status_t ald_i2c_master_recv_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint8_t *buf, uint16_t size);
 ald_status_t ald_i2c_slave_send_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size);
 ald_status_t ald_i2c_slave_recv_by_it(i2c_handle_t *hperh, uint8_t *buf, uint16_t size);
 ald_status_t ald_i2c_mem_write_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                     i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
+                              i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
 ald_status_t ald_i2c_mem_read_by_it(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                    i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
+                             i2c_addr_size_t add_size, uint8_t *buf, uint16_t size);
 
 #ifdef ALD_DMA
-/** Non-Blocking mode: DMA */
+ /** Non-Blocking mode: DMA */
 ald_status_t ald_i2c_master_send_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
-                                        uint8_t *buf, uint16_t size, uint8_t channel);
+                                     uint8_t *buf, uint16_t size, uint8_t channel);
 ald_status_t ald_i2c_master_recv_by_dma(i2c_handle_t *hperh, uint16_t dev_addr,
-                                        uint8_t *buf, uint16_t size, uint8_t channel);
+                                    uint8_t *buf, uint16_t size, uint8_t channel);
 ald_status_t ald_i2c_slave_send_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
 ald_status_t ald_i2c_slave_recv_by_dma(i2c_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
 ald_status_t ald_i2c_mem_write_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr, i2c_addr_size_t add_size,
-                                      uint8_t *buf, uint16_t size, uint8_t channel);
+                                 uint8_t *buf, uint16_t size, uint8_t channel);
 ald_status_t ald_i2c_mem_read_by_dma(i2c_handle_t *hperh, uint16_t dev_addr, uint16_t mem_addr,
-                                     i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel);
+                                i2c_addr_size_t add_size, uint8_t *buf, uint16_t size, uint8_t channel);
 #endif
 /**
  * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_iap.h

@@ -36,10 +36,10 @@ extern "C" {
   * @defgroup IAP_Private_Macros IAP Private Macros
   * @{
   */
-#define IAP_WSP_ADDR	0x10000000
-#define IAP_PE_ADDR	0x10000004
-#define IAP_WP_ADDR	0x10000008
-#define IAP_DWP_ADDR	0x1000000c
+#define IAP_WSP_ADDR	0x10000000U
+#define IAP_PE_ADDR	0x10000004U
+#define IAP_WP_ADDR	0x10000008U
+#define IAP_DWP_ADDR	0x1000000cU
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lcd.h

@@ -38,237 +38,219 @@ extern "C" {
 /**
   * @brief Lcd vlcd voltage type
   */
-typedef enum
-{
-    LCD_VCHPS_3V2 = 0,	/**< 3.2V */
-    LCD_VCHPS_3V8 = 1,	/**< 3.8V */
-    LCD_VCHPS_4V8 = 2,	/**< 4.8V */
-    LCD_VCHPS_5V4 = 3,	/**< 5.4V */
+typedef enum {
+	LCD_VCHPS_3V2 = 0U,	/**< 3.2V */
+	LCD_VCHPS_3V8 = 1U,	/**< 3.8V */
+	LCD_VCHPS_4V8 = 2U,	/**< 4.8V */
+	LCD_VCHPS_5V4 = 3U,	/**< 5.4V */
 } lcd_vchps_t;
 
 /**
   * @brief Lcd function type
   */
-typedef enum
-{
-    LCD_FUNC_DISABLE = 0,	/**< Lcd's function disable */
-    LCD_FUNC_ENABLE  = 1,	/**< Lcd's function enable */
+typedef enum {
+	LCD_FUNC_DISABLE = 0U,	/**< Lcd's function disable */
+	LCD_FUNC_ENABLE  = 1U,	/**< Lcd's function enable */
 } lcd_func_t;
 
 /**
   * @brief Lcd voltage type
   */
-typedef enum
-{
-    LCD_VSEL_VDD  = 0,	/**< VDD */
-    LCD_VSEL_CP   = 1,	/**< Charge pump output */
-    LCD_VSEL_VLCD = 2,	/**< VLCD input */
+typedef enum {
+	LCD_VSEL_VDD  = 0U,	/**< VDD */
+	LCD_VSEL_CP   = 1U,	/**< Charge pump output */
+	LCD_VSEL_VLCD = 2U,	/**< VLCD input */
 } lcd_vsel_t;
 
 /**
   * @brief Lcd resistance select bit
   */
-typedef enum
-{
-    LCD_RES_1MOHM = 0,	/**< 1M ohm */
-    LCD_RES_2MOHM = 1,	/**< 2M ohm */
-    LCD_RES_3MOHM = 2,	/**< 3M ohm */
+typedef enum {
+	LCD_RES_1MOHM = 0U,	/**< 1M ohm */
+	LCD_RES_2MOHM = 1U,	/**< 2M ohm */
+	LCD_RES_3MOHM = 2U,	/**< 3M ohm */
 } lcd_res_t;
 
 /**
   * @brief Lcd bias selector
   */
-typedef enum
-{
-    LCD_BIAS_1_4 = 0,	/**< 1/4 bias */
-    LCD_BIAS_1_2 = 2,	/**< 1/2 bias */
-    LCD_BIAS_1_3 = 3,	/**< 1/3 bias */
+typedef enum {
+	LCD_BIAS_1_4 = 0U,	/**< 1/4 bias */
+	LCD_BIAS_1_2 = 2U,	/**< 1/2 bias */
+	LCD_BIAS_1_3 = 3U,	/**< 1/3 bias */
 } lcd_bias_t;
 
 /**
   * @brief Lcd duty
   */
-typedef enum
-{
-    LCD_DUTY_STATIC = 0,	/**< Static duty (COM0) */
-    LCD_DUTY_1_2    = 1,	/**< 1/2 duty (COM0~COM1) */
-    LCD_DUTY_1_3    = 2,	/**< 1/3 duty (COM0~COM2) */
-    LCD_DUTY_1_4    = 3,	/**< 1/4 duty (COM0~COM3) */
-    LCD_DUTY_1_6    = 4,	/**< 1/6 duty (COM0~COM5) */
-    LCD_DUTY_1_8    = 5,	/**< 1/8 duty (COM0~COM7) */
+typedef enum {
+	LCD_DUTY_STATIC = 0U,	/**< Static duty (COM0) */
+	LCD_DUTY_1_2    = 1U,	/**< 1/2 duty (COM0~COM1) */
+	LCD_DUTY_1_3    = 2U,	/**< 1/3 duty (COM0~COM2) */
+	LCD_DUTY_1_4    = 3U,	/**< 1/4 duty (COM0~COM3) */
+	LCD_DUTY_1_6    = 4U,	/**< 1/6 duty (COM0~COM5) */
+	LCD_DUTY_1_8    = 5U,	/**< 1/8 duty (COM0~COM7) */
 } lcd_duty_t;
 
 /**
   * @brief Lcd prescaler
   */
-typedef enum
-{
-    LCD_PRS_1     = 0, 	/**< CLKPRS = LCDCLK / 1 */
-    LCD_PRS_2     = 1, 	/**< CLKPRS = LCDCLK / 2 */
-    LCD_PRS_4     = 2, 	/**< CLKPRS = LCDCLK / 4 */
-    LCD_PRS_8     = 3, 	/**< CLKPRS = LCDCLK / 8 */
-    LCD_PRS_16    = 4, 	/**< CLKPRS = LCDCLK / 16 */
-    LCD_PRS_32    = 5, 	/**< CLKPRS = LCDCLK / 32 */
-    LCD_PRS_64    = 6, 	/**< CLKPRS = LCDCLK / 64 */
-    LCD_PRS_128   = 7, 	/**< CLKPRS = LCDCLK / 128 */
-    LCD_PRS_256   = 8, 	/**< CLKPRS = LCDCLK / 256 */
-    LCD_PRS_512   = 9, 	/**< CLKPRS = LCDCLK / 512 */
-    LCD_PRS_1024  = 10,	/**< CLKPRS = LCDCLK / 1024 */
-    LCD_PRS_2048  = 11,	/**< CLKPRS = LCDCLK / 2048 */
-    LCD_PRS_4096  = 12,	/**< CLKPRS = LCDCLK / 4096 */
-    LCD_PRS_8192  = 13,	/**< CLKPRS = LCDCLK / 8192 */
-    LCD_PRS_16384 = 14,	/**< CLKPRS = LCDCLK / 16384 */
-    LCD_PRS_32768 = 15,	/**< CLKPRS = LCDCLK / 32768 */
+typedef enum {
+	LCD_PRS_1     = 0U, 	/**< CLKPRS = LCDCLK / 1 */
+	LCD_PRS_2     = 1U, 	/**< CLKPRS = LCDCLK / 2 */
+	LCD_PRS_4     = 2U, 	/**< CLKPRS = LCDCLK / 4 */
+	LCD_PRS_8     = 3U, 	/**< CLKPRS = LCDCLK / 8 */
+	LCD_PRS_16    = 4U, 	/**< CLKPRS = LCDCLK / 16 */
+	LCD_PRS_32    = 5U, 	/**< CLKPRS = LCDCLK / 32 */
+	LCD_PRS_64    = 6U, 	/**< CLKPRS = LCDCLK / 64 */
+	LCD_PRS_128   = 7U, 	/**< CLKPRS = LCDCLK / 128 */
+	LCD_PRS_256   = 8U, 	/**< CLKPRS = LCDCLK / 256 */
+	LCD_PRS_512   = 9U, 	/**< CLKPRS = LCDCLK / 512 */
+	LCD_PRS_1024  = 10U,	/**< CLKPRS = LCDCLK / 1024 */
+	LCD_PRS_2048  = 11U,	/**< CLKPRS = LCDCLK / 2048 */
+	LCD_PRS_4096  = 12U,	/**< CLKPRS = LCDCLK / 4096 */
+	LCD_PRS_8192  = 13U,	/**< CLKPRS = LCDCLK / 8192 */
+	LCD_PRS_16384 = 14U,	/**< CLKPRS = LCDCLK / 16384 */
+	LCD_PRS_32768 = 15U,	/**< CLKPRS = LCDCLK / 32768 */
 } lcd_prs_t;
 
 /**
   * @brief Lcd divider
   */
-typedef enum
-{
-    LCD_DIV_16 = 0, 	/**< DIVCLK = CLKPRS / 16 */
-    LCD_DIV_17 = 1, 	/**< DIVCLK = CLKPRS / 17 */
-    LCD_DIV_18 = 2, 	/**< DIVCLK = CLKPRS / 18 */
-    LCD_DIV_19 = 3, 	/**< DIVCLK = CLKPRS / 19 */
-    LCD_DIV_20 = 4, 	/**< DIVCLK = CLKPRS / 20 */
-    LCD_DIV_21 = 5, 	/**< DIVCLK = CLKPRS / 21 */
-    LCD_DIV_22 = 6, 	/**< DIVCLK = CLKPRS / 22 */
-    LCD_DIV_23 = 7, 	/**< DIVCLK = CLKPRS / 23 */
-    LCD_DIV_24 = 8, 	/**< DIVCLK = CLKPRS / 24 */
-    LCD_DIV_25 = 9, 	/**< DIVCLK = CLKPRS / 25 */
-    LCD_DIV_26 = 10,	/**< DIVCLK = CLKPRS / 26 */
-    LCD_DIV_27 = 11,	/**< DIVCLK = CLKPRS / 27 */
-    LCD_DIV_28 = 12,	/**< DIVCLK = CLKPRS / 28 */
-    LCD_DIV_29 = 13,	/**< DIVCLK = CLKPRS / 29 */
-    LCD_DIV_30 = 14,	/**< DIVCLK = CLKPRS / 30 */
-    LCD_DIV_31 = 15,	/**< DIVCLK = CLKPRS / 31 */
+typedef enum {
+	LCD_DIV_16 = 0U, 	/**< DIVCLK = CLKPRS / 16 */
+	LCD_DIV_17 = 1U, 	/**< DIVCLK = CLKPRS / 17 */
+	LCD_DIV_18 = 2U, 	/**< DIVCLK = CLKPRS / 18 */
+	LCD_DIV_19 = 3U, 	/**< DIVCLK = CLKPRS / 19 */
+	LCD_DIV_20 = 4U, 	/**< DIVCLK = CLKPRS / 20 */
+	LCD_DIV_21 = 5U, 	/**< DIVCLK = CLKPRS / 21 */
+	LCD_DIV_22 = 6U, 	/**< DIVCLK = CLKPRS / 22 */
+	LCD_DIV_23 = 7U, 	/**< DIVCLK = CLKPRS / 23 */
+	LCD_DIV_24 = 8U, 	/**< DIVCLK = CLKPRS / 24 */
+	LCD_DIV_25 = 9U, 	/**< DIVCLK = CLKPRS / 25 */
+	LCD_DIV_26 = 10U,	/**< DIVCLK = CLKPRS / 26 */
+	LCD_DIV_27 = 11U,	/**< DIVCLK = CLKPRS / 27 */
+	LCD_DIV_28 = 12U,	/**< DIVCLK = CLKPRS / 28 */
+	LCD_DIV_29 = 13U,	/**< DIVCLK = CLKPRS / 29 */
+	LCD_DIV_30 = 14U,	/**< DIVCLK = CLKPRS / 30 */
+	LCD_DIV_31 = 15U,	/**< DIVCLK = CLKPRS / 31 */
 } lcd_div_t;
 
 /**
   * @brief Lcd blink mode
   */
-typedef enum
-{
-    LCD_BLINK_OFF           = 0,	/**< Blink disabled */
-    LCD_BLINK_SEG0_COM0     = 1,	/**< Blink enabled on SEG0, COM0 */
-    LCD_BLINK_SEG0_COMX2    = 2,	/**< Blink enabled on SEG0, COMx2 */
-    LCD_BLINK_ALLSEG_ALLCOM = 3,	/**< Blink enabled on all SEG and all COM */
+typedef enum {
+	LCD_BLINK_OFF           = 0U,	/**< Blink disabled */
+	LCD_BLINK_SEG0_COM0     = 1U,	/**< Blink enabled on SEG0, COM0 */
+	LCD_BLINK_SEG0_COMX2    = 2U,	/**< Blink enabled on SEG0, COMx2 */
+	LCD_BLINK_ALLSEG_ALLCOM = 3U,	/**< Blink enabled on all SEG and all COM */
 } lcd_blink_t;
 
 /**
   * @brief Lcd blink frequency
   */
-typedef enum
-{
-    LCD_BLFRQ_8    = 0,	/**< DIVCLK / 8 */
-    LCD_BLFRQ_16   = 1,	/**< DIVCLK / 16 */
-    LCD_BLFRQ_32   = 2,	/**< DIVCLK / 32 */
-    LCD_BLFRQ_64   = 3,	/**< DIVCLK / 64 */
-    LCD_BLFRQ_128  = 4,	/**< DIVCLK / 128 */
-    LCD_BLFRQ_256  = 5,	/**< DIVCLK / 256 */
-    LCD_BLFRQ_512  = 6,	/**< DIVCLK / 512 */
-    LCD_BLFRQ_1024 = 7,	/**< DIVCLK / 1024 */
+typedef enum {
+	LCD_BLFRQ_8    = 0U,	/**< DIVCLK / 8 */
+	LCD_BLFRQ_16   = 1U,	/**< DIVCLK / 16 */
+	LCD_BLFRQ_32   = 2U,	/**< DIVCLK / 32 */
+	LCD_BLFRQ_64   = 3U,	/**< DIVCLK / 64 */
+	LCD_BLFRQ_128  = 4U,	/**< DIVCLK / 128 */
+	LCD_BLFRQ_256  = 5U,	/**< DIVCLK / 256 */
+	LCD_BLFRQ_512  = 6U,	/**< DIVCLK / 512 */
+	LCD_BLFRQ_1024 = 7U,	/**< DIVCLK / 1024 */
 } lcd_blfrq_t;
 
 /**
   * @brief Lcd dead time
   */
-typedef enum
-{
-    LCD_DEAD_TIME_NONE     = 0,	/**< No dead time */
-    LCD_DEAD_TIME_1_DIVCLK = 1,	/**< Dead time is 1 divclk */
-    LCD_DEAD_TIME_2_DIVCLK = 2,	/**< Dead time is 2 divclk */
-    LCD_DEAD_TIME_3_DIVCLK = 3,	/**< Dead time is 3 divclk */
-    LCD_DEAD_TIME_4_DIVCLK = 4,	/**< Dead time is 4 divclk */
-    LCD_DEAD_TIME_5_DIVCLK = 5,	/**< Dead time is 5 divclk */
-    LCD_DEAD_TIME_6_DIVCLK = 6,	/**< Dead time is 6 divclk */
-    LCD_DEAD_TIME_7_DIVCLK = 7,	/**< Dead time is 7 divclk */
+typedef enum {
+	LCD_DEAD_TIME_NONE     = 0U,	/**< No dead time */
+	LCD_DEAD_TIME_1_DIVCLK = 1U,	/**< Dead time is 1 divclk */
+	LCD_DEAD_TIME_2_DIVCLK = 2U,	/**< Dead time is 2 divclk */
+	LCD_DEAD_TIME_3_DIVCLK = 3U,	/**< Dead time is 3 divclk */
+	LCD_DEAD_TIME_4_DIVCLK = 4U,	/**< Dead time is 4 divclk */
+	LCD_DEAD_TIME_5_DIVCLK = 5U,	/**< Dead time is 5 divclk */
+	LCD_DEAD_TIME_6_DIVCLK = 6U,	/**< Dead time is 6 divclk */
+	LCD_DEAD_TIME_7_DIVCLK = 7U,	/**< Dead time is 7 divclk */
 } lcd_dead_t;
 
 /**
   * @brief Lcd pulse keep time
   */
-typedef enum
-{
-    LCD_PON_NONE     = 0,	/**< No pulse keep time */
-    LCD_PON_1_PRSCLK = 1,	/**< Pulse keep 1 prsclk */
-    LCD_PON_2_PRSCLK = 2,	/**< Pulse keep 2 prsclk */
-    LCD_PON_3_PRSCLK = 3,	/**< Pulse keep 3 prsclk */
-    LCD_PON_4_PRSCLK = 4,	/**< Pulse keep 4 prsclk */
-    LCD_PON_5_PRSCLK = 5,	/**< Pulse keep 5 prsclk */
-    LCD_PON_6_PRSCLK = 6,	/**< Pulse keep 6 prsclk */
-    LCD_PON_7_PRSCLK = 7,	/**< Pulse keep 7 prsclk */
+typedef enum {
+	LCD_PON_NONE     = 0U,	/**< No pulse keep time */
+	LCD_PON_1_PRSCLK = 1U,	/**< Pulse keep 1 prsclk */
+	LCD_PON_2_PRSCLK = 2U,	/**< Pulse keep 2 prsclk */
+	LCD_PON_3_PRSCLK = 3U,	/**< Pulse keep 3 prsclk */
+	LCD_PON_4_PRSCLK = 4U,	/**< Pulse keep 4 prsclk */
+	LCD_PON_5_PRSCLK = 5U,	/**< Pulse keep 5 prsclk */
+	LCD_PON_6_PRSCLK = 6U,	/**< Pulse keep 6 prsclk */
+	LCD_PON_7_PRSCLK = 7U,	/**< Pulse keep 7 prsclk */
 } lcd_pluse_on_t;
 
 /**
   * @brief Lcd vgs select
   */
-typedef enum
-{
-    LCD_VGS_0  = 0, 	/**< Grey level display voltage is 30/45 vlcd */
-    LCD_VGS_1  = 1, 	/**< Grey level display voltage is 31/45 vlcd */
-    LCD_VGS_2  = 2, 	/**< Grey level display voltage is 32/45 vlcd */
-    LCD_VGS_3  = 3, 	/**< Grey level display voltage is 33/45 vlcd */
-    LCD_VGS_4  = 4, 	/**< Grey level display voltage is 34/45 vlcd */
-    LCD_VGS_5  = 5, 	/**< Grey level display voltage is 35/45 vlcd */
-    LCD_VGS_6  = 6, 	/**< Grey level display voltage is 36/45 vlcd */
-    LCD_VGS_7  = 7, 	/**< Grey level display voltage is 37/45 vlcd */
-    LCD_VGS_8  = 8, 	/**< Grey level display voltage is 38/45 vlcd */
-    LCD_VGS_9  = 9, 	/**< Grey level display voltage is 39/45 vlcd */
-    LCD_VGS_10 = 10,	/**< Grey level display voltage is 40/45 vlcd */
-    LCD_VGS_11 = 11,	/**< Grey level display voltage is 41/45 vlcd */
-    LCD_VGS_12 = 12,	/**< Grey level display voltage is 42/45 vlcd */
-    LCD_VGS_13 = 13,	/**< Grey level display voltage is 43/45 vlcd */
-    LCD_VGS_14 = 14,	/**< Grey level display voltage is 44/45 vlcd */
-    LCD_VGS_15 = 15,	/**< Grey level display voltage is equal to vlcd */
+typedef enum {
+	LCD_VGS_0  = 0U, 	/**< Grey level display voltage is 30/45 vlcd */
+	LCD_VGS_1  = 1U, 	/**< Grey level display voltage is 31/45 vlcd */
+	LCD_VGS_2  = 2U, 	/**< Grey level display voltage is 32/45 vlcd */
+	LCD_VGS_3  = 3U, 	/**< Grey level display voltage is 33/45 vlcd */
+	LCD_VGS_4  = 4U, 	/**< Grey level display voltage is 34/45 vlcd */
+	LCD_VGS_5  = 5U, 	/**< Grey level display voltage is 35/45 vlcd */
+	LCD_VGS_6  = 6U, 	/**< Grey level display voltage is 36/45 vlcd */
+	LCD_VGS_7  = 7U, 	/**< Grey level display voltage is 37/45 vlcd */
+	LCD_VGS_8  = 8U, 	/**< Grey level display voltage is 38/45 vlcd */
+	LCD_VGS_9  = 9U, 	/**< Grey level display voltage is 39/45 vlcd */
+	LCD_VGS_10 = 10U,	/**< Grey level display voltage is 40/45 vlcd */
+	LCD_VGS_11 = 11U,	/**< Grey level display voltage is 41/45 vlcd */
+	LCD_VGS_12 = 12U,	/**< Grey level display voltage is 42/45 vlcd */
+	LCD_VGS_13 = 13U,	/**< Grey level display voltage is 43/45 vlcd */
+	LCD_VGS_14 = 14U,	/**< Grey level display voltage is 44/45 vlcd */
+	LCD_VGS_15 = 15U,	/**< Grey level display voltage is equal to vlcd */
 } lcd_vgs_t;
 
 /**
   * @brief Lcd wave choose
   */
-typedef enum
-{
-    LCD_WAVE_A = 0,	/**< Wave type is A */
-    LCD_WAVE_B = 1,	/**< Wave type is B */
+typedef enum {
+	LCD_WAVE_A = 0U,	/**< Wave type is A */
+	LCD_WAVE_B = 1U,	/**< Wave type is B */
 } lcd_wfs_t;
 
 /**
   * @brief Lcd status select bit
   */
-typedef enum
-{
-    LCD_STATUS_RDY   = (1U << 0),	/**< VLCD voltage state flag */
-    LCD_STATUS_ENS   = (1U << 1),	/**< LCD Enable state flag*/
-    LCD_STATUS_UDR   = (1U << 2),	/**< Update display request state flag */
-    LCD_STATUS_FCRSF = (1U << 3),	/**< LCD frame control sync flag */
-    LCD_STATUS_ALL   = 0xFFFFFFF,	/**< All flag */
+typedef enum {
+	LCD_STATUS_RDY   = (1U << 0),	/**< VLCD voltage state flag */
+	LCD_STATUS_ENS   = (1U << 1),	/**< LCD Enable state flag*/
+	LCD_STATUS_UDR   = (1U << 2),	/**< Update display request state flag */
+	LCD_STATUS_FCRSF = (1U << 3),	/**< LCD frame control sync flag */
+	LCD_STATUS_ALL   = 0xFFFFFFFU,	/**< All flag */
 } lcd_status_t;
 
 /**
   * @brief Lcd interrupt type
   */
-typedef enum
-{
-    LCD_IT_SOF = (1U << 0),	/**< Start of frame interrupt enable */
-    LCD_IT_UDD = (1U << 1),	/**< Update display done interrupt enable*/
+typedef enum {
+	LCD_IT_SOF = (1U << 0),	/**< Start of frame interrupt enable */
+	LCD_IT_UDD = (1U << 1),	/**< Update display done interrupt enable*/
 } lcd_it_t;
 
 /**
   * @brief Lcd interrupt flag
   */
-typedef enum
-{
-    LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/
-    LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/
+typedef enum {
+	LCD_FLAG_SOF = (1U << 0), /**< Start of frame interrupt enable flag*/
+	LCD_FLAG_UDD = (1U << 1), /**< Update display done interrupt enable flag*/
 } lcd_flag_t;
 
 /**
   * @brief Lcd interrupt type
   */
-typedef enum
-{
-    SEG_0_TO_31  = 0,	/**< Segment 0 to 31 to be set */
-    SEG_32_TO_59 = 1,	/**< Segment 32 to 59 to be set */
+typedef enum {
+	SEG_0_TO_31  = 0U,	/**< Segment 0 to 31 to be set */
+	SEG_32_TO_59 = 1U,	/**< Segment 32 to 59 to be set */
 } lcd_seg_t;
 
 /**
@@ -276,36 +258,35 @@ typedef enum
   */
 typedef struct
 {
-    lcd_vsel_t lcd_vsel;      	/**< Lcd power choose */
-    lcd_vchps_t lcd_vchps;    	/**< Charge pump voltage choose */
-    lcd_func_t lcd_vbufld;    	/**< Low drive mode function */
-    lcd_func_t lcd_vbufhd;    	/**< High drive mode function */
-    uint32_t lcd_dsld;        	/**< Low drive mode level */
-    uint32_t lcd_dshd;        	/**< High drive mode level */
-    lcd_res_t lcd_resld;      	/**< Low dirve mode resistance choose */
-    lcd_res_t lcd_reshd;      	/**< High dirve mode resistance choose */
-    lcd_bias_t lcd_bias;      	/**< LCD bias */
-    lcd_duty_t lcd_duty;      	/**< LCD duty */
-    lcd_wfs_t lcd_wfs;        	/**< Wave choose */
-    lcd_prs_t lcd_prs;        	/**< Lcd clock prs */
-    lcd_div_t lcd_div;        	/**< Lcd div */
-    lcd_dead_t lcd_dead;      	/**< Lcd dead time */
-    lcd_pluse_on_t lcd_pon;   	/**< Lcd pluse on time */
-    lcd_vgs_t lcd_vgs;        	/**< Lcd gray level display voltage */
-    cmu_lcd_clock_sel_t clock;	/**< Lcd clock choose */
+	lcd_vsel_t lcd_vsel;      	/**< Lcd power choose */
+	lcd_vchps_t lcd_vchps;    	/**< Charge pump voltage choose */
+	lcd_func_t lcd_vbufld;    	/**< Low drive mode function */
+	lcd_func_t lcd_vbufhd;    	/**< High drive mode function */
+	uint32_t lcd_dsld;        	/**< Low drive mode level */
+	uint32_t lcd_dshd;        	/**< High drive mode level */
+	lcd_res_t lcd_resld;      	/**< Low dirve mode resistance choose */
+	lcd_res_t lcd_reshd;      	/**< High dirve mode resistance choose */
+	lcd_bias_t lcd_bias;      	/**< LCD bias */
+	lcd_duty_t lcd_duty;      	/**< LCD duty */
+	lcd_wfs_t lcd_wfs;        	/**< Wave choose */
+	lcd_prs_t lcd_prs;        	/**< Lcd clock prs */
+	lcd_div_t lcd_div;        	/**< Lcd div */
+	lcd_dead_t lcd_dead;      	/**< Lcd dead time */
+	lcd_pluse_on_t lcd_pon;   	/**< Lcd pluse on time */
+	lcd_vgs_t lcd_vgs;        	/**< Lcd gray level display voltage */
+	cmu_lcd_clock_sel_t clock;	/**< Lcd clock choose */
 } lcd_init_t;
 
 /**
   * @brief  Lcd handle Structure definition
   */
-typedef struct lcd_handle_s
-{
-    LCD_TypeDef *perh;	/**< LCD registers base address */
-    lcd_init_t init;  	/**< LCD initialize parameters */
-    lock_state_t lock;	/**< Locking object */
+typedef struct lcd_handle_s {
+	LCD_TypeDef *perh;	/**< LCD registers base address */
+	lcd_init_t init;  	/**< LCD initialize parameters */
+	lock_state_t lock;	/**< Locking object */
 
-    void (*display_cplt_cbk)(struct lcd_handle_s *arg);	/**< Display completed callback */
-    void (*frame_start_cbk)(struct lcd_handle_s *arg); 	/**< Frame start callback */
+	void (*display_cplt_cbk)(struct lcd_handle_s *arg);	/**< Display completed callback */
+	void (*frame_start_cbk)(struct lcd_handle_s *arg); 	/**< Frame start callback */
 } lcd_handle_t;
 
 /**
@@ -327,77 +308,77 @@ typedef struct lcd_handle_s
   */
 #define IS_LCD_PERH_TYPE(x)	((x) == LCD)
 #define IS_LCD_VCHPS_TYPE(x)    (((x) == LCD_VCHPS_3V2) || \
-                                 ((x) == LCD_VCHPS_3V8) || \
-                                 ((x) == LCD_VCHPS_4V8) || \
-                                 ((x) == LCD_VCHPS_5V4))
+				 ((x) == LCD_VCHPS_3V8) || \
+				 ((x) == LCD_VCHPS_4V8) || \
+				 ((x) == LCD_VCHPS_5V4))
 #define IS_LCD_VSEL_TYPE(x)     (((x) == LCD_VSEL_VDD) || \
-                                 ((x) == LCD_VSEL_CP)  || \
-                                 ((x) == LCD_VSEL_VLCD))
+				 ((x) == LCD_VSEL_CP)  || \
+				 ((x) == LCD_VSEL_VLCD))
 #define IS_LCD_FUNC_TYPE(x)	(((x) == LCD_FUNC_DISABLE) || \
-                             ((x) == LCD_FUNC_ENABLE))
+				 ((x) == LCD_FUNC_ENABLE))
 #define IS_LCD_LEVEL_TYPE(x)	(((x) > 0) | ((x) <= 0xF))
 #define IS_LCD_RES_TYPE(x)      (((x) == LCD_RES_1MOHM) || \
-                                 ((x) == LCD_RES_2MOHM) || \
-                                 ((x) == LCD_RES_3MOHM))
+				 ((x) == LCD_RES_2MOHM) || \
+				 ((x) == LCD_RES_3MOHM))
 #define IS_LCD_BIAS_TYPE(x)     (((x) == LCD_BIAS_1_4) || \
-                                 ((x) == LCD_BIAS_1_2) || \
-                                 ((x) == LCD_BIAS_1_3))
+				 ((x) == LCD_BIAS_1_2) || \
+				 ((x) == LCD_BIAS_1_3))
 #define IS_LCD_DUTY_TYPE(x)     (((x) == LCD_DUTY_STATIC) || \
-                                 ((x) == LCD_DUTY_1_2)    || \
-                                 ((x) == LCD_DUTY_1_3)    || \
-                                 ((x) == LCD_DUTY_1_4)    || \
-                                 ((x) == LCD_DUTY_1_6)    || \
-                                 ((x) == LCD_DUTY_1_8))
+				 ((x) == LCD_DUTY_1_2)    || \
+				 ((x) == LCD_DUTY_1_3)    || \
+				 ((x) == LCD_DUTY_1_4)    || \
+				 ((x) == LCD_DUTY_1_6)    || \
+				 ((x) == LCD_DUTY_1_8))
 #define IS_LCD_WFS_TYPE(x)	(((x) == LCD_WAVE_A) || \
-                             ((x) == LCD_WAVE_B))
+				 ((x) == LCD_WAVE_B))
 #define IS_LCD_PRS_TYPE(x)      (((x) == LCD_PRS_1)     || \
-                                 ((x) == LCD_PRS_2)     || \
-                                 ((x) == LCD_PRS_4)     || \
-                                 ((x) == LCD_PRS_8)     || \
-                                 ((x) == LCD_PRS_16)    || \
-                                 ((x) == LCD_PRS_32)    || \
-                                 ((x) == LCD_PRS_64)    || \
-                                 ((x) == LCD_PRS_128)   || \
-                                 ((x) == LCD_PRS_256)   || \
-                                 ((x) == LCD_PRS_512)   || \
-                                 ((x) == LCD_PRS_1024)  || \
-                                 ((x) == LCD_PRS_2048)  || \
-                                 ((x) == LCD_PRS_4096)  || \
-                                 ((x) == LCD_PRS_8192)  || \
-                                 ((x) == LCD_PRS_16384) || \
-                                 ((x) == LCD_PRS_32768))
+				 ((x) == LCD_PRS_2)     || \
+				 ((x) == LCD_PRS_4)     || \
+				 ((x) == LCD_PRS_8)     || \
+				 ((x) == LCD_PRS_16)    || \
+				 ((x) == LCD_PRS_32)    || \
+				 ((x) == LCD_PRS_64)    || \
+				 ((x) == LCD_PRS_128)   || \
+				 ((x) == LCD_PRS_256)   || \
+				 ((x) == LCD_PRS_512)   || \
+				 ((x) == LCD_PRS_1024)  || \
+				 ((x) == LCD_PRS_2048)  || \
+				 ((x) == LCD_PRS_4096)  || \
+				 ((x) == LCD_PRS_8192)  || \
+				 ((x) == LCD_PRS_16384) || \
+				 ((x) == LCD_PRS_32768))
 #define IS_LCD_DIV_TYPE(x)      (((x) == LCD_DIV_16) || \
-                                 ((x) == LCD_DIV_17) || \
-                                 ((x) == LCD_DIV_18) || \
-                                 ((x) == LCD_DIV_19) || \
-                                 ((x) == LCD_DIV_20) || \
-                                 ((x) == LCD_DIV_21) || \
-                                 ((x) == LCD_DIV_22) || \
-                                 ((x) == LCD_DIV_23) || \
-                                 ((x) == LCD_DIV_24) || \
-                                 ((x) == LCD_DIV_25) || \
-                                 ((x) == LCD_DIV_26) || \
-                                 ((x) == LCD_DIV_27) || \
-                                 ((x) == LCD_DIV_28) || \
-                                 ((x) == LCD_DIV_29) || \
-                                 ((x) == LCD_DIV_30) || \
-                                 ((x) == LCD_DIV_31))
+				 ((x) == LCD_DIV_17) || \
+				 ((x) == LCD_DIV_18) || \
+				 ((x) == LCD_DIV_19) || \
+				 ((x) == LCD_DIV_20) || \
+				 ((x) == LCD_DIV_21) || \
+				 ((x) == LCD_DIV_22) || \
+				 ((x) == LCD_DIV_23) || \
+				 ((x) == LCD_DIV_24) || \
+				 ((x) == LCD_DIV_25) || \
+				 ((x) == LCD_DIV_26) || \
+				 ((x) == LCD_DIV_27) || \
+				 ((x) == LCD_DIV_28) || \
+				 ((x) == LCD_DIV_29) || \
+				 ((x) == LCD_DIV_30) || \
+				 ((x) == LCD_DIV_31))
 #define IS_LCD_BLINK_MODE(x)    (((x) == LCD_BLINK_OFF)        || \
-                                 ((x) == LCD_BLINK_SEG0_COM0)  || \
-                                 ((x) == LCD_BLINK_SEG0_COMX2) || \
-                                 ((x) == LCD_BLINK_ALLSEG_ALLCOM))
+				 ((x) == LCD_BLINK_SEG0_COM0)  || \
+				 ((x) == LCD_BLINK_SEG0_COMX2) || \
+				 ((x) == LCD_BLINK_ALLSEG_ALLCOM))
 #define IS_LCD_BLFRQ_TYPE(x)    (((x) == LCD_BLFRQ_8)   || \
-                                 ((x) == LCD_BLFRQ_16)  || \
-                                 ((x) == LCD_BLFRQ_32)  || \
-                                 ((x) == LCD_BLFRQ_64)  || \
-                                 ((x) == LCD_BLFRQ_128) || \
-                                 ((x) == LCD_BLFRQ_256) || \
-                                 ((x) == LCD_BLFRQ_512) || \
-                                 ((x) == LCD_BLFRQ_1024))
+				 ((x) == LCD_BLFRQ_16)  || \
+				 ((x) == LCD_BLFRQ_32)  || \
+				 ((x) == LCD_BLFRQ_64)  || \
+				 ((x) == LCD_BLFRQ_128) || \
+				 ((x) == LCD_BLFRQ_256) || \
+				 ((x) == LCD_BLFRQ_512) || \
+				 ((x) == LCD_BLFRQ_1024))
 #define IS_LCD_STATUS_TYPE(x) 	(((x) == LCD_STATUS_RDY)   || \
                                  ((x) == LCD_STATUS_ENS)   || \
                                  ((x) == LCD_STATUS_UDR)   || \
-                                 ((x) == LCD_STATUS_FCRSF) || \
+				 ((x) == LCD_STATUS_FCRSF) || \
                                  ((x) == LCD_STATUS_ALL))
 #define IS_LCD_CLEARFLAG_TYPE(x)(((x) == LCD_FLAG_SOF) || \
                                  ((x) == LCD_FLAG_UDD) || \
@@ -405,41 +386,41 @@ typedef struct lcd_handle_s
 #define IS_LCD_IT_TYPE(x)      	(((x) == LCD_IT_SOF) || \
                                  ((x) == LCD_IT_UDD))
 #define IS_LCD_FLAG_TYPE(x)	(((x) == LCD_FLAG_SOF) || \
-                             ((x) == LCD_FLAG_UDD))
+				 ((x) == LCD_FLAG_UDD))
 #define IS_LCD_SEG_TYPE(x)	(((x) == SEG_0_TO_31) || \
-                             ((x) == SEG_32_TO_59))
+				 ((x) == SEG_32_TO_59))
 #define IS_LCD_DEAD_TYPE(x)	(((x) == LCD_DEAD_TIME_NONE)     || \
-                             ((x) == LCD_DEAD_TIME_1_DIVCLK) || \
-                             ((x) == LCD_DEAD_TIME_2_DIVCLK) || \
-                             ((x) == LCD_DEAD_TIME_3_DIVCLK) || \
-                             ((x) == LCD_DEAD_TIME_4_DIVCLK) || \
-                             ((x) == LCD_DEAD_TIME_5_DIVCLK) || \
-                             ((x) == LCD_DEAD_TIME_6_DIVCLK) || \
-                             ((x) == LCD_DEAD_TIME_7_DIVCLK))
+				 ((x) == LCD_DEAD_TIME_1_DIVCLK) || \
+				 ((x) == LCD_DEAD_TIME_2_DIVCLK) || \
+				 ((x) == LCD_DEAD_TIME_3_DIVCLK) || \
+				 ((x) == LCD_DEAD_TIME_4_DIVCLK) || \
+				 ((x) == LCD_DEAD_TIME_5_DIVCLK) || \
+				 ((x) == LCD_DEAD_TIME_6_DIVCLK) || \
+				 ((x) == LCD_DEAD_TIME_7_DIVCLK))
 #define IS_LCD_PON_TYPE(x)	(((x) == LCD_PON_NONE)     || \
-                             ((x) == LCD_PON_1_PRSCLK) || \
-                             ((x) == LCD_PON_2_PRSCLK) || \
-                             ((x) == LCD_PON_3_PRSCLK) || \
-                             ((x) == LCD_PON_4_PRSCLK) || \
-                             ((x) == LCD_PON_5_PRSCLK) || \
-                             ((x) == LCD_PON_6_PRSCLK) || \
-                             ((x) == LCD_PON_7_PRSCLK))
+				 ((x) == LCD_PON_1_PRSCLK) || \
+				 ((x) == LCD_PON_2_PRSCLK) || \
+				 ((x) == LCD_PON_3_PRSCLK) || \
+				 ((x) == LCD_PON_4_PRSCLK) || \
+				 ((x) == LCD_PON_5_PRSCLK) || \
+				 ((x) == LCD_PON_6_PRSCLK) || \
+				 ((x) == LCD_PON_7_PRSCLK))
 #define IS_LCD_VGS_TYPE(x)	(((x) == LCD_VGS_0)  || \
-                             ((x) == LCD_VGS_1)  || \
-                             ((x) == LCD_VGS_2)  || \
-                             ((x) == LCD_VGS_3)  || \
-                             ((x) == LCD_VGS_4)  || \
-                             ((x) == LCD_VGS_5)  || \
-                             ((x) == LCD_VGS_6)  || \
-                             ((x) == LCD_VGS_7)  || \
-                             ((x) == LCD_VGS_8)  || \
-                             ((x) == LCD_VGS_9)  || \
-                             ((x) == LCD_VGS_10) || \
-                             ((x) == LCD_VGS_11) || \
-                             ((x) == LCD_VGS_12) || \
-                             ((x) == LCD_VGS_13) || \
-                             ((x) == LCD_VGS_14) || \
-                             ((x) == LCD_VGS_15))
+				 ((x) == LCD_VGS_1)  || \
+				 ((x) == LCD_VGS_2)  || \
+				 ((x) == LCD_VGS_3)  || \
+				 ((x) == LCD_VGS_4)  || \
+				 ((x) == LCD_VGS_5)  || \
+				 ((x) == LCD_VGS_6)  || \
+				 ((x) == LCD_VGS_7)  || \
+				 ((x) == LCD_VGS_8)  || \
+				 ((x) == LCD_VGS_9)  || \
+				 ((x) == LCD_VGS_10) || \
+				 ((x) == LCD_VGS_11) || \
+				 ((x) == LCD_VGS_12) || \
+				 ((x) == LCD_VGS_13) || \
+				 ((x) == LCD_VGS_14) || \
+				 ((x) == LCD_VGS_15))
 #define IS_LCD_BUFFER_TYPE(x)	((x) <= 15)
 
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lptim.h

@@ -19,7 +19,7 @@
 #define __ALD_LPTIM_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -41,179 +41,163 @@ extern "C" {
 /**
   * @brief LPTIM clock select
   */
-typedef enum
-{
-    LPTIM_CKSEL_INTERNAL = 0,	/**< Select internal clock */
-    LPTIM_CKSEL_EXTERNAL = 1,	/**< Select external clock */
+typedef enum {
+	LPTIM_CKSEL_INTERNAL = 0U,	/**< Select internal clock */
+	LPTIM_CKSEL_EXTERNAL = 1U,	/**< Select external clock */
 } lptim_cksel_t;
 
 /**
   * @brief LPTIM clock pol
   */
-typedef enum
-{
-    LPTIM_CKPOL_RISING  = 0,	/**< using rising edge */
-    LPTIM_CKPOL_FALLING = 1,	/**< using falling edge */
+typedef enum {
+	LPTIM_CKPOL_RISING  = 0U,	/**< using rising edge */
+	LPTIM_CKPOL_FALLING = 1U,	/**< using falling edge */
 } lptim_ckpol_t;
 
 /**
   * @brief LPTIM clock fliter
   */
-typedef enum
-{
-    LPTIM_CKFLT_0 = 0,	/**< not clock filter */
-    LPTIM_CKFLT_2 = 1,	/**< 2 cycle filter */
-    LPTIM_CKFLT_4 = 2,	/**< 4 cycle filter */
-    LPTIM_CKFLT_8 = 3,	/**< 8 cycle filter */
+typedef enum {
+	LPTIM_CKFLT_0 = 0U,	/**< not clock filter */
+	LPTIM_CKFLT_2 = 1U,	/**< 2 cycle filter */
+	LPTIM_CKFLT_4 = 2U,	/**< 4 cycle filter */
+	LPTIM_CKFLT_8 = 3U,	/**< 8 cycle filter */
 } lptim_ckflt_t;
 
 /**
   * @brief LPTIM trigger fliter
   */
-typedef enum
-{
-    LPTIM_TRGFLT_0 = 0,	/**< not clock filter */
-    LPTIM_TRGFLT_2 = 1,	/**< 2 cycle filter */
-    LPTIM_TRGFLT_4 = 2,	/**< 4 cycle filter */
-    LPTIM_TRGFLT_8 = 3,	/**< 8 cycle filter */
+typedef enum {
+	LPTIM_TRGFLT_0 = 0U,	/**< not clock filter */
+	LPTIM_TRGFLT_2 = 1U,	/**< 2 cycle filter */
+	LPTIM_TRGFLT_4 = 2U,	/**< 4 cycle filter */
+	LPTIM_TRGFLT_8 = 3U,	/**< 8 cycle filter */
 } lptim_trgflt_t;
 
 /**
   * @brief LPTIM prescaler
   */
-typedef enum
-{
-    LPTIM_PRESC_1   = 0,	/**< No prescaler is used */
-    LPTIM_PRESC_2   = 1,	/**< Clock is divided by 2 */
-    LPTIM_PRESC_4   = 2,	/**< Clock is divided by 4 */
-    LPTIM_PRESC_8   = 3,	/**< Clock is divided by 8 */
-    LPTIM_PRESC_16  = 4,	/**< Clock is divided by 16 */
-    LPTIM_PRESC_32  = 5,	/**< Clock is divided by 32 */
-    LPTIM_PRESC_64  = 6,	/**< Clock is divided by 64 */
-    LPTIM_PRESC_128 = 7,	/**< Clock is divided by 128 */
+typedef enum {
+	LPTIM_PRESC_1   = 0U,	/**< No prescaler is used */
+	LPTIM_PRESC_2   = 1U,	/**< Clock is divided by 2 */
+	LPTIM_PRESC_4   = 2U,	/**< Clock is divided by 4 */
+	LPTIM_PRESC_8   = 3U,	/**< Clock is divided by 8 */
+	LPTIM_PRESC_16  = 4U,	/**< Clock is divided by 16 */
+	LPTIM_PRESC_32  = 5U,	/**< Clock is divided by 32 */
+	LPTIM_PRESC_64  = 6U,	/**< Clock is divided by 64 */
+	LPTIM_PRESC_128 = 7U,	/**< Clock is divided by 128 */
 } lptim_presc_t;
 
 /**
   * @brief LPTIM trig select
   */
-typedef enum
-{
-    LPTIM_TRIGSEL_EXT0 = 0,	/**< Trigger select external channel 0 */
-    LPTIM_TRIGSEL_EXT1 = 1,	/**< Trigger select external channel 1 */
-    LPTIM_TRIGSEL_EXT2 = 2,	/**< Trigger select external channel 2 */
-    LPTIM_TRIGSEL_EXT3 = 3,	/**< Trigger select external channel 3 */
-    LPTIM_TRIGSEL_EXT4 = 4,	/**< Trigger select external channel 4 */
-    LPTIM_TRIGSEL_EXT5 = 5,	/**< Trigger select external channel 5 */
-    LPTIM_TRIGSEL_EXT6 = 6,	/**< Trigger select external channel 6 */
-    LPTIM_TRIGSEL_EXT7 = 7,	/**< Trigger select external channel 7 */
+typedef enum {
+	LPTIM_TRIGSEL_EXT0 = 0U,	/**< Trigger select external channel 0 */
+	LPTIM_TRIGSEL_EXT1 = 1U,	/**< Trigger select external channel 1 */
+	LPTIM_TRIGSEL_EXT2 = 2U,	/**< Trigger select external channel 2 */
+	LPTIM_TRIGSEL_EXT3 = 3U,	/**< Trigger select external channel 3 */
+	LPTIM_TRIGSEL_EXT4 = 4U,	/**< Trigger select external channel 4 */
+	LPTIM_TRIGSEL_EXT5 = 5U,	/**< Trigger select external channel 5 */
+	LPTIM_TRIGSEL_EXT6 = 6U,	/**< Trigger select external channel 6 */
+	LPTIM_TRIGSEL_EXT7 = 7U,	/**< Trigger select external channel 7 */
 } lptim_trigsel_t;
 
 /**
   * @brief LPTIM start mode select
   */
-typedef enum
-{
-    LPTIM_MODE_SINGLE     = 0,	/**< Start single mode */
-    LPTIM_MODE_CONTINUOUS = 1,	/**< Start continuous mode */
+typedef enum {
+	LPTIM_MODE_SINGLE     = 0U,	/**< Start single mode */
+	LPTIM_MODE_CONTINUOUS = 1U,	/**< Start continuous mode */
 } lptim_mode_t;
 
 /**
   * @brief LPTIM trig en
   */
-typedef enum
-{
-    LPTIM_TRIGEN_SW      = 0,	/**< software trigger */
-    LPTIM_TRIGEN_RISING  = 1,	/**< rising edge trigger */
-    LPTIM_TRIGEN_FALLING = 2,	/**< falling edge trigger */
-    LPTIM_TRIGEN_BOTH    = 3,	/**< rising and falling edge trigger */
+typedef enum {
+	LPTIM_TRIGEN_SW      = 0U,	/**< software trigger */
+	LPTIM_TRIGEN_RISING  = 1U,	/**< rising edge trigger */
+	LPTIM_TRIGEN_FALLING = 2U,	/**< falling edge trigger */
+	LPTIM_TRIGEN_BOTH    = 3U,	/**< rising and falling edge trigger */
 } lptim_trigen_t;
 
 /**
   * @brief LPTIM wave
   */
-typedef enum
-{
-    LPTIM_WAVE_NONE   = 0,	/**< Output close */
-    LPTIM_WAVE_TOGGLE = 1,	/**< Output toggle */
-    LPTIM_WAVE_PULSE  = 2,	/**< Output pulse */
-    LPTIM_WAVE_PWM    = 3,	/**< Output PWM */
+typedef enum {
+	LPTIM_WAVE_NONE   = 0U,	/**< Output close */
+	LPTIM_WAVE_TOGGLE = 1U,	/**< Output toggle */
+	LPTIM_WAVE_PULSE  = 2U,	/**< Output pulse */
+	LPTIM_WAVE_PWM    = 3U,	/**< Output PWM */
 } lptim_wave_t;
 
 /**
   * @brief LPTIM interrupt
   */
-typedef enum
-{
-    LPTIM_IT_CMPMAT  = 1,	/**< Compare interrupt bit */
-    LPTIM_IT_ARRMAT  = 2,	/**< Update interrupt bit */
-    LPTIM_IT_EXTTRIG = 4,	/**< external trigger interrupt bit */
+typedef enum {
+	LPTIM_IT_CMPMAT  = 1U,	/**< Compare interrupt bit */
+	LPTIM_IT_ARRMAT  = 2U,	/**< Update interrupt bit */
+	LPTIM_IT_EXTTRIG = 4U,	/**< external trigger interrupt bit */
 } lptim_it_t;
 
 /**
   * @brief LPTIM Interrupt flag
   */
-typedef enum
-{
-    LPTIM_FLAG_CMPMAT  = 1,	/**< Compare interrupt flag */
-    LPTIM_FLAG_ARRMAT  = 2,	/**< Update interrupt flag */
-    LPTIM_FLAG_EXTTRIG = 4,	/**< Update interrupt flag */
+typedef enum {
+	LPTIM_FLAG_CMPMAT  = 1U,	/**< Compare interrupt flag */
+	LPTIM_FLAG_ARRMAT  = 2U,	/**< Update interrupt flag */
+	LPTIM_FLAG_EXTTRIG = 4U,	/**< Update interrupt flag */
 } lptim_flag_t;
 
 /**
   * @brief LPTIM state structures definition
   */
-typedef enum
-{
-    LPTIM_STATE_RESET   = 0x00,	/**< Peripheral not yet initialized or disabled */
-    LPTIM_STATE_READY   = 0x01,	/**< Peripheral Initialized and ready for use */
-    LPTIM_STATE_BUSY    = 0x02,	/**< An internal process is ongoing */
-    LPTIM_STATE_TIMEOUT = 0x03,	/**< Timeout state */
-    LPTIM_STATE_ERROR   = 0x04,	/**< Reception process is ongoing */
+typedef enum {
+	LPTIM_STATE_RESET   = 0x00U,	/**< Peripheral not yet initialized or disabled */
+	LPTIM_STATE_READY   = 0x01U,	/**< Peripheral Initialized and ready for use */
+	LPTIM_STATE_BUSY    = 0x02U,	/**< An internal process is ongoing */
+	LPTIM_STATE_TIMEOUT = 0x03U,	/**< Timeout state */
+	LPTIM_STATE_ERROR   = 0x04U,	/**< Reception process is ongoing */
 } lptim_state_t;
 
 /**
   * @brief LPTIM Init Structure definition
   */
-typedef struct
-{
-    lptim_presc_t psc;		/**< Specifies the prescaler value */
-    uint16_t arr;			/**< Specifies the update value */
-    uint16_t cmp;			/**< Specifies the compare value */
-    cmu_lp_perh_clock_sel_t clock;	/**< Specifies the clock choose */
-    lptim_mode_t mode;		/**< Specifies the start mode */
+typedef struct {
+	lptim_presc_t psc;		/**< Specifies the prescaler value */
+	uint16_t arr;			/**< Specifies the update value */
+	uint16_t cmp;			/**< Specifies the compare value */
+	cmu_lp_perh_clock_sel_t clock;	/**< Specifies the clock choose */
+	lptim_mode_t mode;		/**< Specifies the start mode */
 } lptim_init_t;
 
 /**
   * @brief LPTIM trigger Structure definition
   */
-typedef struct
-{
-    lptim_trigen_t mode;	/**< Specifies the trigger mode */
-    lptim_trigsel_t sel;	/**< Specifies the trigger source select */
+typedef struct {
+	lptim_trigen_t mode;	/**< Specifies the trigger mode */
+	lptim_trigsel_t sel;	/**< Specifies the trigger source select */
 } lptim_trigger_init_t;
 
 /**
   * @brief LPTIM trigger Structure definition
   */
-typedef struct
-{
-    lptim_cksel_t sel;	/**< Specifies the clock select */
-    lptim_ckpol_t polarity;	/**< Specifies the clock polarity */
+typedef struct {
+	lptim_cksel_t sel;	/**< Specifies the clock select */
+	lptim_ckpol_t polarity;	/**< Specifies the clock polarity */
 } lptim_clock_source_init_t;
 
 /**
   * @brief  LPTIM Handle Structure definition
   */
-typedef struct lptim_handle_s
-{
-    LPTIM_TypeDef *perh;	/**< Register base address */
-    lptim_init_t init;	/**< LPTIM Time required parameters */
-    lock_state_t lock;	/**< Locking object */
-    lptim_state_t state;	/**< LPTIM operation state */
+typedef struct lptim_handle_s {
+	LPTIM_TypeDef *perh;	/**< Register base address */
+	lptim_init_t init;	/**< LPTIM Time required parameters */
+	lock_state_t lock;	/**< Locking object */
+	lptim_state_t state;	/**< LPTIM operation state */
 
-    void (*trig_cbk)(struct lptim_handle_s *arg);	/**< Trigger callback */
-    void (*update_cbk)(struct lptim_handle_s *arg);	/**< Update callback */
-    void (*cmp_cbk)(struct lptim_handle_s *arg);	/**< Compare callback */
+	void (*trig_cbk)(struct lptim_handle_s *arg);	/**< Trigger callback */
+	void (*update_cbk)(struct lptim_handle_s *arg);	/**< Update callback */
+	void (*cmp_cbk)(struct lptim_handle_s *arg);	/**< Compare callback */
 } lptim_handle_t;
 /**
   * @}
@@ -241,45 +225,45 @@ typedef struct lptim_handle_s
   */
 #define IS_LPTIM(x)		((x) == LPTIM0)
 #define IS_LPTIM_CKSEL(x)	(((x) == LPTIM_CKSEL_INTERNAL) || \
-                             ((x) == LPTIM_CKSEL_EXTERNAL))
+                                 ((x) == LPTIM_CKSEL_EXTERNAL))
 #define IS_LPTIM_CKPOL(x)	(((x) == LPTIM_CKPOL_RISING) || \
-                             ((x) == LPTIM_CKPOL_FALLING))
+                                 ((x) == LPTIM_CKPOL_FALLING))
 #define IS_LPTIM_MODE(x)	(((x) == LPTIM_MODE_SINGLE) || \
-                             ((x) == LPTIM_MODE_CONTINUOUS))
+                                 ((x) == LPTIM_MODE_CONTINUOUS))
 #define IS_LPTIM_CKFLT(x)	(((x) == LPTIM_CKFLT_0) || \
-                             ((x) == LPTIM_CKFLT_2) || \
-                             ((x) == LPTIM_CKFLT_4) || \
-                             ((x) == LPTIM_CKFLT_8))
+                                 ((x) == LPTIM_CKFLT_2) || \
+                                 ((x) == LPTIM_CKFLT_4) || \
+                                 ((x) == LPTIM_CKFLT_8))
 #define IS_LPTIM_TRGFLT(x)	(((x) == LPTIM_TRGFLT_0) || \
-                             ((x) == LPTIM_TRGFLT_2) || \
-                             ((x) == LPTIM_TRGFLT_4) || \
-                             ((x) == LPTIM_TRGFLT_8))
+                                 ((x) == LPTIM_TRGFLT_2) || \
+                                 ((x) == LPTIM_TRGFLT_4) || \
+                                 ((x) == LPTIM_TRGFLT_8))
 #define IS_LPTIM_PRESC(x)	(((x) == LPTIM_PRESC_1)  || \
-                             ((x) == LPTIM_PRESC_2)  || \
-                             ((x) == LPTIM_PRESC_4)  || \
-                             ((x) == LPTIM_PRESC_8)  || \
-                             ((x) == LPTIM_PRESC_16) || \
-                             ((x) == LPTIM_PRESC_32) || \
-                             ((x) == LPTIM_PRESC_64) || \
-                             ((x) == LPTIM_PRESC_128))
+                                 ((x) == LPTIM_PRESC_2)  || \
+                                 ((x) == LPTIM_PRESC_4)  || \
+                                 ((x) == LPTIM_PRESC_8)  || \
+                                 ((x) == LPTIM_PRESC_16) || \
+                                 ((x) == LPTIM_PRESC_32) || \
+                                 ((x) == LPTIM_PRESC_64) || \
+                                 ((x) == LPTIM_PRESC_128))
 #define IS_LPTIM_TRIGSEL(x)	(((x) == LPTIM_TRIGSEL_EXT0) || \
-                             ((x) == LPTIM_TRIGSEL_EXT1) || \
-                             ((x) == LPTIM_TRIGSEL_EXT2) || \
-                             ((x) == LPTIM_TRIGSEL_EXT3) || \
-                             ((x) == LPTIM_TRIGSEL_EXT4) || \
-                             ((x) == LPTIM_TRIGSEL_EXT5) || \
-                             ((x) == LPTIM_TRIGSEL_EXT6) || \
-                             ((x) == LPTIM_TRIGSEL_EXT7))
+                                 ((x) == LPTIM_TRIGSEL_EXT1) || \
+                                 ((x) == LPTIM_TRIGSEL_EXT2) || \
+                                 ((x) == LPTIM_TRIGSEL_EXT3) || \
+                                 ((x) == LPTIM_TRIGSEL_EXT4) || \
+                                 ((x) == LPTIM_TRIGSEL_EXT5) || \
+                                 ((x) == LPTIM_TRIGSEL_EXT6) || \
+                                 ((x) == LPTIM_TRIGSEL_EXT7))
 #define IS_LPTIM_TRIGEN(x)	(((x) == LPTIM_TRIGEN_SW)      || \
-                             ((x) == LPTIM_TRIGEN_RISING)  || \
-                             ((x) == LPTIM_TRIGEN_FALLING) || \
-                             ((x) == LPTIM_TRIGEN_BOTH))
+                                 ((x) == LPTIM_TRIGEN_RISING)  || \
+                                 ((x) == LPTIM_TRIGEN_FALLING) || \
+                                 ((x) == LPTIM_TRIGEN_BOTH))
 #define IS_LPTIM_IT(x)		(((x) == LPTIM_IT_CMPMAT) || \
-                             ((x) == LPTIM_IT_ARRMAT) || \
-                             ((x) == LPTIM_IT_EXTTRIG))
+                                 ((x) == LPTIM_IT_ARRMAT) || \
+                                 ((x) == LPTIM_IT_EXTTRIG))
 #define IS_LPTIM_FLAG(x)	(((x) == LPTIM_FLAG_CMPMAT) || \
-                             ((x) == LPTIM_FLAG_ARRMAT) || \
-                             ((x) == LPTIM_FLAG_EXTTRIG))
+                                 ((x) == LPTIM_FLAG_ARRMAT) || \
+                                 ((x) == LPTIM_FLAG_EXTTRIG))
 /**
   * @}
   */
@@ -303,6 +287,18 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt);
 /** @addtogroup LPTIM_Public_Functions_Group2
   * @{
   */
+ald_status_t ald_lptim_base_init(lptim_handle_t *hperh);
+void ald_lptim_base_start(lptim_handle_t *hperh);
+void ald_lptim_base_stop(lptim_handle_t *hperh);
+void ald_lptim_base_start_by_it(lptim_handle_t *hperh);
+void ald_lptim_base_stop_by_it(lptim_handle_t *hperh);
+/**
+  * @}
+  */
+
+/** @addtogroup LPTIM_Public_Functions_Group3
+  * @{
+  */
 ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh);
 void ald_lptim_toggle_start(lptim_handle_t *hperh);
 void ald_lptim_toggle_stop(lptim_handle_t *hperh);
@@ -312,7 +308,7 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh);
   * @}
   */
 
-/** @addtogroup LPTIM_Public_Functions_Group3
+/** @addtogroup LPTIM_Public_Functions_Group4
   * @{
   */
 ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh);
@@ -324,7 +320,7 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh);
   * @}
   */
 
-/** @addtogroup LPTIM_Public_Functions_Group4
+/** @addtogroup LPTIM_Public_Functions_Group5
   * @{
   */
 ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh);
@@ -336,7 +332,7 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh);
   * @}
   */
 
-/** @addtogroup LPTIM_Public_Functions_Group5
+/** @addtogroup LPTIM_Public_Functions_Group6
   * @{
   */
 void ald_lptim_irq_handler(lptim_handle_t *hperh);
@@ -348,7 +344,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag);
   * @}
   */
 
-/** @addtogroup LPTIM_Public_Functions_Group6
+/** @addtogroup LPTIM_Public_Functions_Group7
   * @{
   */
 lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh);

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_lpuart.h

@@ -126,207 +126,192 @@ extern "C" {
 /**
   * @brief LPUART Word Length
   */
-typedef enum
-{
-    LPUART_WORD_LENGTH_5B = 0x0,	/**< 5-bits */
-    LPUART_WORD_LENGTH_6B = 0x1,	/**< 6-bits */
-    LPUART_WORD_LENGTH_7B = 0x2,	/**< 7-bits */
-    LPUART_WORD_LENGTH_8B = 0x3,	/**< 8-bits */
-    LPUART_WORD_LENGTH_9B = 0x4,	/**< 9-bits */
+typedef enum {
+	LPUART_WORD_LENGTH_5B = 0x0U,	/**< 5-bits */
+	LPUART_WORD_LENGTH_6B = 0x1U,	/**< 6-bits */
+	LPUART_WORD_LENGTH_7B = 0x2U,	/**< 7-bits */
+	LPUART_WORD_LENGTH_8B = 0x3U,	/**< 8-bits */
+	LPUART_WORD_LENGTH_9B = 0x4U,	/**< 9-bits */
 } lpuart_word_length_t;
 
 /**
   * @brief LPUART Stop Bits
   */
-typedef enum
-{
-    LPUART_STOP_BITS_1 = 0x0,	/**< 1-bits */
-    LPUART_STOP_BITS_2 = 0x1,	/**< 2-bits */
+typedef enum {
+	LPUART_STOP_BITS_1 = 0x0U,	/**< 1-bits */
+	LPUART_STOP_BITS_2 = 0x1U,	/**< 2-bits */
 } lpuart_stop_bits_t;
 
 /**
   * @brief LPUART Parity
   */
-typedef enum
-{
-    LPUART_PARITY_NONE = 0x0,	/**< Not parity */
-    LPUART_PARITY_ODD  = 0x1,	/**< Odd parity */
-    LPUART_PARITY_EVEN = 0x3,	/**< Even parity */
+typedef enum {
+	LPUART_PARITY_NONE = 0x0U,	/**< Not parity */
+	LPUART_PARITY_ODD  = 0x1U,	/**< Odd parity */
+	LPUART_PARITY_EVEN = 0x3U,	/**< Even parity */
 } lpuart_parity_t;
 
 /**
   * @brief LPUART Mode
   */
-typedef enum
-{
-    LPUART_MODE_UART  = 0x0,	/**< UART */
-    LPUART_MODE_IrDA  = 0x2,	/**< IrDA */
-    LPUART_MODE_RS485 = 0x3,	/**< RS485 */
+typedef enum {
+	LPUART_MODE_UART  = 0x0U,	/**< UART */
+	LPUART_MODE_IrDA  = 0x2U,	/**< IrDA */
+	LPUART_MODE_RS485 = 0x3U,	/**< RS485 */
 } lpuart_mode_t;
 
 /**
   * @brief LPUART Hardware Flow Control
   */
-typedef enum
-{
-    LPUART_HW_FLOW_CTL_NONE    = 0x0,	/**< None */
-    LPUART_HW_FLOW_CTL_RTS     = 0x1,	/**< RTS */
-    LPUART_HW_FLOW_CTL_CTS     = 0x2,	/**< CTS */
-    LPUART_HW_FLOW_CTL_RTS_CTS = 0x3,	/**< RTS & CTS */
+typedef enum {
+	LPUART_HW_FLOW_CTL_NONE    = 0x0U,	/**< None */
+	LPUART_HW_FLOW_CTL_RTS     = 0x1U,	/**< RTS */
+	LPUART_HW_FLOW_CTL_CTS     = 0x2U,	/**< CTS */
+	LPUART_HW_FLOW_CTL_RTS_CTS = 0x3U,	/**< RTS & CTS */
 } lpuart_hw_flow_ctl_t;
 
 /**
   * @brief ALD LPUART State
   */
-typedef enum
-{
-    LPUART_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-    LPUART_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-    LPUART_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-    LPUART_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-    LPUART_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-    LPUART_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission Reception process is ongoing */
-    LPUART_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-    LPUART_STATE_ERROR      = 0x04,	/**< Error */
+typedef enum {
+	LPUART_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
+	LPUART_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
+	LPUART_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
+	LPUART_STATE_BUSY_TX    = 0x11U,	/**< Data Transmission process is ongoing */
+	LPUART_STATE_BUSY_RX    = 0x21U,	/**< Data Reception process is ongoing */
+	LPUART_STATE_BUSY_TX_RX = 0x31U,	/**< Data Transmission Reception process is ongoing */
+	LPUART_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
+	LPUART_STATE_ERROR      = 0x04U,	/**< Error */
 } lpuart_state_t;
 
 /**
   * @brief LPUART Error Codes
   */
-typedef enum
-{
-    LPUART_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-    LPUART_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-    LPUART_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-    LPUART_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-    LPUART_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-    LPUART_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
+typedef enum {
+	LPUART_ERROR_NONE = ((uint32_t)0x00U),	/**< No error */
+	LPUART_ERROR_PE   = ((uint32_t)0x01U),	/**< Parity error */
+	LPUART_ERROR_NE   = ((uint32_t)0x02U),	/**< Noise error */
+	LPUART_ERROR_FE   = ((uint32_t)0x04U),	/**< frame error */
+	LPUART_ERROR_ORE  = ((uint32_t)0x08U),	/**< Overrun error */
+	LPUART_ERROR_DMA  = ((uint32_t)0x10U),	/**< DMA transfer error */
 } lpuart_error_t;
 
 /**
   * @brief LPUART Init structure definition
   */
-typedef struct
-{
-    uint32_t baud;				/**< Specifies the lpuart communication baud rate */
-    lpuart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
-    lpuart_stop_bits_t stop_bits;		/**< Specifies the number of stop bits transmitted */
-    lpuart_parity_t parity;			/**< Specifies the parity mode */
-    lpuart_mode_t mode;			/**< Specifies uart mode */
-    lpuart_hw_flow_ctl_t fctl;		/**< Specifies wether the hardware flow control mode is enabled or disabled */
-    cmu_lp_perh_clock_sel_t clock;		/**< Specifies clock, only support LOSC and LRC */
+typedef struct {
+	uint32_t baud;				/**< Specifies the lpuart communication baud rate */
+	lpuart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
+	lpuart_stop_bits_t stop_bits;		/**< Specifies the number of stop bits transmitted */
+	lpuart_parity_t parity;			/**< Specifies the parity mode */
+	lpuart_mode_t mode;			/**< Specifies uart mode */
+	lpuart_hw_flow_ctl_t fctl;		/**< Specifies wether the hardware flow control mode is enabled or disabled */
+	cmu_lp_perh_clock_sel_t clock;		/**< Specifies clock, only support LOSC and LRC */
 } lpuart_init_t;
 
 /**
   * @brief  LPUART handle structure definition
   */
-typedef struct lpuart_handle_s
-{
-    LPUART_TypeDef *perh;		/**< LPUART registers base address */
-    lpuart_init_t init;		/**< LPUART communication parameters */
-    uint8_t *tx_buf;		/**< Pointer to LPUART Tx transfer Buffer */
-    uint16_t tx_size;		/**< LPUART Tx Transfer size */
-    uint16_t tx_count;		/**< LPUART Tx Transfer Counter */
-    uint8_t *rx_buf;		/**< Pointer to LPUART Rx transfer Buffer */
-    uint16_t rx_size;		/**< LPUART Rx Transfer size */
-    uint16_t rx_count;		/**< LPUART Rx Transfer Counter */
+typedef struct lpuart_handle_s {
+	LPUART_TypeDef *perh;		/**< LPUART registers base address */
+	lpuart_init_t init;		/**< LPUART communication parameters */
+	uint8_t *tx_buf;		/**< Pointer to LPUART Tx transfer Buffer */
+	uint16_t tx_size;		/**< LPUART Tx Transfer size */
+	uint16_t tx_count;		/**< LPUART Tx Transfer Counter */
+	uint8_t *rx_buf;		/**< Pointer to LPUART Rx transfer Buffer */
+	uint16_t rx_size;		/**< LPUART Rx Transfer size */
+	uint16_t rx_count;		/**< LPUART Rx Transfer Counter */
 #ifdef ALD_DMA
-    dma_handle_t hdmatx;		/**< LPUART Tx DMA Handle parameters */
-    dma_handle_t hdmarx;		/**< LPUART Rx DMA Handle parameters */
+	dma_handle_t hdmatx;		/**< LPUART Tx DMA Handle parameters */
+	dma_handle_t hdmarx;		/**< LPUART Rx DMA Handle parameters */
 #endif
-    lock_state_t lock;            	/**< Locking object */
-    lpuart_state_t state;		/**< LPUART communication state */
-    lpuart_error_t err_code;	/**< LPUART Error code */
+	lock_state_t lock;            	/**< Locking object */
+	lpuart_state_t state;		/**< LPUART communication state */
+	lpuart_error_t err_code;	/**< LPUART Error code */
 
-    void (*tx_cplt_cbk)(struct lpuart_handle_s *arg);	/**< Tx completed callback */
-    void (*rx_cplt_cbk)(struct lpuart_handle_s *arg);	/**< Rx completed callback */
-    void (*error_cbk)(struct lpuart_handle_s *arg);		/**< error callback */
+	void (*tx_cplt_cbk)(struct lpuart_handle_s *arg);	/**< Tx completed callback */
+	void (*rx_cplt_cbk)(struct lpuart_handle_s *arg);	/**< Rx completed callback */
+	void (*error_cbk)(struct lpuart_handle_s *arg);		/**< error callback */
 } lpuart_handle_t;
 
 /**
   * @brief LPUART RS485 Configure Structure definition
   */
-typedef struct
-{
-    type_func_t RS485_NMM;		/**< Normal Point Mode */
-    type_func_t RS485_AAD;		/**< Auto-Address Detect */
-    type_func_t RS485_AUD;		/**< Auto-Direction Mode */
-    type_func_t RS485_ADD_DET;	/**< Eable/Disable Address Detect */
-    uint8_t RS485_ADDCMP;		/**< Address for compare */
+typedef struct {
+	type_func_t RS485_NMM;		/**< Normal Point Mode */
+	type_func_t RS485_AAD;		/**< Auto-Address Detect */
+	type_func_t RS485_AUD;		/**< Auto-Direction Mode */
+	type_func_t RS485_ADD_DET;	/**< Eable/Disable Address Detect */
+	uint8_t RS485_ADDCMP;		/**< Address for compare */
 } lpuart_rs485_config_t;
 
 /**
   * @brief LPUART DMA Requests
   */
-typedef enum
-{
-    LPUART_DMA_REQ_TX = 0x0,	/**< TX dma */
-    LPUART_DMA_REQ_RX = 0x1,	/**< RX dma */
+typedef enum {
+	LPUART_DMA_REQ_TX = 0x0U,	/**< TX dma */
+	LPUART_DMA_REQ_RX = 0x1U,	/**< RX dma */
 } lpuart_dma_req_t;
 
 /**
   * @brief LPUART RXFIFO size
   */
-typedef enum
-{
-    LPUART_RXFIFO_1BYTE  = 0x0,	/**< 1-Byte */
-    LPUART_RXFIFO_4BYTE  = 0x1,	/**< 4-Bytes */
-    LPUART_RXFIFO_8BYTE  = 0x2,	/**< 8-Bytes */
-    LPUART_RXFIFO_14BYTE = 0x3,	/**< 14-Bytes */
+typedef enum {
+	LPUART_RXFIFO_1BYTE  = 0x0U,	/**< 1-Byte */
+	LPUART_RXFIFO_4BYTE  = 0x1U,	/**< 4-Bytes */
+	LPUART_RXFIFO_8BYTE  = 0x2U,	/**< 8-Bytes */
+	LPUART_RXFIFO_14BYTE = 0x3U,	/**< 14-Bytes */
 } lpuart_rxfifo_t;
 
 /**
   * @brief LPUART Interrupts Types
   */
-typedef enum
-{
-    LPUART_IT_RBR    = (1U << 0),	/**< RBR */
-    LPUART_IT_TBEMP  = (1U << 1),	/**< TBEMP */
-    LPUART_IT_CTSDET = (1U << 2),	/**< CTSDET */
-    LPUART_IT_RXTO   = (1U << 3),	/**< RXTO */
-    LPUART_IT_RXOV   = (1U << 4),	/**< RXOV */
-    LPUART_IT_TXOV   = (1U << 5),	/**< TXOV */
-    LPUART_IT_CTSWK  = (1U << 7),	/**< CTSWK */
-    LPUART_IT_DATWK  = (1U << 8),	/**< DATWK */
-    LPUART_IT_PERR   = (1U << 9),	/**< PERR */
-    LPUART_IT_FERR   = (1U << 10),	/**< FERR */
-    LPUART_IT_BRKERR = (1U << 11),	/**< BRKERR */
-    LPUART_IT_ADET   = (1U << 12),	/**< ADET */
-    LPUART_IT_TC     = (1U << 15),	/**< TC */
+typedef enum {
+	LPUART_IT_RBR    = (1U << 0),	/**< RBR */
+	LPUART_IT_TBEMP  = (1U << 1),	/**< TBEMP */
+	LPUART_IT_CTSDET = (1U << 2),	/**< CTSDET */
+	LPUART_IT_RXTO   = (1U << 3),	/**< RXTO */
+	LPUART_IT_RXOV   = (1U << 4),	/**< RXOV */
+	LPUART_IT_TXOV   = (1U << 5),	/**< TXOV */
+	LPUART_IT_CTSWK  = (1U << 7),	/**< CTSWK */
+	LPUART_IT_DATWK  = (1U << 8),	/**< DATWK */
+	LPUART_IT_PERR   = (1U << 9),	/**< PERR */
+	LPUART_IT_FERR   = (1U << 10),	/**< FERR */
+	LPUART_IT_BRKERR = (1U << 11),	/**< BRKERR */
+	LPUART_IT_ADET   = (1U << 12),	/**< ADET */
+	LPUART_IT_TC     = (1U << 15),	/**< TC */
 } lpuart_it_t;
 
 /**
   * @brief LPUART Flags Types
   */
-typedef enum
-{
-    LPUART_IF_RBR    = (1U << 0),	/**< RBR */
-    LPUART_IF_TBEMP  = (1U << 1),	/**< TBEMP */
-    LPUART_IF_CTSDET = (1U << 2),	/**< CTSDET */
-    LPUART_IF_RXTO   = (1U << 3),	/**< RXTO */
-    LPUART_IF_RXOV   = (1U << 4),	/**< RXOV */
-    LPUART_IF_TXOV   = (1U << 5),	/**< TXOV */
-    LPUART_IF_CTSWK  = (1U << 7),	/**< CTSWK */
-    LPUART_IF_DATWK  = (1U << 8),	/**< DATWK */
-    LPUART_IF_PERR   = (1U << 9),	/**< PERR */
-    LPUART_IF_FERR   = (1U << 10),	/**< FERR */
-    LPUART_IF_BRKERR = (1U << 11),	/**< BRKERR */
-    LPUART_IF_ADET   = (1U << 12),	/**< ADET */
-    LPUART_IF_TC     = (1U << 15),	/**< TC */
+typedef enum {
+	LPUART_IF_RBR    = (1U << 0),	/**< RBR */
+	LPUART_IF_TBEMP  = (1U << 1),	/**< TBEMP */
+	LPUART_IF_CTSDET = (1U << 2),	/**< CTSDET */
+	LPUART_IF_RXTO   = (1U << 3),	/**< RXTO */
+	LPUART_IF_RXOV   = (1U << 4),	/**< RXOV */
+	LPUART_IF_TXOV   = (1U << 5),	/**< TXOV */
+	LPUART_IF_CTSWK  = (1U << 7),	/**< CTSWK */
+	LPUART_IF_DATWK  = (1U << 8),	/**< DATWK */
+	LPUART_IF_PERR   = (1U << 9),	/**< PERR */
+	LPUART_IF_FERR   = (1U << 10),	/**< FERR */
+	LPUART_IF_BRKERR = (1U << 11),	/**< BRKERR */
+	LPUART_IF_ADET   = (1U << 12),	/**< ADET */
+	LPUART_IF_TC     = (1U << 15),	/**< TC */
 } lpuart_flag_t;
 
 /**
   * @brief LPUART Status Types
   */
-typedef enum
-{
-    LPUART_STAT_RXEMP   = (1U << 6),	/**< RX FIFO empty */
-    LPUART_STAT_RXFULL  = (1U << 7),	/**< RX FIFO full */
-    LPUART_STAT_TXEMP   = (1U << 14),	/**< TX FIFO empty */
-    LPUART_STAT_TXFULL  = (1U << 15),	/**< TX FIFO full */
-    LPUART_STAT_TXIDLE  = (1U << 16),	/**< TX idle */
-    LPUART_STAT_CTSSTAT = (1U << 17),	/**< CTS status */
-    LPUART_STAT_RTSSTAT = (1U << 18),	/**< RTS status */
+typedef enum {
+	LPUART_STAT_RXEMP   = (1U << 6),	/**< RX FIFO empty */
+	LPUART_STAT_RXFULL  = (1U << 7),	/**< RX FIFO full */
+	LPUART_STAT_TXEMP   = (1U << 14),	/**< TX FIFO empty */
+	LPUART_STAT_TXFULL  = (1U << 15),	/**< TX FIFO full */
+	LPUART_STAT_TXIDLE  = (1U << 16),	/**< TX idle */
+	LPUART_STAT_CTSSTAT = (1U << 17),	/**< CTS status */
+	LPUART_STAT_RTSSTAT = (1U << 18),	/**< RTS status */
 } lpuart_status_t;
 /**
   * @}
@@ -352,10 +337,10 @@ typedef enum
                             ((x) == LPUART_MODE_IrDA) || \
                             ((x) == LPUART_MODE_RS485))
 #define IS_LPUART_HARDWARE_FLOW_CONTROL(x)\
-    (((x) == LPUART_HW_FLOW_CTL_NONE) || \
-     ((x) == LPUART_HW_FLOW_CTL_RTS)  || \
-     ((x) == LPUART_HW_FLOW_CTL_CTS)  || \
-     ((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
+                              (((x) == LPUART_HW_FLOW_CTL_NONE) || \
+                               ((x) == LPUART_HW_FLOW_CTL_RTS)  || \
+                               ((x) == LPUART_HW_FLOW_CTL_CTS)  || \
+                               ((x) == LPUART_HW_FLOW_CTL_RTS_CTS))
 #define IS_LPUART_DMAREQ(x)  (((x) == LPUART_DMA_REQ_TX) || ((x) == LPUART_DMA_REQ_RX))
 #define IS_LPUART_RXFIFO(x)  (((x) == LPUART_RXFIFO_1BYTE) || \
                               ((x) == LPUART_RXFIFO_4BYTE) || \
@@ -388,15 +373,15 @@ typedef enum
                          ((x) == LPUART_IF_ADET)   || \
                          ((x) == LPUART_IF_TC))
 #define IS_LPUART_STAT(x)	(((x) == LPUART_STAT_RXEMP)   || \
-                             ((x) == LPUART_STAT_RXFULL)  || \
-                             ((x) == LPUART_STAT_TXEMP)   || \
-                             ((x) == LPUART_STAT_TXFULL)  || \
-                             ((x) == LPUART_STAT_TXIDLE)  || \
-                             ((x) == LPUART_STAT_CTSSTAT) || \
-                             ((x) == LPUART_STAT_RTSSTAT))
-
-#define LPUART_STATE_TX_MASK	(1 << 4)
-#define LPUART_STATE_RX_MASK	(1 << 5)
+                                 ((x) == LPUART_STAT_RXFULL)  || \
+                                 ((x) == LPUART_STAT_TXEMP)   || \
+                                 ((x) == LPUART_STAT_TXFULL)  || \
+                                 ((x) == LPUART_STAT_TXIDLE)  || \
+                                 ((x) == LPUART_STAT_CTSSTAT) || \
+                                 ((x) == LPUART_STAT_RTSSTAT))
+
+#define LPUART_STATE_TX_MASK	(1U << 4)
+#define LPUART_STATE_RX_MASK	(1U << 5)
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pis.h

@@ -18,7 +18,7 @@
 #define __ALD_PIS_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -37,327 +37,277 @@ extern "C" {
   */
 /**
   * @brief Producer entry
-  * @note  ES32F065x:
-  *          AD16C4T0--TIMER0
-  *          GP16C4T0--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  *
-  *        ES32F033x:
-  *        ES32F093x:
-  *          GP16C4T0--TIMER0
-  *          GP16C4T1--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  */
-typedef enum
-{
-    PIS_NON               = 0x0,	/**< No async */
-    PIS_GPIO_PIN0         = 0x10,	/**< Pin0, level,support async */
-    PIS_GPIO_PIN1         = 0x11,	/**< Pin1, level,support async */
-    PIS_GPIO_PIN2         = 0x12,	/**< Pin2, level,support async */
-    PIS_GPIO_PIN3         = 0x13,	/**< Pin3, level,support async */
-    PIS_GPIO_PIN4         = 0x14,	/**< Pin4, level,support async */
-    PIS_GPIO_PIN5         = 0x15,	/**< Pin5, level,support async */
-    PIS_GPIO_PIN6         = 0x16,	/**< Pin6, level,support async */
-    PIS_GPIO_PIN7         = 0x17,	/**< Pin7, level,support async */
-    PIS_GPIO_PIN8         = 0x18,	/**< Pin8, level,support async */
-    PIS_GPIO_PIN9         = 0x19,	/**< Pin9, level,support async */
-    PIS_GPIO_PIN10        = 0x1a,	/**< Pin10, level,support async */
-    PIS_GPIO_PIN11        = 0x1b,	/**< Pin11, level,support async */
-    PIS_GPIO_PIN12        = 0x1c,	/**< Pin12, level,support async */
-    PIS_GPIO_PIN13        = 0x1d,	/**< Pin13, level,support async */
-    PIS_GPIO_PIN14        = 0x1e,	/**< Pin14, level,support async */
-    PIS_GPIO_PIN15        = 0x1f,	/**< Pin15, level,support async */
-    PIS_ACMP_OUT0         = 0x30,	/**< Acmp0 output, level,support async */
-    PIS_ACMP_OUT1         = 0x31,	/**< Acmp1 output, level,support async */
-    PIS_DAC0_CH0          = 0x40,	/**< Dac0 channel 0, pclk2 pulse,support async */
-    PIS_DAC0_CH1          = 0x41,	/**< Dac0 channel 1, pclk2 pulse,support async */
-    PIS_ADC0_INJECT       = 0x60,	/**< Adc0 inject, pclk2 pulse,support async */
-    PIS_ADC0_REGULAT      = 0x61,	/**< Adc0 regulat, pclk2 pulse,support async */
-    PIS_ADC0_WINDOW       = 0x62,	/**< Adc0 window, no have */
-    PIS_LVD               = 0x70,	/**< Lvd, level,support async */
-    PIS_UART0_ASY_SEND    = 0x80,	/**< Uart0 asy send, pulse,support async */
-    PIS_UART0_ASY_RECV    = 0x81,	/**< Uart0 asy recv, pulse,support async */
-    PIS_UART0_IRDAOUT     = 0x82,	/**< Uart0 irdaout, level,support async */
-    PIS_UART0_RTSOUT      = 0x83,	/**< Uart0 rtsout, level,support async */
-    PIS_UART0_TXOUT       = 0x84,	/**< Uart0 txout, level,support async */
-    PIS_UART0_SYN_SEND    = 0x85,	/**< Uart0 syn send, pulse,support async */
-    PIS_UART0_SYN_RECV    = 0x86,	/**< Uart0 syn recv, pulse,support async */
-    PIS_UART1_ASY_SEND    = 0x90,	/**< Uart1 asy send, pulse,support async */
-    PIS_UART1_ASY_RECV    = 0x91,	/**< Uart1 asy recv, pulse,support async */
-    PIS_UART1_IRDA        = 0x92,	/**< Uart1 irdaout, level,support async */
-    PIS_UART1_RTS         = 0x93,	/**< Uart1 rtsout, level,support async */
-    PIS_UART1_TXOUT       = 0x94,	/**< Uart1 txout, level,support async */
-    PIS_UART1_SYN_SEND    = 0x95,	/**< Uart1 syn send, pulse,support async */
-    PIS_UART1_SYN_RECV    = 0x96,	/**< Uart1 syn recv, pulse,support async */
-    PIS_UART2_ASY_SEND    = 0xa0,	/**< Uart2 asy send, pulse,support async */
-    PIS_UART2_ASY_RECV    = 0xa1,	/**< Uart2 asy recv, pulse,support async */
-    PIS_UART2_IRDA        = 0xa2,	/**< Uart2 irdaout, level,support async */
-    PIS_UART2_RTS         = 0xa3,	/**< Uart2 rtsout, level,support async */
-    PIS_UART2_TXOUT       = 0xa4,	/**< Uart2 txout, level,support async */
-    PIS_UART2_SYN_SEND    = 0xa5,	/**< Uart2 syn send, pulse,support async */
-    PIS_UART2_SYN_RECV    = 0xa6,	/**< Uart2 syn recv, pulse,support async */
-    PIS_UART3_ASY_SEND    = 0xb1,	/**< Uart3 asy send, pulse,support async */
-    PIS_UART3_ASY_RECV    = 0xb2,	/**< Uart3 asy recv, pulse,support async */
-    PIS_UART3_IRDA        = 0xb3,	/**< Uart3 irdaout, level,support async */
-    PIS_UART3_RTS         = 0xb4,	/**< Uart3 rtsout, level,support async */
-    PIS_UART3_TXOUT       = 0xb5,	/**< Uart3 txout, level,support async */
-    PIS_UART3_SYN_SEND    = 0xb6,	/**< Uart3 syn send, pulse,support async */
-    PIS_UART3_SYN_RECV    = 0xb7,	/**< Uart3 syn recv, pulse,support async */
-    PIS_EUART0_RECV       = 0xc0,	/**< Euart0 recv, plck1 pulse */
-    PIS_EUART0_SEND       = 0xc1,	/**< Euart0 send, plck1 pulse */
-    PIS_EUART0_TXOUT      = 0xc2,	/**< Euart0 txout, plck1 level */
-    PIS_EUART1_RECV       = 0xd0,	/**< Euart1 recv, plck1 pulse */
-    PIS_EUART1_SEND       = 0xd1,	/**< Euart1 send, plck1 pulse */
-    PIS_EUART1_TXOUT      = 0xd2,	/**< Euart1 txout, plck1 level */
-    PIS_SPI0_RECV         = 0xe0,	/**< Spi0 recv, plck1 pulse */
-    PIS_SPI0_SEND         = 0xe1,	/**< Spi0 send, plck1 pulse */
-    PIS_SPI0_NE           = 0xe2,	/**< Spi0 ne, plck1 level */
-    PIS_SPI1_RECV         = 0xf0,	/**< Spi1 recv, plck1 pulse */
-    PIS_SPI1_SEND         = 0xf1,	/**< Spi1 send, plck1 pulse */
-    PIS_SPI1_NE           = 0xf2,	/**< Spi1 ne, plck1 level */
-    PIS_I2C0_RECV         = 0x100,	/**< I2c0 recv, plck1 level */
-    PIS_I2C0_SEND         = 0x101,	/**< I2c0 send, plck1 level */
-    PIS_I2C1_RECV         = 0x110,	/**< I2c1 recv, plck1 level */
-    PIS_I2C1_SEND         = 0x111,	/**< I2c1 send, plck1 level */
-    PIS_TIMER0_UPDATA     = 0x120,	/**< Timer0 updata, plck1 pulse */
-    PIS_TIMER0_TRIG       = 0x121,	/**< Timer0 trig, plck1 pulse */
-    PIS_TIMER0_INPUT      = 0x122,	/**< Timer0 input, plck1 pulse */
-    PIS_TIMER0_OUTPUT     = 0x123,	/**< Timer0 output, plck1 pulse */
-    PIS_TIMER1_UPDATA     = 0x130,	/**< Timer1 updata, plck1 pulse */
-    PIS_TIMER1_TRIG       = 0x131,	/**< Timer1 trig, plck1 pulse */
-    PIS_TIMER1_INPUT      = 0x132,	/**< Timer1 input, plck1 pulse */
-    PIS_TIMER1_OUTPUT     = 0x133,	/**< Timer1 output, plck1 pulse */
-    PIS_TIMER2_UPDATA     = 0x140,	/**< Timer2 updata, plck1 pulse */
-    PIS_TIMER2_TRIG       = 0x141,	/**< Timer2 trig, plck1 pulse */
-    PIS_TIMER2_INPUT      = 0x142,	/**< Timer2 input, plck1 pulse */
-    PIS_TIMER2_OUTPUT     = 0x143,	/**< Timer2 output, plck1 pulse */
-    PIS_TIMER3_UPDATA     = 0x150,	/**< Timer0 updata, plck1 pulse */
-    PIS_TIMER3_TRIG       = 0x151,	/**< Timer0 trig, plck1 pulse */
-    PIS_TIMER3_INPUT      = 0x152,	/**< Timer0 input, plck1 pulse */
-    PIS_TIMER3_OUTPUT     = 0x153,	/**< Timer0 output, plck1 pulse */
-    PIS_RTC_CLOCK         = 0x160,	/**< Rtc clock, pulse,support async */
-    PIS_RTC_ALARM         = 0x161,	/**< Rtc alarm, pulse,support async */
-    PIS_LPTIM0_SYN_UPDATA = 0x170,	/**< Lptimer0 syn updata, pulse,support async */
-    PIS_LPTIM0_ASY_UPDATA = 0x171,	/**< Lptimer0 asy updata, pulse,support async */
-    PIS_LPUART0_ASY_RECV  = 0x180,	/**< Lpuart0 asy recv, pulse,support async */
-    PIS_LPUART0_ASY_SEND  = 0x181,	/**< Lpuart0 asy send, pulse,support async */
-    PIS_LPUART0_SYN_RECV  = 0x182,	/**< Lpuart0 syn recv, pulse,support async */
-    PIS_LPUART0_SYN_SEND  = 0x183,	/**< Lpuart0 syn recv, pulse,support async */
-    PIS_DMA               = 0x190,	/**< Dma, pulse,support async */
-    PIS_ADC1_INJECT       = 0x1a0,	/**< Adc1 inject, pclk2 pulse,support async */
-    PIS_ADC1_REGULAT      = 0x1a1,	/**< Adc1 regulat, pclk2 pulse,support async */
-    PIS_ADC1_WINDOW       = 0x1a2,	/**< Adc1 window, no have */
+  * @verbatim
+      In this module, for the convenience of code maintenance,
+      TIMERx is used to indicate the sequence of the timer peripheral.
+      Different product series TIMERx represent different meanings:
+      1. For ES32F065x series:
+      TIMER0 ----> AD16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+     
+      2. For ES32F033x/ES32F093x series:
+      TIMER0 ----> GP16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+    @endverbatim
+  */
+typedef enum {
+	PIS_NON               = 0x0U,	/**< No async */
+	PIS_GPIO_PIN0         = 0x10U,	/**< Pin0, level,support async */
+	PIS_GPIO_PIN1         = 0x11U,	/**< Pin1, level,support async */
+	PIS_GPIO_PIN2         = 0x12U,	/**< Pin2, level,support async */
+	PIS_GPIO_PIN3         = 0x13U,	/**< Pin3, level,support async */
+	PIS_GPIO_PIN4         = 0x14U,	/**< Pin4, level,support async */
+	PIS_GPIO_PIN5         = 0x15U,	/**< Pin5, level,support async */
+	PIS_GPIO_PIN6         = 0x16U,	/**< Pin6, level,support async */
+	PIS_GPIO_PIN7         = 0x17U,	/**< Pin7, level,support async */
+	PIS_GPIO_PIN8         = 0x18U,	/**< Pin8, level,support async */
+	PIS_GPIO_PIN9         = 0x19U,	/**< Pin9, level,support async */
+	PIS_GPIO_PIN10        = 0x1aU,	/**< Pin10, level,support async */
+	PIS_GPIO_PIN11        = 0x1bU,	/**< Pin11, level,support async */
+	PIS_GPIO_PIN12        = 0x1cU,	/**< Pin12, level,support async */
+	PIS_GPIO_PIN13        = 0x1dU,	/**< Pin13, level,support async */
+	PIS_GPIO_PIN14        = 0x1eU,	/**< Pin14, level,support async */
+	PIS_GPIO_PIN15        = 0x1fU,	/**< Pin15, level,support async */
+	PIS_ACMP_OUT0         = 0x30U,	/**< Acmp0 output, level,support async */
+	PIS_ACMP_OUT1         = 0x31U,	/**< Acmp1 output, level,support async */
+	PIS_DAC0_CH0          = 0x40U,	/**< Dac0 channel 0, pclk2 pulse,support async */
+	PIS_DAC0_CH1          = 0x41U,	/**< Dac0 channel 1, pclk2 pulse,support async */
+	PIS_ADC0_INJECT       = 0x60U,	/**< Adc0 inject, pclk2 pulse,support async */
+	PIS_ADC0_REGULAT      = 0x61U,	/**< Adc0 regulat, pclk2 pulse,support async */
+	PIS_ADC0_WINDOW       = 0x62U,	/**< Adc0 window, no have */
+	PIS_LVD               = 0x70U,	/**< Lvd, level,support async */
+	PIS_UART0_ASY_SEND    = 0x80U,	/**< Uart0 asy send, pulse,support async */
+	PIS_UART0_ASY_RECV    = 0x81U,	/**< Uart0 asy recv, pulse,support async */
+	PIS_UART0_IRDAOUT     = 0x82U,	/**< Uart0 irdaout, level,support async */
+	PIS_UART0_RTSOUT      = 0x83U,	/**< Uart0 rtsout, level,support async */
+	PIS_UART0_TXOUT       = 0x84U,	/**< Uart0 txout, level,support async */
+	PIS_UART0_SYN_SEND    = 0x85U,	/**< Uart0 syn send, pulse,support async */
+	PIS_UART0_SYN_RECV    = 0x86U,	/**< Uart0 syn recv, pulse,support async */
+	PIS_UART1_ASY_SEND    = 0x90U,	/**< Uart1 asy send, pulse,support async */
+	PIS_UART1_ASY_RECV    = 0x91U,	/**< Uart1 asy recv, pulse,support async */
+	PIS_UART1_IRDA        = 0x92U,	/**< Uart1 irdaout, level,support async */
+	PIS_UART1_RTS         = 0x93U,	/**< Uart1 rtsout, level,support async */
+	PIS_UART1_TXOUT       = 0x94U,	/**< Uart1 txout, level,support async */
+	PIS_UART1_SYN_SEND    = 0x95U,	/**< Uart1 syn send, pulse,support async */
+	PIS_UART1_SYN_RECV    = 0x96U,	/**< Uart1 syn recv, pulse,support async */
+	PIS_UART2_ASY_SEND    = 0xa0U,	/**< Uart2 asy send, pulse,support async */
+	PIS_UART2_ASY_RECV    = 0xa1U,	/**< Uart2 asy recv, pulse,support async */
+	PIS_UART2_IRDA        = 0xa2U,	/**< Uart2 irdaout, level,support async */
+	PIS_UART2_RTS         = 0xa3U,	/**< Uart2 rtsout, level,support async */
+	PIS_UART2_TXOUT       = 0xa4U,	/**< Uart2 txout, level,support async */
+	PIS_UART2_SYN_SEND    = 0xa5U,	/**< Uart2 syn send, pulse,support async */
+	PIS_UART2_SYN_RECV    = 0xa6U,	/**< Uart2 syn recv, pulse,support async */
+	PIS_UART3_ASY_SEND    = 0xb1U,	/**< Uart3 asy send, pulse,support async */
+	PIS_UART3_ASY_RECV    = 0xb2U,	/**< Uart3 asy recv, pulse,support async */
+	PIS_UART3_IRDA        = 0xb3U,	/**< Uart3 irdaout, level,support async */
+	PIS_UART3_RTS         = 0xb4U,	/**< Uart3 rtsout, level,support async */
+	PIS_UART3_TXOUT       = 0xb5U,	/**< Uart3 txout, level,support async */
+	PIS_UART3_SYN_SEND    = 0xb6U,	/**< Uart3 syn send, pulse,support async */
+	PIS_UART3_SYN_RECV    = 0xb7U,	/**< Uart3 syn recv, pulse,support async */
+	PIS_EUART0_RECV       = 0xc0U,	/**< Euart0 recv, plck1 pulse */
+	PIS_EUART0_SEND       = 0xc1U,	/**< Euart0 send, plck1 pulse */
+	PIS_EUART0_TXOUT      = 0xc2U,	/**< Euart0 txout, plck1 level */
+	PIS_EUART1_RECV       = 0xd0U,	/**< Euart1 recv, plck1 pulse */
+	PIS_EUART1_SEND       = 0xd1U,	/**< Euart1 send, plck1 pulse */
+	PIS_EUART1_TXOUT      = 0xd2U,	/**< Euart1 txout, plck1 level */
+	PIS_SPI0_RECV         = 0xe0U,	/**< Spi0 recv, plck1 pulse */
+	PIS_SPI0_SEND         = 0xe1U,	/**< Spi0 send, plck1 pulse */
+	PIS_SPI0_NE           = 0xe2U,	/**< Spi0 ne, plck1 level */
+	PIS_SPI1_RECV         = 0xf0U,	/**< Spi1 recv, plck1 pulse */
+	PIS_SPI1_SEND         = 0xf1U,	/**< Spi1 send, plck1 pulse */
+	PIS_SPI1_NE           = 0xf2U,	/**< Spi1 ne, plck1 level */
+	PIS_I2C0_RECV         = 0x100U,	/**< I2c0 recv, plck1 level */
+	PIS_I2C0_SEND         = 0x101U,	/**< I2c0 send, plck1 level */
+	PIS_I2C1_RECV         = 0x110U,	/**< I2c1 recv, plck1 level */
+	PIS_I2C1_SEND         = 0x111U,	/**< I2c1 send, plck1 level */
+	PIS_TIMER0_UPDATA     = 0x120U,	/**< Timer0 updata, plck1 pulse */
+	PIS_TIMER0_TRIG       = 0x121U,	/**< Timer0 trig, plck1 pulse */
+	PIS_TIMER0_INPUT      = 0x122U,	/**< Timer0 input, plck1 pulse */
+	PIS_TIMER0_OUTPUT     = 0x123U,	/**< Timer0 output, plck1 pulse */
+	PIS_TIMER1_UPDATA     = 0x130U,	/**< Timer1 updata, plck1 pulse */
+	PIS_TIMER1_TRIG       = 0x131U,	/**< Timer1 trig, plck1 pulse */
+	PIS_TIMER1_INPUT      = 0x132U,	/**< Timer1 input, plck1 pulse */
+	PIS_TIMER1_OUTPUT     = 0x133U,	/**< Timer1 output, plck1 pulse */
+	PIS_TIMER2_UPDATA     = 0x140U,	/**< Timer2 updata, plck1 pulse */
+	PIS_TIMER2_TRIG       = 0x141U,	/**< Timer2 trig, plck1 pulse */
+	PIS_TIMER2_INPUT      = 0x142U,	/**< Timer2 input, plck1 pulse */
+	PIS_TIMER2_OUTPUT     = 0x143U,	/**< Timer2 output, plck1 pulse */
+	PIS_TIMER3_UPDATA     = 0x150U,	/**< Timer0 updata, plck1 pulse */
+	PIS_TIMER3_TRIG       = 0x151U,	/**< Timer0 trig, plck1 pulse */
+	PIS_TIMER3_INPUT      = 0x152U,	/**< Timer0 input, plck1 pulse */
+	PIS_TIMER3_OUTPUT     = 0x153U,	/**< Timer0 output, plck1 pulse */
+	PIS_RTC_CLOCK         = 0x160U,	/**< Rtc clock, pulse,support async */
+	PIS_RTC_ALARM         = 0x161U,	/**< Rtc alarm, pulse,support async */
+	PIS_LPTIM0_SYN_UPDATA = 0x170U,	/**< Lptimer0 syn updata, pulse,support async */
+	PIS_LPTIM0_ASY_UPDATA = 0x171U,	/**< Lptimer0 asy updata, pulse,support async */
+	PIS_LPUART0_ASY_RECV  = 0x180U,	/**< Lpuart0 asy recv, pulse,support async */
+	PIS_LPUART0_ASY_SEND  = 0x181U,	/**< Lpuart0 asy send, pulse,support async */
+	PIS_LPUART0_SYN_RECV  = 0x182U,	/**< Lpuart0 syn recv, pulse,support async */
+	PIS_LPUART0_SYN_SEND  = 0x183U,	/**< Lpuart0 syn recv, pulse,support async */
+	PIS_DMA               = 0x190U,	/**< Dma, pulse,support async */
+	PIS_ADC1_INJECT       = 0x1a0U,	/**< Adc1 inject, pclk2 pulse,support async */
+	PIS_ADC1_REGULAT      = 0x1a1U,	/**< Adc1 regulat, pclk2 pulse,support async */
+	PIS_ADC1_WINDOW       = 0x1a2U,	/**< Adc1 window, no have */
 } pis_src_t;
 
 /**
   * @brief Consumer entry
-  * @note  ES32F065x:
-  *          AD16C4T0--TIMER0
-  *          GP16C4T0--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  *
-  *        ES32F033x:
-  *        ES32F093x:
-  *          GP16C4T0--TIMER0
-  *          GP16C4T1--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
   */
-typedef enum
-{
-    PIS_CH0_TIMER0_BRKIN  = 0x0400,	/**< Timer0 brkin */
-    PIS_CH0_SPI1_CLK      = 0x0F10,	/**< Spi1 clk */
-    PIS_CH0_LPTIM0_EXT0   = 0x0030,	/**< Lptimer0 ext0 */
-    PIS_CH0_ADC1_NORMAL   = 0x0030,	/**< Adc1 normal */
-    PIS_CH1_TIMER0_CH1IN  = 0x0001,	/**< Timer0 ch1in */
-    PIS_CH1_TIMER2_CH1IN  = 0x1001,	/**< Timer2 ch1in */
-    PIS_CH1_TIMER3_CH1IN  = 0x1801,	/**< Timer3 ch1in */
-    PIS_CH1_LPTIM0_EXT1   = 0x0031,	/**< Lptime0 ext1 */
-    PIS_CH1_UART0_RX_IRDA = 0x0011,	/**< Uart0 rx irda */
-    PIS_CH1_ADC1_INSERT   = 0x0031,	/**< Adc1 insert */
-    PIS_CH2_TIMER0_CH2IN  = 0x0102,	/**< Timer0 ch2in */
-    PIS_CH2_TIMER2_CH2IN  = 0x1102,	/**< Timer2 ch2in */
-    PIS_CH2_TIMER3_CH2IN  = 0x1902,	/**< Timer3 ch2in */
-    PIS_CH2_LPTIM0_EXT2   = 0x0032,	/**< Lptime0 ext2 */
-    PIS_CH2_UART1_RX_IRDA = 0x0112,	/**< Uart1 rx irda */
-    PIS_CH3_TIMER0_CH3IN  = 0x0203,	/**< Timer0 ch3in */
-    PIS_CH3_LPTIM0_EXT3   = 0x0033,	/**< Lptime0 ext3 */
-    PIS_CH3_UART2_RX_IRDA = 0x0213,	/**< Uart2 rx irda */
-    PIS_CH4_TIMER0_CH4IN  = 0x0004,	/**< Timer0 ch4in */
-    PIS_CH4_TIMER0_ITR0   = 0x0034,	/**< Timer0 itr0 */
-    PIS_CH4_TIMER2_ITR0   = 0x0034,	/**< Timer2 itr0 */
-    PIS_CH4_TIMER3_ITR0   = 0x0034,	/**< Timer3 itr0 */
-    PIS_CH4_LPTIM0_EXT4   = 0x0434,	/**< Lptime0 ext4 */
-    PIS_CH4_UART3_RX_IRDA = 0x0314,	/**< Uart3 rx irda */
-    PIS_CH5_SPI0_RX       = 0x0C15,	/**< Spi0 rx */
-    PIS_CH5_LPTIM0_EXT5   = 0x0035,	/**< Lptime0 ext5 */
-    PIS_CH5_EUART0_RX     = 0x0615,	/**< Euart0 rx */
-    PIS_CH5_TIMER0_ITR1   = 0x0035,	/**< Timer0 itr1 */
-    PIS_CH5_TIMER2_ITR1   = 0x0035,	/**< Timer2 itr1 */
-    PIS_CH5_TIMER3_ITR1   = 0x0035,	/**< Timer3 itr1 */
-    PIS_CH6_SPI0_CLK      = 0x0D16,	/**< Spi0 clk */
-    PIS_CH6_ADC0_NORMAL   = 0x0036,	/**< Adc0 normal */
-    PIS_CH6_LPTIM0_EXT6   = 0x0036,	/**< Lptime0 ext6 */
-    PIS_CH6_EUART1_RX     = 0x0716,	/**< Euart1 rx */
-    PIS_CH6_TIMER0_ITR2   = 0x0036,	/**< Timer0 itr2 */
-    PIS_CH6_TIMER2_ITR2   = 0x0036,	/**< Timer2 itr2 */
-    PIS_CH6_TIMER3_ITR2   = 0x0036,	/**< Timer3 itr2 */
-    PIS_CH6_DAC_CH1       = 0x0036,	/**< Dac channel 1 */
-    PIS_CH7_SPI1_RX       = 0x0E17,	/**< Spi1 rx */
-    PIS_CH7_ADC0_INSERT   = 0x0037,	/**< Adc0 insert */
-    PIS_CH7_LPTIM0_EXT7   = 0x0037,	/**< Lptime0 ext7 */
-    PIS_CH7_DMA           = 0x0037,	/**< Dma */
-    PIS_CH7_TIMER0_ITR3   = 0x0037,	/**< Timer0 itr3 */
-    PIS_CH7_TIMER2_ITR3   = 0x0037,	/**< Timer2 itr3 */
-    PIS_CH7_TIMER3_ITR3   = 0x0037,	/**< Timer3 itr3 */
-    PIS_CH7_LPUART_RX     = 0x0817,	/**< Lpuart rx */
-    PIS_CH7_DAC_CH0       = 0x0037,	/**< Dac channel 0 */
+typedef enum {
+	PIS_CH0_TIMER0_BRKIN  = 0x0400U,	/**< Timer0 brkin */
+	PIS_CH0_SPI1_CLK      = 0x0F10U,	/**< Spi1 clk */
+	PIS_CH0_LPTIM0_EXT0   = 0x0030U,	/**< Lptimer0 ext0 */
+	PIS_CH0_ADC1_NORMAL   = 0x0030U,	/**< Adc1 normal */
+	PIS_CH1_TIMER0_CH1IN  = 0x0001U,	/**< Timer0 ch1in */
+	PIS_CH1_TIMER2_CH1IN  = 0x1001U,	/**< Timer2 ch1in */
+	PIS_CH1_TIMER3_CH1IN  = 0x1801U,	/**< Timer3 ch1in */
+	PIS_CH1_LPTIM0_EXT1   = 0x0031U,	/**< Lptime0 ext1 */
+	PIS_CH1_UART0_RX_IRDA = 0x0011U,	/**< Uart0 rx irda */
+	PIS_CH1_ADC1_INSERT   = 0x0031U,	/**< Adc1 insert */
+	PIS_CH2_TIMER0_CH2IN  = 0x0102U,	/**< Timer0 ch2in */
+	PIS_CH2_TIMER2_CH2IN  = 0x1102U,	/**< Timer2 ch2in */
+	PIS_CH2_TIMER3_CH2IN  = 0x1902U,	/**< Timer3 ch2in */
+	PIS_CH2_LPTIM0_EXT2   = 0x0032U,	/**< Lptime0 ext2 */
+	PIS_CH2_UART1_RX_IRDA = 0x0112U,	/**< Uart1 rx irda */
+	PIS_CH3_TIMER0_CH3IN  = 0x0203U,	/**< Timer0 ch3in */
+	PIS_CH3_LPTIM0_EXT3   = 0x0033U,	/**< Lptime0 ext3 */
+	PIS_CH3_UART2_RX_IRDA = 0x0213U,	/**< Uart2 rx irda */
+	PIS_CH4_TIMER0_CH4IN  = 0x0004U,	/**< Timer0 ch4in */
+	PIS_CH4_TIMER0_ITR0   = 0x0034U,	/**< Timer0 itr0 */
+	PIS_CH4_TIMER2_ITR0   = 0x0034U,	/**< Timer2 itr0 */
+	PIS_CH4_TIMER3_ITR0   = 0x0034U,	/**< Timer3 itr0 */
+	PIS_CH4_LPTIM0_EXT4   = 0x0434U,	/**< Lptime0 ext4 */
+	PIS_CH4_UART3_RX_IRDA = 0x0314U,	/**< Uart3 rx irda */
+	PIS_CH5_SPI0_RX       = 0x0C15U,	/**< Spi0 rx */
+	PIS_CH5_LPTIM0_EXT5   = 0x0035U,	/**< Lptime0 ext5 */
+	PIS_CH5_EUART0_RX     = 0x0615U,	/**< Euart0 rx */
+	PIS_CH5_TIMER0_ITR1   = 0x0035U,	/**< Timer0 itr1 */
+	PIS_CH5_TIMER2_ITR1   = 0x0035U,	/**< Timer2 itr1 */
+	PIS_CH5_TIMER3_ITR1   = 0x0035U,	/**< Timer3 itr1 */
+	PIS_CH6_SPI0_CLK      = 0x0D16U,	/**< Spi0 clk */
+	PIS_CH6_ADC0_NORMAL   = 0x0036U,	/**< Adc0 normal */
+	PIS_CH6_LPTIM0_EXT6   = 0x0036U,	/**< Lptime0 ext6 */
+	PIS_CH6_EUART1_RX     = 0x0716U,	/**< Euart1 rx */
+	PIS_CH6_TIMER0_ITR2   = 0x0036U,	/**< Timer0 itr2 */
+	PIS_CH6_TIMER2_ITR2   = 0x0036U,	/**< Timer2 itr2 */
+	PIS_CH6_TIMER3_ITR2   = 0x0036U,	/**< Timer3 itr2 */
+	PIS_CH6_DAC_CH1       = 0x0036U,	/**< Dac channel 1 */
+	PIS_CH7_SPI1_RX       = 0x0E17U,	/**< Spi1 rx */
+	PIS_CH7_ADC0_INSERT   = 0x0037U,	/**< Adc0 insert */
+	PIS_CH7_LPTIM0_EXT7   = 0x0037U,	/**< Lptime0 ext7 */
+	PIS_CH7_DMA           = 0x0037U,	/**< Dma */
+	PIS_CH7_TIMER0_ITR3   = 0x0037U,	/**< Timer0 itr3 */
+	PIS_CH7_TIMER2_ITR3   = 0x0037U,	/**< Timer2 itr3 */
+	PIS_CH7_TIMER3_ITR3   = 0x0037U,	/**< Timer3 itr3 */
+	PIS_CH7_LPUART_RX     = 0x0817U,	/**< Lpuart rx */
+	PIS_CH7_DAC_CH0       = 0x0037U,	/**< Dac channel 0 */
 } pis_trig_t;
 
 /**
   * @brief Clock select
   */
-typedef enum
-{
-    PIS_CLK_PCLK1 = 0,	/**< Pclock1 */
-    PIS_CLK_PCLK2 = 1,	/**< Pclock2 */
-    PIS_CLK_SYS   = 2,	/**< Sys clock */
-    PIS_CLK_LP    = 3,	/**< Low power clock */
+typedef enum {
+	PIS_CLK_PCLK1 = 0U,	/**< Pclock1 */
+	PIS_CLK_PCLK2 = 1U,	/**< Pclock2 */
+	PIS_CLK_SYS   = 2U,	/**< Sys clock */
+	PIS_CLK_LP    = 3U,	/**< Low power clock */
 } pis_clock_t;
 
 /**
   * @brief Level select
   */
-typedef enum
-{
-    PIS_EDGE_NONE    = 0,	/**< None edge */
-    PIS_EDGE_UP      = 1,	/**< Up edge */
-    PIS_EDGE_DOWN    = 2,	/**< Down edge */
-    PIS_EDGE_UP_DOWN = 3,	/**< Up and down edge */
+typedef enum {
+	PIS_EDGE_NONE    = 0U,	/**< None edge */
+	PIS_EDGE_UP      = 1U,	/**< Up edge */
+	PIS_EDGE_DOWN    = 2U,	/**< Down edge */
+	PIS_EDGE_UP_DOWN = 3U,	/**< Up and down edge */
 } pis_edge_t;
 
 /**
   * @brief Output style
   */
-typedef enum
-{
-    PIS_OUT_LEVEL = 0,	/**< Level */
-    PIS_OUT_PULSE = 1,	/**< Pulse */
+typedef enum {
+	PIS_OUT_LEVEL = 0U,	/**< Level */
+	PIS_OUT_PULSE = 1U,	/**< Pulse */
 } pis_output_t;
 /**
   * @brief Sync select
   */
-typedef enum
-{
-    PIS_SYN_DIRECT      = 0,	/**< Direct */
-    PIS_SYN_ASY_PCLK1   = 1,	/**< Asy pclk1 */
-    PIS_SYN_ASY_PCLK2   = 2,	/**< Asy pclk2 */
-    PIS_SYN_ASY_PCLK    = 3,	/**< Asy pclk */
-    PIS_SYN_PCLK2_PCLK1 = 4,	/**< Pclk2 to pclk1 */
-    PIS_SYN_PCLK1_PCLK2 = 5,	/**< Pclk1 to pclk2 */
-    PIS_SYN_PCLK12_SYS  = 6,	/**< Pclk1 or pclk2 to sysclk */
+typedef enum {
+	PIS_SYN_DIRECT      = 0U,	/**< Direct */
+	PIS_SYN_ASY_PCLK1   = 1U,	/**< Asy pclk1 */
+	PIS_SYN_ASY_PCLK2   = 2U,	/**< Asy pclk2 */
+	PIS_SYN_ASY_PCLK    = 3U,	/**< Asy pclk */
+	PIS_SYN_PCLK2_PCLK1 = 4U,	/**< Pclk2 to pclk1 */
+	PIS_SYN_PCLK1_PCLK2 = 5U,	/**< Pclk1 to pclk2 */
+	PIS_SYN_PCLK12_SYS  = 6U,	/**< Pclk1 or pclk2 to sysclk */
 } pis_syncsel_t;
 
 /**
   * @brief Pis channel
   */
-typedef enum
-{
-    PIS_CH_0 = 0,	/**< Channel 0 */
-    PIS_CH_1 = 1,	/**< Channel 1 */
-    PIS_CH_2 = 2,	/**< Channel 2 */
-    PIS_CH_3 = 3,	/**< Channel 3 */
-    PIS_CH_4 = 4,	/**< Channel 4 */
-    PIS_CH_5 = 5,	/**< Channel 5 */
-    PIS_CH_6 = 6,	/**< Channel 6 */
-    PIS_CH_7 = 7,	/**< Channel 7 */
+typedef enum {
+	PIS_CH_0 = 0U,	/**< Channel 0 */
+	PIS_CH_1 = 1U,	/**< Channel 1 */
+	PIS_CH_2 = 2U,	/**< Channel 2 */
+	PIS_CH_3 = 3U,	/**< Channel 3 */
+	PIS_CH_4 = 4U,	/**< Channel 4 */
+	PIS_CH_5 = 5U,	/**< Channel 5 */
+	PIS_CH_6 = 6U,	/**< Channel 6 */
+	PIS_CH_7 = 7U,	/**< Channel 7 */
 } pis_ch_t;
 
 /**
   * @brief Pis output channel
   */
-typedef enum
-{
-    PIS_OUT_CH_0 = 0,	/**< Channel 0 */
-    PIS_OUT_CH_1 = 1,	/**< Channel 1 */
-    PIS_OUT_CH_2 = 2,	/**< Channel 2 */
-    PIS_OUT_CH_3 = 3,	/**< Channel 3 */
+typedef enum {
+	PIS_OUT_CH_0 = 0U,	/**< Channel 0 */
+	PIS_OUT_CH_1 = 1U,	/**< Channel 1 */
+	PIS_OUT_CH_2 = 2U,	/**< Channel 2 */
+	PIS_OUT_CH_3 = 3U,	/**< Channel 3 */
 } pis_out_ch_t;
 
 /**
   * @brief Indirect value,no care of it.
   */
-typedef enum
-{
-    PIS_CON_0    = 0,	/**< Con 0 */
-    PIS_CON_1    = 1,	/**< Con 1 */
-    PIS_CON_NONE = 2,	/**< None */
+typedef enum {
+	PIS_CON_0    = 0U,	/**< Con 0 */
+	PIS_CON_1    = 1U,	/**< Con 1 */
+	PIS_CON_NONE = 2U,	/**< None */
 } pis_con_t;
 
-/**
-  * @brief Indirect value,no care of it.
-  */
-typedef union
-{
-    struct
-    {
-        uint8_t ch    : 4;	/**< Channel */
-        uint8_t con   : 4;	/**< Contorl */
-        uint8_t shift : 8;	/**< Shift */
-    };
-    uint16_t HalfWord;
-} pis_divide_t;
-
 /**
   * @brief PIS state structures definition
   */
-typedef enum
-{
-    PIS_STATE_RESET   = 0x00,	/**< Peripheral is not initialized */
-    PIS_STATE_READY   = 0x01,	/**< Peripheral Initialized and ready for use */
-    PIS_STATE_BUSY    = 0x02,	/**< An internal process is ongoing */
-    PIS_STATE_TIMEOUT = 0x03,	/**< Timeout state */
-    PIS_STATE_ERROR   = 0x04,	/**< Error */
+typedef enum {
+	PIS_STATE_RESET   = 0x00U,	/**< Peripheral is not initialized */
+	PIS_STATE_READY   = 0x01U,	/**< Peripheral Initialized and ready for use */
+	PIS_STATE_BUSY    = 0x02U,	/**< An internal process is ongoing */
+	PIS_STATE_TIMEOUT = 0x03U,	/**< Timeout state */
+	PIS_STATE_ERROR   = 0x04U,	/**< Error */
 } pis_state_t;
 
 /**
   * @brief PIS modulate target
   */
-typedef enum
-{
-    PIS_UART0_TX   = 0,	/**< Modulate uart0 tx */
-    PIS_UART1_TX   = 1,	/**< Modulate uart1 tx */
-    PIS_UART2_TX   = 2,	/**< Modulate uart2 tx */
-    PIS_UART3_TX   = 3,	/**< Modulate uart3 tx */
-    PIS_LPUART0_TX = 4,	/**< Modulate lpuart0 tx */
+typedef enum {
+	PIS_UART0_TX   = 0U,	/**< Modulate uart0 tx */
+	PIS_UART1_TX   = 1U,	/**< Modulate uart1 tx */
+	PIS_UART2_TX   = 2U,	/**< Modulate uart2 tx */
+	PIS_UART3_TX   = 3U,	/**< Modulate uart3 tx */
+	PIS_LPUART0_TX = 4U,	/**< Modulate lpuart0 tx */
 } pis_modu_targ_t;
 
 /**
   * @brief PIS modulate level
   */
-typedef enum
-{
-    PIS_LOW_LEVEL  = 0,	/**< Modulate low level */
-    PIS_HIGH_LEVEL = 1,	/**< Modulate high level */
+typedef enum {
+	PIS_LOW_LEVEL  = 0U,	/**< Modulate low level */
+	PIS_HIGH_LEVEL = 1U,	/**< Modulate high level */
 } pis_modu_level_t;
 
 /**
@@ -383,66 +333,61 @@ typedef enum
   *          BS16T2----TIMER5
   *          BS16T3----TIMER7
   */
-typedef enum
-{
-    PIS_SRC_NONE   = 0,	/**< Stop modulate */
-    PIS_SRC_TIMER0 = 1,	/**< Modulate source is TIMER0 */
-    PIS_SRC_TIMER1 = 2,	/**< Modulate source is TIMER1 */
-    PIS_SRC_TIMER2 = 3,	/**< Modulate source is TIMER2 */
-    PIS_SRC_TIMER3 = 4,	/**< Modulate source is TIMER3 */
-    PIS_SRC_TIMER6 = 5,	/**< Modulate source is TIMER6 */
-    PIS_SRC_TIMER7 = 6,	/**< Modulate source is TIMER7 */
-    PIS_SRC_LPTIM0 = 7,	/**< Modulate source is LPTIM0 */
-    PIS_SRC_BUZ    = 8,	/**< Modulate source is buz */
+typedef enum {
+	PIS_SRC_NONE   = 0U,	/**< Stop modulate */
+	PIS_SRC_TIMER0 = 1U,	/**< Modulate source is TIMER0 */
+	PIS_SRC_TIMER1 = 2U,	/**< Modulate source is TIMER1 */
+	PIS_SRC_TIMER2 = 3U,	/**< Modulate source is TIMER2 */
+	PIS_SRC_TIMER3 = 4U,	/**< Modulate source is TIMER3 */
+	PIS_SRC_TIMER6 = 5U,	/**< Modulate source is TIMER6 */
+	PIS_SRC_TIMER7 = 6U,	/**< Modulate source is TIMER7 */
+	PIS_SRC_LPTIM0 = 7U,	/**< Modulate source is LPTIM0 */
+	PIS_SRC_BUZ    = 8U,	/**< Modulate source is buz */
 } pis_modu_src_t;
 
 /**
   * @brief PIS modulate channel
   */
-typedef enum
-{
-    PIS_TIMER_CH1 = 0,	/**< Src is TIMERx and choose channel 1 */
-    PIS_TIMER_CH2 = 1,	/**< Src is TIMERx and choose channel 2 */
-    PIS_TIMER_CH3 = 2,	/**< Src is TIMERx and choose channel 3 */
-    PIS_TIMER_CH4 = 3,	/**< Src is TIMERx and choose channel 4 */
+typedef enum {
+	PIS_TIMER_CH1 = 0U,	/**< Src is TIMERx and choose channel 1 */
+	PIS_TIMER_CH2 = 1U,	/**< Src is TIMERx and choose channel 2 */
+	PIS_TIMER_CH3 = 2U,	/**< Src is TIMERx and choose channel 3 */
+	PIS_TIMER_CH4 = 3U,	/**< Src is TIMERx and choose channel 4 */
 } pis_modu_channel_t;
 
 /**
   * @brief PIS init structure definition
   */
-typedef struct
-{
-    pis_src_t producer_src;		/**< Producer entry */
-    pis_clock_t producer_clk;	/**< Producer module clock */
-    pis_edge_t producer_edge;	/**< Producer module pin output edge */
-    pis_trig_t consumer_trig;	/**< Consumer entry */
-    pis_clock_t consumer_clk;	/**< Consumer clock */
+typedef struct {
+	pis_src_t producer_src;		/**< Producer entry */
+	pis_clock_t producer_clk;	/**< Producer module clock */
+	pis_edge_t producer_edge;	/**< Producer module pin output edge */
+	pis_trig_t consumer_trig;	/**< Consumer entry */
+	pis_clock_t consumer_clk;	/**< Consumer clock */
 } pis_init_t;
 
 /**
   * @brief PIS modulate config structure definition
   */
-typedef struct
-{
-    pis_modu_targ_t target;		/**< Modulate target */
-    pis_modu_level_t level;		/**< Modulate level */
-    pis_modu_src_t src;		/**< Modulate src */
-    pis_modu_channel_t channel;	/**< Modulate channel */
+typedef struct {
+	pis_modu_targ_t target;		/**< Modulate target */
+	pis_modu_level_t level;		/**< Modulate level */
+	pis_modu_src_t src;		/**< Modulate src */
+	pis_modu_channel_t channel;	/**< Modulate channel */
 } pis_modulate_config_t;
 
 /**
   * @brief  PIS Handle Structure definition
   */
-typedef struct pis_handle_s
-{
-    PIS_TypeDef *perh;		/**< Register base address */
-    pis_init_t init;		/**< PIS required parameters */
-    pis_ch_t consumer_ch;		/**< Indirect value, no care of it */
-    pis_con_t consumer_con;		/**< Indirect value, no care of it */
-    uint8_t consumer_pos;	        /**< Indirect value, no care of it */
-    uint32_t check_info;		/**< When destroy a handle ,user need check whether is right that ready to destroy */
-    lock_state_t lock;		/**< Locking object */
-    pis_state_t state;		/**< PIS operation state */
+typedef struct pis_handle_s {
+	PIS_TypeDef *perh;		/**< Register base address */
+	pis_init_t init;		/**< PIS required parameters */
+	pis_ch_t consumer_ch;		/**< Indirect value, no care of it */
+	pis_con_t consumer_con;		/**< Indirect value, no care of it */
+	uint8_t consumer_pos;	        /**< Indirect value, no care of it */
+	uint32_t check_info;		/**< When destroy a handle ,user need check whether is right that ready to destroy */
+	lock_state_t lock;		/**< Locking object */
+	pis_state_t state;		/**< PIS operation state */
 } pis_handle_t;
 /**
   * @}
@@ -454,183 +399,183 @@ typedef struct pis_handle_s
   */
 #define IS_PIS(x) 		(((x) == PIS))
 #define IS_PIS_SRC(x) 		(((x) == PIS_NON)               || \
-                             ((x) == PIS_GPIO_PIN0)         || \
-                             ((x) == PIS_GPIO_PIN1)         || \
-                             ((x) == PIS_GPIO_PIN2)         || \
-                             ((x) == PIS_GPIO_PIN3)         || \
-                             ((x) == PIS_GPIO_PIN4)         || \
-                             ((x) == PIS_GPIO_PIN5)         || \
-                             ((x) == PIS_GPIO_PIN6)         || \
-                             ((x) == PIS_GPIO_PIN7)         || \
-                             ((x) == PIS_GPIO_PIN8)         || \
-                             ((x) == PIS_GPIO_PIN9)         || \
-                             ((x) == PIS_GPIO_PIN10)        || \
-                             ((x) == PIS_GPIO_PIN11)        || \
-                             ((x) == PIS_GPIO_PIN12)        || \
-                             ((x) == PIS_GPIO_PIN13)        || \
-                             ((x) == PIS_GPIO_PIN14)        || \
-                             ((x) == PIS_GPIO_PIN15)        || \
-                             ((x) == PIS_ACMP_OUT0)         || \
-                             ((x) == PIS_ACMP_OUT1)         || \
-                             ((x) == PIS_DAC0_CH1)          || \
-                             ((x) == PIS_ACMP_OUT1)         || \
-                             ((x) == PIS_ADC0_INJECT)       || \
-                             ((x) == PIS_ADC0_REGULAT)      || \
-                             ((x) == PIS_ADC0_WINDOW)       || \
-                             ((x) == PIS_LVD)               || \
-                             ((x) == PIS_UART0_ASY_SEND)    || \
-                             ((x) == PIS_UART0_ASY_RECV)    || \
-                             ((x) == PIS_UART0_IRDAOUT)     || \
-                             ((x) == PIS_UART0_RTSOUT)      || \
-                             ((x) == PIS_UART0_TXOUT)       || \
-                             ((x) == PIS_UART0_SYN_SEND)    || \
-                             ((x) == PIS_UART0_SYN_RECV)    || \
-                             ((x) == PIS_UART1_ASY_SEND)    || \
-                             ((x) == PIS_UART1_ASY_RECV)    || \
-                             ((x) == PIS_UART1_IRDA)        || \
-                             ((x) == PIS_UART1_RTS)         || \
-                             ((x) == PIS_UART1_TXOUT)       || \
-                             ((x) == PIS_UART1_SYN_SEND)    || \
-                             ((x) == PIS_UART1_SYN_RECV)    || \
-                             ((x) == PIS_UART2_ASY_SEND)    || \
-                             ((x) == PIS_UART2_ASY_RECV)    || \
-                             ((x) == PIS_UART2_IRDA)        || \
-                             ((x) == PIS_UART2_RTS)         || \
-                             ((x) == PIS_UART2_TXOUT)       || \
-                             ((x) == PIS_UART2_SYN_SEND)    || \
-                             ((x) == PIS_UART2_SYN_RECV)    || \
-                             ((x) == PIS_UART3_ASY_SEND)    || \
-                             ((x) == PIS_UART3_ASY_RECV)    || \
-                             ((x) == PIS_UART3_IRDA)        || \
-                             ((x) == PIS_UART3_RTS)         || \
-                             ((x) == PIS_UART3_TXOUT)       || \
-                             ((x) == PIS_UART3_SYN_SEND)    || \
-                             ((x) == PIS_UART3_SYN_RECV)    || \
-                             ((x) == PIS_EUART0_RECV)       || \
-                             ((x) == PIS_EUART0_SEND)       || \
-                             ((x) == PIS_EUART0_TXOUT)      || \
-                             ((x) == PIS_EUART1_RECV)       || \
-                             ((x) == PIS_EUART1_SEND)       || \
-                             ((x) == PIS_EUART1_TXOUT)      || \
-                             ((x) == PIS_SPI0_RECV)         || \
-                             ((x) == PIS_SPI0_SEND)         || \
-                             ((x) == PIS_SPI0_NE)           || \
-                             ((x) == PIS_SPI1_RECV)         || \
-                             ((x) == PIS_SPI1_SEND)         || \
-                             ((x) == PIS_SPI1_NE)           || \
-                             ((x) == PIS_I2C0_RECV)         || \
-                             ((x) == PIS_I2C0_SEND)         || \
-                             ((x) == PIS_I2C1_RECV)         || \
-                             ((x) == PIS_I2C1_SEND)         || \
-                             ((x) == PIS_TIMER0_UPDATA)       || \
-                             ((x) == PIS_TIMER0_TRIG)         || \
-                             ((x) == PIS_TIMER0_INPUT)        || \
-                             ((x) == PIS_TIMER0_OUTPUT)       || \
-                             ((x) == PIS_TIMER1_UPDATA)       || \
-                             ((x) == PIS_TIMER1_TRIG)         || \
-                             ((x) == PIS_TIMER1_INPUT)        || \
-                             ((x) == PIS_TIMER1_OUTPUT)       || \
-                             ((x) == PIS_TIMER2_UPDATA)       || \
-                             ((x) == PIS_TIMER2_TRIG)         || \
-                             ((x) == PIS_TIMER2_INPUT)        || \
-                             ((x) == PIS_TIMER2_OUTPUT)       || \
-                             ((x) == PIS_TIMER3_UPDATA)       || \
-                             ((x) == PIS_TIMER3_TRIG)         || \
-                             ((x) == PIS_TIMER3_INPUT)        || \
-                             ((x) == PIS_TIMER3_OUTPUT)       || \
-                             ((x) == PIS_RTC_CLOCK)         || \
-                             ((x) == PIS_RTC_ALARM)         || \
-                             ((x) == PIS_LPTIM0_SYN_UPDATA) || \
-                             ((x) == PIS_LPTIM0_ASY_UPDATA) || \
-                             ((x) == PIS_LPUART0_ASY_RECV)  || \
-                             ((x) == PIS_LPUART0_ASY_SEND)  || \
-                             ((x) == PIS_LPUART0_SYN_RECV)  || \
-                             ((x) == PIS_LPUART0_SYN_SEND)  || \
-                             ((x) == PIS_DMA)               || \
-                             ((x) == PIS_ADC1_INJECT)       || \
-                             ((x) == PIS_ADC1_REGULAT)      || \
-                             ((x) == PIS_ADC1_WINDOW))
+				 ((x) == PIS_GPIO_PIN0)         || \
+				 ((x) == PIS_GPIO_PIN1)         || \
+				 ((x) == PIS_GPIO_PIN2)         || \
+				 ((x) == PIS_GPIO_PIN3)         || \
+				 ((x) == PIS_GPIO_PIN4)         || \
+				 ((x) == PIS_GPIO_PIN5)         || \
+				 ((x) == PIS_GPIO_PIN6)         || \
+				 ((x) == PIS_GPIO_PIN7)         || \
+				 ((x) == PIS_GPIO_PIN8)         || \
+				 ((x) == PIS_GPIO_PIN9)         || \
+				 ((x) == PIS_GPIO_PIN10)        || \
+				 ((x) == PIS_GPIO_PIN11)        || \
+				 ((x) == PIS_GPIO_PIN12)        || \
+				 ((x) == PIS_GPIO_PIN13)        || \
+				 ((x) == PIS_GPIO_PIN14)        || \
+				 ((x) == PIS_GPIO_PIN15)        || \
+				 ((x) == PIS_ACMP_OUT0)         || \
+				 ((x) == PIS_ACMP_OUT1)         || \
+				 ((x) == PIS_DAC0_CH1)          || \
+				 ((x) == PIS_ACMP_OUT1)         || \
+				 ((x) == PIS_ADC0_INJECT)       || \
+				 ((x) == PIS_ADC0_REGULAT)      || \
+				 ((x) == PIS_ADC0_WINDOW)       || \
+				 ((x) == PIS_LVD)               || \
+				 ((x) == PIS_UART0_ASY_SEND)    || \
+				 ((x) == PIS_UART0_ASY_RECV)    || \
+				 ((x) == PIS_UART0_IRDAOUT)     || \
+				 ((x) == PIS_UART0_RTSOUT)      || \
+				 ((x) == PIS_UART0_TXOUT)       || \
+				 ((x) == PIS_UART0_SYN_SEND)    || \
+				 ((x) == PIS_UART0_SYN_RECV)    || \
+				 ((x) == PIS_UART1_ASY_SEND)    || \
+				 ((x) == PIS_UART1_ASY_RECV)    || \
+				 ((x) == PIS_UART1_IRDA)        || \
+				 ((x) == PIS_UART1_RTS)         || \
+				 ((x) == PIS_UART1_TXOUT)       || \
+				 ((x) == PIS_UART1_SYN_SEND)    || \
+				 ((x) == PIS_UART1_SYN_RECV)    || \
+				 ((x) == PIS_UART2_ASY_SEND)    || \
+				 ((x) == PIS_UART2_ASY_RECV)    || \
+				 ((x) == PIS_UART2_IRDA)        || \
+				 ((x) == PIS_UART2_RTS)         || \
+				 ((x) == PIS_UART2_TXOUT)       || \
+				 ((x) == PIS_UART2_SYN_SEND)    || \
+				 ((x) == PIS_UART2_SYN_RECV)    || \
+				 ((x) == PIS_UART3_ASY_SEND)    || \
+				 ((x) == PIS_UART3_ASY_RECV)    || \
+				 ((x) == PIS_UART3_IRDA)        || \
+				 ((x) == PIS_UART3_RTS)         || \
+				 ((x) == PIS_UART3_TXOUT)       || \
+				 ((x) == PIS_UART3_SYN_SEND)    || \
+				 ((x) == PIS_UART3_SYN_RECV)    || \
+				 ((x) == PIS_EUART0_RECV)       || \
+				 ((x) == PIS_EUART0_SEND)       || \
+				 ((x) == PIS_EUART0_TXOUT)      || \
+				 ((x) == PIS_EUART1_RECV)       || \
+				 ((x) == PIS_EUART1_SEND)       || \
+				 ((x) == PIS_EUART1_TXOUT)      || \
+				 ((x) == PIS_SPI0_RECV)         || \
+				 ((x) == PIS_SPI0_SEND)         || \
+				 ((x) == PIS_SPI0_NE)           || \
+				 ((x) == PIS_SPI1_RECV)         || \
+				 ((x) == PIS_SPI1_SEND)         || \
+				 ((x) == PIS_SPI1_NE)           || \
+				 ((x) == PIS_I2C0_RECV)         || \
+				 ((x) == PIS_I2C0_SEND)         || \
+				 ((x) == PIS_I2C1_RECV)         || \
+				 ((x) == PIS_I2C1_SEND)         || \
+				 ((x) == PIS_TIMER0_UPDATA)       || \
+				 ((x) == PIS_TIMER0_TRIG)         || \
+				 ((x) == PIS_TIMER0_INPUT)        || \
+				 ((x) == PIS_TIMER0_OUTPUT)       || \
+				 ((x) == PIS_TIMER1_UPDATA)       || \
+				 ((x) == PIS_TIMER1_TRIG)         || \
+				 ((x) == PIS_TIMER1_INPUT)        || \
+				 ((x) == PIS_TIMER1_OUTPUT)       || \
+				 ((x) == PIS_TIMER2_UPDATA)       || \
+				 ((x) == PIS_TIMER2_TRIG)         || \
+				 ((x) == PIS_TIMER2_INPUT)        || \
+				 ((x) == PIS_TIMER2_OUTPUT)       || \
+				 ((x) == PIS_TIMER3_UPDATA)       || \
+				 ((x) == PIS_TIMER3_TRIG)         || \
+				 ((x) == PIS_TIMER3_INPUT)        || \
+				 ((x) == PIS_TIMER3_OUTPUT)       || \
+				 ((x) == PIS_RTC_CLOCK)         || \
+				 ((x) == PIS_RTC_ALARM)         || \
+				 ((x) == PIS_LPTIM0_SYN_UPDATA) || \
+				 ((x) == PIS_LPTIM0_ASY_UPDATA) || \
+				 ((x) == PIS_LPUART0_ASY_RECV)  || \
+				 ((x) == PIS_LPUART0_ASY_SEND)  || \
+				 ((x) == PIS_LPUART0_SYN_RECV)  || \
+				 ((x) == PIS_LPUART0_SYN_SEND)  || \
+				 ((x) == PIS_DMA)               || \
+				 ((x) == PIS_ADC1_INJECT)       || \
+				 ((x) == PIS_ADC1_REGULAT)      || \
+				 ((x) == PIS_ADC1_WINDOW))
 #define IS_PIS_TRIG(x) 		(((x) == PIS_CH0_TIMER0_BRKIN)    || \
-                             ((x) == PIS_CH0_SPI1_CLK)      || \
-                             ((x) == PIS_CH0_LPTIM0_EXT0)   || \
-                             ((x) == PIS_CH0_ADC1_NORMAL)   || \
-                             ((x) == PIS_CH1_TIMER0_CH1IN)    || \
-                             ((x) == PIS_CH1_TIMER2_CH1IN)    || \
-                             ((x) == PIS_CH1_TIMER3_CH1IN)    || \
-                             ((x) == PIS_CH1_UART0_RX_IRDA) || \
-                             ((x) == PIS_CH1_LPTIM0_EXT1)   || \
-                             ((x) == PIS_CH1_ADC1_INSERT)   || \
-                             ((x) == PIS_CH2_TIMER0_CH2IN)    || \
-                             ((x) == PIS_CH2_TIMER2_CH2IN)    || \
-                             ((x) == PIS_CH2_TIMER3_CH2IN)    || \
-                             ((x) == PIS_CH2_LPTIM0_EXT2)   || \
-                             ((x) == PIS_CH2_UART1_RX_IRDA) || \
-                             ((x) == PIS_CH3_TIMER0_CH3IN)    || \
-                             ((x) == PIS_CH3_LPTIM0_EXT3)   || \
-                             ((x) == PIS_CH3_UART2_RX_IRDA) || \
-                             ((x) == PIS_CH4_TIMER0_CH4IN)    || \
-                             ((x) == PIS_CH4_TIMER0_ITR0)     || \
-                             ((x) == PIS_CH4_TIMER2_ITR0)     || \
-                             ((x) == PIS_CH4_TIMER3_ITR0)     || \
-                             ((x) == PIS_CH4_LPTIM0_EXT4)   || \
-                             ((x) == PIS_CH4_UART3_RX_IRDA) || \
-                             ((x) == PIS_CH5_SPI0_RX)       || \
-                             ((x) == PIS_CH5_LPTIM0_EXT5)   || \
-                             ((x) == PIS_CH5_EUART0_RX)     || \
-                             ((x) == PIS_CH5_TIMER0_ITR1)     || \
-                             ((x) == PIS_CH5_TIMER2_ITR1)     || \
-                             ((x) == PIS_CH5_TIMER3_ITR1)     || \
-                             ((x) == PIS_CH6_SPI0_CLK)      || \
-                             ((x) == PIS_CH6_ADC0_NORMAL)   || \
-                             ((x) == PIS_CH6_LPTIM0_EXT6)   || \
-                             ((x) == PIS_CH6_EUART1_RX)     || \
-                             ((x) == PIS_CH6_TIMER0_ITR2)     || \
-                             ((x) == PIS_CH6_TIMER2_ITR2)     || \
-                             ((x) == PIS_CH6_TIMER3_ITR2)     || \
-                             ((x) == PIS_CH6_DAC_CH1)       || \
-                             ((x) == PIS_CH7_SPI1_RX)       || \
-                             ((x) == PIS_CH7_ADC0_INSERT)   || \
-                             ((x) == PIS_CH7_LPTIM0_EXT7)   || \
-                             ((x) == PIS_CH7_DMA)           || \
-                             ((x) == PIS_CH7_TIMER0_ITR3)     || \
-                             ((x) == PIS_CH7_TIMER2_ITR3)     || \
-                             ((x) == PIS_CH7_TIMER3_ITR3)     || \
-                             ((x) == PIS_CH7_DAC_CH0)       || \
-                             ((x) == PIS_CH7_LPUART_RX))
+				 ((x) == PIS_CH0_SPI1_CLK)      || \
+				 ((x) == PIS_CH0_LPTIM0_EXT0)   || \
+				 ((x) == PIS_CH0_ADC1_NORMAL)   || \
+				 ((x) == PIS_CH1_TIMER0_CH1IN)    || \
+				 ((x) == PIS_CH1_TIMER2_CH1IN)    || \
+				 ((x) == PIS_CH1_TIMER3_CH1IN)    || \
+				 ((x) == PIS_CH1_UART0_RX_IRDA) || \
+				 ((x) == PIS_CH1_LPTIM0_EXT1)   || \
+				 ((x) == PIS_CH1_ADC1_INSERT)   || \
+				 ((x) == PIS_CH2_TIMER0_CH2IN)    || \
+				 ((x) == PIS_CH2_TIMER2_CH2IN)    || \
+				 ((x) == PIS_CH2_TIMER3_CH2IN)    || \
+				 ((x) == PIS_CH2_LPTIM0_EXT2)   || \
+				 ((x) == PIS_CH2_UART1_RX_IRDA) || \
+				 ((x) == PIS_CH3_TIMER0_CH3IN)    || \
+				 ((x) == PIS_CH3_LPTIM0_EXT3)   || \
+				 ((x) == PIS_CH3_UART2_RX_IRDA) || \
+				 ((x) == PIS_CH4_TIMER0_CH4IN)    || \
+				 ((x) == PIS_CH4_TIMER0_ITR0)     || \
+				 ((x) == PIS_CH4_TIMER2_ITR0)     || \
+				 ((x) == PIS_CH4_TIMER3_ITR0)     || \
+				 ((x) == PIS_CH4_LPTIM0_EXT4)   || \
+				 ((x) == PIS_CH4_UART3_RX_IRDA) || \
+				 ((x) == PIS_CH5_SPI0_RX)       || \
+				 ((x) == PIS_CH5_LPTIM0_EXT5)   || \
+				 ((x) == PIS_CH5_EUART0_RX)     || \
+				 ((x) == PIS_CH5_TIMER0_ITR1)     || \
+				 ((x) == PIS_CH5_TIMER2_ITR1)     || \
+				 ((x) == PIS_CH5_TIMER3_ITR1)     || \
+				 ((x) == PIS_CH6_SPI0_CLK)      || \
+				 ((x) == PIS_CH6_ADC0_NORMAL)   || \
+				 ((x) == PIS_CH6_LPTIM0_EXT6)   || \
+				 ((x) == PIS_CH6_EUART1_RX)     || \
+				 ((x) == PIS_CH6_TIMER0_ITR2)     || \
+				 ((x) == PIS_CH6_TIMER2_ITR2)     || \
+				 ((x) == PIS_CH6_TIMER3_ITR2)     || \
+				 ((x) == PIS_CH6_DAC_CH1)       || \
+				 ((x) == PIS_CH7_SPI1_RX)       || \
+				 ((x) == PIS_CH7_ADC0_INSERT)   || \
+				 ((x) == PIS_CH7_LPTIM0_EXT7)   || \
+				 ((x) == PIS_CH7_DMA)           || \
+				 ((x) == PIS_CH7_TIMER0_ITR3)     || \
+				 ((x) == PIS_CH7_TIMER2_ITR3)     || \
+				 ((x) == PIS_CH7_TIMER3_ITR3)     || \
+				 ((x) == PIS_CH7_DAC_CH0)       || \
+				 ((x) == PIS_CH7_LPUART_RX))
 #define IS_PIS_CLOCK(x) 	(((x) == PIS_CLK_PCLK1)  || \
-                             ((x) == PIS_CLK_PCLK2)  || \
-                             ((x) == PIS_CLK_SYS) || \
-                             ((x) == PIS_CLK_LP))
+				 ((x) == PIS_CLK_PCLK2)  || \
+				 ((x) == PIS_CLK_SYS) || \
+				 ((x) == PIS_CLK_LP))
 #define IS_PIS_EDGE(x) 		(((x) == PIS_EDGE_NONE) || \
-                             ((x) == PIS_EDGE_UP)   || \
-                             ((x) == PIS_EDGE_DOWN) || \
-                             ((x) == PIS_EDGE_UP_DOWN))
+				 ((x) == PIS_EDGE_UP)   || \
+				 ((x) == PIS_EDGE_DOWN) || \
+				 ((x) == PIS_EDGE_UP_DOWN))
 #define IS_PIS_OUTPUT(x) 	(((x) == PIS_OUT_LEVEL) || \
-                             ((x) == PIS_OUT_PULSE))
+				 ((x) == PIS_OUT_PULSE))
 #define IS_PIS_OUPUT_CH(x)	(((x) == PIS_OUT_CH_0) || \
-                             ((x) == PIS_OUT_CH_1) || \
-                             ((x) == PIS_OUT_CH_2) || \
-                             ((x) == PIS_OUT_CH_3))
+				 ((x) == PIS_OUT_CH_1) || \
+				 ((x) == PIS_OUT_CH_2) || \
+				 ((x) == PIS_OUT_CH_3))
 #define IS_PIS_MODU_TARGET(x)	(((x) == PIS_UART0_TX) || \
-                                 ((x) == PIS_UART1_TX) || \
-                                 ((x) == PIS_UART2_TX) || \
-                                 ((x) == PIS_UART3_TX) || \
-                                 ((x) == PIS_LPUART0_TX))
+				 ((x) == PIS_UART1_TX) || \
+				 ((x) == PIS_UART2_TX) || \
+				 ((x) == PIS_UART3_TX) || \
+				 ((x) == PIS_LPUART0_TX))
 #define IS_PIS_MODU_LEVEL(x)	(((x) == PIS_LOW_LEVEL) || \
-                                 ((x) == PIS_HIGH_LEVEL))
+				 ((x) == PIS_HIGH_LEVEL))
 #define IS_PIS_MODU_SRC(x)	(((x) == PIS_SRC_NONE)   || \
-                             ((x) == PIS_SRC_TIMER0)   || \
-                             ((x) == PIS_SRC_TIMER1)   || \
-                             ((x) == PIS_SRC_TIMER2)   || \
-                             ((x) == PIS_SRC_TIMER3)   || \
-                             ((x) == PIS_SRC_TIMER6)   || \
-                             ((x) == PIS_SRC_TIMER7)   || \
-                             ((x) == PIS_SRC_LPTIM0) || \
-                             ((x) == PIS_SRC_BUZ))
+				 ((x) == PIS_SRC_TIMER0)   || \
+				 ((x) == PIS_SRC_TIMER1)   || \
+				 ((x) == PIS_SRC_TIMER2)   || \
+				 ((x) == PIS_SRC_TIMER3)   || \
+				 ((x) == PIS_SRC_TIMER6)   || \
+				 ((x) == PIS_SRC_TIMER7)   || \
+				 ((x) == PIS_SRC_LPTIM0) || \
+				 ((x) == PIS_SRC_BUZ))
 #define IS_PIS_MODU_CHANNEL(x)	(((x) == PIS_TIMER_CH1) || \
-                                 ((x) == PIS_TIMER_CH2) || \
-                                 ((x) == PIS_TIMER_CH3) || \
-                                 ((x) == PIS_TIMER_CH4))
+				 ((x) == PIS_TIMER_CH2) || \
+				 ((x) == PIS_TIMER_CH3) || \
+				 ((x) == PIS_TIMER_CH4))
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_pmu.h

@@ -23,6 +23,7 @@ extern "C" {
 
 #include "utils.h"
 #include "ald_syscfg.h"
+#include "ald_bkpc.h"
 
 
 /** @addtogroup ES32FXXX_ALD
@@ -37,66 +38,66 @@ extern "C" {
   * @{
   */
 #define PMU_SRAM0_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define PMU_SRAM0_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSS));\
+	SYSCFG_LOCK();					\
+} while (0)
 #define PMU_SRAM1_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define PMU_SRAM1_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(PMU->PWRCR, BIT(PMU_PWRCR_SRAM_POSE));\
+	SYSCFG_LOCK();					\
+} while (0)
 #define PMU_BXCAN_ENABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	SET_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 #define PMU_BXCAN_DISABLE()				\
-    do {							\
-        SYSCFG_UNLOCK();				\
-        CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK);	\
-        SYSCFG_LOCK();					\
-    } while (0)
+do {							\
+	SYSCFG_UNLOCK();				\
+	CLEAR_BIT(PMU->PWRCR, PMU_PWRCR_BXCAN_MSK);	\
+	SYSCFG_LOCK();					\
+} while (0)
 
 #define PMU_LPSTOP_ENABLE()			\
-    do {						\
-        SYSCFG_UNLOCK();			\
-        SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);	\
-        SYSCFG_LOCK();				\
-    } while (0)
+do {						\
+	SYSCFG_UNLOCK();			\
+	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);	\
+	SYSCFG_LOCK();				\
+} while (0)
 #define PMU_LPSTOP_DISABLE()			\
-    do {						\
-        SYSCFG_UNLOCK();			\
-        CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);	\
-        SYSCFG_LOCK();				\
-    } while (0)
+do {						\
+	SYSCFG_UNLOCK();			\
+	CLEAR_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);	\
+	SYSCFG_LOCK();				\
+} while (0)
 #define PMU_MTSTOP_ENABLE()			\
-    do {						\
-        SYSCFG_UNLOCK();			\
-        SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK);	\
-        SYSCFG_LOCK();				\
-    } while (0)
+do {						\
+	SYSCFG_UNLOCK();			\
+	SET_BIT(PMU->CR, PMU_CR_MTSTOP_MSK);	\
+	SYSCFG_LOCK();				\
+} while (0)
 #define PMU_MTSTOP_DISABLE()			\
-    do {						\
-        SYSCFG_UNLOCK();			\
-        CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK);	\
-        SYSCFG_LOCK();				\
-    } while (0)
+do {						\
+	SYSCFG_UNLOCK();			\
+	CLEAR_BIT(PMU->CR, PMU_CR_MTSTOP_MSK);	\
+	SYSCFG_LOCK();				\
+} while (0)
 
 #define PMU_GET_LVD_STATUS()	(READ_BITS(PMU->LVDCR, PMU_LVDCR_LVDO_MSK, PMU_LVDCR_LVDO_POS))
 /**
@@ -110,57 +111,54 @@ extern "C" {
 /**
   * @brief Low power mode
   */
-typedef enum
-{
-    PMU_LP_STOP1   = 0x0,	/**< Stop1 */
-    PMU_LP_STOP2   = 0x1,	/**< Stop2 */
+typedef enum {
+	PMU_LP_STOP1   = 0x0U,	/**< Stop1 */
+	PMU_LP_STOP2   = 0x1U,	/**< Stop2 */
+	PMU_LP_STANDBY = 0x2U,	/**< Standby */
 } pmu_lp_mode_t;
 
-typedef enum
-{
-    PMU_SR_WUF = (1U << 0),
+typedef enum {
+	PMU_SR_WUF     = (1U << 0),
+	PMU_SR_STANDBY = (1U << 1),
 } pmu_status_t;
 
 /**
   * @brief LVD voltage select
   */
-typedef enum
-{
-    PMU_LVD_VOL_SEL_2_0 = 0x0,	/**< 2.0V ~ 2.05V */
-    PMU_LVD_VOL_SEL_2_1 = 0x1,	/**< 2.1V ~ 2.15V */
-    PMU_LVD_VOL_SEL_2_2 = 0x2,	/**< 2.2V ~ 2.25V */
-    PMU_LVD_VOL_SEL_2_4 = 0x3,	/**< 2.4V ~ 2.45V */
-    PMU_LVD_VOL_SEL_2_6 = 0x4,	/**< 2.6V ~ 2.65V */
-    PMU_LVD_VOL_SEL_2_8 = 0x5,	/**< 2.8V ~ 2.85V */
-    PMU_LVD_VOL_SEL_3_0 = 0x6,	/**< 3.0V ~ 3.05V */
-    PMU_LVD_VOL_SEL_3_6 = 0x7,	/**< 3.6V ~ 3.65V */
-    PMU_LVD_VOL_SEL_4_0 = 0x8,	/**< 4.0V ~ 4.05V */
-    PMU_LVD_VOL_SEL_4_6 = 0x9,	/**< 4.6V ~ 4.65V */
-    PMU_LVD_VOL_SEL_2_3 = 0xA,	/**< 2.3V ~ 2.35V */
-    PMU_LVD_VOL_SEL_EXT = 0xF,	/**< Select external input. It must be 1.2V */
+typedef enum {
+	PMU_LVD_VOL_SEL_2_0 = 0x0U,	/**< 2.0V ~ 2.05V */
+	PMU_LVD_VOL_SEL_2_1 = 0x1U,	/**< 2.1V ~ 2.15V */
+	PMU_LVD_VOL_SEL_2_2 = 0x2U,	/**< 2.2V ~ 2.25V */
+	PMU_LVD_VOL_SEL_2_4 = 0x3U,	/**< 2.4V ~ 2.45V */
+	PMU_LVD_VOL_SEL_2_6 = 0x4U,	/**< 2.6V ~ 2.65V */
+	PMU_LVD_VOL_SEL_2_8 = 0x5U,	/**< 2.8V ~ 2.85V */
+	PMU_LVD_VOL_SEL_3_0 = 0x6U,	/**< 3.0V ~ 3.05V */
+	PMU_LVD_VOL_SEL_3_6 = 0x7U,	/**< 3.6V ~ 3.65V */
+	PMU_LVD_VOL_SEL_4_0 = 0x8U,	/**< 4.0V ~ 4.05V */
+	PMU_LVD_VOL_SEL_4_6 = 0x9U,	/**< 4.6V ~ 4.65V */
+	PMU_LVD_VOL_SEL_2_3 = 0xAU,	/**< 2.3V ~ 2.35V */
+	PMU_LVD_VOL_SEL_EXT = 0xFU,	/**< Select external input. It must be 1.2V */
 } pmu_lvd_voltage_sel_t;
 
 /**
   * @brief LVD trigger mode
   */
-typedef enum
-{
-    PMU_LVD_TRIGGER_RISING_EDGE    = 0x0,	/**< Rising edge */
-    PMU_LVD_TRIGGER_FALLING_EDGE   = 0x1,	/**< Falling edge */
-    PMU_LVD_TRIGGER_HIGH_LEVEL     = 0x2,	/**< High level */
-    PMU_LVD_TRIGGER_LOW_LEVEL      = 0x3,	/**< Low level */
-    PMU_LVD_TRIGGER_RISING_FALLING = 0x4,	/**< Rising and falling edge */
+typedef enum {
+	PMU_LVD_TRIGGER_RISING_EDGE    = 0x0U,	/**< Rising edge */
+	PMU_LVD_TRIGGER_FALLING_EDGE   = 0x1U,	/**< Falling edge */
+	PMU_LVD_TRIGGER_HIGH_LEVEL     = 0x2U,	/**< High level */
+	PMU_LVD_TRIGGER_LOW_LEVEL      = 0x3U,	/**< Low level */
+	PMU_LVD_TRIGGER_RISING_FALLING = 0x4U,	/**< Rising and falling edge */
 } pmu_lvd_trigger_mode_t;
 
 /**
   * @brief LDO output voltage selest in low power mode
   */
-typedef enum
-{
-    PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0,	/**< 1.5V */
-    PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1,	/**< 1.4V */
-    PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2,	/**< 1.3V */
-    PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4,	/**< 1.2V */
+typedef enum {
+	PMU_LDO_LPMODE_OUTPUT_1_5 = 0x0U,	/**< 1.5V */
+	PMU_LDO_LPMODE_OUTPUT_1_4 = 0x1U,	/**< 1.4V */
+	PMU_LDO_LPMODE_OUTPUT_1_3 = 0x2U,	/**< 1.3V */
+	PMU_LDO_LPMODE_OUTPUT_1_2 = 0x4U,	/**< 1.2V */
 } pmu_ldo_lpmode_output_t;
 /**
   * @}
@@ -171,29 +169,30 @@ typedef enum
   * @{
   */
 #define IS_PMU_LP_MODE(x)		(((x) == PMU_LP_STOP1) || \
-                                 ((x) == PMU_LP_STOP2))
-#define IS_PMU_STATUS(x)		((x) == PMU_SR_WUF)
+                                         ((x) == PMU_LP_STOP2) || \
+                                         ((x) == PMU_LP_STANDBY))
+#define IS_PMU_STATUS(x)		(((x) == PMU_SR_WUF) || ((x) == PMU_SR_STANDBY))
 #define IS_PMU_LVD_VOL_SEL(x)		(((x) == PMU_LVD_VOL_SEL_2_0) || \
-                                     ((x) == PMU_LVD_VOL_SEL_2_1) || \
-                                     ((x) == PMU_LVD_VOL_SEL_2_2) || \
-                                     ((x) == PMU_LVD_VOL_SEL_2_4) || \
-                                     ((x) == PMU_LVD_VOL_SEL_2_6) || \
-                                     ((x) == PMU_LVD_VOL_SEL_2_8) || \
-                                     ((x) == PMU_LVD_VOL_SEL_3_0) || \
-                                     ((x) == PMU_LVD_VOL_SEL_3_6) || \
-                                     ((x) == PMU_LVD_VOL_SEL_4_0) || \
-                                     ((x) == PMU_LVD_VOL_SEL_4_6) || \
-                                     ((x) == PMU_LVD_VOL_SEL_2_3) || \
-                                     ((x) == PMU_LVD_VOL_SEL_EXT))
+                                         ((x) == PMU_LVD_VOL_SEL_2_1) || \
+                                         ((x) == PMU_LVD_VOL_SEL_2_2) || \
+                                         ((x) == PMU_LVD_VOL_SEL_2_4) || \
+                                         ((x) == PMU_LVD_VOL_SEL_2_6) || \
+                                         ((x) == PMU_LVD_VOL_SEL_2_8) || \
+                                         ((x) == PMU_LVD_VOL_SEL_3_0) || \
+                                         ((x) == PMU_LVD_VOL_SEL_3_6) || \
+                                         ((x) == PMU_LVD_VOL_SEL_4_0) || \
+                                         ((x) == PMU_LVD_VOL_SEL_4_6) || \
+                                         ((x) == PMU_LVD_VOL_SEL_2_3) || \
+                                         ((x) == PMU_LVD_VOL_SEL_EXT))
 #define IS_PMU_LVD_TRIGGER_MODE(x)	(((x) == PMU_LVD_TRIGGER_RISING_EDGE)  || \
-                                     ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
-                                     ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL)   || \
-                                     ((x) == PMU_LVD_TRIGGER_LOW_LEVEL)    || \
-                                     ((x) == PMU_LVD_TRIGGER_RISING_FALLING))
+                                         ((x) == PMU_LVD_TRIGGER_FALLING_EDGE) || \
+                                         ((x) == PMU_LVD_TRIGGER_HIGH_LEVEL)   || \
+                                         ((x) == PMU_LVD_TRIGGER_LOW_LEVEL)    || \
+                                         ((x) == PMU_LVD_TRIGGER_RISING_FALLING))
 #define IS_PMU_LDO_LPMODE_OUTPUT(x)	(((x) == PMU_LDO_LPMODE_OUTPUT_1_5) || \
-                                     ((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
-                                     ((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
-                                     ((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
+                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_4) || \
+                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_3) || \
+                                         ((x) == PMU_LDO_LPMODE_OUTPUT_1_2))
 /**
   * @}
   */
@@ -207,17 +206,18 @@ typedef enum
 /* Low power mode select */
 __STATIC_INLINE__ void ald_pmu_sleep()
 {
-    __WFI();
+	__WFI();
 }
 
 __STATIC_INLINE__ void ald_pmu_sleep_deep()
 {
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-    __WFI();
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
 }
 
 void ald_pmu_stop1_enter(void);
 void ald_pmu_stop2_enter(void);
+void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level);
 void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state);
 flag_status_t ald_pmu_get_status(pmu_status_t sr);
 void ald_pmu_clear_status(pmu_status_t sr);

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rmu.h

@@ -37,127 +37,128 @@ extern "C" {
 /**
   * @brief RMU BOR fliter
   */
-typedef enum
-{
-    RMU_BORFLT_1 = 0x1,	/**< 1 cycle  */
-    RMU_BORFLT_2 = 0x2,	/**< 2 cycles */
-    RMU_BORFLT_3 = 0x3,	/**< 3 cycles */
-    RMU_BORFLT_4 = 0x4,	/**< 4 cycles */
-    RMU_BORFLT_5 = 0x5,	/**< 5 cycles */
-    RMU_BORFLT_6 = 0x6,	/**< 6 cycles */
-    RMU_BORFLT_7 = 0x7,	/**< 7 cycles */
+typedef enum {
+	RMU_BORFLT_1 = 0x1U,	/**< 1 cycle  */
+	RMU_BORFLT_2 = 0x2U,	/**< 2 cycles */
+	RMU_BORFLT_3 = 0x3U,	/**< 3 cycles */
+	RMU_BORFLT_4 = 0x4U,	/**< 4 cycles */
+	RMU_BORFLT_5 = 0x5U,	/**< 5 cycles */
+	RMU_BORFLT_6 = 0x6U,	/**< 6 cycles */
+	RMU_BORFLT_7 = 0x7U,	/**< 7 cycles */
 } rmu_bor_filter_t;
 
 /**
   * @brief RMU BOR voltage
   */
-typedef enum
-{
-    RMU_VOL_1_7 = 0x0,	/**< 1.7V */
-    RMU_VOL_2_0 = 0x1,	/**< 2.0V */
-    RMU_VOL_2_1 = 0x2,	/**< 2.1V */
-    RMU_VOL_2_2 = 0x3,	/**< 2.2V */
-    RMU_VOL_2_3 = 0x4,	/**< 2.3V */
-    RMU_VOL_2_4 = 0x5,	/**< 2.4V */
-    RMU_VOL_2_5 = 0x6,	/**< 2.5V */
-    RMU_VOL_2_6 = 0x7,	/**< 2.6V */
-    RMU_VOL_2_8 = 0x8,	/**< 2.8V */
-    RMU_VOL_3_0 = 0x9,	/**< 3.0V */
-    RMU_VOL_3_1 = 0xA,	/**< 3.1V */
-    RMU_VOL_3_3 = 0xB,	/**< 3.3V */
-    RMU_VOL_3_6 = 0xC,	/**< 3.6V */
-    RMU_VOL_3_7 = 0xD,	/**< 3.7V */
-    RMU_VOL_4_0 = 0xE,	/**< 4.0V */
-    RMU_VOL_4_3 = 0xF,	/**< 4.3V */
+typedef enum {
+	RMU_VOL_1_8 = 0x0U,	/**< 1.8V */
+	RMU_VOL_2_0 = 0x1U,	/**< 2.0V */
+	RMU_VOL_2_2 = 0x2U,	/**< 2.2V */
+	RMU_VOL_2_4 = 0x3U,	/**< 2.4V */
+	RMU_VOL_2_6 = 0x4U,	/**< 2.6V */
+	RMU_VOL_2_8 = 0x5U,	/**< 2.8V */
+	RMU_VOL_3_0 = 0x6U,	/**< 3.0V */
+	RMU_VOL_3_2 = 0x7U,	/**< 3.2V */
+	RMU_VOL_3_4 = 0x8U,	/**< 3.4V */
+	RMU_VOL_3_6 = 0x9U,	/**< 3.6V */
+	RMU_VOL_3_8 = 0xAU,	/**< 3.8V */
+	RMU_VOL_4_0 = 0xBU,	/**< 4.0V */
+	RMU_VOL_4_2 = 0xCU,	/**< 4.2V */
+	RMU_VOL_4_4 = 0xDU,	/**< 4.4V */
+	RMU_VOL_4_6 = 0xEU,	/**< 4.6V */
+	RMU_VOL_4_8 = 0xFU,	/**< 4.8V */
 } rmu_bor_vol_t;
 
 /**
   * @brief RMU reset status
   */
-typedef enum
-{
-    RMU_RST_POR    = (1U << 0),	/**< POR */
-    RMU_RST_WAKEUP = (1U << 1),	/**< WAKEUP */
-    RMU_RST_BOR    = (1U << 2),	/**< BOR */
-    RMU_RST_NMRST  = (1U << 3),	/**< NMRST */
-    RMU_RST_IWDT   = (1U << 4),	/**< IWDT */
-    RMU_RST_WWDT   = (1U << 5),	/**< WWDT */
-    RMU_RST_LOCKUP = (1U << 6),	/**< LOCKUP */
-    RMU_RST_CHIP   = (1U << 7),	/**< CHIP */
-    RMU_RST_MCU    = (1U << 8),	/**< MCU */
-    RMU_RST_CPU    = (1U << 9),	/**< CPU */
-    RMU_RST_CFG    = (1U << 10),	/**< CFG */
-    RMU_RST_CFGERR = (1U << 16),	/**< CFG Error */
+typedef enum {
+	RMU_RST_POR    = (1U << 0),	/**< POR */
+	RMU_RST_WAKEUP = (1U << 1),	/**< WAKEUP */
+	RMU_RST_BOR    = (1U << 2),	/**< BOR */
+	RMU_RST_NMRST  = (1U << 3),	/**< NMRST */
+	RMU_RST_IWDT   = (1U << 4),	/**< IWDT */
+	RMU_RST_WWDT   = (1U << 5),	/**< WWDT */
+	RMU_RST_LOCKUP = (1U << 6),	/**< LOCKUP */
+	RMU_RST_CHIP   = (1U << 7),	/**< CHIP */
+	RMU_RST_MCU    = (1U << 8),	/**< MCU */
+	RMU_RST_CPU    = (1U << 9),	/**< CPU */
+	RMU_RST_CFG    = (1U << 10),	/**< CFG */
+	RMU_RST_CFGERR = (1U << 16),	/**< CFG Error */
+	RMU_RST_ALL    = (0xFFFFFU),	/**< ALL */
 } rmu_state_t;
 
 /**
   * @brief RMU periperal select bit
-  * @note  ES32F065x:
-  *          AD16C4T0--TIMER0
-  *          GP16C4T0--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
-  *
-  *        ES32F033x:
-  *        ES32F093x:
-  *          GP16C4T0--TIMER0
-  *          GP16C4T1--TIMER6
-  *          GP16C2T0--TIMER2
-  *          GP16C2T1--TIMER3
-  *          BS16T0----TIMER1
-  *          BS16T1----TIMER4
-  *          BS16T2----TIMER5
-  *          BS16T3----TIMER7
+  * @verbatim
+      In this module, for the convenience of code maintenance,
+      TIMERx is used to indicate the sequence of the timer peripheral.
+      Different product series TIMERx represent different meanings:
+      1. For ES32F065x series:
+      TIMER0 ----> AD16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+      TIMER4 ----> BS16T1
+      TIMER5 ----> BS16T2
+      TIMER6 ----> GP16C4T0
+      TIMER7 ----> BS16T3
+     
+      2. For ES32F033x/ES32F093x series:
+      TIMER0 ----> GP16C4T0
+      TIMER1 ----> BS16T0
+      TIMER2 ----> GP16C2T0
+      TIMER3 ----> GP16C2T1
+      TIMER4 ----> BS16T1
+      TIMER5 ----> BS16T2
+      TIMER6 ----> GP16C4T1
+      TIMER7 ----> BS16T3
+    @endverbatim
   */
-typedef enum
-{
-    RMU_PERH_GPIO    = (1U << 0),			/**< AHB1: GPIO */
-    RMU_PERH_CRC     = (1U << 1),			/**< AHB1: CRC */
-    RMU_PERH_CALC    = (1U << 2),			/**< AHB1: CALC */
-    RMU_PERH_CRYPT   = (1U << 3),			/**< AHB1: CRYPT */
-    RMU_PERH_TRNG    = (1U << 4),			/**< AHB1: TRNG */
-    RMU_PERH_PIS     = (1U << 5),			/**< AHB1: PIS */
-    RMU_PERH_CHIP    = (1U << 0)  | (1U << 27),	/**< AHB2: CHIP */
-    RMU_PERH_CPU     = (1U << 1)  | (1U << 27),	/**< AHB2: CPU */
-    RMU_PERH_TIMER0  = (1U << 0)  | (1U << 28),	/**< APB1: TIMER0 */
-    RMU_PERH_TIMER1  = (1U << 1)  | (1U << 28),	/**< APB1: TIMER1 */
-    RMU_PERH_TIMER2  = (1U << 2)  | (1U << 28),	/**< APB1: TIMER2 */
-    RMU_PERH_TIMER3  = (1U << 3)  | (1U << 28),	/**< APB1: TIMER3 */
-    RMU_PERH_TIMER4  = (1U << 4)  | (1U << 28),	/**< APB1: TIMER4 */
-    RMU_PERH_TIMER5  = (1U << 5)  | (1U << 28),	/**< APB1: TIMER5 */
-    RMU_PERH_TIMER6  = (1U << 6)  | (1U << 28),	/**< APB1: TIMER6 */
-    RMU_PERH_TIMER7  = (1U << 7)  | (1U << 28),	/**< APB1: TIMER7 */
-    RMU_PERH_UART0   = (1U << 8)  | (1U << 28),	/**< APB1: UART0 */
-    RMU_PERH_UART1   = (1U << 9)  | (1U << 28),	/**< APB1: UART1 */
-    RMU_PERH_UART2   = (1U << 10) | (1U << 28),	/**< APB1: UART2 */
-    RMU_PERH_UART3   = (1U << 11) | (1U << 28),	/**< APB1: UART3 */
-    RMU_PERH_USART0  = (1U << 12) | (1U << 28),	/**< APB1: EUART0 */
-    RMU_PERH_USART1  = (1U << 13) | (1U << 28),	/**< APB1: EUART1 */
-    RMU_PERH_SPI0    = (1U << 16) | (1U << 28),	/**< APB1: SPI0 */
-    RMU_PERH_SPI1    = (1U << 17) | (1U << 28),	/**< APB1: SPI1 */
-    RMU_PERH_SPI2    = (1U << 18) | (1U << 28),	/**< APB1: SPI2 */
-    RMU_PERH_I2C0    = (1U << 20) | (1U << 28),	/**< APB1: I2C0 */
-    RMU_PERH_I2C1    = (1U << 21) | (1U << 28),	/**< APB1: I2C1 */
-    RMU_PERH_CAN0    = (1U << 24) | (1U << 28),	/**< APB1: CAN0 */
-    RMU_PERH_LPTIM0  = (1U << 0)  | (1U << 29),	/**< APB2: LPTIM0 */
-    RMU_PERH_LPUART0 = (1U << 2)  | (1U << 29),	/**< APB2: LPUART */
-    RMU_PERH_ADC0    = (1U << 4)  | (1U << 29),	/**< APB2: ADC0 */
-    RMU_PERH_ADC1    = (1U << 5)  | (1U << 29),	/**< APB2: ADC1 */
-    RMU_PERH_ACMP0   = (1U << 6)  | (1U << 29),	/**< APB2: ACMP0 */
-    RMU_PERH_ACMP1   = (1U << 7)  | (1U << 29),	/**< APB2: ACMP1 */
-    RMU_PERH_OPAMP   = (1U << 8)  | (1U << 29),	/**< APB2: OPAMP */
-    RMU_PERH_DAC0    = (1U << 9)  | (1U << 29),	/**< APB2: DAC0 */
-    RMU_PERH_WWDT    = (1U << 12) | (1U << 29),	/**< APB2: WWDT */
-    RMU_PERH_LCD     = (1U << 13) | (1U << 29),	/**< APB2: LCD */
-    RMU_PERH_IWDT    = (1U << 14) | (1U << 29),	/**< APB2: IWDT */
-    RMU_PERH_RTC     = (1U << 15) | (1U << 29),	/**< APB2: RTC */
-    RMU_PERH_TSENSE  = (1U << 16) | (1U << 29),	/**< APB2: TSENSE */
-    RMU_PERH_BKPC    = (1U << 17) | (1U << 29),	/**< APB2: BKPC */
-    RMU_PERH_BKPRAM  = (1U << 18) | (1U << 29),	/**< APB2: BKPRAM */
+typedef enum {
+	RMU_PERH_GPIO    = (1U << 0),			/**< AHB1: GPIO */
+	RMU_PERH_CRC     = (1U << 1),			/**< AHB1: CRC */
+	RMU_PERH_CALC    = (1U << 2),			/**< AHB1: CALC */
+	RMU_PERH_CRYPT   = (1U << 3),			/**< AHB1: CRYPT */
+	RMU_PERH_TRNG    = (1U << 4),			/**< AHB1: TRNG */
+	RMU_PERH_PIS     = (1U << 5),			/**< AHB1: PIS */
+	RMU_PERH_CHIP    = (1U << 0)  | (1U << 27),	/**< AHB2: CHIP */
+	RMU_PERH_CPU     = (1U << 1)  | (1U << 27),	/**< AHB2: CPU */
+	RMU_PERH_TIMER0  = (1U << 0)  | (1U << 28),	/**< APB1: TIMER0 */
+	RMU_PERH_TIMER1  = (1U << 1)  | (1U << 28),	/**< APB1: TIMER1 */
+	RMU_PERH_TIMER2  = (1U << 2)  | (1U << 28),	/**< APB1: TIMER2 */
+	RMU_PERH_TIMER3  = (1U << 3)  | (1U << 28),	/**< APB1: TIMER3 */
+	RMU_PERH_TIMER4  = (1U << 4)  | (1U << 28),	/**< APB1: TIMER4 */
+	RMU_PERH_TIMER5  = (1U << 5)  | (1U << 28),	/**< APB1: TIMER5 */
+	RMU_PERH_TIMER6  = (1U << 6)  | (1U << 28),	/**< APB1: TIMER6 */
+	RMU_PERH_TIMER7  = (1U << 7)  | (1U << 28),	/**< APB1: TIMER7 */
+	RMU_PERH_UART0   = (1U << 8)  | (1U << 28),	/**< APB1: UART0 */
+	RMU_PERH_UART1   = (1U << 9)  | (1U << 28),	/**< APB1: UART1 */
+	RMU_PERH_UART2   = (1U << 10) | (1U << 28),	/**< APB1: UART2 */
+	RMU_PERH_UART3   = (1U << 11) | (1U << 28),	/**< APB1: UART3 */
+	RMU_PERH_USART0  = (1U << 12) | (1U << 28),	/**< APB1: EUART0 */
+	RMU_PERH_USART1  = (1U << 13) | (1U << 28),	/**< APB1: EUART1 */
+	RMU_PERH_SPI0    = (1U << 16) | (1U << 28),	/**< APB1: SPI0 */
+	RMU_PERH_SPI1    = (1U << 17) | (1U << 28),	/**< APB1: SPI1 */
+	RMU_PERH_SPI2    = (1U << 18) | (1U << 28),	/**< APB1: SPI2 */
+	RMU_PERH_I2C0    = (1U << 20) | (1U << 28),	/**< APB1: I2C0 */
+	RMU_PERH_I2C1    = (1U << 21) | (1U << 28),	/**< APB1: I2C1 */
+	RMU_PERH_CAN0    = (1U << 24) | (1U << 28),	/**< APB1: CAN0 */
+	RMU_PERH_LPTIM0  = (1U << 0)  | (1U << 29),	/**< APB2: LPTIM0 */
+	RMU_PERH_LPUART0 = (1U << 2)  | (1U << 29),	/**< APB2: LPUART */
+	RMU_PERH_ADC0    = (1U << 4)  | (1U << 29),	/**< APB2: ADC0 */
+	RMU_PERH_ADC1    = (1U << 5)  | (1U << 29),	/**< APB2: ADC1 */
+	RMU_PERH_ACMP0   = (1U << 6)  | (1U << 29),	/**< APB2: ACMP0 */
+	RMU_PERH_ACMP1   = (1U << 7)  | (1U << 29),	/**< APB2: ACMP1 */
+	RMU_PERH_OPAMP   = (1U << 8)  | (1U << 29),	/**< APB2: OPAMP */
+	RMU_PERH_DAC0    = (1U << 9)  | (1U << 29),	/**< APB2: DAC0 */
+	RMU_PERH_WWDT    = (1U << 12) | (1U << 29),	/**< APB2: WWDT */
+	RMU_PERH_LCD     = (1U << 13) | (1U << 29),	/**< APB2: LCD */
+	RMU_PERH_IWDT    = (1U << 14) | (1U << 29),	/**< APB2: IWDT */
+	RMU_PERH_RTC     = (1U << 15) | (1U << 29),	/**< APB2: RTC */
+	RMU_PERH_TSENSE  = (1U << 16) | (1U << 29),	/**< APB2: TSENSE */
+	RMU_PERH_BKPC    = (1U << 17) | (1U << 29),	/**< APB2: BKPC */
+	RMU_PERH_BKPRAM  = (1U << 18) | (1U << 29),	/**< APB2: BKPRAM */
 } rmu_peripheral_t;
 /**
   * @}
@@ -168,40 +169,41 @@ typedef enum
   * @{
   */
 #define IS_RMU_BORFLT(x)	(((x) == RMU_BORFLT_1) || \
-                             ((x) == RMU_BORFLT_2) || \
-                             ((x) == RMU_BORFLT_3) || \
-                             ((x) == RMU_BORFLT_4) || \
-                             ((x) == RMU_BORFLT_5) || \
-                             ((x) == RMU_BORFLT_6) || \
-                             ((x) == RMU_BORFLT_7))
-#define IS_RMU_BORVOL(x)	(((x) == RMU_VOL_1_7) || \
-                             ((x) == RMU_VOL_2_0) || \
-                             ((x) == RMU_VOL_2_1) || \
-                             ((x) == RMU_VOL_2_2) || \
-                             ((x) == RMU_VOL_2_3) || \
-                             ((x) == RMU_VOL_2_4) || \
-                             ((x) == RMU_VOL_2_5) || \
-                             ((x) == RMU_VOL_2_6) || \
-                             ((x) == RMU_VOL_2_8) || \
-                             ((x) == RMU_VOL_3_0) || \
-                             ((x) == RMU_VOL_3_1) || \
-                             ((x) == RMU_VOL_3_3) || \
-                             ((x) == RMU_VOL_3_6) || \
-                             ((x) == RMU_VOL_3_7) || \
-                             ((x) == RMU_VOL_4_0) || \
-                             ((x) == RMU_VOL_4_3))
+                                 ((x) == RMU_BORFLT_2) || \
+                                 ((x) == RMU_BORFLT_3) || \
+                                 ((x) == RMU_BORFLT_4) || \
+                                 ((x) == RMU_BORFLT_5) || \
+                                 ((x) == RMU_BORFLT_6) || \
+                                 ((x) == RMU_BORFLT_7))
+#define IS_RMU_BORVOL(x)	(((x) == RMU_VOL_1_8) || \
+                                 ((x) == RMU_VOL_2_0) || \
+                                 ((x) == RMU_VOL_2_2) || \
+                                 ((x) == RMU_VOL_2_4) || \
+                                 ((x) == RMU_VOL_2_6) || \
+                                 ((x) == RMU_VOL_2_8) || \
+                                 ((x) == RMU_VOL_3_0) || \
+                                 ((x) == RMU_VOL_3_2) || \
+                                 ((x) == RMU_VOL_3_4) || \
+                                 ((x) == RMU_VOL_3_6) || \
+                                 ((x) == RMU_VOL_3_8) || \
+                                 ((x) == RMU_VOL_4_0) || \
+                                 ((x) == RMU_VOL_4_2) || \
+                                 ((x) == RMU_VOL_4_4) || \
+                                 ((x) == RMU_VOL_4_6) || \
+                                 ((x) == RMU_VOL_4_8))
 #define IS_RMU_STATE(x)		(((x) == RMU_RST_POR)    || \
-                             ((x) == RMU_RST_WAKEUP) || \
-                             ((x) == RMU_RST_BOR)    || \
-                             ((x) == RMU_RST_NMRST)  || \
-                             ((x) == RMU_RST_IWDT)   || \
-                             ((x) == RMU_RST_WWDT)   || \
-                             ((x) == RMU_RST_LOCKUP) || \
-                             ((x) == RMU_RST_CHIP)   || \
-                             ((x) == RMU_RST_MCU)    || \
-                             ((x) == RMU_RST_CPU)    || \
-                             ((x) == RMU_RST_CFG)    || \
-                             ((x) == RMU_RST_CFGERR))
+                                 ((x) == RMU_RST_WAKEUP) || \
+                                 ((x) == RMU_RST_BOR)    || \
+                                 ((x) == RMU_RST_NMRST)  || \
+                                 ((x) == RMU_RST_IWDT)   || \
+                                 ((x) == RMU_RST_WWDT)   || \
+                                 ((x) == RMU_RST_LOCKUP) || \
+                                 ((x) == RMU_RST_CHIP)   || \
+                                 ((x) == RMU_RST_MCU)    || \
+                                 ((x) == RMU_RST_CPU)    || \
+                                 ((x) == RMU_RST_CFG)    || \
+                                 ((x) == RMU_RST_CFGERR)    || \
+                                 ((x) == RMU_RST_ALL))
 #define IS_RMU_STATE_CLEAR(x)	(((x) == RMU_RST_POR)    || \
                                  ((x) == RMU_RST_WAKEUP) || \
                                  ((x) == RMU_RST_BOR)    || \
@@ -212,50 +214,51 @@ typedef enum
                                  ((x) == RMU_RST_CHIP)   || \
                                  ((x) == RMU_RST_MCU)    || \
                                  ((x) == RMU_RST_CPU)    || \
-                                 ((x) == RMU_RST_CFG))
+                                 ((x) == RMU_RST_CFG)    || \
+                                 ((x) == RMU_RST_ALL))
 #define IS_RMU_PERH(x)		(((x) == RMU_PERH_GPIO)    || \
-                             ((x) == RMU_PERH_CRC)     || \
-                             ((x) == RMU_PERH_CALC)    || \
-                             ((x) == RMU_PERH_CRYPT)   || \
-                             ((x) == RMU_PERH_TRNG)    || \
-                             ((x) == RMU_PERH_PIS)     || \
-                             ((x) == RMU_PERH_CHIP)    || \
-                             ((x) == RMU_PERH_CPU)     || \
-                             ((x) == RMU_PERH_TIMER0)  || \
-                             ((x) == RMU_PERH_TIMER1)  || \
-                             ((x) == RMU_PERH_TIMER2)  || \
-                             ((x) == RMU_PERH_TIMER3)  || \
-                             ((x) == RMU_PERH_TIMER4)  || \
-                             ((x) == RMU_PERH_TIMER5)  || \
-                             ((x) == RMU_PERH_TIMER6)  || \
-                             ((x) == RMU_PERH_TIMER7)  || \
-                             ((x) == RMU_PERH_UART0)   || \
-                             ((x) == RMU_PERH_UART1)   || \
-                             ((x) == RMU_PERH_UART2)   || \
-                             ((x) == RMU_PERH_UART3)   || \
-                             ((x) == RMU_PERH_USART0)  || \
-                             ((x) == RMU_PERH_USART1)  || \
-                             ((x) == RMU_PERH_SPI0)    || \
-                             ((x) == RMU_PERH_SPI1)    || \
-                             ((x) == RMU_PERH_SPI2)    || \
-                             ((x) == RMU_PERH_I2C0)    || \
-                             ((x) == RMU_PERH_I2C1)    || \
-                             ((x) == RMU_PERH_CAN0)    || \
-                             ((x) == RMU_PERH_LPTIM0)  || \
-                             ((x) == RMU_PERH_LPUART0) || \
-                             ((x) == RMU_PERH_ADC0)    || \
-                             ((x) == RMU_PERH_ADC1)    || \
-                             ((x) == RMU_PERH_ACMP0)   || \
-                             ((x) == RMU_PERH_ACMP1)   || \
-                             ((x) == RMU_PERH_OPAMP)   || \
-                             ((x) == RMU_PERH_DAC0)    || \
-                             ((x) == RMU_PERH_WWDT)    || \
-                             ((x) == RMU_PERH_LCD)     || \
-                             ((x) == RMU_PERH_IWDT)    || \
-                             ((x) == RMU_PERH_RTC)     || \
-                             ((x) == RMU_PERH_TSENSE)    || \
-                             ((x) == RMU_PERH_BKPC)    || \
-                             ((x) == RMU_PERH_BKPRAM))
+                                 ((x) == RMU_PERH_CRC)     || \
+                                 ((x) == RMU_PERH_CALC)    || \
+                                 ((x) == RMU_PERH_CRYPT)   || \
+                                 ((x) == RMU_PERH_TRNG)    || \
+                                 ((x) == RMU_PERH_PIS)     || \
+                                 ((x) == RMU_PERH_CHIP)    || \
+                                 ((x) == RMU_PERH_CPU)     || \
+                                 ((x) == RMU_PERH_TIMER0)  || \
+                                 ((x) == RMU_PERH_TIMER1)  || \
+                                 ((x) == RMU_PERH_TIMER2)  || \
+                                 ((x) == RMU_PERH_TIMER3)  || \
+                                 ((x) == RMU_PERH_TIMER4)  || \
+                                 ((x) == RMU_PERH_TIMER5)  || \
+                                 ((x) == RMU_PERH_TIMER6)  || \
+                                 ((x) == RMU_PERH_TIMER7)  || \
+                                 ((x) == RMU_PERH_UART0)   || \
+                                 ((x) == RMU_PERH_UART1)   || \
+                                 ((x) == RMU_PERH_UART2)   || \
+                                 ((x) == RMU_PERH_UART3)   || \
+                                 ((x) == RMU_PERH_USART0)  || \
+                                 ((x) == RMU_PERH_USART1)  || \
+                                 ((x) == RMU_PERH_SPI0)    || \
+                                 ((x) == RMU_PERH_SPI1)    || \
+                                 ((x) == RMU_PERH_SPI2)    || \
+                                 ((x) == RMU_PERH_I2C0)    || \
+                                 ((x) == RMU_PERH_I2C1)    || \
+                                 ((x) == RMU_PERH_CAN0)    || \
+                                 ((x) == RMU_PERH_LPTIM0)  || \
+                                 ((x) == RMU_PERH_LPUART0) || \
+                                 ((x) == RMU_PERH_ADC0)    || \
+                                 ((x) == RMU_PERH_ADC1)    || \
+                                 ((x) == RMU_PERH_ACMP0)   || \
+                                 ((x) == RMU_PERH_ACMP1)   || \
+                                 ((x) == RMU_PERH_OPAMP)   || \
+                                 ((x) == RMU_PERH_DAC0)    || \
+                                 ((x) == RMU_PERH_WWDT)    || \
+                                 ((x) == RMU_PERH_LCD)     || \
+                                 ((x) == RMU_PERH_IWDT)    || \
+                                 ((x) == RMU_PERH_RTC)     || \
+                                 ((x) == RMU_PERH_TSENSE)    || \
+                                 ((x) == RMU_PERH_BKPC)    || \
+                                 ((x) == RMU_PERH_BKPRAM))
 /**
   * @}
   */
@@ -264,7 +267,7 @@ typedef enum
   * @{
   */
 void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state);
-flag_status_t ald_rmu_get_reset_status(rmu_state_t state);
+uint32_t ald_rmu_get_reset_status(rmu_state_t state);
 void ald_rmu_clear_reset_status(rmu_state_t state);
 void ald_rmu_reset_periperal(rmu_peripheral_t perh);
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_rtc.h

@@ -38,365 +38,335 @@ extern "C" {
 /**
   * @brief Hours format
   */
-typedef enum
-{
-    RTC_HOUR_FORMAT_24 = 0x0,	/**< 24-hours format */
-    RTC_HOUR_FORMAT_12 = 0x1,	/**< 12-hours format */
+typedef enum {
+	RTC_HOUR_FORMAT_24 = 0x0U,	/**< 24-hours format */
+	RTC_HOUR_FORMAT_12 = 0x1U,	/**< 12-hours format */
 } rtc_hour_format_t;
 
 /**
   * @brief Output mode
   */
-typedef enum
-{
-    RTC_OUTPUT_DISABLE = 0x0,	/**< Disable output */
-    RTC_OUTPUT_ALARM_A = 0x1,	/**< Output alarm_a signal */
-    RTC_OUTPUT_ALARM_B = 0x2,	/**< Output alarm_b signal */
-    RTC_OUTPUT_WAKEUP  = 0x3,	/**< Output wakeup signal */
+typedef enum {
+	RTC_OUTPUT_DISABLE = 0x0U,	/**< Disable output */
+	RTC_OUTPUT_ALARM_A = 0x1U,	/**< Output alarm_a signal */
+	RTC_OUTPUT_ALARM_B = 0x2U,	/**< Output alarm_b signal */
+	RTC_OUTPUT_WAKEUP  = 0x3U,	/**< Output wakeup signal */
 } rtc_output_select_t;
 
 /**
   * @brief Output polarity
   */
-typedef enum
-{
-    RTC_OUTPUT_POLARITY_HIGH = 0x0,	/**< Polarity is high */
-    RTC_OUTPUT_POLARITY_LOW  = 0x0,	/**< Polarity is low */
+typedef enum {
+	RTC_OUTPUT_POLARITY_HIGH = 0x0U,	/**< Polarity is high */
+	RTC_OUTPUT_POLARITY_LOW  = 0x1U,	/**< Polarity is low */
 } rtc_output_polarity_t;
 
 /**
   * @brief Initialization structure
   */
-typedef struct
-{
-    rtc_hour_format_t hour_format;		/**< Hours format */
-    uint32_t asynch_pre_div;		/**< Asynchronous predivider value */
-    uint32_t synch_pre_div;			/**< Synchronous predivider value */
-    rtc_output_select_t output;		/**< Output signal type */
-    rtc_output_polarity_t output_polarity;	/**< Output polarity */
+typedef struct {
+	rtc_hour_format_t hour_format;		/**< Hours format */
+	uint32_t asynch_pre_div;		/**< Asynchronous predivider value */
+	uint32_t synch_pre_div;			/**< Synchronous predivider value */
+	rtc_output_select_t output;		/**< Output signal type */
+	rtc_output_polarity_t output_polarity;	/**< Output polarity */
 } rtc_init_t;
 
 /**
   * @brief Source select
   */
-typedef enum
-{
-    RTC_SOURCE_LOSC        = 0x0,	/**< LOSC */
-    RTC_SOURCE_LRC         = 0x1,	/**< LRC */
-    RTC_SOURCE_HRC_DIV_1M  = 0x2,	/**< HRC divide to 1MHz */
-    RTC_SOURCE_HOSC_DIV_1M = 0x3,	/**< HOSC divide to 1MHz */
+typedef enum {
+	RTC_SOURCE_LOSC        = 0x0U,	/**< LOSC */
+	RTC_SOURCE_LRC         = 0x1U,	/**< LRC */
+	RTC_SOURCE_HRC_DIV_1M  = 0x2U,	/**< HRC divide to 1MHz */
+	RTC_SOURCE_HOSC_DIV_1M = 0x3U,	/**< HOSC divide to 1MHz */
 } rtc_source_sel_t;
 
 /**
   * @brief Time structure
   */
-typedef struct
-{
-    uint8_t hour;		/**< Hours */
-    uint8_t minute;		/**< Minutes */
-    uint8_t second;		/**< Seconds */
-    uint16_t sub_sec;	/**< Sub-seconds */
+typedef struct {
+	uint8_t hour;		/**< Hours */
+	uint8_t minute;		/**< Minutes */
+	uint8_t second;		/**< Seconds */
+	uint16_t sub_sec;	/**< Sub-seconds */
 } rtc_time_t;
 
 /**
   * @brief Date structure
   */
-typedef struct
-{
-    uint8_t week;	/**< Weeks */
-    uint8_t day;	/**< days */
-    uint8_t month;	/**< months */
-    uint8_t year;	/**< years */
+typedef struct {
+	uint8_t week;	/**< Weeks */
+	uint8_t day;	/**< days */
+	uint8_t month;	/**< months */
+	uint8_t year;	/**< years */
 } rtc_date_t;
 
 /**
   * @brief Data format
   */
-typedef enum
-{
-    RTC_FORMAT_DEC = 0,
-    RTC_FORMAT_BCD = 1,
+typedef enum {
+	RTC_FORMAT_DEC = 0U,	/**< DEC format */
+	RTC_FORMAT_BCD = 1U,	/**< BCD format */
 } rtc_format_t;
 
 /**
   * @brief Index of alarm
   */
-typedef enum
-{
-    RTC_ALARM_A = 0x0,	/**< Alarm-A */
-    RTC_ALARM_B = 0x1,	/**< Alarm-B */
+typedef enum {
+	RTC_ALARM_A = 0x0U,	/**< Alarm-A */
+	RTC_ALARM_B = 0x1U,	/**< Alarm-B */
 } rtc_alarm_idx_t;
 
 /**
   * @brief Alarm mask
   */
-typedef enum
-{
-    RTC_ALARM_MASK_NONE     = 0x0,		/**< Mask is disable */
-    RTC_ALARM_MASK_WEEK_DAY = (1U << 30),	/**< Mask week or day */
-    RTC_ALARM_MASK_HOUR     = (1U << 23),	/**< Mask hour */
-    RTC_ALARM_MASK_MINUTE   = (1U << 15),	/**< Mask minute */
-    RTC_ALARM_MASK_SECOND   = (1U << 7),	/**< Mask second */
-    RTC_ALARM_MASK_ALL      = 0x40808080,	/**< Mask all */
+typedef enum {
+	RTC_ALARM_MASK_NONE     = 0x0U,		/**< Mask is disable */
+	RTC_ALARM_MASK_WEEK_DAY = (1U << 30),	/**< Mask week or day */
+	RTC_ALARM_MASK_HOUR     = (1U << 23),	/**< Mask hour */
+	RTC_ALARM_MASK_MINUTE   = (1U << 15),	/**< Mask minute */
+	RTC_ALARM_MASK_SECOND   = (1U << 7),	/**< Mask second */
+	RTC_ALARM_MASK_ALL      = 0x40808080U,	/**< Mask all */
 } rtc_alarm_mask_t;
 
 /**
   * @brief Alarm sub-second mask
   */
-typedef enum
-{
-    RTC_ALARM_SS_MASK_NONE  = 0xF,	/**< Mask is disable */
-    RTC_ALARM_SS_MASK_14_1  = 0x1,	/**< Mask bit(1-14) */
-    RTC_ALARM_SS_MASK_14_2  = 0x2,	/**< Mask bit(2-14) */
-    RTC_ALARM_SS_MASK_14_3  = 0x3,	/**< Mask bit(3-14) */
-    RTC_ALARM_SS_MASK_14_4  = 0x4,	/**< Mask bit(4-14) */
-    RTC_ALARM_SS_MASK_14_5  = 0x5,	/**< Mask bit(5-14) */
-    RTC_ALARM_SS_MASK_14_6  = 0x6,	/**< Mask bit(6-14) */
-    RTC_ALARM_SS_MASK_14_7  = 0x7,	/**< Mask bit(7-14) */
-    RTC_ALARM_SS_MASK_14_8  = 0x8,	/**< Mask bit(8-14) */
-    RTC_ALARM_SS_MASK_14_9  = 0x9,	/**< Mask bit(9-14) */
-    RTC_ALARM_SS_MASK_14_10 = 0xA,	/**< Mask bit(10-14) */
-    RTC_ALARM_SS_MASK_14_11 = 0xB,	/**< Mask bit(11-14) */
-    RTC_ALARM_SS_MASK_14_12 = 0xC,	/**< Mask bit(12-14) */
-    RTC_ALARM_SS_MASK_14_13 = 0xD,	/**< Mask bit(13-14) */
-    RTC_ALARM_SS_MASK_14    = 0xE,	/**< Mask bit14 */
-    RTC_ALARM_SS_MASK_ALL   = 0x0,	/**< Mask bit(0-14) */
+typedef enum {
+	RTC_ALARM_SS_MASK_NONE  = 0xFU,	/**< Mask is disable */
+	RTC_ALARM_SS_MASK_14_1  = 0x1U,	/**< Mask bit(1-14) */
+	RTC_ALARM_SS_MASK_14_2  = 0x2U,	/**< Mask bit(2-14) */
+	RTC_ALARM_SS_MASK_14_3  = 0x3U,	/**< Mask bit(3-14) */
+	RTC_ALARM_SS_MASK_14_4  = 0x4U,	/**< Mask bit(4-14) */
+	RTC_ALARM_SS_MASK_14_5  = 0x5U,	/**< Mask bit(5-14) */
+	RTC_ALARM_SS_MASK_14_6  = 0x6U,	/**< Mask bit(6-14) */
+	RTC_ALARM_SS_MASK_14_7  = 0x7U,	/**< Mask bit(7-14) */
+	RTC_ALARM_SS_MASK_14_8  = 0x8U,	/**< Mask bit(8-14) */
+	RTC_ALARM_SS_MASK_14_9  = 0x9U,	/**< Mask bit(9-14) */
+	RTC_ALARM_SS_MASK_14_10 = 0xAU,	/**< Mask bit(10-14) */
+	RTC_ALARM_SS_MASK_14_11 = 0xBU,	/**< Mask bit(11-14) */
+	RTC_ALARM_SS_MASK_14_12 = 0xCU,	/**< Mask bit(12-14) */
+	RTC_ALARM_SS_MASK_14_13 = 0xDU,	/**< Mask bit(13-14) */
+	RTC_ALARM_SS_MASK_14    = 0xEU,	/**< Mask bit14 */
+	RTC_ALARM_SS_MASK_ALL   = 0x0U,	/**< Mask bit(0-14) */
 } rtc_sub_second_mask_t;
 
 /**
   * @brief Alarm select week or day */
-typedef enum
-{
-    RTC_SELECT_DAY  = 0x0,	/**< Alarm select day */
-    RTC_SELECT_WEEK = 0x1,	/**< Alarm select week */
+typedef enum {
+	RTC_SELECT_DAY  = 0x0U,	/**< Alarm select day */
+	RTC_SELECT_WEEK = 0x1U,	/**< Alarm select week */
 } rtc_week_day_sel_t;
 
 /**
   * @brief Alarm structure
   */
-typedef struct
-{
-    rtc_alarm_idx_t idx;		/**< Index of alarm */
-    rtc_time_t time;		/**< Time structure */
-    uint32_t mask;			/**< Alarm mask */
-    rtc_sub_second_mask_t ss_mask;	/**< Alarm sub-second mask */
-    rtc_week_day_sel_t sel;		/**< Select week or day */
-
-    union
-    {
-        uint8_t week;		/**< Alarm select week */
-        uint8_t day;		/**< Alarm select day */
-    };
+typedef struct {
+	rtc_alarm_idx_t idx;		/**< Index of alarm */
+	rtc_time_t time;		/**< Time structure */
+	uint32_t mask;			/**< Alarm mask */
+	rtc_sub_second_mask_t ss_mask;	/**< Alarm sub-second mask */
+	rtc_week_day_sel_t sel;		/**< Select week or day */
+
+	union {
+		uint8_t week;		/**< Alarm select week */
+		uint8_t day;		/**< Alarm select day */
+	};
 } rtc_alarm_t;
 
 /**
   * @brief Time stamp signel select
   */
-typedef enum
-{
-    RTC_TS_SIGNAL_SEL_TAMPER0 = 0,	/**< Select tamper0 */
-    RTC_TS_SIGNAL_SEL_TAMPER1 = 1,	/**< Select tamper1 */
+typedef enum {
+	RTC_TS_SIGNAL_SEL_TAMPER0 = 0U,	/**< Select tamper0 */
+	RTC_TS_SIGNAL_SEL_TAMPER1 = 1U,	/**< Select tamper1 */
 } rtc_ts_signal_sel_t;
 
 /**
   * @brief Time stamp trigger style
   */
-typedef enum
-{
-    RTC_TS_RISING_EDGE  = 0,	/**< Rising edge */
-    RTC_TS_FALLING_EDGE = 1,	/**< Falling edge */
+typedef enum {
+	RTC_TS_RISING_EDGE  = 0U,	/**< Rising edge */
+	RTC_TS_FALLING_EDGE = 1U,	/**< Falling edge */
 } rtc_ts_trigger_style_t;
 
 /**
   * @brief Index of tamper
   */
-typedef enum
-{
-    RTC_TAMPER_0 = 0,	/**< Tamper0 */
-    RTC_TAMPER_1 = 1,	/**< Tamper1 */
+typedef enum {
+	RTC_TAMPER_0 = 0U,	/**< Tamper0 */
+	RTC_TAMPER_1 = 1U,	/**< Tamper1 */
 } rtc_tamper_idx_t;
 
 /**
   * @brief Tamper trigger type
   */
-typedef enum
-{
-    RTC_TAMPER_TRIGGER_LOW  = 0,	/**< High trigger */
-    RTC_TAMPER_TRIGGER_HIGH = 1,	/**< Low trigger */
+typedef enum {
+	RTC_TAMPER_TRIGGER_LOW  = 0U,	/**< High trigger */
+	RTC_TAMPER_TRIGGER_HIGH = 1U,	/**< Low trigger */
 } rtc_tamper_trigger_t;
 
 /**
   * @brief Tamper sampling frequency
   */
-typedef enum
-{
-    RTC_TAMPER_SAMPLING_FREQ_32768 = 0,	/**< RTCCLK / 32768 */
-    RTC_TAMPER_SAMPLING_FREQ_16384 = 1,	/**< RTCCLK / 16384 */
-    RTC_TAMPER_SAMPLING_FREQ_8192  = 2,	/**< RTCCLK / 8192 */
-    RTC_TAMPER_SAMPLING_FREQ_4096  = 3,	/**< RTCCLK / 4096 */
-    RTC_TAMPER_SAMPLING_FREQ_2048  = 4,	/**< RTCCLK / 2048 */
-    RTC_TAMPER_SAMPLING_FREQ_1024  = 5,	/**< RTCCLK / 1024 */
-    RTC_TAMPER_SAMPLING_FREQ_512   = 6,	/**< RTCCLK / 512 */
-    RTC_TAMPER_SAMPLING_FREQ_256   = 7,	/**< RTCCLK / 256 */
+typedef enum {
+	RTC_TAMPER_SAMPLING_FREQ_32768 = 0U,	/**< RTCCLK / 32768 */
+	RTC_TAMPER_SAMPLING_FREQ_16384 = 1U,	/**< RTCCLK / 16384 */
+	RTC_TAMPER_SAMPLING_FREQ_8192  = 2U,	/**< RTCCLK / 8192 */
+	RTC_TAMPER_SAMPLING_FREQ_4096  = 3U,	/**< RTCCLK / 4096 */
+	RTC_TAMPER_SAMPLING_FREQ_2048  = 4U,	/**< RTCCLK / 2048 */
+	RTC_TAMPER_SAMPLING_FREQ_1024  = 5U,	/**< RTCCLK / 1024 */
+	RTC_TAMPER_SAMPLING_FREQ_512   = 6U,	/**< RTCCLK / 512 */
+	RTC_TAMPER_SAMPLING_FREQ_256   = 7U,	/**< RTCCLK / 256 */
 } rtc_tamper_sampling_freq_t;
 
 /**
   * @brief Tamper filter time
   */
-typedef enum
-{
-    RTC_TAMPER_DURATION_1 = 0,	/**< Duration 1 sampling */
-    RTC_TAMPER_DURATION_2 = 1,	/**< Duration 2 sampling */
-    RTC_TAMPER_DURATION_4 = 2,	/**< Duration 4 sampling */
-    RTC_TAMPER_DURATION_8 = 3,	/**< Duration 8 sampling */
+typedef enum {
+	RTC_TAMPER_DURATION_1 = 0U,	/**< Duration 1 sampling */
+	RTC_TAMPER_DURATION_2 = 1U,	/**< Duration 2 sampling */
+	RTC_TAMPER_DURATION_4 = 2U,	/**< Duration 4 sampling */
+	RTC_TAMPER_DURATION_8 = 3U,	/**< Duration 8 sampling */
 } rtc_tamper_duration_t;
 
 /**
   * @brief Tamper structure
   */
-typedef struct
-{
-    rtc_tamper_idx_t idx;			/**< Index of tamper */
-    rtc_tamper_trigger_t trig;		/**< Trigger type */
-    rtc_tamper_sampling_freq_t freq;	/**< Sampling frequency */
-    rtc_tamper_duration_t dur;		/**< Filter time */
-    type_func_t ts;				/**< Enable/Disable trigger time stamp event */
+typedef struct {
+	rtc_tamper_idx_t idx;			/**< Index of tamper */
+	rtc_tamper_trigger_t trig;		/**< Trigger type */
+	rtc_tamper_sampling_freq_t freq;	/**< Sampling frequency */
+	rtc_tamper_duration_t dur;		/**< Filter time */
+	type_func_t ts;				/**< Enable/Disable trigger time stamp event */
 } rtc_tamper_t;
 
 /**
   * @brief Wake-up clock
   */
-typedef enum
-{
-    RTC_WAKEUP_CLOCK_DIV_16   = 0,	/**< RTCCLK / 16 */
-    RTC_WAKEUP_CLOCK_DIV_8    = 1,	/**< RTCCLK / 8 */
-    RTC_WAKEUP_CLOCK_DIV_4    = 2,	/**< RTCCLK / 4 */
-    RTC_WAKEUP_CLOCK_DIV_2    = 3,	/**< RTCCLK / 2 */
-    RTC_WAKEUP_CLOCK_1HZ      = 4,	/**< 1Hz */
-    RTC_WAKEUP_CLOCK_1HZ_PULS = 6,	/**< 1Hz and WUT + 65536 */
+typedef enum {
+	RTC_WAKEUP_CLOCK_DIV_16   = 0U,	/**< RTCCLK / 16 */
+	RTC_WAKEUP_CLOCK_DIV_8    = 1U,	/**< RTCCLK / 8 */
+	RTC_WAKEUP_CLOCK_DIV_4    = 2U,	/**< RTCCLK / 4 */
+	RTC_WAKEUP_CLOCK_DIV_2    = 3U,	/**< RTCCLK / 2 */
+	RTC_WAKEUP_CLOCK_1HZ      = 4U,	/**< 1Hz */
+	RTC_WAKEUP_CLOCK_1HZ_PULS = 6U,	/**< 1Hz and WUT + 65536 */
 } rtc_wakeup_clock_t;
 
 /**
   * @brief RTC clock output type
   */
-typedef enum
-{
-    RTC_CLOCK_OUTPUT_32768 = 0,	/**< 32768Hz */
-    RTC_CLOCK_OUTPUT_1024  = 1,	/**< 1024Hz */
-    RTC_CLOCK_OUTPUT_32    = 2,	/**< 32Hz */
-    RTC_CLOCK_OUTPUT_1     = 3,	/**< 1Hz */
-    RTC_CLOCK_OUTPUT_CAL_1 = 4,	/**< 1Hz after calibration */
-    RTC_CLOCK_OUTPUT_EXA_1 = 5,	/**< Exact 1Hz */
+typedef enum {
+	RTC_CLOCK_OUTPUT_32768 = 0U,	/**< 32768Hz */
+	RTC_CLOCK_OUTPUT_1024  = 1U,	/**< 1024Hz */
+	RTC_CLOCK_OUTPUT_32    = 2U,	/**< 32Hz */
+	RTC_CLOCK_OUTPUT_1     = 3U,	/**< 1Hz */
+	RTC_CLOCK_OUTPUT_CAL_1 = 4U,	/**< 1Hz after calibration */
+	RTC_CLOCK_OUTPUT_EXA_1 = 5U,	/**< Exact 1Hz */
 } rtc_clock_output_t;
 
 /**
   * @ Calibration frequency
   */
-typedef enum
-{
-    RTC_CALI_FREQ_10_SEC = 0,	/**< Calibrate every 10 seconds */
-    RTC_CALI_FREQ_20_SEC = 1,	/**< Calibrate every 20 seconds */
-    RTC_CALI_FREQ_1_MIN  = 2,	/**< Calibrate every 1 minute */
-    RTC_CALI_FREQ_2_MIN  = 3,	/**< Calibrate every 2 minutes */
-    RTC_CALI_FREQ_5_MIN  = 4,	/**< Calibrate every 5 minutes */
-    RTC_CALI_FREQ_10_MIN = 5,	/**< Calibrate every 10 minutes */
-    RTC_CALI_FREQ_20_MIN = 6,	/**< Calibrate every 20 minutes */
-    RTC_CALI_FREQ_1_SEC  = 7,	/**< Calibrate every 1 second */
+typedef enum {
+	RTC_CALI_FREQ_10_SEC = 0U,	/**< Calibrate every 10 seconds */
+	RTC_CALI_FREQ_20_SEC = 1U,	/**< Calibrate every 20 seconds */
+	RTC_CALI_FREQ_1_MIN  = 2U,	/**< Calibrate every 1 minute */
+	RTC_CALI_FREQ_2_MIN  = 3U,	/**< Calibrate every 2 minutes */
+	RTC_CALI_FREQ_5_MIN  = 4U,	/**< Calibrate every 5 minutes */
+	RTC_CALI_FREQ_10_MIN = 5U,	/**< Calibrate every 10 minutes */
+	RTC_CALI_FREQ_20_MIN = 6U,	/**< Calibrate every 20 minutes */
+	RTC_CALI_FREQ_1_SEC  = 7U,	/**< Calibrate every 1 second */
 } rtc_cali_freq_t;
 
 /**
   * @brief Temperature compensate type
   */
-typedef enum
-{
-    RTC_CALI_TC_NONE          = 0,	/**< Temperature compensate disable */
-    RTC_CALI_TC_AUTO_BY_HW    = 1,	/**< Temperature compensate by hardware */
-    RTC_CALI_TC_AUTO_BY_SF    = 2,	/**< Temperature compensate by software */
-    RTC_CALI_TC_AUTO_BY_HW_SF = 3,	/**< Temperature compensate by hardware, trigger by software */
+typedef enum {
+	RTC_CALI_TC_NONE          = 0U,	/**< Temperature compensate disable */
+	RTC_CALI_TC_AUTO_BY_HW    = 1U,	/**< Temperature compensate by hardware */
+	RTC_CALI_TC_AUTO_BY_SF    = 2U,	/**< Temperature compensate by software */
+	RTC_CALI_TC_AUTO_BY_HW_SF = 3U,	/**< Temperature compensate by hardware, trigger by software */
 } rtc_cali_tc_t;
 
 /**
   * @ Calculate frequency
   */
-typedef enum
-{
-    RTC_CALI_CALC_FREQ_10_SEC = 0,	/**< Calculate every 10 seconds */
-    RTC_CALI_CALC_FREQ_20_SEC = 1,	/**< Calculate every 20 seconds */
-    RTC_CALI_CALC_FREQ_1_MIN  = 2,	/**< Calculate every 1 minute */
-    RTC_CALI_CALC_FREQ_2_MIN  = 3,	/**< Calculate every 2 minutes */
-    RTC_CALI_CALC_FREQ_5_MIN  = 4,	/**< Calculate every 5 minutes */
-    RTC_CALI_CALC_FREQ_10_MIN = 5,	/**< Calculate every 10 minutes */
-    RTC_CALI_CALC_FREQ_20_MIN = 6,	/**< Calculate every 20 minutes */
-    RTC_CALI_CALC_FREQ_1_HOUR = 7,	/**< Calculate every 1 hour */
+typedef enum {
+	RTC_CALI_CALC_FREQ_10_SEC = 0U,	/**< Calculate every 10 seconds */
+	RTC_CALI_CALC_FREQ_20_SEC = 1U,	/**< Calculate every 20 seconds */
+	RTC_CALI_CALC_FREQ_1_MIN  = 2U,	/**< Calculate every 1 minute */
+	RTC_CALI_CALC_FREQ_2_MIN  = 3U,	/**< Calculate every 2 minutes */
+	RTC_CALI_CALC_FREQ_5_MIN  = 4U,	/**< Calculate every 5 minutes */
+	RTC_CALI_CALC_FREQ_10_MIN = 5U,	/**< Calculate every 10 minutes */
+	RTC_CALI_CALC_FREQ_20_MIN = 6U,	/**< Calculate every 20 minutes */
+	RTC_CALI_CALC_FREQ_1_HOUR = 7U,	/**< Calculate every 1 hour */
 } rtc_cali_calc_freq_t;
 
 /**
   * @brief Calibration algorithm
   */
-typedef enum
-{
-    RTC_CALI_CALC_4 = 0,	/**< 4-polynomial */
-    RTC_CALI_CALC_2 = 1,	/**< 2-parabola */
+typedef enum {
+	RTC_CALI_CALC_4 = 0U,	/**< 4-polynomial */
+	RTC_CALI_CALC_2 = 1U,	/**< 2-parabola */
 } rtc_cali_calc_t;
 
 /**
   * @brief Calibration structure
   */
-typedef struct
-{
-    rtc_cali_freq_t cali_freq;	/**< calibrate frequency */
-    rtc_cali_tc_t tc;		/**< Temperature compensate type */
-    rtc_cali_calc_freq_t calc_freq;	/**< Calculate frequency */
-    rtc_cali_calc_t calc;		/**< algorithm */
-    type_func_t acc;		/**< Enable/Disable decimal accumulate */
+typedef struct {
+	rtc_cali_freq_t cali_freq;	/**< calibrate frequency */
+	rtc_cali_tc_t tc;		/**< Temperature compensate type */
+	rtc_cali_calc_freq_t calc_freq;	/**< Calculate frequency */
+	rtc_cali_calc_t calc;		/**< algorithm */
+	type_func_t acc;		/**< Enable/Disable decimal accumulate */
 } rtc_cali_t;
 
 /**
   * @brief Interrupt type
   */
-typedef enum
-{
-    RTC_IT_SEC  = (1U << 0),	/**< Second */
-    RTC_IT_MIN  = (1U << 1),	/**< Minute */
-    RTC_IT_HR   = (1U << 2),	/**< Hour */
-    RTC_IT_DAY  = (1U << 3),	/**< Day */
-    RTC_IT_MON  = (1U << 4),	/**< Month */
-    RTC_IT_YR   = (1U << 5),	/**< Year */
-    RTC_IT_ALMA = (1U << 8),	/**< Alarm-A */
-    RTC_IT_ALMB = (1U << 9),	/**< Alarm-B */
-    RTC_IT_TS   = (1U << 10),	/**< Time stamp */
-    RTC_IT_TSOV = (1U << 11),	/**< Time stamp overflow */
-    RTC_IT_TP0  = (1U << 12),	/**< Tamper-0 */
-    RTC_IT_TP1  = (1U << 13),	/**< Tamper-1 */
-    RTC_IT_RSC  = (1U << 16),	/**< Synchronous complete */
-    RTC_IT_SFC  = (1U << 17),	/**< Shift complete */
-    RTC_IT_WU   = (1U << 18),	/**< Wake-up */
-    RTC_IT_TCC  = (1U << 24),	/**< Temperature compensate complete */
-    RTC_IT_TCE  = (1U << 25),	/**< Temperature compensate error */
+typedef enum {
+	RTC_IT_SEC  = (1U << 0),	/**< Second */
+	RTC_IT_MIN  = (1U << 1),	/**< Minute */
+	RTC_IT_HR   = (1U << 2),	/**< Hour */
+	RTC_IT_DAY  = (1U << 3),	/**< Day */
+	RTC_IT_MON  = (1U << 4),	/**< Month */
+	RTC_IT_YR   = (1U << 5),	/**< Year */
+	RTC_IT_ALMA = (1U << 8),	/**< Alarm-A */
+	RTC_IT_ALMB = (1U << 9),	/**< Alarm-B */
+	RTC_IT_TS   = (1U << 10),	/**< Time stamp */
+	RTC_IT_TSOV = (1U << 11),	/**< Time stamp overflow */
+	RTC_IT_TP0  = (1U << 12),	/**< Tamper-0 */
+	RTC_IT_TP1  = (1U << 13),	/**< Tamper-1 */
+	RTC_IT_RSC  = (1U << 16),	/**< Synchronous complete */
+	RTC_IT_SFC  = (1U << 17),	/**< Shift complete */
+	RTC_IT_WU   = (1U << 18),	/**< Wake-up */
+	RTC_IT_TCC  = (1U << 24),	/**< Temperature compensate complete */
+	RTC_IT_TCE  = (1U << 25),	/**< Temperature compensate error */
 } rtc_it_t;
 
 /**
   * @brief Interrupt flag
   */
-typedef enum
-{
-    RTC_IF_SEC  = (1U << 0),	/**< Second */
-    RTC_IF_MIN  = (1U << 1),	/**< Minute */
-    RTC_IF_HR   = (1U << 2),	/**< Hour */
-    RTC_IF_DAY  = (1U << 3),	/**< Day */
-    RTC_IF_MON  = (1U << 4),	/**< Month */
-    RTC_IF_YR   = (1U << 5),	/**< Year */
-    RTC_IF_ALMA = (1U << 8),	/**< Alarm-A */
-    RTC_IF_ALMB = (1U << 9),	/**< Alarm-B */
-    RTC_IF_TS   = (1U << 10),	/**< Time stamp */
-    RTC_IF_TSOV = (1U << 11),	/**< Time stamp overflow */
-    RTC_IF_TP0  = (1U << 12),	/**< Tamper-0 */
-    RTC_IF_TP1  = (1U << 13),	/**< Tamper-1 */
-    RTC_IF_RSC  = (1U << 16),	/**< Synchronous complete */
-    RTC_IF_SFC  = (1U << 17),	/**< Shift complete */
-    RTC_IF_WU   = (1U << 18),	/**< Wake-up */
-    RTC_IF_TCC  = (1U << 24),	/**< Temperature compensate complete */
-    RTC_IF_TCE  = (1U << 25),	/**< Temperature compensate error */
+typedef enum {
+	RTC_IF_SEC  = (1U << 0),	/**< Second */
+	RTC_IF_MIN  = (1U << 1),	/**< Minute */
+	RTC_IF_HR   = (1U << 2),	/**< Hour */
+	RTC_IF_DAY  = (1U << 3),	/**< Day */
+	RTC_IF_MON  = (1U << 4),	/**< Month */
+	RTC_IF_YR   = (1U << 5),	/**< Year */
+	RTC_IF_ALMA = (1U << 8),	/**< Alarm-A */
+	RTC_IF_ALMB = (1U << 9),	/**< Alarm-B */
+	RTC_IF_TS   = (1U << 10),	/**< Time stamp */
+	RTC_IF_TSOV = (1U << 11),	/**< Time stamp overflow */
+	RTC_IF_TP0  = (1U << 12),	/**< Tamper-0 */
+	RTC_IF_TP1  = (1U << 13),	/**< Tamper-1 */
+	RTC_IF_RSC  = (1U << 16),	/**< Synchronous complete */
+	RTC_IF_SFC  = (1U << 17),	/**< Shift complete */
+	RTC_IF_WU   = (1U << 18),	/**< Wake-up */
+	RTC_IF_TCC  = (1U << 24),	/**< Temperature compensate complete */
+	RTC_IF_TCE  = (1U << 25),	/**< Temperature compensate error */
 } rtc_flag_t;
 /**
   * @}
@@ -405,44 +375,44 @@ typedef enum
 /** @defgroup RTC_Public_Macro RTC Public Macros
   * @{
   */
-#define RTC_UNLOCK()		(WRITE_REG(RTC->WPR, 0x55AAAA55))
-#define RTC_LOCK()		(WRITE_REG(RTC->WPR, 0x0))
+#define RTC_UNLOCK()		(WRITE_REG(RTC->WPR, 0x55AAAA55U))
+#define RTC_LOCK()		(WRITE_REG(RTC->WPR, 0x0U))
 #define RTC_BY_PASS_ENABLE()			\
-    do {						\
-        RTC_UNLOCK();				\
-        SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
-        RTC_LOCK();				\
-    } while (0)
+do {						\
+	RTC_UNLOCK();				\
+	SET_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
+	RTC_LOCK();				\
+} while (0)
 #define RTC_BY_PASS_DISABLE()			\
-    do {						\
-        RTC_UNLOCK();				\
-        CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
-        RTC_LOCK();				\
-    } while (0)
+do {						\
+	RTC_UNLOCK();				\
+	CLEAR_BIT(RTC->CON, RTC_CON_SHDBP_MSK);	\
+	RTC_LOCK();				\
+} while (0)
 #define RTC_SUMMER_TIME_ENABLE()		\
-    do {						\
-        RTC_UNLOCK();				\
-        SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
-        RTC_LOCK();				\
-    } while (0)
+do {						\
+	RTC_UNLOCK();				\
+	SET_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
+	RTC_LOCK();				\
+} while (0)
 #define RTC_SUMMER_TIME_DISABLE()		\
-    do {						\
-        RTC_UNLOCK();				\
-        CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
-        RTC_LOCK();				\
-    } while (0)
+do {						\
+	RTC_UNLOCK();				\
+	CLEAR_BIT(RTC->CON, RTC_CON_ADD1H_MSK);	\
+	RTC_LOCK();				\
+} while (0)
 #define RTC_WINTER_TIME_ENABLE()		\
-    do {						\
-        RTC_UNLOCK();				\
-        SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
-        RTC_LOCK();				\
-    } while (0)
+do {						\
+	RTC_UNLOCK();				\
+	SET_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
+	RTC_LOCK();				\
+} while (0)
 #define RTC_WINTER_TIME_DISABLE()		\
-    do {						\
-        RTC_UNLOCK();				\
-        CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
-        RTC_LOCK();				\
-    } while (0)
+do {						\
+	RTC_UNLOCK();				\
+	CLEAR_BIT(RTC->CON, RTC_CON_SUB1H_MSK);	\
+	RTC_LOCK();				\
+} while (0)
 /**
  * @}
  */
@@ -450,10 +420,10 @@ typedef enum
 /** @defgroup CAN_Private_Macros CAN Private Macros
   * @{
   */
-#define RTC_CALI_UNLOCK()	(WRITE_REG(RTC->CALWPR, 0x699655AA))
-#define RTC_CALI_LOCK()		(WRITE_REG(RTC->CALWPR, 0x0))
-#define ALARM_MASK_ALL		0x40808080
-#define RTC_TIMEOUT_VALUE	100
+#define RTC_CALI_UNLOCK()	(WRITE_REG(RTC->CALWPR, 0x699655AAU))
+#define RTC_CALI_LOCK()		(WRITE_REG(RTC->CALWPR, 0x0U))
+#define ALARM_MASK_ALL		0x40808080U
+#define RTC_TIMEOUT_VALUE	100U
 
 #define IS_SHIFT_SUB_SS(x)	((x) < (1U << 15))
 #define IS_RTC_HOUR_FORMAT(x)	(((x) == RTC_HOUR_FORMAT_24) || \
@@ -463,15 +433,15 @@ typedef enum
                                  ((x) == RTC_OUTPUT_ALARM_B) || \
                                  ((x) == RTC_OUTPUT_WAKEUP))
 #define IS_RTC_OUTPUT_POLARITY(x)	(((x) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                     ((x) == RTC_OUTPUT_POLARITY_LOW))
+                                         ((x) == RTC_OUTPUT_POLARITY_LOW))
 #define IS_RTC_SOURCE_SEL(x)	(((x) == RTC_SOURCE_LOSC)        || \
                                  ((x) == RTC_SOURCE_LRC)         || \
                                  ((x) == RTC_SOURCE_HRC_DIV_1M ) || \
                                  ((x) == RTC_SOURCE_HOSC_DIV_1M))
 #define IS_RTC_ALARM(x)		(((x) == RTC_ALARM_A) || \
-                             ((x) == RTC_ALARM_B))
+                                 ((x) == RTC_ALARM_B))
 #define IS_RTC_ALARM_SEL(x)	(((x) == RTC_SELECT_DAY) || \
-                             ((x) == RTC_SELECT_WEEK))
+                                 ((x) == RTC_SELECT_WEEK))
 #define IS_RTC_ALARM_MASK(x)	(((x) == RTC_ALARM_MASK_NONE)     || \
                                  ((x) == RTC_ALARM_MASK_WEEK_DAY) || \
                                  ((x) == RTC_ALARM_MASK_HOUR)     || \
@@ -495,27 +465,27 @@ typedef enum
                                  ((x) == RTC_ALARM_SS_MASK_14)    || \
                                  ((x) == RTC_ALARM_SS_MASK_ALL))
 #define IS_RTC_TS_SIGNAL(x)	(((x) == RTC_TS_SIGNAL_SEL_TAMPER0) || \
-                             ((x) == RTC_TS_SIGNAL_SEL_TAMPER1))
+                                 ((x) == RTC_TS_SIGNAL_SEL_TAMPER1))
 #define IS_RTC_TS_STYLE(x)	(((x) == RTC_TS_RISING_EDGE) || \
-                             ((x) == RTC_TS_FALLING_EDGE))
+                                 ((x) == RTC_TS_FALLING_EDGE))
 #define IS_RTC_FORMAT(x)	(((x) == RTC_FORMAT_DEC) || \
-                             ((x) == RTC_FORMAT_BCD))
+                                 ((x) == RTC_FORMAT_BCD))
 #define IS_RTC_TAMPER(x)	(((x) == RTC_TAMPER_0) || \
-                             ((x) == RTC_TAMPER_1))
+                                 ((x) == RTC_TAMPER_1))
 #define IS_RTC_TAMPER_TRIGGER(x)	(((x) == RTC_TAMPER_TRIGGER_LOW) || \
-                                     ((x) == RTC_TAMPER_TRIGGER_HIGH))
+                                         ((x) == RTC_TAMPER_TRIGGER_HIGH))
 #define IS_RTC_TAMPER_SAMPLING_FREQ(x)	(((x) == RTC_TAMPER_SAMPLING_FREQ_32768) || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_8192)  || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_4096)  || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_2048)  || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_1024)  || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_512)   || \
-        ((x) == RTC_TAMPER_SAMPLING_FREQ_256))
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_16384) || \
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_8192)  || \
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_4096)  || \
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_2048)  || \
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_1024)  || \
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_512)   || \
+                                         ((x) == RTC_TAMPER_SAMPLING_FREQ_256))
 #define IS_RTC_TAMPER_DURATION(x)	(((x) == RTC_TAMPER_DURATION_1) || \
-                                     ((x) == RTC_TAMPER_DURATION_2) || \
-                                     ((x) == RTC_TAMPER_DURATION_4) || \
-                                     ((x) == RTC_TAMPER_DURATION_8))
+                                         ((x) == RTC_TAMPER_DURATION_2) || \
+                                         ((x) == RTC_TAMPER_DURATION_4) || \
+                                         ((x) == RTC_TAMPER_DURATION_8))
 #define IS_RTC_WAKEUP_CLOCK(x)	(((x) == RTC_WAKEUP_CLOCK_DIV_16) || \
                                  ((x) == RTC_WAKEUP_CLOCK_DIV_8)  || \
                                  ((x) == RTC_WAKEUP_CLOCK_DIV_4)  || \
@@ -529,61 +499,61 @@ typedef enum
                                  ((x) == RTC_CLOCK_OUTPUT_CAL_1) || \
                                  ((x) == RTC_CLOCK_OUTPUT_EXA_1))
 #define IS_RTC_CALI_FREQ(x)	(((x) == RTC_CALI_FREQ_10_SEC) || \
-                             ((x) == RTC_CALI_FREQ_20_SEC) || \
-                             ((x) == RTC_CALI_FREQ_1_MIN)  || \
-                             ((x) == RTC_CALI_FREQ_2_MIN)  || \
-                             ((x) == RTC_CALI_FREQ_5_MIN)  || \
-                             ((x) == RTC_CALI_FREQ_10_MIN) || \
-                             ((x) == RTC_CALI_FREQ_20_MIN) || \
-                             ((x) == RTC_CALI_FREQ_1_SEC))
+                                 ((x) == RTC_CALI_FREQ_20_SEC) || \
+                                 ((x) == RTC_CALI_FREQ_1_MIN)  || \
+                                 ((x) == RTC_CALI_FREQ_2_MIN)  || \
+                                 ((x) == RTC_CALI_FREQ_5_MIN)  || \
+                                 ((x) == RTC_CALI_FREQ_10_MIN) || \
+                                 ((x) == RTC_CALI_FREQ_20_MIN) || \
+                                 ((x) == RTC_CALI_FREQ_1_SEC))
 #define IS_RTC_CALI_TC(x)	(((x) == RTC_CALI_TC_NONE)       || \
-                             ((x) == RTC_CALI_TC_AUTO_BY_HW) || \
-                             ((x) == RTC_CALI_TC_AUTO_BY_SF) || \
-                             ((x) == RTC_CALI_TC_AUTO_BY_HW_SF))
+                                 ((x) == RTC_CALI_TC_AUTO_BY_HW) || \
+                                 ((x) == RTC_CALI_TC_AUTO_BY_SF) || \
+                                 ((x) == RTC_CALI_TC_AUTO_BY_HW_SF))
 #define IS_RTC_CALC_FREQ(x)	(((x) == RTC_CALI_CALC_FREQ_10_SEC) || \
-                             ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \
-                             ((x) == RTC_CALI_CALC_FREQ_1_MIN)  || \
-                             ((x) == RTC_CALI_CALC_FREQ_2_MIN)  || \
-                             ((x) == RTC_CALI_CALC_FREQ_5_MIN)  || \
-                             ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \
-                             ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \
-                             ((x) == RTC_CALI_CALC_FREQ_1_HOUR))
+                                 ((x) == RTC_CALI_CALC_FREQ_20_SEC) || \
+                                 ((x) == RTC_CALI_CALC_FREQ_1_MIN)  || \
+                                 ((x) == RTC_CALI_CALC_FREQ_2_MIN)  || \
+                                 ((x) == RTC_CALI_CALC_FREQ_5_MIN)  || \
+                                 ((x) == RTC_CALI_CALC_FREQ_10_MIN) || \
+                                 ((x) == RTC_CALI_CALC_FREQ_20_MIN) || \
+                                 ((x) == RTC_CALI_CALC_FREQ_1_HOUR))
 #define IS_RTC_CALI_CALC(x)	(((x) == RTC_CALI_CALC_4) || \
-                             ((x) == RTC_CALI_CALC_2))
+                                 ((x) == RTC_CALI_CALC_2))
 #define IS_RTC_IT(x)		(((x) == RTC_IT_SEC)  || \
-                             ((x) == RTC_IT_MIN)  || \
-                             ((x) == RTC_IT_HR)   || \
-                             ((x) == RTC_IT_DAY)  || \
-                             ((x) == RTC_IT_MON)  || \
-                             ((x) == RTC_IT_YR)   || \
-                             ((x) == RTC_IT_ALMA) || \
-                             ((x) == RTC_IT_ALMB) || \
-                             ((x) == RTC_IT_TS)   || \
-                             ((x) == RTC_IT_TSOV) || \
-                             ((x) == RTC_IT_TP0)  || \
-                             ((x) == RTC_IT_TP1)  || \
-                             ((x) == RTC_IT_RSC)  || \
-                             ((x) == RTC_IT_SFC)  || \
-                             ((x) == RTC_IT_WU)   || \
-                             ((x) == RTC_IT_TCC)  || \
-                             ((x) == RTC_IT_TCE))
+                                 ((x) == RTC_IT_MIN)  || \
+                                 ((x) == RTC_IT_HR)   || \
+                                 ((x) == RTC_IT_DAY)  || \
+                                 ((x) == RTC_IT_MON)  || \
+                                 ((x) == RTC_IT_YR)   || \
+                                 ((x) == RTC_IT_ALMA) || \
+                                 ((x) == RTC_IT_ALMB) || \
+                                 ((x) == RTC_IT_TS)   || \
+                                 ((x) == RTC_IT_TSOV) || \
+                                 ((x) == RTC_IT_TP0)  || \
+                                 ((x) == RTC_IT_TP1)  || \
+                                 ((x) == RTC_IT_RSC)  || \
+                                 ((x) == RTC_IT_SFC)  || \
+                                 ((x) == RTC_IT_WU)   || \
+                                 ((x) == RTC_IT_TCC)  || \
+                                 ((x) == RTC_IT_TCE))
 #define IS_RTC_IF(x)		(((x) == RTC_IF_SEC)  || \
-                             ((x) == RTC_IF_MIN)  || \
-                             ((x) == RTC_IF_HR)   || \
-                             ((x) == RTC_IF_DAY)  || \
-                             ((x) == RTC_IF_MON)  || \
-                             ((x) == RTC_IF_YR)   || \
-                             ((x) == RTC_IF_ALMA) || \
-                             ((x) == RTC_IF_ALMB) || \
-                             ((x) == RTC_IF_TS)   || \
-                             ((x) == RTC_IF_TSOV) || \
-                             ((x) == RTC_IF_TP0)  || \
-                             ((x) == RTC_IF_TP1)  || \
-                             ((x) == RTC_IF_RSC)  || \
-                             ((x) == RTC_IF_SFC)  || \
-                             ((x) == RTC_IF_WU)   || \
-                             ((x) == RTC_IF_TCC)  || \
-                             ((x) == RTC_IF_TCE))
+                                 ((x) == RTC_IF_MIN)  || \
+                                 ((x) == RTC_IF_HR)   || \
+                                 ((x) == RTC_IF_DAY)  || \
+                                 ((x) == RTC_IF_MON)  || \
+                                 ((x) == RTC_IF_YR)   || \
+                                 ((x) == RTC_IF_ALMA) || \
+                                 ((x) == RTC_IF_ALMB) || \
+                                 ((x) == RTC_IF_TS)   || \
+                                 ((x) == RTC_IF_TSOV) || \
+                                 ((x) == RTC_IF_TP0)  || \
+                                 ((x) == RTC_IF_TP1)  || \
+                                 ((x) == RTC_IF_RSC)  || \
+                                 ((x) == RTC_IF_SFC)  || \
+                                 ((x) == RTC_IF_WU)   || \
+                                 ((x) == RTC_IF_TCC)  || \
+                                 ((x) == RTC_IF_TCE))
 #define IS_RTC_SECOND(x)	((x) < 60)
 #define IS_RTC_MINUTE(x)	((x) < 60)
 #define IS_RTC_HOUR(x)		((x) < 24)

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_smartcard.h

@@ -18,7 +18,7 @@
 #define __ALD_SMARTCARD_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -41,52 +41,50 @@ extern "C" {
 /**
   * @brief SMARTCARD error codes
   */
-typedef enum
-{
-    SMARTCARD_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-    SMARTCARD_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-    SMARTCARD_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-    SMARTCARD_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-    SMARTCARD_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-    SMARTCARD_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
+typedef enum {
+	SMARTCARD_ERROR_NONE = ((uint32_t)0x00U),	/**< No error */
+	SMARTCARD_ERROR_PE   = ((uint32_t)0x01U),	/**< Parity error */
+	SMARTCARD_ERROR_NE   = ((uint32_t)0x02U),	/**< Noise error */
+	SMARTCARD_ERROR_FE   = ((uint32_t)0x04U),	/**< frame error */
+	SMARTCARD_ERROR_ORE  = ((uint32_t)0x08U),	/**< Overrun error */
+	SMARTCARD_ERROR_DMA  = ((uint32_t)0x10U),	/**< DMA transfer error */
 } smartcard_error_t;
 
 /**
   * @brief SMARTCARD Prescaler
   */
-typedef enum
-{
-    SMARTCARD_PRESCALER_SYSCLK_DIV2  = ((uint32_t)0x1),	/**< SYSCLK divided by 2 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV4  = ((uint32_t)0x2),	/**< SYSCLK divided by 4 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV6  = ((uint32_t)0x3),	/**< SYSCLK divided by 6 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV8  = ((uint32_t)0x4),	/**< SYSCLK divided by 8 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5),	/**< SYSCLK divided by 10 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6),	/**< SYSCLK divided by 12 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7),	/**< SYSCLK divided by 14 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8),	/**< SYSCLK divided by 16 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9),	/**< SYSCLK divided by 18 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xA),	/**< SYSCLK divided by 20 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xB),	/**< SYSCLK divided by 22 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xC),	/**< SYSCLK divided by 24 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xD),	/**< SYSCLK divided by 26 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xE),	/**< SYSCLK divided by 28 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xF),	/**< SYSCLK divided by 30 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10),	/**< SYSCLK divided by 32 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11),	/**< SYSCLK divided by 34 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12),	/**< SYSCLK divided by 36 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13),	/**< SYSCLK divided by 38 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14),	/**< SYSCLK divided by 40 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15),	/**< SYSCLK divided by 42 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16),	/**< SYSCLK divided by 44 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17),	/**< SYSCLK divided by 46 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18),	/**< SYSCLK divided by 48 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19),	/**< SYSCLK divided by 50 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1A),	/**< SYSCLK divided by 52 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1B),	/**< SYSCLK divided by 54 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1C),	/**< SYSCLK divided by 56 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1D),	/**< SYSCLK divided by 58 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1E),	/**< SYSCLK divided by 60 */
-    SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1F),	/**< SYSCLK divided by 62 */
+typedef enum {
+	SMARTCARD_PRESCALER_SYSCLK_DIV2  = ((uint32_t)0x1U),	/**< SYSCLK divided by 2 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV4  = ((uint32_t)0x2U),	/**< SYSCLK divided by 4 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV6  = ((uint32_t)0x3U),	/**< SYSCLK divided by 6 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV8  = ((uint32_t)0x4U),	/**< SYSCLK divided by 8 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV10 = ((uint32_t)0x5U),	/**< SYSCLK divided by 10 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV12 = ((uint32_t)0x6U),	/**< SYSCLK divided by 12 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV14 = ((uint32_t)0x7U),	/**< SYSCLK divided by 14 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV16 = ((uint32_t)0x8U),	/**< SYSCLK divided by 16 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV18 = ((uint32_t)0x9U),	/**< SYSCLK divided by 18 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV20 = ((uint32_t)0xAU),	/**< SYSCLK divided by 20 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV22 = ((uint32_t)0xBU),	/**< SYSCLK divided by 22 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV24 = ((uint32_t)0xCU),	/**< SYSCLK divided by 24 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV26 = ((uint32_t)0xDU),	/**< SYSCLK divided by 26 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV28 = ((uint32_t)0xEU),	/**< SYSCLK divided by 28 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV30 = ((uint32_t)0xFU),	/**< SYSCLK divided by 30 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV32 = ((uint32_t)0x10U),	/**< SYSCLK divided by 32 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV34 = ((uint32_t)0x11U),	/**< SYSCLK divided by 34 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV36 = ((uint32_t)0x12U),	/**< SYSCLK divided by 36 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV38 = ((uint32_t)0x13U),	/**< SYSCLK divided by 38 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV40 = ((uint32_t)0x14U),	/**< SYSCLK divided by 40 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV42 = ((uint32_t)0x15U),	/**< SYSCLK divided by 42 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV44 = ((uint32_t)0x16U),	/**< SYSCLK divided by 44 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV46 = ((uint32_t)0x17U),	/**< SYSCLK divided by 46 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV48 = ((uint32_t)0x18U),	/**< SYSCLK divided by 48 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV50 = ((uint32_t)0x19U),	/**< SYSCLK divided by 50 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV52 = ((uint32_t)0x1AU),	/**< SYSCLK divided by 52 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV54 = ((uint32_t)0x1BU),	/**< SYSCLK divided by 54 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV56 = ((uint32_t)0x1CU),	/**< SYSCLK divided by 56 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV58 = ((uint32_t)0x1DU),	/**< SYSCLK divided by 58 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV60 = ((uint32_t)0x1EU),	/**< SYSCLK divided by 60 */
+	SMARTCARD_PRESCALER_SYSCLK_DIV62 = ((uint32_t)0x1FU),	/**< SYSCLK divided by 62 */
 } smartcard_prescaler_t;
 
 /**
@@ -100,69 +98,66 @@ typedef enum
 /**
   * @brief SMARTCARD Init Structure definition
   */
-typedef struct
-{
-    uint32_t baud;			/**< This member configures the SmartCard communication baud rate. */
-    usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
-    usart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted. */
-    usart_parity_t parity;		/**< Specifies the parity mode.
+typedef struct {
+	uint32_t baud;			/**< This member configures the SmartCard communication baud rate. */
+	usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
+	usart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted. */
+	usart_parity_t parity;		/**< Specifies the parity mode.
 						@note When parity is enabled, the computed parity is inserted
                                                       at the MSB position of the transmitted data (9th bit when
                                                       the word length is set to 9 data bits; 8th bit when the
                                                       word length is set to 8 data bits).*/
-    usart_mode_t mode;		/**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
-    usart_cpol_t polarity;		/**< Specifies the steady state of the serial clock. */
-    usart_cpha_t phase;		/**< Specifies the clock transition on which the bit capture is made.*/
-    usart_last_bit_t last_bit;	/**< Specifies whether the clock pulse corresponding to the last transmitted
+	usart_mode_t mode;		/**< Specifies whether the Receive or Transmit mode is enabled or disabled. */
+	usart_cpol_t polarity;		/**< Specifies the steady state of the serial clock. */
+	usart_cpha_t phase;		/**< Specifies the clock transition on which the bit capture is made.*/
+	usart_last_bit_t last_bit;	/**< Specifies whether the clock pulse corresponding to the last transmitted
 					     data bit (MSB) has to be output on the SCLK pin in synchronous mode.
                                              This parameter can be a value of @ref usart_last_bit_t */
-    smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
+	smartcard_prescaler_t prescaler;/**< Specifies the SmartCard Prescaler value used for dividing the system clock
 					     to provide the smartcard clock. The value given in the register (5 significant bits)
 					     is multiplied by 2 to give the division factor of the source clock frequency. */
-    uint32_t guard_time;		/**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
-    type_func_t nack;		/**< Specifies the SmartCard NACK Transmission state. */
+	uint32_t guard_time;		/**< Specifies the SmartCard Guard Time value in terms of number of baud clocks */
+	type_func_t nack;		/**< Specifies the SmartCard NACK Transmission state. */
 } smartcard_init_t;
 
 /**
   * @brief ALD state structures definition
   */
-typedef enum
-{
-    SMARTCARD_STATE_RESET      = 0x00,	/**< Peripheral is not yet Initialized */
-    SMARTCARD_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-    SMARTCARD_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-    SMARTCARD_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-    SMARTCARD_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-    SMARTCARD_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission and Reception process is ongoing */
-    SMARTCARD_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-    SMARTCARD_STATE_ERROR      = 0x04	/**< Error */
+typedef enum {
+	SMARTCARD_STATE_RESET      = 0x00U,	/**< Peripheral is not yet Initialized */
+	SMARTCARD_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
+	SMARTCARD_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
+	SMARTCARD_STATE_BUSY_TX    = 0x11U,	/**< Data Transmission process is ongoing */
+	SMARTCARD_STATE_BUSY_RX    = 0x21U,	/**< Data Reception process is ongoing */
+	SMARTCARD_STATE_BUSY_TX_RX = 0x31U,	/**< Data Transmission and Reception process is ongoing */
+	SMARTCARD_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
+	SMARTCARD_STATE_ERROR      = 0x04U,	/**< Error */
 } smartcard_state_t;
 
 
 /**
   * @brief  SMARTCARD handle structure definition
   */
-typedef struct smartcard_handle_s
-{
-    USART_TypeDef *perh;		/**< USART registers base address */
-    smartcard_init_t init;		/**< SmartCard communication parameters */
-    uint8_t *tx_buf;		/**< Pointer to SmartCard Tx transfer Buffer */
-    uint16_t tx_size;		/**< SmartCard Tx Transfer size */
-    uint16_t tx_count;		/**< SmartCard Tx Transfer Counter */
-    uint8_t *rx_buf;		/**< Pointer to SmartCard Rx transfer Buffer */
-    uint16_t rx_size;		/**< SmartCard Rx Transfer size */
-    uint16_t rx_count;		/**< SmartCard Rx Transfer Counter */
+typedef struct smartcard_handle_s {
+	USART_TypeDef *perh;		/**< USART registers base address */
+	smartcard_init_t init;		/**< SmartCard communication parameters */
+	uint8_t *tx_buf;		/**< Pointer to SmartCard Tx transfer Buffer */
+	uint16_t tx_size;		/**< SmartCard Tx Transfer size */
+	uint16_t tx_count;		/**< SmartCard Tx Transfer Counter */
+	uint8_t *rx_buf;		/**< Pointer to SmartCard Rx transfer Buffer */
+	uint16_t rx_size;		/**< SmartCard Rx Transfer size */
+	uint16_t rx_count;		/**< SmartCard Rx Transfer Counter */
 #ifdef ALD_DMA
-    dma_handle_t hdmatx;		/**< SmartCard Tx DMA Handle parameters */
-    dma_handle_t hdmarx;		/**< SmartCard Rx DMA Handle parameters */
+	dma_handle_t hdmatx;		/**< SmartCard Tx DMA Handle parameters */
+	dma_handle_t hdmarx;		/**< SmartCard Rx DMA Handle parameters */
 #endif
-    lock_state_t lock;		/**< Locking object */
-    smartcard_state_t state;	/**< SmartCard communication state */
-    uint32_t  err_code;		/**< SmartCard Error code */
+	lock_state_t lock;		/**< Locking object */
+	smartcard_state_t state;	/**< SmartCard communication state */
+	uint32_t  err_code;		/**< SmartCard Error code */
 
-    void (*tx_cplt_cbk)(struct smartcard_handle_s *arg);	/**< Tx completed callback */
-    void (*rx_cplt_cbk)(struct smartcard_handle_s *arg);	/**< Rx completed callback */
-    void (*error_cbk)(struct smartcard_handle_s *arg);	/**< error callback */
+	void (*tx_cplt_cbk)(struct smartcard_handle_s *arg);	/**< Tx completed callback */
+	void (*rx_cplt_cbk)(struct smartcard_handle_s *arg);	/**< Rx completed callback */
+	void (*error_cbk)(struct smartcard_handle_s *arg);	/**< error callback */
 } smartcard_handle_t;
 
 /**
@@ -214,7 +209,7 @@ typedef struct smartcard_handle_s
   */
 
 #define IS_SMARTCARD_PRESCALER(x)   (((x) >= SMARTCARD_PRESCALER_SYSCLK_DIV2) && \
-                                     ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
+				     ((x) <= SMARTCARD_PRESCALER_SYSCLK_DIV62))
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_spi.h

@@ -18,7 +18,7 @@
 #define __ALD_SPI_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -39,97 +39,88 @@ extern "C" {
 /**
   * @brief clock phase
   */
-typedef enum
-{
-    SPI_CPHA_FIRST  = 0,	/**< Transiting data in the first edge */
-    SPI_CPHA_SECOND = 1,	/**< Transiting data in the seconde edge */
+typedef enum {
+	SPI_CPHA_FIRST  = 0U,	/**< Transiting data in the first edge */
+	SPI_CPHA_SECOND = 1U,	/**< Transiting data in the seconde edge */
 } spi_cpha_t;
 
 /**
   * @brief clock polarity
   */
-typedef enum
-{
-    SPI_CPOL_LOW  = 0,	/**< Polarity hold low when spi-bus is idle */
-    SPI_CPOL_HIGH = 1,	/**< Polarity hold high when spi-bus is idle */
+typedef enum {
+	SPI_CPOL_LOW  = 0U,	/**< Polarity hold low when spi-bus is idle */
+	SPI_CPOL_HIGH = 1U,	/**< Polarity hold high when spi-bus is idle */
 } spi_cpol_t;
 
 /**
   * @brief master selection
   */
-typedef enum
-{
-    SPI_MODE_SLAVER = 0,	/**< Slave mode */
-    SPI_MODE_MASTER = 1,	/**< Master mode */
+typedef enum {
+	SPI_MODE_SLAVER = 0U,	/**< Slave mode */
+	SPI_MODE_MASTER = 1U,	/**< Master mode */
 } spi_mode_t;
 
 /**
   * @brief baud rate control
   */
-typedef enum
-{
-    SPI_BAUD_2   = 0,	/**< fpclk/2 */
-    SPI_BAUD_4   = 1,	/**< fpclk/4 */
-    SPI_BAUD_8   = 2,	/**< fpclk/8 */
-    SPI_BAUD_16  = 3,	/**< fpclk/16 */
-    SPI_BAUD_32  = 4,	/**< fpclk/32 */
-    SPI_BAUD_64  = 5,	/**< fpclk/64 */
-    SPI_BAUD_128 = 6,	/**< fpclk/128 */
-    SPI_BAUD_256 = 7,	/**< fpclk/256 */
+typedef enum {
+	SPI_BAUD_2   = 0U,	/**< fpclk/2 */
+	SPI_BAUD_4   = 1U,	/**< fpclk/4 */
+	SPI_BAUD_8   = 2U,	/**< fpclk/8 */
+	SPI_BAUD_16  = 3U,	/**< fpclk/16 */
+	SPI_BAUD_32  = 4U,	/**< fpclk/32 */
+	SPI_BAUD_64  = 5U,	/**< fpclk/64 */
+	SPI_BAUD_128 = 6U,	/**< fpclk/128 */
+	SPI_BAUD_256 = 7U,	/**< fpclk/256 */
 } spi_baud_t;
 
 /**
   * @brief frame format
   */
-typedef enum
-{
-    SPI_FIRSTBIT_MSB = 0,	/**< MSB transmitted first */
-    SPI_FIRSTBIT_LSB = 1,	/**< LSB transmitted first */
+typedef enum {
+	SPI_FIRSTBIT_MSB = 0U,	/**< MSB transmitted first */
+	SPI_FIRSTBIT_LSB = 1U,	/**< LSB transmitted first */
 } spi_firstbit_t;
 
 /**
   * @brief data frame format
   */
-typedef enum
-{
-    SPI_DATA_SIZE_8  = 0,	/**< 8-bit data frame format is selected for transmission/reception */
-    SPI_DATA_SIZE_16 = 1,	/**< 16-bit data frame format is selected for transmission/reception */
+typedef enum {
+	SPI_DATA_SIZE_8  = 0U,	/**< 8-bit data frame format is selected for transmission/reception */
+	SPI_DATA_SIZE_16 = 1U,	/**< 16-bit data frame format is selected for transmission/reception */
 } spi_datasize_t;
 
 /**
   * @brief interrupt control
   */
-typedef enum
-{
-    SPI_IT_ERR   = (1U << 5),	/**< error interrupt */
-    SPI_IT_RXBNE = (1U << 6),	/**< rx buffer not empty interrupt */
-    SPI_IT_TXBE  = (1U << 7),	/**< tx buffer empty interrupt */
+typedef enum {
+	SPI_IT_ERR   = (1U << 5),	/**< error interrupt */
+	SPI_IT_RXBNE = (1U << 6),	/**< rx buffer not empty interrupt */
+	SPI_IT_TXBE  = (1U << 7),	/**< tx buffer empty interrupt */
 } spi_it_t;
 
 /**
   * @brief interrupt flag
   */
-typedef enum
-{
-    SPI_IF_RXBNE  = (1U << 0),	/**< receive buffer not empty */
-    SPI_IF_TXBE   = (1U << 1),	/**< transmit buffer empty */
-    SPI_IF_CRCERR = (1U << 4),	/**< crc error flag */
-    SPI_IF_MODF   = (1U << 5),	/**< mode fault */
-    SPI_IF_OVE    = (1U << 6),	/**< overrun flag */
-    SPI_IF_BUSY   = (1U << 7),	/**< busy flag */
+typedef enum {
+	SPI_IF_RXBNE  = (1U << 0),	/**< receive buffer not empty */
+	SPI_IF_TXBE   = (1U << 1),	/**< transmit buffer empty */
+	SPI_IF_CRCERR = (1U << 4),	/**< crc error flag */
+	SPI_IF_MODF   = (1U << 5),	/**< mode fault */
+	SPI_IF_OVE    = (1U << 6),	/**< overrun flag */
+	SPI_IF_BUSY   = (1U << 7),	/**< busy flag */
 } spi_flag_t;
 
 /**
   * @brief SPI error status
   */
-typedef enum
-{
-    SPI_ERROR_NONE = 0,	/**< none */
-    SPI_ERROR_MODF = 1,	/**< mode fault */
-    SPI_ERROR_CRC  = 2,	/**< crc error */
-    SPI_ERROR_OVE  = 4,	/**< overrun error */
-    SPI_ERROR_DMA  = 8,	/**< dma error  */
-    SPI_ERROR_FLAG = 0x10,	/**< interrupt flag error */
+typedef enum {
+	SPI_ERROR_NONE = 0U,	/**< none */
+	SPI_ERROR_MODF = 1U,	/**< mode fault */
+	SPI_ERROR_CRC  = 2U,	/**< crc error */
+	SPI_ERROR_OVE  = 4U,	/**< overrun error */
+	SPI_ERROR_DMA  = 8U,	/**< dma error  */
+	SPI_ERROR_FLAG = 0x10U,	/**< interrupt flag error */
 } spi_error_t;
 
 
@@ -137,104 +128,97 @@ typedef enum
 /**
   * @brief SPI state structures definition
   */
-typedef enum
-{
-    SPI_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-    SPI_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-    SPI_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-    SPI_STATE_BUSY_TX    = 0x11,	/**< transmit is ongoing */
-    SPI_STATE_BUSY_RX    = 0x21,	/**< receive is ongoing */
-    SPI_STATE_BUSY_TX_RX = 0x31,	/**< transmit and receive are ongoing */
-    SPI_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-    SPI_STATE_ERROR      = 0x04,	/**< Error */
+typedef enum {
+	SPI_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
+	SPI_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
+	SPI_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
+	SPI_STATE_BUSY_TX    = 0x11U,	/**< transmit is ongoing */
+	SPI_STATE_BUSY_RX    = 0x21U,	/**< receive is ongoing */
+	SPI_STATE_BUSY_TX_RX = 0x31U,	/**< transmit and receive are ongoing */
+	SPI_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
+	SPI_STATE_ERROR      = 0x04U,	/**< Error */
 } spi_state_t;
 
 /**
   * @brief SPI status definition
   */
-typedef enum
-{
-    SPI_STATUS_RXBNE   = (1U << 0),		/**< Receive not empty status */
-    SPI_STATUS_TXBE    = (1U << 1),		/**< Transmit empty status */
-    SPI_STATUS_CRCERR  = (1U << 4),		/**< CRC error status */
-    SPI_STATUS_MODEERR = (1U << 5),		/**< Mode error status */
-    SPI_STATUS_OVERR   = (1U << 6),		/**< Overflow status */
-    SPI_STATUS_BUSY    = (1U << 7),		/**< Busy status */
+typedef enum {
+	SPI_STATUS_RXBNE   = (1U << 0),		/**< Receive not empty status */
+	SPI_STATUS_TXBE    = (1U << 1),		/**< Transmit empty status */
+	SPI_STATUS_CRCERR  = (1U << 4),		/**< CRC error status */
+	SPI_STATUS_MODEERR = (1U << 5),		/**< Mode error status */
+	SPI_STATUS_OVERR   = (1U << 6),		/**< Overflow status */
+	SPI_STATUS_BUSY    = (1U << 7),		/**< Busy status */
 
 } spi_status_t;
 
 /**
   * @brief SPI direction definition
   */
-typedef enum
-{
-    SPI_DIRECTION_2LINES        = 0,	/**< 2 lines */
-    SPI_DIRECTION_2LINES_RXONLY = 1,	/**< 2 lines only rx */
-    SPI_DIRECTION_1LINE         = 2,	/**< 1 line */
-    SPI_DIRECTION_1LINE_RX      = 3,	/**< 1 line only rx */
+typedef enum {
+	SPI_DIRECTION_2LINES        = 0U,	/**< 2 lines */
+	SPI_DIRECTION_2LINES_RXONLY = 1U,	/**< 2 lines only rx */
+	SPI_DIRECTION_1LINE         = 2U,	/**< 1 line */
+	SPI_DIRECTION_1LINE_RX      = 3U,	/**< 1 line only rx */
 } spi_direction_t;
 
 /**
   * @brief SPI dma request definition
   */
-typedef enum
-{
-    SPI_DMA_REQ_TX = 0,	/**< TX dma request */
-    SPI_DMA_REQ_RX = 1,	/**< RX dma request */
+typedef enum {
+	SPI_DMA_REQ_TX = 0U,	/**< TX dma request */
+	SPI_DMA_REQ_RX = 1U,	/**< RX dma request */
 } spi_dma_req_t;
 
 /**
   * @brief SPI TXE/RXNE status definition
   */
-typedef enum
-{
-    SPI_SR_TXBE       = 0,	/**< SR.TXE set */
-    SPI_SR_RXBNE      = 1,	/**< SR.RXNE set */
-    SPI_SR_TXBE_RXBNE = 2,	/**< SR.TXE and SR.RXNE set */
+typedef enum {
+	SPI_SR_TXBE       = 0U,	/**< SR.TXE set */
+	SPI_SR_RXBNE      = 1U,	/**< SR.RXNE set */
+	SPI_SR_TXBE_RXBNE = 2U,	/**< SR.TXE and SR.RXNE set */
 } spi_sr_status_t;
 
 /**
   * @brief SPI init structure definition
   */
-typedef struct
-{
-    spi_mode_t mode;		/**< SPI mode */
-    spi_direction_t dir;		/**< SPI direction */
-    spi_datasize_t data_size;	/**< SPI data size */
-    spi_baud_t baud;			/**< SPI baudrate prescaler */
-    spi_cpha_t phase;		/**< SPI clock phase */
-    spi_cpol_t polarity;		/**< SPI clock polarity */
-    spi_firstbit_t first_bit;	/**< SPI first bit */
-    type_func_t ss_en;		/**< SPI ssm enable or disable */
-    type_func_t crc_calc;		/**< SPI crc calculation */
-    uint16_t crc_poly;		/**< SPI crc polynomial */
+typedef struct {
+	spi_mode_t mode;		/**< SPI mode */
+	spi_direction_t dir;		/**< SPI direction */
+	spi_datasize_t data_size;	/**< SPI data size */
+	spi_baud_t baud;			/**< SPI baudrate prescaler */
+	spi_cpha_t phase;		/**< SPI clock phase */
+	spi_cpol_t polarity;		/**< SPI clock polarity */
+	spi_firstbit_t first_bit;	/**< SPI first bit */
+	type_func_t ss_en;		/**< SPI ssm enable or disable */
+	type_func_t crc_calc;		/**< SPI crc calculation */
+	uint16_t crc_poly;		/**< SPI crc polynomial */
 } spi_init_t;
 
 /**
   * @brief  SPI handle structure definition
   */
-typedef struct spi_handle_s
-{
-    SPI_TypeDef *perh;	/**< SPI registers base address */
-    spi_init_t init;	/**< SPI communication parameters */
-    uint8_t *tx_buf;	/**< Pointer to SPI Tx transfer buffer */
-    uint16_t tx_size;	/**< SPI Tx transfer size */
-    uint16_t tx_count;	/**< SPI Tx transfer counter */
-    uint8_t *rx_buf;	/**< Pointer to SPI Rx transfer buffer */
-    uint16_t rx_size;	/**< SPI Rx Transfer size */
-    uint16_t rx_count;	/**< SPI Rx Transfer Counter */
+typedef struct spi_handle_s {
+	SPI_TypeDef *perh;	/**< SPI registers base address */
+	spi_init_t init;	/**< SPI communication parameters */
+	uint8_t *tx_buf;	/**< Pointer to SPI Tx transfer buffer */
+	uint16_t tx_size;	/**< SPI Tx transfer size */
+	uint16_t tx_count;	/**< SPI Tx transfer counter */
+	uint8_t *rx_buf;	/**< Pointer to SPI Rx transfer buffer */
+	uint16_t rx_size;	/**< SPI Rx Transfer size */
+	uint16_t rx_count;	/**< SPI Rx Transfer Counter */
 #ifdef ALD_DMA
-    dma_handle_t hdmatx;	/**< SPI Tx DMA handle parameters */
-    dma_handle_t hdmarx;	/**< SPI Rx DMA handle parameters */
+	dma_handle_t hdmatx;	/**< SPI Tx DMA handle parameters */
+	dma_handle_t hdmarx;	/**< SPI Rx DMA handle parameters */
 #endif
-    lock_state_t lock;	/**< Locking object */
-    spi_state_t state;	/**< SPI communication state */
-    uint32_t err_code;	/**< SPI error code */
-
-    void (*tx_cplt_cbk)(struct spi_handle_s *arg);		/**< Tx completed callback */
-    void (*rx_cplt_cbk)(struct spi_handle_s *arg);		/**< Rx completed callback */
-    void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg);	/**< Tx & Rx completed callback */
-    void (*err_cbk)(struct spi_handle_s *arg);		/**< error callback */
+	lock_state_t lock;	/**< Locking object */
+	spi_state_t state;	/**< SPI communication state */
+	uint32_t err_code;	/**< SPI error code */
+
+	void (*tx_cplt_cbk)(struct spi_handle_s *arg);		/**< Tx completed callback */
+	void (*rx_cplt_cbk)(struct spi_handle_s *arg);		/**< Rx completed callback */
+	void (*tx_rx_cplt_cbk)(struct spi_handle_s *arg);	/**< Tx & Rx completed callback */
+	void (*err_cbk)(struct spi_handle_s *arg);		/**< error callback */
 } spi_handle_t;
 /**
   * @}
@@ -247,10 +231,10 @@ typedef struct spi_handle_s
 #define SPI_ENABLE(x)			((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
 #define SPI_DISABLE(x)			((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
 #define SPI_CRC_RESET(x)					\
-    do {								\
-        CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
-        SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
-    } while (0)
+do {								\
+	CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
+	SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK);		\
+} while (0)
 #define SPI_CRCNEXT_ENABLE(x)	(SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
 #define SPI_CRCNEXT_DISABLE(x)	(CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
 #define SPI_RXONLY_ENABLE(x)	(SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
@@ -268,9 +252,12 @@ typedef struct spi_handle_s
 /** @defgroup SPI_Private_Macros   SPI Private Macros
   * @{
   */
-#define IS_SPI(x)	(((x) == SPI0) || \
-                     ((x) == SPI1) || \
-                     ((x) == SPI2))
+#if defined(ES32F065x) || defined(ES32F033x)
+#define IS_SPI(x)	(((x) == SPI0) || ((x) == SPI1))
+#endif
+#if defined(ES32F093x)
+#define IS_SPI(x)	(((x) == SPI0) || ((x) == SPI1) || ((x) == SPI2))
+#endif
 #define IS_SPI_CPHA(x)	(((x) == SPI_CPHA_FIRST) || \
                          ((x) == SPI_CPHA_SECOND))
 #define IS_SPI_CPOL(x)	(((x) == SPI_CPOL_LOW) || \
@@ -286,20 +273,22 @@ typedef struct spi_handle_s
                          ((x) == SPI_BAUD_128) || \
                          ((x) == SPI_BAUD_256))
 #define IS_SPI_DATASIZE(x)	(((x) == SPI_DATA_SIZE_8) || \
-                             ((x) == SPI_DATA_SIZE_16))
+                                 ((x) == SPI_DATA_SIZE_16))
+#define IS_SPI_FIRSTBIT(x)	(((x) == SPI_FIRSTBIT_MSB) || \
+                                 ((x) == SPI_FIRSTBIT_LSB))
 #define IS_SPI_BIDOE(x)		(((x) == SPI_BID_RX) || \
-                             ((x) == SPI_BID_TX))
+                                 ((x) == SPI_BID_TX))
 #define IS_SPI_BIDMODE(x)	(((x) == SPI_BIDMODE_DUAL) || \
-                             ((x) == SPI_BIDMODE_SOLE))
+                                 ((x) == SPI_BIDMODE_SOLE))
 #define IS_SPI_DIRECTION(x)	(((x) == SPI_DIRECTION_2LINES)         || \
-                             ((x) == SPI_DIRECTION_2LINES_RXONLY)  || \
-                             ((x) == SPI_DIRECTION_1LINE)          || \
-                             ((x) == SPI_DIRECTION_1LINE_RX))
+                                 ((x) == SPI_DIRECTION_2LINES_RXONLY)  || \
+                                 ((x) == SPI_DIRECTION_1LINE)          || \
+				 ((x) == SPI_DIRECTION_1LINE_RX))
 #define IS_SPI_DMA_REQ(x)	(((x) == SPI_DMA_REQ_TX) || \
-                             ((x) == SPI_DMA_REQ_RX))
+                                 ((x) == SPI_DMA_REQ_RX))
 #define IS_SPI_SR_STATUS(x)	(((x) == SPI_SR_TXBE)  || \
-                             ((x) == SPI_SR_RXBNE) || \
-                             ((x) == SPI_SR_TXBE_RXBNE))
+                                 ((x) == SPI_SR_RXBNE) || \
+                                 ((x) == SPI_SR_TXBE_RXBNE))
 #define IS_SPI_IT(x)	(((x) == SPI_IT_ERR)   || \
                          ((x) == SPI_IT_RXBNE) || \
                          ((x) == SPI_IT_TXBE))
@@ -310,11 +299,11 @@ typedef struct spi_handle_s
                          ((x) == SPI_IF_OVE)    || \
                          ((x) == SPI_IF_BUSY))
 #define IS_SPI_STATUS(x)	(((x) == SPI_STATUS_RXBNE) || \
-                             ((x) == SPI_STATUS_TXBE)  || \
-                             ((x) == SPI_STATUS_CRCERR) || \
-                             ((x) == SPI_STATUS_MODEERR) || \
-                             ((x) == SPI_STATUS_OVERR)   || \
-                             ((x) == SPI_STATUS_BUSY))
+				 ((x) == SPI_STATUS_TXBE)  || \
+				 ((x) == SPI_STATUS_CRCERR) || \
+				 ((x) == SPI_STATUS_MODEERR) || \
+				 ((x) == SPI_STATUS_OVERR)   || \
+				 ((x) == SPI_STATUS_BUSY))
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_syscfg.h

@@ -18,7 +18,7 @@
 #define __ALD_SYSCFG_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -36,33 +36,33 @@ extern "C" {
 /** @defgroup SYSCFG_Public_Macros SYSCFG Public Macros
   * @{
   */
-#define SYSCFG_LOCK()  		WRITE_REG(SYSCFG->PROT, 0x0)
-#define SYSCFG_UNLOCK()		WRITE_REG(SYSCFG->PROT, 0x55AA6996)
+#define SYSCFG_LOCK()  		WRITE_REG(SYSCFG->PROT, 0x0U)
+#define SYSCFG_UNLOCK()		WRITE_REG(SYSCFG->PROT, 0x55AA6996U)
 #define GET_SYSCFG_LOCK()	READ_BIT(SYSCFG->PROT, SYSCFG_PROT_PROT_MSK)
 
 #define BOOT_FROM_BOOT_ROM()					\
-    do {								\
-        SYSCFG_UNLOCK();					\
-        SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);	\
-        CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);	\
-        SYSCFG_LOCK();						\
-    } while (0)
+do {								\
+	SYSCFG_UNLOCK();					\
+	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);	\
+	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);	\
+	SYSCFG_LOCK();						\
+} while (0)
 
 #define BOOT_FROM_BOOT_FLASH()					\
-    do {								\
-        SYSCFG_UNLOCK();					\
-        CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);	\
-        SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);	\
-        SYSCFG_LOCK();						\
-    } while (0)
+do {								\
+	SYSCFG_UNLOCK();					\
+	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);	\
+	SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);	\
+	SYSCFG_LOCK();						\
+} while (0)
 
 #define BOOT_FROM_FLASH()					\
-    do {								\
-        SYSCFG_UNLOCK();					\
-        CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);	\
-        CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);	\
-        SYSCFG_LOCK();						\
-    } while (0)
+do {								\
+	SYSCFG_UNLOCK();					\
+	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BRRMPEN_MSK);	\
+	CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BFRMPEN_MSK);	\
+	SYSCFG_LOCK();						\
+} while (0)
 /**
   * @}
   */
@@ -73,20 +73,18 @@ extern "C" {
   */
 __STATIC_INLINE__ void ald_vtor_config(uint32_t offset, type_func_t status)
 {
-    SYSCFG_UNLOCK();
-
-    if (status)
-    {
-        MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3F));
-        SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
-    }
-    else
-    {
-        CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
-    }
-
-    SYSCFG_LOCK();
-    return;
+	SYSCFG_UNLOCK();
+
+	if (status) {
+		MODIFY_REG(SYSCFG->VTOR, SYSCFG_VTOR_VTO_MSK, (offset & ~0x3FU));
+		SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
+	}
+	else {
+		CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_VTOEN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_trng.h

@@ -38,93 +38,85 @@ extern "C" {
 /**
   * @brief Data width
   */
-typedef enum
-{
-    TRNG_DSEL_1B  = 0x0,	/**< 1-bit */
-    TRNG_DSEL_8B  = 0x1,	/**< 8-bit */
-    TRNG_DSEL_16B = 0x2,	/**< 16-bit */
-    TRNG_DSEL_32B = 0x3,	/**< 32-bit */
+typedef enum {
+	TRNG_DSEL_1B  = 0x0U,	/**< 1-bit */
+	TRNG_DSEL_8B  = 0x1U,	/**< 8-bit */
+	TRNG_DSEL_16B = 0x2U,	/**< 16-bit */
+	TRNG_DSEL_32B = 0x3U,	/**< 32-bit */
 } trng_data_width_t;
 
 /**
   * @brief seed type
   */
-typedef enum
-{
-    TRNG_SEED_TYPE_0    = 0x0,	/**< Using 0 as seed */
-    TRNG_SEED_TYPE_1    = 0x1,	/**< Using 1 as seed */
-    TRNG_SEED_TYPE_LAST = 0x2,	/**< Using last seed */
-    TRNG_SEED_TYPE_SEED = 0x3,	/**< Using value of register */
+typedef enum {
+	TRNG_SEED_TYPE_0    = 0x0U,	/**< Using 0 as seed */
+	TRNG_SEED_TYPE_1    = 0x1U,	/**< Using 1 as seed */
+	TRNG_SEED_TYPE_LAST = 0x2U,	/**< Using last seed */
+	TRNG_SEED_TYPE_SEED = 0x3U,	/**< Using value of register */
 } trng_seed_type_t;
 
 /**
   * @brief TRNG init structure definition
   */
-typedef struct
-{
-    trng_data_width_t data_width;	/**< The width of data */
-    trng_seed_type_t seed_type;	/**< The seed type */
-    uint32_t seed;			/**< The value of seed */
-    uint16_t t_start;		/**< T(start) = T(hclk) * (t_start + 1), T(start) > 1ms */
-    uint8_t adjc;			/**< Adjust parameter */
-    type_func_t posten;		/**< Data back handle function  */
+typedef struct {
+	trng_data_width_t data_width;	/**< The width of data */
+	trng_seed_type_t seed_type;	/**< The seed type */
+	uint32_t seed;			/**< The value of seed */
+	uint16_t t_start;		/**< T(start) = T(trng) * 2 ^ (t_start + 1), T(start) > 1ms */
+	uint8_t adjc;			/**< Adjust parameter */
+	type_func_t posten;		/**< Data back handle function  */
 } trng_init_t;
 
 /**
   * @brief TRNG state structures definition
   */
-typedef enum
-{
-    TRNG_STATE_RESET = 0x0,	/**< Peripheral is not initialized */
-    TRNG_STATE_READY = 0x1,	/**< Peripheral Initialized and ready for use */
-    TRNG_STATE_BUSY  = 0x2,	/**< An internal process is ongoing */
-    TRNG_STATE_ERROR = 0x4,	/**< Error */
+typedef enum {
+	TRNG_STATE_RESET = 0x0U,	/**< Peripheral is not initialized */
+	TRNG_STATE_READY = 0x1U,	/**< Peripheral Initialized and ready for use */
+	TRNG_STATE_BUSY  = 0x2U,	/**< An internal process is ongoing */
+	TRNG_STATE_ERROR = 0x4U,	/**< Error */
 } trng_state_t;
 
 /**
   * @brief State type
   */
-typedef enum
-{
-    TRNG_STATUS_START = (1U << 0),	/**< Start state */
-    TRNG_STATUS_DAVLD = (1U << 1),	/**< Data valid state */
-    TRNG_STATUS_SERR  = (1U << 2),	/**< Error state */
+typedef enum {
+	TRNG_STATUS_START = (1U << 0),	/**< Start state */
+	TRNG_STATUS_DAVLD = (1U << 1),	/**< Data valid state */
+	TRNG_STATUS_SERR  = (1U << 2),	/**< Error state */
 } trng_status_t;
 
 /**
   * @brief Interrupt type
   */
-typedef enum
-{
-    TRNG_IT_START = (1U << 0),	/**< Start */
-    TRNG_IT_DAVLD = (1U << 1),	/**< Data valid */
-    TRNG_IT_SERR  = (1U << 2),	/**< Error */
+typedef enum {
+	TRNG_IT_START = (1U << 0),	/**< Start */
+	TRNG_IT_DAVLD = (1U << 1),	/**< Data valid */
+	TRNG_IT_SERR  = (1U << 2),	/**< Error */
 } trng_it_t;
 
 /**
   * @brief Interrupt flag type
   */
-typedef enum
-{
-    TRNG_IF_START = (1U << 0),	/**< Start */
-    TRNG_IF_DAVLD = (1U << 1),	/**< Data valid */
-    TRNG_IF_SERR  = (1U << 2),	/**< Error */
+typedef enum {
+	TRNG_IF_START = (1U << 0),	/**< Start */
+	TRNG_IF_DAVLD = (1U << 1),	/**< Data valid */
+	TRNG_IF_SERR  = (1U << 2),	/**< Error */
 } trng_flag_t;
 
 /**
   * @brief  TRNG Handle Structure definition
   */
-typedef struct trng_handle_s
-{
-    TRNG_TypeDef *perh;	/**< Register base address */
-    trng_init_t init;	/**< TRNG required parameters */
-    uint32_t data;		/**< result data */
-    lock_state_t lock; 	/**< Locking object */
-    trng_state_t state;	/**< TRNG operation state */
-
-    void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */
-    void (*err_cplt_cbk)(struct trng_handle_s *arg);  /**< Trng error callback */
-    void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */
+typedef struct trng_handle_s {
+	TRNG_TypeDef *perh;	/**< Register base address */
+	trng_init_t init;	/**< TRNG required parameters */
+	uint32_t data;		/**< result data */
+	lock_state_t lock; 	/**< Locking object */
+	trng_state_t state;	/**< TRNG operation state */
+
+	void (*trng_cplt_cbk)(struct trng_handle_s *arg); /**< Trng completed callback */
+	void (*err_cplt_cbk)(struct trng_handle_s *arg);  /**< Trng error callback */
+	void (*init_cplt_cbk)(struct trng_handle_s *arg); /**< Trng init completed callback */
 } trng_handle_t;
 /**
   * @}
@@ -154,15 +146,16 @@ typedef struct trng_handle_s
                                  ((x) == TRNG_SEED_TYPE_LAST) || \
                                  ((x) == TRNG_SEED_TYPE_SEED))
 #define IS_TRNG_STATUS(x)	(((x) == TRNG_STATUS_START)  || \
-                             ((x) == TRNG_STATUS_DAVLD)  || \
-                             ((x) == TRNG_STATUS_SERR))
-#define IS_TRNG_IT(x)	(((x) == TRNG_IT_START)  || \
-                         ((x) == TRNG_IT_DAVLD)  || \
-                         ((x) == TRNG_IT_SERR))
-#define IS_TRNG_FLAG(x)	(((x) == TRNG_IF_START)  || \
-                         ((x) == TRNG_IF_DAVLD)  || \
-                         ((x) == TRNG_IF_SERR))
-#define IS_TRNG_ADJC(x)	((x) < 4)
+                                 ((x) == TRNG_STATUS_DAVLD)  || \
+                                 ((x) == TRNG_STATUS_SERR))
+#define IS_TRNG_IT(x)		(((x) == TRNG_IT_START)  || \
+                                 ((x) == TRNG_IT_DAVLD)  || \
+                                 ((x) == TRNG_IT_SERR))
+#define IS_TRNG_FLAG(x)		(((x) == TRNG_IF_START)  || \
+                                 ((x) == TRNG_IF_DAVLD)  || \
+                                 ((x) == TRNG_IF_SERR))
+#define IS_TRNG_ADJC(x)		((x) < 4)
+#define IS_TRNG_T_START(x)	((x) < 8)
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_tsense.h

@@ -35,74 +35,74 @@ extern "C" {
 /** @defgroup TSENSE_Public_Macros TSENSE Public Macros
   * @{
   */
-#define TSENSE_LOCK()		(WRITE_REG(TSENSE->WPR, 0x0))
-#define TSENSE_UNLOCK()		(WRITE_REG(TSENSE->WPR, 0xA55A9669))
+#define TSENSE_LOCK()		(WRITE_REG(TSENSE->WPR, 0x0U))
+#define TSENSE_UNLOCK()		(WRITE_REG(TSENSE->WPR, 0xA55A9669U))
 #define TSENSE_ENABLE()					\
-    do {							\
-        TSENSE_UNLOCK();				\
-        SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);		\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);		\
+	TSENSE_LOCK();					\
+} while (0)
 #define TSENSE_DISABLE()				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);	\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);	\
+	TSENSE_LOCK();					\
+} while (0)
 #define TSENSE_REQ_ENABLE()				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);	\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	SET_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);	\
+	TSENSE_LOCK();					\
+} while (0)
 #define TSENSE_REQ_DISABLE()				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);	\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_REQEN_MSK);	\
+	TSENSE_LOCK();					\
+} while (0)
 #define TSENSE_CTN_ENABLE()				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);		\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	SET_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);		\
+	TSENSE_LOCK();					\
+} while (0)
 #define TSENSE_CTN_DISABLE()				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);	\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_CTN_MSK);	\
+	TSENSE_LOCK();					\
+} while (0)
 #define TSENSE_RESET()					\
-    do {							\
-        TSENSE_UNLOCK();				\
-        SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK);		\
-        TSENSE_LOCK();					\
-    } while (0)
+do {							\
+	TSENSE_UNLOCK();				\
+	SET_BIT(TSENSE->CR, TSENSE_CR_RST_MSK);		\
+	TSENSE_LOCK();					\
+} while (0)
 #define	TSENSE_LTGR_WR(data)				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        WRITE_REG(TSENSE->LTGR, (data));		\
-        TSENSE_LOCK();					\
-    } while(0)
+do {							\
+	TSENSE_UNLOCK();				\
+	WRITE_REG(TSENSE->LTGR, (data));		\
+	TSENSE_LOCK();					\
+} while (0)
 #define	TSENSE_HTGR_WR(data)				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        WRITE_REG(TSENSE->HTGR, (data));		\
-        TSENSE_LOCK();					\
-    } while(0)
+do {							\
+	TSENSE_UNLOCK();				\
+	WRITE_REG(TSENSE->HTGR, (data));		\
+	TSENSE_LOCK();					\
+} while (0)
 #define	TSENSE_TBDR_WR(data)				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        WRITE_REG(TSENSE->TBDR, (data));		\
-        TSENSE_LOCK();					\
-    } while(0)
+do {							\
+	TSENSE_UNLOCK();				\
+	WRITE_REG(TSENSE->TBDR, (data));		\
+	TSENSE_LOCK();					\
+} while (0)
 #define	TSENSE_TCALBDR_WR(data)				\
-    do {							\
-        TSENSE_UNLOCK();				\
-        WRITE_REG(TSENSE->TCALBDR, (data));		\
-        TSENSE_LOCK();					\
-    } while(0)
+do {							\
+	TSENSE_UNLOCK();				\
+	WRITE_REG(TSENSE->TCALBDR, (data));		\
+	TSENSE_LOCK();					\
+} while (0)
 /**
   * @}
   */
@@ -113,50 +113,34 @@ extern "C" {
 /**
   * @brief Temperature update time
   */
-typedef enum
-{
-    TSENSE_UPDATE_CYCLE_3 = 0x3,	/**< 3 Cycles */
-    TSENSE_UPDATE_CYCLE_4 = 0x4,	/**< 4 Cycles */
-    TSENSE_UPDATE_CYCLE_5 = 0x5,	/**< 5 Cycles */
-    TSENSE_UPDATE_CYCLE_6 = 0x6,	/**< 6 Cycles */
-    TSENSE_UPDATE_CYCLE_7 = 0x7,	/**< 7 Cycles */
+typedef enum {
+	TSENSE_UPDATE_CYCLE_3 = 0x3U,	/**< 3 Cycles */
+	TSENSE_UPDATE_CYCLE_4 = 0x4U,	/**< 4 Cycles */
+	TSENSE_UPDATE_CYCLE_5 = 0x5U,	/**< 5 Cycles */
+	TSENSE_UPDATE_CYCLE_6 = 0x6U,	/**< 6 Cycles */
+	TSENSE_UPDATE_CYCLE_7 = 0x7U,	/**< 7 Cycles */
 } tsense_update_cycle_t;
 
 /**
   * @brief Temperature output mode
   */
-typedef enum
-{
-    TSENSE_OUTPUT_MODE_200  = 0x0,	/**< 200 cycles update one temperature */
-    TSENSE_OUTPUT_MODE_400  = 0x1,	/**< 400 cycles update one temperature */
-    TSENSE_OUTPUT_MODE_800  = 0x2,	/**< 800 cycles update one temperature */
-    TSENSE_OUTPUT_MODE_1600 = 0x3,	/**< 1600 cycles update one temperature */
-    TSENSE_OUTPUT_MODE_3200 = 0x4,	/**< 3200 cycles update one temperature */
+typedef enum {
+	TSENSE_OUTPUT_MODE_200  = 0x0U,	/**< 200 cycles update one temperature */
+	TSENSE_OUTPUT_MODE_400  = 0x1U,	/**< 400 cycles update one temperature */
+	TSENSE_OUTPUT_MODE_800  = 0x2U,	/**< 800 cycles update one temperature */
+	TSENSE_OUTPUT_MODE_1600 = 0x3U,	/**< 1600 cycles update one temperature */
+	TSENSE_OUTPUT_MODE_3200 = 0x4U,	/**< 3200 cycles update one temperature */
 } tsense_output_mode_t;
 
 /**
   * @brief Source select
   */
-typedef enum
-{
-    TSENSE_SOURCE_LOSC        = 0x0,	/**< LOSC */
-    TSENSE_SOURCE_LRC         = 0x1,	/**< LRC */
-    TSENSE_SOURCE_HRC_DIV_1M  = 0x2,	/**< HRC divide to 1MHz */
-    TSENSE_SOURCE_HOSC_DIV_1M = 0x3,	/**< HOSC divide to 1MHz */
+typedef enum {
+	TSENSE_SOURCE_LOSC        = 0x0U,	/**< LOSC */
+	TSENSE_SOURCE_LRC         = 0x1U,	/**< LRC */
 } tsense_source_sel_t;
 
 
-/**
-  * @brief TSENSE init structure definition
-  */
-typedef struct
-{
-    tsense_update_cycle_t cycle;	/**< Temperature update time */
-    tsense_output_mode_t mode;	/**< Temperature output mode */
-    type_func_t ctn;		/**< Continue mode */
-    uint8_t psc;			/**< Perscaler */
-} tsense_init_t;
-
 /**
   * @brief Define callback function type
   */
@@ -169,20 +153,8 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
   * @defgroup TSENSE_Private_Macros TSENSE Private Macros
   * @{
   */
-#define IS_TSENSE_UPDATE_CYCLE(x)	(((x) == TSENSE_UPDATE_CYCLE_3) || \
-                                     ((x) == TSENSE_UPDATE_CYCLE_4) || \
-                                     ((x) == TSENSE_UPDATE_CYCLE_5) || \
-                                     ((x) == TSENSE_UPDATE_CYCLE_6) || \
-                                     ((x) == TSENSE_UPDATE_CYCLE_7))
-#define IS_TSENSE_OUTPUT_MODE(x)	(((x) == TSENSE_OUTPUT_MODE_200)  || \
-                                     ((x) == TSENSE_OUTPUT_MODE_400)  || \
-                                     ((x) == TSENSE_OUTPUT_MODE_800)  || \
-                                     ((x) == TSENSE_OUTPUT_MODE_1600) || \
-                                     ((x) == TSENSE_OUTPUT_MODE_3200))
-#define IS_TSENSE_SOURCE_SEL(x)	(((x) == TSENSE_SOURCE_LOSC)        || \
-                                 ((x) == TSENSE_SOURCE_LRC)         || \
-                                 ((x) == TSENSE_SOURCE_HRC_DIV_1M ) || \
-                                 ((x) == TSENSE_SOURCE_HOSC_DIV_1M))
+#define IS_TSENSE_SOURCE_SEL(x)	(((x) == TSENSE_SOURCE_LOSC) || \
+                                 ((x) == TSENSE_SOURCE_LRC))
 /**
   * @}
   */
@@ -194,7 +166,7 @@ typedef void (*tsense_cbk)(uint16_t value, ald_status_t status);
   * @{
   */
 /* Initialization functions */
-extern void ald_tsense_init(tsense_init_t *init);
+extern void ald_tsense_init(void);
 extern void ald_tsense_source_select(tsense_source_sel_t sel);
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_uart.h

@@ -74,233 +74,216 @@ extern "C" {
 /**
   * @brief UART word length
   */
-typedef enum
-{
-    UART_WORD_LENGTH_5B = 0x0,	/**< 5-bits */
-    UART_WORD_LENGTH_6B = 0x1,	/**< 6-bits */
-    UART_WORD_LENGTH_7B = 0x2,	/**< 7-bits */
-    UART_WORD_LENGTH_8B = 0x3,	/**< 8-bits */
+typedef enum {
+	UART_WORD_LENGTH_5B = 0x0U,	/**< 5-bits */
+	UART_WORD_LENGTH_6B = 0x1U,	/**< 6-bits */
+	UART_WORD_LENGTH_7B = 0x2U,	/**< 7-bits */
+	UART_WORD_LENGTH_8B = 0x3U,	/**< 8-bits */
 } uart_word_length_t;
 
 /**
   * @brief UART stop bits
   */
-typedef enum
-{
-    UART_STOP_BITS_1   = 0x0,		/**< 1-bits */
-    UART_STOP_BITS_2   = 0x1,		/**< 2-bits */
-    UART_STOP_BITS_0_5 = 0x0,		/**< 0.5-bits, using smartcard mode */
-    UART_STOP_BITS_1_5 = 0x1,		/**< 1.5-bits, using smartcard mode */
+typedef enum {
+	UART_STOP_BITS_1   = 0x0U,	/**< 1-bits */
+	UART_STOP_BITS_2   = 0x1U,	/**< 2-bits */
+	UART_STOP_BITS_0_5 = 0x0U,	/**< 0.5-bits, using smartcard mode */
+	UART_STOP_BITS_1_5 = 0x1U,	/**< 1.5-bits, using smartcard mode */
 } uart_stop_bits_t;
 
 /**
   * @brief UART parity
   */
-typedef enum
-{
-    UART_PARITY_NONE = 0x0,		/**< Not parity */
-    UART_PARITY_ODD  = 0x1,		/**< Odd parity */
-    UART_PARITY_EVEN = 0x3,		/**< Even parity */
+typedef enum {
+	UART_PARITY_NONE = 0x0U,	/**< Not parity */
+	UART_PARITY_ODD  = 0x1U,	/**< Odd parity */
+	UART_PARITY_EVEN = 0x3U,	/**< Even parity */
 } uart_parity_t;
 
 /**
   * @brief UART mode
   */
-typedef enum
-{
-    UART_MODE_UART  = 0x0,		/**< UART */
-    UART_MODE_LIN   = 0x1,		/**< LIN */
-    UART_MODE_IrDA  = 0x2,		/**< IrDA */
-    UART_MODE_RS485 = 0x3,		/**< RS485 */
-    UART_MODE_HDSEL = 0x4,		/**< Single-wire half-duplex */
+typedef enum {
+	UART_MODE_UART  = 0x0U,		/**< UART */
+	UART_MODE_LIN   = 0x1U,		/**< LIN */
+	UART_MODE_IrDA  = 0x2U,		/**< IrDA */
+	UART_MODE_RS485 = 0x3U,		/**< RS485 */
+	UART_MODE_HDSEL = 0x4U,		/**< Single-wire half-duplex */
 } uart_mode_t;
 
 /**
   * @brief UART hardware flow control
   */
-typedef enum
-{
-    UART_HW_FLOW_CTL_DISABLE = 0x0,	/**< Auto-flow-control disable */
-    UART_HW_FLOW_CTL_ENABLE  = 0x1,	/**< Auto-flow-control enable */
+typedef enum {
+	UART_HW_FLOW_CTL_DISABLE = 0x0U,	/**< Auto-flow-control disable */
+	UART_HW_FLOW_CTL_ENABLE  = 0x1U,	/**< Auto-flow-control enable */
 } uart_hw_flow_ctl_t;
 
 /**
   * @brief ALD UART state
   */
-typedef enum
-{
-    UART_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-    UART_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-    UART_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-    UART_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-    UART_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-    UART_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission Reception process is ongoing */
-    UART_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-    UART_STATE_ERROR      = 0x04,	/**< Error */
+typedef enum {
+	UART_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
+	UART_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
+	UART_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
+	UART_STATE_BUSY_TX    = 0x11U,	/**< Data Transmission process is ongoing */
+	UART_STATE_BUSY_RX    = 0x21U,	/**< Data Reception process is ongoing */
+	UART_STATE_BUSY_TX_RX = 0x31U,	/**< Data Transmission Reception process is ongoing */
+	UART_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
+	UART_STATE_ERROR      = 0x04U,	/**< Error */
 } uart_state_t;
 
 /**
   * @brief UART error codes
   */
-typedef enum
-{
-    UART_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-    UART_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-    UART_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-    UART_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-    UART_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-    UART_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
+typedef enum {
+	UART_ERROR_NONE = ((uint32_t)0x00U),	/**< No error */
+	UART_ERROR_PE   = ((uint32_t)0x01U),	/**< Parity error */
+	UART_ERROR_NE   = ((uint32_t)0x02U),	/**< Noise error */
+	UART_ERROR_FE   = ((uint32_t)0x04U),	/**< frame error */
+	UART_ERROR_ORE  = ((uint32_t)0x08U),	/**< Overrun error */
+	UART_ERROR_DMA  = ((uint32_t)0x10U),	/**< DMA transfer error */
 } uart_error_t;
 
 /**
   * @brief UART init structure definition
   */
-typedef struct
-{
-    uint32_t baud;			/**< Specifies the uart communication baud rate */
-    uart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
-    uart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted */
-    uart_parity_t parity;		/**< Specifies the parity mode */
-    uart_mode_t mode;		/**< Specifies uart mode */
-    uart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled */
+typedef struct {
+	uint32_t baud;			/**< Specifies the uart communication baud rate */
+	uart_word_length_t word_length;	/**< Specifies the number of data bits transmitted or received in a frame */
+	uart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted */
+	uart_parity_t parity;		/**< Specifies the parity mode */
+	uart_mode_t mode;		/**< Specifies uart mode */
+	uart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled */
 } uart_init_t;
 
 /**
   * @brief  UART handle structure definition
   */
-typedef struct uart_handle_s
-{
-    UART_TypeDef *perh;	/**< UART registers base address */
-    uart_init_t init;	/**< UART communication parameters */
-    uint8_t *tx_buf;	/**< Pointer to UART Tx transfer Buffer */
-    uint16_t tx_size;	/**< UART Tx Transfer size */
-    uint16_t tx_count;	/**< UART Tx Transfer Counter */
-    uint8_t *rx_buf;	/**< Pointer to UART Rx transfer Buffer */
-    uint16_t rx_size;	/**< UART Rx Transfer size */
-    uint16_t rx_count;	/**< UART Rx Transfer Counter */
+typedef struct uart_handle_s {
+	UART_TypeDef *perh;	/**< UART registers base address */
+	uart_init_t init;	/**< UART communication parameters */
+	uint8_t *tx_buf;	/**< Pointer to UART Tx transfer Buffer */
+	uint16_t tx_size;	/**< UART Tx Transfer size */
+	uint16_t tx_count;	/**< UART Tx Transfer Counter */
+	uint8_t *rx_buf;	/**< Pointer to UART Rx transfer Buffer */
+	uint16_t rx_size;	/**< UART Rx Transfer size */
+	uint16_t rx_count;	/**< UART Rx Transfer Counter */
 #ifdef ALD_DMA
-    dma_handle_t hdmatx;	/**< UART Tx DMA Handle parameters */
-    dma_handle_t hdmarx;	/**< UART Rx DMA Handle parameters */
+	dma_handle_t hdmatx;	/**< UART Tx DMA Handle parameters */
+	dma_handle_t hdmarx;	/**< UART Rx DMA Handle parameters */
 #endif
-    lock_state_t lock;	/**< Locking object */
-    uart_state_t state;	/**< UART communication state */
-    uart_error_t err_code;	/**< UART Error code */
+	lock_state_t lock;	/**< Locking object */
+	uart_state_t state;	/**< UART communication state */
+	uart_error_t err_code;	/**< UART Error code */
 
-    void (*tx_cplt_cbk)(struct uart_handle_s *arg);	/**< Tx completed callback */
-    void (*rx_cplt_cbk)(struct uart_handle_s *arg);	/**< Rx completed callback */
-    void (*error_cbk)(struct uart_handle_s *arg);	/**< error callback */
+	void (*tx_cplt_cbk)(struct uart_handle_s *arg);	/**< Tx completed callback */
+	void (*rx_cplt_cbk)(struct uart_handle_s *arg);	/**< Rx completed callback */
+	void (*error_cbk)(struct uart_handle_s *arg);	/**< error callback */
 } uart_handle_t;
 
 /**
   * @brief UART RS485 configure structure definition
   */
-typedef struct
-{
-    type_func_t normal;	/**< Normal mode */
-    type_func_t dir;	/**< Auto-direction mode */
-    type_func_t invert;	/**< Address detection invert */
-    uint8_t addr;		/**< Address for compare */
+typedef struct {
+	type_func_t normal;	/**< Normal mode */
+	type_func_t dir;	/**< Auto-direction mode */
+	type_func_t invert;	/**< Address detection invert */
+	uint8_t addr;		/**< Address for compare */
 } uart_rs485_config_t;
 
 /**
   * @brief LIN detection break length
   */
-typedef enum
-{
-    LIN_BREAK_LEN_10B = 0x0,	/**< 10-bit break */
-    LIN_BREAK_LEN_11B = 0x1,	/**< 11-bit break */
+typedef enum {
+	LIN_BREAK_LEN_10B = 0x0U,	/**< 10-bit break */
+	LIN_BREAK_LEN_11B = 0x1U,	/**< 11-bit break */
 } uart_lin_break_len_t;
 
 /**
   * @brief UART TXFIFO size
   */
-typedef enum
-{
-    UART_TXFIFO_EMPTY = 0x0,	/**< Empty */
-    UART_TXFIFO_2BYTE = 0x1,	/**< 2-Bytes */
-    UART_TXFIFO_4BYTE = 0x2,	/**< 4-Bytes */
-    UART_TXFIFO_8BYTE = 0x3,	/**< 8-Bytes */
+typedef enum {
+	UART_TXFIFO_EMPTY = 0x0U,	/**< Empty */
+	UART_TXFIFO_2BYTE = 0x1U,	/**< 2-Bytes */
+	UART_TXFIFO_4BYTE = 0x2U,	/**< 4-Bytes */
+	UART_TXFIFO_8BYTE = 0x3U,	/**< 8-Bytes */
 } uart_txfifo_t;
 
 /**
   * @brief UART RXFIFO size
   */
-typedef enum
-{
-    UART_RXFIFO_1BYTE  = 0x0,	/**< 1-Byte */
-    UART_RXFIFO_4BYTE  = 0x1,	/**< 4-Bytes */
-    UART_RXFIFO_8BYTE  = 0x2,	/**< 8-Bytes */
-    UART_RXFIFO_14BYTE = 0x3,	/**< 14-Bytes */
+typedef enum {
+	UART_RXFIFO_1BYTE  = 0x0U,	/**< 1-Byte */
+	UART_RXFIFO_4BYTE  = 0x1U,	/**< 4-Bytes */
+	UART_RXFIFO_8BYTE  = 0x2U,	/**< 8-Bytes */
+	UART_RXFIFO_14BYTE = 0x3U,	/**< 14-Bytes */
 } uart_rxfifo_t;
 
 /**
   * @brief UART auto-baud mode
   */
-typedef enum
-{
-    UART_ABRMOD_1_TO_0 = 0x0,	/**< Detect bit0:1, bit1:0 */
-    UART_ABRMOD_1      = 0x1,	/**< Detect bit0:1 */
-    UART_ABRMOD_0_TO_1 = 0x2,	/**< Detect bit0:0, bit1:1 */
+typedef enum {
+	UART_ABRMOD_1_TO_0 = 0x0U,	/**< Detect bit0:1, bit1:0 */
+	UART_ABRMOD_1      = 0x1U,	/**< Detect bit0:1 */
+	UART_ABRMOD_0_TO_1 = 0x2U,	/**< Detect bit0:0, bit1:1 */
 } uart_auto_baud_mode_t;
 
 /**
   * @brief UART status types
   */
-typedef enum
-{
-    UART_STATUS_DR   = (1U << 0),	/**< Data ready */
-    UART_STATUS_OE   = (1U << 1),	/**< Overrun error */
-    UART_STATUS_PE   = (1U << 2),	/**< Parity error */
-    UART_STATUS_FE   = (1U << 3),	/**< Framing error */
-    UART_STATUS_BI   = (1U << 4),	/**< Break interrupt */
-    UART_STATUS_TBEM = (1U << 5),	/**< Transmit buffer empty */
-    UART_STATUS_TEM  = (1U << 6),	/**< Transmitter empty */
-    UART_STATUS_RFE  = (1U << 7),	/**< Reveiver FIFO data error */
-    UART_STATUS_BUSY = (1U << 8),	/**< UART busy */
-    UART_STATUS_TFNF = (1U << 9),	/**< Transmit FIFO not full */
-    UART_STATUS_TFEM = (1U << 10),	/**< Transmit FIFO not empty */
-    UART_STATUS_RFNE = (1U << 11),	/**< Receive FIFO not empty */
-    UART_STATUS_RFF  = (1U << 12),	/**< Receive FIFO full */
-    UART_STATUS_DCTS = (1U << 14),	/**< Delta clear to send */
-    UART_STATUS_CTS  = (1U << 15),	/**< Clear to send */
+typedef enum {
+	UART_STATUS_DR   = (1U << 0),	/**< Data ready */
+	UART_STATUS_OE   = (1U << 1),	/**< Overrun error */
+	UART_STATUS_PE   = (1U << 2),	/**< Parity error */
+	UART_STATUS_FE   = (1U << 3),	/**< Framing error */
+	UART_STATUS_BI   = (1U << 4),	/**< Break interrupt */
+	UART_STATUS_TBEM = (1U << 5),	/**< Transmit buffer empty */
+	UART_STATUS_TEM  = (1U << 6),	/**< Transmitter empty */
+	UART_STATUS_RFE  = (1U << 7),	/**< Reveiver FIFO data error */
+	UART_STATUS_BUSY = (1U << 8),	/**< UART busy */
+	UART_STATUS_TFNF = (1U << 9),	/**< Transmit FIFO not full */
+	UART_STATUS_TFEM = (1U << 10),	/**< Transmit FIFO not empty */
+	UART_STATUS_RFNE = (1U << 11),	/**< Receive FIFO not empty */
+	UART_STATUS_RFF  = (1U << 12),	/**< Receive FIFO full */
+	UART_STATUS_DCTS = (1U << 14),	/**< Delta clear to send */
+	UART_STATUS_CTS  = (1U << 15),	/**< Clear to send */
 } uart_status_t;
 
 /**
   * @brief UART interrupt types
   */
-typedef enum
-{
-    UART_IT_RXRD  = (1U << 0),	/**< Receive data available */
-    UART_IT_TXS   = (1U << 1),	/**< Tx empty status */
-    UART_IT_RXS   = (1U << 2),	/**< Rx line status */
-    UART_IT_MDS   = (1U << 3),	/**< Modem status */
-    UART_IT_RTO   = (1U << 4),	/**< Receiver timeout */
-    UART_IT_BZ    = (1U << 5),	/**< Busy status */
-    UART_IT_ABE   = (1U << 6),	/**< Auto-baud rate detection end */
-    UART_IT_ABTO  = (1U << 7),	/**< Auto-baud rate detection timeout */
-    UART_IT_LINBK = (1U << 8),	/**< Lin break detection */
-    UART_IT_TC    = (1U << 9),	/**< Transmission complete */
-    UART_IT_EOB   = (1U << 10),	/**< End of block */
-    UART_IT_CM    = (1U << 11),	/**< Character match */
+typedef enum {
+	UART_IT_RXRD  = (1U << 0),	/**< Receive data available */
+	UART_IT_TXS   = (1U << 1),	/**< Tx empty status */
+	UART_IT_RXS   = (1U << 2),	/**< Rx line status */
+	UART_IT_MDS   = (1U << 3),	/**< Modem status */
+	UART_IT_RTO   = (1U << 4),	/**< Receiver timeout */
+	UART_IT_BZ    = (1U << 5),	/**< Busy status */
+	UART_IT_ABE   = (1U << 6),	/**< Auto-baud rate detection end */
+	UART_IT_ABTO  = (1U << 7),	/**< Auto-baud rate detection timeout */
+	UART_IT_LINBK = (1U << 8),	/**< Lin break detection */
+	UART_IT_TC    = (1U << 9),	/**< Transmission complete */
+	UART_IT_EOB   = (1U << 10),	/**< End of block */
+	UART_IT_CM    = (1U << 11),	/**< Character match */
 } uart_it_t;
 
 /**
   * @brief UART flags types
   */
-typedef enum
-{
-    UART_IF_RXRD  = (1U << 0),	/**<  Receive data available */
-    UART_IF_TXS   = (1U << 1),	/**<  Tx empty status */
-    UART_IF_RXS   = (1U << 2),	/**<  Rx line status */
-    UART_IF_MDS   = (1U << 3),	/**<  Modem status */
-    UART_IF_RTO   = (1U << 4),	/**<  Receiver timeout */
-    UART_IF_BZ    = (1U << 5),	/**<  Busy status */
-    UART_IF_ABE   = (1U << 6),	/**<  Auto-baud rate detection end */
-    UART_IF_ABTO  = (1U << 7),	/**<  Auto-baud rate detection timeout */
-    UART_IF_LINBK = (1U << 8),	/**<  Lin break detection */
-    UART_IF_TC    = (1U << 9),	/**<  Transmission complete */
-    UART_IF_EOB   = (1U << 10),	/**<  End of block */
-    UART_IF_CM    = (1U << 11),	/**<  Character match */
+typedef enum {
+	UART_IF_RXRD  = (1U << 0),	/**<  Receive data available */
+	UART_IF_TXS   = (1U << 1),	/**<  Tx empty status */
+	UART_IF_RXS   = (1U << 2),	/**<  Rx line status */
+	UART_IF_MDS   = (1U << 3),	/**<  Modem status */
+	UART_IF_RTO   = (1U << 4),	/**<  Receiver timeout */
+	UART_IF_BZ    = (1U << 5),	/**<  Busy status */
+	UART_IF_ABE   = (1U << 6),	/**<  Auto-baud rate detection end */
+	UART_IF_ABTO  = (1U << 7),	/**<  Auto-baud rate detection timeout */
+	UART_IF_LINBK = (1U << 8),	/**<  Lin break detection */
+	UART_IF_TC    = (1U << 9),	/**<  Transmission complete */
+	UART_IF_EOB   = (1U << 10),	/**<  End of block */
+	UART_IF_CM    = (1U << 11),	/**<  Character match */
 } uart_flag_t;
 /**
   * @}
@@ -318,22 +301,22 @@ typedef enum
                                  ((x) == UART_WORD_LENGTH_7B) || \
                                  ((x) == UART_WORD_LENGTH_8B))
 #define IS_UART_STOPBITS(x)	(((x) == UART_STOP_BITS_1)   || \
-                             ((x) == UART_STOP_BITS_2)   || \
-                             ((x) == UART_STOP_BITS_0_5) || \
-                             ((x) == UART_STOP_BITS_1_5))
+                                 ((x) == UART_STOP_BITS_2)   || \
+                                 ((x) == UART_STOP_BITS_0_5) || \
+                                 ((x) == UART_STOP_BITS_1_5))
 #define IS_UART_PARITY(x)	(((x) == UART_PARITY_NONE)  || \
-                             ((x) == UART_PARITY_ODD) || \
-                             ((x) == UART_PARITY_EVEN))
+                                 ((x) == UART_PARITY_ODD) || \
+                                 ((x) == UART_PARITY_EVEN))
 #define IS_UART_MODE(x)		(((x) == UART_MODE_UART) || \
-                             ((x) == UART_MODE_LIN)  || \
-                             ((x) == UART_MODE_IrDA) || \
-                             ((x) == UART_MODE_RS485) || \
-                             ((x) == UART_MODE_HDSEL))
+                                 ((x) == UART_MODE_LIN)  || \
+                                 ((x) == UART_MODE_IrDA) || \
+                                 ((x) == UART_MODE_RS485) || \
+                                 ((x) == UART_MODE_HDSEL))
 #define IS_UART_HARDWARE_FLOW_CONTROL(x) \
-    (((x) == UART_HW_FLOW_CTL_DISABLE) || \
-     ((x) == UART_HW_FLOW_CTL_ENABLE))
+                                (((x) == UART_HW_FLOW_CTL_DISABLE) || \
+                                 ((x) == UART_HW_FLOW_CTL_ENABLE))
 #define IS_UART_LIN_BREAK_LEN(x)	(((x) == LIN_BREAK_LEN_10B) || \
-                                     ((x) == LIN_BREAK_LEN_11B))
+                                         ((x) == LIN_BREAK_LEN_11B))
 #define IS_UART_TXFIFO_TYPE(x)	(((x) == UART_TXFIFO_EMPTY) || \
                                  ((x) == UART_TXFIFO_2BYTE) || \
                                  ((x) == UART_TXFIFO_4BYTE) || \
@@ -343,47 +326,47 @@ typedef enum
                                  ((x) == UART_RXFIFO_8BYTE) || \
                                  ((x) == UART_RXFIFO_14BYTE))
 #define IS_UART_AUTO_BAUD_MODE(x)	(((x) == UART_ABRMOD_1_TO_0) || \
-                                     ((x) == UART_ABRMOD_1)      || \
-                                     ((x) == UART_ABRMOD_0_TO_1))
+                                         ((x) == UART_ABRMOD_1)      || \
+                                         ((x) == UART_ABRMOD_0_TO_1))
 #define IS_UART_STATUS(x)	(((x) == UART_STATUS_DR)   || \
-                             ((x) == UART_STATUS_OE)   || \
-                             ((x) == UART_STATUS_PE)   || \
-                             ((x) == UART_STATUS_FE)   || \
-                             ((x) == UART_STATUS_BI)   || \
-                             ((x) == UART_STATUS_TBEM) || \
-                             ((x) == UART_STATUS_TEM)  || \
-                             ((x) == UART_STATUS_RFE)  || \
-                             ((x) == UART_STATUS_BUSY) || \
-                             ((x) == UART_STATUS_TFNF) || \
-                             ((x) == UART_STATUS_TFEM) || \
-                             ((x) == UART_STATUS_RFNE) || \
-                             ((x) == UART_STATUS_RFF)  || \
-                             ((x) == UART_STATUS_DCTS) || \
-                             ((x) == UART_STATUS_CTS))
+                                 ((x) == UART_STATUS_OE)   || \
+                                 ((x) == UART_STATUS_PE)   || \
+                                 ((x) == UART_STATUS_FE)   || \
+                                 ((x) == UART_STATUS_BI)   || \
+                                 ((x) == UART_STATUS_TBEM) || \
+                                 ((x) == UART_STATUS_TEM)  || \
+                                 ((x) == UART_STATUS_RFE)  || \
+                                 ((x) == UART_STATUS_BUSY) || \
+                                 ((x) == UART_STATUS_TFNF) || \
+                                 ((x) == UART_STATUS_TFEM) || \
+                                 ((x) == UART_STATUS_RFNE) || \
+                                 ((x) == UART_STATUS_RFF)  || \
+                                 ((x) == UART_STATUS_DCTS) || \
+                                 ((x) == UART_STATUS_CTS))
 #define IS_UART_IT(x)		(((x) == UART_IT_RXRD)  || \
-                             ((x) == UART_IT_TXS)   || \
-                             ((x) == UART_IT_RXS)   || \
-                             ((x) == UART_IT_MDS)   || \
-                             ((x) == UART_IT_RTO)   || \
-                             ((x) == UART_IT_BZ)    || \
-                             ((x) == UART_IT_ABE)   || \
-                             ((x) == UART_IT_ABTO)  || \
-                             ((x) == UART_IT_LINBK) || \
-                             ((x) == UART_IT_TC)    || \
-                             ((x) == UART_IT_EOB)   || \
-                             ((x) == UART_IT_CM))
+                                 ((x) == UART_IT_TXS)   || \
+                                 ((x) == UART_IT_RXS)   || \
+                                 ((x) == UART_IT_MDS)   || \
+                                 ((x) == UART_IT_RTO)   || \
+                                 ((x) == UART_IT_BZ)    || \
+                                 ((x) == UART_IT_ABE)   || \
+                                 ((x) == UART_IT_ABTO)  || \
+                                 ((x) == UART_IT_LINBK) || \
+                                 ((x) == UART_IT_TC)    || \
+                                 ((x) == UART_IT_EOB)   || \
+                                 ((x) == UART_IT_CM))
 #define IS_UART_IF(x)		(((x) == UART_IF_RXRD)  || \
-                             ((x) == UART_IF_TXS)   || \
-                             ((x) == UART_IF_RXS)   || \
-                             ((x) == UART_IF_MDS)   || \
-                             ((x) == UART_IF_RTO)   || \
-                             ((x) == UART_IF_BZ)    || \
-                             ((x) == UART_IF_ABE)   || \
-                             ((x) == UART_IF_ABTO)  || \
-                             ((x) == UART_IF_LINBK) || \
-                             ((x) == UART_IF_TC)    || \
-                             ((x) == UART_IF_EOB)   || \
-                             ((x) == UART_IF_CM))
+                                 ((x) == UART_IF_TXS)   || \
+                                 ((x) == UART_IF_RXS)   || \
+                                 ((x) == UART_IF_MDS)   || \
+                                 ((x) == UART_IF_RTO)   || \
+                                 ((x) == UART_IF_BZ)    || \
+                                 ((x) == UART_IF_ABE)   || \
+                                 ((x) == UART_IF_ABTO)  || \
+                                 ((x) == UART_IF_LINBK) || \
+                                 ((x) == UART_IF_TC)    || \
+                                 ((x) == UART_IF_EOB)   || \
+                                 ((x) == UART_IF_CM))
 #define IS_UART_BAUDRATE(x)	(((x) > 0) && ((x) < 0x44AA21))
 #define IS_UART_DATA(x)		((x) <= 0x1FF)
 
@@ -434,8 +417,8 @@ void ald_uart_irq_handler(uart_handle_t *hperh);
 /* Peripheral Control functions */
 void ald_uart_interrupt_config(uart_handle_t *hperh, uart_it_t it, type_func_t state);
 void ald_uart_dma_req_config(uart_handle_t *hperh, type_func_t state);
-void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
-void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config, uint8_t level);
+void ald_uart_tx_fifo_config(uart_handle_t *hperh, uart_txfifo_t config);
+void ald_uart_rx_fifo_config(uart_handle_t *hperh, uart_rxfifo_t config);
 void ald_uart_lin_send_break(uart_handle_t *hperh);
 void ald_uart_lin_detect_break_len_config(uart_handle_t *hperh, uart_lin_break_len_t len);
 void ald_uart_auto_baud_config(uart_handle_t *hperh, uart_auto_baud_mode_t mode);

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_usart.h

@@ -18,7 +18,7 @@
 #define __ALD_USART_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include "utils.h"
@@ -40,174 +40,159 @@ extern "C" {
 /**
   * @brief usart_word_length
   */
-typedef enum
-{
-    USART_WORD_LENGTH_8B = 0x0,	/**< Word length is 8-bits */
-    USART_WORD_LENGTH_9B = 0x1,	/**< Word length is 9-bits */
+typedef enum {
+	USART_WORD_LENGTH_8B = 0x0U,	/**< Word length is 8-bits */
+	USART_WORD_LENGTH_9B = 0x1U,	/**< Word length is 9-bits */
 } usart_word_length_t;
 
 /**
   * @brief usart_stop_bits
   */
-typedef enum
-{
-    USART_STOP_BITS_1   = 0x0,	/**< Stop bits is 1-bits */
-    USART_STOP_BITS_0_5 = 0x1,	/**< Stop bits is 0.5-bits */
-    USART_STOP_BITS_2   = 0x2,	/**< Stop bits is 2-bits */
-    USART_STOP_BITS_1_5 = 0x3,	/**< Stop bits is 1.5-bits */
+typedef enum {
+	USART_STOP_BITS_1   = 0x0U,	/**< Stop bits is 1-bits */
+	USART_STOP_BITS_0_5 = 0x1U,	/**< Stop bits is 0.5-bits */
+	USART_STOP_BITS_2   = 0x2U,	/**< Stop bits is 2-bits */
+	USART_STOP_BITS_1_5 = 0x3U,	/**< Stop bits is 1.5-bits */
 } usart_stop_bits_t;
 
 /**
   * @brief usart_parity
   */
-typedef enum
-{
-    USART_PARITY_NONE = 0x0,	/**< Not parity */
-    USART_PARITY_EVEN = 0x2,	/**< Even parity */
-    USART_PARITY_ODD  = 0x3,	/**< Odd parity */
+typedef enum {
+	USART_PARITY_NONE = 0x0U,	/**< Not parity */
+	USART_PARITY_EVEN = 0x2U,	/**< Even parity */
+	USART_PARITY_ODD  = 0x3U,	/**< Odd parity */
 } usart_parity_t;
 
 /**
   * @brief usart_mode
   */
-typedef enum
-{
-    USART_MODE_RX    = 0x1,		/**< TX mode */
-    USART_MODE_TX    = 0x2,		/**< RX mode */
-    USART_MODE_TX_RX = 0x3,		/**< TX & RX mode */
+typedef enum {
+	USART_MODE_RX    = 0x1U,	/**< TX mode */
+	USART_MODE_TX    = 0x2U,	/**< RX mode */
+	USART_MODE_TX_RX = 0x3U,	/**< TX & RX mode */
 } usart_mode_t;
 
 /**
   * @brief usart_hardware_flow_control
   */
-typedef enum
-{
-    USART_HW_FLOW_CTL_NONE    = 0x0,	/**< Not flow control */
-    USART_HW_FLOW_CTL_RTS     = 0x1,	/**< RTS flow control */
-    USART_HW_FLOW_CTL_CTS     = 0x2,	/**< CTS flow control */
-    USART_HW_FLOW_CTL_RTS_CTS = 0x3,	/**< RTS & CTS flow control */
+typedef enum {
+	USART_HW_FLOW_CTL_NONE    = 0x0U,	/**< Not flow control */
+	USART_HW_FLOW_CTL_RTS     = 0x1U,	/**< RTS flow control */
+	USART_HW_FLOW_CTL_CTS     = 0x2U,	/**< CTS flow control */
+	USART_HW_FLOW_CTL_RTS_CTS = 0x3U,	/**< RTS & CTS flow control */
 } usart_hw_flow_ctl_t;
 
 /**
   * @brief usart_clock
   */
-typedef enum
-{
-    USART_CLOCK_DISABLE = 0x0,	/**< Disable clock output */
-    USART_CLOCK_ENABLE  = 0x1,	/**< Enable clock output */
+typedef enum {
+	USART_CLOCK_DISABLE = 0x0U,	/**< Disable clock output */
+	USART_CLOCK_ENABLE  = 0x1U,	/**< Enable clock output */
 } usart_clock_t;
 
 /**
   * @brief usart_clock_polarity
   */
-typedef enum
-{
-    USART_CPOL_LOW  = 0x0,		/**< Clock polarity low */
-    USART_CPOL_HIGH = 0x1,		/**< Clock polarity high */
+typedef enum {
+	USART_CPOL_LOW  = 0x0U,		/**< Clock polarity low */
+	USART_CPOL_HIGH = 0x1U,		/**< Clock polarity high */
 } usart_cpol_t;
 
 /**
   * @brief usart_clock_phase
   */
-typedef enum
-{
-    USART_CPHA_1EDGE = 0x0,		/**< Clock phase first edge */
-    USART_CPHA_2EDGE = 0x1,		/**< Clock phase second edge */
+typedef enum {
+	USART_CPHA_1EDGE = 0x0U,	/**< Clock phase first edge */
+	USART_CPHA_2EDGE = 0x1U,	/**< Clock phase second edge */
 } usart_cpha_t;
 
 /**
   * @brief usart_last_bit
   */
-typedef enum
-{
-    USART_LAST_BIT_DISABLE = 0x0,	/**< Disable last bit clock output */
-    USART_LAST_BIT_ENABLE  = 0x1,	/**< Enable last bit clock output */
+typedef enum {
+	USART_LAST_BIT_DISABLE = 0x0U,	/**< Disable last bit clock output */
+	USART_LAST_BIT_ENABLE  = 0x1U,	/**< Enable last bit clock output */
 } usart_last_bit_t;
 
 /**
   * @brief usart state structures definition
   */
-typedef enum
-{
-    USART_STATE_RESET      = 0x00,	/**< Peripheral is not initialized */
-    USART_STATE_READY      = 0x01,	/**< Peripheral Initialized and ready for use */
-    USART_STATE_BUSY       = 0x02,	/**< an internal process is ongoing */
-    USART_STATE_BUSY_TX    = 0x11,	/**< Data Transmission process is ongoing */
-    USART_STATE_BUSY_RX    = 0x21,	/**< Data Reception process is ongoing */
-    USART_STATE_BUSY_TX_RX = 0x31,	/**< Data Transmission Reception process is ongoing */
-    USART_STATE_TIMEOUT    = 0x03,	/**< Timeout state */
-    USART_STATE_ERROR      = 0x04,	/**< Error */
+typedef enum {
+	USART_STATE_RESET      = 0x00U,	/**< Peripheral is not initialized */
+	USART_STATE_READY      = 0x01U,	/**< Peripheral Initialized and ready for use */
+	USART_STATE_BUSY       = 0x02U,	/**< an internal process is ongoing */
+	USART_STATE_BUSY_TX    = 0x11U,	/**< Data Transmission process is ongoing */
+	USART_STATE_BUSY_RX    = 0x21U,	/**< Data Reception process is ongoing */
+	USART_STATE_BUSY_TX_RX = 0x31U,	/**< Data Transmission Reception process is ongoing */
+	USART_STATE_TIMEOUT    = 0x03U,	/**< Timeout state */
+	USART_STATE_ERROR      = 0x04U,	/**< Error */
 } usart_state_t;
 
 /**
   * @brief usart error codes
   */
-typedef enum
-{
-    USART_ERROR_NONE = ((uint32_t)0x00),	/**< No error */
-    USART_ERROR_PE   = ((uint32_t)0x01),	/**< Parity error */
-    USART_ERROR_NE   = ((uint32_t)0x02),	/**< Noise error */
-    USART_ERROR_FE   = ((uint32_t)0x04),	/**< frame error */
-    USART_ERROR_ORE  = ((uint32_t)0x08),	/**< Overrun error */
-    USART_ERROR_DMA  = ((uint32_t)0x10),	/**< DMA transfer error */
+typedef enum {
+	USART_ERROR_NONE = ((uint32_t)0x00U),	/**< No error */
+	USART_ERROR_PE   = ((uint32_t)0x01U),	/**< Parity error */
+	USART_ERROR_NE   = ((uint32_t)0x02U),	/**< Noise error */
+	USART_ERROR_FE   = ((uint32_t)0x04U),	/**< frame error */
+	USART_ERROR_ORE  = ((uint32_t)0x08U),	/**< Overrun error */
+	USART_ERROR_DMA  = ((uint32_t)0x10U),	/**< DMA transfer error */
 } usart_error_t;
 
 
 /**
   * @brief usart init structure definition
   */
-typedef struct
-{
-    uint32_t baud;			/**< This member configures the Usart communication baud rate. */
-    usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
-    usart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted. */
-    usart_parity_t parity;		/**< Specifies the parity mode.
+typedef struct {
+	uint32_t baud;			/**< This member configures the Usart communication baud rate. */
+	usart_word_length_t word_length;/**< Specifies the number of data bits transmitted or received in a frame. */
+	usart_stop_bits_t stop_bits;	/**< Specifies the number of stop bits transmitted. */
+	usart_parity_t parity;		/**< Specifies the parity mode.
 					     @note When parity is enabled, the computed parity is inserted
  						   at the MSB position of the transmitted data (9th bit when
  						   the word length is set to 9 data bits; 8th bit when the
 						   word length is set to 8 data bits). */
-    usart_mode_t mode;		/**< Specifies wether the Receive or Transmit mode is enabled or disabled. */
-    usart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled. */
-    type_func_t over_sampling;	/**< Specifies whether the Over sampling 8 is enabled or disabled. */
+	usart_mode_t mode;		/**< Specifies wether the Receive or Transmit mode is enabled or disabled. */
+	usart_hw_flow_ctl_t fctl;	/**< Specifies wether the hardware flow control mode is enabled or disabled. */
 } usart_init_t;
 
 /**
   * @brief  USART handle structure definition
   */
-typedef struct usart_handle_s
-{
-    USART_TypeDef *perh;	/**< USART registers base address */
-    usart_init_t init;	/**< USART communication parameters */
-    uint8_t *tx_buf;	/**< Pointer to USART Tx transfer buffer */
-    uint16_t tx_size;	/**< USART Tx transfer size */
-    uint16_t tx_count;	/**< USART Tx transfer counter */
-    uint8_t *rx_buf;	/**< Pointer to USART Rx transfer buffer */
-    uint16_t rx_size;	/**< USART Rx Transfer size */
-    uint16_t rx_count;	/**< USART Rx Transfer Counter */
+typedef struct usart_handle_s {
+	USART_TypeDef *perh;	/**< USART registers base address */
+	usart_init_t init;	/**< USART communication parameters */
+	uint8_t *tx_buf;	/**< Pointer to USART Tx transfer buffer */
+	uint16_t tx_size;	/**< USART Tx transfer size */
+	uint16_t tx_count;	/**< USART Tx transfer counter */
+	uint8_t *rx_buf;	/**< Pointer to USART Rx transfer buffer */
+	uint16_t rx_size;	/**< USART Rx Transfer size */
+	uint16_t rx_count;	/**< USART Rx Transfer Counter */
 #ifdef ALD_DMA
-    dma_handle_t hdmatx;	/**< USART Tx DMA handle parameters */
-    dma_handle_t hdmarx;	/**< USART Rx DMA handle parameters */
+	dma_handle_t hdmatx;	/**< USART Tx DMA handle parameters */
+	dma_handle_t hdmarx;	/**< USART Rx DMA handle parameters */
 #endif
-    lock_state_t lock;	/**< Locking object */
-    usart_state_t state;	/**< USART communication state */
-    uint32_t err_code;	/**< USART error code */
-
-    void (*tx_cplt_cbk)(struct usart_handle_s *arg);	/**< Tx completed callback */
-    void (*rx_cplt_cbk)(struct usart_handle_s *arg);	/**< Rx completed callback */
-    void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg);	/**< Tx & Rx completed callback */
-    void (*error_cbk)(struct usart_handle_s *arg);		/**< error callback */
+	lock_state_t lock;	/**< Locking object */
+	usart_state_t state;	/**< USART communication state */
+	uint32_t err_code;	/**< USART error code */
+
+	void (*tx_cplt_cbk)(struct usart_handle_s *arg);	/**< Tx completed callback */
+	void (*rx_cplt_cbk)(struct usart_handle_s *arg);	/**< Rx completed callback */
+	void (*tx_rx_cplt_cbk)(struct usart_handle_s *arg);	/**< Tx & Rx completed callback */
+	void (*error_cbk)(struct usart_handle_s *arg);		/**< error callback */
 } usart_handle_t;
 
 
 /**
   * @brief USART clock init structure definition
   */
-typedef struct
-{
-    usart_clock_t clk;		/**< Pecifies whether the USART clock is enable or disable. */
-    usart_cpol_t polarity;		/**< Specifies the steady state of the serial clock. */
-    usart_cpha_t phase;		/**< Specifies the clock transition on which the bit capture is made. */
-    usart_last_bit_t last_bit;	/**< Specifies whether the clock pulse corresponding to the last transmitted
+typedef struct {
+	usart_clock_t clk;		/**< Pecifies whether the USART clock is enable or disable. */
+	usart_cpol_t polarity;		/**< Specifies the steady state of the serial clock. */
+	usart_cpha_t phase;		/**< Specifies the clock transition on which the bit capture is made. */
+	usart_last_bit_t last_bit;	/**< Specifies whether the clock pulse corresponding to the last transmitted
 				             data bit (MSB) has to be output on the SCLK pin in synchronous mode. */
 } usart_clock_init_t;
 
@@ -215,61 +200,56 @@ typedef struct
 /**
   * @brief usart_dma_request
   */
-typedef enum
-{
-    USART_DMA_REQ_TX = (1U << 7),	/**< TX dma bit */
-    USART_DMA_REQ_RX = (1U << 6),	/**< RX dma bit */
+typedef enum {
+	USART_DMA_REQ_TX = (1U << 7),	/**< TX dma bit */
+	USART_DMA_REQ_RX = (1U << 6),	/**< RX dma bit */
 } usart_dma_req_t;
 
 /**
   * @brief usart_wakeup_methods
   */
-typedef enum
-{
-    USART_WAKEUP_IDLE = 0x0,	/**< Wake up the machine when bus-line is idle */
-    USART_WAKEUP_ADDR = 0x1,	/**< Wake up the machine when match the address */
+typedef enum {
+	USART_WAKEUP_IDLE = 0x0U,	/**< Wake up the machine when bus-line is idle */
+	USART_WAKEUP_ADDR = 0x1U,	/**< Wake up the machine when match the address */
 } usart_wakeup_t;
 
 /**
   * @brief usart_IrDA_low_power
   */
-typedef enum
-{
-    USART_IrDA_MODE_NORMAL    = 0x0,		/**< Normal IrDA mode */
-    USART_IrDA_MODE_LOW_POWER = 0x1,		/**< Low-power IrDA mode */
+typedef enum {
+	USART_IrDA_MODE_NORMAL    = 0x0U,		/**< Normal IrDA mode */
+	USART_IrDA_MODE_LOW_POWER = 0x1U,		/**< Low-power IrDA mode */
 } usart_IrDA_mode_t;
 
 /**
   * @brief USART interrupts definition
   */
-typedef enum
-{
-    USART_IT_PE   = ((1U << 8) | (1U << 16)),	/**< Parity error */
-    USART_IT_TXE  = ((1U << 7) | (1U << 16)),	/**< Tx empty */
-    USART_IT_TC   = ((1U << 6) | (1U << 16)),	/**< Tx complete */
-    USART_IT_RXNE = ((1U << 5) | (1U << 16)),	/**< Rx not empty */
-    USART_IT_IDLE = ((1U << 4) | (1U << 16)),	/**< Idle */
-    USART_IT_CTS  = ((1U << 10) | (1U << 18)),	/**< CTS */
-    USART_IT_ERR  = ((1U << 0) | (1U << 18)),	/**< Error */
-    USART_IT_ORE  = (1U << 3),			/**< Overrun error */
-    USART_IT_NE   = (1U << 2),			/**< Noise error */
-    USART_IT_FE   = (1U << 0),			/**< Frame error */
+typedef enum {
+	USART_IT_PE   = ((1U << 8) | (1U << 16)),	/**< Parity error */
+	USART_IT_TXE  = ((1U << 7) | (1U << 16)),	/**< Tx empty */
+	USART_IT_TC   = ((1U << 6) | (1U << 16)),	/**< Tx complete */
+	USART_IT_RXNE = ((1U << 5) | (1U << 16)),	/**< Rx not empty */
+	USART_IT_IDLE = ((1U << 4) | (1U << 16)),	/**< Idle */
+	USART_IT_CTS  = ((1U << 10)| (1U << 18)),	/**< CTS */
+	USART_IT_ERR  = ((1U << 0) | (1U << 18)),	/**< Error */
+	USART_IT_ORE  = (1U << 3),			/**< Overrun error */
+	USART_IT_NE   = (1U << 2),			/**< Noise error */
+	USART_IT_FE   = (1U << 0),			/**< Frame error */
 } usart_it_t;
 
 /**
   * @brief USART flags
   */
-typedef enum
-{
-    USART_FLAG_CTS  = (1U << 9),	/**< CTS */
-    USART_FLAG_TXE  = (1U << 7),	/**< Tx empty */
-    USART_FLAG_TC   = (1U << 6),	/**< Tx complete */
-    USART_FLAG_RXNE = (1U << 5),	/**< Rx not empty */
-    USART_FLAG_IDLE = (1U << 4),	/**< Idle */
-    USART_FLAG_ORE  = (1U << 3),	/**< Overrun error */
-    USART_FLAG_NE   = (1U << 2),	/**< Noise error */
-    USART_FLAG_FE   = (1U << 1),	/**< Frame error */
-    USART_FLAG_PE   = (1U << 0),	/**< Parity error */
+typedef enum {
+	USART_FLAG_CTS  = (1U << 9),	/**< CTS */
+	USART_FLAG_TXE  = (1U << 7),	/**< Tx empty */
+	USART_FLAG_TC   = (1U << 6),	/**< Tx complete */
+	USART_FLAG_RXNE = (1U << 5),	/**< Rx not empty */
+	USART_FLAG_IDLE = (1U << 4),	/**< Idle */
+	USART_FLAG_ORE  = (1U << 3),	/**< Overrun error */
+	USART_FLAG_NE   = (1U << 2),	/**< Noise error */
+	USART_FLAG_FE   = (1U << 1),	/**< Frame error */
+	USART_FLAG_PE   = (1U << 0),	/**< Parity error */
 } usart_flag_t;
 
 /**
@@ -293,12 +273,12 @@ typedef enum
   * @{
   */
 #define USART_CLEAR_PEFLAG(handle)	\
-    do {					\
-        __IO uint32_t tmpreg;		\
-        tmpreg = (handle)->perh->STAT;	\
-        tmpreg = (handle)->perh->DATA;	\
-        UNUSED(tmpreg);			\
-    } while (0)
+do {					\
+	__IO uint32_t tmpreg;		\
+	tmpreg = (handle)->perh->STAT;	\
+	tmpreg = (handle)->perh->DATA;	\
+	UNUSED(tmpreg);			\
+} while (0)
 /**
   * @}
   */
@@ -339,7 +319,7 @@ typedef enum
   * @{
   */
 #define USART_HWCONTROL_CTS_ENABLE(handle)	\
-    (SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK))
+	(SET_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK))
 /**
   * @}
   */
@@ -348,7 +328,7 @@ typedef enum
   * @{
   */
 #define USART_HWCONTROL_CTS_DISABLE(handle)	\
-    (CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK))
+	(CLEAR_BIT((handle)->perh->CON2, USART_CON2_CTSEN_MSK))
 /**
   * @}
   */
@@ -357,7 +337,7 @@ typedef enum
   * @{
   */
 #define USART_HWCONTROL_RTS_ENABLE(handle)	\
-    (SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK))
+	(SET_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK))
 /**
   * @}
   */
@@ -366,7 +346,7 @@ typedef enum
   * @{
   */
 #define USART_HWCONTROL_RTS_DISABLE(handle)	\
-    (CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK))
+	(CLEAR_BIT((handle)->perh->CON2, USART_CON2_RTSEN_MSK))
 /**
   * @}
   */
@@ -383,9 +363,9 @@ typedef enum
   * @{
   */
 #define USART_DISABLE(handle)	(CLEAR_BIT((handle)->perh->CON0, USART_CON0_EN_MSK))
-/**
- * @}
- */
+ /**
+  * @}
+  */
 
 /**
   * @}
@@ -406,13 +386,13 @@ typedef enum
                             ((x) == USART_PARITY_EVEN) || \
                             ((x) == USART_PARITY_ODD))
 #define IS_USART_MODE(x) (((x) == USART_MODE_RX) || \
-                          ((x) == USART_MODE_TX) || \
-                          ((x) == USART_MODE_TX_RX))
+			  ((x) == USART_MODE_TX) || \
+			  ((x) == USART_MODE_TX_RX))
 #define IS_USART_HARDWARE_FLOW_CONTROL(x)\
-    (((x) == USART_HW_FLOW_CTL_NONE) || \
-     ((x) == USART_HW_FLOW_CTL_RTS)  || \
-     ((x) == USART_HW_FLOW_CTL_CTS)  || \
-     ((x) == USART_HW_FLOW_CTL_RTS_CTS))
+                              (((x) == USART_HW_FLOW_CTL_NONE) || \
+                               ((x) == USART_HW_FLOW_CTL_RTS)  || \
+                               ((x) == USART_HW_FLOW_CTL_CTS)  || \
+                               ((x) == USART_HW_FLOW_CTL_RTS_CTS))
 #define IS_USART_CLOCK(x) (((x) == USART_CLOCK_DISABLE) || \
                            ((x) == USART_CLOCK_ENABLE))
 #define IS_USART_CPOL(x) (((x) == USART_CPOL_LOW) || ((x) == USART_CPOL_HIGH))
@@ -436,7 +416,7 @@ typedef enum
                             ((x) == USART_IT_NE) || ((x) == USART_IT_FE)    || \
                             ((x) == USART_IT_ERR))
 #define IS_USART_CLEAR_IT(x) (((x) == USART_IT_TC) || ((x) == USART_IT_RXNE) || \
-                              ((x) == USART_IT_CTS))
+                               ((x) == USART_IT_CTS))
 
 #define IS_USART_FLAG(x) (((x) == USART_FLAG_PE) || ((x) == USART_FLAG_TXE)   || \
                           ((x) == USART_FLAG_TC) || ((x) == USART_FLAG_RXNE)  || \
@@ -450,8 +430,8 @@ typedef enum
 #define IS_USART_ADDRESS(x)	((x) <= 0xF)
 #define IS_USART_DATA(x)	((x) <= 0x1FF)
 #define DUMMY_DATA		0xFFFF
-#define USART_STATE_TX_MASK	(1 << 4)
-#define USART_STATE_RX_MASK	(1 << 5)
+#define USART_STATE_TX_MASK	(1U << 4)
+#define USART_STATE_RX_MASK	(1U << 5)
 
 /**
   * @}
@@ -509,7 +489,7 @@ ald_status_t ald_usart_send_recv_by_it_sync(usart_handle_t *hperh, uint8_t *tx_b
 ald_status_t ald_usart_send_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
 ald_status_t ald_usart_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
 ald_status_t ald_usart_send_recv_by_dma_sync(usart_handle_t *hperh, uint8_t *tx_buf,
-        uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
+                    uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
 #endif
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/ald_wdt.h

@@ -38,12 +38,11 @@ extern "C" {
 /**
   * @brief Wwdt no dog window
   */
-typedef enum
-{
-    WWDT_WIN_25 = 0x0,	/**< No dog window size: 25% */
-    WWDT_WIN_50 = 0x1,	/**< No dog window size: 50% */
-    WWDT_WIN_75 = 0x2,	/**< No dog window size: 75% */
-    WWDT_WIN_00 = 0x3,	/**< No dog window size: 0% */
+typedef enum {
+	WWDT_WIN_25 = 0x0U,	/**< No dog window size: 25% */
+	WWDT_WIN_50 = 0x1U,	/**< No dog window size: 50% */
+	WWDT_WIN_75 = 0x2U,	/**< No dog window size: 75% */
+	WWDT_WIN_00 = 0x3U,	/**< No dog window size: 0% */
 } wwdt_win_t;
 
 /**
@@ -54,10 +53,10 @@ typedef enum
  * @defgroup WDT_Private_Macros WDT Private Macros
  * @{
  */
-#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551);}
-#define WWDT_LOCK()   {WRITE_REG(WWDT->LOCK, 0xFFFFFFFF);}
-#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551);}
-#define IWDT_LOCK()   {WRITE_REG(IWDT->LOCK, 0xFFFFFFFF);}
+#define WWDT_UNLOCK() {WRITE_REG(WWDT->LOCK, 0x1ACCE551U);}
+#define WWDT_LOCK()   {WRITE_REG(WWDT->LOCK, 0xFFFFFFFFU);}
+#define IWDT_UNLOCK() {WRITE_REG(IWDT->LOCK, 0x1ACCE551U);}
+#define IWDT_LOCK()   {WRITE_REG(IWDT->LOCK, 0xFFFFFFFFU);}
 
 /**
  * @}
@@ -72,7 +71,7 @@ typedef enum
                                  (x == WWDT_WIN_75) || \
                                  (x == WWDT_WIN_00))
 #define IS_FUNC_STATE(x)	(((x) == DISABLE) || \
-                             ((x) == ENABLE))
+				 ((x) == ENABLE))
 /**
  * @}
  */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/type.h

@@ -34,41 +34,36 @@ extern "C" {
 
 #define __isr__
 
-typedef enum
-{
-    RESET = 0x0,
-    SET   = 0x1,
+typedef enum {
+	RESET = 0x0U,
+	SET   = 0x1U,
 } flag_status_t, it_status_t;
 
-typedef enum
-{
-    BIT_RESET = 0x0,
-    BIT_SET   = 0x1,
+typedef enum {
+	BIT_RESET = 0x0U,
+	BIT_SET   = 0x1U,
 } bit_status_t;
 
-typedef enum
-{
-    DISABLE = 0x0,
-    ENABLE  = 0x1,
+typedef enum {
+	DISABLE = 0x0U,
+	ENABLE  = 0x1U,
 } type_func_t;
 #define IS_FUNC_STATE(x)	(((x) == DISABLE) || ((x) == ENABLE))
 
-typedef enum
-{
-    FALSE = 0x0,
-    TRUE  = 0x1,
+typedef enum {
+	FALSE = 0x0U,
+	TRUE  = 0x1U,
 } type_bool_t;
 
-typedef enum
-{
-    UNLOCK = 0x0,
-    LOCK   = 0x1,
+typedef enum {
+	UNLOCK = 0x0U,
+	LOCK   = 0x1U,
 } lock_state_t;
 #define IS_LOCK_STATE(x)	(((x) == UNLOCK) || ((x) == LOCK))
 
 
 #define BIT(x)			((1U << (x)))
-#define BITS(s, e)		((0xffffffff << (s)) & (0xffffffff >> (31 - (e))))
+#define BITS(s, e)		((0xffffffffU << (s)) & (0xffffffffU >> (31 - (e))))
 #define SET_BIT(reg, bit)	((reg) |= (bit))
 #define CLEAR_BIT(reg, bit)	((reg) &= ~(bit))
 #define READ_BIT(reg, bit)	((reg) & (bit))
@@ -77,18 +72,18 @@ typedef enum
 #define WRITE_REG(reg, val)	((reg) = (val))
 #define READ_REG(reg)		((reg))
 #define MODIFY_REG(reg, clearmask, setmask)	\
-    WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
+	WRITE_REG((reg), (((READ_REG(reg)) & (~(clearmask))) | (setmask)))
 #define UNUSED(x)	((void)(x))
 
 #ifdef USE_ASSERT
 #define assert_param(x)			\
-    do {					\
-        if (!(x)) {			\
-            __disable_irq();	\
-            while (1)		\
-                ;		\
-        }				\
-    } while (0)
+do {					\
+	if (!(x)) {			\
+		__disable_irq();	\
+		while (1)		\
+			;		\
+	}				\
+} while (0)
 #else
 #define assert_param(x)
 #endif
@@ -101,23 +96,23 @@ typedef enum
 
 __STATIC_INLINE__ void BITBAND_PER(volatile uint32_t *addr, uint32_t bit, uint32_t val)
 {
-    uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
-    *((volatile uint32_t *)tmp) = (uint32_t)val;
+	uint32_t tmp = BITBAND_PER_BASE + (((uint32_t)addr - PER_MEM_BASE) << 5) + (bit << 2);
+	*((volatile uint32_t *)tmp) = (uint32_t)val;
 }
 
 __STATIC_INLINE__ void BITBAND_SRAM(uint32_t *addr, uint32_t bit, uint32_t val)
 {
-    uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
-    *((volatile uint32_t *)tmp) = (uint32_t)val;
+	uint32_t tmp = BITBAND_RAM_BASE + (((uint32_t)addr - RAM_MEM_BASE) << 5) + (bit << 2);
+	*((volatile uint32_t *)tmp) = (uint32_t)val;
 }
 
 #if defined ( __GNUC__ )
-#ifndef __weak
-#define __weak   __attribute__((weak))
-#endif	/* __weak */
-#ifndef __packed
-#define __packed __attribute__((__packed__))
-#endif	/* __packed */
+	#ifndef __weak
+		#define __weak   __attribute__((weak))
+	#endif	/* __weak */
+	#ifndef __packed
+		#define __packed __attribute__((__packed__))
+	#endif	/* __packed */
 #endif /* __GNUC__ */
 
 #ifdef __cplusplus

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Include/utils.h

@@ -18,7 +18,7 @@
 #define __UTILS_H__
 
 #ifdef __cplusplus
-extern "C" {
+ extern "C" {
 #endif
 
 #include <stdlib.h>
@@ -46,23 +46,21 @@ extern uint32_t __systick_interval;
 /**
   * @brief  ALD Status structures definition
   */
-typedef enum
-{
-    OK      = 0x0,
-    ERROR   = 0x1,
-    BUSY    = 0x2,
-    TIMEOUT = 0x3
+typedef enum {
+	OK      = 0x0U,	/**< Status: OK */
+	ERROR   = 0x1U,	/**< Status: ERROR */
+	BUSY    = 0x2U,	/**< Status: BUSY */
+	TIMEOUT = 0x3U,	/**< Status: TIMEOUT */
 } ald_status_t;
 
 /**
   * @brief  SysTick interval definition
   */
-typedef enum
-{
-    SYSTICK_INTERVAL_1MS    = 1000,	/**< Interval is 1ms */
-    SYSTICK_INTERVAL_10MS   = 100,	/**< Interval is 10ms */
-    SYSTICK_INTERVAL_100MS  = 10,	/**< Interval is 100ms */
-    SYSTICK_INTERVAL_1000MS = 1,	/**< Interval is 1s */
+typedef enum {
+	SYSTICK_INTERVAL_1MS    = 1000U,	/**< Interval is 1ms */
+	SYSTICK_INTERVAL_10MS   = 100U,		/**< Interval is 10ms */
+	SYSTICK_INTERVAL_100MS  = 10U,		/**< Interval is 100ms */
+	SYSTICK_INTERVAL_1000MS = 1U,		/**< Interval is 1s */
 } systick_interval_t;
 /**
   * @}
@@ -71,25 +69,24 @@ typedef enum
 /** @defgroup ALD_Public_Macros Public Macros
   * @{
   */
-#define ALD_MAX_DELAY	0xFFFFFFFF
-
+#define ALD_MAX_DELAY	0xFFFFFFFFU
 #define IS_BIT_SET(reg, bit)	(((reg) & (bit)) != RESET)
 #define IS_BIT_CLR(reg, bit)	(((reg) & (bit)) == RESET)
 #define RESET_HANDLE_STATE(x)	((x)->state = 0)
 #define __LOCK(x)				\
-    do {					\
-        if ((x)->lock == LOCK) {	\
-            return BUSY;		\
-        }				\
-        else {				\
-            (x)->lock = LOCK;	\
-        }				\
-    } while (0)
+	do {					\
+		if ((x)->lock == LOCK) {	\
+			return BUSY;		\
+		}				\
+		else {				\
+			(x)->lock = LOCK;	\
+		}				\
+	} while (0)
 
 #define __UNLOCK(x)				\
-    do {					\
-        (x)->lock = UNLOCK;		\
-    } while (0)
+	do {					\
+		(x)->lock = UNLOCK;		\
+	} while (0)
 
 /**
   * @}
@@ -98,6 +95,10 @@ typedef enum
 /** @defgroup ALD_Private_Macros Private Macros
   * @{
   */
+#define MCU_UID0_ADDR	0x000403E0U
+#define MCU_UID1_ADDR	0x000403E8U
+#define MCU_UID2_ADDR	0x000403F0U
+#define MCU_CHIPID_ADDR	0x000403F8U
 #define IS_PRIO(x)	((x) < 4)
 #define IS_SYSTICK_INTERVAL(x)	(((x) == SYSTICK_INTERVAL_1MS)   || \
                                  ((x) == SYSTICK_INTERVAL_10MS)  || \
@@ -140,7 +141,8 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui
 void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status);
 uint32_t ald_mcu_get_tick(void);
 uint32_t ald_mcu_get_cpu_id(void);
-
+void ald_mcu_get_uid(uint8_t *buf);
+uint32_t ald_mcu_get_chipid(void);
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_acmp.c

@@ -44,86 +44,82 @@
   */
 ald_status_t ald_acmp_init(acmp_handle_t *hperh)
 {
-    uint32_t tmp = 0;
+	uint32_t tmp = 0;
 
-    if (hperh == NULL)
-        return ERROR;
+	if (hperh == NULL)
+		return ERROR;
 
-    if (hperh->init.vdd_level > 63)
-        return ERROR;
+	if (hperh->init.vdd_level > 63)
+		return ERROR;
 
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
-    assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
-    assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
-    assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func));
-    assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port));
-    assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port));
-    assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
-    assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_MODE_TYPE(hperh->init.mode));
+	assert_param(IS_ACMP_WARM_UP_TIME_TYPE(hperh->init.warm_time));
+	assert_param(IS_ACMP_HYSTSEL_TYPE(hperh->init.hystsel));
+	assert_param(IS_ACMP_WARM_FUNC_TYPE(hperh->init.warm_func));
+	assert_param(IS_ACMP_POS_INPUT_TYPE(hperh->init.pos_port));
+	assert_param(IS_ACMP_NEG_INPUT_TYPE(hperh->init.neg_port));
+	assert_param(IS_ACMP_INACTVAL_TYPE(hperh->init.inactval));
+	assert_param(IS_ACMP_EDGE_TYPE(hperh->init.edge));
 
-    __LOCK(hperh);
+	__LOCK(hperh);
 
-    tmp = hperh->perh->CON;
+	tmp = hperh->perh->CON;
 
-    tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
-            (hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS));
+	tmp |= ((hperh->init.mode << ACMP_CON_MODSEL_POSS) | (hperh->init.warm_time << ACMP_CON_WARMUPT_POSS) |
+		(hperh->init.inactval << ACMP_CON_INACTV_POS) | (hperh->init.hystsel << ACMP_CON_HYSTSEL_POSS));
 
-    hperh->perh->CON = tmp;
+	hperh->perh->CON = tmp;
 
-    tmp = hperh->perh->INPUTSEL;
+	tmp = hperh->perh->INPUTSEL;
 
-    tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) |
-            (hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
+	tmp |= ((hperh->init.pos_port << ACMP_INPUTSEL_PSEL_POSS) | (hperh->init.neg_port << ACMP_INPUTSEL_NSEL_POSS) |
+		(hperh->init.vdd_level << ACMP_INPUTSEL_VDDLVL_POSS));
 
-    hperh->perh->INPUTSEL = tmp;
+	hperh->perh->INPUTSEL = tmp;
 
-    if (hperh->init.warm_func == ACMP_WARM_DISABLE)
-        CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
-    else
-        SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
+	if (hperh->init.warm_func == ACMP_WARM_DISABLE)
+		CLEAR_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
+	else
+		SET_BIT(hperh->perh->IES, ACMP_IES_WARMUP_MSK);
 
-    switch (hperh->init.edge)
-    {
-        case ACMP_EDGE_NONE:
-            CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-            CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-            break;
+	switch (hperh->init.edge) {
+	case ACMP_EDGE_NONE:
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
 
-        case ACMP_EDGE_FALL:
-            SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-            CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-            break;
+	case ACMP_EDGE_FALL:
+		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
 
-        case ACMP_EDGE_RISE:
-            CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-            SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-            break;
+	case ACMP_EDGE_RISE:
+		CLEAR_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
 
-        case ACMP_EDGE_ALL:
-            SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
-            SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
-            break;
+	case ACMP_EDGE_ALL:
+		SET_BIT(hperh->perh->CON, ACMP_CON_FALLEN_MSK);
+		SET_BIT(hperh->perh->CON, ACMP_CON_RISEEN_MSK);
+		break;
 
-        default:
-            break;
-    }
+	default:
+		break;
+	}
 
-    SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
+	SET_BIT(hperh->perh->CON, ACMP_CON_EN_MSK);
 
-    tmp = 0;
+	tmp = 0;
+	while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0) {
+		if (tmp++ >= 600000) {
+			__UNLOCK(hperh);
+			return ERROR;
+		}
+	}
 
-    while (READ_BIT(hperh->perh->STAT, ACMP_STAT_ACT_MSK) == 0)
-    {
-        if (tmp++ >= 600000)
-        {
-            __UNLOCK(hperh);
-            return ERROR;
-        }
-    }
-
-    __UNLOCK(hperh);
-    return OK;
+	__UNLOCK(hperh);
+	return OK;
 }
 /**
   * @}
@@ -147,20 +143,20 @@ ald_status_t ald_acmp_init(acmp_handle_t *hperh)
   */
 ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_func_t state)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_IT_TYPE(it));
-    assert_param(IS_FUNC_STATE(state));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_IT_TYPE(it));
+	assert_param(IS_FUNC_STATE(state));
 
-    __LOCK(hperh);
+	__LOCK(hperh);
 
-    if (state)
-        hperh->perh->IES |= it;
-    else
-        hperh->perh->IEC |= it;
+	if (state)
+		hperh->perh->IES |= it;
+	else
+		hperh->perh->IEC |= it;
 
-    __UNLOCK(hperh);
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -175,13 +171,13 @@ ald_status_t ald_acmp_interrupt_config(acmp_handle_t *hperh, acmp_it_t it, type_
   */
 it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_IT_TYPE(it));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_IT_TYPE(it));
 
-    if (hperh->perh->IEV & it)
-        return SET;
-    else
-        return RESET;
+	if (hperh->perh->IEV & it)
+		return SET;
+	else
+		return RESET;
 }
 
 /**
@@ -196,16 +192,15 @@ it_status_t ald_acmp_get_it_status(acmp_handle_t *hperh, acmp_it_t it)
   */
 it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_FLAG_TYPE(flag));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_FLAG_TYPE(flag));
 
-    if (hperh->perh->RIF & flag)
-    {
-        __UNLOCK(hperh);
-        return SET;
-    }
+	if (hperh->perh->RIF & flag) {
+		__UNLOCK(hperh);
+		return SET;
+	}
 
-    return RESET;
+	return RESET;
 }
 
 /** @brief  Clear the specified ACMP it flags.
@@ -217,14 +212,14 @@ it_status_t ald_acmp_get_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
   */
 ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_FLAG_TYPE(flag));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_FLAG_TYPE(flag));
 
-    __LOCK(hperh);
-    hperh->perh->IFC |= flag;
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	hperh->perh->IFC |= flag;
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /** @brief  Set the specified acmp it flags.
@@ -236,14 +231,14 @@ ald_status_t ald_acmp_clear_flag_status(acmp_handle_t *hperh, acmp_flag_t flag)
   */
 ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_IT_TYPE(it));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_IT_TYPE(it));
 
-    __LOCK(hperh);
-    hperh->perh->IFM |= it;
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	hperh->perh->IFM |= it;
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /** @brief  Check whether the specified ACMP flag is set or not.
@@ -257,16 +252,15 @@ ald_status_t acmp_set_it_mask(acmp_handle_t *hperh, acmp_it_t it)
   */
 flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_STATUS_TYPE(status));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_STATUS_TYPE(status));
 
-    if (hperh->perh->STAT & status)
-    {
-        __UNLOCK(hperh);
-        return SET;
-    }
+	if (hperh->perh->STAT & status) {
+		__UNLOCK(hperh);
+		return SET;
+	}
 
-    return RESET;
+	return RESET;
 }
 /**
   * @}
@@ -285,23 +279,19 @@ flag_status_t ald_acmp_get_status(acmp_handle_t *hperh, acmp_status_t status)
   */
 void ald_acmp_irq_handler(acmp_handle_t *hperh)
 {
-    if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET))
-    {
-        if (hperh->acmp_warmup_cplt_cbk)
-            hperh->acmp_warmup_cplt_cbk(hperh);
-
-        ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
-    }
-
-    if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET))
-    {
-        if (hperh->acmp_edge_cplt_cbk)
-            hperh->acmp_edge_cplt_cbk(hperh);
-
-        ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
-    }
-
-    return;
+	if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_WARMUP) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_WARMUP) == SET)) {
+		if (hperh->acmp_warmup_cplt_cbk)
+			hperh->acmp_warmup_cplt_cbk(hperh);
+		ald_acmp_clear_flag_status(hperh, ACMP_FLAG_WARMUP);
+	}
+
+	if ((ald_acmp_get_flag_status(hperh, ACMP_FLAG_EDGE) == SET) && (ald_acmp_get_it_status(hperh, ACMP_IT_EDGE) == SET)) {
+		if (hperh->acmp_edge_cplt_cbk)
+			hperh->acmp_edge_cplt_cbk(hperh);
+		ald_acmp_clear_flag_status(hperh, ACMP_FLAG_EDGE);
+	}
+
+	return;
 }
 
 /**
@@ -314,22 +304,22 @@ void ald_acmp_irq_handler(acmp_handle_t *hperh)
   */
 ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *config)
 {
-    if (hperh == NULL)
-        return ERROR;
+	if (hperh == NULL)
+		return ERROR;
 
-    if (config == NULL)
-        return ERROR;
+	if (config == NULL)
+		return ERROR;
 
-    assert_param(IS_ACMP_TYPE(hperh->perh));
-    assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv));
-    assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_INVERT_TYPE(config->gpio_inv));
+	assert_param(IS_ACMP_OUT_FUNC_TYPE(config->out_func));
 
-    __LOCK(hperh);
-    hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS);
-    hperh->perh->PORT = config->out_func;
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	hperh->perh->CON |= (config->gpio_inv << ACMP_CON_OUTINV_POS);
+	hperh->perh->PORT = config->out_func;
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -340,9 +330,9 @@ ald_status_t ald_acmp_out_config(acmp_handle_t *hperh, acmp_output_config_t *con
   */
 uint8_t ald_acmp_out_result(acmp_handle_t *hperh)
 {
-    assert_param(IS_ACMP_TYPE(hperh->perh));
+	assert_param(IS_ACMP_TYPE(hperh->perh));
 
-    return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
+	return (READ_BIT(hperh->perh->STAT, ACMP_STAT_OUT_MSK) >> ACMP_STAT_OUT_POS);
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_bkpc.c

@@ -41,7 +41,7 @@
   ==============================================================================
   [..]  This section provides functions allowing to:
     (+) ald_bkpc_ldo_config() API can configure LDO in backup field.
-    (+) ald_bkpc_bor_config() API can configure BOR in backup field.
+    (+) ald_bkpc_standby_wakeup_config() API can configure STANDBY wakeup.
 
     @endverbatim
   * @{
@@ -55,40 +55,44 @@
   */
 void ald_bkpc_ldo_config(bkpc_ldo_output_t output, type_func_t state)
 {
-    assert_param(IS_BKPC_LDO_OUTPUT(output));
-    assert_param(IS_FUNC_STATE(state));
+	assert_param(IS_BKPC_LDO_OUTPUT(output));
+	assert_param(IS_FUNC_STATE(state));
 
-    BKPC_UNLOCK();
-    MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS);
+	BKPC_UNLOCK();
+	MODIFY_REG(BKPC->CR, BKPC_CR_MT_STDB_MSK, state << BKPC_CR_MT_STDB_POS);
 
-    if (state)
-        MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS);
+	if (state)
+		MODIFY_REG(BKPC->CR, BKPC_CR_LDO_VSEL_MSK, output << BKPC_CR_LDO_VSEL_POSS);
 
-    BKPC_LOCK();
-    return;
+	BKPC_LOCK();
+	return;
 }
 
 /**
-  * @brief  Configure bor voltage in backup field
-  * @param  vol: Voltage select.
-  * @param  state: DISABLE/ENABLE.
+  * @brief  Configure standby wakeup in backup field
+  * @param  port: Wakeup port
+  * @param  level: HIGH/LOW.
   * @retval None
   */
-void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state)
+void ald_bkpc_standby_wakeup_config(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
 {
-    assert_param(IS_BKPC_BOR_VOL(vol));
-    assert_param(IS_FUNC_STATE(state));
-
-    BKPC_UNLOCK();
-    MODIFY_REG(BKPC->PCR, BKPC_PCR_BOREN_MSK, state << BKPC_PCR_BOREN_POS);
-
-    if (state)
-        MODIFY_REG(BKPC->PCR, BKPC_PCR_BORS_MSK, vol << BKPC_PCR_BORS_POSS);
-
-    BKPC_LOCK();
-    return;
-
-
+	assert_param(IS_BKPC_WAKEUP_PORT(port));
+	assert_param(IS_BKPC_WAKEUP_LEVEL(level));
+
+	if (port == PMU_STANDBY_PORT_SEL_NONE) {
+		BKPC_UNLOCK();
+		CLEAR_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
+		BKPC_LOCK();
+		return;
+	}
+
+	BKPC_UNLOCK();
+	SET_BIT(BKPC->CR, BKPC_CR_WKPEN_MSK);
+	MODIFY_REG(BKPC->CR, BKPC_CR_WKPS_MSK, port << BKPC_CR_WKPS_POSS);
+	MODIFY_REG(BKPC->CR, BKPC_CR_WKPOL_MSK, level << BKPC_CR_WKPOL_POS);
+	BKPC_LOCK();
+
+	return;
 }
 /**
   * @}
@@ -117,13 +121,13 @@ void ald_bkpc_bor_config(bkpc_bor_vol_t vol, type_func_t state)
   */
 void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
 {
-    assert_param(IS_BKPC_RAM_IDX(idx));
+	assert_param(IS_BKPC_RAM_IDX(idx));
 
-    RTC_UNLOCK();
-    WRITE_REG(RTC->BKPR[idx], value);
-    RTC_LOCK();
+	RTC_UNLOCK();
+	WRITE_REG(RTC->BKPR[idx], value);
+	RTC_LOCK();
 
-    return;
+	return;
 }
 
 /**
@@ -133,9 +137,9 @@ void ald_bkpc_write_ram(uint8_t idx, uint32_t value)
   */
 uint32_t ald_bkpc_read_ram(uint8_t idx)
 {
-    assert_param(IS_BKPC_RAM_IDX(idx));
+	assert_param(IS_BKPC_RAM_IDX(idx));
 
-    return READ_REG(RTC->BKPR[idx]);
+	return READ_REG(RTC->BKPR[idx]);
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_calc.c

@@ -45,16 +45,15 @@
 
 /**
   * @brief  Square root operation.
-  * @param  data: The data;
+  * @param  data: The radicand
   * @retval The value of square root.
   */
 uint32_t ald_calc_sqrt(uint32_t data)
 {
-    WRITE_REG(CALC->RDCND, data);
+	WRITE_REG(CALC->RDCND, data);
+	while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
 
-    while (READ_BIT(CALC->SQRTSR, CALC_SQRTSR_BUSY_MSK));
-
-    return READ_REG(CALC->SQRTRES);
+	return READ_REG(CALC->SQRTRES);
 }
 
 /**
@@ -66,15 +65,15 @@ uint32_t ald_calc_sqrt(uint32_t data)
   */
 uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder)
 {
-    CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
-    SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
-    WRITE_REG(CALC->DIVDR, dividend);
-    WRITE_REG(CALC->DIVSR, divisor);
+	CLEAR_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
+	SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
+	WRITE_REG(CALC->DIVDR, dividend);
+	WRITE_REG(CALC->DIVSR, divisor);
 
-    while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
+	while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
 
-    *remainder = READ_REG(CALC->DIVRR);
-    return READ_REG(CALC->DIVQR);
+	*remainder = READ_REG(CALC->DIVRR);
+	return READ_REG(CALC->DIVQR);
 }
 
 /**
@@ -86,15 +85,15 @@ uint32_t ald_calc_div(uint32_t dividend, uint32_t divisor, uint32_t *remainder)
   */
 int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder)
 {
-    SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
-    SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
-    WRITE_REG(CALC->DIVDR, dividend);
-    WRITE_REG(CALC->DIVSR, divisor);
+	SET_BIT(CALC->DIVCSR, CALC_DIVCSR_SIGN_MSK);
+	SET_BIT(CALC->DIVCSR, CALC_DIVCSR_TRM_MSK);
+	WRITE_REG(CALC->DIVDR, dividend);
+	WRITE_REG(CALC->DIVSR, divisor);
 
-    while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
+	while (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_BUSY_MSK));
 
-    *remainder = READ_REG(CALC->DIVRR);
-    return READ_REG(CALC->DIVQR);
+	*remainder = READ_REG(CALC->DIVRR);
+	return READ_REG(CALC->DIVQR);
 }
 
 /**
@@ -103,10 +102,10 @@ int32_t ald_calc_div_sign(int32_t dividend, int32_t divisor, int32_t *remainder)
   */
 flag_status_t ald_calc_get_dz_status(void)
 {
-    if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK))
-        return SET;
+	if (READ_BIT(CALC->DIVCSR, CALC_DIVCSR_DZ_MSK))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_crc.c

@@ -31,8 +31,8 @@
   */
 void ald_crc_reset(crc_handle_t *hperh);
 #ifdef ALD_DMA
-    static void crc_dma_calculate_cplt(void *arg);
-    static void crc_dma_error(void *arg);
+static void crc_dma_calculate_cplt(void *arg);
+static void crc_dma_error(void *arg);
 #endif
 /**
   * @}
@@ -57,38 +57,38 @@ void ald_crc_reset(crc_handle_t *hperh);
   */
 ald_status_t ald_crc_init(crc_handle_t *hperh)
 {
-    uint32_t tmp = 0;
+	uint32_t tmp = 0;
 
-    if (hperh == NULL)
-        return ERROR;
+	if (hperh == NULL)
+		return ERROR;
 
-    assert_param(IS_CRC(hperh->perh));
-    assert_param(IS_CRC_MODE(hperh->init.mode));
-    assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
-    assert_param(IS_FUNC_STATE(hperh->init.data_inv));
-    assert_param(IS_FUNC_STATE(hperh->init.data_rev));
-    assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
+	assert_param(IS_CRC(hperh->perh));
+	assert_param(IS_CRC_MODE(hperh->init.mode));
+	assert_param(IS_FUNC_STATE(hperh->init.chs_rev));
+	assert_param(IS_FUNC_STATE(hperh->init.data_inv));
+	assert_param(IS_FUNC_STATE(hperh->init.data_rev));
+	assert_param(IS_FUNC_STATE(hperh->init.chs_inv));
 
-    ald_crc_reset(hperh);
-    __LOCK(hperh);
+	ald_crc_reset(hperh);
+	__LOCK(hperh);
 
-    CRC_ENABLE(hperh);
+	CRC_ENABLE(hperh);
 
-    tmp = hperh->perh->CR;
+	tmp = hperh->perh->CR;
 
-    tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) |
-            (hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
-            (CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
-            (0 << CRC_CR_BYTORD_POS));
+	tmp |= ((hperh->init.chs_rev << CRC_CR_CHSREV_POS) | (hperh->init.data_inv << CRC_CR_DATREV_POS) |
+		(hperh->init.chs_inv << CRC_CR_CHSINV_POS) | (hperh->init.mode << CRC_CR_MODE_POSS) |
+		(CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS) | (hperh->init.data_rev << CRC_CR_DATREV_POS) |
+		(0 << CRC_CR_BYTORD_POS));
 
-    hperh->perh->CR = tmp;
-    hperh->perh->SEED = hperh->init.seed;
-    CRC_RESET(hperh);
+	hperh->perh->CR = tmp;
+	hperh->perh->SEED = hperh->init.seed;
+	CRC_RESET(hperh);
 
-    hperh->state = CRC_STATE_READY;
+	hperh->state = CRC_STATE_READY;
 
-    __UNLOCK(hperh);
-    return OK;
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -110,26 +110,26 @@ ald_status_t ald_crc_init(crc_handle_t *hperh)
   */
 uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
 {
-    uint32_t i;
-    uint32_t ret;
+	uint32_t i;
+	uint32_t ret;
 
-    assert_param(IS_CRC(hperh->perh));
+	assert_param(IS_CRC(hperh->perh));
 
-    if (buf == NULL || size == 0)
-        return 0;
+	if (buf == NULL || size == 0)
+		return 0;
 
-    __LOCK(hperh);
-    MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
-    hperh->state = CRC_STATE_BUSY;
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
+	hperh->state = CRC_STATE_BUSY;
 
-    for (i = 0; i < size; i++)
-        *((volatile uint8_t *) & (hperh->perh->DATA)) = buf[i];
+	for (i = 0; i < size; i++)
+		*((volatile uint8_t *)&(hperh->perh->DATA)) = buf[i];
 
-    ret          = CRC->CHECKSUM;
-    hperh->state = CRC_STATE_READY;
-    __UNLOCK(hperh);
+	ret          = CRC->CHECKSUM;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
 
-    return ret;
+	return ret;
 }
 
 /**
@@ -142,26 +142,26 @@ uint32_t ald_crc_calculate(crc_handle_t *hperh, uint8_t *buf, uint32_t size)
   */
 uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t size)
 {
-    uint32_t i;
-    uint32_t ret;
+	uint32_t i;
+	uint32_t ret;
 
-    assert_param(IS_CRC(hperh->perh));
+	assert_param(IS_CRC(hperh->perh));
 
-    if (buf == NULL || size == 0)
-        return 0;
+	if (buf == NULL || size == 0)
+		return 0;
 
-    __LOCK(hperh);
-    MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
-    hperh->state = CRC_STATE_BUSY;
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
+	hperh->state = CRC_STATE_BUSY;
 
-    for (i = 0; i < size; i++)
-        *((volatile uint16_t *) & (hperh->perh->DATA)) = buf[i];
+	for (i = 0; i < size; i++)
+		*((volatile uint16_t *)&(hperh->perh->DATA)) = buf[i];
 
-    ret          = CRC->CHECKSUM;
-    hperh->state = CRC_STATE_READY;
-    __UNLOCK(hperh);
+	ret          = CRC->CHECKSUM;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
 
-    return ret;
+	return ret;
 }
 
 /**
@@ -174,26 +174,26 @@ uint32_t ald_crc_calculate_halfword(crc_handle_t *hperh, uint16_t *buf, uint32_t
   */
 uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t size)
 {
-    uint32_t i;
-    uint32_t ret;
+	uint32_t i;
+	uint32_t ret;
 
-    assert_param(IS_CRC(hperh->perh));
+	assert_param(IS_CRC(hperh->perh));
 
-    if (buf == NULL || size == 0)
-        return 0;
+	if (buf == NULL || size == 0)
+		return 0;
 
-    __LOCK(hperh);
-    MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
-    hperh->state = CRC_STATE_BUSY;
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
+	hperh->state = CRC_STATE_BUSY;
 
-    for (i = 0; i < size; i++)
-        CRC->DATA = buf[i];
+	for (i = 0; i < size; i++)
+ 		CRC->DATA = buf[i];
 
-    ret          = CRC->CHECKSUM;
-    hperh->state = CRC_STATE_READY;
-    __UNLOCK(hperh);
+	ret          = CRC->CHECKSUM;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
 
-    return ret;
+	return ret;
 }
 
 /**
@@ -218,44 +218,44 @@ uint32_t ald_crc_calculate_word(crc_handle_t *hperh, uint32_t *buf, uint32_t siz
   */
 ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
 {
-    if (hperh->state != CRC_STATE_READY)
-        return BUSY;
+	if (hperh->state != CRC_STATE_READY)
+		return BUSY;
 
-    if (buf == NULL || size == 0)
-        return ERROR;
+	if (buf == NULL || size == 0)
+		return ERROR;
 
-    __LOCK(hperh);
-    MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_8 << CRC_CR_DATLEN_POSS);
 
-    hperh->state = CRC_STATE_BUSY;
+	hperh->state = CRC_STATE_BUSY;
 
-    hperh->cal_buf = buf;
-    hperh->cal_res = res;
+	hperh->cal_buf = buf;
+	hperh->cal_res = res;
 
-    if (hperh->hdma.perh == NULL)
-        hperh->hdma.perh = DMA0;
+	if (hperh->hdma.perh == NULL)
+		hperh->hdma.perh = DMA0;
 
-    hperh->hdma.cplt_arg = (void *)hperh;
-    hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-    hperh->hdma.err_arg  = (void *)hperh;
-    hperh->hdma.err_cbk  = &crc_dma_error;
+	hperh->hdma.cplt_arg = (void *)hperh;
+	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
+	hperh->hdma.err_arg  = (void *)hperh;
+	hperh->hdma.err_cbk  = &crc_dma_error;
 
-    ald_dma_config_struct(&(hperh->hdma.config));
-    hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
-    hperh->hdma.config.src        = (void *)buf;
-    hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-    hperh->hdma.config.size       = size;
-    hperh->hdma.config.src_inc    = DMA_DATA_INC_BYTE;
-    hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-    hperh->hdma.config.msel       = DMA_MSEL_CRC;
-    hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-    hperh->hdma.config.channel    = channel;
-    ald_dma_config_basic(&(hperh->hdma));
+	ald_dma_config_struct(&(hperh->hdma.config));
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_BYTE;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_BYTE;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
+	hperh->hdma.config.msel       = DMA_MSEL_CRC;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = channel;
+	ald_dma_config_basic(&(hperh->hdma));
 
-    __UNLOCK(hperh);
-    CRC_DMA_ENABLE(hperh);
+	__UNLOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -270,44 +270,44 @@ ald_status_t ald_crc_calculate_by_dma(crc_handle_t *hperh, uint8_t *buf, uint32_
   */
 ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
 {
-    if (hperh->state != CRC_STATE_READY)
-        return BUSY;
+	if (hperh->state != CRC_STATE_READY)
+		return BUSY;
 
-    if (buf == NULL || size == 0)
-        return ERROR;
+	if (buf == NULL || size == 0)
+		return ERROR;
 
-    __LOCK(hperh);
-    MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_16 << CRC_CR_DATLEN_POSS);
 
-    hperh->state = CRC_STATE_BUSY;
+	hperh->state = CRC_STATE_BUSY;
 
-    hperh->cal_buf = (uint8_t *)buf;
-    hperh->cal_res = res;
+	hperh->cal_buf = (uint8_t *)buf;
+	hperh->cal_res = res;
 
-    if (hperh->hdma.perh == NULL)
-        hperh->hdma.perh = DMA0;
+	if (hperh->hdma.perh == NULL)
+		hperh->hdma.perh = DMA0;
 
-    hperh->hdma.cplt_arg = (void *)hperh;
-    hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-    hperh->hdma.err_arg  = (void *)hperh;
-    hperh->hdma.err_cbk  = &crc_dma_error;
+	hperh->hdma.cplt_arg = (void *)hperh;
+	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
+	hperh->hdma.err_arg  = (void *)hperh;
+	hperh->hdma.err_cbk  = &crc_dma_error;
 
-    ald_dma_config_struct(&(hperh->hdma.config));
-    hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
-    hperh->hdma.config.src        = (void *)buf;
-    hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-    hperh->hdma.config.size       = size;
-    hperh->hdma.config.src_inc    = DMA_DATA_INC_HALFWORD;
-    hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-    hperh->hdma.config.msel       = DMA_MSEL_CRC;
-    hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-    hperh->hdma.config.channel    = channel;
-    ald_dma_config_basic(&(hperh->hdma));
+	ald_dma_config_struct(&(hperh->hdma.config));
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_HALFWORD;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_HALFWORD;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
+	hperh->hdma.config.msel       = DMA_MSEL_CRC;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = channel;
+	ald_dma_config_basic(&(hperh->hdma));
 
-    __UNLOCK(hperh);
-    CRC_DMA_ENABLE(hperh);
+	__UNLOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -322,44 +322,44 @@ ald_status_t ald_crc_calculate_halfword_by_dma(crc_handle_t *hperh, uint16_t *bu
   */
 ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, uint32_t *res, uint16_t size, uint8_t channel)
 {
-    if (hperh->state != CRC_STATE_READY)
-        return BUSY;
+	if (hperh->state != CRC_STATE_READY)
+		return BUSY;
 
-    if (buf == NULL || size == 0)
-        return ERROR;
+	if (buf == NULL || size == 0)
+		return ERROR;
 
-    __LOCK(hperh);
-    MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
+	__LOCK(hperh);
+	MODIFY_REG(hperh->perh->CR, CRC_CR_DATLEN_MSK, CRC_DATASIZE_32 << CRC_CR_DATLEN_POSS);
 
-    hperh->state = CRC_STATE_BUSY;
+	hperh->state = CRC_STATE_BUSY;
 
-    hperh->cal_buf = (uint8_t *)buf;
-    hperh->cal_res = res;
+	hperh->cal_buf = (uint8_t *)buf;
+	hperh->cal_res = res;
 
-    if (hperh->hdma.perh == NULL)
-        hperh->hdma.perh = DMA0;
+	if (hperh->hdma.perh == NULL)
+		hperh->hdma.perh = DMA0;
 
-    hperh->hdma.cplt_arg = (void *)hperh;
-    hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
-    hperh->hdma.err_arg  = (void *)hperh;
-    hperh->hdma.err_cbk  = &crc_dma_error;
+	hperh->hdma.cplt_arg = (void *)hperh;
+	hperh->hdma.cplt_cbk = &crc_dma_calculate_cplt;
+	hperh->hdma.err_arg  = (void *)hperh;
+	hperh->hdma.err_cbk  = &crc_dma_error;
 
-    ald_dma_config_struct(&(hperh->hdma.config));
-    hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
-    hperh->hdma.config.src        = (void *)buf;
-    hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
-    hperh->hdma.config.size       = size;
-    hperh->hdma.config.src_inc    = DMA_DATA_INC_WORD;
-    hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
-    hperh->hdma.config.msel       = DMA_MSEL_CRC;
-    hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
-    hperh->hdma.config.channel    = channel;
-    ald_dma_config_basic(&(hperh->hdma));
+	ald_dma_config_struct(&(hperh->hdma.config));
+	hperh->hdma.config.data_width = DMA_DATA_SIZE_WORD;
+	hperh->hdma.config.src        = (void *)buf;
+	hperh->hdma.config.dst        = (void *)&hperh->perh->DATA;
+	hperh->hdma.config.size       = size;
+	hperh->hdma.config.src_inc    = DMA_DATA_INC_WORD;
+	hperh->hdma.config.dst_inc    = DMA_DATA_INC_NONE;
+	hperh->hdma.config.msel       = DMA_MSEL_CRC;
+	hperh->hdma.config.msigsel    = DMA_MSIGSEL_NONE;
+	hperh->hdma.config.channel    = channel;
+	ald_dma_config_basic(&(hperh->hdma));
 
-    __UNLOCK(hperh);
-    CRC_DMA_ENABLE(hperh);
+	__UNLOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
 
-    return OK;
+	return OK;
 }
 
 
@@ -371,11 +371,11 @@ ald_status_t ald_crc_calculate_word_by_dma(crc_handle_t *hperh, uint32_t *buf, u
   */
 ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
 {
-    __LOCK(hperh);
-    CRC_DMA_DISABLE(hperh);
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	CRC_DMA_DISABLE(hperh);
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -386,11 +386,11 @@ ald_status_t ald_crc_dma_pause(crc_handle_t *hperh)
   */
 ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
 {
-    __LOCK(hperh);
-    CRC_DMA_ENABLE(hperh);
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	CRC_DMA_ENABLE(hperh);
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -401,12 +401,12 @@ ald_status_t ald_crc_dma_resume(crc_handle_t *hperh)
   */
 ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
 {
-    __LOCK(hperh);
-    CRC_DMA_DISABLE(hperh);
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	CRC_DMA_DISABLE(hperh);
+	__UNLOCK(hperh);
 
-    hperh->state = CRC_STATE_READY;
-    return OK;
+	hperh->state = CRC_STATE_READY;
+	return OK;
 }
 
 /**
@@ -427,9 +427,9 @@ ald_status_t ald_crc_dma_stop(crc_handle_t *hperh)
   */
 crc_state_t ald_crc_get_state(crc_handle_t *hperh)
 {
-    assert_param(IS_CRC(hperh->perh));
+	assert_param(IS_CRC(hperh->perh));
 
-    return hperh->state;
+	return hperh->state;
 }
 /**
   * @}
@@ -452,13 +452,13 @@ crc_state_t ald_crc_get_state(crc_handle_t *hperh)
   */
 void ald_crc_reset(crc_handle_t *hperh)
 {
-    hperh->perh->DATA = 0x0;
-    hperh->perh->CR   = 0x2;
-    hperh->perh->SEED = 0xFFFFFFFF;
+	hperh->perh->DATA = 0x0;
+	hperh->perh->CR   = 0x2;
+	hperh->perh->SEED = 0xFFFFFFFF;
 
-    hperh->state = CRC_STATE_READY;
-    __UNLOCK(hperh);
-    return;
+	hperh->state = CRC_STATE_READY;
+	__UNLOCK(hperh);
+	return;
 }
 
 #ifdef ALD_DMA
@@ -470,15 +470,15 @@ void ald_crc_reset(crc_handle_t *hperh)
   */
 static void crc_dma_calculate_cplt(void *arg)
 {
-    crc_handle_t *hperh = (crc_handle_t *)arg;
+	crc_handle_t *hperh = (crc_handle_t *)arg;
 
-    *(hperh->cal_res) = CRC->CHECKSUM;
-    CRC_DMA_DISABLE(hperh);
+	*(hperh->cal_res) = CRC->CHECKSUM;
+	CRC_DMA_DISABLE(hperh);
 
-    hperh->state = CRC_STATE_READY;
+	hperh->state = CRC_STATE_READY;
 
-    if (hperh->cal_cplt_cbk)
-        hperh->cal_cplt_cbk(hperh);
+	if (hperh->cal_cplt_cbk)
+		hperh->cal_cplt_cbk(hperh);
 }
 
 /**
@@ -489,15 +489,15 @@ static void crc_dma_calculate_cplt(void *arg)
   */
 static void crc_dma_error(void *arg)
 {
-    crc_handle_t *hperh = (crc_handle_t *)arg;
+	crc_handle_t *hperh = (crc_handle_t *)arg;
 
-    CRC_CLEAR_ERROR_FLAG(hperh);
-    CRC_DMA_DISABLE(hperh);
+	CRC_CLEAR_ERROR_FLAG(hperh);
+	CRC_DMA_DISABLE(hperh);
 
-    hperh->state = CRC_STATE_READY;
+	hperh->state = CRC_STATE_READY;
 
-    if (hperh->err_cplt_cbk)
-        hperh->err_cplt_cbk(hperh);
+	if (hperh->err_cplt_cbk)
+		hperh->err_cplt_cbk(hperh);
 }
 #endif
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_dma.c

@@ -73,7 +73,7 @@
 /** @defgroup DMA_Private_Variables DMA Private Variables
   * @{
   */
-dma_descriptor_t dma0_ctrl_base[28] __attribute__((aligned(512)));
+dma_descriptor_t dma0_ctrl_base[28] __attribute__ ((aligned(512)));
 dma_call_back_t dma0_cbk[6];
 /**
   * @}
@@ -93,74 +93,74 @@ dma_call_back_t dma0_cbk[6];
   */
 static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config_t *p)
 {
-    dma_descriptor_t *descr;
-
-    assert_param(IS_DMA(DMAx));
-    assert_param(IS_CYCLECTRL_TYPE(mode));
-    assert_param(p->src != NULL);
-    assert_param(p->dst != NULL);
-    assert_param(IS_DMA_DATA_SIZE(p->size));
-    assert_param(IS_DMA_DATASIZE_TYPE(p->data_width));
-    assert_param(IS_DMA_DATAINC_TYPE(p->src_inc));
-    assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc));
-    assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power));
-    assert_param(IS_FUNC_STATE(p->primary));
-    assert_param(IS_FUNC_STATE(p->burst));
-    assert_param(IS_FUNC_STATE(p->high_prio));
-    assert_param(IS_FUNC_STATE(p->iterrupt));
-    assert_param(IS_DMA_MSEL_TYPE(p->msel));
-    assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel));
-    assert_param(IS_DMA_CHANNEL(p->channel));
-
-    if (p->primary)
-        descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel;
-    else
-        descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel;
-
-    if (p->src_inc == DMA_DATA_INC_NONE)
-        descr->src = p->src;
-    else
-        descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << p->data_width));
-
-    if (p->dst_inc == DMA_DATA_INC_NONE)
-        descr->dst = p->dst;
-    else
-        descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << p->data_width));
-
-    descr->ctrl.cycle_ctrl    = mode;
-    descr->ctrl.next_useburst = 0;
-    descr->ctrl.n_minus_1     = p->size - 1;
-    descr->ctrl.R_power       = p->R_power;
-    descr->ctrl.src_prot_ctrl = 0,
-                descr->ctrl.dst_prot_ctrl = 0,
-                            descr->ctrl.src_size      = p->data_width;
-    descr->ctrl.src_inc       = p->src_inc;
-    descr->ctrl.dst_size      = p->data_width;
-    descr->ctrl.dst_inc       = p->dst_inc;
-
-    if (p->primary)
-        WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel));
-    else
-        WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel));
-
-    if (p->burst)
-        WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel));
-    else
-        WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel));
-
-    if (p->high_prio)
-        WRITE_REG(DMAx->CHPRSET, (1 << p->channel));
-    else
-        WRITE_REG(DMAx->CHPRCLR, (1 << p->channel));
-
-    if (p->iterrupt)
-        SET_BIT(DMAx->IER, (1 << p->channel));
-    else
-        CLEAR_BIT(DMAx->IER, (1 << p->channel));
-
-    MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS);
-    MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
-    return;
+	dma_descriptor_t *descr;
+
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_CYCLECTRL_TYPE(mode));
+	assert_param(p->src != NULL);
+	assert_param(p->dst != NULL);
+	assert_param(IS_DMA_DATA_SIZE(p->size));
+	assert_param(IS_DMA_DATASIZE_TYPE(p->data_width));
+	assert_param(IS_DMA_DATAINC_TYPE(p->src_inc));
+	assert_param(IS_DMA_DATAINC_TYPE(p->dst_inc));
+	assert_param(IS_DMA_ARBITERCONFIG_TYPE(p->R_power));
+	assert_param(IS_FUNC_STATE(p->primary));
+	assert_param(IS_FUNC_STATE(p->burst));
+	assert_param(IS_FUNC_STATE(p->high_prio));
+	assert_param(IS_FUNC_STATE(p->interrupt));
+	assert_param(IS_DMA_MSEL_TYPE(p->msel));
+	assert_param(IS_DMA_MSIGSEL_TYPE(p->msigsel));
+	assert_param(IS_DMA_CHANNEL(p->channel));
+
+	if (p->primary)
+		descr = (dma_descriptor_t *)(DMAx->CTRLBASE) + p->channel;
+	else
+		descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + p->channel;
+
+	if (p->src_inc == DMA_DATA_INC_NONE)
+		descr->src = p->src;
+	else
+		descr->src = (void *)((uint32_t)p->src + ((p->size - 1) << (uint32_t)p->src_inc));
+
+	if (p->dst_inc == DMA_DATA_INC_NONE)
+		descr->dst = p->dst;
+	else
+		descr->dst = (void *)((uint32_t)p->dst + ((p->size - 1) << (uint32_t)p->dst_inc));
+
+	descr->ctrl.cycle_ctrl    = mode;
+	descr->ctrl.next_useburst = 0;
+	descr->ctrl.n_minus_1     = p->size - 1;
+	descr->ctrl.R_power       = p->R_power;
+	descr->ctrl.src_prot_ctrl = 0,
+	descr->ctrl.dst_prot_ctrl = 0,
+	descr->ctrl.src_size      = p->data_width;
+	descr->ctrl.src_inc       = p->src_inc;
+	descr->ctrl.dst_size      = p->data_width;
+	descr->ctrl.dst_inc       = p->dst_inc;
+
+	if (p->primary)
+		WRITE_REG(DMAx->CHPRIALTCLR, (1 << p->channel));
+	else
+		WRITE_REG(DMAx->CHPRIALTSET, (1 << p->channel));
+
+	if (p->burst)
+		WRITE_REG(DMAx->CHUSEBURSTSET, (1 << p->channel));
+	else
+		WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << p->channel));
+
+	if (p->high_prio)
+		WRITE_REG(DMAx->CHPRSET, (1 << p->channel));
+	else
+		WRITE_REG(DMAx->CHPRCLR, (1 << p->channel));
+
+	if (p->interrupt)
+		SET_BIT(DMAx->IER, (1 << p->channel));
+	else
+		CLEAR_BIT(DMAx->IER, (1 << p->channel));
+
+	MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSEL_MSK, p->msel << DMA_CH0_SELCON_MSEL_POSS);
+	MODIFY_REG(DMAx->CH_SELCON[p->channel], DMA_CH0_SELCON_MSIGSEL_MSK, p->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
+	return;
 }
 
 /**
@@ -169,31 +169,27 @@ static void dma_config_base(DMA_TypeDef *DMAx, dma_cycle_ctrl_t mode, dma_config
   */
 void ald_dma_irq_handler(void)
 {
-    uint32_t i, reg = DMA0->IFLAG;
-
-    for (i = 0; i < DMA_CH_COUNT; ++i)
-    {
-        if (READ_BIT(reg, (1 << i)))
-        {
-            if (dma0_cbk[i].cplt_cbk != NULL)
-                dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
-
-            ald_dma_clear_flag_status(DMA0, i);
-        }
-    }
-
-    if (READ_BIT(reg, (1U << DMA_ERR)))
-    {
-        ald_dma_clear_flag_status(DMA0, DMA_ERR);
-
-        for (i = 0; i < DMA_CH_COUNT; ++i)
-        {
-            if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
-                dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
-        }
-    }
-
-    return;
+	uint32_t i, reg = DMA0->IFLAG;
+
+	for (i = 0; i < DMA_CH_COUNT; ++i) {
+		if (READ_BIT(reg, (1 << i))) {
+			if (dma0_cbk[i].cplt_cbk != NULL)
+				dma0_cbk[i].cplt_cbk(dma0_cbk[i].cplt_arg);
+
+			ald_dma_clear_flag_status(DMA0, i);
+		}
+	}
+
+	if (READ_BIT(reg, (1U << DMA_ERR))) {
+		ald_dma_clear_flag_status(DMA0, DMA_ERR);
+
+		for (i = 0; i < DMA_CH_COUNT; ++i) {
+			if (((DMA0->CHENSET >> i) & 0x1) && (dma0_cbk[i].err_cbk != NULL))
+				dma0_cbk[i].err_cbk(dma0_cbk[i].err_arg);
+		}
+	}
+
+	return;
 }
 /**
   * @}
@@ -230,6 +226,9 @@ void ald_dma_irq_handler(void)
     (+) ald_dma_config_struct(): Configure dma_config_t
         structure using default parameter.
 
+    (+) ald_dma_config_sg_alt_desc(): Configure dma_descriptor_t 
+        structure using specified parameter. This function used
+	in scatter-gather mode(memory or peripheral).
     @endverbatim
   * @{
   */
@@ -241,24 +240,24 @@ void ald_dma_irq_handler(void)
   */
 void ald_dma_reset(DMA_TypeDef *DMAx)
 {
-    uint32_t i;
+	uint32_t i;
 
-    assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA(DMAx));
 
-    WRITE_REG(DMAx->CFG, 0x0);
-    WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF);
-    WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF);
-    WRITE_REG(DMAx->CHENCLR, 0xFFF);
-    WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF);
-    WRITE_REG(DMAx->CHPRCLR, 0xFFF);
-    WRITE_REG(DMAx->ERRCLR, 0x1);
-    WRITE_REG(DMAx->IER, 0x0);
-    WRITE_REG(DMAx->ICFR, 0x80000FFF);
+	WRITE_REG(DMAx->CFG, 0x0);
+	WRITE_REG(DMAx->CHUSEBURSTCLR, 0xFFF);
+	WRITE_REG(DMAx->CHREQMASKCLR, 0xFFF);
+	WRITE_REG(DMAx->CHENCLR, 0xFFF);
+	WRITE_REG(DMAx->CHPRIALTCLR, 0xFFF);
+	WRITE_REG(DMAx->CHPRCLR, 0xFFF);
+	WRITE_REG(DMAx->ERRCLR, 0x1);
+	WRITE_REG(DMAx->IER, 0x0);
+	WRITE_REG(DMAx->ICFR, 0x80000FFF);
 
-    for (i = 0; i < DMA_CH_COUNT; ++i)
-        WRITE_REG(DMAx->CH_SELCON[i], 0x0);
+	for (i = 0; i < DMA_CH_COUNT; ++i)
+		WRITE_REG(DMAx->CH_SELCON[i], 0x0);
 
-    return;
+	return;
 }
 
 /**
@@ -269,20 +268,20 @@ void ald_dma_reset(DMA_TypeDef *DMAx)
   */
 void ald_dma_init(DMA_TypeDef *DMAx)
 {
-    assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA(DMAx));
 
-    memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base));
-    memset(dma0_cbk, 0x0, sizeof(dma0_cbk));
+	memset(dma0_ctrl_base, 0x0, sizeof(dma0_ctrl_base));
+	memset(dma0_cbk, 0x0, sizeof(dma0_cbk));
 
-    ald_dma_reset(DMAx);
-    NVIC_SetPriority(DMA_IRQn, 2);
-    NVIC_EnableIRQ(DMA_IRQn);
-    SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK);
+	ald_dma_reset(DMAx);
+	NVIC_SetPriority(DMA_IRQn, 2);
+	NVIC_EnableIRQ(DMA_IRQn);
+	SET_BIT(DMAx->IER, DMA_IER_DMAERRIE_MSK);
 
-    WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base);
-    SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK);
+	WRITE_REG(DMAx->CTRLBASE, (uint32_t)&dma0_ctrl_base);
+	SET_BIT(DMAx->CFG, DMA_CFG_MASTER_ENABLE_MSK);
 
-    return;
+	return;
 }
 
 /**
@@ -293,16 +292,53 @@ void ald_dma_init(DMA_TypeDef *DMAx)
   */
 void ald_dma_config_struct(dma_config_t *p)
 {
-    p->data_width = DMA_DATA_SIZE_BYTE;
-    p->src_inc    = DMA_DATA_INC_BYTE;
-    p->dst_inc    = DMA_DATA_INC_BYTE;
-    p->R_power    = DMA_R_POWER_1;
-    p->primary    = ENABLE;
-    p->burst      = DISABLE;
-    p->high_prio  = DISABLE;
-    p->iterrupt   = ENABLE;
-
-    return;
+	p->data_width = DMA_DATA_SIZE_BYTE;
+	p->src_inc    = DMA_DATA_INC_BYTE;
+	p->dst_inc    = DMA_DATA_INC_BYTE;
+	p->R_power    = DMA_R_POWER_1;
+	p->primary    = ENABLE;
+	p->burst      = DISABLE;
+	p->high_prio  = DISABLE;
+	p->interrupt  = ENABLE;
+
+	return;
+}
+
+/**
+  * @brief  Configure dma_descriptor_t structure using specified parameter.
+  * @note   This function used in scatter-gather mode(memory or peripheral).
+  * @param  desc: Address of the alternate descriptor.
+  * @param  config: Pointer to the dma_config_t structure.
+  * @param  memory: Memory or peripheral scatter-gather.
+  * @retval None
+  */
+void ald_dma_config_sg_alt_desc(dma_descriptor_t *desc, dma_config_t *config, uint8_t memory)
+{
+	if ((desc == NULL) || (config == NULL))
+		return;
+
+	if (config->src_inc == DMA_DATA_INC_NONE)
+		desc->src = config->src;
+	else
+		desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
+
+	if (config->dst_inc == DMA_DATA_INC_NONE)
+		desc->dst = config->dst;
+	else
+		desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
+
+	desc->ctrl.cycle_ctrl    = memory ? DMA_CYCLE_CTRL_MEM_SG_ALTERNATE : DMA_CYCLE_CTRL_PER_SG_ALTERNATE;
+	desc->ctrl.next_useburst = memory ? 0 : 1;
+	desc->ctrl.n_minus_1     = config->size - 1;
+	desc->ctrl.R_power       = config->R_power;
+	desc->ctrl.src_prot_ctrl = 0;
+	desc->ctrl.dst_prot_ctrl = 0;
+	desc->ctrl.src_size      = config->data_width;
+	desc->ctrl.src_inc       = config->src_inc;
+	desc->ctrl.dst_size      = config->data_width;
+	desc->ctrl.dst_inc       = config->dst_inc;
+
+	return;
 }
 
 /**
@@ -328,6 +364,7 @@ void ald_dma_config_struct(dma_config_t *p)
         (++) ald_dma_config_auto_easy(): Configure DMA channel according
 	     to the specified parameter. If you want use the dma easily,
              you can invoke this function.
+        (++) ald_dma_config_sg_mem(): Carry data used scatter-gather mode.
     (+) Carry data from peripheral to memory or from memory to peripheral,
         this mode APIs are:
 	(++) ald_dma_config_basic(): Configure DMA channel according to
@@ -336,6 +373,8 @@ void ald_dma_config_struct(dma_config_t *p)
         (++) ald_dma_config_basic_easy(): Configure DMA channel according
 	     to the specified parameter. If you want use the dma easily,
              you can invoke this function.
+        (++) ald_dma_ping_pong(): Carry data used ping-pong mode.
+        (++) ald_dma_config_sg_per(): Carry data used scatter-gather mode.
 
     @endverbatim
   * @{
@@ -351,17 +390,17 @@ void ald_dma_config_struct(dma_config_t *p)
   */
 void ald_dma_config_auto(dma_handle_t *hperh)
 {
-    dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
-    dma0_cbk[hperh->config.channel].err_cbk  = hperh->err_cbk;
-    dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
-    dma0_cbk[hperh->config.channel].err_arg  = hperh->err_arg;
-    dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config);
+	dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
+	dma0_cbk[hperh->config.channel].err_cbk  = hperh->err_cbk;
+	dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
+	dma0_cbk[hperh->config.channel].err_arg  = hperh->err_arg;
+	dma_config_base(hperh->perh, DMA_CYCLE_CTRL_AUTO, &hperh->config);
 
-    ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
-    WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-    SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
+	ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
+	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
+	SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
 
-    return;
+	return;
 }
 
 /**
@@ -376,39 +415,35 @@ void ald_dma_config_auto(dma_handle_t *hperh)
   */
 void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
 {
-    dma_descriptor_t *descr;
-
-    if (hperh->config.primary)
-        descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
-    else
-        descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
-
-    if (src)
-    {
-        if (hperh->config.src_inc == DMA_DATA_INC_NONE)
-            descr->src = src;
-        else
-            descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width));
-    }
-
-    if (dst)
-    {
-        if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
-            descr->dst = dst;
-        else
-            descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width));
-    }
-
-    ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
-    descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
-    descr->ctrl.n_minus_1  = size - 1;
-    WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-    SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
-    return;
+	dma_descriptor_t *descr;
+
+	if (hperh->config.primary)
+		descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
+	else
+		descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
+
+	if (src) {
+		if (hperh->config.src_inc == DMA_DATA_INC_NONE)
+			descr->src = src;
+		else
+			descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
+	}
+
+	if (dst) {
+		if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
+			descr->dst = dst;
+		else
+			descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
+	}
+
+	ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
+	descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
+	descr->ctrl.n_minus_1  = size - 1;
+	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
+	SET_BIT(hperh->perh->CHSWREQ, (1 << hperh->config.channel));
+	return;
 }
 
-
-
 /**
   * @brief  Configure DMA channel according to the specified parameter.
   *         The DMA mode is automatic. This mode is used to carry data
@@ -420,33 +455,32 @@ void ald_dma_restart_auto(dma_handle_t *hperh, void *src, void *dst, uint16_t si
   * @param  size: The total number of DMA transfers that DMA cycle contains
   * @param  channel: Channel index which will be used.
   * @param  cbk: DMA complete callback function
-  *
   * @retval None
   */
 void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
-                              uint16_t size, uint8_t channel, void (*cbk)(void *arg))
+                       uint16_t size, uint8_t channel, void (*cbk)(void *arg))
 {
-    dma_handle_t hperh;
+	dma_handle_t hperh;
 
-    assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA(DMAx));
 
-    ald_dma_config_struct(&hperh.config);
-    hperh.config.src     = src;
-    hperh.config.dst     = dst;
-    hperh.config.size    = size;
-    hperh.config.msel    = DMA_MSEL_NONE;
-    hperh.config.msigsel = DMA_MSIGSEL_NONE;
-    hperh.config.channel = channel;
+	ald_dma_config_struct(&hperh.config);
+	hperh.config.src     = src;
+	hperh.config.dst     = dst;
+	hperh.config.size    = size;
+	hperh.config.msel    = DMA_MSEL_NONE;
+	hperh.config.msigsel = DMA_MSIGSEL_NONE;
+	hperh.config.channel = channel;
 
-    hperh.perh     = DMAx;
-    hperh.cplt_cbk = cbk;
-    hperh.cplt_arg = NULL;
-    hperh.err_cbk  = NULL;
+	hperh.perh     = DMAx;
+	hperh.cplt_cbk = cbk;
+	hperh.cplt_arg = NULL;
+	hperh.err_cbk  = NULL;
 
-    ald_dma_clear_flag_status(DMAx, channel);
-    ald_dma_config_auto(&hperh);
+	ald_dma_clear_flag_status(DMAx, channel);
+	ald_dma_config_auto(&hperh);
 
-    return;
+	return;
 }
 
 /**
@@ -460,16 +494,16 @@ void ald_dma_config_auto_easy(DMA_TypeDef *DMAx, void *src, void *dst,
   */
 void ald_dma_config_basic(dma_handle_t *hperh)
 {
-    dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
-    dma0_cbk[hperh->config.channel].err_cbk  = hperh->err_cbk;
-    dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
-    dma0_cbk[hperh->config.channel].err_arg  = hperh->err_arg;
+	dma0_cbk[hperh->config.channel].cplt_cbk = hperh->cplt_cbk;
+	dma0_cbk[hperh->config.channel].err_cbk  = hperh->err_cbk;
+	dma0_cbk[hperh->config.channel].cplt_arg = hperh->cplt_arg;
+	dma0_cbk[hperh->config.channel].err_arg  = hperh->err_arg;
 
-    ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
-    dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config);
-    WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
+	ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
+	dma_config_base(hperh->perh, DMA_CYCLE_CTRL_BASIC, &hperh->config);
+	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
 
-    return;
+	return;
 }
 
 /**
@@ -484,35 +518,33 @@ void ald_dma_config_basic(dma_handle_t *hperh)
   */
 void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t size)
 {
-    dma_descriptor_t *descr;
-
-    if (hperh->config.primary)
-        descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
-    else
-        descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
-
-    if (src)
-    {
-        if (hperh->config.src_inc == DMA_DATA_INC_NONE)
-            descr->src = src;
-        else
-            descr->src = (void *)((uint32_t)src + ((size - 1) << hperh->config.data_width));
-    }
-
-    if (dst)
-    {
-        if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
-            descr->dst = dst;
-        else
-            descr->dst = (void *)((uint32_t)dst + ((size - 1) << hperh->config.data_width));
-    }
-
-    ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
-    descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
-    descr->ctrl.n_minus_1  = size - 1;
-    WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
-
-    return;
+	dma_descriptor_t *descr;
+
+	if (hperh->config.primary)
+		descr = (dma_descriptor_t *)(hperh->perh->CTRLBASE) + hperh->config.channel;
+	else
+		descr = (dma_descriptor_t *)(hperh->perh->ALTCTRLBASE) + hperh->config.channel;
+
+	if (src) {
+		if (hperh->config.src_inc == DMA_DATA_INC_NONE)
+			descr->src = src;
+		else
+			descr->src = (void *)((uint32_t)src + ((size - 1) << (uint32_t)hperh->config.data_width));
+	}
+
+	if (dst) {
+		if (hperh->config.dst_inc == DMA_DATA_INC_NONE)
+			descr->dst = dst;
+		else
+			descr->dst = (void *)((uint32_t)dst + ((size - 1) << (uint32_t)hperh->config.data_width));
+	}
+
+	ald_dma_clear_flag_status(hperh->perh, hperh->config.channel);
+	descr->ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
+	descr->ctrl.n_minus_1  = size - 1;
+	WRITE_REG(hperh->perh->CHENSET, (1 << hperh->config.channel));
+
+	return;
 }
 
 /**
@@ -528,42 +560,248 @@ void ald_dma_restart_basic(dma_handle_t *hperh, void *src, void *dst, uint16_t s
   * @param  msigsel: Input signal to DMA channel @ref dma_msigsel_t
   * @param  channel: Channel index which will be used
   * @param  cbk: DMA complete callback function
-  *
   * @retval None
-  *
- */
+  */
 void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t size, dma_msel_t msel,
-                               dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
+		dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
 {
-    dma_handle_t hperh;
+	dma_handle_t hperh;
+
+	assert_param(IS_DMA(DMAx));
+	ald_dma_config_struct(&hperh.config);
 
-    assert_param(IS_DMA(DMAx));
-    ald_dma_config_struct(&hperh.config);
+	if (((uint32_t)src) >= 0x40000000)
+		hperh.config.src_inc = DMA_DATA_INC_NONE;
 
-    if (((uint32_t)src) >= 0x40000000)
-        hperh.config.src_inc = DMA_DATA_INC_NONE;
+	if (((uint32_t)dst) >= 0x40000000)
+		hperh.config.dst_inc = DMA_DATA_INC_NONE;
 
-    if (((uint32_t)dst) >= 0x40000000)
-        hperh.config.dst_inc = DMA_DATA_INC_NONE;
+	hperh.config.src     = src;
+	hperh.config.dst     = dst;
+	hperh.config.size    = size;
+	hperh.config.msel    = msel;
+	hperh.config.msigsel = msigsel;
+	hperh.config.channel = channel;
 
-    hperh.config.src     = src;
-    hperh.config.dst     = dst;
-    hperh.config.size    = size;
-    hperh.config.msel    = msel;
-    hperh.config.msigsel = msigsel;
-    hperh.config.channel = channel;
+	hperh.perh     = DMAx;
+	hperh.cplt_cbk = cbk;
+	hperh.cplt_arg = NULL;
+	hperh.err_cbk  = NULL;
 
-    hperh.perh     = DMAx;
-    hperh.cplt_cbk = cbk;
-    hperh.cplt_arg = NULL;
-    hperh.err_cbk  = NULL;
+	ald_dma_clear_flag_status(DMAx, channel);
+	ald_dma_config_basic(&hperh);
 
-    ald_dma_clear_flag_status(DMAx, channel);
-    ald_dma_config_basic(&hperh);
+	return;
+}
+
+/**
+  * @brief  Configure DMA channel according to the specified parameter.
+  *         The DMA mode is ping-pong.
+  * @note   The ping-pong mode does not support memory to memory.
+  * @param  DMAx: Pointer to DMA peripheral.
+  * @param  config: Pointer to the dma_config_t structure which contains
+  *         the specified parameters.
+  * @param  first: Whether it is the first transmission. 1-first, 0-not first.
+  * @param  cbk: DMA complete callback function.
+  * @retval None
+  */
+void ald_dma_config_ping_pong(DMA_TypeDef *DMAx, dma_config_t *config,
+                                      uint8_t first, void (*cbk)(void *arg))
+{
+	dma_descriptor_t *desc;
+
+	assert_param(IS_DMA(DMAx));
+	assert_param(config->src != NULL);
+	assert_param(config->dst != NULL);
+	assert_param(IS_DMA_DATA_SIZE(config->size));
+	assert_param(IS_DMA_DATASIZE_TYPE(config->data_width));
+	assert_param(IS_DMA_DATAINC_TYPE(config->src_inc));
+	assert_param(IS_DMA_DATAINC_TYPE(config->dst_inc));
+	assert_param(IS_DMA_ARBITERCONFIG_TYPE(config->R_power));
+	assert_param(IS_FUNC_STATE(config->primary));
+	assert_param(IS_FUNC_STATE(config->burst));
+	assert_param(IS_FUNC_STATE(config->high_prio));
+	assert_param(IS_FUNC_STATE(config->interrupt));
+	assert_param(IS_DMA_MSEL_TYPE(config->msel));
+	assert_param(IS_DMA_MSIGSEL_TYPE(config->msigsel));
+	assert_param(IS_DMA_CHANNEL(config->channel));
+
+	dma0_cbk[config->channel].cplt_cbk = cbk;
+	dma0_cbk[config->channel].err_cbk  = NULL;
+	dma0_cbk[config->channel].cplt_arg = NULL;
+	dma0_cbk[config->channel].err_arg  = NULL;
+
+	if (config->primary)
+		desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + config->channel;
+	else
+		desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + config->channel;
+
+	if (config->src_inc == DMA_DATA_INC_NONE)
+		desc->src = config->src;
+	else
+		desc->src = (void *)((uint32_t)config->src + ((config->size - 1) << (uint32_t)config->data_width));
+
+	if (config->dst_inc == DMA_DATA_INC_NONE)
+		desc->dst = config->dst;
+	else
+		desc->dst = (void *)((uint32_t)config->dst + ((config->size - 1) << (uint32_t)config->data_width));
+
+	desc->ctrl.cycle_ctrl    = DMA_CYCLE_CTRL_PINGPONG;
+	desc->ctrl.next_useburst = 0;
+	desc->ctrl.n_minus_1     = config->size - 1;
+	desc->ctrl.R_power       = config->R_power;
+	desc->ctrl.src_prot_ctrl = 0,
+	desc->ctrl.dst_prot_ctrl = 0,
+	desc->ctrl.src_size      = config->data_width;
+	desc->ctrl.src_inc       = config->src_inc;
+	desc->ctrl.dst_size      = config->data_width;
+	desc->ctrl.dst_inc       = config->dst_inc;
+
+	if (!first)
+		return;
+
+	if (config->primary)
+		WRITE_REG(DMAx->CHPRIALTCLR, (1 << config->channel));
+	else
+		WRITE_REG(DMAx->CHPRIALTSET, (1 << config->channel));
+
+	if (config->burst)
+		WRITE_REG(DMAx->CHUSEBURSTSET, (1 << config->channel));
+	else
+		WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << config->channel));
+
+	if (config->high_prio)
+		WRITE_REG(DMAx->CHPRSET, (1 << config->channel));
+	else
+		WRITE_REG(DMAx->CHPRCLR, (1 << config->channel));
+
+	if (config->interrupt)
+		SET_BIT(DMAx->IER, (1 << config->channel));
+	else
+		CLEAR_BIT(DMAx->IER, (1 << config->channel));
+
+	MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSEL_MSK, config->msel << DMA_CH0_SELCON_MSEL_POSS);
+	MODIFY_REG(DMAx->CH_SELCON[config->channel], DMA_CH0_SELCON_MSIGSEL_MSK, config->msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
+
+	WRITE_REG(DMAx->ICFR, (1 << config->channel));
+	WRITE_REG(DMAx->CHENSET, (1 << config->channel));
+
+	return;
+}
 
-    return;
+/**
+  * @brief  Configure DMA channel according to the specified parameter.
+  *         The DMA mode is memory scatter-gather.
+  * @param  DMAx: Pointer to DMA peripheral.
+  * @param  desc: Pointer to first alternate descriptor.
+  * @param  nr: Number of the alternate descriptor.
+  * @param  channel: Channel index which will be used.
+  * @param  cbk: DMA complete callback function.
+  * @retval None
+ */
+void ald_dma_config_sg_mem(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr,
+	                          uint8_t channel, void (*cbk)(void *arg))
+{
+	dma_descriptor_t *tmp  = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
+	dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
+
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_CHANNEL(channel));
+
+	if ((desc == NULL) || (nr == 0))
+		return;
+
+	dma0_cbk[channel].cplt_cbk = cbk;
+	dma0_cbk[channel].err_cbk  = NULL;
+	dma0_cbk[channel].cplt_arg = NULL;
+	dma0_cbk[channel].err_arg  = NULL;
+
+	tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
+	tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
+	tmp->ctrl.cycle_ctrl    = DMA_CYCLE_CTRL_MEM_SG_PRIMARY;
+	tmp->ctrl.next_useburst = 0;
+	tmp->ctrl.n_minus_1     = (nr << 2) - 1;
+	tmp->ctrl.R_power       = DMA_R_POWER_4;
+	tmp->ctrl.src_prot_ctrl = 0,
+	tmp->ctrl.dst_prot_ctrl = 0,
+	tmp->ctrl.src_size      = DMA_DATA_SIZE_WORD;
+	tmp->ctrl.src_inc       = DMA_DATA_INC_WORD;
+	tmp->ctrl.dst_size      = DMA_DATA_SIZE_WORD;
+	tmp->ctrl.dst_inc       = DMA_DATA_INC_WORD;
+
+	desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_AUTO;
+	WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
+	WRITE_REG(DMAx->CHUSEBURSTCLR, (1 << channel));
+	WRITE_REG(DMAx->CHPRCLR, (1 << channel));
+
+	WRITE_REG(DMAx->ICFR, (1 << channel));
+	SET_BIT(DMAx->IER, (1 << channel));
+	WRITE_REG(DMAx->CHENSET, (1 << channel));
+	SET_BIT(DMAx->CHSWREQ, (1 << channel));
+
+	return;
 }
 
+/**
+  * @brief  Configure DMA channel according to the specified parameter.
+  *         The DMA mode is peripheral scatter-gather.
+  * @note   The size of the first transmission must be 5.
+  * @param  DMAx: Pointer to DMA peripheral.
+  * @param  desc: Pointer to first alternate descriptor.
+  * @param  nr: Number of the alternate descriptor.
+  * @param  burst: 1-Enable burst, 0-Disable burst.
+  * @param  msel: Input source to DMA channel @ref dma_msel_t
+  * @param  msigsel: Input signal to DMA channel @ref dma_msigsel_t
+  * @param  channel: Channel index which will be used.
+  * @param  cbk: DMA complete callback function.
+  * @retval None
+ */
+void ald_dma_config_sg_per(DMA_TypeDef *DMAx, dma_descriptor_t *desc, uint32_t nr, uint8_t burst,
+                    dma_msel_t msel, dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg))
+{
+	dma_descriptor_t *tmp  = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
+	dma_descriptor_t *_tmp = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
+
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_MSEL_TYPE(msel));
+	assert_param(IS_DMA_MSIGSEL_TYPE(msigsel));
+	assert_param(IS_DMA_CHANNEL(channel));
+
+	if ((desc == NULL) || (nr == 0))
+		return;
+
+	dma0_cbk[channel].cplt_cbk = cbk;
+	dma0_cbk[channel].err_cbk  = NULL;
+	dma0_cbk[channel].cplt_arg = NULL;
+	dma0_cbk[channel].err_arg  = NULL;
+
+	tmp->src = (void *)((uint32_t)desc + (((nr << 2) - 1) << DMA_DATA_INC_WORD));
+	tmp->dst = (void *)((uint32_t)_tmp + ((4 - 1) << DMA_DATA_INC_WORD));
+	tmp->ctrl.cycle_ctrl    = DMA_CYCLE_CTRL_PER_SG_PRIMARY;
+	tmp->ctrl.next_useburst = 0;
+	tmp->ctrl.n_minus_1     = (nr << 2) - 1;
+	tmp->ctrl.R_power       = DMA_R_POWER_4;
+	tmp->ctrl.src_prot_ctrl = 0,
+	tmp->ctrl.dst_prot_ctrl = 0,
+	tmp->ctrl.src_size      = DMA_DATA_SIZE_WORD;
+	tmp->ctrl.src_inc       = DMA_DATA_INC_WORD;
+	tmp->ctrl.dst_size      = DMA_DATA_SIZE_WORD;
+	tmp->ctrl.dst_inc       = DMA_DATA_INC_WORD;
+
+	desc[nr - 1].ctrl.cycle_ctrl = DMA_CYCLE_CTRL_BASIC;
+	WRITE_REG(DMAx->CHPRIALTCLR, (1 << channel));
+	burst ? (DMAx->CHUSEBURSTSET = (1 << channel)) : (DMAx->CHUSEBURSTCLR, (1 << channel));
+	WRITE_REG(DMAx->CHPRCLR, (1 << channel));
+
+	MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSEL_MSK, msel << DMA_CH0_SELCON_MSEL_POSS);
+	MODIFY_REG(DMAx->CH_SELCON[channel], DMA_CH0_SELCON_MSIGSEL_MSK, msigsel << DMA_CH0_SELCON_MSIGSEL_POSS);
+
+	WRITE_REG(DMAx->ICFR, (1 << channel));
+	SET_BIT(DMAx->IER, (1 << channel));
+	WRITE_REG(DMAx->CHENSET, (1 << channel));
+
+	return;
+}
 /**
   * @}
   */
@@ -605,28 +843,26 @@ void ald_dma_config_basic_easy(DMA_TypeDef *DMAx, void *src, void *dst, uint16_t
   */
 void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
 {
-    dma_descriptor_t *descr, *alt_descr;
-
-    assert_param(IS_DMA(DMAx));
-    assert_param(IS_DMA_CHANNEL(channel));
-    assert_param(IS_FUNC_STATE(state));
-
-    descr     = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
-    alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
-
-    if (state)
-    {
-        WRITE_REG(DMAx->CHENSET, (1 << channel));
-    }
-    else
-    {
-        memset(descr, 0x00, sizeof(dma_descriptor_t));
-        memset(alt_descr, 0x00, sizeof(dma_descriptor_t));
-        WRITE_REG(DMAx->CH_SELCON[channel], 0x0);
-        WRITE_REG(DMAx->CHENCLR, (1 << channel));
-    }
-
-    return;
+	dma_descriptor_t *descr, *alt_descr;
+
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_CHANNEL(channel));
+	assert_param(IS_FUNC_STATE(state));
+
+	descr     = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
+	alt_descr = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
+
+	if (state) {
+		WRITE_REG(DMAx->CHENSET, (1 << channel));
+	}
+	else {
+		memset(descr, 0x00, sizeof(dma_descriptor_t));
+		memset(alt_descr, 0x00, sizeof(dma_descriptor_t));
+		WRITE_REG(DMAx->CH_SELCON[channel], 0x0);
+		WRITE_REG(DMAx->CHENCLR, (1 << channel));
+	}
+
+	return;
 }
 
 /**
@@ -643,16 +879,16 @@ void ald_dma_channel_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t stat
   */
 void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t state)
 {
-    assert_param(IS_DMA(DMAx));
-    assert_param(IS_DMA_IT_TYPE(channel));
-    assert_param(IS_FUNC_STATE(state));
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_IT_TYPE(channel));
+	assert_param(IS_FUNC_STATE(state));
 
-    if (state)
-        SET_BIT(DMAx->IER, (1 << channel));
-    else
-        CLEAR_BIT(DMAx->IER, (1 << channel));
+	if (state)
+		SET_BIT(DMAx->IER, (1 << channel));
+	else
+		CLEAR_BIT(DMAx->IER, (1 << channel));
 
-    return;
+	return;
 }
 
 /**
@@ -668,13 +904,13 @@ void ald_dma_interrupt_config(DMA_TypeDef *DMAx, uint8_t channel, type_func_t st
   */
 it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel)
 {
-    assert_param(IS_DMA(DMAx));
-    assert_param(IS_DMA_IT_TYPE(channel));
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_IT_TYPE(channel));
 
-    if (READ_BIT(DMAx->IER, (1 << channel)))
-        return SET;
+	if (READ_BIT(DMAx->IER, (1 << channel)))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -690,13 +926,13 @@ it_status_t ald_dma_get_it_status(DMA_TypeDef *DMAx, uint8_t channel)
   */
 flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
 {
-    assert_param(IS_DMA(DMAx));
-    assert_param(IS_DMA_IT_TYPE(channel));
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_IT_TYPE(channel));
 
-    if (READ_BIT(DMAx->IFLAG, (1 << channel)))
-        return SET;
+	if (READ_BIT(DMAx->IFLAG, (1 << channel)))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -709,11 +945,42 @@ flag_status_t ald_dma_get_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
   */
 void ald_dma_clear_flag_status(DMA_TypeDef *DMAx, uint8_t channel)
 {
-    assert_param(IS_DMA(DMAx));
-    assert_param(IS_DMA_IT_TYPE(channel));
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_IT_TYPE(channel));
+
+	WRITE_REG(DMAx->ICFR, (1 << channel));
+	return;
+}
+
+/**
+  * @brief  Get the completion status of the descriptor
+  * @param  DMAx: Pointer to DMA peripheral
+  * @param  channel: Channel index
+  * @retval Completion status:
+  *           - DMA_DESCP_CPLT_PRI: Primary descriptor has been completed
+  *           - DMA_DESCP_CPLT_ALT: Alternate descriptor has been completed
+  *           - DMA_DESCP_CPLT_ALL: Both primary and alternate descriptors have been completed
+  */
+dma_descrp_cplt_t ald_dma_descriptor_cplt_get(DMA_TypeDef *DMAx, uint8_t channel)
+{
+	uint8_t pri, alt;
+	dma_descriptor_t *desc;
+
+	assert_param(IS_DMA(DMAx));
+	assert_param(IS_DMA_IT_TYPE(channel));
+
+	desc = (dma_descriptor_t *)(DMAx->CTRLBASE) + channel;
+	pri  = desc->ctrl.cycle_ctrl;
+	desc = (dma_descriptor_t *)(DMAx->ALTCTRLBASE) + channel;
+	alt  = desc->ctrl.cycle_ctrl;
+
+	if ((pri == 0) && (alt == 0))
+		return DMA_DESCP_CPLT_ALL;
 
-    WRITE_REG(DMAx->ICFR, (1 << channel));
-    return;
+	if (pri == 0)
+		return DMA_DESCP_CPLT_PRI;
+	else
+		return DMA_DESCP_CPLT_ALT;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash.c

@@ -27,9 +27,9 @@
 #ifdef ALD_FLASH
 
 #if defined ( __ICCARM__ )
-    #define __RAMFUNC       __ramfunc
+#define __RAMFUNC       __ramfunc
 #else
-    #define __RAMFUNC
+#define __RAMFUNC
 #endif
 
 /** @defgroup Flash_Private_Variables Flash Private Variables
@@ -51,23 +51,22 @@ static op_cmd_type OP_CMD = OP_FLASH;
   */
 __RAMFUNC static ald_status_t flash_unlock(void)
 {
-    uint16_t i;
-    uint16_t op_cmd = OP_CMD;
+	uint16_t i;
+	uint16_t op_cmd = OP_CMD;
 
-    if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-        return ERROR;
+	if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
+		return ERROR;
 
-    FLASH_REG_UNLOCK();
-    FLASH_IAP_ENABLE();
-    FLASH_REQ();
+	FLASH_REG_UNLOCK();
+	FLASH_IAP_ENABLE();
+	FLASH_REQ();
 
-    for (i = 0; i < 0xFFFF; i++)
-    {
-        if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
-            break;
-    }
+	for (i = 0; i < 0xFFFF; i++) {
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK))
+			break;
+	}
 
-    return i == 0xFFFF ? ERROR : OK;
+	return i == 0xFFFF ? ERROR : OK;
 }
 
 /**
@@ -76,19 +75,18 @@ __RAMFUNC static ald_status_t flash_unlock(void)
   */
 __RAMFUNC static ald_status_t flash_lock(void)
 {
-    uint16_t i;
-    uint16_t op_cmd = OP_CMD;
+	uint16_t i;
+	uint16_t op_cmd = OP_CMD;
 
-    FLASH_REG_UNLOCK();
-    WRITE_REG(MSC->FLASHCR, 0x0);
+	FLASH_REG_UNLOCK();
+	WRITE_REG(MSC->FLASHCR, 0x0);
 
-    for (i = 0; i < 0xFFFF; i++)
-    {
-        if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
-            break;
-    }
+	for (i = 0; i < 0xFFFF; i++) {
+		if (!(READ_BIT(MSC->FLASHSR, MSC_FLASHSR_FLASHACK_MSK)))
+			break;
+	}
 
-    return i == 0xFFFF ? ERROR : OK;
+	return i == 0xFFFF ? ERROR : OK;
 }
 
 /**
@@ -98,50 +96,44 @@ __RAMFUNC static ald_status_t flash_lock(void)
   */
 __RAMFUNC ald_status_t flash_page_erase(uint32_t addr)
 {
-    uint32_t i;
-    uint16_t op_cmd = OP_CMD;
-
-    if (flash_unlock() != OK)
-        goto end;
-
-    if (op_cmd == OP_FLASH)
-    {
-        CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-        MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
-    }
-    else
-    {
-        SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-        MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
-    }
-
-    WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
-
-    for (i = 0; i < 0xFFFF; i++)
-    {
-        if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-            continue;
-
-        if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
-            goto end;
-
-        if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
-            goto end;
-
-        if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
-            break;
-    }
-
-    if (i == 0xFFFF)
-        goto end;
-
-    if (flash_lock() == ERROR)
-        goto end;
-
-    return OK;
+	uint32_t i;
+	uint16_t op_cmd = OP_CMD;
+
+	if (flash_unlock() != OK)
+		goto end;
+
+	if (op_cmd == OP_FLASH) {
+		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, FLASH_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
+	}
+	else {
+		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+		MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, INFO_PAGE_ADDR(addr) << MSC_FLASHADDR_ADDR_POSS);
+	}
+
+	WRITE_REG(MSC->FLASHCMD, FLASH_CMD_PE);
+
+	for (i = 0; i < 0xFFFF; i++) {
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
+			continue;
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_ADDR_OV_MSK))
+			goto end;
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_WRP_FLAG_MSK))
+			goto end;
+		if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_SERA_MSK))
+			break;
+	}
+
+	if (i == 0xFFFF)
+		goto end;
+
+	if (flash_lock() == ERROR)
+		goto end;
+
+	return OK;
 end:
-    flash_lock();
-    return ERROR;
+	flash_lock();
+	return ERROR;
 }
 
 /**
@@ -154,58 +146,52 @@ end:
   */
 __RAMFUNC ald_status_t flash_word_program(uint32_t addr, uint32_t *data, uint32_t len, uint32_t fifo)
 {
-    uint16_t i;
-    uint16_t prog_len;
-    uint32_t *p_data = data;
-    uint16_t op_cmd = OP_CMD;
-
-    if (flash_unlock() != OK)
-        goto end;
-
-    if (op_cmd == OP_FLASH)
-        CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-    else
-        SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
-
-    MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
-    MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
-
-    for (prog_len = 0; prog_len < len; prog_len++)
-    {
-        if (fifo)
-        {
-            WRITE_REG(MSC->FLASHFIFO, p_data[0]);
-            WRITE_REG(MSC->FLASHFIFO, p_data[1]);
-        }
-        else
-        {
-            WRITE_REG(MSC->FLASHDL, p_data[0]);
-            WRITE_REG(MSC->FLASHDH, p_data[1]);
-            WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
-        }
-
-        p_data += 2;
-
-        for (i = 0; i < 0xFFFF; i++)
-        {
-            if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
-                continue;
-
-            if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
-                break;
-        }
-    }
-
-    if (i == 0xFFFF)
-        goto end;
-
-    if (flash_lock() == ERROR)
-        goto end;
-
-    return OK;
+	uint16_t i = 0;
+	uint16_t prog_len;
+	uint32_t *p_data = data;
+	uint16_t op_cmd = OP_CMD;
+
+	if (flash_unlock() != OK)
+		goto end;
+
+	if (op_cmd == OP_FLASH)
+		CLEAR_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+	else
+		SET_BIT(MSC->FLASHADDR, MSC_FLASHADDR_IFREN_MSK);
+
+	MODIFY_REG(MSC->FLASHADDR, MSC_FLASHADDR_ADDR_MSK, addr << MSC_FLASHADDR_ADDR_POSS);
+	MODIFY_REG(MSC->FLASHCR, MSC_FLASHCR_FIFOEN_MSK, fifo << MSC_FLASHCR_FIFOEN_POS);
+
+	for (prog_len = 0; prog_len < len; prog_len++) {
+		if (fifo) {
+			WRITE_REG(MSC->FLASHFIFO, p_data[0]);
+			WRITE_REG(MSC->FLASHFIFO, p_data[1]);
+		}
+		else {
+			WRITE_REG(MSC->FLASHDL, p_data[0]);
+			WRITE_REG(MSC->FLASHDH, p_data[1]);
+			WRITE_REG(MSC->FLASHCMD, FLASH_CMD_WP);
+		}
+
+		p_data += 2;
+
+		for (i = 0; i < 0xFFFF; i++) {
+			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_BUSY_MSK))
+				continue;
+			if (READ_BIT(MSC->FLASHSR, MSC_FLASHSR_PROG_MSK))
+				break;
+		}
+	}
+	if (i == 0xFFFF)
+		goto end;
+
+	if (flash_lock() == ERROR)
+		goto end;
+
+	return OK;
 end:
-    flash_lock();
-    return ERROR;
+	flash_lock();
+	return ERROR;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_flash_ext.c

@@ -84,30 +84,29 @@ static uint8_t write_buf[FLASH_PAGE_SIZE];
   */
 static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
 {
-    uint8_t *addr_to_read;
-    uint8_t value;
-    uint32_t index;
+	uint8_t* addr_to_read;
+	uint8_t value;
+	uint32_t index;
 
-    /* Check the parameters */
-    assert_param(IS_FLASH_ADDRESS(begin_addr));
-    assert_param(IS_FLASH_ADDRESS(end_addr));
+	/* Check the parameters */
+	assert_param(IS_FLASH_ADDRESS(begin_addr));
+	assert_param(IS_FLASH_ADDRESS(end_addr));
 
-    addr_to_read = (uint8_t *)begin_addr;
-    index        = begin_addr;
-    value        = 0xFF;
+	addr_to_read = (uint8_t *)begin_addr;
+	index        = begin_addr;
+	value        = 0xFF;
 
-    if (begin_addr > end_addr)
-        return FALSE;
+	if (begin_addr > end_addr)
+		return FALSE;
 
-    while (index++ <= end_addr)
-    {
-        value = *addr_to_read++;
+	while (index++ <= end_addr) {
+		value = *addr_to_read++;
 
-        if (value != 0xFF)
-            break;
-    }
+		if (value != 0xFF)
+			break;
+	}
 
-    return value == 0xFF ? FALSE : TRUE;
+	return value == 0xFF ? FALSE : TRUE;
 }
 /**
   * @}
@@ -134,24 +133,23 @@ static type_bool_t page_have_writen(uint32_t begin_addr, uint32_t end_addr)
   */
 ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
 {
-    uint32_t i;
-    uint32_t temp;
+	uint32_t i;
+	uint32_t temp;
 
-    assert_param(IS_4BYTES_ALIGN(ram_addr));
-    assert_param(IS_FLASH_ADDRESS(addr));
-    assert_param(IS_FLASH_ADDRESS(addr + len - 1));
+	assert_param(IS_4BYTES_ALIGN(ram_addr));
+	assert_param(IS_FLASH_ADDRESS(addr));
+	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
 
-    temp = (uint32_t)ram_addr;
+	temp = (uint32_t)ram_addr;
 
-    if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
-        return ERROR;
+	if (((temp & 0x3) != 0) || (((addr) & 0x3) != 0))
+		return ERROR;
 
-    for (i = 0; i < len; i++)
-    {
-        ram_addr[i] = ((uint32_t *)addr)[i];
-    }
+	for (i = 0; i < len; i++) {
+		ram_addr[i] = ((uint32_t *)addr)[i];
+	}
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -164,92 +162,84 @@ ald_status_t ald_flash_read(uint32_t *ram_addr, uint32_t addr, uint16_t len)
 
 ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
 {
-    uint32_t index = 0;
-    uint32_t para = 0;
-    uint32_t index2 = 0;
-    uint32_t start_write_addr;
-    uint32_t end_write_addr;
-    uint32_t start_word_addr;
-    uint32_t end_word_addr;
-    uint16_t len_to_write;
-    uint32_t len_index;
-    type_bool_t need_erase_page;
-
-    assert_param(IS_FLASH_ADDRESS(addr));
-    assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-    len_to_write = len;
-
-    __disable_irq();
-
-    while (len_to_write > 0)
-    {
-        need_erase_page = FALSE;
-
-        for (index = 0; index < FLASH_PAGE_SIZE; index++)
-            write_buf[index] = 0xFF;
-
-        start_write_addr = addr + (len - len_to_write);
-        end_write_addr   = addr + len - 1;
-        end_write_addr   = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
-                           ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
-        need_erase_page  = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
-                                            FLASH_WORDEND_ADDR(end_write_addr));
-
-        if (need_erase_page)
-        {
-            if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
-                                        FLASH_PAGE_SIZE >> 2))
-            {
-                __enable_irq();
-                return ERROR;
-            }
-
-            if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr)))
-            {
-                __enable_irq();
-                return ERROR;
-            }
-
-            para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
-            index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
-            index2 = len - len_to_write;
-
-            while (index <= para)
-                write_buf[index++] = buf[index2++];
-
-            index2     = 0;
-            index      = FLASH_PAGE_ADDR(start_write_addr);
-            para       = FLASH_PAGE_ADDR(start_write_addr) + FLASH_PAGE_SIZE;
-            len_index  = FLASH_PAGE_SIZE;
-        }
-        else
-        {
-            para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
-            index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
-            index2 = len - len_to_write;
-
-            while (index <= para)
-                write_buf[index++] = buf[index2++];
-
-            start_word_addr = FLASH_WORD_ADDR(start_write_addr);
-            end_word_addr   = FLASH_WORDEND_ADDR(end_write_addr);
-            index2          = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
-            index           = start_word_addr;
-            len_index       = end_word_addr - start_word_addr + 1;
-        }
-
-        if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO))
-        {
-            __enable_irq();
-            return ERROR;
-        }
-
-        len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
-    }
-
-    __enable_irq();
-    return OK;
+	uint32_t index = 0;
+	uint32_t para = 0;
+	uint32_t index2 = 0;
+	uint32_t start_write_addr;
+	uint32_t end_write_addr;
+	uint32_t start_word_addr;
+	uint32_t end_word_addr;
+	uint16_t len_to_write;
+	uint32_t len_index;
+	type_bool_t need_erase_page;
+
+	assert_param(IS_FLASH_ADDRESS(addr));
+	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
+
+	len_to_write = len;
+
+	__disable_irq();
+	while (len_to_write > 0) {
+		need_erase_page = FALSE;
+
+		for (index = 0; index < FLASH_PAGE_SIZE; index++)
+			write_buf[index] = 0xFF;
+
+		start_write_addr = addr + (len - len_to_write);
+		end_write_addr   = addr + len - 1;
+		end_write_addr   = FLASH_PAGE_ADDR(start_write_addr) == FLASH_PAGE_ADDR(end_write_addr)
+		                   ? end_write_addr : FLASH_PAGEEND_ADDR(start_write_addr);
+		need_erase_page  = page_have_writen(FLASH_WORD_ADDR(start_write_addr),
+		                                    FLASH_WORDEND_ADDR(end_write_addr));
+
+		if (need_erase_page) {
+			if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_write_addr),
+                                 		  FLASH_PAGE_SIZE >> 2)) {
+				__enable_irq();
+				return ERROR;
+			}
+
+			if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_write_addr))) {
+				__enable_irq();
+				return ERROR;
+			}
+
+			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
+			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
+			index2 = len - len_to_write;
+
+			while (index <= para)
+				write_buf[index++] = buf[index2++];
+
+			index2     = 0;
+			index      = FLASH_PAGE_ADDR(start_write_addr);
+			len_index  = FLASH_PAGE_SIZE;
+		}
+		else {
+			para   = end_write_addr & (FLASH_PAGE_SIZE - 1);
+			index  = start_write_addr & (FLASH_PAGE_SIZE - 1);
+			index2 = len - len_to_write;
+
+			while (index <= para)
+				write_buf[index++] = buf[index2++];
+
+			start_word_addr = FLASH_WORD_ADDR(start_write_addr);
+			end_word_addr   = FLASH_WORDEND_ADDR(end_write_addr);
+			index2          = (FLASH_WORD_ADDR(start_word_addr) - FLASH_PAGE_ADDR(start_word_addr));
+			index           = start_word_addr;
+			len_index       = end_word_addr - start_word_addr + 1;
+		}
+
+		if (ERROR == flash_word_program(index, (uint32_t *)(write_buf + index2), (len_index >> 3), FLASH_FIFO)) {
+			__enable_irq();
+			return ERROR;
+		}
+
+		len_to_write = len_to_write - (end_write_addr - start_write_addr + 1);
+	}
+
+	__enable_irq();
+	return OK;
 }
 
 /**
@@ -260,81 +250,69 @@ ald_status_t ald_flash_write(uint32_t addr, uint8_t *buf, uint16_t len)
   */
 ald_status_t ald_flash_erase(uint32_t addr, uint16_t len)
 {
-    int32_t	index;
-    int32_t para;
-    int32_t start_erase_addr;
-    int32_t end_erase_addr;
-    uint16_t len_not_erase;
-    uint32_t len_index;
-    type_bool_t page_need_save;
-
-    assert_param(IS_FLASH_ADDRESS(addr));
-    assert_param(IS_FLASH_ADDRESS(addr + len - 1));
-
-    len_not_erase = len;
-
-    __disable_irq();
-
-    while (len_not_erase > 0)
-    {
-        page_need_save = FALSE;
-
-        start_erase_addr = addr + len - len_not_erase;
-        end_erase_addr   = addr + len - 1;
-        end_erase_addr   = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
-                           ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
-
-        if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr))
-        {
-            if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
-                page_need_save = TRUE;
-        }
-
-        if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr))
-        {
-            if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
-                page_need_save = TRUE;
-        }
-
-        if (page_need_save)
-        {
-            if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
-                                        FLASH_PAGE_SIZE >> 2))
-            {
-                __enable_irq();
-                return ERROR;
-            }
-        }
-
-        if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr)))
-        {
-            __enable_irq();
-            return ERROR;
-        }
-
-        if (page_need_save)
-        {
-            para  = end_erase_addr & (FLASH_PAGE_SIZE - 1);
-            index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
-
-            while (index <= para)
-                write_buf[index++] = 0xFF;
-
-            index     = FLASH_PAGE_ADDR(start_erase_addr);
-            len_index = FLASH_PAGE_SIZE;
-
-            if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO))
-            {
-                __enable_irq();
-                return ERROR;
-            }
-        }
-
-        len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
-    }
-
-    __enable_irq();
-    return OK;
+	uint32_t index;
+	int32_t para;
+	int32_t start_erase_addr;
+	int32_t end_erase_addr;
+	uint16_t len_not_erase;
+	uint32_t len_index;
+	type_bool_t page_need_save;
+
+	assert_param(IS_FLASH_ADDRESS(addr));
+	assert_param(IS_FLASH_ADDRESS(addr + len - 1));
+
+	len_not_erase = len;
+
+	__disable_irq();
+	while (len_not_erase > 0) {
+		page_need_save = FALSE;
+
+		start_erase_addr = addr + len - len_not_erase;
+		end_erase_addr   = addr + len - 1;
+		end_erase_addr   = (FLASH_PAGE_ADDR(start_erase_addr) == FLASH_PAGE_ADDR(end_erase_addr))
+		                    ? end_erase_addr : FLASH_PAGEEND_ADDR(start_erase_addr);
+
+		if (start_erase_addr != FLASH_PAGE_ADDR(start_erase_addr)) {
+			if (page_have_writen(FLASH_PAGE_ADDR(start_erase_addr), (start_erase_addr - 1)))
+				page_need_save = TRUE;
+		}
+		if (end_erase_addr != FLASH_PAGEEND_ADDR(end_erase_addr)) {
+			if (page_have_writen((end_erase_addr + 1), FLASH_PAGEEND_ADDR(end_erase_addr)))
+				page_need_save = TRUE;
+		}
+
+		if (page_need_save) {
+			if (ERROR == ald_flash_read((uint32_t *)write_buf, FLASH_PAGE_ADDR(start_erase_addr),
+			                                                     FLASH_PAGE_SIZE >> 2)) {
+				__enable_irq();
+				return ERROR;
+			}
+		}
+
+		if (ERROR == flash_page_erase(FLASH_PAGE_ADDR(start_erase_addr))) {
+			__enable_irq();
+			return ERROR;
+		}
+
+		if (page_need_save) {
+			para  = end_erase_addr & (FLASH_PAGE_SIZE - 1);
+			index = start_erase_addr & (FLASH_PAGE_SIZE - 1);
+
+			while (index <= para)
+				write_buf[index++] = 0xFF;
+
+			index     = FLASH_PAGE_ADDR(start_erase_addr);
+			len_index = FLASH_PAGE_SIZE;
+			if (ERROR == flash_word_program(index, (uint32_t *)write_buf, (len_index >> 3), FLASH_FIFO)) {
+				__enable_irq();
+				return ERROR;
+			}
+		}
+		len_not_erase = len_not_erase - (end_erase_addr - start_erase_addr + 1);
+	}
+
+	__enable_irq();
+	return OK;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_gpio.c

@@ -168,77 +168,76 @@
   */
 void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
 {
-    uint32_t i, pos, mask, tmp;
-
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
-    assert_param(IS_GPIO_MODE(init->mode));
-    assert_param(IS_GPIO_ODOS(init->odos));
-    assert_param(IS_GPIO_PUPD(init->pupd));
-    assert_param(IS_GPIO_ODRV(init->odrv));
-    assert_param(IS_GPIO_FLT(init->flt));
-    assert_param(IS_GPIO_TYPE(init->type));
-    assert_param(IS_GPIO_FUNC(init->func));
-
-    for (i = 0; i < 16; ++i)
-    {
-        if (((pin >> i) & 0x1) == 0)
-            continue;
-
-        /* Get position and 2-bits mask */
-        pos  = i << 1;
-        mask = 0x3 << pos;
-
-        /* Set PIN mode */
-        tmp  = READ_REG(GPIOx->MODE);
-        tmp &= ~mask;
-        tmp |= (init->mode << pos);
-        WRITE_REG(GPIOx->MODE, tmp);
-
-        /* Set PIN open-drain or push-pull */
-        tmp  = READ_REG(GPIOx->ODOS);
-        tmp &= ~mask;
-        tmp |= (init->odos << pos);
-        WRITE_REG(GPIOx->ODOS, tmp);
-
-        /* Set PIN push-up or/and push-down */
-        tmp  = READ_REG(GPIOx->PUPD);
-        tmp &= ~mask;
-        tmp |= (init->pupd << pos);
-        WRITE_REG(GPIOx->PUPD, tmp);
-
-        /* Set PIN output driver */
-        tmp  = READ_REG(GPIOx->ODRV);
-        tmp &= ~mask;
-        tmp |= (init->odrv << pos);
-        WRITE_REG(GPIOx->ODRV, tmp);
-
-        /* Get position and 1-bit mask */
-        pos  = i;
-        mask = 0x1 << pos;
-
-        /* Set PIN filter enable or disable */
-        tmp  = READ_REG(GPIOx->FLT);
-        tmp &= ~mask;
-        tmp |= (init->flt << pos);
-        WRITE_REG(GPIOx->FLT, tmp);
-
-        /* Set PIN type ttl or smit */
-        tmp  = READ_REG(GPIOx->TYPE);
-        tmp &= ~mask;
-        tmp |= (init->type << pos);
-        WRITE_REG(GPIOx->TYPE, tmp);
-
-        /* Configure PIN function */
-        pos  = i < 8 ? (i << 2) : ((i - 8) << 2);
-        mask = 0xF << pos;
-        tmp  = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1);
-        tmp &= ~mask;
-        tmp |= (init->func << pos);
-        i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp);
-    }
-
-    return;
+	uint32_t i, pos, mask, tmp;
+
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_MODE(init->mode));
+	assert_param(IS_GPIO_ODOS(init->odos));
+	assert_param(IS_GPIO_PUPD(init->pupd));
+	assert_param(IS_GPIO_ODRV(init->odrv));
+	assert_param(IS_GPIO_FLT(init->flt));
+	assert_param(IS_GPIO_TYPE(init->type));
+	assert_param(IS_GPIO_FUNC(init->func));
+
+	for (i = 0; i < 16; ++i) {
+		if (((pin >> i) & 0x1) == 0)
+			continue;
+
+		/* Get position and 2-bits mask */
+		pos  = i << 1;
+		mask = 0x3 << pos;
+
+		/* Set PIN mode */
+		tmp  = READ_REG(GPIOx->MODE);
+		tmp &= ~mask;
+		tmp |= (init->mode << pos);
+		WRITE_REG(GPIOx->MODE, tmp);
+
+		/* Set PIN open-drain or push-pull */
+		tmp  = READ_REG(GPIOx->ODOS);
+		tmp &= ~mask;
+		tmp |= (init->odos << pos);
+		WRITE_REG(GPIOx->ODOS, tmp);
+
+		/* Set PIN push-up or/and push-down */
+		tmp  = READ_REG(GPIOx->PUPD);
+		tmp &= ~mask;
+		tmp |= (init->pupd << pos);
+		WRITE_REG(GPIOx->PUPD, tmp);
+
+		/* Set PIN output driver */
+		tmp  = READ_REG(GPIOx->ODRV);
+		tmp &= ~mask;
+		tmp |= (init->odrv << pos);
+		WRITE_REG(GPIOx->ODRV, tmp);
+
+		/* Get position and 1-bit mask */
+		pos  = i;
+		mask = 0x1 << pos;
+
+		/* Set PIN filter enable or disable */
+		tmp  = READ_REG(GPIOx->FLT);
+		tmp &= ~mask;
+		tmp |= (init->flt << pos);
+		WRITE_REG(GPIOx->FLT, tmp);
+
+		/* Set PIN type ttl or smit */
+		tmp  = READ_REG(GPIOx->TYPE);
+		tmp &= ~mask;
+		tmp |= (init->type << pos);
+		WRITE_REG(GPIOx->TYPE, tmp);
+
+		/* Configure PIN function */
+		pos  = i < 8 ? (i << 2) : ((i - 8) << 2);
+		mask = 0xF << pos;
+		tmp  = i < 8 ? READ_REG(GPIOx->FUNC0) : READ_REG(GPIOx->FUNC1);
+		tmp &= ~mask;
+		tmp |= (init->func << pos);
+		i < 8 ? WRITE_REG(GPIOx->FUNC0, tmp) : WRITE_REG(GPIOx->FUNC1, tmp);
+	}
+
+	return;
 }
 
 /**
@@ -249,19 +248,19 @@ void ald_gpio_init(GPIO_TypeDef *GPIOx, uint16_t pin, gpio_init_t *init)
   */
 void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
 {
-    gpio_init_t init;
-
-    /* Fill GPIO_init_t structure with default parameter */
-    init.mode = GPIO_MODE_OUTPUT;
-    init.odos = GPIO_PUSH_PULL;
-    init.pupd = GPIO_PUSH_UP;
-    init.odrv = GPIO_OUT_DRIVE_NORMAL;
-    init.flt  = GPIO_FILTER_DISABLE;
-    init.type = GPIO_TYPE_CMOS;
-    init.func = GPIO_FUNC_1;
-
-    ald_gpio_init(GPIOx, pin, &init);
-    return;
+	gpio_init_t init;
+
+	/* Fill GPIO_init_t structure with default parameter */
+	init.mode = GPIO_MODE_OUTPUT;
+	init.odos = GPIO_PUSH_PULL;
+	init.pupd = GPIO_PUSH_UP;
+	init.odrv = GPIO_OUT_DRIVE_NORMAL;
+	init.flt  = GPIO_FILTER_DISABLE;
+	init.type = GPIO_TYPE_CMOS;
+	init.func = GPIO_FUNC_1;
+
+	ald_gpio_init(GPIOx, pin, &init);
+	return;
 }
 
 /**
@@ -271,10 +270,10 @@ void ald_gpio_init_default(GPIO_TypeDef *GPIOx, uint16_t pin)
   */
 void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
 {
-    WRITE_REG(GPIOx->FUNC0, 0x00);
-    WRITE_REG(GPIOx->FUNC1, 0x00);
+	WRITE_REG(GPIOx->FUNC0, 0x00);
+	WRITE_REG(GPIOx->FUNC1, 0x00);
 
-    return;
+	return;
 }
 
 /**
@@ -288,67 +287,62 @@ void ald_gpio_func_default(GPIO_TypeDef *GPIOx)
   */
 void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
 {
-    uint8_t i;
-    uint8_t port;
-
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
-    assert_param(IS_FUNC_STATE(init->filter));
-    assert_param(IS_EXTI_FLTCKS_TYPE(init->cks));
-
-    /* Get GPIO port */
-    if (GPIOx == GPIOA)
-        port = 0x0;
-    else if (GPIOx == GPIOB)
-        port = 0x1;
-    else if (GPIOx == GPIOC)
-        port = 2;
-    else if (GPIOx == GPIOD)
-        port = 3;
-    else if (GPIOx == GPIOE)
-        port = 4;
-    else if (GPIOx == GPIOF)
-        port = 5;
-    else if (GPIOx == GPIOG)
-        port = 6;
-    else if (GPIOx == GPIOH)
-        port = 7;
-    else
-        port = 0;
-
-    /* Get Pin index */
-    for (i = 0; i < 16; ++i)
-    {
-        if (((pin >> i) & 0x1) == 0x1)
-            break;
-    }
-
-    /* Select external interrupt line */
-    if (i <= 7)
-    {
-        EXTI->EXTIPSR0 &= ~(0x7 << (i * 4));
-        EXTI->EXTIPSR0 |= (port << (i * 4));
-    }
-    else
-    {
-        i -= 8;
-        EXTI->EXTIPSR1 &= ~(0x7 << (i * 4));
-        EXTI->EXTIPSR1 |= (port << (i * 4));
-    }
-
-    /* Configure filter parameter */
-    if (init->filter == ENABLE)
-    {
-        SET_BIT(EXTI->EXTIFLTCR, pin);
-        MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
-        MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
-    }
-    else
-    {
-        CLEAR_BIT(EXTI->EXTIFLTCR, pin);
-    }
-
-    return;
+	uint8_t i;
+	uint8_t port;
+
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_FUNC_STATE(init->filter));
+	assert_param(IS_EXTI_FLTCKS_TYPE(init->cks));
+
+	/* Get GPIO port */
+	if (GPIOx == GPIOA)
+		port = 0x0;
+	else if (GPIOx == GPIOB)
+		port = 0x1;
+	else if (GPIOx == GPIOC)
+		port = 2;
+	else if (GPIOx == GPIOD)
+		port = 3;
+	else if (GPIOx == GPIOE)
+		port = 4;
+	else if (GPIOx == GPIOF)
+		port = 5;
+	else if (GPIOx == GPIOG)
+		port = 6;
+	else if (GPIOx == GPIOH)
+		port = 7;
+	else
+		port = 0;
+
+	/* Get Pin index */
+	for (i = 0; i < 16; ++i) {
+		if (((pin >> i) & 0x1) == 0x1)
+			break;
+	}
+
+	/* Select external interrupt line */
+	if (i <= 7) {
+		EXTI->EXTIPSR0 &= ~(0x7U << (i * 4));
+		EXTI->EXTIPSR0 |= (port << (i * 4));
+	}
+	else {
+		i -= 8;
+		EXTI->EXTIPSR1 &= ~(0x7U << (i * 4));
+		EXTI->EXTIPSR1 |= (port << (i * 4));
+	}
+
+	/* Configure filter parameter */
+	if (init->filter == ENABLE) {
+		SET_BIT(EXTI->EXTIFLTCR, pin);
+		MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTCKS_MSK, init->cks << GPIO_EXTIFLTCR_FLTCKS_POSS);
+		MODIFY_REG(EXTI->EXTIFLTCR, GPIO_EXTIFLTCR_FLTSEL_MSK, init->filter_time << GPIO_EXTIFLTCR_FLTSEL_POSS);
+	}
+	else {
+		CLEAR_BIT(EXTI->EXTIFLTCR, pin);
+	}
+
+	return;
 }
 /**
   * @}
@@ -373,19 +367,16 @@ void ald_gpio_exti_init(GPIO_TypeDef *GPIOx, uint16_t pin, exti_init_t *init)
   * @param  GPIOx: Where x can be (A--H) to select the GPIO peripheral.
   * @param  pin: Specifies the pin to read.
   * @retval The input pin value
-  *         - BIT_SET
-  *         - BIT_RESET
   */
 uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
 {
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
 
-    if (READ_BIT(GPIOx->DIN, pin))
-        return BIT_SET;
-
-    else
-        return BIT_RESET;
+	if (READ_BIT(GPIOx->DIN, pin))
+		return 1;
+	else
+		return 0;
 }
 
 /**
@@ -397,15 +388,15 @@ uint8_t ald_gpio_read_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
   */
 void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
 {
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
 
-    if ((val & (0x01)) == 0x00)
-        CLEAR_BIT(GPIOx->DOUT, pin);
-    else
-        SET_BIT(GPIOx->DOUT, pin);
+	if ((val & (0x01)) == 0x00)
+		CLEAR_BIT(GPIOx->DOUT, pin);
+	else
+		SET_BIT(GPIOx->DOUT, pin);
 
-    return;
+	return;
 }
 
 /**
@@ -416,11 +407,11 @@ void ald_gpio_write_pin(GPIO_TypeDef *GPIOx, uint16_t pin, uint8_t val)
   */
 void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
 {
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
 
-    WRITE_REG(GPIOx->BIR, pin);
-    return;
+	WRITE_REG(GPIOx->BIR, pin);
+	return;
 }
 
 /**
@@ -431,42 +422,39 @@ void ald_gpio_toggle_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
   */
 void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
 {
-    uint32_t i, pos, mask, tmp, value;
-
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
-
-    for (i = 0; i < 16; ++i)
-    {
-        if (((pin >> i) & 0x1) == 0)
-            continue;
-
-        /* Get position and 2-bits mask */
-        pos  = i << 1;
-        mask = 0x3 << pos;
-
-        /* Get the new direction */
-        tmp = READ_REG(GPIOx->MODE);
-        value = (tmp >> pos) & 0x3;
-
-        if ((value == 2) || (value == 3))
-            value = 1;
-        else if (value == 1)
-        {
-            value = 2;
-        }
-        else
-        {
-            continue; /* do nothing */
-        }
-
-        /* Set PIN mode */
-        tmp &= ~mask;
-        tmp |= (value << pos);
-        WRITE_REG(GPIOx->MODE, tmp);
-    }
-
-    return;
+	uint32_t i, pos, mask, tmp, value;
+
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
+
+	for (i = 0; i < 16; ++i) {
+		if (((pin >> i) & 0x1) == 0)
+			continue;
+
+		/* Get position and 2-bits mask */
+		pos  = i << 1;
+		mask = 0x3 << pos;
+
+		/* Get the new direction */
+		tmp = READ_REG(GPIOx->MODE);
+		value = (tmp >> pos) & 0x3;
+
+		if ((value == 2) || (value == 3))
+			value = 1;
+		else if (value == 1) {
+			value = 2;
+		}
+		else {
+			continue; /* do nothing */
+		}
+
+		/* Set PIN mode */
+		tmp &= ~mask;
+		tmp |= (value << pos);
+		WRITE_REG(GPIOx->MODE, tmp);
+	}
+
+	return;
 }
 
 /**
@@ -479,13 +467,13 @@ void ald_gpio_toggle_dir(GPIO_TypeDef *GPIOx, uint16_t pin)
   */
 void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
 {
-    assert_param(IS_GPIO_PORT(GPIOx));
-    assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PIN(pin));
 
-    MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS);
-    WRITE_REG(GPIOx->LOCK, pin);
+	MODIFY_REG(GPIOx->LOCK, GPIO_LOCK_KEY_MSK, UNLOCK_KEY << GPIO_LOCK_KEY_POSS);
+	WRITE_REG(GPIOx->LOCK, pin);
 
-    return;
+	return;
 }
 
 /**
@@ -495,9 +483,9 @@ void ald_gpio_lock_pin(GPIO_TypeDef *GPIOx, uint16_t pin)
   */
 uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
 {
-    assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PORT(GPIOx));
 
-    return READ_REG(GPIOx->DIN);
+	return READ_REG(GPIOx->DIN);
 }
 
 /**
@@ -508,10 +496,10 @@ uint16_t ald_gpio_read_port(GPIO_TypeDef *GPIOx)
   */
 void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
 {
-    assert_param(IS_GPIO_PORT(GPIOx));
+	assert_param(IS_GPIO_PORT(GPIOx));
 
-    WRITE_REG(GPIOx->DOUT, val);
-    return;
+	WRITE_REG(GPIOx->DOUT, val);
+	return;
 }
 
 
@@ -545,57 +533,47 @@ void ald_gpio_write_port(GPIO_TypeDef *GPIOx, uint16_t val)
   */
 void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, type_func_t status)
 {
-    assert_param(IS_GPIO_PIN(pin));
-    assert_param(IS_TRIGGER_STYLE(style));
-    assert_param(IS_FUNC_STATE(status));
-
-    if (status == ENABLE)
-    {
-        if (style == EXTI_TRIGGER_RISING_EDGE)
-        {
-            SET_BIT(EXTI->EXTIRER, pin);
-        }
-        else if (style == EXTI_TRIGGER_TRAILING_EDGE)
-        {
-            SET_BIT(EXTI->EXTIFER, pin);
-        }
-        else if (style == EXTI_TRIGGER_BOTH_EDGE)
-        {
-            SET_BIT(EXTI->EXTIRER, pin);
-            SET_BIT(EXTI->EXTIFER, pin);
-        }
-        else
-        {
-            ; /* do nothing */
-        }
-
-        WRITE_REG(EXTI->EXTICFR, 0xffff);
-        SET_BIT(EXTI->EXTIEN, pin);
-    }
-    else
-    {
-        if (style == EXTI_TRIGGER_RISING_EDGE)
-        {
-            CLEAR_BIT(EXTI->EXTIRER, pin);
-        }
-        else if (style == EXTI_TRIGGER_TRAILING_EDGE)
-        {
-            CLEAR_BIT(EXTI->EXTIFER, pin);
-        }
-        else if (style == EXTI_TRIGGER_BOTH_EDGE)
-        {
-            CLEAR_BIT(EXTI->EXTIRER, pin);
-            CLEAR_BIT(EXTI->EXTIFER, pin);
-        }
-        else
-        {
-            ; /* do nothing */
-        }
-
-        CLEAR_BIT(EXTI->EXTIEN, pin);
-    }
-
-    return;
+	assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_TRIGGER_STYLE(style));
+	assert_param(IS_FUNC_STATE(status));
+
+	if (status == ENABLE) {
+		if (style == EXTI_TRIGGER_RISING_EDGE) {
+			SET_BIT(EXTI->EXTIRER, pin);
+		}
+		else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
+			SET_BIT(EXTI->EXTIFER, pin);
+		}
+		else if (style == EXTI_TRIGGER_BOTH_EDGE) {
+			SET_BIT(EXTI->EXTIRER, pin);
+			SET_BIT(EXTI->EXTIFER, pin);
+		}
+		else {
+			; /* do nothing */
+		}
+
+		WRITE_REG(EXTI->EXTICFR, 0xffff);
+		SET_BIT(EXTI->EXTIEN, pin);
+	}
+	else {
+		if (style == EXTI_TRIGGER_RISING_EDGE) {
+			CLEAR_BIT(EXTI->EXTIRER, pin);
+		}
+		else if (style == EXTI_TRIGGER_TRAILING_EDGE) {
+			CLEAR_BIT(EXTI->EXTIFER, pin);
+		}
+		else if (style == EXTI_TRIGGER_BOTH_EDGE) {
+			CLEAR_BIT(EXTI->EXTIRER, pin);
+			CLEAR_BIT(EXTI->EXTIFER, pin);
+		}
+		else {
+			; /* do nothing */
+		}
+
+		CLEAR_BIT(EXTI->EXTIEN, pin);
+	}
+
+	return;
 }
 
 /**
@@ -607,12 +585,12 @@ void ald_gpio_exti_interrupt_config(uint16_t pin, exti_trigger_style_t style, ty
   */
 flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
 {
-    assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_PIN(pin));
 
-    if (READ_BIT(EXTI->EXTIFLAG, pin))
-        return SET;
+	if (READ_BIT(EXTI->EXTIFLAG, pin))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -622,10 +600,10 @@ flag_status_t ald_gpio_exti_get_flag_status(uint16_t pin)
   */
 void ald_gpio_exti_clear_flag_status(uint16_t pin)
 {
-    assert_param(IS_GPIO_PIN(pin));
+	assert_param(IS_GPIO_PIN(pin));
 
-    WRITE_REG(EXTI->EXTICFR, pin);
-    return;
+	WRITE_REG(EXTI->EXTICFR, pin);
+	return;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_iap.c

@@ -51,14 +51,14 @@
   */
 uint32_t ald_iap_erase_page(uint32_t addr)
 {
-    uint32_t status;
-    IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
+	uint32_t status;
+	IAP_PE iap_pe = (IAP_PE)(*(uint32_t *)IAP_PE_ADDR);
 
-    __disable_irq();
-    status = (*iap_pe)(addr);
-    __enable_irq();
+	__disable_irq();
+	status = (*iap_pe)(addr);
+	__enable_irq();
 
-    return !status;
+	return !status;
 }
 
 /**
@@ -72,17 +72,17 @@ uint32_t ald_iap_erase_page(uint32_t addr)
   */
 uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
 {
-    uint32_t status;
-    IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
+	uint32_t status;
+	IAP_WP iap_wp = (IAP_WP)(*(uint32_t *)IAP_WP_ADDR);
 
-    if (addr & 0x3)
-        return 1;
+	if (addr & 0x3)
+		return 1;
 
-    __disable_irq();
-    status = (*iap_wp)(addr, data);
-    __enable_irq();
+	__disable_irq();
+	status = (*iap_wp)(addr, data);
+	__enable_irq();
 
-    return !status;
+	return !status;
 }
 
 /**
@@ -97,17 +97,17 @@ uint32_t ald_iap_program_word(uint32_t addr, uint32_t data)
   */
 uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
 {
-    uint32_t status;
-    IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
+	uint32_t status;
+	IAP_DWP iap_dwp = (IAP_DWP)(*(uint32_t *)IAP_DWP_ADDR);
 
-    if (addr & 0x3)
-        return 1;
+	if (addr & 0x3)
+		return 1;
 
-    __disable_irq();
-    status = (*iap_dwp)(addr, data_l, data_h);
-    __enable_irq();
+	__disable_irq();
+	status = (*iap_dwp)(addr, data_l, data_h);
+	__enable_irq();
 
-    return !status;
+	return !status;
 }
 
 /**
@@ -124,17 +124,17 @@ uint32_t ald_iap_program_dword(uint32_t addr, uint32_t data_l, uint32_t data_h)
   */
 uint32_t ald_iap_program_words(uint32_t addr, uint8_t *data, uint32_t len, uint32_t erase)
 {
-    uint32_t status;
-    IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
+	uint32_t status;
+	IAP_WSP iap_wsp = (IAP_WSP)(*(uint32_t *)IAP_WSP_ADDR);
 
-    if ((addr & 0x3) || (len & 0x3))
-        return 1;
+	if ((addr & 0x3) || (len & 0x3))
+		return 1;
 
-    __disable_irq();
-    status = (*iap_wsp)(addr, data, len, erase);
-    __enable_irq();
+	__disable_irq();
+	status = (*iap_wsp)(addr, data, len, erase);
+	__enable_irq();
 
-    return !status;
+	return !status;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lcd.c

@@ -1,18 +1,18 @@
-/**
-  *********************************************************************************
-  *
-  * @file    ald_lcd.c
-  * @brief   LCD module driver.
-  *
-  * @version V1.0
-  * @date    29 Nov 2017
-  * @author  AE Team
-  * @note
-  *
-  * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
-  *
-  *********************************************************************************
-  */
+ /**
+   *********************************************************************************
+   *
+   * @file    ald_lcd.c
+   * @brief   LCD module driver.
+   *
+   * @version V1.0
+   * @date    29 Nov 2017
+   * @author  AE Team
+   * @note
+   *
+   * Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
+   *
+   *********************************************************************************
+   */
 
 #include "ald_lcd.h"
 
@@ -44,53 +44,51 @@
   */
 ald_status_t ald_lcd_init(lcd_handle_t *hperh)
 {
-    uint16_t delay = 0;
-
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps));
-    assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel));
-    assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld));
-    assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd));
-    assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld));
-    assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd));
-    assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld));
-    assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd));
-    assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias));
-    assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty));
-    assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs));
-    assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs));
-    assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div));
-    assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead));
-    assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon));
-    assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs));
-
-    __LOCK(hperh);
-
-    ald_cmu_lcd_clock_select(hperh->init.clock);
-
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS);
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS);
-
-    for (delay = 0; delay < 3000; delay++);
-
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS);
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS);
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS);
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS);
-
-    MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS);
-
-    __UNLOCK(hperh);
-    return OK;
+	uint16_t delay = 0;
+
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_VCHPS_TYPE(hperh->init.lcd_vchps));
+	assert_param(IS_LCD_VSEL_TYPE(hperh->init.lcd_vsel));
+	assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufld));
+	assert_param(IS_LCD_FUNC_TYPE(hperh->init.lcd_vbufhd));
+	assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dsld));
+	assert_param(IS_LCD_LEVEL_TYPE(hperh->init.lcd_dshd));
+	assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_resld));
+	assert_param(IS_LCD_RES_TYPE(hperh->init.lcd_reshd));
+	assert_param(IS_LCD_BIAS_TYPE(hperh->init.lcd_bias));
+	assert_param(IS_LCD_DUTY_TYPE(hperh->init.lcd_duty));
+	assert_param(IS_LCD_WFS_TYPE(hperh->init.lcd_wfs));
+	assert_param(IS_LCD_PRS_TYPE(hperh->init.lcd_prs));
+	assert_param(IS_LCD_DIV_TYPE(hperh->init.lcd_div));
+	assert_param(IS_LCD_DEAD_TYPE(hperh->init.lcd_dead));
+	assert_param(IS_LCD_PON_TYPE(hperh->init.lcd_pon));
+	assert_param(IS_LCD_VGS_TYPE(hperh->init.lcd_vgs));
+
+	__LOCK(hperh);
+
+	ald_cmu_lcd_clock_select(hperh->init.clock);
+
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_WFS_MSK, hperh->init.lcd_wfs << LCD_FCR_WFS_POS);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_PRS_MSK, hperh->init.lcd_prs << LCD_FCR_PRS_POSS);
+	for (delay = 0; delay < 3000; delay++);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_DIV_MSK, hperh->init.lcd_div << LCD_FCR_DIV_POSS);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_DEAD_MSK, hperh->init.lcd_dead << LCD_FCR_DEAD_POSS);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_PON_MSK, hperh->init.lcd_pon << LCD_FCR_PON_POSS);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_VGS_MSK, hperh->init.lcd_vgs << LCD_FCR_VGS_POSS);
+
+	MODIFY_REG(hperh->perh->CR, LCD_CR_DUTY_MSK, hperh->init.lcd_duty << LCD_CR_DUTY_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_BIAS_MSK, hperh->init.lcd_bias << LCD_CR_BIAS_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFHD_MSK, hperh->init.lcd_vbufhd << LCD_CR_VBUFHD_POS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_VBUFLD_MSK, hperh->init.lcd_vbufld << LCD_CR_VBUFLD_POS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_DSHD_MSK, hperh->init.lcd_dshd << LCD_CR_DSHD_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_DSLD_MSK, hperh->init.lcd_dsld << LCD_CR_DSLD_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_RESHD_MSK, hperh->init.lcd_reshd << LCD_CR_RESHD_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_RESLD_MSK, hperh->init.lcd_resld << LCD_CR_RESLD_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_VSEL_MSK, hperh->init.lcd_vsel << LCD_CR_VSEL_POSS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_VCHPS_MSK, hperh->init.lcd_vchps << LCD_CR_VCHPS_POSS);
+
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -102,16 +100,16 @@ ald_status_t ald_lcd_init(lcd_handle_t *hperh)
   */
 ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_FUNC_STATE(state));
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_FUNC_STATE(state));
 
-    __LOCK(hperh);
+	__LOCK(hperh);
 
-    MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS);
-    MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_OE_MSK, state << LCD_CR_OE_POS);
+	MODIFY_REG(hperh->perh->CR, LCD_CR_EN_MSK, state << LCD_CR_EN_POS);
 
-    __UNLOCK(hperh);
-    return OK;
+	__UNLOCK(hperh);
+	return OK;
 }
 /**
   * @}
@@ -132,21 +130,19 @@ ald_status_t ald_lcd_cmd(lcd_handle_t *hperh, type_func_t state)
   */
 ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, lcd_blfrq_t blink_freq)
 {
-    uint16_t delay = 0;
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_BLINK_MODE(blink_mode));
-    assert_param(IS_LCD_BLFRQ_TYPE(blink_freq));
-    __LOCK(hperh);
-
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS);
+	uint16_t delay = 0;
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_BLINK_MODE(blink_mode));
+	assert_param(IS_LCD_BLFRQ_TYPE(blink_freq));
+	__LOCK(hperh);
 
-    for (delay = 0; delay < 3000; delay++);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLMOD_MSK, blink_mode << LCD_FCR_BLMOD_POSS);
+	for (delay = 0; delay < 3000; delay++);
+	MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS);
 
-    MODIFY_REG(hperh->perh->FCR, LCD_FCR_BLFRQ_MSK, blink_freq << LCD_FCR_BLFRQ_POSS);
-
-    __UNLOCK(hperh);
-    return OK;
-}
+	__UNLOCK(hperh);
+	return OK;
+ }
 
 /**
   * @brief Control segment port enable or disable
@@ -158,17 +154,17 @@ ald_status_t ald_lcd_blink_config(lcd_handle_t *hperh, lcd_blink_t blink_mode, l
   */
 ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_data)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_SEG_TYPE(seg));
-    __LOCK(hperh);
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_SEG_TYPE(seg));
+	__LOCK(hperh);
 
-    if (seg == SEG_0_TO_31)
-        WRITE_REG(hperh->perh->SEGCR0, seg_data);
-    else
-        WRITE_REG(hperh->perh->SEGCR1, seg_data);
+	if (seg == SEG_0_TO_31)
+		WRITE_REG(hperh->perh->SEGCR0, seg_data);
+	else
+		WRITE_REG(hperh->perh->SEGCR1, seg_data);
 
-    __UNLOCK(hperh);
-    return OK;
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -181,14 +177,14 @@ ald_status_t ald_lcd_write_seg(lcd_handle_t *hperh, lcd_seg_t seg, uint32_t seg_
   */
 ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_BUFFER_TYPE(buf));
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_BUFFER_TYPE(buf));
 
-    __LOCK(hperh);
-    WRITE_REG(hperh->perh->BUF[buf], buf_data);
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	WRITE_REG(hperh->perh->BUF[buf], buf_data);
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 /**
   * @}
@@ -208,13 +204,13 @@ ald_status_t ald_lcd_write(lcd_handle_t *hperh, uint8_t buf, uint32_t buf_data)
   */
 uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_STATUS_TYPE(lcd_status));
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_STATUS_TYPE(lcd_status));
 
-    if (lcd_status == LCD_STATUS_ALL)
-        return hperh->perh->SR;
-    else
-        return hperh->perh->SR & lcd_status ? 1 : 0;
+	if (lcd_status == LCD_STATUS_ALL)
+		return hperh->perh->SR;
+	else
+		return hperh->perh->SR & lcd_status ? 1 : 0;
 }
 /**
   * @}
@@ -238,18 +234,18 @@ uint32_t ald_lcd_get_status(lcd_handle_t *hperh, lcd_status_t lcd_status)
   */
 ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_func_t state)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_IT_TYPE(it));
-    assert_param(IS_FUNC_STATE(state));
-    __LOCK(hperh);
-
-    if (state)
-        SET_BIT(hperh->perh->IE, it);
-    else
-        CLEAR_BIT(hperh->perh->IE, it);
-
-    __UNLOCK(hperh);
-    return OK;
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_IT_TYPE(it));
+	assert_param(IS_FUNC_STATE(state));
+	__LOCK(hperh);
+
+	if (state)
+		SET_BIT(hperh->perh->IE, it);
+	else
+		CLEAR_BIT(hperh->perh->IE, it);
+
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -264,10 +260,10 @@ ald_status_t ald_lcd_interrupt_config(lcd_handle_t *hperh, lcd_it_t it, type_fun
   */
 flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_IT_TYPE(it));
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_IT_TYPE(it));
 
-    return hperh->perh->IE & it ? SET : RESET;
+	return hperh->perh->IE & it ? SET : RESET;
 }
 
 /**
@@ -282,10 +278,10 @@ flag_status_t ald_lcd_get_it_status(lcd_handle_t *hperh, lcd_it_t it)
   */
 it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_FLAG_TYPE(flag));
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_FLAG_TYPE(flag));
 
-    return hperh->perh->IF & flag ? SET : RESET;
+	return hperh->perh->IF & flag ? SET : RESET;
 }
 
 /**
@@ -300,14 +296,14 @@ it_status_t ald_lcd_get_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
   */
 ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
 {
-    assert_param(IS_LCD_PERH_TYPE(hperh->perh));
-    assert_param(IS_LCD_FLAG_TYPE(flag));
+	assert_param(IS_LCD_PERH_TYPE(hperh->perh));
+	assert_param(IS_LCD_FLAG_TYPE(flag));
 
-    __LOCK(hperh);
-    WRITE_REG(hperh->perh->IFCR, flag);
-    __UNLOCK(hperh);
+	__LOCK(hperh);
+	WRITE_REG(hperh->perh->IFCR, flag);
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -318,23 +314,21 @@ ald_status_t ald_lcd_clear_flag_status(lcd_handle_t *hperh, lcd_flag_t flag)
   */
 void ald_lcd_irq_handler(lcd_handle_t *hperh)
 {
-    if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD))
-    {
-        ald_lcd_clear_flag_status(hperh, LCD_FLAG_UDD);
+	if (ald_lcd_get_flag_status(hperh, LCD_FLAG_UDD)) {
+		ald_lcd_clear_flag_status(hperh, LCD_FLAG_UDD);
 
-        if (hperh->display_cplt_cbk)
-            hperh->display_cplt_cbk(hperh);
-    }
+		if (hperh->display_cplt_cbk)
+			hperh->display_cplt_cbk(hperh);
+	}
 
-    if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF))
-    {
-        ald_lcd_clear_flag_status(hperh, LCD_FLAG_SOF);
+	if (ald_lcd_get_flag_status(hperh, LCD_FLAG_SOF)) {
+		ald_lcd_clear_flag_status(hperh, LCD_FLAG_SOF);
 
-        if (hperh->frame_start_cbk)
-            hperh->frame_start_cbk(hperh);
-    }
+		if (hperh->frame_start_cbk)
+			hperh->frame_start_cbk(hperh);
+	}
 
-    return;
+	return;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_lptim.c

@@ -44,14 +44,14 @@
   */
 void ald_lptim_reset(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM(hperh->perh));
 
-    hperh->state = LPTIM_STATE_BUSY;
-    LPTIM_DISABLE(hperh);
-    hperh->state = LPTIM_STATE_RESET;
-    __UNLOCK(hperh);
+	hperh->state = LPTIM_STATE_BUSY;
+	LPTIM_DISABLE(hperh);
+	hperh->state = LPTIM_STATE_RESET;
+	__UNLOCK(hperh);
 
-    return;
+	return;
 }
 
 /**
@@ -63,14 +63,14 @@ void ald_lptim_reset(lptim_handle_t *hperh)
   */
 void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *config)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_TRIGEN(config->mode));
-    assert_param(IS_LPTIM_TRIGSEL(config->sel));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_TRIGEN(config->mode));
+	assert_param(IS_LPTIM_TRIGSEL(config->sel));
 
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGEN_MSK, (config->mode) << LP16T_CON0_TRIGEN_POSS);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGSEL_MSK, (config->sel) << LP16T_CON0_TRIGSEL_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGEN_MSK, (config->mode) << LP16T_CON0_TRIGEN_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRIGSEL_MSK, (config->sel) << LP16T_CON0_TRIGSEL_POSS);
 
-    return;
+	return;
 }
 
 /**
@@ -82,14 +82,14 @@ void ald_lptim_trigger_config(lptim_handle_t *hperh, lptim_trigger_init_t *confi
   */
 void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_init_t *config)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_CKSEL(config->sel));
-    assert_param(IS_LPTIM_CKPOL(config->polarity));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_CKSEL(config->sel));
+	assert_param(IS_LPTIM_CKPOL(config->polarity));
 
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKSEL_MSK, (config->sel) << LP16T_CON0_CKSEL_POS);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKPOL_MSK, (config->polarity) << LP16T_CON0_CKPOL_POS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKSEL_MSK, (config->sel) << LP16T_CON0_CKSEL_POS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKPOL_MSK, (config->polarity) << LP16T_CON0_CKPOL_POS);
 
-    return;
+	return;
 }
 
 /**
@@ -101,12 +101,12 @@ void ald_lptim_clock_source_config(lptim_handle_t *hperh, lptim_clock_source_ini
   */
 void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_TRGFLT(flt));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_TRGFLT(flt));
 
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRGFLT_MSK, flt << LP16T_CON0_TRGFLT_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_TRGFLT_MSK, flt << LP16T_CON0_TRGFLT_POSS);
 
-    return;
+	return;
 }
 
 /**
@@ -118,19 +118,145 @@ void ald_lptim_trigger_filter_config(lptim_handle_t *hperh, lptim_trgflt_t flt)
   */
 void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_TRGFLT(flt));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_CKFLT(flt));
 
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_CKFLT_MSK, flt << LP16T_CON0_CKFLT_POSS);
 
-    return;
+	return;
 }
 /**
   * @}
   */
 
-/** @defgroup LPTIM_Public_Functions_Group2 LPTIM output toggle functions
-  *  @brief    LPTime output toggle functions
+/** @defgroup LPTIM_Public_Functions_Group2 LPTIM base functions
+  *  @brief   LPTIM base functions
+  *
+  * @verbatim
+  ==============================================================================
+                  ##### Low Pow Time Base functions #####
+  ==============================================================================
+  [..]
+    This section provides functions allowing to:
+    (+) Initialize the LPTIM .
+    (+) Start the LPTIM.
+    (+) Stop the LPTIM.
+    (+) Start the LPTIM and enable interrupt.
+    (+) Stop the LPTIM and disable interrupt.
+
+    @endverbatim
+  * @{
+  */
+/**
+  * @brief  Initializes the TIM according to the specified
+  *		parameters in the tim_handle_t.
+  * @param  hperh: LPTIM handle
+  * @retval Status, see @ref ald_status_t.
+  */
+ald_status_t ald_lptim_base_init(lptim_handle_t *hperh)
+{
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
+
+	__LOCK(hperh);
+	hperh->state = LPTIM_STATE_BUSY;
+
+	ald_cmu_lptim0_clock_select(hperh->init.clock);
+
+	WRITE_REG(hperh->perh->UPDATE, 1);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_NONE << LP16T_CON0_WAVE_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
+	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
+	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
+	WRITE_REG(hperh->perh->UPDATE, 0);
+
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
+
+	hperh->state = LPTIM_STATE_READY;
+	__UNLOCK(hperh);
+	return OK;
+}
+
+/**
+  * @brief  Starts the LPTIM.
+  * @param  hperh: LPTIM handle
+  * @retval None
+  */
+void ald_lptim_base_start(lptim_handle_t *hperh)
+{
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
+
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
+
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
+}
+
+/**
+  * @brief  Stops the LPTIM.
+  * @param  hperh: LPTIM handle
+  * @retval None
+  */
+void ald_lptim_base_stop(lptim_handle_t *hperh)
+{
+	assert_param(IS_LPTIM(hperh->perh));
+
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
+}
+
+/**
+  * @brief  Starts the LPTIM in interrupt mode.
+  * @param  hperh: LPTIM handle
+  * @retval None
+  */
+void ald_lptim_base_start_by_it(lptim_handle_t *hperh)
+{
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
+
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
+
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
+}
+
+/**
+  * @brief  Stops the LPTIM Output toggle in interrupt mode.
+  * @param  hperh: LPTIM handle
+  * @retval None
+  */
+void ald_lptim_base_stop_by_it(lptim_handle_t *hperh)
+{
+	assert_param(IS_LPTIM(hperh->perh));
+
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
+}
+/**
+  * @}
+  */
+
+/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output toggle functions
+  *  @brief   LPTIM output toggle functions
   *
   * @verbatim
   ==============================================================================
@@ -155,28 +281,27 @@ void ald_lptim_clock_filter_config(lptim_handle_t *hperh, lptim_ckflt_t flt)
   */
 ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_PRESC(hperh->init.psc));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
 
-    __LOCK(hperh);
-    hperh->state = LPTIM_STATE_BUSY;
+	__LOCK(hperh);
+	hperh->state = LPTIM_STATE_BUSY;
 
-    ald_cmu_lptim0_clock_select(hperh->init.clock);
+	ald_cmu_lptim0_clock_select(hperh->init.clock);
 
-    WRITE_REG(hperh->perh->UPDATE, 1);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_TOGGLE << LP16T_CON0_WAVE_POSS);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
-    WRITE_REG(hperh->perh->ARR, hperh->init.arr);
-    WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
-    WRITE_REG(hperh->perh->UPDATE, 0);
+	WRITE_REG(hperh->perh->UPDATE, 1);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_TOGGLE << LP16T_CON0_WAVE_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
+	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
+	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
+	WRITE_REG(hperh->perh->UPDATE, 0);
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
-
-    hperh->state = LPTIM_STATE_READY;
-    __UNLOCK(hperh);
-    return OK;
+	hperh->state = LPTIM_STATE_READY;
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -186,21 +311,19 @@ ald_status_t ald_lptim_toggle_init(lptim_handle_t *hperh)
   */
 void ald_lptim_toggle_start(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-    LPTIM_ENABLE(hperh);
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
 
-    if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-        LPTIM_CNTSTART(hperh);
-    else
-        LPTIM_SNGSTART(hperh);
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
 
-    return;
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -210,13 +333,11 @@ void ald_lptim_toggle_start(lptim_handle_t *hperh)
   */
 void ald_lptim_toggle_stop(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM(hperh->perh));
 
-    LPTIM_DISABLE(hperh);
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-    return;
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -226,22 +347,20 @@ void ald_lptim_toggle_stop(lptim_handle_t *hperh)
   */
 void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-    ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
-    LPTIM_ENABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-        LPTIM_CNTSTART(hperh);
-    else
-        LPTIM_SNGSTART(hperh);
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-    return;
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -251,21 +370,19 @@ void ald_lptim_toggle_start_by_it(lptim_handle_t *hperh)
   */
 void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-
-    ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
-    LPTIM_DISABLE(hperh);
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	assert_param(IS_LPTIM(hperh->perh));
 
-    return;
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 /**
   * @}
   */
 
-/** @defgroup LPTIM_Public_Functions_Group3 LPTIM output pulse functions
-  *  @brief    LPTime output pulse functions
+/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pulse functions
+  *  @brief   LPTIM output pulse functions
   *
   * @verbatim
   ==============================================================================
@@ -290,27 +407,26 @@ void ald_lptim_toggle_stop_by_it(lptim_handle_t *hperh)
   */
 ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_PRESC(hperh->init.psc));
-
-    __LOCK(hperh);
-    hperh->state = LPTIM_STATE_BUSY;
-    ald_cmu_lptim0_clock_select(hperh->init.clock);
-
-    WRITE_REG(hperh->perh->UPDATE, 1);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PULSE << LP16T_CON0_WAVE_POSS);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
-    WRITE_REG(hperh->perh->ARR, hperh->init.arr);
-    WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
-    WRITE_REG(hperh->perh->UPDATE, 0);
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
-
-    hperh->state = LPTIM_STATE_READY;
-    __UNLOCK(hperh);
-    return OK;
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
+
+	__LOCK(hperh);
+	hperh->state = LPTIM_STATE_BUSY;
+	ald_cmu_lptim0_clock_select(hperh->init.clock);
+
+	WRITE_REG(hperh->perh->UPDATE, 1);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PULSE << LP16T_CON0_WAVE_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
+	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
+	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
+	WRITE_REG(hperh->perh->UPDATE, 0);
+
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
+
+	hperh->state = LPTIM_STATE_READY;
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -320,21 +436,19 @@ ald_status_t ald_lptim_pulse_init(lptim_handle_t *hperh)
   */
 void ald_lptim_pulse_start(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-    LPTIM_ENABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-        LPTIM_CNTSTART(hperh);
-    else
-        LPTIM_SNGSTART(hperh);
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-    return;
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -344,13 +458,12 @@ void ald_lptim_pulse_start(lptim_handle_t *hperh)
   */
 void ald_lptim_pulse_stop(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-
-    LPTIM_DISABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    return;
+	return;
 }
 
 /**
@@ -360,22 +473,20 @@ void ald_lptim_pulse_stop(lptim_handle_t *hperh)
   */
 void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_MODE(hperh->init.mode));
-
-    ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
-    LPTIM_ENABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, ENABLE);
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-        LPTIM_CNTSTART(hperh);
-    else
-        LPTIM_SNGSTART(hperh);
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-    return;
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -385,21 +496,20 @@ void ald_lptim_pulse_start_by_it(lptim_handle_t *hperh)
   */
 void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-
-    ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
-    LPTIM_DISABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_ARRMAT, DISABLE);
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    return;
+	return;
 }
 /**
   * @}
   */
 
-/** @defgroup LPTIM_Public_Functions_Group4 LPTIM output pwm functions
-  *  @brief    LPTime output pwm functions
+/** @defgroup LPTIM_Public_Functions_Group5 LPTIM output pwm functions
+  *  @brief   LPTIM output pwm functions
   *
   * @verbatim
   ==============================================================================
@@ -424,26 +534,25 @@ void ald_lptim_pulse_stop_by_it(lptim_handle_t *hperh)
   */
 ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_PRESC(hperh->init.psc));
-
-    __LOCK(hperh);
-    hperh->state = LPTIM_STATE_BUSY;
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_PRESC(hperh->init.psc));
 
-    WRITE_REG(hperh->perh->UPDATE, 1);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PWM << LP16T_CON0_WAVE_POSS);
-    MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
-    WRITE_REG(hperh->perh->ARR, hperh->init.arr);
-    WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
-    WRITE_REG(hperh->perh->UPDATE, 0);
+	__LOCK(hperh);
+	hperh->state = LPTIM_STATE_BUSY;
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
+	WRITE_REG(hperh->perh->UPDATE, 1);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_WAVE_MSK, LPTIM_WAVE_PWM << LP16T_CON0_WAVE_POSS);
+	MODIFY_REG(hperh->perh->CON0, LP16T_CON0_PRESC_MSK, (hperh->init.psc) << LP16T_CON0_PRESC_POSS);
+	WRITE_REG(hperh->perh->ARR, hperh->init.arr);
+	WRITE_REG(hperh->perh->CMP, hperh->init.cmp);
+	WRITE_REG(hperh->perh->UPDATE, 0);
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_ARRWBSY_MSK));
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CMPWBSY_MSK));
 
-    hperh->state = LPTIM_STATE_READY;
-    __UNLOCK(hperh);
-    return OK;
+	hperh->state = LPTIM_STATE_READY;
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -453,21 +562,19 @@ ald_status_t ald_lptim_pwm_init(lptim_handle_t *hperh)
   */
 void ald_lptim_pwm_start(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_MODE(hperh->init.mode));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
 
-    LPTIM_ENABLE(hperh);
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
 
-    if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-        LPTIM_CNTSTART(hperh);
-    else
-        LPTIM_SNGSTART(hperh);
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-    return;
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -477,13 +584,12 @@ void ald_lptim_pwm_start(lptim_handle_t *hperh)
   */
 void ald_lptim_pwm_stop(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-
-    LPTIM_DISABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    return;
+	return;
 }
 
 /**
@@ -493,22 +599,20 @@ void ald_lptim_pwm_stop(lptim_handle_t *hperh)
   */
 void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_MODE(hperh->init.mode));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_MODE(hperh->init.mode));
 
-    ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE);
-    LPTIM_ENABLE(hperh);
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, ENABLE);
+	LPTIM_ENABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
+		LPTIM_CNTSTART(hperh);
+	else
+		LPTIM_SNGSTART(hperh);
 
-    if (hperh->init.mode == LPTIM_MODE_CONTINUOUS)
-        LPTIM_CNTSTART(hperh);
-    else
-        LPTIM_SNGSTART(hperh);
-
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
-
-    return;
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	return;
 }
 
 /**
@@ -518,21 +622,20 @@ void ald_lptim_pwm_start_by_it(lptim_handle_t *hperh)
   */
 void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-
-    ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE);
-    LPTIM_DISABLE(hperh);
+	assert_param(IS_LPTIM(hperh->perh));
 
-    while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
+	ald_lptim_interrupt_config(hperh, LPTIM_IT_CMPMAT, DISABLE);
+	LPTIM_DISABLE(hperh);
+	while (READ_BIT(hperh->perh->SYNCSTAT, LP16T_SYNCSTAT_CON1WBSY_MSK));
 
-    return;
+	return;
 }
 /**
   * @}
   */
 
 
-/** @defgroup LPTIM_Public_Functions_Group5 Control functions
+/** @defgroup LPTIM_Public_Functions_Group6 Control functions
   * @brief LPTIM Control functions
   *
   * @{
@@ -544,39 +647,36 @@ void ald_lptim_pwm_stop_by_it(lptim_handle_t *hperh)
   */
 void ald_lptim_irq_handler(lptim_handle_t *hperh)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-
-    /* Output compare event */
-    if (((ald_lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) &&
-            ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET))
-    {
-        ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT);
-
-        if (hperh->cmp_cbk)
-            hperh->cmp_cbk(hperh);
-    }
-
-    /* Output update event */
-    if (((ald_lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) &&
-            ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET))
-    {
-        ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT);
-
-        if (hperh->update_cbk)
-            hperh->update_cbk(hperh);
-    }
-
-    /* Trigger event */
-    if (((ald_lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) &&
-            ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET))
-    {
-        ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG);
-
-        if (hperh->trig_cbk)
-            hperh->trig_cbk(hperh);
-    }
-
-    return;
+	assert_param(IS_LPTIM(hperh->perh));
+
+	/* Output compare event */
+	if (((ald_lptim_get_it_status(hperh, LPTIM_IT_CMPMAT)) != RESET) &&
+                           ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_CMPMAT)) != RESET)) {
+		ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_CMPMAT);
+
+		if (hperh->cmp_cbk)
+			hperh->cmp_cbk(hperh);
+	}
+
+	/* Output update event */
+	if (((ald_lptim_get_it_status(hperh, LPTIM_IT_ARRMAT)) != RESET) &&
+                           ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_ARRMAT)) != RESET)) {
+		ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_ARRMAT);
+
+		if (hperh->update_cbk)
+			hperh->update_cbk(hperh);
+	}
+
+	/* Trigger event */
+	if (((ald_lptim_get_it_status(hperh, LPTIM_IT_EXTTRIG)) != RESET) &&
+                           ((ald_lptim_get_flag_status(hperh, LPTIM_FLAG_EXTTRIG)) != RESET)) {
+		ald_lptim_clear_flag_status(hperh, LPTIM_FLAG_EXTTRIG);
+
+		if (hperh->trig_cbk)
+			hperh->trig_cbk(hperh);
+	}
+
+	return;
 }
 
 /**
@@ -592,16 +692,15 @@ void ald_lptim_irq_handler(lptim_handle_t *hperh)
   */
 void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_t state)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_IT(it));
-    assert_param(IS_FUNC_STATE(state));
-
-    if (state == ENABLE)
-        SET_BIT(hperh->perh->IER, (uint32_t)it);
-    else
-        CLEAR_BIT(hperh->perh->IER, (uint32_t)it);
-
-    return;
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_IT(it));
+	assert_param(IS_FUNC_STATE(state));
+
+	if (state == ENABLE)
+		SET_BIT(hperh->perh->IER, (uint32_t)it);
+	else
+		CLEAR_BIT(hperh->perh->IER, (uint32_t)it);
+	return;
 }
 
 /**
@@ -616,13 +715,13 @@ void ald_lptim_interrupt_config(lptim_handle_t *hperh, lptim_it_t it, type_func_
   */
 it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_IT(it));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_IT(it));
 
-    if (READ_BIT(hperh->perh->IER, it))
-        return SET;
+	if (READ_BIT(hperh->perh->IER, it))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /** @brief  Check whether the specified LPTIM flag is set or not.
@@ -636,13 +735,13 @@ it_status_t ald_lptim_get_it_status(lptim_handle_t *hperh, lptim_it_t it)
   */
 flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_FLAG(flag));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_FLAG(flag));
 
-    if (READ_BIT(hperh->perh->ISR, flag))
-        return SET;
+	if (READ_BIT(hperh->perh->ISR, flag))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /** @brief  Clear the specified LPTIM pending flags.
@@ -654,18 +753,18 @@ flag_status_t ald_lptim_get_flag_status(lptim_handle_t *hperh, lptim_flag_t flag
   */
 void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag)
 {
-    assert_param(IS_LPTIM(hperh->perh));
-    assert_param(IS_LPTIM_FLAG(flag));
+	assert_param(IS_LPTIM(hperh->perh));
+	assert_param(IS_LPTIM_FLAG(flag));
 
-    WRITE_REG(hperh->perh->IFC, (uint32_t)flag);
-    return;
+	WRITE_REG(hperh->perh->IFC, (uint32_t)flag);
+	return;
 }
 /**
   * @}
   */
 
-/** @defgroup LPTIM_Public_Functions_Group6 Peripheral State functions
- *  @brief   Peripheral State functions
+/** @defgroup LPTIM_Public_Functions_Group7 Peripheral State functions
+ *  @brief    Peripheral State functions
  *
  * @verbatim
   ==============================================================================
@@ -685,7 +784,7 @@ void ald_lptim_clear_flag_status(lptim_handle_t *hperh, lptim_flag_t flag)
   */
 lptim_state_t ald_lptim_get_state(lptim_handle_t *hperh)
 {
-    return hperh->state;
+	return hperh->state;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pis.c

@@ -44,99 +44,86 @@
   */
 ald_status_t ald_pis_create(pis_handle_t *hperh)
 {
-    pis_divide_t temp;
-    uint8_t clock_menu = 0;
-
-    if (hperh == NULL)
-        return ERROR;
-
-    assert_param(IS_PIS_SRC(hperh->init.producer_src));
-    assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
-    assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
-    assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
-    assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
-
-    __LOCK(hperh);
-    hperh->perh = PIS;
-
-    /* get location of consumer in channel and position of con0/con1
-     * accord to comsumer_trig information */
-    temp.HalfWord       = (hperh->init.consumer_trig);
-    hperh->consumer_ch  = (pis_ch_t)(temp.ch);
-    hperh->consumer_con = (pis_con_t)(temp.con);
-    hperh->consumer_pos = (1 << temp.shift);
-
-    /* union producer clock and consumer clock */
-    clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk);
-
-    if (hperh->perh->CH_CON[hperh->consumer_ch] != 0)
-    {
-        __UNLOCK(hperh);
-        return BUSY;
-    }
-
-    MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
-    MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
-
-    /* configure sync clock, judging by producer clock with consumer clock */
-    switch (clock_menu)
-    {
-        case 0x00:
-        case 0x11:
-        case 0x22:
-        case 0x33:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS);
-            break;
-
-        case 0x01:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS);
-            break;
-
-        case 0x02:
-        case 0x12:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS);
-            break;
-
-        case 0x21:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS);
-            break;
-
-        case 0x30:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS);
-            break;
-
-        case 0x31:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS);
-            break;
-
-        case 0x32:
-            MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS);
-
-        default:
-            break;
-    }
-
-    MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
-    MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
-    hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
-
-    /* enable consumer bit, switch pin of consumer */
-    switch (hperh->consumer_con)
-    {
-        case PIS_CON_0:
-            PIS->TAR_CON0 |= hperh->consumer_pos;
-            break;
-
-        case PIS_CON_1:
-            PIS->TAR_CON1 |= hperh->consumer_pos;
-            break;
-
-        default:
-            break;
-    }
-
-    __UNLOCK(hperh);
-    return OK;
+	uint8_t clock_menu = 0;
+
+	if (hperh == NULL)
+		return ERROR;
+
+	assert_param(IS_PIS_SRC(hperh->init.producer_src));
+	assert_param(IS_PIS_TRIG(hperh->init.consumer_trig));
+	assert_param(IS_PIS_CLOCK(hperh->init.producer_clk));
+	assert_param(IS_PIS_CLOCK(hperh->init.consumer_clk));
+	assert_param(IS_PIS_EDGE(hperh->init.producer_edge));
+
+	__LOCK(hperh);
+	hperh->perh = PIS;
+
+	/* get location of consumer in channel and position of con0/con1
+	 * accord to comsumer_trig information */
+	hperh->consumer_ch  = (pis_ch_t)(hperh->init.consumer_trig & 0x0F);
+	hperh->consumer_con = (pis_con_t)(((uint32_t)hperh->init.consumer_trig >> 4) & 0x0F);
+	hperh->consumer_pos = (1U << (uint32_t)(((uint32_t)hperh->init.consumer_trig >> 8) & 0xFF));
+
+	/* union producer clock and consumer clock */
+	clock_menu = (hperh->init.producer_clk << 4) | (hperh->init.consumer_clk);
+
+	if (hperh->perh->CH_CON[hperh->consumer_ch] != 0) {
+		__UNLOCK(hperh);
+		return BUSY;
+	}
+
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SRCS_MSK, ((hperh->init.producer_src) >> 4) << PIS_CH0_CON_SRCS_POSS);
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_MSIGS_MSK, ((hperh->init.producer_src) & 0xf) << PIS_CH0_CON_MSIGS_POSS);
+
+	/* configure sync clock, judging by producer clock with consumer clock */
+	switch (clock_menu) {
+	case 0x00:
+	case 0x11:
+	case 0x22:
+	case 0x33:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 0 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	case 0x01:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 5 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	case 0x02:
+	case 0x12:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 6 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	case 0x21:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 4 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	case 0x30:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 1 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	case 0x31:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 2 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	case 0x32:
+		MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_SYNCSEL_MSK, 3 << PIS_CH0_CON_SYNCSEL_POSS);
+		break;
+	default:
+		break;
+	}
+
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_PULCK_MSK, hperh->init.consumer_clk << PIS_CH0_CON_PULCK_POSS);
+	MODIFY_REG(hperh->perh->CH_CON[hperh->consumer_ch], PIS_CH0_CON_EDGS_MSK, hperh->init.producer_edge << PIS_CH0_CON_EDGS_POSS);
+	hperh->check_info = hperh->perh->CH_CON[hperh->consumer_ch];
+
+	/* enable consumer bit, switch pin of consumer */
+	switch (hperh->consumer_con) {
+	case PIS_CON_0:
+		PIS->TAR_CON0 |= hperh->consumer_pos;
+		break;
+	case PIS_CON_1:
+		PIS->TAR_CON1 |= hperh->consumer_pos;
+		break;
+	default:
+		break;
+	}
+
+	__UNLOCK(hperh);
+	return OK;
 }
 
 /**
@@ -148,34 +135,31 @@ ald_status_t ald_pis_create(pis_handle_t *hperh)
   */
 ald_status_t ald_pis_destroy(pis_handle_t *hperh)
 {
-    assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS(hperh->perh));
 
-    if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
-        return ERROR;
+	if (hperh->check_info != hperh->perh->CH_CON[hperh->consumer_ch])
+		return ERROR;
 
-    __LOCK(hperh);
+	__LOCK(hperh);
 
-    CLEAR_BIT(PIS->CH_OER, (1 << hperh->consumer_ch));
-    WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
+	CLEAR_BIT(PIS->CH_OER, (1U << (uint32_t)hperh->consumer_ch));
+	WRITE_REG(hperh->perh->CH_CON[hperh->consumer_ch], 0x0);
 
-    switch (hperh->consumer_con)
-    {
-        case PIS_CON_0:
-            PIS->TAR_CON0 &= ~(hperh->consumer_pos);
-            break;
+	switch (hperh->consumer_con) {
+	case PIS_CON_0:
+		PIS->TAR_CON0 &= ~(hperh->consumer_pos);
+		break;
+	case PIS_CON_1:
+		PIS->TAR_CON1 &= ~(hperh->consumer_pos);
+		break;
+	default:
+		break;
+	}
 
-        case PIS_CON_1:
-            PIS->TAR_CON1 &= ~(hperh->consumer_pos);
-            break;
+	hperh->state = PIS_STATE_RESET;
+	__UNLOCK(hperh);
 
-        default:
-            break;
-    }
-
-    hperh->state = PIS_STATE_RESET;
-    __UNLOCK(hperh);
-
-    return OK;
+	return OK;
 }
 /**
   * @}
@@ -200,13 +184,13 @@ ald_status_t ald_pis_destroy(pis_handle_t *hperh)
   */
 ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
 {
-    assert_param(IS_PIS(hperh->perh));
-    assert_param(IS_PIS_OUPUT_CH(ch));
-    __LOCK(hperh);
-    SET_BIT(PIS->CH_OER, (1 << ch));
-    __UNLOCK(hperh);
+	assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS_OUPUT_CH(ch));
+	__LOCK(hperh);
+	SET_BIT(PIS->CH_OER, (1 << ch));
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -223,13 +207,13 @@ ald_status_t ald_pis_output_start(pis_handle_t *hperh, pis_out_ch_t ch)
   */
 ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
 {
-    assert_param(IS_PIS(hperh->perh));
-    assert_param(IS_PIS_OUPUT_CH(ch));
-    __LOCK(hperh);
-    CLEAR_BIT(PIS->CH_OER, (1 << ch));
-    __UNLOCK(hperh);
+	assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS_OUPUT_CH(ch));
+	__LOCK(hperh);
+	CLEAR_BIT(PIS->CH_OER, (1 << ch));
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 /**
   * @}
@@ -248,8 +232,8 @@ ald_status_t ald_pis_output_stop(pis_handle_t *hperh, pis_out_ch_t ch)
   */
 pis_state_t ald_pis_get_state(pis_handle_t *hperh)
 {
-    assert_param(IS_PIS(hperh->perh));
-    return hperh->state;
+	assert_param(IS_PIS(hperh->perh));
+	return hperh->state;
 }
 
 /**
@@ -272,51 +256,50 @@ pis_state_t ald_pis_get_state(pis_handle_t *hperh)
   */
 ald_status_t ald_pis_modu_config(pis_handle_t *hperh, pis_modulate_config_t *config)
 {
-    assert_param(IS_PIS(hperh->perh));
-    assert_param(IS_PIS_MODU_TARGET(config->target));
-    assert_param(IS_PIS_MODU_LEVEL(config->level));
-    assert_param(IS_PIS_MODU_SRC(config->src));
-    assert_param(IS_PIS_MODU_CHANNEL(config->channel));
-    __LOCK(hperh);
-
-    switch (config->target)
-    {
-        case PIS_UART0_TX:
-            MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-            MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-            MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-            break;
-
-        case PIS_UART1_TX:
-            MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-            MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-            MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-            break;
-
-        case PIS_UART2_TX:
-            MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-            MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-            MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-            break;
-
-        case PIS_UART3_TX:
-            MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-            MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-            MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-            break;
-
-        case PIS_LPUART0_TX:
-            MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
-            MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
-            MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
-            break;
-
-        default:
-            break;
-    }
-
-    __UNLOCK(hperh);
-    return OK;
+	assert_param(IS_PIS(hperh->perh));
+	assert_param(IS_PIS_MODU_TARGET(config->target));
+	assert_param(IS_PIS_MODU_LEVEL(config->level));
+	assert_param(IS_PIS_MODU_SRC(config->src));
+	assert_param(IS_PIS_MODU_CHANNEL(config->channel));
+	__LOCK(hperh);
+
+	switch (config->target) {
+	case PIS_UART0_TX:
+		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_UART1_TX:
+		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART1_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_UART2_TX:
+		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART2_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_UART3_TX:
+		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->UART3_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
+		break;
+
+	case PIS_LPUART0_TX:
+		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMLVLS_MSK, config->level << PIS_TXMCR_TXMLVLS_POS);
+		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXMSS_MSK, config->src << PIS_TXMCR_TXMSS_POSS);
+		MODIFY_REG(hperh->perh->LPUART0_TXMCR, PIS_TXMCR_TXSIGS_MSK, config->channel << PIS_TXMCR_TXSIGS_POSS);
+		break;
+
+	default:
+		break;
+	}
+
+	__UNLOCK(hperh);
+	return OK;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_pmu.c

@@ -15,7 +15,6 @@
   */
 
 #include "ald_pmu.h"
-#include "ald_bkpc.h"
 
 
 /** @addtogroup ES32FXXX_ALD
@@ -39,11 +38,11 @@
   */
 void ald_lvd_irq_handler(void)
 {
-    SYSCFG_UNLOCK();
-    SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-    SYSCFG_LOCK();
+	SYSCFG_UNLOCK();
+	SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
+	SYSCFG_LOCK();
 
-    return;
+	return;
 }
 /**
   * @}
@@ -63,6 +62,7 @@ void ald_lvd_irq_handler(void)
     [..]  This section provides functions allowing to:
       (+) Enter stop1 mode.
       (+) Enter stop2 mode.
+      (+) Enter standby mode.
       (+) Get wakeup status.
       (+) Clear wakeup status.
 
@@ -76,17 +76,17 @@ void ald_lvd_irq_handler(void)
   */
 void ald_pmu_stop1_enter(void)
 {
-    SYSCFG_UNLOCK();
-    SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
-    MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS);
-    SYSCFG_LOCK();
+	SYSCFG_UNLOCK();
+	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
+	MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP1 << PMU_CR_LPM_POSS);
+	SYSCFG_LOCK();
 
-    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-    __WFI();
-    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
+	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 
-    return;
+	return;
 }
 
 /**
@@ -95,17 +95,40 @@ void ald_pmu_stop1_enter(void)
   */
 void ald_pmu_stop2_enter(void)
 {
-    SYSCFG_UNLOCK();
-    SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
-    MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS);
-    SYSCFG_LOCK();
+	SYSCFG_UNLOCK();
+	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
+	MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STOP2 << PMU_CR_LPM_POSS);
+	SYSCFG_LOCK();
 
-    SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
-    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-    __WFI();
-    SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
+	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
 
-    return;
+	return;
+}
+
+/**
+  * @brief  Enter standby mode
+  * @param  port: The port whick wake up the standby mode.
+  * @param  level: Wakeup level.
+  * @retval None
+  */
+void ald_pmu_standby_enter(bkpc_wakeup_port_t port, bkpc_wakeup_level_t level)
+{
+	ald_bkpc_standby_wakeup_config(port, level);
+
+	SYSCFG_UNLOCK();
+	SET_BIT(PMU->CR, PMU_CR_LPSTOP_MSK);
+	MODIFY_REG(PMU->CR, PMU_CR_LPM_MSK, PMU_LP_STANDBY << PMU_CR_LPM_POSS);
+	SYSCFG_LOCK();
+
+	SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
+	SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+	__WFI();
+	SysTick->CTRL |= SysTick_CTRL_ENABLE_Msk;
+
+	return;
 }
 
 /**
@@ -117,23 +140,21 @@ void ald_pmu_stop2_enter(void)
   */
 void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
 {
-    assert_param(IS_FUNC_STATE(state));
-    SYSCFG_UNLOCK();
-
-    if (state)
-    {
-        assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
-
-        MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS);
-        SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
-    }
-    else
-    {
-        CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
-    }
-
-    SYSCFG_LOCK();
-    return;
+	assert_param(IS_FUNC_STATE(state));
+	SYSCFG_UNLOCK();
+
+	if (state) {
+		assert_param(IS_PMU_LDO_LPMODE_OUTPUT(vol));
+
+		MODIFY_REG(PMU->CR, PMU_CR_LPVS_MSK, vol << PMU_CR_LPVS_POSS);
+		SET_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
+	}
+	else {
+		CLEAR_BIT(PMU->CR, PMU_CR_LPRUN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
 }
 
 /**
@@ -143,12 +164,12 @@ void ald_pmu_lprun_config(pmu_ldo_lpmode_output_t vol, type_func_t state)
   */
 flag_status_t ald_pmu_get_status(pmu_status_t sr)
 {
-    assert_param(IS_PMU_STATUS(sr));
+	assert_param(IS_PMU_STATUS(sr));
 
-    if (READ_BIT(PMU->SR, sr))
-        return SET;
+	if (READ_BIT(PMU->SR, sr))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -158,19 +179,17 @@ flag_status_t ald_pmu_get_status(pmu_status_t sr)
   */
 void ald_pmu_clear_status(pmu_status_t sr)
 {
-    assert_param(IS_PMU_STATUS(sr));
-    SYSCFG_UNLOCK();
+	assert_param(IS_PMU_STATUS(sr));
+	SYSCFG_UNLOCK();
 
-    if (sr == PMU_SR_WUF)
-        SET_BIT(PMU->CR, PMU_CR_CWUF_MSK);
-    else
-        SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK);
+	if (sr == PMU_SR_WUF)
+		SET_BIT(PMU->CR, PMU_CR_CWUF_MSK);
+	else
+		SET_BIT(PMU->CR, PMU_CR_CSTANDBYF_MSK);
 
-    SYSCFG_LOCK();
-    return;
+	SYSCFG_LOCK();
+	return;
 }
-
-
 /**
   * @}
   */
@@ -199,36 +218,32 @@ void ald_pmu_clear_status(pmu_status_t sr)
   */
 void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode, type_func_t state)
 {
-    assert_param(IS_FUNC_STATE(state));
-    SYSCFG_UNLOCK();
-
-    if (state)
-    {
-        assert_param(IS_PMU_LVD_VOL_SEL(sel));
-        assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
-
-        MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
-        MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
-        SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
-        SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-        SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
-        SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
-    }
-    else
-    {
-        SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
-        CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
-        CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
-    }
-
-    SYSCFG_LOCK();
-    return;
+	assert_param(IS_FUNC_STATE(state));
+	SYSCFG_UNLOCK();
+
+	if (state) {
+		assert_param(IS_PMU_LVD_VOL_SEL(sel));
+		assert_param(IS_PMU_LVD_TRIGGER_MODE(mode));
+
+		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVDS_MSK, sel << PMU_LVDCR_LVDS_POSS);
+		MODIFY_REG(PMU->LVDCR, PMU_LVDCR_LVIFS_MSK, mode << PMU_LVDCR_LVIFS_POSS);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDFLT_MSK);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
+	}
+	else {
+		SET_BIT(PMU->LVDCR, PMU_LVDCR_LVDCIF_MSK);
+		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDIE_MSK);
+		CLEAR_BIT(PMU->LVDCR, PMU_LVDCR_LVDEN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
 }
 /**
   * @}
   */
-
-
 /**
   * @}
   */
@@ -236,7 +251,6 @@ void ald_pmu_lvd_config(pmu_lvd_voltage_sel_t sel, pmu_lvd_trigger_mode_t mode,
 /**
   * @}
   */
-
 /**
   * @}
   */

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_rmu.c

@@ -40,41 +40,42 @@
   */
 void ald_rmu_bor_config(rmu_bor_filter_t flt, rmu_bor_vol_t vol, type_func_t state)
 {
-    assert_param(IS_FUNC_STATE(state));
-
-    SYSCFG_UNLOCK();
-
-    if (state)
-    {
-        assert_param(IS_RMU_BORFLT(flt));
-        assert_param(IS_RMU_BORVOL(vol));
-
-        MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
-        MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
-        SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
-    }
-    else
-    {
-        CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
-    }
-
-    SYSCFG_LOCK();
-    return;
+	assert_param(IS_FUNC_STATE(state));
+
+	SYSCFG_UNLOCK();
+
+	if (state) {
+		assert_param(IS_RMU_BORFLT(flt));
+		assert_param(IS_RMU_BORVOL(vol));
+
+		MODIFY_REG(RMU->CR, RMU_CR_BORFLT_MSK, flt << RMU_CR_BORFLT_POSS);
+		MODIFY_REG(RMU->CR, RMU_CR_BORVS_MSK, vol << RMU_CR_BORVS_POSS);
+		SET_BIT(RMU->CR, RMU_CR_BOREN_MSK);
+	}
+	else {
+		CLEAR_BIT(RMU->CR, RMU_CR_BOREN_MSK);
+	}
+
+	SYSCFG_LOCK();
+	return;
 }
 
 /**
   * @brief  Get specified reset status
   * @param  state: Speicifies the type of the reset,
-  * @retval The status: SET/RESET.
+  * @retval The status.
   */
-flag_status_t ald_rmu_get_reset_status(rmu_state_t state)
+uint32_t ald_rmu_get_reset_status(rmu_state_t state)
 {
-    assert_param(IS_RMU_STATE(state));
+	assert_param(IS_RMU_STATE(state));
+
+	if (state == RMU_RST_ALL)
+		return RMU->RSTSR;
 
-    if (READ_BIT(RMU->RSTSR, state))
-        return SET;
+	if (READ_BIT(RMU->RSTSR, state))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -84,13 +85,13 @@ flag_status_t ald_rmu_get_reset_status(rmu_state_t state)
   */
 void ald_rmu_clear_reset_status(rmu_state_t state)
 {
-    assert_param(IS_RMU_STATE_CLEAR(state));
+	assert_param(IS_RMU_STATE_CLEAR(state));
 
-    SYSCFG_UNLOCK();
-    WRITE_REG(RMU->CRSTSR, state);
-    SYSCFG_LOCK();
+	SYSCFG_UNLOCK();
+	WRITE_REG(RMU->CRSTSR, state);
+	SYSCFG_LOCK();
 
-    return;
+	return;
 }
 /**
   * @brief  Reset peripheral device
@@ -99,38 +100,37 @@ void ald_rmu_clear_reset_status(rmu_state_t state)
   */
 void ald_rmu_reset_periperal(rmu_peripheral_t perh)
 {
-    uint32_t idx, pos;
+	uint32_t idx, pos;
 
-    assert_param(IS_RMU_PERH(perh));
+	assert_param(IS_RMU_PERH(perh));
 
-    idx = (perh >> 27) & 0x7;
-    pos = perh & ~(0x7 << 27);
-    SYSCFG_UNLOCK();
+	idx = ((uint32_t)perh >> 27) & 0x7;
+	pos = perh & ~(0x7 << 27);
+	SYSCFG_UNLOCK();
 
-    switch (idx)
-    {
-        case 0:
-            WRITE_REG(RMU->AHB1RSTR, pos);
-            break;
+	switch (idx) {
+	case 0:
+		WRITE_REG(RMU->AHB1RSTR, pos);
+		break;
 
-        case 1:
-            WRITE_REG(RMU->AHB2RSTR, pos);
-            break;
+	case 1:
+		WRITE_REG(RMU->AHB2RSTR, pos);
+		break;
 
-        case 2:
-            WRITE_REG(RMU->APB1RSTR, pos);
-            break;
+	case 2:
+		WRITE_REG(RMU->APB1RSTR, pos);
+		break;
 
-        case 4:
-            WRITE_REG(RMU->APB2RSTR, pos);
-            break;
+	case 4:
+		WRITE_REG(RMU->APB2RSTR, pos);
+		break;
 
-        default:
-            break;
-    }
+	default:
+		break;
+	}
 
-    SYSCFG_LOCK();
-    return;
+	SYSCFG_LOCK();
+	return;
 }
 
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_smartcard.c

@@ -122,9 +122,9 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hsmartcard);
 static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh);
 static void smartcard_set_config(smartcard_handle_t *hperh);
 #ifdef ALD_DMA
-    static void smartcard_dma_send_cplt(void *arg);
-    static void smartcard_dma_recv_cplt(void *arg);
-    static void smartcard_dma_error(void *arg);
+static void smartcard_dma_send_cplt(void *arg);
+static void smartcard_dma_recv_cplt(void *arg);
+static void smartcard_dma_error(void *arg);
 #endif
 static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout);
 /**
@@ -204,33 +204,33 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t
   */
 ald_status_t ald_smartcard_init(smartcard_handle_t *hperh)
 {
-    assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
-    assert_param(IS_USART_STOPBITS(hperh->init.stop_bits));
-    assert_param(IS_USART_PARITY(hperh->init.parity));
-    assert_param(IS_USART(hperh->perh));
-    assert_param(IS_FUNC_STATE(hperh->init.nack));
-    assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler));
+	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
+	assert_param(IS_USART_STOPBITS(hperh->init.stop_bits));
+	assert_param(IS_USART_PARITY(hperh->init.parity));
+	assert_param(IS_USART(hperh->perh));
+	assert_param(IS_FUNC_STATE(hperh->init.nack));
+	assert_param(IS_SMARTCARD_PRESCALER(hperh->init.prescaler));
 
-    if (hperh->state == SMARTCARD_STATE_RESET)
-        hperh->lock = UNLOCK;
+	if (hperh->state == SMARTCARD_STATE_RESET)
+		hperh->lock = UNLOCK;
 
-    hperh->state = SMARTCARD_STATE_BUSY;
-    SMARTCARD_DISABLE(hperh);
+	hperh->state = SMARTCARD_STATE_BUSY;
+	SMARTCARD_DISABLE(hperh);
 
-    MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS);
-    MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS);
-    smartcard_set_config(hperh);
+	MODIFY_REG(hperh->perh->GP, USART_GP_PSC_MSK, hperh->init.prescaler << USART_GP_PSC_POSS);
+	MODIFY_REG(hperh->perh->GP, USART_GP_GTVAL_MSK, hperh->init.guard_time << USART_GP_GTVAL_POSS);
+	smartcard_set_config(hperh);
 
-    CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK);
-    CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK);
+	CLEAR_BIT(hperh->perh->CON2, USART_CON2_IREN_MSK);
+	CLEAR_BIT(hperh->perh->CON2, USART_CON2_HDPSEL_MSK);
 
-    SMARTCARD_ENABLE(hperh);
-    MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS);
-    SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK);
+	SMARTCARD_ENABLE(hperh);
+	MODIFY_REG(hperh->perh->CON2, USART_CON2_NACK_MSK, hperh->init.nack << USART_CON2_NACK_POS);
+	SET_BIT(hperh->perh->CON2, USART_CON2_SMARTEN_MSK);
 
-    hperh->err_code = SMARTCARD_ERROR_NONE;
-    hperh->state    = SMARTCARD_STATE_READY;
-    return OK;
+	hperh->err_code = SMARTCARD_ERROR_NONE;
+	hperh->state    = SMARTCARD_STATE_READY;
+	return OK;
 }
 
 /**
@@ -241,22 +241,22 @@ ald_status_t ald_smartcard_init(smartcard_handle_t *hperh)
   */
 ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh)
 {
-    assert_param(IS_USART(hperh->perh));
+	assert_param(IS_USART(hperh->perh));
 
-    hperh->state = SMARTCARD_STATE_BUSY;
-    SMARTCARD_DISABLE(hperh);
+	hperh->state = SMARTCARD_STATE_BUSY;
+	SMARTCARD_DISABLE(hperh);
 
-    WRITE_REG(hperh->perh->CON0, 0x0);
-    WRITE_REG(hperh->perh->CON1, 0x0);
-    WRITE_REG(hperh->perh->CON2, 0x0);
-    WRITE_REG(hperh->perh->BAUDCON, 0x0);
-    WRITE_REG(hperh->perh->GP, 0x0);
+	WRITE_REG(hperh->perh->CON0, 0x0);
+	WRITE_REG(hperh->perh->CON1, 0x0);
+	WRITE_REG(hperh->perh->CON2, 0x0);
+	WRITE_REG(hperh->perh->BAUDCON, 0x0);
+	WRITE_REG(hperh->perh->GP, 0x0);
 
-    hperh->err_code = SMARTCARD_ERROR_NONE;
-    hperh->state    = SMARTCARD_STATE_RESET;
-    __UNLOCK(hperh);
+	hperh->err_code = SMARTCARD_ERROR_NONE;
+	hperh->state    = SMARTCARD_STATE_RESET;
+	__UNLOCK(hperh);
 
-    return OK;
+	return OK;
 }
 /**
   * @}
@@ -322,42 +322,38 @@ ald_status_t ald_smartcard_reset(smartcard_handle_t *hperh)
   */
 ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
 {
-    if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
-        return BUSY;
-
-    if ((buf == NULL) || (size == 0))
-        return  ERROR;
-
-    __LOCK(hperh);
-    hperh->err_code = SMARTCARD_ERROR_NONE;
-    SET_BIT(hperh->state, USART_STATE_TX_MASK);
-
-    hperh->tx_size  = size;
-    hperh->tx_count = size;
-
-    while (hperh->tx_count-- > 0)
-    {
-        if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK)
-        {
-            hperh->state = SMARTCARD_STATE_READY;
-            __UNLOCK(hperh);
-            return TIMEOUT;
-        }
-
-        WRITE_REG(hperh->perh->DATA, *buf++);
-    }
-
-    if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK)
-    {
-        hperh->state = SMARTCARD_STATE_READY;
-        __UNLOCK(hperh);
-        return TIMEOUT;
-    }
-
-    CLEAR_BIT(hperh->state, USART_STATE_TX_MASK);
-    __UNLOCK(hperh);
-
-    return OK;
+	if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
+		return BUSY;
+	if ((buf == NULL) || (size == 0))
+		return  ERROR;
+
+	__LOCK(hperh);
+	hperh->err_code = SMARTCARD_ERROR_NONE;
+	SET_BIT(hperh->state, USART_STATE_TX_MASK);
+
+	hperh->tx_size  = size;
+	hperh->tx_count = size;
+
+	while (hperh->tx_count-- > 0) {
+		if (smartcard_wait_flag(hperh, USART_FLAG_TXE, SET, timeout) != OK) {
+			hperh->state = SMARTCARD_STATE_READY;
+			__UNLOCK(hperh);
+			return TIMEOUT;
+		}
+
+		WRITE_REG(hperh->perh->DATA, *buf++);
+	}
+
+	if (smartcard_wait_flag(hperh, USART_FLAG_TC, SET, timeout) != OK) {
+		hperh->state = SMARTCARD_STATE_READY;
+		__UNLOCK(hperh);
+		return TIMEOUT;
+	}
+
+	CLEAR_BIT(hperh->state, USART_STATE_TX_MASK);
+	__UNLOCK(hperh);
+
+	return OK;
 }
 
 /**
@@ -371,35 +367,32 @@ ald_status_t ald_smartcard_send(smartcard_handle_t *hperh, uint8_t *buf, uint16_
   */
 ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout)
 {
-    if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
-        return BUSY;
+	if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
+		return BUSY;
+	if ((buf == NULL) || (size == 0))
+		return  ERROR;
 
-    if ((buf == NULL) || (size == 0))
-        return  ERROR;
+	__LOCK(hperh);
+	hperh->err_code = SMARTCARD_ERROR_NONE;
+	SET_BIT(hperh->state, USART_STATE_RX_MASK);
 
-    __LOCK(hperh);
-    hperh->err_code = SMARTCARD_ERROR_NONE;
-    SET_BIT(hperh->state, USART_STATE_RX_MASK);
+	hperh->rx_size  = size;
+	hperh->rx_count = size;
 
-    hperh->rx_size  = size;
-    hperh->rx_count = size;
+	while (hperh->rx_count-- > 0) {
+		if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK) {
+			hperh->state = SMARTCARD_STATE_READY;
+			__UNLOCK(hperh);
+			return TIMEOUT;
+		}
 
-    while (hperh->rx_count-- > 0)
-    {
-        if (smartcard_wait_flag(hperh, USART_FLAG_RXNE, SET, timeout) != OK)
-        {
-            hperh->state = SMARTCARD_STATE_READY;
-            __UNLOCK(hperh);
-            return TIMEOUT;
-        }
+		*buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
+	}
 
-        *buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
-    }
+	__UNLOCK(hperh);
+	CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
 
-    __UNLOCK(hperh);
-    CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
-
-    return OK;
+	return OK;
 }
 
 /**
@@ -412,25 +405,24 @@ ald_status_t ald_smartcard_recv(smartcard_handle_t *hperh, uint8_t *buf, uint16_
   */
 ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size)
 {
-    if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
-        return BUSY;
-
-    if ((buf == NULL) || (size == 0))
-        return ERROR;
+	if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
+		return BUSY;
+	if ((buf == NULL) || (size == 0))
+		return ERROR;
 
-    __LOCK(hperh);
-    SET_BIT(hperh->state, USART_STATE_TX_MASK);
+	__LOCK(hperh);
+	SET_BIT(hperh->state, USART_STATE_TX_MASK);
 
-    hperh->tx_buf   = buf;
-    hperh->tx_size  = size;
-    hperh->tx_count = size;
-    hperh->err_code = SMARTCARD_ERROR_NONE;
+	hperh->tx_buf   = buf;
+	hperh->tx_size  = size;
+	hperh->tx_count = size;
+	hperh->err_code = SMARTCARD_ERROR_NONE;
 
-    __UNLOCK(hperh);
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE);
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE);
+	__UNLOCK(hperh);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, ENABLE);
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -443,26 +435,25 @@ ald_status_t ald_smartcard_send_by_it(smartcard_handle_t *hperh, uint8_t *buf, u
   */
 ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size)
 {
-    if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
-        return BUSY;
-
-    if ((buf == NULL) || (size == 0))
-        return ERROR;
+	if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
+		return BUSY;
+	if ((buf == NULL) || (size == 0))
+		return ERROR;
 
-    __LOCK(hperh);
-    SET_BIT(hperh->state, USART_STATE_RX_MASK);
+	__LOCK(hperh);
+	SET_BIT(hperh->state, USART_STATE_RX_MASK);
 
-    hperh->rx_buf   = buf;
-    hperh->rx_size  = size;
-    hperh->rx_count = size;
-    hperh->err_code = SMARTCARD_ERROR_NONE;
+	hperh->rx_buf   = buf;
+	hperh->rx_size  = size;
+	hperh->rx_count = size;
+	hperh->err_code = SMARTCARD_ERROR_NONE;
 
-    __UNLOCK(hperh);
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE);
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE);
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE);
+	__UNLOCK(hperh);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, ENABLE);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, ENABLE);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, ENABLE);
 
-    return OK;
+	return OK;
 }
 
 #ifdef ALD_DMA
@@ -477,44 +468,43 @@ ald_status_t ald_smartcard_recv_by_it(smartcard_handle_t *hperh, uint8_t *buf, u
   */
 ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
 {
-    if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
-        return BUSY;
-
-    if ((buf == NULL) || (size == 0))
-        return ERROR;
-
-    __LOCK(hperh);
-    SET_BIT(hperh->state, USART_STATE_TX_MASK);
-
-    hperh->tx_buf   = buf;
-    hperh->tx_size  = size;
-    hperh->tx_count = size;
-    hperh->err_code = SMARTCARD_ERROR_NONE;
-
-    if (hperh->hdmatx.perh == NULL)
-        hperh->hdmatx.perh = DMA0;
-
-    hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt;
-    hperh->hdmatx.cplt_arg = (void *)hperh;
-    hperh->hdmatx.err_cbk  = smartcard_dma_error;
-    hperh->hdmatx.err_arg  = (void *)hperh;
-
-    ald_dma_config_struct(&hperh->hdmatx.config);
-    hperh->hdmatx.config.src     = (void *)buf;
-    hperh->hdmatx.config.dst     = (void *)&hperh->perh->DATA;
-    hperh->hdmatx.config.size    = size;
-    hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
-    hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
-    hperh->hdmatx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-    hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY;
-    hperh->hdmatx.config.channel = channel;
-    ald_dma_config_basic(&hperh->hdmatx);
-
-    ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC);
-    __UNLOCK(hperh);
-    ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE);
-
-    return OK;
+	if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_RX))
+		return BUSY;
+	if ((buf == NULL) || (size == 0))
+		return ERROR;
+
+	__LOCK(hperh);
+	SET_BIT(hperh->state, USART_STATE_TX_MASK);
+
+	hperh->tx_buf   = buf;
+	hperh->tx_size  = size;
+	hperh->tx_count = size;
+	hperh->err_code = SMARTCARD_ERROR_NONE;
+
+	if (hperh->hdmatx.perh == NULL)
+		hperh->hdmatx.perh = DMA0;
+
+	hperh->hdmatx.cplt_cbk = smartcard_dma_send_cplt;
+	hperh->hdmatx.cplt_arg = (void *)hperh;
+	hperh->hdmatx.err_cbk  = smartcard_dma_error;
+	hperh->hdmatx.err_arg  = (void *)hperh;
+
+	ald_dma_config_struct(&hperh->hdmatx.config);
+	hperh->hdmatx.config.src     = (void *)buf;
+	hperh->hdmatx.config.dst     = (void *)&hperh->perh->DATA;
+	hperh->hdmatx.config.size    = size;
+	hperh->hdmatx.config.src_inc = DMA_DATA_INC_BYTE;
+	hperh->hdmatx.config.dst_inc = DMA_DATA_INC_NONE;
+	hperh->hdmatx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
+	hperh->hdmatx.config.msigsel = DMA_MSIGSEL_USART_TXEMPTY;
+	hperh->hdmatx.config.channel = channel;
+	ald_dma_config_basic(&hperh->hdmatx);
+
+	ald_usart_clear_flag_status((usart_handle_t *)hperh, USART_FLAG_TC);
+	__UNLOCK(hperh);
+	ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, ENABLE);
+
+	return OK;
 }
 
 /**
@@ -529,43 +519,42 @@ ald_status_t ald_smartcard_send_by_dma(smartcard_handle_t *hperh, uint8_t *buf,
   */
 ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel)
 {
-    if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
-        return BUSY;
-
-    if ((buf == NULL) || (size == 0))
-        return ERROR;
-
-    __LOCK(hperh);
-    SET_BIT(hperh->state, USART_STATE_RX_MASK);
-
-    hperh->rx_buf   = buf;
-    hperh->rx_size  = size;
-    hperh->rx_count = size;
-    hperh->err_code = SMARTCARD_ERROR_NONE;
-
-    if (hperh->hdmarx.perh == NULL)
-        hperh->hdmarx.perh = DMA0;
-
-    hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt;
-    hperh->hdmarx.cplt_arg = (void *)hperh;
-    hperh->hdmarx.err_cbk  = smartcard_dma_error;
-    hperh->hdmarx.err_arg  = (void *)hperh;
-
-    ald_dma_config_struct(&hperh->hdmarx.config);
-    hperh->hdmarx.config.src     = (void *)&hperh->perh->DATA;
-    hperh->hdmarx.config.dst     = (void *)buf;
-    hperh->hdmarx.config.size    = size;
-    hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
-    hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
-    hperh->hdmarx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
-    hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR;
-    hperh->hdmarx.config.channel = channel;
-    ald_dma_config_basic(&hperh->hdmarx);
-
-    __UNLOCK(hperh);
-    ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE);
-
-    return OK;
+	if ((hperh->state != SMARTCARD_STATE_READY) && (hperh->state != SMARTCARD_STATE_BUSY_TX))
+		return BUSY;
+	if ((buf == NULL) || (size == 0))
+		return ERROR;
+
+	__LOCK(hperh);
+	SET_BIT(hperh->state, USART_STATE_RX_MASK);
+
+	hperh->rx_buf   = buf;
+	hperh->rx_size  = size;
+	hperh->rx_count = size;
+	hperh->err_code = SMARTCARD_ERROR_NONE;
+
+	if (hperh->hdmarx.perh == NULL)
+		hperh->hdmarx.perh = DMA0;
+
+	hperh->hdmarx.cplt_cbk = smartcard_dma_recv_cplt;
+	hperh->hdmarx.cplt_arg = (void *)hperh;
+	hperh->hdmarx.err_cbk  = smartcard_dma_error;
+	hperh->hdmarx.err_arg  = (void *)hperh;
+
+	ald_dma_config_struct(&hperh->hdmarx.config);
+	hperh->hdmarx.config.src     = (void *)&hperh->perh->DATA;
+	hperh->hdmarx.config.dst     = (void *)buf;
+	hperh->hdmarx.config.size    = size;
+	hperh->hdmarx.config.src_inc = DMA_DATA_INC_NONE;
+	hperh->hdmarx.config.dst_inc = DMA_DATA_INC_BYTE;
+	hperh->hdmarx.config.msel    = hperh->perh == USART0 ? DMA_MSEL_USART0 : DMA_MSEL_USART1;
+	hperh->hdmarx.config.msigsel = DMA_MSIGSEL_USART_RNR;
+	hperh->hdmarx.config.channel = channel;
+	ald_dma_config_basic(&hperh->hdmarx);
+
+	__UNLOCK(hperh);
+	ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, ENABLE);
+
+	return OK;
 }
 #endif
 
@@ -577,65 +566,57 @@ ald_status_t ald_smartcard_recv_by_dma(smartcard_handle_t *hperh, uint8_t *buf,
   */
 void ald_smartcard_irq_handler(smartcard_handle_t *hperh)
 {
-    uint32_t flag;
-    uint32_t source;
-
-    /* Handle parity error */
-    flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE);
-    source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE);
-
-    if ((flag != RESET) && (source != RESET))
-        hperh->err_code |= SMARTCARD_ERROR_PE;
-
-    /* Handle frame error */
-    flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE);
-    source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR);
-
-    if ((flag != RESET) && (source != RESET))
-        hperh->err_code |= SMARTCARD_ERROR_FE;
-
-    /* Handle noise error */
-    flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE);
-
-    if ((flag != RESET) && (source != RESET))
-        hperh->err_code |= SMARTCARD_ERROR_NE;
-
-    /* Handle overrun error */
-    flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE);
-
-    if ((flag != RESET) && (source != RESET))
-        hperh->err_code |= SMARTCARD_ERROR_ORE;
-
-    /* Handle receive */
-    flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE);
-    source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE);
-
-    if ((flag != RESET) && (source != RESET))
-        __smartcard_recv_by_it(hperh);
-
-    /* Handle transmit */
-    flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE);
-    source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE);
-
-    if ((flag != RESET) && (source != RESET))
-        __smartcard_send_by_it(hperh);
-
-    /* Handle transmit complete */
-    flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC);
-    source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC);
-
-    if ((flag != RESET) && (source != RESET))
-        __smartcard_end_send_by_it(hperh);
-
-    /* Handle error */
-    if (hperh->err_code != SMARTCARD_ERROR_NONE)
-    {
-        USART_CLEAR_PEFLAG(hperh);
-        hperh->state = SMARTCARD_STATE_READY;
-
-        if (hperh->error_cbk)
-            hperh->error_cbk(hperh);
-    }
+	uint32_t flag;
+	uint32_t source;
+
+	/* Handle parity error */
+	flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_PE);
+	source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_PE);
+	if ((flag != RESET) && (source != RESET))
+		hperh->err_code |= SMARTCARD_ERROR_PE;
+
+	/* Handle frame error */
+	flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_FE);
+	source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_ERR);
+	if ((flag != RESET) && (source != RESET))
+		hperh->err_code |= SMARTCARD_ERROR_FE;
+
+	/* Handle noise error */
+	flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_NE);
+	if ((flag != RESET) && (source != RESET))
+		hperh->err_code |= SMARTCARD_ERROR_NE;
+
+	/* Handle overrun error */
+	flag = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_ORE);
+	if ((flag != RESET) && (source != RESET))
+		hperh->err_code |= SMARTCARD_ERROR_ORE;
+
+	/* Handle receive */
+	flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_RXNE);
+	source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_RXNE);
+	if ((flag != RESET) && (source != RESET))
+		__smartcard_recv_by_it(hperh);
+
+	/* Handle transmit */
+	flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TXE);
+	source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TXE);
+	if ((flag != RESET) && (source != RESET))
+		__smartcard_send_by_it(hperh);
+
+	/* Handle transmit complete */
+	flag   = ald_usart_get_flag_status((usart_handle_t *)hperh, USART_FLAG_TC);
+	source = ald_usart_get_it_status((usart_handle_t *)hperh, USART_IT_TC);
+	if ((flag != RESET) && (source != RESET))
+		__smartcard_end_send_by_it(hperh);
+
+	/* Handle error */
+	if (hperh->err_code != SMARTCARD_ERROR_NONE) {
+		USART_CLEAR_PEFLAG(hperh);
+		hperh->state = SMARTCARD_STATE_READY;
+
+		if (hperh->error_cbk)
+			hperh->error_cbk(hperh);
+	}
 }
 /**
   * @}
@@ -668,7 +649,7 @@ void ald_smartcard_irq_handler(smartcard_handle_t *hperh)
   */
 smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh)
 {
-    return hperh->state;
+	return hperh->state;
 }
 
 /**
@@ -679,7 +660,7 @@ smartcard_state_t ald_smartcard_get_state(smartcard_handle_t *hperh)
   */
 uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh)
 {
-    return hperh->err_code;
+	return hperh->err_code;
 }
 
 /**
@@ -704,13 +685,13 @@ uint32_t ald_smartcard_get_error(smartcard_handle_t *hperh)
   */
 static void smartcard_dma_send_cplt(void *arg)
 {
-    smartcard_handle_t *hperh = (smartcard_handle_t *)arg;
+	smartcard_handle_t* hperh = ( smartcard_handle_t *)arg;
 
-    hperh->tx_count = 0;
-    ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE);
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE);
+	hperh->tx_count = 0;
+	ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE);
 
-    return;
+	return;
 }
 
 /**
@@ -721,16 +702,16 @@ static void smartcard_dma_send_cplt(void *arg)
   */
 static void smartcard_dma_recv_cplt(void *arg)
 {
-    smartcard_handle_t *hperh = (smartcard_handle_t *)arg;
+	smartcard_handle_t* hperh = ( smartcard_handle_t* )arg;
 
-    hperh->rx_count = 0;
-    ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE);
-    CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
+	hperh->rx_count = 0;
+	ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE);
+	CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
 
-    if (hperh->rx_cplt_cbk)
-        hperh->rx_cplt_cbk(hperh);
+	if (hperh->rx_cplt_cbk)
+		hperh->rx_cplt_cbk(hperh);
 
-    return;
+	return;
 }
 
 /**
@@ -741,20 +722,20 @@ static void smartcard_dma_recv_cplt(void *arg)
   */
 static void smartcard_dma_error(void *arg)
 {
-    smartcard_handle_t *hperh = (smartcard_handle_t *)arg;
+	smartcard_handle_t* hperh = ( smartcard_handle_t* )arg;
 
-    hperh->rx_count = 0;
-    hperh->tx_count = 0;
-    hperh->err_code = SMARTCARD_ERROR_DMA;
-    hperh->state    = SMARTCARD_STATE_READY;
+	hperh->rx_count = 0;
+	hperh->tx_count = 0;
+	hperh->err_code = SMARTCARD_ERROR_DMA;
+	hperh->state    = SMARTCARD_STATE_READY;
 
-    ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE);
-    ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE);
+	ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_TX, DISABLE);
+	ald_usart_dma_req_config((usart_handle_t *)hperh, USART_DMA_REQ_RX, DISABLE);
 
-    if (hperh->error_cbk)
-        hperh->error_cbk(hperh);
+	if (hperh->error_cbk)
+		hperh->error_cbk(hperh);
 
-    return;
+	return;
 }
 #endif
 
@@ -769,27 +750,25 @@ static void smartcard_dma_error(void *arg)
   */
 static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t flag, flag_status_t status, uint32_t timeout)
 {
-    uint32_t tick;
+	uint32_t tick;
 
-    if (timeout == 0)
-        return OK;
+	if (timeout == 0)
+		return OK;
 
-    tick = ald_get_tick();
+	tick = ald_get_tick();
 
-    while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status)
-    {
-        if (((ald_get_tick()) - tick) > timeout)
-        {
-            ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE);
-            ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE);
-            ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE);
-            ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
+	while ((ald_usart_get_flag_status((usart_handle_t *)hperh, flag)) != status) {
+		if (((ald_get_tick()) - tick) > timeout) {
+			ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE);
+			ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE);
+			ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE);
+			ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
 
-            return TIMEOUT;
-        }
-    }
+			return TIMEOUT;
+		}
+	}
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -802,18 +781,17 @@ static ald_status_t smartcard_wait_flag(smartcard_handle_t *hperh, usart_flag_t
   */
 static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh)
 {
-    if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX))
-        return BUSY;
+	if ((hperh->state != SMARTCARD_STATE_BUSY_TX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX))
+		return BUSY;
 
-    WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
+	WRITE_REG(hperh->perh->DATA, *hperh->tx_buf++);
 
-    if (--hperh->tx_count == 0)
-    {
-        ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE);
-        ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE);
-    }
+	if (--hperh->tx_count == 0) {
+		ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TXE, DISABLE);
+		ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, ENABLE);
+	}
 
-    return OK;
+	return OK;
 }
 
 
@@ -825,16 +803,16 @@ static ald_status_t __smartcard_send_by_it(smartcard_handle_t *hperh)
   */
 static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh)
 {
-    ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE);
-    CLEAR_BIT(hperh->state, USART_STATE_TX_MASK);
+	ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_TC, DISABLE);
+	CLEAR_BIT(hperh->state, USART_STATE_TX_MASK);
 
-    if (hperh->state == SMARTCARD_STATE_READY)
-        ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
+	if (hperh->state == SMARTCARD_STATE_READY)
+		ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
 
-    if (hperh->tx_cplt_cbk)
-        hperh->tx_cplt_cbk(hperh);
+	if (hperh->tx_cplt_cbk)
+		hperh->tx_cplt_cbk(hperh);
 
-    return OK;
+	return OK;
 }
 
 
@@ -846,23 +824,22 @@ static ald_status_t __smartcard_end_send_by_it(smartcard_handle_t *hperh)
   */
 static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh)
 {
-    if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX))
-        return BUSY;
+	if ((hperh->state != SMARTCARD_STATE_BUSY_RX) && (hperh->state != SMARTCARD_STATE_BUSY_TX_RX))
+		return BUSY;
 
-    *hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
+	*hperh->rx_buf++ = (uint8_t)(hperh->perh->DATA & 0xFF);
 
-    if (--hperh->rx_count == 0)
-    {
-        ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE);
-        ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE);
-        ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
-        CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
+	if (--hperh->rx_count == 0) {
+		ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_RXNE, DISABLE);
+		ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_PE, DISABLE);
+		ald_usart_interrupt_config((usart_handle_t *)hperh, USART_IT_ERR, DISABLE);
+		CLEAR_BIT(hperh->state, USART_STATE_RX_MASK);
 
-        if (hperh->rx_cplt_cbk)
-            hperh->rx_cplt_cbk(hperh);
-    }
+		if (hperh->rx_cplt_cbk)
+			hperh->rx_cplt_cbk(hperh);
+	}
 
-    return OK;
+	return OK;
 }
 
 /**
@@ -873,68 +850,65 @@ static ald_status_t __smartcard_recv_by_it(smartcard_handle_t *hperh)
   */
 static void smartcard_set_config(smartcard_handle_t *hperh)
 {
-    uint32_t tmp;
-    uint32_t integer;
-    uint32_t fractional;
-
-    /* Check the parameters */
-    assert_param(IS_USART(hperh->perh));
-    assert_param(IS_USART_BAUDRATE(hperh->init.baud));
-    assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
-    assert_param(IS_USART_STOPBITS(hperh->init.stop_bits));
-    assert_param(IS_USART_PARITY(hperh->init.parity));
-    assert_param(IS_USART_MODE(hperh->init.mode));
-
-    MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS);
-    tmp = READ_REG(hperh->perh->CON0);
-    MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS);
-
-    if (hperh->init.parity == USART_PARITY_NONE)
-        CLEAR_BIT(tmp, USART_CON0_PEN_MSK);
-    else
-        SET_BIT(tmp, USART_CON0_PEN_MSK);
-
-    if (hperh->init.parity == USART_PARITY_ODD)
-        SET_BIT(tmp, USART_CON0_PSEL_MSK);
-    else
-        CLEAR_BIT(tmp, USART_CON0_PSEL_MSK);
-
-    WRITE_REG(hperh->perh->CON0, tmp);
-    CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK);
-    CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK);
-    MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS);
-    MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS);
-    tmp = READ_REG(hperh->perh->CON1);
-    SET_BIT(tmp, USART_CON1_SCKEN_MSK);
-    MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS);
-    MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS);
-    MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS);
-
-    /* Determine the integer part */
-    if (READ_BIT(hperh->perh->CON0, (1 << 15)))
-    {
-        /* Integer part computing in case Oversampling mode is 8 Samples */
-        integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud)));
-    }
-    else
-    {
-        /* Integer part computing in case Oversampling mode is 16 Samples */
-        integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud)));
-    }
-
-    tmp = (integer / 100) << 4;
-
-    /* Determine the fractional part */
-    fractional = integer - (100 * (tmp >> 4));
-
-    /* Implement the fractional part in the register */
-    if (READ_BIT(hperh->perh->CON0, (1 << 15)))
-        tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07);
-    else
-        tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F);
-
-    WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp);
-    return;
+	uint32_t tmp;
+	uint32_t integer;
+	uint32_t fractional;
+
+	/* Check the parameters */
+	assert_param(IS_USART(hperh->perh));
+	assert_param(IS_USART_BAUDRATE(hperh->init.baud));
+	assert_param(IS_USART_WORD_LENGTH(hperh->init.word_length));
+	assert_param(IS_USART_STOPBITS(hperh->init.stop_bits));
+	assert_param(IS_USART_PARITY(hperh->init.parity));
+	assert_param(IS_USART_MODE(hperh->init.mode));
+
+	MODIFY_REG(hperh->perh->CON1, USART_CON1_STPLEN_MSK, hperh->init.stop_bits << USART_CON1_STPLEN_POSS);
+	tmp = READ_REG(hperh->perh->CON0);
+	MODIFY_REG(tmp, USART_CON0_DLEN_MSK, hperh->init.word_length << USART_CON0_DLEN_POS);
+
+	if (hperh->init.parity == USART_PARITY_NONE)
+		CLEAR_BIT(tmp, USART_CON0_PEN_MSK);
+	else
+		SET_BIT(tmp, USART_CON0_PEN_MSK);
+
+	if (hperh->init.parity == USART_PARITY_ODD)
+		SET_BIT(tmp, USART_CON0_PSEL_MSK);
+	else
+		CLEAR_BIT(tmp, USART_CON0_PSEL_MSK);
+
+	WRITE_REG(hperh->perh->CON0, tmp);
+	CLEAR_BIT(hperh->perh->CON2, USART_CON2_RTSEN_MSK);
+	CLEAR_BIT(hperh->perh->CON2, USART_CON2_CTSEN_MSK);
+	MODIFY_REG(hperh->perh->CON0, USART_CON0_RXEN_MSK, (hperh->init.mode & 0x1) << USART_CON0_RXEN_POS);
+	MODIFY_REG(hperh->perh->CON0, USART_CON0_TXEN_MSK, ((hperh->init.mode >> 1) & 0x1) << USART_CON0_TXEN_POS);
+	tmp = READ_REG(hperh->perh->CON1);
+	SET_BIT(tmp, USART_CON1_SCKEN_MSK);
+	MODIFY_REG(tmp, USART_CON1_SCKPOL_MSK, hperh->init.polarity << USART_CON1_SCKPOL_POS);
+	MODIFY_REG(tmp, USART_CON1_SCKPHA_MSK, hperh->init.phase << USART_CON1_SCKPHA_POS);
+	MODIFY_REG(tmp, USART_CON1_LBCP_MSK, hperh->init.last_bit << USART_CON1_LBCP_POS);
+
+	/* Determine the integer part */
+	if (READ_BIT(hperh->perh->CON0, (1 << 15))) {
+		/* Integer part computing in case Oversampling mode is 8 Samples */
+		integer = ((25 * ald_cmu_get_pclk1_clock()) / (2 * (hperh->init.baud)));
+	}
+	else {
+		/* Integer part computing in case Oversampling mode is 16 Samples */
+		integer = ((25 * ald_cmu_get_pclk1_clock()) / (4 * (hperh->init.baud)));
+	}
+	tmp = (integer / 100) << 4;
+
+	/* Determine the fractional part */
+	fractional = integer - (100 * (tmp >> 4));
+
+	/* Implement the fractional part in the register */
+	if (READ_BIT(hperh->perh->CON0, (1 << 15)))
+    		tmp |= ((((fractional * 8) + 50) / 100)) & ((uint8_t)0x07);
+	else
+		tmp |= ((((fractional * 16) + 50) / 100)) & ((uint8_t)0x0F);
+
+	WRITE_REG(hperh->perh->BAUDCON, (uint16_t)tmp);
+	return;
 }
 
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_trng.c

@@ -33,7 +33,7 @@
 void trng_reset(trng_handle_t *hperh);
 /**
   * @}
-  */
+  */ 
 
 /** @defgroup TRNG_Public_Functions TRNG Public Functions
   * @{
@@ -68,40 +68,42 @@ void trng_reset(trng_handle_t *hperh);
   */
 ald_status_t ald_trng_init(trng_handle_t *hperh)
 {
-    uint32_t tmp = 0;
+	uint32_t tmp = 0;
 
-    if (hperh == NULL)
-        return ERROR;
+	if (hperh == NULL)
+		return ERROR;
 
-    assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width));
-    assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type));
-    assert_param(IS_TRNG_ADJC(hperh->init.adjc));
+	assert_param(IS_TRNG_DATA_WIDTH(hperh->init.data_width));
+	assert_param(IS_TRNG_SEED_TYPE(hperh->init.seed_type));
+	assert_param(IS_TRNG_ADJC(hperh->init.adjc));
+	assert_param(IS_FUNC_STATE(hperh->init.posten));
+	assert_param(IS_TRNG_T_START(hperh->init.t_start));
 
-    __LOCK(hperh);
-    trng_reset(hperh);
+	__LOCK(hperh);
+	trng_reset(hperh);
 
-    if (hperh->state == TRNG_STATE_RESET)
-        __UNLOCK(hperh);
+	if (hperh->state == TRNG_STATE_RESET)
+		__UNLOCK(hperh);
 
-    tmp = TRNG->CR;
+	tmp = TRNG->CR;
 
-    if (hperh->init.adjc == 0)
-        tmp = (0 << TRNG_CR_ADJM_POS);
-    else
-        tmp = (1 << TRNG_CR_ADJM_POS);
+	if (hperh->init.adjc == 0)
+		tmp = (0 << TRNG_CR_ADJM_POS);
+	else
+		tmp = (1 << TRNG_CR_ADJM_POS);
 
-    tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) |
-            (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) |
-            (hperh->init.posten << TRNG_CR_POSTEN_MSK));
+	tmp |= ((1 << TRNG_CR_TRNGSEL_POS) | (hperh->init.data_width << TRNG_CR_DSEL_POSS) |
+	       (hperh->init.seed_type << TRNG_CR_SDSEL_POSS) | (hperh->init.adjc << TRNG_CR_ADJC_POSS) |
+	       (hperh->init.posten << TRNG_CR_POSTEN_MSK));
 
-    TRNG->CR = tmp;
+	TRNG->CR = tmp;
 
-    WRITE_REG(TRNG->SEED, hperh->init.seed);
-    MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS);
+	WRITE_REG(TRNG->SEED, hperh->init.seed);
+	MODIFY_REG(TRNG->CFGR, TRNG_CFGR_TSTART_MSK, (hperh->init.t_start) << TRNG_CFGR_TSTART_POSS);
 
-    hperh->state = TRNG_STATE_READY;
-    __UNLOCK(hperh);
-    return OK;
+	hperh->state = TRNG_STATE_READY;
+	__UNLOCK(hperh);
+	return OK;
 }
 /**
   * @}
@@ -134,9 +136,9 @@ ald_status_t ald_trng_init(trng_handle_t *hperh)
   */
 uint32_t ald_trng_get_result(trng_handle_t *hperh)
 {
-    hperh->state = TRNG_STATE_READY;
-    hperh->data = hperh->perh->DR;
-    return (uint32_t)hperh->perh->DR;
+	hperh->state = TRNG_STATE_READY;
+	hperh->data = hperh->perh->DR;
+	return (uint32_t)hperh->perh->DR;
 }
 
 /**
@@ -153,15 +155,15 @@ uint32_t ald_trng_get_result(trng_handle_t *hperh)
   */
 void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t state)
 {
-    assert_param(IS_TRNG_IT(it));
-    assert_param(IS_FUNC_STATE(state));
+	assert_param(IS_TRNG_IT(it));
+	assert_param(IS_FUNC_STATE(state));
 
-    if (state)
-        SET_BIT(hperh->perh->IER, it);
-    else
-        CLEAR_BIT(hperh->perh->IER, it);
+	if (state)
+		SET_BIT(hperh->perh->IER, it);
+	else
+		CLEAR_BIT(hperh->perh->IER, it);
 
-    return;
+	return;
 }
 
 /**
@@ -176,12 +178,12 @@ void ald_trng_interrupt_config(trng_handle_t *hperh, trng_it_t it, type_func_t s
   */
 flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status)
 {
-    assert_param(IS_TRNG_STATUS(status));
+	assert_param(IS_TRNG_STATUS(status));
 
-    if (READ_BIT(hperh->perh->SR, status))
-        return SET;
+	if (READ_BIT(hperh->perh->SR, status))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -196,12 +198,12 @@ flag_status_t ald_trng_get_status(trng_handle_t *hperh, trng_status_t status)
   */
 it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it)
 {
-    assert_param(IS_TRNG_IT(it));
+	assert_param(IS_TRNG_IT(it));
 
-    if (READ_BIT(hperh->perh->IER, it))
-        return SET;
+	if (READ_BIT(hperh->perh->IER, it))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -216,12 +218,12 @@ it_status_t ald_trng_get_it_status(trng_handle_t *hperh, trng_it_t it)
   */
 flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
 {
-    assert_param(IS_TRNG_FLAG(flag));
+	assert_param(IS_TRNG_FLAG(flag));
 
-    if (READ_BIT(hperh->perh->IFR, flag))
-        return SET;
+	if (READ_BIT(hperh->perh->IFR, flag))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -234,10 +236,10 @@ flag_status_t ald_trng_get_flag_status(trng_handle_t *hperh, trng_flag_t flag)
   */
 void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
 {
-    assert_param(IS_TRNG_FLAG(flag));
-    WRITE_REG(hperh->perh->IFCR, flag);
+	assert_param(IS_TRNG_FLAG(flag));
+	WRITE_REG(hperh->perh->IFCR, flag);
 
-    return;
+	return;
 }
 
 /**
@@ -248,15 +250,15 @@ void ald_trng_clear_flag_status(trng_handle_t *hperh, trng_flag_t flag)
   */
 void trng_reset(trng_handle_t *hperh)
 {
-    TRNG->CR = 0;
-    TRNG->SEED = 0;
-    TRNG->CFGR = 0x1FF0707;
-    TRNG->IER = 0;
-    TRNG->IFCR = 0xFFFFFFFF;
-
-    hperh->state = TRNG_STATE_READY;
-    __UNLOCK(hperh);
-    return;
+	TRNG->CR = 0;
+	TRNG->SEED = 0;
+	TRNG->CFGR = 0x1FF0707;
+	TRNG->IER = 0;
+	TRNG->IFCR = 0xFFFFFFFF;
+
+	hperh->state = TRNG_STATE_READY;
+	__UNLOCK(hperh);
+	return;
 }
 
 /**
@@ -267,35 +269,28 @@ void trng_reset(trng_handle_t *hperh)
   */
 void ald_trng_irq_handler(trng_handle_t *hperh)
 {
-    if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET)
-    {
-        hperh->state = TRNG_STATE_ERROR;
-        ald_trng_clear_flag_status(hperh, TRNG_IF_SERR);
-
-        if (hperh->err_cplt_cbk)
-            hperh->err_cplt_cbk(hperh);
-
-        return;
-    }
-
-    if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET)
-    {
-        hperh->data = hperh->perh->DR;
-        hperh->state = TRNG_STATE_READY;
-        ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD);
-
-        if (hperh->trng_cplt_cbk)
-            hperh->trng_cplt_cbk(hperh);
-    }
-
-    if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET)
-    {
-        hperh->state = TRNG_STATE_BUSY;
-        ald_trng_clear_flag_status(hperh, TRNG_IF_START);
-
-        if (hperh->init_cplt_cbk)
-            hperh->init_cplt_cbk(hperh);
-    }
+	if (ald_trng_get_flag_status(hperh, TRNG_IF_SERR) == SET) {
+		hperh->state = TRNG_STATE_ERROR;
+		ald_trng_clear_flag_status(hperh, TRNG_IF_SERR);
+		if (hperh->err_cplt_cbk)
+			hperh->err_cplt_cbk(hperh);
+		return;
+	}
+
+	if (ald_trng_get_flag_status(hperh, TRNG_IF_DAVLD) == SET) {
+		hperh->data = hperh->perh->DR;
+		hperh->state = TRNG_STATE_READY;
+		ald_trng_clear_flag_status(hperh, TRNG_IF_DAVLD);
+		if (hperh->trng_cplt_cbk)
+			hperh->trng_cplt_cbk(hperh);
+	}
+
+	if (ald_trng_get_flag_status(hperh, TRNG_IF_START) == SET) {
+		hperh->state = TRNG_STATE_BUSY;
+		ald_trng_clear_flag_status(hperh, TRNG_IF_START);
+		if (hperh->init_cplt_cbk)
+			hperh->init_cplt_cbk(hperh);
+	}
 }
 
 /**

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_tsense.c

@@ -61,26 +61,39 @@ tsense_cbk __tsense_cbk;
 
 /**
   * @brief  Initializes the TSENSE according to the specified
-  *         parameters in the tsense_init_t.
-  * @param  init: Pointer to a tsense_init_t structure that contains
-  *         the configuration information.
   * @retval None
   */
-void ald_tsense_init(tsense_init_t *init)
+void ald_tsense_init(void)
 {
-    assert_param(IS_TSENSE_UPDATE_CYCLE(init->cycle));
-    assert_param(IS_TSENSE_OUTPUT_MODE(init->mode));
-
-    TSENSE_UNLOCK();
-    TSENSE->CR = 0;
-
-    MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, init->cycle << TSENSE_CR_TSU_POSS);
-    MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, init->mode << TSENSE_CR_TOM_POSS);
-    MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, init->ctn << TSENSE_CR_CTN_POS);
-    MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, init->psc << TSENSE_PSR_PRS_POSS);
-    TSENSE_LOCK();
-
-    return;
+	uint16_t tempt, temptinv;
+	uint32_t tscic, tscicinv;
+
+	TSENSE_UNLOCK();
+	TSENSE->CR = 0;
+
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_CTN_MSK, 0x1 << TSENSE_CR_CTN_POS);
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_TSU_MSK, 0x4 << TSENSE_CR_TSU_POSS);
+	MODIFY_REG(TSENSE->CR, TSENSE_CR_TOM_MSK, 0x3 << TSENSE_CR_TOM_POSS);
+	MODIFY_REG(TSENSE->PSR, TSENSE_PSR_PRS_MSK, 0x1 << TSENSE_PSR_PRS_POSS);
+
+	TSENSE->HTGR = 0x88F18;
+	TSENSE->LTGR = 0x85C39;
+	tempt        = *(volatile uint16_t *)0x40348;
+	temptinv     = *(volatile uint16_t *)0x4034A;
+	tscic        = *(volatile uint32_t *)0x40350;
+	tscicinv     = *(volatile uint32_t *)0x40358;
+
+	if ((tempt == (uint16_t)(~temptinv)) && (tscic == (~tscicinv))) {
+		TSENSE->TBDR    = tempt;
+		TSENSE->TCALBDR = (tscic & 0x1FFFFFF) >> 6;
+	}
+	else {
+		TSENSE->TBDR    = 0x1E00;
+		TSENSE->TCALBDR = 0x1FE70;
+	}
+
+	TSENSE_LOCK();
+	return;
 }
 
 /**
@@ -90,26 +103,23 @@ void ald_tsense_init(tsense_init_t *init)
   */
 void ald_tsense_source_select(tsense_source_sel_t sel)
 {
-    assert_param(IS_TSENSE_SOURCE_SEL(sel));
-
-    BKPC_UNLOCK();
-    MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS);
-
-    if (sel == TSENSE_SOURCE_LOSC)
-    {
-        SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
-    }
-    else if (sel == TSENSE_SOURCE_LRC)
-    {
-        SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
-    }
-    else
-    {
-        ; /* do nothing */
-    }
-
-    BKPC_LOCK();
-    return;
+	assert_param(IS_TSENSE_SOURCE_SEL(sel));
+
+	BKPC_UNLOCK();
+	MODIFY_REG(BKPC->PCCR, BKPC_PCCR_TSENSECS_MSK, sel << BKPC_PCCR_TSENSECS_POSS);
+
+	if (sel == TSENSE_SOURCE_LOSC) {
+		SET_BIT(BKPC->CR, BKPC_CR_LOSCEN_MSK);
+	}
+	else if (sel == TSENSE_SOURCE_LRC) {
+		SET_BIT(BKPC->CR, BKPC_CR_LRCEN_MSK);
+	}
+	else {
+		; /* do nothing */
+	}
+
+	BKPC_LOCK();
+	return;
 }
 /**
   * @}
@@ -140,27 +150,40 @@ void ald_tsense_source_select(tsense_source_sel_t sel)
   */
 ald_status_t ald_tsense_get_value(uint16_t *tsense)
 {
-    uint32_t tmp = 0;
+	uint32_t tmp = 0;
+
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
+
+	while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000));
 
-    TSENSE_UNLOCK();
-    SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
-    SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
-    TSENSE_LOCK();
+	if (tmp >= 1000000) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		return TIMEOUT;
+	}
 
-    while ((!(READ_BIT(TSENSE->IF, TSENSE_IF_TSENSE_MSK))) && (tmp++ < 1000000));
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	TSENSE_LOCK();
 
-    if (tmp >= 1000000)
-        return TIMEOUT;
+	if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		return ERROR;
+	}
 
-    TSENSE_UNLOCK();
-    SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
-    TSENSE_LOCK();
+	*tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS);
 
-    if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK))
-        return ERROR;
+	TSENSE_UNLOCK();
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
 
-    *tsense = READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS);
-    return OK;
+	return OK;
 }
 
 /**
@@ -170,15 +193,15 @@ ald_status_t ald_tsense_get_value(uint16_t *tsense)
   */
 void ald_tsense_get_value_by_it(tsense_cbk cbk)
 {
-    __tsense_cbk = cbk;
+	__tsense_cbk = cbk;
 
-    TSENSE_UNLOCK();
-    SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
-    SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK);
-    SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
-    TSENSE_LOCK();
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	SET_BIT(TSENSE->IE, TSENSE_IE_TSENSE_MSK);
+	SET_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
 
-    return;
+	return;
 }
 
 /**
@@ -187,25 +210,32 @@ void ald_tsense_get_value_by_it(tsense_cbk cbk)
   */
 void ald_tsense_irq_handler(void)
 {
-    TSENSE_UNLOCK();
-    SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
-    TSENSE_LOCK();
-
-    if (__tsense_cbk == NULL)
-        return;
-
-    if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK))
-    {
-        __tsense_cbk(0, ERROR);
-        return;
-    }
-
-    __tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK);
-
-    TSENSE_UNLOCK();
-    SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
-    TSENSE_LOCK();
-    return;
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	TSENSE_LOCK();
+
+	if (__tsense_cbk == NULL) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		return;
+	}
+
+	if (READ_BIT(TSENSE->DR, TSENSE_DR_ERR_MSK)) {
+		TSENSE_UNLOCK();
+		CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+		TSENSE_LOCK();
+		__tsense_cbk(0, ERROR);
+		return;
+	}
+
+	__tsense_cbk(READ_BITS(TSENSE->DR, TSENSE_DR_DATA_MSK, TSENSE_DR_DATA_POSS), OK);
+
+	TSENSE_UNLOCK();
+	SET_BIT(TSENSE->IFCR, TSENSE_IFCR_TSENSE_MSK);
+	CLEAR_BIT(TSENSE->CR, TSENSE_CR_EN_MSK);
+	TSENSE_LOCK();
+	return;
 }
 /**
   * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/ald_wdt.c

@@ -46,18 +46,18 @@
  */
 void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt)
 {
-    assert_param(IS_WWDT_WIN_TYPE(win));
-    assert_param(IS_FUNC_STATE(interrupt));
-
-    WWDT_UNLOCK();
-    WRITE_REG(WWDT->LOAD, load);
-    MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS);
-    SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK);
-    SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK);
-    MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS);
-    WWDT_LOCK();
-
-    return;
+	assert_param(IS_WWDT_WIN_TYPE(win));
+	assert_param(IS_FUNC_STATE(interrupt));
+
+	WWDT_UNLOCK();
+	WRITE_REG(WWDT->LOAD, load);
+	MODIFY_REG(WWDT->CON, WWDT_CON_WWDTWIN_MSK, win << WWDT_CON_WWDTWIN_POSS);
+	SET_BIT(WWDT->CON, WWDT_CON_CLKS_MSK);
+	SET_BIT(WWDT->CON, WWDT_CON_RSTEN_MSK);
+	MODIFY_REG(WWDT->CON, WWDT_CON_IE_MSK, interrupt << WWDT_CON_IE_POS);
+	WWDT_LOCK();
+
+	return;
 }
 
 /**
@@ -66,11 +66,11 @@ void ald_wwdt_init(uint32_t load, wwdt_win_t win, type_func_t interrupt)
  */
 void ald_wwdt_start(void)
 {
-    WWDT_UNLOCK();
-    SET_BIT(WWDT->CON, WWDT_CON_EN_MSK);
-    WWDT_LOCK();
+	WWDT_UNLOCK();
+	SET_BIT(WWDT->CON, WWDT_CON_EN_MSK);
+	WWDT_LOCK();
 
-    return;
+	return;
 }
 
 /**
@@ -79,7 +79,7 @@ void ald_wwdt_start(void)
  */
 uint32_t ald_wwdt_get_value(void)
 {
-    return WWDT->VALUE;
+	return WWDT->VALUE;
 }
 
 /**
@@ -88,10 +88,10 @@ uint32_t ald_wwdt_get_value(void)
  */
 it_status_t ald_wwdt_get_flag_status(void)
 {
-    if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK))
-        return SET;
+	if (READ_BIT(WWDT->RIS, WWDT_RIS_WWDTIF_MSK))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -100,8 +100,8 @@ it_status_t ald_wwdt_get_flag_status(void)
  */
 void ald_wwdt_clear_flag_status(void)
 {
-    WRITE_REG(WWDT->INTCLR, 1);
-    return;
+	WRITE_REG(WWDT->INTCLR, 1);
+	return;
 }
 
 /**
@@ -110,11 +110,11 @@ void ald_wwdt_clear_flag_status(void)
  */
 void ald_wwdt_feed_dog(void)
 {
-    WWDT_UNLOCK();
-    WRITE_REG(WWDT->INTCLR, 0x1);
-    WWDT_LOCK();
+	WWDT_UNLOCK();
+	WRITE_REG(WWDT->INTCLR, 0x1);
+	WWDT_LOCK();
 
-    return;
+	return;
 }
 /**
  * @}
@@ -132,16 +132,16 @@ void ald_wwdt_feed_dog(void)
  */
 void ald_iwdt_init(uint32_t load, type_func_t interrupt)
 {
-    assert_param(IS_FUNC_STATE(interrupt));
+	assert_param(IS_FUNC_STATE(interrupt));
 
-    IWDT_UNLOCK();
-    WRITE_REG(IWDT->LOAD, load);
-    SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK);
-    SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK);
-    MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS);
-    IWDT_LOCK();
+	IWDT_UNLOCK();
+	WRITE_REG(IWDT->LOAD, load);
+	SET_BIT(IWDT->CON, IWDT_CON_CLKS_MSK);
+	SET_BIT(IWDT->CON, IWDT_CON_RSTEN_MSK);
+	MODIFY_REG(IWDT->CON, IWDT_CON_IE_MSK, interrupt << IWDT_CON_IE_POS);
+	IWDT_LOCK();
 
-    return;
+	return;
 }
 
 /**
@@ -150,11 +150,11 @@ void ald_iwdt_init(uint32_t load, type_func_t interrupt)
  */
 void ald_iwdt_start(void)
 {
-    IWDT_UNLOCK();
-    SET_BIT(IWDT->CON, IWDT_CON_EN_MSK);
-    IWDT_LOCK();
+	IWDT_UNLOCK();
+	SET_BIT(IWDT->CON, IWDT_CON_EN_MSK);
+	IWDT_LOCK();
 
-    return;
+	return;
 }
 
 /**
@@ -163,7 +163,7 @@ void ald_iwdt_start(void)
  */
 uint32_t ald_iwdt_get_value(void)
 {
-    return IWDT->VALUE;
+	return IWDT->VALUE;
 }
 
 /**
@@ -172,10 +172,10 @@ uint32_t ald_iwdt_get_value(void)
  */
 it_status_t ald_iwdt_get_flag_status(void)
 {
-    if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK))
-        return SET;
+	if (READ_BIT(IWDT->RIS, IWDT_RIS_WDTIF_MSK))
+		return SET;
 
-    return RESET;
+	return RESET;
 }
 
 /**
@@ -184,8 +184,8 @@ it_status_t ald_iwdt_get_flag_status(void)
  */
 void ald_iwdt_clear_flag_status(void)
 {
-    WRITE_REG(IWDT->INTCLR, 1);
-    return;
+	WRITE_REG(IWDT->INTCLR, 1);
+	return;
 }
 
 /**
@@ -194,11 +194,11 @@ void ald_iwdt_clear_flag_status(void)
  */
 void ald_iwdt_feed_dog(void)
 {
-    IWDT_UNLOCK();
-    WRITE_REG(IWDT->INTCLR, 1);
-    IWDT_LOCK();
+	IWDT_UNLOCK();
+	WRITE_REG(IWDT->INTCLR, 1);
+	IWDT_LOCK();
 
-    return;
+	return;
 }
 /**
  * @}

bsp/essemi/es32f0334/libraries/ES32F033x_ALD_StdPeriph_Driver/Source/utils.c

@@ -14,6 +14,7 @@
   *********************************************************************************
   */
 
+#include <string.h>
 #include "utils.h"
 #include "ald_dma.h"
 #include "ald_cmu.h"
@@ -42,9 +43,9 @@
 #define __ALD_VERSION_SUB2	(0x00) /**< [15:8]  sub2 version */
 #define __ALD_VERSION_RC	(0x00) /**< [7:0]  release candidate */
 #define __ALD_VERSION		((__ALD_VERSION_MAIN << 24) | \
-                             (__ALD_VERSION_SUB1 << 16) | \
-                             (__ALD_VERSION_SUB2 << 8 ) | \
-                             (__ALD_VERSION_RC))
+                                 (__ALD_VERSION_SUB1 << 16) | \
+                                 (__ALD_VERSION_SUB2 << 8 ) | \
+                                 (__ALD_VERSION_RC))
 /**
   * @}
   */
@@ -110,12 +111,12 @@ uint32_t __systick_interval = SYSTICK_INTERVAL_1MS;
   */
 void ald_cmu_init(void)
 {
-    ald_cmu_clock_config_default();
-    ald_tick_init(TICK_INT_PRIORITY);
+	ald_cmu_clock_config_default();
+	ald_tick_init(TICK_INT_PRIORITY);
 #ifdef ALD_DMA
-    ald_dma_init(DMA0);
+	ald_dma_init(DMA0);
 #endif
-    return;
+	return;
 }
 
 /**
@@ -134,13 +135,13 @@ void ald_cmu_init(void)
   */
 __weak void ald_tick_init(uint32_t prio)
 {
-    /* Configure the SysTick IRQ */
-    SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS);
+	/* Configure the SysTick IRQ */
+	SysTick_Config(ald_cmu_get_sys_clock() / SYSTICK_INTERVAL_1MS);
 
-    if (prio != 3)
-        NVIC_SetPriority(SysTick_IRQn, prio);
+	if (prio != 3)
+		NVIC_SetPriority(SysTick_IRQn, prio);
 
-    return;
+	return;
 }
 
 /**
@@ -154,15 +155,15 @@ __weak void ald_tick_init(uint32_t prio)
   */
 void ald_systick_interval_select(systick_interval_t value)
 {
-    assert_param(IS_SYSTICK_INTERVAL(value));
+	assert_param(IS_SYSTICK_INTERVAL(value));
 
-    SysTick_Config(ald_cmu_get_sys_clock() / value);
-    __systick_interval = value;
+	SysTick_Config(ald_cmu_get_sys_clock() / value);
+	__systick_interval = value;
 
-    if (TICK_INT_PRIORITY != 3)
-        NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY);
+	if (TICK_INT_PRIORITY != 3)
+		NVIC_SetPriority(SysTick_IRQn, TICK_INT_PRIORITY);
 
-    return;
+	return;
 }
 /**
   * @}
@@ -185,6 +186,9 @@ void ald_systick_interval_select(systick_interval_t value)
       (+) Configure the interrupt
       (+) Provide system tick value
       (+) Get CPU ID
+      (+) Get UID
+      (+) Get CHIPID
+
     @endverbatim
   * @{
   */
@@ -200,7 +204,7 @@ void ald_systick_interval_select(systick_interval_t value)
   */
 __weak void ald_inc_tick_weak(void)
 {
-    ++lib_tick;
+	++lib_tick;
 }
 
 /**
@@ -211,8 +215,8 @@ __weak void ald_inc_tick_weak(void)
   */
 __weak void ald_systick_irq_cbk(void)
 {
-    /* do nothing */
-    return;
+	/* do nothing */
+	return;
 }
 
 /**
@@ -221,10 +225,10 @@ __weak void ald_systick_irq_cbk(void)
   */
 __isr__ void ald_inc_tick(void)
 {
-    ald_inc_tick_weak();
-    ald_systick_irq_cbk();
+	ald_inc_tick_weak();
+	ald_systick_irq_cbk();
 
-    return;
+	return;
 }
 
 /**
@@ -235,7 +239,7 @@ __isr__ void ald_inc_tick(void)
   */
 __weak uint32_t ald_get_tick(void)
 {
-    return lib_tick;
+	return lib_tick;
 }
 
 /**
@@ -251,36 +255,35 @@ __weak uint32_t ald_get_tick(void)
   */
 __weak void ald_delay_ms(__IO uint32_t delay)
 {
-    uint32_t tick, __delay;
+	uint32_t tick, __delay;
 
-    switch (__systick_interval)
-    {
-        case SYSTICK_INTERVAL_1MS:
-            __delay = delay;
-            break;
+	switch (__systick_interval) {
+	case SYSTICK_INTERVAL_1MS:
+		__delay = delay;
+		break;
 
-        case SYSTICK_INTERVAL_10MS:
-            __delay = delay / 10;
-            break;
+	case SYSTICK_INTERVAL_10MS:
+		__delay = delay / 10;
+		break;
 
-        case SYSTICK_INTERVAL_100MS:
-            __delay = delay / 100;
-            break;
+	case SYSTICK_INTERVAL_100MS:
+		__delay = delay / 100;
+		break;
 
-        case SYSTICK_INTERVAL_1000MS:
-            __delay = delay / 1000;
-            break;
+	case SYSTICK_INTERVAL_1000MS:
+		__delay = delay / 1000;
+		break;
 
-        default:
-            __delay = delay;
-            break;
-    }
+	default:
+		__delay = delay;
+		break;
+	}
 
-    tick    = ald_get_tick();
-    __delay = __delay == 0 ? 1 : __delay;
+	tick    = ald_get_tick();
+	__delay = __delay == 0 ? 1 : __delay;
 
-    while ((ald_get_tick() - tick) < __delay)
-        ;
+	while ((ald_get_tick() - tick) < __delay)
+		;
 }
 
 /**
@@ -295,7 +298,7 @@ __weak void ald_delay_ms(__IO uint32_t delay)
   */
 __weak void ald_suspend_tick(void)
 {
-    CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+	CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 }
 
 /**
@@ -310,7 +313,7 @@ __weak void ald_suspend_tick(void)
   */
 __weak void ald_resume_tick(void)
 {
-    SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
+	SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 }
 
 /**
@@ -319,7 +322,7 @@ __weak void ald_resume_tick(void)
   */
 uint32_t ald_get_ald_version(void)
 {
-    return __ALD_VERSION;
+	return __ALD_VERSION;
 }
 
 /**
@@ -332,28 +335,24 @@ uint32_t ald_get_ald_version(void)
   */
 ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, uint32_t timeout)
 {
-    uint32_t tick = ald_get_tick();
-
-    assert_param(timeout > 0);
-
-    if (status == SET)
-    {
-        while (!(IS_BIT_SET(*reg, bit)))
-        {
-            if (((ald_get_tick()) - tick) > timeout)
-                return TIMEOUT;
-        }
-    }
-    else
-    {
-        while ((IS_BIT_SET(*reg, bit)))
-        {
-            if (((ald_get_tick()) - tick) > timeout)
-                return TIMEOUT;
-        }
-    }
-
-    return OK;
+	uint32_t tick = ald_get_tick();
+
+	assert_param(timeout > 0);
+
+	if (status == SET) {
+		while (!(IS_BIT_SET(*reg, bit))) {
+			if (((ald_get_tick()) - tick) > timeout)
+				return TIMEOUT;
+		}
+	}
+	else {
+		while ((IS_BIT_SET(*reg, bit))) {
+			if (((ald_get_tick()) - tick) > timeout)
+				return TIMEOUT;
+		}
+	}
+
+	return OK;
 }
 
 /**
@@ -367,20 +366,18 @@ ald_status_t ald_wait_flag(uint32_t *reg, uint32_t bit, flag_status_t status, ui
   */
 void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status)
 {
-    assert_param(IS_FUNC_STATE(status));
-    assert_param(IS_PRIO(prio));
-
-    if (status == ENABLE)
-    {
-        NVIC_SetPriority(irq, prio);
-        NVIC_EnableIRQ(irq);
-    }
-    else
-    {
-        NVIC_DisableIRQ(irq);
-    }
-
-    return;
+	assert_param(IS_FUNC_STATE(status));
+	assert_param(IS_PRIO(prio));
+
+	if (status == ENABLE) {
+		NVIC_SetPriority(irq, prio);
+		NVIC_EnableIRQ(irq);
+	}
+	else {
+		NVIC_DisableIRQ(irq);
+	}
+
+	return;
 }
 
 /**
@@ -389,10 +386,10 @@ void ald_mcu_irq_config(IRQn_Type irq, uint8_t prio, type_func_t status)
   */
 uint32_t ald_mcu_get_tick(void)
 {
-    uint32_t load = SysTick->LOAD;
-    uint32_t val  = SysTick->VAL;
+	uint32_t load = SysTick->LOAD;
+	uint32_t val  = SysTick->VAL;
 
-    return (load - val);
+	return (load - val);
 }
 
 /**
@@ -401,9 +398,31 @@ uint32_t ald_mcu_get_tick(void)
   */
 uint32_t ald_mcu_get_cpu_id(void)
 {
-    return SCB->CPUID;
+	return SCB->CPUID;
+}
+
+/**
+  * @brief  Get the UID.
+  * @param  buf: Pointer to UID, len: 12Bytes(96-bits)
+  * @retval None
+  */
+void ald_mcu_get_uid(uint8_t *buf)
+{
+	memcpy(&buf[0], (void *)MCU_UID0_ADDR, 4);
+	memcpy(&buf[4], (void *)MCU_UID1_ADDR, 4);
+	memcpy(&buf[8], (void *)MCU_UID2_ADDR, 4);
+
+	return;
 }
 
+/**
+  * @brief  Get the CHIPID
+  * @retval CHPID
+  */
+uint32_t ald_mcu_get_chipid(void)
+{
+	return (uint32_t)*(uint32_t *)MCU_CHIPID_ADDR;
+}
 /**
   * @}
   */

bsp/essemi/es32f0334/project.uvoptx

@@ -73,7 +73,7 @@
         <LExpSel>0</LExpSel>
       </OPTXL>
       <OPTFL>
-        <tvExp>0</tvExp>
+        <tvExp>1</tvExp>
         <tvExpOptDlg>0</tvExpOptDlg>
         <IsCurrentTarget>1</IsCurrentTarget>
       </OPTFL>
@@ -101,7 +101,9 @@
         <sRunDeb>0</sRunDeb>
         <sLrtime>0</sLrtime>
         <bEvRecOn>1</bEvRecOn>
-        <nTsel>2</nTsel>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -118,7 +120,7 @@
         <SetRegEntry>
           <Number>0</Number>
           <Key>CMSIS_AGDI</Key>
-          <Name>-X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO18 -TC10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)</Name>
+          <Name>-X"Any" -UAny -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0ES32F033x.FLM -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM)</Name>
         </SetRegEntry>
         <SetRegEntry>
           <Number>0</Number>
@@ -170,7 +172,967 @@
       <pszMrule></pszMrule>
       <pSingCmds></pSingCmds>
       <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
     </TargetOption>
   </Target>
 
+  <Group>
+    <GroupName>Applications</GroupName>
+    <tvExp>1</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>1</GroupNumber>
+      <FileNumber>1</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>applications\main.c</PathWithFileName>
+      <FilenameWithoutPath>main.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>cpu</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>2</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\backtrace.c</PathWithFileName>
+      <FilenameWithoutPath>backtrace.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>3</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\div0.c</PathWithFileName>
+      <FilenameWithoutPath>div0.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>4</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\common\showmem.c</PathWithFileName>
+      <FilenameWithoutPath>showmem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>5</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m0\cpuport.c</PathWithFileName>
+      <FilenameWithoutPath>cpuport.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>2</GroupNumber>
+      <FileNumber>6</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</PathWithFileName>
+      <FilenameWithoutPath>context_rvds.S</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>DeviceDrivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>7</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\hwtimer\hwtimer.c</PathWithFileName>
+      <FilenameWithoutPath>hwtimer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>8</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\i2c\i2c_core.c</PathWithFileName>
+      <FilenameWithoutPath>i2c_core.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>9</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\i2c\i2c_dev.c</PathWithFileName>
+      <FilenameWithoutPath>i2c_dev.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>10</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\i2c\i2c-bit-ops.c</PathWithFileName>
+      <FilenameWithoutPath>i2c-bit-ops.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>11</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\misc\pin.c</PathWithFileName>
+      <FilenameWithoutPath>pin.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>12</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\misc\adc.c</PathWithFileName>
+      <FilenameWithoutPath>adc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>13</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\misc\rt_drv_pwm.c</PathWithFileName>
+      <FilenameWithoutPath>rt_drv_pwm.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>14</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\pm\pm.c</PathWithFileName>
+      <FilenameWithoutPath>pm.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>15</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\rtc\rtc.c</PathWithFileName>
+      <FilenameWithoutPath>rtc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>16</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\serial\serial.c</PathWithFileName>
+      <FilenameWithoutPath>serial.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>17</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\spi\spi_core.c</PathWithFileName>
+      <FilenameWithoutPath>spi_core.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>18</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\spi\spi_dev.c</PathWithFileName>
+      <FilenameWithoutPath>spi_dev.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>19</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\completion.c</PathWithFileName>
+      <FilenameWithoutPath>completion.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>20</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\dataqueue.c</PathWithFileName>
+      <FilenameWithoutPath>dataqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>21</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\pipe.c</PathWithFileName>
+      <FilenameWithoutPath>pipe.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>22</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\ringblk_buf.c</PathWithFileName>
+      <FilenameWithoutPath>ringblk_buf.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>23</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\ringbuffer.c</PathWithFileName>
+      <FilenameWithoutPath>ringbuffer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>24</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\waitqueue.c</PathWithFileName>
+      <FilenameWithoutPath>waitqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>3</GroupNumber>
+      <FileNumber>25</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\drivers\src\workqueue.c</PathWithFileName>
+      <FilenameWithoutPath>workqueue.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Drivers</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>26</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>drivers\board.c</PathWithFileName>
+      <FilenameWithoutPath>board.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>27</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>drivers\drv_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>drv_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>4</GroupNumber>
+      <FileNumber>28</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>drivers\drv_uart.c</PathWithFileName>
+      <FilenameWithoutPath>drv_uart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>finsh</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>29</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\shell.c</PathWithFileName>
+      <FilenameWithoutPath>shell.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>30</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\cmd.c</PathWithFileName>
+      <FilenameWithoutPath>cmd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>5</GroupNumber>
+      <FileNumber>31</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\components\finsh\msh.c</PathWithFileName>
+      <FilenameWithoutPath>msh.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Kernel</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>32</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\clock.c</PathWithFileName>
+      <FilenameWithoutPath>clock.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>33</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\components.c</PathWithFileName>
+      <FilenameWithoutPath>components.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>34</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\device.c</PathWithFileName>
+      <FilenameWithoutPath>device.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>35</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\idle.c</PathWithFileName>
+      <FilenameWithoutPath>idle.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>36</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\ipc.c</PathWithFileName>
+      <FilenameWithoutPath>ipc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>37</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\irq.c</PathWithFileName>
+      <FilenameWithoutPath>irq.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>38</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\kservice.c</PathWithFileName>
+      <FilenameWithoutPath>kservice.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>39</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\mem.c</PathWithFileName>
+      <FilenameWithoutPath>mem.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>40</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\mempool.c</PathWithFileName>
+      <FilenameWithoutPath>mempool.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>41</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\object.c</PathWithFileName>
+      <FilenameWithoutPath>object.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>42</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\scheduler.c</PathWithFileName>
+      <FilenameWithoutPath>scheduler.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>43</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\signal.c</PathWithFileName>
+      <FilenameWithoutPath>signal.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>44</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\thread.c</PathWithFileName>
+      <FilenameWithoutPath>thread.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>6</GroupNumber>
+      <FileNumber>45</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\..\..\src\timer.c</PathWithFileName>
+      <FilenameWithoutPath>timer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
+  <Group>
+    <GroupName>Libraries</GroupName>
+    <tvExp>0</tvExp>
+    <tvExpOptDlg>0</tvExpOptDlg>
+    <cbSel>0</cbSel>
+    <RteFlg>0</RteFlg>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>46</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_acmp.c</PathWithFileName>
+      <FilenameWithoutPath>ald_acmp.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>47</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_adc.c</PathWithFileName>
+      <FilenameWithoutPath>ald_adc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>48</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_bkpc.c</PathWithFileName>
+      <FilenameWithoutPath>ald_bkpc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>49</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_calc.c</PathWithFileName>
+      <FilenameWithoutPath>ald_calc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>50</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_cmu.c</PathWithFileName>
+      <FilenameWithoutPath>ald_cmu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>51</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crc.c</PathWithFileName>
+      <FilenameWithoutPath>ald_crc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>52</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crypt.c</PathWithFileName>
+      <FilenameWithoutPath>ald_crypt.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>53</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_dma.c</PathWithFileName>
+      <FilenameWithoutPath>ald_dma.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>54</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash.c</PathWithFileName>
+      <FilenameWithoutPath>ald_flash.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>55</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c</PathWithFileName>
+      <FilenameWithoutPath>ald_flash_ext.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>56</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_gpio.c</PathWithFileName>
+      <FilenameWithoutPath>ald_gpio.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>57</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_i2c.c</PathWithFileName>
+      <FilenameWithoutPath>ald_i2c.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>58</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_iap.c</PathWithFileName>
+      <FilenameWithoutPath>ald_iap.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>59</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lcd.c</PathWithFileName>
+      <FilenameWithoutPath>ald_lcd.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>60</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lptim.c</PathWithFileName>
+      <FilenameWithoutPath>ald_lptim.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>61</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lpuart.c</PathWithFileName>
+      <FilenameWithoutPath>ald_lpuart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>62</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pis.c</PathWithFileName>
+      <FilenameWithoutPath>ald_pis.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>63</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pmu.c</PathWithFileName>
+      <FilenameWithoutPath>ald_pmu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>64</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rmu.c</PathWithFileName>
+      <FilenameWithoutPath>ald_rmu.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>65</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rtc.c</PathWithFileName>
+      <FilenameWithoutPath>ald_rtc.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>66</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_smartcard.c</PathWithFileName>
+      <FilenameWithoutPath>ald_smartcard.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>67</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_spi.c</PathWithFileName>
+      <FilenameWithoutPath>ald_spi.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>68</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_timer.c</PathWithFileName>
+      <FilenameWithoutPath>ald_timer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>69</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_trng.c</PathWithFileName>
+      <FilenameWithoutPath>ald_trng.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>70</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_tsense.c</PathWithFileName>
+      <FilenameWithoutPath>ald_tsense.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>71</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_uart.c</PathWithFileName>
+      <FilenameWithoutPath>ald_uart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>72</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_usart.c</PathWithFileName>
+      <FilenameWithoutPath>ald_usart.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>73</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_wdt.c</PathWithFileName>
+      <FilenameWithoutPath>ald_wdt.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>74</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\utils.c</PathWithFileName>
+      <FilenameWithoutPath>utils.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>75</FileNumber>
+      <FileType>2</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>libraries\CMSIS\Device\EastSoft\es32f033x\Startup\keil\startup_es32f033x.s</PathWithFileName>
+      <FilenameWithoutPath>startup_es32f033x.s</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+  </Group>
+
 </ProjectOpt>

bsp/essemi/es32f0334/project.uvprojx

@@ -1,41 +1,46 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
 <Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
+
   <SchemaVersion>2.1</SchemaVersion>
+
   <Header>### uVision Project, (C) Keil Software</Header>
+
   <Targets>
     <Target>
       <TargetName>rt-thread</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
+      <pCCUsed>5060750::V5.06 update 6 (build 750)::ARMCC</pCCUsed>
+      <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>ES32F0334LT</Device>
           <Vendor>Eastsoft</Vendor>
-          <PackID>Eastsoft.ES32_DFP.1.0.1</PackID>
+          <PackID>Eastsoft.ES32_DFP.7.2350</PackID>
           <PackURL>http://www.essemi.com</PackURL>
           <Cpu>IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
-          <FlashUtilSpec />
-          <StartupFile />
+          <FlashUtilSpec></FlashUtilSpec>
+          <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0ES32F033x -FS00 -FL040000 -FP0($$Device:ES32F0334LT$Flash\ES32F033x.FLM))</FlashDriverDll>
           <DeviceId>0</DeviceId>
           <RegisterFile>$$Device:ES32F0334LT$Device\Include\es32f033x.h</RegisterFile>
-          <MemoryEnv />
-          <Cmp />
-          <Asm />
-          <Linker />
-          <OHString />
-          <InfinionOptionDll />
-          <SLE66CMisc />
-          <SLE66AMisc />
-          <SLE66LinkerMisc />
+          <MemoryEnv></MemoryEnv>
+          <Cmp></Cmp>
+          <Asm></Asm>
+          <Linker></Linker>
+          <OHString></OHString>
+          <InfinionOptionDll></InfinionOptionDll>
+          <SLE66CMisc></SLE66CMisc>
+          <SLE66AMisc></SLE66AMisc>
+          <SLE66LinkerMisc></SLE66LinkerMisc>
           <SFDFile>$$Device:ES32F0334LT$SVD\es32f0xx.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
-          <BinPath />
-          <IncludePath />
-          <LibPath />
-          <RegisterFilePath />
-          <DBRegisterFilePath />
+          <BinPath></BinPath>
+          <IncludePath></IncludePath>
+          <LibPath></LibPath>
+          <RegisterFilePath></RegisterFilePath>
+          <DBRegisterFilePath></DBRegisterFilePath>
           <TargetStatus>
             <Error>0</Error>
             <ExitCodeStop>0</ExitCodeStop>
@@ -57,8 +62,8 @@
           <BeforeCompile>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopU1X>0</nStopU1X>
@@ -67,8 +72,8 @@
           <BeforeMake>
             <RunUserProg1>0</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
-            <UserProg1Name />
-            <UserProg2Name />
+            <UserProg1Name></UserProg1Name>
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopB1X>0</nStopB1X>
@@ -78,14 +83,14 @@
             <RunUserProg1>1</RunUserProg1>
             <RunUserProg2>0</RunUserProg2>
             <UserProg1Name>fromelf --bin !L --output rtthread.bin</UserProg1Name>
-            <UserProg2Name />
+            <UserProg2Name></UserProg2Name>
             <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
             <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
             <nStopA1X>0</nStopA1X>
             <nStopA2X>0</nStopA2X>
           </AfterMake>
           <SelectedForBatchBuild>0</SelectedForBatchBuild>
-          <SVCSIdString />
+          <SVCSIdString></SVCSIdString>
         </TargetCommonOption>
         <CommonProperty>
           <UseCPPCompiler>0</UseCPPCompiler>
@@ -99,8 +104,8 @@
           <AssembleAssemblyFile>0</AssembleAssemblyFile>
           <PublicsOnly>0</PublicsOnly>
           <StopOnExitCode>3</StopOnExitCode>
-          <CustomArgument />
-          <IncludeLibraryModules />
+          <CustomArgument></CustomArgument>
+          <IncludeLibraryModules></IncludeLibraryModules>
           <ComprImg>1</ComprImg>
         </CommonProperty>
         <DllOption>
@@ -134,10 +139,10 @@
           <bUseTDR>1</bUseTDR>
           <Flash2>BIN\UL2CM3.DLL</Flash2>
           <Flash3>"" ()</Flash3>
-          <Flash4 />
-          <pFcarmOut />
-          <pFcarmGrp />
-          <pFcArmRoot />
+          <Flash4></Flash4>
+          <pFcarmOut></pFcarmOut>
+          <pFcarmGrp></pFcarmGrp>
+          <pFcArmRoot></pFcArmRoot>
           <FcArmLst>0</FcArmLst>
         </Utilities>
         <TargetArmAds>
@@ -170,7 +175,7 @@
             <RvctClst>0</RvctClst>
             <GenPPlst>0</GenPPlst>
             <AdsCpuType>"Cortex-M0"</AdsCpuType>
-            <RvctDeviceName />
+            <RvctDeviceName></RvctDeviceName>
             <mOS>0</mOS>
             <uocRom>0</uocRom>
             <uocRam>0</uocRam>
@@ -179,6 +184,7 @@
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
             <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -302,7 +308,7 @@
                 <Size>0x0</Size>
               </OCR_RVCT10>
             </OnChipMemories>
-            <RvctStartVector />
+            <RvctStartVector></RvctStartVector>
           </ArmAdsMisc>
           <Cads>
             <interw>1</interw>
@@ -319,6 +325,7 @@
             <uThumb>0</uThumb>
             <uSurpInc>0</uSurpInc>
             <uC99>1</uC99>
+            <uGnu>0</uGnu>
             <useXO>0</useXO>
             <v6Lang>1</v6Lang>
             <v6LangP>1</v6LangP>
@@ -328,10 +335,10 @@
             <v6WtE>0</v6WtE>
             <v6Rtti>0</v6Rtti>
             <VariousControls>
-              <MiscControls />
+              <MiscControls></MiscControls>
               <Define>ES32F033x</Define>
-              <Undefine />
-              <IncludePath>.;..\..\..\include;applications;.;drivers;libraries\CMSIS\Device\EastSoft\es32f033x\Include;libraries\CMSIS\Include;libraries\ES32F033x_ALD_StdPeriph_Driver\Include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common</IncludePath>
+              <Undefine></Undefine>
+              <IncludePath>applications;.;drivers;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;..\..\..\components\drivers\include;..\..\..\components\drivers\include;drivers;..\..\..\components\finsh;.;..\..\..\include;libraries\CMSIS\Device\EastSoft\es32f033x\Include;libraries\CMSIS\Include;libraries\ES32F033x_ALD_StdPeriph_Driver\Include</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -346,10 +353,10 @@
             <useXO>0</useXO>
             <uClangAs>0</uClangAs>
             <VariousControls>
-              <MiscControls />
-              <Define />
-              <Undefine />
-              <IncludePath />
+              <MiscControls></MiscControls>
+              <Define></Define>
+              <Undefine></Undefine>
+              <IncludePath></IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -361,17 +368,266 @@
             <useFile>0</useFile>
             <TextAddressRange>0x08000000</TextAddressRange>
             <DataAddressRange>0x20000000</DataAddressRange>
-            <pXoBase />
-            <ScatterFile />
-            <IncludeLibs />
-            <IncludeLibsPath />
-            <Misc />
-            <LinkerInputFile />
-            <DisabledWarnings />
+            <pXoBase></pXoBase>
+            <ScatterFile></ScatterFile>
+            <IncludeLibs></IncludeLibs>
+            <IncludeLibsPath></IncludeLibsPath>
+            <Misc></Misc>
+            <LinkerInputFile></LinkerInputFile>
+            <DisabledWarnings></DisabledWarnings>
           </LDads>
         </TargetArmAds>
       </TargetOption>
       <Groups>
+        <Group>
+          <GroupName>Applications</GroupName>
+          <Files>
+            <File>
+              <FileName>main.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>applications\main.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>cpu</GroupName>
+          <Files>
+            <File>
+              <FileName>backtrace.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
+            </File>
+            <File>
+              <FileName>div0.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
+            </File>
+            <File>
+              <FileName>showmem.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
+            </File>
+            <File>
+              <FileName>cpuport.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
+            </File>
+            <File>
+              <FileName>context_rvds.S</FileName>
+              <FileType>2</FileType>
+              <FilePath>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>DeviceDrivers</GroupName>
+          <GroupOption>
+            <CommonProperty>
+              <UseCPPCompiler>0</UseCPPCompiler>
+              <RVCTCodeConst>0</RVCTCodeConst>
+              <RVCTZI>0</RVCTZI>
+              <RVCTOtherData>0</RVCTOtherData>
+              <ModuleSelection>0</ModuleSelection>
+              <IncludeInBuild>1</IncludeInBuild>
+              <AlwaysBuild>0</AlwaysBuild>
+              <GenerateAssemblyFile>0</GenerateAssemblyFile>
+              <AssembleAssemblyFile>0</AssembleAssemblyFile>
+              <PublicsOnly>0</PublicsOnly>
+              <StopOnExitCode>3</StopOnExitCode>
+              <CustomArgument></CustomArgument>
+              <IncludeLibraryModules></IncludeLibraryModules>
+              <ComprImg>0</ComprImg>
+            </CommonProperty>
+            <GroupArmAds>
+              <Cads>
+                <interw>2</interw>
+                <Optim>0</Optim>
+                <oTime>2</oTime>
+                <SplitLS>2</SplitLS>
+                <OneElfS>2</OneElfS>
+                <Strict>2</Strict>
+                <EnumInt>2</EnumInt>
+                <PlainCh>2</PlainCh>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <wLevel>0</wLevel>
+                <uThumb>2</uThumb>
+                <uSurpInc>2</uSurpInc>
+                <uC99>2</uC99>
+                <uGnu>2</uGnu>
+                <useXO>2</useXO>
+                <v6Lang>0</v6Lang>
+                <v6LangP>0</v6LangP>
+                <vShortEn>2</vShortEn>
+                <vShortWch>2</vShortWch>
+                <v6Lto>2</v6Lto>
+                <v6WtE>2</v6WtE>
+                <v6Rtti>2</v6Rtti>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define> </Define>
+                  <Undefine> </Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Cads>
+              <Aads>
+                <interw>2</interw>
+                <Ropi>2</Ropi>
+                <Rwpi>2</Rwpi>
+                <thumb>2</thumb>
+                <SplitLS>2</SplitLS>
+                <SwStkChk>2</SwStkChk>
+                <NoWarn>2</NoWarn>
+                <uSurpInc>2</uSurpInc>
+                <useXO>2</useXO>
+                <uClangAs>2</uClangAs>
+                <VariousControls>
+                  <MiscControls></MiscControls>
+                  <Define></Define>
+                  <Undefine></Undefine>
+                  <IncludePath></IncludePath>
+                </VariousControls>
+              </Aads>
+            </GroupArmAds>
+          </GroupOption>
+          <Files>
+            <File>
+              <FileName>hwtimer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\hwtimer\hwtimer.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\i2c\i2c_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\i2c\i2c_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>i2c-bit-ops.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\i2c\i2c-bit-ops.c</FilePath>
+            </File>
+            <File>
+              <FileName>pin.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
+            </File>
+            <File>
+              <FileName>adc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\misc\adc.c</FilePath>
+            </File>
+            <File>
+              <FileName>rt_drv_pwm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\misc\rt_drv_pwm.c</FilePath>
+            </File>
+            <File>
+              <FileName>pm.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\pm\pm.c</FilePath>
+            </File>
+            <File>
+              <FileName>rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\rtc\rtc.c</FilePath>
+            </File>
+            <File>
+              <FileName>serial.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_core.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
+            </File>
+            <File>
+              <FileName>spi_dev.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
+            </File>
+            <File>
+              <FileName>completion.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
+            </File>
+            <File>
+              <FileName>dataqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>pipe.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringblk_buf.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
+            </File>
+            <File>
+              <FileName>ringbuffer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
+            </File>
+            <File>
+              <FileName>waitqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
+            </File>
+            <File>
+              <FileName>workqueue.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>Drivers</GroupName>
+          <Files>
+            <File>
+              <FileName>board.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\board.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_gpio.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_gpio.c</FilePath>
+            </File>
+            <File>
+              <FileName>drv_uart.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_uart.c</FilePath>
+            </File>
+          </Files>
+        </Group>
+        <Group>
+          <GroupName>finsh</GroupName>
+          <Files>
+            <File>
+              <FileName>shell.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
+            </File>
+            <File>
+              <FileName>cmd.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
+            </File>
+            <File>
+              <FileName>msh.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
+            </File>
+          </Files>
+        </Group>
         <Group>
           <GroupName>Kernel</GroupName>
           <Files>
@@ -380,92 +636,66 @@
               <FileType>1</FileType>
               <FilePath>..\..\..\src\clock.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>components.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\components.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>device.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\device.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>idle.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\idle.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ipc.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\ipc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>irq.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\irq.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>kservice.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\kservice.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>mem.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\mem.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>mempool.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\mempool.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>object.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\object.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>scheduler.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\scheduler.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>signal.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\signal.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>thread.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\..\src\thread.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>timer.c</FileName>
               <FileType>1</FileType>
@@ -473,40 +703,6 @@
             </File>
           </Files>
         </Group>
-        <Group>
-          <GroupName>Applications</GroupName>
-          <Files>
-            <File>
-              <FileName>main.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>applications\main.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>Drivers</GroupName>
-          <Files>
-            <File>
-              <FileName>board.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>drivers\board.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>drv_gpio.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>drivers\drv_gpio.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>drv_uart.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>drivers\drv_uart.c</FilePath>
-            </File>
-          </Files>
-        </Group>
         <Group>
           <GroupName>Libraries</GroupName>
           <Files>
@@ -515,204 +711,146 @@
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_acmp.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_adc.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_adc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_bkpc.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_bkpc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_calc.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_calc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_cmu.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_cmu.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_crc.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_crypt.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_crypt.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_dma.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_dma.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_flash.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_flash_ext.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_flash_ext.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_gpio.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_gpio.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_i2c.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_i2c.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_iap.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_iap.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_lcd.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lcd.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_lptim.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lptim.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_lpuart.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_lpuart.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_pis.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pis.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_pmu.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_pmu.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_rmu.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rmu.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_rtc.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_rtc.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_smartcard.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_smartcard.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_spi.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_spi.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_timer.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_timer.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_trng.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_trng.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_tsense.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_tsense.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_uart.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_uart.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_usart.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_usart.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>ald_wdt.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\ald_wdt.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>utils.c</FileName>
               <FileType>1</FileType>
               <FilePath>libraries\ES32F033x_ALD_StdPeriph_Driver\Source\utils.c</FilePath>
             </File>
-          </Files>
-          <Files>
             <File>
               <FileName>startup_es32f033x.s</FileName>
               <FileType>2</FileType>
@@ -720,140 +858,14 @@
             </File>
           </Files>
         </Group>
-        <Group>
-          <GroupName>cpu</GroupName>
-          <Files>
-            <File>
-              <FileName>backtrace.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\common\backtrace.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>div0.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\common\div0.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>showmem.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\common\showmem.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cpuport.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\libcpu\arm\cortex-m0\cpuport.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>context_rvds.S</FileName>
-              <FileType>2</FileType>
-              <FilePath>..\..\..\libcpu\arm\cortex-m0\context_rvds.S</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>DeviceDrivers</GroupName>
-          <Files>
-            <File>
-              <FileName>pin.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\misc\pin.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>serial.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>completion.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\completion.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>dataqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\dataqueue.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>pipe.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\pipe.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>ringblk_buf.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\ringblk_buf.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>ringbuffer.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\ringbuffer.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>waitqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\waitqueue.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>workqueue.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\drivers\src\workqueue.c</FilePath>
-            </File>
-          </Files>
-        </Group>
-        <Group>
-          <GroupName>finsh</GroupName>
-          <Files>
-            <File>
-              <FileName>shell.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\shell.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>cmd.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\cmd.c</FilePath>
-            </File>
-          </Files>
-          <Files>
-            <File>
-              <FileName>msh.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>..\..\..\components\finsh\msh.c</FilePath>
-            </File>
-          </Files>
-        </Group>
       </Groups>
     </Target>
   </Targets>
+
   <RTE>
-    <apis />
-    <components />
-    <files />
+    <apis/>
+    <components/>
+    <files/>
   </RTE>
+
 </Project>

bsp/essemi/es32f0334/rtconfig.h

@@ -39,7 +39,7 @@
 #define RT_USING_CONSOLE
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart1"
-#define RT_VER_NUM 0x40002
+#define RT_VER_NUM 0x40003
 
 /* RT-Thread Components */
 
@@ -76,7 +76,15 @@
 #define RT_PIPE_BUFSZ 512
 #define RT_USING_SERIAL
 #define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_HWTIMER
+#define RT_USING_I2C
+#define RT_USING_I2C_BITOPS
 #define RT_USING_PIN
+#define RT_USING_ADC
+#define RT_USING_PWM
+#define RT_USING_PM
+#define RT_USING_RTC
+#define RT_USING_SPI
 
 /* Using USB */
 
@@ -180,6 +188,8 @@
 
 /* Offboard Peripheral Drivers */
 
+/* Peripheral Drivers test example */
+
 #define SOC_ES32F0334LT
 
 #endif

bsp/essemi/es32f0334/template.uvoptx

@@ -101,7 +101,9 @@
         <sRunDeb>0</sRunDeb>
         <sLrtime>0</sLrtime>
         <bEvRecOn>1</bEvRecOn>
-        <nTsel>2</nTsel>
+        <bSchkAxf>0</bSchkAxf>
+        <bTchkAxf>0</bTchkAxf>
+        <nTsel>3</nTsel>
         <sDll></sDll>
         <sDllPa></sDllPa>
         <sDlgDll></sDlgDll>
@@ -170,6 +172,10 @@
       <pszMrule></pszMrule>
       <pSingCmds></pSingCmds>
       <pMultCmds></pMultCmds>
+      <pMisraNamep></pMisraNamep>
+      <pszMrulep></pszMrulep>
+      <pSingCmdsp></pSingCmdsp>
+      <pMultCmdsp></pMultCmdsp>
     </TargetOption>
   </Target>
 

bsp/essemi/es32f0334/template.uvprojx

@@ -10,11 +10,12 @@
       <TargetName>rt-thread</TargetName>
       <ToolsetNumber>0x4</ToolsetNumber>
       <ToolsetName>ARM-ADS</ToolsetName>
+      <uAC6>0</uAC6>
       <TargetOption>
         <TargetCommonOption>
           <Device>ES32F0334LT</Device>
           <Vendor>Eastsoft</Vendor>
-          <PackID>Eastsoft.ES32_DFP.1.0.1</PackID>
+          <PackID>Eastsoft.ES32_DFP.7.2350</PackID>
           <PackURL>http://www.essemi.com</PackURL>
           <Cpu>IRAM(0x20000000,0x00008000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
           <FlashUtilSpec></FlashUtilSpec>
@@ -182,6 +183,7 @@
             <hadXRAM>0</hadXRAM>
             <uocXRam>0</uocXRam>
             <RvdsVP>0</RvdsVP>
+            <RvdsMve>0</RvdsMve>
             <hadIRAM2>0</hadIRAM2>
             <hadIROM2>0</hadIROM2>
             <StupSel>8</StupSel>
@@ -322,6 +324,7 @@
             <uThumb>0</uThumb>
             <uSurpInc>0</uSurpInc>
             <uC99>1</uC99>
+            <uGnu>0</uGnu>
             <useXO>0</useXO>
             <v6Lang>1</v6Lang>
             <v6LangP>1</v6LangP>

bsp/essemi/es32f0654/.config

@@ -9,7 +9,7 @@
 CONFIG_RT_NAME_MAX=8
 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set
 # CONFIG_RT_USING_SMP is not set
-CONFIG_RT_ALIGN_SIZE=4
+CONFIG_RT_ALIGN_SIZE=8
 # CONFIG_RT_THREAD_PRIORITY_8 is not set
 CONFIG_RT_THREAD_PRIORITY_32=y
 # CONFIG_RT_THREAD_PRIORITY_256 is not set
@@ -64,7 +64,7 @@ CONFIG_RT_USING_DEVICE=y
 CONFIG_RT_USING_CONSOLE=y
 CONFIG_RT_CONSOLEBUF_SIZE=128
 CONFIG_RT_CONSOLE_DEVICE_NAME="uart2"
-CONFIG_RT_VER_NUM=0x40002
+CONFIG_RT_VER_NUM=0x40003
 # CONFIG_RT_USING_CPU_FFS is not set
 # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
 
@@ -114,19 +114,31 @@ CONFIG_RT_PIPE_BUFSZ=512
 CONFIG_RT_USING_SERIAL=y
 # CONFIG_RT_SERIAL_USING_DMA is not set
 CONFIG_RT_SERIAL_RB_BUFSZ=64
-# CONFIG_RT_USING_CAN is not set
-# CONFIG_RT_USING_HWTIMER is not set
+CONFIG_RT_USING_CAN=y
+# CONFIG_RT_CAN_USING_HDR is not set
+CONFIG_RT_USING_HWTIMER=y
 # CONFIG_RT_USING_CPUTIME is not set
-# CONFIG_RT_USING_I2C is not set
+CONFIG_RT_USING_I2C=y
+# CONFIG_RT_I2C_DEBUG is not set
+CONFIG_RT_USING_I2C_BITOPS=y
+# CONFIG_RT_I2C_BITOPS_DEBUG is not set
 CONFIG_RT_USING_PIN=y
-# CONFIG_RT_USING_ADC is not set
-# CONFIG_RT_USING_PWM is not set
+CONFIG_RT_USING_ADC=y
+# CONFIG_RT_USING_DAC is not set
+CONFIG_RT_USING_PWM=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_PM is not set
-# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_PM=y
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_ALARM is not set
+# CONFIG_RT_USING_SOFT_RTC is not set
 # CONFIG_RT_USING_SDIO is not set
-# CONFIG_RT_USING_SPI is not set
+CONFIG_RT_USING_SPI=y
+# CONFIG_RT_USING_QSPI is not set
+# CONFIG_RT_USING_SPI_MSD is not set
+# CONFIG_RT_USING_SFUD is not set
+# CONFIG_RT_USING_ENC28J60 is not set
+# CONFIG_RT_USING_SPI_WIFI is not set
 # CONFIG_RT_USING_WDT is not set
 # CONFIG_RT_USING_AUDIO is not set
 # CONFIG_RT_USING_SENSOR is not set
@@ -192,10 +204,15 @@ CONFIG_RT_USING_PIN=y
 #
 # IoT - internet of things
 #
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
 # CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
 # CONFIG_PKG_USING_WEBCLIENT is not set
 # CONFIG_PKG_USING_WEBNET is not set
 # CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
 # CONFIG_PKG_USING_WEBTERMINAL is not set
 # CONFIG_PKG_USING_CJSON is not set
 # CONFIG_PKG_USING_JSMN is not set
@@ -222,6 +239,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_COAP is not set
 # CONFIG_PKG_USING_NOPOLL is not set
 # CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
 # CONFIG_PKG_USING_PPP_DEVICE is not set
 # CONFIG_PKG_USING_AT_DEVICE is not set
 # CONFIG_PKG_USING_ATSRV_SOCKET is not set
@@ -234,8 +252,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_GAGENT_CLOUD is not set
 # CONFIG_PKG_USING_ALI_IOTKIT is not set
 # CONFIG_PKG_USING_AZURE is not set
-# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
 # CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
 # CONFIG_PKG_USING_NIMBLE is not set
 # CONFIG_PKG_USING_OTA_DOWNLOADER is not set
 # CONFIG_PKG_USING_IPMSG is not set
@@ -249,6 +269,16 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_DLT645 is not set
 # CONFIG_PKG_USING_QXWZ is not set
 # CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
 
 #
 # security packages
@@ -256,6 +286,8 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_MBEDTLS is not set
 # CONFIG_PKG_USING_libsodium is not set
 # CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
 
 #
 # language packages
@@ -272,6 +304,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_STEMWIN is not set
 # CONFIG_PKG_USING_WAVPLAYER is not set
 # CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_HELIX is not set
 
 #
 # tools packages
@@ -286,6 +319,13 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_ADBD is not set
 # CONFIG_PKG_USING_COREMARK is not set
 # CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
 
 #
 # system packages
@@ -296,6 +336,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LWEXT4 is not set
 # CONFIG_PKG_USING_PARTITION is not set
 # CONFIG_PKG_USING_FAL is not set
+# CONFIG_PKG_USING_FLASHDB is not set
 # CONFIG_PKG_USING_SQLITE is not set
 # CONFIG_PKG_USING_RTI is not set
 # CONFIG_PKG_USING_LITTLEVGL2RTT is not set
@@ -304,6 +345,15 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_LITTLEFS is not set
 # CONFIG_PKG_USING_THREAD_POOL is not set
 # CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_PPOOL is not set
 
 #
 # peripheral libraries and drivers
@@ -311,6 +361,7 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_SENSORS_DRIVERS is not set
 # CONFIG_PKG_USING_REALTEK_AMEBA is not set
 # CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
 # CONFIG_PKG_USING_STM32_SDIO is not set
 # CONFIG_PKG_USING_ICM20608 is not set
 # CONFIG_PKG_USING_U8G2 is not set
@@ -319,6 +370,10 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_SX12XX is not set
 # CONFIG_PKG_USING_SIGNAL_LED is not set
 # CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
 # CONFIG_PKG_USING_WM_LIBRARIES is not set
 # CONFIG_PKG_USING_KENDRYTE_SDK is not set
 # CONFIG_PKG_USING_INFRARED is not set
@@ -332,9 +387,27 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_I2C_TOOLS is not set
 # CONFIG_PKG_USING_NRF24L01 is not set
 # CONFIG_PKG_USING_TOUCH_DRIVERS is not set
-# CONFIG_PKG_USING_LCD_DRIVERS is not set
 # CONFIG_PKG_USING_MAX17048 is not set
 # CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
 
 #
 # miscellaneous packages
@@ -369,8 +442,14 @@ CONFIG_RT_USING_PIN=y
 # CONFIG_PKG_USING_ELAPACK is not set
 # CONFIG_PKG_USING_ARMv7M_DWT is not set
 # CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_TETRIS is not set
 # CONFIG_PKG_USING_ULAPACK is not set
 # CONFIG_PKG_USING_UKAL is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
 CONFIG_SOC_ES32F0654LT=y
 
 #
@@ -402,6 +481,11 @@ CONFIG_BSP_USING_UART2=y
 # CONFIG_BSP_USING_I2C0 is not set
 # CONFIG_BSP_USING_I2C1 is not set
 
+#
+# CAN Drivers
+#
+# CONFIG_BSP_USING_CAN is not set
+
 #
 # PWM Drivers
 #
@@ -414,6 +498,7 @@ CONFIG_BSP_USING_UART2=y
 # HWtimer Drivers
 #
 # CONFIG_BSP_USING_HWTIMER0 is not set
+# CONFIG_BSP_USING_HWTIMER1 is not set
 # CONFIG_BSP_USING_HWTIMER2 is not set
 # CONFIG_BSP_USING_HWTIMER3 is not set
 
@@ -440,3 +525,18 @@ CONFIG_BSP_USING_UART2=y
 #
 # Offboard Peripheral Drivers
 #
+
+#
+# Peripheral Drivers test example
+#
+# CONFIG_BSP_USING_EXAMPLE_ADC_VOL is not set
+# CONFIG_BSP_USING_EXAMPLE_HWTIMER is not set
+# CONFIG_BSP_USING_EXAMPLE_I2C is not set
+# CONFIG_BSP_USING_EXAMPLE_LED_BLINK is not set
+# CONFIG_BSP_USING_EXAMPLE_PIN_BEEP is not set
+# CONFIG_BSP_USING_EXAMPLE_PWM_LED is not set
+# CONFIG_BSP_USING_EXAMPLE_RTC is not set
+# CONFIG_BSP_USING_EXAMPLE_SPI is not set
+# CONFIG_BSP_USING_EXAMPLE_UART is not set
+# CONFIG_BSP_USING_EXAMPLE_CAN is not set
+# CONFIG_BSP_USING_EXAMPLE_PM is not set

bsp/essemi/es32f0654/README.md

@@ -90,6 +90,24 @@ msh >
 
 2. 输入`menuconfig`命令配置工程，配置好之后保存退出。
 
+    a）如果需要使用内核用例，先配置rt-thread内核，如图：
+
+    ![kernel_config](figures/k_conf.jpg)
+
+    然后配置内核用例，如图：
+
+    ![kernel_sample](figures/k_ex.jpg)
+
+    b）如果需要使用驱动用例：先使能驱动，如图：
+
+    ![driver_config](figures/d_conf.jpg)
+
+    然后配置驱动用例，如图：
+
+    ![driver_sample](figures/d_ex.jpg)
+
+    
+
 3. 输入`pkgs --update`命令更新软件包。
 
 4. 输入`scons --target=mdk5/iar` 命令重新生成工程。
@@ -98,7 +116,7 @@ msh >
 
 ## 4. 联系人信息
 
-- [wangyongquan](https://github.com/wangyq2018) 
+- [liuhongyan](https://gitee.com/liuhongyan98) 
 
 ## 5. 参考
 

bsp/essemi/es32f0654/drivers/Kconfig

@@ -148,4 +148,53 @@ menu "Hardware Drivers Config"
 
     endmenu
 
+
+    menu "Peripheral Drivers test example"
+
+        config BSP_USING_EXAMPLE_ADC_VOL
+            bool "BSP_USING_EXAMPLE_ADC_VOL"
+            default n
+        
+        config BSP_USING_EXAMPLE_HWTIMER
+            bool "BSP_USING_EXAMPLE_HWTIMER"
+            default n
+
+        config BSP_USING_EXAMPLE_I2C
+            bool "BSP_USING_EXAMPLE_I2C"
+            default n
+
+        config BSP_USING_EXAMPLE_LED_BLINK
+            bool "BSP_USING_EXAMPLE_LED_BLINK"
+            default y
+
+        config BSP_USING_EXAMPLE_PIN_BEEP
+            bool "BSP_USING_EXAMPLE_PIN_BEEP"
+            default y
+
+        config BSP_USING_EXAMPLE_PWM_LED
+            bool "BSP_USING_EXAMPLE_PWM_LED"
+            default n
+
+        config BSP_USING_EXAMPLE_RTC
+            bool "BSP_USING_EXAMPLE_RTC"
+            default n
+
+        config BSP_USING_EXAMPLE_SPI
+            bool "BSP_USING_EXAMPLE_SPI"
+            default n
+
+        config BSP_USING_EXAMPLE_UART
+            bool "BSP_USING_EXAMPLE_UART"
+            default y
+
+        config BSP_USING_EXAMPLE_CAN
+            bool "BSP_USING_EXAMPLE_CAN"
+            default n
+
+        config BSP_USING_EXAMPLE_PM
+            bool "BSP_USING_EXAMPLE_PM"
+            default n
+
+    endmenu
+
 endmenu

bsp/essemi/es32f0654/drivers/SConscript

@@ -2,6 +2,8 @@ from building import *
 
 cwd = GetCurrentDir()
 
+objs = []
+
 # add the general drivers.
 src = Split('''
 board.c
@@ -53,5 +55,47 @@ if GetDepend(['BSP_USING_ADC']):
 
 CPPPATH = [cwd]
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
+objs = objs + group
+
+src   = []
+cwd   = GetCurrentDir()
+include_path = [cwd]
+
+if GetDepend('BSP_USING_EXAMPLE_ADC_VOL'):
+    src += ['bsp_driver_example/adc_vol_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_HWTIMER'):
+    src += ['bsp_driver_example/hwtimer_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_I2C'):
+    src += ['bsp_driver_example/i2c_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_LED_BLINK'):
+    src += ['bsp_driver_example/led_blink_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_PIN_BEEP'):
+    src += ['bsp_driver_example/pin_beep_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_PWM_LED'):
+    src += ['bsp_driver_example/pwm_led_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_RTC'):
+    src += ['bsp_driver_example/rtc_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_UART'):
+    src += ['bsp_driver_example/uart_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_SPI'):
+    src += ['bsp_driver_example/spi_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_CAN'):
+    src += ['bsp_driver_example/can_sample.c']
+
+if GetDepend('BSP_USING_EXAMPLE_PM'):
+    src += ['bsp_driver_example/pm_sample.c']
+
+group = DefineGroup('bsp-drivers-test-samples', src, depend = [''], CPPPATH = include_path)
+
+objs = objs + group
+Return('objs')
 
-Return('group')

bsp/essemi/es32f0654/drivers/bsp_driver_example/.gitignore

@@ -0,0 +1,52 @@
+# Prerequisites
+*.d
+
+# Object files
+*.o
+*.ko
+*.obj
+*.elf
+
+# Linker output
+*.ilk
+*.map
+*.exp
+
+# Precompiled Headers
+*.gch
+*.pch
+
+# Libraries
+*.lib
+*.a
+*.la
+*.lo
+
+# Shared objects (inc. Windows DLLs)
+*.dll
+*.so
+*.so.*
+*.dylib
+
+# Executables
+*.exe
+*.out
+*.app
+*.i*86
+*.x86_64
+*.hex
+
+# Debug files
+*.dSYM/
+*.su
+*.idb
+*.pdb
+
+# Kernel Module Compile Results
+*.mod*
+*.cmd
+.tmp_versions/
+modules.order
+Module.symvers
+Mkfile.old
+dkms.conf

bsp/essemi/es32f0654/drivers/bsp_driver_example/README.md

@@ -0,0 +1,47 @@
+# 外设驱动测试用例
+
+## 1、介绍
+
+这个软件包包含一些外设设备操作的例程。
+
+### 1.1 例程说明
+
+| 文件             | 说明                            |
+| ---------------- | ------------------------------- |
+| adc_vol_sample.c       | 使用 ADC 设备转换电压数据 |
+| can_sample.c | 通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。 |
+| hwtimer_sample.c       | 使用 硬件定时器定时 |
+| i2c_sample.c     | 使用 i2c 设备进行读写 |
+| pm.c | 反复进入不同程度的睡眠。 |
+| led_blink_sample.c     |  使用 pin 设备控制 LED 闪烁 |
+| pin_beep_sample.c      | 使用 pin 设备控制蜂鸣器 |
+| pwm_led_sample.c       | 使用 pwm 设备控制 LED 的亮度 |
+| rtc_sample.c           | 使用 rtc 设备设置年月日时分秒信息 |
+| spi_sample.c     | 使用 spi 设备进行读写 |
+| uart_sample.c          | 使用 serial 设备中断接收及轮询发送模式收发数据 |
+
+### 1.2 依赖
+
+依赖设备管理模块提供的设备驱动。
+
+## 2、如何打开 外设驱动测试用例
+
+使用 外设驱动测试用例 需要在 RT-Thread 的menuconfig中选择它，具体路径如下：
+
+```
+Hardware Driver Config --->
+    Peripheral Driver test example--->
+```
+
+## 3、使用 外设驱动测试用例
+
+在打开 Peripheral Driver test example 后，当进行 BSP 编译时，选择的软件包相关源代码会被加入到 BSP 工程中进行编译。
+
+## 4、注意事项
+
+暂无。
+
+## 5、联系方式 & 感谢
+
+* 维护：[misonyo](https://github.com/misonyo)
+* 主页：https://github.com/RT-Thread-packages/peripheral-sample

bsp/essemi/es32f0654/drivers/bsp_driver_example/adc_vol_sample.c

@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-29     misonyo      first implementation.
+ */
+/*
+ * 程序清单： ADC 设备使用例程
+ * 例程导出了 adc_sample 命令到控制终端
+ * 命令调用格式：adc_sample
+ * 程序功能：通过 ADC 设备采样电压值并转换为数值。
+ *           示例代码参考电压为3.3V,转换位数为12位。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define ADC_DEV_NAME        "adc0"      /* ADC 设备名称 */
+#define ADC_DEV_CHANNEL     5           /* PA1 ADC 通道 */
+#define REFER_VOLTAGE       330         /* 参考电压 3.3V,数据精度乘以100保留2位小数*/
+#define CONVERT_BITS        (1 << 12)   /* 转换位数为12位 */
+
+static int adc_vol_sample(int argc, char *argv[])
+{
+    rt_adc_device_t adc_dev;
+    rt_uint32_t value, vol;
+    rt_err_t ret = RT_EOK;
+
+    /* 查找设备 */
+    adc_dev = (rt_adc_device_t)rt_device_find(ADC_DEV_NAME);
+    if (adc_dev == RT_NULL)
+    {
+        rt_kprintf("adc sample run failed! can't find %s device!\n", ADC_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    /* 使能设备 */
+    ret = rt_adc_enable(adc_dev, ADC_DEV_CHANNEL);
+
+    /* 读取采样值 */
+    value = rt_adc_read(adc_dev, ADC_DEV_CHANNEL);
+    rt_kprintf("the value is :%d \n", value);
+
+    /* 转换为对应电压值 */
+    vol = value * REFER_VOLTAGE / CONVERT_BITS;
+    rt_kprintf("the voltage is :%d.%02d \n", vol / 100, vol % 100);
+
+    /* 关闭通道 */
+    ret = rt_adc_disable(adc_dev, ADC_DEV_CHANNEL);
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(adc_vol_sample, adc voltage convert sample);

bsp/essemi/es32f0654/drivers/bsp_driver_example/can_sample.c

@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-06-25     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 CAN 设备使用例程
+ * 例程导出了 can_sample 命令到控制终端
+ * 命令调用格式：can_sample can2
+ * 命令解释：命令第二个参数是要使用的 CAN 设备名称，为空则使用默认的 CAN 设备
+ * 程序功能：通过 CAN 设备发送一帧，并创建一个线程接收数据然后打印输出。
+*/
+
+#include <rtthread.h>
+#include "rtdevice.h"
+
+#define CAN_DEV_NAME       "can"      /* CAN 设备名称 */
+
+static struct rt_semaphore rx_sem;     /* 用于接收消息的信号量 */
+static rt_device_t can_dev;            /* CAN 设备句柄 */
+
+/* 接收数据回调函数 */
+static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size)
+{
+    /* CAN 接收到数据后产生中断，调用此回调函数，然后发送接收信号量 */
+    rt_sem_release(&rx_sem);
+
+    return RT_EOK;
+}
+
+static void can_rx_thread(void *parameter)
+{
+    int i;
+    struct rt_can_msg rxmsg = {0};
+
+    /* 设置接收回调函数 */
+    rt_device_set_rx_indicate(can_dev, can_rx_call);
+
+#ifdef RT_CAN_USING_HDR
+    
+    rt_err_t res;
+    
+    struct rt_can_filter_item items[5] =
+    {
+        RT_CAN_FILTER_ITEM_INIT(0x100, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，hdr为-1，设置默认过滤表 */
+        RT_CAN_FILTER_ITEM_INIT(0x300, 0, 0, 0, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x300~0x3ff，hdr为-1 */
+        RT_CAN_FILTER_ITEM_INIT(0x211, 0, 0, 0, 0x7ff, RT_NULL, RT_NULL), /* std,match ID:0x211，hdr为-1 */
+        RT_CAN_FILTER_STD_INIT(0x486, RT_NULL, RT_NULL),                  /* std,match ID:0x486，hdr为-1 */
+        {0x555, 0, 0, 0, 0x7ff, 7,}                                       /* std,match ID:0x555，hdr为7，指定设置7号过滤表 */
+    };
+    struct rt_can_filter_config cfg = {5, 1, items}; /* 一共有5个过滤表 */
+    /* 设置硬件过滤表 */
+    res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg);
+    RT_ASSERT(res == RT_EOK);
+#endif
+
+    while (1)
+    {
+        /* hdr值为-1，表示直接从uselist链表读取数据 */
+        rxmsg.hdr = -1;
+        /* 阻塞等待接收信号量 */
+        rt_sem_take(&rx_sem, RT_WAITING_FOREVER);
+        /* 从CAN读取一帧数据 */
+        rt_device_read(can_dev, 0, &rxmsg, sizeof(rxmsg));
+        /* 打印数据ID及内容 */
+        rt_kprintf("ID:%x  ", rxmsg.id);
+        for (i = 0; i < 8; i++)
+        {
+            rt_kprintf("%2x ", rxmsg.data[i]);
+        }
+
+        rt_kprintf("\n");
+    }
+}
+
+int can_sample(int argc, char *argv[])
+{
+    struct rt_can_msg msg = {0};
+    rt_err_t res;
+    rt_size_t  size;
+    rt_thread_t thread;
+    char can_name[RT_NAME_MAX];
+    
+    if (argc == 2)
+    {
+        rt_strncpy(can_name, argv[1], RT_NAME_MAX);
+    }
+    else
+    {
+        rt_strncpy(can_name, CAN_DEV_NAME, RT_NAME_MAX);
+    }
+
+    can_dev = rt_device_find(can_name);
+    if (!can_dev)
+    {
+        rt_kprintf("find %s failed!\n", can_name);
+        return RT_ERROR;
+    }
+
+    /* 初始化CAN接收信号量 */
+    rt_sem_init(&rx_sem, "rx_sem", 0, RT_IPC_FLAG_FIFO);
+
+    /* 以中断接收及发送方式打开CAN设备 */
+    res = rt_device_open(can_dev, RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_INT_RX);
+    RT_ASSERT(res == RT_EOK);
+
+    thread = rt_thread_create("can_rx", can_rx_thread, RT_NULL, 1024, 25, 10);
+    if (thread != RT_NULL)
+    {
+        rt_thread_startup(thread);
+    }
+    else
+    {
+        rt_kprintf("create can_rx thread failed!\n");
+    }
+
+    msg.id = 0x78;              /* ID为0x78 */
+    msg.ide = RT_CAN_STDID;     /* 标准格式 */
+    msg.rtr = RT_CAN_DTR;       /* 数据帧 */
+    msg.len = 8;                /* 数据长度为8 */
+    /* 待发送的8字节数据 */
+    msg.data[0] = 0x00;
+    msg.data[1] = 0x11;
+    msg.data[2] = 0x22;
+    msg.data[3] = 0x33;
+    msg.data[4] = 0x44;
+    msg.data[5] = 0x55;
+    msg.data[6] = 0x66;
+    msg.data[7] = 0x77;
+    /* 发送一帧CAN数据 */
+    size = rt_device_write(can_dev, 0, &msg, sizeof(msg));
+    if (size == 0)
+    {
+        rt_kprintf("can dev write data failed!\n");
+    }
+    
+    return res;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(can_sample, can device sample);

bsp/essemi/es32f0654/drivers/bsp_driver_example/hwtimer_sample.c

@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-11-30     misonyo      first implementation.
+ */
+/*
+ * 程序清单：这是一个 hwtimer 设备使用例程
+ * 例程导出了 hwtimer_sample 命令到控制终端
+ * 命令调用格式：hwtimer_sample
+ * 程序功能：硬件定时器超时回调函数周期性的打印当前tick值，2次tick值之差换算为时间等同于定时时间值。
+*/
+
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define HWTIMER_DEV_NAME   "timer0"     /* 定时器名称 */
+
+/* 定时器超时回调函数 */
+static rt_err_t timeout_cb(rt_device_t dev, rt_size_t size)
+{
+    rt_kprintf("tick is :%d !\n", rt_tick_get());
+
+    return 0;
+}
+
+static int hwtimer_sample(int argc, char *argv[])
+{
+    rt_err_t ret = RT_EOK;
+    rt_hwtimerval_t timeout_s;      /* 定时器超时值 */
+    rt_device_t hw_dev = RT_NULL;   /* 定时器设备句柄 */
+    rt_hwtimer_mode_t mode;         /* 定时器模式 */
+
+    /* 查找定时器设备 */
+    hw_dev = rt_device_find(HWTIMER_DEV_NAME);
+    if (hw_dev == RT_NULL)
+    {
+        rt_kprintf("hwtimer sample run failed! can't find %s device!\n", HWTIMER_DEV_NAME);
+        return RT_ERROR;
+    }
+
+    /* 以读写方式打开设备 */
+    ret = rt_device_open(hw_dev, RT_DEVICE_OFLAG_RDWR);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("open %s device failed!\n", HWTIMER_DEV_NAME);
+        return ret;
+    }
+
+    /* 设置超时回调函数 */
+    rt_device_set_rx_indicate(hw_dev, timeout_cb);
+
+    /* 设置模式为周期性定时器 */
+    mode = HWTIMER_MODE_PERIOD;
+    ret = rt_device_control(hw_dev, HWTIMER_CTRL_MODE_SET, &mode);
+    if (ret != RT_EOK)
+    {
+        rt_kprintf("set mode failed! ret is :%d\n", ret);
+        return ret;
+    }
+
+    /* 设置定时器超时值为5s并启动定时器 */
+    timeout_s.sec = 5;      /* 秒 */
+    timeout_s.usec = 0;     /* 微秒 */
+
+    if (rt_device_write(hw_dev, 0, &timeout_s, sizeof(timeout_s)) != sizeof(timeout_s))
+    {
+        rt_kprintf("set timeout value failed\n");
+        return RT_ERROR;
+    }
+
+    /* 延时3500ms */
+    rt_thread_mdelay(3500);
+
+    /* 读取定时器当前值 */
+    rt_device_read(hw_dev, 0, &timeout_s, sizeof(timeout_s));
+    rt_kprintf("Read: Sec = %d, Usec = %d\n", timeout_s.sec, timeout_s.usec);
+
+    return ret;
+}
+/* 导出到 msh 命令列表中 */
+MSH_CMD_EXPORT(hwtimer_sample, hwtimer sample);