update libcpu: cortex-m0 fault handlers always enable.

libcpu/arm/cortex-m0/context_gcc.S

@@ -182,7 +182,6 @@ rt_hw_context_switch_to:
     MSR     MSP, R0
 
     /* enable interrupts at processor level */
-    CPSIE   F
     CPSIE   I
 
     /* never reach here! */

libcpu/arm/cortex-m0/context_iar.S

@@ -188,7 +188,6 @@ rt_hw_context_switch_to:
     MSR     msp, r0
 
     ; enable interrupts at processor level
-    CPSIE   F
     CPSIE   I
 
     ; never reach here!

libcpu/arm/cortex-m0/context_rvds.S

@@ -191,7 +191,6 @@ rt_hw_context_switch_to    PROC
     MSR     msp, r0
 
     ; enable interrupts at processor level
-    CPSIE   F
     CPSIE   I
 
     ; never reach here!