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@@ -0,0 +1,136 @@
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+/*
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+ * Copyright (c) 2006-2018, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Copyright(c) 2020, Du Huanpeng<548708880@qq.com>
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+ *
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+ */
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+
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+#include <rtthread.h>
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+#include <rtdevice.h>
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+#include <ls2k1000.h>
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+
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+#ifdef RT_USING_PWM
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+
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+#define PWM0_BASE (0xFFFFFFFFBFe02000)
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+#define PWM1_BASE (0xFFFFFFFFBFe02010)
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+#define PWM2_BASE (0xFFFFFFFFBFe02020)
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+#define PWM3_BASE (0xFFFFFFFFBFe02030)
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+
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+#define CTRL_EN (1UL<<0)
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+#define CTRL_OE (1UL<<3)
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+#define CTRL_SINGL (1UL<<4)
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+#define CTRL_INTE (1UL<<5)
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+#define CTRL_INT (1UL<<6)
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+#define CTRL_RST (1UL<<7)
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+#define CTRL_CAPTE (1UL<<8)
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+#define CTRL_INVERT (1UL<<9)
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+#define CTRL_DZONE (1UL<<10)
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+
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+struct loongson_pwm {
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+ rt_uint32_t __PAD0;
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+ rt_uint32_t low_buffer;
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+ rt_uint32_t full_buffer;
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+ rt_uint32_t ctrl;
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+};
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+
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+rt_err_t loongson_pwm_enable(struct rt_device_pwm *device, int channel)
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+{
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+ int **priv;
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+ struct loongson_pwm *chip;
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+ volatile rt_uint64_t *config0;
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+ rt_uint64_t m;
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+
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+ channel %= 4;
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+
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+ config0 = (void *)GEN_CONFIG0_REG;
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+ m = 1ULL << 12 << channel;
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+ *config0 |= m;
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+
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+ priv = device->parent.user_data;
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+ chip = (void *)priv[channel];
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+ chip->ctrl = CTRL_EN;
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+
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+ return RT_EOK;
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+}
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+
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+rt_err_t loongson_pwm_disable(struct rt_device_pwm *device, int channel)
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+{
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+ struct loongson_pwm **chip;
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+ rt_uint64_t m;
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+
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+ chip = device->parent.user_data;
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+ channel %= 4;
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+ chip[channel]->ctrl &= ~CTRL_EN;
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+
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+ return RT_EOK;
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+}
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+
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+rt_err_t loongson_pwm_set(struct rt_device_pwm *device, int channel, rt_uint32_t period, rt_uint32_t pulse)
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+{
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+ struct loongson_pwm *chip;
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+ rt_uint32_t **priv;
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+
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+ priv = device->parent.user_data;
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+ channel %= 4;
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+ chip = (void *)priv[channel];
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+
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+ chip->ctrl &= ~CTRL_EN;
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+ chip->full_buffer = period;
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+ chip->low_buffer = pulse;
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+ chip->ctrl |= CTRL_EN;
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t loongson_pwm_ioctl(struct rt_device_pwm *device, int cmd, void *arg)
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+{
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+ rt_err_t rc;
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+ struct rt_pwm_configuration *cfg;
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+
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+ cfg = (void *)arg;
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+
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+ switch (cmd) {
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+ case PWM_CMD_ENABLE:
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+ rc = loongson_pwm_enable(device, cfg->channel);
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+ break;
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+ case PWM_CMD_DISABLE:
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+ rc = loongson_pwm_disable(device, cfg->channel);
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+ break;
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+ case PWM_CMD_SET:
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+ rc = loongson_pwm_set(device, cfg->channel, cfg->period, cfg->pulse);
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+ break;
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+ case PWM_CMD_GET:
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+ rc = RT_ENOSYS;
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+ break;
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+ default:
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+ rc = RT_EINVAL;
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+ break;
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+ }
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+ return rc;
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+}
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+
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+struct rt_pwm_ops loongson_pwm_ops = {
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+ .control = loongson_pwm_ioctl,
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+};
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+
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+struct rt_device_pwm loongson_pwm = {
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+ .ops = &loongson_pwm_ops,
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+};
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+
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+int loongson_pwm_init(void)
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+{
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+ int rc = RT_EOK;
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+ static rt_uint32_t *priv[] = {
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+ (void *)PWM0_BASE,
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+ (void *)PWM1_BASE,
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+ (void *)PWM2_BASE,
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+ (void *)PWM3_BASE
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+ };
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+ rc = rt_device_pwm_register(&loongson_pwm, "pwm0", &loongson_pwm_ops, &priv);
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+ return rc;
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+}
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+INIT_DEVICE_EXPORT(loongson_pwm_init);
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+
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+#endif /*RT_USING_PWM*/
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