使用宏开关控制ASID开启

components/lwp/Kconfig

@@ -34,6 +34,10 @@ if RT_USING_LWP
         int "The maximum number of lwp thread id"
         default 64
 
+    config LWP_ENABLE_ASID
+        bool "The switch of ASID feature"
+        default n
+
     if ARCH_MM_MMU
         config RT_LWP_SHM_MAX_NR
             int "The maximum number of shared memory"

components/lwp/arch/aarch64/cortex-a/lwp_arch.c

@@ -74,15 +74,4 @@ int arch_expand_user_stack(void *addr)
     return ret;
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp)
-{
-    // TODO
-    return 0;
-}
-
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    // TODO
-}
-
 #endif

components/lwp/arch/aarch64/cortex-a/lwp_arch.h

@@ -41,9 +41,6 @@ rt_inline void icache_invalid_all(void)
     asm volatile ("ic ialluis\n\tisb sy":::"memory");
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
-
 #ifdef __cplusplus
 }
 #endif

components/lwp/arch/risc-v/rv64/lwp_arch.c

@@ -238,15 +238,4 @@ void lwp_set_thread_context(void *exit_addr, void *new_thread_stack, void *user_
      */
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp)
-{
-    // TODO
-    return 0;
-}
-
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    // TODO
-}
-
 #endif

components/lwp/arch/risc-v/rv64/lwp_arch.h

@@ -66,9 +66,6 @@ rt_inline void icache_invalid_all(void)
     //TODO:
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
-
 #ifdef __cplusplus
 }
 #endif

components/lwp/arch/x86/i386/lwp_arch.c

@@ -368,15 +368,4 @@ void lwp_signal_do_return(rt_hw_stack_frame_t *frame)
 }
 #endif /* RT_USING_SIGNALS */
 
-unsigned int arch_get_asid(struct rt_lwp *lwp)
-{
-    // TODO
-    return 0;
-}
-
-void arch_remove_asid(struct rt_lwp *lwp)
-{
-    // TODO
-}
-
 #endif  /* RT_USING_USERSPACE */

components/lwp/arch/x86/i386/lwp_arch.h

@@ -45,9 +45,6 @@ rt_inline unsigned long rt_hw_ffz(unsigned long x)
     return __builtin_ffs(~x) - 1;
 }
 
-unsigned int arch_get_asid(struct rt_lwp *lwp);
-void arch_remove_asid(struct rt_lwp *lwp);
-
 #ifdef __cplusplus
 }
 #endif

components/lwp/lwp_user_mm.c

@@ -35,6 +35,8 @@ void lwp_mmu_switch(struct rt_thread *thread)
 {
     struct rt_lwp *l = RT_NULL;
     void *pre_mmu_table = RT_NULL, *new_mmu_table = RT_NULL;
+    unsigned int asid = 0; 
+    pid_t pid = 0; 
 
     if (thread->lwp)
     {
@@ -49,8 +51,10 @@ void lwp_mmu_switch(struct rt_thread *thread)
     pre_mmu_table = rt_hw_mmu_tbl_get();
     if (pre_mmu_table != new_mmu_table)
     {
-        unsigned int asid = arch_get_asid(l);
-        pid_t pid = l ? l->pid : 0; 
+#ifdef LWP_ENABLE_ASID
+        asid = arch_get_asid(l);
+#endif
+        pid = l ? l->pid : 0; 
         rt_hw_mmu_switch(new_mmu_table, pid, asid);
     }
 }

libcpu/arm/cortex-a/start_gcc.S

@@ -176,7 +176,7 @@ bss_loop:
 #ifdef RT_USING_USERSPACE
     ldr r0, =MMUTable     /* vaddr    */
     add r0, r5            /* to paddr */
-    bl  rt_hw_mmu_switch_kernel
+    bl  rt_hw_mmu_switch
 #else
     bl rt_hw_mmu_init
 #endif
@@ -290,22 +290,6 @@ rt_hw_mmu_switch:
     isb
     mov pc, lr
 
-.global rt_hw_mmu_switch_kernel
-rt_hw_mmu_switch_kernel:
-    orr r0, #0x18
-    mcr p15, 0, r0, c2, c0, 0    /* ttbr0 */
-
-    /*  The nG bit of tlb entries of kernel is 0, 
-        so no need to update ASID, 
-        neither to flush TLB
-    */
-    mcr p15, 0, r0, c7, c5, 0    /* iciallu */
-    mcr p15, 0, r0, c7, c5, 6    /* bpiall */
-
-    dsb
-    isb
-    mov pc, lr
-
 .global rt_hw_mmu_tbl_get
 rt_hw_mmu_tbl_get:
     mrc p15, 0, r0, c2, c0, 0    /* ttbr0 */
@@ -647,7 +631,7 @@ rt_secondary_cpu_entry:
 after_enable_mmu_n:
     ldr     r0, =MMUTable
     add     r0, r5
-    bl      rt_hw_mmu_switch_kernel
+    bl      rt_hw_mmu_switch
 #endif
 
 #ifdef RT_USING_FPU