for stm32radio: modify mac address,set UART rx PIN: IPU,modify key.c

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@351 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/stm32_radio/board.c

@@ -1,371 +1,371 @@
-/*
- * File      : board.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2006-08-23     Bernard      first implementation
- */
-
-#include <rthw.h>
-#include <rtthread.h>
-
-#include "stm32f10x.h"
-#include "board.h"
-
-static void rt_hw_console_init(void);
-
-/**
- * @addtogroup STM32
- */
-
-/*@{*/
-
-/*******************************************************************************
- * Function Name  : RCC_Configuration
- * Description    : Configures the different system clocks.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void RCC_Configuration(void)
-{
-    ErrorStatus HSEStartUpStatus;
-
-    /* RCC system reset(for debug purpose) */
-    RCC_DeInit();
-
-    /* Enable HSE */
-    RCC_HSEConfig(RCC_HSE_ON);
-
-    /* Wait till HSE is ready */
-    HSEStartUpStatus = RCC_WaitForHSEStartUp();
-
-    if (HSEStartUpStatus == SUCCESS)
-    {
-        /* HCLK = SYSCLK */
-        RCC_HCLKConfig(RCC_SYSCLK_Div1);
-
-        /* PCLK2 = HCLK */
-        RCC_PCLK2Config(RCC_HCLK_Div1);
-        /* PCLK1 = HCLK/2 */
-        RCC_PCLK1Config(RCC_HCLK_Div2);
-
-        /* Flash 2 wait state */
-        FLASH_SetLatency(FLASH_Latency_2);
-        /* Enable Prefetch Buffer */
-        FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
-
-        /* PLLCLK = 8MHz * 9 = 72 MHz */
-        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
-
-        /* Enable PLL */
-        RCC_PLLCmd(ENABLE);
-
-        /* Wait till PLL is ready */
-        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
-
-        /* Select PLL as system clock source */
-        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
-        /* Wait till PLL is used as system clock source */
-        while (RCC_GetSYSCLKSource() != 0x08) ;
-    }
-}
-
-/*******************************************************************************
-* Function Name  : NVIC_Configuration
-* Description    : Configures Vector Table base location.
-* Input          : None
-* Output         : None
-* Return         : None
-*******************************************************************************/
-void NVIC_Configuration(void)
-{
-#ifdef  VECT_TAB_RAM
-    /* Set the Vector Table base location at 0x20000000 */
-    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
-#else  /* VECT_TAB_FLASH  */
-    /* Set the Vector Table base location at 0x08000000 */
-    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
-#endif
-
-    /*
-     * set priority group:
-     * 2 bits for pre-emption priority
-     * 2 bits for subpriority
-     */
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
-}
-
-/*******************************************************************************
- * Function Name  : SysTick_Configuration
- * Description    : Configures the SysTick for OS tick.
- * Input          : None
- * Output         : None
- * Return         : None
- *******************************************************************************/
-void  SysTick_Configuration(void)
-{
-    RCC_ClocksTypeDef  rcc_clocks;
-    rt_uint32_t         cnts;
-
-    RCC_GetClocksFreq(&rcc_clocks);
-
-    cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
-
-    SysTick_Config(cnts);
-    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
-}
-
-extern void rt_hw_interrupt_thread_switch(void);
-/**
- * This is the timer interrupt service routine.
- *
- */
-void rt_hw_timer_handler(void)
-{
-    /* enter interrupt */
-    rt_interrupt_enter();
-
-    rt_tick_increase();
-
-    /* leave interrupt */
-    rt_interrupt_leave();
-}
-
-/* NAND Flash */
-#include "fsmc_nand.h"
-
-/**
- * This function will initial STM32 Radio board.
- */
-extern void FSMC_SRAM_Init(void);
-void rt_hw_board_init()
-{
-    NAND_IDTypeDef NAND_ID;
-
-    /* Configure the system clocks */
-    RCC_Configuration();
-
-    /* DM9000A */
-    {
-        GPIO_InitTypeDef GPIO_InitStructure;
-
-        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE,ENABLE);
-
-        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-        GPIO_Init(GPIOE,&GPIO_InitStructure);
-        GPIO_SetBits(GPIOE,GPIO_Pin_5);
-    }
-
-    /* NVIC Configuration */
-    NVIC_Configuration();
-
-    /* Configure the SysTick */
-    SysTick_Configuration();
-
-    /* Console Initialization*/
-    rt_hw_console_init();
-
-    /* FSMC Initialization */
-    FSMC_NAND_Init();
-
-    /* NAND read ID command */
-    FSMC_NAND_ReadID(&NAND_ID);
-    rt_kprintf("\r\n\r\nRead the NAND ID:%02X%02X%02X%02X",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
-
-    /* SRAM init */
-    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
-    FSMC_SRAM_Init();
-
-    /* memtest */
-    {
-        unsigned char * p_extram = (unsigned char *)0x68000000;
-        unsigned int temp;
-
-        rt_kprintf("\r\nmem testing....");
-        for(temp=0; temp<0x80000; temp++)
-        {
-            *p_extram++ = (unsigned char)temp;
-        }
-
-        p_extram = (unsigned char *)0x68000000;
-        for(temp=0; temp<0x80000; temp++)
-        {
-            if( *p_extram++ != (unsigned char)temp )
-            {
-                rt_kprintf("\rmemtest fail @ %08X\r\nsystem halt!!!!!",(unsigned int)p_extram);
-                while(1);
-            }
-        }
-        rt_kprintf("\rmem test pass!!\r\n");
-    }/* memtest */
-
-    {
-        /* PC6 for SDCard Rst */
-        GPIO_InitTypeDef GPIO_InitStructure;
-
-        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
-        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-        GPIO_Init(GPIOC,&GPIO_InitStructure);
-        GPIO_SetBits(GPIOC,GPIO_Pin_6);
-    }
-
-    /* SPI1 config */
-    {
-        GPIO_InitTypeDef GPIO_InitStructure;
-        SPI_InitTypeDef SPI_InitStructure;
-
-        /* Enable SPI1 Periph clock */
-        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
-                               | RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
-                               ENABLE);
-
-        /* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
-        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
-        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-        GPIO_Init(GPIOA, &GPIO_InitStructure);
-
-        /*------------------------ SPI1 configuration ------------------------*/
-        SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
-        SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
-        SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
-        SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
-        SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
-        SPI_InitStructure.SPI_NSS  = SPI_NSS_Soft;
-        SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;/* 72M/64=1.125M */
-        SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
-        SPI_InitStructure.SPI_CRCPolynomial = 7;
-
-        SPI_I2S_DeInit(SPI1);
-        SPI_Init(SPI1, &SPI_InitStructure);
-
-        /* Enable SPI_MASTER */
-        SPI_Cmd(SPI1, ENABLE);
-        SPI_CalculateCRC(SPI1, DISABLE);
-    }
-
-}/* rt_hw_board_init */
-
-#if STM32_CONSOLE_USART == 1
-#define CONSOLE_RX_PIN	GPIO_Pin_9
-#define CONSOLE_TX_PIN	GPIO_Pin_10
-#define CONSOLE_GPIO	GPIOA
-#define CONSOLE_USART	USART1
-#elif STM32_CONSOLE_USART == 2
-
-#if defined(STM32_LD) || defined(STM32_MD)
-#define CONSOLE_RX_PIN	GPIO_Pin_6
-#define CONSOLE_TX_PIN	GPIO_Pin_5
-#define CONSOLE_GPIO	GPIOD
-#elif defined(STM32_HD)
-#define CONSOLE_RX_PIN	GPIO_Pin_3
-#define CONSOLE_TX_PIN	GPIO_Pin_2
-#define CONSOLE_GPIO	GPIOA
-#endif
-
-#define CONSOLE_USART	USART2
-#elif STM32_CONSOLE_USART == 2
-#define CONSOLE_RX_PIN	GPIO_Pin_11
-#define CONSOLE_TX_PIN	GPIO_Pin_10
-#define CONSOLE_GPIO	GPIOB
-#define CONSOLE_USART	USART3
-#endif
-
-/* init console to support rt_kprintf */
-static void rt_hw_console_init()
-{
-    /* Enable USART1 and GPIOA clocks */
-    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1
-                           | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC
-                           | RCC_APB2Periph_GPIOF, ENABLE);
-
-#if STM32_CONSOLE_USART == 0
-#else
-    /* GPIO configuration */
-    {
-        GPIO_InitTypeDef GPIO_InitStructure;
-
-        /* Configure USART1 Tx (PA.09) as alternate function push-pull */
-        GPIO_InitStructure.GPIO_Pin = CONSOLE_RX_PIN;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
-        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-        GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
-
-        /* Configure USART1 Rx (PA.10) as input floating */
-        GPIO_InitStructure.GPIO_Pin = CONSOLE_TX_PIN;
-        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-        GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
-    }
-
-    /* USART configuration */
-    {
-        USART_InitTypeDef USART_InitStructure;
-
-        /* USART configured as follow:
-            - BaudRate = 115200 baud
-            - Word Length = 8 Bits
-            - One Stop Bit
-            - No parity
-            - Hardware flow control disabled (RTS and CTS signals)
-            - Receive and transmit enabled
-            - USART Clock disabled
-            - USART CPOL: Clock is active low
-            - USART CPHA: Data is captured on the middle
-            - USART LastBit: The clock pulse of the last data bit is not output to
-              the SCLK pin
-        */
-        USART_InitStructure.USART_BaudRate = 115200;
-        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
-        USART_InitStructure.USART_StopBits = USART_StopBits_1;
-        USART_InitStructure.USART_Parity = USART_Parity_No;
-        USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-        USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
-        USART_Init(CONSOLE_USART, &USART_InitStructure);
-        /* Enable USART1 */
-        USART_Cmd(CONSOLE_USART, ENABLE);
-    }
-#endif
-}
-
-/* write one character to serial, must not trigger interrupt */
-static void rt_hw_console_putc(const char c)
-{
-    /*
-    	to be polite with serial console add a line feed
-    	to the carriage return character
-    */
-    if (c=='\n')rt_hw_console_putc('\r');
-
-    while (!(CONSOLE_USART->SR & USART_FLAG_TXE));
-    CONSOLE_USART->DR = (c & 0x1FF);
-}
-
-/**
- * This function is used by rt_kprintf to display a string on console.
- *
- * @param str the displayed string
- */
-void rt_hw_console_output(const char* str)
-{
-#if STM32_CONSOLE_USART == 0
-    /* no console */
-#else
-    while (*str)
-    {
-        rt_hw_console_putc (*str++);
-    }
-#endif
-}
-
-/*@}*/
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-23     Bernard      first implementation
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+
+#include "stm32f10x.h"
+#include "board.h"
+
+static void rt_hw_console_init(void);
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+/*******************************************************************************
+ * Function Name  : RCC_Configuration
+ * Description    : Configures the different system clocks.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void RCC_Configuration(void)
+{
+    ErrorStatus HSEStartUpStatus;
+
+    /* RCC system reset(for debug purpose) */
+    RCC_DeInit();
+
+    /* Enable HSE */
+    RCC_HSEConfig(RCC_HSE_ON);
+
+    /* Wait till HSE is ready */
+    HSEStartUpStatus = RCC_WaitForHSEStartUp();
+
+    if (HSEStartUpStatus == SUCCESS)
+    {
+        /* HCLK = SYSCLK */
+        RCC_HCLKConfig(RCC_SYSCLK_Div1);
+
+        /* PCLK2 = HCLK */
+        RCC_PCLK2Config(RCC_HCLK_Div1);
+        /* PCLK1 = HCLK/2 */
+        RCC_PCLK1Config(RCC_HCLK_Div2);
+
+        /* Flash 2 wait state */
+        FLASH_SetLatency(FLASH_Latency_2);
+        /* Enable Prefetch Buffer */
+        FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable);
+
+        /* PLLCLK = 8MHz * 9 = 72 MHz */
+        RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);
+
+        /* Enable PLL */
+        RCC_PLLCmd(ENABLE);
+
+        /* Wait till PLL is ready */
+        while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) ;
+
+        /* Select PLL as system clock source */
+        RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
+
+        /* Wait till PLL is used as system clock source */
+        while (RCC_GetSYSCLKSource() != 0x08) ;
+    }
+}
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+#ifdef  VECT_TAB_RAM
+    /* Set the Vector Table base location at 0x20000000 */
+    NVIC_SetVectorTable(NVIC_VectTab_RAM, 0x0);
+#else  /* VECT_TAB_FLASH  */
+    /* Set the Vector Table base location at 0x08000000 */
+    NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
+#endif
+
+    /*
+     * set priority group:
+     * 2 bits for pre-emption priority
+     * 2 bits for subpriority
+     */
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+    RCC_ClocksTypeDef  rcc_clocks;
+    rt_uint32_t         cnts;
+
+    RCC_GetClocksFreq(&rcc_clocks);
+
+    cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+
+    SysTick_Config(cnts);
+    SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+}
+
+extern void rt_hw_interrupt_thread_switch(void);
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void rt_hw_timer_handler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_tick_increase();
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+/* NAND Flash */
+#include "fsmc_nand.h"
+
+/**
+ * This function will initial STM32 Radio board.
+ */
+extern void FSMC_SRAM_Init(void);
+void rt_hw_board_init()
+{
+    NAND_IDTypeDef NAND_ID;
+
+    /* Configure the system clocks */
+    RCC_Configuration();
+
+    /* DM9000A */
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOE,ENABLE);
+
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_Init(GPIOE,&GPIO_InitStructure);
+        GPIO_SetBits(GPIOE,GPIO_Pin_5);
+    }
+
+    /* NVIC Configuration */
+    NVIC_Configuration();
+
+    /* Configure the SysTick */
+    SysTick_Configuration();
+
+    /* Console Initialization*/
+    rt_hw_console_init();
+
+    /* FSMC Initialization */
+    FSMC_NAND_Init();
+
+    /* NAND read ID command */
+    FSMC_NAND_ReadID(&NAND_ID);
+    rt_kprintf("\r\n\r\nRead the NAND ID:%02X%02X%02X%02X",NAND_ID.Maker_ID,NAND_ID.Device_ID,NAND_ID.Third_ID,NAND_ID.Fourth_ID);
+
+    /* SRAM init */
+    RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
+    FSMC_SRAM_Init();
+
+    /* memtest */
+    {
+        unsigned char * p_extram = (unsigned char *)0x68000000;
+        unsigned int temp;
+
+        rt_kprintf("\r\nmem testing....");
+        for(temp=0; temp<0x80000; temp++)
+        {
+            *p_extram++ = (unsigned char)temp;
+        }
+
+        p_extram = (unsigned char *)0x68000000;
+        for(temp=0; temp<0x80000; temp++)
+        {
+            if( *p_extram++ != (unsigned char)temp )
+            {
+                rt_kprintf("\rmemtest fail @ %08X\r\nsystem halt!!!!!",(unsigned int)p_extram);
+                while(1);
+            }
+        }
+        rt_kprintf("\rmem test pass!!\r\n");
+    }/* memtest */
+
+    {
+        /* PC6 for SDCard Rst */
+        GPIO_InitTypeDef GPIO_InitStructure;
+
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_Init(GPIOC,&GPIO_InitStructure);
+        GPIO_SetBits(GPIOC,GPIO_Pin_6);
+    }
+
+    /* SPI1 config */
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+        SPI_InitTypeDef SPI_InitStructure;
+
+        /* Enable SPI1 Periph clock */
+        RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA
+                               | RCC_APB2Periph_AFIO | RCC_APB2Periph_SPI1,
+                               ENABLE);
+
+        /* Configure SPI1 pins: PA5-SCK, PA6-MISO and PA7-MOSI */
+        GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+        /*------------------------ SPI1 configuration ------------------------*/
+        SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;//SPI_Direction_1Line_Tx;
+        SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+        SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+        SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+        SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+        SPI_InitStructure.SPI_NSS  = SPI_NSS_Soft;
+        SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;/* 72M/64=1.125M */
+        SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+        SPI_InitStructure.SPI_CRCPolynomial = 7;
+
+        SPI_I2S_DeInit(SPI1);
+        SPI_Init(SPI1, &SPI_InitStructure);
+
+        /* Enable SPI_MASTER */
+        SPI_Cmd(SPI1, ENABLE);
+        SPI_CalculateCRC(SPI1, DISABLE);
+    }
+
+}/* rt_hw_board_init */
+
+#if STM32_CONSOLE_USART == 1
+#define CONSOLE_RX_PIN	GPIO_Pin_9
+#define CONSOLE_TX_PIN	GPIO_Pin_10
+#define CONSOLE_GPIO	GPIOA
+#define CONSOLE_USART	USART1
+#elif STM32_CONSOLE_USART == 2
+
+#if defined(STM32_LD) || defined(STM32_MD)
+#define CONSOLE_RX_PIN	GPIO_Pin_6
+#define CONSOLE_TX_PIN	GPIO_Pin_5
+#define CONSOLE_GPIO	GPIOD
+#elif defined(STM32_HD)
+#define CONSOLE_RX_PIN	GPIO_Pin_3
+#define CONSOLE_TX_PIN	GPIO_Pin_2
+#define CONSOLE_GPIO	GPIOA
+#endif
+
+#define CONSOLE_USART	USART2
+#elif STM32_CONSOLE_USART == 2
+#define CONSOLE_RX_PIN	GPIO_Pin_11
+#define CONSOLE_TX_PIN	GPIO_Pin_10
+#define CONSOLE_GPIO	GPIOB
+#define CONSOLE_USART	USART3
+#endif
+
+/* init console to support rt_kprintf */
+static void rt_hw_console_init(void)
+{
+    /* Enable USART1 and GPIOA clocks */
+    RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1
+                           | RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOC
+                           | RCC_APB2Periph_GPIOF, ENABLE);
+
+#if STM32_CONSOLE_USART == 0
+#else
+    /* GPIO configuration */
+    {
+        GPIO_InitTypeDef GPIO_InitStructure;
+
+        /* Configure USART1 Tx (PA.09) as alternate function push-pull */
+        GPIO_InitStructure.GPIO_Pin = CONSOLE_RX_PIN;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+        GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+        GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
+
+        /* Configure USART1 Rx (PA.10) as input floating */
+        GPIO_InitStructure.GPIO_Pin = CONSOLE_TX_PIN;
+        GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
+        GPIO_Init(CONSOLE_GPIO, &GPIO_InitStructure);
+    }
+
+    /* USART configuration */
+    {
+        USART_InitTypeDef USART_InitStructure;
+
+        /* USART configured as follow:
+            - BaudRate = 115200 baud
+            - Word Length = 8 Bits
+            - One Stop Bit
+            - No parity
+            - Hardware flow control disabled (RTS and CTS signals)
+            - Receive and transmit enabled
+            - USART Clock disabled
+            - USART CPOL: Clock is active low
+            - USART CPHA: Data is captured on the middle
+            - USART LastBit: The clock pulse of the last data bit is not output to
+              the SCLK pin
+        */
+        USART_InitStructure.USART_BaudRate = 115200;
+        USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+        USART_InitStructure.USART_StopBits = USART_StopBits_1;
+        USART_InitStructure.USART_Parity = USART_Parity_No;
+        USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+        USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+        USART_Init(CONSOLE_USART, &USART_InitStructure);
+        /* Enable USART1 */
+        USART_Cmd(CONSOLE_USART, ENABLE);
+    }
+#endif
+}
+
+/* write one character to serial, must not trigger interrupt */
+static void rt_hw_console_putc(const char c)
+{
+    /*
+    	to be polite with serial console add a line feed
+    	to the carriage return character
+    */
+    if (c=='\n')rt_hw_console_putc('\r');
+
+    while (!(CONSOLE_USART->SR & USART_FLAG_TXE));
+    CONSOLE_USART->DR = (c & 0x1FF);
+}
+
+/**
+ * This function is used by rt_kprintf to display a string on console.
+ *
+ * @param str the displayed string
+ */
+void rt_hw_console_output(const char* str)
+{
+#if STM32_CONSOLE_USART == 0
+    /* no console */
+#else
+    while (*str)
+    {
+        rt_hw_console_putc (*str++);
+    }
+#endif
+}
+
+/*@}*/

bsp/stm32_radio/dm9000.c

@@ -6,7 +6,7 @@
 #include "stm32f10x.h"
 
 // #define DM9000_DEBUG		1
-#if DM9000_DEBUG
+#if ( DM9000_DEBUG == 1 )
 #define DM9000_TRACE	rt_kprintf
 #else
 #define DM9000_TRACE(...)
@@ -42,7 +42,7 @@ struct rt_dm9000_eth
     struct eth_device parent;
 
     enum DM9000_TYPE type;
-	enum DM9000_PHY_mode mode;
+    enum DM9000_PHY_mode mode;
 
     rt_uint8_t imr_all;
 
@@ -60,7 +60,7 @@ void rt_dm9000_isr(void);
 static void delay_ms(rt_uint32_t ms)
 {
     rt_uint32_t len;
-    for (;ms > 0; ms --)
+    for (; ms > 0; ms --)
         for (len = 0; len < 100; len++ );
 }
 
@@ -159,7 +159,7 @@ void rt_dm9000_isr()
     int_status = dm9000_io_read(DM9000_ISR);               /* Got ISR */
     dm9000_io_write(DM9000_ISR, int_status);    /* Clear ISR status */
 
-	DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
+    DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
 
     /* receive overflow */
     if (int_status & ISR_ROS)
@@ -175,8 +175,8 @@ void rt_dm9000_isr()
     /* Received the coming packet */
     if (int_status & ISR_PRS)
     {
-	    /* disable receive interrupt */
-	    dm9000_device.imr_all = IMR_PAR | IMR_PTM;
+        /* disable receive interrupt */
+        dm9000_device.imr_all = IMR_PAR | IMR_PTM;
 
         /* a frame has been received */
         eth_device_ready(&(dm9000_device.parent));
@@ -193,7 +193,7 @@ void rt_dm9000_isr()
             dm9000_device.packet_cnt --;
             if (dm9000_device.packet_cnt > 0)
             {
-            	DM9000_TRACE("dm9000 isr: tx second packet\n");
+                DM9000_TRACE("dm9000 isr: tx second packet\n");
 
                 /* transmit packet II */
                 /* Set TX length to DM9000 */
@@ -270,20 +270,20 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
     dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN);	/* RX enable */
     dm9000_io_write(DM9000_IMR, IMR_PAR);
 
-	if (dm9000_device.mode == DM9000_AUTO)
-	{
-	    while (!(phy_read(1) & 0x20))
-	    {
-	        /* autonegation complete bit */
-	        rt_thread_delay(10);
-	        i++;
-	        if (i == 10000)
-	        {
-	            rt_kprintf("could not establish link\n");
-	            return 0;
-	        }
-	    }
-	}
+    if (dm9000_device.mode == DM9000_AUTO)
+    {
+        while (!(phy_read(1) & 0x20))
+        {
+            /* autonegation complete bit */
+            rt_thread_delay(10);
+            i++;
+            if (i == 10000)
+            {
+                rt_kprintf("could not establish link\n");
+                return 0;
+            }
+        }
+    }
 
     /* see what we've got */
     lnk = phy_read(17) >> 12;
@@ -362,7 +362,7 @@ static rt_err_t rt_dm9000_control(rt_device_t dev, rt_uint8_t cmd, void *args)
 /* transmit packet. */
 rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
 {
-	DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
+    DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
 
     /* lock DM9000 device */
     rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
@@ -374,43 +374,43 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
     DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
 
     {
-		/* q traverses through linked list of pbuf's
-		 * This list MUST consist of a single packet ONLY */
-		struct pbuf *q;
-		rt_uint16_t pbuf_index = 0;
-		rt_uint8_t word[2], word_index = 0;
-
-		q = p;
-		/* Write data into dm9000a, two bytes at a time
-		 * Handling pbuf's with odd number of bytes correctly
-		 * No attempt to optimize for speed has been made */
-		while (q)
-		{
-			if (pbuf_index < q->len)
-			{
-				word[word_index++] = ((u8_t*)q->payload)[pbuf_index++];
-				if (word_index == 2)
-				{
-				    DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
-					word_index = 0;
-				}
-			}
-			else
-			{
-				q = q->next;
-				pbuf_index = 0;
-			}
-		}
-		/* One byte could still be unsent */
-		if (word_index == 1)
-		{
-		    DM9000_outw(DM9000_DATA_BASE, word[0]);
-		}
+        /* q traverses through linked list of pbuf's
+         * This list MUST consist of a single packet ONLY */
+        struct pbuf *q;
+        rt_uint16_t pbuf_index = 0;
+        rt_uint8_t word[2], word_index = 0;
+
+        q = p;
+        /* Write data into dm9000a, two bytes at a time
+         * Handling pbuf's with odd number of bytes correctly
+         * No attempt to optimize for speed has been made */
+        while (q)
+        {
+            if (pbuf_index < q->len)
+            {
+                word[word_index++] = ((u8_t*)q->payload)[pbuf_index++];
+                if (word_index == 2)
+                {
+                    DM9000_outw(DM9000_DATA_BASE, (word[1] << 8) | word[0]);
+                    word_index = 0;
+                }
+            }
+            else
+            {
+                q = q->next;
+                pbuf_index = 0;
+            }
+        }
+        /* One byte could still be unsent */
+        if (word_index == 1)
+        {
+            DM9000_outw(DM9000_DATA_BASE, word[0]);
+        }
     }
 
     if (dm9000_device.packet_cnt == 0)
     {
-    	DM9000_TRACE("dm9000 tx: first packet\n");
+        DM9000_TRACE("dm9000 tx: first packet\n");
 
         dm9000_device.packet_cnt ++;
         /* Set TX length to DM9000 */
@@ -422,7 +422,7 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
     }
     else
     {
-    	DM9000_TRACE("dm9000 tx: second packet\n");
+        DM9000_TRACE("dm9000 tx: second packet\n");
 
         dm9000_device.packet_cnt ++;
         dm9000_device.queue_packet_len = p->tot_len;
@@ -437,7 +437,7 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
     /* wait ack */
     rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
 
-	DM9000_TRACE("dm9000 tx done\n");
+    DM9000_TRACE("dm9000 tx done\n");
 
     return RT_EOK;
 }
@@ -464,7 +464,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
 
         if (rxbyte > 1)
         {
-			DM9000_TRACE("dm9000 rx: rx error, stop device\n");
+            DM9000_TRACE("dm9000 rx: rx error, stop device\n");
 
             dm9000_io_write(DM9000_RCR, 0x00);	/* Stop Device */
             dm9000_io_write(DM9000_ISR, 0x80);	/* Stop INT request */
@@ -476,7 +476,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
         rx_status = DM9000_inw(DM9000_DATA_BASE);
         rx_len = DM9000_inw(DM9000_DATA_BASE);
 
-		DM9000_TRACE("dm9000 rx: status %04x len %d\n", rx_status, rx_len);
+        DM9000_TRACE("dm9000 rx: status %04x len %d\n", rx_status, rx_len);
 
         /* allocate buffer */
         p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
@@ -497,13 +497,13 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
                     len -= 2;
                 }
             }
-			DM9000_TRACE("\n");
+            DM9000_TRACE("\n");
         }
         else
         {
             rt_uint16_t dummy;
 
-			DM9000_TRACE("dm9000 rx: no pbuf\n");
+            DM9000_TRACE("dm9000 rx: no pbuf\n");
 
             /* no pbuf, discard data from DM9000 */
             data = &dummy;
@@ -517,7 +517,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
         if ((rx_status & 0xbf00) || (rx_len < 0x40)
                 || (rx_len > DM9000_PKT_MAX))
         {
-			rt_kprintf("rx error: status %04x\n", rx_status);
+            rt_kprintf("rx error: status %04x\n", rx_status);
 
             if (rx_status & 0x100)
             {
@@ -548,7 +548,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
     else
     {
         /* restore receive interrupt */
-	    dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
+        dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
         dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
     }
 
@@ -609,7 +609,7 @@ static void GPIO_Configuration()
     EXTI_ClearITPendingBit(EXTI_Line4);
 }
 
-void rt_hw_dm9000_init()
+void rt_hw_dm9000_init(void)
 {
     RCC_Configuration();
     NVIC_Configuration();
@@ -619,9 +619,9 @@ void rt_hw_dm9000_init()
     rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
     dm9000_device.type  = TYPE_DM9000A;
-	dm9000_device.mode	= DM9000_AUTO;
-	dm9000_device.packet_cnt = 0;
-	dm9000_device.queue_packet_len = 0;
+    dm9000_device.mode	= DM9000_AUTO;
+    dm9000_device.packet_cnt = 0;
+    dm9000_device.queue_packet_len = 0;
 
     /*
      * SRAM Tx/Rx pointer automatically return to start address,
@@ -629,12 +629,14 @@ void rt_hw_dm9000_init()
      */
     dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
 
-    dm9000_device.dev_addr[0] = 0x01;
+    /* set mac address: (only for test) */
+    /* oui 00-60-6E DAVICOM SEMICONDUCTOR, INC.*/
+    dm9000_device.dev_addr[0] = 0x00;
     dm9000_device.dev_addr[1] = 0x60;
     dm9000_device.dev_addr[2] = 0x6E;
     dm9000_device.dev_addr[3] = 0x11;
-    dm9000_device.dev_addr[4] = 0x02;
-    dm9000_device.dev_addr[5] = 0x0F;
+    dm9000_device.dev_addr[4] = 0x22;
+    dm9000_device.dev_addr[5] = 0x33;
 
     dm9000_device.parent.parent.init       = rt_dm9000_init;
     dm9000_device.parent.parent.open       = rt_dm9000_open;

bsp/stm32_radio/key.c

@@ -47,16 +47,16 @@ static void key_thread_entry(void *parameter)
 
     while (1)
     {
-        next_delay = 20;
-		kbd_event.key = RTGUIK_UNKNOWN;
+        next_delay = 10;
+        kbd_event.key = RTGUIK_UNKNOWN;
 
         kbd_event.type = RTGUI_KEYDOWN;
         if ( key_enter_GETVALUE() == 0 )
         {
-            rt_thread_delay(next_delay);
+            rt_thread_delay( next_delay*4 );
             if (key_enter_GETVALUE() == 0)
             {
-            	/* HOME key */
+                /* HOME key */
                 rt_kprintf("key_home\n");
                 kbd_event.key  = RTGUIK_HOME;
             }
@@ -90,20 +90,20 @@ static void key_thread_entry(void *parameter)
             rt_kprintf("key_left\n");
             kbd_event.key  = RTGUIK_LEFT;
         }
-		
-		if (kbd_event.key != RTGUIK_UNKNOWN)
-		{
-	        /* post down event */
-	        rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
-
-			next_delay = 10;
-	        /* delay to post up event */
-	        rt_thread_delay(next_delay);
-
-	        /* post up event */
-	        kbd_event.type = RTGUI_KEYUP;
-	        rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
-		}
+
+        if (kbd_event.key != RTGUIK_UNKNOWN)
+        {
+            /* post down event */
+            rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
+
+            next_delay = 10;
+            /* delay to post up event */
+            rt_thread_delay(next_delay);
+
+            /* post up event */
+            kbd_event.type = RTGUI_KEYUP;
+            rtgui_server_post_event(&(kbd_event.parent), sizeof(kbd_event));
+        }
 
         /* wait next key press */
         rt_thread_delay(next_delay);