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+/*
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+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
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+ * Copyright 2016-2017 NXP
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+ *
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+ * Redistribution and use in source and binary forms, with or without modification,
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+ * are permitted provided that the following conditions are met:
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+ *
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+ * o Redistributions of source code must retain the above copyright notice, this list
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+ * of conditions and the following disclaimer.
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+ *
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+ * o Redistributions in binary form must reproduce the above copyright notice, this
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+ * list of conditions and the following disclaimer in the documentation and/or
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+ * other materials provided with the distribution.
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+ *
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+ * o Neither the name of the copyright holder nor the names of its
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+ * contributors may be used to endorse or promote products derived from this
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+ * software without specific prior written permission.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+#ifndef _FSL_PWM_H_
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+#define _FSL_PWM_H_
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+
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+#include "fsl_common.h"
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+
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+/*!
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+ * @addtogroup pwm_driver
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+ * @{
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+ */
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+
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+/*******************************************************************************
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+ * Definitions
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+ ******************************************************************************/
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+
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+/*! @name Driver version */
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+/*@{*/
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+#define FSL_PWM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
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+/*@}*/
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+
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+/*! @brief PWM clock source select. */
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+typedef enum _pwm_clock_source
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+{
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+ KPWM_PERIPHERAL_CLOCK = 0U, /*!< The Peripheral clock is used as the clock */
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+ KPWM_HIGH_FREQUENCY_CLOCK, /*!< High-frequency reference clock is used as the clock */
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+ KPWM_LOW_FREQUENCY_CLOCK /*!< Low-frequency reference clock(32KHz) is used as the clock */
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+} pwm_clock_source_t;
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+
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+/*!
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+ * @brief PWM FIFO water mark select.
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+ * Sets the data level at which the FIFO empty flag will be set
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+ */
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+typedef enum _pwm_fifo_water_mark
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+{
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+ KPWM_FIFO_WATERMARK_1 = 0U, /*!< FIFO empty flag is set when there are more than or equal to 1 empty slots */
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+ KPWM_FIFO_WATERMARK_2, /*!< FIFO empty flag is set when there are more than or equal to 2 empty slots */
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+ KPWM_FIFO_WATERMARK_3, /*!< FIFO empty flag is set when there are more than or equal to 3 empty slots */
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+ KPWM_FIFO_WATERMARK_4 /*!< FIFO empty flag is set when there are more than or equal to 4 empty slots */
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+} pwm_fifo_water_mark_t;
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+
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+/*!
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+ * @brief PWM byte data swap select.
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+ * It determines the byte ordering of the 16-bit data when it goes into the FIFO from the sample register.
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+ */
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+typedef enum _pwm_byte_data_swap
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+{
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+ KPWM_BYTE_NO_SWAP = 0U, /*!< byte ordering remains the same */
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+ KPWM_BYTE_SWAP /*!< byte ordering is reversed */
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+} pwm_byte_data_swap_t;
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+
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+/*! @brief PWM half-word data swap select. */
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+typedef enum _pwm_half_word_data_swap
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+{
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+ KPWM_HALF_WORD_NO_SWAP = 0U, /*!< Half word swapping does not take place */
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+ KPWM_HALF_WORD_SWAP /*!< Half word from write data bus are swapped */
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+} pwm_half_word_data_swap_t;
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+
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+/*! @brief PWM Output Configuration */
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+typedef enum _pwm_output_configuration
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+{
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+ KPWM_SET_AT_ROLLOVER_AND_CLEAR_AT_COMPARISON = 0U, /*!< Output pin is set at
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+ rollover and cleared at comparison */
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+ KPWM_CLEAR_AT_ROLLOVER_AND_SET_AT_COMPARISON, /*!< Output pin is
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+ cleared at rollover and set at comparison */
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+ KPWM_NO_CONFIGURE /*!< PWM output is disconnected */
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+} pwm_output_configuration_t;
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+
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+/*!
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+ * @brief PWM FIFO sample repeat
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+ * It determines the number of times each sample from the FIFO is to be used.
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+ */
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+typedef enum _pwm_sample_repeat
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+{
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+ KPMW_EACH_SAMPLE_ONCE = 0u, /*!< Use each sample once */
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+ KPWM_EACH_SAMPLE_TWICE, /*!< Use each sample twice */
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+ KPWM_EACH_SAMPLE_FOUR_TIMES, /*!< Use each sample four times */
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+ KPWM_EACH_SAMPLE_EIGHT_TIMES /*!< Use each sample eight times */
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+} pwm_sample_repeat_t;
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+
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+/*! @brief List of PWM interrupt options */
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+typedef enum _pwm_interrupt_enable
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+{
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+ KPWM_FIFO_EMPTY_INTERRUPT_ENABLE = (1U << 0), /*!< This bit controls the generation of the FIFO Empty interrupt. */
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+ KPWM_ROLLOVER_INTERRUPT_ENABLE = (1U << 1), /*!< This bit controls the generation of the Rollover interrupt. */
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+ KPWM_CMPARE_INTERRUPT_ENABLE = (1U << 2) /*!< This bit controls the generation of the Compare interrupt */
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+} pwm_interrupt_enable_t;
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+
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+/*! @brief List of PWM status flags */
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+typedef enum _pwm_status_flags
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+{
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+ KPWM_FIFO_EMPTY_FLAG = (1U << 3), /*!< This bit indicates the FIFO data level in comparison to the water
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+ level set by FWM field in the control register. */
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+ KPWM_ROLLOVER_FLAG = (1U << 4), /*!< This bit shows that a roll-over event has occurred. */
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+ KPWM_COMPARE_FLAG = (1U << 5), /*!< This bit shows that a compare event has occurred. */
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+ KPWM_FIFO_WRITE_ERROR_FLAG = (1U << 6) /*!< This bit shows that an attempt
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+ has been made to write FIFO when it is full. */
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+} pwm_status_flags_t;
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+
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+/*! @brief List of PWM FIFO available */
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+typedef enum _pwm_fifo_available
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+{
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+ KPWM_NO_DATA_IN_FIFO_FLAG = 0U, /*!< No data available */
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+ KPWM_ONE_WORD_IN_FIFO_FLAG, /*!< 1 word of data in FIFO */
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+ KPWM_TWO_WWRDS_IN_FIFO_FLAG, /*!< 2 word of data in FIFO */
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+ KPWM_THREE_WORDS_IN_FIFO_FLAG, /*!< 3 word of data in FIFO */
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+ KPWM_FOUR_WORDS_IN_FIFO_FLAG /*!< 4 word of data in FIFO */
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+} pwm_fifo_available_t;
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+
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+typedef struct _pwm_config
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+{
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+ bool enableStopMode; /*!< True: PWM continues to run in stop mode;
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+ False: PWM is paused in stop mode. */
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+ bool enableDozeMode; /*!< True: PWM continues to run in doze mode;
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+ False: PWM is paused in doze mode. */
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+ bool enableWaitMode; /*!< True: PWM continues to run in wait mode;
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+ False: PWM is paused in wait mode. */
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+ bool enableDebugMode; /*!< True: PWM continues to run in debug mode;
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+ False: PWM is paused in debug mode. */
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+ uint16_t prescale; /*!< Pre-scaler to divide down the clock
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+ The prescaler value is not more than 0xFFF. Divide by (value + 1)*/
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+ pwm_clock_source_t clockSource; /*!< Clock source for the counter */
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+ pwm_output_configuration_t outputConfig; /*!< Set the mode of the PWM output on the output pin. */
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+ pwm_fifo_water_mark_t fifoWater; /*!< Set the data level for FIFO. */
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+ pwm_sample_repeat_t sampleRepeat; /*!< The number of times each sample from the FIFO is to be used. */
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+ pwm_byte_data_swap_t byteSwap; /*!< It determines the byte ordering of the 16-bit data when it
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+ goes into the FIFO from the sample register. */
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+ pwm_half_word_data_swap_t halfWordSwap; /*!< It determines which half word data from the 32-bit
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+ IP Bus interface is written into the lower 16 bits of the sample register. */
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+} pwm_config_t;
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+
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+/*******************************************************************************
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+ * API
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+ ******************************************************************************/
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+
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+#if defined(__cplusplus)
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+extern "C" {
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+#endif
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+
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+/*!
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+ * @name Initialization and deinitialization
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+ * @{
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+ */
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+
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+/*!
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+ * @brief Ungates the PWM clock and configures the peripheral for basic operation.
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+ *
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+ * @note This API should be called at the beginning of the application using the PWM driver.
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+ *
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+ * @param base PWM peripheral base address
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+ * @param config Pointer to user's PWM config structure.
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+ *
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+ * @return kStatus_Success means success; else failed.
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+ */
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+status_t pwm_init(PWM_Type *base, const pwm_config_t *config);
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+
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+/*!
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+ * @brief Gate the PWM submodule clock
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+ *
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+ * @param base PWM peripheral base address
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+ */
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+void pwm_deinit(PWM_Type *base);
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+
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+/*!
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+ * @brief Fill in the PWM config struct with the default settings
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+ *
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+ * The default values are:
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+ * @code
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+ * config->enableStopMode = false;
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+ * config->enableDozeMode = false;
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+ * config->enableWaitMode = false;
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+ * config->enableDozeMode = false;
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+ * config->clockSource = kPWM_LowFrequencyClock;
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+ * config->prescale = 0U;
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+ * config->outputConfig = kPWM_SetAtRolloverAndClearAtcomparison;
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+ * config->fifoWater = kPWM_FIFOWaterMark_2;
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+ * config->sampleRepeat = kPWM_EachSampleOnce;
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+ * config->byteSwap = kPWM_ByteNoSwap;
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+ * config->halfWordSwap = kPWM_HalfWordNoSwap;
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+ * @endcode
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+ * @param config Pointer to user's PWM config structure.
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+ */
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+void pwm_get_default_config(pwm_config_t *config);
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+
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+/*! @}*/
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+
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+/*!
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+ * @name PWM start and stop.
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+ * @{
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+ */
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+
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+/*!
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+ * @brief Starts the PWM counter when the PWM is enabled.
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+ *
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+ * When the PWM is enabled, it begins a new period, the output pin is set to start a new period while
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+ * the prescaler and counter are released and counting begins.
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+ *
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+ * @param base PWM peripheral base address
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+ */
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+static inline void pwm_start_timer(PWM_Type *base)
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+{
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+ base->PWMCR |= PWM_PWMCR_EN_MASK;
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+}
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+
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+/*!
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+ * @brief Stops the PWM counter when the pwm is disabled.
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+ *
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+ * @param base PWM peripheral base address
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+ */
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+static inline void pwm_stop_timer(PWM_Type *base)
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+{
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+ base->PWMCR &= ~(PWM_PWMCR_EN_MASK);
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+}
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+
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+/*! @}*/
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+
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+/*!
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+ * @brief Sofrware reset.
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+ *
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+ * PWM is reset when this bit is set to 1. It is a self clearing bit.
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+ * Setting this bit resets all the registers to their reset values except for the STOPEN,
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+ * DOZEN, WAITEN, and DBGEN bits in this control register.
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+ *
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+ * @param base PWM peripheral base address
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+ */
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+static inline void pwm_software_reset(PWM_Type *base)
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+{
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+ base->PWMCR |= PWM_PWMCR_SWR_MASK;
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+}
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+
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+/*!
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+ * @name Interrupt Interface
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+ * @{
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+ */
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+
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+/*!
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+ * @brief Enables the selected PWM interrupts.
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+ *
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+ * @param base PWM peripheral base address
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+ * @param mask The interrupts to enable. This is a logical OR of members of the
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+ * enumeration ::pwm_interrupt_enable_t
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+ */
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+static inline void pwm_enable_interrupts(PWM_Type *base, uint32_t mask)
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+{
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+ base->PWMIR |= (mask & (PWM_PWMIR_FIE_MASK | PWM_PWMIR_RIE_MASK | PWM_PWMIR_CIE_MASK));
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+}
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+
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+/*!
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+ * @brief Disables the selected PWM interrupts.
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+ *
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+ * @param base PWM peripheral base address
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+ * @param mask The interrupts to disable. This is a logical OR of members of the
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+ * enumeration ::pwm_interrupt_enable_t
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+ */
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+static inline void pwm_disable_interrupts(PWM_Type *base, uint32_t mask)
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+{
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+ base->PWMIR &= ~(mask & (PWM_PWMIR_FIE_MASK | PWM_PWMIR_RIE_MASK | PWM_PWMIR_CIE_MASK));
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+}
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+
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+/*!
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+ * @brief Gets the enabled PWM interrupts.
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+ *
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+ * @param base PWM peripheral base address
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+ *
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+ * @return The enabled interrupts. This is the logical OR of members of the
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+ * enumeration ::pwm_interrupt_enable_t
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+ */
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+static inline uint32_t pwm_get_enabled_interrupts(PWM_Type *base)
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+{
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+ return base->PWMIR;
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+}
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+
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+/*! @}*/
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+
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+/*!
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+ * @name Status Interface
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+ * @{
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+ */
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+
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+/*!
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+ * @brief Gets the PWM status flags.
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+ *
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+ * @param base PWM peripheral base address
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+ *
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+ * @return The status flags. This is the logical OR of members of the
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+ * enumeration ::pwm_status_flags_t
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+ */
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+static inline uint32_t pwm_get_status_flags(PWM_Type *base)
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+{
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+ uint32_t statusFlags = base->PWMSR;
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+
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+ statusFlags &= (PWM_PWMSR_FE_MASK | PWM_PWMSR_ROV_MASK | PWM_PWMSR_CMP_MASK | PWM_PWMSR_FWE_MASK);
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+ return statusFlags;
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+}
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+
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+/*!
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+ * @brief Clears the PWM status flags.
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+ *
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+ * @param base PWM peripheral base address
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+ * @param mask The status flags to clear. This is a logical OR of members of the
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+ * enumeration ::pwm_status_flags_t
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+ */
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+static inline void pwm_clear_status_flags(PWM_Type *base, uint32_t mask)
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+{
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+ base->PWMSR = (mask & (PWM_PWMSR_FE_MASK | PWM_PWMSR_ROV_MASK |
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+ PWM_PWMSR_CMP_MASK | PWM_PWMSR_FWE_MASK));
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+}
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+
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+/*!
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+ * @brief Gets the PWM FIFO available.
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+ *
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+ * @param base PWM peripheral base address
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+ *
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+ * @return The status flags. This is the logical OR of members of the
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+ * enumeration ::pwm_fifo_available_t
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+ */
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+static inline uint32_t pwm_get_fifo_available(PWM_Type *base)
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+{
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+ return (base->PWMSR & PWM_PWMSR_FIFOAV_MASK);
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+}
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+
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+/*! @}*/
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+
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+/*!
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+ * @name Sample Interface
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+ * @{
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+ */
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+
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+/*!
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+ * @brief Sets the PWM sample value.
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+ *
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+ * @param base PWM peripheral base address
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+ * @param mask The sample value. This is the input to the 4x16 FIFO. The value in this register denotes
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+ * the value of the sample being currently used.
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+ */
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+static inline void pwm_set_sample_value(PWM_Type *base, uint32_t value)
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+{
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+ base->PWMSAR = (value & PWM_PWMSAR_SAMPLE_MASK);
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+}
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+
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+/*!
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+ * @brief Gets the PWM sample value.
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+ *
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+ * @param base PWM peripheral base address
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+ *
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+ * @return The sample value. It can be read only when the PWM is enable.
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+ */
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+static inline uint32_t pwm_get_sample_value(PWM_Type *base)
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+{
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+ return base->PWMSAR;
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+}
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+
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+/*! @}*/
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+
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+/*!
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+ * @brief Sets the PWM period value.
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+ *
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+ * @param base PWM peripheral base address
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+ * @param mask The period value. The PWM period register (PWM_PWMPR) determines the period of
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+ * the PWM output signal.
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+ * Writing 0xFFFF to this register will achieve the same result as writing 0xFFFE.
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+ * PWMO (Hz) = PCLK(Hz) / (period +2)
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+ */
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+static inline void pwm_set_period_value(PWM_Type *base, uint32_t value)
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+{
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+ base->PWMPR = (value & PWM_PWMPR_PERIOD_MASK);
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+}
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+
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+/*!
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+ * @brief Gets the PWM period value.
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+ *
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+ * @param base PWM peripheral base address
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+ *
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+ * @return The period value. The PWM period register (PWM_PWMPR) determines the period of
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+ * the PWM output signal.
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+ */
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+static inline uint32_t pwm_get_period_value(PWM_Type *base)
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+{
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+ return (base->PWMPR & PWM_PWMPR_PERIOD_MASK);
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+}
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+
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+/*!
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+ * @brief Gets the PWM counter value.
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+ *
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+ * @param base PWM peripheral base address
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+ *
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+ * @return The counter value. The current count value.
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+ */
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+static inline uint32_t pwm_get_counter_value(PWM_Type *base)
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+{
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+ return (base->PWMCNR & PWM_PWMCNR_COUNT_MASK);
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+}
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+
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+#if defined(__cplusplus)
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+}
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+#endif
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+
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+/*! @}*/
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+
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+#endif /* _FSL_PWM_H_ */
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@lin12345678