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+/*
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+ * Copyright (c) 2006-2018, RT-Thread Development Team
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+ *
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+ * SPDX-License-Identifier: Apache-2.0
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2018-12-22 zylx first version
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+ */
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+
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+#ifndef __QSPI_CONFIG_H__
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+#define __QSPI_CONFIG_H__
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+
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+#include <rtthread.h>
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+
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+#ifdef BSP_USING_QSPI
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+#ifndef QSPI_BUS_CONFIG
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+#define QSPI_BUS_CONFIG \
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+ { \
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+ .Instance = QUADSPI, \
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+ .Init.FifoThreshold = 4, \
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+ .Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE, \
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+ .Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE, \
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+ }
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+#endif /* QSPI_BUS_CONFIG */
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+#endif /* BSP_USING_QSPI */
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+
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+#ifdef BSP_QSPI_USING_DMA
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+#ifndef QSPI_DMA_CONFIG
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+#define QSPI_DMA_CONFIG \
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+ { \
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+ .Instance = DMA1_Channel5, \
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+ .Init.Request = DMA_REQUEST_5, \
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+ .Init.Direction = DMA_PERIPH_TO_MEMORY, \
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+ .Init.PeriphInc = DMA_PINC_DISABLE, \
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+ .Init.MemInc = DMA_MINC_ENABLE, \
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+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE, \
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+ .Init.MemDataAlignment = DMA_MDATAALIGN_BYTE, \
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+ .Init.Mode = DMA_NORMAL, \
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+ .Init.Priority = DMA_PRIORITY_LOW \
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+ }
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+#endif /* QSPI_DMA_CONFIG */
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+#endif /* BSP_QSPI_USING_DMA */
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+
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+#define QSPI_DMA_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE()
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+#define QSPI_IRQn QUADSPI_IRQn
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+#define QSPI_DMA_IRQn DMA1_Channel5_IRQn
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+#define QSPI_IRQHandler QUADSPI_IRQHandler
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+#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
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+
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+#endif /* __QSPI_CONFIG_H__ */
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SummerGift