[riscv] add tls switch

components/lwp/arch/risc-v/rv64/lwp_gcc.S

@@ -216,8 +216,15 @@ get_vfp:
     li a0, 0
     ret
 
+.globl rt_cpu_get_thread_idr
+rt_cpu_get_thread_idr:
+    mv a0, tp 
+    ret
+
 .global lwp_set_thread_area
 lwp_set_thread_area:
+.globl rt_cpu_set_thread_idr
+rt_cpu_set_thread_idr:
     mv tp, a0
     ret
 

libcpu/risc-v/t-head/c906/interrupt_gcc.S

@@ -8,6 +8,7 @@
  * 2018/10/02     Bernard      The first version
  * 2018/12/27     Jesven       Add SMP schedule
  * 2021/02/02     lizhirui     Add userspace support
+ * 2021/12/24     JasonHu      Add user setting save/restore
  */
 
 #define __ASSEMBLY__
@@ -138,6 +139,12 @@ copy_context_loop:
     addi s0, s0, -0xfe
     beqz s0, lwp_signal_quit
 
+#ifdef RT_USING_USERSPACE
+    /* save setting when syscall enter */
+    call  rt_thread_self
+    call  lwp_user_setting_save
+#endif
+
     mv a0, sp
     OPEN_INTERRUPT
     call syscall_handler
@@ -155,6 +162,15 @@ syscall_exit:
         dont_ret_to_user:
     #endif
 
+#ifdef RT_USING_USERSPACE
+    /* restore setting when syscall exit */
+    call  rt_thread_self
+    call  lwp_user_setting_restore
+
+    /* after restore the reg `tp`, need modify context */
+    STORE tp, 4 * REGBYTES(sp)
+#endif
+
     //restore context
     RESTORE_ALL
     sret

libcpu/risc-v/t-head/c906/stackframe.h

@@ -51,6 +51,14 @@
 #define FPU_CTX_F31_OFF  248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
 #endif /* ENABLE_FPU */
 
+/**
+ * The register `tp` always save/restore when context switch,
+ * we call `lwp_user_setting_save` when syscall enter,
+ * call `lwp_user_setting_restore` when syscall exit 
+ * and modify context stack after `lwp_user_setting_restore` called
+ * so that the `tp` can be the correct thread area value.
+ */
+
 .macro SAVE_ALL
 
 #ifdef ENABLE_FPU
@@ -69,7 +77,7 @@
     STORE x1, 0 * REGBYTES(sp)
 
     STORE x3,   3 * REGBYTES(sp)
-    STORE x4,   4 * REGBYTES(sp)
+    STORE x4,   4 * REGBYTES(sp) /* save tp */
     STORE x5,   5 * REGBYTES(sp)
     STORE x6,   6 * REGBYTES(sp)
     STORE x7,   7 * REGBYTES(sp)
@@ -160,38 +168,38 @@
 
     li  t0, SSTATUS_FS
     csrs sstatus, t0
-    fld f0, FPU_CTX_F0_OFF(t2)
-    fld f1, FPU_CTX_F1_OFF(t2)
-    fld f2, FPU_CTX_F2_OFF(t2)
-    fld f3, FPU_CTX_F3_OFF(t2)
-    fld f4, FPU_CTX_F4_OFF(t2)
-    fld f5, FPU_CTX_F5_OFF(t2)
-    fld f6, FPU_CTX_F6_OFF(t2)
-    fld f7, FPU_CTX_F7_OFF(t2)
-    fld f8, FPU_CTX_F8_OFF(t2)
-    fld f9, FPU_CTX_F9_OFF(t2)
-    fld f10,FPU_CTX_F10_OFF(t2)
-    fld f11,FPU_CTX_F11_OFF(t2)
-    fld f12,FPU_CTX_F12_OFF(t2)
-    fld f13,FPU_CTX_F13_OFF(t2)
-    fld f14,FPU_CTX_F14_OFF(t2)
-    fld f15,FPU_CTX_F15_OFF(t2)
-    fld f16,FPU_CTX_F16_OFF(t2)
-    fld f17,FPU_CTX_F17_OFF(t2)
-    fld f18,FPU_CTX_F18_OFF(t2)
-    fld f19,FPU_CTX_F19_OFF(t2)
-    fld f20,FPU_CTX_F20_OFF(t2)
-    fld f21,FPU_CTX_F21_OFF(t2)
-    fld f22,FPU_CTX_F22_OFF(t2)
-    fld f23,FPU_CTX_F23_OFF(t2)
-    fld f24,FPU_CTX_F24_OFF(t2)
-    fld f25,FPU_CTX_F25_OFF(t2)
-    fld f26,FPU_CTX_F26_OFF(t2)
-    fld f27,FPU_CTX_F27_OFF(t2)
-    fld f28,FPU_CTX_F28_OFF(t2)
-    fld f29,FPU_CTX_F29_OFF(t2)
-    fld f30,FPU_CTX_F30_OFF(t2)
-    fld f31,FPU_CTX_F31_OFF(t2)
+    fld f0,  FPU_CTX_F0_OFF(t2)
+    fld f1,  FPU_CTX_F1_OFF(t2)
+    fld f2,  FPU_CTX_F2_OFF(t2)
+    fld f3,  FPU_CTX_F3_OFF(t2)
+    fld f4,  FPU_CTX_F4_OFF(t2)
+    fld f5,  FPU_CTX_F5_OFF(t2)
+    fld f6,  FPU_CTX_F6_OFF(t2)
+    fld f7,  FPU_CTX_F7_OFF(t2)
+    fld f8,  FPU_CTX_F8_OFF(t2)
+    fld f9,  FPU_CTX_F9_OFF(t2)
+    fld f10, FPU_CTX_F10_OFF(t2)
+    fld f11, FPU_CTX_F11_OFF(t2)
+    fld f12, FPU_CTX_F12_OFF(t2)
+    fld f13, FPU_CTX_F13_OFF(t2)
+    fld f14, FPU_CTX_F14_OFF(t2)
+    fld f15, FPU_CTX_F15_OFF(t2)
+    fld f16, FPU_CTX_F16_OFF(t2)
+    fld f17, FPU_CTX_F17_OFF(t2)
+    fld f18, FPU_CTX_F18_OFF(t2)
+    fld f19, FPU_CTX_F19_OFF(t2)
+    fld f20, FPU_CTX_F20_OFF(t2)
+    fld f21, FPU_CTX_F21_OFF(t2)
+    fld f22, FPU_CTX_F22_OFF(t2)
+    fld f23, FPU_CTX_F23_OFF(t2)
+    fld f24, FPU_CTX_F24_OFF(t2)
+    fld f25, FPU_CTX_F25_OFF(t2)
+    fld f26, FPU_CTX_F26_OFF(t2)
+    fld f27, FPU_CTX_F27_OFF(t2)
+    fld f28, FPU_CTX_F28_OFF(t2)
+    fld f29, FPU_CTX_F29_OFF(t2)
+    fld f30, FPU_CTX_F30_OFF(t2)
+    fld f31, FPU_CTX_F31_OFF(t2)
 
     /* clr FS domain */
     csrc sstatus, t0
@@ -214,7 +222,7 @@
     LOAD x1,   1 * REGBYTES(sp)
 
     LOAD x3,   3 * REGBYTES(sp)
-    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x4,   4 * REGBYTES(sp) /* restore tp */
     LOAD x5,   5 * REGBYTES(sp)
     LOAD x6,   6 * REGBYTES(sp)
     LOAD x7,   7 * REGBYTES(sp)

libcpu/risc-v/virt64/interrupt_gcc.S

@@ -8,6 +8,7 @@
  * 2018/10/02     Bernard      The first version
  * 2018/12/27     Jesven       Add SMP schedule
  * 2021/02/02     lizhirui     Add userspace support
+ * 2021/12/24     JasonHu      Add user setting save/restore
  */
 
 #define __ASSEMBLY__
@@ -138,6 +139,12 @@ copy_context_loop:
     addi s0, s0, -0xfe
     beqz s0, lwp_signal_quit
 
+#ifdef RT_USING_USERSPACE
+    /* save setting when syscall enter */
+    call  rt_thread_self
+    call  lwp_user_setting_save
+#endif
+
     mv a0, sp
     OPEN_INTERRUPT
     call syscall_handler
@@ -149,21 +156,31 @@ syscall_exit:
     #if defined(RT_USING_USERSPACE) && defined(RT_USING_SIGNALS)
         LOAD s0, 2 * REGBYTES(sp)
         andi s0, s0, 0x100
-        bnez s0, error
+        bnez s0, dont_ret_to_user
         li s0, 0
         j ret_to_user
+        dont_ret_to_user:
     #endif
 
+#ifdef RT_USING_USERSPACE
+    /* restore setting when syscall exit */
+    call  rt_thread_self
+    call  lwp_user_setting_restore
+
+    /* after restore the reg `tp`, need modify context */
+    STORE tp, 4 * REGBYTES(sp)
+#endif
+
     //restore context
     RESTORE_ALL
     sret
 
 .global rt_hw_interrupt_enable
 rt_hw_interrupt_enable:
-    csrs sstatus, a0
+    csrs sstatus, a0    /* restore to old csr */
     jr ra
 
 .global rt_hw_interrupt_disable
 rt_hw_interrupt_disable:
-    csrrci a0, sstatus, 2
+    csrrci a0, sstatus, 2   /* clear SIE */
     jr ra

libcpu/risc-v/virt64/stackframe.h

@@ -51,6 +51,14 @@
 #define FPU_CTX_F31_OFF  248 /* offsetof(fpu_context_t, fpustatus.f[31]) - offsetof(fpu_context_t, fpustatus.f[0]) */
 #endif /* ENABLE_FPU */
 
+/**
+ * The register `tp` always save/restore when context switch,
+ * we call `lwp_user_setting_save` when syscall enter,
+ * call `lwp_user_setting_restore` when syscall exit 
+ * and modify context stack after `lwp_user_setting_restore` called
+ * so that the `tp` can be the correct thread area value.
+ */
+
 .macro SAVE_ALL
 
 #ifdef ENABLE_FPU
@@ -69,7 +77,7 @@
     STORE x1, 0 * REGBYTES(sp)
 
     STORE x3,   3 * REGBYTES(sp)
-    STORE x4,   4 * REGBYTES(sp)
+    STORE x4,   4 * REGBYTES(sp) /* save tp */
     STORE x5,   5 * REGBYTES(sp)
     STORE x6,   6 * REGBYTES(sp)
     STORE x7,   7 * REGBYTES(sp)
@@ -160,38 +168,38 @@
 
     li  t0, SSTATUS_FS
     csrs sstatus, t0
-    fld f0, FPU_CTX_F0_OFF(t2)
-    fld f1, FPU_CTX_F1_OFF(t2)
-    fld f2, FPU_CTX_F2_OFF(t2)
-    fld f3, FPU_CTX_F3_OFF(t2)
-    fld f4, FPU_CTX_F4_OFF(t2)
-    fld f5, FPU_CTX_F5_OFF(t2)
-    fld f6, FPU_CTX_F6_OFF(t2)
-    fld f7, FPU_CTX_F7_OFF(t2)
-    fld f8, FPU_CTX_F8_OFF(t2)
-    fld f9, FPU_CTX_F9_OFF(t2)
-    fld f10,FPU_CTX_F10_OFF(t2)
-    fld f11,FPU_CTX_F11_OFF(t2)
-    fld f12,FPU_CTX_F12_OFF(t2)
-    fld f13,FPU_CTX_F13_OFF(t2)
-    fld f14,FPU_CTX_F14_OFF(t2)
-    fld f15,FPU_CTX_F15_OFF(t2)
-    fld f16,FPU_CTX_F16_OFF(t2)
-    fld f17,FPU_CTX_F17_OFF(t2)
-    fld f18,FPU_CTX_F18_OFF(t2)
-    fld f19,FPU_CTX_F19_OFF(t2)
-    fld f20,FPU_CTX_F20_OFF(t2)
-    fld f21,FPU_CTX_F21_OFF(t2)
-    fld f22,FPU_CTX_F22_OFF(t2)
-    fld f23,FPU_CTX_F23_OFF(t2)
-    fld f24,FPU_CTX_F24_OFF(t2)
-    fld f25,FPU_CTX_F25_OFF(t2)
-    fld f26,FPU_CTX_F26_OFF(t2)
-    fld f27,FPU_CTX_F27_OFF(t2)
-    fld f28,FPU_CTX_F28_OFF(t2)
-    fld f29,FPU_CTX_F29_OFF(t2)
-    fld f30,FPU_CTX_F30_OFF(t2)
-    fld f31,FPU_CTX_F31_OFF(t2)
+    fld f0,  FPU_CTX_F0_OFF(t2)
+    fld f1,  FPU_CTX_F1_OFF(t2)
+    fld f2,  FPU_CTX_F2_OFF(t2)
+    fld f3,  FPU_CTX_F3_OFF(t2)
+    fld f4,  FPU_CTX_F4_OFF(t2)
+    fld f5,  FPU_CTX_F5_OFF(t2)
+    fld f6,  FPU_CTX_F6_OFF(t2)
+    fld f7,  FPU_CTX_F7_OFF(t2)
+    fld f8,  FPU_CTX_F8_OFF(t2)
+    fld f9,  FPU_CTX_F9_OFF(t2)
+    fld f10, FPU_CTX_F10_OFF(t2)
+    fld f11, FPU_CTX_F11_OFF(t2)
+    fld f12, FPU_CTX_F12_OFF(t2)
+    fld f13, FPU_CTX_F13_OFF(t2)
+    fld f14, FPU_CTX_F14_OFF(t2)
+    fld f15, FPU_CTX_F15_OFF(t2)
+    fld f16, FPU_CTX_F16_OFF(t2)
+    fld f17, FPU_CTX_F17_OFF(t2)
+    fld f18, FPU_CTX_F18_OFF(t2)
+    fld f19, FPU_CTX_F19_OFF(t2)
+    fld f20, FPU_CTX_F20_OFF(t2)
+    fld f21, FPU_CTX_F21_OFF(t2)
+    fld f22, FPU_CTX_F22_OFF(t2)
+    fld f23, FPU_CTX_F23_OFF(t2)
+    fld f24, FPU_CTX_F24_OFF(t2)
+    fld f25, FPU_CTX_F25_OFF(t2)
+    fld f26, FPU_CTX_F26_OFF(t2)
+    fld f27, FPU_CTX_F27_OFF(t2)
+    fld f28, FPU_CTX_F28_OFF(t2)
+    fld f29, FPU_CTX_F29_OFF(t2)
+    fld f30, FPU_CTX_F30_OFF(t2)
+    fld f31, FPU_CTX_F31_OFF(t2)
 
     /* clr FS domain */
     csrc sstatus, t0
@@ -214,7 +222,7 @@
     LOAD x1,   1 * REGBYTES(sp)
 
     LOAD x3,   3 * REGBYTES(sp)
-    LOAD x4,   4 * REGBYTES(sp)
+    LOAD x4,   4 * REGBYTES(sp) /* restore tp */
     LOAD x5,   5 * REGBYTES(sp)
     LOAD x6,   6 * REGBYTES(sp)
     LOAD x7,   7 * REGBYTES(sp)