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@@ -5,6 +5,13 @@
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#include "lwipopts.h"
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#include "lwipopts.h"
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#include "stm32f10x.h"
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#include "stm32f10x.h"
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+// #define DM9000_DEBUG 1
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+#if DM9000_DEBUG
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+#define DM9000_TRACE rt_kprintf
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+#else
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+#define DM9000_TRACE(...)
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+#endif
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+
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/*
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/*
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* DM9000 interrupt line is connected to PF7
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* DM9000 interrupt line is connected to PF7
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*/
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*/
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@@ -35,10 +42,15 @@ struct rt_dm9000_eth
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struct eth_device parent;
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struct eth_device parent;
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enum DM9000_TYPE type;
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enum DM9000_TYPE type;
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+ enum DM9000_PHY_mode mode;
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+
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rt_uint8_t imr_all;
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rt_uint8_t imr_all;
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+ rt_uint8_t packet_cnt; /* packet I or II */
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+ rt_uint16_t queue_packet_len; /* queued packet (packet II) */
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+
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/* interface address info. */
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/* interface address info. */
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- rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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+ rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */
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};
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};
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static struct rt_dm9000_eth dm9000_device;
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static struct rt_dm9000_eth dm9000_device;
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static struct rt_semaphore sem_ack, sem_lock;
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static struct rt_semaphore sem_ack, sem_lock;
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@@ -135,8 +147,8 @@ rt_inline void phy_mode_set(rt_uint32_t media_mode)
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/* interrupt service routine */
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/* interrupt service routine */
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void rt_dm9000_isr()
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void rt_dm9000_isr()
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{
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{
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- rt_uint32_t int_status;
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- rt_uint32_t last_io;
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+ rt_uint16_t int_status;
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+ rt_uint16_t last_io;
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last_io = DM9000_IO;
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last_io = DM9000_IO;
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@@ -147,6 +159,8 @@ void rt_dm9000_isr()
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int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
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int_status = dm9000_io_read(DM9000_ISR); /* Got ISR */
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dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
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dm9000_io_write(DM9000_ISR, int_status); /* Clear ISR status */
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+ DM9000_TRACE("dm9000 isr: int status %04x\n", int_status);
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+
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/* receive overflow */
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/* receive overflow */
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if (int_status & ISR_ROS)
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if (int_status & ISR_ROS)
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{
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{
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@@ -177,6 +191,20 @@ void rt_dm9000_isr()
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if (tx_status & (NSR_TX2END | NSR_TX1END))
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if (tx_status & (NSR_TX2END | NSR_TX1END))
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{
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{
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+ dm9000_device.packet_cnt --;
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+ if (dm9000_device.packet_cnt > 0)
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+ {
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+ DM9000_TRACE("dm9000 isr: tx second packet\n");
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+
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+ /* transmit packet II */
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+ /* Set TX length to DM9000 */
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+ dm9000_io_write(DM9000_TXPLL, dm9000_device.queue_packet_len & 0xff);
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+ dm9000_io_write(DM9000_TXPLH, (dm9000_device.queue_packet_len >> 8) & 0xff);
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+
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+ /* Issue TX polling command */
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+ dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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+ }
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+
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/* One packet sent complete */
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/* One packet sent complete */
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rt_sem_release(&sem_ack);
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rt_sem_release(&sem_ack);
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}
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}
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@@ -197,7 +225,7 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
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/* RESET device */
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/* RESET device */
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dm9000_io_write(DM9000_NCR, NCR_RST);
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dm9000_io_write(DM9000_NCR, NCR_RST);
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- delay_ms(100); /* delay 1ms */
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+ delay_ms(1000); /* delay 1ms */
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/* identfy DM9000 */
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/* identfy DM9000 */
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value = dm9000_io_read(DM9000_VIDL);
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value = dm9000_io_read(DM9000_VIDL);
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@@ -215,11 +243,11 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
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/* GPIO0 on pre-activate PHY */
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/* GPIO0 on pre-activate PHY */
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dm9000_io_write(DM9000_GPR, 0x00); /* REG_1F bit0 activate phyxcer */
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dm9000_io_write(DM9000_GPR, 0x00); /* REG_1F bit0 activate phyxcer */
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- // dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
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- // dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
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+ dm9000_io_write(DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
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+ dm9000_io_write(DM9000_GPR, 0x00); /* Enable PHY */
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/* Set PHY */
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/* Set PHY */
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- phy_mode_set(DM9000_AUTO);
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+ phy_mode_set(dm9000_device.mode);
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/* Program operating register */
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/* Program operating register */
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dm9000_io_write(DM9000_NCR, 0x0); /* only intern phy supported by now */
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dm9000_io_write(DM9000_NCR, 0x0); /* only intern phy supported by now */
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@@ -230,7 +258,7 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
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dm9000_io_write(DM9000_SMCR, 0); /* Special Mode */
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dm9000_io_write(DM9000_SMCR, 0); /* Special Mode */
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dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
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dm9000_io_write(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
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dm9000_io_write(DM9000_ISR, 0x0f); /* Clear interrupt status */
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dm9000_io_write(DM9000_ISR, 0x0f); /* Clear interrupt status */
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- dm9000_io_write(DM9000_TCR2, 0x90); /* Switch LED to mode 1 and one packet mode */
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+ dm9000_io_write(DM9000_TCR2, 0x80); /* Switch LED to mode 1 */
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/* set mac address */
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/* set mac address */
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for (i = 0, oft = 0x10; i < 6; i++, oft++)
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for (i = 0, oft = 0x10; i < 6; i++, oft++)
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@@ -243,18 +271,20 @@ static rt_err_t rt_dm9000_init(rt_device_t dev)
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dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
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dm9000_io_write(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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dm9000_io_write(DM9000_IMR, IMR_PAR);
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- i = 0;
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- while (!(phy_read(1) & 0x20))
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- {
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- /* autonegation complete bit */
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- delay_ms(100);
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- i++;
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- if (i == 100000)
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- {
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- rt_kprintf("could not establish link\n");
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- return 0;
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- }
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- }
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+ if (dm9000_device.mode == DM9000_AUTO)
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+ {
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+ while (!(phy_read(1) & 0x20))
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+ {
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+ /* autonegation complete bit */
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+ delay_ms(10);
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+ i++;
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+ if (i == 10000)
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+ {
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+ rt_kprintf("could not establish link\n");
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+ return 0;
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+ }
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+ }
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+ }
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/* see what we've got */
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/* see what we've got */
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lnk = phy_read(17) >> 12;
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lnk = phy_read(17) >> 12;
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@@ -337,9 +367,19 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
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rt_int32_t len;
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rt_int32_t len;
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rt_uint16_t* ptr;
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rt_uint16_t* ptr;
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+#if DM9000_DEBUG
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+ rt_uint8_t* dump_ptr;
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+ rt_uint32_t cnt = 0;
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+#endif
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+
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+ DM9000_TRACE("dm9000 tx: %d\n", p->tot_len);
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+
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/* lock DM9000 device */
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/* lock DM9000 device */
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
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+ /* disable dm9000a interrupt */
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+ dm9000_io_write(DM9000_IMR, IMR_PAR);
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+
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/* Move data to DM9000 TX RAM */
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/* Move data to DM9000 TX RAM */
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DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
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DM9000_outb(DM9000_IO_BASE, DM9000_MWCMD);
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@@ -348,27 +388,56 @@ rt_err_t rt_dm9000_tx( rt_device_t dev, struct pbuf* p)
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len = q->len;
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len = q->len;
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ptr = q->payload;
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ptr = q->payload;
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+#if DM9000_DEBUG
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+ dump_ptr = q->payload;
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+#endif
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+
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/* use 16bit mode to write data to DM9000 RAM */
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/* use 16bit mode to write data to DM9000 RAM */
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while (len > 0)
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while (len > 0)
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{
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{
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DM9000_outw(DM9000_DATA_BASE, *ptr);
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DM9000_outw(DM9000_DATA_BASE, *ptr);
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ptr ++;
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ptr ++;
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len -= 2;
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len -= 2;
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+
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+#ifdef DM9000_DEBUG
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+ DM9000_TRACE("%02x ", *dump_ptr++);
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+ if (++cnt % 16 == 0) DM9000_TRACE("\n");
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+#endif
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}
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}
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}
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}
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+ DM9000_TRACE("\n");
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+
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+ if (dm9000_device.packet_cnt == 0)
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+ {
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+ DM9000_TRACE("dm9000 tx: first packet\n");
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+
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+ dm9000_device.packet_cnt ++;
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+ /* Set TX length to DM9000 */
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+ dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
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+ dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
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+
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+ /* Issue TX polling command */
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+ dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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+ }
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+ else
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+ {
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+ DM9000_TRACE("dm9000 tx: second packet\n");
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- /* Set TX length to DM9000 */
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- dm9000_io_write(DM9000_TXPLL, p->tot_len & 0xff);
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- dm9000_io_write(DM9000_TXPLH, (p->tot_len >> 8) & 0xff);
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+ dm9000_device.packet_cnt ++;
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+ dm9000_device.queue_packet_len = p->tot_len;
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+ }
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- /* Issue TX polling command */
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- dm9000_io_write(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
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+ /* enable dm9000a interrupt */
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+ dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
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/* unlock DM9000 device */
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/* unlock DM9000 device */
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rt_sem_release(&sem_lock);
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rt_sem_release(&sem_lock);
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+ /* wait ack */
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rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
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rt_sem_take(&sem_ack, RT_WAITING_FOREVER);
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+ DM9000_TRACE("dm9000 tx done\n");
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+
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return RT_EOK;
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return RT_EOK;
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}
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}
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@@ -378,6 +447,11 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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struct pbuf* p;
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struct pbuf* p;
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rt_uint32_t rxbyte;
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rt_uint32_t rxbyte;
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+#if DM9000_DEBUG
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+ rt_uint8_t* dump_ptr;
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+ rt_uint32_t cnt = 0;
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+#endif
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+
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/* init p pointer */
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/* init p pointer */
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p = RT_NULL;
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p = RT_NULL;
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@@ -394,6 +468,8 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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if (rxbyte > 1)
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if (rxbyte > 1)
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{
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{
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+ DM9000_TRACE("dm9000 rx: rx error, stop device\n");
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+
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dm9000_io_write(DM9000_RCR, 0x00); /* Stop Device */
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dm9000_io_write(DM9000_RCR, 0x00); /* Stop Device */
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dm9000_io_write(DM9000_ISR, 0x80); /* Stop INT request */
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dm9000_io_write(DM9000_ISR, 0x80); /* Stop INT request */
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}
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}
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@@ -404,6 +480,8 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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rx_status = DM9000_inw(DM9000_DATA_BASE);
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rx_status = DM9000_inw(DM9000_DATA_BASE);
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rx_len = DM9000_inw(DM9000_DATA_BASE);
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rx_len = DM9000_inw(DM9000_DATA_BASE);
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+ DM9000_TRACE("dm9000 rx: status %04x len %d\n", rx_status, rx_len);
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+
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/* allocate buffer */
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/* allocate buffer */
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p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
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p = pbuf_alloc(PBUF_LINK, rx_len, PBUF_RAM);
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if (p != RT_NULL)
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if (p != RT_NULL)
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@@ -416,18 +494,30 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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data = (rt_uint16_t*)q->payload;
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data = (rt_uint16_t*)q->payload;
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len = q->len;
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len = q->len;
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+#if DM9000_DEBUG
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+ dump_ptr = q->payload;
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+#endif
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+
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while (len > 0)
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while (len > 0)
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{
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{
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*data = DM9000_inw(DM9000_DATA_BASE);
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*data = DM9000_inw(DM9000_DATA_BASE);
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data ++;
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data ++;
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len -= 2;
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len -= 2;
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+
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+#if DM9000_DEBUG
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+ DM9000_TRACE("%02x ", *dump_ptr++);
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+ if (++cnt % 16 == 0) DM9000_TRACE("\n");
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+#endif
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}
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}
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}
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}
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+ DM9000_TRACE("\n");
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}
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}
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else
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else
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{
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{
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rt_uint16_t dummy;
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rt_uint16_t dummy;
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+ DM9000_TRACE("dm9000 rx: no pbuf\n");
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+
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/* no pbuf, discard data from DM9000 */
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/* no pbuf, discard data from DM9000 */
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data = &dummy;
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data = &dummy;
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while (rx_len)
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while (rx_len)
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@@ -469,7 +559,7 @@ struct pbuf *rt_dm9000_rx(rt_device_t dev)
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else
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else
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{
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{
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/* restore interrupt */
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/* restore interrupt */
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- dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
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+ // dm9000_io_write(DM9000_IMR, dm9000_device.imr_all);
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}
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}
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/* unlock DM9000 device */
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/* unlock DM9000 device */
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@@ -539,15 +629,19 @@ void rt_hw_dm9000_init()
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NVIC_Configuration();
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NVIC_Configuration();
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GPIO_Configuration();
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GPIO_Configuration();
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- rt_sem_init(&sem_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO);
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+ rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
|
|
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
|
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
|
|
|
|
|
|
- dm9000_device.type = TYPE_DM9000A;
|
|
|
|
|
|
+ dm9000_device.type = TYPE_DM9000A;
|
|
|
|
+ dm9000_device.mode = DM9000_AUTO;
|
|
|
|
+ dm9000_device.packet_cnt = 0;
|
|
|
|
+ dm9000_device.queue_packet_len = 0;
|
|
|
|
+
|
|
/*
|
|
/*
|
|
* SRAM Tx/Rx pointer automatically return to start address,
|
|
* SRAM Tx/Rx pointer automatically return to start address,
|
|
* Packet Transmitted, Packet Received
|
|
* Packet Transmitted, Packet Received
|
|
*/
|
|
*/
|
|
- dm9000_device.imr_all = IMR_PAR | IMR_ROOM | IMR_ROM | IMR_PTM | IMR_PRM;
|
|
|
|
|
|
+ dm9000_device.imr_all = IMR_PAR | IMR_PTM | IMR_PRM;
|
|
|
|
|
|
dm9000_device.dev_addr[0] = 0x01;
|
|
dm9000_device.dev_addr[0] = 0x01;
|
|
dm9000_device.dev_addr[1] = 0x60;
|
|
dm9000_device.dev_addr[1] = 0x60;
|
|
@@ -606,3 +700,4 @@ void rx(void)
|
|
FINSH_FUNCTION_EXPORT(rx, notify packet rx);
|
|
FINSH_FUNCTION_EXPORT(rx, notify packet rx);
|
|
|
|
|
|
#endif
|
|
#endif
|
|
|
|
+
|