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@@ -0,0 +1,795 @@
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+/*
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+ * File : drv_sdio.c
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+ * This file is part of RT-Thread RTOS
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+ * COPYRIGHT (C) 2017, RT-Thread Development Team
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License as published by
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+ * the Free Software Foundation; either version 2 of the License, or
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+ * (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program; if not, write to the Free Software Foundation, Inc.,
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+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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+ *
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+ * Change Logs:
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+ * Date Author Notes
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+ * 2018-02-08 RT-Thread the first version
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+ */
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+#include <rtthread.h>
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+#include <rthw.h>
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+#include <rtdevice.h>
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+#include <string.h>
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+
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+#include "drv_sdio.h"
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+#include "interrupt.h"
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+#include "mmu.h"
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+#include "drv_gpio.h"
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+#include "drv_clock.h"
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+
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+#define DBG_ENABLE
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+#define DBG_SECTION_NAME "[MMC]"
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+// #define DBG_LEVEL DBG_LOG
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+// #define DBG_LEVEL DBG_INFO
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+#define DBG_LEVEL DBG_WARNING
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+// #define DBG_LEVEL DBG_ERROR
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+#define DBG_COLOR
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+#include <rtdbg.h>
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+
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+#ifdef RT_USING_SDIO
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+#define CONFIG_MMC_USE_DMA
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+#define DMA_ALIGN (32U)
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+
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+struct mmc_xfe_des
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+{
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+ rt_uint32_t size; /* block size */
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+ rt_uint32_t num; /* block num */
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+ rt_uint8_t *buff; /* buff addr */
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+ rt_uint32_t flag; /* write or read or stream */
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+#define MMC_DATA_WRITE (1 << 0)
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+#define MMC_DATA_READ (1 << 1)
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+#define MMC_DATA_STREAM (1 << 2)
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+};
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+
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+struct mmc_flag
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+{
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+ volatile rt_uint32_t risr;
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+ volatile rt_uint32_t idst;
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+};
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+
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+struct sdio_drv
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+{
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+ struct rt_mmcsd_host *host;
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+ struct rt_mmcsd_req *req;
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+ struct rt_semaphore rt_sem;
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+ struct mmc_xfe_des xfe;
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+ struct mmc_flag flag;
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+ tina_mmc_t mmc_des;
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+ rt_uint8_t *mmc_buf;
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+ rt_uint8_t usedma;
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+
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+};
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+
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+#ifdef CONFIG_MMC_USE_DMA
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+#ifdef TINA_USING_SDIO0
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+ALIGN(32) static rt_uint8_t dma_buffer[64 * 1024];
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+#endif
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+#endif
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+
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+static void mmc_request_end(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req);
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+
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+static void mmc_delay_us(int us)
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+{
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+ volatile unsigned int temp;
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+
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+ while (us--)
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+ {
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+ temp = 0x2f;
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+ while (temp--)
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+ {
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+ temp = temp;
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+ };
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+ }
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+}
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+
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+static void mmc_dump_errinfo(unsigned int err)
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+{
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+ dbg_log(DBG_ERROR, "[err]:0x%08x, %s%s%s%s%s%s%s%s%s%s%s\n",
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+ err,
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+ err & SDXC_RespErr ? " RE" : "",
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+ err & SDXC_RespCRCErr ? " RCE" : "",
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+ err & SDXC_DataCRCErr ? " DCE" : "",
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+ err & SDXC_RespTimeout ? " RTO" : "",
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+ err & SDXC_DataTimeout ? " DTO" : "",
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+ err & SDXC_DataStarve ? " DS" : "",
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+ err & SDXC_FIFORunErr ? " FE" : "",
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+ err & SDXC_HardWLocked ? " HL" : "",
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+ err & SDXC_StartBitErr ? " SBE" : "",
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+ err & SDXC_EndBitErr ? " EBE" : "",
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+ err == 0 ? " STO" : ""
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+ );
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+}
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+
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+static int mmc_update_clk(tina_mmc_t mmc)
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+{
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+ rt_uint32_t cmd;
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+ rt_uint32_t timeout = 2000000;
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+
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+ /* cmd load */
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+ cmd = SDXC_LOAD_CMD | SDXC_UPDATE_CLOCK_CMD | SDXC_WAIT_OVER_CMD;
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+ mmc->cmdr_reg = cmd;
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+ /* while load success */
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+ while ((mmc->cmdr_reg & SDXC_LOAD_CMD) && (--timeout))
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+ {
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+ mmc_delay_us(1);
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+ }
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+ if (!timeout)
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+ {
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+ dbg_log(DBG_ERROR, "mmc update clk failed\n");
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+ return -RT_ERROR;
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+ }
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+ /* clean interrupt */
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+ mmc->risr_reg = mmc->risr_reg;
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+ return RT_EOK;
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+}
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+
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+static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
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+{
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+ ALIGN(32) static struct mmc_des_v4p1 pdes[128]; // mast ALIGN(32)
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+ unsigned i, rval;
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+ unsigned des_idx;
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+ unsigned length = xfe->size * xfe->num;
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+ unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT;
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+ unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1);
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+
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+ if (remain)
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+ {
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+ buff_frag_num ++;
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+ }
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+ else
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+ {
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+ remain = SDXC_DES_BUFFER_MAX_LEN;
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+ }
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+ memset(pdes, 0, sizeof(pdes));
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+ mmu_clean_dcache((rt_uint32_t)(xfe->buff), length);
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+ for (i = 0, des_idx = 0; i < buff_frag_num; i++, des_idx++)
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+ {
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+ // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
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+ pdes[des_idx].des_chain = 1;
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+ pdes[des_idx].own = 1;
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+ pdes[des_idx].dic = 1;
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+ if ((buff_frag_num > 1) && (i != buff_frag_num - 1))
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+ {
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+ pdes[des_idx].data_buf1_sz = SDXC_DES_BUFFER_MAX_LEN;
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+ }
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+ else
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+ {
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+ pdes[des_idx].data_buf1_sz = remain;
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+ }
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+ pdes[des_idx].buf_addr_ptr1 = (unsigned long)(xfe->buff) + i * SDXC_DES_BUFFER_MAX_LEN;
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+ if (i == 0)
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+ {
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+ pdes[des_idx].first_des = 1;
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+ }
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+
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+ if (i == (buff_frag_num - 1))
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+ {
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+ pdes[des_idx].dic = 0;
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+ pdes[des_idx].last_des = 1;
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+ pdes[des_idx].end_of_ring = 1;
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+ pdes[des_idx].buf_addr_ptr2 = 0;
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+ }
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+ else
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+ {
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+ pdes[des_idx].buf_addr_ptr2 = (unsigned long)&pdes[des_idx+1];
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+ }
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+
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+ dbg_log(DBG_LOG, "frag %d, remain %d, des[%d](%08x): " \
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+ "[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n", \
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+ i, remain, des_idx, (unsigned int)&pdes[des_idx],
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+ (unsigned int)((unsigned int*)&pdes[des_idx])[0], (unsigned int)((unsigned int*)&pdes[des_idx])[1],
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+ (unsigned int)((unsigned int*)&pdes[des_idx])[2], (unsigned int)((unsigned int*)&pdes[des_idx])[3]);
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+ }
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+ mmu_clean_dcache((rt_uint32_t)pdes, sizeof(struct mmc_des_v4p1) * (des_idx + 1));
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+
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+ /*
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+ * GCTRLREG
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+ * GCTRL[2] : DMA reset
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+ * GCTRL[5] : DMA enable
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+ *
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+ * IDMACREG
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+ * IDMAC[0] : IDMA soft reset
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+ * IDMAC[1] : IDMA fix burst flag
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+ * IDMAC[7] : IDMA on
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+ *
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+ * IDIECREG
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+ * IDIE[0] : IDMA transmit interrupt flag
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+ * IDIE[1] : IDMA receive interrupt flag
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+ */
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+ rval = mmc->gctl_reg;
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+ mmc->gctl_reg = rval | (1 << 5) | (1 << 2); /* dma enable */
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+ mmc->dmac_reg = (1 << 0); /* idma reset */
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+ while(mmc->dmac_reg & 0x1) {}; /* wait idma reset done */
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+ mmc->dmac_reg = (1 << 1) | (1 << 7); /* idma on */
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+ rval = mmc->idie_reg & (~3);
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+ if (xfe->flag == MMC_DATA_WRITE)
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+ rval |= (1 << 0);
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+ else
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+ rval |= (1 << 1);
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+ mmc->idie_reg = rval;
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+ mmc->dlba_reg = (unsigned long)pdes;
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+ mmc->fwlr_reg = (2U << 28) | (7U << 16) | 8;
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+
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+ return 0;
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+}
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+
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+static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
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+{
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+ unsigned i;
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+ unsigned byte_cnt = xfe->size * xfe->num;
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+ unsigned *buff = (unsigned *)(xfe->buff);
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+ volatile unsigned timeout = 2000000;
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+
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+ if (xfe->flag == MMC_DATA_WRITE)
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+ {
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+ for (i = 0; i < (byte_cnt >> 2); i++)
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+ {
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+ while(--timeout && (mmc->star_reg & (1 << 3)));
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+
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+ if (timeout <= 0)
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+ {
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+ dbg_log(DBG_ERROR, "write data by cpu failed status:0x%08x\n", mmc->star_reg);
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+ return -RT_ERROR;
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+ }
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+ mmc->fifo_reg = buff[i];
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+ timeout = 2000000;
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+ }
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+ }
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+ else
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+ {
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+ for (i = 0; i < (byte_cnt >> 2); i++)
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+ {
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+ while(--timeout && (mmc->star_reg & (1 << 2)));
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+
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+ if (timeout <= 0)
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+ {
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+ dbg_log(DBG_ERROR, "read data by cpu failed status:0x%08x\n", mmc->star_reg);
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+ return -RT_ERROR;
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+ }
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+ buff[i] = mmc->fifo_reg;
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+ timeout = 2000000;
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+ }
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
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+{
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+ rt_uint32_t rval = 0;
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+
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+ /* disable card clock */
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+ rval = mmc->ckcr_reg;
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+ rval &= ~(1 << 16);
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+ mmc->ckcr_reg = rval;
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+ if (mmc_update_clk(mmc) != RT_EOK)
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+ {
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+ dbg_log(DBG_ERROR, "clk update fail line:%d\n", __LINE__);
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+ return -RT_ERROR;
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+ }
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+
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+ if (mmc == MMC0)
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+ {
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+ mmc_set_clk(SDMMC0, clk);
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+ }
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+ else
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+ {
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+ mmc_set_clk(SDMMC1, clk);
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+ }
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+
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+ /* Re-enable card clock */
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+ rval = mmc->ckcr_reg;
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+ rval |= (0x1 << 16); //(3 << 16);
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+ mmc->ckcr_reg = rval;
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+ if(mmc_update_clk(mmc) != RT_EOK)
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+ {
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+ dbg_log(DBG_ERROR, "clk update fail line:%d\n", __LINE__);
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+ return -RT_ERROR;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static rt_err_t mmc_set_ios(tina_mmc_t mmc, int clk, int bus_width)
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+{
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+ dbg_log(DBG_LOG, "mmc set io bus width:%d clock:%d\n", \
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+ (bus_width == MMCSD_BUS_WIDTH_8 ? 8 : (bus_width == MMCSD_BUS_WIDTH_4 ? 4 : 1)), clk);
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+ /* change clock */
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+ if (clk && (mmc_config_clock(mmc, clk) != RT_EOK))
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+ {
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+ dbg_log(DBG_ERROR, "update clock failed\n");
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+ return -RT_ERROR;
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+ }
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+
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+ /* Change bus width */
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+ if (bus_width == MMCSD_BUS_WIDTH_8)
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+ {
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+ mmc->bwdr_reg = 2;
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+ }
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+ else if (bus_width == MMCSD_BUS_WIDTH_4)
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+ {
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+ mmc->bwdr_reg = 1;
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+ }
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+ else
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+ {
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+ mmc->bwdr_reg = 0;
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+ }
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+
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+ return RT_EOK;
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+}
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+
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+static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
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+{
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+
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+ unsigned int cmdval = 0x80000000;
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+ signed int timeout = 0;
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+ int err = 0;
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+ unsigned int status = 0;
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+ struct rt_mmcsd_data *data = cmd->data;
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+ unsigned int bytecnt = 0;
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+ struct sdio_drv *sdio_des = (struct sdio_drv *)host->private_data;
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+ tina_mmc_t mmc = sdio_des->mmc_des;
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+
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+ timeout = 5000 * 1000;
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+ status = mmc->star_reg;
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+ while (status & (1 << 9))
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+ {
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+ dbg_log(DBG_LOG, "note: check card busy\n");
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+
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+ status = mmc->star_reg;
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+ if (!timeout--)
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+ {
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+ err = -1;
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+ dbg_log(DBG_ERROR, "mmc cmd12 busy timeout data:0x%08x\n", status);
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+ return err;
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+ }
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+ mmc_delay_us(1);
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+ }
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+ /*
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+ * CMDREG
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+ * CMD[5:0] : Command index
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+ * CMD[6] : Has response
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+ * CMD[7] : Long response
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+ * CMD[8] : Check response CRC
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+ * CMD[9] : Has data
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+ * CMD[10] : Write
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+ * CMD[11] : Steam mode
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+ * CMD[12] : Auto stop
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+ * CMD[13] : Wait previous over
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+ * CMD[14] : About cmd
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+ * CMD[15] : Send initialization
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+ * CMD[21] : Update clock
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+ * CMD[31] : Load cmd
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+ */
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+ if (!cmd->cmd_code)
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+ cmdval |= (1 << 15);
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+ if (resp_type(cmd) != RESP_NONE)
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+ cmdval |= (1 << 6);
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+ if (resp_type(cmd) == RESP_R2)
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+ cmdval |= (1 << 7);
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+ if ((resp_type(cmd) != RESP_R3) && (resp_type(cmd) != RESP_R4))
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+ cmdval |= (1 << 8);
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+
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+ if (data)
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+ {
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+ cmdval |= (1 << 9) | (1 << 13);
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+ if (data->flags & DATA_DIR_WRITE)
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+ cmdval |= (1 << 10);
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+ if (data->blks > 1)
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+ cmdval |= (1 << 12);
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+ mmc->bksr_reg = data->blksize;
|
|
|
+ bytecnt = data->blksize * data->blks;
|
|
|
+ mmc->bycr_reg = bytecnt;
|
|
|
+ }
|
|
|
+
|
|
|
+ dbg_log(DBG_LOG, "cmd %d(0x%08x), arg 0x%08x\n", cmd->cmd_code, cmdval | cmd->cmd_code, cmd->arg);
|
|
|
+ mmc->cagr_reg = cmd->arg;
|
|
|
+ if (!data)
|
|
|
+ {
|
|
|
+ mmc->cmdr_reg = cmdval | cmd->cmd_code;
|
|
|
+ mmc->imkr_reg |= 0x1 << 2;
|
|
|
+ }
|
|
|
+
|
|
|
+ /*
|
|
|
+ * transfer data and check status
|
|
|
+ * STATREG[2] : FIFO empty
|
|
|
+ * STATREG[3] : FIFO full
|
|
|
+ */
|
|
|
+ if (data)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_LOG, "mmc trans data %d bytes addr:0x%08x\n", bytecnt, data);
|
|
|
+#ifdef CONFIG_MMC_USE_DMA
|
|
|
+ if (bytecnt > 64)
|
|
|
+ {
|
|
|
+#else
|
|
|
+ if (0)
|
|
|
+ {
|
|
|
+#endif
|
|
|
+ sdio_des->usedma = 1;
|
|
|
+ mmc->gctl_reg = mmc->gctl_reg & (~0x80000000);
|
|
|
+ mmc_trans_data_by_dma(mmc, &sdio_des->xfe);
|
|
|
+ mmc->cmdr_reg = cmdval | cmd->cmd_code;
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ sdio_des->usedma = 0;
|
|
|
+ mmc->gctl_reg = mmc->gctl_reg | 0x80000000;
|
|
|
+ mmc->cmdr_reg = cmdval | cmd->cmd_code;
|
|
|
+ mmc_trans_data_by_cpu(mmc, &sdio_des->xfe);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (data->blks > 1)
|
|
|
+ {
|
|
|
+ mmc->imkr_reg |= (0x1 << 14);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ mmc->imkr_reg |= (0x1 << 3);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ mmc->imkr_reg |= 0xbfc2;
|
|
|
+
|
|
|
+ if (data)
|
|
|
+ {
|
|
|
+ //TODO:2 * bytecnt * 4?
|
|
|
+ timeout = sdio_des->usedma ? (2 * bytecnt * 4) : 100; //0.04us(25M)*2(4bit width)*25()
|
|
|
+ if (timeout < 10)
|
|
|
+ {
|
|
|
+ timeout = 10;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ timeout = 200;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (rt_sem_take(&sdio_des->rt_sem, timeout) != RT_EOK)
|
|
|
+ {
|
|
|
+ err = (mmc->risr_reg | sdio_des->flag.risr) & 0xbfc2;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ err = (mmc->risr_reg | sdio_des->flag.risr) & 0xbfc2;
|
|
|
+ if (err)
|
|
|
+ {
|
|
|
+ cmd->err = -RT_ETIMEOUT;
|
|
|
+ goto out;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (resp_type(cmd) == RESP_R2)
|
|
|
+ {
|
|
|
+ cmd->resp[3] = mmc->resp0_reg;
|
|
|
+ cmd->resp[2] = mmc->resp1_reg;
|
|
|
+ cmd->resp[1] = mmc->resp2_reg;
|
|
|
+ cmd->resp[0] = mmc->resp3_reg;
|
|
|
+ dbg_log(DBG_LOG, "mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n",
|
|
|
+ cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ cmd->resp[0] = mmc->resp0_reg;
|
|
|
+ dbg_log(DBG_LOG, "mmc resp 0x%08x\n", cmd->resp[0]);
|
|
|
+ }
|
|
|
+
|
|
|
+out:
|
|
|
+ if (err)
|
|
|
+ {
|
|
|
+ mmc_dump_errinfo(err & 0xbfc2);
|
|
|
+ }
|
|
|
+ if (data && sdio_des->usedma)
|
|
|
+ {
|
|
|
+ /* IDMASTAREG
|
|
|
+ * IDST[0] : idma tx int
|
|
|
+ * IDST[1] : idma rx int
|
|
|
+ * IDST[2] : idma fatal bus error
|
|
|
+ * IDST[4] : idma descriptor invalid
|
|
|
+ * IDST[5] : idma error summary
|
|
|
+ * IDST[8] : idma normal interrupt sumary
|
|
|
+ * IDST[9] : idma abnormal interrupt sumary
|
|
|
+ */
|
|
|
+ status = mmc->idst_reg;
|
|
|
+ mmc->idst_reg = status;
|
|
|
+ mmc->idie_reg = 0;
|
|
|
+ mmc->dmac_reg = 0;
|
|
|
+ mmc->gctl_reg = mmc->gctl_reg & (~(1 << 5));
|
|
|
+ }
|
|
|
+ if (err)
|
|
|
+ {
|
|
|
+ if (data && (data->flags & DATA_DIR_READ) && (bytecnt == 512))
|
|
|
+ {
|
|
|
+ mmc->gctl_reg = mmc->gctl_reg | 0x80000000;
|
|
|
+ mmc->dbgc_reg = 0xdeb;
|
|
|
+ timeout = 1000;
|
|
|
+ dbg_log(DBG_LOG, "Read remain data\n");
|
|
|
+ while (mmc->bbcr_reg < 512)
|
|
|
+ {
|
|
|
+ unsigned int tmp = mmc->fifo_reg;
|
|
|
+ tmp = tmp;
|
|
|
+ dbg_log(DBG_LOG, "Read data 0x%08x, bbcr 0x%04x\n", tmp, mmc->bbcr_reg);
|
|
|
+ mmc_delay_us(1);
|
|
|
+ if (!(timeout--))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "Read remain data timeout\n");
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ mmc->gctl_reg = 0x7;
|
|
|
+ while (mmc->gctl_reg & 0x7) { };
|
|
|
+
|
|
|
+ mmc_update_clk(mmc);
|
|
|
+ cmd->err = -RT_ETIMEOUT;
|
|
|
+ dbg_log(DBG_ERROR, "mmc cmd %d err\n", cmd->cmd_code);
|
|
|
+ }
|
|
|
+
|
|
|
+ mmc->gctl_reg &= ~(0x1 << 4);
|
|
|
+ mmc->imkr_reg &= ~0xffff;
|
|
|
+ mmc->risr_reg = 0xffffffff;
|
|
|
+ mmc->gctl_reg |= 0x1 << 4;
|
|
|
+ while (!rt_sem_take(&sdio_des->rt_sem, 0)) {}
|
|
|
+ mmc_request_end(sdio_des->host, sdio_des->req);
|
|
|
+
|
|
|
+ return err;
|
|
|
+}
|
|
|
+
|
|
|
+static void mmc_request_end(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
|
|
|
+{
|
|
|
+ struct rt_mmcsd_data *data;
|
|
|
+ unsigned byte_cnt;
|
|
|
+ struct sdio_drv *sdio = (struct sdio_drv *)host->private_data;
|
|
|
+
|
|
|
+#ifdef CONFIG_MMC_USE_DMA
|
|
|
+ data = req->cmd->data;
|
|
|
+ if (data)
|
|
|
+ {
|
|
|
+ byte_cnt = data->blksize * data->blks;
|
|
|
+ if ((byte_cnt > 64) && (data->flags & DATA_DIR_READ))
|
|
|
+ {
|
|
|
+ mmu_invalidate_dcache((rt_uint32_t)sdio->xfe.buff, (rt_uint32_t)byte_cnt);
|
|
|
+
|
|
|
+ if (((rt_uint32_t)data->buf) & (DMA_ALIGN - 1))
|
|
|
+ {
|
|
|
+ memcpy(data->buf, sdio->xfe.buff, byte_cnt);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ mmcsd_req_complete(host);
|
|
|
+}
|
|
|
+
|
|
|
+static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
|
|
|
+{
|
|
|
+ struct rt_mmcsd_data *data;
|
|
|
+ int byte_cnt;
|
|
|
+ struct sdio_drv *sdio;
|
|
|
+
|
|
|
+ sdio = (struct sdio_drv *)host->private_data;
|
|
|
+ sdio->req = req;
|
|
|
+ data = req->cmd->data;
|
|
|
+
|
|
|
+ if (data)
|
|
|
+ {
|
|
|
+ sdio->xfe.size = data->blksize;
|
|
|
+ sdio->xfe.num = data->blks;
|
|
|
+ sdio->xfe.buff = (rt_uint8_t *)data->buf;
|
|
|
+ sdio->xfe.flag = (data->flags & DATA_DIR_WRITE) ? \
|
|
|
+ MMC_DATA_WRITE : MMC_DATA_READ;
|
|
|
+#ifdef CONFIG_MMC_USE_DMA
|
|
|
+ byte_cnt = data->blksize * data->blks;
|
|
|
+ if ((byte_cnt > 64) && (((rt_uint32_t)data->buf) & (DMA_ALIGN - 1)))
|
|
|
+ {
|
|
|
+ sdio->xfe.buff = (rt_uint8_t *)sdio->mmc_buf;
|
|
|
+ if (data->flags & DATA_DIR_WRITE)
|
|
|
+ {
|
|
|
+ memcpy(sdio->mmc_buf, data->buf, byte_cnt);
|
|
|
+ mmu_clean_dcache((rt_uint32_t)sdio->mmc_buf, (rt_uint32_t)byte_cnt);
|
|
|
+ }
|
|
|
+ }
|
|
|
+#endif
|
|
|
+ }
|
|
|
+
|
|
|
+ memset(&sdio->flag, 0, sizeof(struct mmc_flag));
|
|
|
+ mmc_send_cmd(host, req->cmd);
|
|
|
+
|
|
|
+ return;
|
|
|
+}
|
|
|
+
|
|
|
+static void sdio_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
|
|
|
+{
|
|
|
+ int clk = io_cfg->clock;
|
|
|
+ int width = io_cfg->bus_width;
|
|
|
+ struct sdio_drv *sdio_des = (struct sdio_drv *)host->private_data;
|
|
|
+ tina_mmc_t mmc = sdio_des->mmc_des;
|
|
|
+
|
|
|
+ mmc_set_ios(mmc, clk, width);
|
|
|
+}
|
|
|
+
|
|
|
+static const struct rt_mmcsd_host_ops ops =
|
|
|
+{
|
|
|
+ sdio_request_send,
|
|
|
+ sdio_set_iocfg,
|
|
|
+ RT_NULL,
|
|
|
+ RT_NULL,
|
|
|
+};
|
|
|
+
|
|
|
+static void sdio_interrupt_handle(int irqno, void *param)
|
|
|
+{
|
|
|
+ rt_uint32_t risr, idst;
|
|
|
+ rt_uint32_t status;
|
|
|
+ struct sdio_drv *sdio_des = (struct sdio_drv *)param;
|
|
|
+ struct rt_mmcsd_data *data = sdio_des->req->cmd->data;
|
|
|
+ tina_mmc_t mmc = sdio_des->mmc_des;
|
|
|
+
|
|
|
+ risr = mmc->risr_reg;
|
|
|
+ idst = mmc->idst_reg;
|
|
|
+
|
|
|
+ mmc->risr_reg = risr & mmc->imkr_reg;
|
|
|
+ mmc->idst_reg = idst & mmc->idie_reg;
|
|
|
+
|
|
|
+ sdio_des->flag.risr |= risr;
|
|
|
+ sdio_des->flag.idst |= idst;
|
|
|
+
|
|
|
+ if (data)
|
|
|
+ {
|
|
|
+ int done = 0;
|
|
|
+
|
|
|
+ status = sdio_des->flag.risr | mmc->risr_reg;
|
|
|
+ if (data->blks > 1)//not wait auto stop when MMC_CMD_MANUAL is set
|
|
|
+ {
|
|
|
+ if (sdio_des->usedma)
|
|
|
+ done = ((status & (1 << 14)) && (sdio_des->flag.idst & 0x3)) ? 1 : 0;
|
|
|
+ else
|
|
|
+ done = status & (1 << 14);
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ if (sdio_des->usedma)
|
|
|
+ done = ((status & (1 << 3)) && (sdio_des->flag.idst & 0x3)) ? 1 : 0;
|
|
|
+ else
|
|
|
+ done = status & (1 << 3);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (done)
|
|
|
+ {
|
|
|
+ rt_sem_release(&sdio_des->rt_sem);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else
|
|
|
+ {
|
|
|
+ rt_sem_release(&sdio_des->rt_sem);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static void sdio_gpio_init(struct sdio_drv *sdio_des)
|
|
|
+{
|
|
|
+ int pin;
|
|
|
+
|
|
|
+ if ((rt_uint32_t)sdio_des->mmc_des == MMC0_BASE_ADDR)
|
|
|
+ {
|
|
|
+ /* SDC0: PF0-PF5 */
|
|
|
+ for (pin = GPIO_PIN_0; pin <= GPIO_PIN_5; pin++)
|
|
|
+ {
|
|
|
+ gpio_set_func(GPIO_PORT_F, pin, IO_FUN_1);
|
|
|
+ gpio_set_pull_mode(GPIO_PORT_F, pin, PULL_UP);
|
|
|
+ gpio_set_drive_level(GPIO_PORT_F, pin, DRV_LEVEL_2);
|
|
|
+ }
|
|
|
+ }
|
|
|
+ else if ((rt_uint32_t)sdio_des->mmc_des == MMC1_BASE_ADDR)
|
|
|
+ {
|
|
|
+ //todo: config gpio port
|
|
|
+ RT_ASSERT(0);
|
|
|
+ }
|
|
|
+
|
|
|
+}
|
|
|
+
|
|
|
+static void sdio_clk_io_on(struct sdio_drv *sdio_des)
|
|
|
+{
|
|
|
+ if ((rt_uint32_t)sdio_des->mmc_des == MMC0_BASE_ADDR)
|
|
|
+ {
|
|
|
+ CCU->bus_clk_gating0 |= 0x1 << 8;
|
|
|
+ CCU->bus_soft_rst0 |= 0x1 << 8;
|
|
|
+ }
|
|
|
+ else if ((rt_uint32_t)sdio_des->mmc_des == MMC1_BASE_ADDR)
|
|
|
+ {
|
|
|
+ CCU->bus_clk_gating0 |= 0x1 << 9;
|
|
|
+ CCU->bus_soft_rst0 |= 0x1 << 9;
|
|
|
+ }
|
|
|
+
|
|
|
+ mmc_set_clk(SDMMC0, 24000000);
|
|
|
+}
|
|
|
+
|
|
|
+static void sdio_irq_init(void *param)
|
|
|
+{
|
|
|
+ struct sdio_drv *sdio_des = (struct sdio_drv *)param;
|
|
|
+
|
|
|
+ if ((rt_uint32_t)sdio_des->mmc_des == MMC0_BASE_ADDR)
|
|
|
+ {
|
|
|
+ rt_hw_interrupt_install(SDC0_INTERRUPT, sdio_interrupt_handle, param, "mmc0_irq");
|
|
|
+ rt_hw_interrupt_umask(SDC0_INTERRUPT);
|
|
|
+ }
|
|
|
+ else if ((rt_uint32_t)sdio_des->mmc_des == MMC1_BASE_ADDR)
|
|
|
+ {
|
|
|
+ rt_hw_interrupt_install(SDC1_INTERRUPT, sdio_interrupt_handle, param, "mmc1_irq");
|
|
|
+ rt_hw_interrupt_umask(SDC1_INTERRUPT);
|
|
|
+ }
|
|
|
+
|
|
|
+ sdio_des->mmc_des->gctl_reg |= (0x1 << 4);
|
|
|
+}
|
|
|
+
|
|
|
+int tina_sdio_init(void)
|
|
|
+{
|
|
|
+ struct rt_mmcsd_host *host;
|
|
|
+
|
|
|
+#ifdef TINA_USING_SDIO0
|
|
|
+ {
|
|
|
+ static struct sdio_drv _sdio_drv;
|
|
|
+
|
|
|
+ host = mmcsd_alloc_host();
|
|
|
+ if (!host)
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "alloc host failed\n");
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (rt_sem_init(&_sdio_drv.rt_sem, "sdio_sem", RT_NULL, RT_IPC_FLAG_FIFO))
|
|
|
+ {
|
|
|
+ dbg_log(DBG_ERROR, "sem init failed\n");
|
|
|
+ goto err;
|
|
|
+ }
|
|
|
+ _sdio_drv.mmc_des = (tina_mmc_t)MMC0_BASE_ADDR;
|
|
|
+ _sdio_drv.mmc_buf = dma_buffer;
|
|
|
+ //init gpio pin
|
|
|
+ sdio_gpio_init(&_sdio_drv);
|
|
|
+ //clk is on
|
|
|
+ sdio_clk_io_on(&_sdio_drv);
|
|
|
+ //irq init
|
|
|
+ sdio_irq_init(&_sdio_drv);
|
|
|
+
|
|
|
+ host->ops = &ops;
|
|
|
+ host->freq_min = 400 * 1000;
|
|
|
+ host->freq_max = 50 * 1000 * 1000;
|
|
|
+ host->valid_ocr = VDD_26_27 | VDD_27_28 | VDD_28_29 | VDD_29_30 | VDD_30_31 | VDD_31_32 |
|
|
|
+ VDD_32_33 | VDD_33_34 | VDD_34_35 | VDD_35_36;
|
|
|
+ host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ | MMCSD_SUP_HIGHSPEED;
|
|
|
+ host->max_seg_size = 2048;
|
|
|
+ host->max_dma_segs = 10;
|
|
|
+ host->max_blk_size = 512;
|
|
|
+ host->max_blk_count = 4096;
|
|
|
+
|
|
|
+ host->private_data = &_sdio_drv;
|
|
|
+
|
|
|
+ _sdio_drv.host = host;
|
|
|
+
|
|
|
+ mmcsd_change(host);
|
|
|
+ }
|
|
|
+#endif
|
|
|
+
|
|
|
+ return RT_EOK;
|
|
|
+
|
|
|
+err:
|
|
|
+ if (host)
|
|
|
+ {
|
|
|
+ rt_free(host);
|
|
|
+ }
|
|
|
+
|
|
|
+ return RT_ERROR;
|
|
|
+}
|
|
|
+INIT_APP_EXPORT(tina_sdio_init);
|
|
|
+#endif
|
ZYH